drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 101                                   struct drm_i915_gem_object *obj,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 119                                     struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 124                                          struct drm_modeset_acquire_ctx *ctx);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126
 127 struct intel_limit {
 128         struct {
 129                 int min, max;
 130         } dot, vco, n, m, m1, m2, p, p1;
 131
 132         struct {
 133                 int dot_limit;
 134                 int p2_slow, p2_fast;
 135         } p2;
 136 };
 137
 138 /* returns HPLL frequency in kHz */
 139 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 140 {
 141         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 142
 143         /* Obtain SKU information */
 144         mutex_lock(&dev_priv->sb_lock);
 145         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 146                 CCK_FUSE_HPLL_FREQ_MASK;
 147         mutex_unlock(&dev_priv->sb_lock);
 148
 149         return vco_freq[hpll_freq] * 1000;
 150 }
 151
 152 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 153                       const char *name, u32 reg, int ref_freq)
 154 {
 155         u32 val;
 156         int divider;
 157
 158         mutex_lock(&dev_priv->sb_lock);
 159         val = vlv_cck_read(dev_priv, reg);
 160         mutex_unlock(&dev_priv->sb_lock);
 161
 162         divider = val & CCK_FREQUENCY_VALUES;
 163
 164         WARN((val & CCK_FREQUENCY_STATUS) !=
 165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 166              "%s change in progress\n", name);
 167
 168         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 169 }
 170
 171 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 172                            const char *name, u32 reg)
 173 {
 174         if (dev_priv->hpll_freq == 0)
 175                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 176
 177         return vlv_get_cck_clock(dev_priv, name, reg,
 178                                  dev_priv->hpll_freq);
 179 }
 180
 181 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 182 {
 183         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 184                 return;
 185
 186         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 187                                                       CCK_CZ_CLOCK_CONTROL);
 188
 189         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 190 }
 191
 192 static inline u32 /* units of 100MHz */
 193 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 194                     const struct intel_crtc_state *pipe_config)
 195 {
 196         if (HAS_DDI(dev_priv))
 197                 return pipe_config->port_clock; /* SPLL */
 198         else if (IS_GEN5(dev_priv))
 199                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 200         else
 201                 return 270000;
 202 }
 203
 204 static const struct intel_limit intel_limits_i8xx_dac = {
 205         .dot = { .min = 25000, .max = 350000 },
 206         .vco = { .min = 908000, .max = 1512000 },
 207         .n = { .min = 2, .max = 16 },
 208         .m = { .min = 96, .max = 140 },
 209         .m1 = { .min = 18, .max = 26 },
 210         .m2 = { .min = 6, .max = 16 },
 211         .p = { .min = 4, .max = 128 },
 212         .p1 = { .min = 2, .max = 33 },
 213         .p2 = { .dot_limit = 165000,
 214                 .p2_slow = 4, .p2_fast = 2 },
 215 };
 216
 217 static const struct intel_limit intel_limits_i8xx_dvo = {
 218         .dot = { .min = 25000, .max = 350000 },
 219         .vco = { .min = 908000, .max = 1512000 },
 220         .n = { .min = 2, .max = 16 },
 221         .m = { .min = 96, .max = 140 },
 222         .m1 = { .min = 18, .max = 26 },
 223         .m2 = { .min = 6, .max = 16 },
 224         .p = { .min = 4, .max = 128 },
 225         .p1 = { .min = 2, .max = 33 },
 226         .p2 = { .dot_limit = 165000,
 227                 .p2_slow = 4, .p2_fast = 4 },
 228 };
 229
 230 static const struct intel_limit intel_limits_i8xx_lvds = {
 231         .dot = { .min = 25000, .max = 350000 },
 232         .vco = { .min = 908000, .max = 1512000 },
 233         .n = { .min = 2, .max = 16 },
 234         .m = { .min = 96, .max = 140 },
 235         .m1 = { .min = 18, .max = 26 },
 236         .m2 = { .min = 6, .max = 16 },
 237         .p = { .min = 4, .max = 128 },
 238         .p1 = { .min = 1, .max = 6 },
 239         .p2 = { .dot_limit = 165000,
 240                 .p2_slow = 14, .p2_fast = 7 },
 241 };
 242
 243 static const struct intel_limit intel_limits_i9xx_sdvo = {
 244         .dot = { .min = 20000, .max = 400000 },
 245         .vco = { .min = 1400000, .max = 2800000 },
 246         .n = { .min = 1, .max = 6 },
 247         .m = { .min = 70, .max = 120 },
 248         .m1 = { .min = 8, .max = 18 },
 249         .m2 = { .min = 3, .max = 7 },
 250         .p = { .min = 5, .max = 80 },
 251         .p1 = { .min = 1, .max = 8 },
 252         .p2 = { .dot_limit = 200000,
 253                 .p2_slow = 10, .p2_fast = 5 },
 254 };
 255
 256 static const struct intel_limit intel_limits_i9xx_lvds = {
 257         .dot = { .min = 20000, .max = 400000 },
 258         .vco = { .min = 1400000, .max = 2800000 },
 259         .n = { .min = 1, .max = 6 },
 260         .m = { .min = 70, .max = 120 },
 261         .m1 = { .min = 8, .max = 18 },
 262         .m2 = { .min = 3, .max = 7 },
 263         .p = { .min = 7, .max = 98 },
 264         .p1 = { .min = 1, .max = 8 },
 265         .p2 = { .dot_limit = 112000,
 266                 .p2_slow = 14, .p2_fast = 7 },
 267 };
 268
 269
 270 static const struct intel_limit intel_limits_g4x_sdvo = {
 271         .dot = { .min = 25000, .max = 270000 },
 272         .vco = { .min = 1750000, .max = 3500000},
 273         .n = { .min = 1, .max = 4 },
 274         .m = { .min = 104, .max = 138 },
 275         .m1 = { .min = 17, .max = 23 },
 276         .m2 = { .min = 5, .max = 11 },
 277         .p = { .min = 10, .max = 30 },
 278         .p1 = { .min = 1, .max = 3},
 279         .p2 = { .dot_limit = 270000,
 280                 .p2_slow = 10,
 281                 .p2_fast = 10
 282         },
 283 };
 284
 285 static const struct intel_limit intel_limits_g4x_hdmi = {
 286         .dot = { .min = 22000, .max = 400000 },
 287         .vco = { .min = 1750000, .max = 3500000},
 288         .n = { .min = 1, .max = 4 },
 289         .m = { .min = 104, .max = 138 },
 290         .m1 = { .min = 16, .max = 23 },
 291         .m2 = { .min = 5, .max = 11 },
 292         .p = { .min = 5, .max = 80 },
 293         .p1 = { .min = 1, .max = 8},
 294         .p2 = { .dot_limit = 165000,
 295                 .p2_slow = 10, .p2_fast = 5 },
 296 };
 297
 298 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 299         .dot = { .min = 20000, .max = 115000 },
 300         .vco = { .min = 1750000, .max = 3500000 },
 301         .n = { .min = 1, .max = 3 },
 302         .m = { .min = 104, .max = 138 },
 303         .m1 = { .min = 17, .max = 23 },
 304         .m2 = { .min = 5, .max = 11 },
 305         .p = { .min = 28, .max = 112 },
 306         .p1 = { .min = 2, .max = 8 },
 307         .p2 = { .dot_limit = 0,
 308                 .p2_slow = 14, .p2_fast = 14
 309         },
 310 };
 311
 312 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 313         .dot = { .min = 80000, .max = 224000 },
 314         .vco = { .min = 1750000, .max = 3500000 },
 315         .n = { .min = 1, .max = 3 },
 316         .m = { .min = 104, .max = 138 },
 317         .m1 = { .min = 17, .max = 23 },
 318         .m2 = { .min = 5, .max = 11 },
 319         .p = { .min = 14, .max = 42 },
 320         .p1 = { .min = 2, .max = 6 },
 321         .p2 = { .dot_limit = 0,
 322                 .p2_slow = 7, .p2_fast = 7
 323         },
 324 };
 325
 326 static const struct intel_limit intel_limits_pineview_sdvo = {
 327         .dot = { .min = 20000, .max = 400000},
 328         .vco = { .min = 1700000, .max = 3500000 },
 329         /* Pineview's Ncounter is a ring counter */
 330         .n = { .min = 3, .max = 6 },
 331         .m = { .min = 2, .max = 256 },
 332         /* Pineview only has one combined m divider, which we treat as m2. */
 333         .m1 = { .min = 0, .max = 0 },
 334         .m2 = { .min = 0, .max = 254 },
 335         .p = { .min = 5, .max = 80 },
 336         .p1 = { .min = 1, .max = 8 },
 337         .p2 = { .dot_limit = 200000,
 338                 .p2_slow = 10, .p2_fast = 5 },
 339 };
 340
 341 static const struct intel_limit intel_limits_pineview_lvds = {
 342         .dot = { .min = 20000, .max = 400000 },
 343         .vco = { .min = 1700000, .max = 3500000 },
 344         .n = { .min = 3, .max = 6 },
 345         .m = { .min = 2, .max = 256 },
 346         .m1 = { .min = 0, .max = 0 },
 347         .m2 = { .min = 0, .max = 254 },
 348         .p = { .min = 7, .max = 112 },
 349         .p1 = { .min = 1, .max = 8 },
 350         .p2 = { .dot_limit = 112000,
 351                 .p2_slow = 14, .p2_fast = 14 },
 352 };
 353
 354 /* Ironlake / Sandybridge
 355  *
 356  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 357  * the range value for them is (actual_value - 2).
 358  */
 359 static const struct intel_limit intel_limits_ironlake_dac = {
 360         .dot = { .min = 25000, .max = 350000 },
 361         .vco = { .min = 1760000, .max = 3510000 },
 362         .n = { .min = 1, .max = 5 },
 363         .m = { .min = 79, .max = 127 },
 364         .m1 = { .min = 12, .max = 22 },
 365         .m2 = { .min = 5, .max = 9 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 225000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 373         .dot = { .min = 25000, .max = 350000 },
 374         .vco = { .min = 1760000, .max = 3510000 },
 375         .n = { .min = 1, .max = 3 },
 376         .m = { .min = 79, .max = 118 },
 377         .m1 = { .min = 12, .max = 22 },
 378         .m2 = { .min = 5, .max = 9 },
 379         .p = { .min = 28, .max = 112 },
 380         .p1 = { .min = 2, .max = 8 },
 381         .p2 = { .dot_limit = 225000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 386         .dot = { .min = 25000, .max = 350000 },
 387         .vco = { .min = 1760000, .max = 3510000 },
 388         .n = { .min = 1, .max = 3 },
 389         .m = { .min = 79, .max = 127 },
 390         .m1 = { .min = 12, .max = 22 },
 391         .m2 = { .min = 5, .max = 9 },
 392         .p = { .min = 14, .max = 56 },
 393         .p1 = { .min = 2, .max = 8 },
 394         .p2 = { .dot_limit = 225000,
 395                 .p2_slow = 7, .p2_fast = 7 },
 396 };
 397
 398 /* LVDS 100mhz refclk limits. */
 399 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 400         .dot = { .min = 25000, .max = 350000 },
 401         .vco = { .min = 1760000, .max = 3510000 },
 402         .n = { .min = 1, .max = 2 },
 403         .m = { .min = 79, .max = 126 },
 404         .m1 = { .min = 12, .max = 22 },
 405         .m2 = { .min = 5, .max = 9 },
 406         .p = { .min = 28, .max = 112 },
 407         .p1 = { .min = 2, .max = 8 },
 408         .p2 = { .dot_limit = 225000,
 409                 .p2_slow = 14, .p2_fast = 14 },
 410 };
 411
 412 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 413         .dot = { .min = 25000, .max = 350000 },
 414         .vco = { .min = 1760000, .max = 3510000 },
 415         .n = { .min = 1, .max = 3 },
 416         .m = { .min = 79, .max = 126 },
 417         .m1 = { .min = 12, .max = 22 },
 418         .m2 = { .min = 5, .max = 9 },
 419         .p = { .min = 14, .max = 42 },
 420         .p1 = { .min = 2, .max = 6 },
 421         .p2 = { .dot_limit = 225000,
 422                 .p2_slow = 7, .p2_fast = 7 },
 423 };
 424
 425 static const struct intel_limit intel_limits_vlv = {
 426          /*
 427           * These are the data rate limits (measured in fast clocks)
 428           * since those are the strictest limits we have. The fast
 429           * clock and actual rate limits are more relaxed, so checking
 430           * them would make no difference.
 431           */
 432         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 433         .vco = { .min = 4000000, .max = 6000000 },
 434         .n = { .min = 1, .max = 7 },
 435         .m1 = { .min = 2, .max = 3 },
 436         .m2 = { .min = 11, .max = 156 },
 437         .p1 = { .min = 2, .max = 3 },
 438         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 439 };
 440
 441 static const struct intel_limit intel_limits_chv = {
 442         /*
 443          * These are the data rate limits (measured in fast clocks)
 444          * since those are the strictest limits we have.  The fast
 445          * clock and actual rate limits are more relaxed, so checking
 446          * them would make no difference.
 447          */
 448         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 449         .vco = { .min = 4800000, .max = 6480000 },
 450         .n = { .min = 1, .max = 1 },
 451         .m1 = { .min = 2, .max = 2 },
 452         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 453         .p1 = { .min = 2, .max = 4 },
 454         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 455 };
 456
 457 static const struct intel_limit intel_limits_bxt = {
 458         /* FIXME: find real dot limits */
 459         .dot = { .min = 0, .max = INT_MAX },
 460         .vco = { .min = 4800000, .max = 6700000 },
 461         .n = { .min = 1, .max = 1 },
 462         .m1 = { .min = 2, .max = 2 },
 463         /* FIXME: find real m2 limits */
 464         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 465         .p1 = { .min = 2, .max = 4 },
 466         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 467 };
 468
 469 static bool
 470 needs_modeset(struct drm_crtc_state *state)
 471 {
 472         return drm_atomic_crtc_needs_modeset(state);
 473 }
 474
 475 /*
 476  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 477  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 478  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 479  * The helpers' return value is the rate of the clock that is fed to the
 480  * display engine's pipe which can be the above fast dot clock rate or a
 481  * divided-down version of it.
 482  */
 483 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 484 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 485 {
 486         clock->m = clock->m2 + 2;
 487         clock->p = clock->p1 * clock->p2;
 488         if (WARN_ON(clock->n == 0 || clock->p == 0))
 489                 return 0;
 490         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 491         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 492
 493         return clock->dot;
 494 }
 495
 496 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 497 {
 498         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 499 }
 500
 501 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 502 {
 503         clock->m = i9xx_dpll_compute_m(clock);
 504         clock->p = clock->p1 * clock->p2;
 505         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 506                 return 0;
 507         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 508         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 509
 510         return clock->dot;
 511 }
 512
 513 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 514 {
 515         clock->m = clock->m1 * clock->m2;
 516         clock->p = clock->p1 * clock->p2;
 517         if (WARN_ON(clock->n == 0 || clock->p == 0))
 518                 return 0;
 519         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 520         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 521
 522         return clock->dot / 5;
 523 }
 524
 525 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 526 {
 527         clock->m = clock->m1 * clock->m2;
 528         clock->p = clock->p1 * clock->p2;
 529         if (WARN_ON(clock->n == 0 || clock->p == 0))
 530                 return 0;
 531         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 532                         clock->n << 22);
 533         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 534
 535         return clock->dot / 5;
 536 }
 537
 538 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 539 /**
 540  * Returns whether the given set of divisors are valid for a given refclk with
 541  * the given connectors.
 542  */
 543
 544 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 545                                const struct intel_limit *limit,
 546                                const struct dpll *clock)
 547 {
 548         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 549                 INTELPllInvalid("n out of range\n");
 550         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 551                 INTELPllInvalid("p1 out of range\n");
 552         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 553                 INTELPllInvalid("m2 out of range\n");
 554         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 555                 INTELPllInvalid("m1 out of range\n");
 556
 557         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 558             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 559                 if (clock->m1 <= clock->m2)
 560                         INTELPllInvalid("m1 <= m2\n");
 561
 562         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 563             !IS_GEN9_LP(dev_priv)) {
 564                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 565                         INTELPllInvalid("p out of range\n");
 566                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 567                         INTELPllInvalid("m out of range\n");
 568         }
 569
 570         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 571                 INTELPllInvalid("vco out of range\n");
 572         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 573          * connector, etc., rather than just a single range.
 574          */
 575         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 576                 INTELPllInvalid("dot out of range\n");
 577
 578         return true;
 579 }
 580
 581 static int
 582 i9xx_select_p2_div(const struct intel_limit *limit,
 583                    const struct intel_crtc_state *crtc_state,
 584                    int target)
 585 {
 586         struct drm_device *dev = crtc_state->base.crtc->dev;
 587
 588         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 589                 /*
 590                  * For LVDS just rely on its current settings for dual-channel.
 591                  * We haven't figured out how to reliably set up different
 592                  * single/dual channel state, if we even can.
 593                  */
 594                 if (intel_is_dual_link_lvds(dev))
 595                         return limit->p2.p2_fast;
 596                 else
 597                         return limit->p2.p2_slow;
 598         } else {
 599                 if (target < limit->p2.dot_limit)
 600                         return limit->p2.p2_slow;
 601                 else
 602                         return limit->p2.p2_fast;
 603         }
 604 }
 605
 606 /*
 607  * Returns a set of divisors for the desired target clock with the given
 608  * refclk, or FALSE.  The returned values represent the clock equation:
 609  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 610  *
 611  * Target and reference clocks are specified in kHz.
 612  *
 613  * If match_clock is provided, then best_clock P divider must match the P
 614  * divider from @match_clock used for LVDS downclocking.
 615  */
 616 static bool
 617 i9xx_find_best_dpll(const struct intel_limit *limit,
 618                     struct intel_crtc_state *crtc_state,
 619                     int target, int refclk, struct dpll *match_clock,
 620                     struct dpll *best_clock)
 621 {
 622         struct drm_device *dev = crtc_state->base.crtc->dev;
 623         struct dpll clock;
 624         int err = target;
 625
 626         memset(best_clock, 0, sizeof(*best_clock));
 627
 628         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 629
 630         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 631              clock.m1++) {
 632                 for (clock.m2 = limit->m2.min;
 633                      clock.m2 <= limit->m2.max; clock.m2++) {
 634                         if (clock.m2 >= clock.m1)
 635                                 break;
 636                         for (clock.n = limit->n.min;
 637                              clock.n <= limit->n.max; clock.n++) {
 638                                 for (clock.p1 = limit->p1.min;
 639                                         clock.p1 <= limit->p1.max; clock.p1++) {
 640                                         int this_err;
 641
 642                                         i9xx_calc_dpll_params(refclk, &clock);
 643                                         if (!intel_PLL_is_valid(to_i915(dev),
 644                                                                 limit,
 645                                                                 &clock))
 646                                                 continue;
 647                                         if (match_clock &&
 648                                             clock.p != match_clock->p)
 649                                                 continue;
 650
 651                                         this_err = abs(clock.dot - target);
 652                                         if (this_err < err) {
 653                                                 *best_clock = clock;
 654                                                 err = this_err;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660
 661         return (err != target);
 662 }
 663
 664 /*
 665  * Returns a set of divisors for the desired target clock with the given
 666  * refclk, or FALSE.  The returned values represent the clock equation:
 667  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 668  *
 669  * Target and reference clocks are specified in kHz.
 670  *
 671  * If match_clock is provided, then best_clock P divider must match the P
 672  * divider from @match_clock used for LVDS downclocking.
 673  */
 674 static bool
 675 pnv_find_best_dpll(const struct intel_limit *limit,
 676                    struct intel_crtc_state *crtc_state,
 677                    int target, int refclk, struct dpll *match_clock,
 678                    struct dpll *best_clock)
 679 {
 680         struct drm_device *dev = crtc_state->base.crtc->dev;
 681         struct dpll clock;
 682         int err = target;
 683
 684         memset(best_clock, 0, sizeof(*best_clock));
 685
 686         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 687
 688         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 689              clock.m1++) {
 690                 for (clock.m2 = limit->m2.min;
 691                      clock.m2 <= limit->m2.max; clock.m2++) {
 692                         for (clock.n = limit->n.min;
 693                              clock.n <= limit->n.max; clock.n++) {
 694                                 for (clock.p1 = limit->p1.min;
 695                                         clock.p1 <= limit->p1.max; clock.p1++) {
 696                                         int this_err;
 697
 698                                         pnv_calc_dpll_params(refclk, &clock);
 699                                         if (!intel_PLL_is_valid(to_i915(dev),
 700                                                                 limit,
 701                                                                 &clock))
 702                                                 continue;
 703                                         if (match_clock &&
 704                                             clock.p != match_clock->p)
 705                                                 continue;
 706
 707                                         this_err = abs(clock.dot - target);
 708                                         if (this_err < err) {
 709                                                 *best_clock = clock;
 710                                                 err = this_err;
 711                                         }
 712                                 }
 713                         }
 714                 }
 715         }
 716
 717         return (err != target);
 718 }
 719
 720 /*
 721  * Returns a set of divisors for the desired target clock with the given
 722  * refclk, or FALSE.  The returned values represent the clock equation:
 723  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 724  *
 725  * Target and reference clocks are specified in kHz.
 726  *
 727  * If match_clock is provided, then best_clock P divider must match the P
 728  * divider from @match_clock used for LVDS downclocking.
 729  */
 730 static bool
 731 g4x_find_best_dpll(const struct intel_limit *limit,
 732                    struct intel_crtc_state *crtc_state,
 733                    int target, int refclk, struct dpll *match_clock,
 734                    struct dpll *best_clock)
 735 {
 736         struct drm_device *dev = crtc_state->base.crtc->dev;
 737         struct dpll clock;
 738         int max_n;
 739         bool found = false;
 740         /* approximately equals target * 0.00585 */
 741         int err_most = (target >> 8) + (target >> 9);
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744
 745         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 746
 747         max_n = limit->n.max;
 748         /* based on hardware requirement, prefer smaller n to precision */
 749         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 750                 /* based on hardware requirement, prefere larger m1,m2 */
 751                 for (clock.m1 = limit->m1.max;
 752                      clock.m1 >= limit->m1.min; clock.m1--) {
 753                         for (clock.m2 = limit->m2.max;
 754                              clock.m2 >= limit->m2.min; clock.m2--) {
 755                                 for (clock.p1 = limit->p1.max;
 756                                      clock.p1 >= limit->p1.min; clock.p1--) {
 757                                         int this_err;
 758
 759                                         i9xx_calc_dpll_params(refclk, &clock);
 760                                         if (!intel_PLL_is_valid(to_i915(dev),
 761                                                                 limit,
 762                                                                 &clock))
 763                                                 continue;
 764
 765                                         this_err = abs(clock.dot - target);
 766                                         if (this_err < err_most) {
 767                                                 *best_clock = clock;
 768                                                 err_most = this_err;
 769                                                 max_n = clock.n;
 770                                                 found = true;
 771                                         }
 772                                 }
 773                         }
 774                 }
 775         }
 776         return found;
 777 }
 778
 779 /*
 780  * Check if the calculated PLL configuration is more optimal compared to the
 781  * best configuration and error found so far. Return the calculated error.
 782  */
 783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 784                                const struct dpll *calculated_clock,
 785                                const struct dpll *best_clock,
 786                                unsigned int best_error_ppm,
 787                                unsigned int *error_ppm)
 788 {
 789         /*
 790          * For CHV ignore the error and consider only the P value.
 791          * Prefer a bigger P value based on HW requirements.
 792          */
 793         if (IS_CHERRYVIEW(to_i915(dev))) {
 794                 *error_ppm = 0;
 795
 796                 return calculated_clock->p > best_clock->p;
 797         }
 798
 799         if (WARN_ON_ONCE(!target_freq))
 800                 return false;
 801
 802         *error_ppm = div_u64(1000000ULL *
 803                                 abs(target_freq - calculated_clock->dot),
 804                              target_freq);
 805         /*
 806          * Prefer a better P value over a better (smaller) error if the error
 807          * is small. Ensure this preference for future configurations too by
 808          * setting the error to 0.
 809          */
 810         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 811                 *error_ppm = 0;
 812
 813                 return true;
 814         }
 815
 816         return *error_ppm + 10 < best_error_ppm;
 817 }
 818
 819 /*
 820  * Returns a set of divisors for the desired target clock with the given
 821  * refclk, or FALSE.  The returned values represent the clock equation:
 822  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 823  */
 824 static bool
 825 vlv_find_best_dpll(const struct intel_limit *limit,
 826                    struct intel_crtc_state *crtc_state,
 827                    int target, int refclk, struct dpll *match_clock,
 828                    struct dpll *best_clock)
 829 {
 830         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 831         struct drm_device *dev = crtc->base.dev;
 832         struct dpll clock;
 833         unsigned int bestppm = 1000000;
 834         /* min update 19.2 MHz */
 835         int max_n = min(limit->n.max, refclk / 19200);
 836         bool found = false;
 837
 838         target *= 5; /* fast clock */
 839
 840         memset(best_clock, 0, sizeof(*best_clock));
 841
 842         /* based on hardware requirement, prefer smaller n to precision */
 843         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 844                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 845                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 846                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 847                                 clock.p = clock.p1 * clock.p2;
 848                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 849                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 850                                         unsigned int ppm;
 851
 852                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 853                                                                      refclk * clock.m1);
 854
 855                                         vlv_calc_dpll_params(refclk, &clock);
 856
 857                                         if (!intel_PLL_is_valid(to_i915(dev),
 858                                                                 limit,
 859                                                                 &clock))
 860                                                 continue;
 861
 862                                         if (!vlv_PLL_is_optimal(dev, target,
 863                                                                 &clock,
 864                                                                 best_clock,
 865                                                                 bestppm, &ppm))
 866                                                 continue;
 867
 868                                         *best_clock = clock;
 869                                         bestppm = ppm;
 870                                         found = true;
 871                                 }
 872                         }
 873                 }
 874         }
 875
 876         return found;
 877 }
 878
 879 /*
 880  * Returns a set of divisors for the desired target clock with the given
 881  * refclk, or FALSE.  The returned values represent the clock equation:
 882  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 883  */
 884 static bool
 885 chv_find_best_dpll(const struct intel_limit *limit,
 886                    struct intel_crtc_state *crtc_state,
 887                    int target, int refclk, struct dpll *match_clock,
 888                    struct dpll *best_clock)
 889 {
 890         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 891         struct drm_device *dev = crtc->base.dev;
 892         unsigned int best_error_ppm;
 893         struct dpll clock;
 894         uint64_t m2;
 895         int found = false;
 896
 897         memset(best_clock, 0, sizeof(*best_clock));
 898         best_error_ppm = 1000000;
 899
 900         /*
 901          * Based on hardware doc, the n always set to 1, and m1 always
 902          * set to 2.  If requires to support 200Mhz refclk, we need to
 903          * revisit this because n may not 1 anymore.
 904          */
 905         clock.n = 1, clock.m1 = 2;
 906         target *= 5;    /* fast clock */
 907
 908         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 909                 for (clock.p2 = limit->p2.p2_fast;
 910                                 clock.p2 >= limit->p2.p2_slow;
 911                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 912                         unsigned int error_ppm;
 913
 914                         clock.p = clock.p1 * clock.p2;
 915
 916                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 917                                         clock.n) << 22, refclk * clock.m1);
 918
 919                         if (m2 > INT_MAX/clock.m1)
 920                                 continue;
 921
 922                         clock.m2 = m2;
 923
 924                         chv_calc_dpll_params(refclk, &clock);
 925
 926                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 927                                 continue;
 928
 929                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 930                                                 best_error_ppm, &error_ppm))
 931                                 continue;
 932
 933                         *best_clock = clock;
 934                         best_error_ppm = error_ppm;
 935                         found = true;
 936                 }
 937         }
 938
 939         return found;
 940 }
 941
 942 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 943                         struct dpll *best_clock)
 944 {
 945         int refclk = 100000;
 946         const struct intel_limit *limit = &intel_limits_bxt;
 947
 948         return chv_find_best_dpll(limit, crtc_state,
 949                                   target_clock, refclk, NULL, best_clock);
 950 }
 951
 952 bool intel_crtc_active(struct intel_crtc *crtc)
 953 {
 954         /* Be paranoid as we can arrive here with only partial
 955          * state retrieved from the hardware during setup.
 956          *
 957          * We can ditch the adjusted_mode.crtc_clock check as soon
 958          * as Haswell has gained clock readout/fastboot support.
 959          *
 960          * We can ditch the crtc->primary->fb check as soon as we can
 961          * properly reconstruct framebuffers.
 962          *
 963          * FIXME: The intel_crtc->active here should be switched to
 964          * crtc->state->active once we have proper CRTC states wired up
 965          * for atomic.
 966          */
 967         return crtc->active && crtc->base.primary->state->fb &&
 968                 crtc->config->base.adjusted_mode.crtc_clock;
 969 }
 970
 971 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 972                                              enum pipe pipe)
 973 {
 974         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 975
 976         return crtc->config->cpu_transcoder;
 977 }
 978
 979 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
 980 {
 981         i915_reg_t reg = PIPEDSL(pipe);
 982         u32 line1, line2;
 983         u32 line_mask;
 984
 985         if (IS_GEN2(dev_priv))
 986                 line_mask = DSL_LINEMASK_GEN2;
 987         else
 988                 line_mask = DSL_LINEMASK_GEN3;
 989
 990         line1 = I915_READ(reg) & line_mask;
 991         msleep(5);
 992         line2 = I915_READ(reg) & line_mask;
 993
 994         return line1 == line2;
 995 }
 996
 997 /*
 998  * intel_wait_for_pipe_off - wait for pipe to turn off
 999  * @crtc: crtc whose pipe to wait for
1000  *
1001  * After disabling a pipe, we can't wait for vblank in the usual way,
1002  * spinning on the vblank interrupt status bit, since we won't actually
1003  * see an interrupt when the pipe is disabled.
1004  *
1005  * On Gen4 and above:
1006  *   wait for the pipe register state bit to turn off
1007  *
1008  * Otherwise:
1009  *   wait for the display line value to settle (it usually
1010  *   ends up stopping at the start of the next frame).
1011  *
1012  */
1013 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1014 {
1015         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1016         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1017         enum pipe pipe = crtc->pipe;
1018
1019         if (INTEL_GEN(dev_priv) >= 4) {
1020                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1021
1022                 /* Wait for the Pipe State to go off */
1023                 if (intel_wait_for_register(dev_priv,
1024                                             reg, I965_PIPECONF_ACTIVE, 0,
1025                                             100))
1026                         WARN(1, "pipe_off wait timed out\n");
1027         } else {
1028                 /* Wait for the display line to settle */
1029                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         }
1032 }
1033
1034 /* Only for pre-ILK configs */
1035 void assert_pll(struct drm_i915_private *dev_priv,
1036                 enum pipe pipe, bool state)
1037 {
1038         u32 val;
1039         bool cur_state;
1040
1041         val = I915_READ(DPLL(pipe));
1042         cur_state = !!(val & DPLL_VCO_ENABLE);
1043         I915_STATE_WARN(cur_state != state,
1044              "PLL state assertion failure (expected %s, current %s)\n",
1045                         onoff(state), onoff(cur_state));
1046 }
1047
1048 /* XXX: the dsi pll is shared between MIPI DSI ports */
1049 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1050 {
1051         u32 val;
1052         bool cur_state;
1053
1054         mutex_lock(&dev_priv->sb_lock);
1055         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1056         mutex_unlock(&dev_priv->sb_lock);
1057
1058         cur_state = val & DSI_PLL_VCO_EN;
1059         I915_STATE_WARN(cur_state != state,
1060              "DSI PLL state assertion failure (expected %s, current %s)\n",
1061                         onoff(state), onoff(cur_state));
1062 }
1063
1064 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1065                           enum pipe pipe, bool state)
1066 {
1067         bool cur_state;
1068         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1069                                                                       pipe);
1070
1071         if (HAS_DDI(dev_priv)) {
1072                 /* DDI does not have a specific FDI_TX register */
1073                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1074                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1075         } else {
1076                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1077                 cur_state = !!(val & FDI_TX_ENABLE);
1078         }
1079         I915_STATE_WARN(cur_state != state,
1080              "FDI TX state assertion failure (expected %s, current %s)\n",
1081                         onoff(state), onoff(cur_state));
1082 }
1083 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1084 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1085
1086 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1087                           enum pipe pipe, bool state)
1088 {
1089         u32 val;
1090         bool cur_state;
1091
1092         val = I915_READ(FDI_RX_CTL(pipe));
1093         cur_state = !!(val & FDI_RX_ENABLE);
1094         I915_STATE_WARN(cur_state != state,
1095              "FDI RX state assertion failure (expected %s, current %s)\n",
1096                         onoff(state), onoff(cur_state));
1097 }
1098 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1099 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1100
1101 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1102                                       enum pipe pipe)
1103 {
1104         u32 val;
1105
1106         /* ILK FDI PLL is always enabled */
1107         if (IS_GEN5(dev_priv))
1108                 return;
1109
1110         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1111         if (HAS_DDI(dev_priv))
1112                 return;
1113
1114         val = I915_READ(FDI_TX_CTL(pipe));
1115         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1116 }
1117
1118 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1119                        enum pipe pipe, bool state)
1120 {
1121         u32 val;
1122         bool cur_state;
1123
1124         val = I915_READ(FDI_RX_CTL(pipe));
1125         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1126         I915_STATE_WARN(cur_state != state,
1127              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1128                         onoff(state), onoff(cur_state));
1129 }
1130
1131 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1132 {
1133         i915_reg_t pp_reg;
1134         u32 val;
1135         enum pipe panel_pipe = PIPE_A;
1136         bool locked = true;
1137
1138         if (WARN_ON(HAS_DDI(dev_priv)))
1139                 return;
1140
1141         if (HAS_PCH_SPLIT(dev_priv)) {
1142                 u32 port_sel;
1143
1144                 pp_reg = PP_CONTROL(0);
1145                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1146
1147                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1148                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1149                         panel_pipe = PIPE_B;
1150                 /* XXX: else fix for eDP */
1151         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1152                 /* presumably write lock depends on pipe, not port select */
1153                 pp_reg = PP_CONTROL(pipe);
1154                 panel_pipe = pipe;
1155         } else {
1156                 pp_reg = PP_CONTROL(0);
1157                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1158                         panel_pipe = PIPE_B;
1159         }
1160
1161         val = I915_READ(pp_reg);
1162         if (!(val & PANEL_POWER_ON) ||
1163             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1164                 locked = false;
1165
1166         I915_STATE_WARN(panel_pipe == pipe && locked,
1167              "panel assertion failure, pipe %c regs locked\n",
1168              pipe_name(pipe));
1169 }
1170
1171 static void assert_cursor(struct drm_i915_private *dev_priv,
1172                           enum pipe pipe, bool state)
1173 {
1174         bool cur_state;
1175
1176         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1177                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1178         else
1179                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1180
1181         I915_STATE_WARN(cur_state != state,
1182              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1183                         pipe_name(pipe), onoff(state), onoff(cur_state));
1184 }
1185 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1186 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1187
1188 void assert_pipe(struct drm_i915_private *dev_priv,
1189                  enum pipe pipe, bool state)
1190 {
1191         bool cur_state;
1192         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1193                                                                       pipe);
1194         enum intel_display_power_domain power_domain;
1195
1196         /* we keep both pipes enabled on 830 */
1197         if (IS_I830(dev_priv))
1198                 state = true;
1199
1200         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203                 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205                 intel_display_power_put(dev_priv, power_domain);
1206         } else {
1207                 cur_state = false;
1208         }
1209
1210         I915_STATE_WARN(cur_state != state,
1211              "pipe %c assertion failure (expected %s, current %s)\n",
1212                         pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216                          enum plane plane, bool state)
1217 {
1218         u32 val;
1219         bool cur_state;
1220
1221         val = I915_READ(DSPCNTR(plane));
1222         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223         I915_STATE_WARN(cur_state != state,
1224              "plane %c assertion failure (expected %s, current %s)\n",
1225                         plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232                                    enum pipe pipe)
1233 {
1234         int i;
1235
1236         /* Primary planes are fixed to pipes on gen4+ */
1237         if (INTEL_GEN(dev_priv) >= 4) {
1238                 u32 val = I915_READ(DSPCNTR(pipe));
1239                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240                      "plane %c assertion failure, should be disabled but not\n",
1241                      plane_name(pipe));
1242                 return;
1243         }
1244
1245         /* Need to check both planes against the pipe */
1246         for_each_pipe(dev_priv, i) {
1247                 u32 val = I915_READ(DSPCNTR(i));
1248                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249                         DISPPLANE_SEL_PIPE_SHIFT;
1250                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252                      plane_name(i), pipe_name(pipe));
1253         }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257                                     enum pipe pipe)
1258 {
1259         int sprite;
1260
1261         if (INTEL_GEN(dev_priv) >= 9) {
1262                 for_each_sprite(dev_priv, pipe, sprite) {
1263                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266                              sprite, pipe_name(pipe));
1267                 }
1268         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269                 for_each_sprite(dev_priv, pipe, sprite) {
1270                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271                         I915_STATE_WARN(val & SP_ENABLE,
1272                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273                              sprite_name(pipe, sprite), pipe_name(pipe));
1274                 }
1275         } else if (INTEL_GEN(dev_priv) >= 7) {
1276                 u32 val = I915_READ(SPRCTL(pipe));
1277                 I915_STATE_WARN(val & SPRITE_ENABLE,
1278                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279                      plane_name(pipe), pipe_name(pipe));
1280         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1281                 u32 val = I915_READ(DVSCNTR(pipe));
1282                 I915_STATE_WARN(val & DVS_ENABLE,
1283                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                      plane_name(pipe), pipe_name(pipe));
1285         }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291                 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                     enum pipe pipe)
1296 {
1297         u32 val;
1298         bool enabled;
1299
1300         val = I915_READ(PCH_TRANSCONF(pipe));
1301         enabled = !!(val & TRANS_ENABLE);
1302         I915_STATE_WARN(enabled,
1303              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304              pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308                             enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310         if ((val & DP_PORT_EN) == 0)
1311                 return false;
1312
1313         if (HAS_PCH_CPT(dev_priv)) {
1314                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else if (IS_CHERRYVIEW(dev_priv)) {
1318                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & SDVO_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv)) {
1334                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335                         return false;
1336         } else if (IS_CHERRYVIEW(dev_priv)) {
1337                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338                         return false;
1339         } else {
1340                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341                         return false;
1342         }
1343         return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347                               enum pipe pipe, u32 val)
1348 {
1349         if ((val & LVDS_PORT_EN) == 0)
1350                 return false;
1351
1352         if (HAS_PCH_CPT(dev_priv)) {
1353                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354                         return false;
1355         } else {
1356                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357                         return false;
1358         }
1359         return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363                               enum pipe pipe, u32 val)
1364 {
1365         if ((val & ADPA_DAC_ENABLE) == 0)
1366                 return false;
1367         if (HAS_PCH_CPT(dev_priv)) {
1368                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369                         return false;
1370         } else {
1371                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372                         return false;
1373         }
1374         return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378                                    enum pipe pipe, i915_reg_t reg,
1379                                    u32 port_sel)
1380 {
1381         u32 val = I915_READ(reg);
1382         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384              i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387              && (val & DP_PIPEB_SELECT),
1388              "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392                                      enum pipe pipe, i915_reg_t reg)
1393 {
1394         u32 val = I915_READ(reg);
1395         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397              i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400              && (val & SDVO_PIPE_B_SELECT),
1401              "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405                                       enum pipe pipe)
1406 {
1407         u32 val;
1408
1409         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413         val = I915_READ(PCH_ADPA);
1414         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415              "PCH VGA enabled on transcoder %c, should be disabled\n",
1416              pipe_name(pipe));
1417
1418         val = I915_READ(PCH_LVDS);
1419         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429                             const struct intel_crtc_state *pipe_config)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432         enum pipe pipe = crtc->pipe;
1433
1434         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435         POSTING_READ(DPLL(pipe));
1436         udelay(150);
1437
1438         if (intel_wait_for_register(dev_priv,
1439                                     DPLL(pipe),
1440                                     DPLL_LOCK_VLV,
1441                                     DPLL_LOCK_VLV,
1442                                     1))
1443                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447                            const struct intel_crtc_state *pipe_config)
1448 {
1449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450         enum pipe pipe = crtc->pipe;
1451
1452         assert_pipe_disabled(dev_priv, pipe);
1453
1454         /* PLL is protected by panel, make sure we can write it */
1455         assert_panel_unlocked(dev_priv, pipe);
1456
1457         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458                 _vlv_enable_pll(crtc, pipe_config);
1459
1460         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461         POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466                             const struct intel_crtc_state *pipe_config)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469         enum pipe pipe = crtc->pipe;
1470         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471         u32 tmp;
1472
1473         mutex_lock(&dev_priv->sb_lock);
1474
1475         /* Enable back the 10bit clock to display controller */
1476         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477         tmp |= DPIO_DCLKP_EN;
1478         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480         mutex_unlock(&dev_priv->sb_lock);
1481
1482         /*
1483          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484          */
1485         udelay(1);
1486
1487         /* Enable PLL */
1488         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490         /* Check PLL is locked */
1491         if (intel_wait_for_register(dev_priv,
1492                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493                                     1))
1494                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498                            const struct intel_crtc_state *pipe_config)
1499 {
1500         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501         enum pipe pipe = crtc->pipe;
1502
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         /* PLL is protected by panel, make sure we can write it */
1506         assert_panel_unlocked(dev_priv, pipe);
1507
1508         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509                 _chv_enable_pll(crtc, pipe_config);
1510
1511         if (pipe != PIPE_A) {
1512                 /*
1513                  * WaPixelRepeatModeFixForC0:chv
1514                  *
1515                  * DPLLCMD is AWOL. Use chicken bits to propagate
1516                  * the value from DPLLBMD to either pipe B or C.
1517                  */
1518                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520                 I915_WRITE(CBR4_VLV, 0);
1521                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523                 /*
1524                  * DPLLB VGA mode also seems to cause problems.
1525                  * We should always have it disabled.
1526                  */
1527                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528         } else {
1529                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530                 POSTING_READ(DPLL_MD(pipe));
1531         }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536         struct intel_crtc *crtc;
1537         int count = 0;
1538
1539         for_each_intel_crtc(&dev_priv->drm, crtc) {
1540                 count += crtc->base.state->active &&
1541                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542         }
1543
1544         return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         i915_reg_t reg = DPLL(crtc->pipe);
1551         u32 dpll = crtc->config->dpll_hw_state.dpll;
1552         int i;
1553
1554         assert_pipe_disabled(dev_priv, crtc->pipe);
1555
1556         /* PLL is protected by panel, make sure we can write it */
1557         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1558                 assert_panel_unlocked(dev_priv, crtc->pipe);
1559
1560         /* Enable DVO 2x clock on both PLLs if necessary */
1561         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1562                 /*
1563                  * It appears to be important that we don't enable this
1564                  * for the current pipe before otherwise configuring the
1565                  * PLL. No idea how this should be handled if multiple
1566                  * DVO outputs are enabled simultaneosly.
1567                  */
1568                 dpll |= DPLL_DVO_2X_MODE;
1569                 I915_WRITE(DPLL(!crtc->pipe),
1570                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1571         }
1572
1573         /*
1574          * Apparently we need to have VGA mode enabled prior to changing
1575          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1576          * dividers, even though the register value does change.
1577          */
1578         I915_WRITE(reg, 0);
1579
1580         I915_WRITE(reg, dpll);
1581
1582         /* Wait for the clocks to stabilize. */
1583         POSTING_READ(reg);
1584         udelay(150);
1585
1586         if (INTEL_GEN(dev_priv) >= 4) {
1587                 I915_WRITE(DPLL_MD(crtc->pipe),
1588                            crtc->config->dpll_hw_state.dpll_md);
1589         } else {
1590                 /* The pixel multiplier can only be updated once the
1591                  * DPLL is enabled and the clocks are stable.
1592                  *
1593                  * So write it again.
1594                  */
1595                 I915_WRITE(reg, dpll);
1596         }
1597
1598         /* We do this three times for luck */
1599         for (i = 0; i < 3; i++) {
1600                 I915_WRITE(reg, dpll);
1601                 POSTING_READ(reg);
1602                 udelay(150); /* wait for warmup */
1603         }
1604 }
1605
1606 /**
1607  * i9xx_disable_pll - disable a PLL
1608  * @dev_priv: i915 private structure
1609  * @pipe: pipe PLL to disable
1610  *
1611  * Disable the PLL for @pipe, making sure the pipe is off first.
1612  *
1613  * Note!  This is for pre-ILK only.
1614  */
1615 static void i9xx_disable_pll(struct intel_crtc *crtc)
1616 {
1617         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1618         enum pipe pipe = crtc->pipe;
1619
1620         /* Disable DVO 2x clock on both PLLs if necessary */
1621         if (IS_I830(dev_priv) &&
1622             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1623             !intel_num_dvo_pipes(dev_priv)) {
1624                 I915_WRITE(DPLL(PIPE_B),
1625                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1626                 I915_WRITE(DPLL(PIPE_A),
1627                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1628         }
1629
1630         /* Don't disable pipe or pipe PLLs if needed */
1631         if (IS_I830(dev_priv))
1632                 return;
1633
1634         /* Make sure the pipe isn't still relying on us */
1635         assert_pipe_disabled(dev_priv, pipe);
1636
1637         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1638         POSTING_READ(DPLL(pipe));
1639 }
1640
1641 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1642 {
1643         u32 val;
1644
1645         /* Make sure the pipe isn't still relying on us */
1646         assert_pipe_disabled(dev_priv, pipe);
1647
1648         val = DPLL_INTEGRATED_REF_CLK_VLV |
1649                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1650         if (pipe != PIPE_A)
1651                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1652
1653         I915_WRITE(DPLL(pipe), val);
1654         POSTING_READ(DPLL(pipe));
1655 }
1656
1657 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1658 {
1659         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1660         u32 val;
1661
1662         /* Make sure the pipe isn't still relying on us */
1663         assert_pipe_disabled(dev_priv, pipe);
1664
1665         val = DPLL_SSC_REF_CLK_CHV |
1666                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1667         if (pipe != PIPE_A)
1668                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1669
1670         I915_WRITE(DPLL(pipe), val);
1671         POSTING_READ(DPLL(pipe));
1672
1673         mutex_lock(&dev_priv->sb_lock);
1674
1675         /* Disable 10bit clock to display controller */
1676         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1677         val &= ~DPIO_DCLKP_EN;
1678         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1679
1680         mutex_unlock(&dev_priv->sb_lock);
1681 }
1682
1683 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1684                          struct intel_digital_port *dport,
1685                          unsigned int expected_mask)
1686 {
1687         u32 port_mask;
1688         i915_reg_t dpll_reg;
1689
1690         switch (dport->port) {
1691         case PORT_B:
1692                 port_mask = DPLL_PORTB_READY_MASK;
1693                 dpll_reg = DPLL(0);
1694                 break;
1695         case PORT_C:
1696                 port_mask = DPLL_PORTC_READY_MASK;
1697                 dpll_reg = DPLL(0);
1698                 expected_mask <<= 4;
1699                 break;
1700         case PORT_D:
1701                 port_mask = DPLL_PORTD_READY_MASK;
1702                 dpll_reg = DPIO_PHY_STATUS;
1703                 break;
1704         default:
1705                 BUG();
1706         }
1707
1708         if (intel_wait_for_register(dev_priv,
1709                                     dpll_reg, port_mask, expected_mask,
1710                                     1000))
1711                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1712                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1713 }
1714
1715 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1716                                            enum pipe pipe)
1717 {
1718         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1719                                                                 pipe);
1720         i915_reg_t reg;
1721         uint32_t val, pipeconf_val;
1722
1723         /* Make sure PCH DPLL is enabled */
1724         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1725
1726         /* FDI must be feeding us bits for PCH ports */
1727         assert_fdi_tx_enabled(dev_priv, pipe);
1728         assert_fdi_rx_enabled(dev_priv, pipe);
1729
1730         if (HAS_PCH_CPT(dev_priv)) {
1731                 /* Workaround: Set the timing override bit before enabling the
1732                  * pch transcoder. */
1733                 reg = TRANS_CHICKEN2(pipe);
1734                 val = I915_READ(reg);
1735                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1736                 I915_WRITE(reg, val);
1737         }
1738
1739         reg = PCH_TRANSCONF(pipe);
1740         val = I915_READ(reg);
1741         pipeconf_val = I915_READ(PIPECONF(pipe));
1742
1743         if (HAS_PCH_IBX(dev_priv)) {
1744                 /*
1745                  * Make the BPC in transcoder be consistent with
1746                  * that in pipeconf reg. For HDMI we must use 8bpc
1747                  * here for both 8bpc and 12bpc.
1748                  */
1749                 val &= ~PIPECONF_BPC_MASK;
1750                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1751                         val |= PIPECONF_8BPC;
1752                 else
1753                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1754         }
1755
1756         val &= ~TRANS_INTERLACE_MASK;
1757         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1758                 if (HAS_PCH_IBX(dev_priv) &&
1759                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1760                         val |= TRANS_LEGACY_INTERLACED_ILK;
1761                 else
1762                         val |= TRANS_INTERLACED;
1763         else
1764                 val |= TRANS_PROGRESSIVE;
1765
1766         I915_WRITE(reg, val | TRANS_ENABLE);
1767         if (intel_wait_for_register(dev_priv,
1768                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1769                                     100))
1770                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1771 }
1772
1773 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1774                                       enum transcoder cpu_transcoder)
1775 {
1776         u32 val, pipeconf_val;
1777
1778         /* FDI must be feeding us bits for PCH ports */
1779         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1780         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1781
1782         /* Workaround: set timing override bit. */
1783         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1784         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1785         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1786
1787         val = TRANS_ENABLE;
1788         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1789
1790         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1791             PIPECONF_INTERLACED_ILK)
1792                 val |= TRANS_INTERLACED;
1793         else
1794                 val |= TRANS_PROGRESSIVE;
1795
1796         I915_WRITE(LPT_TRANSCONF, val);
1797         if (intel_wait_for_register(dev_priv,
1798                                     LPT_TRANSCONF,
1799                                     TRANS_STATE_ENABLE,
1800                                     TRANS_STATE_ENABLE,
1801                                     100))
1802                 DRM_ERROR("Failed to enable PCH transcoder\n");
1803 }
1804
1805 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1806                                             enum pipe pipe)
1807 {
1808         i915_reg_t reg;
1809         uint32_t val;
1810
1811         /* FDI relies on the transcoder */
1812         assert_fdi_tx_disabled(dev_priv, pipe);
1813         assert_fdi_rx_disabled(dev_priv, pipe);
1814
1815         /* Ports must be off as well */
1816         assert_pch_ports_disabled(dev_priv, pipe);
1817
1818         reg = PCH_TRANSCONF(pipe);
1819         val = I915_READ(reg);
1820         val &= ~TRANS_ENABLE;
1821         I915_WRITE(reg, val);
1822         /* wait for PCH transcoder off, transcoder state */
1823         if (intel_wait_for_register(dev_priv,
1824                                     reg, TRANS_STATE_ENABLE, 0,
1825                                     50))
1826                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1827
1828         if (HAS_PCH_CPT(dev_priv)) {
1829                 /* Workaround: Clear the timing override chicken bit again. */
1830                 reg = TRANS_CHICKEN2(pipe);
1831                 val = I915_READ(reg);
1832                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1833                 I915_WRITE(reg, val);
1834         }
1835 }
1836
1837 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1838 {
1839         u32 val;
1840
1841         val = I915_READ(LPT_TRANSCONF);
1842         val &= ~TRANS_ENABLE;
1843         I915_WRITE(LPT_TRANSCONF, val);
1844         /* wait for PCH transcoder off, transcoder state */
1845         if (intel_wait_for_register(dev_priv,
1846                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1847                                     50))
1848                 DRM_ERROR("Failed to disable PCH transcoder\n");
1849
1850         /* Workaround: clear timing override bit. */
1851         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1852         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1853         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1854 }
1855
1856 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1857 {
1858         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1859
1860         WARN_ON(!crtc->config->has_pch_encoder);
1861
1862         if (HAS_PCH_LPT(dev_priv))
1863                 return TRANSCODER_A;
1864         else
1865                 return (enum transcoder) crtc->pipe;
1866 }
1867
1868 /**
1869  * intel_enable_pipe - enable a pipe, asserting requirements
1870  * @crtc: crtc responsible for the pipe
1871  *
1872  * Enable @crtc's pipe, making sure that various hardware specific requirements
1873  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1874  */
1875 static void intel_enable_pipe(struct intel_crtc *crtc)
1876 {
1877         struct drm_device *dev = crtc->base.dev;
1878         struct drm_i915_private *dev_priv = to_i915(dev);
1879         enum pipe pipe = crtc->pipe;
1880         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1881         i915_reg_t reg;
1882         u32 val;
1883
1884         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1885
1886         assert_planes_disabled(dev_priv, pipe);
1887         assert_cursor_disabled(dev_priv, pipe);
1888         assert_sprites_disabled(dev_priv, pipe);
1889
1890         /*
1891          * A pipe without a PLL won't actually be able to drive bits from
1892          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1893          * need the check.
1894          */
1895         if (HAS_GMCH_DISPLAY(dev_priv)) {
1896                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1897                         assert_dsi_pll_enabled(dev_priv);
1898                 else
1899                         assert_pll_enabled(dev_priv, pipe);
1900         } else {
1901                 if (crtc->config->has_pch_encoder) {
1902                         /* if driving the PCH, we need FDI enabled */
1903                         assert_fdi_rx_pll_enabled(dev_priv,
1904                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1905                         assert_fdi_tx_pll_enabled(dev_priv,
1906                                                   (enum pipe) cpu_transcoder);
1907                 }
1908                 /* FIXME: assert CPU port conditions for SNB+ */
1909         }
1910
1911         reg = PIPECONF(cpu_transcoder);
1912         val = I915_READ(reg);
1913         if (val & PIPECONF_ENABLE) {
1914                 /* we keep both pipes enabled on 830 */
1915                 WARN_ON(!IS_I830(dev_priv));
1916                 return;
1917         }
1918
1919         I915_WRITE(reg, val | PIPECONF_ENABLE);
1920         POSTING_READ(reg);
1921
1922         /*
1923          * Until the pipe starts DSL will read as 0, which would cause
1924          * an apparent vblank timestamp jump, which messes up also the
1925          * frame count when it's derived from the timestamps. So let's
1926          * wait for the pipe to start properly before we call
1927          * drm_crtc_vblank_on()
1928          */
1929         if (dev->max_vblank_count == 0 &&
1930             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1931                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1932 }
1933
1934 /**
1935  * intel_disable_pipe - disable a pipe, asserting requirements
1936  * @crtc: crtc whose pipes is to be disabled
1937  *
1938  * Disable the pipe of @crtc, making sure that various hardware
1939  * specific requirements are met, if applicable, e.g. plane
1940  * disabled, panel fitter off, etc.
1941  *
1942  * Will wait until the pipe has shut down before returning.
1943  */
1944 static void intel_disable_pipe(struct intel_crtc *crtc)
1945 {
1946         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1947         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1948         enum pipe pipe = crtc->pipe;
1949         i915_reg_t reg;
1950         u32 val;
1951
1952         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1953
1954         /*
1955          * Make sure planes won't keep trying to pump pixels to us,
1956          * or we might hang the display.
1957          */
1958         assert_planes_disabled(dev_priv, pipe);
1959         assert_cursor_disabled(dev_priv, pipe);
1960         assert_sprites_disabled(dev_priv, pipe);
1961
1962         reg = PIPECONF(cpu_transcoder);
1963         val = I915_READ(reg);
1964         if ((val & PIPECONF_ENABLE) == 0)
1965                 return;
1966
1967         /*
1968          * Double wide has implications for planes
1969          * so best keep it disabled when not needed.
1970          */
1971         if (crtc->config->double_wide)
1972                 val &= ~PIPECONF_DOUBLE_WIDE;
1973
1974         /* Don't disable pipe or pipe PLLs if needed */
1975         if (!IS_I830(dev_priv))
1976                 val &= ~PIPECONF_ENABLE;
1977
1978         I915_WRITE(reg, val);
1979         if ((val & PIPECONF_ENABLE) == 0)
1980                 intel_wait_for_pipe_off(crtc);
1981 }
1982
1983 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1984 {
1985         return IS_GEN2(dev_priv) ? 2048 : 4096;
1986 }
1987
1988 static unsigned int
1989 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1990 {
1991         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1992         unsigned int cpp = fb->format->cpp[plane];
1993
1994         switch (fb->modifier) {
1995         case DRM_FORMAT_MOD_LINEAR:
1996                 return cpp;
1997         case I915_FORMAT_MOD_X_TILED:
1998                 if (IS_GEN2(dev_priv))
1999                         return 128;
2000                 else
2001                         return 512;
2002         case I915_FORMAT_MOD_Y_TILED:
2003                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2004                         return 128;
2005                 else
2006                         return 512;
2007         case I915_FORMAT_MOD_Yf_TILED:
2008                 switch (cpp) {
2009                 case 1:
2010                         return 64;
2011                 case 2:
2012                 case 4:
2013                         return 128;
2014                 case 8:
2015                 case 16:
2016                         return 256;
2017                 default:
2018                         MISSING_CASE(cpp);
2019                         return cpp;
2020                 }
2021                 break;
2022         default:
2023                 MISSING_CASE(fb->modifier);
2024                 return cpp;
2025         }
2026 }
2027
2028 static unsigned int
2029 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2030 {
2031         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2032                 return 1;
2033         else
2034                 return intel_tile_size(to_i915(fb->dev)) /
2035                         intel_tile_width_bytes(fb, plane);
2036 }
2037
2038 /* Return the tile dimensions in pixel units */
2039 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2040                             unsigned int *tile_width,
2041                             unsigned int *tile_height)
2042 {
2043         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2044         unsigned int cpp = fb->format->cpp[plane];
2045
2046         *tile_width = tile_width_bytes / cpp;
2047         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2048 }
2049
2050 unsigned int
2051 intel_fb_align_height(const struct drm_framebuffer *fb,
2052                       int plane, unsigned int height)
2053 {
2054         unsigned int tile_height = intel_tile_height(fb, plane);
2055
2056         return ALIGN(height, tile_height);
2057 }
2058
2059 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2060 {
2061         unsigned int size = 0;
2062         int i;
2063
2064         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2065                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2066
2067         return size;
2068 }
2069
2070 static void
2071 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2072                         const struct drm_framebuffer *fb,
2073                         unsigned int rotation)
2074 {
2075         view->type = I915_GGTT_VIEW_NORMAL;
2076         if (drm_rotation_90_or_270(rotation)) {
2077                 view->type = I915_GGTT_VIEW_ROTATED;
2078                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2079         }
2080 }
2081
2082 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2083 {
2084         if (IS_I830(dev_priv))
2085                 return 16 * 1024;
2086         else if (IS_I85X(dev_priv))
2087                 return 256;
2088         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2089                 return 32;
2090         else
2091                 return 4 * 1024;
2092 }
2093
2094 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2095 {
2096         if (INTEL_INFO(dev_priv)->gen >= 9)
2097                 return 256 * 1024;
2098         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2099                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2100                 return 128 * 1024;
2101         else if (INTEL_INFO(dev_priv)->gen >= 4)
2102                 return 4 * 1024;
2103         else
2104                 return 0;
2105 }
2106
2107 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2108                                          int plane)
2109 {
2110         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2111
2112         /* AUX_DIST needs only 4K alignment */
2113         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2114                 return 4096;
2115
2116         switch (fb->modifier) {
2117         case DRM_FORMAT_MOD_LINEAR:
2118                 return intel_linear_alignment(dev_priv);
2119         case I915_FORMAT_MOD_X_TILED:
2120                 if (INTEL_GEN(dev_priv) >= 9)
2121                         return 256 * 1024;
2122                 return 0;
2123         case I915_FORMAT_MOD_Y_TILED:
2124         case I915_FORMAT_MOD_Yf_TILED:
2125                 return 1 * 1024 * 1024;
2126         default:
2127                 MISSING_CASE(fb->modifier);
2128                 return 0;
2129         }
2130 }
2131
2132 struct i915_vma *
2133 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2134 {
2135         struct drm_device *dev = fb->dev;
2136         struct drm_i915_private *dev_priv = to_i915(dev);
2137         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2138         struct i915_ggtt_view view;
2139         struct i915_vma *vma;
2140         u32 alignment;
2141
2142         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2143
2144         alignment = intel_surf_alignment(fb, 0);
2145
2146         intel_fill_fb_ggtt_view(&view, fb, rotation);
2147
2148         /* Note that the w/a also requires 64 PTE of padding following the
2149          * bo. We currently fill all unused PTE with the shadow page and so
2150          * we should always have valid PTE following the scanout preventing
2151          * the VT-d warning.
2152          */
2153         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2154                 alignment = 256 * 1024;
2155
2156         /*
2157          * Global gtt pte registers are special registers which actually forward
2158          * writes to a chunk of system memory. Which means that there is no risk
2159          * that the register values disappear as soon as we call
2160          * intel_runtime_pm_put(), so it is correct to wrap only the
2161          * pin/unpin/fence and not more.
2162          */
2163         intel_runtime_pm_get(dev_priv);
2164
2165         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2166         if (IS_ERR(vma))
2167                 goto err;
2168
2169         if (i915_vma_is_map_and_fenceable(vma)) {
2170                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2171                  * fence, whereas 965+ only requires a fence if using
2172                  * framebuffer compression.  For simplicity, we always, when
2173                  * possible, install a fence as the cost is not that onerous.
2174                  *
2175                  * If we fail to fence the tiled scanout, then either the
2176                  * modeset will reject the change (which is highly unlikely as
2177                  * the affected systems, all but one, do not have unmappable
2178                  * space) or we will not be able to enable full powersaving
2179                  * techniques (also likely not to apply due to various limits
2180                  * FBC and the like impose on the size of the buffer, which
2181                  * presumably we violated anyway with this unmappable buffer).
2182                  * Anyway, it is presumably better to stumble onwards with
2183                  * something and try to run the system in a "less than optimal"
2184                  * mode that matches the user configuration.
2185                  */
2186                 if (i915_vma_get_fence(vma) == 0)
2187                         i915_vma_pin_fence(vma);
2188         }
2189
2190         i915_vma_get(vma);
2191 err:
2192         intel_runtime_pm_put(dev_priv);
2193         return vma;
2194 }
2195
2196 void intel_unpin_fb_vma(struct i915_vma *vma)
2197 {
2198         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2199
2200         i915_vma_unpin_fence(vma);
2201         i915_gem_object_unpin_from_display_plane(vma);
2202         i915_vma_put(vma);
2203 }
2204
2205 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2206                           unsigned int rotation)
2207 {
2208         if (drm_rotation_90_or_270(rotation))
2209                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2210         else
2211                 return fb->pitches[plane];
2212 }
2213
2214 /*
2215  * Convert the x/y offsets into a linear offset.
2216  * Only valid with 0/180 degree rotation, which is fine since linear
2217  * offset is only used with linear buffers on pre-hsw and tiled buffers
2218  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2219  */
2220 u32 intel_fb_xy_to_linear(int x, int y,
2221                           const struct intel_plane_state *state,
2222                           int plane)
2223 {
2224         const struct drm_framebuffer *fb = state->base.fb;
2225         unsigned int cpp = fb->format->cpp[plane];
2226         unsigned int pitch = fb->pitches[plane];
2227
2228         return y * pitch + x * cpp;
2229 }
2230
2231 /*
2232  * Add the x/y offsets derived from fb->offsets[] to the user
2233  * specified plane src x/y offsets. The resulting x/y offsets
2234  * specify the start of scanout from the beginning of the gtt mapping.
2235  */
2236 void intel_add_fb_offsets(int *x, int *y,
2237                           const struct intel_plane_state *state,
2238                           int plane)
2239
2240 {
2241         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2242         unsigned int rotation = state->base.rotation;
2243
2244         if (drm_rotation_90_or_270(rotation)) {
2245                 *x += intel_fb->rotated[plane].x;
2246                 *y += intel_fb->rotated[plane].y;
2247         } else {
2248                 *x += intel_fb->normal[plane].x;
2249                 *y += intel_fb->normal[plane].y;
2250         }
2251 }
2252
2253 /*
2254  * Input tile dimensions and pitch must already be
2255  * rotated to match x and y, and in pixel units.
2256  */
2257 static u32 _intel_adjust_tile_offset(int *x, int *y,
2258                                      unsigned int tile_width,
2259                                      unsigned int tile_height,
2260                                      unsigned int tile_size,
2261                                      unsigned int pitch_tiles,
2262                                      u32 old_offset,
2263                                      u32 new_offset)
2264 {
2265         unsigned int pitch_pixels = pitch_tiles * tile_width;
2266         unsigned int tiles;
2267
2268         WARN_ON(old_offset & (tile_size - 1));
2269         WARN_ON(new_offset & (tile_size - 1));
2270         WARN_ON(new_offset > old_offset);
2271
2272         tiles = (old_offset - new_offset) / tile_size;
2273
2274         *y += tiles / pitch_tiles * tile_height;
2275         *x += tiles % pitch_tiles * tile_width;
2276
2277         /* minimize x in case it got needlessly big */
2278         *y += *x / pitch_pixels * tile_height;
2279         *x %= pitch_pixels;
2280
2281         return new_offset;
2282 }
2283
2284 /*
2285  * Adjust the tile offset by moving the difference into
2286  * the x/y offsets.
2287  */
2288 static u32 intel_adjust_tile_offset(int *x, int *y,
2289                                     const struct intel_plane_state *state, int plane,
2290                                     u32 old_offset, u32 new_offset)
2291 {
2292         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2293         const struct drm_framebuffer *fb = state->base.fb;
2294         unsigned int cpp = fb->format->cpp[plane];
2295         unsigned int rotation = state->base.rotation;
2296         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2297
2298         WARN_ON(new_offset > old_offset);
2299
2300         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2301                 unsigned int tile_size, tile_width, tile_height;
2302                 unsigned int pitch_tiles;
2303
2304                 tile_size = intel_tile_size(dev_priv);
2305                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2306
2307                 if (drm_rotation_90_or_270(rotation)) {
2308                         pitch_tiles = pitch / tile_height;
2309                         swap(tile_width, tile_height);
2310                 } else {
2311                         pitch_tiles = pitch / (tile_width * cpp);
2312                 }
2313
2314                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2315                                           tile_size, pitch_tiles,
2316                                           old_offset, new_offset);
2317         } else {
2318                 old_offset += *y * pitch + *x * cpp;
2319
2320                 *y = (old_offset - new_offset) / pitch;
2321                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2322         }
2323
2324         return new_offset;
2325 }
2326
2327 /*
2328  * Computes the linear offset to the base tile and adjusts
2329  * x, y. bytes per pixel is assumed to be a power-of-two.
2330  *
2331  * In the 90/270 rotated case, x and y are assumed
2332  * to be already rotated to match the rotated GTT view, and
2333  * pitch is the tile_height aligned framebuffer height.
2334  *
2335  * This function is used when computing the derived information
2336  * under intel_framebuffer, so using any of that information
2337  * here is not allowed. Anything under drm_framebuffer can be
2338  * used. This is why the user has to pass in the pitch since it
2339  * is specified in the rotated orientation.
2340  */
2341 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2342                                       int *x, int *y,
2343                                       const struct drm_framebuffer *fb, int plane,
2344                                       unsigned int pitch,
2345                                       unsigned int rotation,
2346                                       u32 alignment)
2347 {
2348         uint64_t fb_modifier = fb->modifier;
2349         unsigned int cpp = fb->format->cpp[plane];
2350         u32 offset, offset_aligned;
2351
2352         if (alignment)
2353                 alignment--;
2354
2355         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2356                 unsigned int tile_size, tile_width, tile_height;
2357                 unsigned int tile_rows, tiles, pitch_tiles;
2358
2359                 tile_size = intel_tile_size(dev_priv);
2360                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2361
2362                 if (drm_rotation_90_or_270(rotation)) {
2363                         pitch_tiles = pitch / tile_height;
2364                         swap(tile_width, tile_height);
2365                 } else {
2366                         pitch_tiles = pitch / (tile_width * cpp);
2367                 }
2368
2369                 tile_rows = *y / tile_height;
2370                 *y %= tile_height;
2371
2372                 tiles = *x / tile_width;
2373                 *x %= tile_width;
2374
2375                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2376                 offset_aligned = offset & ~alignment;
2377
2378                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2379                                           tile_size, pitch_tiles,
2380                                           offset, offset_aligned);
2381         } else {
2382                 offset = *y * pitch + *x * cpp;
2383                 offset_aligned = offset & ~alignment;
2384
2385                 *y = (offset & alignment) / pitch;
2386                 *x = ((offset & alignment) - *y * pitch) / cpp;
2387         }
2388
2389         return offset_aligned;
2390 }
2391
2392 u32 intel_compute_tile_offset(int *x, int *y,
2393                               const struct intel_plane_state *state,
2394                               int plane)
2395 {
2396         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2397         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2398         const struct drm_framebuffer *fb = state->base.fb;
2399         unsigned int rotation = state->base.rotation;
2400         int pitch = intel_fb_pitch(fb, plane, rotation);
2401         u32 alignment;
2402
2403         if (intel_plane->id == PLANE_CURSOR)
2404                 alignment = intel_cursor_alignment(dev_priv);
2405         else
2406                 alignment = intel_surf_alignment(fb, plane);
2407
2408         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2409                                           rotation, alignment);
2410 }
2411
2412 /* Convert the fb->offset[] linear offset into x/y offsets */
2413 static void intel_fb_offset_to_xy(int *x, int *y,
2414                                   const struct drm_framebuffer *fb, int plane)
2415 {
2416         unsigned int cpp = fb->format->cpp[plane];
2417         unsigned int pitch = fb->pitches[plane];
2418         u32 linear_offset = fb->offsets[plane];
2419
2420         *y = linear_offset / pitch;
2421         *x = linear_offset % pitch / cpp;
2422 }
2423
2424 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2425 {
2426         switch (fb_modifier) {
2427         case I915_FORMAT_MOD_X_TILED:
2428                 return I915_TILING_X;
2429         case I915_FORMAT_MOD_Y_TILED:
2430                 return I915_TILING_Y;
2431         default:
2432                 return I915_TILING_NONE;
2433         }
2434 }
2435
2436 static int
2437 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2438                    struct drm_framebuffer *fb)
2439 {
2440         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2441         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2442         u32 gtt_offset_rotated = 0;
2443         unsigned int max_size = 0;
2444         int i, num_planes = fb->format->num_planes;
2445         unsigned int tile_size = intel_tile_size(dev_priv);
2446
2447         for (i = 0; i < num_planes; i++) {
2448                 unsigned int width, height;
2449                 unsigned int cpp, size;
2450                 u32 offset;
2451                 int x, y;
2452
2453                 cpp = fb->format->cpp[i];
2454                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2455                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2456
2457                 intel_fb_offset_to_xy(&x, &y, fb, i);
2458
2459                 /*
2460                  * The fence (if used) is aligned to the start of the object
2461                  * so having the framebuffer wrap around across the edge of the
2462                  * fenced region doesn't really work. We have no API to configure
2463                  * the fence start offset within the object (nor could we probably
2464                  * on gen2/3). So it's just easier if we just require that the
2465                  * fb layout agrees with the fence layout. We already check that the
2466                  * fb stride matches the fence stride elsewhere.
2467                  */
2468                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2469                     (x + width) * cpp > fb->pitches[i]) {
2470                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2471                                       i, fb->offsets[i]);
2472                         return -EINVAL;
2473                 }
2474
2475                 /*
2476                  * First pixel of the framebuffer from
2477                  * the start of the normal gtt mapping.
2478                  */
2479                 intel_fb->normal[i].x = x;
2480                 intel_fb->normal[i].y = y;
2481
2482                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2483                                                     fb, i, fb->pitches[i],
2484                                                     DRM_MODE_ROTATE_0, tile_size);
2485                 offset /= tile_size;
2486
2487                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2488                         unsigned int tile_width, tile_height;
2489                         unsigned int pitch_tiles;
2490                         struct drm_rect r;
2491
2492                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2493
2494                         rot_info->plane[i].offset = offset;
2495                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2496                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2497                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2498
2499                         intel_fb->rotated[i].pitch =
2500                                 rot_info->plane[i].height * tile_height;
2501
2502                         /* how many tiles does this plane need */
2503                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2504                         /*
2505                          * If the plane isn't horizontally tile aligned,
2506                          * we need one more tile.
2507                          */
2508                         if (x != 0)
2509                                 size++;
2510
2511                         /* rotate the x/y offsets to match the GTT view */
2512                         r.x1 = x;
2513                         r.y1 = y;
2514                         r.x2 = x + width;
2515                         r.y2 = y + height;
2516                         drm_rect_rotate(&r,
2517                                         rot_info->plane[i].width * tile_width,
2518                                         rot_info->plane[i].height * tile_height,
2519                                         DRM_MODE_ROTATE_270);
2520                         x = r.x1;
2521                         y = r.y1;
2522
2523                         /* rotate the tile dimensions to match the GTT view */
2524                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2525                         swap(tile_width, tile_height);
2526
2527                         /*
2528                          * We only keep the x/y offsets, so push all of the
2529                          * gtt offset into the x/y offsets.
2530                          */
2531                         _intel_adjust_tile_offset(&x, &y,
2532                                                   tile_width, tile_height,
2533                                                   tile_size, pitch_tiles,
2534                                                   gtt_offset_rotated * tile_size, 0);
2535
2536                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2537
2538                         /*
2539                          * First pixel of the framebuffer from
2540                          * the start of the rotated gtt mapping.
2541                          */
2542                         intel_fb->rotated[i].x = x;
2543                         intel_fb->rotated[i].y = y;
2544                 } else {
2545                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2546                                             x * cpp, tile_size);
2547                 }
2548
2549                 /* how many tiles in total needed in the bo */
2550                 max_size = max(max_size, offset + size);
2551         }
2552
2553         if (max_size * tile_size > intel_fb->obj->base.size) {
2554                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2555                               max_size * tile_size, intel_fb->obj->base.size);
2556                 return -EINVAL;
2557         }
2558
2559         return 0;
2560 }
2561
2562 static int i9xx_format_to_fourcc(int format)
2563 {
2564         switch (format) {
2565         case DISPPLANE_8BPP:
2566                 return DRM_FORMAT_C8;
2567         case DISPPLANE_BGRX555:
2568                 return DRM_FORMAT_XRGB1555;
2569         case DISPPLANE_BGRX565:
2570                 return DRM_FORMAT_RGB565;
2571         default:
2572         case DISPPLANE_BGRX888:
2573                 return DRM_FORMAT_XRGB8888;
2574         case DISPPLANE_RGBX888:
2575                 return DRM_FORMAT_XBGR8888;
2576         case DISPPLANE_BGRX101010:
2577                 return DRM_FORMAT_XRGB2101010;
2578         case DISPPLANE_RGBX101010:
2579                 return DRM_FORMAT_XBGR2101010;
2580         }
2581 }
2582
2583 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2584 {
2585         switch (format) {
2586         case PLANE_CTL_FORMAT_RGB_565:
2587                 return DRM_FORMAT_RGB565;
2588         default:
2589         case PLANE_CTL_FORMAT_XRGB_8888:
2590                 if (rgb_order) {
2591                         if (alpha)
2592                                 return DRM_FORMAT_ABGR8888;
2593                         else
2594                                 return DRM_FORMAT_XBGR8888;
2595                 } else {
2596                         if (alpha)
2597                                 return DRM_FORMAT_ARGB8888;
2598                         else
2599                                 return DRM_FORMAT_XRGB8888;
2600                 }
2601         case PLANE_CTL_FORMAT_XRGB_2101010:
2602                 if (rgb_order)
2603                         return DRM_FORMAT_XBGR2101010;
2604                 else
2605                         return DRM_FORMAT_XRGB2101010;
2606         }
2607 }
2608
2609 static bool
2610 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2611                               struct intel_initial_plane_config *plane_config)
2612 {
2613         struct drm_device *dev = crtc->base.dev;
2614         struct drm_i915_private *dev_priv = to_i915(dev);
2615         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2616         struct drm_i915_gem_object *obj = NULL;
2617         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2618         struct drm_framebuffer *fb = &plane_config->fb->base;
2619         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2620         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2621                                     PAGE_SIZE);
2622
2623         size_aligned -= base_aligned;
2624
2625         if (plane_config->size == 0)
2626                 return false;
2627
2628         /* If the FB is too big, just don't use it since fbdev is not very
2629          * important and we should probably use that space with FBC or other
2630          * features. */
2631         if (size_aligned * 2 > ggtt->stolen_usable_size)
2632                 return false;
2633
2634         mutex_lock(&dev->struct_mutex);
2635         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2636                                                              base_aligned,
2637                                                              base_aligned,
2638                                                              size_aligned);
2639         mutex_unlock(&dev->struct_mutex);
2640         if (!obj)
2641                 return false;
2642
2643         if (plane_config->tiling == I915_TILING_X)
2644                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2645
2646         mode_cmd.pixel_format = fb->format->format;
2647         mode_cmd.width = fb->width;
2648         mode_cmd.height = fb->height;
2649         mode_cmd.pitches[0] = fb->pitches[0];
2650         mode_cmd.modifier[0] = fb->modifier;
2651         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2652
2653         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2654                 DRM_DEBUG_KMS("intel fb init failed\n");
2655                 goto out_unref_obj;
2656         }
2657
2658
2659         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2660         return true;
2661
2662 out_unref_obj:
2663         i915_gem_object_put(obj);
2664         return false;
2665 }
2666
2667 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2668 static void
2669 update_state_fb(struct drm_plane *plane)
2670 {
2671         if (plane->fb == plane->state->fb)
2672                 return;
2673
2674         if (plane->state->fb)
2675                 drm_framebuffer_unreference(plane->state->fb);
2676         plane->state->fb = plane->fb;
2677         if (plane->state->fb)
2678                 drm_framebuffer_reference(plane->state->fb);
2679 }
2680
2681 static void
2682 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2683                         struct intel_plane_state *plane_state,
2684                         bool visible)
2685 {
2686         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2687
2688         plane_state->base.visible = visible;
2689
2690         /* FIXME pre-g4x don't work like this */
2691         if (visible) {
2692                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2693                 crtc_state->active_planes |= BIT(plane->id);
2694         } else {
2695                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2696                 crtc_state->active_planes &= ~BIT(plane->id);
2697         }
2698
2699         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2700                       crtc_state->base.crtc->name,
2701                       crtc_state->active_planes);
2702 }
2703
2704 static void
2705 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2706                              struct intel_initial_plane_config *plane_config)
2707 {
2708         struct drm_device *dev = intel_crtc->base.dev;
2709         struct drm_i915_private *dev_priv = to_i915(dev);
2710         struct drm_crtc *c;
2711         struct drm_i915_gem_object *obj;
2712         struct drm_plane *primary = intel_crtc->base.primary;
2713         struct drm_plane_state *plane_state = primary->state;
2714         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2715         struct intel_plane *intel_plane = to_intel_plane(primary);
2716         struct intel_plane_state *intel_state =
2717                 to_intel_plane_state(plane_state);
2718         struct drm_framebuffer *fb;
2719
2720         if (!plane_config->fb)
2721                 return;
2722
2723         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2724                 fb = &plane_config->fb->base;
2725                 goto valid_fb;
2726         }
2727
2728         kfree(plane_config->fb);
2729
2730         /*
2731          * Failed to alloc the obj, check to see if we should share
2732          * an fb with another CRTC instead
2733          */
2734         for_each_crtc(dev, c) {
2735                 struct intel_plane_state *state;
2736
2737                 if (c == &intel_crtc->base)
2738                         continue;
2739
2740                 if (!to_intel_crtc(c)->active)
2741                         continue;
2742
2743                 state = to_intel_plane_state(c->primary->state);
2744                 if (!state->vma)
2745                         continue;
2746
2747                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2748                         fb = c->primary->fb;
2749                         drm_framebuffer_reference(fb);
2750                         goto valid_fb;
2751                 }
2752         }
2753
2754         /*
2755          * We've failed to reconstruct the BIOS FB.  Current display state
2756          * indicates that the primary plane is visible, but has a NULL FB,
2757          * which will lead to problems later if we don't fix it up.  The
2758          * simplest solution is to just disable the primary plane now and
2759          * pretend the BIOS never had it enabled.
2760          */
2761         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2762                                 to_intel_plane_state(plane_state),
2763                                 false);
2764         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2765         trace_intel_disable_plane(primary, intel_crtc);
2766         intel_plane->disable_plane(intel_plane, intel_crtc);
2767
2768         return;
2769
2770 valid_fb:
2771         mutex_lock(&dev->struct_mutex);
2772         intel_state->vma =
2773                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2774         mutex_unlock(&dev->struct_mutex);
2775         if (IS_ERR(intel_state->vma)) {
2776                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2777                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2778
2779                 intel_state->vma = NULL;
2780                 drm_framebuffer_unreference(fb);
2781                 return;
2782         }
2783
2784         plane_state->src_x = 0;
2785         plane_state->src_y = 0;
2786         plane_state->src_w = fb->width << 16;
2787         plane_state->src_h = fb->height << 16;
2788
2789         plane_state->crtc_x = 0;
2790         plane_state->crtc_y = 0;
2791         plane_state->crtc_w = fb->width;
2792         plane_state->crtc_h = fb->height;
2793
2794         intel_state->base.src = drm_plane_state_src(plane_state);
2795         intel_state->base.dst = drm_plane_state_dest(plane_state);
2796
2797         obj = intel_fb_obj(fb);
2798         if (i915_gem_object_is_tiled(obj))
2799                 dev_priv->preserve_bios_swizzle = true;
2800
2801         drm_framebuffer_reference(fb);
2802         primary->fb = primary->state->fb = fb;
2803         primary->crtc = primary->state->crtc = &intel_crtc->base;
2804
2805         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2806                                 to_intel_plane_state(plane_state),
2807                                 true);
2808
2809         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2810                   &obj->frontbuffer_bits);
2811 }
2812
2813 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2814                                unsigned int rotation)
2815 {
2816         int cpp = fb->format->cpp[plane];
2817
2818         switch (fb->modifier) {
2819         case DRM_FORMAT_MOD_LINEAR:
2820         case I915_FORMAT_MOD_X_TILED:
2821                 switch (cpp) {
2822                 case 8:
2823                         return 4096;
2824                 case 4:
2825                 case 2:
2826                 case 1:
2827                         return 8192;
2828                 default:
2829                         MISSING_CASE(cpp);
2830                         break;
2831                 }
2832                 break;
2833         case I915_FORMAT_MOD_Y_TILED:
2834         case I915_FORMAT_MOD_Yf_TILED:
2835                 switch (cpp) {
2836                 case 8:
2837                         return 2048;
2838                 case 4:
2839                         return 4096;
2840                 case 2:
2841                 case 1:
2842                         return 8192;
2843                 default:
2844                         MISSING_CASE(cpp);
2845                         break;
2846                 }
2847                 break;
2848         default:
2849                 MISSING_CASE(fb->modifier);
2850         }
2851
2852         return 2048;
2853 }
2854
2855 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2856 {
2857         const struct drm_framebuffer *fb = plane_state->base.fb;
2858         unsigned int rotation = plane_state->base.rotation;
2859         int x = plane_state->base.src.x1 >> 16;
2860         int y = plane_state->base.src.y1 >> 16;
2861         int w = drm_rect_width(&plane_state->base.src) >> 16;
2862         int h = drm_rect_height(&plane_state->base.src) >> 16;
2863         int max_width = skl_max_plane_width(fb, 0, rotation);
2864         int max_height = 4096;
2865         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2866
2867         if (w > max_width || h > max_height) {
2868                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2869                               w, h, max_width, max_height);
2870                 return -EINVAL;
2871         }
2872
2873         intel_add_fb_offsets(&x, &y, plane_state, 0);
2874         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2875         alignment = intel_surf_alignment(fb, 0);
2876
2877         /*
2878          * AUX surface offset is specified as the distance from the
2879          * main surface offset, and it must be non-negative. Make
2880          * sure that is what we will get.
2881          */
2882         if (offset > aux_offset)
2883                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2884                                                   offset, aux_offset & ~(alignment - 1));
2885
2886         /*
2887          * When using an X-tiled surface, the plane blows up
2888          * if the x offset + width exceed the stride.
2889          *
2890          * TODO: linear and Y-tiled seem fine, Yf untested,
2891          */
2892         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2893                 int cpp = fb->format->cpp[0];
2894
2895                 while ((x + w) * cpp > fb->pitches[0]) {
2896                         if (offset == 0) {
2897                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2898                                 return -EINVAL;
2899                         }
2900
2901                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2902                                                           offset, offset - alignment);
2903                 }
2904         }
2905
2906         plane_state->main.offset = offset;
2907         plane_state->main.x = x;
2908         plane_state->main.y = y;
2909
2910         return 0;
2911 }
2912
2913 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2914 {
2915         const struct drm_framebuffer *fb = plane_state->base.fb;
2916         unsigned int rotation = plane_state->base.rotation;
2917         int max_width = skl_max_plane_width(fb, 1, rotation);
2918         int max_height = 4096;
2919         int x = plane_state->base.src.x1 >> 17;
2920         int y = plane_state->base.src.y1 >> 17;
2921         int w = drm_rect_width(&plane_state->base.src) >> 17;
2922         int h = drm_rect_height(&plane_state->base.src) >> 17;
2923         u32 offset;
2924
2925         intel_add_fb_offsets(&x, &y, plane_state, 1);
2926         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2927
2928         /* FIXME not quite sure how/if these apply to the chroma plane */
2929         if (w > max_width || h > max_height) {
2930                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2931                               w, h, max_width, max_height);
2932                 return -EINVAL;
2933         }
2934
2935         plane_state->aux.offset = offset;
2936         plane_state->aux.x = x;
2937         plane_state->aux.y = y;
2938
2939         return 0;
2940 }
2941
2942 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2943 {
2944         const struct drm_framebuffer *fb = plane_state->base.fb;
2945         unsigned int rotation = plane_state->base.rotation;
2946         int ret;
2947
2948         if (!plane_state->base.visible)
2949                 return 0;
2950
2951         /* Rotate src coordinates to match rotated GTT view */
2952         if (drm_rotation_90_or_270(rotation))
2953                 drm_rect_rotate(&plane_state->base.src,
2954                                 fb->width << 16, fb->height << 16,
2955                                 DRM_MODE_ROTATE_270);
2956
2957         /*
2958          * Handle the AUX surface first since
2959          * the main surface setup depends on it.
2960          */
2961         if (fb->format->format == DRM_FORMAT_NV12) {
2962                 ret = skl_check_nv12_aux_surface(plane_state);
2963                 if (ret)
2964                         return ret;
2965         } else {
2966                 plane_state->aux.offset = ~0xfff;
2967                 plane_state->aux.x = 0;
2968                 plane_state->aux.y = 0;
2969         }
2970
2971         ret = skl_check_main_surface(plane_state);
2972         if (ret)
2973                 return ret;
2974
2975         return 0;
2976 }
2977
2978 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2979                           const struct intel_plane_state *plane_state)
2980 {
2981         struct drm_i915_private *dev_priv =
2982                 to_i915(plane_state->base.plane->dev);
2983         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2984         const struct drm_framebuffer *fb = plane_state->base.fb;
2985         unsigned int rotation = plane_state->base.rotation;
2986         u32 dspcntr;
2987
2988         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2989
2990         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2991             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2992                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2993
2994         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2995                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2996
2997         if (INTEL_GEN(dev_priv) < 4)
2998                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
2999
3000         switch (fb->format->format) {
3001         case DRM_FORMAT_C8:
3002                 dspcntr |= DISPPLANE_8BPP;
3003                 break;
3004         case DRM_FORMAT_XRGB1555:
3005                 dspcntr |= DISPPLANE_BGRX555;
3006                 break;
3007         case DRM_FORMAT_RGB565:
3008                 dspcntr |= DISPPLANE_BGRX565;
3009                 break;
3010         case DRM_FORMAT_XRGB8888:
3011                 dspcntr |= DISPPLANE_BGRX888;
3012                 break;
3013         case DRM_FORMAT_XBGR8888:
3014                 dspcntr |= DISPPLANE_RGBX888;
3015                 break;
3016         case DRM_FORMAT_XRGB2101010:
3017                 dspcntr |= DISPPLANE_BGRX101010;
3018                 break;
3019         case DRM_FORMAT_XBGR2101010:
3020                 dspcntr |= DISPPLANE_RGBX101010;
3021                 break;
3022         default:
3023                 MISSING_CASE(fb->format->format);
3024                 return 0;
3025         }
3026
3027         if (INTEL_GEN(dev_priv) >= 4 &&
3028             fb->modifier == I915_FORMAT_MOD_X_TILED)
3029                 dspcntr |= DISPPLANE_TILED;
3030
3031         if (rotation & DRM_MODE_ROTATE_180)
3032                 dspcntr |= DISPPLANE_ROTATE_180;
3033
3034         if (rotation & DRM_MODE_REFLECT_X)
3035                 dspcntr |= DISPPLANE_MIRROR;
3036
3037         return dspcntr;
3038 }
3039
3040 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3041 {
3042         struct drm_i915_private *dev_priv =
3043                 to_i915(plane_state->base.plane->dev);
3044         int src_x = plane_state->base.src.x1 >> 16;
3045         int src_y = plane_state->base.src.y1 >> 16;
3046         u32 offset;
3047
3048         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3049
3050         if (INTEL_GEN(dev_priv) >= 4)
3051                 offset = intel_compute_tile_offset(&src_x, &src_y,
3052                                                    plane_state, 0);
3053         else
3054                 offset = 0;
3055
3056         /* HSW/BDW do this automagically in hardware */
3057         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3058                 unsigned int rotation = plane_state->base.rotation;
3059                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3060                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3061
3062                 if (rotation & DRM_MODE_ROTATE_180) {
3063                         src_x += src_w - 1;
3064                         src_y += src_h - 1;
3065                 } else if (rotation & DRM_MODE_REFLECT_X) {
3066                         src_x += src_w - 1;
3067                 }
3068         }
3069
3070         plane_state->main.offset = offset;
3071         plane_state->main.x = src_x;
3072         plane_state->main.y = src_y;
3073
3074         return 0;
3075 }
3076
3077 static void i9xx_update_primary_plane(struct intel_plane *primary,
3078                                       const struct intel_crtc_state *crtc_state,
3079                                       const struct intel_plane_state *plane_state)
3080 {
3081         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3082         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3083         const struct drm_framebuffer *fb = plane_state->base.fb;
3084         enum plane plane = primary->plane;
3085         u32 linear_offset;
3086         u32 dspcntr = plane_state->ctl;
3087         i915_reg_t reg = DSPCNTR(plane);
3088         int x = plane_state->main.x;
3089         int y = plane_state->main.y;
3090         unsigned long irqflags;
3091
3092         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3093
3094         if (INTEL_GEN(dev_priv) >= 4)
3095                 crtc->dspaddr_offset = plane_state->main.offset;
3096         else
3097                 crtc->dspaddr_offset = linear_offset;
3098
3099         crtc->adjusted_x = x;
3100         crtc->adjusted_y = y;
3101
3102         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3103
3104         if (INTEL_GEN(dev_priv) < 4) {
3105                 /* pipesrc and dspsize control the size that is scaled from,
3106                  * which should always be the user's requested size.
3107                  */
3108                 I915_WRITE_FW(DSPSIZE(plane),
3109                               ((crtc_state->pipe_src_h - 1) << 16) |
3110                               (crtc_state->pipe_src_w - 1));
3111                 I915_WRITE_FW(DSPPOS(plane), 0);
3112         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3113                 I915_WRITE_FW(PRIMSIZE(plane),
3114                               ((crtc_state->pipe_src_h - 1) << 16) |
3115                               (crtc_state->pipe_src_w - 1));
3116                 I915_WRITE_FW(PRIMPOS(plane), 0);
3117                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3118         }
3119
3120         I915_WRITE_FW(reg, dspcntr);
3121
3122         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3123         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3124                 I915_WRITE_FW(DSPSURF(plane),
3125                               intel_plane_ggtt_offset(plane_state) +
3126                               crtc->dspaddr_offset);
3127                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3128         } else if (INTEL_GEN(dev_priv) >= 4) {
3129                 I915_WRITE_FW(DSPSURF(plane),
3130                               intel_plane_ggtt_offset(plane_state) +
3131                               crtc->dspaddr_offset);
3132                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3133                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3134         } else {
3135                 I915_WRITE_FW(DSPADDR(plane),
3136                               intel_plane_ggtt_offset(plane_state) +
3137                               crtc->dspaddr_offset);
3138         }
3139         POSTING_READ_FW(reg);
3140
3141         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3142 }
3143
3144 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3145                                        struct intel_crtc *crtc)
3146 {
3147         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3148         enum plane plane = primary->plane;
3149         unsigned long irqflags;
3150
3151         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3152
3153         I915_WRITE_FW(DSPCNTR(plane), 0);
3154         if (INTEL_INFO(dev_priv)->gen >= 4)
3155                 I915_WRITE_FW(DSPSURF(plane), 0);
3156         else
3157                 I915_WRITE_FW(DSPADDR(plane), 0);
3158         POSTING_READ_FW(DSPCNTR(plane));
3159
3160         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3161 }
3162
3163 static u32
3164 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3165 {
3166         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3167                 return 64;
3168         else
3169                 return intel_tile_width_bytes(fb, plane);
3170 }
3171
3172 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3173 {
3174         struct drm_device *dev = intel_crtc->base.dev;
3175         struct drm_i915_private *dev_priv = to_i915(dev);
3176
3177         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3178         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3179         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3180 }
3181
3182 /*
3183  * This function detaches (aka. unbinds) unused scalers in hardware
3184  */
3185 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3186 {
3187         struct intel_crtc_scaler_state *scaler_state;
3188         int i;
3189
3190         scaler_state = &intel_crtc->config->scaler_state;
3191
3192         /* loop through and disable scalers that aren't in use */
3193         for (i = 0; i < intel_crtc->num_scalers; i++) {
3194                 if (!scaler_state->scalers[i].in_use)
3195                         skl_detach_scaler(intel_crtc, i);
3196         }
3197 }
3198
3199 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3200                      unsigned int rotation)
3201 {
3202         u32 stride;
3203
3204         if (plane >= fb->format->num_planes)
3205                 return 0;
3206
3207         stride = intel_fb_pitch(fb, plane, rotation);
3208
3209         /*
3210          * The stride is either expressed as a multiple of 64 bytes chunks for
3211          * linear buffers or in number of tiles for tiled buffers.
3212          */
3213         if (drm_rotation_90_or_270(rotation))
3214                 stride /= intel_tile_height(fb, plane);
3215         else
3216                 stride /= intel_fb_stride_alignment(fb, plane);
3217
3218         return stride;
3219 }
3220
3221 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3222 {
3223         switch (pixel_format) {
3224         case DRM_FORMAT_C8:
3225                 return PLANE_CTL_FORMAT_INDEXED;
3226         case DRM_FORMAT_RGB565:
3227                 return PLANE_CTL_FORMAT_RGB_565;
3228         case DRM_FORMAT_XBGR8888:
3229                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3230         case DRM_FORMAT_XRGB8888:
3231                 return PLANE_CTL_FORMAT_XRGB_8888;
3232         /*
3233          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3234          * to be already pre-multiplied. We need to add a knob (or a different
3235          * DRM_FORMAT) for user-space to configure that.
3236          */
3237         case DRM_FORMAT_ABGR8888:
3238                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3239                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3240         case DRM_FORMAT_ARGB8888:
3241                 return PLANE_CTL_FORMAT_XRGB_8888 |
3242                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3243         case DRM_FORMAT_XRGB2101010:
3244                 return PLANE_CTL_FORMAT_XRGB_2101010;
3245         case DRM_FORMAT_XBGR2101010:
3246                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3247         case DRM_FORMAT_YUYV:
3248                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3249         case DRM_FORMAT_YVYU:
3250                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3251         case DRM_FORMAT_UYVY:
3252                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3253         case DRM_FORMAT_VYUY:
3254                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3255         default:
3256                 MISSING_CASE(pixel_format);
3257         }
3258
3259         return 0;
3260 }
3261
3262 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3263 {
3264         switch (fb_modifier) {
3265         case DRM_FORMAT_MOD_LINEAR:
3266                 break;
3267         case I915_FORMAT_MOD_X_TILED:
3268                 return PLANE_CTL_TILED_X;
3269         case I915_FORMAT_MOD_Y_TILED:
3270                 return PLANE_CTL_TILED_Y;
3271         case I915_FORMAT_MOD_Yf_TILED:
3272                 return PLANE_CTL_TILED_YF;
3273         default:
3274                 MISSING_CASE(fb_modifier);
3275         }
3276
3277         return 0;
3278 }
3279
3280 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3281 {
3282         switch (rotation) {
3283         case DRM_MODE_ROTATE_0:
3284                 break;
3285         /*
3286          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3287          * while i915 HW rotation is clockwise, thats why this swapping.
3288          */
3289         case DRM_MODE_ROTATE_90:
3290                 return PLANE_CTL_ROTATE_270;
3291         case DRM_MODE_ROTATE_180:
3292                 return PLANE_CTL_ROTATE_180;
3293         case DRM_MODE_ROTATE_270:
3294                 return PLANE_CTL_ROTATE_90;
3295         default:
3296                 MISSING_CASE(rotation);
3297         }
3298
3299         return 0;
3300 }
3301
3302 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3303                   const struct intel_plane_state *plane_state)
3304 {
3305         struct drm_i915_private *dev_priv =
3306                 to_i915(plane_state->base.plane->dev);
3307         const struct drm_framebuffer *fb = plane_state->base.fb;
3308         unsigned int rotation = plane_state->base.rotation;
3309         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3310         u32 plane_ctl;
3311
3312         plane_ctl = PLANE_CTL_ENABLE;
3313
3314         if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3315                 plane_ctl |=
3316                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3317                         PLANE_CTL_PIPE_CSC_ENABLE |
3318                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3319         }
3320
3321         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3322         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3323         plane_ctl |= skl_plane_ctl_rotation(rotation);
3324
3325         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3326                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3327         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3328                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3329
3330         return plane_ctl;
3331 }
3332
3333 static void skylake_update_primary_plane(struct intel_plane *plane,
3334                                          const struct intel_crtc_state *crtc_state,
3335                                          const struct intel_plane_state *plane_state)
3336 {
3337         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3338         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3339         const struct drm_framebuffer *fb = plane_state->base.fb;
3340         enum plane_id plane_id = plane->id;
3341         enum pipe pipe = plane->pipe;
3342         u32 plane_ctl = plane_state->ctl;
3343         unsigned int rotation = plane_state->base.rotation;
3344         u32 stride = skl_plane_stride(fb, 0, rotation);
3345         u32 surf_addr = plane_state->main.offset;
3346         int scaler_id = plane_state->scaler_id;
3347         int src_x = plane_state->main.x;
3348         int src_y = plane_state->main.y;
3349         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3350         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3351         int dst_x = plane_state->base.dst.x1;
3352         int dst_y = plane_state->base.dst.y1;
3353         int dst_w = drm_rect_width(&plane_state->base.dst);
3354         int dst_h = drm_rect_height(&plane_state->base.dst);
3355         unsigned long irqflags;
3356
3357         /* Sizes are 0 based */
3358         src_w--;
3359         src_h--;
3360         dst_w--;
3361         dst_h--;
3362
3363         crtc->dspaddr_offset = surf_addr;
3364
3365         crtc->adjusted_x = src_x;
3366         crtc->adjusted_y = src_y;
3367
3368         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3369
3370         if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3371                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3372                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
3373                               PLANE_COLOR_PIPE_CSC_ENABLE |
3374                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
3375         }
3376
3377         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3378         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3379         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3380         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3381
3382         if (scaler_id >= 0) {
3383                 uint32_t ps_ctrl = 0;
3384
3385                 WARN_ON(!dst_w || !dst_h);
3386                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3387                         crtc_state->scaler_state.scalers[scaler_id].mode;
3388                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3389                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3390                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3391                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3392                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3393         } else {
3394                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3395         }
3396
3397         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3398                       intel_plane_ggtt_offset(plane_state) + surf_addr);
3399
3400         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3401
3402         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3403 }
3404
3405 static void skylake_disable_primary_plane(struct intel_plane *primary,
3406                                           struct intel_crtc *crtc)
3407 {
3408         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3409         enum plane_id plane_id = primary->id;
3410         enum pipe pipe = primary->pipe;
3411         unsigned long irqflags;
3412
3413         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3414
3415         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3416         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3417         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3418
3419         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3420 }
3421
3422 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3423 {
3424         struct intel_crtc *crtc;
3425
3426         for_each_intel_crtc(&dev_priv->drm, crtc)
3427                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3428 }
3429
3430 static void intel_update_primary_planes(struct drm_device *dev)
3431 {
3432         struct drm_crtc *crtc;
3433
3434         for_each_crtc(dev, crtc) {
3435                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3436                 struct intel_plane_state *plane_state =
3437                         to_intel_plane_state(plane->base.state);
3438
3439                 if (plane_state->base.visible) {
3440                         trace_intel_update_plane(&plane->base,
3441                                                  to_intel_crtc(crtc));
3442
3443                         plane->update_plane(plane,
3444                                             to_intel_crtc_state(crtc->state),
3445                                             plane_state);
3446                 }
3447         }
3448 }
3449
3450 static int
3451 __intel_display_resume(struct drm_device *dev,
3452                        struct drm_atomic_state *state,
3453                        struct drm_modeset_acquire_ctx *ctx)
3454 {
3455         struct drm_crtc_state *crtc_state;
3456         struct drm_crtc *crtc;
3457         int i, ret;
3458
3459         intel_modeset_setup_hw_state(dev, ctx);
3460         i915_redisable_vga(to_i915(dev));
3461
3462         if (!state)
3463                 return 0;
3464
3465         /*
3466          * We've duplicated the state, pointers to the old state are invalid.
3467          *
3468          * Don't attempt to use the old state until we commit the duplicated state.
3469          */
3470         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3471                 /*
3472                  * Force recalculation even if we restore
3473                  * current state. With fast modeset this may not result
3474                  * in a modeset when the state is compatible.
3475                  */
3476                 crtc_state->mode_changed = true;
3477         }
3478
3479         /* ignore any reset values/BIOS leftovers in the WM registers */
3480         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3481                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3482
3483         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3484
3485         WARN_ON(ret == -EDEADLK);
3486         return ret;
3487 }
3488
3489 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3490 {
3491         return intel_has_gpu_reset(dev_priv) &&
3492                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3493 }
3494
3495 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3496 {
3497         struct drm_device *dev = &dev_priv->drm;
3498         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3499         struct drm_atomic_state *state;
3500         int ret;
3501
3502         /*
3503          * Need mode_config.mutex so that we don't
3504          * trample ongoing ->detect() and whatnot.
3505          */
3506         mutex_lock(&dev->mode_config.mutex);
3507         drm_modeset_acquire_init(ctx, 0);
3508         while (1) {
3509                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3510                 if (ret != -EDEADLK)
3511                         break;
3512
3513                 drm_modeset_backoff(ctx);
3514         }
3515
3516         /* reset doesn't touch the display, but flips might get nuked anyway, */
3517         if (!i915.force_reset_modeset_test &&
3518             !gpu_reset_clobbers_display(dev_priv))
3519                 return;
3520
3521         /*
3522          * Disabling the crtcs gracefully seems nicer. Also the
3523          * g33 docs say we should at least disable all the planes.
3524          */
3525         state = drm_atomic_helper_duplicate_state(dev, ctx);
3526         if (IS_ERR(state)) {
3527                 ret = PTR_ERR(state);
3528                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3529                 return;
3530         }
3531
3532         ret = drm_atomic_helper_disable_all(dev, ctx);
3533         if (ret) {
3534                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3535                 drm_atomic_state_put(state);
3536                 return;
3537         }
3538
3539         dev_priv->modeset_restore_state = state;
3540         state->acquire_ctx = ctx;
3541 }
3542
3543 void intel_finish_reset(struct drm_i915_private *dev_priv)
3544 {
3545         struct drm_device *dev = &dev_priv->drm;
3546         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3547         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3548         int ret;
3549
3550         /*
3551          * Flips in the rings will be nuked by the reset,
3552          * so complete all pending flips so that user space
3553          * will get its events and not get stuck.
3554          */
3555         intel_complete_page_flips(dev_priv);
3556
3557         dev_priv->modeset_restore_state = NULL;
3558
3559         /* reset doesn't touch the display */
3560         if (!gpu_reset_clobbers_display(dev_priv)) {
3561                 if (!state) {
3562                         /*
3563                          * Flips in the rings have been nuked by the reset,
3564                          * so update the base address of all primary
3565                          * planes to the the last fb to make sure we're
3566                          * showing the correct fb after a reset.
3567                          *
3568                          * FIXME: Atomic will make this obsolete since we won't schedule
3569                          * CS-based flips (which might get lost in gpu resets) any more.
3570                          */
3571                         intel_update_primary_planes(dev);
3572                 } else {
3573                         ret = __intel_display_resume(dev, state, ctx);
3574                         if (ret)
3575                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3576                 }
3577         } else {
3578                 /*
3579                  * The display has been reset as well,
3580                  * so need a full re-initialization.
3581                  */
3582                 intel_runtime_pm_disable_interrupts(dev_priv);
3583                 intel_runtime_pm_enable_interrupts(dev_priv);
3584
3585                 intel_pps_unlock_regs_wa(dev_priv);
3586                 intel_modeset_init_hw(dev);
3587
3588                 spin_lock_irq(&dev_priv->irq_lock);
3589                 if (dev_priv->display.hpd_irq_setup)
3590                         dev_priv->display.hpd_irq_setup(dev_priv);
3591                 spin_unlock_irq(&dev_priv->irq_lock);
3592
3593                 ret = __intel_display_resume(dev, state, ctx);
3594                 if (ret)
3595                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3596
3597                 intel_hpd_init(dev_priv);
3598         }
3599
3600         if (state)
3601                 drm_atomic_state_put(state);
3602         drm_modeset_drop_locks(ctx);
3603         drm_modeset_acquire_fini(ctx);
3604         mutex_unlock(&dev->mode_config.mutex);
3605 }
3606
3607 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3608 {
3609         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3610
3611         if (i915_reset_backoff(error))
3612                 return true;
3613
3614         if (crtc->reset_count != i915_reset_count(error))
3615                 return true;
3616
3617         return false;
3618 }
3619
3620 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3621 {
3622         struct drm_device *dev = crtc->dev;
3623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624         bool pending;
3625
3626         if (abort_flip_on_reset(intel_crtc))
3627                 return false;
3628
3629         spin_lock_irq(&dev->event_lock);
3630         pending = to_intel_crtc(crtc)->flip_work != NULL;
3631         spin_unlock_irq(&dev->event_lock);
3632
3633         return pending;
3634 }
3635
3636 static void intel_update_pipe_config(struct intel_crtc *crtc,
3637                                      struct intel_crtc_state *old_crtc_state)
3638 {
3639         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3640         struct intel_crtc_state *pipe_config =
3641                 to_intel_crtc_state(crtc->base.state);
3642
3643         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3644         crtc->base.mode = crtc->base.state->mode;
3645
3646         /*
3647          * Update pipe size and adjust fitter if needed: the reason for this is
3648          * that in compute_mode_changes we check the native mode (not the pfit
3649          * mode) to see if we can flip rather than do a full mode set. In the
3650          * fastboot case, we'll flip, but if we don't update the pipesrc and
3651          * pfit state, we'll end up with a big fb scanned out into the wrong
3652          * sized surface.
3653          */
3654
3655         I915_WRITE(PIPESRC(crtc->pipe),
3656                    ((pipe_config->pipe_src_w - 1) << 16) |
3657                    (pipe_config->pipe_src_h - 1));
3658
3659         /* on skylake this is done by detaching scalers */
3660         if (INTEL_GEN(dev_priv) >= 9) {
3661                 skl_detach_scalers(crtc);
3662
3663                 if (pipe_config->pch_pfit.enabled)
3664                         skylake_pfit_enable(crtc);
3665         } else if (HAS_PCH_SPLIT(dev_priv)) {
3666                 if (pipe_config->pch_pfit.enabled)
3667                         ironlake_pfit_enable(crtc);
3668                 else if (old_crtc_state->pch_pfit.enabled)
3669                         ironlake_pfit_disable(crtc, true);
3670         }
3671 }
3672
3673 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3674 {
3675         struct drm_device *dev = crtc->base.dev;
3676         struct drm_i915_private *dev_priv = to_i915(dev);
3677         int pipe = crtc->pipe;
3678         i915_reg_t reg;
3679         u32 temp;
3680
3681         /* enable normal train */
3682         reg = FDI_TX_CTL(pipe);
3683         temp = I915_READ(reg);
3684         if (IS_IVYBRIDGE(dev_priv)) {
3685                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3686                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3687         } else {
3688                 temp &= ~FDI_LINK_TRAIN_NONE;
3689                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3690         }
3691         I915_WRITE(reg, temp);
3692
3693         reg = FDI_RX_CTL(pipe);
3694         temp = I915_READ(reg);
3695         if (HAS_PCH_CPT(dev_priv)) {
3696                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3697                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3698         } else {
3699                 temp &= ~FDI_LINK_TRAIN_NONE;
3700                 temp |= FDI_LINK_TRAIN_NONE;
3701         }
3702         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3703
3704         /* wait one idle pattern time */
3705         POSTING_READ(reg);
3706         udelay(1000);
3707
3708         /* IVB wants error correction enabled */
3709         if (IS_IVYBRIDGE(dev_priv))
3710                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3711                            FDI_FE_ERRC_ENABLE);
3712 }
3713
3714 /* The FDI link training functions for ILK/Ibexpeak. */
3715 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3716                                     const struct intel_crtc_state *crtc_state)
3717 {
3718         struct drm_device *dev = crtc->base.dev;
3719         struct drm_i915_private *dev_priv = to_i915(dev);
3720         int pipe = crtc->pipe;
3721         i915_reg_t reg;
3722         u32 temp, tries;
3723
3724         /* FDI needs bits from pipe first */
3725         assert_pipe_enabled(dev_priv, pipe);
3726
3727         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3728            for train result */
3729         reg = FDI_RX_IMR(pipe);
3730         temp = I915_READ(reg);
3731         temp &= ~FDI_RX_SYMBOL_LOCK;
3732         temp &= ~FDI_RX_BIT_LOCK;
3733         I915_WRITE(reg, temp);
3734         I915_READ(reg);
3735         udelay(150);
3736
3737         /* enable CPU FDI TX and PCH FDI RX */
3738         reg = FDI_TX_CTL(pipe);
3739         temp = I915_READ(reg);
3740         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3741         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3742         temp &= ~FDI_LINK_TRAIN_NONE;
3743         temp |= FDI_LINK_TRAIN_PATTERN_1;
3744         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3745
3746         reg = FDI_RX_CTL(pipe);
3747         temp = I915_READ(reg);
3748         temp &= ~FDI_LINK_TRAIN_NONE;
3749         temp |= FDI_LINK_TRAIN_PATTERN_1;
3750         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3751
3752         POSTING_READ(reg);
3753         udelay(150);
3754
3755         /* Ironlake workaround, enable clock pointer after FDI enable*/
3756         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3757         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3758                    FDI_RX_PHASE_SYNC_POINTER_EN);
3759
3760         reg = FDI_RX_IIR(pipe);
3761         for (tries = 0; tries < 5; tries++) {
3762                 temp = I915_READ(reg);
3763                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3764
3765                 if ((temp & FDI_RX_BIT_LOCK)) {
3766                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3767                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3768                         break;
3769                 }
3770         }
3771         if (tries == 5)
3772                 DRM_ERROR("FDI train 1 fail!\n");
3773
3774         /* Train 2 */
3775         reg = FDI_TX_CTL(pipe);
3776         temp = I915_READ(reg);
3777         temp &= ~FDI_LINK_TRAIN_NONE;
3778         temp |= FDI_LINK_TRAIN_PATTERN_2;
3779         I915_WRITE(reg, temp);
3780
3781         reg = FDI_RX_CTL(pipe);
3782         temp = I915_READ(reg);
3783         temp &= ~FDI_LINK_TRAIN_NONE;
3784         temp |= FDI_LINK_TRAIN_PATTERN_2;
3785         I915_WRITE(reg, temp);
3786
3787         POSTING_READ(reg);
3788         udelay(150);
3789
3790         reg = FDI_RX_IIR(pipe);
3791         for (tries = 0; tries < 5; tries++) {
3792                 temp = I915_READ(reg);
3793                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3794
3795                 if (temp & FDI_RX_SYMBOL_LOCK) {
3796                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3797                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3798                         break;
3799                 }
3800         }
3801         if (tries == 5)
3802                 DRM_ERROR("FDI train 2 fail!\n");
3803
3804         DRM_DEBUG_KMS("FDI train done\n");
3805
3806 }
3807
3808 static const int snb_b_fdi_train_param[] = {
3809         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3810         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3811         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3812         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3813 };
3814
3815 /* The FDI link training functions for SNB/Cougarpoint. */
3816 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3817                                 const struct intel_crtc_state *crtc_state)
3818 {
3819         struct drm_device *dev = crtc->base.dev;
3820         struct drm_i915_private *dev_priv = to_i915(dev);
3821         int pipe = crtc->pipe;
3822         i915_reg_t reg;
3823         u32 temp, i, retry;
3824
3825         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3826            for train result */
3827         reg = FDI_RX_IMR(pipe);
3828         temp = I915_READ(reg);
3829         temp &= ~FDI_RX_SYMBOL_LOCK;
3830         temp &= ~FDI_RX_BIT_LOCK;
3831         I915_WRITE(reg, temp);
3832
3833         POSTING_READ(reg);
3834         udelay(150);
3835
3836         /* enable CPU FDI TX and PCH FDI RX */
3837         reg = FDI_TX_CTL(pipe);
3838         temp = I915_READ(reg);
3839         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3840         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3841         temp &= ~FDI_LINK_TRAIN_NONE;
3842         temp |= FDI_LINK_TRAIN_PATTERN_1;
3843         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3844         /* SNB-B */
3845         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3846         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3847
3848         I915_WRITE(FDI_RX_MISC(pipe),
3849                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3850
3851         reg = FDI_RX_CTL(pipe);
3852         temp = I915_READ(reg);
3853         if (HAS_PCH_CPT(dev_priv)) {
3854                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3855                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3856         } else {
3857                 temp &= ~FDI_LINK_TRAIN_NONE;
3858                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3859         }
3860         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3861
3862         POSTING_READ(reg);
3863         udelay(150);
3864
3865         for (i = 0; i < 4; i++) {
3866                 reg = FDI_TX_CTL(pipe);
3867                 temp = I915_READ(reg);
3868                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3869                 temp |= snb_b_fdi_train_param[i];
3870                 I915_WRITE(reg, temp);
3871
3872                 POSTING_READ(reg);
3873                 udelay(500);
3874
3875                 for (retry = 0; retry < 5; retry++) {
3876                         reg = FDI_RX_IIR(pipe);
3877                         temp = I915_READ(reg);
3878                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3879                         if (temp & FDI_RX_BIT_LOCK) {
3880                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3881                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3882                                 break;
3883                         }
3884                         udelay(50);
3885                 }
3886                 if (retry < 5)
3887                         break;
3888         }
3889         if (i == 4)
3890                 DRM_ERROR("FDI train 1 fail!\n");
3891
3892         /* Train 2 */
3893         reg = FDI_TX_CTL(pipe);
3894         temp = I915_READ(reg);
3895         temp &= ~FDI_LINK_TRAIN_NONE;
3896         temp |= FDI_LINK_TRAIN_PATTERN_2;
3897         if (IS_GEN6(dev_priv)) {
3898                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3899                 /* SNB-B */
3900                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3901         }
3902         I915_WRITE(reg, temp);
3903
3904         reg = FDI_RX_CTL(pipe);
3905         temp = I915_READ(reg);
3906         if (HAS_PCH_CPT(dev_priv)) {
3907                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3908                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3909         } else {
3910                 temp &= ~FDI_LINK_TRAIN_NONE;
3911                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3912         }
3913         I915_WRITE(reg, temp);
3914
3915         POSTING_READ(reg);
3916         udelay(150);
3917
3918         for (i = 0; i < 4; i++) {
3919                 reg = FDI_TX_CTL(pipe);
3920                 temp = I915_READ(reg);
3921                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3922                 temp |= snb_b_fdi_train_param[i];
3923                 I915_WRITE(reg, temp);
3924
3925                 POSTING_READ(reg);
3926                 udelay(500);
3927
3928                 for (retry = 0; retry < 5; retry++) {
3929                         reg = FDI_RX_IIR(pipe);
3930                         temp = I915_READ(reg);
3931                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3932                         if (temp & FDI_RX_SYMBOL_LOCK) {
3933                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3934                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3935                                 break;
3936                         }
3937                         udelay(50);
3938                 }
3939                 if (retry < 5)
3940                         break;
3941         }
3942         if (i == 4)
3943                 DRM_ERROR("FDI train 2 fail!\n");
3944
3945         DRM_DEBUG_KMS("FDI train done.\n");
3946 }
3947
3948 /* Manual link training for Ivy Bridge A0 parts */
3949 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3950                                       const struct intel_crtc_state *crtc_state)
3951 {
3952         struct drm_device *dev = crtc->base.dev;
3953         struct drm_i915_private *dev_priv = to_i915(dev);
3954         int pipe = crtc->pipe;
3955         i915_reg_t reg;
3956         u32 temp, i, j;
3957
3958         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3959            for train result */
3960         reg = FDI_RX_IMR(pipe);
3961         temp = I915_READ(reg);
3962         temp &= ~FDI_RX_SYMBOL_LOCK;
3963         temp &= ~FDI_RX_BIT_LOCK;
3964         I915_WRITE(reg, temp);
3965
3966         POSTING_READ(reg);
3967         udelay(150);
3968
3969         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3970                       I915_READ(FDI_RX_IIR(pipe)));
3971
3972         /* Try each vswing and preemphasis setting twice before moving on */
3973         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3974                 /* disable first in case we need to retry */
3975                 reg = FDI_TX_CTL(pipe);
3976                 temp = I915_READ(reg);
3977                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3978                 temp &= ~FDI_TX_ENABLE;
3979                 I915_WRITE(reg, temp);
3980
3981                 reg = FDI_RX_CTL(pipe);
3982                 temp = I915_READ(reg);
3983                 temp &= ~FDI_LINK_TRAIN_AUTO;
3984                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3985                 temp &= ~FDI_RX_ENABLE;
3986                 I915_WRITE(reg, temp);
3987
3988                 /* enable CPU FDI TX and PCH FDI RX */
3989                 reg = FDI_TX_CTL(pipe);
3990                 temp = I915_READ(reg);
3991                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3992                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3993                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3994                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3995                 temp |= snb_b_fdi_train_param[j/2];
3996                 temp |= FDI_COMPOSITE_SYNC;
3997                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3998
3999                 I915_WRITE(FDI_RX_MISC(pipe),
4000                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4001
4002                 reg = FDI_RX_CTL(pipe);
4003                 temp = I915_READ(reg);
4004                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4005                 temp |= FDI_COMPOSITE_SYNC;
4006                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4007
4008                 POSTING_READ(reg);
4009                 udelay(1); /* should be 0.5us */
4010
4011                 for (i = 0; i < 4; i++) {
4012                         reg = FDI_RX_IIR(pipe);
4013                         temp = I915_READ(reg);
4014                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4015
4016                         if (temp & FDI_RX_BIT_LOCK ||
4017                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4018                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4019                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4020                                               i);
4021                                 break;
4022                         }
4023                         udelay(1); /* should be 0.5us */
4024                 }
4025                 if (i == 4) {
4026                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4027                         continue;
4028                 }
4029
4030                 /* Train 2 */
4031                 reg = FDI_TX_CTL(pipe);
4032                 temp = I915_READ(reg);
4033                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4034                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4035                 I915_WRITE(reg, temp);
4036
4037                 reg = FDI_RX_CTL(pipe);
4038                 temp = I915_READ(reg);
4039                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4040                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4041                 I915_WRITE(reg, temp);
4042
4043                 POSTING_READ(reg);
4044                 udelay(2); /* should be 1.5us */
4045
4046                 for (i = 0; i < 4; i++) {
4047                         reg = FDI_RX_IIR(pipe);
4048                         temp = I915_READ(reg);
4049                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4050
4051                         if (temp & FDI_RX_SYMBOL_LOCK ||
4052                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4053                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4054                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4055                                               i);
4056                                 goto train_done;
4057                         }
4058                         udelay(2); /* should be 1.5us */
4059                 }
4060                 if (i == 4)
4061                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4062         }
4063
4064 train_done:
4065         DRM_DEBUG_KMS("FDI train done.\n");
4066 }
4067
4068 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4069 {
4070         struct drm_device *dev = intel_crtc->base.dev;
4071         struct drm_i915_private *dev_priv = to_i915(dev);
4072         int pipe = intel_crtc->pipe;
4073         i915_reg_t reg;
4074         u32 temp;
4075
4076         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4077         reg = FDI_RX_CTL(pipe);
4078         temp = I915_READ(reg);
4079         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4080         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4081         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4082         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4083
4084         POSTING_READ(reg);
4085         udelay(200);
4086
4087         /* Switch from Rawclk to PCDclk */
4088         temp = I915_READ(reg);
4089         I915_WRITE(reg, temp | FDI_PCDCLK);
4090
4091         POSTING_READ(reg);
4092         udelay(200);
4093
4094         /* Enable CPU FDI TX PLL, always on for Ironlake */
4095         reg = FDI_TX_CTL(pipe);
4096         temp = I915_READ(reg);
4097         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4098                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4099
4100                 POSTING_READ(reg);
4101                 udelay(100);
4102         }
4103 }
4104
4105 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4106 {
4107         struct drm_device *dev = intel_crtc->base.dev;
4108         struct drm_i915_private *dev_priv = to_i915(dev);
4109         int pipe = intel_crtc->pipe;
4110         i915_reg_t reg;
4111         u32 temp;
4112
4113         /* Switch from PCDclk to Rawclk */
4114         reg = FDI_RX_CTL(pipe);
4115         temp = I915_READ(reg);
4116         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4117
4118         /* Disable CPU FDI TX PLL */
4119         reg = FDI_TX_CTL(pipe);
4120         temp = I915_READ(reg);
4121         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4122
4123         POSTING_READ(reg);
4124         udelay(100);
4125
4126         reg = FDI_RX_CTL(pipe);
4127         temp = I915_READ(reg);
4128         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4129
4130         /* Wait for the clocks to turn off. */
4131         POSTING_READ(reg);
4132         udelay(100);
4133 }
4134
4135 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4136 {
4137         struct drm_device *dev = crtc->dev;
4138         struct drm_i915_private *dev_priv = to_i915(dev);
4139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4140         int pipe = intel_crtc->pipe;
4141         i915_reg_t reg;
4142         u32 temp;
4143
4144         /* disable CPU FDI tx and PCH FDI rx */
4145         reg = FDI_TX_CTL(pipe);
4146         temp = I915_READ(reg);
4147         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4148         POSTING_READ(reg);
4149
4150         reg = FDI_RX_CTL(pipe);
4151         temp = I915_READ(reg);
4152         temp &= ~(0x7 << 16);
4153         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4154         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4155
4156         POSTING_READ(reg);
4157         udelay(100);
4158
4159         /* Ironlake workaround, disable clock pointer after downing FDI */
4160         if (HAS_PCH_IBX(dev_priv))
4161                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4162
4163         /* still set train pattern 1 */
4164         reg = FDI_TX_CTL(pipe);
4165         temp = I915_READ(reg);
4166         temp &= ~FDI_LINK_TRAIN_NONE;
4167         temp |= FDI_LINK_TRAIN_PATTERN_1;
4168         I915_WRITE(reg, temp);
4169
4170         reg = FDI_RX_CTL(pipe);
4171         temp = I915_READ(reg);
4172         if (HAS_PCH_CPT(dev_priv)) {
4173                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4174                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4175         } else {
4176                 temp &= ~FDI_LINK_TRAIN_NONE;
4177                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4178         }
4179         /* BPC in FDI rx is consistent with that in PIPECONF */
4180         temp &= ~(0x07 << 16);
4181         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4182         I915_WRITE(reg, temp);
4183
4184         POSTING_READ(reg);
4185         udelay(100);
4186 }
4187
4188 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4189 {
4190         struct intel_crtc *crtc;
4191
4192         /* Note that we don't need to be called with mode_config.lock here
4193          * as our list of CRTC objects is static for the lifetime of the
4194          * device and so cannot disappear as we iterate. Similarly, we can
4195          * happily treat the predicates as racy, atomic checks as userspace
4196          * cannot claim and pin a new fb without at least acquring the
4197          * struct_mutex and so serialising with us.
4198          */
4199         for_each_intel_crtc(&dev_priv->drm, crtc) {
4200                 if (atomic_read(&crtc->unpin_work_count) == 0)
4201                         continue;
4202
4203                 if (crtc->flip_work)
4204                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4205
4206                 return true;
4207         }
4208
4209         return false;
4210 }
4211
4212 static void page_flip_completed(struct intel_crtc *intel_crtc)
4213 {
4214         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4215         struct intel_flip_work *work = intel_crtc->flip_work;
4216
4217         intel_crtc->flip_work = NULL;
4218
4219         if (work->event)
4220                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4221
4222         drm_crtc_vblank_put(&intel_crtc->base);
4223
4224         wake_up_all(&dev_priv->pending_flip_queue);
4225         trace_i915_flip_complete(intel_crtc->plane,
4226                                  work->pending_flip_obj);
4227
4228         queue_work(dev_priv->wq, &work->unpin_work);
4229 }
4230
4231 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4232 {
4233         struct drm_device *dev = crtc->dev;
4234         struct drm_i915_private *dev_priv = to_i915(dev);
4235         long ret;
4236
4237         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4238
4239         ret = wait_event_interruptible_timeout(
4240                                         dev_priv->pending_flip_queue,
4241                                         !intel_crtc_has_pending_flip(crtc),
4242                                         60*HZ);
4243
4244         if (ret < 0)
4245                 return ret;
4246
4247         if (ret == 0) {
4248                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249                 struct intel_flip_work *work;
4250
4251                 spin_lock_irq(&dev->event_lock);
4252                 work = intel_crtc->flip_work;
4253                 if (work && !is_mmio_work(work)) {
4254                         WARN_ONCE(1, "Removing stuck page flip\n");
4255                         page_flip_completed(intel_crtc);
4256                 }
4257                 spin_unlock_irq(&dev->event_lock);
4258         }
4259
4260         return 0;
4261 }
4262
4263 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4264 {
4265         u32 temp;
4266
4267         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4268
4269         mutex_lock(&dev_priv->sb_lock);
4270
4271         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4272         temp |= SBI_SSCCTL_DISABLE;
4273         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4274
4275         mutex_unlock(&dev_priv->sb_lock);
4276 }
4277
4278 /* Program iCLKIP clock to the desired frequency */
4279 static void lpt_program_iclkip(struct intel_crtc *crtc)
4280 {
4281         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4282         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4283         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4284         u32 temp;
4285
4286         lpt_disable_iclkip(dev_priv);
4287
4288         /* The iCLK virtual clock root frequency is in MHz,
4289          * but the adjusted_mode->crtc_clock in in KHz. To get the
4290          * divisors, it is necessary to divide one by another, so we
4291          * convert the virtual clock precision to KHz here for higher
4292          * precision.
4293          */
4294         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4295                 u32 iclk_virtual_root_freq = 172800 * 1000;
4296                 u32 iclk_pi_range = 64;
4297                 u32 desired_divisor;
4298
4299                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4300                                                     clock << auxdiv);
4301                 divsel = (desired_divisor / iclk_pi_range) - 2;
4302                 phaseinc = desired_divisor % iclk_pi_range;
4303
4304                 /*
4305                  * Near 20MHz is a corner case which is
4306                  * out of range for the 7-bit divisor
4307                  */
4308                 if (divsel <= 0x7f)
4309                         break;
4310         }
4311
4312         /* This should not happen with any sane values */
4313         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4314                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4315         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4316                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4317
4318         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4319                         clock,
4320                         auxdiv,
4321                         divsel,
4322                         phasedir,
4323                         phaseinc);
4324
4325         mutex_lock(&dev_priv->sb_lock);
4326
4327         /* Program SSCDIVINTPHASE6 */
4328         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4329         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4330         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4331         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4332         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4333         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4334         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4335         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4336
4337         /* Program SSCAUXDIV */
4338         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4339         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4340         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4341         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4342
4343         /* Enable modulator and associated divider */
4344         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4345         temp &= ~SBI_SSCCTL_DISABLE;
4346         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4347
4348         mutex_unlock(&dev_priv->sb_lock);
4349
4350         /* Wait for initialization time */
4351         udelay(24);
4352
4353         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4354 }
4355
4356 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4357 {
4358         u32 divsel, phaseinc, auxdiv;
4359         u32 iclk_virtual_root_freq = 172800 * 1000;
4360         u32 iclk_pi_range = 64;
4361         u32 desired_divisor;
4362         u32 temp;
4363
4364         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4365                 return 0;
4366
4367         mutex_lock(&dev_priv->sb_lock);
4368
4369         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4370         if (temp & SBI_SSCCTL_DISABLE) {
4371                 mutex_unlock(&dev_priv->sb_lock);
4372                 return 0;
4373         }
4374
4375         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4376         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4377                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4378         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4379                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4380
4381         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4382         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4383                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4384
4385         mutex_unlock(&dev_priv->sb_lock);
4386
4387         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4388
4389         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4390                                  desired_divisor << auxdiv);
4391 }
4392
4393 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4394                                                 enum pipe pch_transcoder)
4395 {
4396         struct drm_device *dev = crtc->base.dev;
4397         struct drm_i915_private *dev_priv = to_i915(dev);
4398         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4399
4400         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4401                    I915_READ(HTOTAL(cpu_transcoder)));
4402         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4403                    I915_READ(HBLANK(cpu_transcoder)));
4404         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4405                    I915_READ(HSYNC(cpu_transcoder)));
4406
4407         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4408                    I915_READ(VTOTAL(cpu_transcoder)));
4409         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4410                    I915_READ(VBLANK(cpu_transcoder)));
4411         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4412                    I915_READ(VSYNC(cpu_transcoder)));
4413         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4414                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4415 }
4416
4417 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4418 {
4419         struct drm_i915_private *dev_priv = to_i915(dev);
4420         uint32_t temp;
4421
4422         temp = I915_READ(SOUTH_CHICKEN1);
4423         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4424                 return;
4425
4426         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4427         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4428
4429         temp &= ~FDI_BC_BIFURCATION_SELECT;
4430         if (enable)
4431                 temp |= FDI_BC_BIFURCATION_SELECT;
4432
4433         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4434         I915_WRITE(SOUTH_CHICKEN1, temp);
4435         POSTING_READ(SOUTH_CHICKEN1);
4436 }
4437
4438 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4439 {
4440         struct drm_device *dev = intel_crtc->base.dev;
4441
4442         switch (intel_crtc->pipe) {
4443         case PIPE_A:
4444                 break;
4445         case PIPE_B:
4446                 if (intel_crtc->config->fdi_lanes > 2)
4447                         cpt_set_fdi_bc_bifurcation(dev, false);
4448                 else
4449                         cpt_set_fdi_bc_bifurcation(dev, true);
4450
4451                 break;
4452         case PIPE_C:
4453                 cpt_set_fdi_bc_bifurcation(dev, true);
4454
4455                 break;
4456         default:
4457                 BUG();
4458         }
4459 }
4460
4461 /* Return which DP Port should be selected for Transcoder DP control */
4462 static enum port
4463 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4464 {
4465         struct drm_device *dev = crtc->base.dev;
4466         struct intel_encoder *encoder;
4467
4468         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4469                 if (encoder->type == INTEL_OUTPUT_DP ||
4470                     encoder->type == INTEL_OUTPUT_EDP)
4471                         return enc_to_dig_port(&encoder->base)->port;
4472         }
4473
4474         return -1;
4475 }
4476
4477 /*
4478  * Enable PCH resources required for PCH ports:
4479  *   - PCH PLLs
4480  *   - FDI training & RX/TX
4481  *   - update transcoder timings
4482  *   - DP transcoding bits
4483  *   - transcoder
4484  */
4485 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4486 {
4487         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4488         struct drm_device *dev = crtc->base.dev;
4489         struct drm_i915_private *dev_priv = to_i915(dev);
4490         int pipe = crtc->pipe;
4491         u32 temp;
4492
4493         assert_pch_transcoder_disabled(dev_priv, pipe);
4494
4495         if (IS_IVYBRIDGE(dev_priv))
4496                 ivybridge_update_fdi_bc_bifurcation(crtc);
4497
4498         /* Write the TU size bits before fdi link training, so that error
4499          * detection works. */
4500         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4501                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4502
4503         /* For PCH output, training FDI link */
4504         dev_priv->display.fdi_link_train(crtc, crtc_state);
4505
4506         /* We need to program the right clock selection before writing the pixel
4507          * mutliplier into the DPLL. */
4508         if (HAS_PCH_CPT(dev_priv)) {
4509                 u32 sel;
4510
4511                 temp = I915_READ(PCH_DPLL_SEL);
4512                 temp |= TRANS_DPLL_ENABLE(pipe);
4513                 sel = TRANS_DPLLB_SEL(pipe);
4514                 if (crtc_state->shared_dpll ==
4515                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4516                         temp |= sel;
4517                 else
4518                         temp &= ~sel;
4519                 I915_WRITE(PCH_DPLL_SEL, temp);
4520         }
4521
4522         /* XXX: pch pll's can be enabled any time before we enable the PCH
4523          * transcoder, and we actually should do this to not upset any PCH
4524          * transcoder that already use the clock when we share it.
4525          *
4526          * Note that enable_shared_dpll tries to do the right thing, but
4527          * get_shared_dpll unconditionally resets the pll - we need that to have
4528          * the right LVDS enable sequence. */
4529         intel_enable_shared_dpll(crtc);
4530
4531         /* set transcoder timing, panel must allow it */
4532         assert_panel_unlocked(dev_priv, pipe);
4533         ironlake_pch_transcoder_set_timings(crtc, pipe);
4534
4535         intel_fdi_normal_train(crtc);
4536
4537         /* For PCH DP, enable TRANS_DP_CTL */
4538         if (HAS_PCH_CPT(dev_priv) &&
4539             intel_crtc_has_dp_encoder(crtc_state)) {
4540                 const struct drm_display_mode *adjusted_mode =
4541                         &crtc_state->base.adjusted_mode;
4542                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4543                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4544                 temp = I915_READ(reg);
4545                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4546                           TRANS_DP_SYNC_MASK |
4547                           TRANS_DP_BPC_MASK);
4548                 temp |= TRANS_DP_OUTPUT_ENABLE;
4549                 temp |= bpc << 9; /* same format but at 11:9 */
4550
4551                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4552                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4553                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4554                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4555
4556                 switch (intel_trans_dp_port_sel(crtc)) {
4557                 case PORT_B:
4558                         temp |= TRANS_DP_PORT_SEL_B;
4559                         break;
4560                 case PORT_C:
4561                         temp |= TRANS_DP_PORT_SEL_C;
4562                         break;
4563                 case PORT_D:
4564                         temp |= TRANS_DP_PORT_SEL_D;
4565                         break;
4566                 default:
4567                         BUG();
4568                 }
4569
4570                 I915_WRITE(reg, temp);
4571         }
4572
4573         ironlake_enable_pch_transcoder(dev_priv, pipe);
4574 }
4575
4576 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4577 {
4578         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4579         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4580         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4581
4582         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4583
4584         lpt_program_iclkip(crtc);
4585
4586         /* Set transcoder timing. */
4587         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4588
4589         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4590 }
4591
4592 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4593 {
4594         struct drm_i915_private *dev_priv = to_i915(dev);
4595         i915_reg_t dslreg = PIPEDSL(pipe);
4596         u32 temp;
4597
4598         temp = I915_READ(dslreg);
4599         udelay(500);
4600         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4601                 if (wait_for(I915_READ(dslreg) != temp, 5))
4602                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4603         }
4604 }
4605
4606 static int
4607 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4608                   unsigned int scaler_user, int *scaler_id,
4609                   int src_w, int src_h, int dst_w, int dst_h)
4610 {
4611         struct intel_crtc_scaler_state *scaler_state =
4612                 &crtc_state->scaler_state;
4613         struct intel_crtc *intel_crtc =
4614                 to_intel_crtc(crtc_state->base.crtc);
4615         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4616         const struct drm_display_mode *adjusted_mode =
4617                 &crtc_state->base.adjusted_mode;
4618         int need_scaling;
4619
4620         /*
4621          * Src coordinates are already rotated by 270 degrees for
4622          * the 90/270 degree plane rotation cases (to match the
4623          * GTT mapping), hence no need to account for rotation here.
4624          */
4625         need_scaling = src_w != dst_w || src_h != dst_h;
4626
4627         /*
4628          * Scaling/fitting not supported in IF-ID mode in GEN9+
4629          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4630          * Once NV12 is enabled, handle it here while allocating scaler
4631          * for NV12.
4632          */
4633         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4634             need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4635                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4636                 return -EINVAL;
4637         }
4638
4639         /*
4640          * if plane is being disabled or scaler is no more required or force detach
4641          *  - free scaler binded to this plane/crtc
4642          *  - in order to do this, update crtc->scaler_usage
4643          *
4644          * Here scaler state in crtc_state is set free so that
4645          * scaler can be assigned to other user. Actual register
4646          * update to free the scaler is done in plane/panel-fit programming.
4647          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4648          */
4649         if (force_detach || !need_scaling) {
4650                 if (*scaler_id >= 0) {
4651                         scaler_state->scaler_users &= ~(1 << scaler_user);
4652                         scaler_state->scalers[*scaler_id].in_use = 0;
4653
4654                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4655                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4656                                 intel_crtc->pipe, scaler_user, *scaler_id,
4657                                 scaler_state->scaler_users);
4658                         *scaler_id = -1;
4659                 }
4660                 return 0;
4661         }
4662
4663         /* range checks */
4664         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4665                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4666
4667                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4668                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4669                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4670                         "size is out of scaler range\n",
4671                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4672                 return -EINVAL;
4673         }
4674
4675         /* mark this plane as a scaler user in crtc_state */
4676         scaler_state->scaler_users |= (1 << scaler_user);
4677         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4678                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4679                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4680                 scaler_state->scaler_users);
4681
4682         return 0;
4683 }
4684
4685 /**
4686  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4687  *
4688  * @state: crtc's scaler state
4689  *
4690  * Return
4691  *     0 - scaler_usage updated successfully
4692  *    error - requested scaling cannot be supported or other error condition
4693  */
4694 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4695 {
4696         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4697
4698         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4699                 &state->scaler_state.scaler_id,
4700                 state->pipe_src_w, state->pipe_src_h,
4701                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4702 }
4703
4704 /**
4705  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4706  *
4707  * @state: crtc's scaler state
4708  * @plane_state: atomic plane state to update
4709  *
4710  * Return
4711  *     0 - scaler_usage updated successfully
4712  *    error - requested scaling cannot be supported or other error condition
4713  */
4714 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4715                                    struct intel_plane_state *plane_state)
4716 {
4717
4718         struct intel_plane *intel_plane =
4719                 to_intel_plane(plane_state->base.plane);
4720         struct drm_framebuffer *fb = plane_state->base.fb;
4721         int ret;
4722
4723         bool force_detach = !fb || !plane_state->base.visible;
4724
4725         ret = skl_update_scaler(crtc_state, force_detach,
4726                                 drm_plane_index(&intel_plane->base),
4727                                 &plane_state->scaler_id,
4728                                 drm_rect_width(&plane_state->base.src) >> 16,
4729                                 drm_rect_height(&plane_state->base.src) >> 16,
4730                                 drm_rect_width(&plane_state->base.dst),
4731                                 drm_rect_height(&plane_state->base.dst));
4732
4733         if (ret || plane_state->scaler_id < 0)
4734                 return ret;
4735
4736         /* check colorkey */
4737         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4738                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4739                               intel_plane->base.base.id,
4740                               intel_plane->base.name);
4741                 return -EINVAL;
4742         }
4743
4744         /* Check src format */
4745         switch (fb->format->format) {
4746         case DRM_FORMAT_RGB565:
4747         case DRM_FORMAT_XBGR8888:
4748         case DRM_FORMAT_XRGB8888:
4749         case DRM_FORMAT_ABGR8888:
4750         case DRM_FORMAT_ARGB8888:
4751         case DRM_FORMAT_XRGB2101010:
4752         case DRM_FORMAT_XBGR2101010:
4753         case DRM_FORMAT_YUYV:
4754         case DRM_FORMAT_YVYU:
4755         case DRM_FORMAT_UYVY:
4756         case DRM_FORMAT_VYUY:
4757                 break;
4758         default:
4759                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4760                               intel_plane->base.base.id, intel_plane->base.name,
4761                               fb->base.id, fb->format->format);
4762                 return -EINVAL;
4763         }
4764
4765         return 0;
4766 }
4767
4768 static void skylake_scaler_disable(struct intel_crtc *crtc)
4769 {
4770         int i;
4771
4772         for (i = 0; i < crtc->num_scalers; i++)
4773                 skl_detach_scaler(crtc, i);
4774 }
4775
4776 static void skylake_pfit_enable(struct intel_crtc *crtc)
4777 {
4778         struct drm_device *dev = crtc->base.dev;
4779         struct drm_i915_private *dev_priv = to_i915(dev);
4780         int pipe = crtc->pipe;
4781         struct intel_crtc_scaler_state *scaler_state =
4782                 &crtc->config->scaler_state;
4783
4784         if (crtc->config->pch_pfit.enabled) {
4785                 int id;
4786
4787                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4788                         return;
4789
4790                 id = scaler_state->scaler_id;
4791                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4792                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4793                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4794                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4795         }
4796 }
4797
4798 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4799 {
4800         struct drm_device *dev = crtc->base.dev;
4801         struct drm_i915_private *dev_priv = to_i915(dev);
4802         int pipe = crtc->pipe;
4803
4804         if (crtc->config->pch_pfit.enabled) {
4805                 /* Force use of hard-coded filter coefficients
4806                  * as some pre-programmed values are broken,
4807                  * e.g. x201.
4808                  */
4809                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4810                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4811                                                  PF_PIPE_SEL_IVB(pipe));
4812                 else
4813                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4814                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4815                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4816         }
4817 }
4818
4819 void hsw_enable_ips(struct intel_crtc *crtc)
4820 {
4821         struct drm_device *dev = crtc->base.dev;
4822         struct drm_i915_private *dev_priv = to_i915(dev);
4823
4824         if (!crtc->config->ips_enabled)
4825                 return;
4826
4827         /*
4828          * We can only enable IPS after we enable a plane and wait for a vblank
4829          * This function is called from post_plane_update, which is run after
4830          * a vblank wait.
4831          */
4832
4833         assert_plane_enabled(dev_priv, crtc->plane);
4834         if (IS_BROADWELL(dev_priv)) {
4835                 mutex_lock(&dev_priv->rps.hw_lock);
4836                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4837                 mutex_unlock(&dev_priv->rps.hw_lock);
4838                 /* Quoting Art Runyan: "its not safe to expect any particular
4839                  * value in IPS_CTL bit 31 after enabling IPS through the
4840                  * mailbox." Moreover, the mailbox may return a bogus state,
4841                  * so we need to just enable it and continue on.
4842                  */
4843         } else {
4844                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4845                 /* The bit only becomes 1 in the next vblank, so this wait here
4846                  * is essentially intel_wait_for_vblank. If we don't have this
4847                  * and don't wait for vblanks until the end of crtc_enable, then
4848                  * the HW state readout code will complain that the expected
4849                  * IPS_CTL value is not the one we read. */
4850                 if (intel_wait_for_register(dev_priv,
4851                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4852                                             50))
4853                         DRM_ERROR("Timed out waiting for IPS enable\n");
4854         }
4855 }
4856
4857 void hsw_disable_ips(struct intel_crtc *crtc)
4858 {
4859         struct drm_device *dev = crtc->base.dev;
4860         struct drm_i915_private *dev_priv = to_i915(dev);
4861
4862         if (!crtc->config->ips_enabled)
4863                 return;
4864
4865         assert_plane_enabled(dev_priv, crtc->plane);
4866         if (IS_BROADWELL(dev_priv)) {
4867                 mutex_lock(&dev_priv->rps.hw_lock);
4868                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4869                 mutex_unlock(&dev_priv->rps.hw_lock);
4870                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4871                 if (intel_wait_for_register(dev_priv,
4872                                             IPS_CTL, IPS_ENABLE, 0,
4873                                             42))
4874                         DRM_ERROR("Timed out waiting for IPS disable\n");
4875         } else {
4876                 I915_WRITE(IPS_CTL, 0);
4877                 POSTING_READ(IPS_CTL);
4878         }
4879
4880         /* We need to wait for a vblank before we can disable the plane. */
4881         intel_wait_for_vblank(dev_priv, crtc->pipe);
4882 }
4883
4884 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4885 {
4886         if (intel_crtc->overlay) {
4887                 struct drm_device *dev = intel_crtc->base.dev;
4888
4889                 mutex_lock(&dev->struct_mutex);
4890                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4891                 mutex_unlock(&dev->struct_mutex);
4892         }
4893
4894         /* Let userspace switch the overlay on again. In most cases userspace
4895          * has to recompute where to put it anyway.
4896          */
4897 }
4898
4899 /**
4900  * intel_post_enable_primary - Perform operations after enabling primary plane
4901  * @crtc: the CRTC whose primary plane was just enabled
4902  *
4903  * Performs potentially sleeping operations that must be done after the primary
4904  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4905  * called due to an explicit primary plane update, or due to an implicit
4906  * re-enable that is caused when a sprite plane is updated to no longer
4907  * completely hide the primary plane.
4908  */
4909 static void
4910 intel_post_enable_primary(struct drm_crtc *crtc)
4911 {
4912         struct drm_device *dev = crtc->dev;
4913         struct drm_i915_private *dev_priv = to_i915(dev);
4914         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4915         int pipe = intel_crtc->pipe;
4916
4917         /*
4918          * FIXME IPS should be fine as long as one plane is
4919          * enabled, but in practice it seems to have problems
4920          * when going from primary only to sprite only and vice
4921          * versa.
4922          */
4923         hsw_enable_ips(intel_crtc);
4924
4925         /*
4926          * Gen2 reports pipe underruns whenever all planes are disabled.
4927          * So don't enable underrun reporting before at least some planes
4928          * are enabled.
4929          * FIXME: Need to fix the logic to work when we turn off all planes
4930          * but leave the pipe running.
4931          */
4932         if (IS_GEN2(dev_priv))
4933                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4934
4935         /* Underruns don't always raise interrupts, so check manually. */
4936         intel_check_cpu_fifo_underruns(dev_priv);
4937         intel_check_pch_fifo_underruns(dev_priv);
4938 }
4939
4940 /* FIXME move all this to pre_plane_update() with proper state tracking */
4941 static void
4942 intel_pre_disable_primary(struct drm_crtc *crtc)
4943 {
4944         struct drm_device *dev = crtc->dev;
4945         struct drm_i915_private *dev_priv = to_i915(dev);
4946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4947         int pipe = intel_crtc->pipe;
4948
4949         /*
4950          * Gen2 reports pipe underruns whenever all planes are disabled.
4951          * So diasble underrun reporting before all the planes get disabled.
4952          * FIXME: Need to fix the logic to work when we turn off all planes
4953          * but leave the pipe running.
4954          */
4955         if (IS_GEN2(dev_priv))
4956                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4957
4958         /*
4959          * FIXME IPS should be fine as long as one plane is
4960          * enabled, but in practice it seems to have problems
4961          * when going from primary only to sprite only and vice
4962          * versa.
4963          */
4964         hsw_disable_ips(intel_crtc);
4965 }
4966
4967 /* FIXME get rid of this and use pre_plane_update */
4968 static void
4969 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4970 {
4971         struct drm_device *dev = crtc->dev;
4972         struct drm_i915_private *dev_priv = to_i915(dev);
4973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4974         int pipe = intel_crtc->pipe;
4975
4976         intel_pre_disable_primary(crtc);
4977
4978         /*
4979          * Vblank time updates from the shadow to live plane control register
4980          * are blocked if the memory self-refresh mode is active at that
4981          * moment. So to make sure the plane gets truly disabled, disable
4982          * first the self-refresh mode. The self-refresh enable bit in turn
4983          * will be checked/applied by the HW only at the next frame start
4984          * event which is after the vblank start event, so we need to have a
4985          * wait-for-vblank between disabling the plane and the pipe.
4986          */
4987         if (HAS_GMCH_DISPLAY(dev_priv) &&
4988             intel_set_memory_cxsr(dev_priv, false))
4989                 intel_wait_for_vblank(dev_priv, pipe);
4990 }
4991
4992 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4993 {
4994         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4995         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4996         struct intel_crtc_state *pipe_config =
4997                 to_intel_crtc_state(crtc->base.state);
4998         struct drm_plane *primary = crtc->base.primary;
4999         struct drm_plane_state *old_pri_state =
5000                 drm_atomic_get_existing_plane_state(old_state, primary);
5001
5002         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5003
5004         if (pipe_config->update_wm_post && pipe_config->base.active)
5005                 intel_update_watermarks(crtc);
5006
5007         if (old_pri_state) {
5008                 struct intel_plane_state *primary_state =
5009                         to_intel_plane_state(primary->state);
5010                 struct intel_plane_state *old_primary_state =
5011                         to_intel_plane_state(old_pri_state);
5012
5013                 intel_fbc_post_update(crtc);
5014
5015                 if (primary_state->base.visible &&
5016                     (needs_modeset(&pipe_config->base) ||
5017                      !old_primary_state->base.visible))
5018                         intel_post_enable_primary(&crtc->base);
5019         }
5020 }
5021
5022 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5023                                    struct intel_crtc_state *pipe_config)
5024 {
5025         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5026         struct drm_device *dev = crtc->base.dev;
5027         struct drm_i915_private *dev_priv = to_i915(dev);
5028         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5029         struct drm_plane *primary = crtc->base.primary;
5030         struct drm_plane_state *old_pri_state =
5031                 drm_atomic_get_existing_plane_state(old_state, primary);
5032         bool modeset = needs_modeset(&pipe_config->base);
5033         struct intel_atomic_state *old_intel_state =
5034                 to_intel_atomic_state(old_state);
5035
5036         if (old_pri_state) {
5037                 struct intel_plane_state *primary_state =
5038                         to_intel_plane_state(primary->state);
5039                 struct intel_plane_state *old_primary_state =
5040                         to_intel_plane_state(old_pri_state);
5041
5042                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5043
5044                 if (old_primary_state->base.visible &&
5045                     (modeset || !primary_state->base.visible))
5046                         intel_pre_disable_primary(&crtc->base);
5047         }
5048
5049         /*
5050          * Vblank time updates from the shadow to live plane control register
5051          * are blocked if the memory self-refresh mode is active at that
5052          * moment. So to make sure the plane gets truly disabled, disable
5053          * first the self-refresh mode. The self-refresh enable bit in turn
5054          * will be checked/applied by the HW only at the next frame start
5055          * event which is after the vblank start event, so we need to have a
5056          * wait-for-vblank between disabling the plane and the pipe.
5057          */
5058         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5059             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5060                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5061
5062         /*
5063          * IVB workaround: must disable low power watermarks for at least
5064          * one frame before enabling scaling.  LP watermarks can be re-enabled
5065          * when scaling is disabled.
5066          *
5067          * WaCxSRDisabledForSpriteScaling:ivb
5068          */
5069         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5070                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5071
5072         /*
5073          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5074          * watermark programming here.
5075          */
5076         if (needs_modeset(&pipe_config->base))
5077                 return;
5078
5079         /*
5080          * For platforms that support atomic watermarks, program the
5081          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5082          * will be the intermediate values that are safe for both pre- and
5083          * post- vblank; when vblank happens, the 'active' values will be set
5084          * to the final 'target' values and we'll do this again to get the
5085          * optimal watermarks.  For gen9+ platforms, the values we program here
5086          * will be the final target values which will get automatically latched
5087          * at vblank time; no further programming will be necessary.
5088          *
5089          * If a platform hasn't been transitioned to atomic watermarks yet,
5090          * we'll continue to update watermarks the old way, if flags tell
5091          * us to.
5092          */
5093         if (dev_priv->display.initial_watermarks != NULL)
5094                 dev_priv->display.initial_watermarks(old_intel_state,
5095                                                      pipe_config);
5096         else if (pipe_config->update_wm_pre)
5097                 intel_update_watermarks(crtc);
5098 }
5099
5100 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5101 {
5102         struct drm_device *dev = crtc->dev;
5103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5104         struct drm_plane *p;
5105         int pipe = intel_crtc->pipe;
5106
5107         intel_crtc_dpms_overlay_disable(intel_crtc);
5108
5109         drm_for_each_plane_mask(p, dev, plane_mask)
5110                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5111
5112         /*
5113          * FIXME: Once we grow proper nuclear flip support out of this we need
5114          * to compute the mask of flip planes precisely. For the time being
5115          * consider this a flip to a NULL plane.
5116          */
5117         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5118 }
5119
5120 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5121                                           struct intel_crtc_state *crtc_state,
5122                                           struct drm_atomic_state *old_state)
5123 {
5124         struct drm_connector_state *conn_state;
5125         struct drm_connector *conn;
5126         int i;
5127
5128         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5129                 struct intel_encoder *encoder =
5130                         to_intel_encoder(conn_state->best_encoder);
5131
5132                 if (conn_state->crtc != crtc)
5133                         continue;
5134
5135                 if (encoder->pre_pll_enable)
5136                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5137         }
5138 }
5139
5140 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5141                                       struct intel_crtc_state *crtc_state,
5142                                       struct drm_atomic_state *old_state)
5143 {
5144         struct drm_connector_state *conn_state;
5145         struct drm_connector *conn;
5146         int i;
5147
5148         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5149                 struct intel_encoder *encoder =
5150                         to_intel_encoder(conn_state->best_encoder);
5151
5152                 if (conn_state->crtc != crtc)
5153                         continue;
5154
5155                 if (encoder->pre_enable)
5156                         encoder->pre_enable(encoder, crtc_state, conn_state);
5157         }
5158 }
5159
5160 static void intel_encoders_enable(struct drm_crtc *crtc,
5161                                   struct intel_crtc_state *crtc_state,
5162                                   struct drm_atomic_state *old_state)
5163 {
5164         struct drm_connector_state *conn_state;
5165         struct drm_connector *conn;
5166         int i;
5167
5168         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5169                 struct intel_encoder *encoder =
5170                         to_intel_encoder(conn_state->best_encoder);
5171
5172                 if (conn_state->crtc != crtc)
5173                         continue;
5174
5175                 encoder->enable(encoder, crtc_state, conn_state);
5176                 intel_opregion_notify_encoder(encoder, true);
5177         }
5178 }
5179
5180 static void intel_encoders_disable(struct drm_crtc *crtc,
5181                                    struct intel_crtc_state *old_crtc_state,
5182                                    struct drm_atomic_state *old_state)
5183 {
5184         struct drm_connector_state *old_conn_state;
5185         struct drm_connector *conn;
5186         int i;
5187
5188         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5189                 struct intel_encoder *encoder =
5190                         to_intel_encoder(old_conn_state->best_encoder);
5191
5192                 if (old_conn_state->crtc != crtc)
5193                         continue;
5194
5195                 intel_opregion_notify_encoder(encoder, false);
5196                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5197         }
5198 }
5199
5200 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5201                                         struct intel_crtc_state *old_crtc_state,
5202                                         struct drm_atomic_state *old_state)
5203 {
5204         struct drm_connector_state *old_conn_state;
5205         struct drm_connector *conn;
5206         int i;
5207
5208         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5209                 struct intel_encoder *encoder =
5210                         to_intel_encoder(old_conn_state->best_encoder);
5211
5212                 if (old_conn_state->crtc != crtc)
5213                         continue;
5214
5215                 if (encoder->post_disable)
5216                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5217         }
5218 }
5219
5220 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5221                                             struct intel_crtc_state *old_crtc_state,
5222                                             struct drm_atomic_state *old_state)
5223 {
5224         struct drm_connector_state *old_conn_state;
5225         struct drm_connector *conn;
5226         int i;
5227
5228         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5229                 struct intel_encoder *encoder =
5230                         to_intel_encoder(old_conn_state->best_encoder);
5231
5232                 if (old_conn_state->crtc != crtc)
5233                         continue;
5234
5235                 if (encoder->post_pll_disable)
5236                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5237         }
5238 }
5239
5240 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5241                                  struct drm_atomic_state *old_state)
5242 {
5243         struct drm_crtc *crtc = pipe_config->base.crtc;
5244         struct drm_device *dev = crtc->dev;
5245         struct drm_i915_private *dev_priv = to_i915(dev);
5246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5247         int pipe = intel_crtc->pipe;
5248         struct intel_atomic_state *old_intel_state =
5249                 to_intel_atomic_state(old_state);
5250
5251         if (WARN_ON(intel_crtc->active))
5252                 return;
5253
5254         /*
5255          * Sometimes spurious CPU pipe underruns happen during FDI
5256          * training, at least with VGA+HDMI cloning. Suppress them.
5257          *
5258          * On ILK we get an occasional spurious CPU pipe underruns
5259          * between eDP port A enable and vdd enable. Also PCH port
5260          * enable seems to result in the occasional CPU pipe underrun.
5261          *
5262          * Spurious PCH underruns also occur during PCH enabling.
5263          */
5264         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5265                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5266         if (intel_crtc->config->has_pch_encoder)
5267                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5268
5269         if (intel_crtc->config->has_pch_encoder)
5270                 intel_prepare_shared_dpll(intel_crtc);
5271
5272         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5273                 intel_dp_set_m_n(intel_crtc, M1_N1);
5274
5275         intel_set_pipe_timings(intel_crtc);
5276         intel_set_pipe_src_size(intel_crtc);
5277
5278         if (intel_crtc->config->has_pch_encoder) {
5279                 intel_cpu_transcoder_set_m_n(intel_crtc,
5280                                      &intel_crtc->config->fdi_m_n, NULL);
5281         }
5282
5283         ironlake_set_pipeconf(crtc);
5284
5285         intel_crtc->active = true;
5286
5287         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5288
5289         if (intel_crtc->config->has_pch_encoder) {
5290                 /* Note: FDI PLL enabling _must_ be done before we enable the
5291                  * cpu pipes, hence this is separate from all the other fdi/pch
5292                  * enabling. */
5293                 ironlake_fdi_pll_enable(intel_crtc);
5294         } else {
5295                 assert_fdi_tx_disabled(dev_priv, pipe);
5296                 assert_fdi_rx_disabled(dev_priv, pipe);
5297         }
5298
5299         ironlake_pfit_enable(intel_crtc);
5300
5301         /*
5302          * On ILK+ LUT must be loaded before the pipe is running but with
5303          * clocks enabled
5304          */
5305         intel_color_load_luts(&pipe_config->base);
5306
5307         if (dev_priv->display.initial_watermarks != NULL)
5308                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5309         intel_enable_pipe(intel_crtc);
5310
5311         if (intel_crtc->config->has_pch_encoder)
5312                 ironlake_pch_enable(pipe_config);
5313
5314         assert_vblank_disabled(crtc);
5315         drm_crtc_vblank_on(crtc);
5316
5317         intel_encoders_enable(crtc, pipe_config, old_state);
5318
5319         if (HAS_PCH_CPT(dev_priv))
5320                 cpt_verify_modeset(dev, intel_crtc->pipe);
5321
5322         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5323         if (intel_crtc->config->has_pch_encoder)
5324                 intel_wait_for_vblank(dev_priv, pipe);
5325         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5326         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5327 }
5328
5329 /* IPS only exists on ULT machines and is tied to pipe A. */
5330 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5331 {
5332         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5333 }
5334
5335 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5336                                 struct drm_atomic_state *old_state)
5337 {
5338         struct drm_crtc *crtc = pipe_config->base.crtc;
5339         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5341         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5342         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5343         struct intel_atomic_state *old_intel_state =
5344                 to_intel_atomic_state(old_state);
5345
5346         if (WARN_ON(intel_crtc->active))
5347                 return;
5348
5349         if (intel_crtc->config->has_pch_encoder)
5350                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5351                                                       false);
5352
5353         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5354
5355         if (intel_crtc->config->shared_dpll)
5356                 intel_enable_shared_dpll(intel_crtc);
5357
5358         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5359                 intel_dp_set_m_n(intel_crtc, M1_N1);
5360
5361         if (!transcoder_is_dsi(cpu_transcoder))
5362                 intel_set_pipe_timings(intel_crtc);
5363
5364         intel_set_pipe_src_size(intel_crtc);
5365
5366         if (cpu_transcoder != TRANSCODER_EDP &&
5367             !transcoder_is_dsi(cpu_transcoder)) {
5368                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5369                            intel_crtc->config->pixel_multiplier - 1);
5370         }
5371
5372         if (intel_crtc->config->has_pch_encoder) {
5373                 intel_cpu_transcoder_set_m_n(intel_crtc,
5374                                      &intel_crtc->config->fdi_m_n, NULL);
5375         }
5376
5377         if (!transcoder_is_dsi(cpu_transcoder))
5378                 haswell_set_pipeconf(crtc);
5379
5380         haswell_set_pipemisc(crtc);
5381
5382         intel_color_set_csc(&pipe_config->base);
5383
5384         intel_crtc->active = true;
5385
5386         if (intel_crtc->config->has_pch_encoder)
5387                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5388         else
5389                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5390
5391         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5392
5393         if (intel_crtc->config->has_pch_encoder)
5394                 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5395
5396         if (!transcoder_is_dsi(cpu_transcoder))
5397                 intel_ddi_enable_pipe_clock(pipe_config);
5398
5399         if (INTEL_GEN(dev_priv) >= 9)
5400                 skylake_pfit_enable(intel_crtc);
5401         else
5402                 ironlake_pfit_enable(intel_crtc);
5403
5404         /*
5405          * On ILK+ LUT must be loaded before the pipe is running but with
5406          * clocks enabled
5407          */
5408         intel_color_load_luts(&pipe_config->base);
5409
5410         intel_ddi_set_pipe_settings(pipe_config);
5411         if (!transcoder_is_dsi(cpu_transcoder))
5412                 intel_ddi_enable_transcoder_func(pipe_config);
5413
5414         if (dev_priv->display.initial_watermarks != NULL)
5415                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5416
5417         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5418         if (!transcoder_is_dsi(cpu_transcoder))
5419                 intel_enable_pipe(intel_crtc);
5420
5421         if (intel_crtc->config->has_pch_encoder)
5422                 lpt_pch_enable(pipe_config);
5423
5424         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5425                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5426
5427         assert_vblank_disabled(crtc);
5428         drm_crtc_vblank_on(crtc);
5429
5430         intel_encoders_enable(crtc, pipe_config, old_state);
5431
5432         if (intel_crtc->config->has_pch_encoder) {
5433                 intel_wait_for_vblank(dev_priv, pipe);
5434                 intel_wait_for_vblank(dev_priv, pipe);
5435                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5436                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5437                                                       true);
5438         }
5439
5440         /* If we change the relative order between pipe/planes enabling, we need
5441          * to change the workaround. */
5442         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5443         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5444                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5445                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5446         }
5447 }
5448
5449 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5450 {
5451         struct drm_device *dev = crtc->base.dev;
5452         struct drm_i915_private *dev_priv = to_i915(dev);
5453         int pipe = crtc->pipe;
5454
5455         /* To avoid upsetting the power well on haswell only disable the pfit if
5456          * it's in use. The hw state code will make sure we get this right. */
5457         if (force || crtc->config->pch_pfit.enabled) {
5458                 I915_WRITE(PF_CTL(pipe), 0);
5459                 I915_WRITE(PF_WIN_POS(pipe), 0);
5460                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5461         }
5462 }
5463
5464 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5465                                   struct drm_atomic_state *old_state)
5466 {
5467         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5468         struct drm_device *dev = crtc->dev;
5469         struct drm_i915_private *dev_priv = to_i915(dev);
5470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5471         int pipe = intel_crtc->pipe;
5472
5473         /*
5474          * Sometimes spurious CPU pipe underruns happen when the
5475          * pipe is already disabled, but FDI RX/TX is still enabled.
5476          * Happens at least with VGA+HDMI cloning. Suppress them.
5477          */
5478         if (intel_crtc->config->has_pch_encoder) {
5479                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5480                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5481         }
5482
5483         intel_encoders_disable(crtc, old_crtc_state, old_state);
5484
5485         drm_crtc_vblank_off(crtc);
5486         assert_vblank_disabled(crtc);
5487
5488         intel_disable_pipe(intel_crtc);
5489
5490         ironlake_pfit_disable(intel_crtc, false);
5491
5492         if (intel_crtc->config->has_pch_encoder)
5493                 ironlake_fdi_disable(crtc);
5494
5495         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5496
5497         if (intel_crtc->config->has_pch_encoder) {
5498                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5499
5500                 if (HAS_PCH_CPT(dev_priv)) {
5501                         i915_reg_t reg;
5502                         u32 temp;
5503
5504                         /* disable TRANS_DP_CTL */
5505                         reg = TRANS_DP_CTL(pipe);
5506                         temp = I915_READ(reg);
5507                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5508                                   TRANS_DP_PORT_SEL_MASK);
5509                         temp |= TRANS_DP_PORT_SEL_NONE;
5510                         I915_WRITE(reg, temp);
5511
5512                         /* disable DPLL_SEL */
5513                         temp = I915_READ(PCH_DPLL_SEL);
5514                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5515                         I915_WRITE(PCH_DPLL_SEL, temp);
5516                 }
5517
5518                 ironlake_fdi_pll_disable(intel_crtc);
5519         }
5520
5521         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5522         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5523 }
5524
5525 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5526                                  struct drm_atomic_state *old_state)
5527 {
5528         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5529         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5531         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5532
5533         if (intel_crtc->config->has_pch_encoder)
5534                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5535                                                       false);
5536
5537         intel_encoders_disable(crtc, old_crtc_state, old_state);
5538
5539         drm_crtc_vblank_off(crtc);
5540         assert_vblank_disabled(crtc);
5541
5542         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5543         if (!transcoder_is_dsi(cpu_transcoder))
5544                 intel_disable_pipe(intel_crtc);
5545
5546         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5547                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5548
5549         if (!transcoder_is_dsi(cpu_transcoder))
5550                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5551
5552         if (INTEL_GEN(dev_priv) >= 9)
5553                 skylake_scaler_disable(intel_crtc);
5554         else
5555                 ironlake_pfit_disable(intel_crtc, false);
5556
5557         if (!transcoder_is_dsi(cpu_transcoder))
5558                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5559
5560         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5561
5562         if (old_crtc_state->has_pch_encoder)
5563                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5564                                                       true);
5565 }
5566
5567 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5568 {
5569         struct drm_device *dev = crtc->base.dev;
5570         struct drm_i915_private *dev_priv = to_i915(dev);
5571         struct intel_crtc_state *pipe_config = crtc->config;
5572
5573         if (!pipe_config->gmch_pfit.control)
5574                 return;
5575
5576         /*
5577          * The panel fitter should only be adjusted whilst the pipe is disabled,
5578          * according to register description and PRM.
5579          */
5580         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5581         assert_pipe_disabled(dev_priv, crtc->pipe);
5582
5583         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5584         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5585
5586         /* Border color in case we don't scale up to the full screen. Black by
5587          * default, change to something else for debugging. */
5588         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5589 }
5590
5591 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5592 {
5593         switch (port) {
5594         case PORT_A:
5595                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5596         case PORT_B:
5597                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5598         case PORT_C:
5599                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5600         case PORT_D:
5601                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5602         case PORT_E:
5603                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5604         default:
5605                 MISSING_CASE(port);
5606                 return POWER_DOMAIN_PORT_OTHER;
5607         }
5608 }
5609
5610 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5611                                   struct intel_crtc_state *crtc_state)
5612 {
5613         struct drm_device *dev = crtc->dev;
5614         struct drm_i915_private *dev_priv = to_i915(dev);
5615         struct drm_encoder *encoder;
5616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5617         enum pipe pipe = intel_crtc->pipe;
5618         u64 mask;
5619         enum transcoder transcoder = crtc_state->cpu_transcoder;
5620
5621         if (!crtc_state->base.active)
5622                 return 0;
5623
5624         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5625         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5626         if (crtc_state->pch_pfit.enabled ||
5627             crtc_state->pch_pfit.force_thru)
5628                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5629
5630         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5631                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5632
5633                 mask |= BIT_ULL(intel_encoder->power_domain);
5634         }
5635
5636         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5637                 mask |= BIT(POWER_DOMAIN_AUDIO);
5638
5639         if (crtc_state->shared_dpll)
5640                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5641
5642         return mask;
5643 }
5644
5645 static u64
5646 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5647                                struct intel_crtc_state *crtc_state)
5648 {
5649         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5651         enum intel_display_power_domain domain;
5652         u64 domains, new_domains, old_domains;
5653
5654         old_domains = intel_crtc->enabled_power_domains;
5655         intel_crtc->enabled_power_domains = new_domains =
5656                 get_crtc_power_domains(crtc, crtc_state);
5657
5658         domains = new_domains & ~old_domains;
5659
5660         for_each_power_domain(domain, domains)
5661                 intel_display_power_get(dev_priv, domain);
5662
5663         return old_domains & ~new_domains;
5664 }
5665
5666 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5667                                       u64 domains)
5668 {
5669         enum intel_display_power_domain domain;
5670
5671         for_each_power_domain(domain, domains)
5672                 intel_display_power_put(dev_priv, domain);
5673 }
5674
5675 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5676                                    struct drm_atomic_state *old_state)
5677 {
5678         struct intel_atomic_state *old_intel_state =
5679                 to_intel_atomic_state(old_state);
5680         struct drm_crtc *crtc = pipe_config->base.crtc;
5681         struct drm_device *dev = crtc->dev;
5682         struct drm_i915_private *dev_priv = to_i915(dev);
5683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5684         int pipe = intel_crtc->pipe;
5685
5686         if (WARN_ON(intel_crtc->active))
5687                 return;
5688
5689         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5690                 intel_dp_set_m_n(intel_crtc, M1_N1);
5691
5692         intel_set_pipe_timings(intel_crtc);
5693         intel_set_pipe_src_size(intel_crtc);
5694
5695         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5696                 struct drm_i915_private *dev_priv = to_i915(dev);
5697
5698                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5699                 I915_WRITE(CHV_CANVAS(pipe), 0);
5700         }
5701
5702         i9xx_set_pipeconf(intel_crtc);
5703
5704         intel_crtc->active = true;
5705
5706         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5707
5708         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5709
5710         if (IS_CHERRYVIEW(dev_priv)) {
5711                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5712                 chv_enable_pll(intel_crtc, intel_crtc->config);
5713         } else {
5714                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5715                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5716         }
5717
5718         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5719
5720         i9xx_pfit_enable(intel_crtc);
5721
5722         intel_color_load_luts(&pipe_config->base);
5723
5724         dev_priv->display.initial_watermarks(old_intel_state,
5725                                              pipe_config);
5726         intel_enable_pipe(intel_crtc);
5727
5728         assert_vblank_disabled(crtc);
5729         drm_crtc_vblank_on(crtc);
5730
5731         intel_encoders_enable(crtc, pipe_config, old_state);
5732 }
5733
5734 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5735 {
5736         struct drm_device *dev = crtc->base.dev;
5737         struct drm_i915_private *dev_priv = to_i915(dev);
5738
5739         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5740         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5741 }
5742
5743 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5744                              struct drm_atomic_state *old_state)
5745 {
5746         struct intel_atomic_state *old_intel_state =
5747                 to_intel_atomic_state(old_state);
5748         struct drm_crtc *crtc = pipe_config->base.crtc;
5749         struct drm_device *dev = crtc->dev;
5750         struct drm_i915_private *dev_priv = to_i915(dev);
5751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5752         enum pipe pipe = intel_crtc->pipe;
5753
5754         if (WARN_ON(intel_crtc->active))
5755                 return;
5756
5757         i9xx_set_pll_dividers(intel_crtc);
5758
5759         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5760                 intel_dp_set_m_n(intel_crtc, M1_N1);
5761
5762         intel_set_pipe_timings(intel_crtc);
5763         intel_set_pipe_src_size(intel_crtc);
5764
5765         i9xx_set_pipeconf(intel_crtc);
5766
5767         intel_crtc->active = true;
5768
5769         if (!IS_GEN2(dev_priv))
5770                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5771
5772         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5773
5774         i9xx_enable_pll(intel_crtc);
5775
5776         i9xx_pfit_enable(intel_crtc);
5777
5778         intel_color_load_luts(&pipe_config->base);
5779
5780         if (dev_priv->display.initial_watermarks != NULL)
5781                 dev_priv->display.initial_watermarks(old_intel_state,
5782                                                      intel_crtc->config);
5783         else
5784                 intel_update_watermarks(intel_crtc);
5785         intel_enable_pipe(intel_crtc);
5786
5787         assert_vblank_disabled(crtc);
5788         drm_crtc_vblank_on(crtc);
5789
5790         intel_encoders_enable(crtc, pipe_config, old_state);
5791 }
5792
5793 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5794 {
5795         struct drm_device *dev = crtc->base.dev;
5796         struct drm_i915_private *dev_priv = to_i915(dev);
5797
5798         if (!crtc->config->gmch_pfit.control)
5799                 return;
5800
5801         assert_pipe_disabled(dev_priv, crtc->pipe);
5802
5803         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5804                          I915_READ(PFIT_CONTROL));
5805         I915_WRITE(PFIT_CONTROL, 0);
5806 }
5807
5808 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5809                               struct drm_atomic_state *old_state)
5810 {
5811         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5812         struct drm_device *dev = crtc->dev;
5813         struct drm_i915_private *dev_priv = to_i915(dev);
5814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5815         int pipe = intel_crtc->pipe;
5816
5817         /*
5818          * On gen2 planes are double buffered but the pipe isn't, so we must
5819          * wait for planes to fully turn off before disabling the pipe.
5820          */
5821         if (IS_GEN2(dev_priv))
5822                 intel_wait_for_vblank(dev_priv, pipe);
5823
5824         intel_encoders_disable(crtc, old_crtc_state, old_state);
5825
5826         drm_crtc_vblank_off(crtc);
5827         assert_vblank_disabled(crtc);
5828
5829         intel_disable_pipe(intel_crtc);
5830
5831         i9xx_pfit_disable(intel_crtc);
5832
5833         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5834
5835         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5836                 if (IS_CHERRYVIEW(dev_priv))
5837                         chv_disable_pll(dev_priv, pipe);
5838                 else if (IS_VALLEYVIEW(dev_priv))
5839                         vlv_disable_pll(dev_priv, pipe);
5840                 else
5841                         i9xx_disable_pll(intel_crtc);
5842         }
5843
5844         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5845
5846         if (!IS_GEN2(dev_priv))
5847                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5848
5849         if (!dev_priv->display.initial_watermarks)
5850                 intel_update_watermarks(intel_crtc);
5851
5852         /* clock the pipe down to 640x480@60 to potentially save power */
5853         if (IS_I830(dev_priv))
5854                 i830_enable_pipe(dev_priv, pipe);
5855 }
5856
5857 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5858                                         struct drm_modeset_acquire_ctx *ctx)
5859 {
5860         struct intel_encoder *encoder;
5861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5862         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5863         enum intel_display_power_domain domain;
5864         u64 domains;
5865         struct drm_atomic_state *state;
5866         struct intel_crtc_state *crtc_state;
5867         int ret;
5868
5869         if (!intel_crtc->active)
5870                 return;
5871
5872         if (crtc->primary->state->visible) {
5873                 WARN_ON(intel_crtc->flip_work);
5874
5875                 intel_pre_disable_primary_noatomic(crtc);
5876
5877                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5878                 crtc->primary->state->visible = false;
5879         }
5880
5881         state = drm_atomic_state_alloc(crtc->dev);
5882         if (!state) {
5883                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5884                               crtc->base.id, crtc->name);
5885                 return;
5886         }
5887
5888         state->acquire_ctx = ctx;
5889
5890         /* Everything's already locked, -EDEADLK can't happen. */
5891         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5892         ret = drm_atomic_add_affected_connectors(state, crtc);
5893
5894         WARN_ON(IS_ERR(crtc_state) || ret);
5895
5896         dev_priv->display.crtc_disable(crtc_state, state);
5897
5898         drm_atomic_state_put(state);
5899
5900         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5901                       crtc->base.id, crtc->name);
5902
5903         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5904         crtc->state->active = false;
5905         intel_crtc->active = false;
5906         crtc->enabled = false;
5907         crtc->state->connector_mask = 0;
5908         crtc->state->encoder_mask = 0;
5909
5910         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5911                 encoder->base.crtc = NULL;
5912
5913         intel_fbc_disable(intel_crtc);
5914         intel_update_watermarks(intel_crtc);
5915         intel_disable_shared_dpll(intel_crtc);
5916
5917         domains = intel_crtc->enabled_power_domains;
5918         for_each_power_domain(domain, domains)
5919                 intel_display_power_put(dev_priv, domain);
5920         intel_crtc->enabled_power_domains = 0;
5921
5922         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5923         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5924 }
5925
5926 /*
5927  * turn all crtc's off, but do not adjust state
5928  * This has to be paired with a call to intel_modeset_setup_hw_state.
5929  */
5930 int intel_display_suspend(struct drm_device *dev)
5931 {
5932         struct drm_i915_private *dev_priv = to_i915(dev);
5933         struct drm_atomic_state *state;
5934         int ret;
5935
5936         state = drm_atomic_helper_suspend(dev);
5937         ret = PTR_ERR_OR_ZERO(state);
5938         if (ret)
5939                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5940         else
5941                 dev_priv->modeset_restore_state = state;
5942         return ret;
5943 }
5944
5945 void intel_encoder_destroy(struct drm_encoder *encoder)
5946 {
5947         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5948
5949         drm_encoder_cleanup(encoder);
5950         kfree(intel_encoder);
5951 }
5952
5953 /* Cross check the actual hw state with our own modeset state tracking (and it's
5954  * internal consistency). */
5955 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5956                                          struct drm_connector_state *conn_state)
5957 {
5958         struct intel_connector *connector = to_intel_connector(conn_state->connector);
5959
5960         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5961                       connector->base.base.id,
5962                       connector->base.name);
5963
5964         if (connector->get_hw_state(connector)) {
5965                 struct intel_encoder *encoder = connector->encoder;
5966
5967                 I915_STATE_WARN(!crtc_state,
5968                          "connector enabled without attached crtc\n");
5969
5970                 if (!crtc_state)
5971                         return;
5972
5973                 I915_STATE_WARN(!crtc_state->active,
5974                       "connector is active, but attached crtc isn't\n");
5975
5976                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5977                         return;
5978
5979                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5980                         "atomic encoder doesn't match attached encoder\n");
5981
5982                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5983                         "attached encoder crtc differs from connector crtc\n");
5984         } else {
5985                 I915_STATE_WARN(crtc_state && crtc_state->active,
5986                         "attached crtc is active, but connector isn't\n");
5987                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
5988                         "best encoder set without crtc!\n");
5989         }
5990 }
5991
5992 int intel_connector_init(struct intel_connector *connector)
5993 {
5994         struct intel_digital_connector_state *conn_state;
5995
5996         /*
5997          * Allocate enough memory to hold intel_digital_connector_state,
5998          * This might be a few bytes too many, but for connectors that don't
5999          * need it we'll free the state and allocate a smaller one on the first
6000          * succesful commit anyway.
6001          */
6002         conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6003         if (!conn_state)
6004                 return -ENOMEM;
6005
6006         __drm_atomic_helper_connector_reset(&connector->base,
6007                                             &conn_state->base);
6008
6009         return 0;
6010 }
6011
6012 struct intel_connector *intel_connector_alloc(void)
6013 {
6014         struct intel_connector *connector;
6015
6016         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6017         if (!connector)
6018                 return NULL;
6019
6020         if (intel_connector_init(connector) < 0) {
6021                 kfree(connector);
6022                 return NULL;
6023         }
6024
6025         return connector;
6026 }
6027
6028 /* Simple connector->get_hw_state implementation for encoders that support only
6029  * one connector and no cloning and hence the encoder state determines the state
6030  * of the connector. */
6031 bool intel_connector_get_hw_state(struct intel_connector *connector)
6032 {
6033         enum pipe pipe = 0;
6034         struct intel_encoder *encoder = connector->encoder;
6035
6036         return encoder->get_hw_state(encoder, &pipe);
6037 }
6038
6039 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6040 {
6041         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6042                 return crtc_state->fdi_lanes;
6043
6044         return 0;
6045 }
6046
6047 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6048                                      struct intel_crtc_state *pipe_config)
6049 {
6050         struct drm_i915_private *dev_priv = to_i915(dev);
6051         struct drm_atomic_state *state = pipe_config->base.state;
6052         struct intel_crtc *other_crtc;
6053         struct intel_crtc_state *other_crtc_state;
6054
6055         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6056                       pipe_name(pipe), pipe_config->fdi_lanes);
6057         if (pipe_config->fdi_lanes > 4) {
6058                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6059                               pipe_name(pipe), pipe_config->fdi_lanes);
6060                 return -EINVAL;
6061         }
6062
6063         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6064                 if (pipe_config->fdi_lanes > 2) {
6065                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6066                                       pipe_config->fdi_lanes);
6067                         return -EINVAL;
6068                 } else {
6069                         return 0;
6070                 }
6071         }
6072
6073         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6074                 return 0;
6075
6076         /* Ivybridge 3 pipe is really complicated */
6077         switch (pipe) {
6078         case PIPE_A:
6079                 return 0;
6080         case PIPE_B:
6081                 if (pipe_config->fdi_lanes <= 2)
6082                         return 0;
6083
6084                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6085                 other_crtc_state =
6086                         intel_atomic_get_crtc_state(state, other_crtc);
6087                 if (IS_ERR(other_crtc_state))
6088                         return PTR_ERR(other_crtc_state);
6089
6090                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6091                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6092                                       pipe_name(pipe), pipe_config->fdi_lanes);
6093                         return -EINVAL;
6094                 }
6095                 return 0;
6096         case PIPE_C:
6097                 if (pipe_config->fdi_lanes > 2) {
6098                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6099                                       pipe_name(pipe), pipe_config->fdi_lanes);
6100                         return -EINVAL;
6101                 }
6102
6103                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6104                 other_crtc_state =
6105                         intel_atomic_get_crtc_state(state, other_crtc);
6106                 if (IS_ERR(other_crtc_state))
6107                         return PTR_ERR(other_crtc_state);
6108
6109                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6110                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6111                         return -EINVAL;
6112                 }
6113                 return 0;
6114         default:
6115                 BUG();
6116         }
6117 }
6118
6119 #define RETRY 1
6120 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6121                                        struct intel_crtc_state *pipe_config)
6122 {
6123         struct drm_device *dev = intel_crtc->base.dev;
6124         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6125         int lane, link_bw, fdi_dotclock, ret;
6126         bool needs_recompute = false;
6127
6128 retry:
6129         /* FDI is a binary signal running at ~2.7GHz, encoding
6130          * each output octet as 10 bits. The actual frequency
6131          * is stored as a divider into a 100MHz clock, and the
6132          * mode pixel clock is stored in units of 1KHz.
6133          * Hence the bw of each lane in terms of the mode signal
6134          * is:
6135          */
6136         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6137
6138         fdi_dotclock = adjusted_mode->crtc_clock;
6139
6140         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6141                                            pipe_config->pipe_bpp);
6142
6143         pipe_config->fdi_lanes = lane;
6144
6145         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6146                                link_bw, &pipe_config->fdi_m_n, false);
6147
6148         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6149         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6150                 pipe_config->pipe_bpp -= 2*3;
6151                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6152                               pipe_config->pipe_bpp);
6153                 needs_recompute = true;
6154                 pipe_config->bw_constrained = true;
6155
6156                 goto retry;
6157         }
6158
6159         if (needs_recompute)
6160                 return RETRY;
6161
6162         return ret;
6163 }
6164
6165 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6166                                      struct intel_crtc_state *pipe_config)
6167 {
6168         if (pipe_config->pipe_bpp > 24)
6169                 return false;
6170
6171         /* HSW can handle pixel rate up to cdclk? */
6172         if (IS_HASWELL(dev_priv))
6173                 return true;
6174
6175         /*
6176          * We compare against max which means we must take
6177          * the increased cdclk requirement into account when
6178          * calculating the new cdclk.
6179          *
6180          * Should measure whether using a lower cdclk w/o IPS
6181          */
6182         return pipe_config->pixel_rate <=
6183                 dev_priv->max_cdclk_freq * 95 / 100;
6184 }
6185
6186 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6187                                    struct intel_crtc_state *pipe_config)
6188 {
6189         struct drm_device *dev = crtc->base.dev;
6190         struct drm_i915_private *dev_priv = to_i915(dev);
6191
6192         pipe_config->ips_enabled = i915.enable_ips &&
6193                 hsw_crtc_supports_ips(crtc) &&
6194                 pipe_config_supports_ips(dev_priv, pipe_config);
6195 }
6196
6197 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6198 {
6199         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6200
6201         /* GDG double wide on either pipe, otherwise pipe A only */
6202         return INTEL_INFO(dev_priv)->gen < 4 &&
6203                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6204 }
6205
6206 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6207 {
6208         uint32_t pixel_rate;
6209
6210         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6211
6212         /*
6213          * We only use IF-ID interlacing. If we ever use
6214          * PF-ID we'll need to adjust the pixel_rate here.
6215          */
6216
6217         if (pipe_config->pch_pfit.enabled) {
6218                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6219                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6220
6221                 pipe_w = pipe_config->pipe_src_w;
6222                 pipe_h = pipe_config->pipe_src_h;
6223
6224                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6225                 pfit_h = pfit_size & 0xFFFF;
6226                 if (pipe_w < pfit_w)
6227                         pipe_w = pfit_w;
6228                 if (pipe_h < pfit_h)
6229                         pipe_h = pfit_h;
6230
6231                 if (WARN_ON(!pfit_w || !pfit_h))
6232                         return pixel_rate;
6233
6234                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6235                                      pfit_w * pfit_h);
6236         }
6237
6238         return pixel_rate;
6239 }
6240
6241 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6242 {
6243         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6244
6245         if (HAS_GMCH_DISPLAY(dev_priv))
6246                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6247                 crtc_state->pixel_rate =
6248                         crtc_state->base.adjusted_mode.crtc_clock;
6249         else
6250                 crtc_state->pixel_rate =
6251                         ilk_pipe_pixel_rate(crtc_state);
6252 }
6253
6254 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6255                                      struct intel_crtc_state *pipe_config)
6256 {
6257         struct drm_device *dev = crtc->base.dev;
6258         struct drm_i915_private *dev_priv = to_i915(dev);
6259         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6260         int clock_limit = dev_priv->max_dotclk_freq;
6261
6262         if (INTEL_GEN(dev_priv) < 4) {
6263                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6264
6265                 /*
6266                  * Enable double wide mode when the dot clock
6267                  * is > 90% of the (display) core speed.
6268                  */
6269                 if (intel_crtc_supports_double_wide(crtc) &&
6270                     adjusted_mode->crtc_clock > clock_limit) {
6271                         clock_limit = dev_priv->max_dotclk_freq;
6272                         pipe_config->double_wide = true;
6273                 }
6274         }
6275
6276         if (adjusted_mode->crtc_clock > clock_limit) {
6277                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6278                               adjusted_mode->crtc_clock, clock_limit,
6279                               yesno(pipe_config->double_wide));
6280                 return -EINVAL;
6281         }
6282
6283         /*
6284          * Pipe horizontal size must be even in:
6285          * - DVO ganged mode
6286          * - LVDS dual channel mode
6287          * - Double wide pipe
6288          */
6289         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6290              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6291                 pipe_config->pipe_src_w &= ~1;
6292
6293         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6294          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6295          */
6296         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6297                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6298                 return -EINVAL;
6299
6300         intel_crtc_compute_pixel_rate(pipe_config);
6301
6302         if (HAS_IPS(dev_priv))
6303                 hsw_compute_ips_config(crtc, pipe_config);
6304
6305         if (pipe_config->has_pch_encoder)
6306                 return ironlake_fdi_compute_config(crtc, pipe_config);
6307
6308         return 0;
6309 }
6310
6311 static void
6312 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6313 {
6314         while (*num > DATA_LINK_M_N_MASK ||
6315                *den > DATA_LINK_M_N_MASK) {
6316                 *num >>= 1;
6317                 *den >>= 1;
6318         }
6319 }
6320
6321 static void compute_m_n(unsigned int m, unsigned int n,
6322                         uint32_t *ret_m, uint32_t *ret_n,
6323                         bool reduce_m_n)
6324 {
6325         /*
6326          * Reduce M/N as much as possible without loss in precision. Several DP
6327          * dongles in particular seem to be fussy about too large *link* M/N
6328          * values. The passed in values are more likely to have the least
6329          * significant bits zero than M after rounding below, so do this first.
6330          */
6331         if (reduce_m_n) {
6332                 while ((m & 1) == 0 && (n & 1) == 0) {
6333                         m >>= 1;
6334                         n >>= 1;
6335                 }
6336         }
6337
6338         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6339         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6340         intel_reduce_m_n_ratio(ret_m, ret_n);
6341 }
6342
6343 void
6344 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6345                        int pixel_clock, int link_clock,
6346                        struct intel_link_m_n *m_n,
6347                        bool reduce_m_n)
6348 {
6349         m_n->tu = 64;
6350
6351         compute_m_n(bits_per_pixel * pixel_clock,
6352                     link_clock * nlanes * 8,
6353                     &m_n->gmch_m, &m_n->gmch_n,
6354                     reduce_m_n);
6355
6356         compute_m_n(pixel_clock, link_clock,
6357                     &m_n->link_m, &m_n->link_n,
6358                     reduce_m_n);
6359 }
6360
6361 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6362 {
6363         if (i915.panel_use_ssc >= 0)
6364                 return i915.panel_use_ssc != 0;
6365         return dev_priv->vbt.lvds_use_ssc
6366                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6367 }
6368
6369 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6370 {
6371         return (1 << dpll->n) << 16 | dpll->m2;
6372 }
6373
6374 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6375 {
6376         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6377 }
6378
6379 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6380                                      struct intel_crtc_state *crtc_state,
6381                                      struct dpll *reduced_clock)
6382 {
6383         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6384         u32 fp, fp2 = 0;
6385
6386         if (IS_PINEVIEW(dev_priv)) {
6387                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6388                 if (reduced_clock)
6389                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6390         } else {
6391                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6392                 if (reduced_clock)
6393                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6394         }
6395
6396         crtc_state->dpll_hw_state.fp0 = fp;
6397
6398         crtc->lowfreq_avail = false;
6399         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6400             reduced_clock) {
6401                 crtc_state->dpll_hw_state.fp1 = fp2;
6402                 crtc->lowfreq_avail = true;
6403         } else {
6404                 crtc_state->dpll_hw_state.fp1 = fp;
6405         }
6406 }
6407
6408 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6409                 pipe)
6410 {
6411         u32 reg_val;
6412
6413         /*
6414          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6415          * and set it to a reasonable value instead.
6416          */
6417         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6418         reg_val &= 0xffffff00;
6419         reg_val |= 0x00000030;
6420         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6421
6422         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6423         reg_val &= 0x00ffffff;
6424         reg_val |= 0x8c000000;
6425         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6426
6427         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6428         reg_val &= 0xffffff00;
6429         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6430
6431         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6432         reg_val &= 0x00ffffff;
6433         reg_val |= 0xb0000000;
6434         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6435 }
6436
6437 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6438                                          struct intel_link_m_n *m_n)
6439 {
6440         struct drm_device *dev = crtc->base.dev;
6441         struct drm_i915_private *dev_priv = to_i915(dev);
6442         int pipe = crtc->pipe;
6443
6444         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6445         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6446         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6447         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6448 }
6449
6450 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6451                                          struct intel_link_m_n *m_n,
6452                                          struct intel_link_m_n *m2_n2)
6453 {
6454         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6455         int pipe = crtc->pipe;
6456         enum transcoder transcoder = crtc->config->cpu_transcoder;
6457
6458         if (INTEL_GEN(dev_priv) >= 5) {
6459                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6460                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6461                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6462                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6463                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6464                  * for gen < 8) and if DRRS is supported (to make sure the
6465                  * registers are not unnecessarily accessed).
6466                  */
6467                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6468                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6469                         I915_WRITE(PIPE_DATA_M2(transcoder),
6470                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6471                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6472                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6473                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6474                 }
6475         } else {
6476                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6477                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6478                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6479                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6480         }
6481 }
6482
6483 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6484 {
6485         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6486
6487         if (m_n == M1_N1) {
6488                 dp_m_n = &crtc->config->dp_m_n;
6489                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6490         } else if (m_n == M2_N2) {
6491
6492                 /*
6493                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6494                  * needs to be programmed into M1_N1.
6495                  */
6496                 dp_m_n = &crtc->config->dp_m2_n2;
6497         } else {
6498                 DRM_ERROR("Unsupported divider value\n");
6499                 return;
6500         }
6501
6502         if (crtc->config->has_pch_encoder)
6503                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6504         else
6505                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6506 }
6507
6508 static void vlv_compute_dpll(struct intel_crtc *crtc,
6509                              struct intel_crtc_state *pipe_config)
6510 {
6511         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6512                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6513         if (crtc->pipe != PIPE_A)
6514                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6515
6516         /* DPLL not used with DSI, but still need the rest set up */
6517         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6518                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6519                         DPLL_EXT_BUFFER_ENABLE_VLV;
6520
6521         pipe_config->dpll_hw_state.dpll_md =
6522                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6523 }
6524
6525 static void chv_compute_dpll(struct intel_crtc *crtc,
6526                              struct intel_crtc_state *pipe_config)
6527 {
6528         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6529                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6530         if (crtc->pipe != PIPE_A)
6531                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6532
6533         /* DPLL not used with DSI, but still need the rest set up */
6534         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6535                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6536
6537         pipe_config->dpll_hw_state.dpll_md =
6538                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6539 }
6540
6541 static void vlv_prepare_pll(struct intel_crtc *crtc,
6542                             const struct intel_crtc_state *pipe_config)
6543 {
6544         struct drm_device *dev = crtc->base.dev;
6545         struct drm_i915_private *dev_priv = to_i915(dev);
6546         enum pipe pipe = crtc->pipe;
6547         u32 mdiv;
6548         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6549         u32 coreclk, reg_val;
6550
6551         /* Enable Refclk */
6552         I915_WRITE(DPLL(pipe),
6553                    pipe_config->dpll_hw_state.dpll &
6554                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6555
6556         /* No need to actually set up the DPLL with DSI */
6557         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6558                 return;
6559
6560         mutex_lock(&dev_priv->sb_lock);
6561
6562         bestn = pipe_config->dpll.n;
6563         bestm1 = pipe_config->dpll.m1;
6564         bestm2 = pipe_config->dpll.m2;
6565         bestp1 = pipe_config->dpll.p1;
6566         bestp2 = pipe_config->dpll.p2;
6567
6568         /* See eDP HDMI DPIO driver vbios notes doc */
6569
6570         /* PLL B needs special handling */
6571         if (pipe == PIPE_B)
6572                 vlv_pllb_recal_opamp(dev_priv, pipe);
6573
6574         /* Set up Tx target for periodic Rcomp update */
6575         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6576
6577         /* Disable target IRef on PLL */
6578         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6579         reg_val &= 0x00ffffff;
6580         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6581
6582         /* Disable fast lock */
6583         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6584
6585         /* Set idtafcrecal before PLL is enabled */
6586         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6587         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6588         mdiv |= ((bestn << DPIO_N_SHIFT));
6589         mdiv |= (1 << DPIO_K_SHIFT);
6590
6591         /*
6592          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6593          * but we don't support that).
6594          * Note: don't use the DAC post divider as it seems unstable.
6595          */
6596         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6597         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6598
6599         mdiv |= DPIO_ENABLE_CALIBRATION;
6600         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6601
6602         /* Set HBR and RBR LPF coefficients */
6603         if (pipe_config->port_clock == 162000 ||
6604             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6605             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6606                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6607                                  0x009f0003);
6608         else
6609                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6610                                  0x00d0000f);
6611
6612         if (intel_crtc_has_dp_encoder(pipe_config)) {
6613                 /* Use SSC source */
6614                 if (pipe == PIPE_A)
6615                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6616                                          0x0df40000);
6617                 else
6618                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6619                                          0x0df70000);
6620         } else { /* HDMI or VGA */
6621                 /* Use bend source */
6622                 if (pipe == PIPE_A)
6623                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6624                                          0x0df70000);
6625                 else
6626                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6627                                          0x0df40000);
6628         }
6629
6630         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6631         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6632         if (intel_crtc_has_dp_encoder(crtc->config))
6633                 coreclk |= 0x01000000;
6634         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6635
6636         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6637         mutex_unlock(&dev_priv->sb_lock);
6638 }
6639
6640 static void chv_prepare_pll(struct intel_crtc *crtc,
6641                             const struct intel_crtc_state *pipe_config)
6642 {
6643         struct drm_device *dev = crtc->base.dev;
6644         struct drm_i915_private *dev_priv = to_i915(dev);
6645         enum pipe pipe = crtc->pipe;
6646         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6647         u32 loopfilter, tribuf_calcntr;
6648         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6649         u32 dpio_val;
6650         int vco;
6651
6652         /* Enable Refclk and SSC */
6653         I915_WRITE(DPLL(pipe),
6654                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6655
6656         /* No need to actually set up the DPLL with DSI */
6657         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6658                 return;
6659
6660         bestn = pipe_config->dpll.n;
6661         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6662         bestm1 = pipe_config->dpll.m1;
6663         bestm2 = pipe_config->dpll.m2 >> 22;
6664         bestp1 = pipe_config->dpll.p1;
6665         bestp2 = pipe_config->dpll.p2;
6666         vco = pipe_config->dpll.vco;
6667         dpio_val = 0;
6668         loopfilter = 0;
6669
6670         mutex_lock(&dev_priv->sb_lock);
6671
6672         /* p1 and p2 divider */
6673         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6674                         5 << DPIO_CHV_S1_DIV_SHIFT |
6675                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6676                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6677                         1 << DPIO_CHV_K_DIV_SHIFT);
6678
6679         /* Feedback post-divider - m2 */
6680         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6681
6682         /* Feedback refclk divider - n and m1 */
6683         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6684                         DPIO_CHV_M1_DIV_BY_2 |
6685                         1 << DPIO_CHV_N_DIV_SHIFT);
6686
6687         /* M2 fraction division */
6688         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6689
6690         /* M2 fraction division enable */
6691         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6692         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6693         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6694         if (bestm2_frac)
6695                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6696         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6697
6698         /* Program digital lock detect threshold */
6699         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6700         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6701                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6702         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6703         if (!bestm2_frac)
6704                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6705         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6706
6707         /* Loop filter */
6708         if (vco == 5400000) {
6709                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6710                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6711                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6712                 tribuf_calcntr = 0x9;
6713         } else if (vco <= 6200000) {
6714                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6715                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6716                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6717                 tribuf_calcntr = 0x9;
6718         } else if (vco <= 6480000) {
6719                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6720                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6721                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6722                 tribuf_calcntr = 0x8;
6723         } else {
6724                 /* Not supported. Apply the same limits as in the max case */
6725                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6726                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6727                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6728                 tribuf_calcntr = 0;
6729         }
6730         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6731
6732         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6733         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6734         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6735         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6736
6737         /* AFC Recal */
6738         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6739                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6740                         DPIO_AFC_RECAL);
6741
6742         mutex_unlock(&dev_priv->sb_lock);
6743 }
6744
6745 /**
6746  * vlv_force_pll_on - forcibly enable just the PLL
6747  * @dev_priv: i915 private structure
6748  * @pipe: pipe PLL to enable
6749  * @dpll: PLL configuration
6750  *
6751  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6752  * in cases where we need the PLL enabled even when @pipe is not going to
6753  * be enabled.
6754  */
6755 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6756                      const struct dpll *dpll)
6757 {
6758         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6759         struct intel_crtc_state *pipe_config;
6760
6761         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6762         if (!pipe_config)
6763                 return -ENOMEM;
6764
6765         pipe_config->base.crtc = &crtc->base;
6766         pipe_config->pixel_multiplier = 1;
6767         pipe_config->dpll = *dpll;
6768
6769         if (IS_CHERRYVIEW(dev_priv)) {
6770                 chv_compute_dpll(crtc, pipe_config);
6771                 chv_prepare_pll(crtc, pipe_config);
6772                 chv_enable_pll(crtc, pipe_config);
6773         } else {
6774                 vlv_compute_dpll(crtc, pipe_config);
6775                 vlv_prepare_pll(crtc, pipe_config);
6776                 vlv_enable_pll(crtc, pipe_config);
6777         }
6778
6779         kfree(pipe_config);
6780
6781         return 0;
6782 }
6783
6784 /**
6785  * vlv_force_pll_off - forcibly disable just the PLL
6786  * @dev_priv: i915 private structure
6787  * @pipe: pipe PLL to disable
6788  *
6789  * Disable the PLL for @pipe. To be used in cases where we need
6790  * the PLL enabled even when @pipe is not going to be enabled.
6791  */
6792 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6793 {
6794         if (IS_CHERRYVIEW(dev_priv))
6795                 chv_disable_pll(dev_priv, pipe);
6796         else
6797                 vlv_disable_pll(dev_priv, pipe);
6798 }
6799
6800 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6801                               struct intel_crtc_state *crtc_state,
6802                               struct dpll *reduced_clock)
6803 {
6804         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6805         u32 dpll;
6806         struct dpll *clock = &crtc_state->dpll;
6807
6808         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6809
6810         dpll = DPLL_VGA_MODE_DIS;
6811
6812         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6813                 dpll |= DPLLB_MODE_LVDS;
6814         else
6815                 dpll |= DPLLB_MODE_DAC_SERIAL;
6816
6817         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6818             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6819                 dpll |= (crtc_state->pixel_multiplier - 1)
6820                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6821         }
6822
6823         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6824             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6825                 dpll |= DPLL_SDVO_HIGH_SPEED;
6826
6827         if (intel_crtc_has_dp_encoder(crtc_state))
6828                 dpll |= DPLL_SDVO_HIGH_SPEED;
6829
6830         /* compute bitmask from p1 value */
6831         if (IS_PINEVIEW(dev_priv))
6832                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6833         else {
6834                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6835                 if (IS_G4X(dev_priv) && reduced_clock)
6836                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6837         }
6838         switch (clock->p2) {
6839         case 5:
6840                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6841                 break;
6842         case 7:
6843                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6844                 break;
6845         case 10:
6846                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6847                 break;
6848         case 14:
6849                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6850                 break;
6851         }
6852         if (INTEL_GEN(dev_priv) >= 4)
6853                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6854
6855         if (crtc_state->sdvo_tv_clock)
6856                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6857         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6858                  intel_panel_use_ssc(dev_priv))
6859                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6860         else
6861                 dpll |= PLL_REF_INPUT_DREFCLK;
6862
6863         dpll |= DPLL_VCO_ENABLE;
6864         crtc_state->dpll_hw_state.dpll = dpll;
6865
6866         if (INTEL_GEN(dev_priv) >= 4) {
6867                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6868                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6869                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6870         }
6871 }
6872
6873 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6874                               struct intel_crtc_state *crtc_state,
6875                               struct dpll *reduced_clock)
6876 {
6877         struct drm_device *dev = crtc->base.dev;
6878         struct drm_i915_private *dev_priv = to_i915(dev);
6879         u32 dpll;
6880         struct dpll *clock = &crtc_state->dpll;
6881
6882         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6883
6884         dpll = DPLL_VGA_MODE_DIS;
6885
6886         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6887                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6888         } else {
6889                 if (clock->p1 == 2)
6890                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6891                 else
6892                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6893                 if (clock->p2 == 4)
6894                         dpll |= PLL_P2_DIVIDE_BY_4;
6895         }
6896
6897         if (!IS_I830(dev_priv) &&
6898             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6899                 dpll |= DPLL_DVO_2X_MODE;
6900
6901         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6902             intel_panel_use_ssc(dev_priv))
6903                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6904         else
6905                 dpll |= PLL_REF_INPUT_DREFCLK;
6906
6907         dpll |= DPLL_VCO_ENABLE;
6908         crtc_state->dpll_hw_state.dpll = dpll;
6909 }
6910
6911 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6912 {
6913         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6914         enum pipe pipe = intel_crtc->pipe;
6915         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6916         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6917         uint32_t crtc_vtotal, crtc_vblank_end;
6918         int vsyncshift = 0;
6919
6920         /* We need to be careful not to changed the adjusted mode, for otherwise
6921          * the hw state checker will get angry at the mismatch. */
6922         crtc_vtotal = adjusted_mode->crtc_vtotal;
6923         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6924
6925         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6926                 /* the chip adds 2 halflines automatically */
6927                 crtc_vtotal -= 1;
6928                 crtc_vblank_end -= 1;
6929
6930                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6931                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6932                 else
6933                         vsyncshift = adjusted_mode->crtc_hsync_start -
6934                                 adjusted_mode->crtc_htotal / 2;
6935                 if (vsyncshift < 0)
6936                         vsyncshift += adjusted_mode->crtc_htotal;
6937         }
6938
6939         if (INTEL_GEN(dev_priv) > 3)
6940                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6941
6942         I915_WRITE(HTOTAL(cpu_transcoder),
6943                    (adjusted_mode->crtc_hdisplay - 1) |
6944                    ((adjusted_mode->crtc_htotal - 1) << 16));
6945         I915_WRITE(HBLANK(cpu_transcoder),
6946                    (adjusted_mode->crtc_hblank_start - 1) |
6947                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6948         I915_WRITE(HSYNC(cpu_transcoder),
6949                    (adjusted_mode->crtc_hsync_start - 1) |
6950                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6951
6952         I915_WRITE(VTOTAL(cpu_transcoder),
6953                    (adjusted_mode->crtc_vdisplay - 1) |
6954                    ((crtc_vtotal - 1) << 16));
6955         I915_WRITE(VBLANK(cpu_transcoder),
6956                    (adjusted_mode->crtc_vblank_start - 1) |
6957                    ((crtc_vblank_end - 1) << 16));
6958         I915_WRITE(VSYNC(cpu_transcoder),
6959                    (adjusted_mode->crtc_vsync_start - 1) |
6960                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6961
6962         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6963          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6964          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6965          * bits. */
6966         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6967             (pipe == PIPE_B || pipe == PIPE_C))
6968                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6969
6970 }
6971
6972 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6973 {
6974         struct drm_device *dev = intel_crtc->base.dev;
6975         struct drm_i915_private *dev_priv = to_i915(dev);
6976         enum pipe pipe = intel_crtc->pipe;
6977
6978         /* pipesrc controls the size that is scaled from, which should
6979          * always be the user's requested size.
6980          */
6981         I915_WRITE(PIPESRC(pipe),
6982                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6983                    (intel_crtc->config->pipe_src_h - 1));
6984 }
6985
6986 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6987                                    struct intel_crtc_state *pipe_config)
6988 {
6989         struct drm_device *dev = crtc->base.dev;
6990         struct drm_i915_private *dev_priv = to_i915(dev);
6991         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6992         uint32_t tmp;
6993
6994         tmp = I915_READ(HTOTAL(cpu_transcoder));
6995         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6996         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6997         tmp = I915_READ(HBLANK(cpu_transcoder));
6998         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6999         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7000         tmp = I915_READ(HSYNC(cpu_transcoder));
7001         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7002         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7003
7004         tmp = I915_READ(VTOTAL(cpu_transcoder));
7005         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7006         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7007         tmp = I915_READ(VBLANK(cpu_transcoder));
7008         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7009         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7010         tmp = I915_READ(VSYNC(cpu_transcoder));
7011         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7012         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7013
7014         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7015                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7016                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7017                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7018         }
7019 }
7020
7021 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7022                                     struct intel_crtc_state *pipe_config)
7023 {
7024         struct drm_device *dev = crtc->base.dev;
7025         struct drm_i915_private *dev_priv = to_i915(dev);
7026         u32 tmp;
7027
7028         tmp = I915_READ(PIPESRC(crtc->pipe));
7029         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7030         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7031
7032         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7033         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7034 }
7035
7036 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7037                                  struct intel_crtc_state *pipe_config)
7038 {
7039         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7040         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7041         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7042         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7043
7044         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7045         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7046         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7047         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7048
7049         mode->flags = pipe_config->base.adjusted_mode.flags;
7050         mode->type = DRM_MODE_TYPE_DRIVER;
7051
7052         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7053
7054         mode->hsync = drm_mode_hsync(mode);
7055         mode->vrefresh = drm_mode_vrefresh(mode);
7056         drm_mode_set_name(mode);
7057 }
7058
7059 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7060 {
7061         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7062         uint32_t pipeconf;
7063
7064         pipeconf = 0;
7065
7066         /* we keep both pipes enabled on 830 */
7067         if (IS_I830(dev_priv))
7068                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7069
7070         if (intel_crtc->config->double_wide)
7071                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7072
7073         /* only g4x and later have fancy bpc/dither controls */
7074         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7075             IS_CHERRYVIEW(dev_priv)) {
7076                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7077                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7078                         pipeconf |= PIPECONF_DITHER_EN |
7079                                     PIPECONF_DITHER_TYPE_SP;
7080
7081                 switch (intel_crtc->config->pipe_bpp) {
7082                 case 18:
7083                         pipeconf |= PIPECONF_6BPC;
7084                         break;
7085                 case 24:
7086                         pipeconf |= PIPECONF_8BPC;
7087                         break;
7088                 case 30:
7089                         pipeconf |= PIPECONF_10BPC;
7090                         break;
7091                 default:
7092                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7093                         BUG();
7094                 }
7095         }
7096
7097         if (HAS_PIPE_CXSR(dev_priv)) {
7098                 if (intel_crtc->lowfreq_avail) {
7099                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7100                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7101                 } else {
7102                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7103                 }
7104         }
7105
7106         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7107                 if (INTEL_GEN(dev_priv) < 4 ||
7108                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7109                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7110                 else
7111                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7112         } else
7113                 pipeconf |= PIPECONF_PROGRESSIVE;
7114
7115         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7116              intel_crtc->config->limited_color_range)
7117                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7118
7119         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7120         POSTING_READ(PIPECONF(intel_crtc->pipe));
7121 }
7122
7123 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7124                                    struct intel_crtc_state *crtc_state)
7125 {
7126         struct drm_device *dev = crtc->base.dev;
7127         struct drm_i915_private *dev_priv = to_i915(dev);
7128         const struct intel_limit *limit;
7129         int refclk = 48000;
7130
7131         memset(&crtc_state->dpll_hw_state, 0,
7132                sizeof(crtc_state->dpll_hw_state));
7133
7134         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7135                 if (intel_panel_use_ssc(dev_priv)) {
7136                         refclk = dev_priv->vbt.lvds_ssc_freq;
7137                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7138                 }
7139
7140                 limit = &intel_limits_i8xx_lvds;
7141         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7142                 limit = &intel_limits_i8xx_dvo;
7143         } else {
7144                 limit = &intel_limits_i8xx_dac;
7145         }
7146
7147         if (!crtc_state->clock_set &&
7148             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7149                                  refclk, NULL, &crtc_state->dpll)) {
7150                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7151                 return -EINVAL;
7152         }
7153
7154         i8xx_compute_dpll(crtc, crtc_state, NULL);
7155
7156         return 0;
7157 }
7158
7159 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7160                                   struct intel_crtc_state *crtc_state)
7161 {
7162         struct drm_device *dev = crtc->base.dev;
7163         struct drm_i915_private *dev_priv = to_i915(dev);
7164         const struct intel_limit *limit;
7165         int refclk = 96000;
7166
7167         memset(&crtc_state->dpll_hw_state, 0,
7168                sizeof(crtc_state->dpll_hw_state));
7169
7170         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7171                 if (intel_panel_use_ssc(dev_priv)) {
7172                         refclk = dev_priv->vbt.lvds_ssc_freq;
7173                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7174                 }
7175
7176                 if (intel_is_dual_link_lvds(dev))
7177                         limit = &intel_limits_g4x_dual_channel_lvds;
7178                 else
7179                         limit = &intel_limits_g4x_single_channel_lvds;
7180         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7181                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7182                 limit = &intel_limits_g4x_hdmi;
7183         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7184                 limit = &intel_limits_g4x_sdvo;
7185         } else {
7186                 /* The option is for other outputs */
7187                 limit = &intel_limits_i9xx_sdvo;
7188         }
7189
7190         if (!crtc_state->clock_set &&
7191             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7192                                 refclk, NULL, &crtc_state->dpll)) {
7193                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7194                 return -EINVAL;
7195         }
7196
7197         i9xx_compute_dpll(crtc, crtc_state, NULL);
7198
7199         return 0;
7200 }
7201
7202 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7203                                   struct intel_crtc_state *crtc_state)
7204 {
7205         struct drm_device *dev = crtc->base.dev;
7206         struct drm_i915_private *dev_priv = to_i915(dev);
7207         const struct intel_limit *limit;
7208         int refclk = 96000;
7209
7210         memset(&crtc_state->dpll_hw_state, 0,
7211                sizeof(crtc_state->dpll_hw_state));
7212
7213         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7214                 if (intel_panel_use_ssc(dev_priv)) {
7215                         refclk = dev_priv->vbt.lvds_ssc_freq;
7216                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7217                 }
7218
7219                 limit = &intel_limits_pineview_lvds;
7220         } else {
7221                 limit = &intel_limits_pineview_sdvo;
7222         }
7223
7224         if (!crtc_state->clock_set &&
7225             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7226                                 refclk, NULL, &crtc_state->dpll)) {
7227                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7228                 return -EINVAL;
7229         }
7230
7231         i9xx_compute_dpll(crtc, crtc_state, NULL);
7232
7233         return 0;
7234 }
7235
7236 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7237                                    struct intel_crtc_state *crtc_state)
7238 {
7239         struct drm_device *dev = crtc->base.dev;
7240         struct drm_i915_private *dev_priv = to_i915(dev);
7241         const struct intel_limit *limit;
7242         int refclk = 96000;
7243
7244         memset(&crtc_state->dpll_hw_state, 0,
7245                sizeof(crtc_state->dpll_hw_state));
7246
7247         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7248                 if (intel_panel_use_ssc(dev_priv)) {
7249                         refclk = dev_priv->vbt.lvds_ssc_freq;
7250                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7251                 }
7252
7253                 limit = &intel_limits_i9xx_lvds;
7254         } else {
7255                 limit = &intel_limits_i9xx_sdvo;
7256         }
7257
7258         if (!crtc_state->clock_set &&
7259             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7260                                  refclk, NULL, &crtc_state->dpll)) {
7261                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7262                 return -EINVAL;
7263         }
7264
7265         i9xx_compute_dpll(crtc, crtc_state, NULL);
7266
7267         return 0;
7268 }
7269
7270 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7271                                   struct intel_crtc_state *crtc_state)
7272 {
7273         int refclk = 100000;
7274         const struct intel_limit *limit = &intel_limits_chv;
7275
7276         memset(&crtc_state->dpll_hw_state, 0,
7277                sizeof(crtc_state->dpll_hw_state));
7278
7279         if (!crtc_state->clock_set &&
7280             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7281                                 refclk, NULL, &crtc_state->dpll)) {
7282                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7283                 return -EINVAL;
7284         }
7285
7286         chv_compute_dpll(crtc, crtc_state);
7287
7288         return 0;
7289 }
7290
7291 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7292                                   struct intel_crtc_state *crtc_state)
7293 {
7294         int refclk = 100000;
7295         const struct intel_limit *limit = &intel_limits_vlv;
7296
7297         memset(&crtc_state->dpll_hw_state, 0,
7298                sizeof(crtc_state->dpll_hw_state));
7299
7300         if (!crtc_state->clock_set &&
7301             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7302                                 refclk, NULL, &crtc_state->dpll)) {
7303                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7304                 return -EINVAL;
7305         }
7306
7307         vlv_compute_dpll(crtc, crtc_state);
7308
7309         return 0;
7310 }
7311
7312 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7313                                  struct intel_crtc_state *pipe_config)
7314 {
7315         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7316         uint32_t tmp;
7317
7318         if (INTEL_GEN(dev_priv) <= 3 &&
7319             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7320                 return;
7321
7322         tmp = I915_READ(PFIT_CONTROL);
7323         if (!(tmp & PFIT_ENABLE))
7324                 return;
7325
7326         /* Check whether the pfit is attached to our pipe. */
7327         if (INTEL_GEN(dev_priv) < 4) {
7328                 if (crtc->pipe != PIPE_B)
7329                         return;
7330         } else {
7331                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7332                         return;
7333         }
7334
7335         pipe_config->gmch_pfit.control = tmp;
7336         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7337 }
7338
7339 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7340                                struct intel_crtc_state *pipe_config)
7341 {
7342         struct drm_device *dev = crtc->base.dev;
7343         struct drm_i915_private *dev_priv = to_i915(dev);
7344         int pipe = pipe_config->cpu_transcoder;
7345         struct dpll clock;
7346         u32 mdiv;
7347         int refclk = 100000;
7348
7349         /* In case of DSI, DPLL will not be used */
7350         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7351                 return;
7352
7353         mutex_lock(&dev_priv->sb_lock);
7354         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7355         mutex_unlock(&dev_priv->sb_lock);
7356
7357         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7358         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7359         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7360         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7361         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7362
7363         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7364 }
7365
7366 static void
7367 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7368                               struct intel_initial_plane_config *plane_config)
7369 {
7370         struct drm_device *dev = crtc->base.dev;
7371         struct drm_i915_private *dev_priv = to_i915(dev);
7372         u32 val, base, offset;
7373         int pipe = crtc->pipe, plane = crtc->plane;
7374         int fourcc, pixel_format;
7375         unsigned int aligned_height;
7376         struct drm_framebuffer *fb;
7377         struct intel_framebuffer *intel_fb;
7378
7379         val = I915_READ(DSPCNTR(plane));
7380         if (!(val & DISPLAY_PLANE_ENABLE))
7381                 return;
7382
7383         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7384         if (!intel_fb) {
7385                 DRM_DEBUG_KMS("failed to alloc fb\n");
7386                 return;
7387         }
7388
7389         fb = &intel_fb->base;
7390
7391         fb->dev = dev;
7392
7393         if (INTEL_GEN(dev_priv) >= 4) {
7394                 if (val & DISPPLANE_TILED) {
7395                         plane_config->tiling = I915_TILING_X;
7396                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7397                 }
7398         }
7399
7400         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7401         fourcc = i9xx_format_to_fourcc(pixel_format);
7402         fb->format = drm_format_info(fourcc);
7403
7404         if (INTEL_GEN(dev_priv) >= 4) {
7405                 if (plane_config->tiling)
7406                         offset = I915_READ(DSPTILEOFF(plane));
7407                 else
7408                         offset = I915_READ(DSPLINOFF(plane));
7409                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7410         } else {
7411                 base = I915_READ(DSPADDR(plane));
7412         }
7413         plane_config->base = base;
7414
7415         val = I915_READ(PIPESRC(pipe));
7416         fb->width = ((val >> 16) & 0xfff) + 1;
7417         fb->height = ((val >> 0) & 0xfff) + 1;
7418
7419         val = I915_READ(DSPSTRIDE(pipe));
7420         fb->pitches[0] = val & 0xffffffc0;
7421
7422         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7423
7424         plane_config->size = fb->pitches[0] * aligned_height;
7425
7426         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7427                       pipe_name(pipe), plane, fb->width, fb->height,
7428                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7429                       plane_config->size);
7430
7431         plane_config->fb = intel_fb;
7432 }
7433
7434 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7435                                struct intel_crtc_state *pipe_config)
7436 {
7437         struct drm_device *dev = crtc->base.dev;
7438         struct drm_i915_private *dev_priv = to_i915(dev);
7439         int pipe = pipe_config->cpu_transcoder;
7440         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7441         struct dpll clock;
7442         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7443         int refclk = 100000;
7444
7445         /* In case of DSI, DPLL will not be used */
7446         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7447                 return;
7448
7449         mutex_lock(&dev_priv->sb_lock);
7450         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7451         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7452         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7453         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7454         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7455         mutex_unlock(&dev_priv->sb_lock);
7456
7457         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7458         clock.m2 = (pll_dw0 & 0xff) << 22;
7459         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7460                 clock.m2 |= pll_dw2 & 0x3fffff;
7461         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7462         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7463         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7464
7465         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7466 }
7467
7468 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7469                                  struct intel_crtc_state *pipe_config)
7470 {
7471         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7472         enum intel_display_power_domain power_domain;
7473         uint32_t tmp;
7474         bool ret;
7475
7476         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7477         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7478                 return false;
7479
7480         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7481         pipe_config->shared_dpll = NULL;
7482
7483         ret = false;
7484
7485         tmp = I915_READ(PIPECONF(crtc->pipe));
7486         if (!(tmp & PIPECONF_ENABLE))
7487                 goto out;
7488
7489         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7490             IS_CHERRYVIEW(dev_priv)) {
7491                 switch (tmp & PIPECONF_BPC_MASK) {
7492                 case PIPECONF_6BPC:
7493                         pipe_config->pipe_bpp = 18;
7494                         break;
7495                 case PIPECONF_8BPC:
7496                         pipe_config->pipe_bpp = 24;
7497                         break;
7498                 case PIPECONF_10BPC:
7499                         pipe_config->pipe_bpp = 30;
7500                         break;
7501                 default:
7502                         break;
7503                 }
7504         }
7505
7506         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7507             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7508                 pipe_config->limited_color_range = true;
7509
7510         if (INTEL_GEN(dev_priv) < 4)
7511                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7512
7513         intel_get_pipe_timings(crtc, pipe_config);
7514         intel_get_pipe_src_size(crtc, pipe_config);
7515
7516         i9xx_get_pfit_config(crtc, pipe_config);
7517
7518         if (INTEL_GEN(dev_priv) >= 4) {
7519                 /* No way to read it out on pipes B and C */
7520                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7521                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7522                 else
7523                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7524                 pipe_config->pixel_multiplier =
7525                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7526                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7527                 pipe_config->dpll_hw_state.dpll_md = tmp;
7528         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7529                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7530                 tmp = I915_READ(DPLL(crtc->pipe));
7531                 pipe_config->pixel_multiplier =
7532                         ((tmp & SDVO_MULTIPLIER_MASK)
7533                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7534         } else {
7535                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7536                  * port and will be fixed up in the encoder->get_config
7537                  * function. */
7538                 pipe_config->pixel_multiplier = 1;
7539         }
7540         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7541         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7542                 /*
7543                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7544                  * on 830. Filter it out here so that we don't
7545                  * report errors due to that.
7546                  */
7547                 if (IS_I830(dev_priv))
7548                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7549
7550                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7551                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7552         } else {
7553                 /* Mask out read-only status bits. */
7554                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7555                                                      DPLL_PORTC_READY_MASK |
7556                                                      DPLL_PORTB_READY_MASK);
7557         }
7558
7559         if (IS_CHERRYVIEW(dev_priv))
7560                 chv_crtc_clock_get(crtc, pipe_config);
7561         else if (IS_VALLEYVIEW(dev_priv))
7562                 vlv_crtc_clock_get(crtc, pipe_config);
7563         else
7564                 i9xx_crtc_clock_get(crtc, pipe_config);
7565
7566         /*
7567          * Normally the dotclock is filled in by the encoder .get_config()
7568          * but in case the pipe is enabled w/o any ports we need a sane
7569          * default.
7570          */
7571         pipe_config->base.adjusted_mode.crtc_clock =
7572                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7573
7574         ret = true;
7575
7576 out:
7577         intel_display_power_put(dev_priv, power_domain);
7578
7579         return ret;
7580 }
7581
7582 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7583 {
7584         struct intel_encoder *encoder;
7585         int i;
7586         u32 val, final;
7587         bool has_lvds = false;
7588         bool has_cpu_edp = false;
7589         bool has_panel = false;
7590         bool has_ck505 = false;
7591         bool can_ssc = false;
7592         bool using_ssc_source = false;
7593
7594         /* We need to take the global config into account */
7595         for_each_intel_encoder(&dev_priv->drm, encoder) {
7596                 switch (encoder->type) {
7597                 case INTEL_OUTPUT_LVDS:
7598                         has_panel = true;
7599                         has_lvds = true;
7600                         break;
7601                 case INTEL_OUTPUT_EDP:
7602                         has_panel = true;
7603                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7604                                 has_cpu_edp = true;
7605                         break;
7606                 default:
7607                         break;
7608                 }
7609         }
7610
7611         if (HAS_PCH_IBX(dev_priv)) {
7612                 has_ck505 = dev_priv->vbt.display_clock_mode;
7613                 can_ssc = has_ck505;
7614         } else {
7615                 has_ck505 = false;
7616                 can_ssc = true;
7617         }
7618
7619         /* Check if any DPLLs are using the SSC source */
7620         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7621                 u32 temp = I915_READ(PCH_DPLL(i));
7622
7623                 if (!(temp & DPLL_VCO_ENABLE))
7624                         continue;
7625
7626                 if ((temp & PLL_REF_INPUT_MASK) ==
7627                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7628                         using_ssc_source = true;
7629                         break;
7630                 }
7631         }
7632
7633         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7634                       has_panel, has_lvds, has_ck505, using_ssc_source);
7635
7636         /* Ironlake: try to setup display ref clock before DPLL
7637          * enabling. This is only under driver's control after
7638          * PCH B stepping, previous chipset stepping should be
7639          * ignoring this setting.
7640          */
7641         val = I915_READ(PCH_DREF_CONTROL);
7642
7643         /* As we must carefully and slowly disable/enable each source in turn,
7644          * compute the final state we want first and check if we need to
7645          * make any changes at all.
7646          */
7647         final = val;
7648         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7649         if (has_ck505)
7650                 final |= DREF_NONSPREAD_CK505_ENABLE;
7651         else
7652                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7653
7654         final &= ~DREF_SSC_SOURCE_MASK;
7655         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7656         final &= ~DREF_SSC1_ENABLE;
7657
7658         if (has_panel) {
7659                 final |= DREF_SSC_SOURCE_ENABLE;
7660
7661                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7662                         final |= DREF_SSC1_ENABLE;
7663
7664                 if (has_cpu_edp) {
7665                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7666                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7667                         else
7668                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7669                 } else
7670                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7671         } else if (using_ssc_source) {
7672                 final |= DREF_SSC_SOURCE_ENABLE;
7673                 final |= DREF_SSC1_ENABLE;
7674         }
7675
7676         if (final == val)
7677                 return;
7678
7679         /* Always enable nonspread source */
7680         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7681
7682         if (has_ck505)
7683                 val |= DREF_NONSPREAD_CK505_ENABLE;
7684         else
7685                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7686
7687         if (has_panel) {
7688                 val &= ~DREF_SSC_SOURCE_MASK;
7689                 val |= DREF_SSC_SOURCE_ENABLE;
7690
7691                 /* SSC must be turned on before enabling the CPU output  */
7692                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7693                         DRM_DEBUG_KMS("Using SSC on panel\n");
7694                         val |= DREF_SSC1_ENABLE;
7695                 } else
7696                         val &= ~DREF_SSC1_ENABLE;
7697
7698                 /* Get SSC going before enabling the outputs */
7699                 I915_WRITE(PCH_DREF_CONTROL, val);
7700                 POSTING_READ(PCH_DREF_CONTROL);
7701                 udelay(200);
7702
7703                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7704
7705                 /* Enable CPU source on CPU attached eDP */
7706                 if (has_cpu_edp) {
7707                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7708                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7709                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7710                         } else
7711                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7712                 } else
7713                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7714
7715                 I915_WRITE(PCH_DREF_CONTROL, val);
7716                 POSTING_READ(PCH_DREF_CONTROL);
7717                 udelay(200);
7718         } else {
7719                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7720
7721                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7722
7723                 /* Turn off CPU output */
7724                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7725
7726                 I915_WRITE(PCH_DREF_CONTROL, val);
7727                 POSTING_READ(PCH_DREF_CONTROL);
7728                 udelay(200);
7729
7730                 if (!using_ssc_source) {
7731                         DRM_DEBUG_KMS("Disabling SSC source\n");
7732
7733                         /* Turn off the SSC source */
7734                         val &= ~DREF_SSC_SOURCE_MASK;
7735                         val |= DREF_SSC_SOURCE_DISABLE;
7736
7737                         /* Turn off SSC1 */
7738                         val &= ~DREF_SSC1_ENABLE;
7739
7740                         I915_WRITE(PCH_DREF_CONTROL, val);
7741                         POSTING_READ(PCH_DREF_CONTROL);
7742                         udelay(200);
7743                 }
7744         }
7745
7746         BUG_ON(val != final);
7747 }
7748
7749 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7750 {
7751         uint32_t tmp;
7752
7753         tmp = I915_READ(SOUTH_CHICKEN2);
7754         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7755         I915_WRITE(SOUTH_CHICKEN2, tmp);
7756
7757         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7758                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7759                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7760
7761         tmp = I915_READ(SOUTH_CHICKEN2);
7762         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7763         I915_WRITE(SOUTH_CHICKEN2, tmp);
7764
7765         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7766                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7767                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7768 }
7769
7770 /* WaMPhyProgramming:hsw */
7771 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7772 {
7773         uint32_t tmp;
7774
7775         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7776         tmp &= ~(0xFF << 24);
7777         tmp |= (0x12 << 24);
7778         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7779
7780         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7781         tmp |= (1 << 11);
7782         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7783
7784         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7785         tmp |= (1 << 11);
7786         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7787
7788         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7789         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7790         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7791
7792         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7793         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7794         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7795
7796         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7797         tmp &= ~(7 << 13);
7798         tmp |= (5 << 13);
7799         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7800
7801         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7802         tmp &= ~(7 << 13);
7803         tmp |= (5 << 13);
7804         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7805
7806         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7807         tmp &= ~0xFF;
7808         tmp |= 0x1C;
7809         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7810
7811         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7812         tmp &= ~0xFF;
7813         tmp |= 0x1C;
7814         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7815
7816         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7817         tmp &= ~(0xFF << 16);
7818         tmp |= (0x1C << 16);
7819         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7820
7821         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7822         tmp &= ~(0xFF << 16);
7823         tmp |= (0x1C << 16);
7824         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7825
7826         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7827         tmp |= (1 << 27);
7828         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7829
7830         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7831         tmp |= (1 << 27);
7832         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7833
7834         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7835         tmp &= ~(0xF << 28);
7836         tmp |= (4 << 28);
7837         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7838
7839         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7840         tmp &= ~(0xF << 28);
7841         tmp |= (4 << 28);
7842         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7843 }
7844
7845 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7846  * Programming" based on the parameters passed:
7847  * - Sequence to enable CLKOUT_DP
7848  * - Sequence to enable CLKOUT_DP without spread
7849  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7850  */
7851 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7852                                  bool with_spread, bool with_fdi)
7853 {
7854         uint32_t reg, tmp;
7855
7856         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7857                 with_spread = true;
7858         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7859             with_fdi, "LP PCH doesn't have FDI\n"))
7860                 with_fdi = false;
7861
7862         mutex_lock(&dev_priv->sb_lock);
7863
7864         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7865         tmp &= ~SBI_SSCCTL_DISABLE;
7866         tmp |= SBI_SSCCTL_PATHALT;
7867         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7868
7869         udelay(24);
7870
7871         if (with_spread) {
7872                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7873                 tmp &= ~SBI_SSCCTL_PATHALT;
7874                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7875
7876                 if (with_fdi) {
7877                         lpt_reset_fdi_mphy(dev_priv);
7878                         lpt_program_fdi_mphy(dev_priv);
7879                 }
7880         }
7881
7882         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7883         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7884         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7885         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7886
7887         mutex_unlock(&dev_priv->sb_lock);
7888 }
7889
7890 /* Sequence to disable CLKOUT_DP */
7891 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7892 {
7893         uint32_t reg, tmp;
7894
7895         mutex_lock(&dev_priv->sb_lock);
7896
7897         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7898         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7899         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7900         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7901
7902         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7903         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7904                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7905                         tmp |= SBI_SSCCTL_PATHALT;
7906                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7907                         udelay(32);
7908                 }
7909                 tmp |= SBI_SSCCTL_DISABLE;
7910                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7911         }
7912
7913         mutex_unlock(&dev_priv->sb_lock);
7914 }
7915
7916 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7917
7918 static const uint16_t sscdivintphase[] = {
7919         [BEND_IDX( 50)] = 0x3B23,
7920         [BEND_IDX( 45)] = 0x3B23,
7921         [BEND_IDX( 40)] = 0x3C23,
7922         [BEND_IDX( 35)] = 0x3C23,
7923         [BEND_IDX( 30)] = 0x3D23,
7924         [BEND_IDX( 25)] = 0x3D23,
7925         [BEND_IDX( 20)] = 0x3E23,
7926         [BEND_IDX( 15)] = 0x3E23,
7927         [BEND_IDX( 10)] = 0x3F23,
7928         [BEND_IDX(  5)] = 0x3F23,
7929         [BEND_IDX(  0)] = 0x0025,
7930         [BEND_IDX( -5)] = 0x0025,
7931         [BEND_IDX(-10)] = 0x0125,
7932         [BEND_IDX(-15)] = 0x0125,
7933         [BEND_IDX(-20)] = 0x0225,
7934         [BEND_IDX(-25)] = 0x0225,
7935         [BEND_IDX(-30)] = 0x0325,
7936         [BEND_IDX(-35)] = 0x0325,
7937         [BEND_IDX(-40)] = 0x0425,
7938         [BEND_IDX(-45)] = 0x0425,
7939         [BEND_IDX(-50)] = 0x0525,
7940 };
7941
7942 /*
7943  * Bend CLKOUT_DP
7944  * steps -50 to 50 inclusive, in steps of 5
7945  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7946  * change in clock period = -(steps / 10) * 5.787 ps
7947  */
7948 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7949 {
7950         uint32_t tmp;
7951         int idx = BEND_IDX(steps);
7952
7953         if (WARN_ON(steps % 5 != 0))
7954                 return;
7955
7956         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7957                 return;
7958
7959         mutex_lock(&dev_priv->sb_lock);
7960
7961         if (steps % 10 != 0)
7962                 tmp = 0xAAAAAAAB;
7963         else
7964                 tmp = 0x00000000;
7965         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7966
7967         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7968         tmp &= 0xffff0000;
7969         tmp |= sscdivintphase[idx];
7970         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7971
7972         mutex_unlock(&dev_priv->sb_lock);
7973 }
7974
7975 #undef BEND_IDX
7976
7977 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7978 {
7979         struct intel_encoder *encoder;
7980         bool has_vga = false;
7981
7982         for_each_intel_encoder(&dev_priv->drm, encoder) {
7983                 switch (encoder->type) {
7984                 case INTEL_OUTPUT_ANALOG:
7985                         has_vga = true;
7986                         break;
7987                 default:
7988                         break;
7989                 }
7990         }
7991
7992         if (has_vga) {
7993                 lpt_bend_clkout_dp(dev_priv, 0);
7994                 lpt_enable_clkout_dp(dev_priv, true, true);
7995         } else {
7996                 lpt_disable_clkout_dp(dev_priv);
7997         }
7998 }
7999
8000 /*
8001  * Initialize reference clocks when the driver loads
8002  */
8003 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8004 {
8005         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8006                 ironlake_init_pch_refclk(dev_priv);
8007         else if (HAS_PCH_LPT(dev_priv))
8008                 lpt_init_pch_refclk(dev_priv);
8009 }
8010
8011 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8012 {
8013         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8015         int pipe = intel_crtc->pipe;
8016         uint32_t val;
8017
8018         val = 0;
8019
8020         switch (intel_crtc->config->pipe_bpp) {
8021         case 18:
8022                 val |= PIPECONF_6BPC;
8023                 break;
8024         case 24:
8025                 val |= PIPECONF_8BPC;
8026                 break;
8027         case 30:
8028                 val |= PIPECONF_10BPC;
8029                 break;
8030         case 36:
8031                 val |= PIPECONF_12BPC;
8032                 break;
8033         default:
8034                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8035                 BUG();
8036         }
8037
8038         if (intel_crtc->config->dither)
8039                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8040
8041         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8042                 val |= PIPECONF_INTERLACED_ILK;
8043         else
8044                 val |= PIPECONF_PROGRESSIVE;
8045
8046         if (intel_crtc->config->limited_color_range)
8047                 val |= PIPECONF_COLOR_RANGE_SELECT;
8048
8049         I915_WRITE(PIPECONF(pipe), val);
8050         POSTING_READ(PIPECONF(pipe));
8051 }
8052
8053 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8054 {
8055         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8057         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8058         u32 val = 0;
8059
8060         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8061                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8062
8063         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8064                 val |= PIPECONF_INTERLACED_ILK;
8065         else
8066                 val |= PIPECONF_PROGRESSIVE;
8067
8068         I915_WRITE(PIPECONF(cpu_transcoder), val);
8069         POSTING_READ(PIPECONF(cpu_transcoder));
8070 }
8071
8072 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8073 {
8074         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8076
8077         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8078                 u32 val = 0;
8079
8080                 switch (intel_crtc->config->pipe_bpp) {
8081                 case 18:
8082                         val |= PIPEMISC_DITHER_6_BPC;
8083                         break;
8084                 case 24:
8085                         val |= PIPEMISC_DITHER_8_BPC;
8086                         break;
8087                 case 30:
8088                         val |= PIPEMISC_DITHER_10_BPC;
8089                         break;
8090                 case 36:
8091                         val |= PIPEMISC_DITHER_12_BPC;
8092                         break;
8093                 default:
8094                         /* Case prevented by pipe_config_set_bpp. */
8095                         BUG();
8096                 }
8097
8098                 if (intel_crtc->config->dither)
8099                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8100
8101                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8102         }
8103 }
8104
8105 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8106 {
8107         /*
8108          * Account for spread spectrum to avoid
8109          * oversubscribing the link. Max center spread
8110          * is 2.5%; use 5% for safety's sake.
8111          */
8112         u32 bps = target_clock * bpp * 21 / 20;
8113         return DIV_ROUND_UP(bps, link_bw * 8);
8114 }
8115
8116 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8117 {
8118         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8119 }
8120
8121 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8122                                   struct intel_crtc_state *crtc_state,
8123                                   struct dpll *reduced_clock)
8124 {
8125         struct drm_crtc *crtc = &intel_crtc->base;
8126         struct drm_device *dev = crtc->dev;
8127         struct drm_i915_private *dev_priv = to_i915(dev);
8128         u32 dpll, fp, fp2;
8129         int factor;
8130
8131         /* Enable autotuning of the PLL clock (if permissible) */
8132         factor = 21;
8133         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8134                 if ((intel_panel_use_ssc(dev_priv) &&
8135                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8136                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8137                         factor = 25;
8138         } else if (crtc_state->sdvo_tv_clock)
8139                 factor = 20;
8140
8141         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8142
8143         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8144                 fp |= FP_CB_TUNE;
8145
8146         if (reduced_clock) {
8147                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8148
8149                 if (reduced_clock->m < factor * reduced_clock->n)
8150                         fp2 |= FP_CB_TUNE;
8151         } else {
8152                 fp2 = fp;
8153         }
8154
8155         dpll = 0;
8156
8157         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8158                 dpll |= DPLLB_MODE_LVDS;
8159         else
8160                 dpll |= DPLLB_MODE_DAC_SERIAL;
8161
8162         dpll |= (crtc_state->pixel_multiplier - 1)
8163                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8164
8165         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8166             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8167                 dpll |= DPLL_SDVO_HIGH_SPEED;
8168
8169         if (intel_crtc_has_dp_encoder(crtc_state))
8170                 dpll |= DPLL_SDVO_HIGH_SPEED;
8171
8172         /*
8173          * The high speed IO clock is only really required for
8174          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8175          * possible to share the DPLL between CRT and HDMI. Enabling
8176          * the clock needlessly does no real harm, except use up a
8177          * bit of power potentially.
8178          *
8179          * We'll limit this to IVB with 3 pipes, since it has only two
8180          * DPLLs and so DPLL sharing is the only way to get three pipes
8181          * driving PCH ports at the same time. On SNB we could do this,
8182          * and potentially avoid enabling the second DPLL, but it's not
8183          * clear if it''s a win or loss power wise. No point in doing
8184          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8185          */
8186         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8187             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8188                 dpll |= DPLL_SDVO_HIGH_SPEED;
8189
8190         /* compute bitmask from p1 value */
8191         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8192         /* also FPA1 */
8193         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8194
8195         switch (crtc_state->dpll.p2) {
8196         case 5:
8197                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8198                 break;
8199         case 7:
8200                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8201                 break;
8202         case 10:
8203                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8204                 break;
8205         case 14:
8206                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8207                 break;
8208         }
8209
8210         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8211             intel_panel_use_ssc(dev_priv))
8212                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8213         else
8214                 dpll |= PLL_REF_INPUT_DREFCLK;
8215
8216         dpll |= DPLL_VCO_ENABLE;
8217
8218         crtc_state->dpll_hw_state.dpll = dpll;
8219         crtc_state->dpll_hw_state.fp0 = fp;
8220         crtc_state->dpll_hw_state.fp1 = fp2;
8221 }
8222
8223 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8224                                        struct intel_crtc_state *crtc_state)
8225 {
8226         struct drm_device *dev = crtc->base.dev;
8227         struct drm_i915_private *dev_priv = to_i915(dev);
8228         const struct intel_limit *limit;
8229         int refclk = 120000;
8230
8231         memset(&crtc_state->dpll_hw_state, 0,
8232                sizeof(crtc_state->dpll_hw_state));
8233
8234         crtc->lowfreq_avail = false;
8235
8236         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8237         if (!crtc_state->has_pch_encoder)
8238                 return 0;
8239
8240         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8241                 if (intel_panel_use_ssc(dev_priv)) {
8242                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8243                                       dev_priv->vbt.lvds_ssc_freq);
8244                         refclk = dev_priv->vbt.lvds_ssc_freq;
8245                 }
8246
8247                 if (intel_is_dual_link_lvds(dev)) {
8248                         if (refclk == 100000)
8249                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8250                         else
8251                                 limit = &intel_limits_ironlake_dual_lvds;
8252                 } else {
8253                         if (refclk == 100000)
8254                                 limit = &intel_limits_ironlake_single_lvds_100m;
8255                         else
8256                                 limit = &intel_limits_ironlake_single_lvds;
8257                 }
8258         } else {
8259                 limit = &intel_limits_ironlake_dac;
8260         }
8261
8262         if (!crtc_state->clock_set &&
8263             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8264                                 refclk, NULL, &crtc_state->dpll)) {
8265                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8266                 return -EINVAL;
8267         }
8268
8269         ironlake_compute_dpll(crtc, crtc_state, NULL);
8270
8271         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8272                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8273                                  pipe_name(crtc->pipe));
8274                 return -EINVAL;
8275         }
8276
8277         return 0;
8278 }
8279
8280 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8281                                          struct intel_link_m_n *m_n)
8282 {
8283         struct drm_device *dev = crtc->base.dev;
8284         struct drm_i915_private *dev_priv = to_i915(dev);
8285         enum pipe pipe = crtc->pipe;
8286
8287         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8288         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8289         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8290                 & ~TU_SIZE_MASK;
8291         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8292         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8293                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8294 }
8295
8296 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8297                                          enum transcoder transcoder,
8298                                          struct intel_link_m_n *m_n,
8299                                          struct intel_link_m_n *m2_n2)
8300 {
8301         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8302         enum pipe pipe = crtc->pipe;
8303
8304         if (INTEL_GEN(dev_priv) >= 5) {
8305                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8306                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8307                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8308                         & ~TU_SIZE_MASK;
8309                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8310                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8311                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8312                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8313                  * gen < 8) and if DRRS is supported (to make sure the
8314                  * registers are not unnecessarily read).
8315                  */
8316                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8317                         crtc->config->has_drrs) {
8318                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8319                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8320                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8321                                         & ~TU_SIZE_MASK;
8322                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8323                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8324                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8325                 }
8326         } else {
8327                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8328                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8329                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8330                         & ~TU_SIZE_MASK;
8331                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8332                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8333                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8334         }
8335 }
8336
8337 void intel_dp_get_m_n(struct intel_crtc *crtc,
8338                       struct intel_crtc_state *pipe_config)
8339 {
8340         if (pipe_config->has_pch_encoder)
8341                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8342         else
8343                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8344                                              &pipe_config->dp_m_n,
8345                                              &pipe_config->dp_m2_n2);
8346 }
8347
8348 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8349                                         struct intel_crtc_state *pipe_config)
8350 {
8351         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8352                                      &pipe_config->fdi_m_n, NULL);
8353 }
8354
8355 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8356                                     struct intel_crtc_state *pipe_config)
8357 {
8358         struct drm_device *dev = crtc->base.dev;
8359         struct drm_i915_private *dev_priv = to_i915(dev);
8360         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8361         uint32_t ps_ctrl = 0;
8362         int id = -1;
8363         int i;
8364
8365         /* find scaler attached to this pipe */
8366         for (i = 0; i < crtc->num_scalers; i++) {
8367                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8368                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8369                         id = i;
8370                         pipe_config->pch_pfit.enabled = true;
8371                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8372                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8373                         break;
8374                 }
8375         }
8376
8377         scaler_state->scaler_id = id;
8378         if (id >= 0) {
8379                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8380         } else {
8381                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8382         }
8383 }
8384
8385 static void
8386 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8387                                  struct intel_initial_plane_config *plane_config)
8388 {
8389         struct drm_device *dev = crtc->base.dev;
8390         struct drm_i915_private *dev_priv = to_i915(dev);
8391         u32 val, base, offset, stride_mult, tiling;
8392         int pipe = crtc->pipe;
8393         int fourcc, pixel_format;
8394         unsigned int aligned_height;
8395         struct drm_framebuffer *fb;
8396         struct intel_framebuffer *intel_fb;
8397
8398         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8399         if (!intel_fb) {
8400                 DRM_DEBUG_KMS("failed to alloc fb\n");
8401                 return;
8402         }
8403
8404         fb = &intel_fb->base;
8405
8406         fb->dev = dev;
8407
8408         val = I915_READ(PLANE_CTL(pipe, 0));
8409         if (!(val & PLANE_CTL_ENABLE))
8410                 goto error;
8411
8412         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8413         fourcc = skl_format_to_fourcc(pixel_format,
8414                                       val & PLANE_CTL_ORDER_RGBX,
8415                                       val & PLANE_CTL_ALPHA_MASK);
8416         fb->format = drm_format_info(fourcc);
8417
8418         tiling = val & PLANE_CTL_TILED_MASK;
8419         switch (tiling) {
8420         case PLANE_CTL_TILED_LINEAR:
8421                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8422                 break;
8423         case PLANE_CTL_TILED_X:
8424                 plane_config->tiling = I915_TILING_X;
8425                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8426                 break;
8427         case PLANE_CTL_TILED_Y:
8428                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8429                 break;
8430         case PLANE_CTL_TILED_YF:
8431                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8432                 break;
8433         default:
8434                 MISSING_CASE(tiling);
8435                 goto error;
8436         }
8437
8438         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8439         plane_config->base = base;
8440
8441         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8442
8443         val = I915_READ(PLANE_SIZE(pipe, 0));
8444         fb->height = ((val >> 16) & 0xfff) + 1;
8445         fb->width = ((val >> 0) & 0x1fff) + 1;
8446
8447         val = I915_READ(PLANE_STRIDE(pipe, 0));
8448         stride_mult = intel_fb_stride_alignment(fb, 0);
8449         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8450
8451         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8452
8453         plane_config->size = fb->pitches[0] * aligned_height;
8454
8455         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8456                       pipe_name(pipe), fb->width, fb->height,
8457                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8458                       plane_config->size);
8459
8460         plane_config->fb = intel_fb;
8461         return;
8462
8463 error:
8464         kfree(intel_fb);
8465 }
8466
8467 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8468                                      struct intel_crtc_state *pipe_config)
8469 {
8470         struct drm_device *dev = crtc->base.dev;
8471         struct drm_i915_private *dev_priv = to_i915(dev);
8472         uint32_t tmp;
8473
8474         tmp = I915_READ(PF_CTL(crtc->pipe));
8475
8476         if (tmp & PF_ENABLE) {
8477                 pipe_config->pch_pfit.enabled = true;
8478                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8479                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8480
8481                 /* We currently do not free assignements of panel fitters on
8482                  * ivb/hsw (since we don't use the higher upscaling modes which
8483                  * differentiates them) so just WARN about this case for now. */
8484                 if (IS_GEN7(dev_priv)) {
8485                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8486                                 PF_PIPE_SEL_IVB(crtc->pipe));
8487                 }
8488         }
8489 }
8490
8491 static void
8492 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8493                                   struct intel_initial_plane_config *plane_config)
8494 {
8495         struct drm_device *dev = crtc->base.dev;
8496         struct drm_i915_private *dev_priv = to_i915(dev);
8497         u32 val, base, offset;
8498         int pipe = crtc->pipe;
8499         int fourcc, pixel_format;
8500         unsigned int aligned_height;
8501         struct drm_framebuffer *fb;
8502         struct intel_framebuffer *intel_fb;
8503
8504         val = I915_READ(DSPCNTR(pipe));
8505         if (!(val & DISPLAY_PLANE_ENABLE))
8506                 return;
8507
8508         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8509         if (!intel_fb) {
8510                 DRM_DEBUG_KMS("failed to alloc fb\n");
8511                 return;
8512         }
8513
8514         fb = &intel_fb->base;
8515
8516         fb->dev = dev;
8517
8518         if (INTEL_GEN(dev_priv) >= 4) {
8519                 if (val & DISPPLANE_TILED) {
8520                         plane_config->tiling = I915_TILING_X;
8521                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8522                 }
8523         }
8524
8525         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8526         fourcc = i9xx_format_to_fourcc(pixel_format);
8527         fb->format = drm_format_info(fourcc);
8528
8529         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8530         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8531                 offset = I915_READ(DSPOFFSET(pipe));
8532         } else {
8533                 if (plane_config->tiling)
8534                         offset = I915_READ(DSPTILEOFF(pipe));
8535                 else
8536                         offset = I915_READ(DSPLINOFF(pipe));
8537         }
8538         plane_config->base = base;
8539
8540         val = I915_READ(PIPESRC(pipe));
8541         fb->width = ((val >> 16) & 0xfff) + 1;
8542         fb->height = ((val >> 0) & 0xfff) + 1;
8543
8544         val = I915_READ(DSPSTRIDE(pipe));
8545         fb->pitches[0] = val & 0xffffffc0;
8546
8547         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8548
8549         plane_config->size = fb->pitches[0] * aligned_height;
8550
8551         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8552                       pipe_name(pipe), fb->width, fb->height,
8553                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8554                       plane_config->size);
8555
8556         plane_config->fb = intel_fb;
8557 }
8558
8559 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8560                                      struct intel_crtc_state *pipe_config)
8561 {
8562         struct drm_device *dev = crtc->base.dev;
8563         struct drm_i915_private *dev_priv = to_i915(dev);
8564         enum intel_display_power_domain power_domain;
8565         uint32_t tmp;
8566         bool ret;
8567
8568         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8569         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8570                 return false;
8571
8572         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8573         pipe_config->shared_dpll = NULL;
8574
8575         ret = false;
8576         tmp = I915_READ(PIPECONF(crtc->pipe));
8577         if (!(tmp & PIPECONF_ENABLE))
8578                 goto out;
8579
8580         switch (tmp & PIPECONF_BPC_MASK) {
8581         case PIPECONF_6BPC:
8582                 pipe_config->pipe_bpp = 18;
8583                 break;
8584         case PIPECONF_8BPC:
8585                 pipe_config->pipe_bpp = 24;
8586                 break;
8587         case PIPECONF_10BPC:
8588                 pipe_config->pipe_bpp = 30;
8589                 break;
8590         case PIPECONF_12BPC:
8591                 pipe_config->pipe_bpp = 36;
8592                 break;
8593         default:
8594                 break;
8595         }
8596
8597         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8598                 pipe_config->limited_color_range = true;
8599
8600         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8601                 struct intel_shared_dpll *pll;
8602                 enum intel_dpll_id pll_id;
8603
8604                 pipe_config->has_pch_encoder = true;
8605
8606                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8607                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8608                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8609
8610                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8611
8612                 if (HAS_PCH_IBX(dev_priv)) {
8613                         /*
8614                          * The pipe->pch transcoder and pch transcoder->pll
8615                          * mapping is fixed.
8616                          */
8617                         pll_id = (enum intel_dpll_id) crtc->pipe;
8618                 } else {
8619                         tmp = I915_READ(PCH_DPLL_SEL);
8620                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8621                                 pll_id = DPLL_ID_PCH_PLL_B;
8622                         else
8623                                 pll_id= DPLL_ID_PCH_PLL_A;
8624                 }
8625
8626                 pipe_config->shared_dpll =
8627                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8628                 pll = pipe_config->shared_dpll;
8629
8630                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8631                                                  &pipe_config->dpll_hw_state));
8632
8633                 tmp = pipe_config->dpll_hw_state.dpll;
8634                 pipe_config->pixel_multiplier =
8635                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8636                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8637
8638                 ironlake_pch_clock_get(crtc, pipe_config);
8639         } else {
8640                 pipe_config->pixel_multiplier = 1;
8641         }
8642
8643         intel_get_pipe_timings(crtc, pipe_config);
8644         intel_get_pipe_src_size(crtc, pipe_config);
8645
8646         ironlake_get_pfit_config(crtc, pipe_config);
8647
8648         ret = true;
8649
8650 out:
8651         intel_display_power_put(dev_priv, power_domain);
8652
8653         return ret;
8654 }
8655
8656 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8657 {
8658         struct drm_device *dev = &dev_priv->drm;
8659         struct intel_crtc *crtc;
8660
8661         for_each_intel_crtc(dev, crtc)
8662                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8663                      pipe_name(crtc->pipe));
8664
8665         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8666         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8667         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8668         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8669         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8670         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8671              "CPU PWM1 enabled\n");
8672         if (IS_HASWELL(dev_priv))
8673                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8674                      "CPU PWM2 enabled\n");
8675         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8676              "PCH PWM1 enabled\n");
8677         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8678              "Utility pin enabled\n");
8679         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8680
8681         /*
8682          * In theory we can still leave IRQs enabled, as long as only the HPD
8683          * interrupts remain enabled. We used to check for that, but since it's
8684          * gen-specific and since we only disable LCPLL after we fully disable
8685          * the interrupts, the check below should be enough.
8686          */
8687         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8688 }
8689
8690 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8691 {
8692         if (IS_HASWELL(dev_priv))
8693                 return I915_READ(D_COMP_HSW);
8694         else
8695                 return I915_READ(D_COMP_BDW);
8696 }
8697
8698 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8699 {
8700         if (IS_HASWELL(dev_priv)) {
8701                 mutex_lock(&dev_priv->rps.hw_lock);
8702                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8703                                             val))
8704                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8705                 mutex_unlock(&dev_priv->rps.hw_lock);
8706         } else {
8707                 I915_WRITE(D_COMP_BDW, val);
8708                 POSTING_READ(D_COMP_BDW);
8709         }
8710 }
8711
8712 /*
8713  * This function implements pieces of two sequences from BSpec:
8714  * - Sequence for display software to disable LCPLL
8715  * - Sequence for display software to allow package C8+
8716  * The steps implemented here are just the steps that actually touch the LCPLL
8717  * register. Callers should take care of disabling all the display engine
8718  * functions, doing the mode unset, fixing interrupts, etc.
8719  */
8720 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8721                               bool switch_to_fclk, bool allow_power_down)
8722 {
8723         uint32_t val;
8724
8725         assert_can_disable_lcpll(dev_priv);
8726
8727         val = I915_READ(LCPLL_CTL);
8728
8729         if (switch_to_fclk) {
8730                 val |= LCPLL_CD_SOURCE_FCLK;
8731                 I915_WRITE(LCPLL_CTL, val);
8732
8733                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8734                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8735                         DRM_ERROR("Switching to FCLK failed\n");
8736
8737                 val = I915_READ(LCPLL_CTL);
8738         }
8739
8740         val |= LCPLL_PLL_DISABLE;
8741         I915_WRITE(LCPLL_CTL, val);
8742         POSTING_READ(LCPLL_CTL);
8743
8744         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8745                 DRM_ERROR("LCPLL still locked\n");
8746
8747         val = hsw_read_dcomp(dev_priv);
8748         val |= D_COMP_COMP_DISABLE;
8749         hsw_write_dcomp(dev_priv, val);
8750         ndelay(100);
8751
8752         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8753                      1))
8754                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8755
8756         if (allow_power_down) {
8757                 val = I915_READ(LCPLL_CTL);
8758                 val |= LCPLL_POWER_DOWN_ALLOW;
8759                 I915_WRITE(LCPLL_CTL, val);
8760                 POSTING_READ(LCPLL_CTL);
8761         }
8762 }
8763
8764 /*
8765  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8766  * source.
8767  */
8768 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8769 {
8770         uint32_t val;
8771
8772         val = I915_READ(LCPLL_CTL);
8773
8774         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8775                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8776                 return;
8777
8778         /*
8779          * Make sure we're not on PC8 state before disabling PC8, otherwise
8780          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8781          */
8782         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8783
8784         if (val & LCPLL_POWER_DOWN_ALLOW) {
8785                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8786                 I915_WRITE(LCPLL_CTL, val);
8787                 POSTING_READ(LCPLL_CTL);
8788         }
8789
8790         val = hsw_read_dcomp(dev_priv);
8791         val |= D_COMP_COMP_FORCE;
8792         val &= ~D_COMP_COMP_DISABLE;
8793         hsw_write_dcomp(dev_priv, val);
8794
8795         val = I915_READ(LCPLL_CTL);
8796         val &= ~LCPLL_PLL_DISABLE;
8797         I915_WRITE(LCPLL_CTL, val);
8798
8799         if (intel_wait_for_register(dev_priv,
8800                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8801                                     5))
8802                 DRM_ERROR("LCPLL not locked yet\n");
8803
8804         if (val & LCPLL_CD_SOURCE_FCLK) {
8805                 val = I915_READ(LCPLL_CTL);
8806                 val &= ~LCPLL_CD_SOURCE_FCLK;
8807                 I915_WRITE(LCPLL_CTL, val);
8808
8809                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8810                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8811                         DRM_ERROR("Switching back to LCPLL failed\n");
8812         }
8813
8814         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8815         intel_update_cdclk(dev_priv);
8816 }
8817
8818 /*
8819  * Package states C8 and deeper are really deep PC states that can only be
8820  * reached when all the devices on the system allow it, so even if the graphics
8821  * device allows PC8+, it doesn't mean the system will actually get to these
8822  * states. Our driver only allows PC8+ when going into runtime PM.
8823  *
8824  * The requirements for PC8+ are that all the outputs are disabled, the power
8825  * well is disabled and most interrupts are disabled, and these are also
8826  * requirements for runtime PM. When these conditions are met, we manually do
8827  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8828  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8829  * hang the machine.
8830  *
8831  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8832  * the state of some registers, so when we come back from PC8+ we need to
8833  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8834  * need to take care of the registers kept by RC6. Notice that this happens even
8835  * if we don't put the device in PCI D3 state (which is what currently happens
8836  * because of the runtime PM support).
8837  *
8838  * For more, read "Display Sequences for Package C8" on the hardware
8839  * documentation.
8840  */
8841 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8842 {
8843         uint32_t val;
8844
8845         DRM_DEBUG_KMS("Enabling package C8+\n");
8846
8847         if (HAS_PCH_LPT_LP(dev_priv)) {
8848                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8849                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8850                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8851         }
8852
8853         lpt_disable_clkout_dp(dev_priv);
8854         hsw_disable_lcpll(dev_priv, true, true);
8855 }
8856
8857 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8858 {
8859         uint32_t val;
8860
8861         DRM_DEBUG_KMS("Disabling package C8+\n");
8862
8863         hsw_restore_lcpll(dev_priv);
8864         lpt_init_pch_refclk(dev_priv);
8865
8866         if (HAS_PCH_LPT_LP(dev_priv)) {
8867                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8868                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8869                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8870         }
8871 }
8872
8873 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8874                                       struct intel_crtc_state *crtc_state)
8875 {
8876         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8877                 struct intel_encoder *encoder =
8878                         intel_ddi_get_crtc_new_encoder(crtc_state);
8879
8880                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8881                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8882                                          pipe_name(crtc->pipe));
8883                         return -EINVAL;
8884                 }
8885         }
8886
8887         crtc->lowfreq_avail = false;
8888
8889         return 0;
8890 }
8891
8892 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8893                                    enum port port,
8894                                    struct intel_crtc_state *pipe_config)
8895 {
8896         enum intel_dpll_id id;
8897         u32 temp;
8898
8899         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8900         id = temp >> (port * 2);
8901
8902         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8903                 return;
8904
8905         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8906 }
8907
8908 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8909                                 enum port port,
8910                                 struct intel_crtc_state *pipe_config)
8911 {
8912         enum intel_dpll_id id;
8913
8914         switch (port) {
8915         case PORT_A:
8916                 id = DPLL_ID_SKL_DPLL0;
8917                 break;
8918         case PORT_B:
8919                 id = DPLL_ID_SKL_DPLL1;
8920                 break;
8921         case PORT_C:
8922                 id = DPLL_ID_SKL_DPLL2;
8923                 break;
8924         default:
8925                 DRM_ERROR("Incorrect port type\n");
8926                 return;
8927         }
8928
8929         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8930 }
8931
8932 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8933                                 enum port port,
8934                                 struct intel_crtc_state *pipe_config)
8935 {
8936         enum intel_dpll_id id;
8937         u32 temp;
8938
8939         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8940         id = temp >> (port * 3 + 1);
8941
8942         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8943                 return;
8944
8945         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8946 }
8947
8948 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8949                                 enum port port,
8950                                 struct intel_crtc_state *pipe_config)
8951 {
8952         enum intel_dpll_id id;
8953         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8954
8955         switch (ddi_pll_sel) {
8956         case PORT_CLK_SEL_WRPLL1:
8957                 id = DPLL_ID_WRPLL1;
8958                 break;
8959         case PORT_CLK_SEL_WRPLL2:
8960                 id = DPLL_ID_WRPLL2;
8961                 break;
8962         case PORT_CLK_SEL_SPLL:
8963                 id = DPLL_ID_SPLL;
8964                 break;
8965         case PORT_CLK_SEL_LCPLL_810:
8966                 id = DPLL_ID_LCPLL_810;
8967                 break;
8968         case PORT_CLK_SEL_LCPLL_1350:
8969                 id = DPLL_ID_LCPLL_1350;
8970                 break;
8971         case PORT_CLK_SEL_LCPLL_2700:
8972                 id = DPLL_ID_LCPLL_2700;
8973                 break;
8974         default:
8975                 MISSING_CASE(ddi_pll_sel);
8976                 /* fall through */
8977         case PORT_CLK_SEL_NONE:
8978                 return;
8979         }
8980
8981         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8982 }
8983
8984 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8985                                      struct intel_crtc_state *pipe_config,
8986                                      u64 *power_domain_mask)
8987 {
8988         struct drm_device *dev = crtc->base.dev;
8989         struct drm_i915_private *dev_priv = to_i915(dev);
8990         enum intel_display_power_domain power_domain;
8991         u32 tmp;
8992
8993         /*
8994          * The pipe->transcoder mapping is fixed with the exception of the eDP
8995          * transcoder handled below.
8996          */
8997         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8998
8999         /*
9000          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9001          * consistency and less surprising code; it's in always on power).
9002          */
9003         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9004         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9005                 enum pipe trans_edp_pipe;
9006                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9007                 default:
9008                         WARN(1, "unknown pipe linked to edp transcoder\n");
9009                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9010                 case TRANS_DDI_EDP_INPUT_A_ON:
9011                         trans_edp_pipe = PIPE_A;
9012                         break;
9013                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9014                         trans_edp_pipe = PIPE_B;
9015                         break;
9016                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9017                         trans_edp_pipe = PIPE_C;
9018                         break;
9019                 }
9020
9021                 if (trans_edp_pipe == crtc->pipe)
9022                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9023         }
9024
9025         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9026         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9027                 return false;
9028         *power_domain_mask |= BIT_ULL(power_domain);
9029
9030         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9031
9032         return tmp & PIPECONF_ENABLE;
9033 }
9034
9035 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9036                                          struct intel_crtc_state *pipe_config,
9037                                          u64 *power_domain_mask)
9038 {
9039         struct drm_device *dev = crtc->base.dev;
9040         struct drm_i915_private *dev_priv = to_i915(dev);
9041         enum intel_display_power_domain power_domain;
9042         enum port port;
9043         enum transcoder cpu_transcoder;
9044         u32 tmp;
9045
9046         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9047                 if (port == PORT_A)
9048                         cpu_transcoder = TRANSCODER_DSI_A;
9049                 else
9050                         cpu_transcoder = TRANSCODER_DSI_C;
9051
9052                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9053                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9054                         continue;
9055                 *power_domain_mask |= BIT_ULL(power_domain);
9056
9057                 /*
9058                  * The PLL needs to be enabled with a valid divider
9059                  * configuration, otherwise accessing DSI registers will hang
9060                  * the machine. See BSpec North Display Engine
9061                  * registers/MIPI[BXT]. We can break out here early, since we
9062                  * need the same DSI PLL to be enabled for both DSI ports.
9063                  */
9064                 if (!intel_dsi_pll_is_enabled(dev_priv))
9065                         break;
9066
9067                 /* XXX: this works for video mode only */
9068                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9069                 if (!(tmp & DPI_ENABLE))
9070                         continue;
9071
9072                 tmp = I915_READ(MIPI_CTRL(port));
9073                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9074                         continue;
9075
9076                 pipe_config->cpu_transcoder = cpu_transcoder;
9077                 break;
9078         }
9079
9080         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9081 }
9082
9083 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9084                                        struct intel_crtc_state *pipe_config)
9085 {
9086         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9087         struct intel_shared_dpll *pll;
9088         enum port port;
9089         uint32_t tmp;
9090
9091         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9092
9093         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9094
9095         if (IS_CANNONLAKE(dev_priv))
9096                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9097         else if (IS_GEN9_BC(dev_priv))
9098                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9099         else if (IS_GEN9_LP(dev_priv))
9100                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9101         else
9102                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9103
9104         pll = pipe_config->shared_dpll;
9105         if (pll) {
9106                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9107                                                  &pipe_config->dpll_hw_state));
9108         }
9109
9110         /*
9111          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9112          * DDI E. So just check whether this pipe is wired to DDI E and whether
9113          * the PCH transcoder is on.
9114          */
9115         if (INTEL_GEN(dev_priv) < 9 &&
9116             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9117                 pipe_config->has_pch_encoder = true;
9118
9119                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9120                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9121                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9122
9123                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9124         }
9125 }
9126
9127 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9128                                     struct intel_crtc_state *pipe_config)
9129 {
9130         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9131         enum intel_display_power_domain power_domain;
9132         u64 power_domain_mask;
9133         bool active;
9134
9135         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9136         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9137                 return false;
9138         power_domain_mask = BIT_ULL(power_domain);
9139
9140         pipe_config->shared_dpll = NULL;
9141
9142         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9143
9144         if (IS_GEN9_LP(dev_priv) &&
9145             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9146                 WARN_ON(active);
9147                 active = true;
9148         }
9149
9150         if (!active)
9151                 goto out;
9152
9153         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9154                 haswell_get_ddi_port_state(crtc, pipe_config);
9155                 intel_get_pipe_timings(crtc, pipe_config);
9156         }
9157
9158         intel_get_pipe_src_size(crtc, pipe_config);
9159
9160         pipe_config->gamma_mode =
9161                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9162
9163         if (INTEL_GEN(dev_priv) >= 9) {
9164                 intel_crtc_init_scalers(crtc, pipe_config);
9165
9166                 pipe_config->scaler_state.scaler_id = -1;
9167                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9168         }
9169
9170         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9171         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9172                 power_domain_mask |= BIT_ULL(power_domain);
9173                 if (INTEL_GEN(dev_priv) >= 9)
9174                         skylake_get_pfit_config(crtc, pipe_config);
9175                 else
9176                         ironlake_get_pfit_config(crtc, pipe_config);
9177         }
9178
9179         if (IS_HASWELL(dev_priv))
9180                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9181                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9182
9183         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9184             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9185                 pipe_config->pixel_multiplier =
9186                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9187         } else {
9188                 pipe_config->pixel_multiplier = 1;
9189         }
9190
9191 out:
9192         for_each_power_domain(power_domain, power_domain_mask)
9193                 intel_display_power_put(dev_priv, power_domain);
9194
9195         return active;
9196 }
9197
9198 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9199 {
9200         struct drm_i915_private *dev_priv =
9201                 to_i915(plane_state->base.plane->dev);
9202         const struct drm_framebuffer *fb = plane_state->base.fb;
9203         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9204         u32 base;
9205
9206         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9207                 base = obj->phys_handle->busaddr;
9208         else
9209                 base = intel_plane_ggtt_offset(plane_state);
9210
9211         base += plane_state->main.offset;
9212
9213         /* ILK+ do this automagically */
9214         if (HAS_GMCH_DISPLAY(dev_priv) &&
9215             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9216                 base += (plane_state->base.crtc_h *
9217                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9218
9219         return base;
9220 }
9221
9222 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9223 {
9224         int x = plane_state->base.crtc_x;
9225         int y = plane_state->base.crtc_y;
9226         u32 pos = 0;
9227
9228         if (x < 0) {
9229                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9230                 x = -x;
9231         }
9232         pos |= x << CURSOR_X_SHIFT;
9233
9234         if (y < 0) {
9235                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9236                 y = -y;
9237         }
9238         pos |= y << CURSOR_Y_SHIFT;
9239
9240         return pos;
9241 }
9242
9243 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9244 {
9245         const struct drm_mode_config *config =
9246                 &plane_state->base.plane->dev->mode_config;
9247         int width = plane_state->base.crtc_w;
9248         int height = plane_state->base.crtc_h;
9249
9250         return width > 0 && width <= config->cursor_width &&
9251                 height > 0 && height <= config->cursor_height;
9252 }
9253
9254 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9255                               struct intel_plane_state *plane_state)
9256 {
9257         const struct drm_framebuffer *fb = plane_state->base.fb;
9258         int src_x, src_y;
9259         u32 offset;
9260         int ret;
9261
9262         ret = drm_plane_helper_check_state(&plane_state->base,
9263                                            &plane_state->clip,
9264                                            DRM_PLANE_HELPER_NO_SCALING,
9265                                            DRM_PLANE_HELPER_NO_SCALING,
9266                                            true, true);
9267         if (ret)
9268                 return ret;
9269
9270         if (!fb)
9271                 return 0;
9272
9273         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9274                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9275                 return -EINVAL;
9276         }
9277
9278         src_x = plane_state->base.src_x >> 16;
9279         src_y = plane_state->base.src_y >> 16;
9280
9281         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9282         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9283
9284         if (src_x != 0 || src_y != 0) {
9285                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9286                 return -EINVAL;
9287         }
9288
9289         plane_state->main.offset = offset;
9290
9291         return 0;
9292 }
9293
9294 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9295                            const struct intel_plane_state *plane_state)
9296 {
9297         const struct drm_framebuffer *fb = plane_state->base.fb;
9298
9299         return CURSOR_ENABLE |
9300                 CURSOR_GAMMA_ENABLE |
9301                 CURSOR_FORMAT_ARGB |
9302                 CURSOR_STRIDE(fb->pitches[0]);
9303 }
9304
9305 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9306 {
9307         int width = plane_state->base.crtc_w;
9308
9309         /*
9310          * 845g/865g are only limited by the width of their cursors,
9311          * the height is arbitrary up to the precision of the register.
9312          */
9313         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9314 }
9315
9316 static int i845_check_cursor(struct intel_plane *plane,
9317                              struct intel_crtc_state *crtc_state,
9318                              struct intel_plane_state *plane_state)
9319 {
9320         const struct drm_framebuffer *fb = plane_state->base.fb;
9321         int ret;
9322
9323         ret = intel_check_cursor(crtc_state, plane_state);
9324         if (ret)
9325                 return ret;
9326
9327         /* if we want to turn off the cursor ignore width and height */
9328         if (!fb)
9329                 return 0;
9330
9331         /* Check for which cursor types we support */
9332         if (!i845_cursor_size_ok(plane_state)) {
9333                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9334                           plane_state->base.crtc_w,
9335                           plane_state->base.crtc_h);
9336                 return -EINVAL;
9337         }
9338
9339         switch (fb->pitches[0]) {
9340         case 256:
9341         case 512:
9342         case 1024:
9343         case 2048:
9344                 break;
9345         default:
9346                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9347                               fb->pitches[0]);
9348                 return -EINVAL;
9349         }
9350
9351         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9352
9353         return 0;
9354 }
9355
9356 static void i845_update_cursor(struct intel_plane *plane,
9357                                const struct intel_crtc_state *crtc_state,
9358                                const struct intel_plane_state *plane_state)
9359 {
9360         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9361         u32 cntl = 0, base = 0, pos = 0, size = 0;
9362         unsigned long irqflags;
9363
9364         if (plane_state && plane_state->base.visible) {
9365                 unsigned int width = plane_state->base.crtc_w;
9366                 unsigned int height = plane_state->base.crtc_h;
9367
9368                 cntl = plane_state->ctl;
9369                 size = (height << 12) | width;
9370
9371                 base = intel_cursor_base(plane_state);
9372                 pos = intel_cursor_position(plane_state);
9373         }
9374
9375         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9376
9377         /* On these chipsets we can only modify the base/size/stride
9378          * whilst the cursor is disabled.
9379          */
9380         if (plane->cursor.base != base ||
9381             plane->cursor.size != size ||
9382             plane->cursor.cntl != cntl) {
9383                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9384                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9385                 I915_WRITE_FW(CURSIZE, size);
9386                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9387                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9388
9389                 plane->cursor.base = base;
9390                 plane->cursor.size = size;
9391                 plane->cursor.cntl = cntl;
9392         } else {
9393                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9394         }
9395
9396         POSTING_READ_FW(CURCNTR(PIPE_A));
9397
9398         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9399 }
9400
9401 static void i845_disable_cursor(struct intel_plane *plane,
9402                                 struct intel_crtc *crtc)
9403 {
9404         i845_update_cursor(plane, NULL, NULL);
9405 }
9406
9407 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9408                            const struct intel_plane_state *plane_state)
9409 {
9410         struct drm_i915_private *dev_priv =
9411                 to_i915(plane_state->base.plane->dev);
9412         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9413         u32 cntl;
9414
9415         cntl = MCURSOR_GAMMA_ENABLE;
9416
9417         if (HAS_DDI(dev_priv))
9418                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9419
9420         cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9421
9422         switch (plane_state->base.crtc_w) {
9423         case 64:
9424                 cntl |= CURSOR_MODE_64_ARGB_AX;
9425                 break;
9426         case 128:
9427                 cntl |= CURSOR_MODE_128_ARGB_AX;
9428                 break;
9429         case 256:
9430                 cntl |= CURSOR_MODE_256_ARGB_AX;
9431                 break;
9432         default:
9433                 MISSING_CASE(plane_state->base.crtc_w);
9434                 return 0;
9435         }
9436
9437         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9438                 cntl |= CURSOR_ROTATE_180;
9439
9440         return cntl;
9441 }
9442
9443 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9444 {
9445         struct drm_i915_private *dev_priv =
9446                 to_i915(plane_state->base.plane->dev);
9447         int width = plane_state->base.crtc_w;
9448         int height = plane_state->base.crtc_h;
9449
9450         if (!intel_cursor_size_ok(plane_state))
9451                 return false;
9452
9453         /* Cursor width is limited to a few power-of-two sizes */
9454         switch (width) {
9455         case 256:
9456         case 128:
9457         case 64:
9458                 break;
9459         default:
9460                 return false;
9461         }
9462
9463         /*
9464          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9465          * height from 8 lines up to the cursor width, when the
9466          * cursor is not rotated. Everything else requires square
9467          * cursors.
9468          */
9469         if (HAS_CUR_FBC(dev_priv) &&
9470             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9471                 if (height < 8 || height > width)
9472                         return false;
9473         } else {
9474                 if (height != width)
9475                         return false;
9476         }
9477
9478         return true;
9479 }
9480
9481 static int i9xx_check_cursor(struct intel_plane *plane,
9482                              struct intel_crtc_state *crtc_state,
9483                              struct intel_plane_state *plane_state)
9484 {
9485         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9486         const struct drm_framebuffer *fb = plane_state->base.fb;
9487         enum pipe pipe = plane->pipe;
9488         int ret;
9489
9490         ret = intel_check_cursor(crtc_state, plane_state);
9491         if (ret)
9492                 return ret;
9493
9494         /* if we want to turn off the cursor ignore width and height */
9495         if (!fb)
9496                 return 0;
9497
9498         /* Check for which cursor types we support */
9499         if (!i9xx_cursor_size_ok(plane_state)) {
9500                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9501                           plane_state->base.crtc_w,
9502                           plane_state->base.crtc_h);
9503                 return -EINVAL;
9504         }
9505
9506         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9507                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9508                               fb->pitches[0], plane_state->base.crtc_w);
9509                 return -EINVAL;
9510         }
9511
9512         /*
9513          * There's something wrong with the cursor on CHV pipe C.
9514          * If it straddles the left edge of the screen then
9515          * moving it away from the edge or disabling it often
9516          * results in a pipe underrun, and often that can lead to
9517          * dead pipe (constant underrun reported, and it scans
9518          * out just a solid color). To recover from that, the
9519          * display power well must be turned off and on again.
9520          * Refuse the put the cursor into that compromised position.
9521          */
9522         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9523             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9524                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9525                 return -EINVAL;
9526         }
9527
9528         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9529
9530         return 0;
9531 }
9532
9533 static void i9xx_update_cursor(struct intel_plane *plane,
9534                                const struct intel_crtc_state *crtc_state,
9535                                const struct intel_plane_state *plane_state)
9536 {
9537         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9538         enum pipe pipe = plane->pipe;
9539         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9540         unsigned long irqflags;
9541
9542         if (plane_state && plane_state->base.visible) {
9543                 cntl = plane_state->ctl;
9544
9545                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9546                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9547
9548                 base = intel_cursor_base(plane_state);
9549                 pos = intel_cursor_position(plane_state);
9550         }
9551
9552         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9553
9554         /*
9555          * On some platforms writing CURCNTR first will also
9556          * cause CURPOS to be armed by the CURBASE write.
9557          * Without the CURCNTR write the CURPOS write would
9558          * arm itself.
9559          *
9560          * CURCNTR and CUR_FBC_CTL are always
9561          * armed by the CURBASE write only.
9562          */
9563         if (plane->cursor.base != base ||
9564             plane->cursor.size != fbc_ctl ||
9565             plane->cursor.cntl != cntl) {
9566                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9567                 if (HAS_CUR_FBC(dev_priv))
9568                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9569                 I915_WRITE_FW(CURPOS(pipe), pos);
9570                 I915_WRITE_FW(CURBASE(pipe), base);
9571
9572                 plane->cursor.base = base;
9573                 plane->cursor.size = fbc_ctl;
9574                 plane->cursor.cntl = cntl;
9575         } else {
9576                 I915_WRITE_FW(CURPOS(pipe), pos);
9577         }
9578
9579         POSTING_READ_FW(CURBASE(pipe));
9580
9581         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9582 }
9583
9584 static void i9xx_disable_cursor(struct intel_plane *plane,
9585                                 struct intel_crtc *crtc)
9586 {
9587         i9xx_update_cursor(plane, NULL, NULL);
9588 }
9589
9590
9591 /* VESA 640x480x72Hz mode to set on the pipe */
9592 static struct drm_display_mode load_detect_mode = {
9593         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9594                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9595 };
9596
9597 struct drm_framebuffer *
9598 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9599                          struct drm_mode_fb_cmd2 *mode_cmd)
9600 {
9601         struct intel_framebuffer *intel_fb;
9602         int ret;
9603
9604         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9605         if (!intel_fb)
9606                 return ERR_PTR(-ENOMEM);
9607
9608         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9609         if (ret)
9610                 goto err;
9611
9612         return &intel_fb->base;
9613
9614 err:
9615         kfree(intel_fb);
9616         return ERR_PTR(ret);
9617 }
9618
9619 static u32
9620 intel_framebuffer_pitch_for_width(int width, int bpp)
9621 {
9622         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9623         return ALIGN(pitch, 64);
9624 }
9625
9626 static u32
9627 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9628 {
9629         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9630         return PAGE_ALIGN(pitch * mode->vdisplay);
9631 }
9632
9633 static struct drm_framebuffer *
9634 intel_framebuffer_create_for_mode(struct drm_device *dev,
9635                                   struct drm_display_mode *mode,
9636                                   int depth, int bpp)
9637 {
9638         struct drm_framebuffer *fb;
9639         struct drm_i915_gem_object *obj;
9640         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9641
9642         obj = i915_gem_object_create(to_i915(dev),
9643                                     intel_framebuffer_size_for_mode(mode, bpp));
9644         if (IS_ERR(obj))
9645                 return ERR_CAST(obj);
9646
9647         mode_cmd.width = mode->hdisplay;
9648         mode_cmd.height = mode->vdisplay;
9649         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9650                                                                 bpp);
9651         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9652
9653         fb = intel_framebuffer_create(obj, &mode_cmd);
9654         if (IS_ERR(fb))
9655                 i915_gem_object_put(obj);
9656
9657         return fb;
9658 }
9659
9660 static struct drm_framebuffer *
9661 mode_fits_in_fbdev(struct drm_device *dev,
9662                    struct drm_display_mode *mode)
9663 {
9664 #ifdef CONFIG_DRM_FBDEV_EMULATION
9665         struct drm_i915_private *dev_priv = to_i915(dev);
9666         struct drm_i915_gem_object *obj;
9667         struct drm_framebuffer *fb;
9668
9669         if (!dev_priv->fbdev)
9670                 return NULL;
9671
9672         if (!dev_priv->fbdev->fb)
9673                 return NULL;
9674
9675         obj = dev_priv->fbdev->fb->obj;
9676         BUG_ON(!obj);
9677
9678         fb = &dev_priv->fbdev->fb->base;
9679         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9680                                                                fb->format->cpp[0] * 8))
9681                 return NULL;
9682
9683         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9684                 return NULL;
9685
9686         drm_framebuffer_reference(fb);
9687         return fb;
9688 #else
9689         return NULL;
9690 #endif
9691 }
9692
9693 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9694                                            struct drm_crtc *crtc,
9695                                            struct drm_display_mode *mode,
9696                                            struct drm_framebuffer *fb,
9697                                            int x, int y)
9698 {
9699         struct drm_plane_state *plane_state;
9700         int hdisplay, vdisplay;
9701         int ret;
9702
9703         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9704         if (IS_ERR(plane_state))
9705                 return PTR_ERR(plane_state);
9706
9707         if (mode)
9708                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9709         else
9710                 hdisplay = vdisplay = 0;
9711
9712         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9713         if (ret)
9714                 return ret;
9715         drm_atomic_set_fb_for_plane(plane_state, fb);
9716         plane_state->crtc_x = 0;
9717         plane_state->crtc_y = 0;
9718         plane_state->crtc_w = hdisplay;
9719         plane_state->crtc_h = vdisplay;
9720         plane_state->src_x = x << 16;
9721         plane_state->src_y = y << 16;
9722         plane_state->src_w = hdisplay << 16;
9723         plane_state->src_h = vdisplay << 16;
9724
9725         return 0;
9726 }
9727
9728 int intel_get_load_detect_pipe(struct drm_connector *connector,
9729                                struct drm_display_mode *mode,
9730                                struct intel_load_detect_pipe *old,
9731                                struct drm_modeset_acquire_ctx *ctx)
9732 {
9733         struct intel_crtc *intel_crtc;
9734         struct intel_encoder *intel_encoder =
9735                 intel_attached_encoder(connector);
9736         struct drm_crtc *possible_crtc;
9737         struct drm_encoder *encoder = &intel_encoder->base;
9738         struct drm_crtc *crtc = NULL;
9739         struct drm_device *dev = encoder->dev;
9740         struct drm_i915_private *dev_priv = to_i915(dev);
9741         struct drm_framebuffer *fb;
9742         struct drm_mode_config *config = &dev->mode_config;
9743         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9744         struct drm_connector_state *connector_state;
9745         struct intel_crtc_state *crtc_state;
9746         int ret, i = -1;
9747
9748         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9749                       connector->base.id, connector->name,
9750                       encoder->base.id, encoder->name);
9751
9752         old->restore_state = NULL;
9753
9754         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9755
9756         /*
9757          * Algorithm gets a little messy:
9758          *
9759          *   - if the connector already has an assigned crtc, use it (but make
9760          *     sure it's on first)
9761          *
9762          *   - try to find the first unused crtc that can drive this connector,
9763          *     and use that if we find one
9764          */
9765
9766         /* See if we already have a CRTC for this connector */
9767         if (connector->state->crtc) {
9768                 crtc = connector->state->crtc;
9769
9770                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9771                 if (ret)
9772                         goto fail;
9773
9774                 /* Make sure the crtc and connector are running */
9775                 goto found;
9776         }
9777
9778         /* Find an unused one (if possible) */
9779         for_each_crtc(dev, possible_crtc) {
9780                 i++;
9781                 if (!(encoder->possible_crtcs & (1 << i)))
9782                         continue;
9783
9784                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9785                 if (ret)
9786                         goto fail;
9787
9788                 if (possible_crtc->state->enable) {
9789                         drm_modeset_unlock(&possible_crtc->mutex);
9790                         continue;
9791                 }
9792
9793                 crtc = possible_crtc;
9794                 break;
9795         }
9796
9797         /*
9798          * If we didn't find an unused CRTC, don't use any.
9799          */
9800         if (!crtc) {
9801                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9802                 ret = -ENODEV;
9803                 goto fail;
9804         }
9805
9806 found:
9807         intel_crtc = to_intel_crtc(crtc);
9808
9809         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9810         if (ret)
9811                 goto fail;
9812
9813         state = drm_atomic_state_alloc(dev);
9814         restore_state = drm_atomic_state_alloc(dev);
9815         if (!state || !restore_state) {
9816                 ret = -ENOMEM;
9817                 goto fail;
9818         }
9819
9820         state->acquire_ctx = ctx;
9821         restore_state->acquire_ctx = ctx;
9822
9823         connector_state = drm_atomic_get_connector_state(state, connector);
9824         if (IS_ERR(connector_state)) {
9825                 ret = PTR_ERR(connector_state);
9826                 goto fail;
9827         }
9828
9829         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9830         if (ret)
9831                 goto fail;
9832
9833         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9834         if (IS_ERR(crtc_state)) {
9835                 ret = PTR_ERR(crtc_state);
9836                 goto fail;
9837         }
9838
9839         crtc_state->base.active = crtc_state->base.enable = true;
9840
9841         if (!mode)
9842                 mode = &load_detect_mode;
9843
9844         /* We need a framebuffer large enough to accommodate all accesses
9845          * that the plane may generate whilst we perform load detection.
9846          * We can not rely on the fbcon either being present (we get called
9847          * during its initialisation to detect all boot displays, or it may
9848          * not even exist) or that it is large enough to satisfy the
9849          * requested mode.
9850          */
9851         fb = mode_fits_in_fbdev(dev, mode);
9852         if (fb == NULL) {
9853                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9854                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9855         } else
9856                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9857         if (IS_ERR(fb)) {
9858                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9859                 ret = PTR_ERR(fb);
9860                 goto fail;
9861         }
9862
9863         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9864         if (ret)
9865                 goto fail;
9866
9867         drm_framebuffer_unreference(fb);
9868
9869         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9870         if (ret)
9871                 goto fail;
9872
9873         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9874         if (!ret)
9875                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9876         if (!ret)
9877                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9878         if (ret) {
9879                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9880                 goto fail;
9881         }
9882
9883         ret = drm_atomic_commit(state);
9884         if (ret) {
9885                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9886                 goto fail;
9887         }
9888
9889         old->restore_state = restore_state;
9890         drm_atomic_state_put(state);
9891
9892         /* let the connector get through one full cycle before testing */
9893         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9894         return true;
9895
9896 fail:
9897         if (state) {
9898                 drm_atomic_state_put(state);
9899                 state = NULL;
9900         }
9901         if (restore_state) {
9902                 drm_atomic_state_put(restore_state);
9903                 restore_state = NULL;
9904         }
9905
9906         if (ret == -EDEADLK)
9907                 return ret;
9908
9909         return false;
9910 }
9911
9912 void intel_release_load_detect_pipe(struct drm_connector *connector,
9913                                     struct intel_load_detect_pipe *old,
9914                                     struct drm_modeset_acquire_ctx *ctx)
9915 {
9916         struct intel_encoder *intel_encoder =
9917                 intel_attached_encoder(connector);
9918         struct drm_encoder *encoder = &intel_encoder->base;
9919         struct drm_atomic_state *state = old->restore_state;
9920         int ret;
9921
9922         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9923                       connector->base.id, connector->name,
9924                       encoder->base.id, encoder->name);
9925
9926         if (!state)
9927                 return;
9928
9929         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9930         if (ret)
9931                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9932         drm_atomic_state_put(state);
9933 }
9934
9935 static int i9xx_pll_refclk(struct drm_device *dev,
9936                            const struct intel_crtc_state *pipe_config)
9937 {
9938         struct drm_i915_private *dev_priv = to_i915(dev);
9939         u32 dpll = pipe_config->dpll_hw_state.dpll;
9940
9941         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9942                 return dev_priv->vbt.lvds_ssc_freq;
9943         else if (HAS_PCH_SPLIT(dev_priv))
9944                 return 120000;
9945         else if (!IS_GEN2(dev_priv))
9946                 return 96000;
9947         else
9948                 return 48000;
9949 }
9950
9951 /* Returns the clock of the currently programmed mode of the given pipe. */
9952 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9953                                 struct intel_crtc_state *pipe_config)
9954 {
9955         struct drm_device *dev = crtc->base.dev;
9956         struct drm_i915_private *dev_priv = to_i915(dev);
9957         int pipe = pipe_config->cpu_transcoder;
9958         u32 dpll = pipe_config->dpll_hw_state.dpll;
9959         u32 fp;
9960         struct dpll clock;
9961         int port_clock;
9962         int refclk = i9xx_pll_refclk(dev, pipe_config);
9963
9964         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9965                 fp = pipe_config->dpll_hw_state.fp0;
9966         else
9967                 fp = pipe_config->dpll_hw_state.fp1;
9968
9969         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9970         if (IS_PINEVIEW(dev_priv)) {
9971                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9972                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9973         } else {
9974                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9975                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9976         }
9977
9978         if (!IS_GEN2(dev_priv)) {
9979                 if (IS_PINEVIEW(dev_priv))
9980                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9981                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9982                 else
9983                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9984                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9985
9986                 switch (dpll & DPLL_MODE_MASK) {
9987                 case DPLLB_MODE_DAC_SERIAL:
9988                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9989                                 5 : 10;
9990                         break;
9991                 case DPLLB_MODE_LVDS:
9992                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9993                                 7 : 14;
9994                         break;
9995                 default:
9996                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9997                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9998                         return;
9999                 }
10000
10001                 if (IS_PINEVIEW(dev_priv))
10002                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10003                 else
10004                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10005         } else {
10006                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10007                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10008
10009                 if (is_lvds) {
10010                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10011                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10012
10013                         if (lvds & LVDS_CLKB_POWER_UP)
10014                                 clock.p2 = 7;
10015                         else
10016                                 clock.p2 = 14;
10017                 } else {
10018                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10019                                 clock.p1 = 2;
10020                         else {
10021                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10022                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10023                         }
10024                         if (dpll & PLL_P2_DIVIDE_BY_4)
10025                                 clock.p2 = 4;
10026                         else
10027                                 clock.p2 = 2;
10028                 }
10029
10030                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10031         }
10032
10033         /*
10034          * This value includes pixel_multiplier. We will use
10035          * port_clock to compute adjusted_mode.crtc_clock in the
10036          * encoder's get_config() function.
10037          */
10038         pipe_config->port_clock = port_clock;
10039 }
10040
10041 int intel_dotclock_calculate(int link_freq,
10042                              const struct intel_link_m_n *m_n)
10043 {
10044         /*
10045          * The calculation for the data clock is:
10046          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10047          * But we want to avoid losing precison if possible, so:
10048          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10049          *
10050          * and the link clock is simpler:
10051          * link_clock = (m * link_clock) / n
10052          */
10053
10054         if (!m_n->link_n)
10055                 return 0;
10056
10057         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10058 }
10059
10060 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10061                                    struct intel_crtc_state *pipe_config)
10062 {
10063         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10064
10065         /* read out port_clock from the DPLL */
10066         i9xx_crtc_clock_get(crtc, pipe_config);
10067
10068         /*
10069          * In case there is an active pipe without active ports,
10070          * we may need some idea for the dotclock anyway.
10071          * Calculate one based on the FDI configuration.
10072          */
10073         pipe_config->base.adjusted_mode.crtc_clock =
10074                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10075                                          &pipe_config->fdi_m_n);
10076 }
10077
10078 /** Returns the currently programmed mode of the given pipe. */
10079 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10080                                              struct drm_crtc *crtc)
10081 {
10082         struct drm_i915_private *dev_priv = to_i915(dev);
10083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10084         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10085         struct drm_display_mode *mode;
10086         struct intel_crtc_state *pipe_config;
10087         int htot = I915_READ(HTOTAL(cpu_transcoder));
10088         int hsync = I915_READ(HSYNC(cpu_transcoder));
10089         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10090         int vsync = I915_READ(VSYNC(cpu_transcoder));
10091         enum pipe pipe = intel_crtc->pipe;
10092
10093         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10094         if (!mode)
10095                 return NULL;
10096
10097         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10098         if (!pipe_config) {
10099                 kfree(mode);
10100                 return NULL;
10101         }
10102
10103         /*
10104          * Construct a pipe_config sufficient for getting the clock info
10105          * back out of crtc_clock_get.
10106          *
10107          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10108          * to use a real value here instead.
10109          */
10110         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10111         pipe_config->pixel_multiplier = 1;
10112         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10113         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10114         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10115         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10116
10117         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10118         mode->hdisplay = (htot & 0xffff) + 1;
10119         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10120         mode->hsync_start = (hsync & 0xffff) + 1;
10121         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10122         mode->vdisplay = (vtot & 0xffff) + 1;
10123         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10124         mode->vsync_start = (vsync & 0xffff) + 1;
10125         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10126
10127         drm_mode_set_name(mode);
10128
10129         kfree(pipe_config);
10130
10131         return mode;
10132 }
10133
10134 static void intel_crtc_destroy(struct drm_crtc *crtc)
10135 {
10136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10137         struct drm_device *dev = crtc->dev;
10138         struct intel_flip_work *work;
10139
10140         spin_lock_irq(&dev->event_lock);
10141         work = intel_crtc->flip_work;
10142         intel_crtc->flip_work = NULL;
10143         spin_unlock_irq(&dev->event_lock);
10144
10145         if (work) {
10146                 cancel_work_sync(&work->mmio_work);
10147                 cancel_work_sync(&work->unpin_work);
10148                 kfree(work);
10149         }
10150
10151         drm_crtc_cleanup(crtc);
10152
10153         kfree(intel_crtc);
10154 }
10155
10156 static void intel_unpin_work_fn(struct work_struct *__work)
10157 {
10158         struct intel_flip_work *work =
10159                 container_of(__work, struct intel_flip_work, unpin_work);
10160         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10161         struct drm_device *dev = crtc->base.dev;
10162         struct drm_plane *primary = crtc->base.primary;
10163
10164         if (is_mmio_work(work))
10165                 flush_work(&work->mmio_work);
10166
10167         mutex_lock(&dev->struct_mutex);
10168         intel_unpin_fb_vma(work->old_vma);
10169         i915_gem_object_put(work->pending_flip_obj);
10170         mutex_unlock(&dev->struct_mutex);
10171
10172         i915_gem_request_put(work->flip_queued_req);
10173
10174         intel_frontbuffer_flip_complete(to_i915(dev),
10175                                         to_intel_plane(primary)->frontbuffer_bit);
10176         intel_fbc_post_update(crtc);
10177         drm_framebuffer_unreference(work->old_fb);
10178
10179         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10180         atomic_dec(&crtc->unpin_work_count);
10181
10182         kfree(work);
10183 }
10184
10185 /* Is 'a' after or equal to 'b'? */
10186 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10187 {
10188         return !((a - b) & 0x80000000);
10189 }
10190
10191 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10192                                    struct intel_flip_work *work)
10193 {
10194         struct drm_device *dev = crtc->base.dev;
10195         struct drm_i915_private *dev_priv = to_i915(dev);
10196
10197         if (abort_flip_on_reset(crtc))
10198                 return true;
10199
10200         /*
10201          * The relevant registers doen't exist on pre-ctg.
10202          * As the flip done interrupt doesn't trigger for mmio
10203          * flips on gmch platforms, a flip count check isn't
10204          * really needed there. But since ctg has the registers,
10205          * include it in the check anyway.
10206          */
10207         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10208                 return true;
10209
10210         /*
10211          * BDW signals flip done immediately if the plane
10212          * is disabled, even if the plane enable is already
10213          * armed to occur at the next vblank :(
10214          */
10215
10216         /*
10217          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10218          * used the same base address. In that case the mmio flip might
10219          * have completed, but the CS hasn't even executed the flip yet.
10220          *
10221          * A flip count check isn't enough as the CS might have updated
10222          * the base address just after start of vblank, but before we
10223          * managed to process the interrupt. This means we'd complete the
10224          * CS flip too soon.
10225          *
10226          * Combining both checks should get us a good enough result. It may
10227          * still happen that the CS flip has been executed, but has not
10228          * yet actually completed. But in case the base address is the same
10229          * anyway, we don't really care.
10230          */
10231         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10232                 crtc->flip_work->gtt_offset &&
10233                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10234                                     crtc->flip_work->flip_count);
10235 }
10236
10237 static bool
10238 __pageflip_finished_mmio(struct intel_crtc *crtc,
10239                                struct intel_flip_work *work)
10240 {
10241         /*
10242          * MMIO work completes when vblank is different from
10243          * flip_queued_vblank.
10244          *
10245          * Reset counter value doesn't matter, this is handled by
10246          * i915_wait_request finishing early, so no need to handle
10247          * reset here.
10248          */
10249         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10250 }
10251
10252
10253 static bool pageflip_finished(struct intel_crtc *crtc,
10254                               struct intel_flip_work *work)
10255 {
10256         if (!atomic_read(&work->pending))
10257                 return false;
10258
10259         smp_rmb();
10260
10261         if (is_mmio_work(work))
10262                 return __pageflip_finished_mmio(crtc, work);
10263         else
10264                 return __pageflip_finished_cs(crtc, work);
10265 }
10266
10267 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10268 {
10269         struct drm_device *dev = &dev_priv->drm;
10270         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10271         struct intel_flip_work *work;
10272         unsigned long flags;
10273
10274         /* Ignore early vblank irqs */
10275         if (!crtc)
10276                 return;
10277
10278         /*
10279          * This is called both by irq handlers and the reset code (to complete
10280          * lost pageflips) so needs the full irqsave spinlocks.
10281          */
10282         spin_lock_irqsave(&dev->event_lock, flags);
10283         work = crtc->flip_work;
10284
10285         if (work != NULL &&
10286             !is_mmio_work(work) &&
10287             pageflip_finished(crtc, work))
10288                 page_flip_completed(crtc);
10289
10290         spin_unlock_irqrestore(&dev->event_lock, flags);
10291 }
10292
10293 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10294 {
10295         struct drm_device *dev = &dev_priv->drm;
10296         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10297         struct intel_flip_work *work;
10298         unsigned long flags;
10299
10300         /* Ignore early vblank irqs */
10301         if (!crtc)
10302                 return;
10303
10304         /*
10305          * This is called both by irq handlers and the reset code (to complete
10306          * lost pageflips) so needs the full irqsave spinlocks.
10307          */
10308         spin_lock_irqsave(&dev->event_lock, flags);
10309         work = crtc->flip_work;
10310
10311         if (work != NULL &&
10312             is_mmio_work(work) &&
10313             pageflip_finished(crtc, work))
10314                 page_flip_completed(crtc);
10315
10316         spin_unlock_irqrestore(&dev->event_lock, flags);
10317 }
10318
10319 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10320                                                struct intel_flip_work *work)
10321 {
10322         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10323
10324         /* Ensure that the work item is consistent when activating it ... */
10325         smp_mb__before_atomic();
10326         atomic_set(&work->pending, 1);
10327 }
10328
10329 static int intel_gen2_queue_flip(struct drm_device *dev,
10330                                  struct drm_crtc *crtc,
10331                                  struct drm_framebuffer *fb,
10332                                  struct drm_i915_gem_object *obj,
10333                                  struct drm_i915_gem_request *req,
10334                                  uint32_t flags)
10335 {
10336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10337         u32 flip_mask, *cs;
10338
10339         cs = intel_ring_begin(req, 6);
10340         if (IS_ERR(cs))
10341                 return PTR_ERR(cs);
10342
10343         /* Can't queue multiple flips, so wait for the previous
10344          * one to finish before executing the next.
10345          */
10346         if (intel_crtc->plane)
10347                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10348         else
10349                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10350         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10351         *cs++ = MI_NOOP;
10352         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10353         *cs++ = fb->pitches[0];
10354         *cs++ = intel_crtc->flip_work->gtt_offset;
10355         *cs++ = 0; /* aux display base address, unused */
10356
10357         return 0;
10358 }
10359
10360 static int intel_gen3_queue_flip(struct drm_device *dev,
10361                                  struct drm_crtc *crtc,
10362                                  struct drm_framebuffer *fb,
10363                                  struct drm_i915_gem_object *obj,
10364                                  struct drm_i915_gem_request *req,
10365                                  uint32_t flags)
10366 {
10367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10368         u32 flip_mask, *cs;
10369
10370         cs = intel_ring_begin(req, 6);
10371         if (IS_ERR(cs))
10372                 return PTR_ERR(cs);
10373
10374         if (intel_crtc->plane)
10375                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10376         else
10377                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10378         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10379         *cs++ = MI_NOOP;
10380         *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10381         *cs++ = fb->pitches[0];
10382         *cs++ = intel_crtc->flip_work->gtt_offset;
10383         *cs++ = MI_NOOP;
10384
10385         return 0;
10386 }
10387
10388 static int intel_gen4_queue_flip(struct drm_device *dev,
10389                                  struct drm_crtc *crtc,
10390                                  struct drm_framebuffer *fb,
10391                                  struct drm_i915_gem_object *obj,
10392                                  struct drm_i915_gem_request *req,
10393                                  uint32_t flags)
10394 {
10395         struct drm_i915_private *dev_priv = to_i915(dev);
10396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10397         u32 pf, pipesrc, *cs;
10398
10399         cs = intel_ring_begin(req, 4);
10400         if (IS_ERR(cs))
10401                 return PTR_ERR(cs);
10402
10403         /* i965+ uses the linear or tiled offsets from the
10404          * Display Registers (which do not change across a page-flip)
10405          * so we need only reprogram the base address.
10406          */
10407         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10408         *cs++ = fb->pitches[0];
10409         *cs++ = intel_crtc->flip_work->gtt_offset |
10410                 intel_fb_modifier_to_tiling(fb->modifier);
10411
10412         /* XXX Enabling the panel-fitter across page-flip is so far
10413          * untested on non-native modes, so ignore it for now.
10414          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10415          */
10416         pf = 0;
10417         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10418         *cs++ = pf | pipesrc;
10419
10420         return 0;
10421 }
10422
10423 static int intel_gen6_queue_flip(struct drm_device *dev,
10424                                  struct drm_crtc *crtc,
10425                                  struct drm_framebuffer *fb,
10426                                  struct drm_i915_gem_object *obj,
10427                                  struct drm_i915_gem_request *req,
10428                                  uint32_t flags)
10429 {
10430         struct drm_i915_private *dev_priv = to_i915(dev);
10431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10432         u32 pf, pipesrc, *cs;
10433
10434         cs = intel_ring_begin(req, 4);
10435         if (IS_ERR(cs))
10436                 return PTR_ERR(cs);
10437
10438         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10439         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10440         *cs++ = intel_crtc->flip_work->gtt_offset;
10441
10442         /* Contrary to the suggestions in the documentation,
10443          * "Enable Panel Fitter" does not seem to be required when page
10444          * flipping with a non-native mode, and worse causes a normal
10445          * modeset to fail.
10446          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10447          */
10448         pf = 0;
10449         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10450         *cs++ = pf | pipesrc;
10451
10452         return 0;
10453 }
10454
10455 static int intel_gen7_queue_flip(struct drm_device *dev,
10456                                  struct drm_crtc *crtc,
10457                                  struct drm_framebuffer *fb,
10458                                  struct drm_i915_gem_object *obj,
10459                                  struct drm_i915_gem_request *req,
10460                                  uint32_t flags)
10461 {
10462         struct drm_i915_private *dev_priv = to_i915(dev);
10463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10464         u32 *cs, plane_bit = 0;
10465         int len, ret;
10466
10467         switch (intel_crtc->plane) {
10468         case PLANE_A:
10469                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10470                 break;
10471         case PLANE_B:
10472                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10473                 break;
10474         case PLANE_C:
10475                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10476                 break;
10477         default:
10478                 WARN_ONCE(1, "unknown plane in flip command\n");
10479                 return -ENODEV;
10480         }
10481
10482         len = 4;
10483         if (req->engine->id == RCS) {
10484                 len += 6;
10485                 /*
10486                  * On Gen 8, SRM is now taking an extra dword to accommodate
10487                  * 48bits addresses, and we need a NOOP for the batch size to
10488                  * stay even.
10489                  */
10490                 if (IS_GEN8(dev_priv))
10491                         len += 2;
10492         }
10493
10494         /*
10495          * BSpec MI_DISPLAY_FLIP for IVB:
10496          * "The full packet must be contained within the same cache line."
10497          *
10498          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10499          * cacheline, if we ever start emitting more commands before
10500          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10501          * then do the cacheline alignment, and finally emit the
10502          * MI_DISPLAY_FLIP.
10503          */
10504         ret = intel_ring_cacheline_align(req);
10505         if (ret)
10506                 return ret;
10507
10508         cs = intel_ring_begin(req, len);
10509         if (IS_ERR(cs))
10510                 return PTR_ERR(cs);
10511
10512         /* Unmask the flip-done completion message. Note that the bspec says that
10513          * we should do this for both the BCS and RCS, and that we must not unmask
10514          * more than one flip event at any time (or ensure that one flip message
10515          * can be sent by waiting for flip-done prior to queueing new flips).
10516          * Experimentation says that BCS works despite DERRMR masking all
10517          * flip-done completion events and that unmasking all planes at once
10518          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10519          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10520          */
10521         if (req->engine->id == RCS) {
10522                 *cs++ = MI_LOAD_REGISTER_IMM(1);
10523                 *cs++ = i915_mmio_reg_offset(DERRMR);
10524                 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10525                           DERRMR_PIPEB_PRI_FLIP_DONE |
10526                           DERRMR_PIPEC_PRI_FLIP_DONE);
10527                 if (IS_GEN8(dev_priv))
10528                         *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10529                                 MI_SRM_LRM_GLOBAL_GTT;
10530                 else
10531                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10532                 *cs++ = i915_mmio_reg_offset(DERRMR);
10533                 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10534                 if (IS_GEN8(dev_priv)) {
10535                         *cs++ = 0;
10536                         *cs++ = MI_NOOP;
10537                 }
10538         }
10539
10540         *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10541         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10542         *cs++ = intel_crtc->flip_work->gtt_offset;
10543         *cs++ = MI_NOOP;
10544
10545         return 0;
10546 }
10547
10548 static bool use_mmio_flip(struct intel_engine_cs *engine,
10549                           struct drm_i915_gem_object *obj)
10550 {
10551         /*
10552          * This is not being used for older platforms, because
10553          * non-availability of flip done interrupt forces us to use
10554          * CS flips. Older platforms derive flip done using some clever
10555          * tricks involving the flip_pending status bits and vblank irqs.
10556          * So using MMIO flips there would disrupt this mechanism.
10557          */
10558
10559         if (engine == NULL)
10560                 return true;
10561
10562         if (INTEL_GEN(engine->i915) < 5)
10563                 return false;
10564
10565         if (i915.use_mmio_flip < 0)
10566                 return false;
10567         else if (i915.use_mmio_flip > 0)
10568                 return true;
10569         else if (i915.enable_execlists)
10570                 return true;
10571
10572         return engine != i915_gem_object_last_write_engine(obj);
10573 }
10574
10575 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10576                              unsigned int rotation,
10577                              struct intel_flip_work *work)
10578 {
10579         struct drm_device *dev = intel_crtc->base.dev;
10580         struct drm_i915_private *dev_priv = to_i915(dev);
10581         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10582         const enum pipe pipe = intel_crtc->pipe;
10583         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10584
10585         ctl = I915_READ(PLANE_CTL(pipe, 0));
10586         ctl &= ~PLANE_CTL_TILED_MASK;
10587         switch (fb->modifier) {
10588         case DRM_FORMAT_MOD_LINEAR:
10589                 break;
10590         case I915_FORMAT_MOD_X_TILED:
10591                 ctl |= PLANE_CTL_TILED_X;
10592                 break;
10593         case I915_FORMAT_MOD_Y_TILED:
10594                 ctl |= PLANE_CTL_TILED_Y;
10595                 break;
10596         case I915_FORMAT_MOD_Yf_TILED:
10597                 ctl |= PLANE_CTL_TILED_YF;
10598                 break;
10599         default:
10600                 MISSING_CASE(fb->modifier);
10601         }
10602
10603         /*
10604          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10605          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10606          */
10607         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10608         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10609
10610         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10611         POSTING_READ(PLANE_SURF(pipe, 0));
10612 }
10613
10614 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10615                              struct intel_flip_work *work)
10616 {
10617         struct drm_device *dev = intel_crtc->base.dev;
10618         struct drm_i915_private *dev_priv = to_i915(dev);
10619         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10620         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10621         u32 dspcntr;
10622
10623         dspcntr = I915_READ(reg);
10624
10625         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10626                 dspcntr |= DISPPLANE_TILED;
10627         else
10628                 dspcntr &= ~DISPPLANE_TILED;
10629
10630         I915_WRITE(reg, dspcntr);
10631
10632         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10633         POSTING_READ(DSPSURF(intel_crtc->plane));
10634 }
10635
10636 static void intel_mmio_flip_work_func(struct work_struct *w)
10637 {
10638         struct intel_flip_work *work =
10639                 container_of(w, struct intel_flip_work, mmio_work);
10640         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10641         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10642         struct intel_framebuffer *intel_fb =
10643                 to_intel_framebuffer(crtc->base.primary->fb);
10644         struct drm_i915_gem_object *obj = intel_fb->obj;
10645
10646         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10647
10648         intel_pipe_update_start(crtc);
10649
10650         if (INTEL_GEN(dev_priv) >= 9)
10651                 skl_do_mmio_flip(crtc, work->rotation, work);
10652         else
10653                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10654                 ilk_do_mmio_flip(crtc, work);
10655
10656         intel_pipe_update_end(crtc, work);
10657 }
10658
10659 static int intel_default_queue_flip(struct drm_device *dev,
10660                                     struct drm_crtc *crtc,
10661                                     struct drm_framebuffer *fb,
10662                                     struct drm_i915_gem_object *obj,
10663                                     struct drm_i915_gem_request *req,
10664                                     uint32_t flags)
10665 {
10666         return -ENODEV;
10667 }
10668
10669 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10670                                       struct intel_crtc *intel_crtc,
10671                                       struct intel_flip_work *work)
10672 {
10673         u32 addr, vblank;
10674
10675         if (!atomic_read(&work->pending))
10676                 return false;
10677
10678         smp_rmb();
10679
10680         vblank = intel_crtc_get_vblank_counter(intel_crtc);
10681         if (work->flip_ready_vblank == 0) {
10682                 if (work->flip_queued_req &&
10683                     !i915_gem_request_completed(work->flip_queued_req))
10684                         return false;
10685
10686                 work->flip_ready_vblank = vblank;
10687         }
10688
10689         if (vblank - work->flip_ready_vblank < 3)
10690                 return false;
10691
10692         /* Potential stall - if we see that the flip has happened,
10693          * assume a missed interrupt. */
10694         if (INTEL_GEN(dev_priv) >= 4)
10695                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10696         else
10697                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10698
10699         /* There is a potential issue here with a false positive after a flip
10700          * to the same address. We could address this by checking for a
10701          * non-incrementing frame counter.
10702          */
10703         return addr == work->gtt_offset;
10704 }
10705
10706 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10707 {
10708         struct drm_device *dev = &dev_priv->drm;
10709         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10710         struct intel_flip_work *work;
10711
10712         WARN_ON(!in_interrupt());
10713
10714         if (crtc == NULL)
10715                 return;
10716
10717         spin_lock(&dev->event_lock);
10718         work = crtc->flip_work;
10719
10720         if (work != NULL && !is_mmio_work(work) &&
10721             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10722                 WARN_ONCE(1,
10723                           "Kicking stuck page flip: queued at %d, now %d\n",
10724                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10725                 page_flip_completed(crtc);
10726                 work = NULL;
10727         }
10728
10729         if (work != NULL && !is_mmio_work(work) &&
10730             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10731                 intel_queue_rps_boost_for_request(work->flip_queued_req);
10732         spin_unlock(&dev->event_lock);
10733 }
10734
10735 __maybe_unused
10736 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10737                                 struct drm_framebuffer *fb,
10738                                 struct drm_pending_vblank_event *event,
10739                                 uint32_t page_flip_flags)
10740 {
10741         struct drm_device *dev = crtc->dev;
10742         struct drm_i915_private *dev_priv = to_i915(dev);
10743         struct drm_framebuffer *old_fb = crtc->primary->fb;
10744         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10746         struct drm_plane *primary = crtc->primary;
10747         enum pipe pipe = intel_crtc->pipe;
10748         struct intel_flip_work *work;
10749         struct intel_engine_cs *engine;
10750         bool mmio_flip;
10751         struct drm_i915_gem_request *request;
10752         struct i915_vma *vma;
10753         int ret;
10754
10755         /*
10756          * drm_mode_page_flip_ioctl() should already catch this, but double
10757          * check to be safe.  In the future we may enable pageflipping from
10758          * a disabled primary plane.
10759          */
10760         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10761                 return -EBUSY;
10762
10763         /* Can't change pixel format via MI display flips. */
10764         if (fb->format != crtc->primary->fb->format)
10765                 return -EINVAL;
10766
10767         /*
10768          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10769          * Note that pitch changes could also affect these register.
10770          */
10771         if (INTEL_GEN(dev_priv) > 3 &&
10772             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10773              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10774                 return -EINVAL;
10775
10776         if (i915_terminally_wedged(&dev_priv->gpu_error))
10777                 goto out_hang;
10778
10779         work = kzalloc(sizeof(*work), GFP_KERNEL);
10780         if (work == NULL)
10781                 return -ENOMEM;
10782
10783         work->event = event;
10784         work->crtc = crtc;
10785         work->old_fb = old_fb;
10786         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10787
10788         ret = drm_crtc_vblank_get(crtc);
10789         if (ret)
10790                 goto free_work;
10791
10792         /* We borrow the event spin lock for protecting flip_work */
10793         spin_lock_irq(&dev->event_lock);
10794         if (intel_crtc->flip_work) {
10795                 /* Before declaring the flip queue wedged, check if
10796                  * the hardware completed the operation behind our backs.
10797                  */
10798                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10799                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10800                         page_flip_completed(intel_crtc);
10801                 } else {
10802                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10803                         spin_unlock_irq(&dev->event_lock);
10804
10805                         drm_crtc_vblank_put(crtc);
10806                         kfree(work);
10807                         return -EBUSY;
10808                 }
10809         }
10810         intel_crtc->flip_work = work;
10811         spin_unlock_irq(&dev->event_lock);
10812
10813         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10814                 flush_workqueue(dev_priv->wq);
10815
10816         /* Reference the objects for the scheduled work. */
10817         drm_framebuffer_reference(work->old_fb);
10818
10819         crtc->primary->fb = fb;
10820         update_state_fb(crtc->primary);
10821
10822         work->pending_flip_obj = i915_gem_object_get(obj);
10823
10824         ret = i915_mutex_lock_interruptible(dev);
10825         if (ret)
10826                 goto cleanup;
10827
10828         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10829         if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10830                 ret = -EIO;
10831                 goto unlock;
10832         }
10833
10834         atomic_inc(&intel_crtc->unpin_work_count);
10835
10836         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10837                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10838
10839         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10840                 engine = dev_priv->engine[BCS];
10841                 if (fb->modifier != old_fb->modifier)
10842                         /* vlv: DISPLAY_FLIP fails to change tiling */
10843                         engine = NULL;
10844         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10845                 engine = dev_priv->engine[BCS];
10846         } else if (INTEL_GEN(dev_priv) >= 7) {
10847                 engine = i915_gem_object_last_write_engine(obj);
10848                 if (engine == NULL || engine->id != RCS)
10849                         engine = dev_priv->engine[BCS];
10850         } else {
10851                 engine = dev_priv->engine[RCS];
10852         }
10853
10854         mmio_flip = use_mmio_flip(engine, obj);
10855
10856         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10857         if (IS_ERR(vma)) {
10858                 ret = PTR_ERR(vma);
10859                 goto cleanup_pending;
10860         }
10861
10862         work->old_vma = to_intel_plane_state(primary->state)->vma;
10863         to_intel_plane_state(primary->state)->vma = vma;
10864
10865         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10866         work->rotation = crtc->primary->state->rotation;
10867
10868         /*
10869          * There's the potential that the next frame will not be compatible with
10870          * FBC, so we want to call pre_update() before the actual page flip.
10871          * The problem is that pre_update() caches some information about the fb
10872          * object, so we want to do this only after the object is pinned. Let's
10873          * be on the safe side and do this immediately before scheduling the
10874          * flip.
10875          */
10876         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10877                              to_intel_plane_state(primary->state));
10878
10879         if (mmio_flip) {
10880                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10881                 queue_work(system_unbound_wq, &work->mmio_work);
10882         } else {
10883                 request = i915_gem_request_alloc(engine,
10884                                                  dev_priv->kernel_context);
10885                 if (IS_ERR(request)) {
10886                         ret = PTR_ERR(request);
10887                         goto cleanup_unpin;
10888                 }
10889
10890                 ret = i915_gem_request_await_object(request, obj, false);
10891                 if (ret)
10892                         goto cleanup_request;
10893
10894                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10895                                                    page_flip_flags);
10896                 if (ret)
10897                         goto cleanup_request;
10898
10899                 intel_mark_page_flip_active(intel_crtc, work);
10900
10901                 work->flip_queued_req = i915_gem_request_get(request);
10902                 i915_add_request(request);
10903         }
10904
10905         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10906         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10907                           to_intel_plane(primary)->frontbuffer_bit);
10908         mutex_unlock(&dev->struct_mutex);
10909
10910         intel_frontbuffer_flip_prepare(to_i915(dev),
10911                                        to_intel_plane(primary)->frontbuffer_bit);
10912
10913         trace_i915_flip_request(intel_crtc->plane, obj);
10914
10915         return 0;
10916
10917 cleanup_request:
10918         i915_add_request(request);
10919 cleanup_unpin:
10920         to_intel_plane_state(primary->state)->vma = work->old_vma;
10921         intel_unpin_fb_vma(vma);
10922 cleanup_pending:
10923         atomic_dec(&intel_crtc->unpin_work_count);
10924 unlock:
10925         mutex_unlock(&dev->struct_mutex);
10926 cleanup:
10927         crtc->primary->fb = old_fb;
10928         update_state_fb(crtc->primary);
10929
10930         i915_gem_object_put(obj);
10931         drm_framebuffer_unreference(work->old_fb);
10932
10933         spin_lock_irq(&dev->event_lock);
10934         intel_crtc->flip_work = NULL;
10935         spin_unlock_irq(&dev->event_lock);
10936
10937         drm_crtc_vblank_put(crtc);
10938 free_work:
10939         kfree(work);
10940
10941         if (ret == -EIO) {
10942                 struct drm_atomic_state *state;
10943                 struct drm_plane_state *plane_state;
10944
10945 out_hang:
10946                 state = drm_atomic_state_alloc(dev);
10947                 if (!state)
10948                         return -ENOMEM;
10949                 state->acquire_ctx = dev->mode_config.acquire_ctx;
10950
10951 retry:
10952                 plane_state = drm_atomic_get_plane_state(state, primary);
10953                 ret = PTR_ERR_OR_ZERO(plane_state);
10954                 if (!ret) {
10955                         drm_atomic_set_fb_for_plane(plane_state, fb);
10956
10957                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10958                         if (!ret)
10959                                 ret = drm_atomic_commit(state);
10960                 }
10961
10962                 if (ret == -EDEADLK) {
10963                         drm_modeset_backoff(state->acquire_ctx);
10964                         drm_atomic_state_clear(state);
10965                         goto retry;
10966                 }
10967
10968                 drm_atomic_state_put(state);
10969
10970                 if (ret == 0 && event) {
10971                         spin_lock_irq(&dev->event_lock);
10972                         drm_crtc_send_vblank_event(crtc, event);
10973                         spin_unlock_irq(&dev->event_lock);
10974                 }
10975         }
10976         return ret;
10977 }
10978
10979
10980 /**
10981  * intel_wm_need_update - Check whether watermarks need updating
10982  * @plane: drm plane
10983  * @state: new plane state
10984  *
10985  * Check current plane state versus the new one to determine whether
10986  * watermarks need to be recalculated.
10987  *
10988  * Returns true or false.
10989  */
10990 static bool intel_wm_need_update(struct drm_plane *plane,
10991                                  struct drm_plane_state *state)
10992 {
10993         struct intel_plane_state *new = to_intel_plane_state(state);
10994         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10995
10996         /* Update watermarks on tiling or size changes. */
10997         if (new->base.visible != cur->base.visible)
10998                 return true;
10999
11000         if (!cur->base.fb || !new->base.fb)
11001                 return false;
11002
11003         if (cur->base.fb->modifier != new->base.fb->modifier ||
11004             cur->base.rotation != new->base.rotation ||
11005             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
11006             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
11007             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
11008             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
11009                 return true;
11010
11011         return false;
11012 }
11013
11014 static bool needs_scaling(struct intel_plane_state *state)
11015 {
11016         int src_w = drm_rect_width(&state->base.src) >> 16;
11017         int src_h = drm_rect_height(&state->base.src) >> 16;
11018         int dst_w = drm_rect_width(&state->base.dst);
11019         int dst_h = drm_rect_height(&state->base.dst);
11020
11021         return (src_w != dst_w || src_h != dst_h);
11022 }
11023
11024 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11025                                     struct drm_plane_state *plane_state)
11026 {
11027         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11028         struct drm_crtc *crtc = crtc_state->crtc;
11029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11030         struct intel_plane *plane = to_intel_plane(plane_state->plane);
11031         struct drm_device *dev = crtc->dev;
11032         struct drm_i915_private *dev_priv = to_i915(dev);
11033         struct intel_plane_state *old_plane_state =
11034                 to_intel_plane_state(plane->base.state);
11035         bool mode_changed = needs_modeset(crtc_state);
11036         bool was_crtc_enabled = crtc->state->active;
11037         bool is_crtc_enabled = crtc_state->active;
11038         bool turn_off, turn_on, visible, was_visible;
11039         struct drm_framebuffer *fb = plane_state->fb;
11040         int ret;
11041
11042         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11043                 ret = skl_update_scaler_plane(
11044                         to_intel_crtc_state(crtc_state),
11045                         to_intel_plane_state(plane_state));
11046                 if (ret)
11047                         return ret;
11048         }
11049
11050         was_visible = old_plane_state->base.visible;
11051         visible = plane_state->visible;
11052
11053         if (!was_crtc_enabled && WARN_ON(was_visible))
11054                 was_visible = false;
11055
11056         /*
11057          * Visibility is calculated as if the crtc was on, but
11058          * after scaler setup everything depends on it being off
11059          * when the crtc isn't active.
11060          *
11061          * FIXME this is wrong for watermarks. Watermarks should also
11062          * be computed as if the pipe would be active. Perhaps move
11063          * per-plane wm computation to the .check_plane() hook, and
11064          * only combine the results from all planes in the current place?
11065          */
11066         if (!is_crtc_enabled) {
11067                 plane_state->visible = visible = false;
11068                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
11069         }
11070
11071         if (!was_visible && !visible)
11072                 return 0;
11073
11074         if (fb != old_plane_state->base.fb)
11075                 pipe_config->fb_changed = true;
11076
11077         turn_off = was_visible && (!visible || mode_changed);
11078         turn_on = visible && (!was_visible || mode_changed);
11079
11080         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11081                          intel_crtc->base.base.id, intel_crtc->base.name,
11082                          plane->base.base.id, plane->base.name,
11083                          fb ? fb->base.id : -1);
11084
11085         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11086                          plane->base.base.id, plane->base.name,
11087                          was_visible, visible,
11088                          turn_off, turn_on, mode_changed);
11089
11090         if (turn_on) {
11091                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11092                         pipe_config->update_wm_pre = true;
11093
11094                 /* must disable cxsr around plane enable/disable */
11095                 if (plane->id != PLANE_CURSOR)
11096                         pipe_config->disable_cxsr = true;
11097         } else if (turn_off) {
11098                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11099                         pipe_config->update_wm_post = true;
11100
11101                 /* must disable cxsr around plane enable/disable */
11102                 if (plane->id != PLANE_CURSOR)
11103                         pipe_config->disable_cxsr = true;
11104         } else if (intel_wm_need_update(&plane->base, plane_state)) {
11105                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11106                         /* FIXME bollocks */
11107                         pipe_config->update_wm_pre = true;
11108                         pipe_config->update_wm_post = true;
11109                 }
11110         }
11111
11112         if (visible || was_visible)
11113                 pipe_config->fb_bits |= plane->frontbuffer_bit;
11114
11115         /*
11116          * WaCxSRDisabledForSpriteScaling:ivb
11117          *
11118          * cstate->update_wm was already set above, so this flag will
11119          * take effect when we commit and program watermarks.
11120          */
11121         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
11122             needs_scaling(to_intel_plane_state(plane_state)) &&
11123             !needs_scaling(old_plane_state))
11124                 pipe_config->disable_lp_wm = true;
11125
11126         return 0;
11127 }
11128
11129 static bool encoders_cloneable(const struct intel_encoder *a,
11130                                const struct intel_encoder *b)
11131 {
11132         /* masks could be asymmetric, so check both ways */
11133         return a == b || (a->cloneable & (1 << b->type) &&
11134                           b->cloneable & (1 << a->type));
11135 }
11136
11137 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11138                                          struct intel_crtc *crtc,
11139                                          struct intel_encoder *encoder)
11140 {
11141         struct intel_encoder *source_encoder;
11142         struct drm_connector *connector;
11143         struct drm_connector_state *connector_state;
11144         int i;
11145
11146         for_each_new_connector_in_state(state, connector, connector_state, i) {
11147                 if (connector_state->crtc != &crtc->base)
11148                         continue;
11149
11150                 source_encoder =
11151                         to_intel_encoder(connector_state->best_encoder);
11152                 if (!encoders_cloneable(encoder, source_encoder))
11153                         return false;
11154         }
11155
11156         return true;
11157 }
11158
11159 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11160                                    struct drm_crtc_state *crtc_state)
11161 {
11162         struct drm_device *dev = crtc->dev;
11163         struct drm_i915_private *dev_priv = to_i915(dev);
11164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11165         struct intel_crtc_state *pipe_config =
11166                 to_intel_crtc_state(crtc_state);
11167         struct drm_atomic_state *state = crtc_state->state;
11168         int ret;
11169         bool mode_changed = needs_modeset(crtc_state);
11170
11171         if (mode_changed && !crtc_state->active)
11172                 pipe_config->update_wm_post = true;
11173
11174         if (mode_changed && crtc_state->enable &&
11175             dev_priv->display.crtc_compute_clock &&
11176             !WARN_ON(pipe_config->shared_dpll)) {
11177                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11178                                                            pipe_config);
11179                 if (ret)
11180                         return ret;
11181         }
11182
11183         if (crtc_state->color_mgmt_changed) {
11184                 ret = intel_color_check(crtc, crtc_state);
11185                 if (ret)
11186                         return ret;
11187
11188                 /*
11189                  * Changing color management on Intel hardware is
11190                  * handled as part of planes update.
11191                  */
11192                 crtc_state->planes_changed = true;
11193         }
11194
11195         ret = 0;
11196         if (dev_priv->display.compute_pipe_wm) {
11197                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11198                 if (ret) {
11199                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11200                         return ret;
11201                 }
11202         }
11203
11204         if (dev_priv->display.compute_intermediate_wm &&
11205             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11206                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11207                         return 0;
11208
11209                 /*
11210                  * Calculate 'intermediate' watermarks that satisfy both the
11211                  * old state and the new state.  We can program these
11212                  * immediately.
11213                  */
11214                 ret = dev_priv->display.compute_intermediate_wm(dev,
11215                                                                 intel_crtc,
11216                                                                 pipe_config);
11217                 if (ret) {
11218                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11219                         return ret;
11220                 }
11221         } else if (dev_priv->display.compute_intermediate_wm) {
11222                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11223                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11224         }
11225
11226         if (INTEL_GEN(dev_priv) >= 9) {
11227                 if (mode_changed)
11228                         ret = skl_update_scaler_crtc(pipe_config);
11229
11230                 if (!ret)
11231                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
11232                                                             pipe_config);
11233                 if (!ret)
11234                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11235                                                          pipe_config);
11236         }
11237
11238         return ret;
11239 }
11240
11241 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11242         .atomic_begin = intel_begin_crtc_commit,
11243         .atomic_flush = intel_finish_crtc_commit,
11244         .atomic_check = intel_crtc_atomic_check,
11245 };
11246
11247 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11248 {
11249         struct intel_connector *connector;
11250         struct drm_connector_list_iter conn_iter;
11251
11252         drm_connector_list_iter_begin(dev, &conn_iter);
11253         for_each_intel_connector_iter(connector, &conn_iter) {
11254                 if (connector->base.state->crtc)
11255                         drm_connector_unreference(&connector->base);
11256
11257                 if (connector->base.encoder) {
11258                         connector->base.state->best_encoder =
11259                                 connector->base.encoder;
11260                         connector->base.state->crtc =
11261                                 connector->base.encoder->crtc;
11262
11263                         drm_connector_reference(&connector->base);
11264                 } else {
11265                         connector->base.state->best_encoder = NULL;
11266                         connector->base.state->crtc = NULL;
11267                 }
11268         }
11269         drm_connector_list_iter_end(&conn_iter);
11270 }
11271
11272 static void
11273 connected_sink_compute_bpp(struct intel_connector *connector,
11274                            struct intel_crtc_state *pipe_config)
11275 {
11276         const struct drm_display_info *info = &connector->base.display_info;
11277         int bpp = pipe_config->pipe_bpp;
11278
11279         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11280                       connector->base.base.id,
11281                       connector->base.name);
11282
11283         /* Don't use an invalid EDID bpc value */
11284         if (info->bpc != 0 && info->bpc * 3 < bpp) {
11285                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11286                               bpp, info->bpc * 3);
11287                 pipe_config->pipe_bpp = info->bpc * 3;
11288         }
11289
11290         /* Clamp bpp to 8 on screens without EDID 1.4 */
11291         if (info->bpc == 0 && bpp > 24) {
11292                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11293                               bpp);
11294                 pipe_config->pipe_bpp = 24;
11295         }
11296 }
11297
11298 static int
11299 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11300                           struct intel_crtc_state *pipe_config)
11301 {
11302         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11303         struct drm_atomic_state *state;
11304         struct drm_connector *connector;
11305         struct drm_connector_state *connector_state;
11306         int bpp, i;
11307
11308         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11309             IS_CHERRYVIEW(dev_priv)))
11310                 bpp = 10*3;
11311         else if (INTEL_GEN(dev_priv) >= 5)
11312                 bpp = 12*3;
11313         else
11314                 bpp = 8*3;
11315
11316
11317         pipe_config->pipe_bpp = bpp;
11318
11319         state = pipe_config->base.state;
11320
11321         /* Clamp display bpp to EDID value */
11322         for_each_new_connector_in_state(state, connector, connector_state, i) {
11323                 if (connector_state->crtc != &crtc->base)
11324                         continue;
11325
11326                 connected_sink_compute_bpp(to_intel_connector(connector),
11327                                            pipe_config);
11328         }
11329
11330         return bpp;
11331 }
11332
11333 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11334 {
11335         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11336                         "type: 0x%x flags: 0x%x\n",
11337                 mode->crtc_clock,
11338                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11339                 mode->crtc_hsync_end, mode->crtc_htotal,
11340                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11341                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11342 }
11343
11344 static inline void
11345 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11346                       unsigned int lane_count, struct intel_link_m_n *m_n)
11347 {
11348         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11349                       id, lane_count,
11350                       m_n->gmch_m, m_n->gmch_n,
11351                       m_n->link_m, m_n->link_n, m_n->tu);
11352 }
11353
11354 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11355                                    struct intel_crtc_state *pipe_config,
11356                                    const char *context)
11357 {
11358         struct drm_device *dev = crtc->base.dev;
11359         struct drm_i915_private *dev_priv = to_i915(dev);
11360         struct drm_plane *plane;
11361         struct intel_plane *intel_plane;
11362         struct intel_plane_state *state;
11363         struct drm_framebuffer *fb;
11364
11365         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11366                       crtc->base.base.id, crtc->base.name, context);
11367
11368         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11369                       transcoder_name(pipe_config->cpu_transcoder),
11370                       pipe_config->pipe_bpp, pipe_config->dither);
11371
11372         if (pipe_config->has_pch_encoder)
11373                 intel_dump_m_n_config(pipe_config, "fdi",
11374                                       pipe_config->fdi_lanes,
11375                                       &pipe_config->fdi_m_n);
11376
11377         if (intel_crtc_has_dp_encoder(pipe_config)) {
11378                 intel_dump_m_n_config(pipe_config, "dp m_n",
11379                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11380                 if (pipe_config->has_drrs)
11381                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11382                                               pipe_config->lane_count,
11383                                               &pipe_config->dp_m2_n2);
11384         }
11385
11386         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11387                       pipe_config->has_audio, pipe_config->has_infoframe);
11388
11389         DRM_DEBUG_KMS("requested mode:\n");
11390         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11391         DRM_DEBUG_KMS("adjusted mode:\n");
11392         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11393         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11394         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11395                       pipe_config->port_clock,
11396                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11397                       pipe_config->pixel_rate);
11398
11399         if (INTEL_GEN(dev_priv) >= 9)
11400                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11401                               crtc->num_scalers,
11402                               pipe_config->scaler_state.scaler_users,
11403                               pipe_config->scaler_state.scaler_id);
11404
11405         if (HAS_GMCH_DISPLAY(dev_priv))
11406                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11407                               pipe_config->gmch_pfit.control,
11408                               pipe_config->gmch_pfit.pgm_ratios,
11409                               pipe_config->gmch_pfit.lvds_border_bits);
11410         else
11411                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11412                               pipe_config->pch_pfit.pos,
11413                               pipe_config->pch_pfit.size,
11414                               enableddisabled(pipe_config->pch_pfit.enabled));
11415
11416         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11417                       pipe_config->ips_enabled, pipe_config->double_wide);
11418
11419         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11420
11421         DRM_DEBUG_KMS("planes on this crtc\n");
11422         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11423                 struct drm_format_name_buf format_name;
11424                 intel_plane = to_intel_plane(plane);
11425                 if (intel_plane->pipe != crtc->pipe)
11426                         continue;
11427
11428                 state = to_intel_plane_state(plane->state);
11429                 fb = state->base.fb;
11430                 if (!fb) {
11431                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11432                                       plane->base.id, plane->name, state->scaler_id);
11433                         continue;
11434                 }
11435
11436                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11437                               plane->base.id, plane->name,
11438                               fb->base.id, fb->width, fb->height,
11439                               drm_get_format_name(fb->format->format, &format_name));
11440                 if (INTEL_GEN(dev_priv) >= 9)
11441                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11442                                       state->scaler_id,
11443                                       state->base.src.x1 >> 16,
11444                                       state->base.src.y1 >> 16,
11445                                       drm_rect_width(&state->base.src) >> 16,
11446                                       drm_rect_height(&state->base.src) >> 16,
11447                                       state->base.dst.x1, state->base.dst.y1,
11448                                       drm_rect_width(&state->base.dst),
11449                                       drm_rect_height(&state->base.dst));
11450         }
11451 }
11452
11453 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11454 {
11455         struct drm_device *dev = state->dev;
11456         struct drm_connector *connector;
11457         struct drm_connector_list_iter conn_iter;
11458         unsigned int used_ports = 0;
11459         unsigned int used_mst_ports = 0;
11460
11461         /*
11462          * Walk the connector list instead of the encoder
11463          * list to detect the problem on ddi platforms
11464          * where there's just one encoder per digital port.
11465          */
11466         drm_connector_list_iter_begin(dev, &conn_iter);
11467         drm_for_each_connector_iter(connector, &conn_iter) {
11468                 struct drm_connector_state *connector_state;
11469                 struct intel_encoder *encoder;
11470
11471                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11472                 if (!connector_state)
11473                         connector_state = connector->state;
11474
11475                 if (!connector_state->best_encoder)
11476                         continue;
11477
11478                 encoder = to_intel_encoder(connector_state->best_encoder);
11479
11480                 WARN_ON(!connector_state->crtc);
11481
11482                 switch (encoder->type) {
11483                         unsigned int port_mask;
11484                 case INTEL_OUTPUT_UNKNOWN:
11485                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11486                                 break;
11487                 case INTEL_OUTPUT_DP:
11488                 case INTEL_OUTPUT_HDMI:
11489                 case INTEL_OUTPUT_EDP:
11490                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11491
11492                         /* the same port mustn't appear more than once */
11493                         if (used_ports & port_mask)
11494                                 return false;
11495
11496                         used_ports |= port_mask;
11497                         break;
11498                 case INTEL_OUTPUT_DP_MST:
11499                         used_mst_ports |=
11500                                 1 << enc_to_mst(&encoder->base)->primary->port;
11501                         break;
11502                 default:
11503                         break;
11504                 }
11505         }
11506         drm_connector_list_iter_end(&conn_iter);
11507
11508         /* can't mix MST and SST/HDMI on the same port */
11509         if (used_ports & used_mst_ports)
11510                 return false;
11511
11512         return true;
11513 }
11514
11515 static void
11516 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11517 {
11518         struct drm_i915_private *dev_priv =
11519                 to_i915(crtc_state->base.crtc->dev);
11520         struct intel_crtc_scaler_state scaler_state;
11521         struct intel_dpll_hw_state dpll_hw_state;
11522         struct intel_shared_dpll *shared_dpll;
11523         struct intel_crtc_wm_state wm_state;
11524         bool force_thru;
11525
11526         /* FIXME: before the switch to atomic started, a new pipe_config was
11527          * kzalloc'd. Code that depends on any field being zero should be
11528          * fixed, so that the crtc_state can be safely duplicated. For now,
11529          * only fields that are know to not cause problems are preserved. */
11530
11531         scaler_state = crtc_state->scaler_state;
11532         shared_dpll = crtc_state->shared_dpll;
11533         dpll_hw_state = crtc_state->dpll_hw_state;
11534         force_thru = crtc_state->pch_pfit.force_thru;
11535         if (IS_G4X(dev_priv) ||
11536             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11537                 wm_state = crtc_state->wm;
11538
11539         /* Keep base drm_crtc_state intact, only clear our extended struct */
11540         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11541         memset(&crtc_state->base + 1, 0,
11542                sizeof(*crtc_state) - sizeof(crtc_state->base));
11543
11544         crtc_state->scaler_state = scaler_state;
11545         crtc_state->shared_dpll = shared_dpll;
11546         crtc_state->dpll_hw_state = dpll_hw_state;
11547         crtc_state->pch_pfit.force_thru = force_thru;
11548         if (IS_G4X(dev_priv) ||
11549             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11550                 crtc_state->wm = wm_state;
11551 }
11552
11553 static int
11554 intel_modeset_pipe_config(struct drm_crtc *crtc,
11555                           struct intel_crtc_state *pipe_config)
11556 {
11557         struct drm_atomic_state *state = pipe_config->base.state;
11558         struct intel_encoder *encoder;
11559         struct drm_connector *connector;
11560         struct drm_connector_state *connector_state;
11561         int base_bpp, ret = -EINVAL;
11562         int i;
11563         bool retry = true;
11564
11565         clear_intel_crtc_state(pipe_config);
11566
11567         pipe_config->cpu_transcoder =
11568                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11569
11570         /*
11571          * Sanitize sync polarity flags based on requested ones. If neither
11572          * positive or negative polarity is requested, treat this as meaning
11573          * negative polarity.
11574          */
11575         if (!(pipe_config->base.adjusted_mode.flags &
11576               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11577                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11578
11579         if (!(pipe_config->base.adjusted_mode.flags &
11580               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11581                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11582
11583         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11584                                              pipe_config);
11585         if (base_bpp < 0)
11586                 goto fail;
11587
11588         /*
11589          * Determine the real pipe dimensions. Note that stereo modes can
11590          * increase the actual pipe size due to the frame doubling and
11591          * insertion of additional space for blanks between the frame. This
11592          * is stored in the crtc timings. We use the requested mode to do this
11593          * computation to clearly distinguish it from the adjusted mode, which
11594          * can be changed by the connectors in the below retry loop.
11595          */
11596         drm_mode_get_hv_timing(&pipe_config->base.mode,
11597                                &pipe_config->pipe_src_w,
11598                                &pipe_config->pipe_src_h);
11599
11600         for_each_new_connector_in_state(state, connector, connector_state, i) {
11601                 if (connector_state->crtc != crtc)
11602                         continue;
11603
11604                 encoder = to_intel_encoder(connector_state->best_encoder);
11605
11606                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11607                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11608                         goto fail;
11609                 }
11610
11611                 /*
11612                  * Determine output_types before calling the .compute_config()
11613                  * hooks so that the hooks can use this information safely.
11614                  */
11615                 pipe_config->output_types |= 1 << encoder->type;
11616         }
11617
11618 encoder_retry:
11619         /* Ensure the port clock defaults are reset when retrying. */
11620         pipe_config->port_clock = 0;
11621         pipe_config->pixel_multiplier = 1;
11622
11623         /* Fill in default crtc timings, allow encoders to overwrite them. */
11624         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11625                               CRTC_STEREO_DOUBLE);
11626
11627         /* Pass our mode to the connectors and the CRTC to give them a chance to
11628          * adjust it according to limitations or connector properties, and also
11629          * a chance to reject the mode entirely.
11630          */
11631         for_each_new_connector_in_state(state, connector, connector_state, i) {
11632                 if (connector_state->crtc != crtc)
11633                         continue;
11634
11635                 encoder = to_intel_encoder(connector_state->best_encoder);
11636
11637                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11638                         DRM_DEBUG_KMS("Encoder config failure\n");
11639                         goto fail;
11640                 }
11641         }
11642
11643         /* Set default port clock if not overwritten by the encoder. Needs to be
11644          * done afterwards in case the encoder adjusts the mode. */
11645         if (!pipe_config->port_clock)
11646                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11647                         * pipe_config->pixel_multiplier;
11648
11649         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11650         if (ret < 0) {
11651                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11652                 goto fail;
11653         }
11654
11655         if (ret == RETRY) {
11656                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11657                         ret = -EINVAL;
11658                         goto fail;
11659                 }
11660
11661                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11662                 retry = false;
11663                 goto encoder_retry;
11664         }
11665
11666         /* Dithering seems to not pass-through bits correctly when it should, so
11667          * only enable it on 6bpc panels and when its not a compliance
11668          * test requesting 6bpc video pattern.
11669          */
11670         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11671                 !pipe_config->dither_force_disable;
11672         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11673                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11674
11675 fail:
11676         return ret;
11677 }
11678
11679 static void
11680 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11681 {
11682         struct drm_crtc *crtc;
11683         struct drm_crtc_state *new_crtc_state;
11684         int i;
11685
11686         /* Double check state. */
11687         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11688                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11689
11690                 /*
11691                  * Update legacy state to satisfy fbc code. This can
11692                  * be removed when fbc uses the atomic state.
11693                  */
11694                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11695                         struct drm_plane_state *plane_state = crtc->primary->state;
11696
11697                         crtc->primary->fb = plane_state->fb;
11698                         crtc->x = plane_state->src_x >> 16;
11699                         crtc->y = plane_state->src_y >> 16;
11700                 }
11701         }
11702 }
11703
11704 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11705 {
11706         int diff;
11707
11708         if (clock1 == clock2)
11709                 return true;
11710
11711         if (!clock1 || !clock2)
11712                 return false;
11713
11714         diff = abs(clock1 - clock2);
11715
11716         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11717                 return true;
11718
11719         return false;
11720 }
11721
11722 static bool
11723 intel_compare_m_n(unsigned int m, unsigned int n,
11724                   unsigned int m2, unsigned int n2,
11725                   bool exact)
11726 {
11727         if (m == m2 && n == n2)
11728                 return true;
11729
11730         if (exact || !m || !n || !m2 || !n2)
11731                 return false;
11732
11733         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11734
11735         if (n > n2) {
11736                 while (n > n2) {
11737                         m2 <<= 1;
11738                         n2 <<= 1;
11739                 }
11740         } else if (n < n2) {
11741                 while (n < n2) {
11742                         m <<= 1;
11743                         n <<= 1;
11744                 }
11745         }
11746
11747         if (n != n2)
11748                 return false;
11749
11750         return intel_fuzzy_clock_check(m, m2);
11751 }
11752
11753 static bool
11754 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11755                        struct intel_link_m_n *m2_n2,
11756                        bool adjust)
11757 {
11758         if (m_n->tu == m2_n2->tu &&
11759             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11760                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11761             intel_compare_m_n(m_n->link_m, m_n->link_n,
11762                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11763                 if (adjust)
11764                         *m2_n2 = *m_n;
11765
11766                 return true;
11767         }
11768
11769         return false;
11770 }
11771
11772 static void __printf(3, 4)
11773 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11774 {
11775         char *level;
11776         unsigned int category;
11777         struct va_format vaf;
11778         va_list args;
11779
11780         if (adjust) {
11781                 level = KERN_DEBUG;
11782                 category = DRM_UT_KMS;
11783         } else {
11784                 level = KERN_ERR;
11785                 category = DRM_UT_NONE;
11786         }
11787
11788         va_start(args, format);
11789         vaf.fmt = format;
11790         vaf.va = &args;
11791
11792         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11793
11794         va_end(args);
11795 }
11796
11797 static bool
11798 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11799                           struct intel_crtc_state *current_config,
11800                           struct intel_crtc_state *pipe_config,
11801                           bool adjust)
11802 {
11803         bool ret = true;
11804
11805 #define PIPE_CONF_CHECK_X(name) \
11806         if (current_config->name != pipe_config->name) { \
11807                 pipe_config_err(adjust, __stringify(name), \
11808                           "(expected 0x%08x, found 0x%08x)\n", \
11809                           current_config->name, \
11810                           pipe_config->name); \
11811                 ret = false; \
11812         }
11813
11814 #define PIPE_CONF_CHECK_I(name) \
11815         if (current_config->name != pipe_config->name) { \
11816                 pipe_config_err(adjust, __stringify(name), \
11817                           "(expected %i, found %i)\n", \
11818                           current_config->name, \
11819                           pipe_config->name); \
11820                 ret = false; \
11821         }
11822
11823 #define PIPE_CONF_CHECK_P(name) \
11824         if (current_config->name != pipe_config->name) { \
11825                 pipe_config_err(adjust, __stringify(name), \
11826                           "(expected %p, found %p)\n", \
11827                           current_config->name, \
11828                           pipe_config->name); \
11829                 ret = false; \
11830         }
11831
11832 #define PIPE_CONF_CHECK_M_N(name) \
11833         if (!intel_compare_link_m_n(&current_config->name, \
11834                                     &pipe_config->name,\
11835                                     adjust)) { \
11836                 pipe_config_err(adjust, __stringify(name), \
11837                           "(expected tu %i gmch %i/%i link %i/%i, " \
11838                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11839                           current_config->name.tu, \
11840                           current_config->name.gmch_m, \
11841                           current_config->name.gmch_n, \
11842                           current_config->name.link_m, \
11843                           current_config->name.link_n, \
11844                           pipe_config->name.tu, \
11845                           pipe_config->name.gmch_m, \
11846                           pipe_config->name.gmch_n, \
11847                           pipe_config->name.link_m, \
11848                           pipe_config->name.link_n); \
11849                 ret = false; \
11850         }
11851
11852 /* This is required for BDW+ where there is only one set of registers for
11853  * switching between high and low RR.
11854  * This macro can be used whenever a comparison has to be made between one
11855  * hw state and multiple sw state variables.
11856  */
11857 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11858         if (!intel_compare_link_m_n(&current_config->name, \
11859                                     &pipe_config->name, adjust) && \
11860             !intel_compare_link_m_n(&current_config->alt_name, \
11861                                     &pipe_config->name, adjust)) { \
11862                 pipe_config_err(adjust, __stringify(name), \
11863                           "(expected tu %i gmch %i/%i link %i/%i, " \
11864                           "or tu %i gmch %i/%i link %i/%i, " \
11865                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11866                           current_config->name.tu, \
11867                           current_config->name.gmch_m, \
11868                           current_config->name.gmch_n, \
11869                           current_config->name.link_m, \
11870                           current_config->name.link_n, \
11871                           current_config->alt_name.tu, \
11872                           current_config->alt_name.gmch_m, \
11873                           current_config->alt_name.gmch_n, \
11874                           current_config->alt_name.link_m, \
11875                           current_config->alt_name.link_n, \
11876                           pipe_config->name.tu, \
11877                           pipe_config->name.gmch_m, \
11878                           pipe_config->name.gmch_n, \
11879                           pipe_config->name.link_m, \
11880                           pipe_config->name.link_n); \
11881                 ret = false; \
11882         }
11883
11884 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11885         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11886                 pipe_config_err(adjust, __stringify(name), \
11887                           "(%x) (expected %i, found %i)\n", \
11888                           (mask), \
11889                           current_config->name & (mask), \
11890                           pipe_config->name & (mask)); \
11891                 ret = false; \
11892         }
11893
11894 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11895         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11896                 pipe_config_err(adjust, __stringify(name), \
11897                           "(expected %i, found %i)\n", \
11898                           current_config->name, \
11899                           pipe_config->name); \
11900                 ret = false; \
11901         }
11902
11903 #define PIPE_CONF_QUIRK(quirk)  \
11904         ((current_config->quirks | pipe_config->quirks) & (quirk))
11905
11906         PIPE_CONF_CHECK_I(cpu_transcoder);
11907
11908         PIPE_CONF_CHECK_I(has_pch_encoder);
11909         PIPE_CONF_CHECK_I(fdi_lanes);
11910         PIPE_CONF_CHECK_M_N(fdi_m_n);
11911
11912         PIPE_CONF_CHECK_I(lane_count);
11913         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11914
11915         if (INTEL_GEN(dev_priv) < 8) {
11916                 PIPE_CONF_CHECK_M_N(dp_m_n);
11917
11918                 if (current_config->has_drrs)
11919                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11920         } else
11921                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11922
11923         PIPE_CONF_CHECK_X(output_types);
11924
11925         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11926         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11927         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11928         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11929         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11930         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11931
11932         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11933         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11934         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11935         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11936         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11937         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11938
11939         PIPE_CONF_CHECK_I(pixel_multiplier);
11940         PIPE_CONF_CHECK_I(has_hdmi_sink);
11941         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11942             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11943                 PIPE_CONF_CHECK_I(limited_color_range);
11944
11945         PIPE_CONF_CHECK_I(hdmi_scrambling);
11946         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11947         PIPE_CONF_CHECK_I(has_infoframe);
11948
11949         PIPE_CONF_CHECK_I(has_audio);
11950
11951         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11952                               DRM_MODE_FLAG_INTERLACE);
11953
11954         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11955                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11956                                       DRM_MODE_FLAG_PHSYNC);
11957                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11958                                       DRM_MODE_FLAG_NHSYNC);
11959                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11960                                       DRM_MODE_FLAG_PVSYNC);
11961                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11962                                       DRM_MODE_FLAG_NVSYNC);
11963         }
11964
11965         PIPE_CONF_CHECK_X(gmch_pfit.control);
11966         /* pfit ratios are autocomputed by the hw on gen4+ */
11967         if (INTEL_GEN(dev_priv) < 4)
11968                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11969         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11970
11971         if (!adjust) {
11972                 PIPE_CONF_CHECK_I(pipe_src_w);
11973                 PIPE_CONF_CHECK_I(pipe_src_h);
11974
11975                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11976                 if (current_config->pch_pfit.enabled) {
11977                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11978                         PIPE_CONF_CHECK_X(pch_pfit.size);
11979                 }
11980
11981                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11982                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11983         }
11984
11985         /* BDW+ don't expose a synchronous way to read the state */
11986         if (IS_HASWELL(dev_priv))
11987                 PIPE_CONF_CHECK_I(ips_enabled);
11988
11989         PIPE_CONF_CHECK_I(double_wide);
11990
11991         PIPE_CONF_CHECK_P(shared_dpll);
11992         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11993         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11994         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11995         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11996         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11997         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11998         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11999         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12000         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12001
12002         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12003         PIPE_CONF_CHECK_X(dsi_pll.div);
12004
12005         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
12006                 PIPE_CONF_CHECK_I(pipe_bpp);
12007
12008         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12009         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12010
12011 #undef PIPE_CONF_CHECK_X
12012 #undef PIPE_CONF_CHECK_I
12013 #undef PIPE_CONF_CHECK_P
12014 #undef PIPE_CONF_CHECK_FLAGS
12015 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12016 #undef PIPE_CONF_QUIRK
12017
12018         return ret;
12019 }
12020
12021 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12022                                            const struct intel_crtc_state *pipe_config)
12023 {
12024         if (pipe_config->has_pch_encoder) {
12025                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12026                                                             &pipe_config->fdi_m_n);
12027                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12028
12029                 /*
12030                  * FDI already provided one idea for the dotclock.
12031                  * Yell if the encoder disagrees.
12032                  */
12033                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12034                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12035                      fdi_dotclock, dotclock);
12036         }
12037 }
12038
12039 static void verify_wm_state(struct drm_crtc *crtc,
12040                             struct drm_crtc_state *new_state)
12041 {
12042         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12043         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12044         struct skl_pipe_wm hw_wm, *sw_wm;
12045         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12046         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
12047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12048         const enum pipe pipe = intel_crtc->pipe;
12049         int plane, level, max_level = ilk_wm_max_level(dev_priv);
12050
12051         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
12052                 return;
12053
12054         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
12055         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
12056
12057         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12058         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12059
12060         /* planes */
12061         for_each_universal_plane(dev_priv, pipe, plane) {
12062                 hw_plane_wm = &hw_wm.planes[plane];
12063                 sw_plane_wm = &sw_wm->planes[plane];
12064
12065                 /* Watermarks */
12066                 for (level = 0; level <= max_level; level++) {
12067                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12068                                                 &sw_plane_wm->wm[level]))
12069                                 continue;
12070
12071                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12072                                   pipe_name(pipe), plane + 1, level,
12073                                   sw_plane_wm->wm[level].plane_en,
12074                                   sw_plane_wm->wm[level].plane_res_b,
12075                                   sw_plane_wm->wm[level].plane_res_l,
12076                                   hw_plane_wm->wm[level].plane_en,
12077                                   hw_plane_wm->wm[level].plane_res_b,
12078                                   hw_plane_wm->wm[level].plane_res_l);
12079                 }
12080
12081                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12082                                          &sw_plane_wm->trans_wm)) {
12083                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12084                                   pipe_name(pipe), plane + 1,
12085                                   sw_plane_wm->trans_wm.plane_en,
12086                                   sw_plane_wm->trans_wm.plane_res_b,
12087                                   sw_plane_wm->trans_wm.plane_res_l,
12088                                   hw_plane_wm->trans_wm.plane_en,
12089                                   hw_plane_wm->trans_wm.plane_res_b,
12090                                   hw_plane_wm->trans_wm.plane_res_l);
12091                 }
12092
12093                 /* DDB */
12094                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
12095                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
12096
12097                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12098                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12099                                   pipe_name(pipe), plane + 1,
12100                                   sw_ddb_entry->start, sw_ddb_entry->end,
12101                                   hw_ddb_entry->start, hw_ddb_entry->end);
12102                 }
12103         }
12104
12105         /*
12106          * cursor
12107          * If the cursor plane isn't active, we may not have updated it's ddb
12108          * allocation. In that case since the ddb allocation will be updated
12109          * once the plane becomes visible, we can skip this check
12110          */
12111         if (1) {
12112                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
12113                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12114
12115                 /* Watermarks */
12116                 for (level = 0; level <= max_level; level++) {
12117                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12118                                                 &sw_plane_wm->wm[level]))
12119                                 continue;
12120
12121                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12122                                   pipe_name(pipe), level,
12123                                   sw_plane_wm->wm[level].plane_en,
12124                                   sw_plane_wm->wm[level].plane_res_b,
12125                                   sw_plane_wm->wm[level].plane_res_l,
12126                                   hw_plane_wm->wm[level].plane_en,
12127                                   hw_plane_wm->wm[level].plane_res_b,
12128                                   hw_plane_wm->wm[level].plane_res_l);
12129                 }
12130
12131                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12132                                          &sw_plane_wm->trans_wm)) {
12133                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12134                                   pipe_name(pipe),
12135                                   sw_plane_wm->trans_wm.plane_en,
12136                                   sw_plane_wm->trans_wm.plane_res_b,
12137                                   sw_plane_wm->trans_wm.plane_res_l,
12138                                   hw_plane_wm->trans_wm.plane_en,
12139                                   hw_plane_wm->trans_wm.plane_res_b,
12140                                   hw_plane_wm->trans_wm.plane_res_l);
12141                 }
12142
12143                 /* DDB */
12144                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12145                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12146
12147                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12148                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12149                                   pipe_name(pipe),
12150                                   sw_ddb_entry->start, sw_ddb_entry->end,
12151                                   hw_ddb_entry->start, hw_ddb_entry->end);
12152                 }
12153         }
12154 }
12155
12156 static void
12157 verify_connector_state(struct drm_device *dev,
12158                        struct drm_atomic_state *state,
12159                        struct drm_crtc *crtc)
12160 {
12161         struct drm_connector *connector;
12162         struct drm_connector_state *new_conn_state;
12163         int i;
12164
12165         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12166                 struct drm_encoder *encoder = connector->encoder;
12167                 struct drm_crtc_state *crtc_state = NULL;
12168
12169                 if (new_conn_state->crtc != crtc)
12170                         continue;
12171
12172                 if (crtc)
12173                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
12174
12175                 intel_connector_verify_state(crtc_state, new_conn_state);
12176
12177                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12178                      "connector's atomic encoder doesn't match legacy encoder\n");
12179         }
12180 }
12181
12182 static void
12183 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12184 {
12185         struct intel_encoder *encoder;
12186         struct drm_connector *connector;
12187         struct drm_connector_state *old_conn_state, *new_conn_state;
12188         int i;
12189
12190         for_each_intel_encoder(dev, encoder) {
12191                 bool enabled = false, found = false;
12192                 enum pipe pipe;
12193
12194                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12195                               encoder->base.base.id,
12196                               encoder->base.name);
12197
12198                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12199                                                    new_conn_state, i) {
12200                         if (old_conn_state->best_encoder == &encoder->base)
12201                                 found = true;
12202
12203                         if (new_conn_state->best_encoder != &encoder->base)
12204                                 continue;
12205                         found = enabled = true;
12206
12207                         I915_STATE_WARN(new_conn_state->crtc !=
12208                                         encoder->base.crtc,
12209                              "connector's crtc doesn't match encoder crtc\n");
12210                 }
12211
12212                 if (!found)
12213                         continue;
12214
12215                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12216                      "encoder's enabled state mismatch "
12217                      "(expected %i, found %i)\n",
12218                      !!encoder->base.crtc, enabled);
12219
12220                 if (!encoder->base.crtc) {
12221                         bool active;
12222
12223                         active = encoder->get_hw_state(encoder, &pipe);
12224                         I915_STATE_WARN(active,
12225                              "encoder detached but still enabled on pipe %c.\n",
12226                              pipe_name(pipe));
12227                 }
12228         }
12229 }
12230
12231 static void
12232 verify_crtc_state(struct drm_crtc *crtc,
12233                   struct drm_crtc_state *old_crtc_state,
12234                   struct drm_crtc_state *new_crtc_state)
12235 {
12236         struct drm_device *dev = crtc->dev;
12237         struct drm_i915_private *dev_priv = to_i915(dev);
12238         struct intel_encoder *encoder;
12239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12240         struct intel_crtc_state *pipe_config, *sw_config;
12241         struct drm_atomic_state *old_state;
12242         bool active;
12243
12244         old_state = old_crtc_state->state;
12245         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12246         pipe_config = to_intel_crtc_state(old_crtc_state);
12247         memset(pipe_config, 0, sizeof(*pipe_config));
12248         pipe_config->base.crtc = crtc;
12249         pipe_config->base.state = old_state;
12250
12251         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12252
12253         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12254
12255         /* we keep both pipes enabled on 830 */
12256         if (IS_I830(dev_priv))
12257                 active = new_crtc_state->active;
12258
12259         I915_STATE_WARN(new_crtc_state->active != active,
12260              "crtc active state doesn't match with hw state "
12261              "(expected %i, found %i)\n", new_crtc_state->active, active);
12262
12263         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12264              "transitional active state does not match atomic hw state "
12265              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12266
12267         for_each_encoder_on_crtc(dev, crtc, encoder) {
12268                 enum pipe pipe;
12269
12270                 active = encoder->get_hw_state(encoder, &pipe);
12271                 I915_STATE_WARN(active != new_crtc_state->active,
12272                         "[ENCODER:%i] active %i with crtc active %i\n",
12273                         encoder->base.base.id, active, new_crtc_state->active);
12274
12275                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12276                                 "Encoder connected to wrong pipe %c\n",
12277                                 pipe_name(pipe));
12278
12279                 if (active) {
12280                         pipe_config->output_types |= 1 << encoder->type;
12281                         encoder->get_config(encoder, pipe_config);
12282                 }
12283         }
12284
12285         intel_crtc_compute_pixel_rate(pipe_config);
12286
12287         if (!new_crtc_state->active)
12288                 return;
12289
12290         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12291
12292         sw_config = to_intel_crtc_state(new_crtc_state);
12293         if (!intel_pipe_config_compare(dev_priv, sw_config,
12294                                        pipe_config, false)) {
12295                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12296                 intel_dump_pipe_config(intel_crtc, pipe_config,
12297                                        "[hw state]");
12298                 intel_dump_pipe_config(intel_crtc, sw_config,
12299                                        "[sw state]");
12300         }
12301 }
12302
12303 static void
12304 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12305                          struct intel_shared_dpll *pll,
12306                          struct drm_crtc *crtc,
12307                          struct drm_crtc_state *new_state)
12308 {
12309         struct intel_dpll_hw_state dpll_hw_state;
12310         unsigned crtc_mask;
12311         bool active;
12312
12313         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12314
12315         DRM_DEBUG_KMS("%s\n", pll->name);
12316
12317         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12318
12319         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12320                 I915_STATE_WARN(!pll->on && pll->active_mask,
12321                      "pll in active use but not on in sw tracking\n");
12322                 I915_STATE_WARN(pll->on && !pll->active_mask,
12323                      "pll is on but not used by any active crtc\n");
12324                 I915_STATE_WARN(pll->on != active,
12325                      "pll on state mismatch (expected %i, found %i)\n",
12326                      pll->on, active);
12327         }
12328
12329         if (!crtc) {
12330                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12331                                 "more active pll users than references: %x vs %x\n",
12332                                 pll->active_mask, pll->state.crtc_mask);
12333
12334                 return;
12335         }
12336
12337         crtc_mask = 1 << drm_crtc_index(crtc);
12338
12339         if (new_state->active)
12340                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12341                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12342                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12343         else
12344                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12345                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12346                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12347
12348         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12349                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12350                         crtc_mask, pll->state.crtc_mask);
12351
12352         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12353                                           &dpll_hw_state,
12354                                           sizeof(dpll_hw_state)),
12355                         "pll hw state mismatch\n");
12356 }
12357
12358 static void
12359 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12360                          struct drm_crtc_state *old_crtc_state,
12361                          struct drm_crtc_state *new_crtc_state)
12362 {
12363         struct drm_i915_private *dev_priv = to_i915(dev);
12364         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12365         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12366
12367         if (new_state->shared_dpll)
12368                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12369
12370         if (old_state->shared_dpll &&
12371             old_state->shared_dpll != new_state->shared_dpll) {
12372                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12373                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12374
12375                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12376                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12377                                 pipe_name(drm_crtc_index(crtc)));
12378                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12379                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12380                                 pipe_name(drm_crtc_index(crtc)));
12381         }
12382 }
12383
12384 static void
12385 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12386                           struct drm_atomic_state *state,
12387                           struct drm_crtc_state *old_state,
12388                           struct drm_crtc_state *new_state)
12389 {
12390         if (!needs_modeset(new_state) &&
12391             !to_intel_crtc_state(new_state)->update_pipe)
12392                 return;
12393
12394         verify_wm_state(crtc, new_state);
12395         verify_connector_state(crtc->dev, state, crtc);
12396         verify_crtc_state(crtc, old_state, new_state);
12397         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12398 }
12399
12400 static void
12401 verify_disabled_dpll_state(struct drm_device *dev)
12402 {
12403         struct drm_i915_private *dev_priv = to_i915(dev);
12404         int i;
12405
12406         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12407                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12408 }
12409
12410 static void
12411 intel_modeset_verify_disabled(struct drm_device *dev,
12412                               struct drm_atomic_state *state)
12413 {
12414         verify_encoder_state(dev, state);
12415         verify_connector_state(dev, state, NULL);
12416         verify_disabled_dpll_state(dev);
12417 }
12418
12419 static void update_scanline_offset(struct intel_crtc *crtc)
12420 {
12421         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12422
12423         /*
12424          * The scanline counter increments at the leading edge of hsync.
12425          *
12426          * On most platforms it starts counting from vtotal-1 on the
12427          * first active line. That means the scanline counter value is
12428          * always one less than what we would expect. Ie. just after
12429          * start of vblank, which also occurs at start of hsync (on the
12430          * last active line), the scanline counter will read vblank_start-1.
12431          *
12432          * On gen2 the scanline counter starts counting from 1 instead
12433          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12434          * to keep the value positive), instead of adding one.
12435          *
12436          * On HSW+ the behaviour of the scanline counter depends on the output
12437          * type. For DP ports it behaves like most other platforms, but on HDMI
12438          * there's an extra 1 line difference. So we need to add two instead of
12439          * one to the value.
12440          *
12441          * On VLV/CHV DSI the scanline counter would appear to increment
12442          * approx. 1/3 of a scanline before start of vblank. Unfortunately
12443          * that means we can't tell whether we're in vblank or not while
12444          * we're on that particular line. We must still set scanline_offset
12445          * to 1 so that the vblank timestamps come out correct when we query
12446          * the scanline counter from within the vblank interrupt handler.
12447          * However if queried just before the start of vblank we'll get an
12448          * answer that's slightly in the future.
12449          */
12450         if (IS_GEN2(dev_priv)) {
12451                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12452                 int vtotal;
12453
12454                 vtotal = adjusted_mode->crtc_vtotal;
12455                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12456                         vtotal /= 2;
12457
12458                 crtc->scanline_offset = vtotal - 1;
12459         } else if (HAS_DDI(dev_priv) &&
12460                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12461                 crtc->scanline_offset = 2;
12462         } else
12463                 crtc->scanline_offset = 1;
12464 }
12465
12466 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12467 {
12468         struct drm_device *dev = state->dev;
12469         struct drm_i915_private *dev_priv = to_i915(dev);
12470         struct drm_crtc *crtc;
12471         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12472         int i;
12473
12474         if (!dev_priv->display.crtc_compute_clock)
12475                 return;
12476
12477         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12478                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12479                 struct intel_shared_dpll *old_dpll =
12480                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
12481
12482                 if (!needs_modeset(new_crtc_state))
12483                         continue;
12484
12485                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12486
12487                 if (!old_dpll)
12488                         continue;
12489
12490                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12491         }
12492 }
12493
12494 /*
12495  * This implements the workaround described in the "notes" section of the mode
12496  * set sequence documentation. When going from no pipes or single pipe to
12497  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12498  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12499  */
12500 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12501 {
12502         struct drm_crtc_state *crtc_state;
12503         struct intel_crtc *intel_crtc;
12504         struct drm_crtc *crtc;
12505         struct intel_crtc_state *first_crtc_state = NULL;
12506         struct intel_crtc_state *other_crtc_state = NULL;
12507         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12508         int i;
12509
12510         /* look at all crtc's that are going to be enabled in during modeset */
12511         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12512                 intel_crtc = to_intel_crtc(crtc);
12513
12514                 if (!crtc_state->active || !needs_modeset(crtc_state))
12515                         continue;
12516
12517                 if (first_crtc_state) {
12518                         other_crtc_state = to_intel_crtc_state(crtc_state);
12519                         break;
12520                 } else {
12521                         first_crtc_state = to_intel_crtc_state(crtc_state);
12522                         first_pipe = intel_crtc->pipe;
12523                 }
12524         }
12525
12526         /* No workaround needed? */
12527         if (!first_crtc_state)
12528                 return 0;
12529
12530         /* w/a possibly needed, check how many crtc's are already enabled. */
12531         for_each_intel_crtc(state->dev, intel_crtc) {
12532                 struct intel_crtc_state *pipe_config;
12533
12534                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12535                 if (IS_ERR(pipe_config))
12536                         return PTR_ERR(pipe_config);
12537
12538                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12539
12540                 if (!pipe_config->base.active ||
12541                     needs_modeset(&pipe_config->base))
12542                         continue;
12543
12544                 /* 2 or more enabled crtcs means no need for w/a */
12545                 if (enabled_pipe != INVALID_PIPE)
12546                         return 0;
12547
12548                 enabled_pipe = intel_crtc->pipe;
12549         }
12550
12551         if (enabled_pipe != INVALID_PIPE)
12552                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12553         else if (other_crtc_state)
12554                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12555
12556         return 0;
12557 }
12558
12559 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12560 {
12561         struct drm_crtc *crtc;
12562
12563         /* Add all pipes to the state */
12564         for_each_crtc(state->dev, crtc) {
12565                 struct drm_crtc_state *crtc_state;
12566
12567                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12568                 if (IS_ERR(crtc_state))
12569                         return PTR_ERR(crtc_state);
12570         }
12571
12572         return 0;
12573 }
12574
12575 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12576 {
12577         struct drm_crtc *crtc;
12578
12579         /*
12580          * Add all pipes to the state, and force
12581          * a modeset on all the active ones.
12582          */
12583         for_each_crtc(state->dev, crtc) {
12584                 struct drm_crtc_state *crtc_state;
12585                 int ret;
12586
12587                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12588                 if (IS_ERR(crtc_state))
12589                         return PTR_ERR(crtc_state);
12590
12591                 if (!crtc_state->active || needs_modeset(crtc_state))
12592                         continue;
12593
12594                 crtc_state->mode_changed = true;
12595
12596                 ret = drm_atomic_add_affected_connectors(state, crtc);
12597                 if (ret)
12598                         return ret;
12599
12600                 ret = drm_atomic_add_affected_planes(state, crtc);
12601                 if (ret)
12602                         return ret;
12603         }
12604
12605         return 0;
12606 }
12607
12608 static int intel_modeset_checks(struct drm_atomic_state *state)
12609 {
12610         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12611         struct drm_i915_private *dev_priv = to_i915(state->dev);
12612         struct drm_crtc *crtc;
12613         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12614         int ret = 0, i;
12615
12616         if (!check_digital_port_conflicts(state)) {
12617                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12618                 return -EINVAL;
12619         }
12620
12621         intel_state->modeset = true;
12622         intel_state->active_crtcs = dev_priv->active_crtcs;
12623         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12624         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12625
12626         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12627                 if (new_crtc_state->active)
12628                         intel_state->active_crtcs |= 1 << i;
12629                 else
12630                         intel_state->active_crtcs &= ~(1 << i);
12631
12632                 if (old_crtc_state->active != new_crtc_state->active)
12633                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12634         }
12635
12636         /*
12637          * See if the config requires any additional preparation, e.g.
12638          * to adjust global state with pipes off.  We need to do this
12639          * here so we can get the modeset_pipe updated config for the new
12640          * mode set on this crtc.  For other crtcs we need to use the
12641          * adjusted_mode bits in the crtc directly.
12642          */
12643         if (dev_priv->display.modeset_calc_cdclk) {
12644                 ret = dev_priv->display.modeset_calc_cdclk(state);
12645                 if (ret < 0)
12646                         return ret;
12647
12648                 /*
12649                  * Writes to dev_priv->cdclk.logical must protected by
12650                  * holding all the crtc locks, even if we don't end up
12651                  * touching the hardware
12652                  */
12653                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12654                                                &intel_state->cdclk.logical)) {
12655                         ret = intel_lock_all_pipes(state);
12656                         if (ret < 0)
12657                                 return ret;
12658                 }
12659
12660                 /* All pipes must be switched off while we change the cdclk. */
12661                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12662                                                &intel_state->cdclk.actual)) {
12663                         ret = intel_modeset_all_pipes(state);
12664                         if (ret < 0)
12665                                 return ret;
12666                 }
12667
12668                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12669                               intel_state->cdclk.logical.cdclk,
12670                               intel_state->cdclk.actual.cdclk);
12671         } else {
12672                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12673         }
12674
12675         intel_modeset_clear_plls(state);
12676
12677         if (IS_HASWELL(dev_priv))
12678                 return haswell_mode_set_planes_workaround(state);
12679
12680         return 0;
12681 }
12682
12683 /*
12684  * Handle calculation of various watermark data at the end of the atomic check
12685  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12686  * handlers to ensure that all derived state has been updated.
12687  */
12688 static int calc_watermark_data(struct drm_atomic_state *state)
12689 {
12690         struct drm_device *dev = state->dev;
12691         struct drm_i915_private *dev_priv = to_i915(dev);
12692
12693         /* Is there platform-specific watermark information to calculate? */
12694         if (dev_priv->display.compute_global_watermarks)
12695                 return dev_priv->display.compute_global_watermarks(state);
12696
12697         return 0;
12698 }
12699
12700 /**
12701  * intel_atomic_check - validate state object
12702  * @dev: drm device
12703  * @state: state to validate
12704  */
12705 static int intel_atomic_check(struct drm_device *dev,
12706                               struct drm_atomic_state *state)
12707 {
12708         struct drm_i915_private *dev_priv = to_i915(dev);
12709         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12710         struct drm_crtc *crtc;
12711         struct drm_crtc_state *old_crtc_state, *crtc_state;
12712         int ret, i;
12713         bool any_ms = false;
12714
12715         ret = drm_atomic_helper_check_modeset(dev, state);
12716         if (ret)
12717                 return ret;
12718
12719         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12720                 struct intel_crtc_state *pipe_config =
12721                         to_intel_crtc_state(crtc_state);
12722
12723                 /* Catch I915_MODE_FLAG_INHERITED */
12724                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12725                         crtc_state->mode_changed = true;
12726
12727                 if (!needs_modeset(crtc_state))
12728                         continue;
12729
12730                 if (!crtc_state->enable) {
12731                         any_ms = true;
12732                         continue;
12733                 }
12734
12735                 /* FIXME: For only active_changed we shouldn't need to do any
12736                  * state recomputation at all. */
12737
12738                 ret = drm_atomic_add_affected_connectors(state, crtc);
12739                 if (ret)
12740                         return ret;
12741
12742                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12743                 if (ret) {
12744                         intel_dump_pipe_config(to_intel_crtc(crtc),
12745                                                pipe_config, "[failed]");
12746                         return ret;
12747                 }
12748
12749                 if (i915.fastboot &&
12750                     intel_pipe_config_compare(dev_priv,
12751                                         to_intel_crtc_state(old_crtc_state),
12752                                         pipe_config, true)) {
12753                         crtc_state->mode_changed = false;
12754                         pipe_config->update_pipe = true;
12755                 }
12756
12757                 if (needs_modeset(crtc_state))
12758                         any_ms = true;
12759
12760                 ret = drm_atomic_add_affected_planes(state, crtc);
12761                 if (ret)
12762                         return ret;
12763
12764                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12765                                        needs_modeset(crtc_state) ?
12766                                        "[modeset]" : "[fastset]");
12767         }
12768
12769         if (any_ms) {
12770                 ret = intel_modeset_checks(state);
12771
12772                 if (ret)
12773                         return ret;
12774         } else {
12775                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12776         }
12777
12778         ret = drm_atomic_helper_check_planes(dev, state);
12779         if (ret)
12780                 return ret;
12781
12782         intel_fbc_choose_crtc(dev_priv, state);
12783         return calc_watermark_data(state);
12784 }
12785
12786 static int intel_atomic_prepare_commit(struct drm_device *dev,
12787                                        struct drm_atomic_state *state)
12788 {
12789         struct drm_i915_private *dev_priv = to_i915(dev);
12790         struct drm_crtc_state *crtc_state;
12791         struct drm_crtc *crtc;
12792         int i, ret;
12793
12794         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12795                 if (state->legacy_cursor_update)
12796                         continue;
12797
12798                 ret = intel_crtc_wait_for_pending_flips(crtc);
12799                 if (ret)
12800                         return ret;
12801
12802                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12803                         flush_workqueue(dev_priv->wq);
12804         }
12805
12806         ret = mutex_lock_interruptible(&dev->struct_mutex);
12807         if (ret)
12808                 return ret;
12809
12810         ret = drm_atomic_helper_prepare_planes(dev, state);
12811         mutex_unlock(&dev->struct_mutex);
12812
12813         return ret;
12814 }
12815
12816 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12817 {
12818         struct drm_device *dev = crtc->base.dev;
12819
12820         if (!dev->max_vblank_count)
12821                 return drm_crtc_accurate_vblank_count(&crtc->base);
12822
12823         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12824 }
12825
12826 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12827                                           struct drm_i915_private *dev_priv,
12828                                           unsigned crtc_mask)
12829 {
12830         unsigned last_vblank_count[I915_MAX_PIPES];
12831         enum pipe pipe;
12832         int ret;
12833
12834         if (!crtc_mask)
12835                 return;
12836
12837         for_each_pipe(dev_priv, pipe) {
12838                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12839                                                                   pipe);
12840
12841                 if (!((1 << pipe) & crtc_mask))
12842                         continue;
12843
12844                 ret = drm_crtc_vblank_get(&crtc->base);
12845                 if (WARN_ON(ret != 0)) {
12846                         crtc_mask &= ~(1 << pipe);
12847                         continue;
12848                 }
12849
12850                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12851         }
12852
12853         for_each_pipe(dev_priv, pipe) {
12854                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12855                                                                   pipe);
12856                 long lret;
12857
12858                 if (!((1 << pipe) & crtc_mask))
12859                         continue;
12860
12861                 lret = wait_event_timeout(dev->vblank[pipe].queue,
12862                                 last_vblank_count[pipe] !=
12863                                         drm_crtc_vblank_count(&crtc->base),
12864                                 msecs_to_jiffies(50));
12865
12866                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12867
12868                 drm_crtc_vblank_put(&crtc->base);
12869         }
12870 }
12871
12872 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12873 {
12874         /* fb updated, need to unpin old fb */
12875         if (crtc_state->fb_changed)
12876                 return true;
12877
12878         /* wm changes, need vblank before final wm's */
12879         if (crtc_state->update_wm_post)
12880                 return true;
12881
12882         if (crtc_state->wm.need_postvbl_update)
12883                 return true;
12884
12885         return false;
12886 }
12887
12888 static void intel_update_crtc(struct drm_crtc *crtc,
12889                               struct drm_atomic_state *state,
12890                               struct drm_crtc_state *old_crtc_state,
12891                               struct drm_crtc_state *new_crtc_state,
12892                               unsigned int *crtc_vblank_mask)
12893 {
12894         struct drm_device *dev = crtc->dev;
12895         struct drm_i915_private *dev_priv = to_i915(dev);
12896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12897         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12898         bool modeset = needs_modeset(new_crtc_state);
12899
12900         if (modeset) {
12901                 update_scanline_offset(intel_crtc);
12902                 dev_priv->display.crtc_enable(pipe_config, state);
12903         } else {
12904                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12905                                        pipe_config);
12906         }
12907
12908         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12909                 intel_fbc_enable(
12910                     intel_crtc, pipe_config,
12911                     to_intel_plane_state(crtc->primary->state));
12912         }
12913
12914         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12915
12916         if (needs_vblank_wait(pipe_config))
12917                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12918 }
12919
12920 static void intel_update_crtcs(struct drm_atomic_state *state,
12921                                unsigned int *crtc_vblank_mask)
12922 {
12923         struct drm_crtc *crtc;
12924         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12925         int i;
12926
12927         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12928                 if (!new_crtc_state->active)
12929                         continue;
12930
12931                 intel_update_crtc(crtc, state, old_crtc_state,
12932                                   new_crtc_state, crtc_vblank_mask);
12933         }
12934 }
12935
12936 static void skl_update_crtcs(struct drm_atomic_state *state,
12937                              unsigned int *crtc_vblank_mask)
12938 {
12939         struct drm_i915_private *dev_priv = to_i915(state->dev);
12940         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12941         struct drm_crtc *crtc;
12942         struct intel_crtc *intel_crtc;
12943         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12944         struct intel_crtc_state *cstate;
12945         unsigned int updated = 0;
12946         bool progress;
12947         enum pipe pipe;
12948         int i;
12949
12950         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12951
12952         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12953                 /* ignore allocations for crtc's that have been turned off. */
12954                 if (new_crtc_state->active)
12955                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12956
12957         /*
12958          * Whenever the number of active pipes changes, we need to make sure we
12959          * update the pipes in the right order so that their ddb allocations
12960          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12961          * cause pipe underruns and other bad stuff.
12962          */
12963         do {
12964                 progress = false;
12965
12966                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12967                         bool vbl_wait = false;
12968                         unsigned int cmask = drm_crtc_mask(crtc);
12969
12970                         intel_crtc = to_intel_crtc(crtc);
12971                         cstate = to_intel_crtc_state(crtc->state);
12972                         pipe = intel_crtc->pipe;
12973
12974                         if (updated & cmask || !cstate->base.active)
12975                                 continue;
12976
12977                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12978                                 continue;
12979
12980                         updated |= cmask;
12981                         entries[i] = &cstate->wm.skl.ddb;
12982
12983                         /*
12984                          * If this is an already active pipe, it's DDB changed,
12985                          * and this isn't the last pipe that needs updating
12986                          * then we need to wait for a vblank to pass for the
12987                          * new ddb allocation to take effect.
12988                          */
12989                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12990                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12991                             !new_crtc_state->active_changed &&
12992                             intel_state->wm_results.dirty_pipes != updated)
12993                                 vbl_wait = true;
12994
12995                         intel_update_crtc(crtc, state, old_crtc_state,
12996                                           new_crtc_state, crtc_vblank_mask);
12997
12998                         if (vbl_wait)
12999                                 intel_wait_for_vblank(dev_priv, pipe);
13000
13001                         progress = true;
13002                 }
13003         } while (progress);
13004 }
13005
13006 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
13007 {
13008         struct intel_atomic_state *state, *next;
13009         struct llist_node *freed;
13010
13011         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
13012         llist_for_each_entry_safe(state, next, freed, freed)
13013                 drm_atomic_state_put(&state->base);
13014 }
13015
13016 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
13017 {
13018         struct drm_i915_private *dev_priv =
13019                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
13020
13021         intel_atomic_helper_free_state(dev_priv);
13022 }
13023
13024 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13025 {
13026         struct drm_device *dev = state->dev;
13027         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13028         struct drm_i915_private *dev_priv = to_i915(dev);
13029         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13030         struct drm_crtc *crtc;
13031         struct intel_crtc_state *intel_cstate;
13032         bool hw_check = intel_state->modeset;
13033         u64 put_domains[I915_MAX_PIPES] = {};
13034         unsigned crtc_vblank_mask = 0;
13035         int i;
13036
13037         drm_atomic_helper_wait_for_dependencies(state);
13038
13039         if (intel_state->modeset)
13040                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13041
13042         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13043                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13044
13045                 if (needs_modeset(new_crtc_state) ||
13046                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
13047                         hw_check = true;
13048
13049                         put_domains[to_intel_crtc(crtc)->pipe] =
13050                                 modeset_get_crtc_power_domains(crtc,
13051                                         to_intel_crtc_state(new_crtc_state));
13052                 }
13053
13054                 if (!needs_modeset(new_crtc_state))
13055                         continue;
13056
13057                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
13058                                        to_intel_crtc_state(new_crtc_state));
13059
13060                 if (old_crtc_state->active) {
13061                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13062                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
13063                         intel_crtc->active = false;
13064                         intel_fbc_disable(intel_crtc);
13065                         intel_disable_shared_dpll(intel_crtc);
13066
13067                         /*
13068                          * Underruns don't always raise
13069                          * interrupts, so check manually.
13070                          */
13071                         intel_check_cpu_fifo_underruns(dev_priv);
13072                         intel_check_pch_fifo_underruns(dev_priv);
13073
13074                         if (!crtc->state->active) {
13075                                 /*
13076                                  * Make sure we don't call initial_watermarks
13077                                  * for ILK-style watermark updates.
13078                                  *
13079                                  * No clue what this is supposed to achieve.
13080                                  */
13081                                 if (INTEL_GEN(dev_priv) >= 9)
13082                                         dev_priv->display.initial_watermarks(intel_state,
13083                                                                              to_intel_crtc_state(crtc->state));
13084                         }
13085                 }
13086         }
13087
13088         /* Only after disabling all output pipelines that will be changed can we
13089          * update the the output configuration. */
13090         intel_modeset_update_crtc_state(state);
13091
13092         if (intel_state->modeset) {
13093                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13094
13095                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
13096
13097                 /*
13098                  * SKL workaround: bspec recommends we disable the SAGV when we
13099                  * have more then one pipe enabled
13100                  */
13101                 if (!intel_can_enable_sagv(state))
13102                         intel_disable_sagv(dev_priv);
13103
13104                 intel_modeset_verify_disabled(dev, state);
13105         }
13106
13107         /* Complete the events for pipes that have now been disabled */
13108         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13109                 bool modeset = needs_modeset(new_crtc_state);
13110
13111                 /* Complete events for now disable pipes here. */
13112                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
13113                         spin_lock_irq(&dev->event_lock);
13114                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
13115                         spin_unlock_irq(&dev->event_lock);
13116
13117                         new_crtc_state->event = NULL;
13118                 }
13119         }
13120
13121         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13122         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
13123
13124         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13125          * already, but still need the state for the delayed optimization. To
13126          * fix this:
13127          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13128          * - schedule that vblank worker _before_ calling hw_done
13129          * - at the start of commit_tail, cancel it _synchrously
13130          * - switch over to the vblank wait helper in the core after that since
13131          *   we don't need out special handling any more.
13132          */
13133         if (!state->legacy_cursor_update)
13134                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13135
13136         /*
13137          * Now that the vblank has passed, we can go ahead and program the
13138          * optimal watermarks on platforms that need two-step watermark
13139          * programming.
13140          *
13141          * TODO: Move this (and other cleanup) to an async worker eventually.
13142          */
13143         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13144                 intel_cstate = to_intel_crtc_state(new_crtc_state);
13145
13146                 if (dev_priv->display.optimize_watermarks)
13147                         dev_priv->display.optimize_watermarks(intel_state,
13148                                                               intel_cstate);
13149         }
13150
13151         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13152                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13153
13154                 if (put_domains[i])
13155                         modeset_put_power_domains(dev_priv, put_domains[i]);
13156
13157                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13158         }
13159
13160         if (intel_state->modeset && intel_can_enable_sagv(state))
13161                 intel_enable_sagv(dev_priv);
13162
13163         drm_atomic_helper_commit_hw_done(state);
13164
13165         if (intel_state->modeset) {
13166                 /* As one of the primary mmio accessors, KMS has a high
13167                  * likelihood of triggering bugs in unclaimed access. After we
13168                  * finish modesetting, see if an error has been flagged, and if
13169                  * so enable debugging for the next modeset - and hope we catch
13170                  * the culprit.
13171                  */
13172                 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13173                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13174         }
13175
13176         mutex_lock(&dev->struct_mutex);
13177         drm_atomic_helper_cleanup_planes(dev, state);
13178         mutex_unlock(&dev->struct_mutex);
13179
13180         drm_atomic_helper_commit_cleanup_done(state);
13181
13182         drm_atomic_state_put(state);
13183
13184         intel_atomic_helper_free_state(dev_priv);
13185 }
13186
13187 static void intel_atomic_commit_work(struct work_struct *work)
13188 {
13189         struct drm_atomic_state *state =
13190                 container_of(work, struct drm_atomic_state, commit_work);
13191
13192         intel_atomic_commit_tail(state);
13193 }
13194
13195 static int __i915_sw_fence_call
13196 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13197                           enum i915_sw_fence_notify notify)
13198 {
13199         struct intel_atomic_state *state =
13200                 container_of(fence, struct intel_atomic_state, commit_ready);
13201
13202         switch (notify) {
13203         case FENCE_COMPLETE:
13204                 if (state->base.commit_work.func)
13205                         queue_work(system_unbound_wq, &state->base.commit_work);
13206                 break;
13207
13208         case FENCE_FREE:
13209                 {
13210                         struct intel_atomic_helper *helper =
13211                                 &to_i915(state->base.dev)->atomic_helper;
13212
13213                         if (llist_add(&state->freed, &helper->free_list))
13214                                 schedule_work(&helper->free_work);
13215                         break;
13216                 }
13217         }
13218
13219         return NOTIFY_DONE;
13220 }
13221
13222 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13223 {
13224         struct drm_plane_state *old_plane_state, *new_plane_state;
13225         struct drm_plane *plane;
13226         int i;
13227
13228         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13229                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13230                                   intel_fb_obj(new_plane_state->fb),
13231                                   to_intel_plane(plane)->frontbuffer_bit);
13232 }
13233
13234 /**
13235  * intel_atomic_commit - commit validated state object
13236  * @dev: DRM device
13237  * @state: the top-level driver state object
13238  * @nonblock: nonblocking commit
13239  *
13240  * This function commits a top-level state object that has been validated
13241  * with drm_atomic_helper_check().
13242  *
13243  * RETURNS
13244  * Zero for success or -errno.
13245  */
13246 static int intel_atomic_commit(struct drm_device *dev,
13247                                struct drm_atomic_state *state,
13248                                bool nonblock)
13249 {
13250         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13251         struct drm_i915_private *dev_priv = to_i915(dev);
13252         int ret = 0;
13253
13254         ret = drm_atomic_helper_setup_commit(state, nonblock);
13255         if (ret)
13256                 return ret;
13257
13258         drm_atomic_state_get(state);
13259         i915_sw_fence_init(&intel_state->commit_ready,
13260                            intel_atomic_commit_ready);
13261
13262         ret = intel_atomic_prepare_commit(dev, state);
13263         if (ret) {
13264                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13265                 i915_sw_fence_commit(&intel_state->commit_ready);
13266                 return ret;
13267         }
13268
13269         /*
13270          * The intel_legacy_cursor_update() fast path takes care
13271          * of avoiding the vblank waits for simple cursor
13272          * movement and flips. For cursor on/off and size changes,
13273          * we want to perform the vblank waits so that watermark
13274          * updates happen during the correct frames. Gen9+ have
13275          * double buffered watermarks and so shouldn't need this.
13276          *
13277          * Do this after drm_atomic_helper_setup_commit() and
13278          * intel_atomic_prepare_commit() because we still want
13279          * to skip the flip and fb cleanup waits. Although that
13280          * does risk yanking the mapping from under the display
13281          * engine.
13282          *
13283          * FIXME doing watermarks and fb cleanup from a vblank worker
13284          * (assuming we had any) would solve these problems.
13285          */
13286         if (INTEL_GEN(dev_priv) < 9)
13287                 state->legacy_cursor_update = false;
13288
13289         ret = drm_atomic_helper_swap_state(state, true);
13290         if (ret) {
13291                 i915_sw_fence_commit(&intel_state->commit_ready);
13292
13293                 mutex_lock(&dev->struct_mutex);
13294                 drm_atomic_helper_cleanup_planes(dev, state);
13295                 mutex_unlock(&dev->struct_mutex);
13296                 return ret;
13297         }
13298         dev_priv->wm.distrust_bios_wm = false;
13299         intel_shared_dpll_swap_state(state);
13300         intel_atomic_track_fbs(state);
13301
13302         if (intel_state->modeset) {
13303                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13304                        sizeof(intel_state->min_pixclk));
13305                 dev_priv->active_crtcs = intel_state->active_crtcs;
13306                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13307                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13308         }
13309
13310         drm_atomic_state_get(state);
13311         INIT_WORK(&state->commit_work,
13312                   nonblock ? intel_atomic_commit_work : NULL);
13313
13314         i915_sw_fence_commit(&intel_state->commit_ready);
13315         if (!nonblock) {
13316                 i915_sw_fence_wait(&intel_state->commit_ready);
13317                 intel_atomic_commit_tail(state);
13318         }
13319
13320         return 0;
13321 }
13322
13323 static const struct drm_crtc_funcs intel_crtc_funcs = {
13324         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13325         .set_config = drm_atomic_helper_set_config,
13326         .set_property = drm_atomic_helper_crtc_set_property,
13327         .destroy = intel_crtc_destroy,
13328         .page_flip = drm_atomic_helper_page_flip,
13329         .atomic_duplicate_state = intel_crtc_duplicate_state,
13330         .atomic_destroy_state = intel_crtc_destroy_state,
13331         .set_crc_source = intel_crtc_set_crc_source,
13332 };
13333
13334 /**
13335  * intel_prepare_plane_fb - Prepare fb for usage on plane
13336  * @plane: drm plane to prepare for
13337  * @fb: framebuffer to prepare for presentation
13338  *
13339  * Prepares a framebuffer for usage on a display plane.  Generally this
13340  * involves pinning the underlying object and updating the frontbuffer tracking
13341  * bits.  Some older platforms need special physical address handling for
13342  * cursor planes.
13343  *
13344  * Must be called with struct_mutex held.
13345  *
13346  * Returns 0 on success, negative error code on failure.
13347  */
13348 int
13349 intel_prepare_plane_fb(struct drm_plane *plane,
13350                        struct drm_plane_state *new_state)
13351 {
13352         struct intel_atomic_state *intel_state =
13353                 to_intel_atomic_state(new_state->state);
13354         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13355         struct drm_framebuffer *fb = new_state->fb;
13356         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13357         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13358         int ret;
13359
13360         if (obj) {
13361                 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13362                     INTEL_INFO(dev_priv)->cursor_needs_physical) {
13363                         const int align = intel_cursor_alignment(dev_priv);
13364
13365                         ret = i915_gem_object_attach_phys(obj, align);
13366                         if (ret) {
13367                                 DRM_DEBUG_KMS("failed to attach phys object\n");
13368                                 return ret;
13369                         }
13370                 } else {
13371                         struct i915_vma *vma;
13372
13373                         vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13374                         if (IS_ERR(vma)) {
13375                                 DRM_DEBUG_KMS("failed to pin object\n");
13376                                 return PTR_ERR(vma);
13377                         }
13378
13379                         to_intel_plane_state(new_state)->vma = vma;
13380                 }
13381         }
13382
13383         if (!obj && !old_obj)
13384                 return 0;
13385
13386         if (old_obj) {
13387                 struct drm_crtc_state *crtc_state =
13388                         drm_atomic_get_existing_crtc_state(new_state->state,
13389                                                            plane->state->crtc);
13390
13391                 /* Big Hammer, we also need to ensure that any pending
13392                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13393                  * current scanout is retired before unpinning the old
13394                  * framebuffer. Note that we rely on userspace rendering
13395                  * into the buffer attached to the pipe they are waiting
13396                  * on. If not, userspace generates a GPU hang with IPEHR
13397                  * point to the MI_WAIT_FOR_EVENT.
13398                  *
13399                  * This should only fail upon a hung GPU, in which case we
13400                  * can safely continue.
13401                  */
13402                 if (needs_modeset(crtc_state)) {
13403                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13404                                                               old_obj->resv, NULL,
13405                                                               false, 0,
13406                                                               GFP_KERNEL);
13407                         if (ret < 0)
13408                                 return ret;
13409                 }
13410         }
13411
13412         if (new_state->fence) { /* explicit fencing */
13413                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13414                                                     new_state->fence,
13415                                                     I915_FENCE_TIMEOUT,
13416                                                     GFP_KERNEL);
13417                 if (ret < 0)
13418                         return ret;
13419         }
13420
13421         if (!obj)
13422                 return 0;
13423
13424         if (!new_state->fence) { /* implicit fencing */
13425                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13426                                                       obj->resv, NULL,
13427                                                       false, I915_FENCE_TIMEOUT,
13428                                                       GFP_KERNEL);
13429                 if (ret < 0)
13430                         return ret;
13431
13432                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13433         }
13434
13435         return 0;
13436 }
13437
13438 /**
13439  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13440  * @plane: drm plane to clean up for
13441  * @fb: old framebuffer that was on plane
13442  *
13443  * Cleans up a framebuffer that has just been removed from a plane.
13444  *
13445  * Must be called with struct_mutex held.
13446  */
13447 void
13448 intel_cleanup_plane_fb(struct drm_plane *plane,
13449                        struct drm_plane_state *old_state)
13450 {
13451         struct i915_vma *vma;
13452
13453         /* Should only be called after a successful intel_prepare_plane_fb()! */
13454         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13455         if (vma)
13456                 intel_unpin_fb_vma(vma);
13457 }
13458
13459 int
13460 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13461 {
13462         struct drm_i915_private *dev_priv;
13463         int max_scale;
13464         int crtc_clock, max_dotclk;
13465
13466         if (!intel_crtc || !crtc_state->base.enable)
13467                 return DRM_PLANE_HELPER_NO_SCALING;
13468
13469         dev_priv = to_i915(intel_crtc->base.dev);
13470
13471         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13472         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13473
13474         if (IS_GEMINILAKE(dev_priv))
13475                 max_dotclk *= 2;
13476
13477         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13478                 return DRM_PLANE_HELPER_NO_SCALING;
13479
13480         /*
13481          * skl max scale is lower of:
13482          *    close to 3 but not 3, -1 is for that purpose
13483          *            or
13484          *    cdclk/crtc_clock
13485          */
13486         max_scale = min((1 << 16) * 3 - 1,
13487                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13488
13489         return max_scale;
13490 }
13491
13492 static int
13493 intel_check_primary_plane(struct intel_plane *plane,
13494                           struct intel_crtc_state *crtc_state,
13495                           struct intel_plane_state *state)
13496 {
13497         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13498         struct drm_crtc *crtc = state->base.crtc;
13499         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13500         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13501         bool can_position = false;
13502         int ret;
13503
13504         if (INTEL_GEN(dev_priv) >= 9) {
13505                 /* use scaler when colorkey is not required */
13506                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13507                         min_scale = 1;
13508                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13509                 }
13510                 can_position = true;
13511         }
13512
13513         ret = drm_plane_helper_check_state(&state->base,
13514                                            &state->clip,
13515                                            min_scale, max_scale,
13516                                            can_position, true);
13517         if (ret)
13518                 return ret;
13519
13520         if (!state->base.fb)
13521                 return 0;
13522
13523         if (INTEL_GEN(dev_priv) >= 9) {
13524                 ret = skl_check_plane_surface(state);
13525                 if (ret)
13526                         return ret;
13527
13528                 state->ctl = skl_plane_ctl(crtc_state, state);
13529         } else {
13530                 ret = i9xx_check_plane_surface(state);
13531                 if (ret)
13532                         return ret;
13533
13534                 state->ctl = i9xx_plane_ctl(crtc_state, state);
13535         }
13536
13537         return 0;
13538 }
13539
13540 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13541                                     struct drm_crtc_state *old_crtc_state)
13542 {
13543         struct drm_device *dev = crtc->dev;
13544         struct drm_i915_private *dev_priv = to_i915(dev);
13545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13546         struct intel_crtc_state *intel_cstate =
13547                 to_intel_crtc_state(crtc->state);
13548         struct intel_crtc_state *old_intel_cstate =
13549                 to_intel_crtc_state(old_crtc_state);
13550         struct intel_atomic_state *old_intel_state =
13551                 to_intel_atomic_state(old_crtc_state->state);
13552         bool modeset = needs_modeset(crtc->state);
13553
13554         if (!modeset &&
13555             (intel_cstate->base.color_mgmt_changed ||
13556              intel_cstate->update_pipe)) {
13557                 intel_color_set_csc(crtc->state);
13558                 intel_color_load_luts(crtc->state);
13559         }
13560
13561         /* Perform vblank evasion around commit operation */
13562         intel_pipe_update_start(intel_crtc);
13563
13564         if (modeset)
13565                 goto out;
13566
13567         if (intel_cstate->update_pipe)
13568                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13569         else if (INTEL_GEN(dev_priv) >= 9)
13570                 skl_detach_scalers(intel_crtc);
13571
13572 out:
13573         if (dev_priv->display.atomic_update_watermarks)
13574                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13575                                                            intel_cstate);
13576 }
13577
13578 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13579                                      struct drm_crtc_state *old_crtc_state)
13580 {
13581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13582
13583         intel_pipe_update_end(intel_crtc, NULL);
13584 }
13585
13586 /**
13587  * intel_plane_destroy - destroy a plane
13588  * @plane: plane to destroy
13589  *
13590  * Common destruction function for all types of planes (primary, cursor,
13591  * sprite).
13592  */
13593 void intel_plane_destroy(struct drm_plane *plane)
13594 {
13595         drm_plane_cleanup(plane);
13596         kfree(to_intel_plane(plane));
13597 }
13598
13599 const struct drm_plane_funcs intel_plane_funcs = {
13600         .update_plane = drm_atomic_helper_update_plane,
13601         .disable_plane = drm_atomic_helper_disable_plane,
13602         .destroy = intel_plane_destroy,
13603         .set_property = drm_atomic_helper_plane_set_property,
13604         .atomic_get_property = intel_plane_atomic_get_property,
13605         .atomic_set_property = intel_plane_atomic_set_property,
13606         .atomic_duplicate_state = intel_plane_duplicate_state,
13607         .atomic_destroy_state = intel_plane_destroy_state,
13608 };
13609
13610 static int
13611 intel_legacy_cursor_update(struct drm_plane *plane,
13612                            struct drm_crtc *crtc,
13613                            struct drm_framebuffer *fb,
13614                            int crtc_x, int crtc_y,
13615                            unsigned int crtc_w, unsigned int crtc_h,
13616                            uint32_t src_x, uint32_t src_y,
13617                            uint32_t src_w, uint32_t src_h,
13618                            struct drm_modeset_acquire_ctx *ctx)
13619 {
13620         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13621         int ret;
13622         struct drm_plane_state *old_plane_state, *new_plane_state;
13623         struct intel_plane *intel_plane = to_intel_plane(plane);
13624         struct drm_framebuffer *old_fb;
13625         struct drm_crtc_state *crtc_state = crtc->state;
13626         struct i915_vma *old_vma;
13627
13628         /*
13629          * When crtc is inactive or there is a modeset pending,
13630          * wait for it to complete in the slowpath
13631          */
13632         if (!crtc_state->active || needs_modeset(crtc_state) ||
13633             to_intel_crtc_state(crtc_state)->update_pipe)
13634                 goto slow;
13635
13636         old_plane_state = plane->state;
13637
13638         /*
13639          * If any parameters change that may affect watermarks,
13640          * take the slowpath. Only changing fb or position should be
13641          * in the fastpath.
13642          */
13643         if (old_plane_state->crtc != crtc ||
13644             old_plane_state->src_w != src_w ||
13645             old_plane_state->src_h != src_h ||
13646             old_plane_state->crtc_w != crtc_w ||
13647             old_plane_state->crtc_h != crtc_h ||
13648             !old_plane_state->fb != !fb)
13649                 goto slow;
13650
13651         new_plane_state = intel_plane_duplicate_state(plane);
13652         if (!new_plane_state)
13653                 return -ENOMEM;
13654
13655         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13656
13657         new_plane_state->src_x = src_x;
13658         new_plane_state->src_y = src_y;
13659         new_plane_state->src_w = src_w;
13660         new_plane_state->src_h = src_h;
13661         new_plane_state->crtc_x = crtc_x;
13662         new_plane_state->crtc_y = crtc_y;
13663         new_plane_state->crtc_w = crtc_w;
13664         new_plane_state->crtc_h = crtc_h;
13665
13666         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13667                                                   to_intel_plane_state(new_plane_state));
13668         if (ret)
13669                 goto out_free;
13670
13671         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13672         if (ret)
13673                 goto out_free;
13674
13675         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13676                 int align = intel_cursor_alignment(dev_priv);
13677
13678                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13679                 if (ret) {
13680                         DRM_DEBUG_KMS("failed to attach phys object\n");
13681                         goto out_unlock;
13682                 }
13683         } else {
13684                 struct i915_vma *vma;
13685
13686                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13687                 if (IS_ERR(vma)) {
13688                         DRM_DEBUG_KMS("failed to pin object\n");
13689
13690                         ret = PTR_ERR(vma);
13691                         goto out_unlock;
13692                 }
13693
13694                 to_intel_plane_state(new_plane_state)->vma = vma;
13695         }
13696
13697         old_fb = old_plane_state->fb;
13698         old_vma = to_intel_plane_state(old_plane_state)->vma;
13699
13700         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13701                           intel_plane->frontbuffer_bit);
13702
13703         /* Swap plane state */
13704         new_plane_state->fence = old_plane_state->fence;
13705         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13706         new_plane_state->fence = NULL;
13707         new_plane_state->fb = old_fb;
13708         to_intel_plane_state(new_plane_state)->vma = old_vma;
13709
13710         if (plane->state->visible) {
13711                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13712                 intel_plane->update_plane(intel_plane,
13713                                           to_intel_crtc_state(crtc->state),
13714                                           to_intel_plane_state(plane->state));
13715         } else {
13716                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13717                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13718         }
13719
13720         intel_cleanup_plane_fb(plane, new_plane_state);
13721
13722 out_unlock:
13723         mutex_unlock(&dev_priv->drm.struct_mutex);
13724 out_free:
13725         intel_plane_destroy_state(plane, new_plane_state);
13726         return ret;
13727
13728 slow:
13729         return drm_atomic_helper_update_plane(plane, crtc, fb,
13730                                               crtc_x, crtc_y, crtc_w, crtc_h,
13731                                               src_x, src_y, src_w, src_h, ctx);
13732 }
13733
13734 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13735         .update_plane = intel_legacy_cursor_update,
13736         .disable_plane = drm_atomic_helper_disable_plane,
13737         .destroy = intel_plane_destroy,
13738         .set_property = drm_atomic_helper_plane_set_property,
13739         .atomic_get_property = intel_plane_atomic_get_property,
13740         .atomic_set_property = intel_plane_atomic_set_property,
13741         .atomic_duplicate_state = intel_plane_duplicate_state,
13742         .atomic_destroy_state = intel_plane_destroy_state,
13743 };
13744
13745 static struct intel_plane *
13746 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13747 {
13748         struct intel_plane *primary = NULL;
13749         struct intel_plane_state *state = NULL;
13750         const uint32_t *intel_primary_formats;
13751         unsigned int supported_rotations;
13752         unsigned int num_formats;
13753         int ret;
13754
13755         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13756         if (!primary) {
13757                 ret = -ENOMEM;
13758                 goto fail;
13759         }
13760
13761         state = intel_create_plane_state(&primary->base);
13762         if (!state) {
13763                 ret = -ENOMEM;
13764                 goto fail;
13765         }
13766
13767         primary->base.state = &state->base;
13768
13769         primary->can_scale = false;
13770         primary->max_downscale = 1;
13771         if (INTEL_GEN(dev_priv) >= 9) {
13772                 primary->can_scale = true;
13773                 state->scaler_id = -1;
13774         }
13775         primary->pipe = pipe;
13776         /*
13777          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13778          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13779          */
13780         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13781                 primary->plane = (enum plane) !pipe;
13782         else
13783                 primary->plane = (enum plane) pipe;
13784         primary->id = PLANE_PRIMARY;
13785         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13786         primary->check_plane = intel_check_primary_plane;
13787
13788         if (INTEL_GEN(dev_priv) >= 9) {
13789                 intel_primary_formats = skl_primary_formats;
13790                 num_formats = ARRAY_SIZE(skl_primary_formats);
13791
13792                 primary->update_plane = skylake_update_primary_plane;
13793                 primary->disable_plane = skylake_disable_primary_plane;
13794         } else if (INTEL_GEN(dev_priv) >= 4) {
13795                 intel_primary_formats = i965_primary_formats;
13796                 num_formats = ARRAY_SIZE(i965_primary_formats);
13797
13798                 primary->update_plane = i9xx_update_primary_plane;
13799                 primary->disable_plane = i9xx_disable_primary_plane;
13800         } else {
13801                 intel_primary_formats = i8xx_primary_formats;
13802                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13803
13804                 primary->update_plane = i9xx_update_primary_plane;
13805                 primary->disable_plane = i9xx_disable_primary_plane;
13806         }
13807
13808         if (INTEL_GEN(dev_priv) >= 9)
13809                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13810                                                0, &intel_plane_funcs,
13811                                                intel_primary_formats, num_formats,
13812                                                NULL,
13813                                                DRM_PLANE_TYPE_PRIMARY,
13814                                                "plane 1%c", pipe_name(pipe));
13815         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13816                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13817                                                0, &intel_plane_funcs,
13818                                                intel_primary_formats, num_formats,
13819                                                NULL,
13820                                                DRM_PLANE_TYPE_PRIMARY,
13821                                                "primary %c", pipe_name(pipe));
13822         else
13823                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13824                                                0, &intel_plane_funcs,
13825                                                intel_primary_formats, num_formats,
13826                                                NULL,
13827                                                DRM_PLANE_TYPE_PRIMARY,
13828                                                "plane %c", plane_name(primary->plane));
13829         if (ret)
13830                 goto fail;
13831
13832         if (INTEL_GEN(dev_priv) >= 9) {
13833                 supported_rotations =
13834                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13835                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13836         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13837                 supported_rotations =
13838                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13839                         DRM_MODE_REFLECT_X;
13840         } else if (INTEL_GEN(dev_priv) >= 4) {
13841                 supported_rotations =
13842                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13843         } else {
13844                 supported_rotations = DRM_MODE_ROTATE_0;
13845         }
13846
13847         if (INTEL_GEN(dev_priv) >= 4)
13848                 drm_plane_create_rotation_property(&primary->base,
13849                                                    DRM_MODE_ROTATE_0,
13850                                                    supported_rotations);
13851
13852         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13853
13854         return primary;
13855
13856 fail:
13857         kfree(state);
13858         kfree(primary);
13859
13860         return ERR_PTR(ret);
13861 }
13862
13863 static struct intel_plane *
13864 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13865                           enum pipe pipe)
13866 {
13867         struct intel_plane *cursor = NULL;
13868         struct intel_plane_state *state = NULL;
13869         int ret;
13870
13871         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13872         if (!cursor) {
13873                 ret = -ENOMEM;
13874                 goto fail;
13875         }
13876
13877         state = intel_create_plane_state(&cursor->base);
13878         if (!state) {
13879                 ret = -ENOMEM;
13880                 goto fail;
13881         }
13882
13883         cursor->base.state = &state->base;
13884
13885         cursor->can_scale = false;
13886         cursor->max_downscale = 1;
13887         cursor->pipe = pipe;
13888         cursor->plane = pipe;
13889         cursor->id = PLANE_CURSOR;
13890         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13891
13892         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13893                 cursor->update_plane = i845_update_cursor;
13894                 cursor->disable_plane = i845_disable_cursor;
13895                 cursor->check_plane = i845_check_cursor;
13896         } else {
13897                 cursor->update_plane = i9xx_update_cursor;
13898                 cursor->disable_plane = i9xx_disable_cursor;
13899                 cursor->check_plane = i9xx_check_cursor;
13900         }
13901
13902         cursor->cursor.base = ~0;
13903         cursor->cursor.cntl = ~0;
13904
13905         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13906                 cursor->cursor.size = ~0;
13907
13908         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13909                                        0, &intel_cursor_plane_funcs,
13910                                        intel_cursor_formats,
13911                                        ARRAY_SIZE(intel_cursor_formats),
13912                                        NULL, DRM_PLANE_TYPE_CURSOR,
13913                                        "cursor %c", pipe_name(pipe));
13914         if (ret)
13915                 goto fail;
13916
13917         if (INTEL_GEN(dev_priv) >= 4)
13918                 drm_plane_create_rotation_property(&cursor->base,
13919                                                    DRM_MODE_ROTATE_0,
13920                                                    DRM_MODE_ROTATE_0 |
13921                                                    DRM_MODE_ROTATE_180);
13922
13923         if (INTEL_GEN(dev_priv) >= 9)
13924                 state->scaler_id = -1;
13925
13926         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13927
13928         return cursor;
13929
13930 fail:
13931         kfree(state);
13932         kfree(cursor);
13933
13934         return ERR_PTR(ret);
13935 }
13936
13937 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13938                                     struct intel_crtc_state *crtc_state)
13939 {
13940         struct intel_crtc_scaler_state *scaler_state =
13941                 &crtc_state->scaler_state;
13942         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13943         int i;
13944
13945         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13946         if (!crtc->num_scalers)
13947                 return;
13948
13949         for (i = 0; i < crtc->num_scalers; i++) {
13950                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13951
13952                 scaler->in_use = 0;
13953                 scaler->mode = PS_SCALER_MODE_DYN;
13954         }
13955
13956         scaler_state->scaler_id = -1;
13957 }
13958
13959 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13960 {
13961         struct intel_crtc *intel_crtc;
13962         struct intel_crtc_state *crtc_state = NULL;
13963         struct intel_plane *primary = NULL;
13964         struct intel_plane *cursor = NULL;
13965         int sprite, ret;
13966
13967         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13968         if (!intel_crtc)
13969                 return -ENOMEM;
13970
13971         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13972         if (!crtc_state) {
13973                 ret = -ENOMEM;
13974                 goto fail;
13975         }
13976         intel_crtc->config = crtc_state;
13977         intel_crtc->base.state = &crtc_state->base;
13978         crtc_state->base.crtc = &intel_crtc->base;
13979
13980         primary = intel_primary_plane_create(dev_priv, pipe);
13981         if (IS_ERR(primary)) {
13982                 ret = PTR_ERR(primary);
13983                 goto fail;
13984         }
13985         intel_crtc->plane_ids_mask |= BIT(primary->id);
13986
13987         for_each_sprite(dev_priv, pipe, sprite) {
13988                 struct intel_plane *plane;
13989
13990                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13991                 if (IS_ERR(plane)) {
13992                         ret = PTR_ERR(plane);
13993                         goto fail;
13994                 }
13995                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13996         }
13997
13998         cursor = intel_cursor_plane_create(dev_priv, pipe);
13999         if (IS_ERR(cursor)) {
14000                 ret = PTR_ERR(cursor);
14001                 goto fail;
14002         }
14003         intel_crtc->plane_ids_mask |= BIT(cursor->id);
14004
14005         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
14006                                         &primary->base, &cursor->base,
14007                                         &intel_crtc_funcs,
14008                                         "pipe %c", pipe_name(pipe));
14009         if (ret)
14010                 goto fail;
14011
14012         intel_crtc->pipe = pipe;
14013         intel_crtc->plane = primary->plane;
14014
14015         /* initialize shared scalers */
14016         intel_crtc_init_scalers(intel_crtc, crtc_state);
14017
14018         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14019                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14020         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
14021         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
14022
14023         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14024
14025         intel_color_init(&intel_crtc->base);
14026
14027         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14028
14029         return 0;
14030
14031 fail:
14032         /*
14033          * drm_mode_config_cleanup() will free up any
14034          * crtcs/planes already initialized.
14035          */
14036         kfree(crtc_state);
14037         kfree(intel_crtc);
14038
14039         return ret;
14040 }
14041
14042 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14043 {
14044         struct drm_device *dev = connector->base.dev;
14045
14046         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14047
14048         if (!connector->base.state->crtc)
14049                 return INVALID_PIPE;
14050
14051         return to_intel_crtc(connector->base.state->crtc)->pipe;
14052 }
14053
14054 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14055                                 struct drm_file *file)
14056 {
14057         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14058         struct drm_crtc *drmmode_crtc;
14059         struct intel_crtc *crtc;
14060
14061         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14062         if (!drmmode_crtc)
14063                 return -ENOENT;
14064
14065         crtc = to_intel_crtc(drmmode_crtc);
14066         pipe_from_crtc_id->pipe = crtc->pipe;
14067
14068         return 0;
14069 }
14070
14071 static int intel_encoder_clones(struct intel_encoder *encoder)
14072 {
14073         struct drm_device *dev = encoder->base.dev;
14074         struct intel_encoder *source_encoder;
14075         int index_mask = 0;
14076         int entry = 0;
14077
14078         for_each_intel_encoder(dev, source_encoder) {
14079                 if (encoders_cloneable(encoder, source_encoder))
14080                         index_mask |= (1 << entry);
14081
14082                 entry++;
14083         }
14084
14085         return index_mask;
14086 }
14087
14088 static bool has_edp_a(struct drm_i915_private *dev_priv)
14089 {
14090         if (!IS_MOBILE(dev_priv))
14091                 return false;
14092
14093         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14094                 return false;
14095
14096         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14097                 return false;
14098
14099         return true;
14100 }
14101
14102 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14103 {
14104         if (INTEL_GEN(dev_priv) >= 9)
14105                 return false;
14106
14107         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14108                 return false;
14109
14110         if (IS_CHERRYVIEW(dev_priv))
14111                 return false;
14112
14113         if (HAS_PCH_LPT_H(dev_priv) &&
14114             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14115                 return false;
14116
14117         /* DDI E can't be used if DDI A requires 4 lanes */
14118         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14119                 return false;
14120
14121         if (!dev_priv->vbt.int_crt_support)
14122                 return false;
14123
14124         return true;
14125 }
14126
14127 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14128 {
14129         int pps_num;
14130         int pps_idx;
14131
14132         if (HAS_DDI(dev_priv))
14133                 return;
14134         /*
14135          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14136          * everywhere where registers can be write protected.
14137          */
14138         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14139                 pps_num = 2;
14140         else
14141                 pps_num = 1;
14142
14143         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14144                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14145
14146                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14147                 I915_WRITE(PP_CONTROL(pps_idx), val);
14148         }
14149 }
14150
14151 static void intel_pps_init(struct drm_i915_private *dev_priv)
14152 {
14153         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14154                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14155         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14156                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14157         else
14158                 dev_priv->pps_mmio_base = PPS_BASE;
14159
14160         intel_pps_unlock_regs_wa(dev_priv);
14161 }
14162
14163 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14164 {
14165         struct intel_encoder *encoder;
14166         bool dpd_is_edp = false;
14167
14168         intel_pps_init(dev_priv);
14169
14170         /*
14171          * intel_edp_init_connector() depends on this completing first, to
14172          * prevent the registeration of both eDP and LVDS and the incorrect
14173          * sharing of the PPS.
14174          */
14175         intel_lvds_init(dev_priv);
14176
14177         if (intel_crt_present(dev_priv))
14178                 intel_crt_init(dev_priv);
14179
14180         if (IS_GEN9_LP(dev_priv)) {
14181                 /*
14182                  * FIXME: Broxton doesn't support port detection via the
14183                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14184                  * detect the ports.
14185                  */
14186                 intel_ddi_init(dev_priv, PORT_A);
14187                 intel_ddi_init(dev_priv, PORT_B);
14188                 intel_ddi_init(dev_priv, PORT_C);
14189
14190                 intel_dsi_init(dev_priv);
14191         } else if (HAS_DDI(dev_priv)) {
14192                 int found;
14193
14194                 /*
14195                  * Haswell uses DDI functions to detect digital outputs.
14196                  * On SKL pre-D0 the strap isn't connected, so we assume
14197                  * it's there.
14198                  */
14199                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14200                 /* WaIgnoreDDIAStrap: skl */
14201                 if (found || IS_GEN9_BC(dev_priv))
14202                         intel_ddi_init(dev_priv, PORT_A);
14203
14204                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14205                  * register */
14206                 found = I915_READ(SFUSE_STRAP);
14207
14208                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14209                         intel_ddi_init(dev_priv, PORT_B);
14210                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14211                         intel_ddi_init(dev_priv, PORT_C);
14212                 if (found & SFUSE_STRAP_DDID_DETECTED)
14213                         intel_ddi_init(dev_priv, PORT_D);
14214                 /*
14215                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14216                  */
14217                 if (IS_GEN9_BC(dev_priv) &&
14218                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14219                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14220                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14221                         intel_ddi_init(dev_priv, PORT_E);
14222
14223         } else if (HAS_PCH_SPLIT(dev_priv)) {
14224                 int found;
14225                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14226
14227                 if (has_edp_a(dev_priv))
14228                         intel_dp_init(dev_priv, DP_A, PORT_A);
14229
14230                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14231                         /* PCH SDVOB multiplex with HDMIB */
14232                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14233                         if (!found)
14234                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14235                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14236                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14237                 }
14238
14239                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14240                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14241
14242                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14243                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14244
14245                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14246                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14247
14248                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14249                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14250         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14251                 bool has_edp, has_port;
14252
14253                 /*
14254                  * The DP_DETECTED bit is the latched state of the DDC
14255                  * SDA pin at boot. However since eDP doesn't require DDC
14256                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14257                  * eDP ports may have been muxed to an alternate function.
14258                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14259                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14260                  * detect eDP ports.
14261                  *
14262                  * Sadly the straps seem to be missing sometimes even for HDMI
14263                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14264                  * and VBT for the presence of the port. Additionally we can't
14265                  * trust the port type the VBT declares as we've seen at least
14266                  * HDMI ports that the VBT claim are DP or eDP.
14267                  */
14268                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14269                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14270                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14271                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14272                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14273                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14274
14275                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14276                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14277                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14278                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14279                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14280                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14281
14282                 if (IS_CHERRYVIEW(dev_priv)) {
14283                         /*
14284                          * eDP not supported on port D,
14285                          * so no need to worry about it
14286                          */
14287                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14288                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14289                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14290                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14291                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14292                 }
14293
14294                 intel_dsi_init(dev_priv);
14295         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14296                 bool found = false;
14297
14298                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14299                         DRM_DEBUG_KMS("probing SDVOB\n");
14300                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14301                         if (!found && IS_G4X(dev_priv)) {
14302                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14303                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14304                         }
14305
14306                         if (!found && IS_G4X(dev_priv))
14307                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14308                 }
14309
14310                 /* Before G4X SDVOC doesn't have its own detect register */
14311
14312                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14313                         DRM_DEBUG_KMS("probing SDVOC\n");
14314                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14315                 }
14316
14317                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14318
14319                         if (IS_G4X(dev_priv)) {
14320                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14321                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14322                         }
14323                         if (IS_G4X(dev_priv))
14324                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14325                 }
14326
14327                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14328                         intel_dp_init(dev_priv, DP_D, PORT_D);
14329         } else if (IS_GEN2(dev_priv))
14330                 intel_dvo_init(dev_priv);
14331
14332         if (SUPPORTS_TV(dev_priv))
14333                 intel_tv_init(dev_priv);
14334
14335         intel_psr_init(dev_priv);
14336
14337         for_each_intel_encoder(&dev_priv->drm, encoder) {
14338                 encoder->base.possible_crtcs = encoder->crtc_mask;
14339                 encoder->base.possible_clones =
14340                         intel_encoder_clones(encoder);
14341         }
14342
14343         intel_init_pch_refclk(dev_priv);
14344
14345         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14346 }
14347
14348 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14349 {
14350         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14351
14352         drm_framebuffer_cleanup(fb);
14353
14354         i915_gem_object_lock(intel_fb->obj);
14355         WARN_ON(!intel_fb->obj->framebuffer_references--);
14356         i915_gem_object_unlock(intel_fb->obj);
14357
14358         i915_gem_object_put(intel_fb->obj);
14359
14360         kfree(intel_fb);
14361 }
14362
14363 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14364                                                 struct drm_file *file,
14365                                                 unsigned int *handle)
14366 {
14367         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14368         struct drm_i915_gem_object *obj = intel_fb->obj;
14369
14370         if (obj->userptr.mm) {
14371                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14372                 return -EINVAL;
14373         }
14374
14375         return drm_gem_handle_create(file, &obj->base, handle);
14376 }
14377
14378 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14379                                         struct drm_file *file,
14380                                         unsigned flags, unsigned color,
14381                                         struct drm_clip_rect *clips,
14382                                         unsigned num_clips)
14383 {
14384         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14385
14386         i915_gem_object_flush_if_display(obj);
14387         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14388
14389         return 0;
14390 }
14391
14392 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14393         .destroy = intel_user_framebuffer_destroy,
14394         .create_handle = intel_user_framebuffer_create_handle,
14395         .dirty = intel_user_framebuffer_dirty,
14396 };
14397
14398 static
14399 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14400                          uint64_t fb_modifier, uint32_t pixel_format)
14401 {
14402         u32 gen = INTEL_GEN(dev_priv);
14403
14404         if (gen >= 9) {
14405                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14406
14407                 /* "The stride in bytes must not exceed the of the size of 8K
14408                  *  pixels and 32K bytes."
14409                  */
14410                 return min(8192 * cpp, 32768);
14411         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14412                 return 32*1024;
14413         } else if (gen >= 4) {
14414                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14415                         return 16*1024;
14416                 else
14417                         return 32*1024;
14418         } else if (gen >= 3) {
14419                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14420                         return 8*1024;
14421                 else
14422                         return 16*1024;
14423         } else {
14424                 /* XXX DSPC is limited to 4k tiled */
14425                 return 8*1024;
14426         }
14427 }
14428
14429 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14430                                   struct drm_i915_gem_object *obj,
14431                                   struct drm_mode_fb_cmd2 *mode_cmd)
14432 {
14433         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14434         struct drm_format_name_buf format_name;
14435         u32 pitch_limit, stride_alignment;
14436         unsigned int tiling, stride;
14437         int ret = -EINVAL;
14438
14439         i915_gem_object_lock(obj);
14440         obj->framebuffer_references++;
14441         tiling = i915_gem_object_get_tiling(obj);
14442         stride = i915_gem_object_get_stride(obj);
14443         i915_gem_object_unlock(obj);
14444
14445         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14446                 /*
14447                  * If there's a fence, enforce that
14448                  * the fb modifier and tiling mode match.
14449                  */
14450                 if (tiling != I915_TILING_NONE &&
14451                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14452                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14453                         goto err;
14454                 }
14455         } else {
14456                 if (tiling == I915_TILING_X) {
14457                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14458                 } else if (tiling == I915_TILING_Y) {
14459                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14460                         goto err;
14461                 }
14462         }
14463
14464         /* Passed in modifier sanity checking. */
14465         switch (mode_cmd->modifier[0]) {
14466         case I915_FORMAT_MOD_Y_TILED:
14467         case I915_FORMAT_MOD_Yf_TILED:
14468                 if (INTEL_GEN(dev_priv) < 9) {
14469                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14470                                       mode_cmd->modifier[0]);
14471                         goto err;
14472                 }
14473         case DRM_FORMAT_MOD_LINEAR:
14474         case I915_FORMAT_MOD_X_TILED:
14475                 break;
14476         default:
14477                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14478                               mode_cmd->modifier[0]);
14479                 goto err;
14480         }
14481
14482         /*
14483          * gen2/3 display engine uses the fence if present,
14484          * so the tiling mode must match the fb modifier exactly.
14485          */
14486         if (INTEL_INFO(dev_priv)->gen < 4 &&
14487             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14488                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14489                 goto err;
14490         }
14491
14492         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14493                                            mode_cmd->pixel_format);
14494         if (mode_cmd->pitches[0] > pitch_limit) {
14495                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14496                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14497                               "tiled" : "linear",
14498                               mode_cmd->pitches[0], pitch_limit);
14499                 goto err;
14500         }
14501
14502         /*
14503          * If there's a fence, enforce that
14504          * the fb pitch and fence stride match.
14505          */
14506         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14507                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14508                               mode_cmd->pitches[0], stride);
14509                 goto err;
14510         }
14511
14512         /* Reject formats not supported by any plane early. */
14513         switch (mode_cmd->pixel_format) {
14514         case DRM_FORMAT_C8:
14515         case DRM_FORMAT_RGB565:
14516         case DRM_FORMAT_XRGB8888:
14517         case DRM_FORMAT_ARGB8888:
14518                 break;
14519         case DRM_FORMAT_XRGB1555:
14520                 if (INTEL_GEN(dev_priv) > 3) {
14521                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14522                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14523                         goto err;
14524                 }
14525                 break;
14526         case DRM_FORMAT_ABGR8888:
14527                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14528                     INTEL_GEN(dev_priv) < 9) {
14529                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14530                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14531                         goto err;
14532                 }
14533                 break;
14534         case DRM_FORMAT_XBGR8888:
14535         case DRM_FORMAT_XRGB2101010:
14536         case DRM_FORMAT_XBGR2101010:
14537                 if (INTEL_GEN(dev_priv) < 4) {
14538                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14539                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14540                         goto err;
14541                 }
14542                 break;
14543         case DRM_FORMAT_ABGR2101010:
14544                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14545                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14546                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14547                         goto err;
14548                 }
14549                 break;
14550         case DRM_FORMAT_YUYV:
14551         case DRM_FORMAT_UYVY:
14552         case DRM_FORMAT_YVYU:
14553         case DRM_FORMAT_VYUY:
14554                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14555                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14556                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14557                         goto err;
14558                 }
14559                 break;
14560         default:
14561                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14562                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14563                 goto err;
14564         }
14565
14566         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14567         if (mode_cmd->offsets[0] != 0)
14568                 goto err;
14569
14570         drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14571                                        &intel_fb->base, mode_cmd);
14572
14573         stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14574         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14575                 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14576                               mode_cmd->pitches[0], stride_alignment);
14577                 goto err;
14578         }
14579
14580         intel_fb->obj = obj;
14581
14582         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14583         if (ret)
14584                 goto err;
14585
14586         ret = drm_framebuffer_init(obj->base.dev,
14587                                    &intel_fb->base,
14588                                    &intel_fb_funcs);
14589         if (ret) {
14590                 DRM_ERROR("framebuffer init failed %d\n", ret);
14591                 goto err;
14592         }
14593
14594         return 0;
14595
14596 err:
14597         i915_gem_object_lock(obj);
14598         obj->framebuffer_references--;
14599         i915_gem_object_unlock(obj);
14600         return ret;
14601 }
14602
14603 static struct drm_framebuffer *
14604 intel_user_framebuffer_create(struct drm_device *dev,
14605                               struct drm_file *filp,
14606                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14607 {
14608         struct drm_framebuffer *fb;
14609         struct drm_i915_gem_object *obj;
14610         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14611
14612         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14613         if (!obj)
14614                 return ERR_PTR(-ENOENT);
14615
14616         fb = intel_framebuffer_create(obj, &mode_cmd);
14617         if (IS_ERR(fb))
14618                 i915_gem_object_put(obj);
14619
14620         return fb;
14621 }
14622
14623 static void intel_atomic_state_free(struct drm_atomic_state *state)
14624 {
14625         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14626
14627         drm_atomic_state_default_release(state);
14628
14629         i915_sw_fence_fini(&intel_state->commit_ready);
14630
14631         kfree(state);
14632 }
14633
14634 static const struct drm_mode_config_funcs intel_mode_funcs = {
14635         .fb_create = intel_user_framebuffer_create,
14636         .output_poll_changed = intel_fbdev_output_poll_changed,
14637         .atomic_check = intel_atomic_check,
14638         .atomic_commit = intel_atomic_commit,
14639         .atomic_state_alloc = intel_atomic_state_alloc,
14640         .atomic_state_clear = intel_atomic_state_clear,
14641         .atomic_state_free = intel_atomic_state_free,
14642 };
14643
14644 /**
14645  * intel_init_display_hooks - initialize the display modesetting hooks
14646  * @dev_priv: device private
14647  */
14648 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14649 {
14650         intel_init_cdclk_hooks(dev_priv);
14651
14652         if (INTEL_INFO(dev_priv)->gen >= 9) {
14653                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14654                 dev_priv->display.get_initial_plane_config =
14655                         skylake_get_initial_plane_config;
14656                 dev_priv->display.crtc_compute_clock =
14657                         haswell_crtc_compute_clock;
14658                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14659                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14660         } else if (HAS_DDI(dev_priv)) {
14661                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14662                 dev_priv->display.get_initial_plane_config =
14663                         ironlake_get_initial_plane_config;
14664                 dev_priv->display.crtc_compute_clock =
14665                         haswell_crtc_compute_clock;
14666                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14667                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14668         } else if (HAS_PCH_SPLIT(dev_priv)) {
14669                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14670                 dev_priv->display.get_initial_plane_config =
14671                         ironlake_get_initial_plane_config;
14672                 dev_priv->display.crtc_compute_clock =
14673                         ironlake_crtc_compute_clock;
14674                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14675                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14676         } else if (IS_CHERRYVIEW(dev_priv)) {
14677                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14678                 dev_priv->display.get_initial_plane_config =
14679                         i9xx_get_initial_plane_config;
14680                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14681                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14682                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14683         } else if (IS_VALLEYVIEW(dev_priv)) {
14684                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14685                 dev_priv->display.get_initial_plane_config =
14686                         i9xx_get_initial_plane_config;
14687                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14688                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14689                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14690         } else if (IS_G4X(dev_priv)) {
14691                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14692                 dev_priv->display.get_initial_plane_config =
14693                         i9xx_get_initial_plane_config;
14694                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14695                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14696                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14697         } else if (IS_PINEVIEW(dev_priv)) {
14698                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14699                 dev_priv->display.get_initial_plane_config =
14700                         i9xx_get_initial_plane_config;
14701                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14702                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14703                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14704         } else if (!IS_GEN2(dev_priv)) {
14705                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14706                 dev_priv->display.get_initial_plane_config =
14707                         i9xx_get_initial_plane_config;
14708                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14709                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14710                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14711         } else {
14712                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14713                 dev_priv->display.get_initial_plane_config =
14714                         i9xx_get_initial_plane_config;
14715                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14716                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14717                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14718         }
14719
14720         if (IS_GEN5(dev_priv)) {
14721                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14722         } else if (IS_GEN6(dev_priv)) {
14723                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14724         } else if (IS_IVYBRIDGE(dev_priv)) {
14725                 /* FIXME: detect B0+ stepping and use auto training */
14726                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14727         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14728                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14729         }
14730
14731         if (dev_priv->info.gen >= 9)
14732                 dev_priv->display.update_crtcs = skl_update_crtcs;
14733         else
14734                 dev_priv->display.update_crtcs = intel_update_crtcs;
14735
14736         switch (INTEL_INFO(dev_priv)->gen) {
14737         case 2:
14738                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14739                 break;
14740
14741         case 3:
14742                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14743                 break;
14744
14745         case 4:
14746         case 5:
14747                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14748                 break;
14749
14750         case 6:
14751                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14752                 break;
14753         case 7:
14754         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14755                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14756                 break;
14757         case 9:
14758                 /* Drop through - unsupported since execlist only. */
14759         default:
14760                 /* Default just returns -ENODEV to indicate unsupported */
14761                 dev_priv->display.queue_flip = intel_default_queue_flip;
14762         }
14763 }
14764
14765 /*
14766  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14767  */
14768 static void quirk_ssc_force_disable(struct drm_device *dev)
14769 {
14770         struct drm_i915_private *dev_priv = to_i915(dev);
14771         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14772         DRM_INFO("applying lvds SSC disable quirk\n");
14773 }
14774
14775 /*
14776  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14777  * brightness value
14778  */
14779 static void quirk_invert_brightness(struct drm_device *dev)
14780 {
14781         struct drm_i915_private *dev_priv = to_i915(dev);
14782         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14783         DRM_INFO("applying inverted panel brightness quirk\n");
14784 }
14785
14786 /* Some VBT's incorrectly indicate no backlight is present */
14787 static void quirk_backlight_present(struct drm_device *dev)
14788 {
14789         struct drm_i915_private *dev_priv = to_i915(dev);
14790         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14791         DRM_INFO("applying backlight present quirk\n");
14792 }
14793
14794 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14795  * which is 300 ms greater than eDP spec T12 min.
14796  */
14797 static void quirk_increase_t12_delay(struct drm_device *dev)
14798 {
14799         struct drm_i915_private *dev_priv = to_i915(dev);
14800
14801         dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14802         DRM_INFO("Applying T12 delay quirk\n");
14803 }
14804
14805 struct intel_quirk {
14806         int device;
14807         int subsystem_vendor;
14808         int subsystem_device;
14809         void (*hook)(struct drm_device *dev);
14810 };
14811
14812 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14813 struct intel_dmi_quirk {
14814         void (*hook)(struct drm_device *dev);
14815         const struct dmi_system_id (*dmi_id_list)[];
14816 };
14817
14818 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14819 {
14820         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14821         return 1;
14822 }
14823
14824 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14825         {
14826                 .dmi_id_list = &(const struct dmi_system_id[]) {
14827                         {
14828                                 .callback = intel_dmi_reverse_brightness,
14829                                 .ident = "NCR Corporation",
14830                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14831                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14832                                 },
14833                         },
14834                         { }  /* terminating entry */
14835                 },
14836                 .hook = quirk_invert_brightness,
14837         },
14838 };
14839
14840 static struct intel_quirk intel_quirks[] = {
14841         /* Lenovo U160 cannot use SSC on LVDS */
14842         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14843
14844         /* Sony Vaio Y cannot use SSC on LVDS */
14845         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14846
14847         /* Acer Aspire 5734Z must invert backlight brightness */
14848         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14849
14850         /* Acer/eMachines G725 */
14851         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14852
14853         /* Acer/eMachines e725 */
14854         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14855
14856         /* Acer/Packard Bell NCL20 */
14857         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14858
14859         /* Acer Aspire 4736Z */
14860         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14861
14862         /* Acer Aspire 5336 */
14863         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14864
14865         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14866         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14867
14868         /* Acer C720 Chromebook (Core i3 4005U) */
14869         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14870
14871         /* Apple Macbook 2,1 (Core 2 T7400) */
14872         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14873
14874         /* Apple Macbook 4,1 */
14875         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14876
14877         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14878         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14879
14880         /* HP Chromebook 14 (Celeron 2955U) */
14881         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14882
14883         /* Dell Chromebook 11 */
14884         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14885
14886         /* Dell Chromebook 11 (2015 version) */
14887         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14888
14889         /* Toshiba Satellite P50-C-18C */
14890         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14891 };
14892
14893 static void intel_init_quirks(struct drm_device *dev)
14894 {
14895         struct pci_dev *d = dev->pdev;
14896         int i;
14897
14898         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14899                 struct intel_quirk *q = &intel_quirks[i];
14900
14901                 if (d->device == q->device &&
14902                     (d->subsystem_vendor == q->subsystem_vendor ||
14903                      q->subsystem_vendor == PCI_ANY_ID) &&
14904                     (d->subsystem_device == q->subsystem_device ||
14905                      q->subsystem_device == PCI_ANY_ID))
14906                         q->hook(dev);
14907         }
14908         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14909                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14910                         intel_dmi_quirks[i].hook(dev);
14911         }
14912 }
14913
14914 /* Disable the VGA plane that we never use */
14915 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14916 {
14917         struct pci_dev *pdev = dev_priv->drm.pdev;
14918         u8 sr1;
14919         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14920
14921         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14922         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14923         outb(SR01, VGA_SR_INDEX);
14924         sr1 = inb(VGA_SR_DATA);
14925         outb(sr1 | 1<<5, VGA_SR_DATA);
14926         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14927         udelay(300);
14928
14929         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14930         POSTING_READ(vga_reg);
14931 }
14932
14933 void intel_modeset_init_hw(struct drm_device *dev)
14934 {
14935         struct drm_i915_private *dev_priv = to_i915(dev);
14936
14937         intel_update_cdclk(dev_priv);
14938         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14939
14940         intel_init_clock_gating(dev_priv);
14941 }
14942
14943 /*
14944  * Calculate what we think the watermarks should be for the state we've read
14945  * out of the hardware and then immediately program those watermarks so that
14946  * we ensure the hardware settings match our internal state.
14947  *
14948  * We can calculate what we think WM's should be by creating a duplicate of the
14949  * current state (which was constructed during hardware readout) and running it
14950  * through the atomic check code to calculate new watermark values in the
14951  * state object.
14952  */
14953 static void sanitize_watermarks(struct drm_device *dev)
14954 {
14955         struct drm_i915_private *dev_priv = to_i915(dev);
14956         struct drm_atomic_state *state;
14957         struct intel_atomic_state *intel_state;
14958         struct drm_crtc *crtc;
14959         struct drm_crtc_state *cstate;
14960         struct drm_modeset_acquire_ctx ctx;
14961         int ret;
14962         int i;
14963
14964         /* Only supported on platforms that use atomic watermark design */
14965         if (!dev_priv->display.optimize_watermarks)
14966                 return;
14967
14968         /*
14969          * We need to hold connection_mutex before calling duplicate_state so
14970          * that the connector loop is protected.
14971          */
14972         drm_modeset_acquire_init(&ctx, 0);
14973 retry:
14974         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14975         if (ret == -EDEADLK) {
14976                 drm_modeset_backoff(&ctx);
14977                 goto retry;
14978         } else if (WARN_ON(ret)) {
14979                 goto fail;
14980         }
14981
14982         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14983         if (WARN_ON(IS_ERR(state)))
14984                 goto fail;
14985
14986         intel_state = to_intel_atomic_state(state);
14987
14988         /*
14989          * Hardware readout is the only time we don't want to calculate
14990          * intermediate watermarks (since we don't trust the current
14991          * watermarks).
14992          */
14993         if (!HAS_GMCH_DISPLAY(dev_priv))
14994                 intel_state->skip_intermediate_wm = true;
14995
14996         ret = intel_atomic_check(dev, state);
14997         if (ret) {
14998                 /*
14999                  * If we fail here, it means that the hardware appears to be
15000                  * programmed in a way that shouldn't be possible, given our
15001                  * understanding of watermark requirements.  This might mean a
15002                  * mistake in the hardware readout code or a mistake in the
15003                  * watermark calculations for a given platform.  Raise a WARN
15004                  * so that this is noticeable.
15005                  *
15006                  * If this actually happens, we'll have to just leave the
15007                  * BIOS-programmed watermarks untouched and hope for the best.
15008                  */
15009                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15010                 goto put_state;
15011         }
15012
15013         /* Write calculated watermark values back */
15014         for_each_new_crtc_in_state(state, crtc, cstate, i) {
15015                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15016
15017                 cs->wm.need_postvbl_update = true;
15018                 dev_priv->display.optimize_watermarks(intel_state, cs);
15019         }
15020
15021 put_state:
15022         drm_atomic_state_put(state);
15023 fail:
15024         drm_modeset_drop_locks(&ctx);
15025         drm_modeset_acquire_fini(&ctx);
15026 }
15027
15028 int intel_modeset_init(struct drm_device *dev)
15029 {
15030         struct drm_i915_private *dev_priv = to_i915(dev);
15031         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15032         enum pipe pipe;
15033         struct intel_crtc *crtc;
15034
15035         drm_mode_config_init(dev);
15036
15037         dev->mode_config.min_width = 0;
15038         dev->mode_config.min_height = 0;
15039
15040         dev->mode_config.preferred_depth = 24;
15041         dev->mode_config.prefer_shadow = 1;
15042
15043         dev->mode_config.allow_fb_modifiers = true;
15044
15045         dev->mode_config.funcs = &intel_mode_funcs;
15046
15047         init_llist_head(&dev_priv->atomic_helper.free_list);
15048         INIT_WORK(&dev_priv->atomic_helper.free_work,
15049                   intel_atomic_helper_free_state_worker);
15050
15051         intel_init_quirks(dev);
15052
15053         intel_init_pm(dev_priv);
15054
15055         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15056                 return 0;
15057
15058         /*
15059          * There may be no VBT; and if the BIOS enabled SSC we can
15060          * just keep using it to avoid unnecessary flicker.  Whereas if the
15061          * BIOS isn't using it, don't assume it will work even if the VBT
15062          * indicates as much.
15063          */
15064         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15065                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15066                                             DREF_SSC1_ENABLE);
15067
15068                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15069                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15070                                      bios_lvds_use_ssc ? "en" : "dis",
15071                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15072                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15073                 }
15074         }
15075
15076         if (IS_GEN2(dev_priv)) {
15077                 dev->mode_config.max_width = 2048;
15078                 dev->mode_config.max_height = 2048;
15079         } else if (IS_GEN3(dev_priv)) {
15080                 dev->mode_config.max_width = 4096;
15081                 dev->mode_config.max_height = 4096;
15082         } else {
15083                 dev->mode_config.max_width = 8192;
15084                 dev->mode_config.max_height = 8192;
15085         }
15086
15087         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15088                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15089                 dev->mode_config.cursor_height = 1023;
15090         } else if (IS_GEN2(dev_priv)) {
15091                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15092                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15093         } else {
15094                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15095                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15096         }
15097
15098         dev->mode_config.fb_base = ggtt->mappable_base;
15099
15100         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15101                       INTEL_INFO(dev_priv)->num_pipes,
15102                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15103
15104         for_each_pipe(dev_priv, pipe) {
15105                 int ret;
15106
15107                 ret = intel_crtc_init(dev_priv, pipe);
15108                 if (ret) {
15109                         drm_mode_config_cleanup(dev);
15110                         return ret;
15111                 }
15112         }
15113
15114         intel_shared_dpll_init(dev);
15115
15116         intel_update_czclk(dev_priv);
15117         intel_modeset_init_hw(dev);
15118
15119         if (dev_priv->max_cdclk_freq == 0)
15120                 intel_update_max_cdclk(dev_priv);
15121
15122         /* Just disable it once at startup */
15123         i915_disable_vga(dev_priv);
15124         intel_setup_outputs(dev_priv);
15125
15126         drm_modeset_lock_all(dev);
15127         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15128         drm_modeset_unlock_all(dev);
15129
15130         for_each_intel_crtc(dev, crtc) {
15131                 struct intel_initial_plane_config plane_config = {};
15132
15133                 if (!crtc->active)
15134                         continue;
15135
15136                 /*
15137                  * Note that reserving the BIOS fb up front prevents us
15138                  * from stuffing other stolen allocations like the ring
15139                  * on top.  This prevents some ugliness at boot time, and
15140                  * can even allow for smooth boot transitions if the BIOS
15141                  * fb is large enough for the active pipe configuration.
15142                  */
15143                 dev_priv->display.get_initial_plane_config(crtc,
15144                                                            &plane_config);
15145
15146                 /*
15147                  * If the fb is shared between multiple heads, we'll
15148                  * just get the first one.
15149                  */
15150                 intel_find_initial_plane_obj(crtc, &plane_config);
15151         }
15152
15153         /*
15154          * Make sure hardware watermarks really match the state we read out.
15155          * Note that we need to do this after reconstructing the BIOS fb's
15156          * since the watermark calculation done here will use pstate->fb.
15157          */
15158         if (!HAS_GMCH_DISPLAY(dev_priv))
15159                 sanitize_watermarks(dev);
15160
15161         return 0;
15162 }
15163
15164 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15165 {
15166         /* 640x480@60Hz, ~25175 kHz */
15167         struct dpll clock = {
15168                 .m1 = 18,
15169                 .m2 = 7,
15170                 .p1 = 13,
15171                 .p2 = 4,
15172                 .n = 2,
15173         };
15174         u32 dpll, fp;
15175         int i;
15176
15177         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15178
15179         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15180                       pipe_name(pipe), clock.vco, clock.dot);
15181
15182         fp = i9xx_dpll_compute_fp(&clock);
15183         dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
15184                 DPLL_VGA_MODE_DIS |
15185                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15186                 PLL_P2_DIVIDE_BY_4 |
15187                 PLL_REF_INPUT_DREFCLK |
15188                 DPLL_VCO_ENABLE;
15189
15190         I915_WRITE(FP0(pipe), fp);
15191         I915_WRITE(FP1(pipe), fp);
15192
15193         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15194         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15195         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15196         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15197         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15198         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15199         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15200
15201         /*
15202          * Apparently we need to have VGA mode enabled prior to changing
15203          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15204          * dividers, even though the register value does change.
15205          */
15206         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15207         I915_WRITE(DPLL(pipe), dpll);
15208
15209         /* Wait for the clocks to stabilize. */
15210         POSTING_READ(DPLL(pipe));
15211         udelay(150);
15212
15213         /* The pixel multiplier can only be updated once the
15214          * DPLL is enabled and the clocks are stable.
15215          *
15216          * So write it again.
15217          */
15218         I915_WRITE(DPLL(pipe), dpll);
15219
15220         /* We do this three times for luck */
15221         for (i = 0; i < 3 ; i++) {
15222                 I915_WRITE(DPLL(pipe), dpll);
15223                 POSTING_READ(DPLL(pipe));
15224                 udelay(150); /* wait for warmup */
15225         }
15226
15227         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15228         POSTING_READ(PIPECONF(pipe));
15229 }
15230
15231 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15232 {
15233         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15234                       pipe_name(pipe));
15235
15236         assert_plane_disabled(dev_priv, PLANE_A);
15237         assert_plane_disabled(dev_priv, PLANE_B);
15238
15239         I915_WRITE(PIPECONF(pipe), 0);
15240         POSTING_READ(PIPECONF(pipe));
15241
15242         if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
15243                 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
15244
15245         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15246         POSTING_READ(DPLL(pipe));
15247 }
15248
15249 static bool
15250 intel_check_plane_mapping(struct intel_crtc *crtc)
15251 {
15252         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15253         u32 val;
15254
15255         if (INTEL_INFO(dev_priv)->num_pipes == 1)
15256                 return true;
15257
15258         val = I915_READ(DSPCNTR(!crtc->plane));
15259
15260         if ((val & DISPLAY_PLANE_ENABLE) &&
15261             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15262                 return false;
15263
15264         return true;
15265 }
15266
15267 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15268 {
15269         struct drm_device *dev = crtc->base.dev;
15270         struct intel_encoder *encoder;
15271
15272         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15273                 return true;
15274
15275         return false;
15276 }
15277
15278 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15279 {
15280         struct drm_device *dev = encoder->base.dev;
15281         struct intel_connector *connector;
15282
15283         for_each_connector_on_encoder(dev, &encoder->base, connector)
15284                 return connector;
15285
15286         return NULL;
15287 }
15288
15289 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15290                               enum transcoder pch_transcoder)
15291 {
15292         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15293                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15294 }
15295
15296 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15297                                 struct drm_modeset_acquire_ctx *ctx)
15298 {
15299         struct drm_device *dev = crtc->base.dev;
15300         struct drm_i915_private *dev_priv = to_i915(dev);
15301         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15302
15303         /* Clear any frame start delays used for debugging left by the BIOS */
15304         if (!transcoder_is_dsi(cpu_transcoder)) {
15305                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15306
15307                 I915_WRITE(reg,
15308                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15309         }
15310
15311         /* restore vblank interrupts to correct state */
15312         drm_crtc_vblank_reset(&crtc->base);
15313         if (crtc->active) {
15314                 struct intel_plane *plane;
15315
15316                 drm_crtc_vblank_on(&crtc->base);
15317
15318                 /* Disable everything but the primary plane */
15319                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15320                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15321                                 continue;
15322
15323                         trace_intel_disable_plane(&plane->base, crtc);
15324                         plane->disable_plane(plane, crtc);
15325                 }
15326         }
15327
15328         /* We need to sanitize the plane -> pipe mapping first because this will
15329          * disable the crtc (and hence change the state) if it is wrong. Note
15330          * that gen4+ has a fixed plane -> pipe mapping.  */
15331         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15332                 bool plane;
15333
15334                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15335                               crtc->base.base.id, crtc->base.name);
15336
15337                 /* Pipe has the wrong plane attached and the plane is active.
15338                  * Temporarily change the plane mapping and disable everything
15339                  * ...  */
15340                 plane = crtc->plane;
15341                 crtc->base.primary->state->visible = true;
15342                 crtc->plane = !plane;
15343                 intel_crtc_disable_noatomic(&crtc->base, ctx);
15344                 crtc->plane = plane;
15345         }
15346
15347         /* Adjust the state of the output pipe according to whether we
15348          * have active connectors/encoders. */
15349         if (crtc->active && !intel_crtc_has_encoders(crtc))
15350                 intel_crtc_disable_noatomic(&crtc->base, ctx);
15351
15352         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15353                 /*
15354                  * We start out with underrun reporting disabled to avoid races.
15355                  * For correct bookkeeping mark this on active crtcs.
15356                  *
15357                  * Also on gmch platforms we dont have any hardware bits to
15358                  * disable the underrun reporting. Which means we need to start
15359                  * out with underrun reporting disabled also on inactive pipes,
15360                  * since otherwise we'll complain about the garbage we read when
15361                  * e.g. coming up after runtime pm.
15362                  *
15363                  * No protection against concurrent access is required - at
15364                  * worst a fifo underrun happens which also sets this to false.
15365                  */
15366                 crtc->cpu_fifo_underrun_disabled = true;
15367                 /*
15368                  * We track the PCH trancoder underrun reporting state
15369                  * within the crtc. With crtc for pipe A housing the underrun
15370                  * reporting state for PCH transcoder A, crtc for pipe B housing
15371                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15372                  * and marking underrun reporting as disabled for the non-existing
15373                  * PCH transcoders B and C would prevent enabling the south
15374                  * error interrupt (see cpt_can_enable_serr_int()).
15375                  */
15376                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15377                         crtc->pch_fifo_underrun_disabled = true;
15378         }
15379 }
15380
15381 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15382 {
15383         struct intel_connector *connector;
15384
15385         /* We need to check both for a crtc link (meaning that the
15386          * encoder is active and trying to read from a pipe) and the
15387          * pipe itself being active. */
15388         bool has_active_crtc = encoder->base.crtc &&
15389                 to_intel_crtc(encoder->base.crtc)->active;
15390
15391         connector = intel_encoder_find_connector(encoder);
15392         if (connector && !has_active_crtc) {
15393                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15394                               encoder->base.base.id,
15395                               encoder->base.name);
15396
15397                 /* Connector is active, but has no active pipe. This is
15398                  * fallout from our resume register restoring. Disable
15399                  * the encoder manually again. */
15400                 if (encoder->base.crtc) {
15401                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15402
15403                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15404                                       encoder->base.base.id,
15405                                       encoder->base.name);
15406                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15407                         if (encoder->post_disable)
15408                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15409                 }
15410                 encoder->base.crtc = NULL;
15411
15412                 /* Inconsistent output/port/pipe state happens presumably due to
15413                  * a bug in one of the get_hw_state functions. Or someplace else
15414                  * in our code, like the register restore mess on resume. Clamp
15415                  * things to off as a safer default. */
15416
15417                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15418                 connector->base.encoder = NULL;
15419         }
15420         /* Enabled encoders without active connectors will be fixed in
15421          * the crtc fixup. */
15422 }
15423
15424 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15425 {
15426         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15427
15428         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15429                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15430                 i915_disable_vga(dev_priv);
15431         }
15432 }
15433
15434 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15435 {
15436         /* This function can be called both from intel_modeset_setup_hw_state or
15437          * at a very early point in our resume sequence, where the power well
15438          * structures are not yet restored. Since this function is at a very
15439          * paranoid "someone might have enabled VGA while we were not looking"
15440          * level, just check if the power well is enabled instead of trying to
15441          * follow the "don't touch the power well if we don't need it" policy
15442          * the rest of the driver uses. */
15443         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15444                 return;
15445
15446         i915_redisable_vga_power_on(dev_priv);
15447
15448         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15449 }
15450
15451 static bool primary_get_hw_state(struct intel_plane *plane)
15452 {
15453         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15454
15455         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15456 }
15457
15458 /* FIXME read out full plane state for all planes */
15459 static void readout_plane_state(struct intel_crtc *crtc)
15460 {
15461         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15462         bool visible;
15463
15464         visible = crtc->active && primary_get_hw_state(primary);
15465
15466         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15467                                 to_intel_plane_state(primary->base.state),
15468                                 visible);
15469 }
15470
15471 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15472 {
15473         struct drm_i915_private *dev_priv = to_i915(dev);
15474         enum pipe pipe;
15475         struct intel_crtc *crtc;
15476         struct intel_encoder *encoder;
15477         struct intel_connector *connector;
15478         struct drm_connector_list_iter conn_iter;
15479         int i;
15480
15481         dev_priv->active_crtcs = 0;
15482
15483         for_each_intel_crtc(dev, crtc) {
15484                 struct intel_crtc_state *crtc_state =
15485                         to_intel_crtc_state(crtc->base.state);
15486
15487                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15488                 memset(crtc_state, 0, sizeof(*crtc_state));
15489                 crtc_state->base.crtc = &crtc->base;
15490
15491                 crtc_state->base.active = crtc_state->base.enable =
15492                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15493
15494                 crtc->base.enabled = crtc_state->base.enable;
15495                 crtc->active = crtc_state->base.active;
15496
15497                 if (crtc_state->base.active)
15498                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15499
15500                 readout_plane_state(crtc);
15501
15502                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15503                               crtc->base.base.id, crtc->base.name,
15504                               enableddisabled(crtc_state->base.active));
15505         }
15506
15507         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15508                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15509
15510                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15511                                                   &pll->state.hw_state);
15512                 pll->state.crtc_mask = 0;
15513                 for_each_intel_crtc(dev, crtc) {
15514                         struct intel_crtc_state *crtc_state =
15515                                 to_intel_crtc_state(crtc->base.state);
15516
15517                         if (crtc_state->base.active &&
15518                             crtc_state->shared_dpll == pll)
15519                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15520                 }
15521                 pll->active_mask = pll->state.crtc_mask;
15522
15523                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15524                               pll->name, pll->state.crtc_mask, pll->on);
15525         }
15526
15527         for_each_intel_encoder(dev, encoder) {
15528                 pipe = 0;
15529
15530                 if (encoder->get_hw_state(encoder, &pipe)) {
15531                         struct intel_crtc_state *crtc_state;
15532
15533                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15534                         crtc_state = to_intel_crtc_state(crtc->base.state);
15535
15536                         encoder->base.crtc = &crtc->base;
15537                         crtc_state->output_types |= 1 << encoder->type;
15538                         encoder->get_config(encoder, crtc_state);
15539                 } else {
15540                         encoder->base.crtc = NULL;
15541                 }
15542
15543                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15544                               encoder->base.base.id, encoder->base.name,
15545                               enableddisabled(encoder->base.crtc),
15546                               pipe_name(pipe));
15547         }
15548
15549         drm_connector_list_iter_begin(dev, &conn_iter);
15550         for_each_intel_connector_iter(connector, &conn_iter) {
15551                 if (connector->get_hw_state(connector)) {
15552                         connector->base.dpms = DRM_MODE_DPMS_ON;
15553
15554                         encoder = connector->encoder;
15555                         connector->base.encoder = &encoder->base;
15556
15557                         if (encoder->base.crtc &&
15558                             encoder->base.crtc->state->active) {
15559                                 /*
15560                                  * This has to be done during hardware readout
15561                                  * because anything calling .crtc_disable may
15562                                  * rely on the connector_mask being accurate.
15563                                  */
15564                                 encoder->base.crtc->state->connector_mask |=
15565                                         1 << drm_connector_index(&connector->base);
15566                                 encoder->base.crtc->state->encoder_mask |=
15567                                         1 << drm_encoder_index(&encoder->base);
15568                         }
15569
15570                 } else {
15571                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15572                         connector->base.encoder = NULL;
15573                 }
15574                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15575                               connector->base.base.id, connector->base.name,
15576                               enableddisabled(connector->base.encoder));
15577         }
15578         drm_connector_list_iter_end(&conn_iter);
15579
15580         for_each_intel_crtc(dev, crtc) {
15581                 struct intel_crtc_state *crtc_state =
15582                         to_intel_crtc_state(crtc->base.state);
15583                 int pixclk = 0;
15584
15585                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15586                 if (crtc_state->base.active) {
15587                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15588                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15589                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15590
15591                         /*
15592                          * The initial mode needs to be set in order to keep
15593                          * the atomic core happy. It wants a valid mode if the
15594                          * crtc's enabled, so we do the above call.
15595                          *
15596                          * But we don't set all the derived state fully, hence
15597                          * set a flag to indicate that a full recalculation is
15598                          * needed on the next commit.
15599                          */
15600                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15601
15602                         intel_crtc_compute_pixel_rate(crtc_state);
15603
15604                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15605                             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15606                                 pixclk = crtc_state->pixel_rate;
15607                         else
15608                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15609
15610                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15611                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15612                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15613
15614                         drm_calc_timestamping_constants(&crtc->base,
15615                                                         &crtc_state->base.adjusted_mode);
15616                         update_scanline_offset(crtc);
15617                 }
15618
15619                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15620
15621                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15622         }
15623 }
15624
15625 static void
15626 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15627 {
15628         struct intel_encoder *encoder;
15629
15630         for_each_intel_encoder(&dev_priv->drm, encoder) {
15631                 u64 get_domains;
15632                 enum intel_display_power_domain domain;
15633
15634                 if (!encoder->get_power_domains)
15635                         continue;
15636
15637                 get_domains = encoder->get_power_domains(encoder);
15638                 for_each_power_domain(domain, get_domains)
15639                         intel_display_power_get(dev_priv, domain);
15640         }
15641 }
15642
15643 /* Scan out the current hw modeset state,
15644  * and sanitizes it to the current state
15645  */
15646 static void
15647 intel_modeset_setup_hw_state(struct drm_device *dev,
15648                              struct drm_modeset_acquire_ctx *ctx)
15649 {
15650         struct drm_i915_private *dev_priv = to_i915(dev);
15651         enum pipe pipe;
15652         struct intel_crtc *crtc;
15653         struct intel_encoder *encoder;
15654         int i;
15655
15656         intel_modeset_readout_hw_state(dev);
15657
15658         /* HW state is read out, now we need to sanitize this mess. */
15659         get_encoder_power_domains(dev_priv);
15660
15661         for_each_intel_encoder(dev, encoder) {
15662                 intel_sanitize_encoder(encoder);
15663         }
15664
15665         for_each_pipe(dev_priv, pipe) {
15666                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15667
15668                 intel_sanitize_crtc(crtc, ctx);
15669                 intel_dump_pipe_config(crtc, crtc->config,
15670                                        "[setup_hw_state]");
15671         }
15672
15673         intel_modeset_update_connector_atomic_state(dev);
15674
15675         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15676                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15677
15678                 if (!pll->on || pll->active_mask)
15679                         continue;
15680
15681                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15682
15683                 pll->funcs.disable(dev_priv, pll);
15684                 pll->on = false;
15685         }
15686
15687         if (IS_G4X(dev_priv)) {
15688                 g4x_wm_get_hw_state(dev);
15689                 g4x_wm_sanitize(dev_priv);
15690         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15691                 vlv_wm_get_hw_state(dev);
15692                 vlv_wm_sanitize(dev_priv);
15693         } else if (IS_GEN9(dev_priv)) {
15694                 skl_wm_get_hw_state(dev);
15695         } else if (HAS_PCH_SPLIT(dev_priv)) {
15696                 ilk_wm_get_hw_state(dev);
15697         }
15698
15699         for_each_intel_crtc(dev, crtc) {
15700                 u64 put_domains;
15701
15702                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15703                 if (WARN_ON(put_domains))
15704                         modeset_put_power_domains(dev_priv, put_domains);
15705         }
15706         intel_display_set_init_power(dev_priv, false);
15707
15708         intel_power_domains_verify_state(dev_priv);
15709
15710         intel_fbc_init_pipe_state(dev_priv);
15711 }
15712
15713 void intel_display_resume(struct drm_device *dev)
15714 {
15715         struct drm_i915_private *dev_priv = to_i915(dev);
15716         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15717         struct drm_modeset_acquire_ctx ctx;
15718         int ret;
15719
15720         dev_priv->modeset_restore_state = NULL;
15721         if (state)
15722                 state->acquire_ctx = &ctx;
15723
15724         drm_modeset_acquire_init(&ctx, 0);
15725
15726         while (1) {
15727                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15728                 if (ret != -EDEADLK)
15729                         break;
15730
15731                 drm_modeset_backoff(&ctx);
15732         }
15733
15734         if (!ret)
15735                 ret = __intel_display_resume(dev, state, &ctx);
15736
15737         drm_modeset_drop_locks(&ctx);
15738         drm_modeset_acquire_fini(&ctx);
15739
15740         if (ret)
15741                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15742         if (state)
15743                 drm_atomic_state_put(state);
15744 }
15745
15746 void intel_modeset_gem_init(struct drm_device *dev)
15747 {
15748         struct drm_i915_private *dev_priv = to_i915(dev);
15749
15750         intel_init_gt_powersave(dev_priv);
15751
15752         intel_setup_overlay(dev_priv);
15753 }
15754
15755 int intel_connector_register(struct drm_connector *connector)
15756 {
15757         struct intel_connector *intel_connector = to_intel_connector(connector);
15758         int ret;
15759
15760         ret = intel_backlight_device_register(intel_connector);
15761         if (ret)
15762                 goto err;
15763
15764         return 0;
15765
15766 err:
15767         return ret;
15768 }
15769
15770 void intel_connector_unregister(struct drm_connector *connector)
15771 {
15772         struct intel_connector *intel_connector = to_intel_connector(connector);
15773
15774         intel_backlight_device_unregister(intel_connector);
15775         intel_panel_destroy_backlight(connector);
15776 }
15777
15778 void intel_modeset_cleanup(struct drm_device *dev)
15779 {
15780         struct drm_i915_private *dev_priv = to_i915(dev);
15781
15782         flush_work(&dev_priv->atomic_helper.free_work);
15783         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15784
15785         intel_disable_gt_powersave(dev_priv);
15786
15787         /*
15788          * Interrupts and polling as the first thing to avoid creating havoc.
15789          * Too much stuff here (turning of connectors, ...) would
15790          * experience fancy races otherwise.
15791          */
15792         intel_irq_uninstall(dev_priv);
15793
15794         /*
15795          * Due to the hpd irq storm handling the hotplug work can re-arm the
15796          * poll handlers. Hence disable polling after hpd handling is shut down.
15797          */
15798         drm_kms_helper_poll_fini(dev);
15799
15800         intel_unregister_dsm_handler();
15801
15802         intel_fbc_global_disable(dev_priv);
15803
15804         /* flush any delayed tasks or pending work */
15805         flush_scheduled_work();
15806
15807         drm_mode_config_cleanup(dev);
15808
15809         intel_cleanup_overlay(dev_priv);
15810
15811         intel_cleanup_gt_powersave(dev_priv);
15812
15813         intel_teardown_gmbus(dev_priv);
15814 }
15815
15816 void intel_connector_attach_encoder(struct intel_connector *connector,
15817                                     struct intel_encoder *encoder)
15818 {
15819         connector->encoder = encoder;
15820         drm_mode_connector_attach_encoder(&connector->base,
15821                                           &encoder->base);
15822 }
15823
15824 /*
15825  * set vga decode state - true == enable VGA decode
15826  */
15827 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15828 {
15829         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15830         u16 gmch_ctrl;
15831
15832         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15833                 DRM_ERROR("failed to read control word\n");
15834                 return -EIO;
15835         }
15836
15837         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15838                 return 0;
15839
15840         if (state)
15841                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15842         else
15843                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15844
15845         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15846                 DRM_ERROR("failed to write control word\n");
15847                 return -EIO;
15848         }
15849
15850         return 0;
15851 }
15852
15853 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15854
15855 struct intel_display_error_state {
15856
15857         u32 power_well_driver;
15858
15859         int num_transcoders;
15860
15861         struct intel_cursor_error_state {
15862                 u32 control;
15863                 u32 position;
15864                 u32 base;
15865                 u32 size;
15866         } cursor[I915_MAX_PIPES];
15867
15868         struct intel_pipe_error_state {
15869                 bool power_domain_on;
15870                 u32 source;
15871                 u32 stat;
15872         } pipe[I915_MAX_PIPES];
15873
15874         struct intel_plane_error_state {
15875                 u32 control;
15876                 u32 stride;
15877                 u32 size;
15878                 u32 pos;
15879                 u32 addr;
15880                 u32 surface;
15881                 u32 tile_offset;
15882         } plane[I915_MAX_PIPES];
15883
15884         struct intel_transcoder_error_state {
15885                 bool power_domain_on;
15886                 enum transcoder cpu_transcoder;
15887
15888                 u32 conf;
15889
15890                 u32 htotal;
15891                 u32 hblank;
15892                 u32 hsync;
15893                 u32 vtotal;
15894                 u32 vblank;
15895                 u32 vsync;
15896         } transcoder[4];
15897 };
15898
15899 struct intel_display_error_state *
15900 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15901 {
15902         struct intel_display_error_state *error;
15903         int transcoders[] = {
15904                 TRANSCODER_A,
15905                 TRANSCODER_B,
15906                 TRANSCODER_C,
15907                 TRANSCODER_EDP,
15908         };
15909         int i;
15910
15911         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15912                 return NULL;
15913
15914         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15915         if (error == NULL)
15916                 return NULL;
15917
15918         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15919                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15920
15921         for_each_pipe(dev_priv, i) {
15922                 error->pipe[i].power_domain_on =
15923                         __intel_display_power_is_enabled(dev_priv,
15924                                                          POWER_DOMAIN_PIPE(i));
15925                 if (!error->pipe[i].power_domain_on)
15926                         continue;
15927
15928                 error->cursor[i].control = I915_READ(CURCNTR(i));
15929                 error->cursor[i].position = I915_READ(CURPOS(i));
15930                 error->cursor[i].base = I915_READ(CURBASE(i));
15931
15932                 error->plane[i].control = I915_READ(DSPCNTR(i));
15933                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15934                 if (INTEL_GEN(dev_priv) <= 3) {
15935                         error->plane[i].size = I915_READ(DSPSIZE(i));
15936                         error->plane[i].pos = I915_READ(DSPPOS(i));
15937                 }
15938                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15939                         error->plane[i].addr = I915_READ(DSPADDR(i));
15940                 if (INTEL_GEN(dev_priv) >= 4) {
15941                         error->plane[i].surface = I915_READ(DSPSURF(i));
15942                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15943                 }
15944
15945                 error->pipe[i].source = I915_READ(PIPESRC(i));
15946
15947                 if (HAS_GMCH_DISPLAY(dev_priv))
15948                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15949         }
15950
15951         /* Note: this does not include DSI transcoders. */
15952         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15953         if (HAS_DDI(dev_priv))
15954                 error->num_transcoders++; /* Account for eDP. */
15955
15956         for (i = 0; i < error->num_transcoders; i++) {
15957                 enum transcoder cpu_transcoder = transcoders[i];
15958
15959                 error->transcoder[i].power_domain_on =
15960                         __intel_display_power_is_enabled(dev_priv,
15961                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15962                 if (!error->transcoder[i].power_domain_on)
15963                         continue;
15964
15965                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15966
15967                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15968                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15969                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15970                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15971                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15972                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15973                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15974         }
15975
15976         return error;
15977 }
15978
15979 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15980
15981 void
15982 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15983                                 struct intel_display_error_state *error)
15984 {
15985         struct drm_i915_private *dev_priv = m->i915;
15986         int i;
15987
15988         if (!error)
15989                 return;
15990
15991         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15992         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15993                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15994                            error->power_well_driver);
15995         for_each_pipe(dev_priv, i) {
15996                 err_printf(m, "Pipe [%d]:\n", i);
15997                 err_printf(m, "  Power: %s\n",
15998                            onoff(error->pipe[i].power_domain_on));
15999                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16000                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16001
16002                 err_printf(m, "Plane [%d]:\n", i);
16003                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16004                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16005                 if (INTEL_GEN(dev_priv) <= 3) {
16006                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16007                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16008                 }
16009                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16010                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16011                 if (INTEL_GEN(dev_priv) >= 4) {
16012                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16013                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16014                 }
16015
16016                 err_printf(m, "Cursor [%d]:\n", i);
16017                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16018                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16019                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16020         }
16021
16022         for (i = 0; i < error->num_transcoders; i++) {
16023                 err_printf(m, "CPU transcoder: %s\n",
16024                            transcoder_name(error->transcoder[i].cpu_transcoder));
16025                 err_printf(m, "  Power: %s\n",
16026                            onoff(error->transcoder[i].power_domain_on));
16027                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16028                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16029                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16030                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16031                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16032                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16033                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16034         }
16035 }
16036
16037 #endif