2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
127 .find_pll = intel_find_best_PLL,
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
141 .find_pll = intel_find_best_PLL,
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
155 .find_pll = intel_find_best_PLL,
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 .find_pll = intel_find_best_PLL,
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
186 .find_pll = intel_g4x_find_best_PLL,
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
200 .find_pll = intel_g4x_find_best_PLL,
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
215 .find_pll = intel_g4x_find_best_PLL,
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
230 .find_pll = intel_g4x_find_best_PLL,
233 static const intel_limit_t intel_limits_g4x_display_port = {
234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 10, .p2_fast = 10 },
244 .find_pll = intel_find_pll_g4x_dp,
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
260 .find_pll = intel_find_best_PLL,
263 static const intel_limit_t intel_limits_pineview_lvds = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
274 .find_pll = intel_find_best_PLL,
277 /* Ironlake / Sandybridge
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
282 static const intel_limit_t intel_limits_ironlake_dac = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
293 .find_pll = intel_g4x_find_best_PLL,
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
307 .find_pll = intel_g4x_find_best_PLL,
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
321 .find_pll = intel_g4x_find_best_PLL,
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
336 .find_pll = intel_g4x_find_best_PLL,
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
347 .p1 = { .min = 2, .max = 6 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 .find_pll = intel_g4x_find_best_PLL,
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 10, .p2_fast = 10 },
364 .find_pll = intel_find_pll_ironlake_dp,
367 static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 4000000, .max = 5994000},
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
395 static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 25000, .max = 270000 },
397 .vco = { .min = 4000000, .max = 6000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 22, .max = 450 },
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
427 val = I915_READ(DPIO_DATA);
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
456 static void vlv_init_dpio(struct drm_device *dev)
458 struct drm_i915_private *dev_priv = dev->dev_private;
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
482 { } /* terminating entry */
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
494 if (dmi_check_system(intel_dual_link_lvds))
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
526 limit = &intel_limits_ironlake_dual_lvds;
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
531 limit = &intel_limits_ironlake_single_lvds;
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
535 limit = &intel_limits_ironlake_display_port;
537 limit = &intel_limits_ironlake_dac;
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
593 limit = &intel_limits_i9xx_sdvo;
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
598 limit = &intel_limits_i8xx_dvo;
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
625 * Returns whether any output on the specified pipe is of the specified type
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
696 clock.p2 = limit->p2.p2_slow;
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
701 clock.p2 = limit->p2.p2_fast;
704 memset(best_clock, 0, sizeof(*best_clock));
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
724 clock.p != match_clock->p)
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
737 return (err != target);
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
757 if (HAS_PCH_SPLIT(dev))
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
763 clock.p2 = limit->p2.p2_fast;
765 clock.p2 = limit->p2.p2_slow;
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
770 clock.p2 = limit->p2.p2_fast;
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
791 clock.p != match_clock->p)
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
813 struct drm_device *dev = crtc->dev;
816 if (target < 200000) {
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
841 if (target < 200000) {
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
873 dotclk = target * 1000;
876 fastclk = dotclk / (2*100);
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
904 if (absppm < bestppm - 10) {
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
935 frame = I915_READ(frame_reg);
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
942 * intel_wait_for_vblank - wait for vblank on a given pipe
944 * @pipe: pipe to wait for
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 int pipestat_reg = PIPESTAT(pipe);
954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
979 DRM_DEBUG_KMS("vblank wait timed out\n");
983 * intel_wait_for_pipe_off - wait for pipe to turn off
985 * @pipe: pipe to wait for
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
992 * wait for the pipe register state bit to turn off
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1003 if (INTEL_INFO(dev)->gen >= 4) {
1004 int reg = PIPECONF(pipe);
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1009 WARN(1, "pipe_off wait timed out\n");
1011 u32 last_line, line_mask;
1012 int reg = PIPEDSL(pipe);
1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1016 line_mask = DSL_LINEMASK_GEN2;
1018 line_mask = DSL_LINEMASK_GEN3;
1020 /* Wait for the display line to settle */
1022 last_line = I915_READ(reg) & line_mask;
1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 WARN(1, "pipe_off wait timed out\n");
1031 static const char *state_string(bool enabled)
1033 return enabled ? "on" : "off";
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1183 int pp_reg, lvds_reg;
1185 enum pipe panel_pipe = PIPE_A;
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1192 pp_reg = PP_CONTROL;
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe), state_string(state), state_string(cur_state));
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1309 if ((val & DP_PORT_EN) == 0)
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1327 if ((val & PORT_ENABLE) == 0)
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1343 if ((val & LVDS_PORT_EN) == 0)
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, int reg, u32 port_sel)
1374 u32 val = I915_READ(reg);
1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe));
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380 && (val & DP_PIPEB_SELECT),
1381 "IBX PCH dp port still using transcoder B\n");
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, int reg)
1387 u32 val = I915_READ(reg);
1388 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390 reg, pipe_name(pipe));
1392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393 && (val & SDVO_PIPE_B_SELECT),
1394 "IBX PCH hdmi port still using transcoder B\n");
1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1408 val = I915_READ(reg);
1409 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
1414 val = I915_READ(reg);
1415 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425 * intel_enable_pll - enable a PLL
1426 * @dev_priv: i915 private structure
1427 * @pipe: pipe PLL to enable
1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1430 * make sure the PLL reg is writable first though, since the panel write
1431 * protect mechanism may be enabled.
1433 * Note! This is for pre-ILK only.
1435 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1437 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1442 /* No really, not for ILK+ */
1443 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1445 /* PLL is protected by panel, make sure we can write it */
1446 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447 assert_panel_unlocked(dev_priv, pipe);
1450 val = I915_READ(reg);
1451 val |= DPLL_VCO_ENABLE;
1453 /* We do this three times for luck */
1454 I915_WRITE(reg, val);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1462 udelay(150); /* wait for warmup */
1466 * intel_disable_pll - disable a PLL
1467 * @dev_priv: i915 private structure
1468 * @pipe: pipe PLL to disable
1470 * Disable the PLL for @pipe, making sure the pipe is off first.
1472 * Note! This is for pre-ILK only.
1474 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1479 /* Don't disable pipe A or pipe A PLLs if needed */
1480 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1483 /* Make sure the pipe isn't still relying on us */
1484 assert_pipe_disabled(dev_priv, pipe);
1487 val = I915_READ(reg);
1488 val &= ~DPLL_VCO_ENABLE;
1489 I915_WRITE(reg, val);
1495 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1497 unsigned long flags;
1499 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1500 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1502 DRM_ERROR("timeout waiting for SBI to become ready\n");
1506 I915_WRITE(SBI_ADDR,
1508 I915_WRITE(SBI_DATA,
1510 I915_WRITE(SBI_CTL_STAT,
1514 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1521 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1525 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1527 unsigned long flags;
1530 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1531 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1533 DRM_ERROR("timeout waiting for SBI to become ready\n");
1537 I915_WRITE(SBI_ADDR,
1539 I915_WRITE(SBI_CTL_STAT,
1543 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1545 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1549 value = I915_READ(SBI_DATA);
1552 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1557 * intel_enable_pch_pll - enable PCH PLL
1558 * @dev_priv: i915 private structure
1559 * @pipe: pipe PLL to enable
1561 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562 * drives the transcoder clock.
1564 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1566 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1567 struct intel_pch_pll *pll;
1571 /* PCH PLLs only available on ILK, SNB and IVB */
1572 BUG_ON(dev_priv->info->gen < 5);
1573 pll = intel_crtc->pch_pll;
1577 if (WARN_ON(pll->refcount == 0))
1580 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581 pll->pll_reg, pll->active, pll->on,
1582 intel_crtc->base.base.id);
1584 /* PCH refclock must be enabled first */
1585 assert_pch_refclk_enabled(dev_priv);
1587 if (pll->active++ && pll->on) {
1588 assert_pch_pll_enabled(dev_priv, pll, NULL);
1592 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1595 val = I915_READ(reg);
1596 val |= DPLL_VCO_ENABLE;
1597 I915_WRITE(reg, val);
1604 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1606 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1611 /* PCH only available on ILK+ */
1612 BUG_ON(dev_priv->info->gen < 5);
1616 if (WARN_ON(pll->refcount == 0))
1619 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620 pll->pll_reg, pll->active, pll->on,
1621 intel_crtc->base.base.id);
1623 if (WARN_ON(pll->active == 0)) {
1624 assert_pch_pll_disabled(dev_priv, pll, NULL);
1628 if (--pll->active) {
1629 assert_pch_pll_enabled(dev_priv, pll, NULL);
1633 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635 /* Make sure transcoder isn't still depending on us */
1636 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1639 val = I915_READ(reg);
1640 val &= ~DPLL_VCO_ENABLE;
1641 I915_WRITE(reg, val);
1648 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1652 u32 val, pipeconf_val;
1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1655 /* PCH only available on ILK+ */
1656 BUG_ON(dev_priv->info->gen < 5);
1658 /* Make sure PCH DPLL is enabled */
1659 assert_pch_pll_enabled(dev_priv,
1660 to_intel_crtc(crtc)->pch_pll,
1661 to_intel_crtc(crtc));
1663 /* FDI must be feeding us bits for PCH ports */
1664 assert_fdi_tx_enabled(dev_priv, pipe);
1665 assert_fdi_rx_enabled(dev_priv, pipe);
1667 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1671 reg = TRANSCONF(pipe);
1672 val = I915_READ(reg);
1673 pipeconf_val = I915_READ(PIPECONF(pipe));
1675 if (HAS_PCH_IBX(dev_priv->dev)) {
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1680 val &= ~PIPE_BPC_MASK;
1681 val |= pipeconf_val & PIPE_BPC_MASK;
1684 val &= ~TRANS_INTERLACE_MASK;
1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1686 if (HAS_PCH_IBX(dev_priv->dev) &&
1687 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688 val |= TRANS_LEGACY_INTERLACED_ILK;
1690 val |= TRANS_INTERLACED;
1692 val |= TRANS_PROGRESSIVE;
1694 I915_WRITE(reg, val | TRANS_ENABLE);
1695 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1699 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1705 /* FDI relies on the transcoder */
1706 assert_fdi_tx_disabled(dev_priv, pipe);
1707 assert_fdi_rx_disabled(dev_priv, pipe);
1709 /* Ports must be off as well */
1710 assert_pch_ports_disabled(dev_priv, pipe);
1712 reg = TRANSCONF(pipe);
1713 val = I915_READ(reg);
1714 val &= ~TRANS_ENABLE;
1715 I915_WRITE(reg, val);
1716 /* wait for PCH transcoder off, transcoder state */
1717 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1718 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1722 * intel_enable_pipe - enable a pipe, asserting requirements
1723 * @dev_priv: i915 private structure
1724 * @pipe: pipe to enable
1725 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1727 * Enable @pipe, making sure that various hardware specific requirements
1728 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1730 * @pipe should be %PIPE_A or %PIPE_B.
1732 * Will wait until the pipe is actually running (i.e. first vblank) before
1735 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1746 if (!HAS_PCH_SPLIT(dev_priv->dev))
1747 assert_pll_enabled(dev_priv, pipe);
1750 /* if driving the PCH, we need FDI enabled */
1751 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1754 /* FIXME: assert CPU port conditions for SNB+ */
1757 reg = PIPECONF(pipe);
1758 val = I915_READ(reg);
1759 if (val & PIPECONF_ENABLE)
1762 I915_WRITE(reg, val | PIPECONF_ENABLE);
1763 intel_wait_for_vblank(dev_priv->dev, pipe);
1767 * intel_disable_pipe - disable a pipe, asserting requirements
1768 * @dev_priv: i915 private structure
1769 * @pipe: pipe to disable
1771 * Disable @pipe, making sure that various hardware specific requirements
1772 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1774 * @pipe should be %PIPE_A or %PIPE_B.
1776 * Will wait until the pipe has shut down before returning.
1778 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1785 * Make sure planes won't keep trying to pump pixels to us,
1786 * or we might hang the display.
1788 assert_planes_disabled(dev_priv, pipe);
1790 /* Don't disable pipe A or pipe A PLLs if needed */
1791 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1794 reg = PIPECONF(pipe);
1795 val = I915_READ(reg);
1796 if ((val & PIPECONF_ENABLE) == 0)
1799 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1800 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1804 * Plane regs are double buffered, going from enabled->disabled needs a
1805 * trigger in order to latch. The display address reg provides this.
1807 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1810 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1815 * intel_enable_plane - enable a display plane on a given pipe
1816 * @dev_priv: i915 private structure
1817 * @plane: plane to enable
1818 * @pipe: pipe being fed
1820 * Enable @plane on @pipe, making sure that @pipe is running first.
1822 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823 enum plane plane, enum pipe pipe)
1828 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829 assert_pipe_enabled(dev_priv, pipe);
1831 reg = DSPCNTR(plane);
1832 val = I915_READ(reg);
1833 if (val & DISPLAY_PLANE_ENABLE)
1836 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1837 intel_flush_display_plane(dev_priv, plane);
1838 intel_wait_for_vblank(dev_priv->dev, pipe);
1842 * intel_disable_plane - disable a display plane
1843 * @dev_priv: i915 private structure
1844 * @plane: plane to disable
1845 * @pipe: pipe consuming the data
1847 * Disable @plane; should be an independent operation.
1849 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850 enum plane plane, enum pipe pipe)
1855 reg = DSPCNTR(plane);
1856 val = I915_READ(reg);
1857 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1860 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1861 intel_flush_display_plane(dev_priv, plane);
1862 intel_wait_for_vblank(dev_priv->dev, pipe);
1866 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1867 struct drm_i915_gem_object *obj,
1868 struct intel_ring_buffer *pipelined)
1870 struct drm_i915_private *dev_priv = dev->dev_private;
1874 switch (obj->tiling_mode) {
1875 case I915_TILING_NONE:
1876 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877 alignment = 128 * 1024;
1878 else if (INTEL_INFO(dev)->gen >= 4)
1879 alignment = 4 * 1024;
1881 alignment = 64 * 1024;
1884 /* pin() will align the object as required by fence */
1888 /* FIXME: Is this true? */
1889 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1895 dev_priv->mm.interruptible = false;
1896 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1898 goto err_interruptible;
1900 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901 * fence, whereas 965+ only requires a fence if using
1902 * framebuffer compression. For simplicity, we always install
1903 * a fence as the cost is not that onerous.
1905 ret = i915_gem_object_get_fence(obj);
1909 i915_gem_object_pin_fence(obj);
1911 dev_priv->mm.interruptible = true;
1915 i915_gem_object_unpin(obj);
1917 dev_priv->mm.interruptible = true;
1921 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1923 i915_gem_object_unpin_fence(obj);
1924 i915_gem_object_unpin(obj);
1927 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928 * is assumed to be a power-of-two. */
1929 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1933 int tile_rows, tiles;
1937 tiles = *x / (512/bpp);
1940 return tile_rows * pitch * 8 + tiles * 4096;
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
1950 struct drm_i915_gem_object *obj;
1951 int plane = intel_crtc->plane;
1952 unsigned long linear_offset;
1961 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
1968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972 switch (fb->bits_per_pixel) {
1974 dspcntr |= DISPPLANE_8BPP;
1977 if (fb->depth == 15)
1978 dspcntr |= DISPPLANE_15_16BPP;
1980 dspcntr |= DISPPLANE_16BPP;
1984 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1987 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1990 if (INTEL_INFO(dev)->gen >= 4) {
1991 if (obj->tiling_mode != I915_TILING_NONE)
1992 dspcntr |= DISPPLANE_TILED;
1994 dspcntr &= ~DISPPLANE_TILED;
1997 I915_WRITE(reg, dspcntr);
1999 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2001 if (INTEL_INFO(dev)->gen >= 4) {
2002 intel_crtc->dspaddr_offset =
2003 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004 fb->bits_per_pixel / 8,
2006 linear_offset -= intel_crtc->dspaddr_offset;
2008 intel_crtc->dspaddr_offset = linear_offset;
2011 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2013 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2014 if (INTEL_INFO(dev)->gen >= 4) {
2015 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016 obj->gtt_offset + intel_crtc->dspaddr_offset);
2017 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2018 I915_WRITE(DSPLINOFF(plane), linear_offset);
2020 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2026 static int ironlake_update_plane(struct drm_crtc *crtc,
2027 struct drm_framebuffer *fb, int x, int y)
2029 struct drm_device *dev = crtc->dev;
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032 struct intel_framebuffer *intel_fb;
2033 struct drm_i915_gem_object *obj;
2034 int plane = intel_crtc->plane;
2035 unsigned long linear_offset;
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2049 intel_fb = to_intel_framebuffer(fb);
2050 obj = intel_fb->obj;
2052 reg = DSPCNTR(plane);
2053 dspcntr = I915_READ(reg);
2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056 switch (fb->bits_per_pixel) {
2058 dspcntr |= DISPPLANE_8BPP;
2061 if (fb->depth != 16)
2064 dspcntr |= DISPPLANE_16BPP;
2068 if (fb->depth == 24)
2069 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070 else if (fb->depth == 30)
2071 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2076 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2080 if (obj->tiling_mode != I915_TILING_NONE)
2081 dspcntr |= DISPPLANE_TILED;
2083 dspcntr &= ~DISPPLANE_TILED;
2086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2088 I915_WRITE(reg, dspcntr);
2090 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2091 intel_crtc->dspaddr_offset =
2092 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2095 linear_offset -= intel_crtc->dspaddr_offset;
2097 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2099 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2100 I915_MODIFY_DISPBASE(DSPSURF(plane),
2101 obj->gtt_offset + intel_crtc->dspaddr_offset);
2102 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103 I915_WRITE(DSPLINOFF(plane), linear_offset);
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112 int x, int y, enum mode_set_atomic state)
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2117 if (dev_priv->display.disable_fbc)
2118 dev_priv->display.disable_fbc(dev);
2119 intel_increase_pllclock(crtc);
2121 return dev_priv->display.update_plane(crtc, fb, x, y);
2125 intel_finish_fb(struct drm_framebuffer *old_fb)
2127 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129 bool was_interruptible = dev_priv->mm.interruptible;
2132 wait_event(dev_priv->pending_flip_queue,
2133 atomic_read(&dev_priv->mm.wedged) ||
2134 atomic_read(&obj->pending_flip) == 0);
2136 /* Big Hammer, we also need to ensure that any pending
2137 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138 * current scanout is retired before unpinning the old
2141 * This should only fail upon a hung GPU, in which case we
2142 * can safely continue.
2144 dev_priv->mm.interruptible = false;
2145 ret = i915_gem_object_finish_gpu(obj);
2146 dev_priv->mm.interruptible = was_interruptible;
2152 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2153 struct drm_framebuffer *fb)
2155 struct drm_device *dev = crtc->dev;
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 struct drm_i915_master_private *master_priv;
2158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2159 struct drm_framebuffer *old_fb;
2164 DRM_ERROR("No FB bound\n");
2168 if(intel_crtc->plane > dev_priv->num_pipe) {
2169 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2171 dev_priv->num_pipe);
2175 mutex_lock(&dev->struct_mutex);
2176 ret = intel_pin_and_fence_fb_obj(dev,
2177 to_intel_framebuffer(fb)->obj,
2180 mutex_unlock(&dev->struct_mutex);
2181 DRM_ERROR("pin & fence failed\n");
2186 intel_finish_fb(crtc->fb);
2188 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2190 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2191 mutex_unlock(&dev->struct_mutex);
2192 DRM_ERROR("failed to update base address\n");
2202 intel_wait_for_vblank(dev, intel_crtc->pipe);
2203 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2206 intel_update_fbc(dev);
2207 mutex_unlock(&dev->struct_mutex);
2209 if (!dev->primary->master)
2212 master_priv = dev->primary->master->driver_priv;
2213 if (!master_priv->sarea_priv)
2216 if (intel_crtc->pipe) {
2217 master_priv->sarea_priv->pipeB_x = x;
2218 master_priv->sarea_priv->pipeB_y = y;
2220 master_priv->sarea_priv->pipeA_x = x;
2221 master_priv->sarea_priv->pipeA_y = y;
2227 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2229 struct drm_device *dev = crtc->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2233 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2234 dpa_ctl = I915_READ(DP_A);
2235 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2237 if (clock < 200000) {
2239 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240 /* workaround for 160Mhz:
2241 1) program 0x4600c bits 15:0 = 0x8124
2242 2) program 0x46010 bit 0 = 1
2243 3) program 0x46034 bit 24 = 1
2244 4) program 0x64000 bit 14 = 1
2246 temp = I915_READ(0x4600c);
2248 I915_WRITE(0x4600c, temp | 0x8124);
2250 temp = I915_READ(0x46010);
2251 I915_WRITE(0x46010, temp | 1);
2253 temp = I915_READ(0x46034);
2254 I915_WRITE(0x46034, temp | (1 << 24));
2256 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2258 I915_WRITE(DP_A, dpa_ctl);
2264 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269 int pipe = intel_crtc->pipe;
2272 /* enable normal train */
2273 reg = FDI_TX_CTL(pipe);
2274 temp = I915_READ(reg);
2275 if (IS_IVYBRIDGE(dev)) {
2276 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2279 temp &= ~FDI_LINK_TRAIN_NONE;
2280 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2282 I915_WRITE(reg, temp);
2284 reg = FDI_RX_CTL(pipe);
2285 temp = I915_READ(reg);
2286 if (HAS_PCH_CPT(dev)) {
2287 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2290 temp &= ~FDI_LINK_TRAIN_NONE;
2291 temp |= FDI_LINK_TRAIN_NONE;
2293 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2295 /* wait one idle pattern time */
2299 /* IVB wants error correction enabled */
2300 if (IS_IVYBRIDGE(dev))
2301 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302 FDI_FE_ERRC_ENABLE);
2305 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 u32 flags = I915_READ(SOUTH_CHICKEN1);
2310 flags |= FDI_PHASE_SYNC_OVR(pipe);
2311 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312 flags |= FDI_PHASE_SYNC_EN(pipe);
2313 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314 POSTING_READ(SOUTH_CHICKEN1);
2317 /* The FDI link training functions for ILK/Ibexpeak. */
2318 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
2324 int plane = intel_crtc->plane;
2325 u32 reg, temp, tries;
2327 /* FDI needs bits from pipe & plane first */
2328 assert_pipe_enabled(dev_priv, pipe);
2329 assert_plane_enabled(dev_priv, plane);
2331 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2333 reg = FDI_RX_IMR(pipe);
2334 temp = I915_READ(reg);
2335 temp &= ~FDI_RX_SYMBOL_LOCK;
2336 temp &= ~FDI_RX_BIT_LOCK;
2337 I915_WRITE(reg, temp);
2341 /* enable CPU FDI TX and PCH FDI RX */
2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
2345 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_PATTERN_1;
2348 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_PATTERN_1;
2354 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2359 /* Ironlake workaround, enable clock pointer after FDI enable*/
2360 if (HAS_PCH_IBX(dev)) {
2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
2366 reg = FDI_RX_IIR(pipe);
2367 for (tries = 0; tries < 5; tries++) {
2368 temp = I915_READ(reg);
2369 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2371 if ((temp & FDI_RX_BIT_LOCK)) {
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
2373 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2378 DRM_ERROR("FDI train 1 fail!\n");
2381 reg = FDI_TX_CTL(pipe);
2382 temp = I915_READ(reg);
2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_2;
2385 I915_WRITE(reg, temp);
2387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_2;
2391 I915_WRITE(reg, temp);
2396 reg = FDI_RX_IIR(pipe);
2397 for (tries = 0; tries < 5; tries++) {
2398 temp = I915_READ(reg);
2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2401 if (temp & FDI_RX_SYMBOL_LOCK) {
2402 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2403 DRM_DEBUG_KMS("FDI train 2 done.\n");
2408 DRM_ERROR("FDI train 2 fail!\n");
2410 DRM_DEBUG_KMS("FDI train done\n");
2414 static const int snb_b_fdi_train_param[] = {
2415 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2421 /* The FDI link training functions for SNB/Cougarpoint. */
2422 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2424 struct drm_device *dev = crtc->dev;
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427 int pipe = intel_crtc->pipe;
2428 u32 reg, temp, i, retry;
2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
2436 I915_WRITE(reg, temp);
2441 /* enable CPU FDI TX and PCH FDI RX */
2442 reg = FDI_TX_CTL(pipe);
2443 temp = I915_READ(reg);
2445 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2450 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2451 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2453 reg = FDI_RX_CTL(pipe);
2454 temp = I915_READ(reg);
2455 if (HAS_PCH_CPT(dev)) {
2456 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_1;
2462 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2467 if (HAS_PCH_CPT(dev))
2468 cpt_phase_pointer_enable(dev, pipe);
2470 for (i = 0; i < 4; i++) {
2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474 temp |= snb_b_fdi_train_param[i];
2475 I915_WRITE(reg, temp);
2480 for (retry = 0; retry < 5; retry++) {
2481 reg = FDI_RX_IIR(pipe);
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484 if (temp & FDI_RX_BIT_LOCK) {
2485 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486 DRM_DEBUG_KMS("FDI train 1 done.\n");
2495 DRM_ERROR("FDI train 1 fail!\n");
2498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_2;
2503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2505 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2507 I915_WRITE(reg, temp);
2509 reg = FDI_RX_CTL(pipe);
2510 temp = I915_READ(reg);
2511 if (HAS_PCH_CPT(dev)) {
2512 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2515 temp &= ~FDI_LINK_TRAIN_NONE;
2516 temp |= FDI_LINK_TRAIN_PATTERN_2;
2518 I915_WRITE(reg, temp);
2523 for (i = 0; i < 4; i++) {
2524 reg = FDI_TX_CTL(pipe);
2525 temp = I915_READ(reg);
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 temp |= snb_b_fdi_train_param[i];
2528 I915_WRITE(reg, temp);
2533 for (retry = 0; retry < 5; retry++) {
2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537 if (temp & FDI_RX_SYMBOL_LOCK) {
2538 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539 DRM_DEBUG_KMS("FDI train 2 done.\n");
2548 DRM_ERROR("FDI train 2 fail!\n");
2550 DRM_DEBUG_KMS("FDI train done.\n");
2553 /* Manual link training for Ivy Bridge A0 parts */
2554 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559 int pipe = intel_crtc->pipe;
2562 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2564 reg = FDI_RX_IMR(pipe);
2565 temp = I915_READ(reg);
2566 temp &= ~FDI_RX_SYMBOL_LOCK;
2567 temp &= ~FDI_RX_BIT_LOCK;
2568 I915_WRITE(reg, temp);
2573 /* enable CPU FDI TX and PCH FDI RX */
2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
2577 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582 temp |= FDI_COMPOSITE_SYNC;
2583 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 temp &= ~FDI_LINK_TRAIN_AUTO;
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590 temp |= FDI_COMPOSITE_SYNC;
2591 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2596 if (HAS_PCH_CPT(dev))
2597 cpt_phase_pointer_enable(dev, pipe);
2599 for (i = 0; i < 4; i++) {
2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
2604 I915_WRITE(reg, temp);
2609 reg = FDI_RX_IIR(pipe);
2610 temp = I915_READ(reg);
2611 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613 if (temp & FDI_RX_BIT_LOCK ||
2614 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616 DRM_DEBUG_KMS("FDI train 1 done.\n");
2621 DRM_ERROR("FDI train 1 fail!\n");
2624 reg = FDI_TX_CTL(pipe);
2625 temp = I915_READ(reg);
2626 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630 I915_WRITE(reg, temp);
2632 reg = FDI_RX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636 I915_WRITE(reg, temp);
2641 for (i = 0; i < 4; i++) {
2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 temp |= snb_b_fdi_train_param[i];
2646 I915_WRITE(reg, temp);
2651 reg = FDI_RX_IIR(pipe);
2652 temp = I915_READ(reg);
2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2655 if (temp & FDI_RX_SYMBOL_LOCK) {
2656 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657 DRM_DEBUG_KMS("FDI train 2 done.\n");
2662 DRM_ERROR("FDI train 2 fail!\n");
2664 DRM_DEBUG_KMS("FDI train done.\n");
2667 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2669 struct drm_device *dev = intel_crtc->base.dev;
2670 struct drm_i915_private *dev_priv = dev->dev_private;
2671 int pipe = intel_crtc->pipe;
2674 /* Write the TU size bits so error detection works */
2675 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2678 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2679 reg = FDI_RX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~((0x7 << 19) | (0x7 << 16));
2682 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2683 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2689 /* Switch from Rawclk to PCDclk */
2690 temp = I915_READ(reg);
2691 I915_WRITE(reg, temp | FDI_PCDCLK);
2696 /* On Haswell, the PLL configuration for ports and pipes is handled
2697 * separately, as part of DDI setup */
2698 if (!IS_HASWELL(dev)) {
2699 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700 reg = FDI_TX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2711 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2713 struct drm_device *dev = intel_crtc->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 int pipe = intel_crtc->pipe;
2718 /* Switch from PCDclk to Rawclk */
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2723 /* Disable CPU FDI TX PLL */
2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2735 /* Wait for the clocks to turn off. */
2740 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 u32 flags = I915_READ(SOUTH_CHICKEN1);
2745 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749 POSTING_READ(SOUTH_CHICKEN1);
2751 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2753 struct drm_device *dev = crtc->dev;
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756 int pipe = intel_crtc->pipe;
2759 /* disable CPU FDI tx and PCH FDI rx */
2760 reg = FDI_TX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~(0x7 << 16);
2768 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2774 /* Ironlake workaround, disable clock pointer after downing FDI */
2775 if (HAS_PCH_IBX(dev)) {
2776 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2777 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778 I915_READ(FDI_RX_CHICKEN(pipe) &
2779 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2780 } else if (HAS_PCH_CPT(dev)) {
2781 cpt_phase_pointer_disable(dev, pipe);
2784 /* still set train pattern 1 */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_PATTERN_1;
2789 I915_WRITE(reg, temp);
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if (HAS_PCH_CPT(dev)) {
2794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2797 temp &= ~FDI_LINK_TRAIN_NONE;
2798 temp |= FDI_LINK_TRAIN_PATTERN_1;
2800 /* BPC in FDI rx is consistent with that in PIPECONF */
2801 temp &= ~(0x07 << 16);
2802 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803 I915_WRITE(reg, temp);
2809 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2811 struct drm_device *dev = crtc->dev;
2813 if (crtc->fb == NULL)
2816 mutex_lock(&dev->struct_mutex);
2817 intel_finish_fb(crtc->fb);
2818 mutex_unlock(&dev->struct_mutex);
2821 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2823 struct drm_device *dev = crtc->dev;
2824 struct intel_encoder *intel_encoder;
2827 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2828 * must be driven by its own crtc; no sharing is possible.
2830 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2832 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2833 * CPU handles all others */
2834 if (IS_HASWELL(dev)) {
2835 /* It is still unclear how this will work on PPT, so throw up a warning */
2836 WARN_ON(!HAS_PCH_LPT(dev));
2838 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2839 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2842 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2843 intel_encoder->type);
2848 switch (intel_encoder->type) {
2849 case INTEL_OUTPUT_EDP:
2850 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2859 /* Program iCLKIP clock to the desired frequency */
2860 static void lpt_program_iclkip(struct drm_crtc *crtc)
2862 struct drm_device *dev = crtc->dev;
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2867 /* It is necessary to ungate the pixclk gate prior to programming
2868 * the divisors, and gate it back when it is done.
2870 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2872 /* Disable SSCCTL */
2873 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2874 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2875 SBI_SSCCTL_DISABLE);
2877 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2878 if (crtc->mode.clock == 20000) {
2883 /* The iCLK virtual clock root frequency is in MHz,
2884 * but the crtc->mode.clock in in KHz. To get the divisors,
2885 * it is necessary to divide one by another, so we
2886 * convert the virtual clock precision to KHz here for higher
2889 u32 iclk_virtual_root_freq = 172800 * 1000;
2890 u32 iclk_pi_range = 64;
2891 u32 desired_divisor, msb_divisor_value, pi_value;
2893 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2894 msb_divisor_value = desired_divisor / iclk_pi_range;
2895 pi_value = desired_divisor % iclk_pi_range;
2898 divsel = msb_divisor_value - 2;
2899 phaseinc = pi_value;
2902 /* This should not happen with any sane values */
2903 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2904 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2905 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2906 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2908 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2915 /* Program SSCDIVINTPHASE6 */
2916 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2917 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2918 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2919 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2920 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2921 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2922 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2924 intel_sbi_write(dev_priv,
2925 SBI_SSCDIVINTPHASE6,
2928 /* Program SSCAUXDIV */
2929 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2930 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2931 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2932 intel_sbi_write(dev_priv,
2937 /* Enable modulator and associated divider */
2938 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2939 temp &= ~SBI_SSCCTL_DISABLE;
2940 intel_sbi_write(dev_priv,
2944 /* Wait for initialization time */
2947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2951 * Enable PCH resources required for PCH ports:
2953 * - FDI training & RX/TX
2954 * - update transcoder timings
2955 * - DP transcoding bits
2958 static void ironlake_pch_enable(struct drm_crtc *crtc)
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
2966 assert_transcoder_disabled(dev_priv, pipe);
2968 /* For PCH output, training FDI link */
2969 dev_priv->display.fdi_link_train(crtc);
2971 intel_enable_pch_pll(intel_crtc);
2973 if (HAS_PCH_LPT(dev)) {
2974 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2975 lpt_program_iclkip(crtc);
2976 } else if (HAS_PCH_CPT(dev)) {
2979 temp = I915_READ(PCH_DPLL_SEL);
2983 temp |= TRANSA_DPLL_ENABLE;
2984 sel = TRANSA_DPLLB_SEL;
2987 temp |= TRANSB_DPLL_ENABLE;
2988 sel = TRANSB_DPLLB_SEL;
2991 temp |= TRANSC_DPLL_ENABLE;
2992 sel = TRANSC_DPLLB_SEL;
2995 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2999 I915_WRITE(PCH_DPLL_SEL, temp);
3002 /* set transcoder timing, panel must allow it */
3003 assert_panel_unlocked(dev_priv, pipe);
3004 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3005 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3006 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3008 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3009 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3010 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3011 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3013 if (!IS_HASWELL(dev))
3014 intel_fdi_normal_train(crtc);
3016 /* For PCH DP, enable TRANS_DP_CTL */
3017 if (HAS_PCH_CPT(dev) &&
3018 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3019 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3020 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3021 reg = TRANS_DP_CTL(pipe);
3022 temp = I915_READ(reg);
3023 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3024 TRANS_DP_SYNC_MASK |
3026 temp |= (TRANS_DP_OUTPUT_ENABLE |
3027 TRANS_DP_ENH_FRAMING);
3028 temp |= bpc << 9; /* same format but at 11:9 */
3030 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3031 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3032 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3033 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3035 switch (intel_trans_dp_port_sel(crtc)) {
3037 temp |= TRANS_DP_PORT_SEL_B;
3040 temp |= TRANS_DP_PORT_SEL_C;
3043 temp |= TRANS_DP_PORT_SEL_D;
3046 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3047 temp |= TRANS_DP_PORT_SEL_B;
3051 I915_WRITE(reg, temp);
3054 intel_enable_transcoder(dev_priv, pipe);
3057 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3059 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3064 if (pll->refcount == 0) {
3065 WARN(1, "bad PCH PLL refcount\n");
3070 intel_crtc->pch_pll = NULL;
3073 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3075 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3076 struct intel_pch_pll *pll;
3079 pll = intel_crtc->pch_pll;
3081 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3082 intel_crtc->base.base.id, pll->pll_reg);
3086 if (HAS_PCH_IBX(dev_priv->dev)) {
3087 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3088 i = intel_crtc->pipe;
3089 pll = &dev_priv->pch_plls[i];
3091 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3092 intel_crtc->base.base.id, pll->pll_reg);
3097 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3098 pll = &dev_priv->pch_plls[i];
3100 /* Only want to check enabled timings first */
3101 if (pll->refcount == 0)
3104 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3105 fp == I915_READ(pll->fp0_reg)) {
3106 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3107 intel_crtc->base.base.id,
3108 pll->pll_reg, pll->refcount, pll->active);
3114 /* Ok no matching timings, maybe there's a free one? */
3115 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3116 pll = &dev_priv->pch_plls[i];
3117 if (pll->refcount == 0) {
3118 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3119 intel_crtc->base.base.id, pll->pll_reg);
3127 intel_crtc->pch_pll = pll;
3129 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3130 prepare: /* separate function? */
3131 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3133 /* Wait for the clocks to stabilize before rewriting the regs */
3134 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3135 POSTING_READ(pll->pll_reg);
3138 I915_WRITE(pll->fp0_reg, fp);
3139 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3144 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3150 temp = I915_READ(dslreg);
3152 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3153 /* Without this, mode sets may fail silently on FDI */
3154 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3156 I915_WRITE(tc2reg, 0);
3157 if (wait_for(I915_READ(dslreg) != temp, 5))
3158 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3162 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3164 struct drm_device *dev = crtc->dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167 struct intel_encoder *encoder;
3168 int pipe = intel_crtc->pipe;
3169 int plane = intel_crtc->plane;
3173 WARN_ON(!crtc->enabled);
3175 if (intel_crtc->active)
3178 intel_crtc->active = true;
3179 intel_update_watermarks(dev);
3181 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3182 temp = I915_READ(PCH_LVDS);
3183 if ((temp & LVDS_PORT_EN) == 0)
3184 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3187 is_pch_port = intel_crtc_driving_pch(crtc);
3190 ironlake_fdi_pll_enable(intel_crtc);
3192 assert_fdi_tx_disabled(dev_priv, pipe);
3193 assert_fdi_rx_disabled(dev_priv, pipe);
3196 for_each_encoder_on_crtc(dev, crtc, encoder)
3197 if (encoder->pre_enable)
3198 encoder->pre_enable(encoder);
3200 if (IS_HASWELL(dev))
3201 intel_ddi_enable_pipe_clock(intel_crtc);
3203 /* Enable panel fitting for LVDS */
3204 if (dev_priv->pch_pf_size &&
3205 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3206 /* Force use of hard-coded filter coefficients
3207 * as some pre-programmed values are broken,
3210 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3211 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3212 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3216 * On ILK+ LUT must be loaded before the pipe is running but with
3219 intel_crtc_load_lut(crtc);
3221 if (IS_HASWELL(dev))
3222 intel_ddi_enable_pipe_func(crtc);
3224 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3225 intel_enable_plane(dev_priv, plane, pipe);
3228 ironlake_pch_enable(crtc);
3230 mutex_lock(&dev->struct_mutex);
3231 intel_update_fbc(dev);
3232 mutex_unlock(&dev->struct_mutex);
3234 intel_crtc_update_cursor(crtc, true);
3236 for_each_encoder_on_crtc(dev, crtc, encoder)
3237 encoder->enable(encoder);
3239 if (HAS_PCH_CPT(dev))
3240 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3243 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3245 struct drm_device *dev = crtc->dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3248 struct intel_encoder *encoder;
3249 int pipe = intel_crtc->pipe;
3250 int plane = intel_crtc->plane;
3254 if (!intel_crtc->active)
3257 for_each_encoder_on_crtc(dev, crtc, encoder)
3258 encoder->disable(encoder);
3260 intel_crtc_wait_for_pending_flips(crtc);
3261 drm_vblank_off(dev, pipe);
3262 intel_crtc_update_cursor(crtc, false);
3264 intel_disable_plane(dev_priv, plane, pipe);
3266 if (dev_priv->cfb_plane == plane)
3267 intel_disable_fbc(dev);
3269 intel_disable_pipe(dev_priv, pipe);
3271 if (IS_HASWELL(dev))
3272 intel_ddi_disable_pipe_func(dev_priv, pipe);
3275 I915_WRITE(PF_CTL(pipe), 0);
3276 I915_WRITE(PF_WIN_SZ(pipe), 0);
3278 if (IS_HASWELL(dev))
3279 intel_ddi_disable_pipe_clock(intel_crtc);
3281 for_each_encoder_on_crtc(dev, crtc, encoder)
3282 if (encoder->post_disable)
3283 encoder->post_disable(encoder);
3285 ironlake_fdi_disable(crtc);
3287 intel_disable_transcoder(dev_priv, pipe);
3289 if (HAS_PCH_CPT(dev)) {
3290 /* disable TRANS_DP_CTL */
3291 reg = TRANS_DP_CTL(pipe);
3292 temp = I915_READ(reg);
3293 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3294 temp |= TRANS_DP_PORT_SEL_NONE;
3295 I915_WRITE(reg, temp);
3297 /* disable DPLL_SEL */
3298 temp = I915_READ(PCH_DPLL_SEL);
3301 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3304 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3307 /* C shares PLL A or B */
3308 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3313 I915_WRITE(PCH_DPLL_SEL, temp);
3316 /* disable PCH DPLL */
3317 intel_disable_pch_pll(intel_crtc);
3319 ironlake_fdi_pll_disable(intel_crtc);
3321 intel_crtc->active = false;
3322 intel_update_watermarks(dev);
3324 mutex_lock(&dev->struct_mutex);
3325 intel_update_fbc(dev);
3326 mutex_unlock(&dev->struct_mutex);
3329 static void ironlake_crtc_off(struct drm_crtc *crtc)
3331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3332 intel_put_pch_pll(intel_crtc);
3335 static void haswell_crtc_off(struct drm_crtc *crtc)
3337 intel_ddi_put_crtc_pll(crtc);
3340 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3342 if (!enable && intel_crtc->overlay) {
3343 struct drm_device *dev = intel_crtc->base.dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3346 mutex_lock(&dev->struct_mutex);
3347 dev_priv->mm.interruptible = false;
3348 (void) intel_overlay_switch_off(intel_crtc->overlay);
3349 dev_priv->mm.interruptible = true;
3350 mutex_unlock(&dev->struct_mutex);
3353 /* Let userspace switch the overlay on again. In most cases userspace
3354 * has to recompute where to put it anyway.
3358 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3360 struct drm_device *dev = crtc->dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3363 struct intel_encoder *encoder;
3364 int pipe = intel_crtc->pipe;
3365 int plane = intel_crtc->plane;
3367 WARN_ON(!crtc->enabled);
3369 if (intel_crtc->active)
3372 intel_crtc->active = true;
3373 intel_update_watermarks(dev);
3375 intel_enable_pll(dev_priv, pipe);
3376 intel_enable_pipe(dev_priv, pipe, false);
3377 intel_enable_plane(dev_priv, plane, pipe);
3379 intel_crtc_load_lut(crtc);
3380 intel_update_fbc(dev);
3382 /* Give the overlay scaler a chance to enable if it's on this pipe */
3383 intel_crtc_dpms_overlay(intel_crtc, true);
3384 intel_crtc_update_cursor(crtc, true);
3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->enable(encoder);
3390 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3392 struct drm_device *dev = crtc->dev;
3393 struct drm_i915_private *dev_priv = dev->dev_private;
3394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3395 struct intel_encoder *encoder;
3396 int pipe = intel_crtc->pipe;
3397 int plane = intel_crtc->plane;
3400 if (!intel_crtc->active)
3403 for_each_encoder_on_crtc(dev, crtc, encoder)
3404 encoder->disable(encoder);
3406 /* Give the overlay scaler a chance to disable if it's on this pipe */
3407 intel_crtc_wait_for_pending_flips(crtc);
3408 drm_vblank_off(dev, pipe);
3409 intel_crtc_dpms_overlay(intel_crtc, false);
3410 intel_crtc_update_cursor(crtc, false);
3412 if (dev_priv->cfb_plane == plane)
3413 intel_disable_fbc(dev);
3415 intel_disable_plane(dev_priv, plane, pipe);
3416 intel_disable_pipe(dev_priv, pipe);
3417 intel_disable_pll(dev_priv, pipe);
3419 intel_crtc->active = false;
3420 intel_update_fbc(dev);
3421 intel_update_watermarks(dev);
3424 static void i9xx_crtc_off(struct drm_crtc *crtc)
3428 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3431 struct drm_device *dev = crtc->dev;
3432 struct drm_i915_master_private *master_priv;
3433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3434 int pipe = intel_crtc->pipe;
3436 if (!dev->primary->master)
3439 master_priv = dev->primary->master->driver_priv;
3440 if (!master_priv->sarea_priv)
3445 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3446 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3449 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3450 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3453 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3459 * Sets the power management mode of the pipe and plane.
3461 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3463 struct drm_device *dev = crtc->dev;
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465 struct intel_encoder *intel_encoder;
3466 bool enable = false;
3468 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3469 enable |= intel_encoder->connectors_active;
3472 dev_priv->display.crtc_enable(crtc);
3474 dev_priv->display.crtc_disable(crtc);
3476 intel_crtc_update_sarea(crtc, enable);
3479 static void intel_crtc_noop(struct drm_crtc *crtc)
3483 static void intel_crtc_disable(struct drm_crtc *crtc)
3485 struct drm_device *dev = crtc->dev;
3486 struct drm_connector *connector;
3487 struct drm_i915_private *dev_priv = dev->dev_private;
3489 /* crtc should still be enabled when we disable it. */
3490 WARN_ON(!crtc->enabled);
3492 dev_priv->display.crtc_disable(crtc);
3493 intel_crtc_update_sarea(crtc, false);
3494 dev_priv->display.off(crtc);
3496 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3497 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3500 mutex_lock(&dev->struct_mutex);
3501 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3502 mutex_unlock(&dev->struct_mutex);
3506 /* Update computed state. */
3507 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3508 if (!connector->encoder || !connector->encoder->crtc)
3511 if (connector->encoder->crtc != crtc)
3514 connector->dpms = DRM_MODE_DPMS_OFF;
3515 to_intel_encoder(connector->encoder)->connectors_active = false;
3519 void intel_modeset_disable(struct drm_device *dev)
3521 struct drm_crtc *crtc;
3523 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3525 intel_crtc_disable(crtc);
3529 void intel_encoder_noop(struct drm_encoder *encoder)
3533 void intel_encoder_destroy(struct drm_encoder *encoder)
3535 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3537 drm_encoder_cleanup(encoder);
3538 kfree(intel_encoder);
3541 /* Simple dpms helper for encodres with just one connector, no cloning and only
3542 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3543 * state of the entire output pipe. */
3544 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3546 if (mode == DRM_MODE_DPMS_ON) {
3547 encoder->connectors_active = true;
3549 intel_crtc_update_dpms(encoder->base.crtc);
3551 encoder->connectors_active = false;
3553 intel_crtc_update_dpms(encoder->base.crtc);
3557 /* Cross check the actual hw state with our own modeset state tracking (and it's
3558 * internal consistency). */
3559 static void intel_connector_check_state(struct intel_connector *connector)
3561 if (connector->get_hw_state(connector)) {
3562 struct intel_encoder *encoder = connector->encoder;
3563 struct drm_crtc *crtc;
3564 bool encoder_enabled;
3567 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3568 connector->base.base.id,
3569 drm_get_connector_name(&connector->base));
3571 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3572 "wrong connector dpms state\n");
3573 WARN(connector->base.encoder != &encoder->base,
3574 "active connector not linked to encoder\n");
3575 WARN(!encoder->connectors_active,
3576 "encoder->connectors_active not set\n");
3578 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3579 WARN(!encoder_enabled, "encoder not enabled\n");
3580 if (WARN_ON(!encoder->base.crtc))
3583 crtc = encoder->base.crtc;
3585 WARN(!crtc->enabled, "crtc not enabled\n");
3586 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3587 WARN(pipe != to_intel_crtc(crtc)->pipe,
3588 "encoder active on the wrong pipe\n");
3592 /* Even simpler default implementation, if there's really no special case to
3594 void intel_connector_dpms(struct drm_connector *connector, int mode)
3596 struct intel_encoder *encoder = intel_attached_encoder(connector);
3598 /* All the simple cases only support two dpms states. */
3599 if (mode != DRM_MODE_DPMS_ON)
3600 mode = DRM_MODE_DPMS_OFF;
3602 if (mode == connector->dpms)
3605 connector->dpms = mode;
3607 /* Only need to change hw state when actually enabled */
3608 if (encoder->base.crtc)
3609 intel_encoder_dpms(encoder, mode);
3611 WARN_ON(encoder->connectors_active != false);
3613 intel_modeset_check_state(connector->dev);
3616 /* Simple connector->get_hw_state implementation for encoders that support only
3617 * one connector and no cloning and hence the encoder state determines the state
3618 * of the connector. */
3619 bool intel_connector_get_hw_state(struct intel_connector *connector)
3622 struct intel_encoder *encoder = connector->encoder;
3624 return encoder->get_hw_state(encoder, &pipe);
3627 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3628 const struct drm_display_mode *mode,
3629 struct drm_display_mode *adjusted_mode)
3631 struct drm_device *dev = crtc->dev;
3633 if (HAS_PCH_SPLIT(dev)) {
3634 /* FDI link clock is fixed at 2.7G */
3635 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3639 /* All interlaced capable intel hw wants timings in frames. Note though
3640 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3641 * timings, so we need to be careful not to clobber these.*/
3642 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3643 drm_mode_set_crtcinfo(adjusted_mode, 0);
3645 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3646 * with a hsync front porch of 0.
3648 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3649 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3655 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3657 return 400000; /* FIXME */
3660 static int i945_get_display_clock_speed(struct drm_device *dev)
3665 static int i915_get_display_clock_speed(struct drm_device *dev)
3670 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3675 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3679 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3681 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3684 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3685 case GC_DISPLAY_CLOCK_333_MHZ:
3688 case GC_DISPLAY_CLOCK_190_200_MHZ:
3694 static int i865_get_display_clock_speed(struct drm_device *dev)
3699 static int i855_get_display_clock_speed(struct drm_device *dev)
3702 /* Assume that the hardware is in the high speed state. This
3703 * should be the default.
3705 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3706 case GC_CLOCK_133_200:
3707 case GC_CLOCK_100_200:
3709 case GC_CLOCK_166_250:
3711 case GC_CLOCK_100_133:
3715 /* Shouldn't happen */
3719 static int i830_get_display_clock_speed(struct drm_device *dev)
3733 fdi_reduce_ratio(u32 *num, u32 *den)
3735 while (*num > 0xffffff || *den > 0xffffff) {
3742 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3743 int link_clock, struct fdi_m_n *m_n)
3745 m_n->tu = 64; /* default size */
3747 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3748 m_n->gmch_m = bits_per_pixel * pixel_clock;
3749 m_n->gmch_n = link_clock * nlanes * 8;
3750 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3752 m_n->link_m = pixel_clock;
3753 m_n->link_n = link_clock;
3754 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3757 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3759 if (i915_panel_use_ssc >= 0)
3760 return i915_panel_use_ssc != 0;
3761 return dev_priv->lvds_use_ssc
3762 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3766 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3767 * @crtc: CRTC structure
3768 * @mode: requested mode
3770 * A pipe may be connected to one or more outputs. Based on the depth of the
3771 * attached framebuffer, choose a good color depth to use on the pipe.
3773 * If possible, match the pipe depth to the fb depth. In some cases, this
3774 * isn't ideal, because the connected output supports a lesser or restricted
3775 * set of depths. Resolve that here:
3776 * LVDS typically supports only 6bpc, so clamp down in that case
3777 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3778 * Displays may support a restricted set as well, check EDID and clamp as
3780 * DP may want to dither down to 6bpc to fit larger modes
3783 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3784 * true if they don't match).
3786 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3787 struct drm_framebuffer *fb,
3788 unsigned int *pipe_bpp,
3789 struct drm_display_mode *mode)
3791 struct drm_device *dev = crtc->dev;
3792 struct drm_i915_private *dev_priv = dev->dev_private;
3793 struct drm_connector *connector;
3794 struct intel_encoder *intel_encoder;
3795 unsigned int display_bpc = UINT_MAX, bpc;
3797 /* Walk the encoders & connectors on this crtc, get min bpc */
3798 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3800 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3801 unsigned int lvds_bpc;
3803 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3809 if (lvds_bpc < display_bpc) {
3810 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3811 display_bpc = lvds_bpc;
3816 /* Not one of the known troublemakers, check the EDID */
3817 list_for_each_entry(connector, &dev->mode_config.connector_list,
3819 if (connector->encoder != &intel_encoder->base)
3822 /* Don't use an invalid EDID bpc value */
3823 if (connector->display_info.bpc &&
3824 connector->display_info.bpc < display_bpc) {
3825 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3826 display_bpc = connector->display_info.bpc;
3831 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3832 * through, clamp it down. (Note: >12bpc will be caught below.)
3834 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3835 if (display_bpc > 8 && display_bpc < 12) {
3836 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3839 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3845 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3846 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3851 * We could just drive the pipe at the highest bpc all the time and
3852 * enable dithering as needed, but that costs bandwidth. So choose
3853 * the minimum value that expresses the full color range of the fb but
3854 * also stays within the max display bpc discovered above.
3857 switch (fb->depth) {
3859 bpc = 8; /* since we go through a colormap */
3863 bpc = 6; /* min is 18bpp */
3875 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3876 bpc = min((unsigned int)8, display_bpc);
3880 display_bpc = min(display_bpc, bpc);
3882 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3885 *pipe_bpp = display_bpc * 3;
3887 return display_bpc != bpc;
3890 static int vlv_get_refclk(struct drm_crtc *crtc)
3892 struct drm_device *dev = crtc->dev;
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 int refclk = 27000; /* for DP & HDMI */
3896 return 100000; /* only one validated so far */
3898 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3900 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3901 if (intel_panel_use_ssc(dev_priv))
3905 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3912 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3914 struct drm_device *dev = crtc->dev;
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3918 if (IS_VALLEYVIEW(dev)) {
3919 refclk = vlv_get_refclk(crtc);
3920 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3921 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3922 refclk = dev_priv->lvds_ssc_freq * 1000;
3923 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3925 } else if (!IS_GEN2(dev)) {
3934 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3935 intel_clock_t *clock)
3937 /* SDVO TV has fixed PLL values depend on its clock range,
3938 this mirrors vbios setting. */
3939 if (adjusted_mode->clock >= 100000
3940 && adjusted_mode->clock < 140500) {
3946 } else if (adjusted_mode->clock >= 140500
3947 && adjusted_mode->clock <= 200000) {
3956 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3957 intel_clock_t *clock,
3958 intel_clock_t *reduced_clock)
3960 struct drm_device *dev = crtc->dev;
3961 struct drm_i915_private *dev_priv = dev->dev_private;
3962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3963 int pipe = intel_crtc->pipe;
3966 if (IS_PINEVIEW(dev)) {
3967 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3969 fp2 = (1 << reduced_clock->n) << 16 |
3970 reduced_clock->m1 << 8 | reduced_clock->m2;
3972 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3974 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3978 I915_WRITE(FP0(pipe), fp);
3980 intel_crtc->lowfreq_avail = false;
3981 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3982 reduced_clock && i915_powersave) {
3983 I915_WRITE(FP1(pipe), fp2);
3984 intel_crtc->lowfreq_avail = true;
3986 I915_WRITE(FP1(pipe), fp);
3990 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3991 struct drm_display_mode *adjusted_mode)
3993 struct drm_device *dev = crtc->dev;
3994 struct drm_i915_private *dev_priv = dev->dev_private;
3995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996 int pipe = intel_crtc->pipe;
3999 temp = I915_READ(LVDS);
4000 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4002 temp |= LVDS_PIPEB_SELECT;
4004 temp &= ~LVDS_PIPEB_SELECT;
4006 /* set the corresponsding LVDS_BORDER bit */
4007 temp |= dev_priv->lvds_border_bits;
4008 /* Set the B0-B3 data pairs corresponding to whether we're going to
4009 * set the DPLLs for dual-channel mode or not.
4012 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4014 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4016 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4017 * appropriately here, but we need to look more thoroughly into how
4018 * panels behave in the two modes.
4020 /* set the dithering flag on LVDS as needed */
4021 if (INTEL_INFO(dev)->gen >= 4) {
4022 if (dev_priv->lvds_dither)
4023 temp |= LVDS_ENABLE_DITHER;
4025 temp &= ~LVDS_ENABLE_DITHER;
4027 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4028 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4029 temp |= LVDS_HSYNC_POLARITY;
4030 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4031 temp |= LVDS_VSYNC_POLARITY;
4032 I915_WRITE(LVDS, temp);
4035 static void vlv_update_pll(struct drm_crtc *crtc,
4036 struct drm_display_mode *mode,
4037 struct drm_display_mode *adjusted_mode,
4038 intel_clock_t *clock, intel_clock_t *reduced_clock,
4041 struct drm_device *dev = crtc->dev;
4042 struct drm_i915_private *dev_priv = dev->dev_private;
4043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4044 int pipe = intel_crtc->pipe;
4045 u32 dpll, mdiv, pdiv;
4046 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4050 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4051 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4053 dpll = DPLL_VGA_MODE_DIS;
4054 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4055 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4056 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4058 I915_WRITE(DPLL(pipe), dpll);
4059 POSTING_READ(DPLL(pipe));
4068 * In Valleyview PLL and program lane counter registers are exposed
4069 * through DPIO interface
4071 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4072 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4073 mdiv |= ((bestn << DPIO_N_SHIFT));
4074 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4075 mdiv |= (1 << DPIO_K_SHIFT);
4076 mdiv |= DPIO_ENABLE_CALIBRATION;
4077 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4079 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4081 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4082 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4083 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4084 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4085 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4087 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4089 dpll |= DPLL_VCO_ENABLE;
4090 I915_WRITE(DPLL(pipe), dpll);
4091 POSTING_READ(DPLL(pipe));
4092 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4093 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4095 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4097 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4098 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4100 I915_WRITE(DPLL(pipe), dpll);
4102 /* Wait for the clocks to stabilize. */
4103 POSTING_READ(DPLL(pipe));
4108 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4110 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4114 I915_WRITE(DPLL_MD(pipe), temp);
4115 POSTING_READ(DPLL_MD(pipe));
4117 /* Now program lane control registers */
4118 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4119 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4124 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4126 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4131 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4135 static void i9xx_update_pll(struct drm_crtc *crtc,
4136 struct drm_display_mode *mode,
4137 struct drm_display_mode *adjusted_mode,
4138 intel_clock_t *clock, intel_clock_t *reduced_clock,
4141 struct drm_device *dev = crtc->dev;
4142 struct drm_i915_private *dev_priv = dev->dev_private;
4143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4144 int pipe = intel_crtc->pipe;
4148 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4150 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4151 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4153 dpll = DPLL_VGA_MODE_DIS;
4155 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4156 dpll |= DPLLB_MODE_LVDS;
4158 dpll |= DPLLB_MODE_DAC_SERIAL;
4160 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4161 if (pixel_multiplier > 1) {
4162 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4163 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4165 dpll |= DPLL_DVO_HIGH_SPEED;
4167 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4168 dpll |= DPLL_DVO_HIGH_SPEED;
4170 /* compute bitmask from p1 value */
4171 if (IS_PINEVIEW(dev))
4172 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4174 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4175 if (IS_G4X(dev) && reduced_clock)
4176 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4178 switch (clock->p2) {
4180 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4183 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4186 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4189 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4192 if (INTEL_INFO(dev)->gen >= 4)
4193 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4195 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4196 dpll |= PLL_REF_INPUT_TVCLKINBC;
4197 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4198 /* XXX: just matching BIOS for now */
4199 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4201 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4202 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4203 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4205 dpll |= PLL_REF_INPUT_DREFCLK;
4207 dpll |= DPLL_VCO_ENABLE;
4208 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4209 POSTING_READ(DPLL(pipe));
4212 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4213 * This is an exception to the general rule that mode_set doesn't turn
4216 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4217 intel_update_lvds(crtc, clock, adjusted_mode);
4219 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4220 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4222 I915_WRITE(DPLL(pipe), dpll);
4224 /* Wait for the clocks to stabilize. */
4225 POSTING_READ(DPLL(pipe));
4228 if (INTEL_INFO(dev)->gen >= 4) {
4231 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4233 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4237 I915_WRITE(DPLL_MD(pipe), temp);
4239 /* The pixel multiplier can only be updated once the
4240 * DPLL is enabled and the clocks are stable.
4242 * So write it again.
4244 I915_WRITE(DPLL(pipe), dpll);
4248 static void i8xx_update_pll(struct drm_crtc *crtc,
4249 struct drm_display_mode *adjusted_mode,
4250 intel_clock_t *clock, intel_clock_t *reduced_clock,
4253 struct drm_device *dev = crtc->dev;
4254 struct drm_i915_private *dev_priv = dev->dev_private;
4255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4256 int pipe = intel_crtc->pipe;
4259 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4261 dpll = DPLL_VGA_MODE_DIS;
4263 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4264 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4267 dpll |= PLL_P1_DIVIDE_BY_TWO;
4269 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4271 dpll |= PLL_P2_DIVIDE_BY_4;
4274 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4275 /* XXX: just matching BIOS for now */
4276 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4278 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4279 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4280 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4282 dpll |= PLL_REF_INPUT_DREFCLK;
4284 dpll |= DPLL_VCO_ENABLE;
4285 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4286 POSTING_READ(DPLL(pipe));
4289 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4290 * This is an exception to the general rule that mode_set doesn't turn
4293 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4294 intel_update_lvds(crtc, clock, adjusted_mode);
4296 I915_WRITE(DPLL(pipe), dpll);
4298 /* Wait for the clocks to stabilize. */
4299 POSTING_READ(DPLL(pipe));
4302 /* The pixel multiplier can only be updated once the
4303 * DPLL is enabled and the clocks are stable.
4305 * So write it again.
4307 I915_WRITE(DPLL(pipe), dpll);
4310 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4311 struct drm_display_mode *mode,
4312 struct drm_display_mode *adjusted_mode)
4314 struct drm_device *dev = intel_crtc->base.dev;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 enum pipe pipe = intel_crtc->pipe;
4317 uint32_t vsyncshift;
4319 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4320 /* the chip adds 2 halflines automatically */
4321 adjusted_mode->crtc_vtotal -= 1;
4322 adjusted_mode->crtc_vblank_end -= 1;
4323 vsyncshift = adjusted_mode->crtc_hsync_start
4324 - adjusted_mode->crtc_htotal / 2;
4329 if (INTEL_INFO(dev)->gen > 3)
4330 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4332 I915_WRITE(HTOTAL(pipe),
4333 (adjusted_mode->crtc_hdisplay - 1) |
4334 ((adjusted_mode->crtc_htotal - 1) << 16));
4335 I915_WRITE(HBLANK(pipe),
4336 (adjusted_mode->crtc_hblank_start - 1) |
4337 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4338 I915_WRITE(HSYNC(pipe),
4339 (adjusted_mode->crtc_hsync_start - 1) |
4340 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4342 I915_WRITE(VTOTAL(pipe),
4343 (adjusted_mode->crtc_vdisplay - 1) |
4344 ((adjusted_mode->crtc_vtotal - 1) << 16));
4345 I915_WRITE(VBLANK(pipe),
4346 (adjusted_mode->crtc_vblank_start - 1) |
4347 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4348 I915_WRITE(VSYNC(pipe),
4349 (adjusted_mode->crtc_vsync_start - 1) |
4350 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4352 /* pipesrc controls the size that is scaled from, which should
4353 * always be the user's requested size.
4355 I915_WRITE(PIPESRC(pipe),
4356 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4359 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4360 struct drm_display_mode *mode,
4361 struct drm_display_mode *adjusted_mode,
4363 struct drm_framebuffer *fb)
4365 struct drm_device *dev = crtc->dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4368 int pipe = intel_crtc->pipe;
4369 int plane = intel_crtc->plane;
4370 int refclk, num_connectors = 0;
4371 intel_clock_t clock, reduced_clock;
4372 u32 dspcntr, pipeconf;
4373 bool ok, has_reduced_clock = false, is_sdvo = false;
4374 bool is_lvds = false, is_tv = false, is_dp = false;
4375 struct intel_encoder *encoder;
4376 const intel_limit_t *limit;
4379 for_each_encoder_on_crtc(dev, crtc, encoder) {
4380 switch (encoder->type) {
4381 case INTEL_OUTPUT_LVDS:
4384 case INTEL_OUTPUT_SDVO:
4385 case INTEL_OUTPUT_HDMI:
4387 if (encoder->needs_tv_clock)
4390 case INTEL_OUTPUT_TVOUT:
4393 case INTEL_OUTPUT_DISPLAYPORT:
4401 refclk = i9xx_get_refclk(crtc, num_connectors);
4404 * Returns a set of divisors for the desired target clock with the given
4405 * refclk, or FALSE. The returned values represent the clock equation:
4406 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4408 limit = intel_limit(crtc, refclk);
4409 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4412 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4416 /* Ensure that the cursor is valid for the new mode before changing... */
4417 intel_crtc_update_cursor(crtc, true);
4419 if (is_lvds && dev_priv->lvds_downclock_avail) {
4421 * Ensure we match the reduced clock's P to the target clock.
4422 * If the clocks don't match, we can't switch the display clock
4423 * by using the FP0/FP1. In such case we will disable the LVDS
4424 * downclock feature.
4426 has_reduced_clock = limit->find_pll(limit, crtc,
4427 dev_priv->lvds_downclock,
4433 if (is_sdvo && is_tv)
4434 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4437 i8xx_update_pll(crtc, adjusted_mode, &clock,
4438 has_reduced_clock ? &reduced_clock : NULL,
4440 else if (IS_VALLEYVIEW(dev))
4441 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4442 has_reduced_clock ? &reduced_clock : NULL,
4445 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4446 has_reduced_clock ? &reduced_clock : NULL,
4449 /* setup pipeconf */
4450 pipeconf = I915_READ(PIPECONF(pipe));
4452 /* Set up the display plane register */
4453 dspcntr = DISPPLANE_GAMMA_ENABLE;
4456 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4458 dspcntr |= DISPPLANE_SEL_PIPE_B;
4460 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4461 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4464 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4468 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4469 pipeconf |= PIPECONF_DOUBLE_WIDE;
4471 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4474 /* default to 8bpc */
4475 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4477 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4478 pipeconf |= PIPECONF_BPP_6 |
4479 PIPECONF_DITHER_EN |
4480 PIPECONF_DITHER_TYPE_SP;
4484 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4485 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4486 pipeconf |= PIPECONF_BPP_6 |
4488 I965_PIPECONF_ACTIVE;
4492 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4493 drm_mode_debug_printmodeline(mode);
4495 if (HAS_PIPE_CXSR(dev)) {
4496 if (intel_crtc->lowfreq_avail) {
4497 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4498 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4500 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4501 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4505 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4506 if (!IS_GEN2(dev) &&
4507 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4508 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4510 pipeconf |= PIPECONF_PROGRESSIVE;
4512 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4514 /* pipesrc and dspsize control the size that is scaled from,
4515 * which should always be the user's requested size.
4517 I915_WRITE(DSPSIZE(plane),
4518 ((mode->vdisplay - 1) << 16) |
4519 (mode->hdisplay - 1));
4520 I915_WRITE(DSPPOS(plane), 0);
4522 I915_WRITE(PIPECONF(pipe), pipeconf);
4523 POSTING_READ(PIPECONF(pipe));
4524 intel_enable_pipe(dev_priv, pipe, false);
4526 intel_wait_for_vblank(dev, pipe);
4528 I915_WRITE(DSPCNTR(plane), dspcntr);
4529 POSTING_READ(DSPCNTR(plane));
4531 ret = intel_pipe_set_base(crtc, x, y, fb);
4533 intel_update_watermarks(dev);
4539 * Initialize reference clocks when the driver loads
4541 void ironlake_init_pch_refclk(struct drm_device *dev)
4543 struct drm_i915_private *dev_priv = dev->dev_private;
4544 struct drm_mode_config *mode_config = &dev->mode_config;
4545 struct intel_encoder *encoder;
4547 bool has_lvds = false;
4548 bool has_cpu_edp = false;
4549 bool has_pch_edp = false;
4550 bool has_panel = false;
4551 bool has_ck505 = false;
4552 bool can_ssc = false;
4554 /* We need to take the global config into account */
4555 list_for_each_entry(encoder, &mode_config->encoder_list,
4557 switch (encoder->type) {
4558 case INTEL_OUTPUT_LVDS:
4562 case INTEL_OUTPUT_EDP:
4564 if (intel_encoder_is_pch_edp(&encoder->base))
4572 if (HAS_PCH_IBX(dev)) {
4573 has_ck505 = dev_priv->display_clock_mode;
4574 can_ssc = has_ck505;
4580 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4581 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4584 /* Ironlake: try to setup display ref clock before DPLL
4585 * enabling. This is only under driver's control after
4586 * PCH B stepping, previous chipset stepping should be
4587 * ignoring this setting.
4589 temp = I915_READ(PCH_DREF_CONTROL);
4590 /* Always enable nonspread source */
4591 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4594 temp |= DREF_NONSPREAD_CK505_ENABLE;
4596 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4599 temp &= ~DREF_SSC_SOURCE_MASK;
4600 temp |= DREF_SSC_SOURCE_ENABLE;
4602 /* SSC must be turned on before enabling the CPU output */
4603 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4604 DRM_DEBUG_KMS("Using SSC on panel\n");
4605 temp |= DREF_SSC1_ENABLE;
4607 temp &= ~DREF_SSC1_ENABLE;
4609 /* Get SSC going before enabling the outputs */
4610 I915_WRITE(PCH_DREF_CONTROL, temp);
4611 POSTING_READ(PCH_DREF_CONTROL);
4614 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4616 /* Enable CPU source on CPU attached eDP */
4618 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4619 DRM_DEBUG_KMS("Using SSC on eDP\n");
4620 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4623 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4625 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4627 I915_WRITE(PCH_DREF_CONTROL, temp);
4628 POSTING_READ(PCH_DREF_CONTROL);
4631 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4633 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4635 /* Turn off CPU output */
4636 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4638 I915_WRITE(PCH_DREF_CONTROL, temp);
4639 POSTING_READ(PCH_DREF_CONTROL);
4642 /* Turn off the SSC source */
4643 temp &= ~DREF_SSC_SOURCE_MASK;
4644 temp |= DREF_SSC_SOURCE_DISABLE;
4647 temp &= ~ DREF_SSC1_ENABLE;
4649 I915_WRITE(PCH_DREF_CONTROL, temp);
4650 POSTING_READ(PCH_DREF_CONTROL);
4655 static int ironlake_get_refclk(struct drm_crtc *crtc)
4657 struct drm_device *dev = crtc->dev;
4658 struct drm_i915_private *dev_priv = dev->dev_private;
4659 struct intel_encoder *encoder;
4660 struct intel_encoder *edp_encoder = NULL;
4661 int num_connectors = 0;
4662 bool is_lvds = false;
4664 for_each_encoder_on_crtc(dev, crtc, encoder) {
4665 switch (encoder->type) {
4666 case INTEL_OUTPUT_LVDS:
4669 case INTEL_OUTPUT_EDP:
4670 edp_encoder = encoder;
4676 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4677 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4678 dev_priv->lvds_ssc_freq);
4679 return dev_priv->lvds_ssc_freq * 1000;
4685 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4686 struct drm_display_mode *adjusted_mode,
4689 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4691 int pipe = intel_crtc->pipe;
4694 val = I915_READ(PIPECONF(pipe));
4696 val &= ~PIPE_BPC_MASK;
4697 switch (intel_crtc->bpp) {
4711 /* Case prevented by intel_choose_pipe_bpp_dither. */
4715 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4717 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4719 val &= ~PIPECONF_INTERLACE_MASK;
4720 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4721 val |= PIPECONF_INTERLACED_ILK;
4723 val |= PIPECONF_PROGRESSIVE;
4725 I915_WRITE(PIPECONF(pipe), val);
4726 POSTING_READ(PIPECONF(pipe));
4729 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4730 struct drm_display_mode *adjusted_mode,
4733 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4735 int pipe = intel_crtc->pipe;
4738 val = I915_READ(PIPECONF(pipe));
4740 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4742 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4744 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4745 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4746 val |= PIPECONF_INTERLACED_ILK;
4748 val |= PIPECONF_PROGRESSIVE;
4750 I915_WRITE(PIPECONF(pipe), val);
4751 POSTING_READ(PIPECONF(pipe));
4754 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4755 struct drm_display_mode *adjusted_mode,
4756 intel_clock_t *clock,
4757 bool *has_reduced_clock,
4758 intel_clock_t *reduced_clock)
4760 struct drm_device *dev = crtc->dev;
4761 struct drm_i915_private *dev_priv = dev->dev_private;
4762 struct intel_encoder *intel_encoder;
4764 const intel_limit_t *limit;
4765 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4767 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4768 switch (intel_encoder->type) {
4769 case INTEL_OUTPUT_LVDS:
4772 case INTEL_OUTPUT_SDVO:
4773 case INTEL_OUTPUT_HDMI:
4775 if (intel_encoder->needs_tv_clock)
4778 case INTEL_OUTPUT_TVOUT:
4784 refclk = ironlake_get_refclk(crtc);
4787 * Returns a set of divisors for the desired target clock with the given
4788 * refclk, or FALSE. The returned values represent the clock equation:
4789 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4791 limit = intel_limit(crtc, refclk);
4792 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4797 if (is_lvds && dev_priv->lvds_downclock_avail) {
4799 * Ensure we match the reduced clock's P to the target clock.
4800 * If the clocks don't match, we can't switch the display clock
4801 * by using the FP0/FP1. In such case we will disable the LVDS
4802 * downclock feature.
4804 *has_reduced_clock = limit->find_pll(limit, crtc,
4805 dev_priv->lvds_downclock,
4811 if (is_sdvo && is_tv)
4812 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4817 static void ironlake_set_m_n(struct drm_crtc *crtc,
4818 struct drm_display_mode *mode,
4819 struct drm_display_mode *adjusted_mode)
4821 struct drm_device *dev = crtc->dev;
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4824 enum pipe pipe = intel_crtc->pipe;
4825 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4826 struct fdi_m_n m_n = {0};
4827 int target_clock, pixel_multiplier, lane, link_bw;
4828 bool is_dp = false, is_cpu_edp = false;
4830 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4831 switch (intel_encoder->type) {
4832 case INTEL_OUTPUT_DISPLAYPORT:
4835 case INTEL_OUTPUT_EDP:
4837 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4839 edp_encoder = intel_encoder;
4845 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4847 /* CPU eDP doesn't require FDI link, so just set DP M/N
4848 according to current link config */
4850 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4852 /* FDI is a binary signal running at ~2.7GHz, encoding
4853 * each output octet as 10 bits. The actual frequency
4854 * is stored as a divider into a 100MHz clock, and the
4855 * mode pixel clock is stored in units of 1KHz.
4856 * Hence the bw of each lane in terms of the mode signal
4859 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4862 /* [e]DP over FDI requires target mode clock instead of link clock. */
4864 target_clock = intel_edp_target_clock(edp_encoder, mode);
4866 target_clock = mode->clock;
4868 target_clock = adjusted_mode->clock;
4872 * Account for spread spectrum to avoid
4873 * oversubscribing the link. Max center spread
4874 * is 2.5%; use 5% for safety's sake.
4876 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4877 lane = bps / (link_bw * 8) + 1;
4880 intel_crtc->fdi_lanes = lane;
4882 if (pixel_multiplier > 1)
4883 link_bw *= pixel_multiplier;
4884 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4887 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4888 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4889 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4890 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4893 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4894 struct drm_display_mode *adjusted_mode,
4895 intel_clock_t *clock, u32 fp)
4897 struct drm_crtc *crtc = &intel_crtc->base;
4898 struct drm_device *dev = crtc->dev;
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900 struct intel_encoder *intel_encoder;
4902 int factor, pixel_multiplier, num_connectors = 0;
4903 bool is_lvds = false, is_sdvo = false, is_tv = false;
4904 bool is_dp = false, is_cpu_edp = false;
4906 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4907 switch (intel_encoder->type) {
4908 case INTEL_OUTPUT_LVDS:
4911 case INTEL_OUTPUT_SDVO:
4912 case INTEL_OUTPUT_HDMI:
4914 if (intel_encoder->needs_tv_clock)
4917 case INTEL_OUTPUT_TVOUT:
4920 case INTEL_OUTPUT_DISPLAYPORT:
4923 case INTEL_OUTPUT_EDP:
4925 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4933 /* Enable autotuning of the PLL clock (if permissible) */
4936 if ((intel_panel_use_ssc(dev_priv) &&
4937 dev_priv->lvds_ssc_freq == 100) ||
4938 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4940 } else if (is_sdvo && is_tv)
4943 if (clock->m < factor * clock->n)
4949 dpll |= DPLLB_MODE_LVDS;
4951 dpll |= DPLLB_MODE_DAC_SERIAL;
4953 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4954 if (pixel_multiplier > 1) {
4955 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4957 dpll |= DPLL_DVO_HIGH_SPEED;
4959 if (is_dp && !is_cpu_edp)
4960 dpll |= DPLL_DVO_HIGH_SPEED;
4962 /* compute bitmask from p1 value */
4963 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4965 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4967 switch (clock->p2) {
4969 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4972 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4975 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4978 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4982 if (is_sdvo && is_tv)
4983 dpll |= PLL_REF_INPUT_TVCLKINBC;
4985 /* XXX: just matching BIOS for now */
4986 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4988 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4989 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4991 dpll |= PLL_REF_INPUT_DREFCLK;
4996 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4997 struct drm_display_mode *mode,
4998 struct drm_display_mode *adjusted_mode,
5000 struct drm_framebuffer *fb)
5002 struct drm_device *dev = crtc->dev;
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005 int pipe = intel_crtc->pipe;
5006 int plane = intel_crtc->plane;
5007 int num_connectors = 0;
5008 intel_clock_t clock, reduced_clock;
5009 u32 dpll, fp = 0, fp2 = 0;
5010 bool ok, has_reduced_clock = false;
5011 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5012 struct intel_encoder *encoder;
5017 for_each_encoder_on_crtc(dev, crtc, encoder) {
5018 switch (encoder->type) {
5019 case INTEL_OUTPUT_LVDS:
5022 case INTEL_OUTPUT_DISPLAYPORT:
5025 case INTEL_OUTPUT_EDP:
5027 if (!intel_encoder_is_pch_edp(&encoder->base))
5035 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5036 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5038 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5039 &has_reduced_clock, &reduced_clock);
5041 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5045 /* Ensure that the cursor is valid for the new mode before changing... */
5046 intel_crtc_update_cursor(crtc, true);
5048 /* determine panel color depth */
5049 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5050 if (is_lvds && dev_priv->lvds_dither)
5053 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5054 if (has_reduced_clock)
5055 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5058 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5060 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5061 drm_mode_debug_printmodeline(mode);
5063 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5065 struct intel_pch_pll *pll;
5067 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5069 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5074 intel_put_pch_pll(intel_crtc);
5076 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5077 * This is an exception to the general rule that mode_set doesn't turn
5081 temp = I915_READ(PCH_LVDS);
5082 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5083 if (HAS_PCH_CPT(dev)) {
5084 temp &= ~PORT_TRANS_SEL_MASK;
5085 temp |= PORT_TRANS_SEL_CPT(pipe);
5088 temp |= LVDS_PIPEB_SELECT;
5090 temp &= ~LVDS_PIPEB_SELECT;
5093 /* set the corresponsding LVDS_BORDER bit */
5094 temp |= dev_priv->lvds_border_bits;
5095 /* Set the B0-B3 data pairs corresponding to whether we're going to
5096 * set the DPLLs for dual-channel mode or not.
5099 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5101 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5103 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5104 * appropriately here, but we need to look more thoroughly into how
5105 * panels behave in the two modes.
5107 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5108 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5109 temp |= LVDS_HSYNC_POLARITY;
5110 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5111 temp |= LVDS_VSYNC_POLARITY;
5112 I915_WRITE(PCH_LVDS, temp);
5115 if (is_dp && !is_cpu_edp) {
5116 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5118 /* For non-DP output, clear any trans DP clock recovery setting.*/
5119 I915_WRITE(TRANSDATA_M1(pipe), 0);
5120 I915_WRITE(TRANSDATA_N1(pipe), 0);
5121 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5122 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5125 if (intel_crtc->pch_pll) {
5126 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5128 /* Wait for the clocks to stabilize. */
5129 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5132 /* The pixel multiplier can only be updated once the
5133 * DPLL is enabled and the clocks are stable.
5135 * So write it again.
5137 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5140 intel_crtc->lowfreq_avail = false;
5141 if (intel_crtc->pch_pll) {
5142 if (is_lvds && has_reduced_clock && i915_powersave) {
5143 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5144 intel_crtc->lowfreq_avail = true;
5146 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5150 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5152 ironlake_set_m_n(crtc, mode, adjusted_mode);
5155 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5157 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5159 intel_wait_for_vblank(dev, pipe);
5161 /* Set up the display plane register */
5162 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5163 POSTING_READ(DSPCNTR(plane));
5165 ret = intel_pipe_set_base(crtc, x, y, fb);
5167 intel_update_watermarks(dev);
5169 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5174 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5175 struct drm_display_mode *mode,
5176 struct drm_display_mode *adjusted_mode,
5178 struct drm_framebuffer *fb)
5180 struct drm_device *dev = crtc->dev;
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5183 int pipe = intel_crtc->pipe;
5184 int plane = intel_crtc->plane;
5185 int num_connectors = 0;
5186 intel_clock_t clock, reduced_clock;
5187 u32 dpll = 0, fp = 0, fp2 = 0;
5188 bool ok, has_reduced_clock = false;
5189 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5190 struct intel_encoder *encoder;
5195 for_each_encoder_on_crtc(dev, crtc, encoder) {
5196 switch (encoder->type) {
5197 case INTEL_OUTPUT_LVDS:
5200 case INTEL_OUTPUT_DISPLAYPORT:
5203 case INTEL_OUTPUT_EDP:
5205 if (!intel_encoder_is_pch_edp(&encoder->base))
5213 /* We are not sure yet this won't happen. */
5214 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5215 INTEL_PCH_TYPE(dev));
5217 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5218 num_connectors, pipe_name(pipe));
5220 WARN_ON(I915_READ(PIPECONF(pipe)) &
5221 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5223 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5225 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5228 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5229 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5233 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5238 /* Ensure that the cursor is valid for the new mode before changing... */
5239 intel_crtc_update_cursor(crtc, true);
5241 /* determine panel color depth */
5242 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5243 if (is_lvds && dev_priv->lvds_dither)
5246 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5247 drm_mode_debug_printmodeline(mode);
5249 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5250 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5251 if (has_reduced_clock)
5252 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5255 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5258 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5259 * own on pre-Haswell/LPT generation */
5261 struct intel_pch_pll *pll;
5263 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5265 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5270 intel_put_pch_pll(intel_crtc);
5272 /* The LVDS pin pair needs to be on before the DPLLs are
5273 * enabled. This is an exception to the general rule that
5274 * mode_set doesn't turn things on.
5277 temp = I915_READ(PCH_LVDS);
5278 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5279 if (HAS_PCH_CPT(dev)) {
5280 temp &= ~PORT_TRANS_SEL_MASK;
5281 temp |= PORT_TRANS_SEL_CPT(pipe);
5284 temp |= LVDS_PIPEB_SELECT;
5286 temp &= ~LVDS_PIPEB_SELECT;
5289 /* set the corresponsding LVDS_BORDER bit */
5290 temp |= dev_priv->lvds_border_bits;
5291 /* Set the B0-B3 data pairs corresponding to whether
5292 * we're going to set the DPLLs for dual-channel mode or
5296 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5298 temp &= ~(LVDS_B0B3_POWER_UP |
5299 LVDS_CLKB_POWER_UP);
5301 /* It would be nice to set 24 vs 18-bit mode
5302 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5303 * look more thoroughly into how panels behave in the
5306 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5307 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5308 temp |= LVDS_HSYNC_POLARITY;
5309 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5310 temp |= LVDS_VSYNC_POLARITY;
5311 I915_WRITE(PCH_LVDS, temp);
5315 if (is_dp && !is_cpu_edp) {
5316 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5318 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5319 /* For non-DP output, clear any trans DP clock recovery
5321 I915_WRITE(TRANSDATA_M1(pipe), 0);
5322 I915_WRITE(TRANSDATA_N1(pipe), 0);
5323 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5324 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5328 intel_crtc->lowfreq_avail = false;
5329 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5330 if (intel_crtc->pch_pll) {
5331 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5333 /* Wait for the clocks to stabilize. */
5334 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5337 /* The pixel multiplier can only be updated once the
5338 * DPLL is enabled and the clocks are stable.
5340 * So write it again.
5342 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5345 if (intel_crtc->pch_pll) {
5346 if (is_lvds && has_reduced_clock && i915_powersave) {
5347 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5348 intel_crtc->lowfreq_avail = true;
5350 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5355 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5357 ironlake_set_m_n(crtc, mode, adjusted_mode);
5359 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5361 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5363 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5365 /* Set up the display plane register */
5366 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5367 POSTING_READ(DSPCNTR(plane));
5369 ret = intel_pipe_set_base(crtc, x, y, fb);
5371 intel_update_watermarks(dev);
5373 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5378 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5379 struct drm_display_mode *mode,
5380 struct drm_display_mode *adjusted_mode,
5382 struct drm_framebuffer *fb)
5384 struct drm_device *dev = crtc->dev;
5385 struct drm_i915_private *dev_priv = dev->dev_private;
5386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5387 int pipe = intel_crtc->pipe;
5390 drm_vblank_pre_modeset(dev, pipe);
5392 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5394 drm_vblank_post_modeset(dev, pipe);
5399 static bool intel_eld_uptodate(struct drm_connector *connector,
5400 int reg_eldv, uint32_t bits_eldv,
5401 int reg_elda, uint32_t bits_elda,
5404 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5405 uint8_t *eld = connector->eld;
5408 i = I915_READ(reg_eldv);
5417 i = I915_READ(reg_elda);
5419 I915_WRITE(reg_elda, i);
5421 for (i = 0; i < eld[2]; i++)
5422 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5428 static void g4x_write_eld(struct drm_connector *connector,
5429 struct drm_crtc *crtc)
5431 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5432 uint8_t *eld = connector->eld;
5437 i = I915_READ(G4X_AUD_VID_DID);
5439 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5440 eldv = G4X_ELDV_DEVCL_DEVBLC;
5442 eldv = G4X_ELDV_DEVCTG;
5444 if (intel_eld_uptodate(connector,
5445 G4X_AUD_CNTL_ST, eldv,
5446 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5447 G4X_HDMIW_HDMIEDID))
5450 i = I915_READ(G4X_AUD_CNTL_ST);
5451 i &= ~(eldv | G4X_ELD_ADDR);
5452 len = (i >> 9) & 0x1f; /* ELD buffer size */
5453 I915_WRITE(G4X_AUD_CNTL_ST, i);
5458 len = min_t(uint8_t, eld[2], len);
5459 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5460 for (i = 0; i < len; i++)
5461 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5463 i = I915_READ(G4X_AUD_CNTL_ST);
5465 I915_WRITE(G4X_AUD_CNTL_ST, i);
5468 static void haswell_write_eld(struct drm_connector *connector,
5469 struct drm_crtc *crtc)
5471 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5472 uint8_t *eld = connector->eld;
5473 struct drm_device *dev = crtc->dev;
5477 int pipe = to_intel_crtc(crtc)->pipe;
5480 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5481 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5482 int aud_config = HSW_AUD_CFG(pipe);
5483 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5486 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5488 /* Audio output enable */
5489 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5490 tmp = I915_READ(aud_cntrl_st2);
5491 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5492 I915_WRITE(aud_cntrl_st2, tmp);
5494 /* Wait for 1 vertical blank */
5495 intel_wait_for_vblank(dev, pipe);
5497 /* Set ELD valid state */
5498 tmp = I915_READ(aud_cntrl_st2);
5499 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5500 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5501 I915_WRITE(aud_cntrl_st2, tmp);
5502 tmp = I915_READ(aud_cntrl_st2);
5503 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5505 /* Enable HDMI mode */
5506 tmp = I915_READ(aud_config);
5507 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5508 /* clear N_programing_enable and N_value_index */
5509 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5510 I915_WRITE(aud_config, tmp);
5512 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5514 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5516 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5517 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5518 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5519 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5521 I915_WRITE(aud_config, 0);
5523 if (intel_eld_uptodate(connector,
5524 aud_cntrl_st2, eldv,
5525 aud_cntl_st, IBX_ELD_ADDRESS,
5529 i = I915_READ(aud_cntrl_st2);
5531 I915_WRITE(aud_cntrl_st2, i);
5536 i = I915_READ(aud_cntl_st);
5537 i &= ~IBX_ELD_ADDRESS;
5538 I915_WRITE(aud_cntl_st, i);
5539 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5540 DRM_DEBUG_DRIVER("port num:%d\n", i);
5542 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5543 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5544 for (i = 0; i < len; i++)
5545 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5547 i = I915_READ(aud_cntrl_st2);
5549 I915_WRITE(aud_cntrl_st2, i);
5553 static void ironlake_write_eld(struct drm_connector *connector,
5554 struct drm_crtc *crtc)
5556 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5557 uint8_t *eld = connector->eld;
5565 int pipe = to_intel_crtc(crtc)->pipe;
5567 if (HAS_PCH_IBX(connector->dev)) {
5568 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5569 aud_config = IBX_AUD_CFG(pipe);
5570 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5571 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5573 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5574 aud_config = CPT_AUD_CFG(pipe);
5575 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5576 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5579 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5581 i = I915_READ(aud_cntl_st);
5582 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5584 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5585 /* operate blindly on all ports */
5586 eldv = IBX_ELD_VALIDB;
5587 eldv |= IBX_ELD_VALIDB << 4;
5588 eldv |= IBX_ELD_VALIDB << 8;
5590 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5591 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5594 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5595 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5596 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5597 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5599 I915_WRITE(aud_config, 0);
5601 if (intel_eld_uptodate(connector,
5602 aud_cntrl_st2, eldv,
5603 aud_cntl_st, IBX_ELD_ADDRESS,
5607 i = I915_READ(aud_cntrl_st2);
5609 I915_WRITE(aud_cntrl_st2, i);
5614 i = I915_READ(aud_cntl_st);
5615 i &= ~IBX_ELD_ADDRESS;
5616 I915_WRITE(aud_cntl_st, i);
5618 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5619 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5620 for (i = 0; i < len; i++)
5621 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5623 i = I915_READ(aud_cntrl_st2);
5625 I915_WRITE(aud_cntrl_st2, i);
5628 void intel_write_eld(struct drm_encoder *encoder,
5629 struct drm_display_mode *mode)
5631 struct drm_crtc *crtc = encoder->crtc;
5632 struct drm_connector *connector;
5633 struct drm_device *dev = encoder->dev;
5634 struct drm_i915_private *dev_priv = dev->dev_private;
5636 connector = drm_select_eld(encoder, mode);
5640 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5642 drm_get_connector_name(connector),
5643 connector->encoder->base.id,
5644 drm_get_encoder_name(connector->encoder));
5646 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5648 if (dev_priv->display.write_eld)
5649 dev_priv->display.write_eld(connector, crtc);
5652 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5653 void intel_crtc_load_lut(struct drm_crtc *crtc)
5655 struct drm_device *dev = crtc->dev;
5656 struct drm_i915_private *dev_priv = dev->dev_private;
5657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5658 int palreg = PALETTE(intel_crtc->pipe);
5661 /* The clocks have to be on to load the palette. */
5662 if (!crtc->enabled || !intel_crtc->active)
5665 /* use legacy palette for Ironlake */
5666 if (HAS_PCH_SPLIT(dev))
5667 palreg = LGC_PALETTE(intel_crtc->pipe);
5669 for (i = 0; i < 256; i++) {
5670 I915_WRITE(palreg + 4 * i,
5671 (intel_crtc->lut_r[i] << 16) |
5672 (intel_crtc->lut_g[i] << 8) |
5673 intel_crtc->lut_b[i]);
5677 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5679 struct drm_device *dev = crtc->dev;
5680 struct drm_i915_private *dev_priv = dev->dev_private;
5681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5682 bool visible = base != 0;
5685 if (intel_crtc->cursor_visible == visible)
5688 cntl = I915_READ(_CURACNTR);
5690 /* On these chipsets we can only modify the base whilst
5691 * the cursor is disabled.
5693 I915_WRITE(_CURABASE, base);
5695 cntl &= ~(CURSOR_FORMAT_MASK);
5696 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5697 cntl |= CURSOR_ENABLE |
5698 CURSOR_GAMMA_ENABLE |
5701 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5702 I915_WRITE(_CURACNTR, cntl);
5704 intel_crtc->cursor_visible = visible;
5707 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5709 struct drm_device *dev = crtc->dev;
5710 struct drm_i915_private *dev_priv = dev->dev_private;
5711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5712 int pipe = intel_crtc->pipe;
5713 bool visible = base != 0;
5715 if (intel_crtc->cursor_visible != visible) {
5716 uint32_t cntl = I915_READ(CURCNTR(pipe));
5718 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5719 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5720 cntl |= pipe << 28; /* Connect to correct pipe */
5722 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5723 cntl |= CURSOR_MODE_DISABLE;
5725 I915_WRITE(CURCNTR(pipe), cntl);
5727 intel_crtc->cursor_visible = visible;
5729 /* and commit changes on next vblank */
5730 I915_WRITE(CURBASE(pipe), base);
5733 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5735 struct drm_device *dev = crtc->dev;
5736 struct drm_i915_private *dev_priv = dev->dev_private;
5737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5738 int pipe = intel_crtc->pipe;
5739 bool visible = base != 0;
5741 if (intel_crtc->cursor_visible != visible) {
5742 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5744 cntl &= ~CURSOR_MODE;
5745 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5747 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5748 cntl |= CURSOR_MODE_DISABLE;
5750 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5752 intel_crtc->cursor_visible = visible;
5754 /* and commit changes on next vblank */
5755 I915_WRITE(CURBASE_IVB(pipe), base);
5758 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5759 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5762 struct drm_device *dev = crtc->dev;
5763 struct drm_i915_private *dev_priv = dev->dev_private;
5764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5765 int pipe = intel_crtc->pipe;
5766 int x = intel_crtc->cursor_x;
5767 int y = intel_crtc->cursor_y;
5773 if (on && crtc->enabled && crtc->fb) {
5774 base = intel_crtc->cursor_addr;
5775 if (x > (int) crtc->fb->width)
5778 if (y > (int) crtc->fb->height)
5784 if (x + intel_crtc->cursor_width < 0)
5787 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5790 pos |= x << CURSOR_X_SHIFT;
5793 if (y + intel_crtc->cursor_height < 0)
5796 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5799 pos |= y << CURSOR_Y_SHIFT;
5801 visible = base != 0;
5802 if (!visible && !intel_crtc->cursor_visible)
5805 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5806 I915_WRITE(CURPOS_IVB(pipe), pos);
5807 ivb_update_cursor(crtc, base);
5809 I915_WRITE(CURPOS(pipe), pos);
5810 if (IS_845G(dev) || IS_I865G(dev))
5811 i845_update_cursor(crtc, base);
5813 i9xx_update_cursor(crtc, base);
5817 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5818 struct drm_file *file,
5820 uint32_t width, uint32_t height)
5822 struct drm_device *dev = crtc->dev;
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5825 struct drm_i915_gem_object *obj;
5829 /* if we want to turn off the cursor ignore width and height */
5831 DRM_DEBUG_KMS("cursor off\n");
5834 mutex_lock(&dev->struct_mutex);
5838 /* Currently we only support 64x64 cursors */
5839 if (width != 64 || height != 64) {
5840 DRM_ERROR("we currently only support 64x64 cursors\n");
5844 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5845 if (&obj->base == NULL)
5848 if (obj->base.size < width * height * 4) {
5849 DRM_ERROR("buffer is to small\n");
5854 /* we only need to pin inside GTT if cursor is non-phy */
5855 mutex_lock(&dev->struct_mutex);
5856 if (!dev_priv->info->cursor_needs_physical) {
5857 if (obj->tiling_mode) {
5858 DRM_ERROR("cursor cannot be tiled\n");
5863 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5865 DRM_ERROR("failed to move cursor bo into the GTT\n");
5869 ret = i915_gem_object_put_fence(obj);
5871 DRM_ERROR("failed to release fence for cursor");
5875 addr = obj->gtt_offset;
5877 int align = IS_I830(dev) ? 16 * 1024 : 256;
5878 ret = i915_gem_attach_phys_object(dev, obj,
5879 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5882 DRM_ERROR("failed to attach phys object\n");
5885 addr = obj->phys_obj->handle->busaddr;
5889 I915_WRITE(CURSIZE, (height << 12) | width);
5892 if (intel_crtc->cursor_bo) {
5893 if (dev_priv->info->cursor_needs_physical) {
5894 if (intel_crtc->cursor_bo != obj)
5895 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5897 i915_gem_object_unpin(intel_crtc->cursor_bo);
5898 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5901 mutex_unlock(&dev->struct_mutex);
5903 intel_crtc->cursor_addr = addr;
5904 intel_crtc->cursor_bo = obj;
5905 intel_crtc->cursor_width = width;
5906 intel_crtc->cursor_height = height;
5908 intel_crtc_update_cursor(crtc, true);
5912 i915_gem_object_unpin(obj);
5914 mutex_unlock(&dev->struct_mutex);
5916 drm_gem_object_unreference_unlocked(&obj->base);
5920 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5924 intel_crtc->cursor_x = x;
5925 intel_crtc->cursor_y = y;
5927 intel_crtc_update_cursor(crtc, true);
5932 /** Sets the color ramps on behalf of RandR */
5933 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5934 u16 blue, int regno)
5936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5938 intel_crtc->lut_r[regno] = red >> 8;
5939 intel_crtc->lut_g[regno] = green >> 8;
5940 intel_crtc->lut_b[regno] = blue >> 8;
5943 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5944 u16 *blue, int regno)
5946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5948 *red = intel_crtc->lut_r[regno] << 8;
5949 *green = intel_crtc->lut_g[regno] << 8;
5950 *blue = intel_crtc->lut_b[regno] << 8;
5953 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5954 u16 *blue, uint32_t start, uint32_t size)
5956 int end = (start + size > 256) ? 256 : start + size, i;
5957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5959 for (i = start; i < end; i++) {
5960 intel_crtc->lut_r[i] = red[i] >> 8;
5961 intel_crtc->lut_g[i] = green[i] >> 8;
5962 intel_crtc->lut_b[i] = blue[i] >> 8;
5965 intel_crtc_load_lut(crtc);
5969 * Get a pipe with a simple mode set on it for doing load-based monitor
5972 * It will be up to the load-detect code to adjust the pipe as appropriate for
5973 * its requirements. The pipe will be connected to no other encoders.
5975 * Currently this code will only succeed if there is a pipe with no encoders
5976 * configured for it. In the future, it could choose to temporarily disable
5977 * some outputs to free up a pipe for its use.
5979 * \return crtc, or NULL if no pipes are available.
5982 /* VESA 640x480x72Hz mode to set on the pipe */
5983 static struct drm_display_mode load_detect_mode = {
5984 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5985 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5988 static struct drm_framebuffer *
5989 intel_framebuffer_create(struct drm_device *dev,
5990 struct drm_mode_fb_cmd2 *mode_cmd,
5991 struct drm_i915_gem_object *obj)
5993 struct intel_framebuffer *intel_fb;
5996 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5998 drm_gem_object_unreference_unlocked(&obj->base);
5999 return ERR_PTR(-ENOMEM);
6002 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6004 drm_gem_object_unreference_unlocked(&obj->base);
6006 return ERR_PTR(ret);
6009 return &intel_fb->base;
6013 intel_framebuffer_pitch_for_width(int width, int bpp)
6015 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6016 return ALIGN(pitch, 64);
6020 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6022 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6023 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6026 static struct drm_framebuffer *
6027 intel_framebuffer_create_for_mode(struct drm_device *dev,
6028 struct drm_display_mode *mode,
6031 struct drm_i915_gem_object *obj;
6032 struct drm_mode_fb_cmd2 mode_cmd;
6034 obj = i915_gem_alloc_object(dev,
6035 intel_framebuffer_size_for_mode(mode, bpp));
6037 return ERR_PTR(-ENOMEM);
6039 mode_cmd.width = mode->hdisplay;
6040 mode_cmd.height = mode->vdisplay;
6041 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6043 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6045 return intel_framebuffer_create(dev, &mode_cmd, obj);
6048 static struct drm_framebuffer *
6049 mode_fits_in_fbdev(struct drm_device *dev,
6050 struct drm_display_mode *mode)
6052 struct drm_i915_private *dev_priv = dev->dev_private;
6053 struct drm_i915_gem_object *obj;
6054 struct drm_framebuffer *fb;
6056 if (dev_priv->fbdev == NULL)
6059 obj = dev_priv->fbdev->ifb.obj;
6063 fb = &dev_priv->fbdev->ifb.base;
6064 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6065 fb->bits_per_pixel))
6068 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6074 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6075 struct drm_display_mode *mode,
6076 struct intel_load_detect_pipe *old)
6078 struct intel_crtc *intel_crtc;
6079 struct intel_encoder *intel_encoder =
6080 intel_attached_encoder(connector);
6081 struct drm_crtc *possible_crtc;
6082 struct drm_encoder *encoder = &intel_encoder->base;
6083 struct drm_crtc *crtc = NULL;
6084 struct drm_device *dev = encoder->dev;
6085 struct drm_framebuffer *fb;
6088 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6089 connector->base.id, drm_get_connector_name(connector),
6090 encoder->base.id, drm_get_encoder_name(encoder));
6093 * Algorithm gets a little messy:
6095 * - if the connector already has an assigned crtc, use it (but make
6096 * sure it's on first)
6098 * - try to find the first unused crtc that can drive this connector,
6099 * and use that if we find one
6102 /* See if we already have a CRTC for this connector */
6103 if (encoder->crtc) {
6104 crtc = encoder->crtc;
6106 old->dpms_mode = connector->dpms;
6107 old->load_detect_temp = false;
6109 /* Make sure the crtc and connector are running */
6110 if (connector->dpms != DRM_MODE_DPMS_ON)
6111 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6116 /* Find an unused one (if possible) */
6117 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6119 if (!(encoder->possible_crtcs & (1 << i)))
6121 if (!possible_crtc->enabled) {
6122 crtc = possible_crtc;
6128 * If we didn't find an unused CRTC, don't use any.
6131 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6135 intel_encoder->new_crtc = to_intel_crtc(crtc);
6136 to_intel_connector(connector)->new_encoder = intel_encoder;
6138 intel_crtc = to_intel_crtc(crtc);
6139 old->dpms_mode = connector->dpms;
6140 old->load_detect_temp = true;
6141 old->release_fb = NULL;
6144 mode = &load_detect_mode;
6146 /* We need a framebuffer large enough to accommodate all accesses
6147 * that the plane may generate whilst we perform load detection.
6148 * We can not rely on the fbcon either being present (we get called
6149 * during its initialisation to detect all boot displays, or it may
6150 * not even exist) or that it is large enough to satisfy the
6153 fb = mode_fits_in_fbdev(dev, mode);
6155 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6156 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6157 old->release_fb = fb;
6159 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6161 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6165 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6166 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6167 if (old->release_fb)
6168 old->release_fb->funcs->destroy(old->release_fb);
6172 /* let the connector get through one full cycle before testing */
6173 intel_wait_for_vblank(dev, intel_crtc->pipe);
6177 connector->encoder = NULL;
6178 encoder->crtc = NULL;
6182 void intel_release_load_detect_pipe(struct drm_connector *connector,
6183 struct intel_load_detect_pipe *old)
6185 struct intel_encoder *intel_encoder =
6186 intel_attached_encoder(connector);
6187 struct drm_encoder *encoder = &intel_encoder->base;
6189 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6190 connector->base.id, drm_get_connector_name(connector),
6191 encoder->base.id, drm_get_encoder_name(encoder));
6193 if (old->load_detect_temp) {
6194 struct drm_crtc *crtc = encoder->crtc;
6196 to_intel_connector(connector)->new_encoder = NULL;
6197 intel_encoder->new_crtc = NULL;
6198 intel_set_mode(crtc, NULL, 0, 0, NULL);
6200 if (old->release_fb)
6201 old->release_fb->funcs->destroy(old->release_fb);
6206 /* Switch crtc and encoder back off if necessary */
6207 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6208 connector->funcs->dpms(connector, old->dpms_mode);
6211 /* Returns the clock of the currently programmed mode of the given pipe. */
6212 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6214 struct drm_i915_private *dev_priv = dev->dev_private;
6215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6216 int pipe = intel_crtc->pipe;
6217 u32 dpll = I915_READ(DPLL(pipe));
6219 intel_clock_t clock;
6221 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6222 fp = I915_READ(FP0(pipe));
6224 fp = I915_READ(FP1(pipe));
6226 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6227 if (IS_PINEVIEW(dev)) {
6228 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6229 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6231 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6232 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6235 if (!IS_GEN2(dev)) {
6236 if (IS_PINEVIEW(dev))
6237 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6238 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6240 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6241 DPLL_FPA01_P1_POST_DIV_SHIFT);
6243 switch (dpll & DPLL_MODE_MASK) {
6244 case DPLLB_MODE_DAC_SERIAL:
6245 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6248 case DPLLB_MODE_LVDS:
6249 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6253 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6254 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6258 /* XXX: Handle the 100Mhz refclk */
6259 intel_clock(dev, 96000, &clock);
6261 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6264 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6265 DPLL_FPA01_P1_POST_DIV_SHIFT);
6268 if ((dpll & PLL_REF_INPUT_MASK) ==
6269 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6270 /* XXX: might not be 66MHz */
6271 intel_clock(dev, 66000, &clock);
6273 intel_clock(dev, 48000, &clock);
6275 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6278 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6279 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6281 if (dpll & PLL_P2_DIVIDE_BY_4)
6286 intel_clock(dev, 48000, &clock);
6290 /* XXX: It would be nice to validate the clocks, but we can't reuse
6291 * i830PllIsValid() because it relies on the xf86_config connector
6292 * configuration being accurate, which it isn't necessarily.
6298 /** Returns the currently programmed mode of the given pipe. */
6299 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6300 struct drm_crtc *crtc)
6302 struct drm_i915_private *dev_priv = dev->dev_private;
6303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6304 int pipe = intel_crtc->pipe;
6305 struct drm_display_mode *mode;
6306 int htot = I915_READ(HTOTAL(pipe));
6307 int hsync = I915_READ(HSYNC(pipe));
6308 int vtot = I915_READ(VTOTAL(pipe));
6309 int vsync = I915_READ(VSYNC(pipe));
6311 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6315 mode->clock = intel_crtc_clock_get(dev, crtc);
6316 mode->hdisplay = (htot & 0xffff) + 1;
6317 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6318 mode->hsync_start = (hsync & 0xffff) + 1;
6319 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6320 mode->vdisplay = (vtot & 0xffff) + 1;
6321 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6322 mode->vsync_start = (vsync & 0xffff) + 1;
6323 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6325 drm_mode_set_name(mode);
6330 static void intel_increase_pllclock(struct drm_crtc *crtc)
6332 struct drm_device *dev = crtc->dev;
6333 drm_i915_private_t *dev_priv = dev->dev_private;
6334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6335 int pipe = intel_crtc->pipe;
6336 int dpll_reg = DPLL(pipe);
6339 if (HAS_PCH_SPLIT(dev))
6342 if (!dev_priv->lvds_downclock_avail)
6345 dpll = I915_READ(dpll_reg);
6346 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6347 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6349 assert_panel_unlocked(dev_priv, pipe);
6351 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6352 I915_WRITE(dpll_reg, dpll);
6353 intel_wait_for_vblank(dev, pipe);
6355 dpll = I915_READ(dpll_reg);
6356 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6357 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6361 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6363 struct drm_device *dev = crtc->dev;
6364 drm_i915_private_t *dev_priv = dev->dev_private;
6365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6367 if (HAS_PCH_SPLIT(dev))
6370 if (!dev_priv->lvds_downclock_avail)
6374 * Since this is called by a timer, we should never get here in
6377 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6378 int pipe = intel_crtc->pipe;
6379 int dpll_reg = DPLL(pipe);
6382 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6384 assert_panel_unlocked(dev_priv, pipe);
6386 dpll = I915_READ(dpll_reg);
6387 dpll |= DISPLAY_RATE_SELECT_FPA1;
6388 I915_WRITE(dpll_reg, dpll);
6389 intel_wait_for_vblank(dev, pipe);
6390 dpll = I915_READ(dpll_reg);
6391 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6392 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6397 void intel_mark_busy(struct drm_device *dev)
6399 i915_update_gfx_val(dev->dev_private);
6402 void intel_mark_idle(struct drm_device *dev)
6406 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6408 struct drm_device *dev = obj->base.dev;
6409 struct drm_crtc *crtc;
6411 if (!i915_powersave)
6414 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6418 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6419 intel_increase_pllclock(crtc);
6423 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6425 struct drm_device *dev = obj->base.dev;
6426 struct drm_crtc *crtc;
6428 if (!i915_powersave)
6431 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6435 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6436 intel_decrease_pllclock(crtc);
6440 static void intel_crtc_destroy(struct drm_crtc *crtc)
6442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6443 struct drm_device *dev = crtc->dev;
6444 struct intel_unpin_work *work;
6445 unsigned long flags;
6447 spin_lock_irqsave(&dev->event_lock, flags);
6448 work = intel_crtc->unpin_work;
6449 intel_crtc->unpin_work = NULL;
6450 spin_unlock_irqrestore(&dev->event_lock, flags);
6453 cancel_work_sync(&work->work);
6457 drm_crtc_cleanup(crtc);
6462 static void intel_unpin_work_fn(struct work_struct *__work)
6464 struct intel_unpin_work *work =
6465 container_of(__work, struct intel_unpin_work, work);
6467 mutex_lock(&work->dev->struct_mutex);
6468 intel_unpin_fb_obj(work->old_fb_obj);
6469 drm_gem_object_unreference(&work->pending_flip_obj->base);
6470 drm_gem_object_unreference(&work->old_fb_obj->base);
6472 intel_update_fbc(work->dev);
6473 mutex_unlock(&work->dev->struct_mutex);
6477 static void do_intel_finish_page_flip(struct drm_device *dev,
6478 struct drm_crtc *crtc)
6480 drm_i915_private_t *dev_priv = dev->dev_private;
6481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6482 struct intel_unpin_work *work;
6483 struct drm_i915_gem_object *obj;
6484 struct drm_pending_vblank_event *e;
6485 struct timeval tnow, tvbl;
6486 unsigned long flags;
6488 /* Ignore early vblank irqs */
6489 if (intel_crtc == NULL)
6492 do_gettimeofday(&tnow);
6494 spin_lock_irqsave(&dev->event_lock, flags);
6495 work = intel_crtc->unpin_work;
6496 if (work == NULL || !work->pending) {
6497 spin_unlock_irqrestore(&dev->event_lock, flags);
6501 intel_crtc->unpin_work = NULL;
6505 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6507 /* Called before vblank count and timestamps have
6508 * been updated for the vblank interval of flip
6509 * completion? Need to increment vblank count and
6510 * add one videorefresh duration to returned timestamp
6511 * to account for this. We assume this happened if we
6512 * get called over 0.9 frame durations after the last
6513 * timestamped vblank.
6515 * This calculation can not be used with vrefresh rates
6516 * below 5Hz (10Hz to be on the safe side) without
6517 * promoting to 64 integers.
6519 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6520 9 * crtc->framedur_ns) {
6521 e->event.sequence++;
6522 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6526 e->event.tv_sec = tvbl.tv_sec;
6527 e->event.tv_usec = tvbl.tv_usec;
6529 list_add_tail(&e->base.link,
6530 &e->base.file_priv->event_list);
6531 wake_up_interruptible(&e->base.file_priv->event_wait);
6534 drm_vblank_put(dev, intel_crtc->pipe);
6536 spin_unlock_irqrestore(&dev->event_lock, flags);
6538 obj = work->old_fb_obj;
6540 atomic_clear_mask(1 << intel_crtc->plane,
6541 &obj->pending_flip.counter);
6542 if (atomic_read(&obj->pending_flip) == 0)
6543 wake_up(&dev_priv->pending_flip_queue);
6545 schedule_work(&work->work);
6547 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6550 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6552 drm_i915_private_t *dev_priv = dev->dev_private;
6553 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6555 do_intel_finish_page_flip(dev, crtc);
6558 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6560 drm_i915_private_t *dev_priv = dev->dev_private;
6561 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6563 do_intel_finish_page_flip(dev, crtc);
6566 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6568 drm_i915_private_t *dev_priv = dev->dev_private;
6569 struct intel_crtc *intel_crtc =
6570 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6571 unsigned long flags;
6573 spin_lock_irqsave(&dev->event_lock, flags);
6574 if (intel_crtc->unpin_work) {
6575 if ((++intel_crtc->unpin_work->pending) > 1)
6576 DRM_ERROR("Prepared flip multiple times\n");
6578 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6580 spin_unlock_irqrestore(&dev->event_lock, flags);
6583 static int intel_gen2_queue_flip(struct drm_device *dev,
6584 struct drm_crtc *crtc,
6585 struct drm_framebuffer *fb,
6586 struct drm_i915_gem_object *obj)
6588 struct drm_i915_private *dev_priv = dev->dev_private;
6589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6591 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6594 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6598 ret = intel_ring_begin(ring, 6);
6602 /* Can't queue multiple flips, so wait for the previous
6603 * one to finish before executing the next.
6605 if (intel_crtc->plane)
6606 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6608 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6609 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6610 intel_ring_emit(ring, MI_NOOP);
6611 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6612 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6613 intel_ring_emit(ring, fb->pitches[0]);
6614 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6615 intel_ring_emit(ring, 0); /* aux display base address, unused */
6616 intel_ring_advance(ring);
6620 intel_unpin_fb_obj(obj);
6625 static int intel_gen3_queue_flip(struct drm_device *dev,
6626 struct drm_crtc *crtc,
6627 struct drm_framebuffer *fb,
6628 struct drm_i915_gem_object *obj)
6630 struct drm_i915_private *dev_priv = dev->dev_private;
6631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6633 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6636 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6640 ret = intel_ring_begin(ring, 6);
6644 if (intel_crtc->plane)
6645 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6647 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6648 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6649 intel_ring_emit(ring, MI_NOOP);
6650 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6651 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6652 intel_ring_emit(ring, fb->pitches[0]);
6653 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6654 intel_ring_emit(ring, MI_NOOP);
6656 intel_ring_advance(ring);
6660 intel_unpin_fb_obj(obj);
6665 static int intel_gen4_queue_flip(struct drm_device *dev,
6666 struct drm_crtc *crtc,
6667 struct drm_framebuffer *fb,
6668 struct drm_i915_gem_object *obj)
6670 struct drm_i915_private *dev_priv = dev->dev_private;
6671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6672 uint32_t pf, pipesrc;
6673 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6676 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6680 ret = intel_ring_begin(ring, 4);
6684 /* i965+ uses the linear or tiled offsets from the
6685 * Display Registers (which do not change across a page-flip)
6686 * so we need only reprogram the base address.
6688 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6689 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6690 intel_ring_emit(ring, fb->pitches[0]);
6691 intel_ring_emit(ring,
6692 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6695 /* XXX Enabling the panel-fitter across page-flip is so far
6696 * untested on non-native modes, so ignore it for now.
6697 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6700 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6701 intel_ring_emit(ring, pf | pipesrc);
6702 intel_ring_advance(ring);
6706 intel_unpin_fb_obj(obj);
6711 static int intel_gen6_queue_flip(struct drm_device *dev,
6712 struct drm_crtc *crtc,
6713 struct drm_framebuffer *fb,
6714 struct drm_i915_gem_object *obj)
6716 struct drm_i915_private *dev_priv = dev->dev_private;
6717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6718 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6719 uint32_t pf, pipesrc;
6722 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6726 ret = intel_ring_begin(ring, 4);
6730 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6731 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6732 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6733 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6735 /* Contrary to the suggestions in the documentation,
6736 * "Enable Panel Fitter" does not seem to be required when page
6737 * flipping with a non-native mode, and worse causes a normal
6739 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6742 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6743 intel_ring_emit(ring, pf | pipesrc);
6744 intel_ring_advance(ring);
6748 intel_unpin_fb_obj(obj);
6754 * On gen7 we currently use the blit ring because (in early silicon at least)
6755 * the render ring doesn't give us interrpts for page flip completion, which
6756 * means clients will hang after the first flip is queued. Fortunately the
6757 * blit ring generates interrupts properly, so use it instead.
6759 static int intel_gen7_queue_flip(struct drm_device *dev,
6760 struct drm_crtc *crtc,
6761 struct drm_framebuffer *fb,
6762 struct drm_i915_gem_object *obj)
6764 struct drm_i915_private *dev_priv = dev->dev_private;
6765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6766 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6767 uint32_t plane_bit = 0;
6770 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6774 switch(intel_crtc->plane) {
6776 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6779 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6782 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6785 WARN_ONCE(1, "unknown plane in flip command\n");
6790 ret = intel_ring_begin(ring, 4);
6794 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6795 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6796 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6797 intel_ring_emit(ring, (MI_NOOP));
6798 intel_ring_advance(ring);
6802 intel_unpin_fb_obj(obj);
6807 static int intel_default_queue_flip(struct drm_device *dev,
6808 struct drm_crtc *crtc,
6809 struct drm_framebuffer *fb,
6810 struct drm_i915_gem_object *obj)
6815 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6816 struct drm_framebuffer *fb,
6817 struct drm_pending_vblank_event *event)
6819 struct drm_device *dev = crtc->dev;
6820 struct drm_i915_private *dev_priv = dev->dev_private;
6821 struct intel_framebuffer *intel_fb;
6822 struct drm_i915_gem_object *obj;
6823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6824 struct intel_unpin_work *work;
6825 unsigned long flags;
6828 /* Can't change pixel format via MI display flips. */
6829 if (fb->pixel_format != crtc->fb->pixel_format)
6833 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6834 * Note that pitch changes could also affect these register.
6836 if (INTEL_INFO(dev)->gen > 3 &&
6837 (fb->offsets[0] != crtc->fb->offsets[0] ||
6838 fb->pitches[0] != crtc->fb->pitches[0]))
6841 work = kzalloc(sizeof *work, GFP_KERNEL);
6845 work->event = event;
6846 work->dev = crtc->dev;
6847 intel_fb = to_intel_framebuffer(crtc->fb);
6848 work->old_fb_obj = intel_fb->obj;
6849 INIT_WORK(&work->work, intel_unpin_work_fn);
6851 ret = drm_vblank_get(dev, intel_crtc->pipe);
6855 /* We borrow the event spin lock for protecting unpin_work */
6856 spin_lock_irqsave(&dev->event_lock, flags);
6857 if (intel_crtc->unpin_work) {
6858 spin_unlock_irqrestore(&dev->event_lock, flags);
6860 drm_vblank_put(dev, intel_crtc->pipe);
6862 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6865 intel_crtc->unpin_work = work;
6866 spin_unlock_irqrestore(&dev->event_lock, flags);
6868 intel_fb = to_intel_framebuffer(fb);
6869 obj = intel_fb->obj;
6871 ret = i915_mutex_lock_interruptible(dev);
6875 /* Reference the objects for the scheduled work. */
6876 drm_gem_object_reference(&work->old_fb_obj->base);
6877 drm_gem_object_reference(&obj->base);
6881 work->pending_flip_obj = obj;
6883 work->enable_stall_check = true;
6885 /* Block clients from rendering to the new back buffer until
6886 * the flip occurs and the object is no longer visible.
6888 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6890 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6892 goto cleanup_pending;
6894 intel_disable_fbc(dev);
6895 intel_mark_fb_busy(obj);
6896 mutex_unlock(&dev->struct_mutex);
6898 trace_i915_flip_request(intel_crtc->plane, obj);
6903 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6904 drm_gem_object_unreference(&work->old_fb_obj->base);
6905 drm_gem_object_unreference(&obj->base);
6906 mutex_unlock(&dev->struct_mutex);
6909 spin_lock_irqsave(&dev->event_lock, flags);
6910 intel_crtc->unpin_work = NULL;
6911 spin_unlock_irqrestore(&dev->event_lock, flags);
6913 drm_vblank_put(dev, intel_crtc->pipe);
6920 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6921 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6922 .load_lut = intel_crtc_load_lut,
6923 .disable = intel_crtc_noop,
6926 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6928 struct intel_encoder *other_encoder;
6929 struct drm_crtc *crtc = &encoder->new_crtc->base;
6934 list_for_each_entry(other_encoder,
6935 &crtc->dev->mode_config.encoder_list,
6938 if (&other_encoder->new_crtc->base != crtc ||
6939 encoder == other_encoder)
6948 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6949 struct drm_crtc *crtc)
6951 struct drm_device *dev;
6952 struct drm_crtc *tmp;
6955 WARN(!crtc, "checking null crtc?\n");
6959 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6965 if (encoder->possible_crtcs & crtc_mask)
6971 * intel_modeset_update_staged_output_state
6973 * Updates the staged output configuration state, e.g. after we've read out the
6976 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6978 struct intel_encoder *encoder;
6979 struct intel_connector *connector;
6981 list_for_each_entry(connector, &dev->mode_config.connector_list,
6983 connector->new_encoder =
6984 to_intel_encoder(connector->base.encoder);
6987 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6990 to_intel_crtc(encoder->base.crtc);
6995 * intel_modeset_commit_output_state
6997 * This function copies the stage display pipe configuration to the real one.
6999 static void intel_modeset_commit_output_state(struct drm_device *dev)
7001 struct intel_encoder *encoder;
7002 struct intel_connector *connector;
7004 list_for_each_entry(connector, &dev->mode_config.connector_list,
7006 connector->base.encoder = &connector->new_encoder->base;
7009 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7011 encoder->base.crtc = &encoder->new_crtc->base;
7015 static struct drm_display_mode *
7016 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7017 struct drm_display_mode *mode)
7019 struct drm_device *dev = crtc->dev;
7020 struct drm_display_mode *adjusted_mode;
7021 struct drm_encoder_helper_funcs *encoder_funcs;
7022 struct intel_encoder *encoder;
7024 adjusted_mode = drm_mode_duplicate(dev, mode);
7026 return ERR_PTR(-ENOMEM);
7028 /* Pass our mode to the connectors and the CRTC to give them a chance to
7029 * adjust it according to limitations or connector properties, and also
7030 * a chance to reject the mode entirely.
7032 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7035 if (&encoder->new_crtc->base != crtc)
7037 encoder_funcs = encoder->base.helper_private;
7038 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7040 DRM_DEBUG_KMS("Encoder fixup failed\n");
7045 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7046 DRM_DEBUG_KMS("CRTC fixup failed\n");
7049 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7051 return adjusted_mode;
7053 drm_mode_destroy(dev, adjusted_mode);
7054 return ERR_PTR(-EINVAL);
7057 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7058 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7060 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7061 unsigned *prepare_pipes, unsigned *disable_pipes)
7063 struct intel_crtc *intel_crtc;
7064 struct drm_device *dev = crtc->dev;
7065 struct intel_encoder *encoder;
7066 struct intel_connector *connector;
7067 struct drm_crtc *tmp_crtc;
7069 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7071 /* Check which crtcs have changed outputs connected to them, these need
7072 * to be part of the prepare_pipes mask. We don't (yet) support global
7073 * modeset across multiple crtcs, so modeset_pipes will only have one
7074 * bit set at most. */
7075 list_for_each_entry(connector, &dev->mode_config.connector_list,
7077 if (connector->base.encoder == &connector->new_encoder->base)
7080 if (connector->base.encoder) {
7081 tmp_crtc = connector->base.encoder->crtc;
7083 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7086 if (connector->new_encoder)
7088 1 << connector->new_encoder->new_crtc->pipe;
7091 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7093 if (encoder->base.crtc == &encoder->new_crtc->base)
7096 if (encoder->base.crtc) {
7097 tmp_crtc = encoder->base.crtc;
7099 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7102 if (encoder->new_crtc)
7103 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7106 /* Check for any pipes that will be fully disabled ... */
7107 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7111 /* Don't try to disable disabled crtcs. */
7112 if (!intel_crtc->base.enabled)
7115 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7117 if (encoder->new_crtc == intel_crtc)
7122 *disable_pipes |= 1 << intel_crtc->pipe;
7126 /* set_mode is also used to update properties on life display pipes. */
7127 intel_crtc = to_intel_crtc(crtc);
7129 *prepare_pipes |= 1 << intel_crtc->pipe;
7131 /* We only support modeset on one single crtc, hence we need to do that
7132 * only for the passed in crtc iff we change anything else than just
7135 * This is actually not true, to be fully compatible with the old crtc
7136 * helper we automatically disable _any_ output (i.e. doesn't need to be
7137 * connected to the crtc we're modesetting on) if it's disconnected.
7138 * Which is a rather nutty api (since changed the output configuration
7139 * without userspace's explicit request can lead to confusion), but
7140 * alas. Hence we currently need to modeset on all pipes we prepare. */
7142 *modeset_pipes = *prepare_pipes;
7144 /* ... and mask these out. */
7145 *modeset_pipes &= ~(*disable_pipes);
7146 *prepare_pipes &= ~(*disable_pipes);
7149 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7151 struct drm_encoder *encoder;
7152 struct drm_device *dev = crtc->dev;
7154 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7155 if (encoder->crtc == crtc)
7162 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7164 struct intel_encoder *intel_encoder;
7165 struct intel_crtc *intel_crtc;
7166 struct drm_connector *connector;
7168 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7170 if (!intel_encoder->base.crtc)
7173 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7175 if (prepare_pipes & (1 << intel_crtc->pipe))
7176 intel_encoder->connectors_active = false;
7179 intel_modeset_commit_output_state(dev);
7181 /* Update computed state. */
7182 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7184 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7187 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7188 if (!connector->encoder || !connector->encoder->crtc)
7191 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7193 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7194 struct drm_property *dpms_property =
7195 dev->mode_config.dpms_property;
7197 connector->dpms = DRM_MODE_DPMS_ON;
7198 drm_connector_property_set_value(connector,
7202 intel_encoder = to_intel_encoder(connector->encoder);
7203 intel_encoder->connectors_active = true;
7209 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7210 list_for_each_entry((intel_crtc), \
7211 &(dev)->mode_config.crtc_list, \
7213 if (mask & (1 <<(intel_crtc)->pipe)) \
7216 intel_modeset_check_state(struct drm_device *dev)
7218 struct intel_crtc *crtc;
7219 struct intel_encoder *encoder;
7220 struct intel_connector *connector;
7222 list_for_each_entry(connector, &dev->mode_config.connector_list,
7224 /* This also checks the encoder/connector hw state with the
7225 * ->get_hw_state callbacks. */
7226 intel_connector_check_state(connector);
7228 WARN(&connector->new_encoder->base != connector->base.encoder,
7229 "connector's staged encoder doesn't match current encoder\n");
7232 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7234 bool enabled = false;
7235 bool active = false;
7236 enum pipe pipe, tracked_pipe;
7238 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7239 encoder->base.base.id,
7240 drm_get_encoder_name(&encoder->base));
7242 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7243 "encoder's stage crtc doesn't match current crtc\n");
7244 WARN(encoder->connectors_active && !encoder->base.crtc,
7245 "encoder's active_connectors set, but no crtc\n");
7247 list_for_each_entry(connector, &dev->mode_config.connector_list,
7249 if (connector->base.encoder != &encoder->base)
7252 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7255 WARN(!!encoder->base.crtc != enabled,
7256 "encoder's enabled state mismatch "
7257 "(expected %i, found %i)\n",
7258 !!encoder->base.crtc, enabled);
7259 WARN(active && !encoder->base.crtc,
7260 "active encoder with no crtc\n");
7262 WARN(encoder->connectors_active != active,
7263 "encoder's computed active state doesn't match tracked active state "
7264 "(expected %i, found %i)\n", active, encoder->connectors_active);
7266 active = encoder->get_hw_state(encoder, &pipe);
7267 WARN(active != encoder->connectors_active,
7268 "encoder's hw state doesn't match sw tracking "
7269 "(expected %i, found %i)\n",
7270 encoder->connectors_active, active);
7272 if (!encoder->base.crtc)
7275 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7276 WARN(active && pipe != tracked_pipe,
7277 "active encoder's pipe doesn't match"
7278 "(expected %i, found %i)\n",
7279 tracked_pipe, pipe);
7283 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7285 bool enabled = false;
7286 bool active = false;
7288 DRM_DEBUG_KMS("[CRTC:%d]\n",
7289 crtc->base.base.id);
7291 WARN(crtc->active && !crtc->base.enabled,
7292 "active crtc, but not enabled in sw tracking\n");
7294 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7296 if (encoder->base.crtc != &crtc->base)
7299 if (encoder->connectors_active)
7302 WARN(active != crtc->active,
7303 "crtc's computed active state doesn't match tracked active state "
7304 "(expected %i, found %i)\n", active, crtc->active);
7305 WARN(enabled != crtc->base.enabled,
7306 "crtc's computed enabled state doesn't match tracked enabled state "
7307 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7309 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7313 bool intel_set_mode(struct drm_crtc *crtc,
7314 struct drm_display_mode *mode,
7315 int x, int y, struct drm_framebuffer *fb)
7317 struct drm_device *dev = crtc->dev;
7318 drm_i915_private_t *dev_priv = dev->dev_private;
7319 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7320 struct drm_encoder_helper_funcs *encoder_funcs;
7321 struct drm_encoder *encoder;
7322 struct intel_crtc *intel_crtc;
7323 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7326 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7327 &prepare_pipes, &disable_pipes);
7329 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7330 modeset_pipes, prepare_pipes, disable_pipes);
7332 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7333 intel_crtc_disable(&intel_crtc->base);
7335 saved_hwmode = crtc->hwmode;
7336 saved_mode = crtc->mode;
7338 /* Hack: Because we don't (yet) support global modeset on multiple
7339 * crtcs, we don't keep track of the new mode for more than one crtc.
7340 * Hence simply check whether any bit is set in modeset_pipes in all the
7341 * pieces of code that are not yet converted to deal with mutliple crtcs
7342 * changing their mode at the same time. */
7343 adjusted_mode = NULL;
7344 if (modeset_pipes) {
7345 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7346 if (IS_ERR(adjusted_mode)) {
7351 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7352 if (intel_crtc->base.enabled)
7353 dev_priv->display.crtc_disable(&intel_crtc->base);
7356 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7357 * to set it here already despite that we pass it down the callchain.
7362 /* Only after disabling all output pipelines that will be changed can we
7363 * update the the output configuration. */
7364 intel_modeset_update_state(dev, prepare_pipes);
7366 /* Set up the DPLL and any encoders state that needs to adjust or depend
7369 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7370 ret = !intel_crtc_mode_set(&intel_crtc->base,
7371 mode, adjusted_mode,
7376 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7378 if (encoder->crtc != &intel_crtc->base)
7381 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7382 encoder->base.id, drm_get_encoder_name(encoder),
7383 mode->base.id, mode->name);
7384 encoder_funcs = encoder->helper_private;
7385 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7389 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7390 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7391 dev_priv->display.crtc_enable(&intel_crtc->base);
7393 if (modeset_pipes) {
7394 /* Store real post-adjustment hardware mode. */
7395 crtc->hwmode = *adjusted_mode;
7397 /* Calculate and store various constants which
7398 * are later needed by vblank and swap-completion
7399 * timestamping. They are derived from true hwmode.
7401 drm_calc_timestamping_constants(crtc);
7404 /* FIXME: add subpixel order */
7406 drm_mode_destroy(dev, adjusted_mode);
7407 if (!ret && crtc->enabled) {
7408 crtc->hwmode = saved_hwmode;
7409 crtc->mode = saved_mode;
7411 intel_modeset_check_state(dev);
7417 #undef for_each_intel_crtc_masked
7419 static void intel_set_config_free(struct intel_set_config *config)
7424 kfree(config->save_connector_encoders);
7425 kfree(config->save_encoder_crtcs);
7429 static int intel_set_config_save_state(struct drm_device *dev,
7430 struct intel_set_config *config)
7432 struct drm_encoder *encoder;
7433 struct drm_connector *connector;
7436 config->save_encoder_crtcs =
7437 kcalloc(dev->mode_config.num_encoder,
7438 sizeof(struct drm_crtc *), GFP_KERNEL);
7439 if (!config->save_encoder_crtcs)
7442 config->save_connector_encoders =
7443 kcalloc(dev->mode_config.num_connector,
7444 sizeof(struct drm_encoder *), GFP_KERNEL);
7445 if (!config->save_connector_encoders)
7448 /* Copy data. Note that driver private data is not affected.
7449 * Should anything bad happen only the expected state is
7450 * restored, not the drivers personal bookkeeping.
7453 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7454 config->save_encoder_crtcs[count++] = encoder->crtc;
7458 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7459 config->save_connector_encoders[count++] = connector->encoder;
7465 static void intel_set_config_restore_state(struct drm_device *dev,
7466 struct intel_set_config *config)
7468 struct intel_encoder *encoder;
7469 struct intel_connector *connector;
7473 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7475 to_intel_crtc(config->save_encoder_crtcs[count++]);
7479 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7480 connector->new_encoder =
7481 to_intel_encoder(config->save_connector_encoders[count++]);
7486 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7487 struct intel_set_config *config)
7490 /* We should be able to check here if the fb has the same properties
7491 * and then just flip_or_move it */
7492 if (set->crtc->fb != set->fb) {
7493 /* If we have no fb then treat it as a full mode set */
7494 if (set->crtc->fb == NULL) {
7495 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7496 config->mode_changed = true;
7497 } else if (set->fb == NULL) {
7498 config->mode_changed = true;
7499 } else if (set->fb->depth != set->crtc->fb->depth) {
7500 config->mode_changed = true;
7501 } else if (set->fb->bits_per_pixel !=
7502 set->crtc->fb->bits_per_pixel) {
7503 config->mode_changed = true;
7505 config->fb_changed = true;
7508 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7509 config->fb_changed = true;
7511 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7512 DRM_DEBUG_KMS("modes are different, full mode set\n");
7513 drm_mode_debug_printmodeline(&set->crtc->mode);
7514 drm_mode_debug_printmodeline(set->mode);
7515 config->mode_changed = true;
7520 intel_modeset_stage_output_state(struct drm_device *dev,
7521 struct drm_mode_set *set,
7522 struct intel_set_config *config)
7524 struct drm_crtc *new_crtc;
7525 struct intel_connector *connector;
7526 struct intel_encoder *encoder;
7529 /* The upper layers ensure that we either disabl a crtc or have a list
7530 * of connectors. For paranoia, double-check this. */
7531 WARN_ON(!set->fb && (set->num_connectors != 0));
7532 WARN_ON(set->fb && (set->num_connectors == 0));
7535 list_for_each_entry(connector, &dev->mode_config.connector_list,
7537 /* Otherwise traverse passed in connector list and get encoders
7539 for (ro = 0; ro < set->num_connectors; ro++) {
7540 if (set->connectors[ro] == &connector->base) {
7541 connector->new_encoder = connector->encoder;
7546 /* If we disable the crtc, disable all its connectors. Also, if
7547 * the connector is on the changing crtc but not on the new
7548 * connector list, disable it. */
7549 if ((!set->fb || ro == set->num_connectors) &&
7550 connector->base.encoder &&
7551 connector->base.encoder->crtc == set->crtc) {
7552 connector->new_encoder = NULL;
7554 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7555 connector->base.base.id,
7556 drm_get_connector_name(&connector->base));
7560 if (&connector->new_encoder->base != connector->base.encoder) {
7561 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7562 config->mode_changed = true;
7565 /* Disable all disconnected encoders. */
7566 if (connector->base.status == connector_status_disconnected)
7567 connector->new_encoder = NULL;
7569 /* connector->new_encoder is now updated for all connectors. */
7571 /* Update crtc of enabled connectors. */
7573 list_for_each_entry(connector, &dev->mode_config.connector_list,
7575 if (!connector->new_encoder)
7578 new_crtc = connector->new_encoder->base.crtc;
7580 for (ro = 0; ro < set->num_connectors; ro++) {
7581 if (set->connectors[ro] == &connector->base)
7582 new_crtc = set->crtc;
7585 /* Make sure the new CRTC will work with the encoder */
7586 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7590 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7592 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7593 connector->base.base.id,
7594 drm_get_connector_name(&connector->base),
7598 /* Check for any encoders that needs to be disabled. */
7599 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7601 list_for_each_entry(connector,
7602 &dev->mode_config.connector_list,
7604 if (connector->new_encoder == encoder) {
7605 WARN_ON(!connector->new_encoder->new_crtc);
7610 encoder->new_crtc = NULL;
7612 /* Only now check for crtc changes so we don't miss encoders
7613 * that will be disabled. */
7614 if (&encoder->new_crtc->base != encoder->base.crtc) {
7615 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7616 config->mode_changed = true;
7619 /* Now we've also updated encoder->new_crtc for all encoders. */
7624 static int intel_crtc_set_config(struct drm_mode_set *set)
7626 struct drm_device *dev;
7627 struct drm_mode_set save_set;
7628 struct intel_set_config *config;
7633 BUG_ON(!set->crtc->helper_private);
7638 /* The fb helper likes to play gross jokes with ->mode_set_config.
7639 * Unfortunately the crtc helper doesn't do much at all for this case,
7640 * so we have to cope with this madness until the fb helper is fixed up. */
7641 if (set->fb && set->num_connectors == 0)
7645 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7646 set->crtc->base.id, set->fb->base.id,
7647 (int)set->num_connectors, set->x, set->y);
7649 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7652 dev = set->crtc->dev;
7655 config = kzalloc(sizeof(*config), GFP_KERNEL);
7659 ret = intel_set_config_save_state(dev, config);
7663 save_set.crtc = set->crtc;
7664 save_set.mode = &set->crtc->mode;
7665 save_set.x = set->crtc->x;
7666 save_set.y = set->crtc->y;
7667 save_set.fb = set->crtc->fb;
7669 /* Compute whether we need a full modeset, only an fb base update or no
7670 * change at all. In the future we might also check whether only the
7671 * mode changed, e.g. for LVDS where we only change the panel fitter in
7673 intel_set_config_compute_mode_changes(set, config);
7675 ret = intel_modeset_stage_output_state(dev, set, config);
7679 if (config->mode_changed) {
7681 DRM_DEBUG_KMS("attempting to set mode from"
7683 drm_mode_debug_printmodeline(set->mode);
7686 if (!intel_set_mode(set->crtc, set->mode,
7687 set->x, set->y, set->fb)) {
7688 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7689 set->crtc->base.id);
7693 } else if (config->fb_changed) {
7694 ret = intel_pipe_set_base(set->crtc,
7695 set->x, set->y, set->fb);
7698 intel_set_config_free(config);
7703 intel_set_config_restore_state(dev, config);
7705 /* Try to restore the config */
7706 if (config->mode_changed &&
7707 !intel_set_mode(save_set.crtc, save_set.mode,
7708 save_set.x, save_set.y, save_set.fb))
7709 DRM_ERROR("failed to restore config after modeset failure\n");
7712 intel_set_config_free(config);
7716 static const struct drm_crtc_funcs intel_crtc_funcs = {
7717 .cursor_set = intel_crtc_cursor_set,
7718 .cursor_move = intel_crtc_cursor_move,
7719 .gamma_set = intel_crtc_gamma_set,
7720 .set_config = intel_crtc_set_config,
7721 .destroy = intel_crtc_destroy,
7722 .page_flip = intel_crtc_page_flip,
7725 static void intel_cpu_pll_init(struct drm_device *dev)
7727 if (IS_HASWELL(dev))
7728 intel_ddi_pll_init(dev);
7731 static void intel_pch_pll_init(struct drm_device *dev)
7733 drm_i915_private_t *dev_priv = dev->dev_private;
7736 if (dev_priv->num_pch_pll == 0) {
7737 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7741 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7742 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7743 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7744 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7748 static void intel_crtc_init(struct drm_device *dev, int pipe)
7750 drm_i915_private_t *dev_priv = dev->dev_private;
7751 struct intel_crtc *intel_crtc;
7754 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7755 if (intel_crtc == NULL)
7758 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7760 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7761 for (i = 0; i < 256; i++) {
7762 intel_crtc->lut_r[i] = i;
7763 intel_crtc->lut_g[i] = i;
7764 intel_crtc->lut_b[i] = i;
7767 /* Swap pipes & planes for FBC on pre-965 */
7768 intel_crtc->pipe = pipe;
7769 intel_crtc->plane = pipe;
7770 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7771 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7772 intel_crtc->plane = !pipe;
7775 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7776 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7777 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7778 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7780 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7782 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7785 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7786 struct drm_file *file)
7788 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7789 struct drm_mode_object *drmmode_obj;
7790 struct intel_crtc *crtc;
7792 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7795 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7796 DRM_MODE_OBJECT_CRTC);
7799 DRM_ERROR("no such CRTC id\n");
7803 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7804 pipe_from_crtc_id->pipe = crtc->pipe;
7809 static int intel_encoder_clones(struct intel_encoder *encoder)
7811 struct drm_device *dev = encoder->base.dev;
7812 struct intel_encoder *source_encoder;
7816 list_for_each_entry(source_encoder,
7817 &dev->mode_config.encoder_list, base.head) {
7819 if (encoder == source_encoder)
7820 index_mask |= (1 << entry);
7822 /* Intel hw has only one MUX where enocoders could be cloned. */
7823 if (encoder->cloneable && source_encoder->cloneable)
7824 index_mask |= (1 << entry);
7832 static bool has_edp_a(struct drm_device *dev)
7834 struct drm_i915_private *dev_priv = dev->dev_private;
7836 if (!IS_MOBILE(dev))
7839 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7843 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7849 static void intel_setup_outputs(struct drm_device *dev)
7851 struct drm_i915_private *dev_priv = dev->dev_private;
7852 struct intel_encoder *encoder;
7853 bool dpd_is_edp = false;
7856 has_lvds = intel_lvds_init(dev);
7857 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7858 /* disable the panel fitter on everything but LVDS */
7859 I915_WRITE(PFIT_CONTROL, 0);
7862 if (HAS_PCH_SPLIT(dev)) {
7863 dpd_is_edp = intel_dpd_is_edp(dev);
7866 intel_dp_init(dev, DP_A, PORT_A);
7868 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7869 intel_dp_init(dev, PCH_DP_D, PORT_D);
7872 intel_crt_init(dev);
7874 if (IS_HASWELL(dev)) {
7877 /* Haswell uses DDI functions to detect digital outputs */
7878 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7879 /* DDI A only supports eDP */
7881 intel_ddi_init(dev, PORT_A);
7883 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7885 found = I915_READ(SFUSE_STRAP);
7887 if (found & SFUSE_STRAP_DDIB_DETECTED)
7888 intel_ddi_init(dev, PORT_B);
7889 if (found & SFUSE_STRAP_DDIC_DETECTED)
7890 intel_ddi_init(dev, PORT_C);
7891 if (found & SFUSE_STRAP_DDID_DETECTED)
7892 intel_ddi_init(dev, PORT_D);
7893 } else if (HAS_PCH_SPLIT(dev)) {
7896 if (I915_READ(HDMIB) & PORT_DETECTED) {
7897 /* PCH SDVOB multiplex with HDMIB */
7898 found = intel_sdvo_init(dev, PCH_SDVOB, true);
7900 intel_hdmi_init(dev, HDMIB, PORT_B);
7901 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7902 intel_dp_init(dev, PCH_DP_B, PORT_B);
7905 if (I915_READ(HDMIC) & PORT_DETECTED)
7906 intel_hdmi_init(dev, HDMIC, PORT_C);
7908 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7909 intel_hdmi_init(dev, HDMID, PORT_D);
7911 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7912 intel_dp_init(dev, PCH_DP_C, PORT_C);
7914 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7915 intel_dp_init(dev, PCH_DP_D, PORT_D);
7916 } else if (IS_VALLEYVIEW(dev)) {
7919 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
7920 if (I915_READ(DP_C) & DP_DETECTED)
7921 intel_dp_init(dev, DP_C, PORT_C);
7923 if (I915_READ(SDVOB) & PORT_DETECTED) {
7924 /* SDVOB multiplex with HDMIB */
7925 found = intel_sdvo_init(dev, SDVOB, true);
7927 intel_hdmi_init(dev, SDVOB, PORT_B);
7928 if (!found && (I915_READ(DP_B) & DP_DETECTED))
7929 intel_dp_init(dev, DP_B, PORT_B);
7932 if (I915_READ(SDVOC) & PORT_DETECTED)
7933 intel_hdmi_init(dev, SDVOC, PORT_C);
7935 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7938 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7939 DRM_DEBUG_KMS("probing SDVOB\n");
7940 found = intel_sdvo_init(dev, SDVOB, true);
7941 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7942 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7943 intel_hdmi_init(dev, SDVOB, PORT_B);
7946 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7947 DRM_DEBUG_KMS("probing DP_B\n");
7948 intel_dp_init(dev, DP_B, PORT_B);
7952 /* Before G4X SDVOC doesn't have its own detect register */
7954 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7955 DRM_DEBUG_KMS("probing SDVOC\n");
7956 found = intel_sdvo_init(dev, SDVOC, false);
7959 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7961 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7962 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7963 intel_hdmi_init(dev, SDVOC, PORT_C);
7965 if (SUPPORTS_INTEGRATED_DP(dev)) {
7966 DRM_DEBUG_KMS("probing DP_C\n");
7967 intel_dp_init(dev, DP_C, PORT_C);
7971 if (SUPPORTS_INTEGRATED_DP(dev) &&
7972 (I915_READ(DP_D) & DP_DETECTED)) {
7973 DRM_DEBUG_KMS("probing DP_D\n");
7974 intel_dp_init(dev, DP_D, PORT_D);
7976 } else if (IS_GEN2(dev))
7977 intel_dvo_init(dev);
7979 if (SUPPORTS_TV(dev))
7982 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7983 encoder->base.possible_crtcs = encoder->crtc_mask;
7984 encoder->base.possible_clones =
7985 intel_encoder_clones(encoder);
7988 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7989 ironlake_init_pch_refclk(dev);
7992 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7994 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7996 drm_framebuffer_cleanup(fb);
7997 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8002 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8003 struct drm_file *file,
8004 unsigned int *handle)
8006 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8007 struct drm_i915_gem_object *obj = intel_fb->obj;
8009 return drm_gem_handle_create(file, &obj->base, handle);
8012 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8013 .destroy = intel_user_framebuffer_destroy,
8014 .create_handle = intel_user_framebuffer_create_handle,
8017 int intel_framebuffer_init(struct drm_device *dev,
8018 struct intel_framebuffer *intel_fb,
8019 struct drm_mode_fb_cmd2 *mode_cmd,
8020 struct drm_i915_gem_object *obj)
8024 if (obj->tiling_mode == I915_TILING_Y)
8027 if (mode_cmd->pitches[0] & 63)
8030 switch (mode_cmd->pixel_format) {
8031 case DRM_FORMAT_RGB332:
8032 case DRM_FORMAT_RGB565:
8033 case DRM_FORMAT_XRGB8888:
8034 case DRM_FORMAT_XBGR8888:
8035 case DRM_FORMAT_ARGB8888:
8036 case DRM_FORMAT_XRGB2101010:
8037 case DRM_FORMAT_ARGB2101010:
8038 /* RGB formats are common across chipsets */
8040 case DRM_FORMAT_YUYV:
8041 case DRM_FORMAT_UYVY:
8042 case DRM_FORMAT_YVYU:
8043 case DRM_FORMAT_VYUY:
8046 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8047 mode_cmd->pixel_format);
8051 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8053 DRM_ERROR("framebuffer init failed %d\n", ret);
8057 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8058 intel_fb->obj = obj;
8062 static struct drm_framebuffer *
8063 intel_user_framebuffer_create(struct drm_device *dev,
8064 struct drm_file *filp,
8065 struct drm_mode_fb_cmd2 *mode_cmd)
8067 struct drm_i915_gem_object *obj;
8069 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8070 mode_cmd->handles[0]));
8071 if (&obj->base == NULL)
8072 return ERR_PTR(-ENOENT);
8074 return intel_framebuffer_create(dev, mode_cmd, obj);
8077 static const struct drm_mode_config_funcs intel_mode_funcs = {
8078 .fb_create = intel_user_framebuffer_create,
8079 .output_poll_changed = intel_fb_output_poll_changed,
8082 /* Set up chip specific display functions */
8083 static void intel_init_display(struct drm_device *dev)
8085 struct drm_i915_private *dev_priv = dev->dev_private;
8087 /* We always want a DPMS function */
8088 if (IS_HASWELL(dev)) {
8089 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8090 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8091 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8092 dev_priv->display.off = haswell_crtc_off;
8093 dev_priv->display.update_plane = ironlake_update_plane;
8094 } else if (HAS_PCH_SPLIT(dev)) {
8095 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8096 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8097 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8098 dev_priv->display.off = ironlake_crtc_off;
8099 dev_priv->display.update_plane = ironlake_update_plane;
8101 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8102 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8103 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8104 dev_priv->display.off = i9xx_crtc_off;
8105 dev_priv->display.update_plane = i9xx_update_plane;
8108 /* Returns the core display clock speed */
8109 if (IS_VALLEYVIEW(dev))
8110 dev_priv->display.get_display_clock_speed =
8111 valleyview_get_display_clock_speed;
8112 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8113 dev_priv->display.get_display_clock_speed =
8114 i945_get_display_clock_speed;
8115 else if (IS_I915G(dev))
8116 dev_priv->display.get_display_clock_speed =
8117 i915_get_display_clock_speed;
8118 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8119 dev_priv->display.get_display_clock_speed =
8120 i9xx_misc_get_display_clock_speed;
8121 else if (IS_I915GM(dev))
8122 dev_priv->display.get_display_clock_speed =
8123 i915gm_get_display_clock_speed;
8124 else if (IS_I865G(dev))
8125 dev_priv->display.get_display_clock_speed =
8126 i865_get_display_clock_speed;
8127 else if (IS_I85X(dev))
8128 dev_priv->display.get_display_clock_speed =
8129 i855_get_display_clock_speed;
8131 dev_priv->display.get_display_clock_speed =
8132 i830_get_display_clock_speed;
8134 if (HAS_PCH_SPLIT(dev)) {
8136 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8137 dev_priv->display.write_eld = ironlake_write_eld;
8138 } else if (IS_GEN6(dev)) {
8139 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8140 dev_priv->display.write_eld = ironlake_write_eld;
8141 } else if (IS_IVYBRIDGE(dev)) {
8142 /* FIXME: detect B0+ stepping and use auto training */
8143 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8144 dev_priv->display.write_eld = ironlake_write_eld;
8145 } else if (IS_HASWELL(dev)) {
8146 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8147 dev_priv->display.write_eld = haswell_write_eld;
8149 dev_priv->display.update_wm = NULL;
8150 } else if (IS_G4X(dev)) {
8151 dev_priv->display.write_eld = g4x_write_eld;
8154 /* Default just returns -ENODEV to indicate unsupported */
8155 dev_priv->display.queue_flip = intel_default_queue_flip;
8157 switch (INTEL_INFO(dev)->gen) {
8159 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8163 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8168 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8172 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8175 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8181 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8182 * resume, or other times. This quirk makes sure that's the case for
8185 static void quirk_pipea_force(struct drm_device *dev)
8187 struct drm_i915_private *dev_priv = dev->dev_private;
8189 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8190 DRM_INFO("applying pipe a force quirk\n");
8194 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8196 static void quirk_ssc_force_disable(struct drm_device *dev)
8198 struct drm_i915_private *dev_priv = dev->dev_private;
8199 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8200 DRM_INFO("applying lvds SSC disable quirk\n");
8204 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8207 static void quirk_invert_brightness(struct drm_device *dev)
8209 struct drm_i915_private *dev_priv = dev->dev_private;
8210 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8211 DRM_INFO("applying inverted panel brightness quirk\n");
8214 struct intel_quirk {
8216 int subsystem_vendor;
8217 int subsystem_device;
8218 void (*hook)(struct drm_device *dev);
8221 static struct intel_quirk intel_quirks[] = {
8222 /* HP Mini needs pipe A force quirk (LP: #322104) */
8223 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8225 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8226 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8228 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8229 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8231 /* 855 & before need to leave pipe A & dpll A up */
8232 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8233 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8234 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8236 /* Lenovo U160 cannot use SSC on LVDS */
8237 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8239 /* Sony Vaio Y cannot use SSC on LVDS */
8240 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8242 /* Acer Aspire 5734Z must invert backlight brightness */
8243 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8246 static void intel_init_quirks(struct drm_device *dev)
8248 struct pci_dev *d = dev->pdev;
8251 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8252 struct intel_quirk *q = &intel_quirks[i];
8254 if (d->device == q->device &&
8255 (d->subsystem_vendor == q->subsystem_vendor ||
8256 q->subsystem_vendor == PCI_ANY_ID) &&
8257 (d->subsystem_device == q->subsystem_device ||
8258 q->subsystem_device == PCI_ANY_ID))
8263 /* Disable the VGA plane that we never use */
8264 static void i915_disable_vga(struct drm_device *dev)
8266 struct drm_i915_private *dev_priv = dev->dev_private;
8270 if (HAS_PCH_SPLIT(dev))
8271 vga_reg = CPU_VGACNTRL;
8275 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8276 outb(SR01, VGA_SR_INDEX);
8277 sr1 = inb(VGA_SR_DATA);
8278 outb(sr1 | 1<<5, VGA_SR_DATA);
8279 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8282 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8283 POSTING_READ(vga_reg);
8286 void intel_modeset_init_hw(struct drm_device *dev)
8288 /* We attempt to init the necessary power wells early in the initialization
8289 * time, so the subsystems that expect power to be enabled can work.
8291 intel_init_power_wells(dev);
8293 intel_prepare_ddi(dev);
8295 intel_init_clock_gating(dev);
8297 mutex_lock(&dev->struct_mutex);
8298 intel_enable_gt_powersave(dev);
8299 mutex_unlock(&dev->struct_mutex);
8302 void intel_modeset_init(struct drm_device *dev)
8304 struct drm_i915_private *dev_priv = dev->dev_private;
8307 drm_mode_config_init(dev);
8309 dev->mode_config.min_width = 0;
8310 dev->mode_config.min_height = 0;
8312 dev->mode_config.preferred_depth = 24;
8313 dev->mode_config.prefer_shadow = 1;
8315 dev->mode_config.funcs = &intel_mode_funcs;
8317 intel_init_quirks(dev);
8321 intel_init_display(dev);
8324 dev->mode_config.max_width = 2048;
8325 dev->mode_config.max_height = 2048;
8326 } else if (IS_GEN3(dev)) {
8327 dev->mode_config.max_width = 4096;
8328 dev->mode_config.max_height = 4096;
8330 dev->mode_config.max_width = 8192;
8331 dev->mode_config.max_height = 8192;
8333 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8335 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8336 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8338 for (i = 0; i < dev_priv->num_pipe; i++) {
8339 intel_crtc_init(dev, i);
8340 ret = intel_plane_init(dev, i);
8342 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8345 intel_cpu_pll_init(dev);
8346 intel_pch_pll_init(dev);
8348 /* Just disable it once at startup */
8349 i915_disable_vga(dev);
8350 intel_setup_outputs(dev);
8354 intel_connector_break_all_links(struct intel_connector *connector)
8356 connector->base.dpms = DRM_MODE_DPMS_OFF;
8357 connector->base.encoder = NULL;
8358 connector->encoder->connectors_active = false;
8359 connector->encoder->base.crtc = NULL;
8362 static void intel_enable_pipe_a(struct drm_device *dev)
8364 struct intel_connector *connector;
8365 struct drm_connector *crt = NULL;
8366 struct intel_load_detect_pipe load_detect_temp;
8368 /* We can't just switch on the pipe A, we need to set things up with a
8369 * proper mode and output configuration. As a gross hack, enable pipe A
8370 * by enabling the load detect pipe once. */
8371 list_for_each_entry(connector,
8372 &dev->mode_config.connector_list,
8374 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8375 crt = &connector->base;
8383 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8384 intel_release_load_detect_pipe(crt, &load_detect_temp);
8389 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8391 struct drm_device *dev = crtc->base.dev;
8392 struct drm_i915_private *dev_priv = dev->dev_private;
8395 /* Clear any frame start delays used for debugging left by the BIOS */
8396 reg = PIPECONF(crtc->pipe);
8397 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8399 /* We need to sanitize the plane -> pipe mapping first because this will
8400 * disable the crtc (and hence change the state) if it is wrong. */
8401 if (!HAS_PCH_SPLIT(dev)) {
8402 struct intel_connector *connector;
8405 reg = DSPCNTR(crtc->plane);
8406 val = I915_READ(reg);
8408 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8409 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8412 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8413 crtc->base.base.id);
8415 /* Pipe has the wrong plane attached and the plane is active.
8416 * Temporarily change the plane mapping and disable everything
8418 plane = crtc->plane;
8419 crtc->plane = !plane;
8420 dev_priv->display.crtc_disable(&crtc->base);
8421 crtc->plane = plane;
8423 /* ... and break all links. */
8424 list_for_each_entry(connector, &dev->mode_config.connector_list,
8426 if (connector->encoder->base.crtc != &crtc->base)
8429 intel_connector_break_all_links(connector);
8432 WARN_ON(crtc->active);
8433 crtc->base.enabled = false;
8437 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8438 crtc->pipe == PIPE_A && !crtc->active) {
8439 /* BIOS forgot to enable pipe A, this mostly happens after
8440 * resume. Force-enable the pipe to fix this, the update_dpms
8441 * call below we restore the pipe to the right state, but leave
8442 * the required bits on. */
8443 intel_enable_pipe_a(dev);
8446 /* Adjust the state of the output pipe according to whether we
8447 * have active connectors/encoders. */
8448 intel_crtc_update_dpms(&crtc->base);
8450 if (crtc->active != crtc->base.enabled) {
8451 struct intel_encoder *encoder;
8453 /* This can happen either due to bugs in the get_hw_state
8454 * functions or because the pipe is force-enabled due to the
8456 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8458 crtc->base.enabled ? "enabled" : "disabled",
8459 crtc->active ? "enabled" : "disabled");
8461 crtc->base.enabled = crtc->active;
8463 /* Because we only establish the connector -> encoder ->
8464 * crtc links if something is active, this means the
8465 * crtc is now deactivated. Break the links. connector
8466 * -> encoder links are only establish when things are
8467 * actually up, hence no need to break them. */
8468 WARN_ON(crtc->active);
8470 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8471 WARN_ON(encoder->connectors_active);
8472 encoder->base.crtc = NULL;
8477 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8479 struct intel_connector *connector;
8480 struct drm_device *dev = encoder->base.dev;
8482 /* We need to check both for a crtc link (meaning that the
8483 * encoder is active and trying to read from a pipe) and the
8484 * pipe itself being active. */
8485 bool has_active_crtc = encoder->base.crtc &&
8486 to_intel_crtc(encoder->base.crtc)->active;
8488 if (encoder->connectors_active && !has_active_crtc) {
8489 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8490 encoder->base.base.id,
8491 drm_get_encoder_name(&encoder->base));
8493 /* Connector is active, but has no active pipe. This is
8494 * fallout from our resume register restoring. Disable
8495 * the encoder manually again. */
8496 if (encoder->base.crtc) {
8497 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8498 encoder->base.base.id,
8499 drm_get_encoder_name(&encoder->base));
8500 encoder->disable(encoder);
8503 /* Inconsistent output/port/pipe state happens presumably due to
8504 * a bug in one of the get_hw_state functions. Or someplace else
8505 * in our code, like the register restore mess on resume. Clamp
8506 * things to off as a safer default. */
8507 list_for_each_entry(connector,
8508 &dev->mode_config.connector_list,
8510 if (connector->encoder != encoder)
8513 intel_connector_break_all_links(connector);
8516 /* Enabled encoders without active connectors will be fixed in
8517 * the crtc fixup. */
8520 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8521 * and i915 state tracking structures. */
8522 void intel_modeset_setup_hw_state(struct drm_device *dev)
8524 struct drm_i915_private *dev_priv = dev->dev_private;
8527 struct intel_crtc *crtc;
8528 struct intel_encoder *encoder;
8529 struct intel_connector *connector;
8531 for_each_pipe(pipe) {
8532 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8534 tmp = I915_READ(PIPECONF(pipe));
8535 if (tmp & PIPECONF_ENABLE)
8536 crtc->active = true;
8538 crtc->active = false;
8540 crtc->base.enabled = crtc->active;
8542 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8544 crtc->active ? "enabled" : "disabled");
8547 if (IS_HASWELL(dev))
8548 intel_ddi_setup_hw_pll_state(dev);
8550 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8554 if (encoder->get_hw_state(encoder, &pipe)) {
8555 encoder->base.crtc =
8556 dev_priv->pipe_to_crtc_mapping[pipe];
8558 encoder->base.crtc = NULL;
8561 encoder->connectors_active = false;
8562 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8563 encoder->base.base.id,
8564 drm_get_encoder_name(&encoder->base),
8565 encoder->base.crtc ? "enabled" : "disabled",
8569 list_for_each_entry(connector, &dev->mode_config.connector_list,
8571 if (connector->get_hw_state(connector)) {
8572 connector->base.dpms = DRM_MODE_DPMS_ON;
8573 connector->encoder->connectors_active = true;
8574 connector->base.encoder = &connector->encoder->base;
8576 connector->base.dpms = DRM_MODE_DPMS_OFF;
8577 connector->base.encoder = NULL;
8579 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8580 connector->base.base.id,
8581 drm_get_connector_name(&connector->base),
8582 connector->base.encoder ? "enabled" : "disabled");
8585 /* HW state is read out, now we need to sanitize this mess. */
8586 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8588 intel_sanitize_encoder(encoder);
8591 for_each_pipe(pipe) {
8592 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8593 intel_sanitize_crtc(crtc);
8596 intel_modeset_update_staged_output_state(dev);
8598 intel_modeset_check_state(dev);
8601 void intel_modeset_gem_init(struct drm_device *dev)
8603 intel_modeset_init_hw(dev);
8605 intel_setup_overlay(dev);
8607 intel_modeset_setup_hw_state(dev);
8610 void intel_modeset_cleanup(struct drm_device *dev)
8612 struct drm_i915_private *dev_priv = dev->dev_private;
8613 struct drm_crtc *crtc;
8614 struct intel_crtc *intel_crtc;
8616 drm_kms_helper_poll_fini(dev);
8617 mutex_lock(&dev->struct_mutex);
8619 intel_unregister_dsm_handler();
8622 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8623 /* Skip inactive CRTCs */
8627 intel_crtc = to_intel_crtc(crtc);
8628 intel_increase_pllclock(crtc);
8631 intel_disable_fbc(dev);
8633 intel_disable_gt_powersave(dev);
8635 ironlake_teardown_rc6(dev);
8637 if (IS_VALLEYVIEW(dev))
8640 mutex_unlock(&dev->struct_mutex);
8642 /* Disable the irq before mode object teardown, for the irq might
8643 * enqueue unpin/hotplug work. */
8644 drm_irq_uninstall(dev);
8645 cancel_work_sync(&dev_priv->hotplug_work);
8646 cancel_work_sync(&dev_priv->rps.work);
8648 /* flush any delayed tasks or pending work */
8649 flush_scheduled_work();
8651 drm_mode_config_cleanup(dev);
8655 * Return which encoder is currently attached for connector.
8657 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8659 return &intel_attached_encoder(connector)->base;
8662 void intel_connector_attach_encoder(struct intel_connector *connector,
8663 struct intel_encoder *encoder)
8665 connector->encoder = encoder;
8666 drm_mode_connector_attach_encoder(&connector->base,
8671 * set vga decode state - true == enable VGA decode
8673 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8675 struct drm_i915_private *dev_priv = dev->dev_private;
8678 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8680 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8682 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8683 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8687 #ifdef CONFIG_DEBUG_FS
8688 #include <linux/seq_file.h>
8690 struct intel_display_error_state {
8691 struct intel_cursor_error_state {
8696 } cursor[I915_MAX_PIPES];
8698 struct intel_pipe_error_state {
8708 } pipe[I915_MAX_PIPES];
8710 struct intel_plane_error_state {
8718 } plane[I915_MAX_PIPES];
8721 struct intel_display_error_state *
8722 intel_display_capture_error_state(struct drm_device *dev)
8724 drm_i915_private_t *dev_priv = dev->dev_private;
8725 struct intel_display_error_state *error;
8728 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8733 error->cursor[i].control = I915_READ(CURCNTR(i));
8734 error->cursor[i].position = I915_READ(CURPOS(i));
8735 error->cursor[i].base = I915_READ(CURBASE(i));
8737 error->plane[i].control = I915_READ(DSPCNTR(i));
8738 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8739 error->plane[i].size = I915_READ(DSPSIZE(i));
8740 error->plane[i].pos = I915_READ(DSPPOS(i));
8741 error->plane[i].addr = I915_READ(DSPADDR(i));
8742 if (INTEL_INFO(dev)->gen >= 4) {
8743 error->plane[i].surface = I915_READ(DSPSURF(i));
8744 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8747 error->pipe[i].conf = I915_READ(PIPECONF(i));
8748 error->pipe[i].source = I915_READ(PIPESRC(i));
8749 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8750 error->pipe[i].hblank = I915_READ(HBLANK(i));
8751 error->pipe[i].hsync = I915_READ(HSYNC(i));
8752 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8753 error->pipe[i].vblank = I915_READ(VBLANK(i));
8754 error->pipe[i].vsync = I915_READ(VSYNC(i));
8761 intel_display_print_error_state(struct seq_file *m,
8762 struct drm_device *dev,
8763 struct intel_display_error_state *error)
8765 drm_i915_private_t *dev_priv = dev->dev_private;
8768 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8770 seq_printf(m, "Pipe [%d]:\n", i);
8771 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8772 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8773 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8774 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8775 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8776 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8777 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8778 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8780 seq_printf(m, "Plane [%d]:\n", i);
8781 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8782 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8783 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8784 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8785 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8786 if (INTEL_INFO(dev)->gen >= 4) {
8787 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8788 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8791 seq_printf(m, "Cursor [%d]:\n", i);
8792 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8793 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8794 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);