2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82 intel_pch_rawclk(struct drm_device *dev)
84 struct drm_i915_private *dev_priv = dev->dev_private;
86 WARN_ON(!HAS_PCH_SPLIT(dev));
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
114 static inline u32 /* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device *dev)
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
124 static const intel_limit_t intel_limits_i8xx_dvo = {
125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
135 .find_pll = intel_find_best_PLL,
138 static const intel_limit_t intel_limits_i8xx_lvds = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
149 .find_pll = intel_find_best_PLL,
152 static const intel_limit_t intel_limits_i9xx_sdvo = {
153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 8, .max = 18 },
158 .m2 = { .min = 3, .max = 7 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
163 .find_pll = intel_find_best_PLL,
166 static const intel_limit_t intel_limits_i9xx_lvds = {
167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 8, .max = 18 },
172 .m2 = { .min = 3, .max = 7 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
177 .find_pll = intel_find_best_PLL,
181 static const intel_limit_t intel_limits_g4x_sdvo = {
182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
194 .find_pll = intel_g4x_find_best_PLL,
197 static const intel_limit_t intel_limits_g4x_hdmi = {
198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
208 .find_pll = intel_g4x_find_best_PLL,
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
223 .find_pll = intel_g4x_find_best_PLL,
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
238 .find_pll = intel_g4x_find_best_PLL,
241 static const intel_limit_t intel_limits_g4x_display_port = {
242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 10, .p2_fast = 10 },
252 .find_pll = intel_find_pll_g4x_dp,
255 static const intel_limit_t intel_limits_pineview_sdvo = {
256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
268 .find_pll = intel_find_best_PLL,
271 static const intel_limit_t intel_limits_pineview_lvds = {
272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
282 .find_pll = intel_find_best_PLL,
285 /* Ironlake / Sandybridge
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
290 static const intel_limit_t intel_limits_ironlake_dac = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
301 .find_pll = intel_g4x_find_best_PLL,
304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
315 .find_pll = intel_g4x_find_best_PLL,
318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
329 .find_pll = intel_g4x_find_best_PLL,
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 .find_pll = intel_g4x_find_best_PLL,
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 .find_pll = intel_g4x_find_best_PLL,
361 static const intel_limit_t intel_limits_ironlake_display_port = {
362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
371 .p2_slow = 10, .p2_fast = 10 },
372 .find_pll = intel_find_pll_ironlake_dp,
375 static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
389 static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
391 .vco = { .min = 4000000, .max = 5994000},
392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
403 static const intel_limit_t intel_limits_vlv_dp = {
404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
406 .n = { .min = 1, .max = 7 },
407 .m = { .min = 22, .max = 450 },
408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
434 return I915_READ(DPIO_DATA);
437 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
455 static void vlv_init_dpio(struct drm_device *dev)
457 struct drm_i915_private *dev_priv = dev->dev_private;
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
466 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
469 struct drm_device *dev = crtc->dev;
470 const intel_limit_t *limit;
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
473 if (intel_is_dual_link_lvds(dev)) {
474 /* LVDS dual channel */
475 if (refclk == 100000)
476 limit = &intel_limits_ironlake_dual_lvds_100m;
478 limit = &intel_limits_ironlake_dual_lvds;
480 if (refclk == 100000)
481 limit = &intel_limits_ironlake_single_lvds_100m;
483 limit = &intel_limits_ironlake_single_lvds;
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
487 limit = &intel_limits_ironlake_display_port;
489 limit = &intel_limits_ironlake_dac;
494 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
496 struct drm_device *dev = crtc->dev;
497 const intel_limit_t *limit;
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
500 if (intel_is_dual_link_lvds(dev))
501 /* LVDS with dual channel */
502 limit = &intel_limits_g4x_dual_channel_lvds;
504 /* LVDS with dual channel */
505 limit = &intel_limits_g4x_single_channel_lvds;
506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
508 limit = &intel_limits_g4x_hdmi;
509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
510 limit = &intel_limits_g4x_sdvo;
511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
512 limit = &intel_limits_g4x_display_port;
513 } else /* The option is for other outputs */
514 limit = &intel_limits_i9xx_sdvo;
519 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
524 if (HAS_PCH_SPLIT(dev))
525 limit = intel_ironlake_limit(crtc, refclk);
526 else if (IS_G4X(dev)) {
527 limit = intel_g4x_limit(crtc);
528 } else if (IS_PINEVIEW(dev)) {
529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
530 limit = &intel_limits_pineview_lvds;
532 limit = &intel_limits_pineview_sdvo;
533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
539 limit = &intel_limits_vlv_dp;
540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
544 limit = &intel_limits_i9xx_sdvo;
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
547 limit = &intel_limits_i8xx_lvds;
549 limit = &intel_limits_i8xx_dvo;
554 /* m1 is reserved as 0 in Pineview, n is a ring counter */
555 static void pineview_clock(int refclk, intel_clock_t *clock)
557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
563 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
576 * Returns whether any output on the specified pipe is of the specified type
578 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
580 struct drm_device *dev = crtc->dev;
581 struct intel_encoder *encoder;
583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
590 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
596 static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
601 INTELPllInvalid("p1 out of range\n");
602 if (clock->p < limit->p.min || limit->p.max < clock->p)
603 INTELPllInvalid("p out of range\n");
604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
605 INTELPllInvalid("m2 out of range\n");
606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
607 INTELPllInvalid("m1 out of range\n");
608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
609 INTELPllInvalid("m1 <= m2\n");
610 if (clock->m < limit->m.min || limit->m.max < clock->m)
611 INTELPllInvalid("m out of range\n");
612 if (clock->n < limit->n.min || limit->n.max < clock->n)
613 INTELPllInvalid("n out of range\n");
614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
615 INTELPllInvalid("vco out of range\n");
616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
620 INTELPllInvalid("dot out of range\n");
626 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
631 struct drm_device *dev = crtc->dev;
635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
641 if (intel_is_dual_link_lvds(dev))
642 clock.p2 = limit->p2.p2_fast;
644 clock.p2 = limit->p2.p2_slow;
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
649 clock.p2 = limit->p2.p2_fast;
652 memset(best_clock, 0, sizeof(*best_clock));
654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
667 intel_clock(dev, refclk, &clock);
668 if (!intel_PLL_is_valid(dev, limit,
672 clock.p != match_clock->p)
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
685 return (err != target);
689 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
693 struct drm_device *dev = crtc->dev;
697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
704 if (HAS_PCH_SPLIT(dev))
708 if (intel_is_dual_link_lvds(dev))
709 clock.p2 = limit->p2.p2_fast;
711 clock.p2 = limit->p2.p2_slow;
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
716 clock.p2 = limit->p2.p2_fast;
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
732 intel_clock(dev, refclk, &clock);
733 if (!intel_PLL_is_valid(dev, limit,
737 clock.p != match_clock->p)
740 this_err = abs(clock.dot - target);
741 if (this_err < err_most) {
755 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
759 struct drm_device *dev = crtc->dev;
762 if (target < 200000) {
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
780 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
782 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
787 if (target < 200000) {
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
808 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
819 dotclk = target * 1000;
822 fastclk = dotclk / (2*100);
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
850 if (absppm < bestppm - 10) {
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
876 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882 return intel_crtc->cpu_transcoder;
885 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
890 frame = I915_READ(frame_reg);
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
897 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @pipe: pipe to wait for
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
904 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
906 struct drm_i915_private *dev_priv = dev->dev_private;
907 int pipestat_reg = PIPESTAT(pipe);
909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
930 /* Wait for vblank interrupt bit to set */
931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
934 DRM_DEBUG_KMS("vblank wait timed out\n");
938 * intel_wait_for_pipe_off - wait for pipe to turn off
940 * @pipe: pipe to wait for
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
947 * wait for the pipe register state bit to turn off
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
954 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
956 struct drm_i915_private *dev_priv = dev->dev_private;
957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
960 if (INTEL_INFO(dev)->gen >= 4) {
961 int reg = PIPECONF(cpu_transcoder);
963 /* Wait for the Pipe State to go off */
964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
966 WARN(1, "pipe_off wait timed out\n");
968 u32 last_line, line_mask;
969 int reg = PIPEDSL(pipe);
970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
973 line_mask = DSL_LINEMASK_GEN2;
975 line_mask = DSL_LINEMASK_GEN3;
977 /* Wait for the display line to settle */
979 last_line = I915_READ(reg) & line_mask;
981 } while (((I915_READ(reg) & line_mask) != last_line) &&
982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
984 WARN(1, "pipe_off wait timed out\n");
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
993 * Returns true if @port is connected, false otherwise.
995 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1003 bit = SDE_PORTB_HOTPLUG;
1006 bit = SDE_PORTC_HOTPLUG;
1009 bit = SDE_PORTD_HOTPLUG;
1015 switch(port->port) {
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1030 return I915_READ(SDEISR) & bit;
1033 static const char *state_string(bool enabled)
1035 return enabled ? "on" : "off";
1038 /* Only for pre-ILK configs */
1039 static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1053 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1057 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1099 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1125 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1128 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1142 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1156 if (HAS_DDI(dev_priv->dev))
1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1164 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1175 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1178 int pp_reg, lvds_reg;
1180 enum pipe panel_pipe = PIPE_A;
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1187 pp_reg = PP_CONTROL;
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
1204 void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1217 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1221 reg = PIPECONF(cpu_transcoder);
1222 val = I915_READ(reg);
1223 cur_state = !!(val & PIPECONF_ENABLE);
1226 WARN(cur_state != state,
1227 "pipe %c assertion failure (expected %s, current %s)\n",
1228 pipe_name(pipe), state_string(state), state_string(cur_state));
1231 static void assert_plane(struct drm_i915_private *dev_priv,
1232 enum plane plane, bool state)
1238 reg = DSPCNTR(plane);
1239 val = I915_READ(reg);
1240 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241 WARN(cur_state != state,
1242 "plane %c assertion failure (expected %s, current %s)\n",
1243 plane_name(plane), state_string(state), state_string(cur_state));
1246 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1249 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1256 /* Planes are fixed to pipes on ILK+ */
1257 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
1260 WARN((val & DISPLAY_PLANE_ENABLE),
1261 "plane %c assertion failure, should be disabled but not\n",
1266 /* Need to check both planes against the pipe */
1267 for (i = 0; i < 2; i++) {
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
1278 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1283 if (HAS_PCH_LPT(dev_priv->dev)) {
1284 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1288 val = I915_READ(PCH_DREF_CONTROL);
1289 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290 DREF_SUPERSPREAD_SOURCE_MASK));
1291 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1294 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1301 reg = TRANSCONF(pipe);
1302 val = I915_READ(reg);
1303 enabled = !!(val & TRANS_ENABLE);
1305 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1309 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, u32 port_sel, u32 val)
1312 if ((val & DP_PORT_EN) == 0)
1315 if (HAS_PCH_CPT(dev_priv->dev)) {
1316 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1330 if ((val & PORT_ENABLE) == 0)
1333 if (HAS_PCH_CPT(dev_priv->dev)) {
1334 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1337 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1343 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344 enum pipe pipe, u32 val)
1346 if ((val & LVDS_PORT_EN) == 0)
1349 if (HAS_PCH_CPT(dev_priv->dev)) {
1350 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1353 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1359 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1362 if ((val & ADPA_DAC_ENABLE) == 0)
1364 if (HAS_PCH_CPT(dev_priv->dev)) {
1365 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1368 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1374 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1375 enum pipe pipe, int reg, u32 port_sel)
1377 u32 val = I915_READ(reg);
1378 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1379 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1380 reg, pipe_name(pipe));
1382 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383 && (val & DP_PIPEB_SELECT),
1384 "IBX PCH dp port still using transcoder B\n");
1387 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, int reg)
1390 u32 val = I915_READ(reg);
1391 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1392 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1393 reg, pipe_name(pipe));
1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396 && (val & SDVO_PIPE_B_SELECT),
1397 "IBX PCH hdmi port still using transcoder B\n");
1400 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1406 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1411 val = I915_READ(reg);
1412 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1413 "PCH VGA enabled on transcoder %c, should be disabled\n",
1417 val = I915_READ(reg);
1418 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1419 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1422 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1428 * intel_enable_pll - enable a PLL
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1432 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1433 * make sure the PLL reg is writable first though, since the panel write
1434 * protect mechanism may be enabled.
1436 * Note! This is for pre-ILK only.
1438 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1440 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1445 /* No really, not for ILK+ */
1446 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1448 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450 assert_panel_unlocked(dev_priv, pipe);
1453 val = I915_READ(reg);
1454 val |= DPLL_VCO_ENABLE;
1456 /* We do this three times for luck */
1457 I915_WRITE(reg, val);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1462 udelay(150); /* wait for warmup */
1463 I915_WRITE(reg, val);
1465 udelay(150); /* wait for warmup */
1469 * intel_disable_pll - disable a PLL
1470 * @dev_priv: i915 private structure
1471 * @pipe: pipe PLL to disable
1473 * Disable the PLL for @pipe, making sure the pipe is off first.
1475 * Note! This is for pre-ILK only.
1477 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1482 /* Don't disable pipe A or pipe A PLLs if needed */
1483 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1486 /* Make sure the pipe isn't still relying on us */
1487 assert_pipe_disabled(dev_priv, pipe);
1490 val = I915_READ(reg);
1491 val &= ~DPLL_VCO_ENABLE;
1492 I915_WRITE(reg, val);
1498 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499 enum intel_sbi_destination destination)
1503 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1505 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1507 DRM_ERROR("timeout waiting for SBI to become ready\n");
1511 I915_WRITE(SBI_ADDR, (reg << 16));
1512 I915_WRITE(SBI_DATA, value);
1514 if (destination == SBI_ICLK)
1515 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1517 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1520 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1522 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1528 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529 enum intel_sbi_destination destination)
1532 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1534 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1536 DRM_ERROR("timeout waiting for SBI to become ready\n");
1540 I915_WRITE(SBI_ADDR, (reg << 16));
1542 if (destination == SBI_ICLK)
1543 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1545 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1548 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1550 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1554 return I915_READ(SBI_DATA);
1558 * ironlake_enable_pch_pll - enable PCH PLL
1559 * @dev_priv: i915 private structure
1560 * @pipe: pipe PLL to enable
1562 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563 * drives the transcoder clock.
1565 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1567 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568 struct intel_pch_pll *pll;
1572 /* PCH PLLs only available on ILK, SNB and IVB */
1573 BUG_ON(dev_priv->info->gen < 5);
1574 pll = intel_crtc->pch_pll;
1578 if (WARN_ON(pll->refcount == 0))
1581 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582 pll->pll_reg, pll->active, pll->on,
1583 intel_crtc->base.base.id);
1585 /* PCH refclock must be enabled first */
1586 assert_pch_refclk_enabled(dev_priv);
1588 if (pll->active++ && pll->on) {
1589 assert_pch_pll_enabled(dev_priv, pll, NULL);
1593 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1596 val = I915_READ(reg);
1597 val |= DPLL_VCO_ENABLE;
1598 I915_WRITE(reg, val);
1605 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1607 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1612 /* PCH only available on ILK+ */
1613 BUG_ON(dev_priv->info->gen < 5);
1617 if (WARN_ON(pll->refcount == 0))
1620 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621 pll->pll_reg, pll->active, pll->on,
1622 intel_crtc->base.base.id);
1624 if (WARN_ON(pll->active == 0)) {
1625 assert_pch_pll_disabled(dev_priv, pll, NULL);
1629 if (--pll->active) {
1630 assert_pch_pll_enabled(dev_priv, pll, NULL);
1634 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1636 /* Make sure transcoder isn't still depending on us */
1637 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1640 val = I915_READ(reg);
1641 val &= ~DPLL_VCO_ENABLE;
1642 I915_WRITE(reg, val);
1649 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1652 struct drm_device *dev = dev_priv->dev;
1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654 uint32_t reg, val, pipeconf_val;
1656 /* PCH only available on ILK+ */
1657 BUG_ON(dev_priv->info->gen < 5);
1659 /* Make sure PCH DPLL is enabled */
1660 assert_pch_pll_enabled(dev_priv,
1661 to_intel_crtc(crtc)->pch_pll,
1662 to_intel_crtc(crtc));
1664 /* FDI must be feeding us bits for PCH ports */
1665 assert_fdi_tx_enabled(dev_priv, pipe);
1666 assert_fdi_rx_enabled(dev_priv, pipe);
1668 if (HAS_PCH_CPT(dev)) {
1669 /* Workaround: Set the timing override bit before enabling the
1670 * pch transcoder. */
1671 reg = TRANS_CHICKEN2(pipe);
1672 val = I915_READ(reg);
1673 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674 I915_WRITE(reg, val);
1677 reg = TRANSCONF(pipe);
1678 val = I915_READ(reg);
1679 pipeconf_val = I915_READ(PIPECONF(pipe));
1681 if (HAS_PCH_IBX(dev_priv->dev)) {
1683 * make the BPC in transcoder be consistent with
1684 * that in pipeconf reg.
1686 val &= ~PIPECONF_BPC_MASK;
1687 val |= pipeconf_val & PIPECONF_BPC_MASK;
1690 val &= ~TRANS_INTERLACE_MASK;
1691 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1692 if (HAS_PCH_IBX(dev_priv->dev) &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694 val |= TRANS_LEGACY_INTERLACED_ILK;
1696 val |= TRANS_INTERLACED;
1698 val |= TRANS_PROGRESSIVE;
1700 I915_WRITE(reg, val | TRANS_ENABLE);
1701 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1705 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1706 enum transcoder cpu_transcoder)
1708 u32 val, pipeconf_val;
1710 /* PCH only available on ILK+ */
1711 BUG_ON(dev_priv->info->gen < 5);
1713 /* FDI must be feeding us bits for PCH ports */
1714 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1715 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1717 /* Workaround: set timing override bit. */
1718 val = I915_READ(_TRANSA_CHICKEN2);
1719 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1720 I915_WRITE(_TRANSA_CHICKEN2, val);
1723 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1725 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726 PIPECONF_INTERLACED_ILK)
1727 val |= TRANS_INTERLACED;
1729 val |= TRANS_PROGRESSIVE;
1731 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1732 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733 DRM_ERROR("Failed to enable PCH transcoder\n");
1736 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1739 struct drm_device *dev = dev_priv->dev;
1742 /* FDI relies on the transcoder */
1743 assert_fdi_tx_disabled(dev_priv, pipe);
1744 assert_fdi_rx_disabled(dev_priv, pipe);
1746 /* Ports must be off as well */
1747 assert_pch_ports_disabled(dev_priv, pipe);
1749 reg = TRANSCONF(pipe);
1750 val = I915_READ(reg);
1751 val &= ~TRANS_ENABLE;
1752 I915_WRITE(reg, val);
1753 /* wait for PCH transcoder off, transcoder state */
1754 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1755 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1757 if (!HAS_PCH_IBX(dev)) {
1758 /* Workaround: Clear the timing override chicken bit again. */
1759 reg = TRANS_CHICKEN2(pipe);
1760 val = I915_READ(reg);
1761 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762 I915_WRITE(reg, val);
1766 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1770 val = I915_READ(_TRANSACONF);
1771 val &= ~TRANS_ENABLE;
1772 I915_WRITE(_TRANSACONF, val);
1773 /* wait for PCH transcoder off, transcoder state */
1774 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775 DRM_ERROR("Failed to disable PCH transcoder\n");
1777 /* Workaround: clear timing override bit. */
1778 val = I915_READ(_TRANSA_CHICKEN2);
1779 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1780 I915_WRITE(_TRANSA_CHICKEN2, val);
1784 * intel_enable_pipe - enable a pipe, asserting requirements
1785 * @dev_priv: i915 private structure
1786 * @pipe: pipe to enable
1787 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1789 * Enable @pipe, making sure that various hardware specific requirements
1790 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1792 * @pipe should be %PIPE_A or %PIPE_B.
1794 * Will wait until the pipe is actually running (i.e. first vblank) before
1797 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1800 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1802 enum pipe pch_transcoder;
1806 if (HAS_PCH_LPT(dev_priv->dev))
1807 pch_transcoder = TRANSCODER_A;
1809 pch_transcoder = pipe;
1812 * A pipe without a PLL won't actually be able to drive bits from
1813 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1816 if (!HAS_PCH_SPLIT(dev_priv->dev))
1817 assert_pll_enabled(dev_priv, pipe);
1820 /* if driving the PCH, we need FDI enabled */
1821 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1822 assert_fdi_tx_pll_enabled(dev_priv,
1823 (enum pipe) cpu_transcoder);
1825 /* FIXME: assert CPU port conditions for SNB+ */
1828 reg = PIPECONF(cpu_transcoder);
1829 val = I915_READ(reg);
1830 if (val & PIPECONF_ENABLE)
1833 I915_WRITE(reg, val | PIPECONF_ENABLE);
1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1838 * intel_disable_pipe - disable a pipe, asserting requirements
1839 * @dev_priv: i915 private structure
1840 * @pipe: pipe to disable
1842 * Disable @pipe, making sure that various hardware specific requirements
1843 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1845 * @pipe should be %PIPE_A or %PIPE_B.
1847 * Will wait until the pipe has shut down before returning.
1849 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1852 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1858 * Make sure planes won't keep trying to pump pixels to us,
1859 * or we might hang the display.
1861 assert_planes_disabled(dev_priv, pipe);
1863 /* Don't disable pipe A or pipe A PLLs if needed */
1864 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1867 reg = PIPECONF(cpu_transcoder);
1868 val = I915_READ(reg);
1869 if ((val & PIPECONF_ENABLE) == 0)
1872 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1873 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1877 * Plane regs are double buffered, going from enabled->disabled needs a
1878 * trigger in order to latch. The display address reg provides this.
1880 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1883 if (dev_priv->info->gen >= 4)
1884 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1886 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1890 * intel_enable_plane - enable a display plane on a given pipe
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to enable
1893 * @pipe: pipe being fed
1895 * Enable @plane on @pipe, making sure that @pipe is running first.
1897 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1903 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904 assert_pipe_enabled(dev_priv, pipe);
1906 reg = DSPCNTR(plane);
1907 val = I915_READ(reg);
1908 if (val & DISPLAY_PLANE_ENABLE)
1911 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1912 intel_flush_display_plane(dev_priv, plane);
1913 intel_wait_for_vblank(dev_priv->dev, pipe);
1917 * intel_disable_plane - disable a display plane
1918 * @dev_priv: i915 private structure
1919 * @plane: plane to disable
1920 * @pipe: pipe consuming the data
1922 * Disable @plane; should be an independent operation.
1924 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925 enum plane plane, enum pipe pipe)
1930 reg = DSPCNTR(plane);
1931 val = I915_READ(reg);
1932 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1935 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1936 intel_flush_display_plane(dev_priv, plane);
1937 intel_wait_for_vblank(dev_priv->dev, pipe);
1941 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1942 struct drm_i915_gem_object *obj,
1943 struct intel_ring_buffer *pipelined)
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1949 switch (obj->tiling_mode) {
1950 case I915_TILING_NONE:
1951 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952 alignment = 128 * 1024;
1953 else if (INTEL_INFO(dev)->gen >= 4)
1954 alignment = 4 * 1024;
1956 alignment = 64 * 1024;
1959 /* pin() will align the object as required by fence */
1963 /* FIXME: Is this true? */
1964 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1970 dev_priv->mm.interruptible = false;
1971 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1973 goto err_interruptible;
1975 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976 * fence, whereas 965+ only requires a fence if using
1977 * framebuffer compression. For simplicity, we always install
1978 * a fence as the cost is not that onerous.
1980 ret = i915_gem_object_get_fence(obj);
1984 i915_gem_object_pin_fence(obj);
1986 dev_priv->mm.interruptible = true;
1990 i915_gem_object_unpin(obj);
1992 dev_priv->mm.interruptible = true;
1996 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1998 i915_gem_object_unpin_fence(obj);
1999 i915_gem_object_unpin(obj);
2002 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003 * is assumed to be a power-of-two. */
2004 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2008 int tile_rows, tiles;
2012 tiles = *x / (512/bpp);
2015 return tile_rows * pitch * 8 + tiles * 4096;
2018 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
2025 struct drm_i915_gem_object *obj;
2026 int plane = intel_crtc->plane;
2027 unsigned long linear_offset;
2036 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2040 intel_fb = to_intel_framebuffer(fb);
2041 obj = intel_fb->obj;
2043 reg = DSPCNTR(plane);
2044 dspcntr = I915_READ(reg);
2045 /* Mask out pixel format bits in case we change it */
2046 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2047 switch (fb->pixel_format) {
2049 dspcntr |= DISPPLANE_8BPP;
2051 case DRM_FORMAT_XRGB1555:
2052 case DRM_FORMAT_ARGB1555:
2053 dspcntr |= DISPPLANE_BGRX555;
2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
2075 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2079 if (INTEL_INFO(dev)->gen >= 4) {
2080 if (obj->tiling_mode != I915_TILING_NONE)
2081 dspcntr |= DISPPLANE_TILED;
2083 dspcntr &= ~DISPPLANE_TILED;
2086 I915_WRITE(reg, dspcntr);
2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2090 if (INTEL_INFO(dev)->gen >= 4) {
2091 intel_crtc->dspaddr_offset =
2092 intel_gen4_compute_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2095 linear_offset -= intel_crtc->dspaddr_offset;
2097 intel_crtc->dspaddr_offset = linear_offset;
2100 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2103 if (INTEL_INFO(dev)->gen >= 4) {
2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 obj->gtt_offset + intel_crtc->dspaddr_offset);
2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
2109 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2115 static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
2124 unsigned long linear_offset;
2134 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2145 switch (fb->pixel_format) {
2147 dspcntr |= DISPPLANE_8BPP;
2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
2169 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2173 if (obj->tiling_mode != I915_TILING_NONE)
2174 dspcntr |= DISPPLANE_TILED;
2176 dspcntr &= ~DISPPLANE_TILED;
2179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2181 I915_WRITE(reg, dspcntr);
2183 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2184 intel_crtc->dspaddr_offset =
2185 intel_gen4_compute_offset_xtiled(&x, &y,
2186 fb->bits_per_pixel / 8,
2188 linear_offset -= intel_crtc->dspaddr_offset;
2190 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2192 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2193 I915_MODIFY_DISPBASE(DSPSURF(plane),
2194 obj->gtt_offset + intel_crtc->dspaddr_offset);
2195 if (IS_HASWELL(dev)) {
2196 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2198 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199 I915_WRITE(DSPLINOFF(plane), linear_offset);
2206 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2208 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209 int x, int y, enum mode_set_atomic state)
2211 struct drm_device *dev = crtc->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2214 if (dev_priv->display.disable_fbc)
2215 dev_priv->display.disable_fbc(dev);
2216 intel_increase_pllclock(crtc);
2218 return dev_priv->display.update_plane(crtc, fb, x, y);
2222 intel_finish_fb(struct drm_framebuffer *old_fb)
2224 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2226 bool was_interruptible = dev_priv->mm.interruptible;
2229 /* Big Hammer, we also need to ensure that any pending
2230 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2231 * current scanout is retired before unpinning the old
2234 * This should only fail upon a hung GPU, in which case we
2235 * can safely continue.
2237 dev_priv->mm.interruptible = false;
2238 ret = i915_gem_object_finish_gpu(obj);
2239 dev_priv->mm.interruptible = was_interruptible;
2244 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246 struct drm_device *dev = crtc->dev;
2247 struct drm_i915_master_private *master_priv;
2248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250 if (!dev->primary->master)
2253 master_priv = dev->primary->master->driver_priv;
2254 if (!master_priv->sarea_priv)
2257 switch (intel_crtc->pipe) {
2259 master_priv->sarea_priv->pipeA_x = x;
2260 master_priv->sarea_priv->pipeA_y = y;
2263 master_priv->sarea_priv->pipeB_x = x;
2264 master_priv->sarea_priv->pipeB_y = y;
2272 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2273 struct drm_framebuffer *fb)
2275 struct drm_device *dev = crtc->dev;
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2278 struct drm_framebuffer *old_fb;
2283 DRM_ERROR("No FB bound\n");
2287 if(intel_crtc->plane > dev_priv->num_pipe) {
2288 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2290 dev_priv->num_pipe);
2294 mutex_lock(&dev->struct_mutex);
2295 ret = intel_pin_and_fence_fb_obj(dev,
2296 to_intel_framebuffer(fb)->obj,
2299 mutex_unlock(&dev->struct_mutex);
2300 DRM_ERROR("pin & fence failed\n");
2305 intel_finish_fb(crtc->fb);
2307 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2309 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2310 mutex_unlock(&dev->struct_mutex);
2311 DRM_ERROR("failed to update base address\n");
2321 intel_wait_for_vblank(dev, intel_crtc->pipe);
2322 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2325 intel_update_fbc(dev);
2326 mutex_unlock(&dev->struct_mutex);
2328 intel_crtc_update_sarea_pos(crtc, x, y);
2333 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2335 struct drm_device *dev = crtc->dev;
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338 int pipe = intel_crtc->pipe;
2341 /* enable normal train */
2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
2344 if (IS_IVYBRIDGE(dev)) {
2345 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2346 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2348 temp &= ~FDI_LINK_TRAIN_NONE;
2349 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2351 I915_WRITE(reg, temp);
2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
2355 if (HAS_PCH_CPT(dev)) {
2356 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2359 temp &= ~FDI_LINK_TRAIN_NONE;
2360 temp |= FDI_LINK_TRAIN_NONE;
2362 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2364 /* wait one idle pattern time */
2368 /* IVB wants error correction enabled */
2369 if (IS_IVYBRIDGE(dev))
2370 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2371 FDI_FE_ERRC_ENABLE);
2374 static void ivb_modeset_global_resources(struct drm_device *dev)
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 struct intel_crtc *pipe_B_crtc =
2378 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2379 struct intel_crtc *pipe_C_crtc =
2380 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2383 /* When everything is off disable fdi C so that we could enable fdi B
2384 * with all lanes. XXX: This misses the case where a pipe is not using
2385 * any pch resources and so doesn't need any fdi lanes. */
2386 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2387 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2390 temp = I915_READ(SOUTH_CHICKEN1);
2391 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393 I915_WRITE(SOUTH_CHICKEN1, temp);
2397 /* The FDI link training functions for ILK/Ibexpeak. */
2398 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
2404 int plane = intel_crtc->plane;
2405 u32 reg, temp, tries;
2407 /* FDI needs bits from pipe & plane first */
2408 assert_pipe_enabled(dev_priv, pipe);
2409 assert_plane_enabled(dev_priv, plane);
2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
2417 I915_WRITE(reg, temp);
2421 /* enable CPU FDI TX and PCH FDI RX */
2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
2425 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1;
2428 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2439 /* Ironlake workaround, enable clock pointer after FDI enable*/
2440 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442 FDI_RX_PHASE_SYNC_POINTER_EN);
2444 reg = FDI_RX_IIR(pipe);
2445 for (tries = 0; tries < 5; tries++) {
2446 temp = I915_READ(reg);
2447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2449 if ((temp & FDI_RX_BIT_LOCK)) {
2450 DRM_DEBUG_KMS("FDI train 1 done.\n");
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2456 DRM_ERROR("FDI train 1 fail!\n");
2459 reg = FDI_TX_CTL(pipe);
2460 temp = I915_READ(reg);
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_2;
2463 I915_WRITE(reg, temp);
2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 I915_WRITE(reg, temp);
2474 reg = FDI_RX_IIR(pipe);
2475 for (tries = 0; tries < 5; tries++) {
2476 temp = I915_READ(reg);
2477 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2479 if (temp & FDI_RX_SYMBOL_LOCK) {
2480 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2481 DRM_DEBUG_KMS("FDI train 2 done.\n");
2486 DRM_ERROR("FDI train 2 fail!\n");
2488 DRM_DEBUG_KMS("FDI train done\n");
2492 static const int snb_b_fdi_train_param[] = {
2493 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2499 /* The FDI link training functions for SNB/Cougarpoint. */
2500 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2502 struct drm_device *dev = crtc->dev;
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505 int pipe = intel_crtc->pipe;
2506 u32 reg, temp, i, retry;
2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
2512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
2514 I915_WRITE(reg, temp);
2519 /* enable CPU FDI TX and PCH FDI RX */
2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
2523 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_1;
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2531 I915_WRITE(FDI_RX_MISC(pipe),
2532 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1;
2543 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2548 for (i = 0; i < 4; i++) {
2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
2553 I915_WRITE(reg, temp);
2558 for (retry = 0; retry < 5; retry++) {
2559 reg = FDI_RX_IIR(pipe);
2560 temp = I915_READ(reg);
2561 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562 if (temp & FDI_RX_BIT_LOCK) {
2563 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564 DRM_DEBUG_KMS("FDI train 1 done.\n");
2573 DRM_ERROR("FDI train 1 fail!\n");
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585 I915_WRITE(reg, temp);
2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_2;
2596 I915_WRITE(reg, temp);
2601 for (i = 0; i < 4; i++) {
2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
2606 I915_WRITE(reg, temp);
2611 for (retry = 0; retry < 5; retry++) {
2612 reg = FDI_RX_IIR(pipe);
2613 temp = I915_READ(reg);
2614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615 if (temp & FDI_RX_SYMBOL_LOCK) {
2616 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617 DRM_DEBUG_KMS("FDI train 2 done.\n");
2626 DRM_ERROR("FDI train 2 fail!\n");
2628 DRM_DEBUG_KMS("FDI train done.\n");
2631 /* Manual link training for Ivy Bridge A0 parts */
2632 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
2640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2642 reg = FDI_RX_IMR(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_RX_SYMBOL_LOCK;
2645 temp &= ~FDI_RX_BIT_LOCK;
2646 I915_WRITE(reg, temp);
2651 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652 I915_READ(FDI_RX_IIR(pipe)));
2654 /* enable CPU FDI TX and PCH FDI RX */
2655 reg = FDI_TX_CTL(pipe);
2656 temp = I915_READ(reg);
2658 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2659 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2663 temp |= FDI_COMPOSITE_SYNC;
2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2674 temp |= FDI_COMPOSITE_SYNC;
2675 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2680 for (i = 0; i < 4; i++) {
2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684 temp |= snb_b_fdi_train_param[i];
2685 I915_WRITE(reg, temp);
2690 reg = FDI_RX_IIR(pipe);
2691 temp = I915_READ(reg);
2692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2694 if (temp & FDI_RX_BIT_LOCK ||
2695 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2697 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2702 DRM_ERROR("FDI train 1 fail!\n");
2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711 I915_WRITE(reg, temp);
2713 reg = FDI_RX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717 I915_WRITE(reg, temp);
2722 for (i = 0; i < 4; i++) {
2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= snb_b_fdi_train_param[i];
2727 I915_WRITE(reg, temp);
2732 reg = FDI_RX_IIR(pipe);
2733 temp = I915_READ(reg);
2734 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2736 if (temp & FDI_RX_SYMBOL_LOCK) {
2737 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2738 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2743 DRM_ERROR("FDI train 2 fail!\n");
2745 DRM_DEBUG_KMS("FDI train done.\n");
2748 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2750 struct drm_device *dev = intel_crtc->base.dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 int pipe = intel_crtc->pipe;
2756 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 temp &= ~((0x7 << 19) | (0x7 << 16));
2760 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2761 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2762 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2767 /* Switch from Rawclk to PCDclk */
2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp | FDI_PCDCLK);
2774 /* Enable CPU FDI TX PLL, always on for Ironlake */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2785 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2787 struct drm_device *dev = intel_crtc->base.dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 int pipe = intel_crtc->pipe;
2792 /* Switch from PCDclk to Rawclk */
2793 reg = FDI_RX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2797 /* Disable CPU FDI TX PLL */
2798 reg = FDI_TX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2809 /* Wait for the clocks to turn off. */
2814 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2822 /* disable CPU FDI tx and PCH FDI rx */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 temp &= ~(0x7 << 16);
2831 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2832 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2837 /* Ironlake workaround, disable clock pointer after downing FDI */
2838 if (HAS_PCH_IBX(dev)) {
2839 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2842 /* still set train pattern 1 */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 I915_WRITE(reg, temp);
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if (HAS_PCH_CPT(dev)) {
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2855 temp &= ~FDI_LINK_TRAIN_NONE;
2856 temp |= FDI_LINK_TRAIN_PATTERN_1;
2858 /* BPC in FDI rx is consistent with that in PIPECONF */
2859 temp &= ~(0x07 << 16);
2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861 I915_WRITE(reg, temp);
2867 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2872 unsigned long flags;
2875 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2876 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2879 spin_lock_irqsave(&dev->event_lock, flags);
2880 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2881 spin_unlock_irqrestore(&dev->event_lock, flags);
2886 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2888 struct drm_device *dev = crtc->dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2891 if (crtc->fb == NULL)
2894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2896 wait_event(dev_priv->pending_flip_queue,
2897 !intel_crtc_has_pending_flip(crtc));
2899 mutex_lock(&dev->struct_mutex);
2900 intel_finish_fb(crtc->fb);
2901 mutex_unlock(&dev->struct_mutex);
2904 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2906 struct drm_device *dev = crtc->dev;
2907 struct intel_encoder *intel_encoder;
2910 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2911 * must be driven by its own crtc; no sharing is possible.
2913 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2914 switch (intel_encoder->type) {
2915 case INTEL_OUTPUT_EDP:
2916 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2925 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2927 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2930 /* Program iCLKIP clock to the desired frequency */
2931 static void lpt_program_iclkip(struct drm_crtc *crtc)
2933 struct drm_device *dev = crtc->dev;
2934 struct drm_i915_private *dev_priv = dev->dev_private;
2935 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2938 mutex_lock(&dev_priv->dpio_lock);
2940 /* It is necessary to ungate the pixclk gate prior to programming
2941 * the divisors, and gate it back when it is done.
2943 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2945 /* Disable SSCCTL */
2946 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2947 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2951 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2952 if (crtc->mode.clock == 20000) {
2957 /* The iCLK virtual clock root frequency is in MHz,
2958 * but the crtc->mode.clock in in KHz. To get the divisors,
2959 * it is necessary to divide one by another, so we
2960 * convert the virtual clock precision to KHz here for higher
2963 u32 iclk_virtual_root_freq = 172800 * 1000;
2964 u32 iclk_pi_range = 64;
2965 u32 desired_divisor, msb_divisor_value, pi_value;
2967 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2968 msb_divisor_value = desired_divisor / iclk_pi_range;
2969 pi_value = desired_divisor % iclk_pi_range;
2972 divsel = msb_divisor_value - 2;
2973 phaseinc = pi_value;
2976 /* This should not happen with any sane values */
2977 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2978 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2979 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2980 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2982 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2989 /* Program SSCDIVINTPHASE6 */
2990 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2991 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2992 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2993 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2994 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2995 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2996 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2997 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2999 /* Program SSCAUXDIV */
3000 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3001 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3002 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3003 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3005 /* Enable modulator and associated divider */
3006 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3007 temp &= ~SBI_SSCCTL_DISABLE;
3008 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3010 /* Wait for initialization time */
3013 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3015 mutex_unlock(&dev_priv->dpio_lock);
3019 * Enable PCH resources required for PCH ports:
3021 * - FDI training & RX/TX
3022 * - update transcoder timings
3023 * - DP transcoding bits
3026 static void ironlake_pch_enable(struct drm_crtc *crtc)
3028 struct drm_device *dev = crtc->dev;
3029 struct drm_i915_private *dev_priv = dev->dev_private;
3030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 int pipe = intel_crtc->pipe;
3034 assert_transcoder_disabled(dev_priv, pipe);
3036 /* Write the TU size bits before fdi link training, so that error
3037 * detection works. */
3038 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3039 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3041 /* For PCH output, training FDI link */
3042 dev_priv->display.fdi_link_train(crtc);
3044 /* XXX: pch pll's can be enabled any time before we enable the PCH
3045 * transcoder, and we actually should do this to not upset any PCH
3046 * transcoder that already use the clock when we share it.
3048 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3049 * unconditionally resets the pll - we need that to have the right LVDS
3050 * enable sequence. */
3051 ironlake_enable_pch_pll(intel_crtc);
3053 if (HAS_PCH_CPT(dev)) {
3056 temp = I915_READ(PCH_DPLL_SEL);
3060 temp |= TRANSA_DPLL_ENABLE;
3061 sel = TRANSA_DPLLB_SEL;
3064 temp |= TRANSB_DPLL_ENABLE;
3065 sel = TRANSB_DPLLB_SEL;
3068 temp |= TRANSC_DPLL_ENABLE;
3069 sel = TRANSC_DPLLB_SEL;
3072 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3076 I915_WRITE(PCH_DPLL_SEL, temp);
3079 /* set transcoder timing, panel must allow it */
3080 assert_panel_unlocked(dev_priv, pipe);
3081 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3082 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3083 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3085 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3086 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3087 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3088 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3090 intel_fdi_normal_train(crtc);
3092 /* For PCH DP, enable TRANS_DP_CTL */
3093 if (HAS_PCH_CPT(dev) &&
3094 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3095 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3096 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3097 reg = TRANS_DP_CTL(pipe);
3098 temp = I915_READ(reg);
3099 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3100 TRANS_DP_SYNC_MASK |
3102 temp |= (TRANS_DP_OUTPUT_ENABLE |
3103 TRANS_DP_ENH_FRAMING);
3104 temp |= bpc << 9; /* same format but at 11:9 */
3106 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3107 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3108 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3109 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3111 switch (intel_trans_dp_port_sel(crtc)) {
3113 temp |= TRANS_DP_PORT_SEL_B;
3116 temp |= TRANS_DP_PORT_SEL_C;
3119 temp |= TRANS_DP_PORT_SEL_D;
3125 I915_WRITE(reg, temp);
3128 ironlake_enable_pch_transcoder(dev_priv, pipe);
3131 static void lpt_pch_enable(struct drm_crtc *crtc)
3133 struct drm_device *dev = crtc->dev;
3134 struct drm_i915_private *dev_priv = dev->dev_private;
3135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3136 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3138 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3140 lpt_program_iclkip(crtc);
3142 /* Set transcoder timing. */
3143 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3144 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3145 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3147 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3148 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3149 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3150 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3152 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3155 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3157 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3162 if (pll->refcount == 0) {
3163 WARN(1, "bad PCH PLL refcount\n");
3168 intel_crtc->pch_pll = NULL;
3171 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3173 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3174 struct intel_pch_pll *pll;
3177 pll = intel_crtc->pch_pll;
3179 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3180 intel_crtc->base.base.id, pll->pll_reg);
3184 if (HAS_PCH_IBX(dev_priv->dev)) {
3185 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3186 i = intel_crtc->pipe;
3187 pll = &dev_priv->pch_plls[i];
3189 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3190 intel_crtc->base.base.id, pll->pll_reg);
3195 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3196 pll = &dev_priv->pch_plls[i];
3198 /* Only want to check enabled timings first */
3199 if (pll->refcount == 0)
3202 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3203 fp == I915_READ(pll->fp0_reg)) {
3204 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3205 intel_crtc->base.base.id,
3206 pll->pll_reg, pll->refcount, pll->active);
3212 /* Ok no matching timings, maybe there's a free one? */
3213 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3214 pll = &dev_priv->pch_plls[i];
3215 if (pll->refcount == 0) {
3216 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3217 intel_crtc->base.base.id, pll->pll_reg);
3225 intel_crtc->pch_pll = pll;
3227 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3228 prepare: /* separate function? */
3229 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3231 /* Wait for the clocks to stabilize before rewriting the regs */
3232 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3233 POSTING_READ(pll->pll_reg);
3236 I915_WRITE(pll->fp0_reg, fp);
3237 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3242 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3244 struct drm_i915_private *dev_priv = dev->dev_private;
3245 int dslreg = PIPEDSL(pipe);
3248 temp = I915_READ(dslreg);
3250 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3251 if (wait_for(I915_READ(dslreg) != temp, 5))
3252 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3256 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3258 struct drm_device *dev = crtc->dev;
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3261 struct intel_encoder *encoder;
3262 int pipe = intel_crtc->pipe;
3263 int plane = intel_crtc->plane;
3267 WARN_ON(!crtc->enabled);
3269 if (intel_crtc->active)
3272 intel_crtc->active = true;
3273 intel_update_watermarks(dev);
3275 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3276 temp = I915_READ(PCH_LVDS);
3277 if ((temp & LVDS_PORT_EN) == 0)
3278 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3281 is_pch_port = ironlake_crtc_driving_pch(crtc);
3284 /* Note: FDI PLL enabling _must_ be done before we enable the
3285 * cpu pipes, hence this is separate from all the other fdi/pch
3287 ironlake_fdi_pll_enable(intel_crtc);
3289 assert_fdi_tx_disabled(dev_priv, pipe);
3290 assert_fdi_rx_disabled(dev_priv, pipe);
3293 for_each_encoder_on_crtc(dev, crtc, encoder)
3294 if (encoder->pre_enable)
3295 encoder->pre_enable(encoder);
3297 /* Enable panel fitting for LVDS */
3298 if (dev_priv->pch_pf_size &&
3299 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3300 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3301 /* Force use of hard-coded filter coefficients
3302 * as some pre-programmed values are broken,
3305 if (IS_IVYBRIDGE(dev))
3306 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3307 PF_PIPE_SEL_IVB(pipe));
3309 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3310 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3311 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3315 * On ILK+ LUT must be loaded before the pipe is running but with
3318 intel_crtc_load_lut(crtc);
3320 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3321 intel_enable_plane(dev_priv, plane, pipe);
3324 ironlake_pch_enable(crtc);
3326 mutex_lock(&dev->struct_mutex);
3327 intel_update_fbc(dev);
3328 mutex_unlock(&dev->struct_mutex);
3330 intel_crtc_update_cursor(crtc, true);
3332 for_each_encoder_on_crtc(dev, crtc, encoder)
3333 encoder->enable(encoder);
3335 if (HAS_PCH_CPT(dev))
3336 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3339 * There seems to be a race in PCH platform hw (at least on some
3340 * outputs) where an enabled pipe still completes any pageflip right
3341 * away (as if the pipe is off) instead of waiting for vblank. As soon
3342 * as the first vblank happend, everything works as expected. Hence just
3343 * wait for one vblank before returning to avoid strange things
3346 intel_wait_for_vblank(dev, intel_crtc->pipe);
3349 static void haswell_crtc_enable(struct drm_crtc *crtc)
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354 struct intel_encoder *encoder;
3355 int pipe = intel_crtc->pipe;
3356 int plane = intel_crtc->plane;
3359 WARN_ON(!crtc->enabled);
3361 if (intel_crtc->active)
3364 intel_crtc->active = true;
3365 intel_update_watermarks(dev);
3367 is_pch_port = haswell_crtc_driving_pch(crtc);
3370 dev_priv->display.fdi_link_train(crtc);
3372 for_each_encoder_on_crtc(dev, crtc, encoder)
3373 if (encoder->pre_enable)
3374 encoder->pre_enable(encoder);
3376 intel_ddi_enable_pipe_clock(intel_crtc);
3378 /* Enable panel fitting for eDP */
3379 if (dev_priv->pch_pf_size &&
3380 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3381 /* Force use of hard-coded filter coefficients
3382 * as some pre-programmed values are broken,
3385 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3386 PF_PIPE_SEL_IVB(pipe));
3387 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3388 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3392 * On ILK+ LUT must be loaded before the pipe is running but with
3395 intel_crtc_load_lut(crtc);
3397 intel_ddi_set_pipe_settings(crtc);
3398 intel_ddi_enable_pipe_func(crtc);
3400 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3401 intel_enable_plane(dev_priv, plane, pipe);
3404 lpt_pch_enable(crtc);
3406 mutex_lock(&dev->struct_mutex);
3407 intel_update_fbc(dev);
3408 mutex_unlock(&dev->struct_mutex);
3410 intel_crtc_update_cursor(crtc, true);
3412 for_each_encoder_on_crtc(dev, crtc, encoder)
3413 encoder->enable(encoder);
3416 * There seems to be a race in PCH platform hw (at least on some
3417 * outputs) where an enabled pipe still completes any pageflip right
3418 * away (as if the pipe is off) instead of waiting for vblank. As soon
3419 * as the first vblank happend, everything works as expected. Hence just
3420 * wait for one vblank before returning to avoid strange things
3423 intel_wait_for_vblank(dev, intel_crtc->pipe);
3426 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3428 struct drm_device *dev = crtc->dev;
3429 struct drm_i915_private *dev_priv = dev->dev_private;
3430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3431 struct intel_encoder *encoder;
3432 int pipe = intel_crtc->pipe;
3433 int plane = intel_crtc->plane;
3437 if (!intel_crtc->active)
3440 for_each_encoder_on_crtc(dev, crtc, encoder)
3441 encoder->disable(encoder);
3443 intel_crtc_wait_for_pending_flips(crtc);
3444 drm_vblank_off(dev, pipe);
3445 intel_crtc_update_cursor(crtc, false);
3447 intel_disable_plane(dev_priv, plane, pipe);
3449 if (dev_priv->cfb_plane == plane)
3450 intel_disable_fbc(dev);
3452 intel_disable_pipe(dev_priv, pipe);
3455 I915_WRITE(PF_CTL(pipe), 0);
3456 I915_WRITE(PF_WIN_SZ(pipe), 0);
3458 for_each_encoder_on_crtc(dev, crtc, encoder)
3459 if (encoder->post_disable)
3460 encoder->post_disable(encoder);
3462 ironlake_fdi_disable(crtc);
3464 ironlake_disable_pch_transcoder(dev_priv, pipe);
3466 if (HAS_PCH_CPT(dev)) {
3467 /* disable TRANS_DP_CTL */
3468 reg = TRANS_DP_CTL(pipe);
3469 temp = I915_READ(reg);
3470 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3471 temp |= TRANS_DP_PORT_SEL_NONE;
3472 I915_WRITE(reg, temp);
3474 /* disable DPLL_SEL */
3475 temp = I915_READ(PCH_DPLL_SEL);
3478 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3481 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3484 /* C shares PLL A or B */
3485 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3490 I915_WRITE(PCH_DPLL_SEL, temp);
3493 /* disable PCH DPLL */
3494 intel_disable_pch_pll(intel_crtc);
3496 ironlake_fdi_pll_disable(intel_crtc);
3498 intel_crtc->active = false;
3499 intel_update_watermarks(dev);
3501 mutex_lock(&dev->struct_mutex);
3502 intel_update_fbc(dev);
3503 mutex_unlock(&dev->struct_mutex);
3506 static void haswell_crtc_disable(struct drm_crtc *crtc)
3508 struct drm_device *dev = crtc->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 struct intel_encoder *encoder;
3512 int pipe = intel_crtc->pipe;
3513 int plane = intel_crtc->plane;
3514 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3517 if (!intel_crtc->active)
3520 is_pch_port = haswell_crtc_driving_pch(crtc);
3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 encoder->disable(encoder);
3525 intel_crtc_wait_for_pending_flips(crtc);
3526 drm_vblank_off(dev, pipe);
3527 intel_crtc_update_cursor(crtc, false);
3529 intel_disable_plane(dev_priv, plane, pipe);
3531 if (dev_priv->cfb_plane == plane)
3532 intel_disable_fbc(dev);
3534 intel_disable_pipe(dev_priv, pipe);
3536 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3539 I915_WRITE(PF_CTL(pipe), 0);
3540 I915_WRITE(PF_WIN_SZ(pipe), 0);
3542 intel_ddi_disable_pipe_clock(intel_crtc);
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3549 lpt_disable_pch_transcoder(dev_priv);
3550 intel_ddi_fdi_disable(crtc);
3553 intel_crtc->active = false;
3554 intel_update_watermarks(dev);
3556 mutex_lock(&dev->struct_mutex);
3557 intel_update_fbc(dev);
3558 mutex_unlock(&dev->struct_mutex);
3561 static void ironlake_crtc_off(struct drm_crtc *crtc)
3563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564 intel_put_pch_pll(intel_crtc);
3567 static void haswell_crtc_off(struct drm_crtc *crtc)
3569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3572 * start using it. */
3573 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3575 intel_ddi_put_crtc_pll(crtc);
3578 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3580 if (!enable && intel_crtc->overlay) {
3581 struct drm_device *dev = intel_crtc->base.dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3584 mutex_lock(&dev->struct_mutex);
3585 dev_priv->mm.interruptible = false;
3586 (void) intel_overlay_switch_off(intel_crtc->overlay);
3587 dev_priv->mm.interruptible = true;
3588 mutex_unlock(&dev->struct_mutex);
3591 /* Let userspace switch the overlay on again. In most cases userspace
3592 * has to recompute where to put it anyway.
3596 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3598 struct drm_device *dev = crtc->dev;
3599 struct drm_i915_private *dev_priv = dev->dev_private;
3600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3601 struct intel_encoder *encoder;
3602 int pipe = intel_crtc->pipe;
3603 int plane = intel_crtc->plane;
3605 WARN_ON(!crtc->enabled);
3607 if (intel_crtc->active)
3610 intel_crtc->active = true;
3611 intel_update_watermarks(dev);
3613 intel_enable_pll(dev_priv, pipe);
3615 for_each_encoder_on_crtc(dev, crtc, encoder)
3616 if (encoder->pre_enable)
3617 encoder->pre_enable(encoder);
3619 intel_enable_pipe(dev_priv, pipe, false);
3620 intel_enable_plane(dev_priv, plane, pipe);
3622 intel_crtc_load_lut(crtc);
3623 intel_update_fbc(dev);
3625 /* Give the overlay scaler a chance to enable if it's on this pipe */
3626 intel_crtc_dpms_overlay(intel_crtc, true);
3627 intel_crtc_update_cursor(crtc, true);
3629 for_each_encoder_on_crtc(dev, crtc, encoder)
3630 encoder->enable(encoder);
3633 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3635 struct drm_device *dev = crtc->dev;
3636 struct drm_i915_private *dev_priv = dev->dev_private;
3637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638 struct intel_encoder *encoder;
3639 int pipe = intel_crtc->pipe;
3640 int plane = intel_crtc->plane;
3644 if (!intel_crtc->active)
3647 for_each_encoder_on_crtc(dev, crtc, encoder)
3648 encoder->disable(encoder);
3650 /* Give the overlay scaler a chance to disable if it's on this pipe */
3651 intel_crtc_wait_for_pending_flips(crtc);
3652 drm_vblank_off(dev, pipe);
3653 intel_crtc_dpms_overlay(intel_crtc, false);
3654 intel_crtc_update_cursor(crtc, false);
3656 if (dev_priv->cfb_plane == plane)
3657 intel_disable_fbc(dev);
3659 intel_disable_plane(dev_priv, plane, pipe);
3660 intel_disable_pipe(dev_priv, pipe);
3662 /* Disable pannel fitter if it is on this pipe. */
3663 pctl = I915_READ(PFIT_CONTROL);
3664 if ((pctl & PFIT_ENABLE) &&
3665 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3666 I915_WRITE(PFIT_CONTROL, 0);
3668 intel_disable_pll(dev_priv, pipe);
3670 intel_crtc->active = false;
3671 intel_update_fbc(dev);
3672 intel_update_watermarks(dev);
3675 static void i9xx_crtc_off(struct drm_crtc *crtc)
3679 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3682 struct drm_device *dev = crtc->dev;
3683 struct drm_i915_master_private *master_priv;
3684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3685 int pipe = intel_crtc->pipe;
3687 if (!dev->primary->master)
3690 master_priv = dev->primary->master->driver_priv;
3691 if (!master_priv->sarea_priv)
3696 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3697 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3700 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3701 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3704 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3710 * Sets the power management mode of the pipe and plane.
3712 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3714 struct drm_device *dev = crtc->dev;
3715 struct drm_i915_private *dev_priv = dev->dev_private;
3716 struct intel_encoder *intel_encoder;
3717 bool enable = false;
3719 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3720 enable |= intel_encoder->connectors_active;
3723 dev_priv->display.crtc_enable(crtc);
3725 dev_priv->display.crtc_disable(crtc);
3727 intel_crtc_update_sarea(crtc, enable);
3730 static void intel_crtc_noop(struct drm_crtc *crtc)
3734 static void intel_crtc_disable(struct drm_crtc *crtc)
3736 struct drm_device *dev = crtc->dev;
3737 struct drm_connector *connector;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741 /* crtc should still be enabled when we disable it. */
3742 WARN_ON(!crtc->enabled);
3744 intel_crtc->eld_vld = false;
3745 dev_priv->display.crtc_disable(crtc);
3746 intel_crtc_update_sarea(crtc, false);
3747 dev_priv->display.off(crtc);
3749 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3750 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3753 mutex_lock(&dev->struct_mutex);
3754 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3755 mutex_unlock(&dev->struct_mutex);
3759 /* Update computed state. */
3760 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3761 if (!connector->encoder || !connector->encoder->crtc)
3764 if (connector->encoder->crtc != crtc)
3767 connector->dpms = DRM_MODE_DPMS_OFF;
3768 to_intel_encoder(connector->encoder)->connectors_active = false;
3772 void intel_modeset_disable(struct drm_device *dev)
3774 struct drm_crtc *crtc;
3776 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3778 intel_crtc_disable(crtc);
3782 void intel_encoder_noop(struct drm_encoder *encoder)
3786 void intel_encoder_destroy(struct drm_encoder *encoder)
3788 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3790 drm_encoder_cleanup(encoder);
3791 kfree(intel_encoder);
3794 /* Simple dpms helper for encodres with just one connector, no cloning and only
3795 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3796 * state of the entire output pipe. */
3797 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3799 if (mode == DRM_MODE_DPMS_ON) {
3800 encoder->connectors_active = true;
3802 intel_crtc_update_dpms(encoder->base.crtc);
3804 encoder->connectors_active = false;
3806 intel_crtc_update_dpms(encoder->base.crtc);
3810 /* Cross check the actual hw state with our own modeset state tracking (and it's
3811 * internal consistency). */
3812 static void intel_connector_check_state(struct intel_connector *connector)
3814 if (connector->get_hw_state(connector)) {
3815 struct intel_encoder *encoder = connector->encoder;
3816 struct drm_crtc *crtc;
3817 bool encoder_enabled;
3820 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3821 connector->base.base.id,
3822 drm_get_connector_name(&connector->base));
3824 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3825 "wrong connector dpms state\n");
3826 WARN(connector->base.encoder != &encoder->base,
3827 "active connector not linked to encoder\n");
3828 WARN(!encoder->connectors_active,
3829 "encoder->connectors_active not set\n");
3831 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3832 WARN(!encoder_enabled, "encoder not enabled\n");
3833 if (WARN_ON(!encoder->base.crtc))
3836 crtc = encoder->base.crtc;
3838 WARN(!crtc->enabled, "crtc not enabled\n");
3839 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3840 WARN(pipe != to_intel_crtc(crtc)->pipe,
3841 "encoder active on the wrong pipe\n");
3845 /* Even simpler default implementation, if there's really no special case to
3847 void intel_connector_dpms(struct drm_connector *connector, int mode)
3849 struct intel_encoder *encoder = intel_attached_encoder(connector);
3851 /* All the simple cases only support two dpms states. */
3852 if (mode != DRM_MODE_DPMS_ON)
3853 mode = DRM_MODE_DPMS_OFF;
3855 if (mode == connector->dpms)
3858 connector->dpms = mode;
3860 /* Only need to change hw state when actually enabled */
3861 if (encoder->base.crtc)
3862 intel_encoder_dpms(encoder, mode);
3864 WARN_ON(encoder->connectors_active != false);
3866 intel_modeset_check_state(connector->dev);
3869 /* Simple connector->get_hw_state implementation for encoders that support only
3870 * one connector and no cloning and hence the encoder state determines the state
3871 * of the connector. */
3872 bool intel_connector_get_hw_state(struct intel_connector *connector)
3875 struct intel_encoder *encoder = connector->encoder;
3877 return encoder->get_hw_state(encoder, &pipe);
3880 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3881 const struct drm_display_mode *mode,
3882 struct drm_display_mode *adjusted_mode)
3884 struct drm_device *dev = crtc->dev;
3886 if (HAS_PCH_SPLIT(dev)) {
3887 /* FDI link clock is fixed at 2.7G */
3888 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3892 /* All interlaced capable intel hw wants timings in frames. Note though
3893 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3894 * timings, so we need to be careful not to clobber these.*/
3895 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3896 drm_mode_set_crtcinfo(adjusted_mode, 0);
3898 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3899 * with a hsync front porch of 0.
3901 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3902 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3908 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3910 return 400000; /* FIXME */
3913 static int i945_get_display_clock_speed(struct drm_device *dev)
3918 static int i915_get_display_clock_speed(struct drm_device *dev)
3923 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3928 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3932 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3934 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3937 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3938 case GC_DISPLAY_CLOCK_333_MHZ:
3941 case GC_DISPLAY_CLOCK_190_200_MHZ:
3947 static int i865_get_display_clock_speed(struct drm_device *dev)
3952 static int i855_get_display_clock_speed(struct drm_device *dev)
3955 /* Assume that the hardware is in the high speed state. This
3956 * should be the default.
3958 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3959 case GC_CLOCK_133_200:
3960 case GC_CLOCK_100_200:
3962 case GC_CLOCK_166_250:
3964 case GC_CLOCK_100_133:
3968 /* Shouldn't happen */
3972 static int i830_get_display_clock_speed(struct drm_device *dev)
3978 intel_reduce_ratio(uint32_t *num, uint32_t *den)
3980 while (*num > 0xffffff || *den > 0xffffff) {
3987 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3988 int pixel_clock, int link_clock,
3989 struct intel_link_m_n *m_n)
3992 m_n->gmch_m = bits_per_pixel * pixel_clock;
3993 m_n->gmch_n = link_clock * nlanes * 8;
3994 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3995 m_n->link_m = pixel_clock;
3996 m_n->link_n = link_clock;
3997 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4000 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4002 if (i915_panel_use_ssc >= 0)
4003 return i915_panel_use_ssc != 0;
4004 return dev_priv->lvds_use_ssc
4005 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4009 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4010 * @crtc: CRTC structure
4011 * @mode: requested mode
4013 * A pipe may be connected to one or more outputs. Based on the depth of the
4014 * attached framebuffer, choose a good color depth to use on the pipe.
4016 * If possible, match the pipe depth to the fb depth. In some cases, this
4017 * isn't ideal, because the connected output supports a lesser or restricted
4018 * set of depths. Resolve that here:
4019 * LVDS typically supports only 6bpc, so clamp down in that case
4020 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4021 * Displays may support a restricted set as well, check EDID and clamp as
4023 * DP may want to dither down to 6bpc to fit larger modes
4026 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4027 * true if they don't match).
4029 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4030 struct drm_framebuffer *fb,
4031 unsigned int *pipe_bpp,
4032 struct drm_display_mode *mode)
4034 struct drm_device *dev = crtc->dev;
4035 struct drm_i915_private *dev_priv = dev->dev_private;
4036 struct drm_connector *connector;
4037 struct intel_encoder *intel_encoder;
4038 unsigned int display_bpc = UINT_MAX, bpc;
4040 /* Walk the encoders & connectors on this crtc, get min bpc */
4041 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4043 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4044 unsigned int lvds_bpc;
4046 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4052 if (lvds_bpc < display_bpc) {
4053 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4054 display_bpc = lvds_bpc;
4059 /* Not one of the known troublemakers, check the EDID */
4060 list_for_each_entry(connector, &dev->mode_config.connector_list,
4062 if (connector->encoder != &intel_encoder->base)
4065 /* Don't use an invalid EDID bpc value */
4066 if (connector->display_info.bpc &&
4067 connector->display_info.bpc < display_bpc) {
4068 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4069 display_bpc = connector->display_info.bpc;
4073 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4074 /* Use VBT settings if we have an eDP panel */
4075 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4077 if (edp_bpc && edp_bpc < display_bpc) {
4078 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4079 display_bpc = edp_bpc;
4085 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4086 * through, clamp it down. (Note: >12bpc will be caught below.)
4088 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4089 if (display_bpc > 8 && display_bpc < 12) {
4090 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4093 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4099 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4100 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4105 * We could just drive the pipe at the highest bpc all the time and
4106 * enable dithering as needed, but that costs bandwidth. So choose
4107 * the minimum value that expresses the full color range of the fb but
4108 * also stays within the max display bpc discovered above.
4111 switch (fb->depth) {
4113 bpc = 8; /* since we go through a colormap */
4117 bpc = 6; /* min is 18bpp */
4129 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4130 bpc = min((unsigned int)8, display_bpc);
4134 display_bpc = min(display_bpc, bpc);
4136 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4139 *pipe_bpp = display_bpc * 3;
4141 return display_bpc != bpc;
4144 static int vlv_get_refclk(struct drm_crtc *crtc)
4146 struct drm_device *dev = crtc->dev;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int refclk = 27000; /* for DP & HDMI */
4150 return 100000; /* only one validated so far */
4152 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4154 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4155 if (intel_panel_use_ssc(dev_priv))
4159 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4166 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4168 struct drm_device *dev = crtc->dev;
4169 struct drm_i915_private *dev_priv = dev->dev_private;
4172 if (IS_VALLEYVIEW(dev)) {
4173 refclk = vlv_get_refclk(crtc);
4174 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4175 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4176 refclk = dev_priv->lvds_ssc_freq * 1000;
4177 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4179 } else if (!IS_GEN2(dev)) {
4188 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4189 intel_clock_t *clock)
4191 /* SDVO TV has fixed PLL values depend on its clock range,
4192 this mirrors vbios setting. */
4193 if (adjusted_mode->clock >= 100000
4194 && adjusted_mode->clock < 140500) {
4200 } else if (adjusted_mode->clock >= 140500
4201 && adjusted_mode->clock <= 200000) {
4210 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4211 intel_clock_t *clock,
4212 intel_clock_t *reduced_clock)
4214 struct drm_device *dev = crtc->dev;
4215 struct drm_i915_private *dev_priv = dev->dev_private;
4216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217 int pipe = intel_crtc->pipe;
4220 if (IS_PINEVIEW(dev)) {
4221 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4223 fp2 = (1 << reduced_clock->n) << 16 |
4224 reduced_clock->m1 << 8 | reduced_clock->m2;
4226 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4228 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4232 I915_WRITE(FP0(pipe), fp);
4234 intel_crtc->lowfreq_avail = false;
4235 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4236 reduced_clock && i915_powersave) {
4237 I915_WRITE(FP1(pipe), fp2);
4238 intel_crtc->lowfreq_avail = true;
4240 I915_WRITE(FP1(pipe), fp);
4244 static void vlv_update_pll(struct drm_crtc *crtc,
4245 struct drm_display_mode *mode,
4246 struct drm_display_mode *adjusted_mode,
4247 intel_clock_t *clock, intel_clock_t *reduced_clock,
4250 struct drm_device *dev = crtc->dev;
4251 struct drm_i915_private *dev_priv = dev->dev_private;
4252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253 int pipe = intel_crtc->pipe;
4254 u32 dpll, mdiv, pdiv;
4255 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4259 mutex_lock(&dev_priv->dpio_lock);
4261 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4262 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4264 dpll = DPLL_VGA_MODE_DIS;
4265 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4266 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4267 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4269 I915_WRITE(DPLL(pipe), dpll);
4270 POSTING_READ(DPLL(pipe));
4279 * In Valleyview PLL and program lane counter registers are exposed
4280 * through DPIO interface
4282 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4283 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4284 mdiv |= ((bestn << DPIO_N_SHIFT));
4285 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4286 mdiv |= (1 << DPIO_K_SHIFT);
4287 mdiv |= DPIO_ENABLE_CALIBRATION;
4288 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4290 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4292 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4293 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4294 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4295 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4296 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4298 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4300 dpll |= DPLL_VCO_ENABLE;
4301 I915_WRITE(DPLL(pipe), dpll);
4302 POSTING_READ(DPLL(pipe));
4303 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4304 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4306 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4308 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4309 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4311 I915_WRITE(DPLL(pipe), dpll);
4313 /* Wait for the clocks to stabilize. */
4314 POSTING_READ(DPLL(pipe));
4319 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4321 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4325 I915_WRITE(DPLL_MD(pipe), temp);
4326 POSTING_READ(DPLL_MD(pipe));
4328 /* Now program lane control registers */
4329 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4330 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4335 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4337 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4342 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4345 mutex_unlock(&dev_priv->dpio_lock);
4348 static void i9xx_update_pll(struct drm_crtc *crtc,
4349 struct drm_display_mode *mode,
4350 struct drm_display_mode *adjusted_mode,
4351 intel_clock_t *clock, intel_clock_t *reduced_clock,
4354 struct drm_device *dev = crtc->dev;
4355 struct drm_i915_private *dev_priv = dev->dev_private;
4356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4357 struct intel_encoder *encoder;
4358 int pipe = intel_crtc->pipe;
4362 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4364 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4365 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4367 dpll = DPLL_VGA_MODE_DIS;
4369 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4370 dpll |= DPLLB_MODE_LVDS;
4372 dpll |= DPLLB_MODE_DAC_SERIAL;
4374 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4375 if (pixel_multiplier > 1) {
4376 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4377 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4379 dpll |= DPLL_DVO_HIGH_SPEED;
4381 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4382 dpll |= DPLL_DVO_HIGH_SPEED;
4384 /* compute bitmask from p1 value */
4385 if (IS_PINEVIEW(dev))
4386 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4388 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4389 if (IS_G4X(dev) && reduced_clock)
4390 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4392 switch (clock->p2) {
4394 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4397 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4400 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4403 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4406 if (INTEL_INFO(dev)->gen >= 4)
4407 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4409 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4410 dpll |= PLL_REF_INPUT_TVCLKINBC;
4411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4412 /* XXX: just matching BIOS for now */
4413 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4415 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4416 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4417 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4419 dpll |= PLL_REF_INPUT_DREFCLK;
4421 dpll |= DPLL_VCO_ENABLE;
4422 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4423 POSTING_READ(DPLL(pipe));
4426 for_each_encoder_on_crtc(dev, crtc, encoder)
4427 if (encoder->pre_pll_enable)
4428 encoder->pre_pll_enable(encoder);
4430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4431 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4433 I915_WRITE(DPLL(pipe), dpll);
4435 /* Wait for the clocks to stabilize. */
4436 POSTING_READ(DPLL(pipe));
4439 if (INTEL_INFO(dev)->gen >= 4) {
4442 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4444 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4448 I915_WRITE(DPLL_MD(pipe), temp);
4450 /* The pixel multiplier can only be updated once the
4451 * DPLL is enabled and the clocks are stable.
4453 * So write it again.
4455 I915_WRITE(DPLL(pipe), dpll);
4459 static void i8xx_update_pll(struct drm_crtc *crtc,
4460 struct drm_display_mode *adjusted_mode,
4461 intel_clock_t *clock, intel_clock_t *reduced_clock,
4464 struct drm_device *dev = crtc->dev;
4465 struct drm_i915_private *dev_priv = dev->dev_private;
4466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4467 struct intel_encoder *encoder;
4468 int pipe = intel_crtc->pipe;
4471 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4473 dpll = DPLL_VGA_MODE_DIS;
4475 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4476 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4479 dpll |= PLL_P1_DIVIDE_BY_TWO;
4481 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4483 dpll |= PLL_P2_DIVIDE_BY_4;
4486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4487 /* XXX: just matching BIOS for now */
4488 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4490 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4491 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4492 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4494 dpll |= PLL_REF_INPUT_DREFCLK;
4496 dpll |= DPLL_VCO_ENABLE;
4497 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4498 POSTING_READ(DPLL(pipe));
4501 for_each_encoder_on_crtc(dev, crtc, encoder)
4502 if (encoder->pre_pll_enable)
4503 encoder->pre_pll_enable(encoder);
4505 I915_WRITE(DPLL(pipe), dpll);
4507 /* Wait for the clocks to stabilize. */
4508 POSTING_READ(DPLL(pipe));
4511 /* The pixel multiplier can only be updated once the
4512 * DPLL is enabled and the clocks are stable.
4514 * So write it again.
4516 I915_WRITE(DPLL(pipe), dpll);
4519 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4520 struct drm_display_mode *mode,
4521 struct drm_display_mode *adjusted_mode)
4523 struct drm_device *dev = intel_crtc->base.dev;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 enum pipe pipe = intel_crtc->pipe;
4526 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4527 uint32_t vsyncshift;
4529 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4530 /* the chip adds 2 halflines automatically */
4531 adjusted_mode->crtc_vtotal -= 1;
4532 adjusted_mode->crtc_vblank_end -= 1;
4533 vsyncshift = adjusted_mode->crtc_hsync_start
4534 - adjusted_mode->crtc_htotal / 2;
4539 if (INTEL_INFO(dev)->gen > 3)
4540 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4542 I915_WRITE(HTOTAL(cpu_transcoder),
4543 (adjusted_mode->crtc_hdisplay - 1) |
4544 ((adjusted_mode->crtc_htotal - 1) << 16));
4545 I915_WRITE(HBLANK(cpu_transcoder),
4546 (adjusted_mode->crtc_hblank_start - 1) |
4547 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4548 I915_WRITE(HSYNC(cpu_transcoder),
4549 (adjusted_mode->crtc_hsync_start - 1) |
4550 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4552 I915_WRITE(VTOTAL(cpu_transcoder),
4553 (adjusted_mode->crtc_vdisplay - 1) |
4554 ((adjusted_mode->crtc_vtotal - 1) << 16));
4555 I915_WRITE(VBLANK(cpu_transcoder),
4556 (adjusted_mode->crtc_vblank_start - 1) |
4557 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4558 I915_WRITE(VSYNC(cpu_transcoder),
4559 (adjusted_mode->crtc_vsync_start - 1) |
4560 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4562 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4563 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4564 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4566 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4567 (pipe == PIPE_B || pipe == PIPE_C))
4568 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4570 /* pipesrc controls the size that is scaled from, which should
4571 * always be the user's requested size.
4573 I915_WRITE(PIPESRC(pipe),
4574 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4577 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4578 struct drm_display_mode *mode,
4579 struct drm_display_mode *adjusted_mode,
4581 struct drm_framebuffer *fb)
4583 struct drm_device *dev = crtc->dev;
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4586 int pipe = intel_crtc->pipe;
4587 int plane = intel_crtc->plane;
4588 int refclk, num_connectors = 0;
4589 intel_clock_t clock, reduced_clock;
4590 u32 dspcntr, pipeconf;
4591 bool ok, has_reduced_clock = false, is_sdvo = false;
4592 bool is_lvds = false, is_tv = false, is_dp = false;
4593 struct intel_encoder *encoder;
4594 const intel_limit_t *limit;
4597 for_each_encoder_on_crtc(dev, crtc, encoder) {
4598 switch (encoder->type) {
4599 case INTEL_OUTPUT_LVDS:
4602 case INTEL_OUTPUT_SDVO:
4603 case INTEL_OUTPUT_HDMI:
4605 if (encoder->needs_tv_clock)
4608 case INTEL_OUTPUT_TVOUT:
4611 case INTEL_OUTPUT_DISPLAYPORT:
4619 refclk = i9xx_get_refclk(crtc, num_connectors);
4622 * Returns a set of divisors for the desired target clock with the given
4623 * refclk, or FALSE. The returned values represent the clock equation:
4624 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4626 limit = intel_limit(crtc, refclk);
4627 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4630 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4634 /* Ensure that the cursor is valid for the new mode before changing... */
4635 intel_crtc_update_cursor(crtc, true);
4637 if (is_lvds && dev_priv->lvds_downclock_avail) {
4639 * Ensure we match the reduced clock's P to the target clock.
4640 * If the clocks don't match, we can't switch the display clock
4641 * by using the FP0/FP1. In such case we will disable the LVDS
4642 * downclock feature.
4644 has_reduced_clock = limit->find_pll(limit, crtc,
4645 dev_priv->lvds_downclock,
4651 if (is_sdvo && is_tv)
4652 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4655 i8xx_update_pll(crtc, adjusted_mode, &clock,
4656 has_reduced_clock ? &reduced_clock : NULL,
4658 else if (IS_VALLEYVIEW(dev))
4659 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4660 has_reduced_clock ? &reduced_clock : NULL,
4663 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4664 has_reduced_clock ? &reduced_clock : NULL,
4667 /* setup pipeconf */
4668 pipeconf = I915_READ(PIPECONF(pipe));
4670 /* Set up the display plane register */
4671 dspcntr = DISPPLANE_GAMMA_ENABLE;
4674 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4676 dspcntr |= DISPPLANE_SEL_PIPE_B;
4678 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4679 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4682 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4686 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4687 pipeconf |= PIPECONF_DOUBLE_WIDE;
4689 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4692 /* default to 8bpc */
4693 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4695 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4696 pipeconf |= PIPECONF_6BPC |
4697 PIPECONF_DITHER_EN |
4698 PIPECONF_DITHER_TYPE_SP;
4702 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4703 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4704 pipeconf |= PIPECONF_6BPC |
4706 I965_PIPECONF_ACTIVE;
4710 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4711 drm_mode_debug_printmodeline(mode);
4713 if (HAS_PIPE_CXSR(dev)) {
4714 if (intel_crtc->lowfreq_avail) {
4715 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4716 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4718 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4719 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4723 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4724 if (!IS_GEN2(dev) &&
4725 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4726 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4728 pipeconf |= PIPECONF_PROGRESSIVE;
4730 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4732 /* pipesrc and dspsize control the size that is scaled from,
4733 * which should always be the user's requested size.
4735 I915_WRITE(DSPSIZE(plane),
4736 ((mode->vdisplay - 1) << 16) |
4737 (mode->hdisplay - 1));
4738 I915_WRITE(DSPPOS(plane), 0);
4740 I915_WRITE(PIPECONF(pipe), pipeconf);
4741 POSTING_READ(PIPECONF(pipe));
4742 intel_enable_pipe(dev_priv, pipe, false);
4744 intel_wait_for_vblank(dev, pipe);
4746 I915_WRITE(DSPCNTR(plane), dspcntr);
4747 POSTING_READ(DSPCNTR(plane));
4749 ret = intel_pipe_set_base(crtc, x, y, fb);
4751 intel_update_watermarks(dev);
4756 static void ironlake_init_pch_refclk(struct drm_device *dev)
4758 struct drm_i915_private *dev_priv = dev->dev_private;
4759 struct drm_mode_config *mode_config = &dev->mode_config;
4760 struct intel_encoder *encoder;
4762 bool has_lvds = false;
4763 bool has_cpu_edp = false;
4764 bool has_pch_edp = false;
4765 bool has_panel = false;
4766 bool has_ck505 = false;
4767 bool can_ssc = false;
4769 /* We need to take the global config into account */
4770 list_for_each_entry(encoder, &mode_config->encoder_list,
4772 switch (encoder->type) {
4773 case INTEL_OUTPUT_LVDS:
4777 case INTEL_OUTPUT_EDP:
4779 if (intel_encoder_is_pch_edp(&encoder->base))
4787 if (HAS_PCH_IBX(dev)) {
4788 has_ck505 = dev_priv->display_clock_mode;
4789 can_ssc = has_ck505;
4795 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4796 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4799 /* Ironlake: try to setup display ref clock before DPLL
4800 * enabling. This is only under driver's control after
4801 * PCH B stepping, previous chipset stepping should be
4802 * ignoring this setting.
4804 temp = I915_READ(PCH_DREF_CONTROL);
4805 /* Always enable nonspread source */
4806 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4809 temp |= DREF_NONSPREAD_CK505_ENABLE;
4811 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4814 temp &= ~DREF_SSC_SOURCE_MASK;
4815 temp |= DREF_SSC_SOURCE_ENABLE;
4817 /* SSC must be turned on before enabling the CPU output */
4818 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4819 DRM_DEBUG_KMS("Using SSC on panel\n");
4820 temp |= DREF_SSC1_ENABLE;
4822 temp &= ~DREF_SSC1_ENABLE;
4824 /* Get SSC going before enabling the outputs */
4825 I915_WRITE(PCH_DREF_CONTROL, temp);
4826 POSTING_READ(PCH_DREF_CONTROL);
4829 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4831 /* Enable CPU source on CPU attached eDP */
4833 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4834 DRM_DEBUG_KMS("Using SSC on eDP\n");
4835 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4838 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4840 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4842 I915_WRITE(PCH_DREF_CONTROL, temp);
4843 POSTING_READ(PCH_DREF_CONTROL);
4846 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4848 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4850 /* Turn off CPU output */
4851 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4853 I915_WRITE(PCH_DREF_CONTROL, temp);
4854 POSTING_READ(PCH_DREF_CONTROL);
4857 /* Turn off the SSC source */
4858 temp &= ~DREF_SSC_SOURCE_MASK;
4859 temp |= DREF_SSC_SOURCE_DISABLE;
4862 temp &= ~ DREF_SSC1_ENABLE;
4864 I915_WRITE(PCH_DREF_CONTROL, temp);
4865 POSTING_READ(PCH_DREF_CONTROL);
4870 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4871 static void lpt_init_pch_refclk(struct drm_device *dev)
4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874 struct drm_mode_config *mode_config = &dev->mode_config;
4875 struct intel_encoder *encoder;
4876 bool has_vga = false;
4877 bool is_sdv = false;
4880 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4881 switch (encoder->type) {
4882 case INTEL_OUTPUT_ANALOG:
4891 mutex_lock(&dev_priv->dpio_lock);
4893 /* XXX: Rip out SDV support once Haswell ships for real. */
4894 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4897 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4898 tmp &= ~SBI_SSCCTL_DISABLE;
4899 tmp |= SBI_SSCCTL_PATHALT;
4900 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4904 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4905 tmp &= ~SBI_SSCCTL_PATHALT;
4906 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4909 tmp = I915_READ(SOUTH_CHICKEN2);
4910 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4911 I915_WRITE(SOUTH_CHICKEN2, tmp);
4913 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4914 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4915 DRM_ERROR("FDI mPHY reset assert timeout\n");
4917 tmp = I915_READ(SOUTH_CHICKEN2);
4918 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4919 I915_WRITE(SOUTH_CHICKEN2, tmp);
4921 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4922 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4924 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4927 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4928 tmp &= ~(0xFF << 24);
4929 tmp |= (0x12 << 24);
4930 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4933 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4935 tmp |= (1 << 6) | (1 << 0);
4936 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4940 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4942 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4945 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4947 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4949 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4951 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4954 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4955 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4956 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4958 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4959 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4960 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4962 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4964 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4966 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4968 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4971 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4972 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4973 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4975 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4976 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4977 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4980 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4983 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4985 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4988 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4991 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4994 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4996 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4999 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5001 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5002 tmp &= ~(0xFF << 16);
5003 tmp |= (0x1C << 16);
5004 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5006 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5007 tmp &= ~(0xFF << 16);
5008 tmp |= (0x1C << 16);
5009 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5012 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5014 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5016 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5018 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5020 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5021 tmp &= ~(0xF << 28);
5023 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5025 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5026 tmp &= ~(0xF << 28);
5028 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5031 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5032 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5033 tmp |= SBI_DBUFF0_ENABLE;
5034 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5036 mutex_unlock(&dev_priv->dpio_lock);
5040 * Initialize reference clocks when the driver loads
5042 void intel_init_pch_refclk(struct drm_device *dev)
5044 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5045 ironlake_init_pch_refclk(dev);
5046 else if (HAS_PCH_LPT(dev))
5047 lpt_init_pch_refclk(dev);
5050 static int ironlake_get_refclk(struct drm_crtc *crtc)
5052 struct drm_device *dev = crtc->dev;
5053 struct drm_i915_private *dev_priv = dev->dev_private;
5054 struct intel_encoder *encoder;
5055 struct intel_encoder *edp_encoder = NULL;
5056 int num_connectors = 0;
5057 bool is_lvds = false;
5059 for_each_encoder_on_crtc(dev, crtc, encoder) {
5060 switch (encoder->type) {
5061 case INTEL_OUTPUT_LVDS:
5064 case INTEL_OUTPUT_EDP:
5065 edp_encoder = encoder;
5071 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5072 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5073 dev_priv->lvds_ssc_freq);
5074 return dev_priv->lvds_ssc_freq * 1000;
5080 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5081 struct drm_display_mode *adjusted_mode,
5084 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5086 int pipe = intel_crtc->pipe;
5089 val = I915_READ(PIPECONF(pipe));
5091 val &= ~PIPECONF_BPC_MASK;
5092 switch (intel_crtc->bpp) {
5094 val |= PIPECONF_6BPC;
5097 val |= PIPECONF_8BPC;
5100 val |= PIPECONF_10BPC;
5103 val |= PIPECONF_12BPC;
5106 /* Case prevented by intel_choose_pipe_bpp_dither. */
5110 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5112 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5114 val &= ~PIPECONF_INTERLACE_MASK;
5115 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5116 val |= PIPECONF_INTERLACED_ILK;
5118 val |= PIPECONF_PROGRESSIVE;
5120 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5121 val |= PIPECONF_COLOR_RANGE_SELECT;
5123 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5125 I915_WRITE(PIPECONF(pipe), val);
5126 POSTING_READ(PIPECONF(pipe));
5130 * Set up the pipe CSC unit.
5132 * Currently only full range RGB to limited range RGB conversion
5133 * is supported, but eventually this should handle various
5134 * RGB<->YCbCr scenarios as well.
5136 static void intel_set_pipe_csc(struct drm_crtc *crtc,
5137 const struct drm_display_mode *adjusted_mode)
5139 struct drm_device *dev = crtc->dev;
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5142 int pipe = intel_crtc->pipe;
5143 uint16_t coeff = 0x7800; /* 1.0 */
5146 * TODO: Check what kind of values actually come out of the pipe
5147 * with these coeff/postoff values and adjust to get the best
5148 * accuracy. Perhaps we even need to take the bpc value into
5152 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5153 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5156 * GY/GU and RY/RU should be the other way around according
5157 * to BSpec, but reality doesn't agree. Just set them up in
5158 * a way that results in the correct picture.
5160 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5161 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5163 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5164 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5166 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5167 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5169 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5170 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5171 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5173 if (INTEL_INFO(dev)->gen > 6) {
5174 uint16_t postoff = 0;
5176 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5177 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5179 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5180 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5181 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5183 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5185 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5187 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5188 mode |= CSC_BLACK_SCREEN_OFFSET;
5190 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5194 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5195 struct drm_display_mode *adjusted_mode,
5198 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5200 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5203 val = I915_READ(PIPECONF(cpu_transcoder));
5205 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5207 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5209 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5210 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5211 val |= PIPECONF_INTERLACED_ILK;
5213 val |= PIPECONF_PROGRESSIVE;
5215 I915_WRITE(PIPECONF(cpu_transcoder), val);
5216 POSTING_READ(PIPECONF(cpu_transcoder));
5219 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5220 struct drm_display_mode *adjusted_mode,
5221 intel_clock_t *clock,
5222 bool *has_reduced_clock,
5223 intel_clock_t *reduced_clock)
5225 struct drm_device *dev = crtc->dev;
5226 struct drm_i915_private *dev_priv = dev->dev_private;
5227 struct intel_encoder *intel_encoder;
5229 const intel_limit_t *limit;
5230 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5232 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5233 switch (intel_encoder->type) {
5234 case INTEL_OUTPUT_LVDS:
5237 case INTEL_OUTPUT_SDVO:
5238 case INTEL_OUTPUT_HDMI:
5240 if (intel_encoder->needs_tv_clock)
5243 case INTEL_OUTPUT_TVOUT:
5249 refclk = ironlake_get_refclk(crtc);
5252 * Returns a set of divisors for the desired target clock with the given
5253 * refclk, or FALSE. The returned values represent the clock equation:
5254 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5256 limit = intel_limit(crtc, refclk);
5257 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5262 if (is_lvds && dev_priv->lvds_downclock_avail) {
5264 * Ensure we match the reduced clock's P to the target clock.
5265 * If the clocks don't match, we can't switch the display clock
5266 * by using the FP0/FP1. In such case we will disable the LVDS
5267 * downclock feature.
5269 *has_reduced_clock = limit->find_pll(limit, crtc,
5270 dev_priv->lvds_downclock,
5276 if (is_sdvo && is_tv)
5277 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5282 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5287 temp = I915_READ(SOUTH_CHICKEN1);
5288 if (temp & FDI_BC_BIFURCATION_SELECT)
5291 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5292 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5294 temp |= FDI_BC_BIFURCATION_SELECT;
5295 DRM_DEBUG_KMS("enabling fdi C rx\n");
5296 I915_WRITE(SOUTH_CHICKEN1, temp);
5297 POSTING_READ(SOUTH_CHICKEN1);
5300 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5302 struct drm_device *dev = intel_crtc->base.dev;
5303 struct drm_i915_private *dev_priv = dev->dev_private;
5304 struct intel_crtc *pipe_B_crtc =
5305 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5307 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5308 intel_crtc->pipe, intel_crtc->fdi_lanes);
5309 if (intel_crtc->fdi_lanes > 4) {
5310 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5311 intel_crtc->pipe, intel_crtc->fdi_lanes);
5312 /* Clamp lanes to avoid programming the hw with bogus values. */
5313 intel_crtc->fdi_lanes = 4;
5318 if (dev_priv->num_pipe == 2)
5321 switch (intel_crtc->pipe) {
5325 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5326 intel_crtc->fdi_lanes > 2) {
5327 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5328 intel_crtc->pipe, intel_crtc->fdi_lanes);
5329 /* Clamp lanes to avoid programming the hw with bogus values. */
5330 intel_crtc->fdi_lanes = 2;
5335 if (intel_crtc->fdi_lanes > 2)
5336 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5338 cpt_enable_fdi_bc_bifurcation(dev);
5342 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5343 if (intel_crtc->fdi_lanes > 2) {
5344 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5345 intel_crtc->pipe, intel_crtc->fdi_lanes);
5346 /* Clamp lanes to avoid programming the hw with bogus values. */
5347 intel_crtc->fdi_lanes = 2;
5352 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5356 cpt_enable_fdi_bc_bifurcation(dev);
5364 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5367 * Account for spread spectrum to avoid
5368 * oversubscribing the link. Max center spread
5369 * is 2.5%; use 5% for safety's sake.
5371 u32 bps = target_clock * bpp * 21 / 20;
5372 return bps / (link_bw * 8) + 1;
5375 static void ironlake_set_m_n(struct drm_crtc *crtc,
5376 struct drm_display_mode *mode,
5377 struct drm_display_mode *adjusted_mode)
5379 struct drm_device *dev = crtc->dev;
5380 struct drm_i915_private *dev_priv = dev->dev_private;
5381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5382 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5383 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5384 struct intel_link_m_n m_n = {0};
5385 int target_clock, pixel_multiplier, lane, link_bw;
5386 bool is_dp = false, is_cpu_edp = false;
5388 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5389 switch (intel_encoder->type) {
5390 case INTEL_OUTPUT_DISPLAYPORT:
5393 case INTEL_OUTPUT_EDP:
5395 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5397 edp_encoder = intel_encoder;
5403 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5405 /* CPU eDP doesn't require FDI link, so just set DP M/N
5406 according to current link config */
5408 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5410 /* FDI is a binary signal running at ~2.7GHz, encoding
5411 * each output octet as 10 bits. The actual frequency
5412 * is stored as a divider into a 100MHz clock, and the
5413 * mode pixel clock is stored in units of 1KHz.
5414 * Hence the bw of each lane in terms of the mode signal
5417 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5420 /* [e]DP over FDI requires target mode clock instead of link clock. */
5422 target_clock = intel_edp_target_clock(edp_encoder, mode);
5424 target_clock = mode->clock;
5426 target_clock = adjusted_mode->clock;
5429 lane = ironlake_get_lanes_required(target_clock, link_bw,
5432 intel_crtc->fdi_lanes = lane;
5434 if (pixel_multiplier > 1)
5435 link_bw *= pixel_multiplier;
5436 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
5438 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5439 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5440 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5441 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5444 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5445 struct drm_display_mode *adjusted_mode,
5446 intel_clock_t *clock, u32 fp)
5448 struct drm_crtc *crtc = &intel_crtc->base;
5449 struct drm_device *dev = crtc->dev;
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451 struct intel_encoder *intel_encoder;
5453 int factor, pixel_multiplier, num_connectors = 0;
5454 bool is_lvds = false, is_sdvo = false, is_tv = false;
5455 bool is_dp = false, is_cpu_edp = false;
5457 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5458 switch (intel_encoder->type) {
5459 case INTEL_OUTPUT_LVDS:
5462 case INTEL_OUTPUT_SDVO:
5463 case INTEL_OUTPUT_HDMI:
5465 if (intel_encoder->needs_tv_clock)
5468 case INTEL_OUTPUT_TVOUT:
5471 case INTEL_OUTPUT_DISPLAYPORT:
5474 case INTEL_OUTPUT_EDP:
5476 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5484 /* Enable autotuning of the PLL clock (if permissible) */
5487 if ((intel_panel_use_ssc(dev_priv) &&
5488 dev_priv->lvds_ssc_freq == 100) ||
5489 intel_is_dual_link_lvds(dev))
5491 } else if (is_sdvo && is_tv)
5494 if (clock->m < factor * clock->n)
5500 dpll |= DPLLB_MODE_LVDS;
5502 dpll |= DPLLB_MODE_DAC_SERIAL;
5504 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5505 if (pixel_multiplier > 1) {
5506 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5508 dpll |= DPLL_DVO_HIGH_SPEED;
5510 if (is_dp && !is_cpu_edp)
5511 dpll |= DPLL_DVO_HIGH_SPEED;
5513 /* compute bitmask from p1 value */
5514 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5516 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5518 switch (clock->p2) {
5520 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5523 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5526 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5529 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5533 if (is_sdvo && is_tv)
5534 dpll |= PLL_REF_INPUT_TVCLKINBC;
5536 /* XXX: just matching BIOS for now */
5537 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5539 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5540 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5542 dpll |= PLL_REF_INPUT_DREFCLK;
5547 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5548 struct drm_display_mode *mode,
5549 struct drm_display_mode *adjusted_mode,
5551 struct drm_framebuffer *fb)
5553 struct drm_device *dev = crtc->dev;
5554 struct drm_i915_private *dev_priv = dev->dev_private;
5555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5556 int pipe = intel_crtc->pipe;
5557 int plane = intel_crtc->plane;
5558 int num_connectors = 0;
5559 intel_clock_t clock, reduced_clock;
5560 u32 dpll, fp = 0, fp2 = 0;
5561 bool ok, has_reduced_clock = false;
5562 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5563 struct intel_encoder *encoder;
5565 bool dither, fdi_config_ok;
5567 for_each_encoder_on_crtc(dev, crtc, encoder) {
5568 switch (encoder->type) {
5569 case INTEL_OUTPUT_LVDS:
5572 case INTEL_OUTPUT_DISPLAYPORT:
5575 case INTEL_OUTPUT_EDP:
5577 if (!intel_encoder_is_pch_edp(&encoder->base))
5585 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5586 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5588 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5589 &has_reduced_clock, &reduced_clock);
5591 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5595 /* Ensure that the cursor is valid for the new mode before changing... */
5596 intel_crtc_update_cursor(crtc, true);
5598 /* determine panel color depth */
5599 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5601 if (is_lvds && dev_priv->lvds_dither)
5604 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5605 if (has_reduced_clock)
5606 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5609 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5611 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5612 drm_mode_debug_printmodeline(mode);
5614 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5616 struct intel_pch_pll *pll;
5618 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5620 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5625 intel_put_pch_pll(intel_crtc);
5627 if (is_dp && !is_cpu_edp)
5628 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5630 for_each_encoder_on_crtc(dev, crtc, encoder)
5631 if (encoder->pre_pll_enable)
5632 encoder->pre_pll_enable(encoder);
5634 if (intel_crtc->pch_pll) {
5635 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5637 /* Wait for the clocks to stabilize. */
5638 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5641 /* The pixel multiplier can only be updated once the
5642 * DPLL is enabled and the clocks are stable.
5644 * So write it again.
5646 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5649 intel_crtc->lowfreq_avail = false;
5650 if (intel_crtc->pch_pll) {
5651 if (is_lvds && has_reduced_clock && i915_powersave) {
5652 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5653 intel_crtc->lowfreq_avail = true;
5655 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5659 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5661 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5662 * ironlake_check_fdi_lanes. */
5663 ironlake_set_m_n(crtc, mode, adjusted_mode);
5665 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5667 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5669 intel_wait_for_vblank(dev, pipe);
5671 /* Set up the display plane register */
5672 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5673 POSTING_READ(DSPCNTR(plane));
5675 ret = intel_pipe_set_base(crtc, x, y, fb);
5677 intel_update_watermarks(dev);
5679 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5681 return fdi_config_ok ? ret : -EINVAL;
5684 static void haswell_modeset_global_resources(struct drm_device *dev)
5686 struct drm_i915_private *dev_priv = dev->dev_private;
5687 bool enable = false;
5688 struct intel_crtc *crtc;
5689 struct intel_encoder *encoder;
5691 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5692 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5694 /* XXX: Should check for edp transcoder here, but thanks to init
5695 * sequence that's not yet available. Just in case desktop eDP
5696 * on PORT D is possible on haswell, too. */
5699 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5701 if (encoder->type != INTEL_OUTPUT_EDP &&
5702 encoder->connectors_active)
5706 /* Even the eDP panel fitter is outside the always-on well. */
5707 if (dev_priv->pch_pf_size)
5710 intel_set_power_well(dev, enable);
5713 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5714 struct drm_display_mode *mode,
5715 struct drm_display_mode *adjusted_mode,
5717 struct drm_framebuffer *fb)
5719 struct drm_device *dev = crtc->dev;
5720 struct drm_i915_private *dev_priv = dev->dev_private;
5721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5722 int pipe = intel_crtc->pipe;
5723 int plane = intel_crtc->plane;
5724 int num_connectors = 0;
5725 bool is_dp = false, is_cpu_edp = false;
5726 struct intel_encoder *encoder;
5730 for_each_encoder_on_crtc(dev, crtc, encoder) {
5731 switch (encoder->type) {
5732 case INTEL_OUTPUT_DISPLAYPORT:
5735 case INTEL_OUTPUT_EDP:
5737 if (!intel_encoder_is_pch_edp(&encoder->base))
5745 /* We are not sure yet this won't happen. */
5746 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5747 INTEL_PCH_TYPE(dev));
5749 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5750 num_connectors, pipe_name(pipe));
5752 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5753 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5755 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5757 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5760 /* Ensure that the cursor is valid for the new mode before changing... */
5761 intel_crtc_update_cursor(crtc, true);
5763 /* determine panel color depth */
5764 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5767 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5768 drm_mode_debug_printmodeline(mode);
5770 if (is_dp && !is_cpu_edp)
5771 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5773 intel_crtc->lowfreq_avail = false;
5775 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5777 if (!is_dp || is_cpu_edp)
5778 ironlake_set_m_n(crtc, mode, adjusted_mode);
5780 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5782 intel_set_pipe_csc(crtc, adjusted_mode);
5784 /* Set up the display plane register */
5785 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5786 POSTING_READ(DSPCNTR(plane));
5788 ret = intel_pipe_set_base(crtc, x, y, fb);
5790 intel_update_watermarks(dev);
5792 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5797 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5798 struct drm_display_mode *mode,
5799 struct drm_display_mode *adjusted_mode,
5801 struct drm_framebuffer *fb)
5803 struct drm_device *dev = crtc->dev;
5804 struct drm_i915_private *dev_priv = dev->dev_private;
5805 struct drm_encoder_helper_funcs *encoder_funcs;
5806 struct intel_encoder *encoder;
5807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5808 int pipe = intel_crtc->pipe;
5811 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5812 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5814 intel_crtc->cpu_transcoder = pipe;
5816 drm_vblank_pre_modeset(dev, pipe);
5818 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5820 drm_vblank_post_modeset(dev, pipe);
5825 for_each_encoder_on_crtc(dev, crtc, encoder) {
5826 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5827 encoder->base.base.id,
5828 drm_get_encoder_name(&encoder->base),
5829 mode->base.id, mode->name);
5830 encoder_funcs = encoder->base.helper_private;
5831 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5837 static bool intel_eld_uptodate(struct drm_connector *connector,
5838 int reg_eldv, uint32_t bits_eldv,
5839 int reg_elda, uint32_t bits_elda,
5842 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5843 uint8_t *eld = connector->eld;
5846 i = I915_READ(reg_eldv);
5855 i = I915_READ(reg_elda);
5857 I915_WRITE(reg_elda, i);
5859 for (i = 0; i < eld[2]; i++)
5860 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5866 static void g4x_write_eld(struct drm_connector *connector,
5867 struct drm_crtc *crtc)
5869 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5870 uint8_t *eld = connector->eld;
5875 i = I915_READ(G4X_AUD_VID_DID);
5877 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5878 eldv = G4X_ELDV_DEVCL_DEVBLC;
5880 eldv = G4X_ELDV_DEVCTG;
5882 if (intel_eld_uptodate(connector,
5883 G4X_AUD_CNTL_ST, eldv,
5884 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5885 G4X_HDMIW_HDMIEDID))
5888 i = I915_READ(G4X_AUD_CNTL_ST);
5889 i &= ~(eldv | G4X_ELD_ADDR);
5890 len = (i >> 9) & 0x1f; /* ELD buffer size */
5891 I915_WRITE(G4X_AUD_CNTL_ST, i);
5896 len = min_t(uint8_t, eld[2], len);
5897 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5898 for (i = 0; i < len; i++)
5899 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5901 i = I915_READ(G4X_AUD_CNTL_ST);
5903 I915_WRITE(G4X_AUD_CNTL_ST, i);
5906 static void haswell_write_eld(struct drm_connector *connector,
5907 struct drm_crtc *crtc)
5909 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5910 uint8_t *eld = connector->eld;
5911 struct drm_device *dev = crtc->dev;
5912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5916 int pipe = to_intel_crtc(crtc)->pipe;
5919 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5920 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5921 int aud_config = HSW_AUD_CFG(pipe);
5922 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5925 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5927 /* Audio output enable */
5928 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5929 tmp = I915_READ(aud_cntrl_st2);
5930 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5931 I915_WRITE(aud_cntrl_st2, tmp);
5933 /* Wait for 1 vertical blank */
5934 intel_wait_for_vblank(dev, pipe);
5936 /* Set ELD valid state */
5937 tmp = I915_READ(aud_cntrl_st2);
5938 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5939 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5940 I915_WRITE(aud_cntrl_st2, tmp);
5941 tmp = I915_READ(aud_cntrl_st2);
5942 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5944 /* Enable HDMI mode */
5945 tmp = I915_READ(aud_config);
5946 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5947 /* clear N_programing_enable and N_value_index */
5948 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5949 I915_WRITE(aud_config, tmp);
5951 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5953 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5954 intel_crtc->eld_vld = true;
5956 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5957 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5958 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5959 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5961 I915_WRITE(aud_config, 0);
5963 if (intel_eld_uptodate(connector,
5964 aud_cntrl_st2, eldv,
5965 aud_cntl_st, IBX_ELD_ADDRESS,
5969 i = I915_READ(aud_cntrl_st2);
5971 I915_WRITE(aud_cntrl_st2, i);
5976 i = I915_READ(aud_cntl_st);
5977 i &= ~IBX_ELD_ADDRESS;
5978 I915_WRITE(aud_cntl_st, i);
5979 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5980 DRM_DEBUG_DRIVER("port num:%d\n", i);
5982 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5983 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5984 for (i = 0; i < len; i++)
5985 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5987 i = I915_READ(aud_cntrl_st2);
5989 I915_WRITE(aud_cntrl_st2, i);
5993 static void ironlake_write_eld(struct drm_connector *connector,
5994 struct drm_crtc *crtc)
5996 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5997 uint8_t *eld = connector->eld;
6005 int pipe = to_intel_crtc(crtc)->pipe;
6007 if (HAS_PCH_IBX(connector->dev)) {
6008 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6009 aud_config = IBX_AUD_CFG(pipe);
6010 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6011 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6013 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6014 aud_config = CPT_AUD_CFG(pipe);
6015 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6016 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6019 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6021 i = I915_READ(aud_cntl_st);
6022 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6024 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6025 /* operate blindly on all ports */
6026 eldv = IBX_ELD_VALIDB;
6027 eldv |= IBX_ELD_VALIDB << 4;
6028 eldv |= IBX_ELD_VALIDB << 8;
6030 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6031 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6034 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6035 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6036 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6037 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6039 I915_WRITE(aud_config, 0);
6041 if (intel_eld_uptodate(connector,
6042 aud_cntrl_st2, eldv,
6043 aud_cntl_st, IBX_ELD_ADDRESS,
6047 i = I915_READ(aud_cntrl_st2);
6049 I915_WRITE(aud_cntrl_st2, i);
6054 i = I915_READ(aud_cntl_st);
6055 i &= ~IBX_ELD_ADDRESS;
6056 I915_WRITE(aud_cntl_st, i);
6058 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6059 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6060 for (i = 0; i < len; i++)
6061 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6063 i = I915_READ(aud_cntrl_st2);
6065 I915_WRITE(aud_cntrl_st2, i);
6068 void intel_write_eld(struct drm_encoder *encoder,
6069 struct drm_display_mode *mode)
6071 struct drm_crtc *crtc = encoder->crtc;
6072 struct drm_connector *connector;
6073 struct drm_device *dev = encoder->dev;
6074 struct drm_i915_private *dev_priv = dev->dev_private;
6076 connector = drm_select_eld(encoder, mode);
6080 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6082 drm_get_connector_name(connector),
6083 connector->encoder->base.id,
6084 drm_get_encoder_name(connector->encoder));
6086 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6088 if (dev_priv->display.write_eld)
6089 dev_priv->display.write_eld(connector, crtc);
6092 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6093 void intel_crtc_load_lut(struct drm_crtc *crtc)
6095 struct drm_device *dev = crtc->dev;
6096 struct drm_i915_private *dev_priv = dev->dev_private;
6097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6098 int palreg = PALETTE(intel_crtc->pipe);
6101 /* The clocks have to be on to load the palette. */
6102 if (!crtc->enabled || !intel_crtc->active)
6105 /* use legacy palette for Ironlake */
6106 if (HAS_PCH_SPLIT(dev))
6107 palreg = LGC_PALETTE(intel_crtc->pipe);
6109 for (i = 0; i < 256; i++) {
6110 I915_WRITE(palreg + 4 * i,
6111 (intel_crtc->lut_r[i] << 16) |
6112 (intel_crtc->lut_g[i] << 8) |
6113 intel_crtc->lut_b[i]);
6117 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6119 struct drm_device *dev = crtc->dev;
6120 struct drm_i915_private *dev_priv = dev->dev_private;
6121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122 bool visible = base != 0;
6125 if (intel_crtc->cursor_visible == visible)
6128 cntl = I915_READ(_CURACNTR);
6130 /* On these chipsets we can only modify the base whilst
6131 * the cursor is disabled.
6133 I915_WRITE(_CURABASE, base);
6135 cntl &= ~(CURSOR_FORMAT_MASK);
6136 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6137 cntl |= CURSOR_ENABLE |
6138 CURSOR_GAMMA_ENABLE |
6141 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6142 I915_WRITE(_CURACNTR, cntl);
6144 intel_crtc->cursor_visible = visible;
6147 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6149 struct drm_device *dev = crtc->dev;
6150 struct drm_i915_private *dev_priv = dev->dev_private;
6151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152 int pipe = intel_crtc->pipe;
6153 bool visible = base != 0;
6155 if (intel_crtc->cursor_visible != visible) {
6156 uint32_t cntl = I915_READ(CURCNTR(pipe));
6158 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6159 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6160 cntl |= pipe << 28; /* Connect to correct pipe */
6162 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6163 cntl |= CURSOR_MODE_DISABLE;
6165 I915_WRITE(CURCNTR(pipe), cntl);
6167 intel_crtc->cursor_visible = visible;
6169 /* and commit changes on next vblank */
6170 I915_WRITE(CURBASE(pipe), base);
6173 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6175 struct drm_device *dev = crtc->dev;
6176 struct drm_i915_private *dev_priv = dev->dev_private;
6177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178 int pipe = intel_crtc->pipe;
6179 bool visible = base != 0;
6181 if (intel_crtc->cursor_visible != visible) {
6182 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6184 cntl &= ~CURSOR_MODE;
6185 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6187 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6188 cntl |= CURSOR_MODE_DISABLE;
6190 if (IS_HASWELL(dev))
6191 cntl |= CURSOR_PIPE_CSC_ENABLE;
6192 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6194 intel_crtc->cursor_visible = visible;
6196 /* and commit changes on next vblank */
6197 I915_WRITE(CURBASE_IVB(pipe), base);
6200 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6201 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6204 struct drm_device *dev = crtc->dev;
6205 struct drm_i915_private *dev_priv = dev->dev_private;
6206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207 int pipe = intel_crtc->pipe;
6208 int x = intel_crtc->cursor_x;
6209 int y = intel_crtc->cursor_y;
6215 if (on && crtc->enabled && crtc->fb) {
6216 base = intel_crtc->cursor_addr;
6217 if (x > (int) crtc->fb->width)
6220 if (y > (int) crtc->fb->height)
6226 if (x + intel_crtc->cursor_width < 0)
6229 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6232 pos |= x << CURSOR_X_SHIFT;
6235 if (y + intel_crtc->cursor_height < 0)
6238 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6241 pos |= y << CURSOR_Y_SHIFT;
6243 visible = base != 0;
6244 if (!visible && !intel_crtc->cursor_visible)
6247 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6248 I915_WRITE(CURPOS_IVB(pipe), pos);
6249 ivb_update_cursor(crtc, base);
6251 I915_WRITE(CURPOS(pipe), pos);
6252 if (IS_845G(dev) || IS_I865G(dev))
6253 i845_update_cursor(crtc, base);
6255 i9xx_update_cursor(crtc, base);
6259 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6260 struct drm_file *file,
6262 uint32_t width, uint32_t height)
6264 struct drm_device *dev = crtc->dev;
6265 struct drm_i915_private *dev_priv = dev->dev_private;
6266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6267 struct drm_i915_gem_object *obj;
6271 /* if we want to turn off the cursor ignore width and height */
6273 DRM_DEBUG_KMS("cursor off\n");
6276 mutex_lock(&dev->struct_mutex);
6280 /* Currently we only support 64x64 cursors */
6281 if (width != 64 || height != 64) {
6282 DRM_ERROR("we currently only support 64x64 cursors\n");
6286 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6287 if (&obj->base == NULL)
6290 if (obj->base.size < width * height * 4) {
6291 DRM_ERROR("buffer is to small\n");
6296 /* we only need to pin inside GTT if cursor is non-phy */
6297 mutex_lock(&dev->struct_mutex);
6298 if (!dev_priv->info->cursor_needs_physical) {
6299 if (obj->tiling_mode) {
6300 DRM_ERROR("cursor cannot be tiled\n");
6305 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6307 DRM_ERROR("failed to move cursor bo into the GTT\n");
6311 ret = i915_gem_object_put_fence(obj);
6313 DRM_ERROR("failed to release fence for cursor");
6317 addr = obj->gtt_offset;
6319 int align = IS_I830(dev) ? 16 * 1024 : 256;
6320 ret = i915_gem_attach_phys_object(dev, obj,
6321 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6324 DRM_ERROR("failed to attach phys object\n");
6327 addr = obj->phys_obj->handle->busaddr;
6331 I915_WRITE(CURSIZE, (height << 12) | width);
6334 if (intel_crtc->cursor_bo) {
6335 if (dev_priv->info->cursor_needs_physical) {
6336 if (intel_crtc->cursor_bo != obj)
6337 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6339 i915_gem_object_unpin(intel_crtc->cursor_bo);
6340 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6343 mutex_unlock(&dev->struct_mutex);
6345 intel_crtc->cursor_addr = addr;
6346 intel_crtc->cursor_bo = obj;
6347 intel_crtc->cursor_width = width;
6348 intel_crtc->cursor_height = height;
6350 intel_crtc_update_cursor(crtc, true);
6354 i915_gem_object_unpin(obj);
6356 mutex_unlock(&dev->struct_mutex);
6358 drm_gem_object_unreference_unlocked(&obj->base);
6362 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6366 intel_crtc->cursor_x = x;
6367 intel_crtc->cursor_y = y;
6369 intel_crtc_update_cursor(crtc, true);
6374 /** Sets the color ramps on behalf of RandR */
6375 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6376 u16 blue, int regno)
6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6380 intel_crtc->lut_r[regno] = red >> 8;
6381 intel_crtc->lut_g[regno] = green >> 8;
6382 intel_crtc->lut_b[regno] = blue >> 8;
6385 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6386 u16 *blue, int regno)
6388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390 *red = intel_crtc->lut_r[regno] << 8;
6391 *green = intel_crtc->lut_g[regno] << 8;
6392 *blue = intel_crtc->lut_b[regno] << 8;
6395 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6396 u16 *blue, uint32_t start, uint32_t size)
6398 int end = (start + size > 256) ? 256 : start + size, i;
6399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6401 for (i = start; i < end; i++) {
6402 intel_crtc->lut_r[i] = red[i] >> 8;
6403 intel_crtc->lut_g[i] = green[i] >> 8;
6404 intel_crtc->lut_b[i] = blue[i] >> 8;
6407 intel_crtc_load_lut(crtc);
6411 * Get a pipe with a simple mode set on it for doing load-based monitor
6414 * It will be up to the load-detect code to adjust the pipe as appropriate for
6415 * its requirements. The pipe will be connected to no other encoders.
6417 * Currently this code will only succeed if there is a pipe with no encoders
6418 * configured for it. In the future, it could choose to temporarily disable
6419 * some outputs to free up a pipe for its use.
6421 * \return crtc, or NULL if no pipes are available.
6424 /* VESA 640x480x72Hz mode to set on the pipe */
6425 static struct drm_display_mode load_detect_mode = {
6426 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6427 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6430 static struct drm_framebuffer *
6431 intel_framebuffer_create(struct drm_device *dev,
6432 struct drm_mode_fb_cmd2 *mode_cmd,
6433 struct drm_i915_gem_object *obj)
6435 struct intel_framebuffer *intel_fb;
6438 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6440 drm_gem_object_unreference_unlocked(&obj->base);
6441 return ERR_PTR(-ENOMEM);
6444 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6446 drm_gem_object_unreference_unlocked(&obj->base);
6448 return ERR_PTR(ret);
6451 return &intel_fb->base;
6455 intel_framebuffer_pitch_for_width(int width, int bpp)
6457 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6458 return ALIGN(pitch, 64);
6462 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6464 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6465 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6468 static struct drm_framebuffer *
6469 intel_framebuffer_create_for_mode(struct drm_device *dev,
6470 struct drm_display_mode *mode,
6473 struct drm_i915_gem_object *obj;
6474 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6476 obj = i915_gem_alloc_object(dev,
6477 intel_framebuffer_size_for_mode(mode, bpp));
6479 return ERR_PTR(-ENOMEM);
6481 mode_cmd.width = mode->hdisplay;
6482 mode_cmd.height = mode->vdisplay;
6483 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6485 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6487 return intel_framebuffer_create(dev, &mode_cmd, obj);
6490 static struct drm_framebuffer *
6491 mode_fits_in_fbdev(struct drm_device *dev,
6492 struct drm_display_mode *mode)
6494 struct drm_i915_private *dev_priv = dev->dev_private;
6495 struct drm_i915_gem_object *obj;
6496 struct drm_framebuffer *fb;
6498 if (dev_priv->fbdev == NULL)
6501 obj = dev_priv->fbdev->ifb.obj;
6505 fb = &dev_priv->fbdev->ifb.base;
6506 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6507 fb->bits_per_pixel))
6510 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6516 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6517 struct drm_display_mode *mode,
6518 struct intel_load_detect_pipe *old)
6520 struct intel_crtc *intel_crtc;
6521 struct intel_encoder *intel_encoder =
6522 intel_attached_encoder(connector);
6523 struct drm_crtc *possible_crtc;
6524 struct drm_encoder *encoder = &intel_encoder->base;
6525 struct drm_crtc *crtc = NULL;
6526 struct drm_device *dev = encoder->dev;
6527 struct drm_framebuffer *fb;
6530 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6531 connector->base.id, drm_get_connector_name(connector),
6532 encoder->base.id, drm_get_encoder_name(encoder));
6535 * Algorithm gets a little messy:
6537 * - if the connector already has an assigned crtc, use it (but make
6538 * sure it's on first)
6540 * - try to find the first unused crtc that can drive this connector,
6541 * and use that if we find one
6544 /* See if we already have a CRTC for this connector */
6545 if (encoder->crtc) {
6546 crtc = encoder->crtc;
6548 mutex_lock(&crtc->mutex);
6550 old->dpms_mode = connector->dpms;
6551 old->load_detect_temp = false;
6553 /* Make sure the crtc and connector are running */
6554 if (connector->dpms != DRM_MODE_DPMS_ON)
6555 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6560 /* Find an unused one (if possible) */
6561 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6563 if (!(encoder->possible_crtcs & (1 << i)))
6565 if (!possible_crtc->enabled) {
6566 crtc = possible_crtc;
6572 * If we didn't find an unused CRTC, don't use any.
6575 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6579 mutex_lock(&crtc->mutex);
6580 intel_encoder->new_crtc = to_intel_crtc(crtc);
6581 to_intel_connector(connector)->new_encoder = intel_encoder;
6583 intel_crtc = to_intel_crtc(crtc);
6584 old->dpms_mode = connector->dpms;
6585 old->load_detect_temp = true;
6586 old->release_fb = NULL;
6589 mode = &load_detect_mode;
6591 /* We need a framebuffer large enough to accommodate all accesses
6592 * that the plane may generate whilst we perform load detection.
6593 * We can not rely on the fbcon either being present (we get called
6594 * during its initialisation to detect all boot displays, or it may
6595 * not even exist) or that it is large enough to satisfy the
6598 fb = mode_fits_in_fbdev(dev, mode);
6600 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6601 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6602 old->release_fb = fb;
6604 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6606 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6607 mutex_unlock(&crtc->mutex);
6611 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6612 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6613 if (old->release_fb)
6614 old->release_fb->funcs->destroy(old->release_fb);
6615 mutex_unlock(&crtc->mutex);
6619 /* let the connector get through one full cycle before testing */
6620 intel_wait_for_vblank(dev, intel_crtc->pipe);
6624 void intel_release_load_detect_pipe(struct drm_connector *connector,
6625 struct intel_load_detect_pipe *old)
6627 struct intel_encoder *intel_encoder =
6628 intel_attached_encoder(connector);
6629 struct drm_encoder *encoder = &intel_encoder->base;
6630 struct drm_crtc *crtc = encoder->crtc;
6632 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6633 connector->base.id, drm_get_connector_name(connector),
6634 encoder->base.id, drm_get_encoder_name(encoder));
6636 if (old->load_detect_temp) {
6637 to_intel_connector(connector)->new_encoder = NULL;
6638 intel_encoder->new_crtc = NULL;
6639 intel_set_mode(crtc, NULL, 0, 0, NULL);
6641 if (old->release_fb) {
6642 drm_framebuffer_unregister_private(old->release_fb);
6643 drm_framebuffer_unreference(old->release_fb);
6646 mutex_unlock(&crtc->mutex);
6650 /* Switch crtc and encoder back off if necessary */
6651 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6652 connector->funcs->dpms(connector, old->dpms_mode);
6654 mutex_unlock(&crtc->mutex);
6657 /* Returns the clock of the currently programmed mode of the given pipe. */
6658 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6660 struct drm_i915_private *dev_priv = dev->dev_private;
6661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6662 int pipe = intel_crtc->pipe;
6663 u32 dpll = I915_READ(DPLL(pipe));
6665 intel_clock_t clock;
6667 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6668 fp = I915_READ(FP0(pipe));
6670 fp = I915_READ(FP1(pipe));
6672 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6673 if (IS_PINEVIEW(dev)) {
6674 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6675 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6677 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6678 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6681 if (!IS_GEN2(dev)) {
6682 if (IS_PINEVIEW(dev))
6683 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6684 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6686 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6687 DPLL_FPA01_P1_POST_DIV_SHIFT);
6689 switch (dpll & DPLL_MODE_MASK) {
6690 case DPLLB_MODE_DAC_SERIAL:
6691 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6694 case DPLLB_MODE_LVDS:
6695 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6699 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6700 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6704 /* XXX: Handle the 100Mhz refclk */
6705 intel_clock(dev, 96000, &clock);
6707 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6710 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6711 DPLL_FPA01_P1_POST_DIV_SHIFT);
6714 if ((dpll & PLL_REF_INPUT_MASK) ==
6715 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6716 /* XXX: might not be 66MHz */
6717 intel_clock(dev, 66000, &clock);
6719 intel_clock(dev, 48000, &clock);
6721 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6724 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6725 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6727 if (dpll & PLL_P2_DIVIDE_BY_4)
6732 intel_clock(dev, 48000, &clock);
6736 /* XXX: It would be nice to validate the clocks, but we can't reuse
6737 * i830PllIsValid() because it relies on the xf86_config connector
6738 * configuration being accurate, which it isn't necessarily.
6744 /** Returns the currently programmed mode of the given pipe. */
6745 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6746 struct drm_crtc *crtc)
6748 struct drm_i915_private *dev_priv = dev->dev_private;
6749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6750 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6751 struct drm_display_mode *mode;
6752 int htot = I915_READ(HTOTAL(cpu_transcoder));
6753 int hsync = I915_READ(HSYNC(cpu_transcoder));
6754 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6755 int vsync = I915_READ(VSYNC(cpu_transcoder));
6757 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6761 mode->clock = intel_crtc_clock_get(dev, crtc);
6762 mode->hdisplay = (htot & 0xffff) + 1;
6763 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6764 mode->hsync_start = (hsync & 0xffff) + 1;
6765 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6766 mode->vdisplay = (vtot & 0xffff) + 1;
6767 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6768 mode->vsync_start = (vsync & 0xffff) + 1;
6769 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6771 drm_mode_set_name(mode);
6776 static void intel_increase_pllclock(struct drm_crtc *crtc)
6778 struct drm_device *dev = crtc->dev;
6779 drm_i915_private_t *dev_priv = dev->dev_private;
6780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6781 int pipe = intel_crtc->pipe;
6782 int dpll_reg = DPLL(pipe);
6785 if (HAS_PCH_SPLIT(dev))
6788 if (!dev_priv->lvds_downclock_avail)
6791 dpll = I915_READ(dpll_reg);
6792 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6793 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6795 assert_panel_unlocked(dev_priv, pipe);
6797 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6798 I915_WRITE(dpll_reg, dpll);
6799 intel_wait_for_vblank(dev, pipe);
6801 dpll = I915_READ(dpll_reg);
6802 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6803 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6807 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6809 struct drm_device *dev = crtc->dev;
6810 drm_i915_private_t *dev_priv = dev->dev_private;
6811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6813 if (HAS_PCH_SPLIT(dev))
6816 if (!dev_priv->lvds_downclock_avail)
6820 * Since this is called by a timer, we should never get here in
6823 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6824 int pipe = intel_crtc->pipe;
6825 int dpll_reg = DPLL(pipe);
6828 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6830 assert_panel_unlocked(dev_priv, pipe);
6832 dpll = I915_READ(dpll_reg);
6833 dpll |= DISPLAY_RATE_SELECT_FPA1;
6834 I915_WRITE(dpll_reg, dpll);
6835 intel_wait_for_vblank(dev, pipe);
6836 dpll = I915_READ(dpll_reg);
6837 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6838 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6843 void intel_mark_busy(struct drm_device *dev)
6845 i915_update_gfx_val(dev->dev_private);
6848 void intel_mark_idle(struct drm_device *dev)
6850 struct drm_crtc *crtc;
6852 if (!i915_powersave)
6855 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6859 intel_decrease_pllclock(crtc);
6863 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6865 struct drm_device *dev = obj->base.dev;
6866 struct drm_crtc *crtc;
6868 if (!i915_powersave)
6871 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6875 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6876 intel_increase_pllclock(crtc);
6880 static void intel_crtc_destroy(struct drm_crtc *crtc)
6882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6883 struct drm_device *dev = crtc->dev;
6884 struct intel_unpin_work *work;
6885 unsigned long flags;
6887 spin_lock_irqsave(&dev->event_lock, flags);
6888 work = intel_crtc->unpin_work;
6889 intel_crtc->unpin_work = NULL;
6890 spin_unlock_irqrestore(&dev->event_lock, flags);
6893 cancel_work_sync(&work->work);
6897 drm_crtc_cleanup(crtc);
6902 static void intel_unpin_work_fn(struct work_struct *__work)
6904 struct intel_unpin_work *work =
6905 container_of(__work, struct intel_unpin_work, work);
6906 struct drm_device *dev = work->crtc->dev;
6908 mutex_lock(&dev->struct_mutex);
6909 intel_unpin_fb_obj(work->old_fb_obj);
6910 drm_gem_object_unreference(&work->pending_flip_obj->base);
6911 drm_gem_object_unreference(&work->old_fb_obj->base);
6913 intel_update_fbc(dev);
6914 mutex_unlock(&dev->struct_mutex);
6916 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6917 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6922 static void do_intel_finish_page_flip(struct drm_device *dev,
6923 struct drm_crtc *crtc)
6925 drm_i915_private_t *dev_priv = dev->dev_private;
6926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6927 struct intel_unpin_work *work;
6928 struct drm_i915_gem_object *obj;
6929 unsigned long flags;
6931 /* Ignore early vblank irqs */
6932 if (intel_crtc == NULL)
6935 spin_lock_irqsave(&dev->event_lock, flags);
6936 work = intel_crtc->unpin_work;
6938 /* Ensure we don't miss a work->pending update ... */
6941 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6942 spin_unlock_irqrestore(&dev->event_lock, flags);
6946 /* and that the unpin work is consistent wrt ->pending. */
6949 intel_crtc->unpin_work = NULL;
6952 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6954 drm_vblank_put(dev, intel_crtc->pipe);
6956 spin_unlock_irqrestore(&dev->event_lock, flags);
6958 obj = work->old_fb_obj;
6960 wake_up_all(&dev_priv->pending_flip_queue);
6962 queue_work(dev_priv->wq, &work->work);
6964 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6967 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6969 drm_i915_private_t *dev_priv = dev->dev_private;
6970 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6972 do_intel_finish_page_flip(dev, crtc);
6975 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6977 drm_i915_private_t *dev_priv = dev->dev_private;
6978 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6980 do_intel_finish_page_flip(dev, crtc);
6983 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6985 drm_i915_private_t *dev_priv = dev->dev_private;
6986 struct intel_crtc *intel_crtc =
6987 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6988 unsigned long flags;
6990 /* NB: An MMIO update of the plane base pointer will also
6991 * generate a page-flip completion irq, i.e. every modeset
6992 * is also accompanied by a spurious intel_prepare_page_flip().
6994 spin_lock_irqsave(&dev->event_lock, flags);
6995 if (intel_crtc->unpin_work)
6996 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6997 spin_unlock_irqrestore(&dev->event_lock, flags);
7000 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7002 /* Ensure that the work item is consistent when activating it ... */
7004 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7005 /* and that it is marked active as soon as the irq could fire. */
7009 static int intel_gen2_queue_flip(struct drm_device *dev,
7010 struct drm_crtc *crtc,
7011 struct drm_framebuffer *fb,
7012 struct drm_i915_gem_object *obj)
7014 struct drm_i915_private *dev_priv = dev->dev_private;
7015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7017 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7020 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7024 ret = intel_ring_begin(ring, 6);
7028 /* Can't queue multiple flips, so wait for the previous
7029 * one to finish before executing the next.
7031 if (intel_crtc->plane)
7032 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7034 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7035 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7036 intel_ring_emit(ring, MI_NOOP);
7037 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7038 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7039 intel_ring_emit(ring, fb->pitches[0]);
7040 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7041 intel_ring_emit(ring, 0); /* aux display base address, unused */
7043 intel_mark_page_flip_active(intel_crtc);
7044 intel_ring_advance(ring);
7048 intel_unpin_fb_obj(obj);
7053 static int intel_gen3_queue_flip(struct drm_device *dev,
7054 struct drm_crtc *crtc,
7055 struct drm_framebuffer *fb,
7056 struct drm_i915_gem_object *obj)
7058 struct drm_i915_private *dev_priv = dev->dev_private;
7059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7061 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7064 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7068 ret = intel_ring_begin(ring, 6);
7072 if (intel_crtc->plane)
7073 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7075 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7076 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7077 intel_ring_emit(ring, MI_NOOP);
7078 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7079 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7080 intel_ring_emit(ring, fb->pitches[0]);
7081 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7082 intel_ring_emit(ring, MI_NOOP);
7084 intel_mark_page_flip_active(intel_crtc);
7085 intel_ring_advance(ring);
7089 intel_unpin_fb_obj(obj);
7094 static int intel_gen4_queue_flip(struct drm_device *dev,
7095 struct drm_crtc *crtc,
7096 struct drm_framebuffer *fb,
7097 struct drm_i915_gem_object *obj)
7099 struct drm_i915_private *dev_priv = dev->dev_private;
7100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7101 uint32_t pf, pipesrc;
7102 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7105 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7109 ret = intel_ring_begin(ring, 4);
7113 /* i965+ uses the linear or tiled offsets from the
7114 * Display Registers (which do not change across a page-flip)
7115 * so we need only reprogram the base address.
7117 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7118 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7119 intel_ring_emit(ring, fb->pitches[0]);
7120 intel_ring_emit(ring,
7121 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7124 /* XXX Enabling the panel-fitter across page-flip is so far
7125 * untested on non-native modes, so ignore it for now.
7126 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7129 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7130 intel_ring_emit(ring, pf | pipesrc);
7132 intel_mark_page_flip_active(intel_crtc);
7133 intel_ring_advance(ring);
7137 intel_unpin_fb_obj(obj);
7142 static int intel_gen6_queue_flip(struct drm_device *dev,
7143 struct drm_crtc *crtc,
7144 struct drm_framebuffer *fb,
7145 struct drm_i915_gem_object *obj)
7147 struct drm_i915_private *dev_priv = dev->dev_private;
7148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7149 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7150 uint32_t pf, pipesrc;
7153 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7157 ret = intel_ring_begin(ring, 4);
7161 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7162 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7163 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7164 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7166 /* Contrary to the suggestions in the documentation,
7167 * "Enable Panel Fitter" does not seem to be required when page
7168 * flipping with a non-native mode, and worse causes a normal
7170 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7173 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7174 intel_ring_emit(ring, pf | pipesrc);
7176 intel_mark_page_flip_active(intel_crtc);
7177 intel_ring_advance(ring);
7181 intel_unpin_fb_obj(obj);
7187 * On gen7 we currently use the blit ring because (in early silicon at least)
7188 * the render ring doesn't give us interrpts for page flip completion, which
7189 * means clients will hang after the first flip is queued. Fortunately the
7190 * blit ring generates interrupts properly, so use it instead.
7192 static int intel_gen7_queue_flip(struct drm_device *dev,
7193 struct drm_crtc *crtc,
7194 struct drm_framebuffer *fb,
7195 struct drm_i915_gem_object *obj)
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7199 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7200 uint32_t plane_bit = 0;
7203 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7207 switch(intel_crtc->plane) {
7209 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7212 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7215 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7218 WARN_ONCE(1, "unknown plane in flip command\n");
7223 ret = intel_ring_begin(ring, 4);
7227 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7228 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7229 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7230 intel_ring_emit(ring, (MI_NOOP));
7232 intel_mark_page_flip_active(intel_crtc);
7233 intel_ring_advance(ring);
7237 intel_unpin_fb_obj(obj);
7242 static int intel_default_queue_flip(struct drm_device *dev,
7243 struct drm_crtc *crtc,
7244 struct drm_framebuffer *fb,
7245 struct drm_i915_gem_object *obj)
7250 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7251 struct drm_framebuffer *fb,
7252 struct drm_pending_vblank_event *event)
7254 struct drm_device *dev = crtc->dev;
7255 struct drm_i915_private *dev_priv = dev->dev_private;
7256 struct intel_framebuffer *intel_fb;
7257 struct drm_i915_gem_object *obj;
7258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7259 struct intel_unpin_work *work;
7260 unsigned long flags;
7263 /* Can't change pixel format via MI display flips. */
7264 if (fb->pixel_format != crtc->fb->pixel_format)
7268 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7269 * Note that pitch changes could also affect these register.
7271 if (INTEL_INFO(dev)->gen > 3 &&
7272 (fb->offsets[0] != crtc->fb->offsets[0] ||
7273 fb->pitches[0] != crtc->fb->pitches[0]))
7276 work = kzalloc(sizeof *work, GFP_KERNEL);
7280 work->event = event;
7282 intel_fb = to_intel_framebuffer(crtc->fb);
7283 work->old_fb_obj = intel_fb->obj;
7284 INIT_WORK(&work->work, intel_unpin_work_fn);
7286 ret = drm_vblank_get(dev, intel_crtc->pipe);
7290 /* We borrow the event spin lock for protecting unpin_work */
7291 spin_lock_irqsave(&dev->event_lock, flags);
7292 if (intel_crtc->unpin_work) {
7293 spin_unlock_irqrestore(&dev->event_lock, flags);
7295 drm_vblank_put(dev, intel_crtc->pipe);
7297 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7300 intel_crtc->unpin_work = work;
7301 spin_unlock_irqrestore(&dev->event_lock, flags);
7303 intel_fb = to_intel_framebuffer(fb);
7304 obj = intel_fb->obj;
7306 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7307 flush_workqueue(dev_priv->wq);
7309 ret = i915_mutex_lock_interruptible(dev);
7313 /* Reference the objects for the scheduled work. */
7314 drm_gem_object_reference(&work->old_fb_obj->base);
7315 drm_gem_object_reference(&obj->base);
7319 work->pending_flip_obj = obj;
7321 work->enable_stall_check = true;
7323 atomic_inc(&intel_crtc->unpin_work_count);
7324 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7326 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7328 goto cleanup_pending;
7330 intel_disable_fbc(dev);
7331 intel_mark_fb_busy(obj);
7332 mutex_unlock(&dev->struct_mutex);
7334 trace_i915_flip_request(intel_crtc->plane, obj);
7339 atomic_dec(&intel_crtc->unpin_work_count);
7340 drm_gem_object_unreference(&work->old_fb_obj->base);
7341 drm_gem_object_unreference(&obj->base);
7342 mutex_unlock(&dev->struct_mutex);
7345 spin_lock_irqsave(&dev->event_lock, flags);
7346 intel_crtc->unpin_work = NULL;
7347 spin_unlock_irqrestore(&dev->event_lock, flags);
7349 drm_vblank_put(dev, intel_crtc->pipe);
7356 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7357 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7358 .load_lut = intel_crtc_load_lut,
7359 .disable = intel_crtc_noop,
7362 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7364 struct intel_encoder *other_encoder;
7365 struct drm_crtc *crtc = &encoder->new_crtc->base;
7370 list_for_each_entry(other_encoder,
7371 &crtc->dev->mode_config.encoder_list,
7374 if (&other_encoder->new_crtc->base != crtc ||
7375 encoder == other_encoder)
7384 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7385 struct drm_crtc *crtc)
7387 struct drm_device *dev;
7388 struct drm_crtc *tmp;
7391 WARN(!crtc, "checking null crtc?\n");
7395 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7401 if (encoder->possible_crtcs & crtc_mask)
7407 * intel_modeset_update_staged_output_state
7409 * Updates the staged output configuration state, e.g. after we've read out the
7412 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7414 struct intel_encoder *encoder;
7415 struct intel_connector *connector;
7417 list_for_each_entry(connector, &dev->mode_config.connector_list,
7419 connector->new_encoder =
7420 to_intel_encoder(connector->base.encoder);
7423 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7426 to_intel_crtc(encoder->base.crtc);
7431 * intel_modeset_commit_output_state
7433 * This function copies the stage display pipe configuration to the real one.
7435 static void intel_modeset_commit_output_state(struct drm_device *dev)
7437 struct intel_encoder *encoder;
7438 struct intel_connector *connector;
7440 list_for_each_entry(connector, &dev->mode_config.connector_list,
7442 connector->base.encoder = &connector->new_encoder->base;
7445 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7447 encoder->base.crtc = &encoder->new_crtc->base;
7451 static struct drm_display_mode *
7452 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7453 struct drm_display_mode *mode)
7455 struct drm_device *dev = crtc->dev;
7456 struct drm_display_mode *adjusted_mode;
7457 struct drm_encoder_helper_funcs *encoder_funcs;
7458 struct intel_encoder *encoder;
7460 adjusted_mode = drm_mode_duplicate(dev, mode);
7462 return ERR_PTR(-ENOMEM);
7464 /* Pass our mode to the connectors and the CRTC to give them a chance to
7465 * adjust it according to limitations or connector properties, and also
7466 * a chance to reject the mode entirely.
7468 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7471 if (&encoder->new_crtc->base != crtc)
7473 encoder_funcs = encoder->base.helper_private;
7474 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7476 DRM_DEBUG_KMS("Encoder fixup failed\n");
7481 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7482 DRM_DEBUG_KMS("CRTC fixup failed\n");
7485 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7487 return adjusted_mode;
7489 drm_mode_destroy(dev, adjusted_mode);
7490 return ERR_PTR(-EINVAL);
7493 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7494 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7496 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7497 unsigned *prepare_pipes, unsigned *disable_pipes)
7499 struct intel_crtc *intel_crtc;
7500 struct drm_device *dev = crtc->dev;
7501 struct intel_encoder *encoder;
7502 struct intel_connector *connector;
7503 struct drm_crtc *tmp_crtc;
7505 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7507 /* Check which crtcs have changed outputs connected to them, these need
7508 * to be part of the prepare_pipes mask. We don't (yet) support global
7509 * modeset across multiple crtcs, so modeset_pipes will only have one
7510 * bit set at most. */
7511 list_for_each_entry(connector, &dev->mode_config.connector_list,
7513 if (connector->base.encoder == &connector->new_encoder->base)
7516 if (connector->base.encoder) {
7517 tmp_crtc = connector->base.encoder->crtc;
7519 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7522 if (connector->new_encoder)
7524 1 << connector->new_encoder->new_crtc->pipe;
7527 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7529 if (encoder->base.crtc == &encoder->new_crtc->base)
7532 if (encoder->base.crtc) {
7533 tmp_crtc = encoder->base.crtc;
7535 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7538 if (encoder->new_crtc)
7539 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7542 /* Check for any pipes that will be fully disabled ... */
7543 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7547 /* Don't try to disable disabled crtcs. */
7548 if (!intel_crtc->base.enabled)
7551 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7553 if (encoder->new_crtc == intel_crtc)
7558 *disable_pipes |= 1 << intel_crtc->pipe;
7562 /* set_mode is also used to update properties on life display pipes. */
7563 intel_crtc = to_intel_crtc(crtc);
7565 *prepare_pipes |= 1 << intel_crtc->pipe;
7567 /* We only support modeset on one single crtc, hence we need to do that
7568 * only for the passed in crtc iff we change anything else than just
7571 * This is actually not true, to be fully compatible with the old crtc
7572 * helper we automatically disable _any_ output (i.e. doesn't need to be
7573 * connected to the crtc we're modesetting on) if it's disconnected.
7574 * Which is a rather nutty api (since changed the output configuration
7575 * without userspace's explicit request can lead to confusion), but
7576 * alas. Hence we currently need to modeset on all pipes we prepare. */
7578 *modeset_pipes = *prepare_pipes;
7580 /* ... and mask these out. */
7581 *modeset_pipes &= ~(*disable_pipes);
7582 *prepare_pipes &= ~(*disable_pipes);
7585 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7587 struct drm_encoder *encoder;
7588 struct drm_device *dev = crtc->dev;
7590 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7591 if (encoder->crtc == crtc)
7598 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7600 struct intel_encoder *intel_encoder;
7601 struct intel_crtc *intel_crtc;
7602 struct drm_connector *connector;
7604 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7606 if (!intel_encoder->base.crtc)
7609 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7611 if (prepare_pipes & (1 << intel_crtc->pipe))
7612 intel_encoder->connectors_active = false;
7615 intel_modeset_commit_output_state(dev);
7617 /* Update computed state. */
7618 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7620 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7623 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7624 if (!connector->encoder || !connector->encoder->crtc)
7627 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7629 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7630 struct drm_property *dpms_property =
7631 dev->mode_config.dpms_property;
7633 connector->dpms = DRM_MODE_DPMS_ON;
7634 drm_object_property_set_value(&connector->base,
7638 intel_encoder = to_intel_encoder(connector->encoder);
7639 intel_encoder->connectors_active = true;
7645 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7646 list_for_each_entry((intel_crtc), \
7647 &(dev)->mode_config.crtc_list, \
7649 if (mask & (1 <<(intel_crtc)->pipe)) \
7652 intel_modeset_check_state(struct drm_device *dev)
7654 struct intel_crtc *crtc;
7655 struct intel_encoder *encoder;
7656 struct intel_connector *connector;
7658 list_for_each_entry(connector, &dev->mode_config.connector_list,
7660 /* This also checks the encoder/connector hw state with the
7661 * ->get_hw_state callbacks. */
7662 intel_connector_check_state(connector);
7664 WARN(&connector->new_encoder->base != connector->base.encoder,
7665 "connector's staged encoder doesn't match current encoder\n");
7668 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7670 bool enabled = false;
7671 bool active = false;
7672 enum pipe pipe, tracked_pipe;
7674 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7675 encoder->base.base.id,
7676 drm_get_encoder_name(&encoder->base));
7678 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7679 "encoder's stage crtc doesn't match current crtc\n");
7680 WARN(encoder->connectors_active && !encoder->base.crtc,
7681 "encoder's active_connectors set, but no crtc\n");
7683 list_for_each_entry(connector, &dev->mode_config.connector_list,
7685 if (connector->base.encoder != &encoder->base)
7688 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7691 WARN(!!encoder->base.crtc != enabled,
7692 "encoder's enabled state mismatch "
7693 "(expected %i, found %i)\n",
7694 !!encoder->base.crtc, enabled);
7695 WARN(active && !encoder->base.crtc,
7696 "active encoder with no crtc\n");
7698 WARN(encoder->connectors_active != active,
7699 "encoder's computed active state doesn't match tracked active state "
7700 "(expected %i, found %i)\n", active, encoder->connectors_active);
7702 active = encoder->get_hw_state(encoder, &pipe);
7703 WARN(active != encoder->connectors_active,
7704 "encoder's hw state doesn't match sw tracking "
7705 "(expected %i, found %i)\n",
7706 encoder->connectors_active, active);
7708 if (!encoder->base.crtc)
7711 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7712 WARN(active && pipe != tracked_pipe,
7713 "active encoder's pipe doesn't match"
7714 "(expected %i, found %i)\n",
7715 tracked_pipe, pipe);
7719 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7721 bool enabled = false;
7722 bool active = false;
7724 DRM_DEBUG_KMS("[CRTC:%d]\n",
7725 crtc->base.base.id);
7727 WARN(crtc->active && !crtc->base.enabled,
7728 "active crtc, but not enabled in sw tracking\n");
7730 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7732 if (encoder->base.crtc != &crtc->base)
7735 if (encoder->connectors_active)
7738 WARN(active != crtc->active,
7739 "crtc's computed active state doesn't match tracked active state "
7740 "(expected %i, found %i)\n", active, crtc->active);
7741 WARN(enabled != crtc->base.enabled,
7742 "crtc's computed enabled state doesn't match tracked enabled state "
7743 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7745 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7749 int intel_set_mode(struct drm_crtc *crtc,
7750 struct drm_display_mode *mode,
7751 int x, int y, struct drm_framebuffer *fb)
7753 struct drm_device *dev = crtc->dev;
7754 drm_i915_private_t *dev_priv = dev->dev_private;
7755 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
7756 struct intel_crtc *intel_crtc;
7757 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7760 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7763 saved_hwmode = saved_mode + 1;
7765 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7766 &prepare_pipes, &disable_pipes);
7768 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7769 modeset_pipes, prepare_pipes, disable_pipes);
7771 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7772 intel_crtc_disable(&intel_crtc->base);
7774 *saved_hwmode = crtc->hwmode;
7775 *saved_mode = crtc->mode;
7777 /* Hack: Because we don't (yet) support global modeset on multiple
7778 * crtcs, we don't keep track of the new mode for more than one crtc.
7779 * Hence simply check whether any bit is set in modeset_pipes in all the
7780 * pieces of code that are not yet converted to deal with mutliple crtcs
7781 * changing their mode at the same time. */
7782 adjusted_mode = NULL;
7783 if (modeset_pipes) {
7784 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7785 if (IS_ERR(adjusted_mode)) {
7786 ret = PTR_ERR(adjusted_mode);
7791 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7792 if (intel_crtc->base.enabled)
7793 dev_priv->display.crtc_disable(&intel_crtc->base);
7796 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7797 * to set it here already despite that we pass it down the callchain.
7802 /* Only after disabling all output pipelines that will be changed can we
7803 * update the the output configuration. */
7804 intel_modeset_update_state(dev, prepare_pipes);
7806 if (dev_priv->display.modeset_global_resources)
7807 dev_priv->display.modeset_global_resources(dev);
7809 /* Set up the DPLL and any encoders state that needs to adjust or depend
7812 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7813 ret = intel_crtc_mode_set(&intel_crtc->base,
7814 mode, adjusted_mode,
7820 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7821 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7822 dev_priv->display.crtc_enable(&intel_crtc->base);
7824 if (modeset_pipes) {
7825 /* Store real post-adjustment hardware mode. */
7826 crtc->hwmode = *adjusted_mode;
7828 /* Calculate and store various constants which
7829 * are later needed by vblank and swap-completion
7830 * timestamping. They are derived from true hwmode.
7832 drm_calc_timestamping_constants(crtc);
7835 /* FIXME: add subpixel order */
7837 drm_mode_destroy(dev, adjusted_mode);
7838 if (ret && crtc->enabled) {
7839 crtc->hwmode = *saved_hwmode;
7840 crtc->mode = *saved_mode;
7842 intel_modeset_check_state(dev);
7850 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7852 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7855 #undef for_each_intel_crtc_masked
7857 static void intel_set_config_free(struct intel_set_config *config)
7862 kfree(config->save_connector_encoders);
7863 kfree(config->save_encoder_crtcs);
7867 static int intel_set_config_save_state(struct drm_device *dev,
7868 struct intel_set_config *config)
7870 struct drm_encoder *encoder;
7871 struct drm_connector *connector;
7874 config->save_encoder_crtcs =
7875 kcalloc(dev->mode_config.num_encoder,
7876 sizeof(struct drm_crtc *), GFP_KERNEL);
7877 if (!config->save_encoder_crtcs)
7880 config->save_connector_encoders =
7881 kcalloc(dev->mode_config.num_connector,
7882 sizeof(struct drm_encoder *), GFP_KERNEL);
7883 if (!config->save_connector_encoders)
7886 /* Copy data. Note that driver private data is not affected.
7887 * Should anything bad happen only the expected state is
7888 * restored, not the drivers personal bookkeeping.
7891 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7892 config->save_encoder_crtcs[count++] = encoder->crtc;
7896 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7897 config->save_connector_encoders[count++] = connector->encoder;
7903 static void intel_set_config_restore_state(struct drm_device *dev,
7904 struct intel_set_config *config)
7906 struct intel_encoder *encoder;
7907 struct intel_connector *connector;
7911 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7913 to_intel_crtc(config->save_encoder_crtcs[count++]);
7917 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7918 connector->new_encoder =
7919 to_intel_encoder(config->save_connector_encoders[count++]);
7924 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7925 struct intel_set_config *config)
7928 /* We should be able to check here if the fb has the same properties
7929 * and then just flip_or_move it */
7930 if (set->crtc->fb != set->fb) {
7931 /* If we have no fb then treat it as a full mode set */
7932 if (set->crtc->fb == NULL) {
7933 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7934 config->mode_changed = true;
7935 } else if (set->fb == NULL) {
7936 config->mode_changed = true;
7937 } else if (set->fb->depth != set->crtc->fb->depth) {
7938 config->mode_changed = true;
7939 } else if (set->fb->bits_per_pixel !=
7940 set->crtc->fb->bits_per_pixel) {
7941 config->mode_changed = true;
7943 config->fb_changed = true;
7946 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7947 config->fb_changed = true;
7949 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7950 DRM_DEBUG_KMS("modes are different, full mode set\n");
7951 drm_mode_debug_printmodeline(&set->crtc->mode);
7952 drm_mode_debug_printmodeline(set->mode);
7953 config->mode_changed = true;
7958 intel_modeset_stage_output_state(struct drm_device *dev,
7959 struct drm_mode_set *set,
7960 struct intel_set_config *config)
7962 struct drm_crtc *new_crtc;
7963 struct intel_connector *connector;
7964 struct intel_encoder *encoder;
7967 /* The upper layers ensure that we either disable a crtc or have a list
7968 * of connectors. For paranoia, double-check this. */
7969 WARN_ON(!set->fb && (set->num_connectors != 0));
7970 WARN_ON(set->fb && (set->num_connectors == 0));
7973 list_for_each_entry(connector, &dev->mode_config.connector_list,
7975 /* Otherwise traverse passed in connector list and get encoders
7977 for (ro = 0; ro < set->num_connectors; ro++) {
7978 if (set->connectors[ro] == &connector->base) {
7979 connector->new_encoder = connector->encoder;
7984 /* If we disable the crtc, disable all its connectors. Also, if
7985 * the connector is on the changing crtc but not on the new
7986 * connector list, disable it. */
7987 if ((!set->fb || ro == set->num_connectors) &&
7988 connector->base.encoder &&
7989 connector->base.encoder->crtc == set->crtc) {
7990 connector->new_encoder = NULL;
7992 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7993 connector->base.base.id,
7994 drm_get_connector_name(&connector->base));
7998 if (&connector->new_encoder->base != connector->base.encoder) {
7999 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8000 config->mode_changed = true;
8003 /* connector->new_encoder is now updated for all connectors. */
8005 /* Update crtc of enabled connectors. */
8007 list_for_each_entry(connector, &dev->mode_config.connector_list,
8009 if (!connector->new_encoder)
8012 new_crtc = connector->new_encoder->base.crtc;
8014 for (ro = 0; ro < set->num_connectors; ro++) {
8015 if (set->connectors[ro] == &connector->base)
8016 new_crtc = set->crtc;
8019 /* Make sure the new CRTC will work with the encoder */
8020 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8024 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8026 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8027 connector->base.base.id,
8028 drm_get_connector_name(&connector->base),
8032 /* Check for any encoders that needs to be disabled. */
8033 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8035 list_for_each_entry(connector,
8036 &dev->mode_config.connector_list,
8038 if (connector->new_encoder == encoder) {
8039 WARN_ON(!connector->new_encoder->new_crtc);
8044 encoder->new_crtc = NULL;
8046 /* Only now check for crtc changes so we don't miss encoders
8047 * that will be disabled. */
8048 if (&encoder->new_crtc->base != encoder->base.crtc) {
8049 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8050 config->mode_changed = true;
8053 /* Now we've also updated encoder->new_crtc for all encoders. */
8058 static int intel_crtc_set_config(struct drm_mode_set *set)
8060 struct drm_device *dev;
8061 struct drm_mode_set save_set;
8062 struct intel_set_config *config;
8067 BUG_ON(!set->crtc->helper_private);
8072 /* The fb helper likes to play gross jokes with ->mode_set_config.
8073 * Unfortunately the crtc helper doesn't do much at all for this case,
8074 * so we have to cope with this madness until the fb helper is fixed up. */
8075 if (set->fb && set->num_connectors == 0)
8079 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8080 set->crtc->base.id, set->fb->base.id,
8081 (int)set->num_connectors, set->x, set->y);
8083 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8086 dev = set->crtc->dev;
8089 config = kzalloc(sizeof(*config), GFP_KERNEL);
8093 ret = intel_set_config_save_state(dev, config);
8097 save_set.crtc = set->crtc;
8098 save_set.mode = &set->crtc->mode;
8099 save_set.x = set->crtc->x;
8100 save_set.y = set->crtc->y;
8101 save_set.fb = set->crtc->fb;
8103 /* Compute whether we need a full modeset, only an fb base update or no
8104 * change at all. In the future we might also check whether only the
8105 * mode changed, e.g. for LVDS where we only change the panel fitter in
8107 intel_set_config_compute_mode_changes(set, config);
8109 ret = intel_modeset_stage_output_state(dev, set, config);
8113 if (config->mode_changed) {
8115 DRM_DEBUG_KMS("attempting to set mode from"
8117 drm_mode_debug_printmodeline(set->mode);
8120 ret = intel_set_mode(set->crtc, set->mode,
8121 set->x, set->y, set->fb);
8123 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8124 set->crtc->base.id, ret);
8127 } else if (config->fb_changed) {
8128 ret = intel_pipe_set_base(set->crtc,
8129 set->x, set->y, set->fb);
8132 intel_set_config_free(config);
8137 intel_set_config_restore_state(dev, config);
8139 /* Try to restore the config */
8140 if (config->mode_changed &&
8141 intel_set_mode(save_set.crtc, save_set.mode,
8142 save_set.x, save_set.y, save_set.fb))
8143 DRM_ERROR("failed to restore config after modeset failure\n");
8146 intel_set_config_free(config);
8150 static const struct drm_crtc_funcs intel_crtc_funcs = {
8151 .cursor_set = intel_crtc_cursor_set,
8152 .cursor_move = intel_crtc_cursor_move,
8153 .gamma_set = intel_crtc_gamma_set,
8154 .set_config = intel_crtc_set_config,
8155 .destroy = intel_crtc_destroy,
8156 .page_flip = intel_crtc_page_flip,
8159 static void intel_cpu_pll_init(struct drm_device *dev)
8162 intel_ddi_pll_init(dev);
8165 static void intel_pch_pll_init(struct drm_device *dev)
8167 drm_i915_private_t *dev_priv = dev->dev_private;
8170 if (dev_priv->num_pch_pll == 0) {
8171 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8175 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8176 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8177 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8178 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8182 static void intel_crtc_init(struct drm_device *dev, int pipe)
8184 drm_i915_private_t *dev_priv = dev->dev_private;
8185 struct intel_crtc *intel_crtc;
8188 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8189 if (intel_crtc == NULL)
8192 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8194 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8195 for (i = 0; i < 256; i++) {
8196 intel_crtc->lut_r[i] = i;
8197 intel_crtc->lut_g[i] = i;
8198 intel_crtc->lut_b[i] = i;
8201 /* Swap pipes & planes for FBC on pre-965 */
8202 intel_crtc->pipe = pipe;
8203 intel_crtc->plane = pipe;
8204 intel_crtc->cpu_transcoder = pipe;
8205 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8206 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8207 intel_crtc->plane = !pipe;
8210 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8211 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8212 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8213 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8215 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8217 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8220 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8221 struct drm_file *file)
8223 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8224 struct drm_mode_object *drmmode_obj;
8225 struct intel_crtc *crtc;
8227 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8230 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8231 DRM_MODE_OBJECT_CRTC);
8234 DRM_ERROR("no such CRTC id\n");
8238 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8239 pipe_from_crtc_id->pipe = crtc->pipe;
8244 static int intel_encoder_clones(struct intel_encoder *encoder)
8246 struct drm_device *dev = encoder->base.dev;
8247 struct intel_encoder *source_encoder;
8251 list_for_each_entry(source_encoder,
8252 &dev->mode_config.encoder_list, base.head) {
8254 if (encoder == source_encoder)
8255 index_mask |= (1 << entry);
8257 /* Intel hw has only one MUX where enocoders could be cloned. */
8258 if (encoder->cloneable && source_encoder->cloneable)
8259 index_mask |= (1 << entry);
8267 static bool has_edp_a(struct drm_device *dev)
8269 struct drm_i915_private *dev_priv = dev->dev_private;
8271 if (!IS_MOBILE(dev))
8274 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8278 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8284 static void intel_setup_outputs(struct drm_device *dev)
8286 struct drm_i915_private *dev_priv = dev->dev_private;
8287 struct intel_encoder *encoder;
8288 bool dpd_is_edp = false;
8291 has_lvds = intel_lvds_init(dev);
8292 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8293 /* disable the panel fitter on everything but LVDS */
8294 I915_WRITE(PFIT_CONTROL, 0);
8297 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8298 intel_crt_init(dev);
8303 /* Haswell uses DDI functions to detect digital outputs */
8304 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8305 /* DDI A only supports eDP */
8307 intel_ddi_init(dev, PORT_A);
8309 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8311 found = I915_READ(SFUSE_STRAP);
8313 if (found & SFUSE_STRAP_DDIB_DETECTED)
8314 intel_ddi_init(dev, PORT_B);
8315 if (found & SFUSE_STRAP_DDIC_DETECTED)
8316 intel_ddi_init(dev, PORT_C);
8317 if (found & SFUSE_STRAP_DDID_DETECTED)
8318 intel_ddi_init(dev, PORT_D);
8319 } else if (HAS_PCH_SPLIT(dev)) {
8321 dpd_is_edp = intel_dpd_is_edp(dev);
8324 intel_dp_init(dev, DP_A, PORT_A);
8326 if (I915_READ(HDMIB) & PORT_DETECTED) {
8327 /* PCH SDVOB multiplex with HDMIB */
8328 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8330 intel_hdmi_init(dev, HDMIB, PORT_B);
8331 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8332 intel_dp_init(dev, PCH_DP_B, PORT_B);
8335 if (I915_READ(HDMIC) & PORT_DETECTED)
8336 intel_hdmi_init(dev, HDMIC, PORT_C);
8338 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8339 intel_hdmi_init(dev, HDMID, PORT_D);
8341 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8342 intel_dp_init(dev, PCH_DP_C, PORT_C);
8344 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8345 intel_dp_init(dev, PCH_DP_D, PORT_D);
8346 } else if (IS_VALLEYVIEW(dev)) {
8347 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8348 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8349 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8351 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8352 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8353 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8354 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8357 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8358 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
8360 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8363 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8364 DRM_DEBUG_KMS("probing SDVOB\n");
8365 found = intel_sdvo_init(dev, SDVOB, true);
8366 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8367 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8368 intel_hdmi_init(dev, SDVOB, PORT_B);
8371 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8372 DRM_DEBUG_KMS("probing DP_B\n");
8373 intel_dp_init(dev, DP_B, PORT_B);
8377 /* Before G4X SDVOC doesn't have its own detect register */
8379 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8380 DRM_DEBUG_KMS("probing SDVOC\n");
8381 found = intel_sdvo_init(dev, SDVOC, false);
8384 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8386 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8387 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8388 intel_hdmi_init(dev, SDVOC, PORT_C);
8390 if (SUPPORTS_INTEGRATED_DP(dev)) {
8391 DRM_DEBUG_KMS("probing DP_C\n");
8392 intel_dp_init(dev, DP_C, PORT_C);
8396 if (SUPPORTS_INTEGRATED_DP(dev) &&
8397 (I915_READ(DP_D) & DP_DETECTED)) {
8398 DRM_DEBUG_KMS("probing DP_D\n");
8399 intel_dp_init(dev, DP_D, PORT_D);
8401 } else if (IS_GEN2(dev))
8402 intel_dvo_init(dev);
8404 if (SUPPORTS_TV(dev))
8407 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8408 encoder->base.possible_crtcs = encoder->crtc_mask;
8409 encoder->base.possible_clones =
8410 intel_encoder_clones(encoder);
8413 intel_init_pch_refclk(dev);
8415 drm_helper_move_panel_connectors_to_head(dev);
8418 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8420 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8422 drm_framebuffer_cleanup(fb);
8423 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8428 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8429 struct drm_file *file,
8430 unsigned int *handle)
8432 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8433 struct drm_i915_gem_object *obj = intel_fb->obj;
8435 return drm_gem_handle_create(file, &obj->base, handle);
8438 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8439 .destroy = intel_user_framebuffer_destroy,
8440 .create_handle = intel_user_framebuffer_create_handle,
8443 int intel_framebuffer_init(struct drm_device *dev,
8444 struct intel_framebuffer *intel_fb,
8445 struct drm_mode_fb_cmd2 *mode_cmd,
8446 struct drm_i915_gem_object *obj)
8450 if (obj->tiling_mode == I915_TILING_Y) {
8451 DRM_DEBUG("hardware does not support tiling Y\n");
8455 if (mode_cmd->pitches[0] & 63) {
8456 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8457 mode_cmd->pitches[0]);
8461 /* FIXME <= Gen4 stride limits are bit unclear */
8462 if (mode_cmd->pitches[0] > 32768) {
8463 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8464 mode_cmd->pitches[0]);
8468 if (obj->tiling_mode != I915_TILING_NONE &&
8469 mode_cmd->pitches[0] != obj->stride) {
8470 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8471 mode_cmd->pitches[0], obj->stride);
8475 /* Reject formats not supported by any plane early. */
8476 switch (mode_cmd->pixel_format) {
8478 case DRM_FORMAT_RGB565:
8479 case DRM_FORMAT_XRGB8888:
8480 case DRM_FORMAT_ARGB8888:
8482 case DRM_FORMAT_XRGB1555:
8483 case DRM_FORMAT_ARGB1555:
8484 if (INTEL_INFO(dev)->gen > 3) {
8485 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8489 case DRM_FORMAT_XBGR8888:
8490 case DRM_FORMAT_ABGR8888:
8491 case DRM_FORMAT_XRGB2101010:
8492 case DRM_FORMAT_ARGB2101010:
8493 case DRM_FORMAT_XBGR2101010:
8494 case DRM_FORMAT_ABGR2101010:
8495 if (INTEL_INFO(dev)->gen < 4) {
8496 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8500 case DRM_FORMAT_YUYV:
8501 case DRM_FORMAT_UYVY:
8502 case DRM_FORMAT_YVYU:
8503 case DRM_FORMAT_VYUY:
8504 if (INTEL_INFO(dev)->gen < 5) {
8505 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8510 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8514 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8515 if (mode_cmd->offsets[0] != 0)
8518 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8519 intel_fb->obj = obj;
8521 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8523 DRM_ERROR("framebuffer init failed %d\n", ret);
8530 static struct drm_framebuffer *
8531 intel_user_framebuffer_create(struct drm_device *dev,
8532 struct drm_file *filp,
8533 struct drm_mode_fb_cmd2 *mode_cmd)
8535 struct drm_i915_gem_object *obj;
8537 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8538 mode_cmd->handles[0]));
8539 if (&obj->base == NULL)
8540 return ERR_PTR(-ENOENT);
8542 return intel_framebuffer_create(dev, mode_cmd, obj);
8545 static const struct drm_mode_config_funcs intel_mode_funcs = {
8546 .fb_create = intel_user_framebuffer_create,
8547 .output_poll_changed = intel_fb_output_poll_changed,
8550 /* Set up chip specific display functions */
8551 static void intel_init_display(struct drm_device *dev)
8553 struct drm_i915_private *dev_priv = dev->dev_private;
8555 /* We always want a DPMS function */
8557 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8558 dev_priv->display.crtc_enable = haswell_crtc_enable;
8559 dev_priv->display.crtc_disable = haswell_crtc_disable;
8560 dev_priv->display.off = haswell_crtc_off;
8561 dev_priv->display.update_plane = ironlake_update_plane;
8562 } else if (HAS_PCH_SPLIT(dev)) {
8563 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8564 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8565 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8566 dev_priv->display.off = ironlake_crtc_off;
8567 dev_priv->display.update_plane = ironlake_update_plane;
8569 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8570 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8571 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8572 dev_priv->display.off = i9xx_crtc_off;
8573 dev_priv->display.update_plane = i9xx_update_plane;
8576 /* Returns the core display clock speed */
8577 if (IS_VALLEYVIEW(dev))
8578 dev_priv->display.get_display_clock_speed =
8579 valleyview_get_display_clock_speed;
8580 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8581 dev_priv->display.get_display_clock_speed =
8582 i945_get_display_clock_speed;
8583 else if (IS_I915G(dev))
8584 dev_priv->display.get_display_clock_speed =
8585 i915_get_display_clock_speed;
8586 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8587 dev_priv->display.get_display_clock_speed =
8588 i9xx_misc_get_display_clock_speed;
8589 else if (IS_I915GM(dev))
8590 dev_priv->display.get_display_clock_speed =
8591 i915gm_get_display_clock_speed;
8592 else if (IS_I865G(dev))
8593 dev_priv->display.get_display_clock_speed =
8594 i865_get_display_clock_speed;
8595 else if (IS_I85X(dev))
8596 dev_priv->display.get_display_clock_speed =
8597 i855_get_display_clock_speed;
8599 dev_priv->display.get_display_clock_speed =
8600 i830_get_display_clock_speed;
8602 if (HAS_PCH_SPLIT(dev)) {
8604 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8605 dev_priv->display.write_eld = ironlake_write_eld;
8606 } else if (IS_GEN6(dev)) {
8607 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8608 dev_priv->display.write_eld = ironlake_write_eld;
8609 } else if (IS_IVYBRIDGE(dev)) {
8610 /* FIXME: detect B0+ stepping and use auto training */
8611 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8612 dev_priv->display.write_eld = ironlake_write_eld;
8613 dev_priv->display.modeset_global_resources =
8614 ivb_modeset_global_resources;
8615 } else if (IS_HASWELL(dev)) {
8616 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8617 dev_priv->display.write_eld = haswell_write_eld;
8618 dev_priv->display.modeset_global_resources =
8619 haswell_modeset_global_resources;
8621 } else if (IS_G4X(dev)) {
8622 dev_priv->display.write_eld = g4x_write_eld;
8625 /* Default just returns -ENODEV to indicate unsupported */
8626 dev_priv->display.queue_flip = intel_default_queue_flip;
8628 switch (INTEL_INFO(dev)->gen) {
8630 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8634 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8639 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8643 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8646 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8652 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8653 * resume, or other times. This quirk makes sure that's the case for
8656 static void quirk_pipea_force(struct drm_device *dev)
8658 struct drm_i915_private *dev_priv = dev->dev_private;
8660 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8661 DRM_INFO("applying pipe a force quirk\n");
8665 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8667 static void quirk_ssc_force_disable(struct drm_device *dev)
8669 struct drm_i915_private *dev_priv = dev->dev_private;
8670 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8671 DRM_INFO("applying lvds SSC disable quirk\n");
8675 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8678 static void quirk_invert_brightness(struct drm_device *dev)
8680 struct drm_i915_private *dev_priv = dev->dev_private;
8681 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8682 DRM_INFO("applying inverted panel brightness quirk\n");
8685 struct intel_quirk {
8687 int subsystem_vendor;
8688 int subsystem_device;
8689 void (*hook)(struct drm_device *dev);
8692 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8693 struct intel_dmi_quirk {
8694 void (*hook)(struct drm_device *dev);
8695 const struct dmi_system_id (*dmi_id_list)[];
8698 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8700 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8704 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8706 .dmi_id_list = &(const struct dmi_system_id[]) {
8708 .callback = intel_dmi_reverse_brightness,
8709 .ident = "NCR Corporation",
8710 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8711 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8714 { } /* terminating entry */
8716 .hook = quirk_invert_brightness,
8720 static struct intel_quirk intel_quirks[] = {
8721 /* HP Mini needs pipe A force quirk (LP: #322104) */
8722 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8724 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8725 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8727 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8728 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8730 /* 830/845 need to leave pipe A & dpll A up */
8731 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8732 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8734 /* Lenovo U160 cannot use SSC on LVDS */
8735 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8737 /* Sony Vaio Y cannot use SSC on LVDS */
8738 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8740 /* Acer Aspire 5734Z must invert backlight brightness */
8741 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8743 /* Acer/eMachines G725 */
8744 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8746 /* Acer/eMachines e725 */
8747 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8749 /* Acer/Packard Bell NCL20 */
8750 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8752 /* Acer Aspire 4736Z */
8753 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8756 static void intel_init_quirks(struct drm_device *dev)
8758 struct pci_dev *d = dev->pdev;
8761 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8762 struct intel_quirk *q = &intel_quirks[i];
8764 if (d->device == q->device &&
8765 (d->subsystem_vendor == q->subsystem_vendor ||
8766 q->subsystem_vendor == PCI_ANY_ID) &&
8767 (d->subsystem_device == q->subsystem_device ||
8768 q->subsystem_device == PCI_ANY_ID))
8771 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8772 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8773 intel_dmi_quirks[i].hook(dev);
8777 /* Disable the VGA plane that we never use */
8778 static void i915_disable_vga(struct drm_device *dev)
8780 struct drm_i915_private *dev_priv = dev->dev_private;
8782 u32 vga_reg = i915_vgacntrl_reg(dev);
8784 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8785 outb(SR01, VGA_SR_INDEX);
8786 sr1 = inb(VGA_SR_DATA);
8787 outb(sr1 | 1<<5, VGA_SR_DATA);
8788 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8791 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8792 POSTING_READ(vga_reg);
8795 void intel_modeset_init_hw(struct drm_device *dev)
8797 intel_init_power_well(dev);
8799 intel_prepare_ddi(dev);
8801 intel_init_clock_gating(dev);
8803 mutex_lock(&dev->struct_mutex);
8804 intel_enable_gt_powersave(dev);
8805 mutex_unlock(&dev->struct_mutex);
8808 void intel_modeset_init(struct drm_device *dev)
8810 struct drm_i915_private *dev_priv = dev->dev_private;
8813 drm_mode_config_init(dev);
8815 dev->mode_config.min_width = 0;
8816 dev->mode_config.min_height = 0;
8818 dev->mode_config.preferred_depth = 24;
8819 dev->mode_config.prefer_shadow = 1;
8821 dev->mode_config.funcs = &intel_mode_funcs;
8823 intel_init_quirks(dev);
8827 intel_init_display(dev);
8830 dev->mode_config.max_width = 2048;
8831 dev->mode_config.max_height = 2048;
8832 } else if (IS_GEN3(dev)) {
8833 dev->mode_config.max_width = 4096;
8834 dev->mode_config.max_height = 4096;
8836 dev->mode_config.max_width = 8192;
8837 dev->mode_config.max_height = 8192;
8839 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8841 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8842 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8844 for (i = 0; i < dev_priv->num_pipe; i++) {
8845 intel_crtc_init(dev, i);
8846 ret = intel_plane_init(dev, i);
8848 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8851 intel_cpu_pll_init(dev);
8852 intel_pch_pll_init(dev);
8854 /* Just disable it once at startup */
8855 i915_disable_vga(dev);
8856 intel_setup_outputs(dev);
8858 /* Just in case the BIOS is doing something questionable. */
8859 intel_disable_fbc(dev);
8863 intel_connector_break_all_links(struct intel_connector *connector)
8865 connector->base.dpms = DRM_MODE_DPMS_OFF;
8866 connector->base.encoder = NULL;
8867 connector->encoder->connectors_active = false;
8868 connector->encoder->base.crtc = NULL;
8871 static void intel_enable_pipe_a(struct drm_device *dev)
8873 struct intel_connector *connector;
8874 struct drm_connector *crt = NULL;
8875 struct intel_load_detect_pipe load_detect_temp;
8877 /* We can't just switch on the pipe A, we need to set things up with a
8878 * proper mode and output configuration. As a gross hack, enable pipe A
8879 * by enabling the load detect pipe once. */
8880 list_for_each_entry(connector,
8881 &dev->mode_config.connector_list,
8883 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8884 crt = &connector->base;
8892 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8893 intel_release_load_detect_pipe(crt, &load_detect_temp);
8899 intel_check_plane_mapping(struct intel_crtc *crtc)
8901 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8904 if (dev_priv->num_pipe == 1)
8907 reg = DSPCNTR(!crtc->plane);
8908 val = I915_READ(reg);
8910 if ((val & DISPLAY_PLANE_ENABLE) &&
8911 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8917 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8919 struct drm_device *dev = crtc->base.dev;
8920 struct drm_i915_private *dev_priv = dev->dev_private;
8923 /* Clear any frame start delays used for debugging left by the BIOS */
8924 reg = PIPECONF(crtc->cpu_transcoder);
8925 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8927 /* We need to sanitize the plane -> pipe mapping first because this will
8928 * disable the crtc (and hence change the state) if it is wrong. Note
8929 * that gen4+ has a fixed plane -> pipe mapping. */
8930 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8931 struct intel_connector *connector;
8934 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8935 crtc->base.base.id);
8937 /* Pipe has the wrong plane attached and the plane is active.
8938 * Temporarily change the plane mapping and disable everything
8940 plane = crtc->plane;
8941 crtc->plane = !plane;
8942 dev_priv->display.crtc_disable(&crtc->base);
8943 crtc->plane = plane;
8945 /* ... and break all links. */
8946 list_for_each_entry(connector, &dev->mode_config.connector_list,
8948 if (connector->encoder->base.crtc != &crtc->base)
8951 intel_connector_break_all_links(connector);
8954 WARN_ON(crtc->active);
8955 crtc->base.enabled = false;
8958 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8959 crtc->pipe == PIPE_A && !crtc->active) {
8960 /* BIOS forgot to enable pipe A, this mostly happens after
8961 * resume. Force-enable the pipe to fix this, the update_dpms
8962 * call below we restore the pipe to the right state, but leave
8963 * the required bits on. */
8964 intel_enable_pipe_a(dev);
8967 /* Adjust the state of the output pipe according to whether we
8968 * have active connectors/encoders. */
8969 intel_crtc_update_dpms(&crtc->base);
8971 if (crtc->active != crtc->base.enabled) {
8972 struct intel_encoder *encoder;
8974 /* This can happen either due to bugs in the get_hw_state
8975 * functions or because the pipe is force-enabled due to the
8977 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8979 crtc->base.enabled ? "enabled" : "disabled",
8980 crtc->active ? "enabled" : "disabled");
8982 crtc->base.enabled = crtc->active;
8984 /* Because we only establish the connector -> encoder ->
8985 * crtc links if something is active, this means the
8986 * crtc is now deactivated. Break the links. connector
8987 * -> encoder links are only establish when things are
8988 * actually up, hence no need to break them. */
8989 WARN_ON(crtc->active);
8991 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8992 WARN_ON(encoder->connectors_active);
8993 encoder->base.crtc = NULL;
8998 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9000 struct intel_connector *connector;
9001 struct drm_device *dev = encoder->base.dev;
9003 /* We need to check both for a crtc link (meaning that the
9004 * encoder is active and trying to read from a pipe) and the
9005 * pipe itself being active. */
9006 bool has_active_crtc = encoder->base.crtc &&
9007 to_intel_crtc(encoder->base.crtc)->active;
9009 if (encoder->connectors_active && !has_active_crtc) {
9010 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9011 encoder->base.base.id,
9012 drm_get_encoder_name(&encoder->base));
9014 /* Connector is active, but has no active pipe. This is
9015 * fallout from our resume register restoring. Disable
9016 * the encoder manually again. */
9017 if (encoder->base.crtc) {
9018 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9019 encoder->base.base.id,
9020 drm_get_encoder_name(&encoder->base));
9021 encoder->disable(encoder);
9024 /* Inconsistent output/port/pipe state happens presumably due to
9025 * a bug in one of the get_hw_state functions. Or someplace else
9026 * in our code, like the register restore mess on resume. Clamp
9027 * things to off as a safer default. */
9028 list_for_each_entry(connector,
9029 &dev->mode_config.connector_list,
9031 if (connector->encoder != encoder)
9034 intel_connector_break_all_links(connector);
9037 /* Enabled encoders without active connectors will be fixed in
9038 * the crtc fixup. */
9041 void i915_redisable_vga(struct drm_device *dev)
9043 struct drm_i915_private *dev_priv = dev->dev_private;
9044 u32 vga_reg = i915_vgacntrl_reg(dev);
9046 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9047 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9048 i915_disable_vga(dev);
9052 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9053 * and i915 state tracking structures. */
9054 void intel_modeset_setup_hw_state(struct drm_device *dev,
9057 struct drm_i915_private *dev_priv = dev->dev_private;
9060 struct intel_crtc *crtc;
9061 struct intel_encoder *encoder;
9062 struct intel_connector *connector;
9065 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9067 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9068 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9069 case TRANS_DDI_EDP_INPUT_A_ON:
9070 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9073 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9076 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9081 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9082 crtc->cpu_transcoder = TRANSCODER_EDP;
9084 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9089 for_each_pipe(pipe) {
9090 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9092 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9093 if (tmp & PIPECONF_ENABLE)
9094 crtc->active = true;
9096 crtc->active = false;
9098 crtc->base.enabled = crtc->active;
9100 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9102 crtc->active ? "enabled" : "disabled");
9106 intel_ddi_setup_hw_pll_state(dev);
9108 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9112 if (encoder->get_hw_state(encoder, &pipe)) {
9113 encoder->base.crtc =
9114 dev_priv->pipe_to_crtc_mapping[pipe];
9116 encoder->base.crtc = NULL;
9119 encoder->connectors_active = false;
9120 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9121 encoder->base.base.id,
9122 drm_get_encoder_name(&encoder->base),
9123 encoder->base.crtc ? "enabled" : "disabled",
9127 list_for_each_entry(connector, &dev->mode_config.connector_list,
9129 if (connector->get_hw_state(connector)) {
9130 connector->base.dpms = DRM_MODE_DPMS_ON;
9131 connector->encoder->connectors_active = true;
9132 connector->base.encoder = &connector->encoder->base;
9134 connector->base.dpms = DRM_MODE_DPMS_OFF;
9135 connector->base.encoder = NULL;
9137 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9138 connector->base.base.id,
9139 drm_get_connector_name(&connector->base),
9140 connector->base.encoder ? "enabled" : "disabled");
9143 /* HW state is read out, now we need to sanitize this mess. */
9144 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9146 intel_sanitize_encoder(encoder);
9149 for_each_pipe(pipe) {
9150 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9151 intel_sanitize_crtc(crtc);
9154 if (force_restore) {
9155 for_each_pipe(pipe) {
9156 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
9159 i915_redisable_vga(dev);
9161 intel_modeset_update_staged_output_state(dev);
9164 intel_modeset_check_state(dev);
9166 drm_mode_config_reset(dev);
9169 void intel_modeset_gem_init(struct drm_device *dev)
9171 intel_modeset_init_hw(dev);
9173 intel_setup_overlay(dev);
9175 intel_modeset_setup_hw_state(dev, false);
9178 void intel_modeset_cleanup(struct drm_device *dev)
9180 struct drm_i915_private *dev_priv = dev->dev_private;
9181 struct drm_crtc *crtc;
9182 struct intel_crtc *intel_crtc;
9184 drm_kms_helper_poll_fini(dev);
9185 mutex_lock(&dev->struct_mutex);
9187 intel_unregister_dsm_handler();
9190 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9191 /* Skip inactive CRTCs */
9195 intel_crtc = to_intel_crtc(crtc);
9196 intel_increase_pllclock(crtc);
9199 intel_disable_fbc(dev);
9201 intel_disable_gt_powersave(dev);
9203 ironlake_teardown_rc6(dev);
9205 if (IS_VALLEYVIEW(dev))
9208 mutex_unlock(&dev->struct_mutex);
9210 /* Disable the irq before mode object teardown, for the irq might
9211 * enqueue unpin/hotplug work. */
9212 drm_irq_uninstall(dev);
9213 cancel_work_sync(&dev_priv->hotplug_work);
9214 cancel_work_sync(&dev_priv->rps.work);
9216 /* flush any delayed tasks or pending work */
9217 flush_scheduled_work();
9219 drm_mode_config_cleanup(dev);
9221 intel_cleanup_overlay(dev);
9225 * Return which encoder is currently attached for connector.
9227 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9229 return &intel_attached_encoder(connector)->base;
9232 void intel_connector_attach_encoder(struct intel_connector *connector,
9233 struct intel_encoder *encoder)
9235 connector->encoder = encoder;
9236 drm_mode_connector_attach_encoder(&connector->base,
9241 * set vga decode state - true == enable VGA decode
9243 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9245 struct drm_i915_private *dev_priv = dev->dev_private;
9248 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9250 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9252 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9253 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9257 #ifdef CONFIG_DEBUG_FS
9258 #include <linux/seq_file.h>
9260 struct intel_display_error_state {
9261 struct intel_cursor_error_state {
9266 } cursor[I915_MAX_PIPES];
9268 struct intel_pipe_error_state {
9278 } pipe[I915_MAX_PIPES];
9280 struct intel_plane_error_state {
9288 } plane[I915_MAX_PIPES];
9291 struct intel_display_error_state *
9292 intel_display_capture_error_state(struct drm_device *dev)
9294 drm_i915_private_t *dev_priv = dev->dev_private;
9295 struct intel_display_error_state *error;
9296 enum transcoder cpu_transcoder;
9299 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9304 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9306 error->cursor[i].control = I915_READ(CURCNTR(i));
9307 error->cursor[i].position = I915_READ(CURPOS(i));
9308 error->cursor[i].base = I915_READ(CURBASE(i));
9310 error->plane[i].control = I915_READ(DSPCNTR(i));
9311 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9312 error->plane[i].size = I915_READ(DSPSIZE(i));
9313 error->plane[i].pos = I915_READ(DSPPOS(i));
9314 error->plane[i].addr = I915_READ(DSPADDR(i));
9315 if (INTEL_INFO(dev)->gen >= 4) {
9316 error->plane[i].surface = I915_READ(DSPSURF(i));
9317 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9320 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9321 error->pipe[i].source = I915_READ(PIPESRC(i));
9322 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9323 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9324 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9325 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9326 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9327 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9334 intel_display_print_error_state(struct seq_file *m,
9335 struct drm_device *dev,
9336 struct intel_display_error_state *error)
9338 drm_i915_private_t *dev_priv = dev->dev_private;
9341 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9343 seq_printf(m, "Pipe [%d]:\n", i);
9344 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9345 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9346 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9347 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9348 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9349 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9350 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9351 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9353 seq_printf(m, "Plane [%d]:\n", i);
9354 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9355 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9356 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9357 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9358 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9359 if (INTEL_INFO(dev)->gen >= 4) {
9360 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9361 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9364 seq_printf(m, "Cursor [%d]:\n", i);
9365 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9366 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9367 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);