drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 /* returns HPLL frequency in kHz */
 136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 137 {
 138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 139
 140         /* Obtain SKU information */
 141         mutex_lock(&dev_priv->sb_lock);
 142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 143                 CCK_FUSE_HPLL_FREQ_MASK;
 144         mutex_unlock(&dev_priv->sb_lock);
 145
 146         return vco_freq[hpll_freq] * 1000;
 147 }
 148
 149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 150                                   const char *name, u32 reg)
 151 {
 152         u32 val;
 153         int divider;
 154
 155         if (dev_priv->hpll_freq == 0)
 156                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 157
 158         mutex_lock(&dev_priv->sb_lock);
 159         val = vlv_cck_read(dev_priv, reg);
 160         mutex_unlock(&dev_priv->sb_lock);
 161
 162         divider = val & CCK_FREQUENCY_VALUES;
 163
 164         WARN((val & CCK_FREQUENCY_STATUS) !=
 165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 166              "%s change in progress\n", name);
 167
 168         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 169 }
 170
 171 int
 172 intel_pch_rawclk(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175
 176         WARN_ON(!HAS_PCH_SPLIT(dev));
 177
 178         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 179 }
 180
 181 /* hrawclock is 1/4 the FSB frequency */
 182 int intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (!IS_VALLEYVIEW(dev_priv))
 217                 return;
 218
 219         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 220                                                       CCK_CZ_CLOCK_CONTROL);
 221
 222         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 223 }
 224
 225 static inline u32 /* units of 100MHz */
 226 intel_fdi_link_freq(struct drm_device *dev)
 227 {
 228         if (IS_GEN5(dev)) {
 229                 struct drm_i915_private *dev_priv = dev->dev_private;
 230                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 231         } else
 232                 return 27;
 233 }
 234
 235 static const intel_limit_t intel_limits_i8xx_dac = {
 236         .dot = { .min = 25000, .max = 350000 },
 237         .vco = { .min = 908000, .max = 1512000 },
 238         .n = { .min = 2, .max = 16 },
 239         .m = { .min = 96, .max = 140 },
 240         .m1 = { .min = 18, .max = 26 },
 241         .m2 = { .min = 6, .max = 16 },
 242         .p = { .min = 4, .max = 128 },
 243         .p1 = { .min = 2, .max = 33 },
 244         .p2 = { .dot_limit = 165000,
 245                 .p2_slow = 4, .p2_fast = 2 },
 246 };
 247
 248 static const intel_limit_t intel_limits_i8xx_dvo = {
 249         .dot = { .min = 25000, .max = 350000 },
 250         .vco = { .min = 908000, .max = 1512000 },
 251         .n = { .min = 2, .max = 16 },
 252         .m = { .min = 96, .max = 140 },
 253         .m1 = { .min = 18, .max = 26 },
 254         .m2 = { .min = 6, .max = 16 },
 255         .p = { .min = 4, .max = 128 },
 256         .p1 = { .min = 2, .max = 33 },
 257         .p2 = { .dot_limit = 165000,
 258                 .p2_slow = 4, .p2_fast = 4 },
 259 };
 260
 261 static const intel_limit_t intel_limits_i8xx_lvds = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 908000, .max = 1512000 },
 264         .n = { .min = 2, .max = 16 },
 265         .m = { .min = 96, .max = 140 },
 266         .m1 = { .min = 18, .max = 26 },
 267         .m2 = { .min = 6, .max = 16 },
 268         .p = { .min = 4, .max = 128 },
 269         .p1 = { .min = 1, .max = 6 },
 270         .p2 = { .dot_limit = 165000,
 271                 .p2_slow = 14, .p2_fast = 7 },
 272 };
 273
 274 static const intel_limit_t intel_limits_i9xx_sdvo = {
 275         .dot = { .min = 20000, .max = 400000 },
 276         .vco = { .min = 1400000, .max = 2800000 },
 277         .n = { .min = 1, .max = 6 },
 278         .m = { .min = 70, .max = 120 },
 279         .m1 = { .min = 8, .max = 18 },
 280         .m2 = { .min = 3, .max = 7 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 200000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285 };
 286
 287 static const intel_limit_t intel_limits_i9xx_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1400000, .max = 2800000 },
 290         .n = { .min = 1, .max = 6 },
 291         .m = { .min = 70, .max = 120 },
 292         .m1 = { .min = 8, .max = 18 },
 293         .m2 = { .min = 3, .max = 7 },
 294         .p = { .min = 7, .max = 98 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 7 },
 298 };
 299
 300
 301 static const intel_limit_t intel_limits_g4x_sdvo = {
 302         .dot = { .min = 25000, .max = 270000 },
 303         .vco = { .min = 1750000, .max = 3500000},
 304         .n = { .min = 1, .max = 4 },
 305         .m = { .min = 104, .max = 138 },
 306         .m1 = { .min = 17, .max = 23 },
 307         .m2 = { .min = 5, .max = 11 },
 308         .p = { .min = 10, .max = 30 },
 309         .p1 = { .min = 1, .max = 3},
 310         .p2 = { .dot_limit = 270000,
 311                 .p2_slow = 10,
 312                 .p2_fast = 10
 313         },
 314 };
 315
 316 static const intel_limit_t intel_limits_g4x_hdmi = {
 317         .dot = { .min = 22000, .max = 400000 },
 318         .vco = { .min = 1750000, .max = 3500000},
 319         .n = { .min = 1, .max = 4 },
 320         .m = { .min = 104, .max = 138 },
 321         .m1 = { .min = 16, .max = 23 },
 322         .m2 = { .min = 5, .max = 11 },
 323         .p = { .min = 5, .max = 80 },
 324         .p1 = { .min = 1, .max = 8},
 325         .p2 = { .dot_limit = 165000,
 326                 .p2_slow = 10, .p2_fast = 5 },
 327 };
 328
 329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 330         .dot = { .min = 20000, .max = 115000 },
 331         .vco = { .min = 1750000, .max = 3500000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 28, .max = 112 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 0,
 339                 .p2_slow = 14, .p2_fast = 14
 340         },
 341 };
 342
 343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 344         .dot = { .min = 80000, .max = 224000 },
 345         .vco = { .min = 1750000, .max = 3500000 },
 346         .n = { .min = 1, .max = 3 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 17, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 14, .max = 42 },
 351         .p1 = { .min = 2, .max = 6 },
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 7, .p2_fast = 7
 354         },
 355 };
 356
 357 static const intel_limit_t intel_limits_pineview_sdvo = {
 358         .dot = { .min = 20000, .max = 400000},
 359         .vco = { .min = 1700000, .max = 3500000 },
 360         /* Pineview's Ncounter is a ring counter */
 361         .n = { .min = 3, .max = 6 },
 362         .m = { .min = 2, .max = 256 },
 363         /* Pineview only has one combined m divider, which we treat as m2. */
 364         .m1 = { .min = 0, .max = 0 },
 365         .m2 = { .min = 0, .max = 254 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 200000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const intel_limit_t intel_limits_pineview_lvds = {
 373         .dot = { .min = 20000, .max = 400000 },
 374         .vco = { .min = 1700000, .max = 3500000 },
 375         .n = { .min = 3, .max = 6 },
 376         .m = { .min = 2, .max = 256 },
 377         .m1 = { .min = 0, .max = 0 },
 378         .m2 = { .min = 0, .max = 254 },
 379         .p = { .min = 7, .max = 112 },
 380         .p1 = { .min = 1, .max = 8 },
 381         .p2 = { .dot_limit = 112000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 /* Ironlake / Sandybridge
 386  *
 387  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 388  * the range value for them is (actual_value - 2).
 389  */
 390 static const intel_limit_t intel_limits_ironlake_dac = {
 391         .dot = { .min = 25000, .max = 350000 },
 392         .vco = { .min = 1760000, .max = 3510000 },
 393         .n = { .min = 1, .max = 5 },
 394         .m = { .min = 79, .max = 127 },
 395         .m1 = { .min = 12, .max = 22 },
 396         .m2 = { .min = 5, .max = 9 },
 397         .p = { .min = 5, .max = 80 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 225000,
 400                 .p2_slow = 10, .p2_fast = 5 },
 401 };
 402
 403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 404         .dot = { .min = 25000, .max = 350000 },
 405         .vco = { .min = 1760000, .max = 3510000 },
 406         .n = { .min = 1, .max = 3 },
 407         .m = { .min = 79, .max = 118 },
 408         .m1 = { .min = 12, .max = 22 },
 409         .m2 = { .min = 5, .max = 9 },
 410         .p = { .min = 28, .max = 112 },
 411         .p1 = { .min = 2, .max = 8 },
 412         .p2 = { .dot_limit = 225000,
 413                 .p2_slow = 14, .p2_fast = 14 },
 414 };
 415
 416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 417         .dot = { .min = 25000, .max = 350000 },
 418         .vco = { .min = 1760000, .max = 3510000 },
 419         .n = { .min = 1, .max = 3 },
 420         .m = { .min = 79, .max = 127 },
 421         .m1 = { .min = 12, .max = 22 },
 422         .m2 = { .min = 5, .max = 9 },
 423         .p = { .min = 14, .max = 56 },
 424         .p1 = { .min = 2, .max = 8 },
 425         .p2 = { .dot_limit = 225000,
 426                 .p2_slow = 7, .p2_fast = 7 },
 427 };
 428
 429 /* LVDS 100mhz refclk limits. */
 430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 2 },
 434         .m = { .min = 79, .max = 126 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 126 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 42 },
 451         .p1 = { .min = 2, .max = 6 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 static const intel_limit_t intel_limits_vlv = {
 457          /*
 458           * These are the data rate limits (measured in fast clocks)
 459           * since those are the strictest limits we have. The fast
 460           * clock and actual rate limits are more relaxed, so checking
 461           * them would make no difference.
 462           */
 463         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 464         .vco = { .min = 4000000, .max = 6000000 },
 465         .n = { .min = 1, .max = 7 },
 466         .m1 = { .min = 2, .max = 3 },
 467         .m2 = { .min = 11, .max = 156 },
 468         .p1 = { .min = 2, .max = 3 },
 469         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 470 };
 471
 472 static const intel_limit_t intel_limits_chv = {
 473         /*
 474          * These are the data rate limits (measured in fast clocks)
 475          * since those are the strictest limits we have.  The fast
 476          * clock and actual rate limits are more relaxed, so checking
 477          * them would make no difference.
 478          */
 479         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 480         .vco = { .min = 4800000, .max = 6480000 },
 481         .n = { .min = 1, .max = 1 },
 482         .m1 = { .min = 2, .max = 2 },
 483         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 484         .p1 = { .min = 2, .max = 4 },
 485         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 486 };
 487
 488 static const intel_limit_t intel_limits_bxt = {
 489         /* FIXME: find real dot limits */
 490         .dot = { .min = 0, .max = INT_MAX },
 491         .vco = { .min = 4800000, .max = 6700000 },
 492         .n = { .min = 1, .max = 1 },
 493         .m1 = { .min = 2, .max = 2 },
 494         /* FIXME: find real m2 limits */
 495         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 496         .p1 = { .min = 2, .max = 4 },
 497         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 498 };
 499
 500 static bool
 501 needs_modeset(struct drm_crtc_state *state)
 502 {
 503         return drm_atomic_crtc_needs_modeset(state);
 504 }
 505
 506 /**
 507  * Returns whether any output on the specified pipe is of the specified type
 508  */
 509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 510 {
 511         struct drm_device *dev = crtc->base.dev;
 512         struct intel_encoder *encoder;
 513
 514         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 515                 if (encoder->type == type)
 516                         return true;
 517
 518         return false;
 519 }
 520
 521 /**
 522  * Returns whether any output on the specified pipe will have the specified
 523  * type after a staged modeset is complete, i.e., the same as
 524  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 525  * encoder->crtc.
 526  */
 527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 528                                       int type)
 529 {
 530         struct drm_atomic_state *state = crtc_state->base.state;
 531         struct drm_connector *connector;
 532         struct drm_connector_state *connector_state;
 533         struct intel_encoder *encoder;
 534         int i, num_connectors = 0;
 535
 536         for_each_connector_in_state(state, connector, connector_state, i) {
 537                 if (connector_state->crtc != crtc_state->base.crtc)
 538                         continue;
 539
 540                 num_connectors++;
 541
 542                 encoder = to_intel_encoder(connector_state->best_encoder);
 543                 if (encoder->type == type)
 544                         return true;
 545         }
 546
 547         WARN_ON(num_connectors == 0);
 548
 549         return false;
 550 }
 551
 552 static const intel_limit_t *
 553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 554 {
 555         struct drm_device *dev = crtc_state->base.crtc->dev;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 559                 if (intel_is_dual_link_lvds(dev)) {
 560                         if (refclk == 100000)
 561                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 562                         else
 563                                 limit = &intel_limits_ironlake_dual_lvds;
 564                 } else {
 565                         if (refclk == 100000)
 566                                 limit = &intel_limits_ironlake_single_lvds_100m;
 567                         else
 568                                 limit = &intel_limits_ironlake_single_lvds;
 569                 }
 570         } else
 571                 limit = &intel_limits_ironlake_dac;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *
 577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 578 {
 579         struct drm_device *dev = crtc_state->base.crtc->dev;
 580         const intel_limit_t *limit;
 581
 582         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 583                 if (intel_is_dual_link_lvds(dev))
 584                         limit = &intel_limits_g4x_dual_channel_lvds;
 585                 else
 586                         limit = &intel_limits_g4x_single_channel_lvds;
 587         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 588                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 589                 limit = &intel_limits_g4x_hdmi;
 590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 591                 limit = &intel_limits_g4x_sdvo;
 592         } else /* The option is for other outputs */
 593                 limit = &intel_limits_i9xx_sdvo;
 594
 595         return limit;
 596 }
 597
 598 static const intel_limit_t *
 599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 600 {
 601         struct drm_device *dev = crtc_state->base.crtc->dev;
 602         const intel_limit_t *limit;
 603
 604         if (IS_BROXTON(dev))
 605                 limit = &intel_limits_bxt;
 606         else if (HAS_PCH_SPLIT(dev))
 607                 limit = intel_ironlake_limit(crtc_state, refclk);
 608         else if (IS_G4X(dev)) {
 609                 limit = intel_g4x_limit(crtc_state);
 610         } else if (IS_PINEVIEW(dev)) {
 611                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 612                         limit = &intel_limits_pineview_lvds;
 613                 else
 614                         limit = &intel_limits_pineview_sdvo;
 615         } else if (IS_CHERRYVIEW(dev)) {
 616                 limit = &intel_limits_chv;
 617         } else if (IS_VALLEYVIEW(dev)) {
 618                 limit = &intel_limits_vlv;
 619         } else if (!IS_GEN2(dev)) {
 620                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 621                         limit = &intel_limits_i9xx_lvds;
 622                 else
 623                         limit = &intel_limits_i9xx_sdvo;
 624         } else {
 625                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 626                         limit = &intel_limits_i8xx_lvds;
 627                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 628                         limit = &intel_limits_i8xx_dvo;
 629                 else
 630                         limit = &intel_limits_i8xx_dac;
 631         }
 632         return limit;
 633 }
 634
 635 /*
 636  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 637  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 638  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 639  * The helpers' return value is the rate of the clock that is fed to the
 640  * display engine's pipe which can be the above fast dot clock rate or a
 641  * divided-down version of it.
 642  */
 643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 645 {
 646         clock->m = clock->m2 + 2;
 647         clock->p = clock->p1 * clock->p2;
 648         if (WARN_ON(clock->n == 0 || clock->p == 0))
 649                 return 0;
 650         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 651         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 652
 653         return clock->dot;
 654 }
 655
 656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 657 {
 658         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 659 }
 660
 661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 662 {
 663         clock->m = i9xx_dpll_compute_m(clock);
 664         clock->p = clock->p1 * clock->p2;
 665         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 666                 return 0;
 667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 669
 670         return clock->dot;
 671 }
 672
 673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 674 {
 675         clock->m = clock->m1 * clock->m2;
 676         clock->p = clock->p1 * clock->p2;
 677         if (WARN_ON(clock->n == 0 || clock->p == 0))
 678                 return 0;
 679         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 680         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 681
 682         return clock->dot / 5;
 683 }
 684
 685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 686 {
 687         clock->m = clock->m1 * clock->m2;
 688         clock->p = clock->p1 * clock->p2;
 689         if (WARN_ON(clock->n == 0 || clock->p == 0))
 690                 return 0;
 691         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 692                         clock->n << 22);
 693         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 694
 695         return clock->dot / 5;
 696 }
 697
 698 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 699 /**
 700  * Returns whether the given set of divisors are valid for a given refclk with
 701  * the given connectors.
 702  */
 703
 704 static bool intel_PLL_is_valid(struct drm_device *dev,
 705                                const intel_limit_t *limit,
 706                                const intel_clock_t *clock)
 707 {
 708         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 709                 INTELPllInvalid("n out of range\n");
 710         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 711                 INTELPllInvalid("p1 out of range\n");
 712         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 713                 INTELPllInvalid("m2 out of range\n");
 714         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 715                 INTELPllInvalid("m1 out of range\n");
 716
 717         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 718                 if (clock->m1 <= clock->m2)
 719                         INTELPllInvalid("m1 <= m2\n");
 720
 721         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 722                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 723                         INTELPllInvalid("p out of range\n");
 724                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 725                         INTELPllInvalid("m out of range\n");
 726         }
 727
 728         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 729                 INTELPllInvalid("vco out of range\n");
 730         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 731          * connector, etc., rather than just a single range.
 732          */
 733         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 734                 INTELPllInvalid("dot out of range\n");
 735
 736         return true;
 737 }
 738
 739 static int
 740 i9xx_select_p2_div(const intel_limit_t *limit,
 741                    const struct intel_crtc_state *crtc_state,
 742                    int target)
 743 {
 744         struct drm_device *dev = crtc_state->base.crtc->dev;
 745
 746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 747                 /*
 748                  * For LVDS just rely on its current settings for dual-channel.
 749                  * We haven't figured out how to reliably set up different
 750                  * single/dual channel state, if we even can.
 751                  */
 752                 if (intel_is_dual_link_lvds(dev))
 753                         return limit->p2.p2_fast;
 754                 else
 755                         return limit->p2.p2_slow;
 756         } else {
 757                 if (target < limit->p2.dot_limit)
 758                         return limit->p2.p2_slow;
 759                 else
 760                         return limit->p2.p2_fast;
 761         }
 762 }
 763
 764 static bool
 765 i9xx_find_best_dpll(const intel_limit_t *limit,
 766                     struct intel_crtc_state *crtc_state,
 767                     int target, int refclk, intel_clock_t *match_clock,
 768                     intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         if (clock.m2 >= clock.m1)
 783                                 break;
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         i9xx_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794                                         if (match_clock &&
 795                                             clock.p != match_clock->p)
 796                                                 continue;
 797
 798                                         this_err = abs(clock.dot - target);
 799                                         if (this_err < err) {
 800                                                 *best_clock = clock;
 801                                                 err = this_err;
 802                                         }
 803                                 }
 804                         }
 805                 }
 806         }
 807
 808         return (err != target);
 809 }
 810
 811 static bool
 812 pnv_find_best_dpll(const intel_limit_t *limit,
 813                    struct intel_crtc_state *crtc_state,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc_state->base.crtc->dev;
 818         intel_clock_t clock;
 819         int err = target;
 820
 821         memset(best_clock, 0, sizeof(*best_clock));
 822
 823         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         for (clock.n = limit->n.min;
 830                              clock.n <= limit->n.max; clock.n++) {
 831                                 for (clock.p1 = limit->p1.min;
 832                                         clock.p1 <= limit->p1.max; clock.p1++) {
 833                                         int this_err;
 834
 835                                         pnv_calc_dpll_params(refclk, &clock);
 836                                         if (!intel_PLL_is_valid(dev, limit,
 837                                                                 &clock))
 838                                                 continue;
 839                                         if (match_clock &&
 840                                             clock.p != match_clock->p)
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 g4x_find_best_dpll(const intel_limit_t *limit,
 858                    struct intel_crtc_state *crtc_state,
 859                    int target, int refclk, intel_clock_t *match_clock,
 860                    intel_clock_t *best_clock)
 861 {
 862         struct drm_device *dev = crtc_state->base.crtc->dev;
 863         intel_clock_t clock;
 864         int max_n;
 865         bool found = false;
 866         /* approximately equals target * 0.00585 */
 867         int err_most = (target >> 8) + (target >> 9);
 868
 869         memset(best_clock, 0, sizeof(*best_clock));
 870
 871         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 872
 873         max_n = limit->n.max;
 874         /* based on hardware requirement, prefer smaller n to precision */
 875         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 876                 /* based on hardware requirement, prefere larger m1,m2 */
 877                 for (clock.m1 = limit->m1.max;
 878                      clock.m1 >= limit->m1.min; clock.m1--) {
 879                         for (clock.m2 = limit->m2.max;
 880                              clock.m2 >= limit->m2.min; clock.m2--) {
 881                                 for (clock.p1 = limit->p1.max;
 882                                      clock.p1 >= limit->p1.min; clock.p1--) {
 883                                         int this_err;
 884
 885                                         i9xx_calc_dpll_params(refclk, &clock);
 886                                         if (!intel_PLL_is_valid(dev, limit,
 887                                                                 &clock))
 888                                                 continue;
 889
 890                                         this_err = abs(clock.dot - target);
 891                                         if (this_err < err_most) {
 892                                                 *best_clock = clock;
 893                                                 err_most = this_err;
 894                                                 max_n = clock.n;
 895                                                 found = true;
 896                                         }
 897                                 }
 898                         }
 899                 }
 900         }
 901         return found;
 902 }
 903
 904 /*
 905  * Check if the calculated PLL configuration is more optimal compared to the
 906  * best configuration and error found so far. Return the calculated error.
 907  */
 908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 909                                const intel_clock_t *calculated_clock,
 910                                const intel_clock_t *best_clock,
 911                                unsigned int best_error_ppm,
 912                                unsigned int *error_ppm)
 913 {
 914         /*
 915          * For CHV ignore the error and consider only the P value.
 916          * Prefer a bigger P value based on HW requirements.
 917          */
 918         if (IS_CHERRYVIEW(dev)) {
 919                 *error_ppm = 0;
 920
 921                 return calculated_clock->p > best_clock->p;
 922         }
 923
 924         if (WARN_ON_ONCE(!target_freq))
 925                 return false;
 926
 927         *error_ppm = div_u64(1000000ULL *
 928                                 abs(target_freq - calculated_clock->dot),
 929                              target_freq);
 930         /*
 931          * Prefer a better P value over a better (smaller) error if the error
 932          * is small. Ensure this preference for future configurations too by
 933          * setting the error to 0.
 934          */
 935         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 936                 *error_ppm = 0;
 937
 938                 return true;
 939         }
 940
 941         return *error_ppm + 10 < best_error_ppm;
 942 }
 943
 944 static bool
 945 vlv_find_best_dpll(const intel_limit_t *limit,
 946                    struct intel_crtc_state *crtc_state,
 947                    int target, int refclk, intel_clock_t *match_clock,
 948                    intel_clock_t *best_clock)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 951         struct drm_device *dev = crtc->base.dev;
 952         intel_clock_t clock;
 953         unsigned int bestppm = 1000000;
 954         /* min update 19.2 MHz */
 955         int max_n = min(limit->n.max, refclk / 19200);
 956         bool found = false;
 957
 958         target *= 5; /* fast clock */
 959
 960         memset(best_clock, 0, sizeof(*best_clock));
 961
 962         /* based on hardware requirement, prefer smaller n to precision */
 963         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 964                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 965                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 966                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 967                                 clock.p = clock.p1 * clock.p2;
 968                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 969                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 970                                         unsigned int ppm;
 971
 972                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 973                                                                      refclk * clock.m1);
 974
 975                                         vlv_calc_dpll_params(refclk, &clock);
 976
 977                                         if (!intel_PLL_is_valid(dev, limit,
 978                                                                 &clock))
 979                                                 continue;
 980
 981                                         if (!vlv_PLL_is_optimal(dev, target,
 982                                                                 &clock,
 983                                                                 best_clock,
 984                                                                 bestppm, &ppm))
 985                                                 continue;
 986
 987                                         *best_clock = clock;
 988                                         bestppm = ppm;
 989                                         found = true;
 990                                 }
 991                         }
 992                 }
 993         }
 994
 995         return found;
 996 }
 997
 998 static bool
 999 chv_find_best_dpll(const intel_limit_t *limit,
1000                    struct intel_crtc_state *crtc_state,
1001                    int target, int refclk, intel_clock_t *match_clock,
1002                    intel_clock_t *best_clock)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005         struct drm_device *dev = crtc->base.dev;
1006         unsigned int best_error_ppm;
1007         intel_clock_t clock;
1008         uint64_t m2;
1009         int found = false;
1010
1011         memset(best_clock, 0, sizeof(*best_clock));
1012         best_error_ppm = 1000000;
1013
1014         /*
1015          * Based on hardware doc, the n always set to 1, and m1 always
1016          * set to 2.  If requires to support 200Mhz refclk, we need to
1017          * revisit this because n may not 1 anymore.
1018          */
1019         clock.n = 1, clock.m1 = 2;
1020         target *= 5;    /* fast clock */
1021
1022         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023                 for (clock.p2 = limit->p2.p2_fast;
1024                                 clock.p2 >= limit->p2.p2_slow;
1025                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026                         unsigned int error_ppm;
1027
1028                         clock.p = clock.p1 * clock.p2;
1029
1030                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031                                         clock.n) << 22, refclk * clock.m1);
1032
1033                         if (m2 > INT_MAX/clock.m1)
1034                                 continue;
1035
1036                         clock.m2 = m2;
1037
1038                         chv_calc_dpll_params(refclk, &clock);
1039
1040                         if (!intel_PLL_is_valid(dev, limit, &clock))
1041                                 continue;
1042
1043                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044                                                 best_error_ppm, &error_ppm))
1045                                 continue;
1046
1047                         *best_clock = clock;
1048                         best_error_ppm = error_ppm;
1049                         found = true;
1050                 }
1051         }
1052
1053         return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057                         intel_clock_t *best_clock)
1058 {
1059         int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062                                   target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069         /* Be paranoid as we can arrive here with only partial
1070          * state retrieved from the hardware during setup.
1071          *
1072          * We can ditch the adjusted_mode.crtc_clock check as soon
1073          * as Haswell has gained clock readout/fastboot support.
1074          *
1075          * We can ditch the crtc->primary->fb check as soon as we can
1076          * properly reconstruct framebuffers.
1077          *
1078          * FIXME: The intel_crtc->active here should be switched to
1079          * crtc->state->active once we have proper CRTC states wired up
1080          * for atomic.
1081          */
1082         return intel_crtc->active && crtc->primary->state->fb &&
1083                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087                                              enum pipe pipe)
1088 {
1089         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092         return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         i915_reg_t reg = PIPEDSL(pipe);
1099         u32 line1, line2;
1100         u32 line_mask;
1101
1102         if (IS_GEN2(dev))
1103                 line_mask = DSL_LINEMASK_GEN2;
1104         else
1105                 line_mask = DSL_LINEMASK_GEN3;
1106
1107         line1 = I915_READ(reg) & line_mask;
1108         msleep(5);
1109         line2 = I915_READ(reg) & line_mask;
1110
1111         return line1 == line2;
1112 }
1113
1114 /*
1115  * intel_wait_for_pipe_off - wait for pipe to turn off
1116  * @crtc: crtc whose pipe to wait for
1117  *
1118  * After disabling a pipe, we can't wait for vblank in the usual way,
1119  * spinning on the vblank interrupt status bit, since we won't actually
1120  * see an interrupt when the pipe is disabled.
1121  *
1122  * On Gen4 and above:
1123  *   wait for the pipe register state bit to turn off
1124  *
1125  * Otherwise:
1126  *   wait for the display line value to settle (it usually
1127  *   ends up stopping at the start of the next frame).
1128  *
1129  */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132         struct drm_device *dev = crtc->base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135         enum pipe pipe = crtc->pipe;
1136
1137         if (INTEL_INFO(dev)->gen >= 4) {
1138                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1139
1140                 /* Wait for the Pipe State to go off */
1141                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142                              100))
1143                         WARN(1, "pipe_off wait timed out\n");
1144         } else {
1145                 /* Wait for the display line to settle */
1146                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153         return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158                 enum pipe pipe, bool state)
1159 {
1160         u32 val;
1161         bool cur_state;
1162
1163         val = I915_READ(DPLL(pipe));
1164         cur_state = !!(val & DPLL_VCO_ENABLE);
1165         I915_STATE_WARN(cur_state != state,
1166              "PLL state assertion failure (expected %s, current %s)\n",
1167              state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173         u32 val;
1174         bool cur_state;
1175
1176         mutex_lock(&dev_priv->sb_lock);
1177         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178         mutex_unlock(&dev_priv->sb_lock);
1179
1180         cur_state = val & DSI_PLL_VCO_EN;
1181         I915_STATE_WARN(cur_state != state,
1182              "DSI PLL state assertion failure (expected %s, current %s)\n",
1183              state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193         if (crtc->config->shared_dpll < 0)
1194                 return NULL;
1195
1196         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201                         struct intel_shared_dpll *pll,
1202                         bool state)
1203 {
1204         bool cur_state;
1205         struct intel_dpll_hw_state hw_state;
1206
1207         if (WARN (!pll,
1208                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1209                 return;
1210
1211         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212         I915_STATE_WARN(cur_state != state,
1213              "%s assertion failure (expected %s, current %s)\n",
1214              pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218                           enum pipe pipe, bool state)
1219 {
1220         bool cur_state;
1221         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222                                                                       pipe);
1223
1224         if (HAS_DDI(dev_priv->dev)) {
1225                 /* DDI does not have a specific FDI_TX register */
1226                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228         } else {
1229                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230                 cur_state = !!(val & FDI_TX_ENABLE);
1231         }
1232         I915_STATE_WARN(cur_state != state,
1233              "FDI TX state assertion failure (expected %s, current %s)\n",
1234              state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240                           enum pipe pipe, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(FDI_RX_CTL(pipe));
1246         cur_state = !!(val & FDI_RX_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "FDI RX state assertion failure (expected %s, current %s)\n",
1249              state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255                                       enum pipe pipe)
1256 {
1257         u32 val;
1258
1259         /* ILK FDI PLL is always enabled */
1260         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261                 return;
1262
1263         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264         if (HAS_DDI(dev_priv->dev))
1265                 return;
1266
1267         val = I915_READ(FDI_TX_CTL(pipe));
1268         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272                        enum pipe pipe, bool state)
1273 {
1274         u32 val;
1275         bool cur_state;
1276
1277         val = I915_READ(FDI_RX_CTL(pipe));
1278         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279         I915_STATE_WARN(cur_state != state,
1280              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281              state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285                            enum pipe pipe)
1286 {
1287         struct drm_device *dev = dev_priv->dev;
1288         i915_reg_t pp_reg;
1289         u32 val;
1290         enum pipe panel_pipe = PIPE_A;
1291         bool locked = true;
1292
1293         if (WARN_ON(HAS_DDI(dev)))
1294                 return;
1295
1296         if (HAS_PCH_SPLIT(dev)) {
1297                 u32 port_sel;
1298
1299                 pp_reg = PCH_PP_CONTROL;
1300                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304                         panel_pipe = PIPE_B;
1305                 /* XXX: else fix for eDP */
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 /* presumably write lock depends on pipe, not port select */
1308                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309                 panel_pipe = pipe;
1310         } else {
1311                 pp_reg = PP_CONTROL;
1312                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313                         panel_pipe = PIPE_B;
1314         }
1315
1316         val = I915_READ(pp_reg);
1317         if (!(val & PANEL_POWER_ON) ||
1318             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319                 locked = false;
1320
1321         I915_STATE_WARN(panel_pipe == pipe && locked,
1322              "panel assertion failure, pipe %c regs locked\n",
1323              pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327                           enum pipe pipe, bool state)
1328 {
1329         struct drm_device *dev = dev_priv->dev;
1330         bool cur_state;
1331
1332         if (IS_845G(dev) || IS_I865G(dev))
1333                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334         else
1335                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345                  enum pipe pipe, bool state)
1346 {
1347         bool cur_state;
1348         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349                                                                       pipe);
1350
1351         /* if we need the pipe quirk it must be always on */
1352         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354                 state = true;
1355
1356         if (!intel_display_power_is_enabled(dev_priv,
1357                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358                 cur_state = false;
1359         } else {
1360                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361                 cur_state = !!(val & PIPECONF_ENABLE);
1362         }
1363
1364         I915_STATE_WARN(cur_state != state,
1365              "pipe %c assertion failure (expected %s, current %s)\n",
1366              pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370                          enum plane plane, bool state)
1371 {
1372         u32 val;
1373         bool cur_state;
1374
1375         val = I915_READ(DSPCNTR(plane));
1376         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377         I915_STATE_WARN(cur_state != state,
1378              "plane %c assertion failure (expected %s, current %s)\n",
1379              plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe)
1387 {
1388         struct drm_device *dev = dev_priv->dev;
1389         int i;
1390
1391         /* Primary planes are fixed to pipes on gen4+ */
1392         if (INTEL_INFO(dev)->gen >= 4) {
1393                 u32 val = I915_READ(DSPCNTR(pipe));
1394                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395                      "plane %c assertion failure, should be disabled but not\n",
1396                      plane_name(pipe));
1397                 return;
1398         }
1399
1400         /* Need to check both planes against the pipe */
1401         for_each_pipe(dev_priv, i) {
1402                 u32 val = I915_READ(DSPCNTR(i));
1403                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404                         DISPPLANE_SEL_PIPE_SHIFT;
1405                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407                      plane_name(i), pipe_name(pipe));
1408         }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412                                     enum pipe pipe)
1413 {
1414         struct drm_device *dev = dev_priv->dev;
1415         int sprite;
1416
1417         if (INTEL_INFO(dev)->gen >= 9) {
1418                 for_each_sprite(dev_priv, pipe, sprite) {
1419                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422                              sprite, pipe_name(pipe));
1423                 }
1424         } else if (IS_VALLEYVIEW(dev)) {
1425                 for_each_sprite(dev_priv, pipe, sprite) {
1426                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1427                         I915_STATE_WARN(val & SP_ENABLE,
1428                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429                              sprite_name(pipe, sprite), pipe_name(pipe));
1430                 }
1431         } else if (INTEL_INFO(dev)->gen >= 7) {
1432                 u32 val = I915_READ(SPRCTL(pipe));
1433                 I915_STATE_WARN(val & SPRITE_ENABLE,
1434                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435                      plane_name(pipe), pipe_name(pipe));
1436         } else if (INTEL_INFO(dev)->gen >= 5) {
1437                 u32 val = I915_READ(DVSCNTR(pipe));
1438                 I915_STATE_WARN(val & DVS_ENABLE,
1439                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440                      plane_name(pipe), pipe_name(pipe));
1441         }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447                 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452         u32 val;
1453         bool enabled;
1454
1455         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457         val = I915_READ(PCH_DREF_CONTROL);
1458         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459                             DREF_SUPERSPREAD_SOURCE_MASK));
1460         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464                                            enum pipe pipe)
1465 {
1466         u32 val;
1467         bool enabled;
1468
1469         val = I915_READ(PCH_TRANSCONF(pipe));
1470         enabled = !!(val & TRANS_ENABLE);
1471         I915_STATE_WARN(enabled,
1472              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473              pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477                             enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479         if ((val & DP_PORT_EN) == 0)
1480                 return false;
1481
1482         if (HAS_PCH_CPT(dev_priv->dev)) {
1483                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1484                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1485                         return false;
1486         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1487                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1488                         return false;
1489         } else {
1490                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1491                         return false;
1492         }
1493         return true;
1494 }
1495
1496 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1497                               enum pipe pipe, u32 val)
1498 {
1499         if ((val & SDVO_ENABLE) == 0)
1500                 return false;
1501
1502         if (HAS_PCH_CPT(dev_priv->dev)) {
1503                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1504                         return false;
1505         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1506                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1507                         return false;
1508         } else {
1509                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1510                         return false;
1511         }
1512         return true;
1513 }
1514
1515 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1516                               enum pipe pipe, u32 val)
1517 {
1518         if ((val & LVDS_PORT_EN) == 0)
1519                 return false;
1520
1521         if (HAS_PCH_CPT(dev_priv->dev)) {
1522                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1523                         return false;
1524         } else {
1525                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1526                         return false;
1527         }
1528         return true;
1529 }
1530
1531 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1532                               enum pipe pipe, u32 val)
1533 {
1534         if ((val & ADPA_DAC_ENABLE) == 0)
1535                 return false;
1536         if (HAS_PCH_CPT(dev_priv->dev)) {
1537                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1538                         return false;
1539         } else {
1540                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1541                         return false;
1542         }
1543         return true;
1544 }
1545
1546 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1547                                    enum pipe pipe, i915_reg_t reg,
1548                                    u32 port_sel)
1549 {
1550         u32 val = I915_READ(reg);
1551         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553              i915_mmio_reg_offset(reg), pipe_name(pipe));
1554
1555         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556              && (val & DP_PIPEB_SELECT),
1557              "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561                                      enum pipe pipe, i915_reg_t reg)
1562 {
1563         u32 val = I915_READ(reg);
1564         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566              i915_mmio_reg_offset(reg), pipe_name(pipe));
1567
1568         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569              && (val & SDVO_PIPE_B_SELECT),
1570              "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574                                       enum pipe pipe)
1575 {
1576         u32 val;
1577
1578         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582         val = I915_READ(PCH_ADPA);
1583         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584              "PCH VGA enabled on transcoder %c, should be disabled\n",
1585              pipe_name(pipe));
1586
1587         val = I915_READ(PCH_LVDS);
1588         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590              pipe_name(pipe));
1591
1592         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598                            const struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_device *dev = crtc->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         i915_reg_t reg = DPLL(crtc->pipe);
1603         u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605         assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607         /* No really, not for ILK+ */
1608         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610         /* PLL is protected by panel, make sure we can write it */
1611         if (IS_MOBILE(dev_priv->dev))
1612                 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150);
1617
1618         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622         POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637                            const struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_device *dev = crtc->base.dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 tmp;
1644
1645         assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649         mutex_lock(&dev_priv->sb_lock);
1650
1651         /* Enable back the 10bit clock to display controller */
1652         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653         tmp |= DPIO_DCLKP_EN;
1654         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656         mutex_unlock(&dev_priv->sb_lock);
1657
1658         /*
1659          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660          */
1661         udelay(1);
1662
1663         /* Enable PLL */
1664         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666         /* Check PLL is locked */
1667         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670         /* not sure when this should be written */
1671         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672         POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677         struct intel_crtc *crtc;
1678         int count = 0;
1679
1680         for_each_intel_crtc(dev, crtc)
1681                 count += crtc->base.state->active &&
1682                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684         return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689         struct drm_device *dev = crtc->base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         i915_reg_t reg = DPLL(crtc->pipe);
1692         u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694         assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696         /* No really, not for ILK+ */
1697         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699         /* PLL is protected by panel, make sure we can write it */
1700         if (IS_MOBILE(dev) && !IS_I830(dev))
1701                 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703         /* Enable DVO 2x clock on both PLLs if necessary */
1704         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705                 /*
1706                  * It appears to be important that we don't enable this
1707                  * for the current pipe before otherwise configuring the
1708                  * PLL. No idea how this should be handled if multiple
1709                  * DVO outputs are enabled simultaneosly.
1710                  */
1711                 dpll |= DPLL_DVO_2X_MODE;
1712                 I915_WRITE(DPLL(!crtc->pipe),
1713                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714         }
1715
1716         /*
1717          * Apparently we need to have VGA mode enabled prior to changing
1718          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719          * dividers, even though the register value does change.
1720          */
1721         I915_WRITE(reg, 0);
1722
1723         I915_WRITE(reg, dpll);
1724
1725         /* Wait for the clocks to stabilize. */
1726         POSTING_READ(reg);
1727         udelay(150);
1728
1729         if (INTEL_INFO(dev)->gen >= 4) {
1730                 I915_WRITE(DPLL_MD(crtc->pipe),
1731                            crtc->config->dpll_hw_state.dpll_md);
1732         } else {
1733                 /* The pixel multiplier can only be updated once the
1734                  * DPLL is enabled and the clocks are stable.
1735                  *
1736                  * So write it again.
1737                  */
1738                 I915_WRITE(reg, dpll);
1739         }
1740
1741         /* We do this three times for luck */
1742         I915_WRITE(reg, dpll);
1743         POSTING_READ(reg);
1744         udelay(150); /* wait for warmup */
1745         I915_WRITE(reg, dpll);
1746         POSTING_READ(reg);
1747         udelay(150); /* wait for warmup */
1748         I915_WRITE(reg, dpll);
1749         POSTING_READ(reg);
1750         udelay(150); /* wait for warmup */
1751 }
1752
1753 /**
1754  * i9xx_disable_pll - disable a PLL
1755  * @dev_priv: i915 private structure
1756  * @pipe: pipe PLL to disable
1757  *
1758  * Disable the PLL for @pipe, making sure the pipe is off first.
1759  *
1760  * Note!  This is for pre-ILK only.
1761  */
1762 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 {
1764         struct drm_device *dev = crtc->base.dev;
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766         enum pipe pipe = crtc->pipe;
1767
1768         /* Disable DVO 2x clock on both PLLs if necessary */
1769         if (IS_I830(dev) &&
1770             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771             !intel_num_dvo_pipes(dev)) {
1772                 I915_WRITE(DPLL(PIPE_B),
1773                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774                 I915_WRITE(DPLL(PIPE_A),
1775                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776         }
1777
1778         /* Don't disable pipe or pipe PLLs if needed */
1779         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1780             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1781                 return;
1782
1783         /* Make sure the pipe isn't still relying on us */
1784         assert_pipe_disabled(dev_priv, pipe);
1785
1786         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1787         POSTING_READ(DPLL(pipe));
1788 }
1789
1790 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791 {
1792         u32 val;
1793
1794         /* Make sure the pipe isn't still relying on us */
1795         assert_pipe_disabled(dev_priv, pipe);
1796
1797         /*
1798          * Leave integrated clock source and reference clock enabled for pipe B.
1799          * The latter is needed for VGA hotplug / manual detection.
1800          */
1801         val = DPLL_VGA_MODE_DIS;
1802         if (pipe == PIPE_B)
1803                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1804         I915_WRITE(DPLL(pipe), val);
1805         POSTING_READ(DPLL(pipe));
1806
1807 }
1808
1809 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 {
1811         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1812         u32 val;
1813
1814         /* Make sure the pipe isn't still relying on us */
1815         assert_pipe_disabled(dev_priv, pipe);
1816
1817         /* Set PLL en = 0 */
1818         val = DPLL_SSC_REF_CLK_CHV |
1819                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820         if (pipe != PIPE_A)
1821                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822         I915_WRITE(DPLL(pipe), val);
1823         POSTING_READ(DPLL(pipe));
1824
1825         mutex_lock(&dev_priv->sb_lock);
1826
1827         /* Disable 10bit clock to display controller */
1828         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829         val &= ~DPIO_DCLKP_EN;
1830         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832         mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836                          struct intel_digital_port *dport,
1837                          unsigned int expected_mask)
1838 {
1839         u32 port_mask;
1840         i915_reg_t dpll_reg;
1841
1842         switch (dport->port) {
1843         case PORT_B:
1844                 port_mask = DPLL_PORTB_READY_MASK;
1845                 dpll_reg = DPLL(0);
1846                 break;
1847         case PORT_C:
1848                 port_mask = DPLL_PORTC_READY_MASK;
1849                 dpll_reg = DPLL(0);
1850                 expected_mask <<= 4;
1851                 break;
1852         case PORT_D:
1853                 port_mask = DPLL_PORTD_READY_MASK;
1854                 dpll_reg = DPIO_PHY_STATUS;
1855                 break;
1856         default:
1857                 BUG();
1858         }
1859
1860         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867         struct drm_device *dev = crtc->base.dev;
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871         if (WARN_ON(pll == NULL))
1872                 return;
1873
1874         WARN_ON(!pll->config.crtc_mask);
1875         if (pll->active == 0) {
1876                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877                 WARN_ON(pll->on);
1878                 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880                 pll->mode_set(dev_priv, pll);
1881         }
1882 }
1883
1884 /**
1885  * intel_enable_shared_dpll - enable PCH PLL
1886  * @dev_priv: i915 private structure
1887  * @pipe: pipe PLL to enable
1888  *
1889  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890  * drives the transcoder clock.
1891  */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894         struct drm_device *dev = crtc->base.dev;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898         if (WARN_ON(pll == NULL))
1899                 return;
1900
1901         if (WARN_ON(pll->config.crtc_mask == 0))
1902                 return;
1903
1904         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905                       pll->name, pll->active, pll->on,
1906                       crtc->base.base.id);
1907
1908         if (pll->active++) {
1909                 WARN_ON(!pll->on);
1910                 assert_shared_dpll_enabled(dev_priv, pll);
1911                 return;
1912         }
1913         WARN_ON(pll->on);
1914
1915         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918         pll->enable(dev_priv, pll);
1919         pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924         struct drm_device *dev = crtc->base.dev;
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928         /* PCH only available on ILK+ */
1929         if (INTEL_INFO(dev)->gen < 5)
1930                 return;
1931
1932         if (pll == NULL)
1933                 return;
1934
1935         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1936                 return;
1937
1938         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939                       pll->name, pll->active, pll->on,
1940                       crtc->base.base.id);
1941
1942         if (WARN_ON(pll->active == 0)) {
1943                 assert_shared_dpll_disabled(dev_priv, pll);
1944                 return;
1945         }
1946
1947         assert_shared_dpll_enabled(dev_priv, pll);
1948         WARN_ON(!pll->on);
1949         if (--pll->active)
1950                 return;
1951
1952         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1953         pll->disable(dev_priv, pll);
1954         pll->on = false;
1955
1956         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1957 }
1958
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1960                                            enum pipe pipe)
1961 {
1962         struct drm_device *dev = dev_priv->dev;
1963         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965         i915_reg_t reg;
1966         uint32_t val, pipeconf_val;
1967
1968         /* PCH only available on ILK+ */
1969         BUG_ON(!HAS_PCH_SPLIT(dev));
1970
1971         /* Make sure PCH DPLL is enabled */
1972         assert_shared_dpll_enabled(dev_priv,
1973                                    intel_crtc_to_shared_dpll(intel_crtc));
1974
1975         /* FDI must be feeding us bits for PCH ports */
1976         assert_fdi_tx_enabled(dev_priv, pipe);
1977         assert_fdi_rx_enabled(dev_priv, pipe);
1978
1979         if (HAS_PCH_CPT(dev)) {
1980                 /* Workaround: Set the timing override bit before enabling the
1981                  * pch transcoder. */
1982                 reg = TRANS_CHICKEN2(pipe);
1983                 val = I915_READ(reg);
1984                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1985                 I915_WRITE(reg, val);
1986         }
1987
1988         reg = PCH_TRANSCONF(pipe);
1989         val = I915_READ(reg);
1990         pipeconf_val = I915_READ(PIPECONF(pipe));
1991
1992         if (HAS_PCH_IBX(dev_priv->dev)) {
1993                 /*
1994                  * Make the BPC in transcoder be consistent with
1995                  * that in pipeconf reg. For HDMI we must use 8bpc
1996                  * here for both 8bpc and 12bpc.
1997                  */
1998                 val &= ~PIPECONF_BPC_MASK;
1999                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2000                         val |= PIPECONF_8BPC;
2001                 else
2002                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2003         }
2004
2005         val &= ~TRANS_INTERLACE_MASK;
2006         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2007                 if (HAS_PCH_IBX(dev_priv->dev) &&
2008                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2009                         val |= TRANS_LEGACY_INTERLACED_ILK;
2010                 else
2011                         val |= TRANS_INTERLACED;
2012         else
2013                 val |= TRANS_PROGRESSIVE;
2014
2015         I915_WRITE(reg, val | TRANS_ENABLE);
2016         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2017                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2018 }
2019
2020 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2021                                       enum transcoder cpu_transcoder)
2022 {
2023         u32 val, pipeconf_val;
2024
2025         /* PCH only available on ILK+ */
2026         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2027
2028         /* FDI must be feeding us bits for PCH ports */
2029         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2030         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2031
2032         /* Workaround: set timing override bit. */
2033         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2034         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2035         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2036
2037         val = TRANS_ENABLE;
2038         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2039
2040         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2041             PIPECONF_INTERLACED_ILK)
2042                 val |= TRANS_INTERLACED;
2043         else
2044                 val |= TRANS_PROGRESSIVE;
2045
2046         I915_WRITE(LPT_TRANSCONF, val);
2047         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2048                 DRM_ERROR("Failed to enable PCH transcoder\n");
2049 }
2050
2051 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2052                                             enum pipe pipe)
2053 {
2054         struct drm_device *dev = dev_priv->dev;
2055         i915_reg_t reg;
2056         uint32_t val;
2057
2058         /* FDI relies on the transcoder */
2059         assert_fdi_tx_disabled(dev_priv, pipe);
2060         assert_fdi_rx_disabled(dev_priv, pipe);
2061
2062         /* Ports must be off as well */
2063         assert_pch_ports_disabled(dev_priv, pipe);
2064
2065         reg = PCH_TRANSCONF(pipe);
2066         val = I915_READ(reg);
2067         val &= ~TRANS_ENABLE;
2068         I915_WRITE(reg, val);
2069         /* wait for PCH transcoder off, transcoder state */
2070         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2071                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2072
2073         if (HAS_PCH_CPT(dev)) {
2074                 /* Workaround: Clear the timing override chicken bit again. */
2075                 reg = TRANS_CHICKEN2(pipe);
2076                 val = I915_READ(reg);
2077                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2078                 I915_WRITE(reg, val);
2079         }
2080 }
2081
2082 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2083 {
2084         u32 val;
2085
2086         val = I915_READ(LPT_TRANSCONF);
2087         val &= ~TRANS_ENABLE;
2088         I915_WRITE(LPT_TRANSCONF, val);
2089         /* wait for PCH transcoder off, transcoder state */
2090         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2091                 DRM_ERROR("Failed to disable PCH transcoder\n");
2092
2093         /* Workaround: clear timing override bit. */
2094         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2095         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2096         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2097 }
2098
2099 /**
2100  * intel_enable_pipe - enable a pipe, asserting requirements
2101  * @crtc: crtc responsible for the pipe
2102  *
2103  * Enable @crtc's pipe, making sure that various hardware specific requirements
2104  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2105  */
2106 static void intel_enable_pipe(struct intel_crtc *crtc)
2107 {
2108         struct drm_device *dev = crtc->base.dev;
2109         struct drm_i915_private *dev_priv = dev->dev_private;
2110         enum pipe pipe = crtc->pipe;
2111         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2112         enum pipe pch_transcoder;
2113         i915_reg_t reg;
2114         u32 val;
2115
2116         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2117
2118         assert_planes_disabled(dev_priv, pipe);
2119         assert_cursor_disabled(dev_priv, pipe);
2120         assert_sprites_disabled(dev_priv, pipe);
2121
2122         if (HAS_PCH_LPT(dev_priv->dev))
2123                 pch_transcoder = TRANSCODER_A;
2124         else
2125                 pch_transcoder = pipe;
2126
2127         /*
2128          * A pipe without a PLL won't actually be able to drive bits from
2129          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2130          * need the check.
2131          */
2132         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2133                 if (crtc->config->has_dsi_encoder)
2134                         assert_dsi_pll_enabled(dev_priv);
2135                 else
2136                         assert_pll_enabled(dev_priv, pipe);
2137         else {
2138                 if (crtc->config->has_pch_encoder) {
2139                         /* if driving the PCH, we need FDI enabled */
2140                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2141                         assert_fdi_tx_pll_enabled(dev_priv,
2142                                                   (enum pipe) cpu_transcoder);
2143                 }
2144                 /* FIXME: assert CPU port conditions for SNB+ */
2145         }
2146
2147         reg = PIPECONF(cpu_transcoder);
2148         val = I915_READ(reg);
2149         if (val & PIPECONF_ENABLE) {
2150                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2151                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2152                 return;
2153         }
2154
2155         I915_WRITE(reg, val | PIPECONF_ENABLE);
2156         POSTING_READ(reg);
2157 }
2158
2159 /**
2160  * intel_disable_pipe - disable a pipe, asserting requirements
2161  * @crtc: crtc whose pipes is to be disabled
2162  *
2163  * Disable the pipe of @crtc, making sure that various hardware
2164  * specific requirements are met, if applicable, e.g. plane
2165  * disabled, panel fitter off, etc.
2166  *
2167  * Will wait until the pipe has shut down before returning.
2168  */
2169 static void intel_disable_pipe(struct intel_crtc *crtc)
2170 {
2171         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2172         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2173         enum pipe pipe = crtc->pipe;
2174         i915_reg_t reg;
2175         u32 val;
2176
2177         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2178
2179         /*
2180          * Make sure planes won't keep trying to pump pixels to us,
2181          * or we might hang the display.
2182          */
2183         assert_planes_disabled(dev_priv, pipe);
2184         assert_cursor_disabled(dev_priv, pipe);
2185         assert_sprites_disabled(dev_priv, pipe);
2186
2187         reg = PIPECONF(cpu_transcoder);
2188         val = I915_READ(reg);
2189         if ((val & PIPECONF_ENABLE) == 0)
2190                 return;
2191
2192         /*
2193          * Double wide has implications for planes
2194          * so best keep it disabled when not needed.
2195          */
2196         if (crtc->config->double_wide)
2197                 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199         /* Don't disable pipe or pipe PLLs if needed */
2200         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2202                 val &= ~PIPECONF_ENABLE;
2203
2204         I915_WRITE(reg, val);
2205         if ((val & PIPECONF_ENABLE) == 0)
2206                 intel_wait_for_pipe_off(crtc);
2207 }
2208
2209 static bool need_vtd_wa(struct drm_device *dev)
2210 {
2211 #ifdef CONFIG_INTEL_IOMMU
2212         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2213                 return true;
2214 #endif
2215         return false;
2216 }
2217
2218 unsigned int
2219 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2220                   uint64_t fb_format_modifier, unsigned int plane)
2221 {
2222         unsigned int tile_height;
2223         uint32_t pixel_bytes;
2224
2225         switch (fb_format_modifier) {
2226         case DRM_FORMAT_MOD_NONE:
2227                 tile_height = 1;
2228                 break;
2229         case I915_FORMAT_MOD_X_TILED:
2230                 tile_height = IS_GEN2(dev) ? 16 : 8;
2231                 break;
2232         case I915_FORMAT_MOD_Y_TILED:
2233                 tile_height = 32;
2234                 break;
2235         case I915_FORMAT_MOD_Yf_TILED:
2236                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2237                 switch (pixel_bytes) {
2238                 default:
2239                 case 1:
2240                         tile_height = 64;
2241                         break;
2242                 case 2:
2243                 case 4:
2244                         tile_height = 32;
2245                         break;
2246                 case 8:
2247                         tile_height = 16;
2248                         break;
2249                 case 16:
2250                         WARN_ONCE(1,
2251                                   "128-bit pixels are not supported for display!");
2252                         tile_height = 16;
2253                         break;
2254                 }
2255                 break;
2256         default:
2257                 MISSING_CASE(fb_format_modifier);
2258                 tile_height = 1;
2259                 break;
2260         }
2261
2262         return tile_height;
2263 }
2264
2265 unsigned int
2266 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2267                       uint32_t pixel_format, uint64_t fb_format_modifier)
2268 {
2269         return ALIGN(height, intel_tile_height(dev, pixel_format,
2270                                                fb_format_modifier, 0));
2271 }
2272
2273 static void
2274 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2275                         const struct drm_plane_state *plane_state)
2276 {
2277         struct intel_rotation_info *info = &view->params.rotation_info;
2278         unsigned int tile_height, tile_pitch;
2279
2280         *view = i915_ggtt_view_normal;
2281
2282         if (!plane_state)
2283                 return;
2284
2285         if (!intel_rotation_90_or_270(plane_state->rotation))
2286                 return;
2287
2288         *view = i915_ggtt_view_rotated;
2289
2290         info->height = fb->height;
2291         info->pixel_format = fb->pixel_format;
2292         info->pitch = fb->pitches[0];
2293         info->uv_offset = fb->offsets[1];
2294         info->fb_modifier = fb->modifier[0];
2295
2296         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2297                                         fb->modifier[0], 0);
2298         tile_pitch = PAGE_SIZE / tile_height;
2299         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2300         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2301         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2302
2303         if (info->pixel_format == DRM_FORMAT_NV12) {
2304                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305                                                 fb->modifier[0], 1);
2306                 tile_pitch = PAGE_SIZE / tile_height;
2307                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2309                                                      tile_height);
2310                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2311                                 PAGE_SIZE;
2312         }
2313 }
2314
2315 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2316 {
2317         if (INTEL_INFO(dev_priv)->gen >= 9)
2318                 return 256 * 1024;
2319         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2320                  IS_VALLEYVIEW(dev_priv))
2321                 return 128 * 1024;
2322         else if (INTEL_INFO(dev_priv)->gen >= 4)
2323                 return 4 * 1024;
2324         else
2325                 return 0;
2326 }
2327
2328 int
2329 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2330                            struct drm_framebuffer *fb,
2331                            const struct drm_plane_state *plane_state)
2332 {
2333         struct drm_device *dev = fb->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2336         struct i915_ggtt_view view;
2337         u32 alignment;
2338         int ret;
2339
2340         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2341
2342         switch (fb->modifier[0]) {
2343         case DRM_FORMAT_MOD_NONE:
2344                 alignment = intel_linear_alignment(dev_priv);
2345                 break;
2346         case I915_FORMAT_MOD_X_TILED:
2347                 if (INTEL_INFO(dev)->gen >= 9)
2348                         alignment = 256 * 1024;
2349                 else {
2350                         /* pin() will align the object as required by fence */
2351                         alignment = 0;
2352                 }
2353                 break;
2354         case I915_FORMAT_MOD_Y_TILED:
2355         case I915_FORMAT_MOD_Yf_TILED:
2356                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2357                           "Y tiling bo slipped through, driver bug!\n"))
2358                         return -EINVAL;
2359                 alignment = 1 * 1024 * 1024;
2360                 break;
2361         default:
2362                 MISSING_CASE(fb->modifier[0]);
2363                 return -EINVAL;
2364         }
2365
2366         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2367
2368         /* Note that the w/a also requires 64 PTE of padding following the
2369          * bo. We currently fill all unused PTE with the shadow page and so
2370          * we should always have valid PTE following the scanout preventing
2371          * the VT-d warning.
2372          */
2373         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2374                 alignment = 256 * 1024;
2375
2376         /*
2377          * Global gtt pte registers are special registers which actually forward
2378          * writes to a chunk of system memory. Which means that there is no risk
2379          * that the register values disappear as soon as we call
2380          * intel_runtime_pm_put(), so it is correct to wrap only the
2381          * pin/unpin/fence and not more.
2382          */
2383         intel_runtime_pm_get(dev_priv);
2384
2385         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2386                                                    &view);
2387         if (ret)
2388                 goto err_pm;
2389
2390         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2391          * fence, whereas 965+ only requires a fence if using
2392          * framebuffer compression.  For simplicity, we always install
2393          * a fence as the cost is not that onerous.
2394          */
2395         if (view.type == I915_GGTT_VIEW_NORMAL) {
2396                 ret = i915_gem_object_get_fence(obj);
2397                 if (ret == -EDEADLK) {
2398                         /*
2399                          * -EDEADLK means there are no free fences
2400                          * no pending flips.
2401                          *
2402                          * This is propagated to atomic, but it uses
2403                          * -EDEADLK to force a locking recovery, so
2404                          * change the returned error to -EBUSY.
2405                          */
2406                         ret = -EBUSY;
2407                         goto err_unpin;
2408                 } else if (ret)
2409                         goto err_unpin;
2410
2411                 i915_gem_object_pin_fence(obj);
2412         }
2413
2414         intel_runtime_pm_put(dev_priv);
2415         return 0;
2416
2417 err_unpin:
2418         i915_gem_object_unpin_from_display_plane(obj, &view);
2419 err_pm:
2420         intel_runtime_pm_put(dev_priv);
2421         return ret;
2422 }
2423
2424 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2425                                const struct drm_plane_state *plane_state)
2426 {
2427         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2428         struct i915_ggtt_view view;
2429
2430         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2431
2432         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2433
2434         if (view.type == I915_GGTT_VIEW_NORMAL)
2435                 i915_gem_object_unpin_fence(obj);
2436
2437         i915_gem_object_unpin_from_display_plane(obj, &view);
2438 }
2439
2440 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2441  * is assumed to be a power-of-two. */
2442 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2443                                              int *x, int *y,
2444                                              unsigned int tiling_mode,
2445                                              unsigned int cpp,
2446                                              unsigned int pitch)
2447 {
2448         if (tiling_mode != I915_TILING_NONE) {
2449                 unsigned int tile_rows, tiles;
2450
2451                 tile_rows = *y / 8;
2452                 *y %= 8;
2453
2454                 tiles = *x / (512/cpp);
2455                 *x %= 512/cpp;
2456
2457                 return tile_rows * pitch * 8 + tiles * 4096;
2458         } else {
2459                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2460                 unsigned int offset;
2461
2462                 offset = *y * pitch + *x * cpp;
2463                 *y = (offset & alignment) / pitch;
2464                 *x = ((offset & alignment) - *y * pitch) / cpp;
2465                 return offset & ~alignment;
2466         }
2467 }
2468
2469 static int i9xx_format_to_fourcc(int format)
2470 {
2471         switch (format) {
2472         case DISPPLANE_8BPP:
2473                 return DRM_FORMAT_C8;
2474         case DISPPLANE_BGRX555:
2475                 return DRM_FORMAT_XRGB1555;
2476         case DISPPLANE_BGRX565:
2477                 return DRM_FORMAT_RGB565;
2478         default:
2479         case DISPPLANE_BGRX888:
2480                 return DRM_FORMAT_XRGB8888;
2481         case DISPPLANE_RGBX888:
2482                 return DRM_FORMAT_XBGR8888;
2483         case DISPPLANE_BGRX101010:
2484                 return DRM_FORMAT_XRGB2101010;
2485         case DISPPLANE_RGBX101010:
2486                 return DRM_FORMAT_XBGR2101010;
2487         }
2488 }
2489
2490 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2491 {
2492         switch (format) {
2493         case PLANE_CTL_FORMAT_RGB_565:
2494                 return DRM_FORMAT_RGB565;
2495         default:
2496         case PLANE_CTL_FORMAT_XRGB_8888:
2497                 if (rgb_order) {
2498                         if (alpha)
2499                                 return DRM_FORMAT_ABGR8888;
2500                         else
2501                                 return DRM_FORMAT_XBGR8888;
2502                 } else {
2503                         if (alpha)
2504                                 return DRM_FORMAT_ARGB8888;
2505                         else
2506                                 return DRM_FORMAT_XRGB8888;
2507                 }
2508         case PLANE_CTL_FORMAT_XRGB_2101010:
2509                 if (rgb_order)
2510                         return DRM_FORMAT_XBGR2101010;
2511                 else
2512                         return DRM_FORMAT_XRGB2101010;
2513         }
2514 }
2515
2516 static bool
2517 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2518                               struct intel_initial_plane_config *plane_config)
2519 {
2520         struct drm_device *dev = crtc->base.dev;
2521         struct drm_i915_private *dev_priv = to_i915(dev);
2522         struct drm_i915_gem_object *obj = NULL;
2523         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2524         struct drm_framebuffer *fb = &plane_config->fb->base;
2525         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2526         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2527                                     PAGE_SIZE);
2528
2529         size_aligned -= base_aligned;
2530
2531         if (plane_config->size == 0)
2532                 return false;
2533
2534         /* If the FB is too big, just don't use it since fbdev is not very
2535          * important and we should probably use that space with FBC or other
2536          * features. */
2537         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2538                 return false;
2539
2540         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541                                                              base_aligned,
2542                                                              base_aligned,
2543                                                              size_aligned);
2544         if (!obj)
2545                 return false;
2546
2547         obj->tiling_mode = plane_config->tiling;
2548         if (obj->tiling_mode == I915_TILING_X)
2549                 obj->stride = fb->pitches[0];
2550
2551         mode_cmd.pixel_format = fb->pixel_format;
2552         mode_cmd.width = fb->width;
2553         mode_cmd.height = fb->height;
2554         mode_cmd.pitches[0] = fb->pitches[0];
2555         mode_cmd.modifier[0] = fb->modifier[0];
2556         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2557
2558         mutex_lock(&dev->struct_mutex);
2559         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2560                                    &mode_cmd, obj)) {
2561                 DRM_DEBUG_KMS("intel fb init failed\n");
2562                 goto out_unref_obj;
2563         }
2564         mutex_unlock(&dev->struct_mutex);
2565
2566         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2567         return true;
2568
2569 out_unref_obj:
2570         drm_gem_object_unreference(&obj->base);
2571         mutex_unlock(&dev->struct_mutex);
2572         return false;
2573 }
2574
2575 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2576 static void
2577 update_state_fb(struct drm_plane *plane)
2578 {
2579         if (plane->fb == plane->state->fb)
2580                 return;
2581
2582         if (plane->state->fb)
2583                 drm_framebuffer_unreference(plane->state->fb);
2584         plane->state->fb = plane->fb;
2585         if (plane->state->fb)
2586                 drm_framebuffer_reference(plane->state->fb);
2587 }
2588
2589 static void
2590 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591                              struct intel_initial_plane_config *plane_config)
2592 {
2593         struct drm_device *dev = intel_crtc->base.dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct drm_crtc *c;
2596         struct intel_crtc *i;
2597         struct drm_i915_gem_object *obj;
2598         struct drm_plane *primary = intel_crtc->base.primary;
2599         struct drm_plane_state *plane_state = primary->state;
2600         struct drm_framebuffer *fb;
2601
2602         if (!plane_config->fb)
2603                 return;
2604
2605         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2606                 fb = &plane_config->fb->base;
2607                 goto valid_fb;
2608         }
2609
2610         kfree(plane_config->fb);
2611
2612         /*
2613          * Failed to alloc the obj, check to see if we should share
2614          * an fb with another CRTC instead
2615          */
2616         for_each_crtc(dev, c) {
2617                 i = to_intel_crtc(c);
2618
2619                 if (c == &intel_crtc->base)
2620                         continue;
2621
2622                 if (!i->active)
2623                         continue;
2624
2625                 fb = c->primary->fb;
2626                 if (!fb)
2627                         continue;
2628
2629                 obj = intel_fb_obj(fb);
2630                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2631                         drm_framebuffer_reference(fb);
2632                         goto valid_fb;
2633                 }
2634         }
2635
2636         return;
2637
2638 valid_fb:
2639         plane_state->src_x = 0;
2640         plane_state->src_y = 0;
2641         plane_state->src_w = fb->width << 16;
2642         plane_state->src_h = fb->height << 16;
2643
2644         plane_state->crtc_x = 0;
2645         plane_state->crtc_y = 0;
2646         plane_state->crtc_w = fb->width;
2647         plane_state->crtc_h = fb->height;
2648
2649         obj = intel_fb_obj(fb);
2650         if (obj->tiling_mode != I915_TILING_NONE)
2651                 dev_priv->preserve_bios_swizzle = true;
2652
2653         drm_framebuffer_reference(fb);
2654         primary->fb = primary->state->fb = fb;
2655         primary->crtc = primary->state->crtc = &intel_crtc->base;
2656         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2657         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2658 }
2659
2660 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2661                                       struct drm_framebuffer *fb,
2662                                       int x, int y)
2663 {
2664         struct drm_device *dev = crtc->dev;
2665         struct drm_i915_private *dev_priv = dev->dev_private;
2666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2667         struct drm_plane *primary = crtc->primary;
2668         bool visible = to_intel_plane_state(primary->state)->visible;
2669         struct drm_i915_gem_object *obj;
2670         int plane = intel_crtc->plane;
2671         unsigned long linear_offset;
2672         u32 dspcntr;
2673         i915_reg_t reg = DSPCNTR(plane);
2674         int pixel_size;
2675
2676         if (!visible || !fb) {
2677                 I915_WRITE(reg, 0);
2678                 if (INTEL_INFO(dev)->gen >= 4)
2679                         I915_WRITE(DSPSURF(plane), 0);
2680                 else
2681                         I915_WRITE(DSPADDR(plane), 0);
2682                 POSTING_READ(reg);
2683                 return;
2684         }
2685
2686         obj = intel_fb_obj(fb);
2687         if (WARN_ON(obj == NULL))
2688                 return;
2689
2690         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2691
2692         dspcntr = DISPPLANE_GAMMA_ENABLE;
2693
2694         dspcntr |= DISPLAY_PLANE_ENABLE;
2695
2696         if (INTEL_INFO(dev)->gen < 4) {
2697                 if (intel_crtc->pipe == PIPE_B)
2698                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2699
2700                 /* pipesrc and dspsize control the size that is scaled from,
2701                  * which should always be the user's requested size.
2702                  */
2703                 I915_WRITE(DSPSIZE(plane),
2704                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705                            (intel_crtc->config->pipe_src_w - 1));
2706                 I915_WRITE(DSPPOS(plane), 0);
2707         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2708                 I915_WRITE(PRIMSIZE(plane),
2709                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2710                            (intel_crtc->config->pipe_src_w - 1));
2711                 I915_WRITE(PRIMPOS(plane), 0);
2712                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2713         }
2714
2715         switch (fb->pixel_format) {
2716         case DRM_FORMAT_C8:
2717                 dspcntr |= DISPPLANE_8BPP;
2718                 break;
2719         case DRM_FORMAT_XRGB1555:
2720                 dspcntr |= DISPPLANE_BGRX555;
2721                 break;
2722         case DRM_FORMAT_RGB565:
2723                 dspcntr |= DISPPLANE_BGRX565;
2724                 break;
2725         case DRM_FORMAT_XRGB8888:
2726                 dspcntr |= DISPPLANE_BGRX888;
2727                 break;
2728         case DRM_FORMAT_XBGR8888:
2729                 dspcntr |= DISPPLANE_RGBX888;
2730                 break;
2731         case DRM_FORMAT_XRGB2101010:
2732                 dspcntr |= DISPPLANE_BGRX101010;
2733                 break;
2734         case DRM_FORMAT_XBGR2101010:
2735                 dspcntr |= DISPPLANE_RGBX101010;
2736                 break;
2737         default:
2738                 BUG();
2739         }
2740
2741         if (INTEL_INFO(dev)->gen >= 4 &&
2742             obj->tiling_mode != I915_TILING_NONE)
2743                 dspcntr |= DISPPLANE_TILED;
2744
2745         if (IS_G4X(dev))
2746                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2747
2748         linear_offset = y * fb->pitches[0] + x * pixel_size;
2749
2750         if (INTEL_INFO(dev)->gen >= 4) {
2751                 intel_crtc->dspaddr_offset =
2752                         intel_gen4_compute_page_offset(dev_priv,
2753                                                        &x, &y, obj->tiling_mode,
2754                                                        pixel_size,
2755                                                        fb->pitches[0]);
2756                 linear_offset -= intel_crtc->dspaddr_offset;
2757         } else {
2758                 intel_crtc->dspaddr_offset = linear_offset;
2759         }
2760
2761         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2762                 dspcntr |= DISPPLANE_ROTATE_180;
2763
2764                 x += (intel_crtc->config->pipe_src_w - 1);
2765                 y += (intel_crtc->config->pipe_src_h - 1);
2766
2767                 /* Finding the last pixel of the last line of the display
2768                 data and adding to linear_offset*/
2769                 linear_offset +=
2770                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2771                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2772         }
2773
2774         intel_crtc->adjusted_x = x;
2775         intel_crtc->adjusted_y = y;
2776
2777         I915_WRITE(reg, dspcntr);
2778
2779         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2780         if (INTEL_INFO(dev)->gen >= 4) {
2781                 I915_WRITE(DSPSURF(plane),
2782                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2783                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2784                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2785         } else
2786                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2787         POSTING_READ(reg);
2788 }
2789
2790 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2791                                           struct drm_framebuffer *fb,
2792                                           int x, int y)
2793 {
2794         struct drm_device *dev = crtc->dev;
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797         struct drm_plane *primary = crtc->primary;
2798         bool visible = to_intel_plane_state(primary->state)->visible;
2799         struct drm_i915_gem_object *obj;
2800         int plane = intel_crtc->plane;
2801         unsigned long linear_offset;
2802         u32 dspcntr;
2803         i915_reg_t reg = DSPCNTR(plane);
2804         int pixel_size;
2805
2806         if (!visible || !fb) {
2807                 I915_WRITE(reg, 0);
2808                 I915_WRITE(DSPSURF(plane), 0);
2809                 POSTING_READ(reg);
2810                 return;
2811         }
2812
2813         obj = intel_fb_obj(fb);
2814         if (WARN_ON(obj == NULL))
2815                 return;
2816
2817         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2818
2819         dspcntr = DISPPLANE_GAMMA_ENABLE;
2820
2821         dspcntr |= DISPLAY_PLANE_ENABLE;
2822
2823         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2824                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2825
2826         switch (fb->pixel_format) {
2827         case DRM_FORMAT_C8:
2828                 dspcntr |= DISPPLANE_8BPP;
2829                 break;
2830         case DRM_FORMAT_RGB565:
2831                 dspcntr |= DISPPLANE_BGRX565;
2832                 break;
2833         case DRM_FORMAT_XRGB8888:
2834                 dspcntr |= DISPPLANE_BGRX888;
2835                 break;
2836         case DRM_FORMAT_XBGR8888:
2837                 dspcntr |= DISPPLANE_RGBX888;
2838                 break;
2839         case DRM_FORMAT_XRGB2101010:
2840                 dspcntr |= DISPPLANE_BGRX101010;
2841                 break;
2842         case DRM_FORMAT_XBGR2101010:
2843                 dspcntr |= DISPPLANE_RGBX101010;
2844                 break;
2845         default:
2846                 BUG();
2847         }
2848
2849         if (obj->tiling_mode != I915_TILING_NONE)
2850                 dspcntr |= DISPPLANE_TILED;
2851
2852         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2853                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2854
2855         linear_offset = y * fb->pitches[0] + x * pixel_size;
2856         intel_crtc->dspaddr_offset =
2857                 intel_gen4_compute_page_offset(dev_priv,
2858                                                &x, &y, obj->tiling_mode,
2859                                                pixel_size,
2860                                                fb->pitches[0]);
2861         linear_offset -= intel_crtc->dspaddr_offset;
2862         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2863                 dspcntr |= DISPPLANE_ROTATE_180;
2864
2865                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2866                         x += (intel_crtc->config->pipe_src_w - 1);
2867                         y += (intel_crtc->config->pipe_src_h - 1);
2868
2869                         /* Finding the last pixel of the last line of the display
2870                         data and adding to linear_offset*/
2871                         linear_offset +=
2872                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2873                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2874                 }
2875         }
2876
2877         intel_crtc->adjusted_x = x;
2878         intel_crtc->adjusted_y = y;
2879
2880         I915_WRITE(reg, dspcntr);
2881
2882         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2883         I915_WRITE(DSPSURF(plane),
2884                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2885         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2886                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2887         } else {
2888                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2889                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2890         }
2891         POSTING_READ(reg);
2892 }
2893
2894 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2895                               uint32_t pixel_format)
2896 {
2897         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2898
2899         /*
2900          * The stride is either expressed as a multiple of 64 bytes
2901          * chunks for linear buffers or in number of tiles for tiled
2902          * buffers.
2903          */
2904         switch (fb_modifier) {
2905         case DRM_FORMAT_MOD_NONE:
2906                 return 64;
2907         case I915_FORMAT_MOD_X_TILED:
2908                 if (INTEL_INFO(dev)->gen == 2)
2909                         return 128;
2910                 return 512;
2911         case I915_FORMAT_MOD_Y_TILED:
2912                 /* No need to check for old gens and Y tiling since this is
2913                  * about the display engine and those will be blocked before
2914                  * we get here.
2915                  */
2916                 return 128;
2917         case I915_FORMAT_MOD_Yf_TILED:
2918                 if (bits_per_pixel == 8)
2919                         return 64;
2920                 else
2921                         return 128;
2922         default:
2923                 MISSING_CASE(fb_modifier);
2924                 return 64;
2925         }
2926 }
2927
2928 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2929                            struct drm_i915_gem_object *obj,
2930                            unsigned int plane)
2931 {
2932         struct i915_ggtt_view view;
2933         struct i915_vma *vma;
2934         u64 offset;
2935
2936         intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2937                                 intel_plane->base.state);
2938
2939         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2940         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2941                 view.type))
2942                 return -1;
2943
2944         offset = vma->node.start;
2945
2946         if (plane == 1) {
2947                 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2948                           PAGE_SIZE;
2949         }
2950
2951         WARN_ON(upper_32_bits(offset));
2952
2953         return lower_32_bits(offset);
2954 }
2955
2956 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2957 {
2958         struct drm_device *dev = intel_crtc->base.dev;
2959         struct drm_i915_private *dev_priv = dev->dev_private;
2960
2961         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2962         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2963         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2964 }
2965
2966 /*
2967  * This function detaches (aka. unbinds) unused scalers in hardware
2968  */
2969 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2970 {
2971         struct intel_crtc_scaler_state *scaler_state;
2972         int i;
2973
2974         scaler_state = &intel_crtc->config->scaler_state;
2975
2976         /* loop through and disable scalers that aren't in use */
2977         for (i = 0; i < intel_crtc->num_scalers; i++) {
2978                 if (!scaler_state->scalers[i].in_use)
2979                         skl_detach_scaler(intel_crtc, i);
2980         }
2981 }
2982
2983 u32 skl_plane_ctl_format(uint32_t pixel_format)
2984 {
2985         switch (pixel_format) {
2986         case DRM_FORMAT_C8:
2987                 return PLANE_CTL_FORMAT_INDEXED;
2988         case DRM_FORMAT_RGB565:
2989                 return PLANE_CTL_FORMAT_RGB_565;
2990         case DRM_FORMAT_XBGR8888:
2991                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2992         case DRM_FORMAT_XRGB8888:
2993                 return PLANE_CTL_FORMAT_XRGB_8888;
2994         /*
2995          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2996          * to be already pre-multiplied. We need to add a knob (or a different
2997          * DRM_FORMAT) for user-space to configure that.
2998          */
2999         case DRM_FORMAT_ABGR8888:
3000                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3001                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3002         case DRM_FORMAT_ARGB8888:
3003                 return PLANE_CTL_FORMAT_XRGB_8888 |
3004                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3005         case DRM_FORMAT_XRGB2101010:
3006                 return PLANE_CTL_FORMAT_XRGB_2101010;
3007         case DRM_FORMAT_XBGR2101010:
3008                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3009         case DRM_FORMAT_YUYV:
3010                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3011         case DRM_FORMAT_YVYU:
3012                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3013         case DRM_FORMAT_UYVY:
3014                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3015         case DRM_FORMAT_VYUY:
3016                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3017         default:
3018                 MISSING_CASE(pixel_format);
3019         }
3020
3021         return 0;
3022 }
3023
3024 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3025 {
3026         switch (fb_modifier) {
3027         case DRM_FORMAT_MOD_NONE:
3028                 break;
3029         case I915_FORMAT_MOD_X_TILED:
3030                 return PLANE_CTL_TILED_X;
3031         case I915_FORMAT_MOD_Y_TILED:
3032                 return PLANE_CTL_TILED_Y;
3033         case I915_FORMAT_MOD_Yf_TILED:
3034                 return PLANE_CTL_TILED_YF;
3035         default:
3036                 MISSING_CASE(fb_modifier);
3037         }
3038
3039         return 0;
3040 }
3041
3042 u32 skl_plane_ctl_rotation(unsigned int rotation)
3043 {
3044         switch (rotation) {
3045         case BIT(DRM_ROTATE_0):
3046                 break;
3047         /*
3048          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3049          * while i915 HW rotation is clockwise, thats why this swapping.
3050          */
3051         case BIT(DRM_ROTATE_90):
3052                 return PLANE_CTL_ROTATE_270;
3053         case BIT(DRM_ROTATE_180):
3054                 return PLANE_CTL_ROTATE_180;
3055         case BIT(DRM_ROTATE_270):
3056                 return PLANE_CTL_ROTATE_90;
3057         default:
3058                 MISSING_CASE(rotation);
3059         }
3060
3061         return 0;
3062 }
3063
3064 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3065                                          struct drm_framebuffer *fb,
3066                                          int x, int y)
3067 {
3068         struct drm_device *dev = crtc->dev;
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3071         struct drm_plane *plane = crtc->primary;
3072         bool visible = to_intel_plane_state(plane->state)->visible;
3073         struct drm_i915_gem_object *obj;
3074         int pipe = intel_crtc->pipe;
3075         u32 plane_ctl, stride_div, stride;
3076         u32 tile_height, plane_offset, plane_size;
3077         unsigned int rotation;
3078         int x_offset, y_offset;
3079         u32 surf_addr;
3080         struct intel_crtc_state *crtc_state = intel_crtc->config;
3081         struct intel_plane_state *plane_state;
3082         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3083         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3084         int scaler_id = -1;
3085
3086         plane_state = to_intel_plane_state(plane->state);
3087
3088         if (!visible || !fb) {
3089                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3090                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3091                 POSTING_READ(PLANE_CTL(pipe, 0));
3092                 return;
3093         }
3094
3095         plane_ctl = PLANE_CTL_ENABLE |
3096                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3097                     PLANE_CTL_PIPE_CSC_ENABLE;
3098
3099         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3100         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3101         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3102
3103         rotation = plane->state->rotation;
3104         plane_ctl |= skl_plane_ctl_rotation(rotation);
3105
3106         obj = intel_fb_obj(fb);
3107         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3108                                                fb->pixel_format);
3109         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3110
3111         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3112
3113         scaler_id = plane_state->scaler_id;
3114         src_x = plane_state->src.x1 >> 16;
3115         src_y = plane_state->src.y1 >> 16;
3116         src_w = drm_rect_width(&plane_state->src) >> 16;
3117         src_h = drm_rect_height(&plane_state->src) >> 16;
3118         dst_x = plane_state->dst.x1;
3119         dst_y = plane_state->dst.y1;
3120         dst_w = drm_rect_width(&plane_state->dst);
3121         dst_h = drm_rect_height(&plane_state->dst);
3122
3123         WARN_ON(x != src_x || y != src_y);
3124
3125         if (intel_rotation_90_or_270(rotation)) {
3126                 /* stride = Surface height in tiles */
3127                 tile_height = intel_tile_height(dev, fb->pixel_format,
3128                                                 fb->modifier[0], 0);
3129                 stride = DIV_ROUND_UP(fb->height, tile_height);
3130                 x_offset = stride * tile_height - y - src_h;
3131                 y_offset = x;
3132                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3133         } else {
3134                 stride = fb->pitches[0] / stride_div;
3135                 x_offset = x;
3136                 y_offset = y;
3137                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3138         }
3139         plane_offset = y_offset << 16 | x_offset;
3140
3141         intel_crtc->adjusted_x = x_offset;
3142         intel_crtc->adjusted_y = y_offset;
3143
3144         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3145         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3146         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3147         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3148
3149         if (scaler_id >= 0) {
3150                 uint32_t ps_ctrl = 0;
3151
3152                 WARN_ON(!dst_w || !dst_h);
3153                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3154                         crtc_state->scaler_state.scalers[scaler_id].mode;
3155                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3156                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3157                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3158                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3159                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3160         } else {
3161                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3162         }
3163
3164         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3165
3166         POSTING_READ(PLANE_SURF(pipe, 0));
3167 }
3168
3169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3170 static int
3171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3172                            int x, int y, enum mode_set_atomic state)
3173 {
3174         struct drm_device *dev = crtc->dev;
3175         struct drm_i915_private *dev_priv = dev->dev_private;
3176
3177         if (dev_priv->fbc.disable_fbc)
3178                 dev_priv->fbc.disable_fbc(dev_priv);
3179
3180         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3181
3182         return 0;
3183 }
3184
3185 static void intel_complete_page_flips(struct drm_device *dev)
3186 {
3187         struct drm_crtc *crtc;
3188
3189         for_each_crtc(dev, crtc) {
3190                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3191                 enum plane plane = intel_crtc->plane;
3192
3193                 intel_prepare_page_flip(dev, plane);
3194                 intel_finish_page_flip_plane(dev, plane);
3195         }
3196 }
3197
3198 static void intel_update_primary_planes(struct drm_device *dev)
3199 {
3200         struct drm_crtc *crtc;
3201
3202         for_each_crtc(dev, crtc) {
3203                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3204                 struct intel_plane_state *plane_state;
3205
3206                 drm_modeset_lock_crtc(crtc, &plane->base);
3207                 plane_state = to_intel_plane_state(plane->base.state);
3208
3209                 if (crtc->state->active && plane_state->base.fb)
3210                         plane->commit_plane(&plane->base, plane_state);
3211
3212                 drm_modeset_unlock_crtc(crtc);
3213         }
3214 }
3215
3216 void intel_prepare_reset(struct drm_device *dev)
3217 {
3218         /* no reset support for gen2 */
3219         if (IS_GEN2(dev))
3220                 return;
3221
3222         /* reset doesn't touch the display */
3223         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3224                 return;
3225
3226         drm_modeset_lock_all(dev);
3227         /*
3228          * Disabling the crtcs gracefully seems nicer. Also the
3229          * g33 docs say we should at least disable all the planes.
3230          */
3231         intel_display_suspend(dev);
3232 }
3233
3234 void intel_finish_reset(struct drm_device *dev)
3235 {
3236         struct drm_i915_private *dev_priv = to_i915(dev);
3237
3238         /*
3239          * Flips in the rings will be nuked by the reset,
3240          * so complete all pending flips so that user space
3241          * will get its events and not get stuck.
3242          */
3243         intel_complete_page_flips(dev);
3244
3245         /* no reset support for gen2 */
3246         if (IS_GEN2(dev))
3247                 return;
3248
3249         /* reset doesn't touch the display */
3250         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3251                 /*
3252                  * Flips in the rings have been nuked by the reset,
3253                  * so update the base address of all primary
3254                  * planes to the the last fb to make sure we're
3255                  * showing the correct fb after a reset.
3256                  *
3257                  * FIXME: Atomic will make this obsolete since we won't schedule
3258                  * CS-based flips (which might get lost in gpu resets) any more.
3259                  */
3260                 intel_update_primary_planes(dev);
3261                 return;
3262         }
3263
3264         /*
3265          * The display has been reset as well,
3266          * so need a full re-initialization.
3267          */
3268         intel_runtime_pm_disable_interrupts(dev_priv);
3269         intel_runtime_pm_enable_interrupts(dev_priv);
3270
3271         intel_modeset_init_hw(dev);
3272
3273         spin_lock_irq(&dev_priv->irq_lock);
3274         if (dev_priv->display.hpd_irq_setup)
3275                 dev_priv->display.hpd_irq_setup(dev);
3276         spin_unlock_irq(&dev_priv->irq_lock);
3277
3278         intel_display_resume(dev);
3279
3280         intel_hpd_init(dev_priv);
3281
3282         drm_modeset_unlock_all(dev);
3283 }
3284
3285 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3286 {
3287         struct drm_device *dev = crtc->dev;
3288         struct drm_i915_private *dev_priv = dev->dev_private;
3289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290         bool pending;
3291
3292         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3293             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3294                 return false;
3295
3296         spin_lock_irq(&dev->event_lock);
3297         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3298         spin_unlock_irq(&dev->event_lock);
3299
3300         return pending;
3301 }
3302
3303 static void intel_update_pipe_config(struct intel_crtc *crtc,
3304                                      struct intel_crtc_state *old_crtc_state)
3305 {
3306         struct drm_device *dev = crtc->base.dev;
3307         struct drm_i915_private *dev_priv = dev->dev_private;
3308         struct intel_crtc_state *pipe_config =
3309                 to_intel_crtc_state(crtc->base.state);
3310
3311         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3312         crtc->base.mode = crtc->base.state->mode;
3313
3314         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3315                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3316                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3317
3318         if (HAS_DDI(dev))
3319                 intel_set_pipe_csc(&crtc->base);
3320
3321         /*
3322          * Update pipe size and adjust fitter if needed: the reason for this is
3323          * that in compute_mode_changes we check the native mode (not the pfit
3324          * mode) to see if we can flip rather than do a full mode set. In the
3325          * fastboot case, we'll flip, but if we don't update the pipesrc and
3326          * pfit state, we'll end up with a big fb scanned out into the wrong
3327          * sized surface.
3328          */
3329
3330         I915_WRITE(PIPESRC(crtc->pipe),
3331                    ((pipe_config->pipe_src_w - 1) << 16) |
3332                    (pipe_config->pipe_src_h - 1));
3333
3334         /* on skylake this is done by detaching scalers */
3335         if (INTEL_INFO(dev)->gen >= 9) {
3336                 skl_detach_scalers(crtc);
3337
3338                 if (pipe_config->pch_pfit.enabled)
3339                         skylake_pfit_enable(crtc);
3340         } else if (HAS_PCH_SPLIT(dev)) {
3341                 if (pipe_config->pch_pfit.enabled)
3342                         ironlake_pfit_enable(crtc);
3343                 else if (old_crtc_state->pch_pfit.enabled)
3344                         ironlake_pfit_disable(crtc, true);
3345         }
3346 }
3347
3348 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3349 {
3350         struct drm_device *dev = crtc->dev;
3351         struct drm_i915_private *dev_priv = dev->dev_private;
3352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3353         int pipe = intel_crtc->pipe;
3354         i915_reg_t reg;
3355         u32 temp;
3356
3357         /* enable normal train */
3358         reg = FDI_TX_CTL(pipe);
3359         temp = I915_READ(reg);
3360         if (IS_IVYBRIDGE(dev)) {
3361                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3362                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3363         } else {
3364                 temp &= ~FDI_LINK_TRAIN_NONE;
3365                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3366         }
3367         I915_WRITE(reg, temp);
3368
3369         reg = FDI_RX_CTL(pipe);
3370         temp = I915_READ(reg);
3371         if (HAS_PCH_CPT(dev)) {
3372                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3373                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3374         } else {
3375                 temp &= ~FDI_LINK_TRAIN_NONE;
3376                 temp |= FDI_LINK_TRAIN_NONE;
3377         }
3378         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3379
3380         /* wait one idle pattern time */
3381         POSTING_READ(reg);
3382         udelay(1000);
3383
3384         /* IVB wants error correction enabled */
3385         if (IS_IVYBRIDGE(dev))
3386                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3387                            FDI_FE_ERRC_ENABLE);
3388 }
3389
3390 /* The FDI link training functions for ILK/Ibexpeak. */
3391 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3392 {
3393         struct drm_device *dev = crtc->dev;
3394         struct drm_i915_private *dev_priv = dev->dev_private;
3395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396         int pipe = intel_crtc->pipe;
3397         i915_reg_t reg;
3398         u32 temp, tries;
3399
3400         /* FDI needs bits from pipe first */
3401         assert_pipe_enabled(dev_priv, pipe);
3402
3403         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404            for train result */
3405         reg = FDI_RX_IMR(pipe);
3406         temp = I915_READ(reg);
3407         temp &= ~FDI_RX_SYMBOL_LOCK;
3408         temp &= ~FDI_RX_BIT_LOCK;
3409         I915_WRITE(reg, temp);
3410         I915_READ(reg);
3411         udelay(150);
3412
3413         /* enable CPU FDI TX and PCH FDI RX */
3414         reg = FDI_TX_CTL(pipe);
3415         temp = I915_READ(reg);
3416         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3417         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3418         temp &= ~FDI_LINK_TRAIN_NONE;
3419         temp |= FDI_LINK_TRAIN_PATTERN_1;
3420         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3421
3422         reg = FDI_RX_CTL(pipe);
3423         temp = I915_READ(reg);
3424         temp &= ~FDI_LINK_TRAIN_NONE;
3425         temp |= FDI_LINK_TRAIN_PATTERN_1;
3426         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428         POSTING_READ(reg);
3429         udelay(150);
3430
3431         /* Ironlake workaround, enable clock pointer after FDI enable*/
3432         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434                    FDI_RX_PHASE_SYNC_POINTER_EN);
3435
3436         reg = FDI_RX_IIR(pipe);
3437         for (tries = 0; tries < 5; tries++) {
3438                 temp = I915_READ(reg);
3439                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441                 if ((temp & FDI_RX_BIT_LOCK)) {
3442                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3443                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3444                         break;
3445                 }
3446         }
3447         if (tries == 5)
3448                 DRM_ERROR("FDI train 1 fail!\n");
3449
3450         /* Train 2 */
3451         reg = FDI_TX_CTL(pipe);
3452         temp = I915_READ(reg);
3453         temp &= ~FDI_LINK_TRAIN_NONE;
3454         temp |= FDI_LINK_TRAIN_PATTERN_2;
3455         I915_WRITE(reg, temp);
3456
3457         reg = FDI_RX_CTL(pipe);
3458         temp = I915_READ(reg);
3459         temp &= ~FDI_LINK_TRAIN_NONE;
3460         temp |= FDI_LINK_TRAIN_PATTERN_2;
3461         I915_WRITE(reg, temp);
3462
3463         POSTING_READ(reg);
3464         udelay(150);
3465
3466         reg = FDI_RX_IIR(pipe);
3467         for (tries = 0; tries < 5; tries++) {
3468                 temp = I915_READ(reg);
3469                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471                 if (temp & FDI_RX_SYMBOL_LOCK) {
3472                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3473                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3474                         break;
3475                 }
3476         }
3477         if (tries == 5)
3478                 DRM_ERROR("FDI train 2 fail!\n");
3479
3480         DRM_DEBUG_KMS("FDI train done\n");
3481
3482 }
3483
3484 static const int snb_b_fdi_train_param[] = {
3485         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489 };
3490
3491 /* The FDI link training functions for SNB/Cougarpoint. */
3492 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493 {
3494         struct drm_device *dev = crtc->dev;
3495         struct drm_i915_private *dev_priv = dev->dev_private;
3496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497         int pipe = intel_crtc->pipe;
3498         i915_reg_t reg;
3499         u32 temp, i, retry;
3500
3501         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3502            for train result */
3503         reg = FDI_RX_IMR(pipe);
3504         temp = I915_READ(reg);
3505         temp &= ~FDI_RX_SYMBOL_LOCK;
3506         temp &= ~FDI_RX_BIT_LOCK;
3507         I915_WRITE(reg, temp);
3508
3509         POSTING_READ(reg);
3510         udelay(150);
3511
3512         /* enable CPU FDI TX and PCH FDI RX */
3513         reg = FDI_TX_CTL(pipe);
3514         temp = I915_READ(reg);
3515         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3516         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3517         temp &= ~FDI_LINK_TRAIN_NONE;
3518         temp |= FDI_LINK_TRAIN_PATTERN_1;
3519         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3520         /* SNB-B */
3521         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3522         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3523
3524         I915_WRITE(FDI_RX_MISC(pipe),
3525                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3526
3527         reg = FDI_RX_CTL(pipe);
3528         temp = I915_READ(reg);
3529         if (HAS_PCH_CPT(dev)) {
3530                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3531                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3532         } else {
3533                 temp &= ~FDI_LINK_TRAIN_NONE;
3534                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3535         }
3536         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3537
3538         POSTING_READ(reg);
3539         udelay(150);
3540
3541         for (i = 0; i < 4; i++) {
3542                 reg = FDI_TX_CTL(pipe);
3543                 temp = I915_READ(reg);
3544                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3545                 temp |= snb_b_fdi_train_param[i];
3546                 I915_WRITE(reg, temp);
3547
3548                 POSTING_READ(reg);
3549                 udelay(500);
3550
3551                 for (retry = 0; retry < 5; retry++) {
3552                         reg = FDI_RX_IIR(pipe);
3553                         temp = I915_READ(reg);
3554                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3555                         if (temp & FDI_RX_BIT_LOCK) {
3556                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3557                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3558                                 break;
3559                         }
3560                         udelay(50);
3561                 }
3562                 if (retry < 5)
3563                         break;
3564         }
3565         if (i == 4)
3566                 DRM_ERROR("FDI train 1 fail!\n");
3567
3568         /* Train 2 */
3569         reg = FDI_TX_CTL(pipe);
3570         temp = I915_READ(reg);
3571         temp &= ~FDI_LINK_TRAIN_NONE;
3572         temp |= FDI_LINK_TRAIN_PATTERN_2;
3573         if (IS_GEN6(dev)) {
3574                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3575                 /* SNB-B */
3576                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3577         }
3578         I915_WRITE(reg, temp);
3579
3580         reg = FDI_RX_CTL(pipe);
3581         temp = I915_READ(reg);
3582         if (HAS_PCH_CPT(dev)) {
3583                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3584                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3585         } else {
3586                 temp &= ~FDI_LINK_TRAIN_NONE;
3587                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3588         }
3589         I915_WRITE(reg, temp);
3590
3591         POSTING_READ(reg);
3592         udelay(150);
3593
3594         for (i = 0; i < 4; i++) {
3595                 reg = FDI_TX_CTL(pipe);
3596                 temp = I915_READ(reg);
3597                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3598                 temp |= snb_b_fdi_train_param[i];
3599                 I915_WRITE(reg, temp);
3600
3601                 POSTING_READ(reg);
3602                 udelay(500);
3603
3604                 for (retry = 0; retry < 5; retry++) {
3605                         reg = FDI_RX_IIR(pipe);
3606                         temp = I915_READ(reg);
3607                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3608                         if (temp & FDI_RX_SYMBOL_LOCK) {
3609                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3610                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3611                                 break;
3612                         }
3613                         udelay(50);
3614                 }
3615                 if (retry < 5)
3616                         break;
3617         }
3618         if (i == 4)
3619                 DRM_ERROR("FDI train 2 fail!\n");
3620
3621         DRM_DEBUG_KMS("FDI train done.\n");
3622 }
3623
3624 /* Manual link training for Ivy Bridge A0 parts */
3625 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3626 {
3627         struct drm_device *dev = crtc->dev;
3628         struct drm_i915_private *dev_priv = dev->dev_private;
3629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630         int pipe = intel_crtc->pipe;
3631         i915_reg_t reg;
3632         u32 temp, i, j;
3633
3634         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3635            for train result */
3636         reg = FDI_RX_IMR(pipe);
3637         temp = I915_READ(reg);
3638         temp &= ~FDI_RX_SYMBOL_LOCK;
3639         temp &= ~FDI_RX_BIT_LOCK;
3640         I915_WRITE(reg, temp);
3641
3642         POSTING_READ(reg);
3643         udelay(150);
3644
3645         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646                       I915_READ(FDI_RX_IIR(pipe)));
3647
3648         /* Try each vswing and preemphasis setting twice before moving on */
3649         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650                 /* disable first in case we need to retry */
3651                 reg = FDI_TX_CTL(pipe);
3652                 temp = I915_READ(reg);
3653                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654                 temp &= ~FDI_TX_ENABLE;
3655                 I915_WRITE(reg, temp);
3656
3657                 reg = FDI_RX_CTL(pipe);
3658                 temp = I915_READ(reg);
3659                 temp &= ~FDI_LINK_TRAIN_AUTO;
3660                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661                 temp &= ~FDI_RX_ENABLE;
3662                 I915_WRITE(reg, temp);
3663
3664                 /* enable CPU FDI TX and PCH FDI RX */
3665                 reg = FDI_TX_CTL(pipe);
3666                 temp = I915_READ(reg);
3667                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3668                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3669                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3670                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3671                 temp |= snb_b_fdi_train_param[j/2];
3672                 temp |= FDI_COMPOSITE_SYNC;
3673                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3674
3675                 I915_WRITE(FDI_RX_MISC(pipe),
3676                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3677
3678                 reg = FDI_RX_CTL(pipe);
3679                 temp = I915_READ(reg);
3680                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681                 temp |= FDI_COMPOSITE_SYNC;
3682                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3683
3684                 POSTING_READ(reg);
3685                 udelay(1); /* should be 0.5us */
3686
3687                 for (i = 0; i < 4; i++) {
3688                         reg = FDI_RX_IIR(pipe);
3689                         temp = I915_READ(reg);
3690                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3691
3692                         if (temp & FDI_RX_BIT_LOCK ||
3693                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3696                                               i);
3697                                 break;
3698                         }
3699                         udelay(1); /* should be 0.5us */
3700                 }
3701                 if (i == 4) {
3702                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3703                         continue;
3704                 }
3705
3706                 /* Train 2 */
3707                 reg = FDI_TX_CTL(pipe);
3708                 temp = I915_READ(reg);
3709                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711                 I915_WRITE(reg, temp);
3712
3713                 reg = FDI_RX_CTL(pipe);
3714                 temp = I915_READ(reg);
3715                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3717                 I915_WRITE(reg, temp);
3718
3719                 POSTING_READ(reg);
3720                 udelay(2); /* should be 1.5us */
3721
3722                 for (i = 0; i < 4; i++) {
3723                         reg = FDI_RX_IIR(pipe);
3724                         temp = I915_READ(reg);
3725                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3726
3727                         if (temp & FDI_RX_SYMBOL_LOCK ||
3728                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3731                                               i);
3732                                 goto train_done;
3733                         }
3734                         udelay(2); /* should be 1.5us */
3735                 }
3736                 if (i == 4)
3737                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3738         }
3739
3740 train_done:
3741         DRM_DEBUG_KMS("FDI train done.\n");
3742 }
3743
3744 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3745 {
3746         struct drm_device *dev = intel_crtc->base.dev;
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         int pipe = intel_crtc->pipe;
3749         i915_reg_t reg;
3750         u32 temp;
3751
3752         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3756         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3757         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3759
3760         POSTING_READ(reg);
3761         udelay(200);
3762
3763         /* Switch from Rawclk to PCDclk */
3764         temp = I915_READ(reg);
3765         I915_WRITE(reg, temp | FDI_PCDCLK);
3766
3767         POSTING_READ(reg);
3768         udelay(200);
3769
3770         /* Enable CPU FDI TX PLL, always on for Ironlake */
3771         reg = FDI_TX_CTL(pipe);
3772         temp = I915_READ(reg);
3773         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3775
3776                 POSTING_READ(reg);
3777                 udelay(100);
3778         }
3779 }
3780
3781 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3782 {
3783         struct drm_device *dev = intel_crtc->base.dev;
3784         struct drm_i915_private *dev_priv = dev->dev_private;
3785         int pipe = intel_crtc->pipe;
3786         i915_reg_t reg;
3787         u32 temp;
3788
3789         /* Switch from PCDclk to Rawclk */
3790         reg = FDI_RX_CTL(pipe);
3791         temp = I915_READ(reg);
3792         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3793
3794         /* Disable CPU FDI TX PLL */
3795         reg = FDI_TX_CTL(pipe);
3796         temp = I915_READ(reg);
3797         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3798
3799         POSTING_READ(reg);
3800         udelay(100);
3801
3802         reg = FDI_RX_CTL(pipe);
3803         temp = I915_READ(reg);
3804         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3805
3806         /* Wait for the clocks to turn off. */
3807         POSTING_READ(reg);
3808         udelay(100);
3809 }
3810
3811 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3812 {
3813         struct drm_device *dev = crtc->dev;
3814         struct drm_i915_private *dev_priv = dev->dev_private;
3815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3816         int pipe = intel_crtc->pipe;
3817         i915_reg_t reg;
3818         u32 temp;
3819
3820         /* disable CPU FDI tx and PCH FDI rx */
3821         reg = FDI_TX_CTL(pipe);
3822         temp = I915_READ(reg);
3823         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3824         POSTING_READ(reg);
3825
3826         reg = FDI_RX_CTL(pipe);
3827         temp = I915_READ(reg);
3828         temp &= ~(0x7 << 16);
3829         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3830         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3831
3832         POSTING_READ(reg);
3833         udelay(100);
3834
3835         /* Ironlake workaround, disable clock pointer after downing FDI */
3836         if (HAS_PCH_IBX(dev))
3837                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3838
3839         /* still set train pattern 1 */
3840         reg = FDI_TX_CTL(pipe);
3841         temp = I915_READ(reg);
3842         temp &= ~FDI_LINK_TRAIN_NONE;
3843         temp |= FDI_LINK_TRAIN_PATTERN_1;
3844         I915_WRITE(reg, temp);
3845
3846         reg = FDI_RX_CTL(pipe);
3847         temp = I915_READ(reg);
3848         if (HAS_PCH_CPT(dev)) {
3849                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3850                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3851         } else {
3852                 temp &= ~FDI_LINK_TRAIN_NONE;
3853                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854         }
3855         /* BPC in FDI rx is consistent with that in PIPECONF */
3856         temp &= ~(0x07 << 16);
3857         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3858         I915_WRITE(reg, temp);
3859
3860         POSTING_READ(reg);
3861         udelay(100);
3862 }
3863
3864 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3865 {
3866         struct intel_crtc *crtc;
3867
3868         /* Note that we don't need to be called with mode_config.lock here
3869          * as our list of CRTC objects is static for the lifetime of the
3870          * device and so cannot disappear as we iterate. Similarly, we can
3871          * happily treat the predicates as racy, atomic checks as userspace
3872          * cannot claim and pin a new fb without at least acquring the
3873          * struct_mutex and so serialising with us.
3874          */
3875         for_each_intel_crtc(dev, crtc) {
3876                 if (atomic_read(&crtc->unpin_work_count) == 0)
3877                         continue;
3878
3879                 if (crtc->unpin_work)
3880                         intel_wait_for_vblank(dev, crtc->pipe);
3881
3882                 return true;
3883         }
3884
3885         return false;
3886 }
3887
3888 static void page_flip_completed(struct intel_crtc *intel_crtc)
3889 {
3890         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3891         struct intel_unpin_work *work = intel_crtc->unpin_work;
3892
3893         /* ensure that the unpin work is consistent wrt ->pending. */
3894         smp_rmb();
3895         intel_crtc->unpin_work = NULL;
3896
3897         if (work->event)
3898                 drm_send_vblank_event(intel_crtc->base.dev,
3899                                       intel_crtc->pipe,
3900                                       work->event);
3901
3902         drm_crtc_vblank_put(&intel_crtc->base);
3903
3904         wake_up_all(&dev_priv->pending_flip_queue);
3905         queue_work(dev_priv->wq, &work->work);
3906
3907         trace_i915_flip_complete(intel_crtc->plane,
3908                                  work->pending_flip_obj);
3909 }
3910
3911 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3912 {
3913         struct drm_device *dev = crtc->dev;
3914         struct drm_i915_private *dev_priv = dev->dev_private;
3915         long ret;
3916
3917         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3918
3919         ret = wait_event_interruptible_timeout(
3920                                         dev_priv->pending_flip_queue,
3921                                         !intel_crtc_has_pending_flip(crtc),
3922                                         60*HZ);
3923
3924         if (ret < 0)
3925                 return ret;
3926
3927         if (ret == 0) {
3928                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3929
3930                 spin_lock_irq(&dev->event_lock);
3931                 if (intel_crtc->unpin_work) {
3932                         WARN_ONCE(1, "Removing stuck page flip\n");
3933                         page_flip_completed(intel_crtc);
3934                 }
3935                 spin_unlock_irq(&dev->event_lock);
3936         }
3937
3938         return 0;
3939 }
3940
3941 /* Program iCLKIP clock to the desired frequency */
3942 static void lpt_program_iclkip(struct drm_crtc *crtc)
3943 {
3944         struct drm_device *dev = crtc->dev;
3945         struct drm_i915_private *dev_priv = dev->dev_private;
3946         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3947         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3948         u32 temp;
3949
3950         mutex_lock(&dev_priv->sb_lock);
3951
3952         /* It is necessary to ungate the pixclk gate prior to programming
3953          * the divisors, and gate it back when it is done.
3954          */
3955         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3956
3957         /* Disable SSCCTL */
3958         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3959                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3960                                 SBI_SSCCTL_DISABLE,
3961                         SBI_ICLK);
3962
3963         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3964         if (clock == 20000) {
3965                 auxdiv = 1;
3966                 divsel = 0x41;
3967                 phaseinc = 0x20;
3968         } else {
3969                 /* The iCLK virtual clock root frequency is in MHz,
3970                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3971                  * divisors, it is necessary to divide one by another, so we
3972                  * convert the virtual clock precision to KHz here for higher
3973                  * precision.
3974                  */
3975                 u32 iclk_virtual_root_freq = 172800 * 1000;
3976                 u32 iclk_pi_range = 64;
3977                 u32 desired_divisor, msb_divisor_value, pi_value;
3978
3979                 desired_divisor = (iclk_virtual_root_freq / clock);
3980                 msb_divisor_value = desired_divisor / iclk_pi_range;
3981                 pi_value = desired_divisor % iclk_pi_range;
3982
3983                 auxdiv = 0;
3984                 divsel = msb_divisor_value - 2;
3985                 phaseinc = pi_value;
3986         }
3987
3988         /* This should not happen with any sane values */
3989         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3990                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3991         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3992                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3993
3994         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3995                         clock,
3996                         auxdiv,
3997                         divsel,
3998                         phasedir,
3999                         phaseinc);
4000
4001         /* Program SSCDIVINTPHASE6 */
4002         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4003         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4004         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4005         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4006         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4007         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4008         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4009         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4010
4011         /* Program SSCAUXDIV */
4012         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4013         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4014         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4015         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4016
4017         /* Enable modulator and associated divider */
4018         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4019         temp &= ~SBI_SSCCTL_DISABLE;
4020         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4021
4022         /* Wait for initialization time */
4023         udelay(24);
4024
4025         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4026
4027         mutex_unlock(&dev_priv->sb_lock);
4028 }
4029
4030 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4031                                                 enum pipe pch_transcoder)
4032 {
4033         struct drm_device *dev = crtc->base.dev;
4034         struct drm_i915_private *dev_priv = dev->dev_private;
4035         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4036
4037         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4038                    I915_READ(HTOTAL(cpu_transcoder)));
4039         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4040                    I915_READ(HBLANK(cpu_transcoder)));
4041         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4042                    I915_READ(HSYNC(cpu_transcoder)));
4043
4044         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4045                    I915_READ(VTOTAL(cpu_transcoder)));
4046         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4047                    I915_READ(VBLANK(cpu_transcoder)));
4048         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4049                    I915_READ(VSYNC(cpu_transcoder)));
4050         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4051                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4052 }
4053
4054 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4055 {
4056         struct drm_i915_private *dev_priv = dev->dev_private;
4057         uint32_t temp;
4058
4059         temp = I915_READ(SOUTH_CHICKEN1);
4060         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4061                 return;
4062
4063         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4064         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4065
4066         temp &= ~FDI_BC_BIFURCATION_SELECT;
4067         if (enable)
4068                 temp |= FDI_BC_BIFURCATION_SELECT;
4069
4070         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4071         I915_WRITE(SOUTH_CHICKEN1, temp);
4072         POSTING_READ(SOUTH_CHICKEN1);
4073 }
4074
4075 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4076 {
4077         struct drm_device *dev = intel_crtc->base.dev;
4078
4079         switch (intel_crtc->pipe) {
4080         case PIPE_A:
4081                 break;
4082         case PIPE_B:
4083                 if (intel_crtc->config->fdi_lanes > 2)
4084                         cpt_set_fdi_bc_bifurcation(dev, false);
4085                 else
4086                         cpt_set_fdi_bc_bifurcation(dev, true);
4087
4088                 break;
4089         case PIPE_C:
4090                 cpt_set_fdi_bc_bifurcation(dev, true);
4091
4092                 break;
4093         default:
4094                 BUG();
4095         }
4096 }
4097
4098 /* Return which DP Port should be selected for Transcoder DP control */
4099 static enum port
4100 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4101 {
4102         struct drm_device *dev = crtc->dev;
4103         struct intel_encoder *encoder;
4104
4105         for_each_encoder_on_crtc(dev, crtc, encoder) {
4106                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4107                     encoder->type == INTEL_OUTPUT_EDP)
4108                         return enc_to_dig_port(&encoder->base)->port;
4109         }
4110
4111         return -1;
4112 }
4113
4114 /*
4115  * Enable PCH resources required for PCH ports:
4116  *   - PCH PLLs
4117  *   - FDI training & RX/TX
4118  *   - update transcoder timings
4119  *   - DP transcoding bits
4120  *   - transcoder
4121  */
4122 static void ironlake_pch_enable(struct drm_crtc *crtc)
4123 {
4124         struct drm_device *dev = crtc->dev;
4125         struct drm_i915_private *dev_priv = dev->dev_private;
4126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4127         int pipe = intel_crtc->pipe;
4128         u32 temp;
4129
4130         assert_pch_transcoder_disabled(dev_priv, pipe);
4131
4132         if (IS_IVYBRIDGE(dev))
4133                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4134
4135         /* Write the TU size bits before fdi link training, so that error
4136          * detection works. */
4137         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4138                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4139
4140         /*
4141          * Sometimes spurious CPU pipe underruns happen during FDI
4142          * training, at least with VGA+HDMI cloning. Suppress them.
4143          */
4144         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4145
4146         /* For PCH output, training FDI link */
4147         dev_priv->display.fdi_link_train(crtc);
4148
4149         /* We need to program the right clock selection before writing the pixel
4150          * mutliplier into the DPLL. */
4151         if (HAS_PCH_CPT(dev)) {
4152                 u32 sel;
4153
4154                 temp = I915_READ(PCH_DPLL_SEL);
4155                 temp |= TRANS_DPLL_ENABLE(pipe);
4156                 sel = TRANS_DPLLB_SEL(pipe);
4157                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4158                         temp |= sel;
4159                 else
4160                         temp &= ~sel;
4161                 I915_WRITE(PCH_DPLL_SEL, temp);
4162         }
4163
4164         /* XXX: pch pll's can be enabled any time before we enable the PCH
4165          * transcoder, and we actually should do this to not upset any PCH
4166          * transcoder that already use the clock when we share it.
4167          *
4168          * Note that enable_shared_dpll tries to do the right thing, but
4169          * get_shared_dpll unconditionally resets the pll - we need that to have
4170          * the right LVDS enable sequence. */
4171         intel_enable_shared_dpll(intel_crtc);
4172
4173         /* set transcoder timing, panel must allow it */
4174         assert_panel_unlocked(dev_priv, pipe);
4175         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4176
4177         intel_fdi_normal_train(crtc);
4178
4179         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4180
4181         /* For PCH DP, enable TRANS_DP_CTL */
4182         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4183                 const struct drm_display_mode *adjusted_mode =
4184                         &intel_crtc->config->base.adjusted_mode;
4185                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4186                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4187                 temp = I915_READ(reg);
4188                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4189                           TRANS_DP_SYNC_MASK |
4190                           TRANS_DP_BPC_MASK);
4191                 temp |= TRANS_DP_OUTPUT_ENABLE;
4192                 temp |= bpc << 9; /* same format but at 11:9 */
4193
4194                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4195                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4196                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4197                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4198
4199                 switch (intel_trans_dp_port_sel(crtc)) {
4200                 case PORT_B:
4201                         temp |= TRANS_DP_PORT_SEL_B;
4202                         break;
4203                 case PORT_C:
4204                         temp |= TRANS_DP_PORT_SEL_C;
4205                         break;
4206                 case PORT_D:
4207                         temp |= TRANS_DP_PORT_SEL_D;
4208                         break;
4209                 default:
4210                         BUG();
4211                 }
4212
4213                 I915_WRITE(reg, temp);
4214         }
4215
4216         ironlake_enable_pch_transcoder(dev_priv, pipe);
4217 }
4218
4219 static void lpt_pch_enable(struct drm_crtc *crtc)
4220 {
4221         struct drm_device *dev = crtc->dev;
4222         struct drm_i915_private *dev_priv = dev->dev_private;
4223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4224         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4225
4226         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4227
4228         lpt_program_iclkip(crtc);
4229
4230         /* Set transcoder timing. */
4231         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4232
4233         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4234 }
4235
4236 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4237                                                 struct intel_crtc_state *crtc_state)
4238 {
4239         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4240         struct intel_shared_dpll *pll;
4241         struct intel_shared_dpll_config *shared_dpll;
4242         enum intel_dpll_id i;
4243         int max = dev_priv->num_shared_dpll;
4244
4245         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4246
4247         if (HAS_PCH_IBX(dev_priv->dev)) {
4248                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4249                 i = (enum intel_dpll_id) crtc->pipe;
4250                 pll = &dev_priv->shared_dplls[i];
4251
4252                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4253                               crtc->base.base.id, pll->name);
4254
4255                 WARN_ON(shared_dpll[i].crtc_mask);
4256
4257                 goto found;
4258         }
4259
4260         if (IS_BROXTON(dev_priv->dev)) {
4261                 /* PLL is attached to port in bxt */
4262                 struct intel_encoder *encoder;
4263                 struct intel_digital_port *intel_dig_port;
4264
4265                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4266                 if (WARN_ON(!encoder))
4267                         return NULL;
4268
4269                 intel_dig_port = enc_to_dig_port(&encoder->base);
4270                 /* 1:1 mapping between ports and PLLs */
4271                 i = (enum intel_dpll_id)intel_dig_port->port;
4272                 pll = &dev_priv->shared_dplls[i];
4273                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4274                         crtc->base.base.id, pll->name);
4275                 WARN_ON(shared_dpll[i].crtc_mask);
4276
4277                 goto found;
4278         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4279                 /* Do not consider SPLL */
4280                 max = 2;
4281
4282         for (i = 0; i < max; i++) {
4283                 pll = &dev_priv->shared_dplls[i];
4284
4285                 /* Only want to check enabled timings first */
4286                 if (shared_dpll[i].crtc_mask == 0)
4287                         continue;
4288
4289                 if (memcmp(&crtc_state->dpll_hw_state,
4290                            &shared_dpll[i].hw_state,
4291                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4292                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4293                                       crtc->base.base.id, pll->name,
4294                                       shared_dpll[i].crtc_mask,
4295                                       pll->active);
4296                         goto found;
4297                 }
4298         }
4299
4300         /* Ok no matching timings, maybe there's a free one? */
4301         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4302                 pll = &dev_priv->shared_dplls[i];
4303                 if (shared_dpll[i].crtc_mask == 0) {
4304                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4305                                       crtc->base.base.id, pll->name);
4306                         goto found;
4307                 }
4308         }
4309
4310         return NULL;
4311
4312 found:
4313         if (shared_dpll[i].crtc_mask == 0)
4314                 shared_dpll[i].hw_state =
4315                         crtc_state->dpll_hw_state;
4316
4317         crtc_state->shared_dpll = i;
4318         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4319                          pipe_name(crtc->pipe));
4320
4321         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4322
4323         return pll;
4324 }
4325
4326 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4327 {
4328         struct drm_i915_private *dev_priv = to_i915(state->dev);
4329         struct intel_shared_dpll_config *shared_dpll;
4330         struct intel_shared_dpll *pll;
4331         enum intel_dpll_id i;
4332
4333         if (!to_intel_atomic_state(state)->dpll_set)
4334                 return;
4335
4336         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4337         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4338                 pll = &dev_priv->shared_dplls[i];
4339                 pll->config = shared_dpll[i];
4340         }
4341 }
4342
4343 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4344 {
4345         struct drm_i915_private *dev_priv = dev->dev_private;
4346         i915_reg_t dslreg = PIPEDSL(pipe);
4347         u32 temp;
4348
4349         temp = I915_READ(dslreg);
4350         udelay(500);
4351         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4352                 if (wait_for(I915_READ(dslreg) != temp, 5))
4353                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4354         }
4355 }
4356
4357 static int
4358 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4359                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4360                   int src_w, int src_h, int dst_w, int dst_h)
4361 {
4362         struct intel_crtc_scaler_state *scaler_state =
4363                 &crtc_state->scaler_state;
4364         struct intel_crtc *intel_crtc =
4365                 to_intel_crtc(crtc_state->base.crtc);
4366         int need_scaling;
4367
4368         need_scaling = intel_rotation_90_or_270(rotation) ?
4369                 (src_h != dst_w || src_w != dst_h):
4370                 (src_w != dst_w || src_h != dst_h);
4371
4372         /*
4373          * if plane is being disabled or scaler is no more required or force detach
4374          *  - free scaler binded to this plane/crtc
4375          *  - in order to do this, update crtc->scaler_usage
4376          *
4377          * Here scaler state in crtc_state is set free so that
4378          * scaler can be assigned to other user. Actual register
4379          * update to free the scaler is done in plane/panel-fit programming.
4380          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4381          */
4382         if (force_detach || !need_scaling) {
4383                 if (*scaler_id >= 0) {
4384                         scaler_state->scaler_users &= ~(1 << scaler_user);
4385                         scaler_state->scalers[*scaler_id].in_use = 0;
4386
4387                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4388                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4389                                 intel_crtc->pipe, scaler_user, *scaler_id,
4390                                 scaler_state->scaler_users);
4391                         *scaler_id = -1;
4392                 }
4393                 return 0;
4394         }
4395
4396         /* range checks */
4397         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4398                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4399
4400                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4401                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4402                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4403                         "size is out of scaler range\n",
4404                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4405                 return -EINVAL;
4406         }
4407
4408         /* mark this plane as a scaler user in crtc_state */
4409         scaler_state->scaler_users |= (1 << scaler_user);
4410         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4411                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4412                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4413                 scaler_state->scaler_users);
4414
4415         return 0;
4416 }
4417
4418 /**
4419  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4420  *
4421  * @state: crtc's scaler state
4422  *
4423  * Return
4424  *     0 - scaler_usage updated successfully
4425  *    error - requested scaling cannot be supported or other error condition
4426  */
4427 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4428 {
4429         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4430         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4431
4432         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4433                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4434
4435         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4436                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4437                 state->pipe_src_w, state->pipe_src_h,
4438                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4439 }
4440
4441 /**
4442  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4443  *
4444  * @state: crtc's scaler state
4445  * @plane_state: atomic plane state to update
4446  *
4447  * Return
4448  *     0 - scaler_usage updated successfully
4449  *    error - requested scaling cannot be supported or other error condition
4450  */
4451 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4452                                    struct intel_plane_state *plane_state)
4453 {
4454
4455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4456         struct intel_plane *intel_plane =
4457                 to_intel_plane(plane_state->base.plane);
4458         struct drm_framebuffer *fb = plane_state->base.fb;
4459         int ret;
4460
4461         bool force_detach = !fb || !plane_state->visible;
4462
4463         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4464                       intel_plane->base.base.id, intel_crtc->pipe,
4465                       drm_plane_index(&intel_plane->base));
4466
4467         ret = skl_update_scaler(crtc_state, force_detach,
4468                                 drm_plane_index(&intel_plane->base),
4469                                 &plane_state->scaler_id,
4470                                 plane_state->base.rotation,
4471                                 drm_rect_width(&plane_state->src) >> 16,
4472                                 drm_rect_height(&plane_state->src) >> 16,
4473                                 drm_rect_width(&plane_state->dst),
4474                                 drm_rect_height(&plane_state->dst));
4475
4476         if (ret || plane_state->scaler_id < 0)
4477                 return ret;
4478
4479         /* check colorkey */
4480         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4481                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4482                               intel_plane->base.base.id);
4483                 return -EINVAL;
4484         }
4485
4486         /* Check src format */
4487         switch (fb->pixel_format) {
4488         case DRM_FORMAT_RGB565:
4489         case DRM_FORMAT_XBGR8888:
4490         case DRM_FORMAT_XRGB8888:
4491         case DRM_FORMAT_ABGR8888:
4492         case DRM_FORMAT_ARGB8888:
4493         case DRM_FORMAT_XRGB2101010:
4494         case DRM_FORMAT_XBGR2101010:
4495         case DRM_FORMAT_YUYV:
4496         case DRM_FORMAT_YVYU:
4497         case DRM_FORMAT_UYVY:
4498         case DRM_FORMAT_VYUY:
4499                 break;
4500         default:
4501                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4502                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4503                 return -EINVAL;
4504         }
4505
4506         return 0;
4507 }
4508
4509 static void skylake_scaler_disable(struct intel_crtc *crtc)
4510 {
4511         int i;
4512
4513         for (i = 0; i < crtc->num_scalers; i++)
4514                 skl_detach_scaler(crtc, i);
4515 }
4516
4517 static void skylake_pfit_enable(struct intel_crtc *crtc)
4518 {
4519         struct drm_device *dev = crtc->base.dev;
4520         struct drm_i915_private *dev_priv = dev->dev_private;
4521         int pipe = crtc->pipe;
4522         struct intel_crtc_scaler_state *scaler_state =
4523                 &crtc->config->scaler_state;
4524
4525         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4526
4527         if (crtc->config->pch_pfit.enabled) {
4528                 int id;
4529
4530                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4531                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4532                         return;
4533                 }
4534
4535                 id = scaler_state->scaler_id;
4536                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4537                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4538                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4539                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4540
4541                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4542         }
4543 }
4544
4545 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4546 {
4547         struct drm_device *dev = crtc->base.dev;
4548         struct drm_i915_private *dev_priv = dev->dev_private;
4549         int pipe = crtc->pipe;
4550
4551         if (crtc->config->pch_pfit.enabled) {
4552                 /* Force use of hard-coded filter coefficients
4553                  * as some pre-programmed values are broken,
4554                  * e.g. x201.
4555                  */
4556                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4557                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4558                                                  PF_PIPE_SEL_IVB(pipe));
4559                 else
4560                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4561                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4562                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4563         }
4564 }
4565
4566 void hsw_enable_ips(struct intel_crtc *crtc)
4567 {
4568         struct drm_device *dev = crtc->base.dev;
4569         struct drm_i915_private *dev_priv = dev->dev_private;
4570
4571         if (!crtc->config->ips_enabled)
4572                 return;
4573
4574         /* We can only enable IPS after we enable a plane and wait for a vblank */
4575         intel_wait_for_vblank(dev, crtc->pipe);
4576
4577         assert_plane_enabled(dev_priv, crtc->plane);
4578         if (IS_BROADWELL(dev)) {
4579                 mutex_lock(&dev_priv->rps.hw_lock);
4580                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4581                 mutex_unlock(&dev_priv->rps.hw_lock);
4582                 /* Quoting Art Runyan: "its not safe to expect any particular
4583                  * value in IPS_CTL bit 31 after enabling IPS through the
4584                  * mailbox." Moreover, the mailbox may return a bogus state,
4585                  * so we need to just enable it and continue on.
4586                  */
4587         } else {
4588                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4589                 /* The bit only becomes 1 in the next vblank, so this wait here
4590                  * is essentially intel_wait_for_vblank. If we don't have this
4591                  * and don't wait for vblanks until the end of crtc_enable, then
4592                  * the HW state readout code will complain that the expected
4593                  * IPS_CTL value is not the one we read. */
4594                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4595                         DRM_ERROR("Timed out waiting for IPS enable\n");
4596         }
4597 }
4598
4599 void hsw_disable_ips(struct intel_crtc *crtc)
4600 {
4601         struct drm_device *dev = crtc->base.dev;
4602         struct drm_i915_private *dev_priv = dev->dev_private;
4603
4604         if (!crtc->config->ips_enabled)
4605                 return;
4606
4607         assert_plane_enabled(dev_priv, crtc->plane);
4608         if (IS_BROADWELL(dev)) {
4609                 mutex_lock(&dev_priv->rps.hw_lock);
4610                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4611                 mutex_unlock(&dev_priv->rps.hw_lock);
4612                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4613                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4614                         DRM_ERROR("Timed out waiting for IPS disable\n");
4615         } else {
4616                 I915_WRITE(IPS_CTL, 0);
4617                 POSTING_READ(IPS_CTL);
4618         }
4619
4620         /* We need to wait for a vblank before we can disable the plane. */
4621         intel_wait_for_vblank(dev, crtc->pipe);
4622 }
4623
4624 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4625 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4626 {
4627         struct drm_device *dev = crtc->dev;
4628         struct drm_i915_private *dev_priv = dev->dev_private;
4629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4630         enum pipe pipe = intel_crtc->pipe;
4631         int i;
4632         bool reenable_ips = false;
4633
4634         /* The clocks have to be on to load the palette. */
4635         if (!crtc->state->active)
4636                 return;
4637
4638         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4639                 if (intel_crtc->config->has_dsi_encoder)
4640                         assert_dsi_pll_enabled(dev_priv);
4641                 else
4642                         assert_pll_enabled(dev_priv, pipe);
4643         }
4644
4645         /* Workaround : Do not read or write the pipe palette/gamma data while
4646          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4647          */
4648         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4649             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4650              GAMMA_MODE_MODE_SPLIT)) {
4651                 hsw_disable_ips(intel_crtc);
4652                 reenable_ips = true;
4653         }
4654
4655         for (i = 0; i < 256; i++) {
4656                 i915_reg_t palreg;
4657
4658                 if (HAS_GMCH_DISPLAY(dev))
4659                         palreg = PALETTE(pipe, i);
4660                 else
4661                         palreg = LGC_PALETTE(pipe, i);
4662
4663                 I915_WRITE(palreg,
4664                            (intel_crtc->lut_r[i] << 16) |
4665                            (intel_crtc->lut_g[i] << 8) |
4666                            intel_crtc->lut_b[i]);
4667         }
4668
4669         if (reenable_ips)
4670                 hsw_enable_ips(intel_crtc);
4671 }
4672
4673 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4674 {
4675         if (intel_crtc->overlay) {
4676                 struct drm_device *dev = intel_crtc->base.dev;
4677                 struct drm_i915_private *dev_priv = dev->dev_private;
4678
4679                 mutex_lock(&dev->struct_mutex);
4680                 dev_priv->mm.interruptible = false;
4681                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4682                 dev_priv->mm.interruptible = true;
4683                 mutex_unlock(&dev->struct_mutex);
4684         }
4685
4686         /* Let userspace switch the overlay on again. In most cases userspace
4687          * has to recompute where to put it anyway.
4688          */
4689 }
4690
4691 /**
4692  * intel_post_enable_primary - Perform operations after enabling primary plane
4693  * @crtc: the CRTC whose primary plane was just enabled
4694  *
4695  * Performs potentially sleeping operations that must be done after the primary
4696  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4697  * called due to an explicit primary plane update, or due to an implicit
4698  * re-enable that is caused when a sprite plane is updated to no longer
4699  * completely hide the primary plane.
4700  */
4701 static void
4702 intel_post_enable_primary(struct drm_crtc *crtc)
4703 {
4704         struct drm_device *dev = crtc->dev;
4705         struct drm_i915_private *dev_priv = dev->dev_private;
4706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4707         int pipe = intel_crtc->pipe;
4708
4709         /*
4710          * BDW signals flip done immediately if the plane
4711          * is disabled, even if the plane enable is already
4712          * armed to occur at the next vblank :(
4713          */
4714         if (IS_BROADWELL(dev))
4715                 intel_wait_for_vblank(dev, pipe);
4716
4717         /*
4718          * FIXME IPS should be fine as long as one plane is
4719          * enabled, but in practice it seems to have problems
4720          * when going from primary only to sprite only and vice
4721          * versa.
4722          */
4723         hsw_enable_ips(intel_crtc);
4724
4725         /*
4726          * Gen2 reports pipe underruns whenever all planes are disabled.
4727          * So don't enable underrun reporting before at least some planes
4728          * are enabled.
4729          * FIXME: Need to fix the logic to work when we turn off all planes
4730          * but leave the pipe running.
4731          */
4732         if (IS_GEN2(dev))
4733                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4734
4735         /* Underruns don't always raise interrupts, so check manually. */
4736         intel_check_cpu_fifo_underruns(dev_priv);
4737         intel_check_pch_fifo_underruns(dev_priv);
4738 }
4739
4740 /**
4741  * intel_pre_disable_primary - Perform operations before disabling primary plane
4742  * @crtc: the CRTC whose primary plane is to be disabled
4743  *
4744  * Performs potentially sleeping operations that must be done before the
4745  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4746  * be called due to an explicit primary plane update, or due to an implicit
4747  * disable that is caused when a sprite plane completely hides the primary
4748  * plane.
4749  */
4750 static void
4751 intel_pre_disable_primary(struct drm_crtc *crtc)
4752 {
4753         struct drm_device *dev = crtc->dev;
4754         struct drm_i915_private *dev_priv = dev->dev_private;
4755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4756         int pipe = intel_crtc->pipe;
4757
4758         /*
4759          * Gen2 reports pipe underruns whenever all planes are disabled.
4760          * So diasble underrun reporting before all the planes get disabled.
4761          * FIXME: Need to fix the logic to work when we turn off all planes
4762          * but leave the pipe running.
4763          */
4764         if (IS_GEN2(dev))
4765                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4766
4767         /*
4768          * Vblank time updates from the shadow to live plane control register
4769          * are blocked if the memory self-refresh mode is active at that
4770          * moment. So to make sure the plane gets truly disabled, disable
4771          * first the self-refresh mode. The self-refresh enable bit in turn
4772          * will be checked/applied by the HW only at the next frame start
4773          * event which is after the vblank start event, so we need to have a
4774          * wait-for-vblank between disabling the plane and the pipe.
4775          */
4776         if (HAS_GMCH_DISPLAY(dev)) {
4777                 intel_set_memory_cxsr(dev_priv, false);
4778                 dev_priv->wm.vlv.cxsr = false;
4779                 intel_wait_for_vblank(dev, pipe);
4780         }
4781
4782         /*
4783          * FIXME IPS should be fine as long as one plane is
4784          * enabled, but in practice it seems to have problems
4785          * when going from primary only to sprite only and vice
4786          * versa.
4787          */
4788         hsw_disable_ips(intel_crtc);
4789 }
4790
4791 static void intel_post_plane_update(struct intel_crtc *crtc)
4792 {
4793         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4794         struct drm_device *dev = crtc->base.dev;
4795         struct drm_i915_private *dev_priv = dev->dev_private;
4796
4797         if (atomic->wait_vblank)
4798                 intel_wait_for_vblank(dev, crtc->pipe);
4799
4800         intel_frontbuffer_flip(dev, atomic->fb_bits);
4801
4802         if (atomic->disable_cxsr)
4803                 crtc->wm.cxsr_allowed = true;
4804
4805         if (crtc->atomic.update_wm_post)
4806                 intel_update_watermarks(&crtc->base);
4807
4808         if (atomic->update_fbc)
4809                 intel_fbc_update(dev_priv);
4810
4811         if (atomic->post_enable_primary)
4812                 intel_post_enable_primary(&crtc->base);
4813
4814         memset(atomic, 0, sizeof(*atomic));
4815 }
4816
4817 static void intel_pre_plane_update(struct intel_crtc *crtc)
4818 {
4819         struct drm_device *dev = crtc->base.dev;
4820         struct drm_i915_private *dev_priv = dev->dev_private;
4821         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4822
4823         if (atomic->disable_fbc)
4824                 intel_fbc_disable_crtc(crtc);
4825
4826         if (crtc->atomic.disable_ips)
4827                 hsw_disable_ips(crtc);
4828
4829         if (atomic->pre_disable_primary)
4830                 intel_pre_disable_primary(&crtc->base);
4831
4832         if (atomic->disable_cxsr) {
4833                 crtc->wm.cxsr_allowed = false;
4834                 intel_set_memory_cxsr(dev_priv, false);
4835         }
4836 }
4837
4838 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4839 {
4840         struct drm_device *dev = crtc->dev;
4841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4842         struct drm_plane *p;
4843         int pipe = intel_crtc->pipe;
4844
4845         intel_crtc_dpms_overlay_disable(intel_crtc);
4846
4847         drm_for_each_plane_mask(p, dev, plane_mask)
4848                 to_intel_plane(p)->disable_plane(p, crtc);
4849
4850         /*
4851          * FIXME: Once we grow proper nuclear flip support out of this we need
4852          * to compute the mask of flip planes precisely. For the time being
4853          * consider this a flip to a NULL plane.
4854          */
4855         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4856 }
4857
4858 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4859 {
4860         struct drm_device *dev = crtc->dev;
4861         struct drm_i915_private *dev_priv = dev->dev_private;
4862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4863         struct intel_encoder *encoder;
4864         int pipe = intel_crtc->pipe;
4865
4866         if (WARN_ON(intel_crtc->active))
4867                 return;
4868
4869         if (intel_crtc->config->has_pch_encoder)
4870                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4871
4872         if (intel_crtc->config->has_pch_encoder)
4873                 intel_prepare_shared_dpll(intel_crtc);
4874
4875         if (intel_crtc->config->has_dp_encoder)
4876                 intel_dp_set_m_n(intel_crtc, M1_N1);
4877
4878         intel_set_pipe_timings(intel_crtc);
4879
4880         if (intel_crtc->config->has_pch_encoder) {
4881                 intel_cpu_transcoder_set_m_n(intel_crtc,
4882                                      &intel_crtc->config->fdi_m_n, NULL);
4883         }
4884
4885         ironlake_set_pipeconf(crtc);
4886
4887         intel_crtc->active = true;
4888
4889         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4890
4891         for_each_encoder_on_crtc(dev, crtc, encoder)
4892                 if (encoder->pre_enable)
4893                         encoder->pre_enable(encoder);
4894
4895         if (intel_crtc->config->has_pch_encoder) {
4896                 /* Note: FDI PLL enabling _must_ be done before we enable the
4897                  * cpu pipes, hence this is separate from all the other fdi/pch
4898                  * enabling. */
4899                 ironlake_fdi_pll_enable(intel_crtc);
4900         } else {
4901                 assert_fdi_tx_disabled(dev_priv, pipe);
4902                 assert_fdi_rx_disabled(dev_priv, pipe);
4903         }
4904
4905         ironlake_pfit_enable(intel_crtc);
4906
4907         /*
4908          * On ILK+ LUT must be loaded before the pipe is running but with
4909          * clocks enabled
4910          */
4911         intel_crtc_load_lut(crtc);
4912
4913         intel_update_watermarks(crtc);
4914         intel_enable_pipe(intel_crtc);
4915
4916         if (intel_crtc->config->has_pch_encoder)
4917                 ironlake_pch_enable(crtc);
4918
4919         assert_vblank_disabled(crtc);
4920         drm_crtc_vblank_on(crtc);
4921
4922         for_each_encoder_on_crtc(dev, crtc, encoder)
4923                 encoder->enable(encoder);
4924
4925         if (HAS_PCH_CPT(dev))
4926                 cpt_verify_modeset(dev, intel_crtc->pipe);
4927
4928         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4929         if (intel_crtc->config->has_pch_encoder)
4930                 intel_wait_for_vblank(dev, pipe);
4931         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4932 }
4933
4934 /* IPS only exists on ULT machines and is tied to pipe A. */
4935 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4936 {
4937         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4938 }
4939
4940 static void haswell_crtc_enable(struct drm_crtc *crtc)
4941 {
4942         struct drm_device *dev = crtc->dev;
4943         struct drm_i915_private *dev_priv = dev->dev_private;
4944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4945         struct intel_encoder *encoder;
4946         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4947         struct intel_crtc_state *pipe_config =
4948                 to_intel_crtc_state(crtc->state);
4949
4950         if (WARN_ON(intel_crtc->active))
4951                 return;
4952
4953         if (intel_crtc->config->has_pch_encoder)
4954                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4955                                                       false);
4956
4957         if (intel_crtc_to_shared_dpll(intel_crtc))
4958                 intel_enable_shared_dpll(intel_crtc);
4959
4960         if (intel_crtc->config->has_dp_encoder)
4961                 intel_dp_set_m_n(intel_crtc, M1_N1);
4962
4963         intel_set_pipe_timings(intel_crtc);
4964
4965         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4966                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4967                            intel_crtc->config->pixel_multiplier - 1);
4968         }
4969
4970         if (intel_crtc->config->has_pch_encoder) {
4971                 intel_cpu_transcoder_set_m_n(intel_crtc,
4972                                      &intel_crtc->config->fdi_m_n, NULL);
4973         }
4974
4975         haswell_set_pipeconf(crtc);
4976
4977         intel_set_pipe_csc(crtc);
4978
4979         intel_crtc->active = true;
4980
4981         if (intel_crtc->config->has_pch_encoder)
4982                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4983         else
4984                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4985
4986         for_each_encoder_on_crtc(dev, crtc, encoder) {
4987                 if (encoder->pre_enable)
4988                         encoder->pre_enable(encoder);
4989         }
4990
4991         if (intel_crtc->config->has_pch_encoder)
4992                 dev_priv->display.fdi_link_train(crtc);
4993
4994         if (!intel_crtc->config->has_dsi_encoder)
4995                 intel_ddi_enable_pipe_clock(intel_crtc);
4996
4997         if (INTEL_INFO(dev)->gen >= 9)
4998                 skylake_pfit_enable(intel_crtc);
4999         else
5000                 ironlake_pfit_enable(intel_crtc);
5001
5002         /*
5003          * On ILK+ LUT must be loaded before the pipe is running but with
5004          * clocks enabled
5005          */
5006         intel_crtc_load_lut(crtc);
5007
5008         intel_ddi_set_pipe_settings(crtc);
5009         if (!intel_crtc->config->has_dsi_encoder)
5010                 intel_ddi_enable_transcoder_func(crtc);
5011
5012         intel_update_watermarks(crtc);
5013         intel_enable_pipe(intel_crtc);
5014
5015         if (intel_crtc->config->has_pch_encoder)
5016                 lpt_pch_enable(crtc);
5017
5018         if (intel_crtc->config->dp_encoder_is_mst)
5019                 intel_ddi_set_vc_payload_alloc(crtc, true);
5020
5021         assert_vblank_disabled(crtc);
5022         drm_crtc_vblank_on(crtc);
5023
5024         for_each_encoder_on_crtc(dev, crtc, encoder) {
5025                 encoder->enable(encoder);
5026                 intel_opregion_notify_encoder(encoder, true);
5027         }
5028
5029         if (intel_crtc->config->has_pch_encoder) {
5030                 intel_wait_for_vblank(dev, pipe);
5031                 intel_wait_for_vblank(dev, pipe);
5032                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5033                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5034                                                       true);
5035         }
5036
5037         /* If we change the relative order between pipe/planes enabling, we need
5038          * to change the workaround. */
5039         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5040         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5041                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5042                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5043         }
5044 }
5045
5046 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5047 {
5048         struct drm_device *dev = crtc->base.dev;
5049         struct drm_i915_private *dev_priv = dev->dev_private;
5050         int pipe = crtc->pipe;
5051
5052         /* To avoid upsetting the power well on haswell only disable the pfit if
5053          * it's in use. The hw state code will make sure we get this right. */
5054         if (force || crtc->config->pch_pfit.enabled) {
5055                 I915_WRITE(PF_CTL(pipe), 0);
5056                 I915_WRITE(PF_WIN_POS(pipe), 0);
5057                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5058         }
5059 }
5060
5061 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5062 {
5063         struct drm_device *dev = crtc->dev;
5064         struct drm_i915_private *dev_priv = dev->dev_private;
5065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066         struct intel_encoder *encoder;
5067         int pipe = intel_crtc->pipe;
5068
5069         if (intel_crtc->config->has_pch_encoder)
5070                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5071
5072         for_each_encoder_on_crtc(dev, crtc, encoder)
5073                 encoder->disable(encoder);
5074
5075         drm_crtc_vblank_off(crtc);
5076         assert_vblank_disabled(crtc);
5077
5078         /*
5079          * Sometimes spurious CPU pipe underruns happen when the
5080          * pipe is already disabled, but FDI RX/TX is still enabled.
5081          * Happens at least with VGA+HDMI cloning. Suppress them.
5082          */
5083         if (intel_crtc->config->has_pch_encoder)
5084                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5085
5086         intel_disable_pipe(intel_crtc);
5087
5088         ironlake_pfit_disable(intel_crtc, false);
5089
5090         if (intel_crtc->config->has_pch_encoder) {
5091                 ironlake_fdi_disable(crtc);
5092                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5093         }
5094
5095         for_each_encoder_on_crtc(dev, crtc, encoder)
5096                 if (encoder->post_disable)
5097                         encoder->post_disable(encoder);
5098
5099         if (intel_crtc->config->has_pch_encoder) {
5100                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5101
5102                 if (HAS_PCH_CPT(dev)) {
5103                         i915_reg_t reg;
5104                         u32 temp;
5105
5106                         /* disable TRANS_DP_CTL */
5107                         reg = TRANS_DP_CTL(pipe);
5108                         temp = I915_READ(reg);
5109                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5110                                   TRANS_DP_PORT_SEL_MASK);
5111                         temp |= TRANS_DP_PORT_SEL_NONE;
5112                         I915_WRITE(reg, temp);
5113
5114                         /* disable DPLL_SEL */
5115                         temp = I915_READ(PCH_DPLL_SEL);
5116                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5117                         I915_WRITE(PCH_DPLL_SEL, temp);
5118                 }
5119
5120                 ironlake_fdi_pll_disable(intel_crtc);
5121         }
5122
5123         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5124 }
5125
5126 static void haswell_crtc_disable(struct drm_crtc *crtc)
5127 {
5128         struct drm_device *dev = crtc->dev;
5129         struct drm_i915_private *dev_priv = dev->dev_private;
5130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5131         struct intel_encoder *encoder;
5132         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5133
5134         if (intel_crtc->config->has_pch_encoder)
5135                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5136                                                       false);
5137
5138         for_each_encoder_on_crtc(dev, crtc, encoder) {
5139                 intel_opregion_notify_encoder(encoder, false);
5140                 encoder->disable(encoder);
5141         }
5142
5143         drm_crtc_vblank_off(crtc);
5144         assert_vblank_disabled(crtc);
5145
5146         intel_disable_pipe(intel_crtc);
5147
5148         if (intel_crtc->config->dp_encoder_is_mst)
5149                 intel_ddi_set_vc_payload_alloc(crtc, false);
5150
5151         if (!intel_crtc->config->has_dsi_encoder)
5152                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5153
5154         if (INTEL_INFO(dev)->gen >= 9)
5155                 skylake_scaler_disable(intel_crtc);
5156         else
5157                 ironlake_pfit_disable(intel_crtc, false);
5158
5159         if (!intel_crtc->config->has_dsi_encoder)
5160                 intel_ddi_disable_pipe_clock(intel_crtc);
5161
5162         if (intel_crtc->config->has_pch_encoder) {
5163                 lpt_disable_pch_transcoder(dev_priv);
5164                 intel_ddi_fdi_disable(crtc);
5165         }
5166
5167         for_each_encoder_on_crtc(dev, crtc, encoder)
5168                 if (encoder->post_disable)
5169                         encoder->post_disable(encoder);
5170
5171         if (intel_crtc->config->has_pch_encoder)
5172                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5173                                                       true);
5174 }
5175
5176 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5177 {
5178         struct drm_device *dev = crtc->base.dev;
5179         struct drm_i915_private *dev_priv = dev->dev_private;
5180         struct intel_crtc_state *pipe_config = crtc->config;
5181
5182         if (!pipe_config->gmch_pfit.control)
5183                 return;
5184
5185         /*
5186          * The panel fitter should only be adjusted whilst the pipe is disabled,
5187          * according to register description and PRM.
5188          */
5189         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5190         assert_pipe_disabled(dev_priv, crtc->pipe);
5191
5192         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5193         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5194
5195         /* Border color in case we don't scale up to the full screen. Black by
5196          * default, change to something else for debugging. */
5197         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5198 }
5199
5200 static enum intel_display_power_domain port_to_power_domain(enum port port)
5201 {
5202         switch (port) {
5203         case PORT_A:
5204                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5205         case PORT_B:
5206                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5207         case PORT_C:
5208                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5209         case PORT_D:
5210                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5211         case PORT_E:
5212                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5213         default:
5214                 MISSING_CASE(port);
5215                 return POWER_DOMAIN_PORT_OTHER;
5216         }
5217 }
5218
5219 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5220 {
5221         switch (port) {
5222         case PORT_A:
5223                 return POWER_DOMAIN_AUX_A;
5224         case PORT_B:
5225                 return POWER_DOMAIN_AUX_B;
5226         case PORT_C:
5227                 return POWER_DOMAIN_AUX_C;
5228         case PORT_D:
5229                 return POWER_DOMAIN_AUX_D;
5230         case PORT_E:
5231                 /* FIXME: Check VBT for actual wiring of PORT E */
5232                 return POWER_DOMAIN_AUX_D;
5233         default:
5234                 MISSING_CASE(port);
5235                 return POWER_DOMAIN_AUX_A;
5236         }
5237 }
5238
5239 enum intel_display_power_domain
5240 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5241 {
5242         struct drm_device *dev = intel_encoder->base.dev;
5243         struct intel_digital_port *intel_dig_port;
5244
5245         switch (intel_encoder->type) {
5246         case INTEL_OUTPUT_UNKNOWN:
5247                 /* Only DDI platforms should ever use this output type */
5248                 WARN_ON_ONCE(!HAS_DDI(dev));
5249         case INTEL_OUTPUT_DISPLAYPORT:
5250         case INTEL_OUTPUT_HDMI:
5251         case INTEL_OUTPUT_EDP:
5252                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5253                 return port_to_power_domain(intel_dig_port->port);
5254         case INTEL_OUTPUT_DP_MST:
5255                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5256                 return port_to_power_domain(intel_dig_port->port);
5257         case INTEL_OUTPUT_ANALOG:
5258                 return POWER_DOMAIN_PORT_CRT;
5259         case INTEL_OUTPUT_DSI:
5260                 return POWER_DOMAIN_PORT_DSI;
5261         default:
5262                 return POWER_DOMAIN_PORT_OTHER;
5263         }
5264 }
5265
5266 enum intel_display_power_domain
5267 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5268 {
5269         struct drm_device *dev = intel_encoder->base.dev;
5270         struct intel_digital_port *intel_dig_port;
5271
5272         switch (intel_encoder->type) {
5273         case INTEL_OUTPUT_UNKNOWN:
5274         case INTEL_OUTPUT_HDMI:
5275                 /*
5276                  * Only DDI platforms should ever use these output types.
5277                  * We can get here after the HDMI detect code has already set
5278                  * the type of the shared encoder. Since we can't be sure
5279                  * what's the status of the given connectors, play safe and
5280                  * run the DP detection too.
5281                  */
5282                 WARN_ON_ONCE(!HAS_DDI(dev));
5283         case INTEL_OUTPUT_DISPLAYPORT:
5284         case INTEL_OUTPUT_EDP:
5285                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5286                 return port_to_aux_power_domain(intel_dig_port->port);
5287         case INTEL_OUTPUT_DP_MST:
5288                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5289                 return port_to_aux_power_domain(intel_dig_port->port);
5290         default:
5291                 MISSING_CASE(intel_encoder->type);
5292                 return POWER_DOMAIN_AUX_A;
5293         }
5294 }
5295
5296 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5297 {
5298         struct drm_device *dev = crtc->dev;
5299         struct intel_encoder *intel_encoder;
5300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5301         enum pipe pipe = intel_crtc->pipe;
5302         unsigned long mask;
5303         enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5304
5305         if (!crtc->state->active)
5306                 return 0;
5307
5308         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5309         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5310         if (intel_crtc->config->pch_pfit.enabled ||
5311             intel_crtc->config->pch_pfit.force_thru)
5312                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5313
5314         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5315                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5316
5317         return mask;
5318 }
5319
5320 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5321 {
5322         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5324         enum intel_display_power_domain domain;
5325         unsigned long domains, new_domains, old_domains;
5326
5327         old_domains = intel_crtc->enabled_power_domains;
5328         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5329
5330         domains = new_domains & ~old_domains;
5331
5332         for_each_power_domain(domain, domains)
5333                 intel_display_power_get(dev_priv, domain);
5334
5335         return old_domains & ~new_domains;
5336 }
5337
5338 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5339                                       unsigned long domains)
5340 {
5341         enum intel_display_power_domain domain;
5342
5343         for_each_power_domain(domain, domains)
5344                 intel_display_power_put(dev_priv, domain);
5345 }
5346
5347 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5348 {
5349         struct drm_device *dev = state->dev;
5350         struct drm_i915_private *dev_priv = dev->dev_private;
5351         unsigned long put_domains[I915_MAX_PIPES] = {};
5352         struct drm_crtc_state *crtc_state;
5353         struct drm_crtc *crtc;
5354         int i;
5355
5356         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5357                 if (needs_modeset(crtc->state))
5358                         put_domains[to_intel_crtc(crtc)->pipe] =
5359                                 modeset_get_crtc_power_domains(crtc);
5360         }
5361
5362         if (dev_priv->display.modeset_commit_cdclk) {
5363                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5364
5365                 if (cdclk != dev_priv->cdclk_freq &&
5366                     !WARN_ON(!state->allow_modeset))
5367                         dev_priv->display.modeset_commit_cdclk(state);
5368         }
5369
5370         for (i = 0; i < I915_MAX_PIPES; i++)
5371                 if (put_domains[i])
5372                         modeset_put_power_domains(dev_priv, put_domains[i]);
5373 }
5374
5375 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5376 {
5377         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5378
5379         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5380             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5381                 return max_cdclk_freq;
5382         else if (IS_CHERRYVIEW(dev_priv))
5383                 return max_cdclk_freq*95/100;
5384         else if (INTEL_INFO(dev_priv)->gen < 4)
5385                 return 2*max_cdclk_freq*90/100;
5386         else
5387                 return max_cdclk_freq*90/100;
5388 }
5389
5390 static void intel_update_max_cdclk(struct drm_device *dev)
5391 {
5392         struct drm_i915_private *dev_priv = dev->dev_private;
5393
5394         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5395                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5396
5397                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5398                         dev_priv->max_cdclk_freq = 675000;
5399                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5400                         dev_priv->max_cdclk_freq = 540000;
5401                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5402                         dev_priv->max_cdclk_freq = 450000;
5403                 else
5404                         dev_priv->max_cdclk_freq = 337500;
5405         } else if (IS_BROADWELL(dev))  {
5406                 /*
5407                  * FIXME with extra cooling we can allow
5408                  * 540 MHz for ULX and 675 Mhz for ULT.
5409                  * How can we know if extra cooling is
5410                  * available? PCI ID, VTB, something else?
5411                  */
5412                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5413                         dev_priv->max_cdclk_freq = 450000;
5414                 else if (IS_BDW_ULX(dev))
5415                         dev_priv->max_cdclk_freq = 450000;
5416                 else if (IS_BDW_ULT(dev))
5417                         dev_priv->max_cdclk_freq = 540000;
5418                 else
5419                         dev_priv->max_cdclk_freq = 675000;
5420         } else if (IS_CHERRYVIEW(dev)) {
5421                 dev_priv->max_cdclk_freq = 320000;
5422         } else if (IS_VALLEYVIEW(dev)) {
5423                 dev_priv->max_cdclk_freq = 400000;
5424         } else {
5425                 /* otherwise assume cdclk is fixed */
5426                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5427         }
5428
5429         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5430
5431         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5432                          dev_priv->max_cdclk_freq);
5433
5434         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5435                          dev_priv->max_dotclk_freq);
5436 }
5437
5438 static void intel_update_cdclk(struct drm_device *dev)
5439 {
5440         struct drm_i915_private *dev_priv = dev->dev_private;
5441
5442         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5443         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5444                          dev_priv->cdclk_freq);
5445
5446         /*
5447          * Program the gmbus_freq based on the cdclk frequency.
5448          * BSpec erroneously claims we should aim for 4MHz, but
5449          * in fact 1MHz is the correct frequency.
5450          */
5451         if (IS_VALLEYVIEW(dev)) {
5452                 /*
5453                  * Program the gmbus_freq based on the cdclk frequency.
5454                  * BSpec erroneously claims we should aim for 4MHz, but
5455                  * in fact 1MHz is the correct frequency.
5456                  */
5457                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5458         }
5459
5460         if (dev_priv->max_cdclk_freq == 0)
5461                 intel_update_max_cdclk(dev);
5462 }
5463
5464 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5465 {
5466         struct drm_i915_private *dev_priv = dev->dev_private;
5467         uint32_t divider;
5468         uint32_t ratio;
5469         uint32_t current_freq;
5470         int ret;
5471
5472         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5473         switch (frequency) {
5474         case 144000:
5475                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5476                 ratio = BXT_DE_PLL_RATIO(60);
5477                 break;
5478         case 288000:
5479                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5480                 ratio = BXT_DE_PLL_RATIO(60);
5481                 break;
5482         case 384000:
5483                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5484                 ratio = BXT_DE_PLL_RATIO(60);
5485                 break;
5486         case 576000:
5487                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5488                 ratio = BXT_DE_PLL_RATIO(60);
5489                 break;
5490         case 624000:
5491                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5492                 ratio = BXT_DE_PLL_RATIO(65);
5493                 break;
5494         case 19200:
5495                 /*
5496                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5497                  * to suppress GCC warning.
5498                  */
5499                 ratio = 0;
5500                 divider = 0;
5501                 break;
5502         default:
5503                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5504
5505                 return;
5506         }
5507
5508         mutex_lock(&dev_priv->rps.hw_lock);
5509         /* Inform power controller of upcoming frequency change */
5510         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5511                                       0x80000000);
5512         mutex_unlock(&dev_priv->rps.hw_lock);
5513
5514         if (ret) {
5515                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5516                           ret, frequency);
5517                 return;
5518         }
5519
5520         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5521         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5522         current_freq = current_freq * 500 + 1000;
5523
5524         /*
5525          * DE PLL has to be disabled when
5526          * - setting to 19.2MHz (bypass, PLL isn't used)
5527          * - before setting to 624MHz (PLL needs toggling)
5528          * - before setting to any frequency from 624MHz (PLL needs toggling)
5529          */
5530         if (frequency == 19200 || frequency == 624000 ||
5531             current_freq == 624000) {
5532                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5533                 /* Timeout 200us */
5534                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5535                              1))
5536                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5537         }
5538
5539         if (frequency != 19200) {
5540                 uint32_t val;
5541
5542                 val = I915_READ(BXT_DE_PLL_CTL);
5543                 val &= ~BXT_DE_PLL_RATIO_MASK;
5544                 val |= ratio;
5545                 I915_WRITE(BXT_DE_PLL_CTL, val);
5546
5547                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5548                 /* Timeout 200us */
5549                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5550                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5551
5552                 val = I915_READ(CDCLK_CTL);
5553                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5554                 val |= divider;
5555                 /*
5556                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5557                  * enable otherwise.
5558                  */
5559                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5560                 if (frequency >= 500000)
5561                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5562
5563                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5564                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5565                 val |= (frequency - 1000) / 500;
5566                 I915_WRITE(CDCLK_CTL, val);
5567         }
5568
5569         mutex_lock(&dev_priv->rps.hw_lock);
5570         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5571                                       DIV_ROUND_UP(frequency, 25000));
5572         mutex_unlock(&dev_priv->rps.hw_lock);
5573
5574         if (ret) {
5575                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5576                           ret, frequency);
5577                 return;
5578         }
5579
5580         intel_update_cdclk(dev);
5581 }
5582
5583 void broxton_init_cdclk(struct drm_device *dev)
5584 {
5585         struct drm_i915_private *dev_priv = dev->dev_private;
5586         uint32_t val;
5587
5588         /*
5589          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5590          * or else the reset will hang because there is no PCH to respond.
5591          * Move the handshake programming to initialization sequence.
5592          * Previously was left up to BIOS.
5593          */
5594         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5595         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5596         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5597
5598         /* Enable PG1 for cdclk */
5599         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5600
5601         /* check if cd clock is enabled */
5602         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5603                 DRM_DEBUG_KMS("Display already initialized\n");
5604                 return;
5605         }
5606
5607         /*
5608          * FIXME:
5609          * - The initial CDCLK needs to be read from VBT.
5610          *   Need to make this change after VBT has changes for BXT.
5611          * - check if setting the max (or any) cdclk freq is really necessary
5612          *   here, it belongs to modeset time
5613          */
5614         broxton_set_cdclk(dev, 624000);
5615
5616         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5617         POSTING_READ(DBUF_CTL);
5618
5619         udelay(10);
5620
5621         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5622                 DRM_ERROR("DBuf power enable timeout!\n");
5623 }
5624
5625 void broxton_uninit_cdclk(struct drm_device *dev)
5626 {
5627         struct drm_i915_private *dev_priv = dev->dev_private;
5628
5629         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5630         POSTING_READ(DBUF_CTL);
5631
5632         udelay(10);
5633
5634         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5635                 DRM_ERROR("DBuf power disable timeout!\n");
5636
5637         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5638         broxton_set_cdclk(dev, 19200);
5639
5640         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5641 }
5642
5643 static const struct skl_cdclk_entry {
5644         unsigned int freq;
5645         unsigned int vco;
5646 } skl_cdclk_frequencies[] = {
5647         { .freq = 308570, .vco = 8640 },
5648         { .freq = 337500, .vco = 8100 },
5649         { .freq = 432000, .vco = 8640 },
5650         { .freq = 450000, .vco = 8100 },
5651         { .freq = 540000, .vco = 8100 },
5652         { .freq = 617140, .vco = 8640 },
5653         { .freq = 675000, .vco = 8100 },
5654 };
5655
5656 static unsigned int skl_cdclk_decimal(unsigned int freq)
5657 {
5658         return (freq - 1000) / 500;
5659 }
5660
5661 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5662 {
5663         unsigned int i;
5664
5665         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5666                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5667
5668                 if (e->freq == freq)
5669                         return e->vco;
5670         }
5671
5672         return 8100;
5673 }
5674
5675 static void
5676 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5677 {
5678         unsigned int min_freq;
5679         u32 val;
5680
5681         /* select the minimum CDCLK before enabling DPLL 0 */
5682         val = I915_READ(CDCLK_CTL);
5683         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5684         val |= CDCLK_FREQ_337_308;
5685
5686         if (required_vco == 8640)
5687                 min_freq = 308570;
5688         else
5689                 min_freq = 337500;
5690
5691         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5692
5693         I915_WRITE(CDCLK_CTL, val);
5694         POSTING_READ(CDCLK_CTL);
5695
5696         /*
5697          * We always enable DPLL0 with the lowest link rate possible, but still
5698          * taking into account the VCO required to operate the eDP panel at the
5699          * desired frequency. The usual DP link rates operate with a VCO of
5700          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5701          * The modeset code is responsible for the selection of the exact link
5702          * rate later on, with the constraint of choosing a frequency that
5703          * works with required_vco.
5704          */
5705         val = I915_READ(DPLL_CTRL1);
5706
5707         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5708                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5709         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5710         if (required_vco == 8640)
5711                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5712                                             SKL_DPLL0);
5713         else
5714                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5715                                             SKL_DPLL0);
5716
5717         I915_WRITE(DPLL_CTRL1, val);
5718         POSTING_READ(DPLL_CTRL1);
5719
5720         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5721
5722         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5723                 DRM_ERROR("DPLL0 not locked\n");
5724 }
5725
5726 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5727 {
5728         int ret;
5729         u32 val;
5730
5731         /* inform PCU we want to change CDCLK */
5732         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5733         mutex_lock(&dev_priv->rps.hw_lock);
5734         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5735         mutex_unlock(&dev_priv->rps.hw_lock);
5736
5737         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5738 }
5739
5740 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5741 {
5742         unsigned int i;
5743
5744         for (i = 0; i < 15; i++) {
5745                 if (skl_cdclk_pcu_ready(dev_priv))
5746                         return true;
5747                 udelay(10);
5748         }
5749
5750         return false;
5751 }
5752
5753 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5754 {
5755         struct drm_device *dev = dev_priv->dev;
5756         u32 freq_select, pcu_ack;
5757
5758         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5759
5760         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5761                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5762                 return;
5763         }
5764
5765         /* set CDCLK_CTL */
5766         switch(freq) {
5767         case 450000:
5768         case 432000:
5769                 freq_select = CDCLK_FREQ_450_432;
5770                 pcu_ack = 1;
5771                 break;
5772         case 540000:
5773                 freq_select = CDCLK_FREQ_540;
5774                 pcu_ack = 2;
5775                 break;
5776         case 308570:
5777         case 337500:
5778         default:
5779                 freq_select = CDCLK_FREQ_337_308;
5780                 pcu_ack = 0;
5781                 break;
5782         case 617140:
5783         case 675000:
5784                 freq_select = CDCLK_FREQ_675_617;
5785                 pcu_ack = 3;
5786                 break;
5787         }
5788
5789         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5790         POSTING_READ(CDCLK_CTL);
5791
5792         /* inform PCU of the change */
5793         mutex_lock(&dev_priv->rps.hw_lock);
5794         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5795         mutex_unlock(&dev_priv->rps.hw_lock);
5796
5797         intel_update_cdclk(dev);
5798 }
5799
5800 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5801 {
5802         /* disable DBUF power */
5803         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5804         POSTING_READ(DBUF_CTL);
5805
5806         udelay(10);
5807
5808         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5809                 DRM_ERROR("DBuf power disable timeout\n");
5810
5811         /* disable DPLL0 */
5812         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5813         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5814                 DRM_ERROR("Couldn't disable DPLL0\n");
5815 }
5816
5817 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5818 {
5819         unsigned int required_vco;
5820
5821         /* DPLL0 not enabled (happens on early BIOS versions) */
5822         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5823                 /* enable DPLL0 */
5824                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5825                 skl_dpll0_enable(dev_priv, required_vco);
5826         }
5827
5828         /* set CDCLK to the frequency the BIOS chose */
5829         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5830
5831         /* enable DBUF power */
5832         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5833         POSTING_READ(DBUF_CTL);
5834
5835         udelay(10);
5836
5837         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5838                 DRM_ERROR("DBuf power enable timeout\n");
5839 }
5840
5841 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5842 {
5843         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5844         uint32_t cdctl = I915_READ(CDCLK_CTL);
5845         int freq = dev_priv->skl_boot_cdclk;
5846
5847         /*
5848          * check if the pre-os intialized the display
5849          * There is SWF18 scratchpad register defined which is set by the
5850          * pre-os which can be used by the OS drivers to check the status
5851          */
5852         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5853                 goto sanitize;
5854
5855         /* Is PLL enabled and locked ? */
5856         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5857                 goto sanitize;
5858
5859         /* DPLL okay; verify the cdclock
5860          *
5861          * Noticed in some instances that the freq selection is correct but
5862          * decimal part is programmed wrong from BIOS where pre-os does not
5863          * enable display. Verify the same as well.
5864          */
5865         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5866                 /* All well; nothing to sanitize */
5867                 return false;
5868 sanitize:
5869         /*
5870          * As of now initialize with max cdclk till
5871          * we get dynamic cdclk support
5872          * */
5873         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5874         skl_init_cdclk(dev_priv);
5875
5876         /* we did have to sanitize */
5877         return true;
5878 }
5879
5880 /* Adjust CDclk dividers to allow high res or save power if possible */
5881 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5882 {
5883         struct drm_i915_private *dev_priv = dev->dev_private;
5884         u32 val, cmd;
5885
5886         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5887                                         != dev_priv->cdclk_freq);
5888
5889         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5890                 cmd = 2;
5891         else if (cdclk == 266667)
5892                 cmd = 1;
5893         else
5894                 cmd = 0;
5895
5896         mutex_lock(&dev_priv->rps.hw_lock);
5897         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5898         val &= ~DSPFREQGUAR_MASK;
5899         val |= (cmd << DSPFREQGUAR_SHIFT);
5900         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5901         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5902                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5903                      50)) {
5904                 DRM_ERROR("timed out waiting for CDclk change\n");
5905         }
5906         mutex_unlock(&dev_priv->rps.hw_lock);
5907
5908         mutex_lock(&dev_priv->sb_lock);
5909
5910         if (cdclk == 400000) {
5911                 u32 divider;
5912
5913                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5914
5915                 /* adjust cdclk divider */
5916                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5917                 val &= ~CCK_FREQUENCY_VALUES;
5918                 val |= divider;
5919                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5920
5921                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5922                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5923                              50))
5924                         DRM_ERROR("timed out waiting for CDclk change\n");
5925         }
5926
5927         /* adjust self-refresh exit latency value */
5928         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5929         val &= ~0x7f;
5930
5931         /*
5932          * For high bandwidth configs, we set a higher latency in the bunit
5933          * so that the core display fetch happens in time to avoid underruns.
5934          */
5935         if (cdclk == 400000)
5936                 val |= 4500 / 250; /* 4.5 usec */
5937         else
5938                 val |= 3000 / 250; /* 3.0 usec */
5939         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5940
5941         mutex_unlock(&dev_priv->sb_lock);
5942
5943         intel_update_cdclk(dev);
5944 }
5945
5946 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5947 {
5948         struct drm_i915_private *dev_priv = dev->dev_private;
5949         u32 val, cmd;
5950
5951         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5952                                                 != dev_priv->cdclk_freq);
5953
5954         switch (cdclk) {
5955         case 333333:
5956         case 320000:
5957         case 266667:
5958         case 200000:
5959                 break;
5960         default:
5961                 MISSING_CASE(cdclk);
5962                 return;
5963         }
5964
5965         /*
5966          * Specs are full of misinformation, but testing on actual
5967          * hardware has shown that we just need to write the desired
5968          * CCK divider into the Punit register.
5969          */
5970         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5971
5972         mutex_lock(&dev_priv->rps.hw_lock);
5973         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5974         val &= ~DSPFREQGUAR_MASK_CHV;
5975         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5976         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5977         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5978                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5979                      50)) {
5980                 DRM_ERROR("timed out waiting for CDclk change\n");
5981         }
5982         mutex_unlock(&dev_priv->rps.hw_lock);
5983
5984         intel_update_cdclk(dev);
5985 }
5986
5987 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5988                                  int max_pixclk)
5989 {
5990         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5991         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5992
5993         /*
5994          * Really only a few cases to deal with, as only 4 CDclks are supported:
5995          *   200MHz
5996          *   267MHz
5997          *   320/333MHz (depends on HPLL freq)
5998          *   400MHz (VLV only)
5999          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6000          * of the lower bin and adjust if needed.
6001          *
6002          * We seem to get an unstable or solid color picture at 200MHz.
6003          * Not sure what's wrong. For now use 200MHz only when all pipes
6004          * are off.
6005          */
6006         if (!IS_CHERRYVIEW(dev_priv) &&
6007             max_pixclk > freq_320*limit/100)
6008                 return 400000;
6009         else if (max_pixclk > 266667*limit/100)
6010                 return freq_320;
6011         else if (max_pixclk > 0)
6012                 return 266667;
6013         else
6014                 return 200000;
6015 }
6016
6017 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6018                               int max_pixclk)
6019 {
6020         /*
6021          * FIXME:
6022          * - remove the guardband, it's not needed on BXT
6023          * - set 19.2MHz bypass frequency if there are no active pipes
6024          */
6025         if (max_pixclk > 576000*9/10)
6026                 return 624000;
6027         else if (max_pixclk > 384000*9/10)
6028                 return 576000;
6029         else if (max_pixclk > 288000*9/10)
6030                 return 384000;
6031         else if (max_pixclk > 144000*9/10)
6032                 return 288000;
6033         else
6034                 return 144000;
6035 }
6036
6037 /* Compute the max pixel clock for new configuration. Uses atomic state if
6038  * that's non-NULL, look at current state otherwise. */
6039 static int intel_mode_max_pixclk(struct drm_device *dev,
6040                                  struct drm_atomic_state *state)
6041 {
6042         struct intel_crtc *intel_crtc;
6043         struct intel_crtc_state *crtc_state;
6044         int max_pixclk = 0;
6045
6046         for_each_intel_crtc(dev, intel_crtc) {
6047                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6048                 if (IS_ERR(crtc_state))
6049                         return PTR_ERR(crtc_state);
6050
6051                 if (!crtc_state->base.enable)
6052                         continue;
6053
6054                 max_pixclk = max(max_pixclk,
6055                                  crtc_state->base.adjusted_mode.crtc_clock);
6056         }
6057
6058         return max_pixclk;
6059 }
6060
6061 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6062 {
6063         struct drm_device *dev = state->dev;
6064         struct drm_i915_private *dev_priv = dev->dev_private;
6065         int max_pixclk = intel_mode_max_pixclk(dev, state);
6066
6067         if (max_pixclk < 0)
6068                 return max_pixclk;
6069
6070         to_intel_atomic_state(state)->cdclk =
6071                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6072
6073         return 0;
6074 }
6075
6076 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6077 {
6078         struct drm_device *dev = state->dev;
6079         struct drm_i915_private *dev_priv = dev->dev_private;
6080         int max_pixclk = intel_mode_max_pixclk(dev, state);
6081
6082         if (max_pixclk < 0)
6083                 return max_pixclk;
6084
6085         to_intel_atomic_state(state)->cdclk =
6086                 broxton_calc_cdclk(dev_priv, max_pixclk);
6087
6088         return 0;
6089 }
6090
6091 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6092 {
6093         unsigned int credits, default_credits;
6094
6095         if (IS_CHERRYVIEW(dev_priv))
6096                 default_credits = PFI_CREDIT(12);
6097         else
6098                 default_credits = PFI_CREDIT(8);
6099
6100         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6101                 /* CHV suggested value is 31 or 63 */
6102                 if (IS_CHERRYVIEW(dev_priv))
6103                         credits = PFI_CREDIT_63;
6104                 else
6105                         credits = PFI_CREDIT(15);
6106         } else {
6107                 credits = default_credits;
6108         }
6109
6110         /*
6111          * WA - write default credits before re-programming
6112          * FIXME: should we also set the resend bit here?
6113          */
6114         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6115                    default_credits);
6116
6117         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6118                    credits | PFI_CREDIT_RESEND);
6119
6120         /*
6121          * FIXME is this guaranteed to clear
6122          * immediately or should we poll for it?
6123          */
6124         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6125 }
6126
6127 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6128 {
6129         struct drm_device *dev = old_state->dev;
6130         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6131         struct drm_i915_private *dev_priv = dev->dev_private;
6132
6133         /*
6134          * FIXME: We can end up here with all power domains off, yet
6135          * with a CDCLK frequency other than the minimum. To account
6136          * for this take the PIPE-A power domain, which covers the HW
6137          * blocks needed for the following programming. This can be
6138          * removed once it's guaranteed that we get here either with
6139          * the minimum CDCLK set, or the required power domains
6140          * enabled.
6141          */
6142         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6143
6144         if (IS_CHERRYVIEW(dev))
6145                 cherryview_set_cdclk(dev, req_cdclk);
6146         else
6147                 valleyview_set_cdclk(dev, req_cdclk);
6148
6149         vlv_program_pfi_credits(dev_priv);
6150
6151         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6152 }
6153
6154 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6155 {
6156         struct drm_device *dev = crtc->dev;
6157         struct drm_i915_private *dev_priv = to_i915(dev);
6158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6159         struct intel_encoder *encoder;
6160         int pipe = intel_crtc->pipe;
6161
6162         if (WARN_ON(intel_crtc->active))
6163                 return;
6164
6165         if (intel_crtc->config->has_dp_encoder)
6166                 intel_dp_set_m_n(intel_crtc, M1_N1);
6167
6168         intel_set_pipe_timings(intel_crtc);
6169
6170         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6171                 struct drm_i915_private *dev_priv = dev->dev_private;
6172
6173                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6174                 I915_WRITE(CHV_CANVAS(pipe), 0);
6175         }
6176
6177         i9xx_set_pipeconf(intel_crtc);
6178
6179         intel_crtc->active = true;
6180
6181         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6182
6183         for_each_encoder_on_crtc(dev, crtc, encoder)
6184                 if (encoder->pre_pll_enable)
6185                         encoder->pre_pll_enable(encoder);
6186
6187         if (!intel_crtc->config->has_dsi_encoder) {
6188                 if (IS_CHERRYVIEW(dev)) {
6189                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6190                         chv_enable_pll(intel_crtc, intel_crtc->config);
6191                 } else {
6192                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6193                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6194                 }
6195         }
6196
6197         for_each_encoder_on_crtc(dev, crtc, encoder)
6198                 if (encoder->pre_enable)
6199                         encoder->pre_enable(encoder);
6200
6201         i9xx_pfit_enable(intel_crtc);
6202
6203         intel_crtc_load_lut(crtc);
6204
6205         intel_enable_pipe(intel_crtc);
6206
6207         assert_vblank_disabled(crtc);
6208         drm_crtc_vblank_on(crtc);
6209
6210         for_each_encoder_on_crtc(dev, crtc, encoder)
6211                 encoder->enable(encoder);
6212 }
6213
6214 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6215 {
6216         struct drm_device *dev = crtc->base.dev;
6217         struct drm_i915_private *dev_priv = dev->dev_private;
6218
6219         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6220         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6221 }
6222
6223 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6224 {
6225         struct drm_device *dev = crtc->dev;
6226         struct drm_i915_private *dev_priv = to_i915(dev);
6227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6228         struct intel_encoder *encoder;
6229         int pipe = intel_crtc->pipe;
6230
6231         if (WARN_ON(intel_crtc->active))
6232                 return;
6233
6234         i9xx_set_pll_dividers(intel_crtc);
6235
6236         if (intel_crtc->config->has_dp_encoder)
6237                 intel_dp_set_m_n(intel_crtc, M1_N1);
6238
6239         intel_set_pipe_timings(intel_crtc);
6240
6241         i9xx_set_pipeconf(intel_crtc);
6242
6243         intel_crtc->active = true;
6244
6245         if (!IS_GEN2(dev))
6246                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6247
6248         for_each_encoder_on_crtc(dev, crtc, encoder)
6249                 if (encoder->pre_enable)
6250                         encoder->pre_enable(encoder);
6251
6252         i9xx_enable_pll(intel_crtc);
6253
6254         i9xx_pfit_enable(intel_crtc);
6255
6256         intel_crtc_load_lut(crtc);
6257
6258         intel_update_watermarks(crtc);
6259         intel_enable_pipe(intel_crtc);
6260
6261         assert_vblank_disabled(crtc);
6262         drm_crtc_vblank_on(crtc);
6263
6264         for_each_encoder_on_crtc(dev, crtc, encoder)
6265                 encoder->enable(encoder);
6266 }
6267
6268 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6269 {
6270         struct drm_device *dev = crtc->base.dev;
6271         struct drm_i915_private *dev_priv = dev->dev_private;
6272
6273         if (!crtc->config->gmch_pfit.control)
6274                 return;
6275
6276         assert_pipe_disabled(dev_priv, crtc->pipe);
6277
6278         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6279                          I915_READ(PFIT_CONTROL));
6280         I915_WRITE(PFIT_CONTROL, 0);
6281 }
6282
6283 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6284 {
6285         struct drm_device *dev = crtc->dev;
6286         struct drm_i915_private *dev_priv = dev->dev_private;
6287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6288         struct intel_encoder *encoder;
6289         int pipe = intel_crtc->pipe;
6290
6291         /*
6292          * On gen2 planes are double buffered but the pipe isn't, so we must
6293          * wait for planes to fully turn off before disabling the pipe.
6294          * We also need to wait on all gmch platforms because of the
6295          * self-refresh mode constraint explained above.
6296          */
6297         intel_wait_for_vblank(dev, pipe);
6298
6299         for_each_encoder_on_crtc(dev, crtc, encoder)
6300                 encoder->disable(encoder);
6301
6302         drm_crtc_vblank_off(crtc);
6303         assert_vblank_disabled(crtc);
6304
6305         intel_disable_pipe(intel_crtc);
6306
6307         i9xx_pfit_disable(intel_crtc);
6308
6309         for_each_encoder_on_crtc(dev, crtc, encoder)
6310                 if (encoder->post_disable)
6311                         encoder->post_disable(encoder);
6312
6313         if (!intel_crtc->config->has_dsi_encoder) {
6314                 if (IS_CHERRYVIEW(dev))
6315                         chv_disable_pll(dev_priv, pipe);
6316                 else if (IS_VALLEYVIEW(dev))
6317                         vlv_disable_pll(dev_priv, pipe);
6318                 else
6319                         i9xx_disable_pll(intel_crtc);
6320         }
6321
6322         for_each_encoder_on_crtc(dev, crtc, encoder)
6323                 if (encoder->post_pll_disable)
6324                         encoder->post_pll_disable(encoder);
6325
6326         if (!IS_GEN2(dev))
6327                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6328 }
6329
6330 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6331 {
6332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6333         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6334         enum intel_display_power_domain domain;
6335         unsigned long domains;
6336
6337         if (!intel_crtc->active)
6338                 return;
6339
6340         if (to_intel_plane_state(crtc->primary->state)->visible) {
6341                 WARN_ON(intel_crtc->unpin_work);
6342
6343                 intel_pre_disable_primary(crtc);
6344         }
6345
6346         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6347         dev_priv->display.crtc_disable(crtc);
6348         intel_crtc->active = false;
6349         intel_update_watermarks(crtc);
6350         intel_disable_shared_dpll(intel_crtc);
6351
6352         domains = intel_crtc->enabled_power_domains;
6353         for_each_power_domain(domain, domains)
6354                 intel_display_power_put(dev_priv, domain);
6355         intel_crtc->enabled_power_domains = 0;
6356 }
6357
6358 /*
6359  * turn all crtc's off, but do not adjust state
6360  * This has to be paired with a call to intel_modeset_setup_hw_state.
6361  */
6362 int intel_display_suspend(struct drm_device *dev)
6363 {
6364         struct drm_mode_config *config = &dev->mode_config;
6365         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6366         struct drm_atomic_state *state;
6367         struct drm_crtc *crtc;
6368         unsigned crtc_mask = 0;
6369         int ret = 0;
6370
6371         if (WARN_ON(!ctx))
6372                 return 0;
6373
6374         lockdep_assert_held(&ctx->ww_ctx);
6375         state = drm_atomic_state_alloc(dev);
6376         if (WARN_ON(!state))
6377                 return -ENOMEM;
6378
6379         state->acquire_ctx = ctx;
6380         state->allow_modeset = true;
6381
6382         for_each_crtc(dev, crtc) {
6383                 struct drm_crtc_state *crtc_state =
6384                         drm_atomic_get_crtc_state(state, crtc);
6385
6386                 ret = PTR_ERR_OR_ZERO(crtc_state);
6387                 if (ret)
6388                         goto free;
6389
6390                 if (!crtc_state->active)
6391                         continue;
6392
6393                 crtc_state->active = false;
6394                 crtc_mask |= 1 << drm_crtc_index(crtc);
6395         }
6396
6397         if (crtc_mask) {
6398                 ret = drm_atomic_commit(state);
6399
6400                 if (!ret) {
6401                         for_each_crtc(dev, crtc)
6402                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6403                                         crtc->state->active = true;
6404
6405                         return ret;
6406                 }
6407         }
6408
6409 free:
6410         if (ret)
6411                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6412         drm_atomic_state_free(state);
6413         return ret;
6414 }
6415
6416 void intel_encoder_destroy(struct drm_encoder *encoder)
6417 {
6418         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6419
6420         drm_encoder_cleanup(encoder);
6421         kfree(intel_encoder);
6422 }
6423
6424 /* Cross check the actual hw state with our own modeset state tracking (and it's
6425  * internal consistency). */
6426 static void intel_connector_check_state(struct intel_connector *connector)
6427 {
6428         struct drm_crtc *crtc = connector->base.state->crtc;
6429
6430         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6431                       connector->base.base.id,
6432                       connector->base.name);
6433
6434         if (connector->get_hw_state(connector)) {
6435                 struct intel_encoder *encoder = connector->encoder;
6436                 struct drm_connector_state *conn_state = connector->base.state;
6437
6438                 I915_STATE_WARN(!crtc,
6439                          "connector enabled without attached crtc\n");
6440
6441                 if (!crtc)
6442                         return;
6443
6444                 I915_STATE_WARN(!crtc->state->active,
6445                       "connector is active, but attached crtc isn't\n");
6446
6447                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6448                         return;
6449
6450                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6451                         "atomic encoder doesn't match attached encoder\n");
6452
6453                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6454                         "attached encoder crtc differs from connector crtc\n");
6455         } else {
6456                 I915_STATE_WARN(crtc && crtc->state->active,
6457                         "attached crtc is active, but connector isn't\n");
6458                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6459                         "best encoder set without crtc!\n");
6460         }
6461 }
6462
6463 int intel_connector_init(struct intel_connector *connector)
6464 {
6465         struct drm_connector_state *connector_state;
6466
6467         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6468         if (!connector_state)
6469                 return -ENOMEM;
6470
6471         connector->base.state = connector_state;
6472         return 0;
6473 }
6474
6475 struct intel_connector *intel_connector_alloc(void)
6476 {
6477         struct intel_connector *connector;
6478
6479         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6480         if (!connector)
6481                 return NULL;
6482
6483         if (intel_connector_init(connector) < 0) {
6484                 kfree(connector);
6485                 return NULL;
6486         }
6487
6488         return connector;
6489 }
6490
6491 /* Simple connector->get_hw_state implementation for encoders that support only
6492  * one connector and no cloning and hence the encoder state determines the state
6493  * of the connector. */
6494 bool intel_connector_get_hw_state(struct intel_connector *connector)
6495 {
6496         enum pipe pipe = 0;
6497         struct intel_encoder *encoder = connector->encoder;
6498
6499         return encoder->get_hw_state(encoder, &pipe);
6500 }
6501
6502 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6503 {
6504         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6505                 return crtc_state->fdi_lanes;
6506
6507         return 0;
6508 }
6509
6510 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6511                                      struct intel_crtc_state *pipe_config)
6512 {
6513         struct drm_atomic_state *state = pipe_config->base.state;
6514         struct intel_crtc *other_crtc;
6515         struct intel_crtc_state *other_crtc_state;
6516
6517         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6518                       pipe_name(pipe), pipe_config->fdi_lanes);
6519         if (pipe_config->fdi_lanes > 4) {
6520                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6521                               pipe_name(pipe), pipe_config->fdi_lanes);
6522                 return -EINVAL;
6523         }
6524
6525         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6526                 if (pipe_config->fdi_lanes > 2) {
6527                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6528                                       pipe_config->fdi_lanes);
6529                         return -EINVAL;
6530                 } else {
6531                         return 0;
6532                 }
6533         }
6534
6535         if (INTEL_INFO(dev)->num_pipes == 2)
6536                 return 0;
6537
6538         /* Ivybridge 3 pipe is really complicated */
6539         switch (pipe) {
6540         case PIPE_A:
6541                 return 0;
6542         case PIPE_B:
6543                 if (pipe_config->fdi_lanes <= 2)
6544                         return 0;
6545
6546                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6547                 other_crtc_state =
6548                         intel_atomic_get_crtc_state(state, other_crtc);
6549                 if (IS_ERR(other_crtc_state))
6550                         return PTR_ERR(other_crtc_state);
6551
6552                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6553                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6554                                       pipe_name(pipe), pipe_config->fdi_lanes);
6555                         return -EINVAL;
6556                 }
6557                 return 0;
6558         case PIPE_C:
6559                 if (pipe_config->fdi_lanes > 2) {
6560                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6561                                       pipe_name(pipe), pipe_config->fdi_lanes);
6562                         return -EINVAL;
6563                 }
6564
6565                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6566                 other_crtc_state =
6567                         intel_atomic_get_crtc_state(state, other_crtc);
6568                 if (IS_ERR(other_crtc_state))
6569                         return PTR_ERR(other_crtc_state);
6570
6571                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6572                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6573                         return -EINVAL;
6574                 }
6575                 return 0;
6576         default:
6577                 BUG();
6578         }
6579 }
6580
6581 #define RETRY 1
6582 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6583                                        struct intel_crtc_state *pipe_config)
6584 {
6585         struct drm_device *dev = intel_crtc->base.dev;
6586         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6587         int lane, link_bw, fdi_dotclock, ret;
6588         bool needs_recompute = false;
6589
6590 retry:
6591         /* FDI is a binary signal running at ~2.7GHz, encoding
6592          * each output octet as 10 bits. The actual frequency
6593          * is stored as a divider into a 100MHz clock, and the
6594          * mode pixel clock is stored in units of 1KHz.
6595          * Hence the bw of each lane in terms of the mode signal
6596          * is:
6597          */
6598         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6599
6600         fdi_dotclock = adjusted_mode->crtc_clock;
6601
6602         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6603                                            pipe_config->pipe_bpp);
6604
6605         pipe_config->fdi_lanes = lane;
6606
6607         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6608                                link_bw, &pipe_config->fdi_m_n);
6609
6610         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6611                                        intel_crtc->pipe, pipe_config);
6612         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6613                 pipe_config->pipe_bpp -= 2*3;
6614                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6615                               pipe_config->pipe_bpp);
6616                 needs_recompute = true;
6617                 pipe_config->bw_constrained = true;
6618
6619                 goto retry;
6620         }
6621
6622         if (needs_recompute)
6623                 return RETRY;
6624
6625         return ret;
6626 }
6627
6628 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6629                                      struct intel_crtc_state *pipe_config)
6630 {
6631         if (pipe_config->pipe_bpp > 24)
6632                 return false;
6633
6634         /* HSW can handle pixel rate up to cdclk? */
6635         if (IS_HASWELL(dev_priv->dev))
6636                 return true;
6637
6638         /*
6639          * We compare against max which means we must take
6640          * the increased cdclk requirement into account when
6641          * calculating the new cdclk.
6642          *
6643          * Should measure whether using a lower cdclk w/o IPS
6644          */
6645         return ilk_pipe_pixel_rate(pipe_config) <=
6646                 dev_priv->max_cdclk_freq * 95 / 100;
6647 }
6648
6649 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6650                                    struct intel_crtc_state *pipe_config)
6651 {
6652         struct drm_device *dev = crtc->base.dev;
6653         struct drm_i915_private *dev_priv = dev->dev_private;
6654
6655         pipe_config->ips_enabled = i915.enable_ips &&
6656                 hsw_crtc_supports_ips(crtc) &&
6657                 pipe_config_supports_ips(dev_priv, pipe_config);
6658 }
6659
6660 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6661 {
6662         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6663
6664         /* GDG double wide on either pipe, otherwise pipe A only */
6665         return INTEL_INFO(dev_priv)->gen < 4 &&
6666                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6667 }
6668
6669 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6670                                      struct intel_crtc_state *pipe_config)
6671 {
6672         struct drm_device *dev = crtc->base.dev;
6673         struct drm_i915_private *dev_priv = dev->dev_private;
6674         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6675
6676         /* FIXME should check pixel clock limits on all platforms */
6677         if (INTEL_INFO(dev)->gen < 4) {
6678                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6679
6680                 /*
6681                  * Enable double wide mode when the dot clock
6682                  * is > 90% of the (display) core speed.
6683                  */
6684                 if (intel_crtc_supports_double_wide(crtc) &&
6685                     adjusted_mode->crtc_clock > clock_limit) {
6686                         clock_limit *= 2;
6687                         pipe_config->double_wide = true;
6688                 }
6689
6690                 if (adjusted_mode->crtc_clock > clock_limit) {
6691                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6692                                       adjusted_mode->crtc_clock, clock_limit,
6693                                       yesno(pipe_config->double_wide));
6694                         return -EINVAL;
6695                 }
6696         }
6697
6698         /*
6699          * Pipe horizontal size must be even in:
6700          * - DVO ganged mode
6701          * - LVDS dual channel mode
6702          * - Double wide pipe
6703          */
6704         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6705              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6706                 pipe_config->pipe_src_w &= ~1;
6707
6708         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6709          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6710          */
6711         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6712                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6713                 return -EINVAL;
6714
6715         if (HAS_IPS(dev))
6716                 hsw_compute_ips_config(crtc, pipe_config);
6717
6718         if (pipe_config->has_pch_encoder)
6719                 return ironlake_fdi_compute_config(crtc, pipe_config);
6720
6721         return 0;
6722 }
6723
6724 static int skylake_get_display_clock_speed(struct drm_device *dev)
6725 {
6726         struct drm_i915_private *dev_priv = to_i915(dev);
6727         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6728         uint32_t cdctl = I915_READ(CDCLK_CTL);
6729         uint32_t linkrate;
6730
6731         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6732                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6733
6734         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6735                 return 540000;
6736
6737         linkrate = (I915_READ(DPLL_CTRL1) &
6738                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6739
6740         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6741             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6742                 /* vco 8640 */
6743                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6744                 case CDCLK_FREQ_450_432:
6745                         return 432000;
6746                 case CDCLK_FREQ_337_308:
6747                         return 308570;
6748                 case CDCLK_FREQ_675_617:
6749                         return 617140;
6750                 default:
6751                         WARN(1, "Unknown cd freq selection\n");
6752                 }
6753         } else {
6754                 /* vco 8100 */
6755                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6756                 case CDCLK_FREQ_450_432:
6757                         return 450000;
6758                 case CDCLK_FREQ_337_308:
6759                         return 337500;
6760                 case CDCLK_FREQ_675_617:
6761                         return 675000;
6762                 default:
6763                         WARN(1, "Unknown cd freq selection\n");
6764                 }
6765         }
6766
6767         /* error case, do as if DPLL0 isn't enabled */
6768         return 24000;
6769 }
6770
6771 static int broxton_get_display_clock_speed(struct drm_device *dev)
6772 {
6773         struct drm_i915_private *dev_priv = to_i915(dev);
6774         uint32_t cdctl = I915_READ(CDCLK_CTL);
6775         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6776         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6777         int cdclk;
6778
6779         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6780                 return 19200;
6781
6782         cdclk = 19200 * pll_ratio / 2;
6783
6784         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6785         case BXT_CDCLK_CD2X_DIV_SEL_1:
6786                 return cdclk;  /* 576MHz or 624MHz */
6787         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6788                 return cdclk * 2 / 3; /* 384MHz */
6789         case BXT_CDCLK_CD2X_DIV_SEL_2:
6790                 return cdclk / 2; /* 288MHz */
6791         case BXT_CDCLK_CD2X_DIV_SEL_4:
6792                 return cdclk / 4; /* 144MHz */
6793         }
6794
6795         /* error case, do as if DE PLL isn't enabled */
6796         return 19200;
6797 }
6798
6799 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6800 {
6801         struct drm_i915_private *dev_priv = dev->dev_private;
6802         uint32_t lcpll = I915_READ(LCPLL_CTL);
6803         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6804
6805         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6806                 return 800000;
6807         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6808                 return 450000;
6809         else if (freq == LCPLL_CLK_FREQ_450)
6810                 return 450000;
6811         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6812                 return 540000;
6813         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6814                 return 337500;
6815         else
6816                 return 675000;
6817 }
6818
6819 static int haswell_get_display_clock_speed(struct drm_device *dev)
6820 {
6821         struct drm_i915_private *dev_priv = dev->dev_private;
6822         uint32_t lcpll = I915_READ(LCPLL_CTL);
6823         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6824
6825         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6826                 return 800000;
6827         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6828                 return 450000;
6829         else if (freq == LCPLL_CLK_FREQ_450)
6830                 return 450000;
6831         else if (IS_HSW_ULT(dev))
6832                 return 337500;
6833         else
6834                 return 540000;
6835 }
6836
6837 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6838 {
6839         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6840                                       CCK_DISPLAY_CLOCK_CONTROL);
6841 }
6842
6843 static int ilk_get_display_clock_speed(struct drm_device *dev)
6844 {
6845         return 450000;
6846 }
6847
6848 static int i945_get_display_clock_speed(struct drm_device *dev)
6849 {
6850         return 400000;
6851 }
6852
6853 static int i915_get_display_clock_speed(struct drm_device *dev)
6854 {
6855         return 333333;
6856 }
6857
6858 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6859 {
6860         return 200000;
6861 }
6862
6863 static int pnv_get_display_clock_speed(struct drm_device *dev)
6864 {
6865         u16 gcfgc = 0;
6866
6867         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6868
6869         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6870         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6871                 return 266667;
6872         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6873                 return 333333;
6874         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6875                 return 444444;
6876         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6877                 return 200000;
6878         default:
6879                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6880         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6881                 return 133333;
6882         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6883                 return 166667;
6884         }
6885 }
6886
6887 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6888 {
6889         u16 gcfgc = 0;
6890
6891         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6892
6893         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6894                 return 133333;
6895         else {
6896                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6897                 case GC_DISPLAY_CLOCK_333_MHZ:
6898                         return 333333;
6899                 default:
6900                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6901                         return 190000;
6902                 }
6903         }
6904 }
6905
6906 static int i865_get_display_clock_speed(struct drm_device *dev)
6907 {
6908         return 266667;
6909 }
6910
6911 static int i85x_get_display_clock_speed(struct drm_device *dev)
6912 {
6913         u16 hpllcc = 0;
6914
6915         /*
6916          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6917          * encoding is different :(
6918          * FIXME is this the right way to detect 852GM/852GMV?
6919          */
6920         if (dev->pdev->revision == 0x1)
6921                 return 133333;
6922
6923         pci_bus_read_config_word(dev->pdev->bus,
6924                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6925
6926         /* Assume that the hardware is in the high speed state.  This
6927          * should be the default.
6928          */
6929         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6930         case GC_CLOCK_133_200:
6931         case GC_CLOCK_133_200_2:
6932         case GC_CLOCK_100_200:
6933                 return 200000;
6934         case GC_CLOCK_166_250:
6935                 return 250000;
6936         case GC_CLOCK_100_133:
6937                 return 133333;
6938         case GC_CLOCK_133_266:
6939         case GC_CLOCK_133_266_2:
6940         case GC_CLOCK_166_266:
6941                 return 266667;
6942         }
6943
6944         /* Shouldn't happen */
6945         return 0;
6946 }
6947
6948 static int i830_get_display_clock_speed(struct drm_device *dev)
6949 {
6950         return 133333;
6951 }
6952
6953 static unsigned int intel_hpll_vco(struct drm_device *dev)
6954 {
6955         struct drm_i915_private *dev_priv = dev->dev_private;
6956         static const unsigned int blb_vco[8] = {
6957                 [0] = 3200000,
6958                 [1] = 4000000,
6959                 [2] = 5333333,
6960                 [3] = 4800000,
6961                 [4] = 6400000,
6962         };
6963         static const unsigned int pnv_vco[8] = {
6964                 [0] = 3200000,
6965                 [1] = 4000000,
6966                 [2] = 5333333,
6967                 [3] = 4800000,
6968                 [4] = 2666667,
6969         };
6970         static const unsigned int cl_vco[8] = {
6971                 [0] = 3200000,
6972                 [1] = 4000000,
6973                 [2] = 5333333,
6974                 [3] = 6400000,
6975                 [4] = 3333333,
6976                 [5] = 3566667,
6977                 [6] = 4266667,
6978         };
6979         static const unsigned int elk_vco[8] = {
6980                 [0] = 3200000,
6981                 [1] = 4000000,
6982                 [2] = 5333333,
6983                 [3] = 4800000,
6984         };
6985         static const unsigned int ctg_vco[8] = {
6986                 [0] = 3200000,
6987                 [1] = 4000000,
6988                 [2] = 5333333,
6989                 [3] = 6400000,
6990                 [4] = 2666667,
6991                 [5] = 4266667,
6992         };
6993         const unsigned int *vco_table;
6994         unsigned int vco;
6995         uint8_t tmp = 0;
6996
6997         /* FIXME other chipsets? */
6998         if (IS_GM45(dev))
6999                 vco_table = ctg_vco;
7000         else if (IS_G4X(dev))
7001                 vco_table = elk_vco;
7002         else if (IS_CRESTLINE(dev))
7003                 vco_table = cl_vco;
7004         else if (IS_PINEVIEW(dev))
7005                 vco_table = pnv_vco;
7006         else if (IS_G33(dev))
7007                 vco_table = blb_vco;
7008         else
7009                 return 0;
7010
7011         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7012
7013         vco = vco_table[tmp & 0x7];
7014         if (vco == 0)
7015                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7016         else
7017                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7018
7019         return vco;
7020 }
7021
7022 static int gm45_get_display_clock_speed(struct drm_device *dev)
7023 {
7024         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7025         uint16_t tmp = 0;
7026
7027         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7028
7029         cdclk_sel = (tmp >> 12) & 0x1;
7030
7031         switch (vco) {
7032         case 2666667:
7033         case 4000000:
7034         case 5333333:
7035                 return cdclk_sel ? 333333 : 222222;
7036         case 3200000:
7037                 return cdclk_sel ? 320000 : 228571;
7038         default:
7039                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7040                 return 222222;
7041         }
7042 }
7043
7044 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7045 {
7046         static const uint8_t div_3200[] = { 16, 10,  8 };
7047         static const uint8_t div_4000[] = { 20, 12, 10 };
7048         static const uint8_t div_5333[] = { 24, 16, 14 };
7049         const uint8_t *div_table;
7050         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7051         uint16_t tmp = 0;
7052
7053         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7054
7055         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7056
7057         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7058                 goto fail;
7059
7060         switch (vco) {
7061         case 3200000:
7062                 div_table = div_3200;
7063                 break;
7064         case 4000000:
7065                 div_table = div_4000;
7066                 break;
7067         case 5333333:
7068                 div_table = div_5333;
7069                 break;
7070         default:
7071                 goto fail;
7072         }
7073
7074         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7075
7076 fail:
7077         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7078         return 200000;
7079 }
7080
7081 static int g33_get_display_clock_speed(struct drm_device *dev)
7082 {
7083         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7084         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7085         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7086         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7087         const uint8_t *div_table;
7088         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7089         uint16_t tmp = 0;
7090
7091         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7092
7093         cdclk_sel = (tmp >> 4) & 0x7;
7094
7095         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7096                 goto fail;
7097
7098         switch (vco) {
7099         case 3200000:
7100                 div_table = div_3200;
7101                 break;
7102         case 4000000:
7103                 div_table = div_4000;
7104                 break;
7105         case 4800000:
7106                 div_table = div_4800;
7107                 break;
7108         case 5333333:
7109                 div_table = div_5333;
7110                 break;
7111         default:
7112                 goto fail;
7113         }
7114
7115         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7116
7117 fail:
7118         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7119         return 190476;
7120 }
7121
7122 static void
7123 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7124 {
7125         while (*num > DATA_LINK_M_N_MASK ||
7126                *den > DATA_LINK_M_N_MASK) {
7127                 *num >>= 1;
7128                 *den >>= 1;
7129         }
7130 }
7131
7132 static void compute_m_n(unsigned int m, unsigned int n,
7133                         uint32_t *ret_m, uint32_t *ret_n)
7134 {
7135         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7136         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7137         intel_reduce_m_n_ratio(ret_m, ret_n);
7138 }
7139
7140 void
7141 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7142                        int pixel_clock, int link_clock,
7143                        struct intel_link_m_n *m_n)
7144 {
7145         m_n->tu = 64;
7146
7147         compute_m_n(bits_per_pixel * pixel_clock,
7148                     link_clock * nlanes * 8,
7149                     &m_n->gmch_m, &m_n->gmch_n);
7150
7151         compute_m_n(pixel_clock, link_clock,
7152                     &m_n->link_m, &m_n->link_n);
7153 }
7154
7155 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7156 {
7157         if (i915.panel_use_ssc >= 0)
7158                 return i915.panel_use_ssc != 0;
7159         return dev_priv->vbt.lvds_use_ssc
7160                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7161 }
7162
7163 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7164                            int num_connectors)
7165 {
7166         struct drm_device *dev = crtc_state->base.crtc->dev;
7167         struct drm_i915_private *dev_priv = dev->dev_private;
7168         int refclk;
7169
7170         WARN_ON(!crtc_state->base.state);
7171
7172         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7173                 refclk = 100000;
7174         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7175             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7176                 refclk = dev_priv->vbt.lvds_ssc_freq;
7177                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7178         } else if (!IS_GEN2(dev)) {
7179                 refclk = 96000;
7180         } else {
7181                 refclk = 48000;
7182         }
7183
7184         return refclk;
7185 }
7186
7187 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7188 {
7189         return (1 << dpll->n) << 16 | dpll->m2;
7190 }
7191
7192 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7193 {
7194         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7195 }
7196
7197 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7198                                      struct intel_crtc_state *crtc_state,
7199                                      intel_clock_t *reduced_clock)
7200 {
7201         struct drm_device *dev = crtc->base.dev;
7202         u32 fp, fp2 = 0;
7203
7204         if (IS_PINEVIEW(dev)) {
7205                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7206                 if (reduced_clock)
7207                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7208         } else {
7209                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7210                 if (reduced_clock)
7211                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7212         }
7213
7214         crtc_state->dpll_hw_state.fp0 = fp;
7215
7216         crtc->lowfreq_avail = false;
7217         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7218             reduced_clock) {
7219                 crtc_state->dpll_hw_state.fp1 = fp2;
7220                 crtc->lowfreq_avail = true;
7221         } else {
7222                 crtc_state->dpll_hw_state.fp1 = fp;
7223         }
7224 }
7225
7226 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7227                 pipe)
7228 {
7229         u32 reg_val;
7230
7231         /*
7232          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7233          * and set it to a reasonable value instead.
7234          */
7235         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7236         reg_val &= 0xffffff00;
7237         reg_val |= 0x00000030;
7238         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7239
7240         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7241         reg_val &= 0x8cffffff;
7242         reg_val = 0x8c000000;
7243         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7244
7245         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7246         reg_val &= 0xffffff00;
7247         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7248
7249         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7250         reg_val &= 0x00ffffff;
7251         reg_val |= 0xb0000000;
7252         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7253 }
7254
7255 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7256                                          struct intel_link_m_n *m_n)
7257 {
7258         struct drm_device *dev = crtc->base.dev;
7259         struct drm_i915_private *dev_priv = dev->dev_private;
7260         int pipe = crtc->pipe;
7261
7262         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7263         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7264         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7265         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7266 }
7267
7268 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7269                                          struct intel_link_m_n *m_n,
7270                                          struct intel_link_m_n *m2_n2)
7271 {
7272         struct drm_device *dev = crtc->base.dev;
7273         struct drm_i915_private *dev_priv = dev->dev_private;
7274         int pipe = crtc->pipe;
7275         enum transcoder transcoder = crtc->config->cpu_transcoder;
7276
7277         if (INTEL_INFO(dev)->gen >= 5) {
7278                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7279                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7280                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7281                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7282                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7283                  * for gen < 8) and if DRRS is supported (to make sure the
7284                  * registers are not unnecessarily accessed).
7285                  */
7286                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7287                         crtc->config->has_drrs) {
7288                         I915_WRITE(PIPE_DATA_M2(transcoder),
7289                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7290                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7291                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7292                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7293                 }
7294         } else {
7295                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7296                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7297                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7298                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7299         }
7300 }
7301
7302 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7303 {
7304         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7305
7306         if (m_n == M1_N1) {
7307                 dp_m_n = &crtc->config->dp_m_n;
7308                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7309         } else if (m_n == M2_N2) {
7310
7311                 /*
7312                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7313                  * needs to be programmed into M1_N1.
7314                  */
7315                 dp_m_n = &crtc->config->dp_m2_n2;
7316         } else {
7317                 DRM_ERROR("Unsupported divider value\n");
7318                 return;
7319         }
7320
7321         if (crtc->config->has_pch_encoder)
7322                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7323         else
7324                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7325 }
7326
7327 static void vlv_compute_dpll(struct intel_crtc *crtc,
7328                              struct intel_crtc_state *pipe_config)
7329 {
7330         u32 dpll, dpll_md;
7331
7332         /*
7333          * Enable DPIO clock input. We should never disable the reference
7334          * clock for pipe B, since VGA hotplug / manual detection depends
7335          * on it.
7336          */
7337         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7338                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7339         /* We should never disable this, set it here for state tracking */
7340         if (crtc->pipe == PIPE_B)
7341                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7342         dpll |= DPLL_VCO_ENABLE;
7343         pipe_config->dpll_hw_state.dpll = dpll;
7344
7345         dpll_md = (pipe_config->pixel_multiplier - 1)
7346                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7347         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7348 }
7349
7350 static void vlv_prepare_pll(struct intel_crtc *crtc,
7351                             const struct intel_crtc_state *pipe_config)
7352 {
7353         struct drm_device *dev = crtc->base.dev;
7354         struct drm_i915_private *dev_priv = dev->dev_private;
7355         int pipe = crtc->pipe;
7356         u32 mdiv;
7357         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7358         u32 coreclk, reg_val;
7359
7360         mutex_lock(&dev_priv->sb_lock);
7361
7362         bestn = pipe_config->dpll.n;
7363         bestm1 = pipe_config->dpll.m1;
7364         bestm2 = pipe_config->dpll.m2;
7365         bestp1 = pipe_config->dpll.p1;
7366         bestp2 = pipe_config->dpll.p2;
7367
7368         /* See eDP HDMI DPIO driver vbios notes doc */
7369
7370         /* PLL B needs special handling */
7371         if (pipe == PIPE_B)
7372                 vlv_pllb_recal_opamp(dev_priv, pipe);
7373
7374         /* Set up Tx target for periodic Rcomp update */
7375         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7376
7377         /* Disable target IRef on PLL */
7378         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7379         reg_val &= 0x00ffffff;
7380         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7381
7382         /* Disable fast lock */
7383         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7384
7385         /* Set idtafcrecal before PLL is enabled */
7386         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7387         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7388         mdiv |= ((bestn << DPIO_N_SHIFT));
7389         mdiv |= (1 << DPIO_K_SHIFT);
7390
7391         /*
7392          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7393          * but we don't support that).
7394          * Note: don't use the DAC post divider as it seems unstable.
7395          */
7396         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7397         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7398
7399         mdiv |= DPIO_ENABLE_CALIBRATION;
7400         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7401
7402         /* Set HBR and RBR LPF coefficients */
7403         if (pipe_config->port_clock == 162000 ||
7404             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7405             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7406                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7407                                  0x009f0003);
7408         else
7409                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7410                                  0x00d0000f);
7411
7412         if (pipe_config->has_dp_encoder) {
7413                 /* Use SSC source */
7414                 if (pipe == PIPE_A)
7415                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7416                                          0x0df40000);
7417                 else
7418                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7419                                          0x0df70000);
7420         } else { /* HDMI or VGA */
7421                 /* Use bend source */
7422                 if (pipe == PIPE_A)
7423                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7424                                          0x0df70000);
7425                 else
7426                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7427                                          0x0df40000);
7428         }
7429
7430         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7431         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7432         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7433             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7434                 coreclk |= 0x01000000;
7435         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7436
7437         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7438         mutex_unlock(&dev_priv->sb_lock);
7439 }
7440
7441 static void chv_compute_dpll(struct intel_crtc *crtc,
7442                              struct intel_crtc_state *pipe_config)
7443 {
7444         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7445                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7446                 DPLL_VCO_ENABLE;
7447         if (crtc->pipe != PIPE_A)
7448                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7449
7450         pipe_config->dpll_hw_state.dpll_md =
7451                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7452 }
7453
7454 static void chv_prepare_pll(struct intel_crtc *crtc,
7455                             const struct intel_crtc_state *pipe_config)
7456 {
7457         struct drm_device *dev = crtc->base.dev;
7458         struct drm_i915_private *dev_priv = dev->dev_private;
7459         int pipe = crtc->pipe;
7460         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7461         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7462         u32 loopfilter, tribuf_calcntr;
7463         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7464         u32 dpio_val;
7465         int vco;
7466
7467         bestn = pipe_config->dpll.n;
7468         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7469         bestm1 = pipe_config->dpll.m1;
7470         bestm2 = pipe_config->dpll.m2 >> 22;
7471         bestp1 = pipe_config->dpll.p1;
7472         bestp2 = pipe_config->dpll.p2;
7473         vco = pipe_config->dpll.vco;
7474         dpio_val = 0;
7475         loopfilter = 0;
7476
7477         /*
7478          * Enable Refclk and SSC
7479          */
7480         I915_WRITE(dpll_reg,
7481                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7482
7483         mutex_lock(&dev_priv->sb_lock);
7484
7485         /* p1 and p2 divider */
7486         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7487                         5 << DPIO_CHV_S1_DIV_SHIFT |
7488                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7489                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7490                         1 << DPIO_CHV_K_DIV_SHIFT);
7491
7492         /* Feedback post-divider - m2 */
7493         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7494
7495         /* Feedback refclk divider - n and m1 */
7496         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7497                         DPIO_CHV_M1_DIV_BY_2 |
7498                         1 << DPIO_CHV_N_DIV_SHIFT);
7499
7500         /* M2 fraction division */
7501         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7502
7503         /* M2 fraction division enable */
7504         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7505         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7506         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7507         if (bestm2_frac)
7508                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7509         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7510
7511         /* Program digital lock detect threshold */
7512         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7513         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7514                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7515         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7516         if (!bestm2_frac)
7517                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7518         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7519
7520         /* Loop filter */
7521         if (vco == 5400000) {
7522                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7523                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7524                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7525                 tribuf_calcntr = 0x9;
7526         } else if (vco <= 6200000) {
7527                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7528                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7529                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7530                 tribuf_calcntr = 0x9;
7531         } else if (vco <= 6480000) {
7532                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7533                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7534                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7535                 tribuf_calcntr = 0x8;
7536         } else {
7537                 /* Not supported. Apply the same limits as in the max case */
7538                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7539                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7540                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7541                 tribuf_calcntr = 0;
7542         }
7543         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7544
7545         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7546         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7547         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7548         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7549
7550         /* AFC Recal */
7551         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7552                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7553                         DPIO_AFC_RECAL);
7554
7555         mutex_unlock(&dev_priv->sb_lock);
7556 }
7557
7558 /**
7559  * vlv_force_pll_on - forcibly enable just the PLL
7560  * @dev_priv: i915 private structure
7561  * @pipe: pipe PLL to enable
7562  * @dpll: PLL configuration
7563  *
7564  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7565  * in cases where we need the PLL enabled even when @pipe is not going to
7566  * be enabled.
7567  */
7568 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7569                       const struct dpll *dpll)
7570 {
7571         struct intel_crtc *crtc =
7572                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7573         struct intel_crtc_state pipe_config = {
7574                 .base.crtc = &crtc->base,
7575                 .pixel_multiplier = 1,
7576                 .dpll = *dpll,
7577         };
7578
7579         if (IS_CHERRYVIEW(dev)) {
7580                 chv_compute_dpll(crtc, &pipe_config);
7581                 chv_prepare_pll(crtc, &pipe_config);
7582                 chv_enable_pll(crtc, &pipe_config);
7583         } else {
7584                 vlv_compute_dpll(crtc, &pipe_config);
7585                 vlv_prepare_pll(crtc, &pipe_config);
7586                 vlv_enable_pll(crtc, &pipe_config);
7587         }
7588 }
7589
7590 /**
7591  * vlv_force_pll_off - forcibly disable just the PLL
7592  * @dev_priv: i915 private structure
7593  * @pipe: pipe PLL to disable
7594  *
7595  * Disable the PLL for @pipe. To be used in cases where we need
7596  * the PLL enabled even when @pipe is not going to be enabled.
7597  */
7598 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7599 {
7600         if (IS_CHERRYVIEW(dev))
7601                 chv_disable_pll(to_i915(dev), pipe);
7602         else
7603                 vlv_disable_pll(to_i915(dev), pipe);
7604 }
7605
7606 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7607                               struct intel_crtc_state *crtc_state,
7608                               intel_clock_t *reduced_clock,
7609                               int num_connectors)
7610 {
7611         struct drm_device *dev = crtc->base.dev;
7612         struct drm_i915_private *dev_priv = dev->dev_private;
7613         u32 dpll;
7614         bool is_sdvo;
7615         struct dpll *clock = &crtc_state->dpll;
7616
7617         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7618
7619         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7620                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7621
7622         dpll = DPLL_VGA_MODE_DIS;
7623
7624         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7625                 dpll |= DPLLB_MODE_LVDS;
7626         else
7627                 dpll |= DPLLB_MODE_DAC_SERIAL;
7628
7629         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7630                 dpll |= (crtc_state->pixel_multiplier - 1)
7631                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7632         }
7633
7634         if (is_sdvo)
7635                 dpll |= DPLL_SDVO_HIGH_SPEED;
7636
7637         if (crtc_state->has_dp_encoder)
7638                 dpll |= DPLL_SDVO_HIGH_SPEED;
7639
7640         /* compute bitmask from p1 value */
7641         if (IS_PINEVIEW(dev))
7642                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7643         else {
7644                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7645                 if (IS_G4X(dev) && reduced_clock)
7646                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7647         }
7648         switch (clock->p2) {
7649         case 5:
7650                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7651                 break;
7652         case 7:
7653                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7654                 break;
7655         case 10:
7656                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7657                 break;
7658         case 14:
7659                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7660                 break;
7661         }
7662         if (INTEL_INFO(dev)->gen >= 4)
7663                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7664
7665         if (crtc_state->sdvo_tv_clock)
7666                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7667         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7668                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7669                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7670         else
7671                 dpll |= PLL_REF_INPUT_DREFCLK;
7672
7673         dpll |= DPLL_VCO_ENABLE;
7674         crtc_state->dpll_hw_state.dpll = dpll;
7675
7676         if (INTEL_INFO(dev)->gen >= 4) {
7677                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7678                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7679                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7680         }
7681 }
7682
7683 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7684                               struct intel_crtc_state *crtc_state,
7685                               intel_clock_t *reduced_clock,
7686                               int num_connectors)
7687 {
7688         struct drm_device *dev = crtc->base.dev;
7689         struct drm_i915_private *dev_priv = dev->dev_private;
7690         u32 dpll;
7691         struct dpll *clock = &crtc_state->dpll;
7692
7693         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7694
7695         dpll = DPLL_VGA_MODE_DIS;
7696
7697         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7698                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7699         } else {
7700                 if (clock->p1 == 2)
7701                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7702                 else
7703                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7704                 if (clock->p2 == 4)
7705                         dpll |= PLL_P2_DIVIDE_BY_4;
7706         }
7707
7708         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7709                 dpll |= DPLL_DVO_2X_MODE;
7710
7711         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7712                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7713                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7714         else
7715                 dpll |= PLL_REF_INPUT_DREFCLK;
7716
7717         dpll |= DPLL_VCO_ENABLE;
7718         crtc_state->dpll_hw_state.dpll = dpll;
7719 }
7720
7721 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7722 {
7723         struct drm_device *dev = intel_crtc->base.dev;
7724         struct drm_i915_private *dev_priv = dev->dev_private;
7725         enum pipe pipe = intel_crtc->pipe;
7726         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7727         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7728         uint32_t crtc_vtotal, crtc_vblank_end;
7729         int vsyncshift = 0;
7730
7731         /* We need to be careful not to changed the adjusted mode, for otherwise
7732          * the hw state checker will get angry at the mismatch. */
7733         crtc_vtotal = adjusted_mode->crtc_vtotal;
7734         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7735
7736         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7737                 /* the chip adds 2 halflines automatically */
7738                 crtc_vtotal -= 1;
7739                 crtc_vblank_end -= 1;
7740
7741                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7742                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7743                 else
7744                         vsyncshift = adjusted_mode->crtc_hsync_start -
7745                                 adjusted_mode->crtc_htotal / 2;
7746                 if (vsyncshift < 0)
7747                         vsyncshift += adjusted_mode->crtc_htotal;
7748         }
7749
7750         if (INTEL_INFO(dev)->gen > 3)
7751                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7752
7753         I915_WRITE(HTOTAL(cpu_transcoder),
7754                    (adjusted_mode->crtc_hdisplay - 1) |
7755                    ((adjusted_mode->crtc_htotal - 1) << 16));
7756         I915_WRITE(HBLANK(cpu_transcoder),
7757                    (adjusted_mode->crtc_hblank_start - 1) |
7758                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7759         I915_WRITE(HSYNC(cpu_transcoder),
7760                    (adjusted_mode->crtc_hsync_start - 1) |
7761                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7762
7763         I915_WRITE(VTOTAL(cpu_transcoder),
7764                    (adjusted_mode->crtc_vdisplay - 1) |
7765                    ((crtc_vtotal - 1) << 16));
7766         I915_WRITE(VBLANK(cpu_transcoder),
7767                    (adjusted_mode->crtc_vblank_start - 1) |
7768                    ((crtc_vblank_end - 1) << 16));
7769         I915_WRITE(VSYNC(cpu_transcoder),
7770                    (adjusted_mode->crtc_vsync_start - 1) |
7771                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7772
7773         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7774          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7775          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7776          * bits. */
7777         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7778             (pipe == PIPE_B || pipe == PIPE_C))
7779                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7780
7781         /* pipesrc controls the size that is scaled from, which should
7782          * always be the user's requested size.
7783          */
7784         I915_WRITE(PIPESRC(pipe),
7785                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7786                    (intel_crtc->config->pipe_src_h - 1));
7787 }
7788
7789 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7790                                    struct intel_crtc_state *pipe_config)
7791 {
7792         struct drm_device *dev = crtc->base.dev;
7793         struct drm_i915_private *dev_priv = dev->dev_private;
7794         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7795         uint32_t tmp;
7796
7797         tmp = I915_READ(HTOTAL(cpu_transcoder));
7798         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7799         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7800         tmp = I915_READ(HBLANK(cpu_transcoder));
7801         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7802         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7803         tmp = I915_READ(HSYNC(cpu_transcoder));
7804         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7805         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7806
7807         tmp = I915_READ(VTOTAL(cpu_transcoder));
7808         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7809         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7810         tmp = I915_READ(VBLANK(cpu_transcoder));
7811         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7812         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7813         tmp = I915_READ(VSYNC(cpu_transcoder));
7814         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7815         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7816
7817         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7818                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7819                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7820                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7821         }
7822
7823         tmp = I915_READ(PIPESRC(crtc->pipe));
7824         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7825         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7826
7827         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7828         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7829 }
7830
7831 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7832                                  struct intel_crtc_state *pipe_config)
7833 {
7834         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7835         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7836         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7837         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7838
7839         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7840         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7841         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7842         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7843
7844         mode->flags = pipe_config->base.adjusted_mode.flags;
7845         mode->type = DRM_MODE_TYPE_DRIVER;
7846
7847         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7848         mode->flags |= pipe_config->base.adjusted_mode.flags;
7849
7850         mode->hsync = drm_mode_hsync(mode);
7851         mode->vrefresh = drm_mode_vrefresh(mode);
7852         drm_mode_set_name(mode);
7853 }
7854
7855 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7856 {
7857         struct drm_device *dev = intel_crtc->base.dev;
7858         struct drm_i915_private *dev_priv = dev->dev_private;
7859         uint32_t pipeconf;
7860
7861         pipeconf = 0;
7862
7863         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7864             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7865                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7866
7867         if (intel_crtc->config->double_wide)
7868                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7869
7870         /* only g4x and later have fancy bpc/dither controls */
7871         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7872                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7873                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7874                         pipeconf |= PIPECONF_DITHER_EN |
7875                                     PIPECONF_DITHER_TYPE_SP;
7876
7877                 switch (intel_crtc->config->pipe_bpp) {
7878                 case 18:
7879                         pipeconf |= PIPECONF_6BPC;
7880                         break;
7881                 case 24:
7882                         pipeconf |= PIPECONF_8BPC;
7883                         break;
7884                 case 30:
7885                         pipeconf |= PIPECONF_10BPC;
7886                         break;
7887                 default:
7888                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7889                         BUG();
7890                 }
7891         }
7892
7893         if (HAS_PIPE_CXSR(dev)) {
7894                 if (intel_crtc->lowfreq_avail) {
7895                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7896                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7897                 } else {
7898                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7899                 }
7900         }
7901
7902         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7903                 if (INTEL_INFO(dev)->gen < 4 ||
7904                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7905                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7906                 else
7907                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7908         } else
7909                 pipeconf |= PIPECONF_PROGRESSIVE;
7910
7911         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7912                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7913
7914         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7915         POSTING_READ(PIPECONF(intel_crtc->pipe));
7916 }
7917
7918 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7919                                    struct intel_crtc_state *crtc_state)
7920 {
7921         struct drm_device *dev = crtc->base.dev;
7922         struct drm_i915_private *dev_priv = dev->dev_private;
7923         int refclk, num_connectors = 0;
7924         intel_clock_t clock;
7925         bool ok;
7926         const intel_limit_t *limit;
7927         struct drm_atomic_state *state = crtc_state->base.state;
7928         struct drm_connector *connector;
7929         struct drm_connector_state *connector_state;
7930         int i;
7931
7932         memset(&crtc_state->dpll_hw_state, 0,
7933                sizeof(crtc_state->dpll_hw_state));
7934
7935         if (crtc_state->has_dsi_encoder)
7936                 return 0;
7937
7938         for_each_connector_in_state(state, connector, connector_state, i) {
7939                 if (connector_state->crtc == &crtc->base)
7940                         num_connectors++;
7941         }
7942
7943         if (!crtc_state->clock_set) {
7944                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7945
7946                 /*
7947                  * Returns a set of divisors for the desired target clock with
7948                  * the given refclk, or FALSE.  The returned values represent
7949                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7950                  * 2) / p1 / p2.
7951                  */
7952                 limit = intel_limit(crtc_state, refclk);
7953                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7954                                                  crtc_state->port_clock,
7955                                                  refclk, NULL, &clock);
7956                 if (!ok) {
7957                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7958                         return -EINVAL;
7959                 }
7960
7961                 /* Compat-code for transition, will disappear. */
7962                 crtc_state->dpll.n = clock.n;
7963                 crtc_state->dpll.m1 = clock.m1;
7964                 crtc_state->dpll.m2 = clock.m2;
7965                 crtc_state->dpll.p1 = clock.p1;
7966                 crtc_state->dpll.p2 = clock.p2;
7967         }
7968
7969         if (IS_GEN2(dev)) {
7970                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7971                                   num_connectors);
7972         } else if (IS_CHERRYVIEW(dev)) {
7973                 chv_compute_dpll(crtc, crtc_state);
7974         } else if (IS_VALLEYVIEW(dev)) {
7975                 vlv_compute_dpll(crtc, crtc_state);
7976         } else {
7977                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7978                                   num_connectors);
7979         }
7980
7981         return 0;
7982 }
7983
7984 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7985                                  struct intel_crtc_state *pipe_config)
7986 {
7987         struct drm_device *dev = crtc->base.dev;
7988         struct drm_i915_private *dev_priv = dev->dev_private;
7989         uint32_t tmp;
7990
7991         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7992                 return;
7993
7994         tmp = I915_READ(PFIT_CONTROL);
7995         if (!(tmp & PFIT_ENABLE))
7996                 return;
7997
7998         /* Check whether the pfit is attached to our pipe. */
7999         if (INTEL_INFO(dev)->gen < 4) {
8000                 if (crtc->pipe != PIPE_B)
8001                         return;
8002         } else {
8003                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8004                         return;
8005         }
8006
8007         pipe_config->gmch_pfit.control = tmp;
8008         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8009         if (INTEL_INFO(dev)->gen < 5)
8010                 pipe_config->gmch_pfit.lvds_border_bits =
8011                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8012 }
8013
8014 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8015                                struct intel_crtc_state *pipe_config)
8016 {
8017         struct drm_device *dev = crtc->base.dev;
8018         struct drm_i915_private *dev_priv = dev->dev_private;
8019         int pipe = pipe_config->cpu_transcoder;
8020         intel_clock_t clock;
8021         u32 mdiv;
8022         int refclk = 100000;
8023
8024         /* In case of MIPI DPLL will not even be used */
8025         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8026                 return;
8027
8028         mutex_lock(&dev_priv->sb_lock);
8029         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8030         mutex_unlock(&dev_priv->sb_lock);
8031
8032         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8033         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8034         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8035         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8036         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8037
8038         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8039 }
8040
8041 static void
8042 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8043                               struct intel_initial_plane_config *plane_config)
8044 {
8045         struct drm_device *dev = crtc->base.dev;
8046         struct drm_i915_private *dev_priv = dev->dev_private;
8047         u32 val, base, offset;
8048         int pipe = crtc->pipe, plane = crtc->plane;
8049         int fourcc, pixel_format;
8050         unsigned int aligned_height;
8051         struct drm_framebuffer *fb;
8052         struct intel_framebuffer *intel_fb;
8053
8054         val = I915_READ(DSPCNTR(plane));
8055         if (!(val & DISPLAY_PLANE_ENABLE))
8056                 return;
8057
8058         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8059         if (!intel_fb) {
8060                 DRM_DEBUG_KMS("failed to alloc fb\n");
8061                 return;
8062         }
8063
8064         fb = &intel_fb->base;
8065
8066         if (INTEL_INFO(dev)->gen >= 4) {
8067                 if (val & DISPPLANE_TILED) {
8068                         plane_config->tiling = I915_TILING_X;
8069                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8070                 }
8071         }
8072
8073         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8074         fourcc = i9xx_format_to_fourcc(pixel_format);
8075         fb->pixel_format = fourcc;
8076         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8077
8078         if (INTEL_INFO(dev)->gen >= 4) {
8079                 if (plane_config->tiling)
8080                         offset = I915_READ(DSPTILEOFF(plane));
8081                 else
8082                         offset = I915_READ(DSPLINOFF(plane));
8083                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8084         } else {
8085                 base = I915_READ(DSPADDR(plane));
8086         }
8087         plane_config->base = base;
8088
8089         val = I915_READ(PIPESRC(pipe));
8090         fb->width = ((val >> 16) & 0xfff) + 1;
8091         fb->height = ((val >> 0) & 0xfff) + 1;
8092
8093         val = I915_READ(DSPSTRIDE(pipe));
8094         fb->pitches[0] = val & 0xffffffc0;
8095
8096         aligned_height = intel_fb_align_height(dev, fb->height,
8097                                                fb->pixel_format,
8098                                                fb->modifier[0]);
8099
8100         plane_config->size = fb->pitches[0] * aligned_height;
8101
8102         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8103                       pipe_name(pipe), plane, fb->width, fb->height,
8104                       fb->bits_per_pixel, base, fb->pitches[0],
8105                       plane_config->size);
8106
8107         plane_config->fb = intel_fb;
8108 }
8109
8110 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8111                                struct intel_crtc_state *pipe_config)
8112 {
8113         struct drm_device *dev = crtc->base.dev;
8114         struct drm_i915_private *dev_priv = dev->dev_private;
8115         int pipe = pipe_config->cpu_transcoder;
8116         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8117         intel_clock_t clock;
8118         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8119         int refclk = 100000;
8120
8121         mutex_lock(&dev_priv->sb_lock);
8122         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8123         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8124         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8125         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8126         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8127         mutex_unlock(&dev_priv->sb_lock);
8128
8129         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8130         clock.m2 = (pll_dw0 & 0xff) << 22;
8131         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8132                 clock.m2 |= pll_dw2 & 0x3fffff;
8133         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8134         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8135         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8136
8137         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8138 }
8139
8140 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8141                                  struct intel_crtc_state *pipe_config)
8142 {
8143         struct drm_device *dev = crtc->base.dev;
8144         struct drm_i915_private *dev_priv = dev->dev_private;
8145         uint32_t tmp;
8146
8147         if (!intel_display_power_is_enabled(dev_priv,
8148                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8149                 return false;
8150
8151         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8152         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8153
8154         tmp = I915_READ(PIPECONF(crtc->pipe));
8155         if (!(tmp & PIPECONF_ENABLE))
8156                 return false;
8157
8158         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8159                 switch (tmp & PIPECONF_BPC_MASK) {
8160                 case PIPECONF_6BPC:
8161                         pipe_config->pipe_bpp = 18;
8162                         break;
8163                 case PIPECONF_8BPC:
8164                         pipe_config->pipe_bpp = 24;
8165                         break;
8166                 case PIPECONF_10BPC:
8167                         pipe_config->pipe_bpp = 30;
8168                         break;
8169                 default:
8170                         break;
8171                 }
8172         }
8173
8174         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8175                 pipe_config->limited_color_range = true;
8176
8177         if (INTEL_INFO(dev)->gen < 4)
8178                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8179
8180         intel_get_pipe_timings(crtc, pipe_config);
8181
8182         i9xx_get_pfit_config(crtc, pipe_config);
8183
8184         if (INTEL_INFO(dev)->gen >= 4) {
8185                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8186                 pipe_config->pixel_multiplier =
8187                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8188                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8189                 pipe_config->dpll_hw_state.dpll_md = tmp;
8190         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8191                 tmp = I915_READ(DPLL(crtc->pipe));
8192                 pipe_config->pixel_multiplier =
8193                         ((tmp & SDVO_MULTIPLIER_MASK)
8194                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8195         } else {
8196                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8197                  * port and will be fixed up in the encoder->get_config
8198                  * function. */
8199                 pipe_config->pixel_multiplier = 1;
8200         }
8201         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8202         if (!IS_VALLEYVIEW(dev)) {
8203                 /*
8204                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8205                  * on 830. Filter it out here so that we don't
8206                  * report errors due to that.
8207                  */
8208                 if (IS_I830(dev))
8209                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8210
8211                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8212                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8213         } else {
8214                 /* Mask out read-only status bits. */
8215                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8216                                                      DPLL_PORTC_READY_MASK |
8217                                                      DPLL_PORTB_READY_MASK);
8218         }
8219
8220         if (IS_CHERRYVIEW(dev))
8221                 chv_crtc_clock_get(crtc, pipe_config);
8222         else if (IS_VALLEYVIEW(dev))
8223                 vlv_crtc_clock_get(crtc, pipe_config);
8224         else
8225                 i9xx_crtc_clock_get(crtc, pipe_config);
8226
8227         /*
8228          * Normally the dotclock is filled in by the encoder .get_config()
8229          * but in case the pipe is enabled w/o any ports we need a sane
8230          * default.
8231          */
8232         pipe_config->base.adjusted_mode.crtc_clock =
8233                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8234
8235         return true;
8236 }
8237
8238 static void ironlake_init_pch_refclk(struct drm_device *dev)
8239 {
8240         struct drm_i915_private *dev_priv = dev->dev_private;
8241         struct intel_encoder *encoder;
8242         u32 val, final;
8243         bool has_lvds = false;
8244         bool has_cpu_edp = false;
8245         bool has_panel = false;
8246         bool has_ck505 = false;
8247         bool can_ssc = false;
8248
8249         /* We need to take the global config into account */
8250         for_each_intel_encoder(dev, encoder) {
8251                 switch (encoder->type) {
8252                 case INTEL_OUTPUT_LVDS:
8253                         has_panel = true;
8254                         has_lvds = true;
8255                         break;
8256                 case INTEL_OUTPUT_EDP:
8257                         has_panel = true;
8258                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8259                                 has_cpu_edp = true;
8260                         break;
8261                 default:
8262                         break;
8263                 }
8264         }
8265
8266         if (HAS_PCH_IBX(dev)) {
8267                 has_ck505 = dev_priv->vbt.display_clock_mode;
8268                 can_ssc = has_ck505;
8269         } else {
8270                 has_ck505 = false;
8271                 can_ssc = true;
8272         }
8273
8274         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8275                       has_panel, has_lvds, has_ck505);
8276
8277         /* Ironlake: try to setup display ref clock before DPLL
8278          * enabling. This is only under driver's control after
8279          * PCH B stepping, previous chipset stepping should be
8280          * ignoring this setting.
8281          */
8282         val = I915_READ(PCH_DREF_CONTROL);
8283
8284         /* As we must carefully and slowly disable/enable each source in turn,
8285          * compute the final state we want first and check if we need to
8286          * make any changes at all.
8287          */
8288         final = val;
8289         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8290         if (has_ck505)
8291                 final |= DREF_NONSPREAD_CK505_ENABLE;
8292         else
8293                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8294
8295         final &= ~DREF_SSC_SOURCE_MASK;
8296         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8297         final &= ~DREF_SSC1_ENABLE;
8298
8299         if (has_panel) {
8300                 final |= DREF_SSC_SOURCE_ENABLE;
8301
8302                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8303                         final |= DREF_SSC1_ENABLE;
8304
8305                 if (has_cpu_edp) {
8306                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8307                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8308                         else
8309                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8310                 } else
8311                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8312         } else {
8313                 final |= DREF_SSC_SOURCE_DISABLE;
8314                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8315         }
8316
8317         if (final == val)
8318                 return;
8319
8320         /* Always enable nonspread source */
8321         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8322
8323         if (has_ck505)
8324                 val |= DREF_NONSPREAD_CK505_ENABLE;
8325         else
8326                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8327
8328         if (has_panel) {
8329                 val &= ~DREF_SSC_SOURCE_MASK;
8330                 val |= DREF_SSC_SOURCE_ENABLE;
8331
8332                 /* SSC must be turned on before enabling the CPU output  */
8333                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8334                         DRM_DEBUG_KMS("Using SSC on panel\n");
8335                         val |= DREF_SSC1_ENABLE;
8336                 } else
8337                         val &= ~DREF_SSC1_ENABLE;
8338
8339                 /* Get SSC going before enabling the outputs */
8340                 I915_WRITE(PCH_DREF_CONTROL, val);
8341                 POSTING_READ(PCH_DREF_CONTROL);
8342                 udelay(200);
8343
8344                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8345
8346                 /* Enable CPU source on CPU attached eDP */
8347                 if (has_cpu_edp) {
8348                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8349                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8350                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8351                         } else
8352                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8353                 } else
8354                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8355
8356                 I915_WRITE(PCH_DREF_CONTROL, val);
8357                 POSTING_READ(PCH_DREF_CONTROL);
8358                 udelay(200);
8359         } else {
8360                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8361
8362                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8363
8364                 /* Turn off CPU output */
8365                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8366
8367                 I915_WRITE(PCH_DREF_CONTROL, val);
8368                 POSTING_READ(PCH_DREF_CONTROL);
8369                 udelay(200);
8370
8371                 /* Turn off the SSC source */
8372                 val &= ~DREF_SSC_SOURCE_MASK;
8373                 val |= DREF_SSC_SOURCE_DISABLE;
8374
8375                 /* Turn off SSC1 */
8376                 val &= ~DREF_SSC1_ENABLE;
8377
8378                 I915_WRITE(PCH_DREF_CONTROL, val);
8379                 POSTING_READ(PCH_DREF_CONTROL);
8380                 udelay(200);
8381         }
8382
8383         BUG_ON(val != final);
8384 }
8385
8386 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8387 {
8388         uint32_t tmp;
8389
8390         tmp = I915_READ(SOUTH_CHICKEN2);
8391         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8392         I915_WRITE(SOUTH_CHICKEN2, tmp);
8393
8394         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8395                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8396                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8397
8398         tmp = I915_READ(SOUTH_CHICKEN2);
8399         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8400         I915_WRITE(SOUTH_CHICKEN2, tmp);
8401
8402         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8403                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8404                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8405 }
8406
8407 /* WaMPhyProgramming:hsw */
8408 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8409 {
8410         uint32_t tmp;
8411
8412         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8413         tmp &= ~(0xFF << 24);
8414         tmp |= (0x12 << 24);
8415         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8416
8417         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8418         tmp |= (1 << 11);
8419         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8420
8421         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8422         tmp |= (1 << 11);
8423         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8424
8425         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8426         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8427         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8428
8429         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8430         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8431         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8432
8433         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8434         tmp &= ~(7 << 13);
8435         tmp |= (5 << 13);
8436         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8437
8438         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8439         tmp &= ~(7 << 13);
8440         tmp |= (5 << 13);
8441         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8442
8443         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8444         tmp &= ~0xFF;
8445         tmp |= 0x1C;
8446         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8447
8448         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8449         tmp &= ~0xFF;
8450         tmp |= 0x1C;
8451         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8452
8453         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8454         tmp &= ~(0xFF << 16);
8455         tmp |= (0x1C << 16);
8456         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8457
8458         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8459         tmp &= ~(0xFF << 16);
8460         tmp |= (0x1C << 16);
8461         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8462
8463         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8464         tmp |= (1 << 27);
8465         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8466
8467         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8468         tmp |= (1 << 27);
8469         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8470
8471         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8472         tmp &= ~(0xF << 28);
8473         tmp |= (4 << 28);
8474         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8475
8476         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8477         tmp &= ~(0xF << 28);
8478         tmp |= (4 << 28);
8479         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8480 }
8481
8482 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8483  * Programming" based on the parameters passed:
8484  * - Sequence to enable CLKOUT_DP
8485  * - Sequence to enable CLKOUT_DP without spread
8486  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8487  */
8488 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8489                                  bool with_fdi)
8490 {
8491         struct drm_i915_private *dev_priv = dev->dev_private;
8492         uint32_t reg, tmp;
8493
8494         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8495                 with_spread = true;
8496         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8497                 with_fdi = false;
8498
8499         mutex_lock(&dev_priv->sb_lock);
8500
8501         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8502         tmp &= ~SBI_SSCCTL_DISABLE;
8503         tmp |= SBI_SSCCTL_PATHALT;
8504         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8505
8506         udelay(24);
8507
8508         if (with_spread) {
8509                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8510                 tmp &= ~SBI_SSCCTL_PATHALT;
8511                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8512
8513                 if (with_fdi) {
8514                         lpt_reset_fdi_mphy(dev_priv);
8515                         lpt_program_fdi_mphy(dev_priv);
8516                 }
8517         }
8518
8519         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8520         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8521         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8522         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8523
8524         mutex_unlock(&dev_priv->sb_lock);
8525 }
8526
8527 /* Sequence to disable CLKOUT_DP */
8528 static void lpt_disable_clkout_dp(struct drm_device *dev)
8529 {
8530         struct drm_i915_private *dev_priv = dev->dev_private;
8531         uint32_t reg, tmp;
8532
8533         mutex_lock(&dev_priv->sb_lock);
8534
8535         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8536         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8537         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8538         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8539
8540         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8541         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8542                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8543                         tmp |= SBI_SSCCTL_PATHALT;
8544                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8545                         udelay(32);
8546                 }
8547                 tmp |= SBI_SSCCTL_DISABLE;
8548                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8549         }
8550
8551         mutex_unlock(&dev_priv->sb_lock);
8552 }
8553
8554 static void lpt_init_pch_refclk(struct drm_device *dev)
8555 {
8556         struct intel_encoder *encoder;
8557         bool has_vga = false;
8558
8559         for_each_intel_encoder(dev, encoder) {
8560                 switch (encoder->type) {
8561                 case INTEL_OUTPUT_ANALOG:
8562                         has_vga = true;
8563                         break;
8564                 default:
8565                         break;
8566                 }
8567         }
8568
8569         if (has_vga)
8570                 lpt_enable_clkout_dp(dev, true, true);
8571         else
8572                 lpt_disable_clkout_dp(dev);
8573 }
8574
8575 /*
8576  * Initialize reference clocks when the driver loads
8577  */
8578 void intel_init_pch_refclk(struct drm_device *dev)
8579 {
8580         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8581                 ironlake_init_pch_refclk(dev);
8582         else if (HAS_PCH_LPT(dev))
8583                 lpt_init_pch_refclk(dev);
8584 }
8585
8586 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8587 {
8588         struct drm_device *dev = crtc_state->base.crtc->dev;
8589         struct drm_i915_private *dev_priv = dev->dev_private;
8590         struct drm_atomic_state *state = crtc_state->base.state;
8591         struct drm_connector *connector;
8592         struct drm_connector_state *connector_state;
8593         struct intel_encoder *encoder;
8594         int num_connectors = 0, i;
8595         bool is_lvds = false;
8596
8597         for_each_connector_in_state(state, connector, connector_state, i) {
8598                 if (connector_state->crtc != crtc_state->base.crtc)
8599                         continue;
8600
8601                 encoder = to_intel_encoder(connector_state->best_encoder);
8602
8603                 switch (encoder->type) {
8604                 case INTEL_OUTPUT_LVDS:
8605                         is_lvds = true;
8606                         break;
8607                 default:
8608                         break;
8609                 }
8610                 num_connectors++;
8611         }
8612
8613         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8614                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8615                               dev_priv->vbt.lvds_ssc_freq);
8616                 return dev_priv->vbt.lvds_ssc_freq;
8617         }
8618
8619         return 120000;
8620 }
8621
8622 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8623 {
8624         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8626         int pipe = intel_crtc->pipe;
8627         uint32_t val;
8628
8629         val = 0;
8630
8631         switch (intel_crtc->config->pipe_bpp) {
8632         case 18:
8633                 val |= PIPECONF_6BPC;
8634                 break;
8635         case 24:
8636                 val |= PIPECONF_8BPC;
8637                 break;
8638         case 30:
8639                 val |= PIPECONF_10BPC;
8640                 break;
8641         case 36:
8642                 val |= PIPECONF_12BPC;
8643                 break;
8644         default:
8645                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8646                 BUG();
8647         }
8648
8649         if (intel_crtc->config->dither)
8650                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8651
8652         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8653                 val |= PIPECONF_INTERLACED_ILK;
8654         else
8655                 val |= PIPECONF_PROGRESSIVE;
8656
8657         if (intel_crtc->config->limited_color_range)
8658                 val |= PIPECONF_COLOR_RANGE_SELECT;
8659
8660         I915_WRITE(PIPECONF(pipe), val);
8661         POSTING_READ(PIPECONF(pipe));
8662 }
8663
8664 /*
8665  * Set up the pipe CSC unit.
8666  *
8667  * Currently only full range RGB to limited range RGB conversion
8668  * is supported, but eventually this should handle various
8669  * RGB<->YCbCr scenarios as well.
8670  */
8671 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8672 {
8673         struct drm_device *dev = crtc->dev;
8674         struct drm_i915_private *dev_priv = dev->dev_private;
8675         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8676         int pipe = intel_crtc->pipe;
8677         uint16_t coeff = 0x7800; /* 1.0 */
8678
8679         /*
8680          * TODO: Check what kind of values actually come out of the pipe
8681          * with these coeff/postoff values and adjust to get the best
8682          * accuracy. Perhaps we even need to take the bpc value into
8683          * consideration.
8684          */
8685
8686         if (intel_crtc->config->limited_color_range)
8687                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8688
8689         /*
8690          * GY/GU and RY/RU should be the other way around according
8691          * to BSpec, but reality doesn't agree. Just set them up in
8692          * a way that results in the correct picture.
8693          */
8694         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8695         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8696
8697         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8698         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8699
8700         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8701         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8702
8703         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8704         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8705         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8706
8707         if (INTEL_INFO(dev)->gen > 6) {
8708                 uint16_t postoff = 0;
8709
8710                 if (intel_crtc->config->limited_color_range)
8711                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8712
8713                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8714                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8715                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8716
8717                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8718         } else {
8719                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8720
8721                 if (intel_crtc->config->limited_color_range)
8722                         mode |= CSC_BLACK_SCREEN_OFFSET;
8723
8724                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8725         }
8726 }
8727
8728 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8729 {
8730         struct drm_device *dev = crtc->dev;
8731         struct drm_i915_private *dev_priv = dev->dev_private;
8732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8733         enum pipe pipe = intel_crtc->pipe;
8734         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8735         uint32_t val;
8736
8737         val = 0;
8738
8739         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8740                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8741
8742         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8743                 val |= PIPECONF_INTERLACED_ILK;
8744         else
8745                 val |= PIPECONF_PROGRESSIVE;
8746
8747         I915_WRITE(PIPECONF(cpu_transcoder), val);
8748         POSTING_READ(PIPECONF(cpu_transcoder));
8749
8750         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8751         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8752
8753         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8754                 val = 0;
8755
8756                 switch (intel_crtc->config->pipe_bpp) {
8757                 case 18:
8758                         val |= PIPEMISC_DITHER_6_BPC;
8759                         break;
8760                 case 24:
8761                         val |= PIPEMISC_DITHER_8_BPC;
8762                         break;
8763                 case 30:
8764                         val |= PIPEMISC_DITHER_10_BPC;
8765                         break;
8766                 case 36:
8767                         val |= PIPEMISC_DITHER_12_BPC;
8768                         break;
8769                 default:
8770                         /* Case prevented by pipe_config_set_bpp. */
8771                         BUG();
8772                 }
8773
8774                 if (intel_crtc->config->dither)
8775                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8776
8777                 I915_WRITE(PIPEMISC(pipe), val);
8778         }
8779 }
8780
8781 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8782                                     struct intel_crtc_state *crtc_state,
8783                                     intel_clock_t *clock,
8784                                     bool *has_reduced_clock,
8785                                     intel_clock_t *reduced_clock)
8786 {
8787         struct drm_device *dev = crtc->dev;
8788         struct drm_i915_private *dev_priv = dev->dev_private;
8789         int refclk;
8790         const intel_limit_t *limit;
8791         bool ret;
8792
8793         refclk = ironlake_get_refclk(crtc_state);
8794
8795         /*
8796          * Returns a set of divisors for the desired target clock with the given
8797          * refclk, or FALSE.  The returned values represent the clock equation:
8798          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8799          */
8800         limit = intel_limit(crtc_state, refclk);
8801         ret = dev_priv->display.find_dpll(limit, crtc_state,
8802                                           crtc_state->port_clock,
8803                                           refclk, NULL, clock);
8804         if (!ret)
8805                 return false;
8806
8807         return true;
8808 }
8809
8810 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8811 {
8812         /*
8813          * Account for spread spectrum to avoid
8814          * oversubscribing the link. Max center spread
8815          * is 2.5%; use 5% for safety's sake.
8816          */
8817         u32 bps = target_clock * bpp * 21 / 20;
8818         return DIV_ROUND_UP(bps, link_bw * 8);
8819 }
8820
8821 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8822 {
8823         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8824 }
8825
8826 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8827                                       struct intel_crtc_state *crtc_state,
8828                                       u32 *fp,
8829                                       intel_clock_t *reduced_clock, u32 *fp2)
8830 {
8831         struct drm_crtc *crtc = &intel_crtc->base;
8832         struct drm_device *dev = crtc->dev;
8833         struct drm_i915_private *dev_priv = dev->dev_private;
8834         struct drm_atomic_state *state = crtc_state->base.state;
8835         struct drm_connector *connector;
8836         struct drm_connector_state *connector_state;
8837         struct intel_encoder *encoder;
8838         uint32_t dpll;
8839         int factor, num_connectors = 0, i;
8840         bool is_lvds = false, is_sdvo = false;
8841
8842         for_each_connector_in_state(state, connector, connector_state, i) {
8843                 if (connector_state->crtc != crtc_state->base.crtc)
8844                         continue;
8845
8846                 encoder = to_intel_encoder(connector_state->best_encoder);
8847
8848                 switch (encoder->type) {
8849                 case INTEL_OUTPUT_LVDS:
8850                         is_lvds = true;
8851                         break;
8852                 case INTEL_OUTPUT_SDVO:
8853                 case INTEL_OUTPUT_HDMI:
8854                         is_sdvo = true;
8855                         break;
8856                 default:
8857                         break;
8858                 }
8859
8860                 num_connectors++;
8861         }
8862
8863         /* Enable autotuning of the PLL clock (if permissible) */
8864         factor = 21;
8865         if (is_lvds) {
8866                 if ((intel_panel_use_ssc(dev_priv) &&
8867                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8868                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8869                         factor = 25;
8870         } else if (crtc_state->sdvo_tv_clock)
8871                 factor = 20;
8872
8873         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8874                 *fp |= FP_CB_TUNE;
8875
8876         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8877                 *fp2 |= FP_CB_TUNE;
8878
8879         dpll = 0;
8880
8881         if (is_lvds)
8882                 dpll |= DPLLB_MODE_LVDS;
8883         else
8884                 dpll |= DPLLB_MODE_DAC_SERIAL;
8885
8886         dpll |= (crtc_state->pixel_multiplier - 1)
8887                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8888
8889         if (is_sdvo)
8890                 dpll |= DPLL_SDVO_HIGH_SPEED;
8891         if (crtc_state->has_dp_encoder)
8892                 dpll |= DPLL_SDVO_HIGH_SPEED;
8893
8894         /* compute bitmask from p1 value */
8895         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8896         /* also FPA1 */
8897         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8898
8899         switch (crtc_state->dpll.p2) {
8900         case 5:
8901                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8902                 break;
8903         case 7:
8904                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8905                 break;
8906         case 10:
8907                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8908                 break;
8909         case 14:
8910                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8911                 break;
8912         }
8913
8914         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8915                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8916         else
8917                 dpll |= PLL_REF_INPUT_DREFCLK;
8918
8919         return dpll | DPLL_VCO_ENABLE;
8920 }
8921
8922 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8923                                        struct intel_crtc_state *crtc_state)
8924 {
8925         struct drm_device *dev = crtc->base.dev;
8926         intel_clock_t clock, reduced_clock;
8927         u32 dpll = 0, fp = 0, fp2 = 0;
8928         bool ok, has_reduced_clock = false;
8929         bool is_lvds = false;
8930         struct intel_shared_dpll *pll;
8931
8932         memset(&crtc_state->dpll_hw_state, 0,
8933                sizeof(crtc_state->dpll_hw_state));
8934
8935         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8936
8937         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8938              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8939
8940         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8941                                      &has_reduced_clock, &reduced_clock);
8942         if (!ok && !crtc_state->clock_set) {
8943                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8944                 return -EINVAL;
8945         }
8946         /* Compat-code for transition, will disappear. */
8947         if (!crtc_state->clock_set) {
8948                 crtc_state->dpll.n = clock.n;
8949                 crtc_state->dpll.m1 = clock.m1;
8950                 crtc_state->dpll.m2 = clock.m2;
8951                 crtc_state->dpll.p1 = clock.p1;
8952                 crtc_state->dpll.p2 = clock.p2;
8953         }
8954
8955         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8956         if (crtc_state->has_pch_encoder) {
8957                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8958                 if (has_reduced_clock)
8959                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8960
8961                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8962                                              &fp, &reduced_clock,
8963                                              has_reduced_clock ? &fp2 : NULL);
8964
8965                 crtc_state->dpll_hw_state.dpll = dpll;
8966                 crtc_state->dpll_hw_state.fp0 = fp;
8967                 if (has_reduced_clock)
8968                         crtc_state->dpll_hw_state.fp1 = fp2;
8969                 else
8970                         crtc_state->dpll_hw_state.fp1 = fp;
8971
8972                 pll = intel_get_shared_dpll(crtc, crtc_state);
8973                 if (pll == NULL) {
8974                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8975                                          pipe_name(crtc->pipe));
8976                         return -EINVAL;
8977                 }
8978         }
8979
8980         if (is_lvds && has_reduced_clock)
8981                 crtc->lowfreq_avail = true;
8982         else
8983                 crtc->lowfreq_avail = false;
8984
8985         return 0;
8986 }
8987
8988 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8989                                          struct intel_link_m_n *m_n)
8990 {
8991         struct drm_device *dev = crtc->base.dev;
8992         struct drm_i915_private *dev_priv = dev->dev_private;
8993         enum pipe pipe = crtc->pipe;
8994
8995         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8996         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8997         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8998                 & ~TU_SIZE_MASK;
8999         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9000         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9001                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9002 }
9003
9004 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9005                                          enum transcoder transcoder,
9006                                          struct intel_link_m_n *m_n,
9007                                          struct intel_link_m_n *m2_n2)
9008 {
9009         struct drm_device *dev = crtc->base.dev;
9010         struct drm_i915_private *dev_priv = dev->dev_private;
9011         enum pipe pipe = crtc->pipe;
9012
9013         if (INTEL_INFO(dev)->gen >= 5) {
9014                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9015                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9016                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9017                         & ~TU_SIZE_MASK;
9018                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9019                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9020                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9021                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9022                  * gen < 8) and if DRRS is supported (to make sure the
9023                  * registers are not unnecessarily read).
9024                  */
9025                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9026                         crtc->config->has_drrs) {
9027                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9028                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9029                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9030                                         & ~TU_SIZE_MASK;
9031                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9032                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9033                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9034                 }
9035         } else {
9036                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9037                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9038                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9039                         & ~TU_SIZE_MASK;
9040                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9041                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9042                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9043         }
9044 }
9045
9046 void intel_dp_get_m_n(struct intel_crtc *crtc,
9047                       struct intel_crtc_state *pipe_config)
9048 {
9049         if (pipe_config->has_pch_encoder)
9050                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9051         else
9052                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9053                                              &pipe_config->dp_m_n,
9054                                              &pipe_config->dp_m2_n2);
9055 }
9056
9057 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9058                                         struct intel_crtc_state *pipe_config)
9059 {
9060         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9061                                      &pipe_config->fdi_m_n, NULL);
9062 }
9063
9064 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9065                                     struct intel_crtc_state *pipe_config)
9066 {
9067         struct drm_device *dev = crtc->base.dev;
9068         struct drm_i915_private *dev_priv = dev->dev_private;
9069         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9070         uint32_t ps_ctrl = 0;
9071         int id = -1;
9072         int i;
9073
9074         /* find scaler attached to this pipe */
9075         for (i = 0; i < crtc->num_scalers; i++) {
9076                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9077                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9078                         id = i;
9079                         pipe_config->pch_pfit.enabled = true;
9080                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9081                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9082                         break;
9083                 }
9084         }
9085
9086         scaler_state->scaler_id = id;
9087         if (id >= 0) {
9088                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9089         } else {
9090                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9091         }
9092 }
9093
9094 static void
9095 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9096                                  struct intel_initial_plane_config *plane_config)
9097 {
9098         struct drm_device *dev = crtc->base.dev;
9099         struct drm_i915_private *dev_priv = dev->dev_private;
9100         u32 val, base, offset, stride_mult, tiling;
9101         int pipe = crtc->pipe;
9102         int fourcc, pixel_format;
9103         unsigned int aligned_height;
9104         struct drm_framebuffer *fb;
9105         struct intel_framebuffer *intel_fb;
9106
9107         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9108         if (!intel_fb) {
9109                 DRM_DEBUG_KMS("failed to alloc fb\n");
9110                 return;
9111         }
9112
9113         fb = &intel_fb->base;
9114
9115         val = I915_READ(PLANE_CTL(pipe, 0));
9116         if (!(val & PLANE_CTL_ENABLE))
9117                 goto error;
9118
9119         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9120         fourcc = skl_format_to_fourcc(pixel_format,
9121                                       val & PLANE_CTL_ORDER_RGBX,
9122                                       val & PLANE_CTL_ALPHA_MASK);
9123         fb->pixel_format = fourcc;
9124         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9125
9126         tiling = val & PLANE_CTL_TILED_MASK;
9127         switch (tiling) {
9128         case PLANE_CTL_TILED_LINEAR:
9129                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9130                 break;
9131         case PLANE_CTL_TILED_X:
9132                 plane_config->tiling = I915_TILING_X;
9133                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9134                 break;
9135         case PLANE_CTL_TILED_Y:
9136                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9137                 break;
9138         case PLANE_CTL_TILED_YF:
9139                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9140                 break;
9141         default:
9142                 MISSING_CASE(tiling);
9143                 goto error;
9144         }
9145
9146         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9147         plane_config->base = base;
9148
9149         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9150
9151         val = I915_READ(PLANE_SIZE(pipe, 0));
9152         fb->height = ((val >> 16) & 0xfff) + 1;
9153         fb->width = ((val >> 0) & 0x1fff) + 1;
9154
9155         val = I915_READ(PLANE_STRIDE(pipe, 0));
9156         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9157                                                 fb->pixel_format);
9158         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9159
9160         aligned_height = intel_fb_align_height(dev, fb->height,
9161                                                fb->pixel_format,
9162                                                fb->modifier[0]);
9163
9164         plane_config->size = fb->pitches[0] * aligned_height;
9165
9166         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9167                       pipe_name(pipe), fb->width, fb->height,
9168                       fb->bits_per_pixel, base, fb->pitches[0],
9169                       plane_config->size);
9170
9171         plane_config->fb = intel_fb;
9172         return;
9173
9174 error:
9175         kfree(fb);
9176 }
9177
9178 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9179                                      struct intel_crtc_state *pipe_config)
9180 {
9181         struct drm_device *dev = crtc->base.dev;
9182         struct drm_i915_private *dev_priv = dev->dev_private;
9183         uint32_t tmp;
9184
9185         tmp = I915_READ(PF_CTL(crtc->pipe));
9186
9187         if (tmp & PF_ENABLE) {
9188                 pipe_config->pch_pfit.enabled = true;
9189                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9190                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9191
9192                 /* We currently do not free assignements of panel fitters on
9193                  * ivb/hsw (since we don't use the higher upscaling modes which
9194                  * differentiates them) so just WARN about this case for now. */
9195                 if (IS_GEN7(dev)) {
9196                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9197                                 PF_PIPE_SEL_IVB(crtc->pipe));
9198                 }
9199         }
9200 }
9201
9202 static void
9203 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9204                                   struct intel_initial_plane_config *plane_config)
9205 {
9206         struct drm_device *dev = crtc->base.dev;
9207         struct drm_i915_private *dev_priv = dev->dev_private;
9208         u32 val, base, offset;
9209         int pipe = crtc->pipe;
9210         int fourcc, pixel_format;
9211         unsigned int aligned_height;
9212         struct drm_framebuffer *fb;
9213         struct intel_framebuffer *intel_fb;
9214
9215         val = I915_READ(DSPCNTR(pipe));
9216         if (!(val & DISPLAY_PLANE_ENABLE))
9217                 return;
9218
9219         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9220         if (!intel_fb) {
9221                 DRM_DEBUG_KMS("failed to alloc fb\n");
9222                 return;
9223         }
9224
9225         fb = &intel_fb->base;
9226
9227         if (INTEL_INFO(dev)->gen >= 4) {
9228                 if (val & DISPPLANE_TILED) {
9229                         plane_config->tiling = I915_TILING_X;
9230                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9231                 }
9232         }
9233
9234         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9235         fourcc = i9xx_format_to_fourcc(pixel_format);
9236         fb->pixel_format = fourcc;
9237         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9238
9239         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9240         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9241                 offset = I915_READ(DSPOFFSET(pipe));
9242         } else {
9243                 if (plane_config->tiling)
9244                         offset = I915_READ(DSPTILEOFF(pipe));
9245                 else
9246                         offset = I915_READ(DSPLINOFF(pipe));
9247         }
9248         plane_config->base = base;
9249
9250         val = I915_READ(PIPESRC(pipe));
9251         fb->width = ((val >> 16) & 0xfff) + 1;
9252         fb->height = ((val >> 0) & 0xfff) + 1;
9253
9254         val = I915_READ(DSPSTRIDE(pipe));
9255         fb->pitches[0] = val & 0xffffffc0;
9256
9257         aligned_height = intel_fb_align_height(dev, fb->height,
9258                                                fb->pixel_format,
9259                                                fb->modifier[0]);
9260
9261         plane_config->size = fb->pitches[0] * aligned_height;
9262
9263         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9264                       pipe_name(pipe), fb->width, fb->height,
9265                       fb->bits_per_pixel, base, fb->pitches[0],
9266                       plane_config->size);
9267
9268         plane_config->fb = intel_fb;
9269 }
9270
9271 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9272                                      struct intel_crtc_state *pipe_config)
9273 {
9274         struct drm_device *dev = crtc->base.dev;
9275         struct drm_i915_private *dev_priv = dev->dev_private;
9276         uint32_t tmp;
9277
9278         if (!intel_display_power_is_enabled(dev_priv,
9279                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9280                 return false;
9281
9282         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9283         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9284
9285         tmp = I915_READ(PIPECONF(crtc->pipe));
9286         if (!(tmp & PIPECONF_ENABLE))
9287                 return false;
9288
9289         switch (tmp & PIPECONF_BPC_MASK) {
9290         case PIPECONF_6BPC:
9291                 pipe_config->pipe_bpp = 18;
9292                 break;
9293         case PIPECONF_8BPC:
9294                 pipe_config->pipe_bpp = 24;
9295                 break;
9296         case PIPECONF_10BPC:
9297                 pipe_config->pipe_bpp = 30;
9298                 break;
9299         case PIPECONF_12BPC:
9300                 pipe_config->pipe_bpp = 36;
9301                 break;
9302         default:
9303                 break;
9304         }
9305
9306         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9307                 pipe_config->limited_color_range = true;
9308
9309         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9310                 struct intel_shared_dpll *pll;
9311
9312                 pipe_config->has_pch_encoder = true;
9313
9314                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9315                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9316                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9317
9318                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9319
9320                 if (HAS_PCH_IBX(dev_priv->dev)) {
9321                         pipe_config->shared_dpll =
9322                                 (enum intel_dpll_id) crtc->pipe;
9323                 } else {
9324                         tmp = I915_READ(PCH_DPLL_SEL);
9325                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9326                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9327                         else
9328                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9329                 }
9330
9331                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9332
9333                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9334                                            &pipe_config->dpll_hw_state));
9335
9336                 tmp = pipe_config->dpll_hw_state.dpll;
9337                 pipe_config->pixel_multiplier =
9338                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9339                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9340
9341                 ironlake_pch_clock_get(crtc, pipe_config);
9342         } else {
9343                 pipe_config->pixel_multiplier = 1;
9344         }
9345
9346         intel_get_pipe_timings(crtc, pipe_config);
9347
9348         ironlake_get_pfit_config(crtc, pipe_config);
9349
9350         return true;
9351 }
9352
9353 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9354 {
9355         struct drm_device *dev = dev_priv->dev;
9356         struct intel_crtc *crtc;
9357
9358         for_each_intel_crtc(dev, crtc)
9359                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9360                      pipe_name(crtc->pipe));
9361
9362         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9363         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9364         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9365         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9366         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9367         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9368              "CPU PWM1 enabled\n");
9369         if (IS_HASWELL(dev))
9370                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9371                      "CPU PWM2 enabled\n");
9372         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9373              "PCH PWM1 enabled\n");
9374         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9375              "Utility pin enabled\n");
9376         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9377
9378         /*
9379          * In theory we can still leave IRQs enabled, as long as only the HPD
9380          * interrupts remain enabled. We used to check for that, but since it's
9381          * gen-specific and since we only disable LCPLL after we fully disable
9382          * the interrupts, the check below should be enough.
9383          */
9384         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9385 }
9386
9387 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9388 {
9389         struct drm_device *dev = dev_priv->dev;
9390
9391         if (IS_HASWELL(dev))
9392                 return I915_READ(D_COMP_HSW);
9393         else
9394                 return I915_READ(D_COMP_BDW);
9395 }
9396
9397 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9398 {
9399         struct drm_device *dev = dev_priv->dev;
9400
9401         if (IS_HASWELL(dev)) {
9402                 mutex_lock(&dev_priv->rps.hw_lock);
9403                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9404                                             val))
9405                         DRM_ERROR("Failed to write to D_COMP\n");
9406                 mutex_unlock(&dev_priv->rps.hw_lock);
9407         } else {
9408                 I915_WRITE(D_COMP_BDW, val);
9409                 POSTING_READ(D_COMP_BDW);
9410         }
9411 }
9412
9413 /*
9414  * This function implements pieces of two sequences from BSpec:
9415  * - Sequence for display software to disable LCPLL
9416  * - Sequence for display software to allow package C8+
9417  * The steps implemented here are just the steps that actually touch the LCPLL
9418  * register. Callers should take care of disabling all the display engine
9419  * functions, doing the mode unset, fixing interrupts, etc.
9420  */
9421 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9422                               bool switch_to_fclk, bool allow_power_down)
9423 {
9424         uint32_t val;
9425
9426         assert_can_disable_lcpll(dev_priv);
9427
9428         val = I915_READ(LCPLL_CTL);
9429
9430         if (switch_to_fclk) {
9431                 val |= LCPLL_CD_SOURCE_FCLK;
9432                 I915_WRITE(LCPLL_CTL, val);
9433
9434                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9435                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9436                         DRM_ERROR("Switching to FCLK failed\n");
9437
9438                 val = I915_READ(LCPLL_CTL);
9439         }
9440
9441         val |= LCPLL_PLL_DISABLE;
9442         I915_WRITE(LCPLL_CTL, val);
9443         POSTING_READ(LCPLL_CTL);
9444
9445         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9446                 DRM_ERROR("LCPLL still locked\n");
9447
9448         val = hsw_read_dcomp(dev_priv);
9449         val |= D_COMP_COMP_DISABLE;
9450         hsw_write_dcomp(dev_priv, val);
9451         ndelay(100);
9452
9453         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9454                      1))
9455                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9456
9457         if (allow_power_down) {
9458                 val = I915_READ(LCPLL_CTL);
9459                 val |= LCPLL_POWER_DOWN_ALLOW;
9460                 I915_WRITE(LCPLL_CTL, val);
9461                 POSTING_READ(LCPLL_CTL);
9462         }
9463 }
9464
9465 /*
9466  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9467  * source.
9468  */
9469 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9470 {
9471         uint32_t val;
9472
9473         val = I915_READ(LCPLL_CTL);
9474
9475         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9476                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9477                 return;
9478
9479         /*
9480          * Make sure we're not on PC8 state before disabling PC8, otherwise
9481          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9482          */
9483         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9484
9485         if (val & LCPLL_POWER_DOWN_ALLOW) {
9486                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9487                 I915_WRITE(LCPLL_CTL, val);
9488                 POSTING_READ(LCPLL_CTL);
9489         }
9490
9491         val = hsw_read_dcomp(dev_priv);
9492         val |= D_COMP_COMP_FORCE;
9493         val &= ~D_COMP_COMP_DISABLE;
9494         hsw_write_dcomp(dev_priv, val);
9495
9496         val = I915_READ(LCPLL_CTL);
9497         val &= ~LCPLL_PLL_DISABLE;
9498         I915_WRITE(LCPLL_CTL, val);
9499
9500         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9501                 DRM_ERROR("LCPLL not locked yet\n");
9502
9503         if (val & LCPLL_CD_SOURCE_FCLK) {
9504                 val = I915_READ(LCPLL_CTL);
9505                 val &= ~LCPLL_CD_SOURCE_FCLK;
9506                 I915_WRITE(LCPLL_CTL, val);
9507
9508                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9509                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9510                         DRM_ERROR("Switching back to LCPLL failed\n");
9511         }
9512
9513         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9514         intel_update_cdclk(dev_priv->dev);
9515 }
9516
9517 /*
9518  * Package states C8 and deeper are really deep PC states that can only be
9519  * reached when all the devices on the system allow it, so even if the graphics
9520  * device allows PC8+, it doesn't mean the system will actually get to these
9521  * states. Our driver only allows PC8+ when going into runtime PM.
9522  *
9523  * The requirements for PC8+ are that all the outputs are disabled, the power
9524  * well is disabled and most interrupts are disabled, and these are also
9525  * requirements for runtime PM. When these conditions are met, we manually do
9526  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9527  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9528  * hang the machine.
9529  *
9530  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9531  * the state of some registers, so when we come back from PC8+ we need to
9532  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9533  * need to take care of the registers kept by RC6. Notice that this happens even
9534  * if we don't put the device in PCI D3 state (which is what currently happens
9535  * because of the runtime PM support).
9536  *
9537  * For more, read "Display Sequences for Package C8" on the hardware
9538  * documentation.
9539  */
9540 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9541 {
9542         struct drm_device *dev = dev_priv->dev;
9543         uint32_t val;
9544
9545         DRM_DEBUG_KMS("Enabling package C8+\n");
9546
9547         if (HAS_PCH_LPT_LP(dev)) {
9548                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9549                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9550                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9551         }
9552
9553         lpt_disable_clkout_dp(dev);
9554         hsw_disable_lcpll(dev_priv, true, true);
9555 }
9556
9557 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9558 {
9559         struct drm_device *dev = dev_priv->dev;
9560         uint32_t val;
9561
9562         DRM_DEBUG_KMS("Disabling package C8+\n");
9563
9564         hsw_restore_lcpll(dev_priv);
9565         lpt_init_pch_refclk(dev);
9566
9567         if (HAS_PCH_LPT_LP(dev)) {
9568                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9569                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9570                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9571         }
9572
9573         intel_prepare_ddi(dev);
9574 }
9575
9576 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9577 {
9578         struct drm_device *dev = old_state->dev;
9579         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9580
9581         broxton_set_cdclk(dev, req_cdclk);
9582 }
9583
9584 /* compute the max rate for new configuration */
9585 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9586 {
9587         struct intel_crtc *intel_crtc;
9588         struct intel_crtc_state *crtc_state;
9589         int max_pixel_rate = 0;
9590
9591         for_each_intel_crtc(state->dev, intel_crtc) {
9592                 int pixel_rate;
9593
9594                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9595                 if (IS_ERR(crtc_state))
9596                         return PTR_ERR(crtc_state);
9597
9598                 if (!crtc_state->base.enable)
9599                         continue;
9600
9601                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9602
9603                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9604                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9605                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9606
9607                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9608         }
9609
9610         return max_pixel_rate;
9611 }
9612
9613 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9614 {
9615         struct drm_i915_private *dev_priv = dev->dev_private;
9616         uint32_t val, data;
9617         int ret;
9618
9619         if (WARN((I915_READ(LCPLL_CTL) &
9620                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9621                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9622                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9623                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9624                  "trying to change cdclk frequency with cdclk not enabled\n"))
9625                 return;
9626
9627         mutex_lock(&dev_priv->rps.hw_lock);
9628         ret = sandybridge_pcode_write(dev_priv,
9629                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9630         mutex_unlock(&dev_priv->rps.hw_lock);
9631         if (ret) {
9632                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9633                 return;
9634         }
9635
9636         val = I915_READ(LCPLL_CTL);
9637         val |= LCPLL_CD_SOURCE_FCLK;
9638         I915_WRITE(LCPLL_CTL, val);
9639
9640         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9641                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9642                 DRM_ERROR("Switching to FCLK failed\n");
9643
9644         val = I915_READ(LCPLL_CTL);
9645         val &= ~LCPLL_CLK_FREQ_MASK;
9646
9647         switch (cdclk) {
9648         case 450000:
9649                 val |= LCPLL_CLK_FREQ_450;
9650                 data = 0;
9651                 break;
9652         case 540000:
9653                 val |= LCPLL_CLK_FREQ_54O_BDW;
9654                 data = 1;
9655                 break;
9656         case 337500:
9657                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9658                 data = 2;
9659                 break;
9660         case 675000:
9661                 val |= LCPLL_CLK_FREQ_675_BDW;
9662                 data = 3;
9663                 break;
9664         default:
9665                 WARN(1, "invalid cdclk frequency\n");
9666                 return;
9667         }
9668
9669         I915_WRITE(LCPLL_CTL, val);
9670
9671         val = I915_READ(LCPLL_CTL);
9672         val &= ~LCPLL_CD_SOURCE_FCLK;
9673         I915_WRITE(LCPLL_CTL, val);
9674
9675         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9676                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9677                 DRM_ERROR("Switching back to LCPLL failed\n");
9678
9679         mutex_lock(&dev_priv->rps.hw_lock);
9680         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9681         mutex_unlock(&dev_priv->rps.hw_lock);
9682
9683         intel_update_cdclk(dev);
9684
9685         WARN(cdclk != dev_priv->cdclk_freq,
9686              "cdclk requested %d kHz but got %d kHz\n",
9687              cdclk, dev_priv->cdclk_freq);
9688 }
9689
9690 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9691 {
9692         struct drm_i915_private *dev_priv = to_i915(state->dev);
9693         int max_pixclk = ilk_max_pixel_rate(state);
9694         int cdclk;
9695
9696         /*
9697          * FIXME should also account for plane ratio
9698          * once 64bpp pixel formats are supported.
9699          */
9700         if (max_pixclk > 540000)
9701                 cdclk = 675000;
9702         else if (max_pixclk > 450000)
9703                 cdclk = 540000;
9704         else if (max_pixclk > 337500)
9705                 cdclk = 450000;
9706         else
9707                 cdclk = 337500;
9708
9709         /*
9710          * FIXME move the cdclk caclulation to
9711          * compute_config() so we can fail gracegully.
9712          */
9713         if (cdclk > dev_priv->max_cdclk_freq) {
9714                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9715                           cdclk, dev_priv->max_cdclk_freq);
9716                 cdclk = dev_priv->max_cdclk_freq;
9717         }
9718
9719         to_intel_atomic_state(state)->cdclk = cdclk;
9720
9721         return 0;
9722 }
9723
9724 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9725 {
9726         struct drm_device *dev = old_state->dev;
9727         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9728
9729         broadwell_set_cdclk(dev, req_cdclk);
9730 }
9731
9732 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9733                                       struct intel_crtc_state *crtc_state)
9734 {
9735         if (!intel_ddi_pll_select(crtc, crtc_state))
9736                 return -EINVAL;
9737
9738         crtc->lowfreq_avail = false;
9739
9740         return 0;
9741 }
9742
9743 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9744                                 enum port port,
9745                                 struct intel_crtc_state *pipe_config)
9746 {
9747         switch (port) {
9748         case PORT_A:
9749                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9750                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9751                 break;
9752         case PORT_B:
9753                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9754                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9755                 break;
9756         case PORT_C:
9757                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9758                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9759                 break;
9760         default:
9761                 DRM_ERROR("Incorrect port type\n");
9762         }
9763 }
9764
9765 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9766                                 enum port port,
9767                                 struct intel_crtc_state *pipe_config)
9768 {
9769         u32 temp, dpll_ctl1;
9770
9771         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9772         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9773
9774         switch (pipe_config->ddi_pll_sel) {
9775         case SKL_DPLL0:
9776                 /*
9777                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9778                  * of the shared DPLL framework and thus needs to be read out
9779                  * separately
9780                  */
9781                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9782                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9783                 break;
9784         case SKL_DPLL1:
9785                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9786                 break;
9787         case SKL_DPLL2:
9788                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9789                 break;
9790         case SKL_DPLL3:
9791                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9792                 break;
9793         }
9794 }
9795
9796 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9797                                 enum port port,
9798                                 struct intel_crtc_state *pipe_config)
9799 {
9800         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9801
9802         switch (pipe_config->ddi_pll_sel) {
9803         case PORT_CLK_SEL_WRPLL1:
9804                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9805                 break;
9806         case PORT_CLK_SEL_WRPLL2:
9807                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9808                 break;
9809         case PORT_CLK_SEL_SPLL:
9810                 pipe_config->shared_dpll = DPLL_ID_SPLL;
9811         }
9812 }
9813
9814 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9815                                        struct intel_crtc_state *pipe_config)
9816 {
9817         struct drm_device *dev = crtc->base.dev;
9818         struct drm_i915_private *dev_priv = dev->dev_private;
9819         struct intel_shared_dpll *pll;
9820         enum port port;
9821         uint32_t tmp;
9822
9823         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9824
9825         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9826
9827         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9828                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9829         else if (IS_BROXTON(dev))
9830                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9831         else
9832                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9833
9834         if (pipe_config->shared_dpll >= 0) {
9835                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9836
9837                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9838                                            &pipe_config->dpll_hw_state));
9839         }
9840
9841         /*
9842          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9843          * DDI E. So just check whether this pipe is wired to DDI E and whether
9844          * the PCH transcoder is on.
9845          */
9846         if (INTEL_INFO(dev)->gen < 9 &&
9847             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9848                 pipe_config->has_pch_encoder = true;
9849
9850                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9851                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9852                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9853
9854                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9855         }
9856 }
9857
9858 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9859                                     struct intel_crtc_state *pipe_config)
9860 {
9861         struct drm_device *dev = crtc->base.dev;
9862         struct drm_i915_private *dev_priv = dev->dev_private;
9863         enum intel_display_power_domain pfit_domain;
9864         uint32_t tmp;
9865
9866         if (!intel_display_power_is_enabled(dev_priv,
9867                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9868                 return false;
9869
9870         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9871         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9872
9873         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9874         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9875                 enum pipe trans_edp_pipe;
9876                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9877                 default:
9878                         WARN(1, "unknown pipe linked to edp transcoder\n");
9879                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9880                 case TRANS_DDI_EDP_INPUT_A_ON:
9881                         trans_edp_pipe = PIPE_A;
9882                         break;
9883                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9884                         trans_edp_pipe = PIPE_B;
9885                         break;
9886                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9887                         trans_edp_pipe = PIPE_C;
9888                         break;
9889                 }
9890
9891                 if (trans_edp_pipe == crtc->pipe)
9892                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9893         }
9894
9895         if (!intel_display_power_is_enabled(dev_priv,
9896                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9897                 return false;
9898
9899         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9900         if (!(tmp & PIPECONF_ENABLE))
9901                 return false;
9902
9903         haswell_get_ddi_port_state(crtc, pipe_config);
9904
9905         intel_get_pipe_timings(crtc, pipe_config);
9906
9907         if (INTEL_INFO(dev)->gen >= 9) {
9908                 skl_init_scalers(dev, crtc, pipe_config);
9909         }
9910
9911         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9912
9913         if (INTEL_INFO(dev)->gen >= 9) {
9914                 pipe_config->scaler_state.scaler_id = -1;
9915                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9916         }
9917
9918         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9919                 if (INTEL_INFO(dev)->gen >= 9)
9920                         skylake_get_pfit_config(crtc, pipe_config);
9921                 else
9922                         ironlake_get_pfit_config(crtc, pipe_config);
9923         }
9924
9925         if (IS_HASWELL(dev))
9926                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9927                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9928
9929         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9930                 pipe_config->pixel_multiplier =
9931                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9932         } else {
9933                 pipe_config->pixel_multiplier = 1;
9934         }
9935
9936         return true;
9937 }
9938
9939 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9940 {
9941         struct drm_device *dev = crtc->dev;
9942         struct drm_i915_private *dev_priv = dev->dev_private;
9943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9944         uint32_t cntl = 0, size = 0;
9945
9946         if (base) {
9947                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9948                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9949                 unsigned int stride = roundup_pow_of_two(width) * 4;
9950
9951                 switch (stride) {
9952                 default:
9953                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9954                                   width, stride);
9955                         stride = 256;
9956                         /* fallthrough */
9957                 case 256:
9958                 case 512:
9959                 case 1024:
9960                 case 2048:
9961                         break;
9962                 }
9963
9964                 cntl |= CURSOR_ENABLE |
9965                         CURSOR_GAMMA_ENABLE |
9966                         CURSOR_FORMAT_ARGB |
9967                         CURSOR_STRIDE(stride);
9968
9969                 size = (height << 12) | width;
9970         }
9971
9972         if (intel_crtc->cursor_cntl != 0 &&
9973             (intel_crtc->cursor_base != base ||
9974              intel_crtc->cursor_size != size ||
9975              intel_crtc->cursor_cntl != cntl)) {
9976                 /* On these chipsets we can only modify the base/size/stride
9977                  * whilst the cursor is disabled.
9978                  */
9979                 I915_WRITE(CURCNTR(PIPE_A), 0);
9980                 POSTING_READ(CURCNTR(PIPE_A));
9981                 intel_crtc->cursor_cntl = 0;
9982         }
9983
9984         if (intel_crtc->cursor_base != base) {
9985                 I915_WRITE(CURBASE(PIPE_A), base);
9986                 intel_crtc->cursor_base = base;
9987         }
9988
9989         if (intel_crtc->cursor_size != size) {
9990                 I915_WRITE(CURSIZE, size);
9991                 intel_crtc->cursor_size = size;
9992         }
9993
9994         if (intel_crtc->cursor_cntl != cntl) {
9995                 I915_WRITE(CURCNTR(PIPE_A), cntl);
9996                 POSTING_READ(CURCNTR(PIPE_A));
9997                 intel_crtc->cursor_cntl = cntl;
9998         }
9999 }
10000
10001 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
10002 {
10003         struct drm_device *dev = crtc->dev;
10004         struct drm_i915_private *dev_priv = dev->dev_private;
10005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10006         int pipe = intel_crtc->pipe;
10007         uint32_t cntl;
10008
10009         cntl = 0;
10010         if (base) {
10011                 cntl = MCURSOR_GAMMA_ENABLE;
10012                 switch (intel_crtc->base.cursor->state->crtc_w) {
10013                         case 64:
10014                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10015                                 break;
10016                         case 128:
10017                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10018                                 break;
10019                         case 256:
10020                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10021                                 break;
10022                         default:
10023                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10024                                 return;
10025                 }
10026                 cntl |= pipe << 28; /* Connect to correct pipe */
10027
10028                 if (HAS_DDI(dev))
10029                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10030         }
10031
10032         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10033                 cntl |= CURSOR_ROTATE_180;
10034
10035         if (intel_crtc->cursor_cntl != cntl) {
10036                 I915_WRITE(CURCNTR(pipe), cntl);
10037                 POSTING_READ(CURCNTR(pipe));
10038                 intel_crtc->cursor_cntl = cntl;
10039         }
10040
10041         /* and commit changes on next vblank */
10042         I915_WRITE(CURBASE(pipe), base);
10043         POSTING_READ(CURBASE(pipe));
10044
10045         intel_crtc->cursor_base = base;
10046 }
10047
10048 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10049 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10050                                      bool on)
10051 {
10052         struct drm_device *dev = crtc->dev;
10053         struct drm_i915_private *dev_priv = dev->dev_private;
10054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10055         int pipe = intel_crtc->pipe;
10056         struct drm_plane_state *cursor_state = crtc->cursor->state;
10057         int x = cursor_state->crtc_x;
10058         int y = cursor_state->crtc_y;
10059         u32 base = 0, pos = 0;
10060
10061         if (on)
10062                 base = intel_crtc->cursor_addr;
10063
10064         if (x >= intel_crtc->config->pipe_src_w)
10065                 base = 0;
10066
10067         if (y >= intel_crtc->config->pipe_src_h)
10068                 base = 0;
10069
10070         if (x < 0) {
10071                 if (x + cursor_state->crtc_w <= 0)
10072                         base = 0;
10073
10074                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10075                 x = -x;
10076         }
10077         pos |= x << CURSOR_X_SHIFT;
10078
10079         if (y < 0) {
10080                 if (y + cursor_state->crtc_h <= 0)
10081                         base = 0;
10082
10083                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10084                 y = -y;
10085         }
10086         pos |= y << CURSOR_Y_SHIFT;
10087
10088         if (base == 0 && intel_crtc->cursor_base == 0)
10089                 return;
10090
10091         I915_WRITE(CURPOS(pipe), pos);
10092
10093         /* ILK+ do this automagically */
10094         if (HAS_GMCH_DISPLAY(dev) &&
10095             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10096                 base += (cursor_state->crtc_h *
10097                          cursor_state->crtc_w - 1) * 4;
10098         }
10099
10100         if (IS_845G(dev) || IS_I865G(dev))
10101                 i845_update_cursor(crtc, base);
10102         else
10103                 i9xx_update_cursor(crtc, base);
10104 }
10105
10106 static bool cursor_size_ok(struct drm_device *dev,
10107                            uint32_t width, uint32_t height)
10108 {
10109         if (width == 0 || height == 0)
10110                 return false;
10111
10112         /*
10113          * 845g/865g are special in that they are only limited by
10114          * the width of their cursors, the height is arbitrary up to
10115          * the precision of the register. Everything else requires
10116          * square cursors, limited to a few power-of-two sizes.
10117          */
10118         if (IS_845G(dev) || IS_I865G(dev)) {
10119                 if ((width & 63) != 0)
10120                         return false;
10121
10122                 if (width > (IS_845G(dev) ? 64 : 512))
10123                         return false;
10124
10125                 if (height > 1023)
10126                         return false;
10127         } else {
10128                 switch (width | height) {
10129                 case 256:
10130                 case 128:
10131                         if (IS_GEN2(dev))
10132                                 return false;
10133                 case 64:
10134                         break;
10135                 default:
10136                         return false;
10137                 }
10138         }
10139
10140         return true;
10141 }
10142
10143 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10144                                  u16 *blue, uint32_t start, uint32_t size)
10145 {
10146         int end = (start + size > 256) ? 256 : start + size, i;
10147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10148
10149         for (i = start; i < end; i++) {
10150                 intel_crtc->lut_r[i] = red[i] >> 8;
10151                 intel_crtc->lut_g[i] = green[i] >> 8;
10152                 intel_crtc->lut_b[i] = blue[i] >> 8;
10153         }
10154
10155         intel_crtc_load_lut(crtc);
10156 }
10157
10158 /* VESA 640x480x72Hz mode to set on the pipe */
10159 static struct drm_display_mode load_detect_mode = {
10160         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10161                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10162 };
10163
10164 struct drm_framebuffer *
10165 __intel_framebuffer_create(struct drm_device *dev,
10166                            struct drm_mode_fb_cmd2 *mode_cmd,
10167                            struct drm_i915_gem_object *obj)
10168 {
10169         struct intel_framebuffer *intel_fb;
10170         int ret;
10171
10172         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10173         if (!intel_fb)
10174                 return ERR_PTR(-ENOMEM);
10175
10176         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10177         if (ret)
10178                 goto err;
10179
10180         return &intel_fb->base;
10181
10182 err:
10183         kfree(intel_fb);
10184         return ERR_PTR(ret);
10185 }
10186
10187 static struct drm_framebuffer *
10188 intel_framebuffer_create(struct drm_device *dev,
10189                          struct drm_mode_fb_cmd2 *mode_cmd,
10190                          struct drm_i915_gem_object *obj)
10191 {
10192         struct drm_framebuffer *fb;
10193         int ret;
10194
10195         ret = i915_mutex_lock_interruptible(dev);
10196         if (ret)
10197                 return ERR_PTR(ret);
10198         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10199         mutex_unlock(&dev->struct_mutex);
10200
10201         return fb;
10202 }
10203
10204 static u32
10205 intel_framebuffer_pitch_for_width(int width, int bpp)
10206 {
10207         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10208         return ALIGN(pitch, 64);
10209 }
10210
10211 static u32
10212 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10213 {
10214         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10215         return PAGE_ALIGN(pitch * mode->vdisplay);
10216 }
10217
10218 static struct drm_framebuffer *
10219 intel_framebuffer_create_for_mode(struct drm_device *dev,
10220                                   struct drm_display_mode *mode,
10221                                   int depth, int bpp)
10222 {
10223         struct drm_framebuffer *fb;
10224         struct drm_i915_gem_object *obj;
10225         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10226
10227         obj = i915_gem_alloc_object(dev,
10228                                     intel_framebuffer_size_for_mode(mode, bpp));
10229         if (obj == NULL)
10230                 return ERR_PTR(-ENOMEM);
10231
10232         mode_cmd.width = mode->hdisplay;
10233         mode_cmd.height = mode->vdisplay;
10234         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10235                                                                 bpp);
10236         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10237
10238         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10239         if (IS_ERR(fb))
10240                 drm_gem_object_unreference_unlocked(&obj->base);
10241
10242         return fb;
10243 }
10244
10245 static struct drm_framebuffer *
10246 mode_fits_in_fbdev(struct drm_device *dev,
10247                    struct drm_display_mode *mode)
10248 {
10249 #ifdef CONFIG_DRM_FBDEV_EMULATION
10250         struct drm_i915_private *dev_priv = dev->dev_private;
10251         struct drm_i915_gem_object *obj;
10252         struct drm_framebuffer *fb;
10253
10254         if (!dev_priv->fbdev)
10255                 return NULL;
10256
10257         if (!dev_priv->fbdev->fb)
10258                 return NULL;
10259
10260         obj = dev_priv->fbdev->fb->obj;
10261         BUG_ON(!obj);
10262
10263         fb = &dev_priv->fbdev->fb->base;
10264         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10265                                                                fb->bits_per_pixel))
10266                 return NULL;
10267
10268         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10269                 return NULL;
10270
10271         return fb;
10272 #else
10273         return NULL;
10274 #endif
10275 }
10276
10277 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10278                                            struct drm_crtc *crtc,
10279                                            struct drm_display_mode *mode,
10280                                            struct drm_framebuffer *fb,
10281                                            int x, int y)
10282 {
10283         struct drm_plane_state *plane_state;
10284         int hdisplay, vdisplay;
10285         int ret;
10286
10287         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10288         if (IS_ERR(plane_state))
10289                 return PTR_ERR(plane_state);
10290
10291         if (mode)
10292                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10293         else
10294                 hdisplay = vdisplay = 0;
10295
10296         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10297         if (ret)
10298                 return ret;
10299         drm_atomic_set_fb_for_plane(plane_state, fb);
10300         plane_state->crtc_x = 0;
10301         plane_state->crtc_y = 0;
10302         plane_state->crtc_w = hdisplay;
10303         plane_state->crtc_h = vdisplay;
10304         plane_state->src_x = x << 16;
10305         plane_state->src_y = y << 16;
10306         plane_state->src_w = hdisplay << 16;
10307         plane_state->src_h = vdisplay << 16;
10308
10309         return 0;
10310 }
10311
10312 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10313                                 struct drm_display_mode *mode,
10314                                 struct intel_load_detect_pipe *old,
10315                                 struct drm_modeset_acquire_ctx *ctx)
10316 {
10317         struct intel_crtc *intel_crtc;
10318         struct intel_encoder *intel_encoder =
10319                 intel_attached_encoder(connector);
10320         struct drm_crtc *possible_crtc;
10321         struct drm_encoder *encoder = &intel_encoder->base;
10322         struct drm_crtc *crtc = NULL;
10323         struct drm_device *dev = encoder->dev;
10324         struct drm_framebuffer *fb;
10325         struct drm_mode_config *config = &dev->mode_config;
10326         struct drm_atomic_state *state = NULL;
10327         struct drm_connector_state *connector_state;
10328         struct intel_crtc_state *crtc_state;
10329         int ret, i = -1;
10330
10331         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10332                       connector->base.id, connector->name,
10333                       encoder->base.id, encoder->name);
10334
10335 retry:
10336         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10337         if (ret)
10338                 goto fail;
10339
10340         /*
10341          * Algorithm gets a little messy:
10342          *
10343          *   - if the connector already has an assigned crtc, use it (but make
10344          *     sure it's on first)
10345          *
10346          *   - try to find the first unused crtc that can drive this connector,
10347          *     and use that if we find one
10348          */
10349
10350         /* See if we already have a CRTC for this connector */
10351         if (encoder->crtc) {
10352                 crtc = encoder->crtc;
10353
10354                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10355                 if (ret)
10356                         goto fail;
10357                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10358                 if (ret)
10359                         goto fail;
10360
10361                 old->dpms_mode = connector->dpms;
10362                 old->load_detect_temp = false;
10363
10364                 /* Make sure the crtc and connector are running */
10365                 if (connector->dpms != DRM_MODE_DPMS_ON)
10366                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10367
10368                 return true;
10369         }
10370
10371         /* Find an unused one (if possible) */
10372         for_each_crtc(dev, possible_crtc) {
10373                 i++;
10374                 if (!(encoder->possible_crtcs & (1 << i)))
10375                         continue;
10376                 if (possible_crtc->state->enable)
10377                         continue;
10378
10379                 crtc = possible_crtc;
10380                 break;
10381         }
10382
10383         /*
10384          * If we didn't find an unused CRTC, don't use any.
10385          */
10386         if (!crtc) {
10387                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10388                 goto fail;
10389         }
10390
10391         ret = drm_modeset_lock(&crtc->mutex, ctx);
10392         if (ret)
10393                 goto fail;
10394         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10395         if (ret)
10396                 goto fail;
10397
10398         intel_crtc = to_intel_crtc(crtc);
10399         old->dpms_mode = connector->dpms;
10400         old->load_detect_temp = true;
10401         old->release_fb = NULL;
10402
10403         state = drm_atomic_state_alloc(dev);
10404         if (!state)
10405                 return false;
10406
10407         state->acquire_ctx = ctx;
10408
10409         connector_state = drm_atomic_get_connector_state(state, connector);
10410         if (IS_ERR(connector_state)) {
10411                 ret = PTR_ERR(connector_state);
10412                 goto fail;
10413         }
10414
10415         connector_state->crtc = crtc;
10416         connector_state->best_encoder = &intel_encoder->base;
10417
10418         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10419         if (IS_ERR(crtc_state)) {
10420                 ret = PTR_ERR(crtc_state);
10421                 goto fail;
10422         }
10423
10424         crtc_state->base.active = crtc_state->base.enable = true;
10425
10426         if (!mode)
10427                 mode = &load_detect_mode;
10428
10429         /* We need a framebuffer large enough to accommodate all accesses
10430          * that the plane may generate whilst we perform load detection.
10431          * We can not rely on the fbcon either being present (we get called
10432          * during its initialisation to detect all boot displays, or it may
10433          * not even exist) or that it is large enough to satisfy the
10434          * requested mode.
10435          */
10436         fb = mode_fits_in_fbdev(dev, mode);
10437         if (fb == NULL) {
10438                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10439                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10440                 old->release_fb = fb;
10441         } else
10442                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10443         if (IS_ERR(fb)) {
10444                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10445                 goto fail;
10446         }
10447
10448         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10449         if (ret)
10450                 goto fail;
10451
10452         drm_mode_copy(&crtc_state->base.mode, mode);
10453
10454         if (drm_atomic_commit(state)) {
10455                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10456                 if (old->release_fb)
10457                         old->release_fb->funcs->destroy(old->release_fb);
10458                 goto fail;
10459         }
10460         crtc->primary->crtc = crtc;
10461
10462         /* let the connector get through one full cycle before testing */
10463         intel_wait_for_vblank(dev, intel_crtc->pipe);
10464         return true;
10465
10466 fail:
10467         drm_atomic_state_free(state);
10468         state = NULL;
10469
10470         if (ret == -EDEADLK) {
10471                 drm_modeset_backoff(ctx);
10472                 goto retry;
10473         }
10474
10475         return false;
10476 }
10477
10478 void intel_release_load_detect_pipe(struct drm_connector *connector,
10479                                     struct intel_load_detect_pipe *old,
10480                                     struct drm_modeset_acquire_ctx *ctx)
10481 {
10482         struct drm_device *dev = connector->dev;
10483         struct intel_encoder *intel_encoder =
10484                 intel_attached_encoder(connector);
10485         struct drm_encoder *encoder = &intel_encoder->base;
10486         struct drm_crtc *crtc = encoder->crtc;
10487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10488         struct drm_atomic_state *state;
10489         struct drm_connector_state *connector_state;
10490         struct intel_crtc_state *crtc_state;
10491         int ret;
10492
10493         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10494                       connector->base.id, connector->name,
10495                       encoder->base.id, encoder->name);
10496
10497         if (old->load_detect_temp) {
10498                 state = drm_atomic_state_alloc(dev);
10499                 if (!state)
10500                         goto fail;
10501
10502                 state->acquire_ctx = ctx;
10503
10504                 connector_state = drm_atomic_get_connector_state(state, connector);
10505                 if (IS_ERR(connector_state))
10506                         goto fail;
10507
10508                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10509                 if (IS_ERR(crtc_state))
10510                         goto fail;
10511
10512                 connector_state->best_encoder = NULL;
10513                 connector_state->crtc = NULL;
10514
10515                 crtc_state->base.enable = crtc_state->base.active = false;
10516
10517                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10518                                                       0, 0);
10519                 if (ret)
10520                         goto fail;
10521
10522                 ret = drm_atomic_commit(state);
10523                 if (ret)
10524                         goto fail;
10525
10526                 if (old->release_fb) {
10527                         drm_framebuffer_unregister_private(old->release_fb);
10528                         drm_framebuffer_unreference(old->release_fb);
10529                 }
10530
10531                 return;
10532         }
10533
10534         /* Switch crtc and encoder back off if necessary */
10535         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10536                 connector->funcs->dpms(connector, old->dpms_mode);
10537
10538         return;
10539 fail:
10540         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10541         drm_atomic_state_free(state);
10542 }
10543
10544 static int i9xx_pll_refclk(struct drm_device *dev,
10545                            const struct intel_crtc_state *pipe_config)
10546 {
10547         struct drm_i915_private *dev_priv = dev->dev_private;
10548         u32 dpll = pipe_config->dpll_hw_state.dpll;
10549
10550         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10551                 return dev_priv->vbt.lvds_ssc_freq;
10552         else if (HAS_PCH_SPLIT(dev))
10553                 return 120000;
10554         else if (!IS_GEN2(dev))
10555                 return 96000;
10556         else
10557                 return 48000;
10558 }
10559
10560 /* Returns the clock of the currently programmed mode of the given pipe. */
10561 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10562                                 struct intel_crtc_state *pipe_config)
10563 {
10564         struct drm_device *dev = crtc->base.dev;
10565         struct drm_i915_private *dev_priv = dev->dev_private;
10566         int pipe = pipe_config->cpu_transcoder;
10567         u32 dpll = pipe_config->dpll_hw_state.dpll;
10568         u32 fp;
10569         intel_clock_t clock;
10570         int port_clock;
10571         int refclk = i9xx_pll_refclk(dev, pipe_config);
10572
10573         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10574                 fp = pipe_config->dpll_hw_state.fp0;
10575         else
10576                 fp = pipe_config->dpll_hw_state.fp1;
10577
10578         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10579         if (IS_PINEVIEW(dev)) {
10580                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10581                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10582         } else {
10583                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10584                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10585         }
10586
10587         if (!IS_GEN2(dev)) {
10588                 if (IS_PINEVIEW(dev))
10589                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10590                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10591                 else
10592                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10593                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10594
10595                 switch (dpll & DPLL_MODE_MASK) {
10596                 case DPLLB_MODE_DAC_SERIAL:
10597                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10598                                 5 : 10;
10599                         break;
10600                 case DPLLB_MODE_LVDS:
10601                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10602                                 7 : 14;
10603                         break;
10604                 default:
10605                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10606                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10607                         return;
10608                 }
10609
10610                 if (IS_PINEVIEW(dev))
10611                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10612                 else
10613                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10614         } else {
10615                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10616                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10617
10618                 if (is_lvds) {
10619                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10620                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10621
10622                         if (lvds & LVDS_CLKB_POWER_UP)
10623                                 clock.p2 = 7;
10624                         else
10625                                 clock.p2 = 14;
10626                 } else {
10627                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10628                                 clock.p1 = 2;
10629                         else {
10630                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10631                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10632                         }
10633                         if (dpll & PLL_P2_DIVIDE_BY_4)
10634                                 clock.p2 = 4;
10635                         else
10636                                 clock.p2 = 2;
10637                 }
10638
10639                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10640         }
10641
10642         /*
10643          * This value includes pixel_multiplier. We will use
10644          * port_clock to compute adjusted_mode.crtc_clock in the
10645          * encoder's get_config() function.
10646          */
10647         pipe_config->port_clock = port_clock;
10648 }
10649
10650 int intel_dotclock_calculate(int link_freq,
10651                              const struct intel_link_m_n *m_n)
10652 {
10653         /*
10654          * The calculation for the data clock is:
10655          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10656          * But we want to avoid losing precison if possible, so:
10657          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10658          *
10659          * and the link clock is simpler:
10660          * link_clock = (m * link_clock) / n
10661          */
10662
10663         if (!m_n->link_n)
10664                 return 0;
10665
10666         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10667 }
10668
10669 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10670                                    struct intel_crtc_state *pipe_config)
10671 {
10672         struct drm_device *dev = crtc->base.dev;
10673
10674         /* read out port_clock from the DPLL */
10675         i9xx_crtc_clock_get(crtc, pipe_config);
10676
10677         /*
10678          * This value does not include pixel_multiplier.
10679          * We will check that port_clock and adjusted_mode.crtc_clock
10680          * agree once we know their relationship in the encoder's
10681          * get_config() function.
10682          */
10683         pipe_config->base.adjusted_mode.crtc_clock =
10684                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10685                                          &pipe_config->fdi_m_n);
10686 }
10687
10688 /** Returns the currently programmed mode of the given pipe. */
10689 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10690                                              struct drm_crtc *crtc)
10691 {
10692         struct drm_i915_private *dev_priv = dev->dev_private;
10693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10694         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10695         struct drm_display_mode *mode;
10696         struct intel_crtc_state pipe_config;
10697         int htot = I915_READ(HTOTAL(cpu_transcoder));
10698         int hsync = I915_READ(HSYNC(cpu_transcoder));
10699         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10700         int vsync = I915_READ(VSYNC(cpu_transcoder));
10701         enum pipe pipe = intel_crtc->pipe;
10702
10703         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10704         if (!mode)
10705                 return NULL;
10706
10707         /*
10708          * Construct a pipe_config sufficient for getting the clock info
10709          * back out of crtc_clock_get.
10710          *
10711          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10712          * to use a real value here instead.
10713          */
10714         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10715         pipe_config.pixel_multiplier = 1;
10716         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10717         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10718         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10719         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10720
10721         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10722         mode->hdisplay = (htot & 0xffff) + 1;
10723         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10724         mode->hsync_start = (hsync & 0xffff) + 1;
10725         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10726         mode->vdisplay = (vtot & 0xffff) + 1;
10727         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10728         mode->vsync_start = (vsync & 0xffff) + 1;
10729         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10730
10731         drm_mode_set_name(mode);
10732
10733         return mode;
10734 }
10735
10736 void intel_mark_busy(struct drm_device *dev)
10737 {
10738         struct drm_i915_private *dev_priv = dev->dev_private;
10739
10740         if (dev_priv->mm.busy)
10741                 return;
10742
10743         intel_runtime_pm_get(dev_priv);
10744         i915_update_gfx_val(dev_priv);
10745         if (INTEL_INFO(dev)->gen >= 6)
10746                 gen6_rps_busy(dev_priv);
10747         dev_priv->mm.busy = true;
10748 }
10749
10750 void intel_mark_idle(struct drm_device *dev)
10751 {
10752         struct drm_i915_private *dev_priv = dev->dev_private;
10753
10754         if (!dev_priv->mm.busy)
10755                 return;
10756
10757         dev_priv->mm.busy = false;
10758
10759         if (INTEL_INFO(dev)->gen >= 6)
10760                 gen6_rps_idle(dev->dev_private);
10761
10762         intel_runtime_pm_put(dev_priv);
10763 }
10764
10765 static void intel_crtc_destroy(struct drm_crtc *crtc)
10766 {
10767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10768         struct drm_device *dev = crtc->dev;
10769         struct intel_unpin_work *work;
10770
10771         spin_lock_irq(&dev->event_lock);
10772         work = intel_crtc->unpin_work;
10773         intel_crtc->unpin_work = NULL;
10774         spin_unlock_irq(&dev->event_lock);
10775
10776         if (work) {
10777                 cancel_work_sync(&work->work);
10778                 kfree(work);
10779         }
10780
10781         drm_crtc_cleanup(crtc);
10782
10783         kfree(intel_crtc);
10784 }
10785
10786 static void intel_unpin_work_fn(struct work_struct *__work)
10787 {
10788         struct intel_unpin_work *work =
10789                 container_of(__work, struct intel_unpin_work, work);
10790         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10791         struct drm_device *dev = crtc->base.dev;
10792         struct drm_plane *primary = crtc->base.primary;
10793
10794         mutex_lock(&dev->struct_mutex);
10795         intel_unpin_fb_obj(work->old_fb, primary->state);
10796         drm_gem_object_unreference(&work->pending_flip_obj->base);
10797
10798         if (work->flip_queued_req)
10799                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10800         mutex_unlock(&dev->struct_mutex);
10801
10802         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10803         drm_framebuffer_unreference(work->old_fb);
10804
10805         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10806         atomic_dec(&crtc->unpin_work_count);
10807
10808         kfree(work);
10809 }
10810
10811 static void do_intel_finish_page_flip(struct drm_device *dev,
10812                                       struct drm_crtc *crtc)
10813 {
10814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10815         struct intel_unpin_work *work;
10816         unsigned long flags;
10817
10818         /* Ignore early vblank irqs */
10819         if (intel_crtc == NULL)
10820                 return;
10821
10822         /*
10823          * This is called both by irq handlers and the reset code (to complete
10824          * lost pageflips) so needs the full irqsave spinlocks.
10825          */
10826         spin_lock_irqsave(&dev->event_lock, flags);
10827         work = intel_crtc->unpin_work;
10828
10829         /* Ensure we don't miss a work->pending update ... */
10830         smp_rmb();
10831
10832         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10833                 spin_unlock_irqrestore(&dev->event_lock, flags);
10834                 return;
10835         }
10836
10837         page_flip_completed(intel_crtc);
10838
10839         spin_unlock_irqrestore(&dev->event_lock, flags);
10840 }
10841
10842 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10843 {
10844         struct drm_i915_private *dev_priv = dev->dev_private;
10845         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10846
10847         do_intel_finish_page_flip(dev, crtc);
10848 }
10849
10850 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10851 {
10852         struct drm_i915_private *dev_priv = dev->dev_private;
10853         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10854
10855         do_intel_finish_page_flip(dev, crtc);
10856 }
10857
10858 /* Is 'a' after or equal to 'b'? */
10859 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10860 {
10861         return !((a - b) & 0x80000000);
10862 }
10863
10864 static bool page_flip_finished(struct intel_crtc *crtc)
10865 {
10866         struct drm_device *dev = crtc->base.dev;
10867         struct drm_i915_private *dev_priv = dev->dev_private;
10868
10869         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10870             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10871                 return true;
10872
10873         /*
10874          * The relevant registers doen't exist on pre-ctg.
10875          * As the flip done interrupt doesn't trigger for mmio
10876          * flips on gmch platforms, a flip count check isn't
10877          * really needed there. But since ctg has the registers,
10878          * include it in the check anyway.
10879          */
10880         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10881                 return true;
10882
10883         /*
10884          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10885          * used the same base address. In that case the mmio flip might
10886          * have completed, but the CS hasn't even executed the flip yet.
10887          *
10888          * A flip count check isn't enough as the CS might have updated
10889          * the base address just after start of vblank, but before we
10890          * managed to process the interrupt. This means we'd complete the
10891          * CS flip too soon.
10892          *
10893          * Combining both checks should get us a good enough result. It may
10894          * still happen that the CS flip has been executed, but has not
10895          * yet actually completed. But in case the base address is the same
10896          * anyway, we don't really care.
10897          */
10898         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10899                 crtc->unpin_work->gtt_offset &&
10900                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10901                                     crtc->unpin_work->flip_count);
10902 }
10903
10904 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10905 {
10906         struct drm_i915_private *dev_priv = dev->dev_private;
10907         struct intel_crtc *intel_crtc =
10908                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10909         unsigned long flags;
10910
10911
10912         /*
10913          * This is called both by irq handlers and the reset code (to complete
10914          * lost pageflips) so needs the full irqsave spinlocks.
10915          *
10916          * NB: An MMIO update of the plane base pointer will also
10917          * generate a page-flip completion irq, i.e. every modeset
10918          * is also accompanied by a spurious intel_prepare_page_flip().
10919          */
10920         spin_lock_irqsave(&dev->event_lock, flags);
10921         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10922                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10923         spin_unlock_irqrestore(&dev->event_lock, flags);
10924 }
10925
10926 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10927 {
10928         /* Ensure that the work item is consistent when activating it ... */
10929         smp_wmb();
10930         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10931         /* and that it is marked active as soon as the irq could fire. */
10932         smp_wmb();
10933 }
10934
10935 static int intel_gen2_queue_flip(struct drm_device *dev,
10936                                  struct drm_crtc *crtc,
10937                                  struct drm_framebuffer *fb,
10938                                  struct drm_i915_gem_object *obj,
10939                                  struct drm_i915_gem_request *req,
10940                                  uint32_t flags)
10941 {
10942         struct intel_engine_cs *ring = req->ring;
10943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10944         u32 flip_mask;
10945         int ret;
10946
10947         ret = intel_ring_begin(req, 6);
10948         if (ret)
10949                 return ret;
10950
10951         /* Can't queue multiple flips, so wait for the previous
10952          * one to finish before executing the next.
10953          */
10954         if (intel_crtc->plane)
10955                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10956         else
10957                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10958         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10959         intel_ring_emit(ring, MI_NOOP);
10960         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10961                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10962         intel_ring_emit(ring, fb->pitches[0]);
10963         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10964         intel_ring_emit(ring, 0); /* aux display base address, unused */
10965
10966         intel_mark_page_flip_active(intel_crtc->unpin_work);
10967         return 0;
10968 }
10969
10970 static int intel_gen3_queue_flip(struct drm_device *dev,
10971                                  struct drm_crtc *crtc,
10972                                  struct drm_framebuffer *fb,
10973                                  struct drm_i915_gem_object *obj,
10974                                  struct drm_i915_gem_request *req,
10975                                  uint32_t flags)
10976 {
10977         struct intel_engine_cs *ring = req->ring;
10978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10979         u32 flip_mask;
10980         int ret;
10981
10982         ret = intel_ring_begin(req, 6);
10983         if (ret)
10984                 return ret;
10985
10986         if (intel_crtc->plane)
10987                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10988         else
10989                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10990         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10991         intel_ring_emit(ring, MI_NOOP);
10992         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10993                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10994         intel_ring_emit(ring, fb->pitches[0]);
10995         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10996         intel_ring_emit(ring, MI_NOOP);
10997
10998         intel_mark_page_flip_active(intel_crtc->unpin_work);
10999         return 0;
11000 }
11001
11002 static int intel_gen4_queue_flip(struct drm_device *dev,
11003                                  struct drm_crtc *crtc,
11004                                  struct drm_framebuffer *fb,
11005                                  struct drm_i915_gem_object *obj,
11006                                  struct drm_i915_gem_request *req,
11007                                  uint32_t flags)
11008 {
11009         struct intel_engine_cs *ring = req->ring;
11010         struct drm_i915_private *dev_priv = dev->dev_private;
11011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11012         uint32_t pf, pipesrc;
11013         int ret;
11014
11015         ret = intel_ring_begin(req, 4);
11016         if (ret)
11017                 return ret;
11018
11019         /* i965+ uses the linear or tiled offsets from the
11020          * Display Registers (which do not change across a page-flip)
11021          * so we need only reprogram the base address.
11022          */
11023         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11024                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11025         intel_ring_emit(ring, fb->pitches[0]);
11026         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11027                         obj->tiling_mode);
11028
11029         /* XXX Enabling the panel-fitter across page-flip is so far
11030          * untested on non-native modes, so ignore it for now.
11031          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11032          */
11033         pf = 0;
11034         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11035         intel_ring_emit(ring, pf | pipesrc);
11036
11037         intel_mark_page_flip_active(intel_crtc->unpin_work);
11038         return 0;
11039 }
11040
11041 static int intel_gen6_queue_flip(struct drm_device *dev,
11042                                  struct drm_crtc *crtc,
11043                                  struct drm_framebuffer *fb,
11044                                  struct drm_i915_gem_object *obj,
11045                                  struct drm_i915_gem_request *req,
11046                                  uint32_t flags)
11047 {
11048         struct intel_engine_cs *ring = req->ring;
11049         struct drm_i915_private *dev_priv = dev->dev_private;
11050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11051         uint32_t pf, pipesrc;
11052         int ret;
11053
11054         ret = intel_ring_begin(req, 4);
11055         if (ret)
11056                 return ret;
11057
11058         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11059                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11060         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11061         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11062
11063         /* Contrary to the suggestions in the documentation,
11064          * "Enable Panel Fitter" does not seem to be required when page
11065          * flipping with a non-native mode, and worse causes a normal
11066          * modeset to fail.
11067          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11068          */
11069         pf = 0;
11070         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11071         intel_ring_emit(ring, pf | pipesrc);
11072
11073         intel_mark_page_flip_active(intel_crtc->unpin_work);
11074         return 0;
11075 }
11076
11077 static int intel_gen7_queue_flip(struct drm_device *dev,
11078                                  struct drm_crtc *crtc,
11079                                  struct drm_framebuffer *fb,
11080                                  struct drm_i915_gem_object *obj,
11081                                  struct drm_i915_gem_request *req,
11082                                  uint32_t flags)
11083 {
11084         struct intel_engine_cs *ring = req->ring;
11085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11086         uint32_t plane_bit = 0;
11087         int len, ret;
11088
11089         switch (intel_crtc->plane) {
11090         case PLANE_A:
11091                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11092                 break;
11093         case PLANE_B:
11094                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11095                 break;
11096         case PLANE_C:
11097                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11098                 break;
11099         default:
11100                 WARN_ONCE(1, "unknown plane in flip command\n");
11101                 return -ENODEV;
11102         }
11103
11104         len = 4;
11105         if (ring->id == RCS) {
11106                 len += 6;
11107                 /*
11108                  * On Gen 8, SRM is now taking an extra dword to accommodate
11109                  * 48bits addresses, and we need a NOOP for the batch size to
11110                  * stay even.
11111                  */
11112                 if (IS_GEN8(dev))
11113                         len += 2;
11114         }
11115
11116         /*
11117          * BSpec MI_DISPLAY_FLIP for IVB:
11118          * "The full packet must be contained within the same cache line."
11119          *
11120          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11121          * cacheline, if we ever start emitting more commands before
11122          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11123          * then do the cacheline alignment, and finally emit the
11124          * MI_DISPLAY_FLIP.
11125          */
11126         ret = intel_ring_cacheline_align(req);
11127         if (ret)
11128                 return ret;
11129
11130         ret = intel_ring_begin(req, len);
11131         if (ret)
11132                 return ret;
11133
11134         /* Unmask the flip-done completion message. Note that the bspec says that
11135          * we should do this for both the BCS and RCS, and that we must not unmask
11136          * more than one flip event at any time (or ensure that one flip message
11137          * can be sent by waiting for flip-done prior to queueing new flips).
11138          * Experimentation says that BCS works despite DERRMR masking all
11139          * flip-done completion events and that unmasking all planes at once
11140          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11141          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11142          */
11143         if (ring->id == RCS) {
11144                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11145                 intel_ring_emit_reg(ring, DERRMR);
11146                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11147                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11148                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11149                 if (IS_GEN8(dev))
11150                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11151                                               MI_SRM_LRM_GLOBAL_GTT);
11152                 else
11153                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11154                                               MI_SRM_LRM_GLOBAL_GTT);
11155                 intel_ring_emit_reg(ring, DERRMR);
11156                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11157                 if (IS_GEN8(dev)) {
11158                         intel_ring_emit(ring, 0);
11159                         intel_ring_emit(ring, MI_NOOP);
11160                 }
11161         }
11162
11163         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11164         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11165         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11166         intel_ring_emit(ring, (MI_NOOP));
11167
11168         intel_mark_page_flip_active(intel_crtc->unpin_work);
11169         return 0;
11170 }
11171
11172 static bool use_mmio_flip(struct intel_engine_cs *ring,
11173                           struct drm_i915_gem_object *obj)
11174 {
11175         /*
11176          * This is not being used for older platforms, because
11177          * non-availability of flip done interrupt forces us to use
11178          * CS flips. Older platforms derive flip done using some clever
11179          * tricks involving the flip_pending status bits and vblank irqs.
11180          * So using MMIO flips there would disrupt this mechanism.
11181          */
11182
11183         if (ring == NULL)
11184                 return true;
11185
11186         if (INTEL_INFO(ring->dev)->gen < 5)
11187                 return false;
11188
11189         if (i915.use_mmio_flip < 0)
11190                 return false;
11191         else if (i915.use_mmio_flip > 0)
11192                 return true;
11193         else if (i915.enable_execlists)
11194                 return true;
11195         else
11196                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11197 }
11198
11199 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11200                              unsigned int rotation,
11201                              struct intel_unpin_work *work)
11202 {
11203         struct drm_device *dev = intel_crtc->base.dev;
11204         struct drm_i915_private *dev_priv = dev->dev_private;
11205         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11206         const enum pipe pipe = intel_crtc->pipe;
11207         u32 ctl, stride, tile_height;
11208
11209         ctl = I915_READ(PLANE_CTL(pipe, 0));
11210         ctl &= ~PLANE_CTL_TILED_MASK;
11211         switch (fb->modifier[0]) {
11212         case DRM_FORMAT_MOD_NONE:
11213                 break;
11214         case I915_FORMAT_MOD_X_TILED:
11215                 ctl |= PLANE_CTL_TILED_X;
11216                 break;
11217         case I915_FORMAT_MOD_Y_TILED:
11218                 ctl |= PLANE_CTL_TILED_Y;
11219                 break;
11220         case I915_FORMAT_MOD_Yf_TILED:
11221                 ctl |= PLANE_CTL_TILED_YF;
11222                 break;
11223         default:
11224                 MISSING_CASE(fb->modifier[0]);
11225         }
11226
11227         /*
11228          * The stride is either expressed as a multiple of 64 bytes chunks for
11229          * linear buffers or in number of tiles for tiled buffers.
11230          */
11231         if (intel_rotation_90_or_270(rotation)) {
11232                 /* stride = Surface height in tiles */
11233                 tile_height = intel_tile_height(dev, fb->pixel_format,
11234                                                 fb->modifier[0], 0);
11235                 stride = DIV_ROUND_UP(fb->height, tile_height);
11236         } else {
11237                 stride = fb->pitches[0] /
11238                                 intel_fb_stride_alignment(dev, fb->modifier[0],
11239                                                           fb->pixel_format);
11240         }
11241
11242         /*
11243          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11244          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11245          */
11246         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11247         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11248
11249         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11250         POSTING_READ(PLANE_SURF(pipe, 0));
11251 }
11252
11253 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11254                              struct intel_unpin_work *work)
11255 {
11256         struct drm_device *dev = intel_crtc->base.dev;
11257         struct drm_i915_private *dev_priv = dev->dev_private;
11258         struct intel_framebuffer *intel_fb =
11259                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11260         struct drm_i915_gem_object *obj = intel_fb->obj;
11261         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11262         u32 dspcntr;
11263
11264         dspcntr = I915_READ(reg);
11265
11266         if (obj->tiling_mode != I915_TILING_NONE)
11267                 dspcntr |= DISPPLANE_TILED;
11268         else
11269                 dspcntr &= ~DISPPLANE_TILED;
11270
11271         I915_WRITE(reg, dspcntr);
11272
11273         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11274         POSTING_READ(DSPSURF(intel_crtc->plane));
11275 }
11276
11277 /*
11278  * XXX: This is the temporary way to update the plane registers until we get
11279  * around to using the usual plane update functions for MMIO flips
11280  */
11281 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11282 {
11283         struct intel_crtc *crtc = mmio_flip->crtc;
11284         struct intel_unpin_work *work;
11285
11286         spin_lock_irq(&crtc->base.dev->event_lock);
11287         work = crtc->unpin_work;
11288         spin_unlock_irq(&crtc->base.dev->event_lock);
11289         if (work == NULL)
11290                 return;
11291
11292         intel_mark_page_flip_active(work);
11293
11294         intel_pipe_update_start(crtc);
11295
11296         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11297                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11298         else
11299                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11300                 ilk_do_mmio_flip(crtc, work);
11301
11302         intel_pipe_update_end(crtc);
11303 }
11304
11305 static void intel_mmio_flip_work_func(struct work_struct *work)
11306 {
11307         struct intel_mmio_flip *mmio_flip =
11308                 container_of(work, struct intel_mmio_flip, work);
11309
11310         if (mmio_flip->req) {
11311                 WARN_ON(__i915_wait_request(mmio_flip->req,
11312                                             mmio_flip->crtc->reset_counter,
11313                                             false, NULL,
11314                                             &mmio_flip->i915->rps.mmioflips));
11315                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11316         }
11317
11318         intel_do_mmio_flip(mmio_flip);
11319         kfree(mmio_flip);
11320 }
11321
11322 static int intel_queue_mmio_flip(struct drm_device *dev,
11323                                  struct drm_crtc *crtc,
11324                                  struct drm_i915_gem_object *obj)
11325 {
11326         struct intel_mmio_flip *mmio_flip;
11327
11328         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11329         if (mmio_flip == NULL)
11330                 return -ENOMEM;
11331
11332         mmio_flip->i915 = to_i915(dev);
11333         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11334         mmio_flip->crtc = to_intel_crtc(crtc);
11335         mmio_flip->rotation = crtc->primary->state->rotation;
11336
11337         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11338         schedule_work(&mmio_flip->work);
11339
11340         return 0;
11341 }
11342
11343 static int intel_default_queue_flip(struct drm_device *dev,
11344                                     struct drm_crtc *crtc,
11345                                     struct drm_framebuffer *fb,
11346                                     struct drm_i915_gem_object *obj,
11347                                     struct drm_i915_gem_request *req,
11348                                     uint32_t flags)
11349 {
11350         return -ENODEV;
11351 }
11352
11353 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11354                                          struct drm_crtc *crtc)
11355 {
11356         struct drm_i915_private *dev_priv = dev->dev_private;
11357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11358         struct intel_unpin_work *work = intel_crtc->unpin_work;
11359         u32 addr;
11360
11361         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11362                 return true;
11363
11364         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11365                 return false;
11366
11367         if (!work->enable_stall_check)
11368                 return false;
11369
11370         if (work->flip_ready_vblank == 0) {
11371                 if (work->flip_queued_req &&
11372                     !i915_gem_request_completed(work->flip_queued_req, true))
11373                         return false;
11374
11375                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11376         }
11377
11378         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11379                 return false;
11380
11381         /* Potential stall - if we see that the flip has happened,
11382          * assume a missed interrupt. */
11383         if (INTEL_INFO(dev)->gen >= 4)
11384                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11385         else
11386                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11387
11388         /* There is a potential issue here with a false positive after a flip
11389          * to the same address. We could address this by checking for a
11390          * non-incrementing frame counter.
11391          */
11392         return addr == work->gtt_offset;
11393 }
11394
11395 void intel_check_page_flip(struct drm_device *dev, int pipe)
11396 {
11397         struct drm_i915_private *dev_priv = dev->dev_private;
11398         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11400         struct intel_unpin_work *work;
11401
11402         WARN_ON(!in_interrupt());
11403
11404         if (crtc == NULL)
11405                 return;
11406
11407         spin_lock(&dev->event_lock);
11408         work = intel_crtc->unpin_work;
11409         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11410                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11411                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11412                 page_flip_completed(intel_crtc);
11413                 work = NULL;
11414         }
11415         if (work != NULL &&
11416             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11417                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11418         spin_unlock(&dev->event_lock);
11419 }
11420
11421 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11422                                 struct drm_framebuffer *fb,
11423                                 struct drm_pending_vblank_event *event,
11424                                 uint32_t page_flip_flags)
11425 {
11426         struct drm_device *dev = crtc->dev;
11427         struct drm_i915_private *dev_priv = dev->dev_private;
11428         struct drm_framebuffer *old_fb = crtc->primary->fb;
11429         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11431         struct drm_plane *primary = crtc->primary;
11432         enum pipe pipe = intel_crtc->pipe;
11433         struct intel_unpin_work *work;
11434         struct intel_engine_cs *ring;
11435         bool mmio_flip;
11436         struct drm_i915_gem_request *request = NULL;
11437         int ret;
11438
11439         /*
11440          * drm_mode_page_flip_ioctl() should already catch this, but double
11441          * check to be safe.  In the future we may enable pageflipping from
11442          * a disabled primary plane.
11443          */
11444         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11445                 return -EBUSY;
11446
11447         /* Can't change pixel format via MI display flips. */
11448         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11449                 return -EINVAL;
11450
11451         /*
11452          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11453          * Note that pitch changes could also affect these register.
11454          */
11455         if (INTEL_INFO(dev)->gen > 3 &&
11456             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11457              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11458                 return -EINVAL;
11459
11460         if (i915_terminally_wedged(&dev_priv->gpu_error))
11461                 goto out_hang;
11462
11463         work = kzalloc(sizeof(*work), GFP_KERNEL);
11464         if (work == NULL)
11465                 return -ENOMEM;
11466
11467         work->event = event;
11468         work->crtc = crtc;
11469         work->old_fb = old_fb;
11470         INIT_WORK(&work->work, intel_unpin_work_fn);
11471
11472         ret = drm_crtc_vblank_get(crtc);
11473         if (ret)
11474                 goto free_work;
11475
11476         /* We borrow the event spin lock for protecting unpin_work */
11477         spin_lock_irq(&dev->event_lock);
11478         if (intel_crtc->unpin_work) {
11479                 /* Before declaring the flip queue wedged, check if
11480                  * the hardware completed the operation behind our backs.
11481                  */
11482                 if (__intel_pageflip_stall_check(dev, crtc)) {
11483                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11484                         page_flip_completed(intel_crtc);
11485                 } else {
11486                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11487                         spin_unlock_irq(&dev->event_lock);
11488
11489                         drm_crtc_vblank_put(crtc);
11490                         kfree(work);
11491                         return -EBUSY;
11492                 }
11493         }
11494         intel_crtc->unpin_work = work;
11495         spin_unlock_irq(&dev->event_lock);
11496
11497         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11498                 flush_workqueue(dev_priv->wq);
11499
11500         /* Reference the objects for the scheduled work. */
11501         drm_framebuffer_reference(work->old_fb);
11502         drm_gem_object_reference(&obj->base);
11503
11504         crtc->primary->fb = fb;
11505         update_state_fb(crtc->primary);
11506
11507         work->pending_flip_obj = obj;
11508
11509         ret = i915_mutex_lock_interruptible(dev);
11510         if (ret)
11511                 goto cleanup;
11512
11513         atomic_inc(&intel_crtc->unpin_work_count);
11514         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11515
11516         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11517                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11518
11519         if (IS_VALLEYVIEW(dev)) {
11520                 ring = &dev_priv->ring[BCS];
11521                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11522                         /* vlv: DISPLAY_FLIP fails to change tiling */
11523                         ring = NULL;
11524         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11525                 ring = &dev_priv->ring[BCS];
11526         } else if (INTEL_INFO(dev)->gen >= 7) {
11527                 ring = i915_gem_request_get_ring(obj->last_write_req);
11528                 if (ring == NULL || ring->id != RCS)
11529                         ring = &dev_priv->ring[BCS];
11530         } else {
11531                 ring = &dev_priv->ring[RCS];
11532         }
11533
11534         mmio_flip = use_mmio_flip(ring, obj);
11535
11536         /* When using CS flips, we want to emit semaphores between rings.
11537          * However, when using mmio flips we will create a task to do the
11538          * synchronisation, so all we want here is to pin the framebuffer
11539          * into the display plane and skip any waits.
11540          */
11541         if (!mmio_flip) {
11542                 ret = i915_gem_object_sync(obj, ring, &request);
11543                 if (ret)
11544                         goto cleanup_pending;
11545         }
11546
11547         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11548                                          crtc->primary->state);
11549         if (ret)
11550                 goto cleanup_pending;
11551
11552         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11553                                                   obj, 0);
11554         work->gtt_offset += intel_crtc->dspaddr_offset;
11555
11556         if (mmio_flip) {
11557                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11558                 if (ret)
11559                         goto cleanup_unpin;
11560
11561                 i915_gem_request_assign(&work->flip_queued_req,
11562                                         obj->last_write_req);
11563         } else {
11564                 if (!request) {
11565                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11566                         if (ret)
11567                                 goto cleanup_unpin;
11568                 }
11569
11570                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11571                                                    page_flip_flags);
11572                 if (ret)
11573                         goto cleanup_unpin;
11574
11575                 i915_gem_request_assign(&work->flip_queued_req, request);
11576         }
11577
11578         if (request)
11579                 i915_add_request_no_flush(request);
11580
11581         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11582         work->enable_stall_check = true;
11583
11584         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11585                           to_intel_plane(primary)->frontbuffer_bit);
11586         mutex_unlock(&dev->struct_mutex);
11587
11588         intel_fbc_disable_crtc(intel_crtc);
11589         intel_frontbuffer_flip_prepare(dev,
11590                                        to_intel_plane(primary)->frontbuffer_bit);
11591
11592         trace_i915_flip_request(intel_crtc->plane, obj);
11593
11594         return 0;
11595
11596 cleanup_unpin:
11597         intel_unpin_fb_obj(fb, crtc->primary->state);
11598 cleanup_pending:
11599         if (request)
11600                 i915_gem_request_cancel(request);
11601         atomic_dec(&intel_crtc->unpin_work_count);
11602         mutex_unlock(&dev->struct_mutex);
11603 cleanup:
11604         crtc->primary->fb = old_fb;
11605         update_state_fb(crtc->primary);
11606
11607         drm_gem_object_unreference_unlocked(&obj->base);
11608         drm_framebuffer_unreference(work->old_fb);
11609
11610         spin_lock_irq(&dev->event_lock);
11611         intel_crtc->unpin_work = NULL;
11612         spin_unlock_irq(&dev->event_lock);
11613
11614         drm_crtc_vblank_put(crtc);
11615 free_work:
11616         kfree(work);
11617
11618         if (ret == -EIO) {
11619                 struct drm_atomic_state *state;
11620                 struct drm_plane_state *plane_state;
11621
11622 out_hang:
11623                 state = drm_atomic_state_alloc(dev);
11624                 if (!state)
11625                         return -ENOMEM;
11626                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11627
11628 retry:
11629                 plane_state = drm_atomic_get_plane_state(state, primary);
11630                 ret = PTR_ERR_OR_ZERO(plane_state);
11631                 if (!ret) {
11632                         drm_atomic_set_fb_for_plane(plane_state, fb);
11633
11634                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11635                         if (!ret)
11636                                 ret = drm_atomic_commit(state);
11637                 }
11638
11639                 if (ret == -EDEADLK) {
11640                         drm_modeset_backoff(state->acquire_ctx);
11641                         drm_atomic_state_clear(state);
11642                         goto retry;
11643                 }
11644
11645                 if (ret)
11646                         drm_atomic_state_free(state);
11647
11648                 if (ret == 0 && event) {
11649                         spin_lock_irq(&dev->event_lock);
11650                         drm_send_vblank_event(dev, pipe, event);
11651                         spin_unlock_irq(&dev->event_lock);
11652                 }
11653         }
11654         return ret;
11655 }
11656
11657
11658 /**
11659  * intel_wm_need_update - Check whether watermarks need updating
11660  * @plane: drm plane
11661  * @state: new plane state
11662  *
11663  * Check current plane state versus the new one to determine whether
11664  * watermarks need to be recalculated.
11665  *
11666  * Returns true or false.
11667  */
11668 static bool intel_wm_need_update(struct drm_plane *plane,
11669                                  struct drm_plane_state *state)
11670 {
11671         struct intel_plane_state *new = to_intel_plane_state(state);
11672         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11673
11674         /* Update watermarks on tiling or size changes. */
11675         if (!plane->state->fb || !state->fb ||
11676             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11677             plane->state->rotation != state->rotation ||
11678             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11679             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11680             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11681             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11682                 return true;
11683
11684         return false;
11685 }
11686
11687 static bool needs_scaling(struct intel_plane_state *state)
11688 {
11689         int src_w = drm_rect_width(&state->src) >> 16;
11690         int src_h = drm_rect_height(&state->src) >> 16;
11691         int dst_w = drm_rect_width(&state->dst);
11692         int dst_h = drm_rect_height(&state->dst);
11693
11694         return (src_w != dst_w || src_h != dst_h);
11695 }
11696
11697 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11698                                     struct drm_plane_state *plane_state)
11699 {
11700         struct drm_crtc *crtc = crtc_state->crtc;
11701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11702         struct drm_plane *plane = plane_state->plane;
11703         struct drm_device *dev = crtc->dev;
11704         struct drm_i915_private *dev_priv = dev->dev_private;
11705         struct intel_plane_state *old_plane_state =
11706                 to_intel_plane_state(plane->state);
11707         int idx = intel_crtc->base.base.id, ret;
11708         int i = drm_plane_index(plane);
11709         bool mode_changed = needs_modeset(crtc_state);
11710         bool was_crtc_enabled = crtc->state->active;
11711         bool is_crtc_enabled = crtc_state->active;
11712         bool turn_off, turn_on, visible, was_visible;
11713         struct drm_framebuffer *fb = plane_state->fb;
11714
11715         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11716             plane->type != DRM_PLANE_TYPE_CURSOR) {
11717                 ret = skl_update_scaler_plane(
11718                         to_intel_crtc_state(crtc_state),
11719                         to_intel_plane_state(plane_state));
11720                 if (ret)
11721                         return ret;
11722         }
11723
11724         was_visible = old_plane_state->visible;
11725         visible = to_intel_plane_state(plane_state)->visible;
11726
11727         if (!was_crtc_enabled && WARN_ON(was_visible))
11728                 was_visible = false;
11729
11730         if (!is_crtc_enabled && WARN_ON(visible))
11731                 visible = false;
11732
11733         if (!was_visible && !visible)
11734                 return 0;
11735
11736         turn_off = was_visible && (!visible || mode_changed);
11737         turn_on = visible && (!was_visible || mode_changed);
11738
11739         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11740                          plane->base.id, fb ? fb->base.id : -1);
11741
11742         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11743                          plane->base.id, was_visible, visible,
11744                          turn_off, turn_on, mode_changed);
11745
11746         if (turn_on) {
11747                 intel_crtc->atomic.update_wm_pre = true;
11748                 /* must disable cxsr around plane enable/disable */
11749                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11750                         intel_crtc->atomic.disable_cxsr = true;
11751                         /* to potentially re-enable cxsr */
11752                         intel_crtc->atomic.wait_vblank = true;
11753                         intel_crtc->atomic.update_wm_post = true;
11754                 }
11755         } else if (turn_off) {
11756                 intel_crtc->atomic.update_wm_post = true;
11757                 /* must disable cxsr around plane enable/disable */
11758                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11759                         if (is_crtc_enabled)
11760                                 intel_crtc->atomic.wait_vblank = true;
11761                         intel_crtc->atomic.disable_cxsr = true;
11762                 }
11763         } else if (intel_wm_need_update(plane, plane_state)) {
11764                 intel_crtc->atomic.update_wm_pre = true;
11765         }
11766
11767         if (visible || was_visible)
11768                 intel_crtc->atomic.fb_bits |=
11769                         to_intel_plane(plane)->frontbuffer_bit;
11770
11771         switch (plane->type) {
11772         case DRM_PLANE_TYPE_PRIMARY:
11773                 intel_crtc->atomic.pre_disable_primary = turn_off;
11774                 intel_crtc->atomic.post_enable_primary = turn_on;
11775
11776                 if (turn_off) {
11777                         /*
11778                          * FIXME: Actually if we will still have any other
11779                          * plane enabled on the pipe we could let IPS enabled
11780                          * still, but for now lets consider that when we make
11781                          * primary invisible by setting DSPCNTR to 0 on
11782                          * update_primary_plane function IPS needs to be
11783                          * disable.
11784                          */
11785                         intel_crtc->atomic.disable_ips = true;
11786
11787                         intel_crtc->atomic.disable_fbc = true;
11788                 }
11789
11790                 /*
11791                  * FBC does not work on some platforms for rotated
11792                  * planes, so disable it when rotation is not 0 and
11793                  * update it when rotation is set back to 0.
11794                  *
11795                  * FIXME: This is redundant with the fbc update done in
11796                  * the primary plane enable function except that that
11797                  * one is done too late. We eventually need to unify
11798                  * this.
11799                  */
11800
11801                 if (visible &&
11802                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11803                     dev_priv->fbc.crtc == intel_crtc &&
11804                     plane_state->rotation != BIT(DRM_ROTATE_0))
11805                         intel_crtc->atomic.disable_fbc = true;
11806
11807                 /*
11808                  * BDW signals flip done immediately if the plane
11809                  * is disabled, even if the plane enable is already
11810                  * armed to occur at the next vblank :(
11811                  */
11812                 if (turn_on && IS_BROADWELL(dev))
11813                         intel_crtc->atomic.wait_vblank = true;
11814
11815                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11816                 break;
11817         case DRM_PLANE_TYPE_CURSOR:
11818                 break;
11819         case DRM_PLANE_TYPE_OVERLAY:
11820                 /*
11821                  * WaCxSRDisabledForSpriteScaling:ivb
11822                  *
11823                  * cstate->update_wm was already set above, so this flag will
11824                  * take effect when we commit and program watermarks.
11825                  */
11826                 if (IS_IVYBRIDGE(dev) &&
11827                     needs_scaling(to_intel_plane_state(plane_state)) &&
11828                     !needs_scaling(old_plane_state)) {
11829                         to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11830                 } else if (turn_off && !mode_changed) {
11831                         intel_crtc->atomic.wait_vblank = true;
11832                         intel_crtc->atomic.update_sprite_watermarks |=
11833                                 1 << i;
11834                 }
11835
11836                 break;
11837         }
11838         return 0;
11839 }
11840
11841 static bool encoders_cloneable(const struct intel_encoder *a,
11842                                const struct intel_encoder *b)
11843 {
11844         /* masks could be asymmetric, so check both ways */
11845         return a == b || (a->cloneable & (1 << b->type) &&
11846                           b->cloneable & (1 << a->type));
11847 }
11848
11849 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11850                                          struct intel_crtc *crtc,
11851                                          struct intel_encoder *encoder)
11852 {
11853         struct intel_encoder *source_encoder;
11854         struct drm_connector *connector;
11855         struct drm_connector_state *connector_state;
11856         int i;
11857
11858         for_each_connector_in_state(state, connector, connector_state, i) {
11859                 if (connector_state->crtc != &crtc->base)
11860                         continue;
11861
11862                 source_encoder =
11863                         to_intel_encoder(connector_state->best_encoder);
11864                 if (!encoders_cloneable(encoder, source_encoder))
11865                         return false;
11866         }
11867
11868         return true;
11869 }
11870
11871 static bool check_encoder_cloning(struct drm_atomic_state *state,
11872                                   struct intel_crtc *crtc)
11873 {
11874         struct intel_encoder *encoder;
11875         struct drm_connector *connector;
11876         struct drm_connector_state *connector_state;
11877         int i;
11878
11879         for_each_connector_in_state(state, connector, connector_state, i) {
11880                 if (connector_state->crtc != &crtc->base)
11881                         continue;
11882
11883                 encoder = to_intel_encoder(connector_state->best_encoder);
11884                 if (!check_single_encoder_cloning(state, crtc, encoder))
11885                         return false;
11886         }
11887
11888         return true;
11889 }
11890
11891 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11892                                    struct drm_crtc_state *crtc_state)
11893 {
11894         struct drm_device *dev = crtc->dev;
11895         struct drm_i915_private *dev_priv = dev->dev_private;
11896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11897         struct intel_crtc_state *pipe_config =
11898                 to_intel_crtc_state(crtc_state);
11899         struct drm_atomic_state *state = crtc_state->state;
11900         int ret;
11901         bool mode_changed = needs_modeset(crtc_state);
11902
11903         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11904                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11905                 return -EINVAL;
11906         }
11907
11908         if (mode_changed && !crtc_state->active)
11909                 intel_crtc->atomic.update_wm_post = true;
11910
11911         if (mode_changed && crtc_state->enable &&
11912             dev_priv->display.crtc_compute_clock &&
11913             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11914                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11915                                                            pipe_config);
11916                 if (ret)
11917                         return ret;
11918         }
11919
11920         ret = 0;
11921         if (dev_priv->display.compute_pipe_wm) {
11922                 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11923                 if (ret)
11924                         return ret;
11925         }
11926
11927         if (INTEL_INFO(dev)->gen >= 9) {
11928                 if (mode_changed)
11929                         ret = skl_update_scaler_crtc(pipe_config);
11930
11931                 if (!ret)
11932                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11933                                                          pipe_config);
11934         }
11935
11936         return ret;
11937 }
11938
11939 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11940         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11941         .load_lut = intel_crtc_load_lut,
11942         .atomic_begin = intel_begin_crtc_commit,
11943         .atomic_flush = intel_finish_crtc_commit,
11944         .atomic_check = intel_crtc_atomic_check,
11945 };
11946
11947 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11948 {
11949         struct intel_connector *connector;
11950
11951         for_each_intel_connector(dev, connector) {
11952                 if (connector->base.encoder) {
11953                         connector->base.state->best_encoder =
11954                                 connector->base.encoder;
11955                         connector->base.state->crtc =
11956                                 connector->base.encoder->crtc;
11957                 } else {
11958                         connector->base.state->best_encoder = NULL;
11959                         connector->base.state->crtc = NULL;
11960                 }
11961         }
11962 }
11963
11964 static void
11965 connected_sink_compute_bpp(struct intel_connector *connector,
11966                            struct intel_crtc_state *pipe_config)
11967 {
11968         int bpp = pipe_config->pipe_bpp;
11969
11970         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11971                 connector->base.base.id,
11972                 connector->base.name);
11973
11974         /* Don't use an invalid EDID bpc value */
11975         if (connector->base.display_info.bpc &&
11976             connector->base.display_info.bpc * 3 < bpp) {
11977                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11978                               bpp, connector->base.display_info.bpc*3);
11979                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11980         }
11981
11982         /* Clamp bpp to 8 on screens without EDID 1.4 */
11983         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11984                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11985                               bpp);
11986                 pipe_config->pipe_bpp = 24;
11987         }
11988 }
11989
11990 static int
11991 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11992                           struct intel_crtc_state *pipe_config)
11993 {
11994         struct drm_device *dev = crtc->base.dev;
11995         struct drm_atomic_state *state;
11996         struct drm_connector *connector;
11997         struct drm_connector_state *connector_state;
11998         int bpp, i;
11999
12000         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
12001                 bpp = 10*3;
12002         else if (INTEL_INFO(dev)->gen >= 5)
12003                 bpp = 12*3;
12004         else
12005                 bpp = 8*3;
12006
12007
12008         pipe_config->pipe_bpp = bpp;
12009
12010         state = pipe_config->base.state;
12011
12012         /* Clamp display bpp to EDID value */
12013         for_each_connector_in_state(state, connector, connector_state, i) {
12014                 if (connector_state->crtc != &crtc->base)
12015                         continue;
12016
12017                 connected_sink_compute_bpp(to_intel_connector(connector),
12018                                            pipe_config);
12019         }
12020
12021         return bpp;
12022 }
12023
12024 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12025 {
12026         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12027                         "type: 0x%x flags: 0x%x\n",
12028                 mode->crtc_clock,
12029                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12030                 mode->crtc_hsync_end, mode->crtc_htotal,
12031                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12032                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12033 }
12034
12035 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12036                                    struct intel_crtc_state *pipe_config,
12037                                    const char *context)
12038 {
12039         struct drm_device *dev = crtc->base.dev;
12040         struct drm_plane *plane;
12041         struct intel_plane *intel_plane;
12042         struct intel_plane_state *state;
12043         struct drm_framebuffer *fb;
12044
12045         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12046                       context, pipe_config, pipe_name(crtc->pipe));
12047
12048         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12049         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12050                       pipe_config->pipe_bpp, pipe_config->dither);
12051         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12052                       pipe_config->has_pch_encoder,
12053                       pipe_config->fdi_lanes,
12054                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12055                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12056                       pipe_config->fdi_m_n.tu);
12057         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12058                       pipe_config->has_dp_encoder,
12059                       pipe_config->lane_count,
12060                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12061                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12062                       pipe_config->dp_m_n.tu);
12063
12064         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12065                       pipe_config->has_dp_encoder,
12066                       pipe_config->lane_count,
12067                       pipe_config->dp_m2_n2.gmch_m,
12068                       pipe_config->dp_m2_n2.gmch_n,
12069                       pipe_config->dp_m2_n2.link_m,
12070                       pipe_config->dp_m2_n2.link_n,
12071                       pipe_config->dp_m2_n2.tu);
12072
12073         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12074                       pipe_config->has_audio,
12075                       pipe_config->has_infoframe);
12076
12077         DRM_DEBUG_KMS("requested mode:\n");
12078         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12079         DRM_DEBUG_KMS("adjusted mode:\n");
12080         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12081         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12082         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12083         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12084                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12085         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12086                       crtc->num_scalers,
12087                       pipe_config->scaler_state.scaler_users,
12088                       pipe_config->scaler_state.scaler_id);
12089         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12090                       pipe_config->gmch_pfit.control,
12091                       pipe_config->gmch_pfit.pgm_ratios,
12092                       pipe_config->gmch_pfit.lvds_border_bits);
12093         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12094                       pipe_config->pch_pfit.pos,
12095                       pipe_config->pch_pfit.size,
12096                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12097         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12098         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12099
12100         if (IS_BROXTON(dev)) {
12101                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12102                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12103                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12104                               pipe_config->ddi_pll_sel,
12105                               pipe_config->dpll_hw_state.ebb0,
12106                               pipe_config->dpll_hw_state.ebb4,
12107                               pipe_config->dpll_hw_state.pll0,
12108                               pipe_config->dpll_hw_state.pll1,
12109                               pipe_config->dpll_hw_state.pll2,
12110                               pipe_config->dpll_hw_state.pll3,
12111                               pipe_config->dpll_hw_state.pll6,
12112                               pipe_config->dpll_hw_state.pll8,
12113                               pipe_config->dpll_hw_state.pll9,
12114                               pipe_config->dpll_hw_state.pll10,
12115                               pipe_config->dpll_hw_state.pcsdw12);
12116         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12117                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12118                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12119                               pipe_config->ddi_pll_sel,
12120                               pipe_config->dpll_hw_state.ctrl1,
12121                               pipe_config->dpll_hw_state.cfgcr1,
12122                               pipe_config->dpll_hw_state.cfgcr2);
12123         } else if (HAS_DDI(dev)) {
12124                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12125                               pipe_config->ddi_pll_sel,
12126                               pipe_config->dpll_hw_state.wrpll,
12127                               pipe_config->dpll_hw_state.spll);
12128         } else {
12129                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12130                               "fp0: 0x%x, fp1: 0x%x\n",
12131                               pipe_config->dpll_hw_state.dpll,
12132                               pipe_config->dpll_hw_state.dpll_md,
12133                               pipe_config->dpll_hw_state.fp0,
12134                               pipe_config->dpll_hw_state.fp1);
12135         }
12136
12137         DRM_DEBUG_KMS("planes on this crtc\n");
12138         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12139                 intel_plane = to_intel_plane(plane);
12140                 if (intel_plane->pipe != crtc->pipe)
12141                         continue;
12142
12143                 state = to_intel_plane_state(plane->state);
12144                 fb = state->base.fb;
12145                 if (!fb) {
12146                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12147                                 "disabled, scaler_id = %d\n",
12148                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12149                                 plane->base.id, intel_plane->pipe,
12150                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12151                                 drm_plane_index(plane), state->scaler_id);
12152                         continue;
12153                 }
12154
12155                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12156                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12157                         plane->base.id, intel_plane->pipe,
12158                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12159                         drm_plane_index(plane));
12160                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12161                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12162                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12163                         state->scaler_id,
12164                         state->src.x1 >> 16, state->src.y1 >> 16,
12165                         drm_rect_width(&state->src) >> 16,
12166                         drm_rect_height(&state->src) >> 16,
12167                         state->dst.x1, state->dst.y1,
12168                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12169         }
12170 }
12171
12172 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12173 {
12174         struct drm_device *dev = state->dev;
12175         struct intel_encoder *encoder;
12176         struct drm_connector *connector;
12177         struct drm_connector_state *connector_state;
12178         unsigned int used_ports = 0;
12179         int i;
12180
12181         /*
12182          * Walk the connector list instead of the encoder
12183          * list to detect the problem on ddi platforms
12184          * where there's just one encoder per digital port.
12185          */
12186         for_each_connector_in_state(state, connector, connector_state, i) {
12187                 if (!connector_state->best_encoder)
12188                         continue;
12189
12190                 encoder = to_intel_encoder(connector_state->best_encoder);
12191
12192                 WARN_ON(!connector_state->crtc);
12193
12194                 switch (encoder->type) {
12195                         unsigned int port_mask;
12196                 case INTEL_OUTPUT_UNKNOWN:
12197                         if (WARN_ON(!HAS_DDI(dev)))
12198                                 break;
12199                 case INTEL_OUTPUT_DISPLAYPORT:
12200                 case INTEL_OUTPUT_HDMI:
12201                 case INTEL_OUTPUT_EDP:
12202                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12203
12204                         /* the same port mustn't appear more than once */
12205                         if (used_ports & port_mask)
12206                                 return false;
12207
12208                         used_ports |= port_mask;
12209                 default:
12210                         break;
12211                 }
12212         }
12213
12214         return true;
12215 }
12216
12217 static void
12218 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12219 {
12220         struct drm_crtc_state tmp_state;
12221         struct intel_crtc_scaler_state scaler_state;
12222         struct intel_dpll_hw_state dpll_hw_state;
12223         enum intel_dpll_id shared_dpll;
12224         uint32_t ddi_pll_sel;
12225         bool force_thru;
12226
12227         /* FIXME: before the switch to atomic started, a new pipe_config was
12228          * kzalloc'd. Code that depends on any field being zero should be
12229          * fixed, so that the crtc_state can be safely duplicated. For now,
12230          * only fields that are know to not cause problems are preserved. */
12231
12232         tmp_state = crtc_state->base;
12233         scaler_state = crtc_state->scaler_state;
12234         shared_dpll = crtc_state->shared_dpll;
12235         dpll_hw_state = crtc_state->dpll_hw_state;
12236         ddi_pll_sel = crtc_state->ddi_pll_sel;
12237         force_thru = crtc_state->pch_pfit.force_thru;
12238
12239         memset(crtc_state, 0, sizeof *crtc_state);
12240
12241         crtc_state->base = tmp_state;
12242         crtc_state->scaler_state = scaler_state;
12243         crtc_state->shared_dpll = shared_dpll;
12244         crtc_state->dpll_hw_state = dpll_hw_state;
12245         crtc_state->ddi_pll_sel = ddi_pll_sel;
12246         crtc_state->pch_pfit.force_thru = force_thru;
12247 }
12248
12249 static int
12250 intel_modeset_pipe_config(struct drm_crtc *crtc,
12251                           struct intel_crtc_state *pipe_config)
12252 {
12253         struct drm_atomic_state *state = pipe_config->base.state;
12254         struct intel_encoder *encoder;
12255         struct drm_connector *connector;
12256         struct drm_connector_state *connector_state;
12257         int base_bpp, ret = -EINVAL;
12258         int i;
12259         bool retry = true;
12260
12261         clear_intel_crtc_state(pipe_config);
12262
12263         pipe_config->cpu_transcoder =
12264                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12265
12266         /*
12267          * Sanitize sync polarity flags based on requested ones. If neither
12268          * positive or negative polarity is requested, treat this as meaning
12269          * negative polarity.
12270          */
12271         if (!(pipe_config->base.adjusted_mode.flags &
12272               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12273                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12274
12275         if (!(pipe_config->base.adjusted_mode.flags &
12276               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12277                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12278
12279         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12280                                              pipe_config);
12281         if (base_bpp < 0)
12282                 goto fail;
12283
12284         /*
12285          * Determine the real pipe dimensions. Note that stereo modes can
12286          * increase the actual pipe size due to the frame doubling and
12287          * insertion of additional space for blanks between the frame. This
12288          * is stored in the crtc timings. We use the requested mode to do this
12289          * computation to clearly distinguish it from the adjusted mode, which
12290          * can be changed by the connectors in the below retry loop.
12291          */
12292         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12293                                &pipe_config->pipe_src_w,
12294                                &pipe_config->pipe_src_h);
12295
12296 encoder_retry:
12297         /* Ensure the port clock defaults are reset when retrying. */
12298         pipe_config->port_clock = 0;
12299         pipe_config->pixel_multiplier = 1;
12300
12301         /* Fill in default crtc timings, allow encoders to overwrite them. */
12302         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12303                               CRTC_STEREO_DOUBLE);
12304
12305         /* Pass our mode to the connectors and the CRTC to give them a chance to
12306          * adjust it according to limitations or connector properties, and also
12307          * a chance to reject the mode entirely.
12308          */
12309         for_each_connector_in_state(state, connector, connector_state, i) {
12310                 if (connector_state->crtc != crtc)
12311                         continue;
12312
12313                 encoder = to_intel_encoder(connector_state->best_encoder);
12314
12315                 if (!(encoder->compute_config(encoder, pipe_config))) {
12316                         DRM_DEBUG_KMS("Encoder config failure\n");
12317                         goto fail;
12318                 }
12319         }
12320
12321         /* Set default port clock if not overwritten by the encoder. Needs to be
12322          * done afterwards in case the encoder adjusts the mode. */
12323         if (!pipe_config->port_clock)
12324                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12325                         * pipe_config->pixel_multiplier;
12326
12327         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12328         if (ret < 0) {
12329                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12330                 goto fail;
12331         }
12332
12333         if (ret == RETRY) {
12334                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12335                         ret = -EINVAL;
12336                         goto fail;
12337                 }
12338
12339                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12340                 retry = false;
12341                 goto encoder_retry;
12342         }
12343
12344         /* Dithering seems to not pass-through bits correctly when it should, so
12345          * only enable it on 6bpc panels. */
12346         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12347         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12348                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12349
12350 fail:
12351         return ret;
12352 }
12353
12354 static void
12355 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12356 {
12357         struct drm_crtc *crtc;
12358         struct drm_crtc_state *crtc_state;
12359         int i;
12360
12361         /* Double check state. */
12362         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12363                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12364
12365                 /* Update hwmode for vblank functions */
12366                 if (crtc->state->active)
12367                         crtc->hwmode = crtc->state->adjusted_mode;
12368                 else
12369                         crtc->hwmode.crtc_clock = 0;
12370
12371                 /*
12372                  * Update legacy state to satisfy fbc code. This can
12373                  * be removed when fbc uses the atomic state.
12374                  */
12375                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12376                         struct drm_plane_state *plane_state = crtc->primary->state;
12377
12378                         crtc->primary->fb = plane_state->fb;
12379                         crtc->x = plane_state->src_x >> 16;
12380                         crtc->y = plane_state->src_y >> 16;
12381                 }
12382         }
12383 }
12384
12385 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12386 {
12387         int diff;
12388
12389         if (clock1 == clock2)
12390                 return true;
12391
12392         if (!clock1 || !clock2)
12393                 return false;
12394
12395         diff = abs(clock1 - clock2);
12396
12397         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12398                 return true;
12399
12400         return false;
12401 }
12402
12403 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12404         list_for_each_entry((intel_crtc), \
12405                             &(dev)->mode_config.crtc_list, \
12406                             base.head) \
12407                 if (mask & (1 <<(intel_crtc)->pipe))
12408
12409 static bool
12410 intel_compare_m_n(unsigned int m, unsigned int n,
12411                   unsigned int m2, unsigned int n2,
12412                   bool exact)
12413 {
12414         if (m == m2 && n == n2)
12415                 return true;
12416
12417         if (exact || !m || !n || !m2 || !n2)
12418                 return false;
12419
12420         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12421
12422         if (m > m2) {
12423                 while (m > m2) {
12424                         m2 <<= 1;
12425                         n2 <<= 1;
12426                 }
12427         } else if (m < m2) {
12428                 while (m < m2) {
12429                         m <<= 1;
12430                         n <<= 1;
12431                 }
12432         }
12433
12434         return m == m2 && n == n2;
12435 }
12436
12437 static bool
12438 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12439                        struct intel_link_m_n *m2_n2,
12440                        bool adjust)
12441 {
12442         if (m_n->tu == m2_n2->tu &&
12443             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12444                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12445             intel_compare_m_n(m_n->link_m, m_n->link_n,
12446                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12447                 if (adjust)
12448                         *m2_n2 = *m_n;
12449
12450                 return true;
12451         }
12452
12453         return false;
12454 }
12455
12456 static bool
12457 intel_pipe_config_compare(struct drm_device *dev,
12458                           struct intel_crtc_state *current_config,
12459                           struct intel_crtc_state *pipe_config,
12460                           bool adjust)
12461 {
12462         bool ret = true;
12463
12464 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12465         do { \
12466                 if (!adjust) \
12467                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12468                 else \
12469                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12470         } while (0)
12471
12472 #define PIPE_CONF_CHECK_X(name) \
12473         if (current_config->name != pipe_config->name) { \
12474                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12475                           "(expected 0x%08x, found 0x%08x)\n", \
12476                           current_config->name, \
12477                           pipe_config->name); \
12478                 ret = false; \
12479         }
12480
12481 #define PIPE_CONF_CHECK_I(name) \
12482         if (current_config->name != pipe_config->name) { \
12483                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12484                           "(expected %i, found %i)\n", \
12485                           current_config->name, \
12486                           pipe_config->name); \
12487                 ret = false; \
12488         }
12489
12490 #define PIPE_CONF_CHECK_M_N(name) \
12491         if (!intel_compare_link_m_n(&current_config->name, \
12492                                     &pipe_config->name,\
12493                                     adjust)) { \
12494                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12495                           "(expected tu %i gmch %i/%i link %i/%i, " \
12496                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12497                           current_config->name.tu, \
12498                           current_config->name.gmch_m, \
12499                           current_config->name.gmch_n, \
12500                           current_config->name.link_m, \
12501                           current_config->name.link_n, \
12502                           pipe_config->name.tu, \
12503                           pipe_config->name.gmch_m, \
12504                           pipe_config->name.gmch_n, \
12505                           pipe_config->name.link_m, \
12506                           pipe_config->name.link_n); \
12507                 ret = false; \
12508         }
12509
12510 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12511         if (!intel_compare_link_m_n(&current_config->name, \
12512                                     &pipe_config->name, adjust) && \
12513             !intel_compare_link_m_n(&current_config->alt_name, \
12514                                     &pipe_config->name, adjust)) { \
12515                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12516                           "(expected tu %i gmch %i/%i link %i/%i, " \
12517                           "or tu %i gmch %i/%i link %i/%i, " \
12518                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12519                           current_config->name.tu, \
12520                           current_config->name.gmch_m, \
12521                           current_config->name.gmch_n, \
12522                           current_config->name.link_m, \
12523                           current_config->name.link_n, \
12524                           current_config->alt_name.tu, \
12525                           current_config->alt_name.gmch_m, \
12526                           current_config->alt_name.gmch_n, \
12527                           current_config->alt_name.link_m, \
12528                           current_config->alt_name.link_n, \
12529                           pipe_config->name.tu, \
12530                           pipe_config->name.gmch_m, \
12531                           pipe_config->name.gmch_n, \
12532                           pipe_config->name.link_m, \
12533                           pipe_config->name.link_n); \
12534                 ret = false; \
12535         }
12536
12537 /* This is required for BDW+ where there is only one set of registers for
12538  * switching between high and low RR.
12539  * This macro can be used whenever a comparison has to be made between one
12540  * hw state and multiple sw state variables.
12541  */
12542 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12543         if ((current_config->name != pipe_config->name) && \
12544                 (current_config->alt_name != pipe_config->name)) { \
12545                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12546                                   "(expected %i or %i, found %i)\n", \
12547                                   current_config->name, \
12548                                   current_config->alt_name, \
12549                                   pipe_config->name); \
12550                         ret = false; \
12551         }
12552
12553 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12554         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12555                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12556                           "(expected %i, found %i)\n", \
12557                           current_config->name & (mask), \
12558                           pipe_config->name & (mask)); \
12559                 ret = false; \
12560         }
12561
12562 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12563         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12564                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12565                           "(expected %i, found %i)\n", \
12566                           current_config->name, \
12567                           pipe_config->name); \
12568                 ret = false; \
12569         }
12570
12571 #define PIPE_CONF_QUIRK(quirk)  \
12572         ((current_config->quirks | pipe_config->quirks) & (quirk))
12573
12574         PIPE_CONF_CHECK_I(cpu_transcoder);
12575
12576         PIPE_CONF_CHECK_I(has_pch_encoder);
12577         PIPE_CONF_CHECK_I(fdi_lanes);
12578         PIPE_CONF_CHECK_M_N(fdi_m_n);
12579
12580         PIPE_CONF_CHECK_I(has_dp_encoder);
12581         PIPE_CONF_CHECK_I(lane_count);
12582
12583         if (INTEL_INFO(dev)->gen < 8) {
12584                 PIPE_CONF_CHECK_M_N(dp_m_n);
12585
12586                 PIPE_CONF_CHECK_I(has_drrs);
12587                 if (current_config->has_drrs)
12588                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12589         } else
12590                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12591
12592         PIPE_CONF_CHECK_I(has_dsi_encoder);
12593
12594         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12595         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12596         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12597         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12598         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12599         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12600
12601         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12602         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12603         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12604         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12605         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12606         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12607
12608         PIPE_CONF_CHECK_I(pixel_multiplier);
12609         PIPE_CONF_CHECK_I(has_hdmi_sink);
12610         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12611             IS_VALLEYVIEW(dev))
12612                 PIPE_CONF_CHECK_I(limited_color_range);
12613         PIPE_CONF_CHECK_I(has_infoframe);
12614
12615         PIPE_CONF_CHECK_I(has_audio);
12616
12617         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12618                               DRM_MODE_FLAG_INTERLACE);
12619
12620         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12621                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12622                                       DRM_MODE_FLAG_PHSYNC);
12623                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12624                                       DRM_MODE_FLAG_NHSYNC);
12625                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12626                                       DRM_MODE_FLAG_PVSYNC);
12627                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12628                                       DRM_MODE_FLAG_NVSYNC);
12629         }
12630
12631         PIPE_CONF_CHECK_X(gmch_pfit.control);
12632         /* pfit ratios are autocomputed by the hw on gen4+ */
12633         if (INTEL_INFO(dev)->gen < 4)
12634                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12635         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12636
12637         if (!adjust) {
12638                 PIPE_CONF_CHECK_I(pipe_src_w);
12639                 PIPE_CONF_CHECK_I(pipe_src_h);
12640
12641                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12642                 if (current_config->pch_pfit.enabled) {
12643                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12644                         PIPE_CONF_CHECK_X(pch_pfit.size);
12645                 }
12646
12647                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12648         }
12649
12650         /* BDW+ don't expose a synchronous way to read the state */
12651         if (IS_HASWELL(dev))
12652                 PIPE_CONF_CHECK_I(ips_enabled);
12653
12654         PIPE_CONF_CHECK_I(double_wide);
12655
12656         PIPE_CONF_CHECK_X(ddi_pll_sel);
12657
12658         PIPE_CONF_CHECK_I(shared_dpll);
12659         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12660         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12661         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12662         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12663         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12664         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12665         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12666         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12667         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12668
12669         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12670                 PIPE_CONF_CHECK_I(pipe_bpp);
12671
12672         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12673         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12674
12675 #undef PIPE_CONF_CHECK_X
12676 #undef PIPE_CONF_CHECK_I
12677 #undef PIPE_CONF_CHECK_I_ALT
12678 #undef PIPE_CONF_CHECK_FLAGS
12679 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12680 #undef PIPE_CONF_QUIRK
12681 #undef INTEL_ERR_OR_DBG_KMS
12682
12683         return ret;
12684 }
12685
12686 static void check_wm_state(struct drm_device *dev)
12687 {
12688         struct drm_i915_private *dev_priv = dev->dev_private;
12689         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12690         struct intel_crtc *intel_crtc;
12691         int plane;
12692
12693         if (INTEL_INFO(dev)->gen < 9)
12694                 return;
12695
12696         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12697         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12698
12699         for_each_intel_crtc(dev, intel_crtc) {
12700                 struct skl_ddb_entry *hw_entry, *sw_entry;
12701                 const enum pipe pipe = intel_crtc->pipe;
12702
12703                 if (!intel_crtc->active)
12704                         continue;
12705
12706                 /* planes */
12707                 for_each_plane(dev_priv, pipe, plane) {
12708                         hw_entry = &hw_ddb.plane[pipe][plane];
12709                         sw_entry = &sw_ddb->plane[pipe][plane];
12710
12711                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12712                                 continue;
12713
12714                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12715                                   "(expected (%u,%u), found (%u,%u))\n",
12716                                   pipe_name(pipe), plane + 1,
12717                                   sw_entry->start, sw_entry->end,
12718                                   hw_entry->start, hw_entry->end);
12719                 }
12720
12721                 /* cursor */
12722                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12723                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12724
12725                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12726                         continue;
12727
12728                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12729                           "(expected (%u,%u), found (%u,%u))\n",
12730                           pipe_name(pipe),
12731                           sw_entry->start, sw_entry->end,
12732                           hw_entry->start, hw_entry->end);
12733         }
12734 }
12735
12736 static void
12737 check_connector_state(struct drm_device *dev,
12738                       struct drm_atomic_state *old_state)
12739 {
12740         struct drm_connector_state *old_conn_state;
12741         struct drm_connector *connector;
12742         int i;
12743
12744         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12745                 struct drm_encoder *encoder = connector->encoder;
12746                 struct drm_connector_state *state = connector->state;
12747
12748                 /* This also checks the encoder/connector hw state with the
12749                  * ->get_hw_state callbacks. */
12750                 intel_connector_check_state(to_intel_connector(connector));
12751
12752                 I915_STATE_WARN(state->best_encoder != encoder,
12753                      "connector's atomic encoder doesn't match legacy encoder\n");
12754         }
12755 }
12756
12757 static void
12758 check_encoder_state(struct drm_device *dev)
12759 {
12760         struct intel_encoder *encoder;
12761         struct intel_connector *connector;
12762
12763         for_each_intel_encoder(dev, encoder) {
12764                 bool enabled = false;
12765                 enum pipe pipe;
12766
12767                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12768                               encoder->base.base.id,
12769                               encoder->base.name);
12770
12771                 for_each_intel_connector(dev, connector) {
12772                         if (connector->base.state->best_encoder != &encoder->base)
12773                                 continue;
12774                         enabled = true;
12775
12776                         I915_STATE_WARN(connector->base.state->crtc !=
12777                                         encoder->base.crtc,
12778                              "connector's crtc doesn't match encoder crtc\n");
12779                 }
12780
12781                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12782                      "encoder's enabled state mismatch "
12783                      "(expected %i, found %i)\n",
12784                      !!encoder->base.crtc, enabled);
12785
12786                 if (!encoder->base.crtc) {
12787                         bool active;
12788
12789                         active = encoder->get_hw_state(encoder, &pipe);
12790                         I915_STATE_WARN(active,
12791                              "encoder detached but still enabled on pipe %c.\n",
12792                              pipe_name(pipe));
12793                 }
12794         }
12795 }
12796
12797 static void
12798 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12799 {
12800         struct drm_i915_private *dev_priv = dev->dev_private;
12801         struct intel_encoder *encoder;
12802         struct drm_crtc_state *old_crtc_state;
12803         struct drm_crtc *crtc;
12804         int i;
12805
12806         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12807                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12808                 struct intel_crtc_state *pipe_config, *sw_config;
12809                 bool active;
12810
12811                 if (!needs_modeset(crtc->state) &&
12812                     !to_intel_crtc_state(crtc->state)->update_pipe)
12813                         continue;
12814
12815                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12816                 pipe_config = to_intel_crtc_state(old_crtc_state);
12817                 memset(pipe_config, 0, sizeof(*pipe_config));
12818                 pipe_config->base.crtc = crtc;
12819                 pipe_config->base.state = old_state;
12820
12821                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12822                               crtc->base.id);
12823
12824                 active = dev_priv->display.get_pipe_config(intel_crtc,
12825                                                            pipe_config);
12826
12827                 /* hw state is inconsistent with the pipe quirk */
12828                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12829                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12830                         active = crtc->state->active;
12831
12832                 I915_STATE_WARN(crtc->state->active != active,
12833                      "crtc active state doesn't match with hw state "
12834                      "(expected %i, found %i)\n", crtc->state->active, active);
12835
12836                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12837                      "transitional active state does not match atomic hw state "
12838                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12839
12840                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12841                         enum pipe pipe;
12842
12843                         active = encoder->get_hw_state(encoder, &pipe);
12844                         I915_STATE_WARN(active != crtc->state->active,
12845                                 "[ENCODER:%i] active %i with crtc active %i\n",
12846                                 encoder->base.base.id, active, crtc->state->active);
12847
12848                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12849                                         "Encoder connected to wrong pipe %c\n",
12850                                         pipe_name(pipe));
12851
12852                         if (active)
12853                                 encoder->get_config(encoder, pipe_config);
12854                 }
12855
12856                 if (!crtc->state->active)
12857                         continue;
12858
12859                 sw_config = to_intel_crtc_state(crtc->state);
12860                 if (!intel_pipe_config_compare(dev, sw_config,
12861                                                pipe_config, false)) {
12862                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12863                         intel_dump_pipe_config(intel_crtc, pipe_config,
12864                                                "[hw state]");
12865                         intel_dump_pipe_config(intel_crtc, sw_config,
12866                                                "[sw state]");
12867                 }
12868         }
12869 }
12870
12871 static void
12872 check_shared_dpll_state(struct drm_device *dev)
12873 {
12874         struct drm_i915_private *dev_priv = dev->dev_private;
12875         struct intel_crtc *crtc;
12876         struct intel_dpll_hw_state dpll_hw_state;
12877         int i;
12878
12879         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12880                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12881                 int enabled_crtcs = 0, active_crtcs = 0;
12882                 bool active;
12883
12884                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12885
12886                 DRM_DEBUG_KMS("%s\n", pll->name);
12887
12888                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12889
12890                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12891                      "more active pll users than references: %i vs %i\n",
12892                      pll->active, hweight32(pll->config.crtc_mask));
12893                 I915_STATE_WARN(pll->active && !pll->on,
12894                      "pll in active use but not on in sw tracking\n");
12895                 I915_STATE_WARN(pll->on && !pll->active,
12896                      "pll in on but not on in use in sw tracking\n");
12897                 I915_STATE_WARN(pll->on != active,
12898                      "pll on state mismatch (expected %i, found %i)\n",
12899                      pll->on, active);
12900
12901                 for_each_intel_crtc(dev, crtc) {
12902                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12903                                 enabled_crtcs++;
12904                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12905                                 active_crtcs++;
12906                 }
12907                 I915_STATE_WARN(pll->active != active_crtcs,
12908                      "pll active crtcs mismatch (expected %i, found %i)\n",
12909                      pll->active, active_crtcs);
12910                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12911                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12912                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12913
12914                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12915                                        sizeof(dpll_hw_state)),
12916                      "pll hw state mismatch\n");
12917         }
12918 }
12919
12920 static void
12921 intel_modeset_check_state(struct drm_device *dev,
12922                           struct drm_atomic_state *old_state)
12923 {
12924         check_wm_state(dev);
12925         check_connector_state(dev, old_state);
12926         check_encoder_state(dev);
12927         check_crtc_state(dev, old_state);
12928         check_shared_dpll_state(dev);
12929 }
12930
12931 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12932                                      int dotclock)
12933 {
12934         /*
12935          * FDI already provided one idea for the dotclock.
12936          * Yell if the encoder disagrees.
12937          */
12938         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12939              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12940              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12941 }
12942
12943 static void update_scanline_offset(struct intel_crtc *crtc)
12944 {
12945         struct drm_device *dev = crtc->base.dev;
12946
12947         /*
12948          * The scanline counter increments at the leading edge of hsync.
12949          *
12950          * On most platforms it starts counting from vtotal-1 on the
12951          * first active line. That means the scanline counter value is
12952          * always one less than what we would expect. Ie. just after
12953          * start of vblank, which also occurs at start of hsync (on the
12954          * last active line), the scanline counter will read vblank_start-1.
12955          *
12956          * On gen2 the scanline counter starts counting from 1 instead
12957          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12958          * to keep the value positive), instead of adding one.
12959          *
12960          * On HSW+ the behaviour of the scanline counter depends on the output
12961          * type. For DP ports it behaves like most other platforms, but on HDMI
12962          * there's an extra 1 line difference. So we need to add two instead of
12963          * one to the value.
12964          */
12965         if (IS_GEN2(dev)) {
12966                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12967                 int vtotal;
12968
12969                 vtotal = adjusted_mode->crtc_vtotal;
12970                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12971                         vtotal /= 2;
12972
12973                 crtc->scanline_offset = vtotal - 1;
12974         } else if (HAS_DDI(dev) &&
12975                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12976                 crtc->scanline_offset = 2;
12977         } else
12978                 crtc->scanline_offset = 1;
12979 }
12980
12981 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12982 {
12983         struct drm_device *dev = state->dev;
12984         struct drm_i915_private *dev_priv = to_i915(dev);
12985         struct intel_shared_dpll_config *shared_dpll = NULL;
12986         struct intel_crtc *intel_crtc;
12987         struct intel_crtc_state *intel_crtc_state;
12988         struct drm_crtc *crtc;
12989         struct drm_crtc_state *crtc_state;
12990         int i;
12991
12992         if (!dev_priv->display.crtc_compute_clock)
12993                 return;
12994
12995         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12996                 int dpll;
12997
12998                 intel_crtc = to_intel_crtc(crtc);
12999                 intel_crtc_state = to_intel_crtc_state(crtc_state);
13000                 dpll = intel_crtc_state->shared_dpll;
13001
13002                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13003                         continue;
13004
13005                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13006
13007                 if (!shared_dpll)
13008                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13009
13010                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13011         }
13012 }
13013
13014 /*
13015  * This implements the workaround described in the "notes" section of the mode
13016  * set sequence documentation. When going from no pipes or single pipe to
13017  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13018  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13019  */
13020 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13021 {
13022         struct drm_crtc_state *crtc_state;
13023         struct intel_crtc *intel_crtc;
13024         struct drm_crtc *crtc;
13025         struct intel_crtc_state *first_crtc_state = NULL;
13026         struct intel_crtc_state *other_crtc_state = NULL;
13027         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13028         int i;
13029
13030         /* look at all crtc's that are going to be enabled in during modeset */
13031         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13032                 intel_crtc = to_intel_crtc(crtc);
13033
13034                 if (!crtc_state->active || !needs_modeset(crtc_state))
13035                         continue;
13036
13037                 if (first_crtc_state) {
13038                         other_crtc_state = to_intel_crtc_state(crtc_state);
13039                         break;
13040                 } else {
13041                         first_crtc_state = to_intel_crtc_state(crtc_state);
13042                         first_pipe = intel_crtc->pipe;
13043                 }
13044         }
13045
13046         /* No workaround needed? */
13047         if (!first_crtc_state)
13048                 return 0;
13049
13050         /* w/a possibly needed, check how many crtc's are already enabled. */
13051         for_each_intel_crtc(state->dev, intel_crtc) {
13052                 struct intel_crtc_state *pipe_config;
13053
13054                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13055                 if (IS_ERR(pipe_config))
13056                         return PTR_ERR(pipe_config);
13057
13058                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13059
13060                 if (!pipe_config->base.active ||
13061                     needs_modeset(&pipe_config->base))
13062                         continue;
13063
13064                 /* 2 or more enabled crtcs means no need for w/a */
13065                 if (enabled_pipe != INVALID_PIPE)
13066                         return 0;
13067
13068                 enabled_pipe = intel_crtc->pipe;
13069         }
13070
13071         if (enabled_pipe != INVALID_PIPE)
13072                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13073         else if (other_crtc_state)
13074                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13075
13076         return 0;
13077 }
13078
13079 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13080 {
13081         struct drm_crtc *crtc;
13082         struct drm_crtc_state *crtc_state;
13083         int ret = 0;
13084
13085         /* add all active pipes to the state */
13086         for_each_crtc(state->dev, crtc) {
13087                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13088                 if (IS_ERR(crtc_state))
13089                         return PTR_ERR(crtc_state);
13090
13091                 if (!crtc_state->active || needs_modeset(crtc_state))
13092                         continue;
13093
13094                 crtc_state->mode_changed = true;
13095
13096                 ret = drm_atomic_add_affected_connectors(state, crtc);
13097                 if (ret)
13098                         break;
13099
13100                 ret = drm_atomic_add_affected_planes(state, crtc);
13101                 if (ret)
13102                         break;
13103         }
13104
13105         return ret;
13106 }
13107
13108 static int intel_modeset_checks(struct drm_atomic_state *state)
13109 {
13110         struct drm_device *dev = state->dev;
13111         struct drm_i915_private *dev_priv = dev->dev_private;
13112         int ret;
13113
13114         if (!check_digital_port_conflicts(state)) {
13115                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13116                 return -EINVAL;
13117         }
13118
13119         /*
13120          * See if the config requires any additional preparation, e.g.
13121          * to adjust global state with pipes off.  We need to do this
13122          * here so we can get the modeset_pipe updated config for the new
13123          * mode set on this crtc.  For other crtcs we need to use the
13124          * adjusted_mode bits in the crtc directly.
13125          */
13126         if (dev_priv->display.modeset_calc_cdclk) {
13127                 unsigned int cdclk;
13128
13129                 ret = dev_priv->display.modeset_calc_cdclk(state);
13130
13131                 cdclk = to_intel_atomic_state(state)->cdclk;
13132                 if (!ret && cdclk != dev_priv->cdclk_freq)
13133                         ret = intel_modeset_all_pipes(state);
13134
13135                 if (ret < 0)
13136                         return ret;
13137         } else
13138                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13139
13140         intel_modeset_clear_plls(state);
13141
13142         if (IS_HASWELL(dev))
13143                 return haswell_mode_set_planes_workaround(state);
13144
13145         return 0;
13146 }
13147
13148 /*
13149  * Handle calculation of various watermark data at the end of the atomic check
13150  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13151  * handlers to ensure that all derived state has been updated.
13152  */
13153 static void calc_watermark_data(struct drm_atomic_state *state)
13154 {
13155         struct drm_device *dev = state->dev;
13156         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13157         struct drm_crtc *crtc;
13158         struct drm_crtc_state *cstate;
13159         struct drm_plane *plane;
13160         struct drm_plane_state *pstate;
13161
13162         /*
13163          * Calculate watermark configuration details now that derived
13164          * plane/crtc state is all properly updated.
13165          */
13166         drm_for_each_crtc(crtc, dev) {
13167                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13168                         crtc->state;
13169
13170                 if (cstate->active)
13171                         intel_state->wm_config.num_pipes_active++;
13172         }
13173         drm_for_each_legacy_plane(plane, dev) {
13174                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13175                         plane->state;
13176
13177                 if (!to_intel_plane_state(pstate)->visible)
13178                         continue;
13179
13180                 intel_state->wm_config.sprites_enabled = true;
13181                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13182                     pstate->crtc_h != pstate->src_h >> 16)
13183                         intel_state->wm_config.sprites_scaled = true;
13184         }
13185 }
13186
13187 /**
13188  * intel_atomic_check - validate state object
13189  * @dev: drm device
13190  * @state: state to validate
13191  */
13192 static int intel_atomic_check(struct drm_device *dev,
13193                               struct drm_atomic_state *state)
13194 {
13195         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13196         struct drm_crtc *crtc;
13197         struct drm_crtc_state *crtc_state;
13198         int ret, i;
13199         bool any_ms = false;
13200
13201         ret = drm_atomic_helper_check_modeset(dev, state);
13202         if (ret)
13203                 return ret;
13204
13205         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13206                 struct intel_crtc_state *pipe_config =
13207                         to_intel_crtc_state(crtc_state);
13208
13209                 memset(&to_intel_crtc(crtc)->atomic, 0,
13210                        sizeof(struct intel_crtc_atomic_commit));
13211
13212                 /* Catch I915_MODE_FLAG_INHERITED */
13213                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13214                         crtc_state->mode_changed = true;
13215
13216                 if (!crtc_state->enable) {
13217                         if (needs_modeset(crtc_state))
13218                                 any_ms = true;
13219                         continue;
13220                 }
13221
13222                 if (!needs_modeset(crtc_state))
13223                         continue;
13224
13225                 /* FIXME: For only active_changed we shouldn't need to do any
13226                  * state recomputation at all. */
13227
13228                 ret = drm_atomic_add_affected_connectors(state, crtc);
13229                 if (ret)
13230                         return ret;
13231
13232                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13233                 if (ret)
13234                         return ret;
13235
13236                 if (i915.fastboot &&
13237                     intel_pipe_config_compare(state->dev,
13238                                         to_intel_crtc_state(crtc->state),
13239                                         pipe_config, true)) {
13240                         crtc_state->mode_changed = false;
13241                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13242                 }
13243
13244                 if (needs_modeset(crtc_state)) {
13245                         any_ms = true;
13246
13247                         ret = drm_atomic_add_affected_planes(state, crtc);
13248                         if (ret)
13249                                 return ret;
13250                 }
13251
13252                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13253                                        needs_modeset(crtc_state) ?
13254                                        "[modeset]" : "[fastset]");
13255         }
13256
13257         if (any_ms) {
13258                 ret = intel_modeset_checks(state);
13259
13260                 if (ret)
13261                         return ret;
13262         } else
13263                 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13264
13265         ret = drm_atomic_helper_check_planes(state->dev, state);
13266         if (ret)
13267                 return ret;
13268
13269         calc_watermark_data(state);
13270
13271         return 0;
13272 }
13273
13274 static int intel_atomic_prepare_commit(struct drm_device *dev,
13275                                        struct drm_atomic_state *state,
13276                                        bool async)
13277 {
13278         struct drm_i915_private *dev_priv = dev->dev_private;
13279         struct drm_plane_state *plane_state;
13280         struct drm_crtc_state *crtc_state;
13281         struct drm_plane *plane;
13282         struct drm_crtc *crtc;
13283         int i, ret;
13284
13285         if (async) {
13286                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13287                 return -EINVAL;
13288         }
13289
13290         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13291                 ret = intel_crtc_wait_for_pending_flips(crtc);
13292                 if (ret)
13293                         return ret;
13294
13295                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13296                         flush_workqueue(dev_priv->wq);
13297         }
13298
13299         ret = mutex_lock_interruptible(&dev->struct_mutex);
13300         if (ret)
13301                 return ret;
13302
13303         ret = drm_atomic_helper_prepare_planes(dev, state);
13304         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13305                 u32 reset_counter;
13306
13307                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13308                 mutex_unlock(&dev->struct_mutex);
13309
13310                 for_each_plane_in_state(state, plane, plane_state, i) {
13311                         struct intel_plane_state *intel_plane_state =
13312                                 to_intel_plane_state(plane_state);
13313
13314                         if (!intel_plane_state->wait_req)
13315                                 continue;
13316
13317                         ret = __i915_wait_request(intel_plane_state->wait_req,
13318                                                   reset_counter, true,
13319                                                   NULL, NULL);
13320
13321                         /* Swallow -EIO errors to allow updates during hw lockup. */
13322                         if (ret == -EIO)
13323                                 ret = 0;
13324
13325                         if (ret)
13326                                 break;
13327                 }
13328
13329                 if (!ret)
13330                         return 0;
13331
13332                 mutex_lock(&dev->struct_mutex);
13333                 drm_atomic_helper_cleanup_planes(dev, state);
13334         }
13335
13336         mutex_unlock(&dev->struct_mutex);
13337         return ret;
13338 }
13339
13340 /**
13341  * intel_atomic_commit - commit validated state object
13342  * @dev: DRM device
13343  * @state: the top-level driver state object
13344  * @async: asynchronous commit
13345  *
13346  * This function commits a top-level state object that has been validated
13347  * with drm_atomic_helper_check().
13348  *
13349  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13350  * we can only handle plane-related operations and do not yet support
13351  * asynchronous commit.
13352  *
13353  * RETURNS
13354  * Zero for success or -errno.
13355  */
13356 static int intel_atomic_commit(struct drm_device *dev,
13357                                struct drm_atomic_state *state,
13358                                bool async)
13359 {
13360         struct drm_i915_private *dev_priv = dev->dev_private;
13361         struct drm_crtc_state *crtc_state;
13362         struct drm_crtc *crtc;
13363         int ret = 0;
13364         int i;
13365         bool any_ms = false;
13366
13367         ret = intel_atomic_prepare_commit(dev, state, async);
13368         if (ret) {
13369                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13370                 return ret;
13371         }
13372
13373         drm_atomic_helper_swap_state(dev, state);
13374         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13375
13376         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13377                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13378
13379                 if (!needs_modeset(crtc->state))
13380                         continue;
13381
13382                 any_ms = true;
13383                 intel_pre_plane_update(intel_crtc);
13384
13385                 if (crtc_state->active) {
13386                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13387                         dev_priv->display.crtc_disable(crtc);
13388                         intel_crtc->active = false;
13389                         intel_disable_shared_dpll(intel_crtc);
13390
13391                         /*
13392                          * Underruns don't always raise
13393                          * interrupts, so check manually.
13394                          */
13395                         intel_check_cpu_fifo_underruns(dev_priv);
13396                         intel_check_pch_fifo_underruns(dev_priv);
13397                 }
13398         }
13399
13400         /* Only after disabling all output pipelines that will be changed can we
13401          * update the the output configuration. */
13402         intel_modeset_update_crtc_state(state);
13403
13404         if (any_ms) {
13405                 intel_shared_dpll_commit(state);
13406
13407                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13408                 modeset_update_crtc_power_domains(state);
13409         }
13410
13411         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13412         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13413                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13414                 bool modeset = needs_modeset(crtc->state);
13415                 bool update_pipe = !modeset &&
13416                         to_intel_crtc_state(crtc->state)->update_pipe;
13417                 unsigned long put_domains = 0;
13418
13419                 if (modeset)
13420                         intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13421
13422                 if (modeset && crtc->state->active) {
13423                         update_scanline_offset(to_intel_crtc(crtc));
13424                         dev_priv->display.crtc_enable(crtc);
13425                 }
13426
13427                 if (update_pipe) {
13428                         put_domains = modeset_get_crtc_power_domains(crtc);
13429
13430                         /* make sure intel_modeset_check_state runs */
13431                         any_ms = true;
13432                 }
13433
13434                 if (!modeset)
13435                         intel_pre_plane_update(intel_crtc);
13436
13437                 if (crtc->state->active &&
13438                     (crtc->state->planes_changed || update_pipe))
13439                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13440
13441                 if (put_domains)
13442                         modeset_put_power_domains(dev_priv, put_domains);
13443
13444                 intel_post_plane_update(intel_crtc);
13445
13446                 if (modeset)
13447                         intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13448         }
13449
13450         /* FIXME: add subpixel order */
13451
13452         drm_atomic_helper_wait_for_vblanks(dev, state);
13453
13454         mutex_lock(&dev->struct_mutex);
13455         drm_atomic_helper_cleanup_planes(dev, state);
13456         mutex_unlock(&dev->struct_mutex);
13457
13458         if (any_ms)
13459                 intel_modeset_check_state(dev, state);
13460
13461         drm_atomic_state_free(state);
13462
13463         return 0;
13464 }
13465
13466 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13467 {
13468         struct drm_device *dev = crtc->dev;
13469         struct drm_atomic_state *state;
13470         struct drm_crtc_state *crtc_state;
13471         int ret;
13472
13473         state = drm_atomic_state_alloc(dev);
13474         if (!state) {
13475                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13476                               crtc->base.id);
13477                 return;
13478         }
13479
13480         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13481
13482 retry:
13483         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13484         ret = PTR_ERR_OR_ZERO(crtc_state);
13485         if (!ret) {
13486                 if (!crtc_state->active)
13487                         goto out;
13488
13489                 crtc_state->mode_changed = true;
13490                 ret = drm_atomic_commit(state);
13491         }
13492
13493         if (ret == -EDEADLK) {
13494                 drm_atomic_state_clear(state);
13495                 drm_modeset_backoff(state->acquire_ctx);
13496                 goto retry;
13497         }
13498
13499         if (ret)
13500 out:
13501                 drm_atomic_state_free(state);
13502 }
13503
13504 #undef for_each_intel_crtc_masked
13505
13506 static const struct drm_crtc_funcs intel_crtc_funcs = {
13507         .gamma_set = intel_crtc_gamma_set,
13508         .set_config = drm_atomic_helper_set_config,
13509         .destroy = intel_crtc_destroy,
13510         .page_flip = intel_crtc_page_flip,
13511         .atomic_duplicate_state = intel_crtc_duplicate_state,
13512         .atomic_destroy_state = intel_crtc_destroy_state,
13513 };
13514
13515 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13516                                       struct intel_shared_dpll *pll,
13517                                       struct intel_dpll_hw_state *hw_state)
13518 {
13519         uint32_t val;
13520
13521         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13522                 return false;
13523
13524         val = I915_READ(PCH_DPLL(pll->id));
13525         hw_state->dpll = val;
13526         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13527         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13528
13529         return val & DPLL_VCO_ENABLE;
13530 }
13531
13532 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13533                                   struct intel_shared_dpll *pll)
13534 {
13535         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13536         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13537 }
13538
13539 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13540                                 struct intel_shared_dpll *pll)
13541 {
13542         /* PCH refclock must be enabled first */
13543         ibx_assert_pch_refclk_enabled(dev_priv);
13544
13545         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13546
13547         /* Wait for the clocks to stabilize. */
13548         POSTING_READ(PCH_DPLL(pll->id));
13549         udelay(150);
13550
13551         /* The pixel multiplier can only be updated once the
13552          * DPLL is enabled and the clocks are stable.
13553          *
13554          * So write it again.
13555          */
13556         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13557         POSTING_READ(PCH_DPLL(pll->id));
13558         udelay(200);
13559 }
13560
13561 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13562                                  struct intel_shared_dpll *pll)
13563 {
13564         struct drm_device *dev = dev_priv->dev;
13565         struct intel_crtc *crtc;
13566
13567         /* Make sure no transcoder isn't still depending on us. */
13568         for_each_intel_crtc(dev, crtc) {
13569                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13570                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13571         }
13572
13573         I915_WRITE(PCH_DPLL(pll->id), 0);
13574         POSTING_READ(PCH_DPLL(pll->id));
13575         udelay(200);
13576 }
13577
13578 static char *ibx_pch_dpll_names[] = {
13579         "PCH DPLL A",
13580         "PCH DPLL B",
13581 };
13582
13583 static void ibx_pch_dpll_init(struct drm_device *dev)
13584 {
13585         struct drm_i915_private *dev_priv = dev->dev_private;
13586         int i;
13587
13588         dev_priv->num_shared_dpll = 2;
13589
13590         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13591                 dev_priv->shared_dplls[i].id = i;
13592                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13593                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13594                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13595                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13596                 dev_priv->shared_dplls[i].get_hw_state =
13597                         ibx_pch_dpll_get_hw_state;
13598         }
13599 }
13600
13601 static void intel_shared_dpll_init(struct drm_device *dev)
13602 {
13603         struct drm_i915_private *dev_priv = dev->dev_private;
13604
13605         if (HAS_DDI(dev))
13606                 intel_ddi_pll_init(dev);
13607         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13608                 ibx_pch_dpll_init(dev);
13609         else
13610                 dev_priv->num_shared_dpll = 0;
13611
13612         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13613 }
13614
13615 /**
13616  * intel_prepare_plane_fb - Prepare fb for usage on plane
13617  * @plane: drm plane to prepare for
13618  * @fb: framebuffer to prepare for presentation
13619  *
13620  * Prepares a framebuffer for usage on a display plane.  Generally this
13621  * involves pinning the underlying object and updating the frontbuffer tracking
13622  * bits.  Some older platforms need special physical address handling for
13623  * cursor planes.
13624  *
13625  * Must be called with struct_mutex held.
13626  *
13627  * Returns 0 on success, negative error code on failure.
13628  */
13629 int
13630 intel_prepare_plane_fb(struct drm_plane *plane,
13631                        const struct drm_plane_state *new_state)
13632 {
13633         struct drm_device *dev = plane->dev;
13634         struct drm_framebuffer *fb = new_state->fb;
13635         struct intel_plane *intel_plane = to_intel_plane(plane);
13636         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13637         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13638         int ret = 0;
13639
13640         if (!obj && !old_obj)
13641                 return 0;
13642
13643         if (old_obj) {
13644                 struct drm_crtc_state *crtc_state =
13645                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13646
13647                 /* Big Hammer, we also need to ensure that any pending
13648                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13649                  * current scanout is retired before unpinning the old
13650                  * framebuffer. Note that we rely on userspace rendering
13651                  * into the buffer attached to the pipe they are waiting
13652                  * on. If not, userspace generates a GPU hang with IPEHR
13653                  * point to the MI_WAIT_FOR_EVENT.
13654                  *
13655                  * This should only fail upon a hung GPU, in which case we
13656                  * can safely continue.
13657                  */
13658                 if (needs_modeset(crtc_state))
13659                         ret = i915_gem_object_wait_rendering(old_obj, true);
13660
13661                 /* Swallow -EIO errors to allow updates during hw lockup. */
13662                 if (ret && ret != -EIO)
13663                         return ret;
13664         }
13665
13666         if (!obj) {
13667                 ret = 0;
13668         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13669             INTEL_INFO(dev)->cursor_needs_physical) {
13670                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13671                 ret = i915_gem_object_attach_phys(obj, align);
13672                 if (ret)
13673                         DRM_DEBUG_KMS("failed to attach phys object\n");
13674         } else {
13675                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13676         }
13677
13678         if (ret == 0) {
13679                 if (obj) {
13680                         struct intel_plane_state *plane_state =
13681                                 to_intel_plane_state(new_state);
13682
13683                         i915_gem_request_assign(&plane_state->wait_req,
13684                                                 obj->last_write_req);
13685                 }
13686
13687                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13688         }
13689
13690         return ret;
13691 }
13692
13693 /**
13694  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13695  * @plane: drm plane to clean up for
13696  * @fb: old framebuffer that was on plane
13697  *
13698  * Cleans up a framebuffer that has just been removed from a plane.
13699  *
13700  * Must be called with struct_mutex held.
13701  */
13702 void
13703 intel_cleanup_plane_fb(struct drm_plane *plane,
13704                        const struct drm_plane_state *old_state)
13705 {
13706         struct drm_device *dev = plane->dev;
13707         struct intel_plane *intel_plane = to_intel_plane(plane);
13708         struct intel_plane_state *old_intel_state;
13709         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13710         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13711
13712         old_intel_state = to_intel_plane_state(old_state);
13713
13714         if (!obj && !old_obj)
13715                 return;
13716
13717         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13718             !INTEL_INFO(dev)->cursor_needs_physical))
13719                 intel_unpin_fb_obj(old_state->fb, old_state);
13720
13721         /* prepare_fb aborted? */
13722         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13723             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13724                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13725
13726         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13727
13728 }
13729
13730 int
13731 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13732 {
13733         int max_scale;
13734         struct drm_device *dev;
13735         struct drm_i915_private *dev_priv;
13736         int crtc_clock, cdclk;
13737
13738         if (!intel_crtc || !crtc_state)
13739                 return DRM_PLANE_HELPER_NO_SCALING;
13740
13741         dev = intel_crtc->base.dev;
13742         dev_priv = dev->dev_private;
13743         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13744         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13745
13746         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13747                 return DRM_PLANE_HELPER_NO_SCALING;
13748
13749         /*
13750          * skl max scale is lower of:
13751          *    close to 3 but not 3, -1 is for that purpose
13752          *            or
13753          *    cdclk/crtc_clock
13754          */
13755         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13756
13757         return max_scale;
13758 }
13759
13760 static int
13761 intel_check_primary_plane(struct drm_plane *plane,
13762                           struct intel_crtc_state *crtc_state,
13763                           struct intel_plane_state *state)
13764 {
13765         struct drm_crtc *crtc = state->base.crtc;
13766         struct drm_framebuffer *fb = state->base.fb;
13767         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13768         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13769         bool can_position = false;
13770
13771         /* use scaler when colorkey is not required */
13772         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13773             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13774                 min_scale = 1;
13775                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13776                 can_position = true;
13777         }
13778
13779         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13780                                              &state->dst, &state->clip,
13781                                              min_scale, max_scale,
13782                                              can_position, true,
13783                                              &state->visible);
13784 }
13785
13786 static void
13787 intel_commit_primary_plane(struct drm_plane *plane,
13788                            struct intel_plane_state *state)
13789 {
13790         struct drm_crtc *crtc = state->base.crtc;
13791         struct drm_framebuffer *fb = state->base.fb;
13792         struct drm_device *dev = plane->dev;
13793         struct drm_i915_private *dev_priv = dev->dev_private;
13794
13795         crtc = crtc ? crtc : plane->crtc;
13796
13797         dev_priv->display.update_primary_plane(crtc, fb,
13798                                                state->src.x1 >> 16,
13799                                                state->src.y1 >> 16);
13800 }
13801
13802 static void
13803 intel_disable_primary_plane(struct drm_plane *plane,
13804                             struct drm_crtc *crtc)
13805 {
13806         struct drm_device *dev = plane->dev;
13807         struct drm_i915_private *dev_priv = dev->dev_private;
13808
13809         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13810 }
13811
13812 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13813                                     struct drm_crtc_state *old_crtc_state)
13814 {
13815         struct drm_device *dev = crtc->dev;
13816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13817         struct intel_crtc_state *old_intel_state =
13818                 to_intel_crtc_state(old_crtc_state);
13819         bool modeset = needs_modeset(crtc->state);
13820
13821         if (intel_crtc->atomic.update_wm_pre)
13822                 intel_update_watermarks(crtc);
13823
13824         /* Perform vblank evasion around commit operation */
13825         intel_pipe_update_start(intel_crtc);
13826
13827         if (modeset)
13828                 return;
13829
13830         if (to_intel_crtc_state(crtc->state)->update_pipe)
13831                 intel_update_pipe_config(intel_crtc, old_intel_state);
13832         else if (INTEL_INFO(dev)->gen >= 9)
13833                 skl_detach_scalers(intel_crtc);
13834 }
13835
13836 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13837                                      struct drm_crtc_state *old_crtc_state)
13838 {
13839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13840
13841         intel_pipe_update_end(intel_crtc);
13842 }
13843
13844 /**
13845  * intel_plane_destroy - destroy a plane
13846  * @plane: plane to destroy
13847  *
13848  * Common destruction function for all types of planes (primary, cursor,
13849  * sprite).
13850  */
13851 void intel_plane_destroy(struct drm_plane *plane)
13852 {
13853         struct intel_plane *intel_plane = to_intel_plane(plane);
13854         drm_plane_cleanup(plane);
13855         kfree(intel_plane);
13856 }
13857
13858 const struct drm_plane_funcs intel_plane_funcs = {
13859         .update_plane = drm_atomic_helper_update_plane,
13860         .disable_plane = drm_atomic_helper_disable_plane,
13861         .destroy = intel_plane_destroy,
13862         .set_property = drm_atomic_helper_plane_set_property,
13863         .atomic_get_property = intel_plane_atomic_get_property,
13864         .atomic_set_property = intel_plane_atomic_set_property,
13865         .atomic_duplicate_state = intel_plane_duplicate_state,
13866         .atomic_destroy_state = intel_plane_destroy_state,
13867
13868 };
13869
13870 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13871                                                     int pipe)
13872 {
13873         struct intel_plane *primary;
13874         struct intel_plane_state *state;
13875         const uint32_t *intel_primary_formats;
13876         unsigned int num_formats;
13877
13878         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13879         if (primary == NULL)
13880                 return NULL;
13881
13882         state = intel_create_plane_state(&primary->base);
13883         if (!state) {
13884                 kfree(primary);
13885                 return NULL;
13886         }
13887         primary->base.state = &state->base;
13888
13889         primary->can_scale = false;
13890         primary->max_downscale = 1;
13891         if (INTEL_INFO(dev)->gen >= 9) {
13892                 primary->can_scale = true;
13893                 state->scaler_id = -1;
13894         }
13895         primary->pipe = pipe;
13896         primary->plane = pipe;
13897         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13898         primary->check_plane = intel_check_primary_plane;
13899         primary->commit_plane = intel_commit_primary_plane;
13900         primary->disable_plane = intel_disable_primary_plane;
13901         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13902                 primary->plane = !pipe;
13903
13904         if (INTEL_INFO(dev)->gen >= 9) {
13905                 intel_primary_formats = skl_primary_formats;
13906                 num_formats = ARRAY_SIZE(skl_primary_formats);
13907         } else if (INTEL_INFO(dev)->gen >= 4) {
13908                 intel_primary_formats = i965_primary_formats;
13909                 num_formats = ARRAY_SIZE(i965_primary_formats);
13910         } else {
13911                 intel_primary_formats = i8xx_primary_formats;
13912                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13913         }
13914
13915         drm_universal_plane_init(dev, &primary->base, 0,
13916                                  &intel_plane_funcs,
13917                                  intel_primary_formats, num_formats,
13918                                  DRM_PLANE_TYPE_PRIMARY);
13919
13920         if (INTEL_INFO(dev)->gen >= 4)
13921                 intel_create_rotation_property(dev, primary);
13922
13923         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13924
13925         return &primary->base;
13926 }
13927
13928 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13929 {
13930         if (!dev->mode_config.rotation_property) {
13931                 unsigned long flags = BIT(DRM_ROTATE_0) |
13932                         BIT(DRM_ROTATE_180);
13933
13934                 if (INTEL_INFO(dev)->gen >= 9)
13935                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13936
13937                 dev->mode_config.rotation_property =
13938                         drm_mode_create_rotation_property(dev, flags);
13939         }
13940         if (dev->mode_config.rotation_property)
13941                 drm_object_attach_property(&plane->base.base,
13942                                 dev->mode_config.rotation_property,
13943                                 plane->base.state->rotation);
13944 }
13945
13946 static int
13947 intel_check_cursor_plane(struct drm_plane *plane,
13948                          struct intel_crtc_state *crtc_state,
13949                          struct intel_plane_state *state)
13950 {
13951         struct drm_crtc *crtc = crtc_state->base.crtc;
13952         struct drm_framebuffer *fb = state->base.fb;
13953         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13954         unsigned stride;
13955         int ret;
13956
13957         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13958                                             &state->dst, &state->clip,
13959                                             DRM_PLANE_HELPER_NO_SCALING,
13960                                             DRM_PLANE_HELPER_NO_SCALING,
13961                                             true, true, &state->visible);
13962         if (ret)
13963                 return ret;
13964
13965         /* if we want to turn off the cursor ignore width and height */
13966         if (!obj)
13967                 return 0;
13968
13969         /* Check for which cursor types we support */
13970         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13971                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13972                           state->base.crtc_w, state->base.crtc_h);
13973                 return -EINVAL;
13974         }
13975
13976         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13977         if (obj->base.size < stride * state->base.crtc_h) {
13978                 DRM_DEBUG_KMS("buffer is too small\n");
13979                 return -ENOMEM;
13980         }
13981
13982         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13983                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13984                 return -EINVAL;
13985         }
13986
13987         return 0;
13988 }
13989
13990 static void
13991 intel_disable_cursor_plane(struct drm_plane *plane,
13992                            struct drm_crtc *crtc)
13993 {
13994         intel_crtc_update_cursor(crtc, false);
13995 }
13996
13997 static void
13998 intel_commit_cursor_plane(struct drm_plane *plane,
13999                           struct intel_plane_state *state)
14000 {
14001         struct drm_crtc *crtc = state->base.crtc;
14002         struct drm_device *dev = plane->dev;
14003         struct intel_crtc *intel_crtc;
14004         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14005         uint32_t addr;
14006
14007         crtc = crtc ? crtc : plane->crtc;
14008         intel_crtc = to_intel_crtc(crtc);
14009
14010         if (intel_crtc->cursor_bo == obj)
14011                 goto update;
14012
14013         if (!obj)
14014                 addr = 0;
14015         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14016                 addr = i915_gem_obj_ggtt_offset(obj);
14017         else
14018                 addr = obj->phys_handle->busaddr;
14019
14020         intel_crtc->cursor_addr = addr;
14021         intel_crtc->cursor_bo = obj;
14022
14023 update:
14024         intel_crtc_update_cursor(crtc, state->visible);
14025 }
14026
14027 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14028                                                    int pipe)
14029 {
14030         struct intel_plane *cursor;
14031         struct intel_plane_state *state;
14032
14033         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14034         if (cursor == NULL)
14035                 return NULL;
14036
14037         state = intel_create_plane_state(&cursor->base);
14038         if (!state) {
14039                 kfree(cursor);
14040                 return NULL;
14041         }
14042         cursor->base.state = &state->base;
14043
14044         cursor->can_scale = false;
14045         cursor->max_downscale = 1;
14046         cursor->pipe = pipe;
14047         cursor->plane = pipe;
14048         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14049         cursor->check_plane = intel_check_cursor_plane;
14050         cursor->commit_plane = intel_commit_cursor_plane;
14051         cursor->disable_plane = intel_disable_cursor_plane;
14052
14053         drm_universal_plane_init(dev, &cursor->base, 0,
14054                                  &intel_plane_funcs,
14055                                  intel_cursor_formats,
14056                                  ARRAY_SIZE(intel_cursor_formats),
14057                                  DRM_PLANE_TYPE_CURSOR);
14058
14059         if (INTEL_INFO(dev)->gen >= 4) {
14060                 if (!dev->mode_config.rotation_property)
14061                         dev->mode_config.rotation_property =
14062                                 drm_mode_create_rotation_property(dev,
14063                                                         BIT(DRM_ROTATE_0) |
14064                                                         BIT(DRM_ROTATE_180));
14065                 if (dev->mode_config.rotation_property)
14066                         drm_object_attach_property(&cursor->base.base,
14067                                 dev->mode_config.rotation_property,
14068                                 state->base.rotation);
14069         }
14070
14071         if (INTEL_INFO(dev)->gen >=9)
14072                 state->scaler_id = -1;
14073
14074         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14075
14076         return &cursor->base;
14077 }
14078
14079 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14080         struct intel_crtc_state *crtc_state)
14081 {
14082         int i;
14083         struct intel_scaler *intel_scaler;
14084         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14085
14086         for (i = 0; i < intel_crtc->num_scalers; i++) {
14087                 intel_scaler = &scaler_state->scalers[i];
14088                 intel_scaler->in_use = 0;
14089                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14090         }
14091
14092         scaler_state->scaler_id = -1;
14093 }
14094
14095 static void intel_crtc_init(struct drm_device *dev, int pipe)
14096 {
14097         struct drm_i915_private *dev_priv = dev->dev_private;
14098         struct intel_crtc *intel_crtc;
14099         struct intel_crtc_state *crtc_state = NULL;
14100         struct drm_plane *primary = NULL;
14101         struct drm_plane *cursor = NULL;
14102         int i, ret;
14103
14104         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14105         if (intel_crtc == NULL)
14106                 return;
14107
14108         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14109         if (!crtc_state)
14110                 goto fail;
14111         intel_crtc->config = crtc_state;
14112         intel_crtc->base.state = &crtc_state->base;
14113         crtc_state->base.crtc = &intel_crtc->base;
14114
14115         /* initialize shared scalers */
14116         if (INTEL_INFO(dev)->gen >= 9) {
14117                 if (pipe == PIPE_C)
14118                         intel_crtc->num_scalers = 1;
14119                 else
14120                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14121
14122                 skl_init_scalers(dev, intel_crtc, crtc_state);
14123         }
14124
14125         primary = intel_primary_plane_create(dev, pipe);
14126         if (!primary)
14127                 goto fail;
14128
14129         cursor = intel_cursor_plane_create(dev, pipe);
14130         if (!cursor)
14131                 goto fail;
14132
14133         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14134                                         cursor, &intel_crtc_funcs);
14135         if (ret)
14136                 goto fail;
14137
14138         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14139         for (i = 0; i < 256; i++) {
14140                 intel_crtc->lut_r[i] = i;
14141                 intel_crtc->lut_g[i] = i;
14142                 intel_crtc->lut_b[i] = i;
14143         }
14144
14145         /*
14146          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14147          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14148          */
14149         intel_crtc->pipe = pipe;
14150         intel_crtc->plane = pipe;
14151         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14152                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14153                 intel_crtc->plane = !pipe;
14154         }
14155
14156         intel_crtc->cursor_base = ~0;
14157         intel_crtc->cursor_cntl = ~0;
14158         intel_crtc->cursor_size = ~0;
14159
14160         intel_crtc->wm.cxsr_allowed = true;
14161
14162         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14163                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14164         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14165         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14166
14167         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14168
14169         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14170         return;
14171
14172 fail:
14173         if (primary)
14174                 drm_plane_cleanup(primary);
14175         if (cursor)
14176                 drm_plane_cleanup(cursor);
14177         kfree(crtc_state);
14178         kfree(intel_crtc);
14179 }
14180
14181 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14182 {
14183         struct drm_encoder *encoder = connector->base.encoder;
14184         struct drm_device *dev = connector->base.dev;
14185
14186         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14187
14188         if (!encoder || WARN_ON(!encoder->crtc))
14189                 return INVALID_PIPE;
14190
14191         return to_intel_crtc(encoder->crtc)->pipe;
14192 }
14193
14194 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14195                                 struct drm_file *file)
14196 {
14197         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14198         struct drm_crtc *drmmode_crtc;
14199         struct intel_crtc *crtc;
14200
14201         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14202
14203         if (!drmmode_crtc) {
14204                 DRM_ERROR("no such CRTC id\n");
14205                 return -ENOENT;
14206         }
14207
14208         crtc = to_intel_crtc(drmmode_crtc);
14209         pipe_from_crtc_id->pipe = crtc->pipe;
14210
14211         return 0;
14212 }
14213
14214 static int intel_encoder_clones(struct intel_encoder *encoder)
14215 {
14216         struct drm_device *dev = encoder->base.dev;
14217         struct intel_encoder *source_encoder;
14218         int index_mask = 0;
14219         int entry = 0;
14220
14221         for_each_intel_encoder(dev, source_encoder) {
14222                 if (encoders_cloneable(encoder, source_encoder))
14223                         index_mask |= (1 << entry);
14224
14225                 entry++;
14226         }
14227
14228         return index_mask;
14229 }
14230
14231 static bool has_edp_a(struct drm_device *dev)
14232 {
14233         struct drm_i915_private *dev_priv = dev->dev_private;
14234
14235         if (!IS_MOBILE(dev))
14236                 return false;
14237
14238         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14239                 return false;
14240
14241         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14242                 return false;
14243
14244         return true;
14245 }
14246
14247 static bool intel_crt_present(struct drm_device *dev)
14248 {
14249         struct drm_i915_private *dev_priv = dev->dev_private;
14250
14251         if (INTEL_INFO(dev)->gen >= 9)
14252                 return false;
14253
14254         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14255                 return false;
14256
14257         if (IS_CHERRYVIEW(dev))
14258                 return false;
14259
14260         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14261                 return false;
14262
14263         return true;
14264 }
14265
14266 static void intel_setup_outputs(struct drm_device *dev)
14267 {
14268         struct drm_i915_private *dev_priv = dev->dev_private;
14269         struct intel_encoder *encoder;
14270         bool dpd_is_edp = false;
14271
14272         intel_lvds_init(dev);
14273
14274         if (intel_crt_present(dev))
14275                 intel_crt_init(dev);
14276
14277         if (IS_BROXTON(dev)) {
14278                 /*
14279                  * FIXME: Broxton doesn't support port detection via the
14280                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14281                  * detect the ports.
14282                  */
14283                 intel_ddi_init(dev, PORT_A);
14284                 intel_ddi_init(dev, PORT_B);
14285                 intel_ddi_init(dev, PORT_C);
14286         } else if (HAS_DDI(dev)) {
14287                 int found;
14288
14289                 /*
14290                  * Haswell uses DDI functions to detect digital outputs.
14291                  * On SKL pre-D0 the strap isn't connected, so we assume
14292                  * it's there.
14293                  */
14294                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14295                 /* WaIgnoreDDIAStrap: skl */
14296                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14297                         intel_ddi_init(dev, PORT_A);
14298
14299                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14300                  * register */
14301                 found = I915_READ(SFUSE_STRAP);
14302
14303                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14304                         intel_ddi_init(dev, PORT_B);
14305                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14306                         intel_ddi_init(dev, PORT_C);
14307                 if (found & SFUSE_STRAP_DDID_DETECTED)
14308                         intel_ddi_init(dev, PORT_D);
14309                 /*
14310                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14311                  */
14312                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14313                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14314                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14315                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14316                         intel_ddi_init(dev, PORT_E);
14317
14318         } else if (HAS_PCH_SPLIT(dev)) {
14319                 int found;
14320                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14321
14322                 if (has_edp_a(dev))
14323                         intel_dp_init(dev, DP_A, PORT_A);
14324
14325                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14326                         /* PCH SDVOB multiplex with HDMIB */
14327                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14328                         if (!found)
14329                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14330                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14331                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14332                 }
14333
14334                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14335                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14336
14337                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14338                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14339
14340                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14341                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14342
14343                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14344                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14345         } else if (IS_VALLEYVIEW(dev)) {
14346                 /*
14347                  * The DP_DETECTED bit is the latched state of the DDC
14348                  * SDA pin at boot. However since eDP doesn't require DDC
14349                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14350                  * eDP ports may have been muxed to an alternate function.
14351                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14352                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14353                  * detect eDP ports.
14354                  */
14355                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14356                     !intel_dp_is_edp(dev, PORT_B))
14357                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14358                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14359                     intel_dp_is_edp(dev, PORT_B))
14360                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14361
14362                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14363                     !intel_dp_is_edp(dev, PORT_C))
14364                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14365                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14366                     intel_dp_is_edp(dev, PORT_C))
14367                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14368
14369                 if (IS_CHERRYVIEW(dev)) {
14370                         /* eDP not supported on port D, so don't check VBT */
14371                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14372                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14373                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14374                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14375                 }
14376
14377                 intel_dsi_init(dev);
14378         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14379                 bool found = false;
14380
14381                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14382                         DRM_DEBUG_KMS("probing SDVOB\n");
14383                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14384                         if (!found && IS_G4X(dev)) {
14385                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14386                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14387                         }
14388
14389                         if (!found && IS_G4X(dev))
14390                                 intel_dp_init(dev, DP_B, PORT_B);
14391                 }
14392
14393                 /* Before G4X SDVOC doesn't have its own detect register */
14394
14395                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14396                         DRM_DEBUG_KMS("probing SDVOC\n");
14397                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14398                 }
14399
14400                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14401
14402                         if (IS_G4X(dev)) {
14403                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14404                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14405                         }
14406                         if (IS_G4X(dev))
14407                                 intel_dp_init(dev, DP_C, PORT_C);
14408                 }
14409
14410                 if (IS_G4X(dev) &&
14411                     (I915_READ(DP_D) & DP_DETECTED))
14412                         intel_dp_init(dev, DP_D, PORT_D);
14413         } else if (IS_GEN2(dev))
14414                 intel_dvo_init(dev);
14415
14416         if (SUPPORTS_TV(dev))
14417                 intel_tv_init(dev);
14418
14419         intel_psr_init(dev);
14420
14421         for_each_intel_encoder(dev, encoder) {
14422                 encoder->base.possible_crtcs = encoder->crtc_mask;
14423                 encoder->base.possible_clones =
14424                         intel_encoder_clones(encoder);
14425         }
14426
14427         intel_init_pch_refclk(dev);
14428
14429         drm_helper_move_panel_connectors_to_head(dev);
14430 }
14431
14432 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14433 {
14434         struct drm_device *dev = fb->dev;
14435         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14436
14437         drm_framebuffer_cleanup(fb);
14438         mutex_lock(&dev->struct_mutex);
14439         WARN_ON(!intel_fb->obj->framebuffer_references--);
14440         drm_gem_object_unreference(&intel_fb->obj->base);
14441         mutex_unlock(&dev->struct_mutex);
14442         kfree(intel_fb);
14443 }
14444
14445 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14446                                                 struct drm_file *file,
14447                                                 unsigned int *handle)
14448 {
14449         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14450         struct drm_i915_gem_object *obj = intel_fb->obj;
14451
14452         if (obj->userptr.mm) {
14453                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14454                 return -EINVAL;
14455         }
14456
14457         return drm_gem_handle_create(file, &obj->base, handle);
14458 }
14459
14460 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14461                                         struct drm_file *file,
14462                                         unsigned flags, unsigned color,
14463                                         struct drm_clip_rect *clips,
14464                                         unsigned num_clips)
14465 {
14466         struct drm_device *dev = fb->dev;
14467         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14468         struct drm_i915_gem_object *obj = intel_fb->obj;
14469
14470         mutex_lock(&dev->struct_mutex);
14471         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14472         mutex_unlock(&dev->struct_mutex);
14473
14474         return 0;
14475 }
14476
14477 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14478         .destroy = intel_user_framebuffer_destroy,
14479         .create_handle = intel_user_framebuffer_create_handle,
14480         .dirty = intel_user_framebuffer_dirty,
14481 };
14482
14483 static
14484 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14485                          uint32_t pixel_format)
14486 {
14487         u32 gen = INTEL_INFO(dev)->gen;
14488
14489         if (gen >= 9) {
14490                 /* "The stride in bytes must not exceed the of the size of 8K
14491                  *  pixels and 32K bytes."
14492                  */
14493                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14494         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14495                 return 32*1024;
14496         } else if (gen >= 4) {
14497                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14498                         return 16*1024;
14499                 else
14500                         return 32*1024;
14501         } else if (gen >= 3) {
14502                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14503                         return 8*1024;
14504                 else
14505                         return 16*1024;
14506         } else {
14507                 /* XXX DSPC is limited to 4k tiled */
14508                 return 8*1024;
14509         }
14510 }
14511
14512 static int intel_framebuffer_init(struct drm_device *dev,
14513                                   struct intel_framebuffer *intel_fb,
14514                                   struct drm_mode_fb_cmd2 *mode_cmd,
14515                                   struct drm_i915_gem_object *obj)
14516 {
14517         unsigned int aligned_height;
14518         int ret;
14519         u32 pitch_limit, stride_alignment;
14520
14521         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14522
14523         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14524                 /* Enforce that fb modifier and tiling mode match, but only for
14525                  * X-tiled. This is needed for FBC. */
14526                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14527                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14528                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14529                         return -EINVAL;
14530                 }
14531         } else {
14532                 if (obj->tiling_mode == I915_TILING_X)
14533                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14534                 else if (obj->tiling_mode == I915_TILING_Y) {
14535                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14536                         return -EINVAL;
14537                 }
14538         }
14539
14540         /* Passed in modifier sanity checking. */
14541         switch (mode_cmd->modifier[0]) {
14542         case I915_FORMAT_MOD_Y_TILED:
14543         case I915_FORMAT_MOD_Yf_TILED:
14544                 if (INTEL_INFO(dev)->gen < 9) {
14545                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14546                                   mode_cmd->modifier[0]);
14547                         return -EINVAL;
14548                 }
14549         case DRM_FORMAT_MOD_NONE:
14550         case I915_FORMAT_MOD_X_TILED:
14551                 break;
14552         default:
14553                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14554                           mode_cmd->modifier[0]);
14555                 return -EINVAL;
14556         }
14557
14558         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14559                                                      mode_cmd->pixel_format);
14560         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14561                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14562                           mode_cmd->pitches[0], stride_alignment);
14563                 return -EINVAL;
14564         }
14565
14566         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14567                                            mode_cmd->pixel_format);
14568         if (mode_cmd->pitches[0] > pitch_limit) {
14569                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14570                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14571                           "tiled" : "linear",
14572                           mode_cmd->pitches[0], pitch_limit);
14573                 return -EINVAL;
14574         }
14575
14576         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14577             mode_cmd->pitches[0] != obj->stride) {
14578                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14579                           mode_cmd->pitches[0], obj->stride);
14580                 return -EINVAL;
14581         }
14582
14583         /* Reject formats not supported by any plane early. */
14584         switch (mode_cmd->pixel_format) {
14585         case DRM_FORMAT_C8:
14586         case DRM_FORMAT_RGB565:
14587         case DRM_FORMAT_XRGB8888:
14588         case DRM_FORMAT_ARGB8888:
14589                 break;
14590         case DRM_FORMAT_XRGB1555:
14591                 if (INTEL_INFO(dev)->gen > 3) {
14592                         DRM_DEBUG("unsupported pixel format: %s\n",
14593                                   drm_get_format_name(mode_cmd->pixel_format));
14594                         return -EINVAL;
14595                 }
14596                 break;
14597         case DRM_FORMAT_ABGR8888:
14598                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14599                         DRM_DEBUG("unsupported pixel format: %s\n",
14600                                   drm_get_format_name(mode_cmd->pixel_format));
14601                         return -EINVAL;
14602                 }
14603                 break;
14604         case DRM_FORMAT_XBGR8888:
14605         case DRM_FORMAT_XRGB2101010:
14606         case DRM_FORMAT_XBGR2101010:
14607                 if (INTEL_INFO(dev)->gen < 4) {
14608                         DRM_DEBUG("unsupported pixel format: %s\n",
14609                                   drm_get_format_name(mode_cmd->pixel_format));
14610                         return -EINVAL;
14611                 }
14612                 break;
14613         case DRM_FORMAT_ABGR2101010:
14614                 if (!IS_VALLEYVIEW(dev)) {
14615                         DRM_DEBUG("unsupported pixel format: %s\n",
14616                                   drm_get_format_name(mode_cmd->pixel_format));
14617                         return -EINVAL;
14618                 }
14619                 break;
14620         case DRM_FORMAT_YUYV:
14621         case DRM_FORMAT_UYVY:
14622         case DRM_FORMAT_YVYU:
14623         case DRM_FORMAT_VYUY:
14624                 if (INTEL_INFO(dev)->gen < 5) {
14625                         DRM_DEBUG("unsupported pixel format: %s\n",
14626                                   drm_get_format_name(mode_cmd->pixel_format));
14627                         return -EINVAL;
14628                 }
14629                 break;
14630         default:
14631                 DRM_DEBUG("unsupported pixel format: %s\n",
14632                           drm_get_format_name(mode_cmd->pixel_format));
14633                 return -EINVAL;
14634         }
14635
14636         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14637         if (mode_cmd->offsets[0] != 0)
14638                 return -EINVAL;
14639
14640         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14641                                                mode_cmd->pixel_format,
14642                                                mode_cmd->modifier[0]);
14643         /* FIXME drm helper for size checks (especially planar formats)? */
14644         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14645                 return -EINVAL;
14646
14647         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14648         intel_fb->obj = obj;
14649         intel_fb->obj->framebuffer_references++;
14650
14651         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14652         if (ret) {
14653                 DRM_ERROR("framebuffer init failed %d\n", ret);
14654                 return ret;
14655         }
14656
14657         return 0;
14658 }
14659
14660 static struct drm_framebuffer *
14661 intel_user_framebuffer_create(struct drm_device *dev,
14662                               struct drm_file *filp,
14663                               struct drm_mode_fb_cmd2 *user_mode_cmd)
14664 {
14665         struct drm_framebuffer *fb;
14666         struct drm_i915_gem_object *obj;
14667         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14668
14669         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14670                                                 mode_cmd.handles[0]));
14671         if (&obj->base == NULL)
14672                 return ERR_PTR(-ENOENT);
14673
14674         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14675         if (IS_ERR(fb))
14676                 drm_gem_object_unreference_unlocked(&obj->base);
14677
14678         return fb;
14679 }
14680
14681 #ifndef CONFIG_DRM_FBDEV_EMULATION
14682 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14683 {
14684 }
14685 #endif
14686
14687 static const struct drm_mode_config_funcs intel_mode_funcs = {
14688         .fb_create = intel_user_framebuffer_create,
14689         .output_poll_changed = intel_fbdev_output_poll_changed,
14690         .atomic_check = intel_atomic_check,
14691         .atomic_commit = intel_atomic_commit,
14692         .atomic_state_alloc = intel_atomic_state_alloc,
14693         .atomic_state_clear = intel_atomic_state_clear,
14694 };
14695
14696 /* Set up chip specific display functions */
14697 static void intel_init_display(struct drm_device *dev)
14698 {
14699         struct drm_i915_private *dev_priv = dev->dev_private;
14700
14701         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14702                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14703         else if (IS_CHERRYVIEW(dev))
14704                 dev_priv->display.find_dpll = chv_find_best_dpll;
14705         else if (IS_VALLEYVIEW(dev))
14706                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14707         else if (IS_PINEVIEW(dev))
14708                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14709         else
14710                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14711
14712         if (INTEL_INFO(dev)->gen >= 9) {
14713                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14714                 dev_priv->display.get_initial_plane_config =
14715                         skylake_get_initial_plane_config;
14716                 dev_priv->display.crtc_compute_clock =
14717                         haswell_crtc_compute_clock;
14718                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14719                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14720                 dev_priv->display.update_primary_plane =
14721                         skylake_update_primary_plane;
14722         } else if (HAS_DDI(dev)) {
14723                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14724                 dev_priv->display.get_initial_plane_config =
14725                         ironlake_get_initial_plane_config;
14726                 dev_priv->display.crtc_compute_clock =
14727                         haswell_crtc_compute_clock;
14728                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14729                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14730                 dev_priv->display.update_primary_plane =
14731                         ironlake_update_primary_plane;
14732         } else if (HAS_PCH_SPLIT(dev)) {
14733                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14734                 dev_priv->display.get_initial_plane_config =
14735                         ironlake_get_initial_plane_config;
14736                 dev_priv->display.crtc_compute_clock =
14737                         ironlake_crtc_compute_clock;
14738                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14739                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14740                 dev_priv->display.update_primary_plane =
14741                         ironlake_update_primary_plane;
14742         } else if (IS_VALLEYVIEW(dev)) {
14743                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14744                 dev_priv->display.get_initial_plane_config =
14745                         i9xx_get_initial_plane_config;
14746                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14747                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14748                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14749                 dev_priv->display.update_primary_plane =
14750                         i9xx_update_primary_plane;
14751         } else {
14752                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14753                 dev_priv->display.get_initial_plane_config =
14754                         i9xx_get_initial_plane_config;
14755                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14756                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14757                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14758                 dev_priv->display.update_primary_plane =
14759                         i9xx_update_primary_plane;
14760         }
14761
14762         /* Returns the core display clock speed */
14763         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14764                 dev_priv->display.get_display_clock_speed =
14765                         skylake_get_display_clock_speed;
14766         else if (IS_BROXTON(dev))
14767                 dev_priv->display.get_display_clock_speed =
14768                         broxton_get_display_clock_speed;
14769         else if (IS_BROADWELL(dev))
14770                 dev_priv->display.get_display_clock_speed =
14771                         broadwell_get_display_clock_speed;
14772         else if (IS_HASWELL(dev))
14773                 dev_priv->display.get_display_clock_speed =
14774                         haswell_get_display_clock_speed;
14775         else if (IS_VALLEYVIEW(dev))
14776                 dev_priv->display.get_display_clock_speed =
14777                         valleyview_get_display_clock_speed;
14778         else if (IS_GEN5(dev))
14779                 dev_priv->display.get_display_clock_speed =
14780                         ilk_get_display_clock_speed;
14781         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14782                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14783                 dev_priv->display.get_display_clock_speed =
14784                         i945_get_display_clock_speed;
14785         else if (IS_GM45(dev))
14786                 dev_priv->display.get_display_clock_speed =
14787                         gm45_get_display_clock_speed;
14788         else if (IS_CRESTLINE(dev))
14789                 dev_priv->display.get_display_clock_speed =
14790                         i965gm_get_display_clock_speed;
14791         else if (IS_PINEVIEW(dev))
14792                 dev_priv->display.get_display_clock_speed =
14793                         pnv_get_display_clock_speed;
14794         else if (IS_G33(dev) || IS_G4X(dev))
14795                 dev_priv->display.get_display_clock_speed =
14796                         g33_get_display_clock_speed;
14797         else if (IS_I915G(dev))
14798                 dev_priv->display.get_display_clock_speed =
14799                         i915_get_display_clock_speed;
14800         else if (IS_I945GM(dev) || IS_845G(dev))
14801                 dev_priv->display.get_display_clock_speed =
14802                         i9xx_misc_get_display_clock_speed;
14803         else if (IS_PINEVIEW(dev))
14804                 dev_priv->display.get_display_clock_speed =
14805                         pnv_get_display_clock_speed;
14806         else if (IS_I915GM(dev))
14807                 dev_priv->display.get_display_clock_speed =
14808                         i915gm_get_display_clock_speed;
14809         else if (IS_I865G(dev))
14810                 dev_priv->display.get_display_clock_speed =
14811                         i865_get_display_clock_speed;
14812         else if (IS_I85X(dev))
14813                 dev_priv->display.get_display_clock_speed =
14814                         i85x_get_display_clock_speed;
14815         else { /* 830 */
14816                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14817                 dev_priv->display.get_display_clock_speed =
14818                         i830_get_display_clock_speed;
14819         }
14820
14821         if (IS_GEN5(dev)) {
14822                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14823         } else if (IS_GEN6(dev)) {
14824                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14825         } else if (IS_IVYBRIDGE(dev)) {
14826                 /* FIXME: detect B0+ stepping and use auto training */
14827                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14828         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14829                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14830                 if (IS_BROADWELL(dev)) {
14831                         dev_priv->display.modeset_commit_cdclk =
14832                                 broadwell_modeset_commit_cdclk;
14833                         dev_priv->display.modeset_calc_cdclk =
14834                                 broadwell_modeset_calc_cdclk;
14835                 }
14836         } else if (IS_VALLEYVIEW(dev)) {
14837                 dev_priv->display.modeset_commit_cdclk =
14838                         valleyview_modeset_commit_cdclk;
14839                 dev_priv->display.modeset_calc_cdclk =
14840                         valleyview_modeset_calc_cdclk;
14841         } else if (IS_BROXTON(dev)) {
14842                 dev_priv->display.modeset_commit_cdclk =
14843                         broxton_modeset_commit_cdclk;
14844                 dev_priv->display.modeset_calc_cdclk =
14845                         broxton_modeset_calc_cdclk;
14846         }
14847
14848         switch (INTEL_INFO(dev)->gen) {
14849         case 2:
14850                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14851                 break;
14852
14853         case 3:
14854                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14855                 break;
14856
14857         case 4:
14858         case 5:
14859                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14860                 break;
14861
14862         case 6:
14863                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14864                 break;
14865         case 7:
14866         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14867                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14868                 break;
14869         case 9:
14870                 /* Drop through - unsupported since execlist only. */
14871         default:
14872                 /* Default just returns -ENODEV to indicate unsupported */
14873                 dev_priv->display.queue_flip = intel_default_queue_flip;
14874         }
14875
14876         mutex_init(&dev_priv->pps_mutex);
14877 }
14878
14879 /*
14880  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14881  * resume, or other times.  This quirk makes sure that's the case for
14882  * affected systems.
14883  */
14884 static void quirk_pipea_force(struct drm_device *dev)
14885 {
14886         struct drm_i915_private *dev_priv = dev->dev_private;
14887
14888         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14889         DRM_INFO("applying pipe a force quirk\n");
14890 }
14891
14892 static void quirk_pipeb_force(struct drm_device *dev)
14893 {
14894         struct drm_i915_private *dev_priv = dev->dev_private;
14895
14896         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14897         DRM_INFO("applying pipe b force quirk\n");
14898 }
14899
14900 /*
14901  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14902  */
14903 static void quirk_ssc_force_disable(struct drm_device *dev)
14904 {
14905         struct drm_i915_private *dev_priv = dev->dev_private;
14906         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14907         DRM_INFO("applying lvds SSC disable quirk\n");
14908 }
14909
14910 /*
14911  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14912  * brightness value
14913  */
14914 static void quirk_invert_brightness(struct drm_device *dev)
14915 {
14916         struct drm_i915_private *dev_priv = dev->dev_private;
14917         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14918         DRM_INFO("applying inverted panel brightness quirk\n");
14919 }
14920
14921 /* Some VBT's incorrectly indicate no backlight is present */
14922 static void quirk_backlight_present(struct drm_device *dev)
14923 {
14924         struct drm_i915_private *dev_priv = dev->dev_private;
14925         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14926         DRM_INFO("applying backlight present quirk\n");
14927 }
14928
14929 struct intel_quirk {
14930         int device;
14931         int subsystem_vendor;
14932         int subsystem_device;
14933         void (*hook)(struct drm_device *dev);
14934 };
14935
14936 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14937 struct intel_dmi_quirk {
14938         void (*hook)(struct drm_device *dev);
14939         const struct dmi_system_id (*dmi_id_list)[];
14940 };
14941
14942 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14943 {
14944         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14945         return 1;
14946 }
14947
14948 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14949         {
14950                 .dmi_id_list = &(const struct dmi_system_id[]) {
14951                         {
14952                                 .callback = intel_dmi_reverse_brightness,
14953                                 .ident = "NCR Corporation",
14954                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14955                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14956                                 },
14957                         },
14958                         { }  /* terminating entry */
14959                 },
14960                 .hook = quirk_invert_brightness,
14961         },
14962 };
14963
14964 static struct intel_quirk intel_quirks[] = {
14965         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14966         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14967
14968         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14969         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14970
14971         /* 830 needs to leave pipe A & dpll A up */
14972         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14973
14974         /* 830 needs to leave pipe B & dpll B up */
14975         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14976
14977         /* Lenovo U160 cannot use SSC on LVDS */
14978         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14979
14980         /* Sony Vaio Y cannot use SSC on LVDS */
14981         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14982
14983         /* Acer Aspire 5734Z must invert backlight brightness */
14984         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14985
14986         /* Acer/eMachines G725 */
14987         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14988
14989         /* Acer/eMachines e725 */
14990         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14991
14992         /* Acer/Packard Bell NCL20 */
14993         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14994
14995         /* Acer Aspire 4736Z */
14996         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14997
14998         /* Acer Aspire 5336 */
14999         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15000
15001         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15002         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15003
15004         /* Acer C720 Chromebook (Core i3 4005U) */
15005         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15006
15007         /* Apple Macbook 2,1 (Core 2 T7400) */
15008         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15009
15010         /* Apple Macbook 4,1 */
15011         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15012
15013         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15014         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15015
15016         /* HP Chromebook 14 (Celeron 2955U) */
15017         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15018
15019         /* Dell Chromebook 11 */
15020         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15021
15022         /* Dell Chromebook 11 (2015 version) */
15023         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15024 };
15025
15026 static void intel_init_quirks(struct drm_device *dev)
15027 {
15028         struct pci_dev *d = dev->pdev;
15029         int i;
15030
15031         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15032                 struct intel_quirk *q = &intel_quirks[i];
15033
15034                 if (d->device == q->device &&
15035                     (d->subsystem_vendor == q->subsystem_vendor ||
15036                      q->subsystem_vendor == PCI_ANY_ID) &&
15037                     (d->subsystem_device == q->subsystem_device ||
15038                      q->subsystem_device == PCI_ANY_ID))
15039                         q->hook(dev);
15040         }
15041         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15042                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15043                         intel_dmi_quirks[i].hook(dev);
15044         }
15045 }
15046
15047 /* Disable the VGA plane that we never use */
15048 static void i915_disable_vga(struct drm_device *dev)
15049 {
15050         struct drm_i915_private *dev_priv = dev->dev_private;
15051         u8 sr1;
15052         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15053
15054         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15055         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15056         outb(SR01, VGA_SR_INDEX);
15057         sr1 = inb(VGA_SR_DATA);
15058         outb(sr1 | 1<<5, VGA_SR_DATA);
15059         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15060         udelay(300);
15061
15062         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15063         POSTING_READ(vga_reg);
15064 }
15065
15066 void intel_modeset_init_hw(struct drm_device *dev)
15067 {
15068         intel_update_cdclk(dev);
15069         intel_prepare_ddi(dev);
15070         intel_init_clock_gating(dev);
15071         intel_enable_gt_powersave(dev);
15072 }
15073
15074 void intel_modeset_init(struct drm_device *dev)
15075 {
15076         struct drm_i915_private *dev_priv = dev->dev_private;
15077         int sprite, ret;
15078         enum pipe pipe;
15079         struct intel_crtc *crtc;
15080
15081         drm_mode_config_init(dev);
15082
15083         dev->mode_config.min_width = 0;
15084         dev->mode_config.min_height = 0;
15085
15086         dev->mode_config.preferred_depth = 24;
15087         dev->mode_config.prefer_shadow = 1;
15088
15089         dev->mode_config.allow_fb_modifiers = true;
15090
15091         dev->mode_config.funcs = &intel_mode_funcs;
15092
15093         intel_init_quirks(dev);
15094
15095         intel_init_pm(dev);
15096
15097         if (INTEL_INFO(dev)->num_pipes == 0)
15098                 return;
15099
15100         /*
15101          * There may be no VBT; and if the BIOS enabled SSC we can
15102          * just keep using it to avoid unnecessary flicker.  Whereas if the
15103          * BIOS isn't using it, don't assume it will work even if the VBT
15104          * indicates as much.
15105          */
15106         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15107                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15108                                             DREF_SSC1_ENABLE);
15109
15110                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15111                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15112                                      bios_lvds_use_ssc ? "en" : "dis",
15113                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15114                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15115                 }
15116         }
15117
15118         intel_init_display(dev);
15119         intel_init_audio(dev);
15120
15121         if (IS_GEN2(dev)) {
15122                 dev->mode_config.max_width = 2048;
15123                 dev->mode_config.max_height = 2048;
15124         } else if (IS_GEN3(dev)) {
15125                 dev->mode_config.max_width = 4096;
15126                 dev->mode_config.max_height = 4096;
15127         } else {
15128                 dev->mode_config.max_width = 8192;
15129                 dev->mode_config.max_height = 8192;
15130         }
15131
15132         if (IS_845G(dev) || IS_I865G(dev)) {
15133                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15134                 dev->mode_config.cursor_height = 1023;
15135         } else if (IS_GEN2(dev)) {
15136                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15137                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15138         } else {
15139                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15140                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15141         }
15142
15143         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15144
15145         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15146                       INTEL_INFO(dev)->num_pipes,
15147                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15148
15149         for_each_pipe(dev_priv, pipe) {
15150                 intel_crtc_init(dev, pipe);
15151                 for_each_sprite(dev_priv, pipe, sprite) {
15152                         ret = intel_plane_init(dev, pipe, sprite);
15153                         if (ret)
15154                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15155                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15156                 }
15157         }
15158
15159         intel_update_czclk(dev_priv);
15160         intel_update_cdclk(dev);
15161
15162         intel_shared_dpll_init(dev);
15163
15164         /* Just disable it once at startup */
15165         i915_disable_vga(dev);
15166         intel_setup_outputs(dev);
15167
15168         drm_modeset_lock_all(dev);
15169         intel_modeset_setup_hw_state(dev);
15170         drm_modeset_unlock_all(dev);
15171
15172         for_each_intel_crtc(dev, crtc) {
15173                 struct intel_initial_plane_config plane_config = {};
15174
15175                 if (!crtc->active)
15176                         continue;
15177
15178                 /*
15179                  * Note that reserving the BIOS fb up front prevents us
15180                  * from stuffing other stolen allocations like the ring
15181                  * on top.  This prevents some ugliness at boot time, and
15182                  * can even allow for smooth boot transitions if the BIOS
15183                  * fb is large enough for the active pipe configuration.
15184                  */
15185                 dev_priv->display.get_initial_plane_config(crtc,
15186                                                            &plane_config);
15187
15188                 /*
15189                  * If the fb is shared between multiple heads, we'll
15190                  * just get the first one.
15191                  */
15192                 intel_find_initial_plane_obj(crtc, &plane_config);
15193         }
15194 }
15195
15196 static void intel_enable_pipe_a(struct drm_device *dev)
15197 {
15198         struct intel_connector *connector;
15199         struct drm_connector *crt = NULL;
15200         struct intel_load_detect_pipe load_detect_temp;
15201         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15202
15203         /* We can't just switch on the pipe A, we need to set things up with a
15204          * proper mode and output configuration. As a gross hack, enable pipe A
15205          * by enabling the load detect pipe once. */
15206         for_each_intel_connector(dev, connector) {
15207                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15208                         crt = &connector->base;
15209                         break;
15210                 }
15211         }
15212
15213         if (!crt)
15214                 return;
15215
15216         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15217                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15218 }
15219
15220 static bool
15221 intel_check_plane_mapping(struct intel_crtc *crtc)
15222 {
15223         struct drm_device *dev = crtc->base.dev;
15224         struct drm_i915_private *dev_priv = dev->dev_private;
15225         u32 val;
15226
15227         if (INTEL_INFO(dev)->num_pipes == 1)
15228                 return true;
15229
15230         val = I915_READ(DSPCNTR(!crtc->plane));
15231
15232         if ((val & DISPLAY_PLANE_ENABLE) &&
15233             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15234                 return false;
15235
15236         return true;
15237 }
15238
15239 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15240 {
15241         struct drm_device *dev = crtc->base.dev;
15242         struct intel_encoder *encoder;
15243
15244         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15245                 return true;
15246
15247         return false;
15248 }
15249
15250 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15251 {
15252         struct drm_device *dev = crtc->base.dev;
15253         struct drm_i915_private *dev_priv = dev->dev_private;
15254         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15255
15256         /* Clear any frame start delays used for debugging left by the BIOS */
15257         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15258
15259         /* restore vblank interrupts to correct state */
15260         drm_crtc_vblank_reset(&crtc->base);
15261         if (crtc->active) {
15262                 struct intel_plane *plane;
15263
15264                 drm_crtc_vblank_on(&crtc->base);
15265
15266                 /* Disable everything but the primary plane */
15267                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15268                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15269                                 continue;
15270
15271                         plane->disable_plane(&plane->base, &crtc->base);
15272                 }
15273         }
15274
15275         /* We need to sanitize the plane -> pipe mapping first because this will
15276          * disable the crtc (and hence change the state) if it is wrong. Note
15277          * that gen4+ has a fixed plane -> pipe mapping.  */
15278         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15279                 bool plane;
15280
15281                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15282                               crtc->base.base.id);
15283
15284                 /* Pipe has the wrong plane attached and the plane is active.
15285                  * Temporarily change the plane mapping and disable everything
15286                  * ...  */
15287                 plane = crtc->plane;
15288                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15289                 crtc->plane = !plane;
15290                 intel_crtc_disable_noatomic(&crtc->base);
15291                 crtc->plane = plane;
15292         }
15293
15294         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15295             crtc->pipe == PIPE_A && !crtc->active) {
15296                 /* BIOS forgot to enable pipe A, this mostly happens after
15297                  * resume. Force-enable the pipe to fix this, the update_dpms
15298                  * call below we restore the pipe to the right state, but leave
15299                  * the required bits on. */
15300                 intel_enable_pipe_a(dev);
15301         }
15302
15303         /* Adjust the state of the output pipe according to whether we
15304          * have active connectors/encoders. */
15305         if (!intel_crtc_has_encoders(crtc))
15306                 intel_crtc_disable_noatomic(&crtc->base);
15307
15308         if (crtc->active != crtc->base.state->active) {
15309                 struct intel_encoder *encoder;
15310
15311                 /* This can happen either due to bugs in the get_hw_state
15312                  * functions or because of calls to intel_crtc_disable_noatomic,
15313                  * or because the pipe is force-enabled due to the
15314                  * pipe A quirk. */
15315                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15316                               crtc->base.base.id,
15317                               crtc->base.state->enable ? "enabled" : "disabled",
15318                               crtc->active ? "enabled" : "disabled");
15319
15320                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15321                 crtc->base.state->active = crtc->active;
15322                 crtc->base.enabled = crtc->active;
15323
15324                 /* Because we only establish the connector -> encoder ->
15325                  * crtc links if something is active, this means the
15326                  * crtc is now deactivated. Break the links. connector
15327                  * -> encoder links are only establish when things are
15328                  *  actually up, hence no need to break them. */
15329                 WARN_ON(crtc->active);
15330
15331                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15332                         encoder->base.crtc = NULL;
15333         }
15334
15335         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15336                 /*
15337                  * We start out with underrun reporting disabled to avoid races.
15338                  * For correct bookkeeping mark this on active crtcs.
15339                  *
15340                  * Also on gmch platforms we dont have any hardware bits to
15341                  * disable the underrun reporting. Which means we need to start
15342                  * out with underrun reporting disabled also on inactive pipes,
15343                  * since otherwise we'll complain about the garbage we read when
15344                  * e.g. coming up after runtime pm.
15345                  *
15346                  * No protection against concurrent access is required - at
15347                  * worst a fifo underrun happens which also sets this to false.
15348                  */
15349                 crtc->cpu_fifo_underrun_disabled = true;
15350                 crtc->pch_fifo_underrun_disabled = true;
15351         }
15352 }
15353
15354 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15355 {
15356         struct intel_connector *connector;
15357         struct drm_device *dev = encoder->base.dev;
15358         bool active = false;
15359
15360         /* We need to check both for a crtc link (meaning that the
15361          * encoder is active and trying to read from a pipe) and the
15362          * pipe itself being active. */
15363         bool has_active_crtc = encoder->base.crtc &&
15364                 to_intel_crtc(encoder->base.crtc)->active;
15365
15366         for_each_intel_connector(dev, connector) {
15367                 if (connector->base.encoder != &encoder->base)
15368                         continue;
15369
15370                 active = true;
15371                 break;
15372         }
15373
15374         if (active && !has_active_crtc) {
15375                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15376                               encoder->base.base.id,
15377                               encoder->base.name);
15378
15379                 /* Connector is active, but has no active pipe. This is
15380                  * fallout from our resume register restoring. Disable
15381                  * the encoder manually again. */
15382                 if (encoder->base.crtc) {
15383                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15384                                       encoder->base.base.id,
15385                                       encoder->base.name);
15386                         encoder->disable(encoder);
15387                         if (encoder->post_disable)
15388                                 encoder->post_disable(encoder);
15389                 }
15390                 encoder->base.crtc = NULL;
15391
15392                 /* Inconsistent output/port/pipe state happens presumably due to
15393                  * a bug in one of the get_hw_state functions. Or someplace else
15394                  * in our code, like the register restore mess on resume. Clamp
15395                  * things to off as a safer default. */
15396                 for_each_intel_connector(dev, connector) {
15397                         if (connector->encoder != encoder)
15398                                 continue;
15399                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15400                         connector->base.encoder = NULL;
15401                 }
15402         }
15403         /* Enabled encoders without active connectors will be fixed in
15404          * the crtc fixup. */
15405 }
15406
15407 void i915_redisable_vga_power_on(struct drm_device *dev)
15408 {
15409         struct drm_i915_private *dev_priv = dev->dev_private;
15410         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15411
15412         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15413                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15414                 i915_disable_vga(dev);
15415         }
15416 }
15417
15418 void i915_redisable_vga(struct drm_device *dev)
15419 {
15420         struct drm_i915_private *dev_priv = dev->dev_private;
15421
15422         /* This function can be called both from intel_modeset_setup_hw_state or
15423          * at a very early point in our resume sequence, where the power well
15424          * structures are not yet restored. Since this function is at a very
15425          * paranoid "someone might have enabled VGA while we were not looking"
15426          * level, just check if the power well is enabled instead of trying to
15427          * follow the "don't touch the power well if we don't need it" policy
15428          * the rest of the driver uses. */
15429         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15430                 return;
15431
15432         i915_redisable_vga_power_on(dev);
15433 }
15434
15435 static bool primary_get_hw_state(struct intel_plane *plane)
15436 {
15437         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15438
15439         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15440 }
15441
15442 /* FIXME read out full plane state for all planes */
15443 static void readout_plane_state(struct intel_crtc *crtc)
15444 {
15445         struct drm_plane *primary = crtc->base.primary;
15446         struct intel_plane_state *plane_state =
15447                 to_intel_plane_state(primary->state);
15448
15449         plane_state->visible = crtc->active &&
15450                 primary_get_hw_state(to_intel_plane(primary));
15451
15452         if (plane_state->visible)
15453                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15454 }
15455
15456 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15457 {
15458         struct drm_i915_private *dev_priv = dev->dev_private;
15459         enum pipe pipe;
15460         struct intel_crtc *crtc;
15461         struct intel_encoder *encoder;
15462         struct intel_connector *connector;
15463         int i;
15464
15465         for_each_intel_crtc(dev, crtc) {
15466                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15467                 memset(crtc->config, 0, sizeof(*crtc->config));
15468                 crtc->config->base.crtc = &crtc->base;
15469
15470                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15471                                                                  crtc->config);
15472
15473                 crtc->base.state->active = crtc->active;
15474                 crtc->base.enabled = crtc->active;
15475
15476                 readout_plane_state(crtc);
15477
15478                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15479                               crtc->base.base.id,
15480                               crtc->active ? "enabled" : "disabled");
15481         }
15482
15483         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15484                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15485
15486                 pll->on = pll->get_hw_state(dev_priv, pll,
15487                                             &pll->config.hw_state);
15488                 pll->active = 0;
15489                 pll->config.crtc_mask = 0;
15490                 for_each_intel_crtc(dev, crtc) {
15491                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15492                                 pll->active++;
15493                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15494                         }
15495                 }
15496
15497                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15498                               pll->name, pll->config.crtc_mask, pll->on);
15499
15500                 if (pll->config.crtc_mask)
15501                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15502         }
15503
15504         for_each_intel_encoder(dev, encoder) {
15505                 pipe = 0;
15506
15507                 if (encoder->get_hw_state(encoder, &pipe)) {
15508                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15509                         encoder->base.crtc = &crtc->base;
15510                         encoder->get_config(encoder, crtc->config);
15511                 } else {
15512                         encoder->base.crtc = NULL;
15513                 }
15514
15515                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15516                               encoder->base.base.id,
15517                               encoder->base.name,
15518                               encoder->base.crtc ? "enabled" : "disabled",
15519                               pipe_name(pipe));
15520         }
15521
15522         for_each_intel_connector(dev, connector) {
15523                 if (connector->get_hw_state(connector)) {
15524                         connector->base.dpms = DRM_MODE_DPMS_ON;
15525                         connector->base.encoder = &connector->encoder->base;
15526                 } else {
15527                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15528                         connector->base.encoder = NULL;
15529                 }
15530                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15531                               connector->base.base.id,
15532                               connector->base.name,
15533                               connector->base.encoder ? "enabled" : "disabled");
15534         }
15535
15536         for_each_intel_crtc(dev, crtc) {
15537                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15538
15539                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15540                 if (crtc->base.state->active) {
15541                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15542                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15543                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15544
15545                         /*
15546                          * The initial mode needs to be set in order to keep
15547                          * the atomic core happy. It wants a valid mode if the
15548                          * crtc's enabled, so we do the above call.
15549                          *
15550                          * At this point some state updated by the connectors
15551                          * in their ->detect() callback has not run yet, so
15552                          * no recalculation can be done yet.
15553                          *
15554                          * Even if we could do a recalculation and modeset
15555                          * right now it would cause a double modeset if
15556                          * fbdev or userspace chooses a different initial mode.
15557                          *
15558                          * If that happens, someone indicated they wanted a
15559                          * mode change, which means it's safe to do a full
15560                          * recalculation.
15561                          */
15562                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15563
15564                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15565                         update_scanline_offset(crtc);
15566                 }
15567         }
15568 }
15569
15570 /* Scan out the current hw modeset state,
15571  * and sanitizes it to the current state
15572  */
15573 static void
15574 intel_modeset_setup_hw_state(struct drm_device *dev)
15575 {
15576         struct drm_i915_private *dev_priv = dev->dev_private;
15577         enum pipe pipe;
15578         struct intel_crtc *crtc;
15579         struct intel_encoder *encoder;
15580         int i;
15581
15582         intel_modeset_readout_hw_state(dev);
15583
15584         /* HW state is read out, now we need to sanitize this mess. */
15585         for_each_intel_encoder(dev, encoder) {
15586                 intel_sanitize_encoder(encoder);
15587         }
15588
15589         for_each_pipe(dev_priv, pipe) {
15590                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15591                 intel_sanitize_crtc(crtc);
15592                 intel_dump_pipe_config(crtc, crtc->config,
15593                                        "[setup_hw_state]");
15594         }
15595
15596         intel_modeset_update_connector_atomic_state(dev);
15597
15598         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15599                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15600
15601                 if (!pll->on || pll->active)
15602                         continue;
15603
15604                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15605
15606                 pll->disable(dev_priv, pll);
15607                 pll->on = false;
15608         }
15609
15610         if (IS_VALLEYVIEW(dev))
15611                 vlv_wm_get_hw_state(dev);
15612         else if (IS_GEN9(dev))
15613                 skl_wm_get_hw_state(dev);
15614         else if (HAS_PCH_SPLIT(dev))
15615                 ilk_wm_get_hw_state(dev);
15616
15617         for_each_intel_crtc(dev, crtc) {
15618                 unsigned long put_domains;
15619
15620                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15621                 if (WARN_ON(put_domains))
15622                         modeset_put_power_domains(dev_priv, put_domains);
15623         }
15624         intel_display_set_init_power(dev_priv, false);
15625 }
15626
15627 void intel_display_resume(struct drm_device *dev)
15628 {
15629         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15630         struct intel_connector *conn;
15631         struct intel_plane *plane;
15632         struct drm_crtc *crtc;
15633         int ret;
15634
15635         if (!state)
15636                 return;
15637
15638         state->acquire_ctx = dev->mode_config.acquire_ctx;
15639
15640         /* preserve complete old state, including dpll */
15641         intel_atomic_get_shared_dpll_state(state);
15642
15643         for_each_crtc(dev, crtc) {
15644                 struct drm_crtc_state *crtc_state =
15645                         drm_atomic_get_crtc_state(state, crtc);
15646
15647                 ret = PTR_ERR_OR_ZERO(crtc_state);
15648                 if (ret)
15649                         goto err;
15650
15651                 /* force a restore */
15652                 crtc_state->mode_changed = true;
15653         }
15654
15655         for_each_intel_plane(dev, plane) {
15656                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15657                 if (ret)
15658                         goto err;
15659         }
15660
15661         for_each_intel_connector(dev, conn) {
15662                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15663                 if (ret)
15664                         goto err;
15665         }
15666
15667         intel_modeset_setup_hw_state(dev);
15668
15669         i915_redisable_vga(dev);
15670         ret = drm_atomic_commit(state);
15671         if (!ret)
15672                 return;
15673
15674 err:
15675         DRM_ERROR("Restoring old state failed with %i\n", ret);
15676         drm_atomic_state_free(state);
15677 }
15678
15679 void intel_modeset_gem_init(struct drm_device *dev)
15680 {
15681         struct drm_crtc *c;
15682         struct drm_i915_gem_object *obj;
15683         int ret;
15684
15685         mutex_lock(&dev->struct_mutex);
15686         intel_init_gt_powersave(dev);
15687         mutex_unlock(&dev->struct_mutex);
15688
15689         intel_modeset_init_hw(dev);
15690
15691         intel_setup_overlay(dev);
15692
15693         /*
15694          * Make sure any fbs we allocated at startup are properly
15695          * pinned & fenced.  When we do the allocation it's too early
15696          * for this.
15697          */
15698         for_each_crtc(dev, c) {
15699                 obj = intel_fb_obj(c->primary->fb);
15700                 if (obj == NULL)
15701                         continue;
15702
15703                 mutex_lock(&dev->struct_mutex);
15704                 ret = intel_pin_and_fence_fb_obj(c->primary,
15705                                                  c->primary->fb,
15706                                                  c->primary->state);
15707                 mutex_unlock(&dev->struct_mutex);
15708                 if (ret) {
15709                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15710                                   to_intel_crtc(c)->pipe);
15711                         drm_framebuffer_unreference(c->primary->fb);
15712                         c->primary->fb = NULL;
15713                         c->primary->crtc = c->primary->state->crtc = NULL;
15714                         update_state_fb(c->primary);
15715                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15716                 }
15717         }
15718
15719         intel_backlight_register(dev);
15720 }
15721
15722 void intel_connector_unregister(struct intel_connector *intel_connector)
15723 {
15724         struct drm_connector *connector = &intel_connector->base;
15725
15726         intel_panel_destroy_backlight(connector);
15727         drm_connector_unregister(connector);
15728 }
15729
15730 void intel_modeset_cleanup(struct drm_device *dev)
15731 {
15732         struct drm_i915_private *dev_priv = dev->dev_private;
15733         struct drm_connector *connector;
15734
15735         intel_disable_gt_powersave(dev);
15736
15737         intel_backlight_unregister(dev);
15738
15739         /*
15740          * Interrupts and polling as the first thing to avoid creating havoc.
15741          * Too much stuff here (turning of connectors, ...) would
15742          * experience fancy races otherwise.
15743          */
15744         intel_irq_uninstall(dev_priv);
15745
15746         /*
15747          * Due to the hpd irq storm handling the hotplug work can re-arm the
15748          * poll handlers. Hence disable polling after hpd handling is shut down.
15749          */
15750         drm_kms_helper_poll_fini(dev);
15751
15752         intel_unregister_dsm_handler();
15753
15754         intel_fbc_disable(dev_priv);
15755
15756         /* flush any delayed tasks or pending work */
15757         flush_scheduled_work();
15758
15759         /* destroy the backlight and sysfs files before encoders/connectors */
15760         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15761                 struct intel_connector *intel_connector;
15762
15763                 intel_connector = to_intel_connector(connector);
15764                 intel_connector->unregister(intel_connector);
15765         }
15766
15767         drm_mode_config_cleanup(dev);
15768
15769         intel_cleanup_overlay(dev);
15770
15771         mutex_lock(&dev->struct_mutex);
15772         intel_cleanup_gt_powersave(dev);
15773         mutex_unlock(&dev->struct_mutex);
15774 }
15775
15776 /*
15777  * Return which encoder is currently attached for connector.
15778  */
15779 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15780 {
15781         return &intel_attached_encoder(connector)->base;
15782 }
15783
15784 void intel_connector_attach_encoder(struct intel_connector *connector,
15785                                     struct intel_encoder *encoder)
15786 {
15787         connector->encoder = encoder;
15788         drm_mode_connector_attach_encoder(&connector->base,
15789                                           &encoder->base);
15790 }
15791
15792 /*
15793  * set vga decode state - true == enable VGA decode
15794  */
15795 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15796 {
15797         struct drm_i915_private *dev_priv = dev->dev_private;
15798         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15799         u16 gmch_ctrl;
15800
15801         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15802                 DRM_ERROR("failed to read control word\n");
15803                 return -EIO;
15804         }
15805
15806         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15807                 return 0;
15808
15809         if (state)
15810                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15811         else
15812                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15813
15814         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15815                 DRM_ERROR("failed to write control word\n");
15816                 return -EIO;
15817         }
15818
15819         return 0;
15820 }
15821
15822 struct intel_display_error_state {
15823
15824         u32 power_well_driver;
15825
15826         int num_transcoders;
15827
15828         struct intel_cursor_error_state {
15829                 u32 control;
15830                 u32 position;
15831                 u32 base;
15832                 u32 size;
15833         } cursor[I915_MAX_PIPES];
15834
15835         struct intel_pipe_error_state {
15836                 bool power_domain_on;
15837                 u32 source;
15838                 u32 stat;
15839         } pipe[I915_MAX_PIPES];
15840
15841         struct intel_plane_error_state {
15842                 u32 control;
15843                 u32 stride;
15844                 u32 size;
15845                 u32 pos;
15846                 u32 addr;
15847                 u32 surface;
15848                 u32 tile_offset;
15849         } plane[I915_MAX_PIPES];
15850
15851         struct intel_transcoder_error_state {
15852                 bool power_domain_on;
15853                 enum transcoder cpu_transcoder;
15854
15855                 u32 conf;
15856
15857                 u32 htotal;
15858                 u32 hblank;
15859                 u32 hsync;
15860                 u32 vtotal;
15861                 u32 vblank;
15862                 u32 vsync;
15863         } transcoder[4];
15864 };
15865
15866 struct intel_display_error_state *
15867 intel_display_capture_error_state(struct drm_device *dev)
15868 {
15869         struct drm_i915_private *dev_priv = dev->dev_private;
15870         struct intel_display_error_state *error;
15871         int transcoders[] = {
15872                 TRANSCODER_A,
15873                 TRANSCODER_B,
15874                 TRANSCODER_C,
15875                 TRANSCODER_EDP,
15876         };
15877         int i;
15878
15879         if (INTEL_INFO(dev)->num_pipes == 0)
15880                 return NULL;
15881
15882         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15883         if (error == NULL)
15884                 return NULL;
15885
15886         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15887                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15888
15889         for_each_pipe(dev_priv, i) {
15890                 error->pipe[i].power_domain_on =
15891                         __intel_display_power_is_enabled(dev_priv,
15892                                                          POWER_DOMAIN_PIPE(i));
15893                 if (!error->pipe[i].power_domain_on)
15894                         continue;
15895
15896                 error->cursor[i].control = I915_READ(CURCNTR(i));
15897                 error->cursor[i].position = I915_READ(CURPOS(i));
15898                 error->cursor[i].base = I915_READ(CURBASE(i));
15899
15900                 error->plane[i].control = I915_READ(DSPCNTR(i));
15901                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15902                 if (INTEL_INFO(dev)->gen <= 3) {
15903                         error->plane[i].size = I915_READ(DSPSIZE(i));
15904                         error->plane[i].pos = I915_READ(DSPPOS(i));
15905                 }
15906                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15907                         error->plane[i].addr = I915_READ(DSPADDR(i));
15908                 if (INTEL_INFO(dev)->gen >= 4) {
15909                         error->plane[i].surface = I915_READ(DSPSURF(i));
15910                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15911                 }
15912
15913                 error->pipe[i].source = I915_READ(PIPESRC(i));
15914
15915                 if (HAS_GMCH_DISPLAY(dev))
15916                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15917         }
15918
15919         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15920         if (HAS_DDI(dev_priv->dev))
15921                 error->num_transcoders++; /* Account for eDP. */
15922
15923         for (i = 0; i < error->num_transcoders; i++) {
15924                 enum transcoder cpu_transcoder = transcoders[i];
15925
15926                 error->transcoder[i].power_domain_on =
15927                         __intel_display_power_is_enabled(dev_priv,
15928                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15929                 if (!error->transcoder[i].power_domain_on)
15930                         continue;
15931
15932                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15933
15934                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15935                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15936                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15937                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15938                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15939                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15940                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15941         }
15942
15943         return error;
15944 }
15945
15946 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15947
15948 void
15949 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15950                                 struct drm_device *dev,
15951                                 struct intel_display_error_state *error)
15952 {
15953         struct drm_i915_private *dev_priv = dev->dev_private;
15954         int i;
15955
15956         if (!error)
15957                 return;
15958
15959         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15960         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15961                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15962                            error->power_well_driver);
15963         for_each_pipe(dev_priv, i) {
15964                 err_printf(m, "Pipe [%d]:\n", i);
15965                 err_printf(m, "  Power: %s\n",
15966                            error->pipe[i].power_domain_on ? "on" : "off");
15967                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15968                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15969
15970                 err_printf(m, "Plane [%d]:\n", i);
15971                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15972                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15973                 if (INTEL_INFO(dev)->gen <= 3) {
15974                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15975                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15976                 }
15977                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15978                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15979                 if (INTEL_INFO(dev)->gen >= 4) {
15980                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15981                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15982                 }
15983
15984                 err_printf(m, "Cursor [%d]:\n", i);
15985                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15986                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15987                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15988         }
15989
15990         for (i = 0; i < error->num_transcoders; i++) {
15991                 err_printf(m, "CPU transcoder: %c\n",
15992                            transcoder_name(error->transcoder[i].cpu_transcoder));
15993                 err_printf(m, "  Power: %s\n",
15994                            error->transcoder[i].power_domain_on ? "on" : "off");
15995                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15996                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15997                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15998                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15999                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16000                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16001                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16002         }
16003 }
16004
16005 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16006 {
16007         struct intel_crtc *crtc;
16008
16009         for_each_intel_crtc(dev, crtc) {
16010                 struct intel_unpin_work *work;
16011
16012                 spin_lock_irq(&dev->event_lock);
16013
16014                 work = crtc->unpin_work;
16015
16016                 if (work && work->event &&
16017                     work->event->base.file_priv == file) {
16018                         kfree(work->event);
16019                         work->event = NULL;
16020                 }
16021
16022                 spin_unlock_irq(&dev->event_lock);
16023         }
16024 }