2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
65 typedef struct intel_limit intel_limit_t;
67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
72 intel_pch_rawclk(struct drm_device *dev)
74 struct drm_i915_private *dev_priv = dev->dev_private;
76 WARN_ON(!HAS_PCH_SPLIT(dev));
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
81 static inline u32 /* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device *dev)
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac = {
92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds = {
118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo = {
131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds = {
144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo = {
158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi = {
173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
213 static const intel_limit_t intel_limits_pineview_sdvo = {
214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
228 static const intel_limit_t intel_limits_pineview_lvds = {
229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac = {
247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
307 .p1 = { .min = 2, .max = 6 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
312 static const intel_limit_t intel_limits_vlv = {
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
320 .vco = { .min = 4000000, .max = 6000000 },
321 .n = { .min = 1, .max = 7 },
322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
324 .p1 = { .min = 2, .max = 3 },
325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
328 static void vlv_clock(int refclk, intel_clock_t *clock)
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 if (WARN_ON(clock->n == 0 || clock->p == 0))
334 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
335 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
339 * Returns whether any output on the specified pipe is of the specified type
341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
356 struct drm_device *dev = crtc->dev;
357 const intel_limit_t *limit;
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
360 if (intel_is_dual_link_lvds(dev)) {
361 if (refclk == 100000)
362 limit = &intel_limits_ironlake_dual_lvds_100m;
364 limit = &intel_limits_ironlake_dual_lvds;
366 if (refclk == 100000)
367 limit = &intel_limits_ironlake_single_lvds_100m;
369 limit = &intel_limits_ironlake_single_lvds;
372 limit = &intel_limits_ironlake_dac;
377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
379 struct drm_device *dev = crtc->dev;
380 const intel_limit_t *limit;
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
383 if (intel_is_dual_link_lvds(dev))
384 limit = &intel_limits_g4x_dual_channel_lvds;
386 limit = &intel_limits_g4x_single_channel_lvds;
387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
389 limit = &intel_limits_g4x_hdmi;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
391 limit = &intel_limits_g4x_sdvo;
392 } else /* The option is for other outputs */
393 limit = &intel_limits_i9xx_sdvo;
398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
403 if (HAS_PCH_SPLIT(dev))
404 limit = intel_ironlake_limit(crtc, refclk);
405 else if (IS_G4X(dev)) {
406 limit = intel_g4x_limit(crtc);
407 } else if (IS_PINEVIEW(dev)) {
408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
409 limit = &intel_limits_pineview_lvds;
411 limit = &intel_limits_pineview_sdvo;
412 } else if (IS_VALLEYVIEW(dev)) {
413 limit = &intel_limits_vlv;
414 } else if (!IS_GEN2(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
416 limit = &intel_limits_i9xx_lvds;
418 limit = &intel_limits_i9xx_sdvo;
420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
421 limit = &intel_limits_i8xx_lvds;
422 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
423 limit = &intel_limits_i8xx_dvo;
425 limit = &intel_limits_i8xx_dac;
430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
431 static void pineview_clock(int refclk, intel_clock_t *clock)
433 clock->m = clock->m2 + 2;
434 clock->p = clock->p1 * clock->p2;
435 if (WARN_ON(clock->n == 0 || clock->p == 0))
437 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
438 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
443 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
446 static void i9xx_clock(int refclk, intel_clock_t *clock)
448 clock->m = i9xx_dpll_compute_m(clock);
449 clock->p = clock->p1 * clock->p2;
450 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
452 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
453 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
462 static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
466 if (clock->n < limit->n.min || limit->n.max < clock->n)
467 INTELPllInvalid("n out of range\n");
468 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
469 INTELPllInvalid("p1 out of range\n");
470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
473 INTELPllInvalid("m1 out of range\n");
475 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
476 if (clock->m1 <= clock->m2)
477 INTELPllInvalid("m1 <= m2\n");
479 if (!IS_VALLEYVIEW(dev)) {
480 if (clock->p < limit->p.min || limit->p.max < clock->p)
481 INTELPllInvalid("p out of range\n");
482 if (clock->m < limit->m.min || limit->m.max < clock->m)
483 INTELPllInvalid("m out of range\n");
486 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
487 INTELPllInvalid("vco out of range\n");
488 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489 * connector, etc., rather than just a single range.
491 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
492 INTELPllInvalid("dot out of range\n");
498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
499 int target, int refclk, intel_clock_t *match_clock,
500 intel_clock_t *best_clock)
502 struct drm_device *dev = crtc->dev;
506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
508 * For LVDS just rely on its current settings for dual-channel.
509 * We haven't figured out how to reliably set up different
510 * single/dual channel state, if we even can.
512 if (intel_is_dual_link_lvds(dev))
513 clock.p2 = limit->p2.p2_fast;
515 clock.p2 = limit->p2.p2_slow;
517 if (target < limit->p2.dot_limit)
518 clock.p2 = limit->p2.p2_slow;
520 clock.p2 = limit->p2.p2_fast;
523 memset(best_clock, 0, sizeof(*best_clock));
525 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
527 for (clock.m2 = limit->m2.min;
528 clock.m2 <= limit->m2.max; clock.m2++) {
529 if (clock.m2 >= clock.m1)
531 for (clock.n = limit->n.min;
532 clock.n <= limit->n.max; clock.n++) {
533 for (clock.p1 = limit->p1.min;
534 clock.p1 <= limit->p1.max; clock.p1++) {
537 i9xx_clock(refclk, &clock);
538 if (!intel_PLL_is_valid(dev, limit,
542 clock.p != match_clock->p)
545 this_err = abs(clock.dot - target);
546 if (this_err < err) {
555 return (err != target);
559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
560 int target, int refclk, intel_clock_t *match_clock,
561 intel_clock_t *best_clock)
563 struct drm_device *dev = crtc->dev;
567 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
569 * For LVDS just rely on its current settings for dual-channel.
570 * We haven't figured out how to reliably set up different
571 * single/dual channel state, if we even can.
573 if (intel_is_dual_link_lvds(dev))
574 clock.p2 = limit->p2.p2_fast;
576 clock.p2 = limit->p2.p2_slow;
578 if (target < limit->p2.dot_limit)
579 clock.p2 = limit->p2.p2_slow;
581 clock.p2 = limit->p2.p2_fast;
584 memset(best_clock, 0, sizeof(*best_clock));
586 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
588 for (clock.m2 = limit->m2.min;
589 clock.m2 <= limit->m2.max; clock.m2++) {
590 for (clock.n = limit->n.min;
591 clock.n <= limit->n.max; clock.n++) {
592 for (clock.p1 = limit->p1.min;
593 clock.p1 <= limit->p1.max; clock.p1++) {
596 pineview_clock(refclk, &clock);
597 if (!intel_PLL_is_valid(dev, limit,
601 clock.p != match_clock->p)
604 this_err = abs(clock.dot - target);
605 if (this_err < err) {
614 return (err != target);
618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
619 int target, int refclk, intel_clock_t *match_clock,
620 intel_clock_t *best_clock)
622 struct drm_device *dev = crtc->dev;
626 /* approximately equals target * 0.00585 */
627 int err_most = (target >> 8) + (target >> 9);
630 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
631 if (intel_is_dual_link_lvds(dev))
632 clock.p2 = limit->p2.p2_fast;
634 clock.p2 = limit->p2.p2_slow;
636 if (target < limit->p2.dot_limit)
637 clock.p2 = limit->p2.p2_slow;
639 clock.p2 = limit->p2.p2_fast;
642 memset(best_clock, 0, sizeof(*best_clock));
643 max_n = limit->n.max;
644 /* based on hardware requirement, prefer smaller n to precision */
645 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
646 /* based on hardware requirement, prefere larger m1,m2 */
647 for (clock.m1 = limit->m1.max;
648 clock.m1 >= limit->m1.min; clock.m1--) {
649 for (clock.m2 = limit->m2.max;
650 clock.m2 >= limit->m2.min; clock.m2--) {
651 for (clock.p1 = limit->p1.max;
652 clock.p1 >= limit->p1.min; clock.p1--) {
655 i9xx_clock(refclk, &clock);
656 if (!intel_PLL_is_valid(dev, limit,
660 this_err = abs(clock.dot - target);
661 if (this_err < err_most) {
675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
679 struct drm_device *dev = crtc->dev;
681 unsigned int bestppm = 1000000;
682 /* min update 19.2 MHz */
683 int max_n = min(limit->n.max, refclk / 19200);
686 target *= 5; /* fast clock */
688 memset(best_clock, 0, sizeof(*best_clock));
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
692 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
693 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
694 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
695 clock.p = clock.p1 * clock.p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
698 unsigned int ppm, diff;
700 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
703 vlv_clock(refclk, &clock);
705 if (!intel_PLL_is_valid(dev, limit,
709 diff = abs(clock.dot - target);
710 ppm = div_u64(1000000ULL * diff, target);
712 if (ppm < 100 && clock.p > best_clock->p) {
718 if (bestppm >= 10 && ppm < bestppm - 10) {
731 bool intel_crtc_active(struct drm_crtc *crtc)
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
735 /* Be paranoid as we can arrive here with only partial
736 * state retrieved from the hardware during setup.
738 * We can ditch the adjusted_mode.crtc_clock check as soon
739 * as Haswell has gained clock readout/fastboot support.
741 * We can ditch the crtc->fb check as soon as we can
742 * properly reconstruct framebuffers.
744 return intel_crtc->active && crtc->fb &&
745 intel_crtc->config.adjusted_mode.crtc_clock;
748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
754 return intel_crtc->config.cpu_transcoder;
757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
762 frame = I915_READ(frame_reg);
764 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
765 DRM_DEBUG_KMS("vblank wait timed out\n");
769 * intel_wait_for_vblank - wait for vblank on a given pipe
771 * @pipe: pipe to wait for
773 * Wait for vblank to occur on a given pipe. Needed for various bits of
776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
778 struct drm_i915_private *dev_priv = dev->dev_private;
779 int pipestat_reg = PIPESTAT(pipe);
781 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
782 g4x_wait_for_vblank(dev, pipe);
786 /* Clear existing vblank status. Note this will clear any other
787 * sticky status fields as well.
789 * This races with i915_driver_irq_handler() with the result
790 * that either function could miss a vblank event. Here it is not
791 * fatal, as we will either wait upon the next vblank interrupt or
792 * timeout. Generally speaking intel_wait_for_vblank() is only
793 * called during modeset at which time the GPU should be idle and
794 * should *not* be performing page flips and thus not waiting on
796 * Currently, the result of us stealing a vblank from the irq
797 * handler is that a single frame will be skipped during swapbuffers.
799 I915_WRITE(pipestat_reg,
800 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
802 /* Wait for vblank interrupt bit to set */
803 if (wait_for(I915_READ(pipestat_reg) &
804 PIPE_VBLANK_INTERRUPT_STATUS,
806 DRM_DEBUG_KMS("vblank wait timed out\n");
809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 u32 reg = PIPEDSL(pipe);
817 line_mask = DSL_LINEMASK_GEN2;
819 line_mask = DSL_LINEMASK_GEN3;
821 line1 = I915_READ(reg) & line_mask;
823 line2 = I915_READ(reg) & line_mask;
825 return line1 == line2;
829 * intel_wait_for_pipe_off - wait for pipe to turn off
831 * @pipe: pipe to wait for
833 * After disabling a pipe, we can't wait for vblank in the usual way,
834 * spinning on the vblank interrupt status bit, since we won't actually
835 * see an interrupt when the pipe is disabled.
838 * wait for the pipe register state bit to turn off
841 * wait for the display line value to settle (it usually
842 * ends up stopping at the start of the next frame).
845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
851 if (INTEL_INFO(dev)->gen >= 4) {
852 int reg = PIPECONF(cpu_transcoder);
854 /* Wait for the Pipe State to go off */
855 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
857 WARN(1, "pipe_off wait timed out\n");
859 /* Wait for the display line to settle */
860 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
861 WARN(1, "pipe_off wait timed out\n");
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
870 * Returns true if @port is connected, false otherwise.
872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
877 if (HAS_PCH_IBX(dev_priv->dev)) {
880 bit = SDE_PORTB_HOTPLUG;
883 bit = SDE_PORTC_HOTPLUG;
886 bit = SDE_PORTD_HOTPLUG;
894 bit = SDE_PORTB_HOTPLUG_CPT;
897 bit = SDE_PORTC_HOTPLUG_CPT;
900 bit = SDE_PORTD_HOTPLUG_CPT;
907 return I915_READ(SDEISR) & bit;
910 static const char *state_string(bool enabled)
912 return enabled ? "on" : "off";
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949 struct intel_shared_dpll *
950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
954 if (crtc->config.shared_dpll < 0)
957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
966 struct intel_dpll_hw_state hw_state;
968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
974 "asserting DPLL %s with no DPLL\n", state_string(state)))
977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
978 WARN(cur_state != state,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
995 val = I915_READ(reg);
996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv->dev))
1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1063 int pp_reg, lvds_reg;
1065 enum pipe panel_pipe = PIPE_A;
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1072 pp_reg = PP_CONTROL;
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1092 struct drm_device *dev = dev_priv->dev;
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe), state_string(state), state_string(cur_state));
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1157 struct drm_device *dev = dev_priv->dev;
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1172 /* Need to check both planes against the pipe */
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1187 struct drm_device *dev = dev_priv->dev;
1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1201 val = I915_READ(reg);
1202 WARN((val & SPRITE_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
1207 val = I915_READ(reg);
1208 WARN((val & DVS_ENABLE),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe), pipe_name(pipe));
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1248 if ((val & DP_PORT_EN) == 0)
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1266 if ((val & SDVO_ENABLE) == 0)
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1282 if ((val & LVDS_PORT_EN) == 0)
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1363 static void intel_init_dpio(struct drm_device *dev)
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1367 if (!IS_VALLEYVIEW(dev))
1370 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1372 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1373 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1374 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1375 * b. The other bits such as sfr settings / modesel may all be set
1378 * This should only be done on init and resume from S3 with both
1379 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1381 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1384 static void vlv_enable_pll(struct intel_crtc *crtc)
1386 struct drm_device *dev = crtc->base.dev;
1387 struct drm_i915_private *dev_priv = dev->dev_private;
1388 int reg = DPLL(crtc->pipe);
1389 u32 dpll = crtc->config.dpll_hw_state.dpll;
1391 assert_pipe_disabled(dev_priv, crtc->pipe);
1393 /* No really, not for ILK+ */
1394 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1396 /* PLL is protected by panel, make sure we can write it */
1397 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1398 assert_panel_unlocked(dev_priv, crtc->pipe);
1400 I915_WRITE(reg, dpll);
1404 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1405 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1407 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1408 POSTING_READ(DPLL_MD(crtc->pipe));
1410 /* We do this three times for luck */
1411 I915_WRITE(reg, dpll);
1413 udelay(150); /* wait for warmup */
1414 I915_WRITE(reg, dpll);
1416 udelay(150); /* wait for warmup */
1417 I915_WRITE(reg, dpll);
1419 udelay(150); /* wait for warmup */
1422 static void i9xx_enable_pll(struct intel_crtc *crtc)
1424 struct drm_device *dev = crtc->base.dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 int reg = DPLL(crtc->pipe);
1427 u32 dpll = crtc->config.dpll_hw_state.dpll;
1429 assert_pipe_disabled(dev_priv, crtc->pipe);
1431 /* No really, not for ILK+ */
1432 BUG_ON(dev_priv->info->gen >= 5);
1434 /* PLL is protected by panel, make sure we can write it */
1435 if (IS_MOBILE(dev) && !IS_I830(dev))
1436 assert_panel_unlocked(dev_priv, crtc->pipe);
1438 I915_WRITE(reg, dpll);
1440 /* Wait for the clocks to stabilize. */
1444 if (INTEL_INFO(dev)->gen >= 4) {
1445 I915_WRITE(DPLL_MD(crtc->pipe),
1446 crtc->config.dpll_hw_state.dpll_md);
1448 /* The pixel multiplier can only be updated once the
1449 * DPLL is enabled and the clocks are stable.
1451 * So write it again.
1453 I915_WRITE(reg, dpll);
1456 /* We do this three times for luck */
1457 I915_WRITE(reg, dpll);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, dpll);
1462 udelay(150); /* wait for warmup */
1463 I915_WRITE(reg, dpll);
1465 udelay(150); /* wait for warmup */
1469 * i9xx_disable_pll - disable a PLL
1470 * @dev_priv: i915 private structure
1471 * @pipe: pipe PLL to disable
1473 * Disable the PLL for @pipe, making sure the pipe is off first.
1475 * Note! This is for pre-ILK only.
1477 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1479 /* Don't disable pipe A or pipe A PLLs if needed */
1480 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1483 /* Make sure the pipe isn't still relying on us */
1484 assert_pipe_disabled(dev_priv, pipe);
1486 I915_WRITE(DPLL(pipe), 0);
1487 POSTING_READ(DPLL(pipe));
1490 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1494 /* Make sure the pipe isn't still relying on us */
1495 assert_pipe_disabled(dev_priv, pipe);
1497 /* Leave integrated clock source enabled */
1499 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1500 I915_WRITE(DPLL(pipe), val);
1501 POSTING_READ(DPLL(pipe));
1504 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1505 struct intel_digital_port *dport)
1509 switch (dport->port) {
1511 port_mask = DPLL_PORTB_READY_MASK;
1514 port_mask = DPLL_PORTC_READY_MASK;
1520 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1521 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1522 port_name(dport->port), I915_READ(DPLL(0)));
1526 * ironlake_enable_shared_dpll - enable PCH PLL
1527 * @dev_priv: i915 private structure
1528 * @pipe: pipe PLL to enable
1530 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1531 * drives the transcoder clock.
1533 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1535 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1536 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1538 /* PCH PLLs only available on ILK, SNB and IVB */
1539 BUG_ON(dev_priv->info->gen < 5);
1540 if (WARN_ON(pll == NULL))
1543 if (WARN_ON(pll->refcount == 0))
1546 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1547 pll->name, pll->active, pll->on,
1548 crtc->base.base.id);
1550 if (pll->active++) {
1552 assert_shared_dpll_enabled(dev_priv, pll);
1557 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1558 pll->enable(dev_priv, pll);
1562 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1564 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1565 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1567 /* PCH only available on ILK+ */
1568 BUG_ON(dev_priv->info->gen < 5);
1569 if (WARN_ON(pll == NULL))
1572 if (WARN_ON(pll->refcount == 0))
1575 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1576 pll->name, pll->active, pll->on,
1577 crtc->base.base.id);
1579 if (WARN_ON(pll->active == 0)) {
1580 assert_shared_dpll_disabled(dev_priv, pll);
1584 assert_shared_dpll_enabled(dev_priv, pll);
1589 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1590 pll->disable(dev_priv, pll);
1594 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1597 struct drm_device *dev = dev_priv->dev;
1598 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1600 uint32_t reg, val, pipeconf_val;
1602 /* PCH only available on ILK+ */
1603 BUG_ON(dev_priv->info->gen < 5);
1605 /* Make sure PCH DPLL is enabled */
1606 assert_shared_dpll_enabled(dev_priv,
1607 intel_crtc_to_shared_dpll(intel_crtc));
1609 /* FDI must be feeding us bits for PCH ports */
1610 assert_fdi_tx_enabled(dev_priv, pipe);
1611 assert_fdi_rx_enabled(dev_priv, pipe);
1613 if (HAS_PCH_CPT(dev)) {
1614 /* Workaround: Set the timing override bit before enabling the
1615 * pch transcoder. */
1616 reg = TRANS_CHICKEN2(pipe);
1617 val = I915_READ(reg);
1618 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1619 I915_WRITE(reg, val);
1622 reg = PCH_TRANSCONF(pipe);
1623 val = I915_READ(reg);
1624 pipeconf_val = I915_READ(PIPECONF(pipe));
1626 if (HAS_PCH_IBX(dev_priv->dev)) {
1628 * make the BPC in transcoder be consistent with
1629 * that in pipeconf reg.
1631 val &= ~PIPECONF_BPC_MASK;
1632 val |= pipeconf_val & PIPECONF_BPC_MASK;
1635 val &= ~TRANS_INTERLACE_MASK;
1636 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1637 if (HAS_PCH_IBX(dev_priv->dev) &&
1638 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1639 val |= TRANS_LEGACY_INTERLACED_ILK;
1641 val |= TRANS_INTERLACED;
1643 val |= TRANS_PROGRESSIVE;
1645 I915_WRITE(reg, val | TRANS_ENABLE);
1646 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1647 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1650 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1651 enum transcoder cpu_transcoder)
1653 u32 val, pipeconf_val;
1655 /* PCH only available on ILK+ */
1656 BUG_ON(dev_priv->info->gen < 5);
1658 /* FDI must be feeding us bits for PCH ports */
1659 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1660 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1662 /* Workaround: set timing override bit. */
1663 val = I915_READ(_TRANSA_CHICKEN2);
1664 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1665 I915_WRITE(_TRANSA_CHICKEN2, val);
1668 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1670 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1671 PIPECONF_INTERLACED_ILK)
1672 val |= TRANS_INTERLACED;
1674 val |= TRANS_PROGRESSIVE;
1676 I915_WRITE(LPT_TRANSCONF, val);
1677 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1678 DRM_ERROR("Failed to enable PCH transcoder\n");
1681 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1684 struct drm_device *dev = dev_priv->dev;
1687 /* FDI relies on the transcoder */
1688 assert_fdi_tx_disabled(dev_priv, pipe);
1689 assert_fdi_rx_disabled(dev_priv, pipe);
1691 /* Ports must be off as well */
1692 assert_pch_ports_disabled(dev_priv, pipe);
1694 reg = PCH_TRANSCONF(pipe);
1695 val = I915_READ(reg);
1696 val &= ~TRANS_ENABLE;
1697 I915_WRITE(reg, val);
1698 /* wait for PCH transcoder off, transcoder state */
1699 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1700 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1702 if (!HAS_PCH_IBX(dev)) {
1703 /* Workaround: Clear the timing override chicken bit again. */
1704 reg = TRANS_CHICKEN2(pipe);
1705 val = I915_READ(reg);
1706 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1707 I915_WRITE(reg, val);
1711 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1715 val = I915_READ(LPT_TRANSCONF);
1716 val &= ~TRANS_ENABLE;
1717 I915_WRITE(LPT_TRANSCONF, val);
1718 /* wait for PCH transcoder off, transcoder state */
1719 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1720 DRM_ERROR("Failed to disable PCH transcoder\n");
1722 /* Workaround: clear timing override bit. */
1723 val = I915_READ(_TRANSA_CHICKEN2);
1724 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1725 I915_WRITE(_TRANSA_CHICKEN2, val);
1729 * intel_enable_pipe - enable a pipe, asserting requirements
1730 * @dev_priv: i915 private structure
1731 * @pipe: pipe to enable
1732 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1734 * Enable @pipe, making sure that various hardware specific requirements
1735 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1737 * @pipe should be %PIPE_A or %PIPE_B.
1739 * Will wait until the pipe is actually running (i.e. first vblank) before
1742 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1743 bool pch_port, bool dsi)
1745 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1747 enum pipe pch_transcoder;
1751 assert_planes_disabled(dev_priv, pipe);
1752 assert_cursor_disabled(dev_priv, pipe);
1753 assert_sprites_disabled(dev_priv, pipe);
1755 if (HAS_PCH_LPT(dev_priv->dev))
1756 pch_transcoder = TRANSCODER_A;
1758 pch_transcoder = pipe;
1761 * A pipe without a PLL won't actually be able to drive bits from
1762 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1765 if (!HAS_PCH_SPLIT(dev_priv->dev))
1767 assert_dsi_pll_enabled(dev_priv);
1769 assert_pll_enabled(dev_priv, pipe);
1772 /* if driving the PCH, we need FDI enabled */
1773 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1774 assert_fdi_tx_pll_enabled(dev_priv,
1775 (enum pipe) cpu_transcoder);
1777 /* FIXME: assert CPU port conditions for SNB+ */
1780 reg = PIPECONF(cpu_transcoder);
1781 val = I915_READ(reg);
1782 if (val & PIPECONF_ENABLE)
1785 I915_WRITE(reg, val | PIPECONF_ENABLE);
1786 intel_wait_for_vblank(dev_priv->dev, pipe);
1790 * intel_disable_pipe - disable a pipe, asserting requirements
1791 * @dev_priv: i915 private structure
1792 * @pipe: pipe to disable
1794 * Disable @pipe, making sure that various hardware specific requirements
1795 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1797 * @pipe should be %PIPE_A or %PIPE_B.
1799 * Will wait until the pipe has shut down before returning.
1801 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1804 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1810 * Make sure planes won't keep trying to pump pixels to us,
1811 * or we might hang the display.
1813 assert_planes_disabled(dev_priv, pipe);
1814 assert_cursor_disabled(dev_priv, pipe);
1815 assert_sprites_disabled(dev_priv, pipe);
1817 /* Don't disable pipe A or pipe A PLLs if needed */
1818 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821 reg = PIPECONF(cpu_transcoder);
1822 val = I915_READ(reg);
1823 if ((val & PIPECONF_ENABLE) == 0)
1826 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1827 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1831 * Plane regs are double buffered, going from enabled->disabled needs a
1832 * trigger in order to latch. The display address reg provides this.
1834 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1837 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1839 I915_WRITE(reg, I915_READ(reg));
1844 * intel_enable_primary_plane - enable the primary plane on a given pipe
1845 * @dev_priv: i915 private structure
1846 * @plane: plane to enable
1847 * @pipe: pipe being fed
1849 * Enable @plane on @pipe, making sure that @pipe is running first.
1851 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1852 enum plane plane, enum pipe pipe)
1854 struct intel_crtc *intel_crtc =
1855 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1859 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860 assert_pipe_enabled(dev_priv, pipe);
1862 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1864 intel_crtc->primary_enabled = true;
1866 reg = DSPCNTR(plane);
1867 val = I915_READ(reg);
1868 if (val & DISPLAY_PLANE_ENABLE)
1871 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1872 intel_flush_primary_plane(dev_priv, plane);
1873 intel_wait_for_vblank(dev_priv->dev, pipe);
1877 * intel_disable_primary_plane - disable the primary plane
1878 * @dev_priv: i915 private structure
1879 * @plane: plane to disable
1880 * @pipe: pipe consuming the data
1882 * Disable @plane; should be an independent operation.
1884 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1885 enum plane plane, enum pipe pipe)
1887 struct intel_crtc *intel_crtc =
1888 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1892 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1894 intel_crtc->primary_enabled = false;
1896 reg = DSPCNTR(plane);
1897 val = I915_READ(reg);
1898 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1901 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1902 intel_flush_primary_plane(dev_priv, plane);
1903 intel_wait_for_vblank(dev_priv->dev, pipe);
1906 static bool need_vtd_wa(struct drm_device *dev)
1908 #ifdef CONFIG_INTEL_IOMMU
1909 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1916 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1917 struct drm_i915_gem_object *obj,
1918 struct intel_ring_buffer *pipelined)
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1924 switch (obj->tiling_mode) {
1925 case I915_TILING_NONE:
1926 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1927 alignment = 128 * 1024;
1928 else if (INTEL_INFO(dev)->gen >= 4)
1929 alignment = 4 * 1024;
1931 alignment = 64 * 1024;
1934 /* pin() will align the object as required by fence */
1938 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1944 /* Note that the w/a also requires 64 PTE of padding following the
1945 * bo. We currently fill all unused PTE with the shadow page and so
1946 * we should always have valid PTE following the scanout preventing
1949 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1950 alignment = 256 * 1024;
1952 dev_priv->mm.interruptible = false;
1953 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1955 goto err_interruptible;
1957 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1958 * fence, whereas 965+ only requires a fence if using
1959 * framebuffer compression. For simplicity, we always install
1960 * a fence as the cost is not that onerous.
1962 ret = i915_gem_object_get_fence(obj);
1966 i915_gem_object_pin_fence(obj);
1968 dev_priv->mm.interruptible = true;
1972 i915_gem_object_unpin_from_display_plane(obj);
1974 dev_priv->mm.interruptible = true;
1978 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1980 i915_gem_object_unpin_fence(obj);
1981 i915_gem_object_unpin_from_display_plane(obj);
1984 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1985 * is assumed to be a power-of-two. */
1986 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1987 unsigned int tiling_mode,
1991 if (tiling_mode != I915_TILING_NONE) {
1992 unsigned int tile_rows, tiles;
1997 tiles = *x / (512/cpp);
2000 return tile_rows * pitch * 8 + tiles * 4096;
2002 unsigned int offset;
2004 offset = *y * pitch + *x * cpp;
2006 *x = (offset & 4095) / cpp;
2007 return offset & -4096;
2011 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2014 struct drm_device *dev = crtc->dev;
2015 struct drm_i915_private *dev_priv = dev->dev_private;
2016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2017 struct intel_framebuffer *intel_fb;
2018 struct drm_i915_gem_object *obj;
2019 int plane = intel_crtc->plane;
2020 unsigned long linear_offset;
2029 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2033 intel_fb = to_intel_framebuffer(fb);
2034 obj = intel_fb->obj;
2036 reg = DSPCNTR(plane);
2037 dspcntr = I915_READ(reg);
2038 /* Mask out pixel format bits in case we change it */
2039 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2040 switch (fb->pixel_format) {
2042 dspcntr |= DISPPLANE_8BPP;
2044 case DRM_FORMAT_XRGB1555:
2045 case DRM_FORMAT_ARGB1555:
2046 dspcntr |= DISPPLANE_BGRX555;
2048 case DRM_FORMAT_RGB565:
2049 dspcntr |= DISPPLANE_BGRX565;
2051 case DRM_FORMAT_XRGB8888:
2052 case DRM_FORMAT_ARGB8888:
2053 dspcntr |= DISPPLANE_BGRX888;
2055 case DRM_FORMAT_XBGR8888:
2056 case DRM_FORMAT_ABGR8888:
2057 dspcntr |= DISPPLANE_RGBX888;
2059 case DRM_FORMAT_XRGB2101010:
2060 case DRM_FORMAT_ARGB2101010:
2061 dspcntr |= DISPPLANE_BGRX101010;
2063 case DRM_FORMAT_XBGR2101010:
2064 case DRM_FORMAT_ABGR2101010:
2065 dspcntr |= DISPPLANE_RGBX101010;
2071 if (INTEL_INFO(dev)->gen >= 4) {
2072 if (obj->tiling_mode != I915_TILING_NONE)
2073 dspcntr |= DISPPLANE_TILED;
2075 dspcntr &= ~DISPPLANE_TILED;
2079 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2081 I915_WRITE(reg, dspcntr);
2083 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2085 if (INTEL_INFO(dev)->gen >= 4) {
2086 intel_crtc->dspaddr_offset =
2087 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2088 fb->bits_per_pixel / 8,
2090 linear_offset -= intel_crtc->dspaddr_offset;
2092 intel_crtc->dspaddr_offset = linear_offset;
2095 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2096 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2098 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2099 if (INTEL_INFO(dev)->gen >= 4) {
2100 I915_MODIFY_DISPBASE(DSPSURF(plane),
2101 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2102 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103 I915_WRITE(DSPLINOFF(plane), linear_offset);
2105 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2111 static int ironlake_update_plane(struct drm_crtc *crtc,
2112 struct drm_framebuffer *fb, int x, int y)
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2117 struct intel_framebuffer *intel_fb;
2118 struct drm_i915_gem_object *obj;
2119 int plane = intel_crtc->plane;
2120 unsigned long linear_offset;
2130 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2134 intel_fb = to_intel_framebuffer(fb);
2135 obj = intel_fb->obj;
2137 reg = DSPCNTR(plane);
2138 dspcntr = I915_READ(reg);
2139 /* Mask out pixel format bits in case we change it */
2140 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2141 switch (fb->pixel_format) {
2143 dspcntr |= DISPPLANE_8BPP;
2145 case DRM_FORMAT_RGB565:
2146 dspcntr |= DISPPLANE_BGRX565;
2148 case DRM_FORMAT_XRGB8888:
2149 case DRM_FORMAT_ARGB8888:
2150 dspcntr |= DISPPLANE_BGRX888;
2152 case DRM_FORMAT_XBGR8888:
2153 case DRM_FORMAT_ABGR8888:
2154 dspcntr |= DISPPLANE_RGBX888;
2156 case DRM_FORMAT_XRGB2101010:
2157 case DRM_FORMAT_ARGB2101010:
2158 dspcntr |= DISPPLANE_BGRX101010;
2160 case DRM_FORMAT_XBGR2101010:
2161 case DRM_FORMAT_ABGR2101010:
2162 dspcntr |= DISPPLANE_RGBX101010;
2168 if (obj->tiling_mode != I915_TILING_NONE)
2169 dspcntr |= DISPPLANE_TILED;
2171 dspcntr &= ~DISPPLANE_TILED;
2173 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2174 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2176 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2178 I915_WRITE(reg, dspcntr);
2180 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2181 intel_crtc->dspaddr_offset =
2182 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2183 fb->bits_per_pixel / 8,
2185 linear_offset -= intel_crtc->dspaddr_offset;
2187 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2188 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2190 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2191 I915_MODIFY_DISPBASE(DSPSURF(plane),
2192 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2193 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2194 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2196 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2197 I915_WRITE(DSPLINOFF(plane), linear_offset);
2204 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2206 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2207 int x, int y, enum mode_set_atomic state)
2209 struct drm_device *dev = crtc->dev;
2210 struct drm_i915_private *dev_priv = dev->dev_private;
2212 if (dev_priv->display.disable_fbc)
2213 dev_priv->display.disable_fbc(dev);
2214 intel_increase_pllclock(crtc);
2216 return dev_priv->display.update_plane(crtc, fb, x, y);
2219 void intel_display_handle_reset(struct drm_device *dev)
2221 struct drm_i915_private *dev_priv = dev->dev_private;
2222 struct drm_crtc *crtc;
2225 * Flips in the rings have been nuked by the reset,
2226 * so complete all pending flips so that user space
2227 * will get its events and not get stuck.
2229 * Also update the base address of all primary
2230 * planes to the the last fb to make sure we're
2231 * showing the correct fb after a reset.
2233 * Need to make two loops over the crtcs so that we
2234 * don't try to grab a crtc mutex before the
2235 * pending_flip_queue really got woken up.
2238 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2240 enum plane plane = intel_crtc->plane;
2242 intel_prepare_page_flip(dev, plane);
2243 intel_finish_page_flip_plane(dev, plane);
2246 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2249 mutex_lock(&crtc->mutex);
2251 * FIXME: Once we have proper support for primary planes (and
2252 * disabling them without disabling the entire crtc) allow again
2255 if (intel_crtc->active && crtc->fb)
2256 dev_priv->display.update_plane(crtc, crtc->fb,
2258 mutex_unlock(&crtc->mutex);
2263 intel_finish_fb(struct drm_framebuffer *old_fb)
2265 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2266 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2267 bool was_interruptible = dev_priv->mm.interruptible;
2270 /* Big Hammer, we also need to ensure that any pending
2271 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2272 * current scanout is retired before unpinning the old
2275 * This should only fail upon a hung GPU, in which case we
2276 * can safely continue.
2278 dev_priv->mm.interruptible = false;
2279 ret = i915_gem_object_finish_gpu(obj);
2280 dev_priv->mm.interruptible = was_interruptible;
2285 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2287 struct drm_device *dev = crtc->dev;
2288 struct drm_i915_master_private *master_priv;
2289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 if (!dev->primary->master)
2294 master_priv = dev->primary->master->driver_priv;
2295 if (!master_priv->sarea_priv)
2298 switch (intel_crtc->pipe) {
2300 master_priv->sarea_priv->pipeA_x = x;
2301 master_priv->sarea_priv->pipeA_y = y;
2304 master_priv->sarea_priv->pipeB_x = x;
2305 master_priv->sarea_priv->pipeB_y = y;
2313 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2314 struct drm_framebuffer *fb)
2316 struct drm_device *dev = crtc->dev;
2317 struct drm_i915_private *dev_priv = dev->dev_private;
2318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2319 struct drm_framebuffer *old_fb;
2324 DRM_ERROR("No FB bound\n");
2328 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2329 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2330 plane_name(intel_crtc->plane),
2331 INTEL_INFO(dev)->num_pipes);
2335 mutex_lock(&dev->struct_mutex);
2336 ret = intel_pin_and_fence_fb_obj(dev,
2337 to_intel_framebuffer(fb)->obj,
2340 mutex_unlock(&dev->struct_mutex);
2341 DRM_ERROR("pin & fence failed\n");
2346 * Update pipe size and adjust fitter if needed: the reason for this is
2347 * that in compute_mode_changes we check the native mode (not the pfit
2348 * mode) to see if we can flip rather than do a full mode set. In the
2349 * fastboot case, we'll flip, but if we don't update the pipesrc and
2350 * pfit state, we'll end up with a big fb scanned out into the wrong
2353 * To fix this properly, we need to hoist the checks up into
2354 * compute_mode_changes (or above), check the actual pfit state and
2355 * whether the platform allows pfit disable with pipe active, and only
2356 * then update the pipesrc and pfit state, even on the flip path.
2358 if (i915_fastboot) {
2359 const struct drm_display_mode *adjusted_mode =
2360 &intel_crtc->config.adjusted_mode;
2362 I915_WRITE(PIPESRC(intel_crtc->pipe),
2363 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2364 (adjusted_mode->crtc_vdisplay - 1));
2365 if (!intel_crtc->config.pch_pfit.enabled &&
2366 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2367 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2368 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2369 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2370 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2374 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2376 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2377 mutex_unlock(&dev->struct_mutex);
2378 DRM_ERROR("failed to update base address\n");
2388 if (intel_crtc->active && old_fb != fb)
2389 intel_wait_for_vblank(dev, intel_crtc->pipe);
2390 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2393 intel_update_fbc(dev);
2394 intel_edp_psr_update(dev);
2395 mutex_unlock(&dev->struct_mutex);
2397 intel_crtc_update_sarea_pos(crtc, x, y);
2402 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2404 struct drm_device *dev = crtc->dev;
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407 int pipe = intel_crtc->pipe;
2410 /* enable normal train */
2411 reg = FDI_TX_CTL(pipe);
2412 temp = I915_READ(reg);
2413 if (IS_IVYBRIDGE(dev)) {
2414 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2415 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2417 temp &= ~FDI_LINK_TRAIN_NONE;
2418 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2420 I915_WRITE(reg, temp);
2422 reg = FDI_RX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 if (HAS_PCH_CPT(dev)) {
2425 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_NONE;
2431 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2433 /* wait one idle pattern time */
2437 /* IVB wants error correction enabled */
2438 if (IS_IVYBRIDGE(dev))
2439 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2440 FDI_FE_ERRC_ENABLE);
2443 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2445 return crtc->base.enabled && crtc->active &&
2446 crtc->config.has_pch_encoder;
2449 static void ivb_modeset_global_resources(struct drm_device *dev)
2451 struct drm_i915_private *dev_priv = dev->dev_private;
2452 struct intel_crtc *pipe_B_crtc =
2453 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2454 struct intel_crtc *pipe_C_crtc =
2455 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2459 * When everything is off disable fdi C so that we could enable fdi B
2460 * with all lanes. Note that we don't care about enabled pipes without
2461 * an enabled pch encoder.
2463 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2464 !pipe_has_enabled_pch(pipe_C_crtc)) {
2465 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2466 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2468 temp = I915_READ(SOUTH_CHICKEN1);
2469 temp &= ~FDI_BC_BIFURCATION_SELECT;
2470 DRM_DEBUG_KMS("disabling fdi C rx\n");
2471 I915_WRITE(SOUTH_CHICKEN1, temp);
2475 /* The FDI link training functions for ILK/Ibexpeak. */
2476 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2478 struct drm_device *dev = crtc->dev;
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481 int pipe = intel_crtc->pipe;
2482 int plane = intel_crtc->plane;
2483 u32 reg, temp, tries;
2485 /* FDI needs bits from pipe & plane first */
2486 assert_pipe_enabled(dev_priv, pipe);
2487 assert_plane_enabled(dev_priv, plane);
2489 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2491 reg = FDI_RX_IMR(pipe);
2492 temp = I915_READ(reg);
2493 temp &= ~FDI_RX_SYMBOL_LOCK;
2494 temp &= ~FDI_RX_BIT_LOCK;
2495 I915_WRITE(reg, temp);
2499 /* enable CPU FDI TX and PCH FDI RX */
2500 reg = FDI_TX_CTL(pipe);
2501 temp = I915_READ(reg);
2502 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2503 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2508 reg = FDI_RX_CTL(pipe);
2509 temp = I915_READ(reg);
2510 temp &= ~FDI_LINK_TRAIN_NONE;
2511 temp |= FDI_LINK_TRAIN_PATTERN_1;
2512 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2517 /* Ironlake workaround, enable clock pointer after FDI enable*/
2518 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2519 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2520 FDI_RX_PHASE_SYNC_POINTER_EN);
2522 reg = FDI_RX_IIR(pipe);
2523 for (tries = 0; tries < 5; tries++) {
2524 temp = I915_READ(reg);
2525 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2527 if ((temp & FDI_RX_BIT_LOCK)) {
2528 DRM_DEBUG_KMS("FDI train 1 done.\n");
2529 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2534 DRM_ERROR("FDI train 1 fail!\n");
2537 reg = FDI_TX_CTL(pipe);
2538 temp = I915_READ(reg);
2539 temp &= ~FDI_LINK_TRAIN_NONE;
2540 temp |= FDI_LINK_TRAIN_PATTERN_2;
2541 I915_WRITE(reg, temp);
2543 reg = FDI_RX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 I915_WRITE(reg, temp);
2552 reg = FDI_RX_IIR(pipe);
2553 for (tries = 0; tries < 5; tries++) {
2554 temp = I915_READ(reg);
2555 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2557 if (temp & FDI_RX_SYMBOL_LOCK) {
2558 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2559 DRM_DEBUG_KMS("FDI train 2 done.\n");
2564 DRM_ERROR("FDI train 2 fail!\n");
2566 DRM_DEBUG_KMS("FDI train done\n");
2570 static const int snb_b_fdi_train_param[] = {
2571 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2572 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2573 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2574 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2577 /* The FDI link training functions for SNB/Cougarpoint. */
2578 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2580 struct drm_device *dev = crtc->dev;
2581 struct drm_i915_private *dev_priv = dev->dev_private;
2582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2583 int pipe = intel_crtc->pipe;
2584 u32 reg, temp, i, retry;
2586 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2588 reg = FDI_RX_IMR(pipe);
2589 temp = I915_READ(reg);
2590 temp &= ~FDI_RX_SYMBOL_LOCK;
2591 temp &= ~FDI_RX_BIT_LOCK;
2592 I915_WRITE(reg, temp);
2597 /* enable CPU FDI TX and PCH FDI RX */
2598 reg = FDI_TX_CTL(pipe);
2599 temp = I915_READ(reg);
2600 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2601 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2602 temp &= ~FDI_LINK_TRAIN_NONE;
2603 temp |= FDI_LINK_TRAIN_PATTERN_1;
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2606 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2607 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2609 I915_WRITE(FDI_RX_MISC(pipe),
2610 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2612 reg = FDI_RX_CTL(pipe);
2613 temp = I915_READ(reg);
2614 if (HAS_PCH_CPT(dev)) {
2615 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2616 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2618 temp &= ~FDI_LINK_TRAIN_NONE;
2619 temp |= FDI_LINK_TRAIN_PATTERN_1;
2621 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2626 for (i = 0; i < 4; i++) {
2627 reg = FDI_TX_CTL(pipe);
2628 temp = I915_READ(reg);
2629 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630 temp |= snb_b_fdi_train_param[i];
2631 I915_WRITE(reg, temp);
2636 for (retry = 0; retry < 5; retry++) {
2637 reg = FDI_RX_IIR(pipe);
2638 temp = I915_READ(reg);
2639 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2640 if (temp & FDI_RX_BIT_LOCK) {
2641 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2642 DRM_DEBUG_KMS("FDI train 1 done.\n");
2651 DRM_ERROR("FDI train 1 fail!\n");
2654 reg = FDI_TX_CTL(pipe);
2655 temp = I915_READ(reg);
2656 temp &= ~FDI_LINK_TRAIN_NONE;
2657 temp |= FDI_LINK_TRAIN_PATTERN_2;
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2661 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2663 I915_WRITE(reg, temp);
2665 reg = FDI_RX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 if (HAS_PCH_CPT(dev)) {
2668 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2669 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2671 temp &= ~FDI_LINK_TRAIN_NONE;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2;
2674 I915_WRITE(reg, temp);
2679 for (i = 0; i < 4; i++) {
2680 reg = FDI_TX_CTL(pipe);
2681 temp = I915_READ(reg);
2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683 temp |= snb_b_fdi_train_param[i];
2684 I915_WRITE(reg, temp);
2689 for (retry = 0; retry < 5; retry++) {
2690 reg = FDI_RX_IIR(pipe);
2691 temp = I915_READ(reg);
2692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693 if (temp & FDI_RX_SYMBOL_LOCK) {
2694 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2695 DRM_DEBUG_KMS("FDI train 2 done.\n");
2704 DRM_ERROR("FDI train 2 fail!\n");
2706 DRM_DEBUG_KMS("FDI train done.\n");
2709 /* Manual link training for Ivy Bridge A0 parts */
2710 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2712 struct drm_device *dev = crtc->dev;
2713 struct drm_i915_private *dev_priv = dev->dev_private;
2714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2715 int pipe = intel_crtc->pipe;
2716 u32 reg, temp, i, j;
2718 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2720 reg = FDI_RX_IMR(pipe);
2721 temp = I915_READ(reg);
2722 temp &= ~FDI_RX_SYMBOL_LOCK;
2723 temp &= ~FDI_RX_BIT_LOCK;
2724 I915_WRITE(reg, temp);
2729 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2730 I915_READ(FDI_RX_IIR(pipe)));
2732 /* Try each vswing and preemphasis setting twice before moving on */
2733 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2734 /* disable first in case we need to retry */
2735 reg = FDI_TX_CTL(pipe);
2736 temp = I915_READ(reg);
2737 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2738 temp &= ~FDI_TX_ENABLE;
2739 I915_WRITE(reg, temp);
2741 reg = FDI_RX_CTL(pipe);
2742 temp = I915_READ(reg);
2743 temp &= ~FDI_LINK_TRAIN_AUTO;
2744 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2745 temp &= ~FDI_RX_ENABLE;
2746 I915_WRITE(reg, temp);
2748 /* enable CPU FDI TX and PCH FDI RX */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2752 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2753 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2754 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2755 temp |= snb_b_fdi_train_param[j/2];
2756 temp |= FDI_COMPOSITE_SYNC;
2757 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2759 I915_WRITE(FDI_RX_MISC(pipe),
2760 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2762 reg = FDI_RX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2765 temp |= FDI_COMPOSITE_SYNC;
2766 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2769 udelay(1); /* should be 0.5us */
2771 for (i = 0; i < 4; i++) {
2772 reg = FDI_RX_IIR(pipe);
2773 temp = I915_READ(reg);
2774 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2776 if (temp & FDI_RX_BIT_LOCK ||
2777 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2778 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2779 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2783 udelay(1); /* should be 0.5us */
2786 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2791 reg = FDI_TX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2794 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2795 I915_WRITE(reg, temp);
2797 reg = FDI_RX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2800 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2801 I915_WRITE(reg, temp);
2804 udelay(2); /* should be 1.5us */
2806 for (i = 0; i < 4; i++) {
2807 reg = FDI_RX_IIR(pipe);
2808 temp = I915_READ(reg);
2809 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2811 if (temp & FDI_RX_SYMBOL_LOCK ||
2812 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2813 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2814 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2818 udelay(2); /* should be 1.5us */
2821 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2825 DRM_DEBUG_KMS("FDI train done.\n");
2828 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2830 struct drm_device *dev = intel_crtc->base.dev;
2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832 int pipe = intel_crtc->pipe;
2836 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2837 reg = FDI_RX_CTL(pipe);
2838 temp = I915_READ(reg);
2839 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2840 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2841 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2842 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2847 /* Switch from Rawclk to PCDclk */
2848 temp = I915_READ(reg);
2849 I915_WRITE(reg, temp | FDI_PCDCLK);
2854 /* Enable CPU FDI TX PLL, always on for Ironlake */
2855 reg = FDI_TX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2858 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2865 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2867 struct drm_device *dev = intel_crtc->base.dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 int pipe = intel_crtc->pipe;
2872 /* Switch from PCDclk to Rawclk */
2873 reg = FDI_RX_CTL(pipe);
2874 temp = I915_READ(reg);
2875 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2877 /* Disable CPU FDI TX PLL */
2878 reg = FDI_TX_CTL(pipe);
2879 temp = I915_READ(reg);
2880 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2885 reg = FDI_RX_CTL(pipe);
2886 temp = I915_READ(reg);
2887 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2889 /* Wait for the clocks to turn off. */
2894 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2896 struct drm_device *dev = crtc->dev;
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2899 int pipe = intel_crtc->pipe;
2902 /* disable CPU FDI tx and PCH FDI rx */
2903 reg = FDI_TX_CTL(pipe);
2904 temp = I915_READ(reg);
2905 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2908 reg = FDI_RX_CTL(pipe);
2909 temp = I915_READ(reg);
2910 temp &= ~(0x7 << 16);
2911 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2912 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2917 /* Ironlake workaround, disable clock pointer after downing FDI */
2918 if (HAS_PCH_IBX(dev)) {
2919 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2922 /* still set train pattern 1 */
2923 reg = FDI_TX_CTL(pipe);
2924 temp = I915_READ(reg);
2925 temp &= ~FDI_LINK_TRAIN_NONE;
2926 temp |= FDI_LINK_TRAIN_PATTERN_1;
2927 I915_WRITE(reg, temp);
2929 reg = FDI_RX_CTL(pipe);
2930 temp = I915_READ(reg);
2931 if (HAS_PCH_CPT(dev)) {
2932 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2933 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2935 temp &= ~FDI_LINK_TRAIN_NONE;
2936 temp |= FDI_LINK_TRAIN_PATTERN_1;
2938 /* BPC in FDI rx is consistent with that in PIPECONF */
2939 temp &= ~(0x07 << 16);
2940 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2941 I915_WRITE(reg, temp);
2947 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2949 struct drm_device *dev = crtc->dev;
2950 struct drm_i915_private *dev_priv = dev->dev_private;
2951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2952 unsigned long flags;
2955 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2956 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2959 spin_lock_irqsave(&dev->event_lock, flags);
2960 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2961 spin_unlock_irqrestore(&dev->event_lock, flags);
2966 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2971 if (crtc->fb == NULL)
2974 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2976 wait_event(dev_priv->pending_flip_queue,
2977 !intel_crtc_has_pending_flip(crtc));
2979 mutex_lock(&dev->struct_mutex);
2980 intel_finish_fb(crtc->fb);
2981 mutex_unlock(&dev->struct_mutex);
2984 /* Program iCLKIP clock to the desired frequency */
2985 static void lpt_program_iclkip(struct drm_crtc *crtc)
2987 struct drm_device *dev = crtc->dev;
2988 struct drm_i915_private *dev_priv = dev->dev_private;
2989 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2990 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2993 mutex_lock(&dev_priv->dpio_lock);
2995 /* It is necessary to ungate the pixclk gate prior to programming
2996 * the divisors, and gate it back when it is done.
2998 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3000 /* Disable SSCCTL */
3001 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3002 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3006 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3007 if (clock == 20000) {
3012 /* The iCLK virtual clock root frequency is in MHz,
3013 * but the adjusted_mode->crtc_clock in in KHz. To get the
3014 * divisors, it is necessary to divide one by another, so we
3015 * convert the virtual clock precision to KHz here for higher
3018 u32 iclk_virtual_root_freq = 172800 * 1000;
3019 u32 iclk_pi_range = 64;
3020 u32 desired_divisor, msb_divisor_value, pi_value;
3022 desired_divisor = (iclk_virtual_root_freq / clock);
3023 msb_divisor_value = desired_divisor / iclk_pi_range;
3024 pi_value = desired_divisor % iclk_pi_range;
3027 divsel = msb_divisor_value - 2;
3028 phaseinc = pi_value;
3031 /* This should not happen with any sane values */
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3033 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3034 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3035 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3037 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3044 /* Program SSCDIVINTPHASE6 */
3045 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3046 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3048 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3049 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3050 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3051 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3052 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3054 /* Program SSCAUXDIV */
3055 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3056 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3057 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3058 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3060 /* Enable modulator and associated divider */
3061 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3062 temp &= ~SBI_SSCCTL_DISABLE;
3063 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3065 /* Wait for initialization time */
3068 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3070 mutex_unlock(&dev_priv->dpio_lock);
3073 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3074 enum pipe pch_transcoder)
3076 struct drm_device *dev = crtc->base.dev;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3080 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3081 I915_READ(HTOTAL(cpu_transcoder)));
3082 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3083 I915_READ(HBLANK(cpu_transcoder)));
3084 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3085 I915_READ(HSYNC(cpu_transcoder)));
3087 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3088 I915_READ(VTOTAL(cpu_transcoder)));
3089 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3090 I915_READ(VBLANK(cpu_transcoder)));
3091 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3092 I915_READ(VSYNC(cpu_transcoder)));
3093 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3094 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3097 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3102 temp = I915_READ(SOUTH_CHICKEN1);
3103 if (temp & FDI_BC_BIFURCATION_SELECT)
3106 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3107 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3109 temp |= FDI_BC_BIFURCATION_SELECT;
3110 DRM_DEBUG_KMS("enabling fdi C rx\n");
3111 I915_WRITE(SOUTH_CHICKEN1, temp);
3112 POSTING_READ(SOUTH_CHICKEN1);
3115 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3117 struct drm_device *dev = intel_crtc->base.dev;
3118 struct drm_i915_private *dev_priv = dev->dev_private;
3120 switch (intel_crtc->pipe) {
3124 if (intel_crtc->config.fdi_lanes > 2)
3125 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3127 cpt_enable_fdi_bc_bifurcation(dev);
3131 cpt_enable_fdi_bc_bifurcation(dev);
3140 * Enable PCH resources required for PCH ports:
3142 * - FDI training & RX/TX
3143 * - update transcoder timings
3144 * - DP transcoding bits
3147 static void ironlake_pch_enable(struct drm_crtc *crtc)
3149 struct drm_device *dev = crtc->dev;
3150 struct drm_i915_private *dev_priv = dev->dev_private;
3151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3152 int pipe = intel_crtc->pipe;
3155 assert_pch_transcoder_disabled(dev_priv, pipe);
3157 if (IS_IVYBRIDGE(dev))
3158 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3160 /* Write the TU size bits before fdi link training, so that error
3161 * detection works. */
3162 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3163 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3165 /* For PCH output, training FDI link */
3166 dev_priv->display.fdi_link_train(crtc);
3168 /* We need to program the right clock selection before writing the pixel
3169 * mutliplier into the DPLL. */
3170 if (HAS_PCH_CPT(dev)) {
3173 temp = I915_READ(PCH_DPLL_SEL);
3174 temp |= TRANS_DPLL_ENABLE(pipe);
3175 sel = TRANS_DPLLB_SEL(pipe);
3176 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3180 I915_WRITE(PCH_DPLL_SEL, temp);
3183 /* XXX: pch pll's can be enabled any time before we enable the PCH
3184 * transcoder, and we actually should do this to not upset any PCH
3185 * transcoder that already use the clock when we share it.
3187 * Note that enable_shared_dpll tries to do the right thing, but
3188 * get_shared_dpll unconditionally resets the pll - we need that to have
3189 * the right LVDS enable sequence. */
3190 ironlake_enable_shared_dpll(intel_crtc);
3192 /* set transcoder timing, panel must allow it */
3193 assert_panel_unlocked(dev_priv, pipe);
3194 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3196 intel_fdi_normal_train(crtc);
3198 /* For PCH DP, enable TRANS_DP_CTL */
3199 if (HAS_PCH_CPT(dev) &&
3200 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3201 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3202 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3203 reg = TRANS_DP_CTL(pipe);
3204 temp = I915_READ(reg);
3205 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3206 TRANS_DP_SYNC_MASK |
3208 temp |= (TRANS_DP_OUTPUT_ENABLE |
3209 TRANS_DP_ENH_FRAMING);
3210 temp |= bpc << 9; /* same format but at 11:9 */
3212 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3213 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3214 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3215 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3217 switch (intel_trans_dp_port_sel(crtc)) {
3219 temp |= TRANS_DP_PORT_SEL_B;
3222 temp |= TRANS_DP_PORT_SEL_C;
3225 temp |= TRANS_DP_PORT_SEL_D;
3231 I915_WRITE(reg, temp);
3234 ironlake_enable_pch_transcoder(dev_priv, pipe);
3237 static void lpt_pch_enable(struct drm_crtc *crtc)
3239 struct drm_device *dev = crtc->dev;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3244 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3246 lpt_program_iclkip(crtc);
3248 /* Set transcoder timing. */
3249 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3251 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3254 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3256 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3261 if (pll->refcount == 0) {
3262 WARN(1, "bad %s refcount\n", pll->name);
3266 if (--pll->refcount == 0) {
3268 WARN_ON(pll->active);
3271 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3274 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3276 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3277 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3278 enum intel_dpll_id i;
3281 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3282 crtc->base.base.id, pll->name);
3283 intel_put_shared_dpll(crtc);
3286 if (HAS_PCH_IBX(dev_priv->dev)) {
3287 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3288 i = (enum intel_dpll_id) crtc->pipe;
3289 pll = &dev_priv->shared_dplls[i];
3291 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3292 crtc->base.base.id, pll->name);
3297 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3298 pll = &dev_priv->shared_dplls[i];
3300 /* Only want to check enabled timings first */
3301 if (pll->refcount == 0)
3304 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3305 sizeof(pll->hw_state)) == 0) {
3306 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3308 pll->name, pll->refcount, pll->active);
3314 /* Ok no matching timings, maybe there's a free one? */
3315 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3316 pll = &dev_priv->shared_dplls[i];
3317 if (pll->refcount == 0) {
3318 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3319 crtc->base.base.id, pll->name);
3327 crtc->config.shared_dpll = i;
3328 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3329 pipe_name(crtc->pipe));
3331 if (pll->active == 0) {
3332 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3333 sizeof(pll->hw_state));
3335 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3337 assert_shared_dpll_disabled(dev_priv, pll);
3339 pll->mode_set(dev_priv, pll);
3346 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349 int dslreg = PIPEDSL(pipe);
3352 temp = I915_READ(dslreg);
3354 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3355 if (wait_for(I915_READ(dslreg) != temp, 5))
3356 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3360 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3362 struct drm_device *dev = crtc->base.dev;
3363 struct drm_i915_private *dev_priv = dev->dev_private;
3364 int pipe = crtc->pipe;
3366 if (crtc->config.pch_pfit.enabled) {
3367 /* Force use of hard-coded filter coefficients
3368 * as some pre-programmed values are broken,
3371 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3372 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3373 PF_PIPE_SEL_IVB(pipe));
3375 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3376 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3377 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3381 static void intel_enable_planes(struct drm_crtc *crtc)
3383 struct drm_device *dev = crtc->dev;
3384 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3385 struct intel_plane *intel_plane;
3387 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3388 if (intel_plane->pipe == pipe)
3389 intel_plane_restore(&intel_plane->base);
3392 static void intel_disable_planes(struct drm_crtc *crtc)
3394 struct drm_device *dev = crtc->dev;
3395 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3396 struct intel_plane *intel_plane;
3398 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3399 if (intel_plane->pipe == pipe)
3400 intel_plane_disable(&intel_plane->base);
3403 void hsw_enable_ips(struct intel_crtc *crtc)
3405 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3407 if (!crtc->config.ips_enabled)
3410 /* We can only enable IPS after we enable a plane and wait for a vblank.
3411 * We guarantee that the plane is enabled by calling intel_enable_ips
3412 * only after intel_enable_plane. And intel_enable_plane already waits
3413 * for a vblank, so all we need to do here is to enable the IPS bit. */
3414 assert_plane_enabled(dev_priv, crtc->plane);
3415 if (IS_BROADWELL(crtc->base.dev)) {
3416 mutex_lock(&dev_priv->rps.hw_lock);
3417 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3418 mutex_unlock(&dev_priv->rps.hw_lock);
3419 /* Quoting Art Runyan: "its not safe to expect any particular
3420 * value in IPS_CTL bit 31 after enabling IPS through the
3421 * mailbox." Therefore we need to defer waiting on the state
3423 * TODO: need to fix this for state checker
3426 I915_WRITE(IPS_CTL, IPS_ENABLE);
3427 /* The bit only becomes 1 in the next vblank, so this wait here
3428 * is essentially intel_wait_for_vblank. If we don't have this
3429 * and don't wait for vblanks until the end of crtc_enable, then
3430 * the HW state readout code will complain that the expected
3431 * IPS_CTL value is not the one we read. */
3432 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3433 DRM_ERROR("Timed out waiting for IPS enable\n");
3437 void hsw_disable_ips(struct intel_crtc *crtc)
3439 struct drm_device *dev = crtc->base.dev;
3440 struct drm_i915_private *dev_priv = dev->dev_private;
3442 if (!crtc->config.ips_enabled)
3445 assert_plane_enabled(dev_priv, crtc->plane);
3446 if (IS_BROADWELL(crtc->base.dev)) {
3447 mutex_lock(&dev_priv->rps.hw_lock);
3448 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3449 mutex_unlock(&dev_priv->rps.hw_lock);
3451 I915_WRITE(IPS_CTL, 0);
3452 POSTING_READ(IPS_CTL);
3454 /* We need to wait for a vblank before we can disable the plane. */
3455 intel_wait_for_vblank(dev, crtc->pipe);
3458 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3459 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3461 struct drm_device *dev = crtc->dev;
3462 struct drm_i915_private *dev_priv = dev->dev_private;
3463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3464 enum pipe pipe = intel_crtc->pipe;
3465 int palreg = PALETTE(pipe);
3467 bool reenable_ips = false;
3469 /* The clocks have to be on to load the palette. */
3470 if (!crtc->enabled || !intel_crtc->active)
3473 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3474 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3475 assert_dsi_pll_enabled(dev_priv);
3477 assert_pll_enabled(dev_priv, pipe);
3480 /* use legacy palette for Ironlake */
3481 if (HAS_PCH_SPLIT(dev))
3482 palreg = LGC_PALETTE(pipe);
3484 /* Workaround : Do not read or write the pipe palette/gamma data while
3485 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3487 if (intel_crtc->config.ips_enabled &&
3488 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3489 GAMMA_MODE_MODE_SPLIT)) {
3490 hsw_disable_ips(intel_crtc);
3491 reenable_ips = true;
3494 for (i = 0; i < 256; i++) {
3495 I915_WRITE(palreg + 4 * i,
3496 (intel_crtc->lut_r[i] << 16) |
3497 (intel_crtc->lut_g[i] << 8) |
3498 intel_crtc->lut_b[i]);
3502 hsw_enable_ips(intel_crtc);
3505 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3507 struct drm_device *dev = crtc->dev;
3508 struct drm_i915_private *dev_priv = dev->dev_private;
3509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3510 struct intel_encoder *encoder;
3511 int pipe = intel_crtc->pipe;
3512 int plane = intel_crtc->plane;
3514 WARN_ON(!crtc->enabled);
3516 if (intel_crtc->active)
3519 intel_crtc->active = true;
3521 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3522 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3524 for_each_encoder_on_crtc(dev, crtc, encoder)
3525 if (encoder->pre_enable)
3526 encoder->pre_enable(encoder);
3528 if (intel_crtc->config.has_pch_encoder) {
3529 /* Note: FDI PLL enabling _must_ be done before we enable the
3530 * cpu pipes, hence this is separate from all the other fdi/pch
3532 ironlake_fdi_pll_enable(intel_crtc);
3534 assert_fdi_tx_disabled(dev_priv, pipe);
3535 assert_fdi_rx_disabled(dev_priv, pipe);
3538 ironlake_pfit_enable(intel_crtc);
3541 * On ILK+ LUT must be loaded before the pipe is running but with
3544 intel_crtc_load_lut(crtc);
3546 intel_update_watermarks(crtc);
3547 intel_enable_pipe(dev_priv, pipe,
3548 intel_crtc->config.has_pch_encoder, false);
3549 intel_enable_primary_plane(dev_priv, plane, pipe);
3550 intel_enable_planes(crtc);
3551 intel_crtc_update_cursor(crtc, true);
3553 if (intel_crtc->config.has_pch_encoder)
3554 ironlake_pch_enable(crtc);
3556 mutex_lock(&dev->struct_mutex);
3557 intel_update_fbc(dev);
3558 mutex_unlock(&dev->struct_mutex);
3560 for_each_encoder_on_crtc(dev, crtc, encoder)
3561 encoder->enable(encoder);
3563 if (HAS_PCH_CPT(dev))
3564 cpt_verify_modeset(dev, intel_crtc->pipe);
3567 * There seems to be a race in PCH platform hw (at least on some
3568 * outputs) where an enabled pipe still completes any pageflip right
3569 * away (as if the pipe is off) instead of waiting for vblank. As soon
3570 * as the first vblank happend, everything works as expected. Hence just
3571 * wait for one vblank before returning to avoid strange things
3574 intel_wait_for_vblank(dev, intel_crtc->pipe);
3577 /* IPS only exists on ULT machines and is tied to pipe A. */
3578 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3580 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3583 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3585 struct drm_device *dev = crtc->dev;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3588 int pipe = intel_crtc->pipe;
3589 int plane = intel_crtc->plane;
3591 intel_enable_primary_plane(dev_priv, plane, pipe);
3592 intel_enable_planes(crtc);
3593 intel_crtc_update_cursor(crtc, true);
3595 hsw_enable_ips(intel_crtc);
3597 mutex_lock(&dev->struct_mutex);
3598 intel_update_fbc(dev);
3599 mutex_unlock(&dev->struct_mutex);
3602 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3604 struct drm_device *dev = crtc->dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3607 int pipe = intel_crtc->pipe;
3608 int plane = intel_crtc->plane;
3610 intel_crtc_wait_for_pending_flips(crtc);
3611 drm_vblank_off(dev, pipe);
3613 /* FBC must be disabled before disabling the plane on HSW. */
3614 if (dev_priv->fbc.plane == plane)
3615 intel_disable_fbc(dev);
3617 hsw_disable_ips(intel_crtc);
3619 intel_crtc_update_cursor(crtc, false);
3620 intel_disable_planes(crtc);
3621 intel_disable_primary_plane(dev_priv, plane, pipe);
3625 * This implements the workaround described in the "notes" section of the mode
3626 * set sequence documentation. When going from no pipes or single pipe to
3627 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3628 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3630 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3632 struct drm_device *dev = crtc->base.dev;
3633 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3635 /* We want to get the other_active_crtc only if there's only 1 other
3637 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3638 if (!crtc_it->active || crtc_it == crtc)
3641 if (other_active_crtc)
3644 other_active_crtc = crtc_it;
3646 if (!other_active_crtc)
3649 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3650 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3653 static void haswell_crtc_enable(struct drm_crtc *crtc)
3655 struct drm_device *dev = crtc->dev;
3656 struct drm_i915_private *dev_priv = dev->dev_private;
3657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3658 struct intel_encoder *encoder;
3659 int pipe = intel_crtc->pipe;
3661 WARN_ON(!crtc->enabled);
3663 if (intel_crtc->active)
3666 intel_crtc->active = true;
3668 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3669 if (intel_crtc->config.has_pch_encoder)
3670 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3672 if (intel_crtc->config.has_pch_encoder)
3673 dev_priv->display.fdi_link_train(crtc);
3675 for_each_encoder_on_crtc(dev, crtc, encoder)
3676 if (encoder->pre_enable)
3677 encoder->pre_enable(encoder);
3679 intel_ddi_enable_pipe_clock(intel_crtc);
3681 ironlake_pfit_enable(intel_crtc);
3684 * On ILK+ LUT must be loaded before the pipe is running but with
3687 intel_crtc_load_lut(crtc);
3689 intel_ddi_set_pipe_settings(crtc);
3690 intel_ddi_enable_transcoder_func(crtc);
3692 intel_update_watermarks(crtc);
3693 intel_enable_pipe(dev_priv, pipe,
3694 intel_crtc->config.has_pch_encoder, false);
3696 if (intel_crtc->config.has_pch_encoder)
3697 lpt_pch_enable(crtc);
3699 for_each_encoder_on_crtc(dev, crtc, encoder) {
3700 encoder->enable(encoder);
3701 intel_opregion_notify_encoder(encoder, true);
3704 /* If we change the relative order between pipe/planes enabling, we need
3705 * to change the workaround. */
3706 haswell_mode_set_planes_workaround(intel_crtc);
3707 haswell_crtc_enable_planes(crtc);
3710 * There seems to be a race in PCH platform hw (at least on some
3711 * outputs) where an enabled pipe still completes any pageflip right
3712 * away (as if the pipe is off) instead of waiting for vblank. As soon
3713 * as the first vblank happend, everything works as expected. Hence just
3714 * wait for one vblank before returning to avoid strange things
3717 intel_wait_for_vblank(dev, intel_crtc->pipe);
3720 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3722 struct drm_device *dev = crtc->base.dev;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 int pipe = crtc->pipe;
3726 /* To avoid upsetting the power well on haswell only disable the pfit if
3727 * it's in use. The hw state code will make sure we get this right. */
3728 if (crtc->config.pch_pfit.enabled) {
3729 I915_WRITE(PF_CTL(pipe), 0);
3730 I915_WRITE(PF_WIN_POS(pipe), 0);
3731 I915_WRITE(PF_WIN_SZ(pipe), 0);
3735 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3737 struct drm_device *dev = crtc->dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740 struct intel_encoder *encoder;
3741 int pipe = intel_crtc->pipe;
3742 int plane = intel_crtc->plane;
3746 if (!intel_crtc->active)
3749 for_each_encoder_on_crtc(dev, crtc, encoder)
3750 encoder->disable(encoder);
3752 intel_crtc_wait_for_pending_flips(crtc);
3753 drm_vblank_off(dev, pipe);
3755 if (dev_priv->fbc.plane == plane)
3756 intel_disable_fbc(dev);
3758 intel_crtc_update_cursor(crtc, false);
3759 intel_disable_planes(crtc);
3760 intel_disable_primary_plane(dev_priv, plane, pipe);
3762 if (intel_crtc->config.has_pch_encoder)
3763 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3765 intel_disable_pipe(dev_priv, pipe);
3767 ironlake_pfit_disable(intel_crtc);
3769 for_each_encoder_on_crtc(dev, crtc, encoder)
3770 if (encoder->post_disable)
3771 encoder->post_disable(encoder);
3773 if (intel_crtc->config.has_pch_encoder) {
3774 ironlake_fdi_disable(crtc);
3776 ironlake_disable_pch_transcoder(dev_priv, pipe);
3777 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3779 if (HAS_PCH_CPT(dev)) {
3780 /* disable TRANS_DP_CTL */
3781 reg = TRANS_DP_CTL(pipe);
3782 temp = I915_READ(reg);
3783 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3784 TRANS_DP_PORT_SEL_MASK);
3785 temp |= TRANS_DP_PORT_SEL_NONE;
3786 I915_WRITE(reg, temp);
3788 /* disable DPLL_SEL */
3789 temp = I915_READ(PCH_DPLL_SEL);
3790 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3791 I915_WRITE(PCH_DPLL_SEL, temp);
3794 /* disable PCH DPLL */
3795 intel_disable_shared_dpll(intel_crtc);
3797 ironlake_fdi_pll_disable(intel_crtc);
3800 intel_crtc->active = false;
3801 intel_update_watermarks(crtc);
3803 mutex_lock(&dev->struct_mutex);
3804 intel_update_fbc(dev);
3805 mutex_unlock(&dev->struct_mutex);
3808 static void haswell_crtc_disable(struct drm_crtc *crtc)
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 struct intel_encoder *encoder;
3814 int pipe = intel_crtc->pipe;
3815 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3817 if (!intel_crtc->active)
3820 haswell_crtc_disable_planes(crtc);
3822 for_each_encoder_on_crtc(dev, crtc, encoder) {
3823 intel_opregion_notify_encoder(encoder, false);
3824 encoder->disable(encoder);
3827 if (intel_crtc->config.has_pch_encoder)
3828 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3829 intel_disable_pipe(dev_priv, pipe);
3831 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3833 ironlake_pfit_disable(intel_crtc);
3835 intel_ddi_disable_pipe_clock(intel_crtc);
3837 for_each_encoder_on_crtc(dev, crtc, encoder)
3838 if (encoder->post_disable)
3839 encoder->post_disable(encoder);
3841 if (intel_crtc->config.has_pch_encoder) {
3842 lpt_disable_pch_transcoder(dev_priv);
3843 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3844 intel_ddi_fdi_disable(crtc);
3847 intel_crtc->active = false;
3848 intel_update_watermarks(crtc);
3850 mutex_lock(&dev->struct_mutex);
3851 intel_update_fbc(dev);
3852 mutex_unlock(&dev->struct_mutex);
3855 static void ironlake_crtc_off(struct drm_crtc *crtc)
3857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3858 intel_put_shared_dpll(intel_crtc);
3861 static void haswell_crtc_off(struct drm_crtc *crtc)
3863 intel_ddi_put_crtc_pll(crtc);
3866 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3868 if (!enable && intel_crtc->overlay) {
3869 struct drm_device *dev = intel_crtc->base.dev;
3870 struct drm_i915_private *dev_priv = dev->dev_private;
3872 mutex_lock(&dev->struct_mutex);
3873 dev_priv->mm.interruptible = false;
3874 (void) intel_overlay_switch_off(intel_crtc->overlay);
3875 dev_priv->mm.interruptible = true;
3876 mutex_unlock(&dev->struct_mutex);
3879 /* Let userspace switch the overlay on again. In most cases userspace
3880 * has to recompute where to put it anyway.
3885 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3886 * cursor plane briefly if not already running after enabling the display
3888 * This workaround avoids occasional blank screens when self refresh is
3892 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3894 u32 cntl = I915_READ(CURCNTR(pipe));
3896 if ((cntl & CURSOR_MODE) == 0) {
3897 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3899 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3900 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3901 intel_wait_for_vblank(dev_priv->dev, pipe);
3902 I915_WRITE(CURCNTR(pipe), cntl);
3903 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3904 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3908 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3910 struct drm_device *dev = crtc->base.dev;
3911 struct drm_i915_private *dev_priv = dev->dev_private;
3912 struct intel_crtc_config *pipe_config = &crtc->config;
3914 if (!crtc->config.gmch_pfit.control)
3918 * The panel fitter should only be adjusted whilst the pipe is disabled,
3919 * according to register description and PRM.
3921 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3922 assert_pipe_disabled(dev_priv, crtc->pipe);
3924 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3925 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3927 /* Border color in case we don't scale up to the full screen. Black by
3928 * default, change to something else for debugging. */
3929 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3932 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3934 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3936 /* Obtain SKU information */
3937 mutex_lock(&dev_priv->dpio_lock);
3938 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3939 CCK_FUSE_HPLL_FREQ_MASK;
3940 mutex_unlock(&dev_priv->dpio_lock);
3942 return vco_freq[hpll_freq];
3945 /* Adjust CDclk dividers to allow high res or save power if possible */
3946 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3948 struct drm_i915_private *dev_priv = dev->dev_private;
3951 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3953 else if (cdclk == 266)
3958 mutex_lock(&dev_priv->rps.hw_lock);
3959 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3960 val &= ~DSPFREQGUAR_MASK;
3961 val |= (cmd << DSPFREQGUAR_SHIFT);
3962 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3963 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3964 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3966 DRM_ERROR("timed out waiting for CDclk change\n");
3968 mutex_unlock(&dev_priv->rps.hw_lock);
3973 vco = valleyview_get_vco(dev_priv);
3974 divider = ((vco << 1) / cdclk) - 1;
3976 mutex_lock(&dev_priv->dpio_lock);
3977 /* adjust cdclk divider */
3978 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3981 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3982 mutex_unlock(&dev_priv->dpio_lock);
3985 mutex_lock(&dev_priv->dpio_lock);
3986 /* adjust self-refresh exit latency value */
3987 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
3991 * For high bandwidth configs, we set a higher latency in the bunit
3992 * so that the core display fetch happens in time to avoid underruns.
3995 val |= 4500 / 250; /* 4.5 usec */
3997 val |= 3000 / 250; /* 3.0 usec */
3998 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
3999 mutex_unlock(&dev_priv->dpio_lock);
4001 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4002 intel_i2c_reset(dev);
4005 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4010 vco = valleyview_get_vco(dev_priv);
4012 mutex_lock(&dev_priv->dpio_lock);
4013 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4014 mutex_unlock(&dev_priv->dpio_lock);
4018 cur_cdclk = (vco << 1) / (divider + 1);
4023 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4028 cur_cdclk = valleyview_cur_cdclk(dev_priv);
4031 * Really only a few cases to deal with, as only 4 CDclks are supported:
4036 * So we check to see whether we're above 90% of the lower bin and
4039 if (max_pixclk > 288000) {
4041 } else if (max_pixclk > 240000) {
4045 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4048 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4049 unsigned modeset_pipes,
4050 struct intel_crtc_config *pipe_config)
4052 struct drm_device *dev = dev_priv->dev;
4053 struct intel_crtc *intel_crtc;
4056 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4058 if (modeset_pipes & (1 << intel_crtc->pipe))
4059 max_pixclk = max(max_pixclk,
4060 pipe_config->adjusted_mode.crtc_clock);
4061 else if (intel_crtc->base.enabled)
4062 max_pixclk = max(max_pixclk,
4063 intel_crtc->config.adjusted_mode.crtc_clock);
4069 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4070 unsigned *prepare_pipes,
4071 unsigned modeset_pipes,
4072 struct intel_crtc_config *pipe_config)
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 struct intel_crtc *intel_crtc;
4076 int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4078 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4080 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4083 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4085 if (intel_crtc->base.enabled)
4086 *prepare_pipes |= (1 << intel_crtc->pipe);
4089 static void valleyview_modeset_global_resources(struct drm_device *dev)
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4092 int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4093 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4094 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4096 if (req_cdclk != cur_cdclk)
4097 valleyview_set_cdclk(dev, req_cdclk);
4100 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4102 struct drm_device *dev = crtc->dev;
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105 struct intel_encoder *encoder;
4106 int pipe = intel_crtc->pipe;
4107 int plane = intel_crtc->plane;
4110 WARN_ON(!crtc->enabled);
4112 if (intel_crtc->active)
4115 intel_crtc->active = true;
4117 for_each_encoder_on_crtc(dev, crtc, encoder)
4118 if (encoder->pre_pll_enable)
4119 encoder->pre_pll_enable(encoder);
4121 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4124 vlv_enable_pll(intel_crtc);
4126 for_each_encoder_on_crtc(dev, crtc, encoder)
4127 if (encoder->pre_enable)
4128 encoder->pre_enable(encoder);
4130 i9xx_pfit_enable(intel_crtc);
4132 intel_crtc_load_lut(crtc);
4134 intel_update_watermarks(crtc);
4135 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4136 intel_enable_primary_plane(dev_priv, plane, pipe);
4137 intel_enable_planes(crtc);
4138 intel_crtc_update_cursor(crtc, true);
4140 intel_update_fbc(dev);
4142 for_each_encoder_on_crtc(dev, crtc, encoder)
4143 encoder->enable(encoder);
4146 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4148 struct drm_device *dev = crtc->dev;
4149 struct drm_i915_private *dev_priv = dev->dev_private;
4150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151 struct intel_encoder *encoder;
4152 int pipe = intel_crtc->pipe;
4153 int plane = intel_crtc->plane;
4155 WARN_ON(!crtc->enabled);
4157 if (intel_crtc->active)
4160 intel_crtc->active = true;
4162 for_each_encoder_on_crtc(dev, crtc, encoder)
4163 if (encoder->pre_enable)
4164 encoder->pre_enable(encoder);
4166 i9xx_enable_pll(intel_crtc);
4168 i9xx_pfit_enable(intel_crtc);
4170 intel_crtc_load_lut(crtc);
4172 intel_update_watermarks(crtc);
4173 intel_enable_pipe(dev_priv, pipe, false, false);
4174 intel_enable_primary_plane(dev_priv, plane, pipe);
4175 intel_enable_planes(crtc);
4176 /* The fixup needs to happen before cursor is enabled */
4178 g4x_fixup_plane(dev_priv, pipe);
4179 intel_crtc_update_cursor(crtc, true);
4181 /* Give the overlay scaler a chance to enable if it's on this pipe */
4182 intel_crtc_dpms_overlay(intel_crtc, true);
4184 intel_update_fbc(dev);
4186 for_each_encoder_on_crtc(dev, crtc, encoder)
4187 encoder->enable(encoder);
4190 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4192 struct drm_device *dev = crtc->base.dev;
4193 struct drm_i915_private *dev_priv = dev->dev_private;
4195 if (!crtc->config.gmch_pfit.control)
4198 assert_pipe_disabled(dev_priv, crtc->pipe);
4200 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4201 I915_READ(PFIT_CONTROL));
4202 I915_WRITE(PFIT_CONTROL, 0);
4205 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4207 struct drm_device *dev = crtc->dev;
4208 struct drm_i915_private *dev_priv = dev->dev_private;
4209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4210 struct intel_encoder *encoder;
4211 int pipe = intel_crtc->pipe;
4212 int plane = intel_crtc->plane;
4214 if (!intel_crtc->active)
4217 for_each_encoder_on_crtc(dev, crtc, encoder)
4218 encoder->disable(encoder);
4220 /* Give the overlay scaler a chance to disable if it's on this pipe */
4221 intel_crtc_wait_for_pending_flips(crtc);
4222 drm_vblank_off(dev, pipe);
4224 if (dev_priv->fbc.plane == plane)
4225 intel_disable_fbc(dev);
4227 intel_crtc_dpms_overlay(intel_crtc, false);
4228 intel_crtc_update_cursor(crtc, false);
4229 intel_disable_planes(crtc);
4230 intel_disable_primary_plane(dev_priv, plane, pipe);
4232 intel_disable_pipe(dev_priv, pipe);
4234 i9xx_pfit_disable(intel_crtc);
4236 for_each_encoder_on_crtc(dev, crtc, encoder)
4237 if (encoder->post_disable)
4238 encoder->post_disable(encoder);
4240 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4241 vlv_disable_pll(dev_priv, pipe);
4242 else if (!IS_VALLEYVIEW(dev))
4243 i9xx_disable_pll(dev_priv, pipe);
4245 intel_crtc->active = false;
4246 intel_update_watermarks(crtc);
4248 intel_update_fbc(dev);
4251 static void i9xx_crtc_off(struct drm_crtc *crtc)
4255 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4258 struct drm_device *dev = crtc->dev;
4259 struct drm_i915_master_private *master_priv;
4260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4261 int pipe = intel_crtc->pipe;
4263 if (!dev->primary->master)
4266 master_priv = dev->primary->master->driver_priv;
4267 if (!master_priv->sarea_priv)
4272 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4273 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4276 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4277 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4280 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4286 * Sets the power management mode of the pipe and plane.
4288 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4290 struct drm_device *dev = crtc->dev;
4291 struct drm_i915_private *dev_priv = dev->dev_private;
4292 struct intel_encoder *intel_encoder;
4293 bool enable = false;
4295 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4296 enable |= intel_encoder->connectors_active;
4299 dev_priv->display.crtc_enable(crtc);
4301 dev_priv->display.crtc_disable(crtc);
4303 intel_crtc_update_sarea(crtc, enable);
4306 static void intel_crtc_disable(struct drm_crtc *crtc)
4308 struct drm_device *dev = crtc->dev;
4309 struct drm_connector *connector;
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4313 /* crtc should still be enabled when we disable it. */
4314 WARN_ON(!crtc->enabled);
4316 dev_priv->display.crtc_disable(crtc);
4317 intel_crtc->eld_vld = false;
4318 intel_crtc_update_sarea(crtc, false);
4319 dev_priv->display.off(crtc);
4321 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4322 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4323 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4326 mutex_lock(&dev->struct_mutex);
4327 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4328 mutex_unlock(&dev->struct_mutex);
4332 /* Update computed state. */
4333 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4334 if (!connector->encoder || !connector->encoder->crtc)
4337 if (connector->encoder->crtc != crtc)
4340 connector->dpms = DRM_MODE_DPMS_OFF;
4341 to_intel_encoder(connector->encoder)->connectors_active = false;
4345 void intel_encoder_destroy(struct drm_encoder *encoder)
4347 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4349 drm_encoder_cleanup(encoder);
4350 kfree(intel_encoder);
4353 /* Simple dpms helper for encoders with just one connector, no cloning and only
4354 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4355 * state of the entire output pipe. */
4356 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4358 if (mode == DRM_MODE_DPMS_ON) {
4359 encoder->connectors_active = true;
4361 intel_crtc_update_dpms(encoder->base.crtc);
4363 encoder->connectors_active = false;
4365 intel_crtc_update_dpms(encoder->base.crtc);
4369 /* Cross check the actual hw state with our own modeset state tracking (and it's
4370 * internal consistency). */
4371 static void intel_connector_check_state(struct intel_connector *connector)
4373 if (connector->get_hw_state(connector)) {
4374 struct intel_encoder *encoder = connector->encoder;
4375 struct drm_crtc *crtc;
4376 bool encoder_enabled;
4379 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4380 connector->base.base.id,
4381 drm_get_connector_name(&connector->base));
4383 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4384 "wrong connector dpms state\n");
4385 WARN(connector->base.encoder != &encoder->base,
4386 "active connector not linked to encoder\n");
4387 WARN(!encoder->connectors_active,
4388 "encoder->connectors_active not set\n");
4390 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4391 WARN(!encoder_enabled, "encoder not enabled\n");
4392 if (WARN_ON(!encoder->base.crtc))
4395 crtc = encoder->base.crtc;
4397 WARN(!crtc->enabled, "crtc not enabled\n");
4398 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4399 WARN(pipe != to_intel_crtc(crtc)->pipe,
4400 "encoder active on the wrong pipe\n");
4404 /* Even simpler default implementation, if there's really no special case to
4406 void intel_connector_dpms(struct drm_connector *connector, int mode)
4408 /* All the simple cases only support two dpms states. */
4409 if (mode != DRM_MODE_DPMS_ON)
4410 mode = DRM_MODE_DPMS_OFF;
4412 if (mode == connector->dpms)
4415 connector->dpms = mode;
4417 /* Only need to change hw state when actually enabled */
4418 if (connector->encoder)
4419 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4421 intel_modeset_check_state(connector->dev);
4424 /* Simple connector->get_hw_state implementation for encoders that support only
4425 * one connector and no cloning and hence the encoder state determines the state
4426 * of the connector. */
4427 bool intel_connector_get_hw_state(struct intel_connector *connector)
4430 struct intel_encoder *encoder = connector->encoder;
4432 return encoder->get_hw_state(encoder, &pipe);
4435 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4436 struct intel_crtc_config *pipe_config)
4438 struct drm_i915_private *dev_priv = dev->dev_private;
4439 struct intel_crtc *pipe_B_crtc =
4440 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4442 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4443 pipe_name(pipe), pipe_config->fdi_lanes);
4444 if (pipe_config->fdi_lanes > 4) {
4445 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4446 pipe_name(pipe), pipe_config->fdi_lanes);
4450 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4451 if (pipe_config->fdi_lanes > 2) {
4452 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4453 pipe_config->fdi_lanes);
4460 if (INTEL_INFO(dev)->num_pipes == 2)
4463 /* Ivybridge 3 pipe is really complicated */
4468 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4469 pipe_config->fdi_lanes > 2) {
4470 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4471 pipe_name(pipe), pipe_config->fdi_lanes);
4476 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4477 pipe_B_crtc->config.fdi_lanes <= 2) {
4478 if (pipe_config->fdi_lanes > 2) {
4479 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4480 pipe_name(pipe), pipe_config->fdi_lanes);
4484 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4494 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4495 struct intel_crtc_config *pipe_config)
4497 struct drm_device *dev = intel_crtc->base.dev;
4498 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4499 int lane, link_bw, fdi_dotclock;
4500 bool setup_ok, needs_recompute = false;
4503 /* FDI is a binary signal running at ~2.7GHz, encoding
4504 * each output octet as 10 bits. The actual frequency
4505 * is stored as a divider into a 100MHz clock, and the
4506 * mode pixel clock is stored in units of 1KHz.
4507 * Hence the bw of each lane in terms of the mode signal
4510 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4512 fdi_dotclock = adjusted_mode->crtc_clock;
4514 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4515 pipe_config->pipe_bpp);
4517 pipe_config->fdi_lanes = lane;
4519 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4520 link_bw, &pipe_config->fdi_m_n);
4522 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4523 intel_crtc->pipe, pipe_config);
4524 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4525 pipe_config->pipe_bpp -= 2*3;
4526 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4527 pipe_config->pipe_bpp);
4528 needs_recompute = true;
4529 pipe_config->bw_constrained = true;
4534 if (needs_recompute)
4537 return setup_ok ? 0 : -EINVAL;
4540 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4541 struct intel_crtc_config *pipe_config)
4543 pipe_config->ips_enabled = i915_enable_ips &&
4544 hsw_crtc_supports_ips(crtc) &&
4545 pipe_config->pipe_bpp <= 24;
4548 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4549 struct intel_crtc_config *pipe_config)
4551 struct drm_device *dev = crtc->base.dev;
4552 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4554 /* FIXME should check pixel clock limits on all platforms */
4555 if (INTEL_INFO(dev)->gen < 4) {
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4558 dev_priv->display.get_display_clock_speed(dev);
4561 * Enable pixel doubling when the dot clock
4562 * is > 90% of the (display) core speed.
4564 * GDG double wide on either pipe,
4565 * otherwise pipe A only.
4567 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4568 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4570 pipe_config->double_wide = true;
4573 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4578 * Pipe horizontal size must be even in:
4580 * - LVDS dual channel mode
4581 * - Double wide pipe
4583 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4584 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4585 pipe_config->pipe_src_w &= ~1;
4587 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4588 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4590 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4591 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4594 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4595 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4596 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4597 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4599 pipe_config->pipe_bpp = 8*3;
4603 hsw_compute_ips_config(crtc, pipe_config);
4605 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4606 * clock survives for now. */
4607 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4608 pipe_config->shared_dpll = crtc->config.shared_dpll;
4610 if (pipe_config->has_pch_encoder)
4611 return ironlake_fdi_compute_config(crtc, pipe_config);
4616 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4618 return 400000; /* FIXME */
4621 static int i945_get_display_clock_speed(struct drm_device *dev)
4626 static int i915_get_display_clock_speed(struct drm_device *dev)
4631 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4636 static int pnv_get_display_clock_speed(struct drm_device *dev)
4640 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4642 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4643 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4645 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4647 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4649 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4652 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4653 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4655 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4660 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4664 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4666 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4669 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4670 case GC_DISPLAY_CLOCK_333_MHZ:
4673 case GC_DISPLAY_CLOCK_190_200_MHZ:
4679 static int i865_get_display_clock_speed(struct drm_device *dev)
4684 static int i855_get_display_clock_speed(struct drm_device *dev)
4687 /* Assume that the hardware is in the high speed state. This
4688 * should be the default.
4690 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4691 case GC_CLOCK_133_200:
4692 case GC_CLOCK_100_200:
4694 case GC_CLOCK_166_250:
4696 case GC_CLOCK_100_133:
4700 /* Shouldn't happen */
4704 static int i830_get_display_clock_speed(struct drm_device *dev)
4710 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4712 while (*num > DATA_LINK_M_N_MASK ||
4713 *den > DATA_LINK_M_N_MASK) {
4719 static void compute_m_n(unsigned int m, unsigned int n,
4720 uint32_t *ret_m, uint32_t *ret_n)
4722 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4723 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4724 intel_reduce_m_n_ratio(ret_m, ret_n);
4728 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4729 int pixel_clock, int link_clock,
4730 struct intel_link_m_n *m_n)
4734 compute_m_n(bits_per_pixel * pixel_clock,
4735 link_clock * nlanes * 8,
4736 &m_n->gmch_m, &m_n->gmch_n);
4738 compute_m_n(pixel_clock, link_clock,
4739 &m_n->link_m, &m_n->link_n);
4742 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4744 if (i915_panel_use_ssc >= 0)
4745 return i915_panel_use_ssc != 0;
4746 return dev_priv->vbt.lvds_use_ssc
4747 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4750 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4752 struct drm_device *dev = crtc->dev;
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4756 if (IS_VALLEYVIEW(dev)) {
4758 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4759 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4760 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4761 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4763 } else if (!IS_GEN2(dev)) {
4772 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4774 return (1 << dpll->n) << 16 | dpll->m2;
4777 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4779 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4782 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4783 intel_clock_t *reduced_clock)
4785 struct drm_device *dev = crtc->base.dev;
4786 struct drm_i915_private *dev_priv = dev->dev_private;
4787 int pipe = crtc->pipe;
4790 if (IS_PINEVIEW(dev)) {
4791 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4793 fp2 = pnv_dpll_compute_fp(reduced_clock);
4795 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4797 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4800 I915_WRITE(FP0(pipe), fp);
4801 crtc->config.dpll_hw_state.fp0 = fp;
4803 crtc->lowfreq_avail = false;
4804 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4805 reduced_clock && i915_powersave) {
4806 I915_WRITE(FP1(pipe), fp2);
4807 crtc->config.dpll_hw_state.fp1 = fp2;
4808 crtc->lowfreq_avail = true;
4810 I915_WRITE(FP1(pipe), fp);
4811 crtc->config.dpll_hw_state.fp1 = fp;
4815 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4821 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4822 * and set it to a reasonable value instead.
4824 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4825 reg_val &= 0xffffff00;
4826 reg_val |= 0x00000030;
4827 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4829 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4830 reg_val &= 0x8cffffff;
4831 reg_val = 0x8c000000;
4832 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4834 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4835 reg_val &= 0xffffff00;
4836 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4838 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4839 reg_val &= 0x00ffffff;
4840 reg_val |= 0xb0000000;
4841 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4844 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4845 struct intel_link_m_n *m_n)
4847 struct drm_device *dev = crtc->base.dev;
4848 struct drm_i915_private *dev_priv = dev->dev_private;
4849 int pipe = crtc->pipe;
4851 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4852 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4853 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4854 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4857 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4858 struct intel_link_m_n *m_n)
4860 struct drm_device *dev = crtc->base.dev;
4861 struct drm_i915_private *dev_priv = dev->dev_private;
4862 int pipe = crtc->pipe;
4863 enum transcoder transcoder = crtc->config.cpu_transcoder;
4865 if (INTEL_INFO(dev)->gen >= 5) {
4866 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4867 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4868 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4869 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4871 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4872 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4873 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4874 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4878 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4880 if (crtc->config.has_pch_encoder)
4881 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4883 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4886 static void vlv_update_pll(struct intel_crtc *crtc)
4888 struct drm_device *dev = crtc->base.dev;
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 int pipe = crtc->pipe;
4892 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4893 u32 coreclk, reg_val, dpll_md;
4895 mutex_lock(&dev_priv->dpio_lock);
4897 bestn = crtc->config.dpll.n;
4898 bestm1 = crtc->config.dpll.m1;
4899 bestm2 = crtc->config.dpll.m2;
4900 bestp1 = crtc->config.dpll.p1;
4901 bestp2 = crtc->config.dpll.p2;
4903 /* See eDP HDMI DPIO driver vbios notes doc */
4905 /* PLL B needs special handling */
4907 vlv_pllb_recal_opamp(dev_priv, pipe);
4909 /* Set up Tx target for periodic Rcomp update */
4910 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4912 /* Disable target IRef on PLL */
4913 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4914 reg_val &= 0x00ffffff;
4915 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4917 /* Disable fast lock */
4918 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4920 /* Set idtafcrecal before PLL is enabled */
4921 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4922 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4923 mdiv |= ((bestn << DPIO_N_SHIFT));
4924 mdiv |= (1 << DPIO_K_SHIFT);
4927 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4928 * but we don't support that).
4929 * Note: don't use the DAC post divider as it seems unstable.
4931 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4932 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4934 mdiv |= DPIO_ENABLE_CALIBRATION;
4935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4937 /* Set HBR and RBR LPF coefficients */
4938 if (crtc->config.port_clock == 162000 ||
4939 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4940 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4947 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4948 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4949 /* Use SSC source */
4951 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4956 } else { /* HDMI or VGA */
4957 /* Use bend source */
4959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4966 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4967 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4968 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4969 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4970 coreclk |= 0x01000000;
4971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4973 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4975 /* Enable DPIO clock input */
4976 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4977 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4978 /* We should never disable this, set it here for state tracking */
4980 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4981 dpll |= DPLL_VCO_ENABLE;
4982 crtc->config.dpll_hw_state.dpll = dpll;
4984 dpll_md = (crtc->config.pixel_multiplier - 1)
4985 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4986 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4988 if (crtc->config.has_dp_encoder)
4989 intel_dp_set_m_n(crtc);
4991 mutex_unlock(&dev_priv->dpio_lock);
4994 static void i9xx_update_pll(struct intel_crtc *crtc,
4995 intel_clock_t *reduced_clock,
4998 struct drm_device *dev = crtc->base.dev;
4999 struct drm_i915_private *dev_priv = dev->dev_private;
5002 struct dpll *clock = &crtc->config.dpll;
5004 i9xx_update_pll_dividers(crtc, reduced_clock);
5006 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5007 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5009 dpll = DPLL_VGA_MODE_DIS;
5011 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5012 dpll |= DPLLB_MODE_LVDS;
5014 dpll |= DPLLB_MODE_DAC_SERIAL;
5016 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5017 dpll |= (crtc->config.pixel_multiplier - 1)
5018 << SDVO_MULTIPLIER_SHIFT_HIRES;
5022 dpll |= DPLL_SDVO_HIGH_SPEED;
5024 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5025 dpll |= DPLL_SDVO_HIGH_SPEED;
5027 /* compute bitmask from p1 value */
5028 if (IS_PINEVIEW(dev))
5029 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5031 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5032 if (IS_G4X(dev) && reduced_clock)
5033 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5035 switch (clock->p2) {
5037 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5040 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5043 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5046 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5049 if (INTEL_INFO(dev)->gen >= 4)
5050 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5052 if (crtc->config.sdvo_tv_clock)
5053 dpll |= PLL_REF_INPUT_TVCLKINBC;
5054 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5055 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5056 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5058 dpll |= PLL_REF_INPUT_DREFCLK;
5060 dpll |= DPLL_VCO_ENABLE;
5061 crtc->config.dpll_hw_state.dpll = dpll;
5063 if (INTEL_INFO(dev)->gen >= 4) {
5064 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5065 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5066 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5069 if (crtc->config.has_dp_encoder)
5070 intel_dp_set_m_n(crtc);
5073 static void i8xx_update_pll(struct intel_crtc *crtc,
5074 intel_clock_t *reduced_clock,
5077 struct drm_device *dev = crtc->base.dev;
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5080 struct dpll *clock = &crtc->config.dpll;
5082 i9xx_update_pll_dividers(crtc, reduced_clock);
5084 dpll = DPLL_VGA_MODE_DIS;
5086 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5087 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5090 dpll |= PLL_P1_DIVIDE_BY_TWO;
5092 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5094 dpll |= PLL_P2_DIVIDE_BY_4;
5097 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5098 dpll |= DPLL_DVO_2X_MODE;
5100 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5101 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5102 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5104 dpll |= PLL_REF_INPUT_DREFCLK;
5106 dpll |= DPLL_VCO_ENABLE;
5107 crtc->config.dpll_hw_state.dpll = dpll;
5110 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5112 struct drm_device *dev = intel_crtc->base.dev;
5113 struct drm_i915_private *dev_priv = dev->dev_private;
5114 enum pipe pipe = intel_crtc->pipe;
5115 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5116 struct drm_display_mode *adjusted_mode =
5117 &intel_crtc->config.adjusted_mode;
5118 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5120 /* We need to be careful not to changed the adjusted mode, for otherwise
5121 * the hw state checker will get angry at the mismatch. */
5122 crtc_vtotal = adjusted_mode->crtc_vtotal;
5123 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5125 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5126 /* the chip adds 2 halflines automatically */
5128 crtc_vblank_end -= 1;
5129 vsyncshift = adjusted_mode->crtc_hsync_start
5130 - adjusted_mode->crtc_htotal / 2;
5135 if (INTEL_INFO(dev)->gen > 3)
5136 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5138 I915_WRITE(HTOTAL(cpu_transcoder),
5139 (adjusted_mode->crtc_hdisplay - 1) |
5140 ((adjusted_mode->crtc_htotal - 1) << 16));
5141 I915_WRITE(HBLANK(cpu_transcoder),
5142 (adjusted_mode->crtc_hblank_start - 1) |
5143 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5144 I915_WRITE(HSYNC(cpu_transcoder),
5145 (adjusted_mode->crtc_hsync_start - 1) |
5146 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5148 I915_WRITE(VTOTAL(cpu_transcoder),
5149 (adjusted_mode->crtc_vdisplay - 1) |
5150 ((crtc_vtotal - 1) << 16));
5151 I915_WRITE(VBLANK(cpu_transcoder),
5152 (adjusted_mode->crtc_vblank_start - 1) |
5153 ((crtc_vblank_end - 1) << 16));
5154 I915_WRITE(VSYNC(cpu_transcoder),
5155 (adjusted_mode->crtc_vsync_start - 1) |
5156 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5158 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5159 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5160 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5162 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5163 (pipe == PIPE_B || pipe == PIPE_C))
5164 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5166 /* pipesrc controls the size that is scaled from, which should
5167 * always be the user's requested size.
5169 I915_WRITE(PIPESRC(pipe),
5170 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5171 (intel_crtc->config.pipe_src_h - 1));
5174 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5175 struct intel_crtc_config *pipe_config)
5177 struct drm_device *dev = crtc->base.dev;
5178 struct drm_i915_private *dev_priv = dev->dev_private;
5179 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5182 tmp = I915_READ(HTOTAL(cpu_transcoder));
5183 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5184 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5185 tmp = I915_READ(HBLANK(cpu_transcoder));
5186 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5187 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5188 tmp = I915_READ(HSYNC(cpu_transcoder));
5189 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5190 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5192 tmp = I915_READ(VTOTAL(cpu_transcoder));
5193 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5194 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5195 tmp = I915_READ(VBLANK(cpu_transcoder));
5196 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5197 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5198 tmp = I915_READ(VSYNC(cpu_transcoder));
5199 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5200 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5202 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5203 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5204 pipe_config->adjusted_mode.crtc_vtotal += 1;
5205 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5208 tmp = I915_READ(PIPESRC(crtc->pipe));
5209 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5210 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5212 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5213 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5216 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5217 struct intel_crtc_config *pipe_config)
5219 struct drm_crtc *crtc = &intel_crtc->base;
5221 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5222 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5223 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5224 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5226 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5227 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5228 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5229 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5231 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5233 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5234 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5237 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5239 struct drm_device *dev = intel_crtc->base.dev;
5240 struct drm_i915_private *dev_priv = dev->dev_private;
5245 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5246 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5247 pipeconf |= PIPECONF_ENABLE;
5249 if (intel_crtc->config.double_wide)
5250 pipeconf |= PIPECONF_DOUBLE_WIDE;
5252 /* only g4x and later have fancy bpc/dither controls */
5253 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5254 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5255 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5256 pipeconf |= PIPECONF_DITHER_EN |
5257 PIPECONF_DITHER_TYPE_SP;
5259 switch (intel_crtc->config.pipe_bpp) {
5261 pipeconf |= PIPECONF_6BPC;
5264 pipeconf |= PIPECONF_8BPC;
5267 pipeconf |= PIPECONF_10BPC;
5270 /* Case prevented by intel_choose_pipe_bpp_dither. */
5275 if (HAS_PIPE_CXSR(dev)) {
5276 if (intel_crtc->lowfreq_avail) {
5277 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5278 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5280 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5284 if (!IS_GEN2(dev) &&
5285 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5286 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5288 pipeconf |= PIPECONF_PROGRESSIVE;
5290 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5291 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5293 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5294 POSTING_READ(PIPECONF(intel_crtc->pipe));
5297 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5299 struct drm_framebuffer *fb)
5301 struct drm_device *dev = crtc->dev;
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5304 int pipe = intel_crtc->pipe;
5305 int plane = intel_crtc->plane;
5306 int refclk, num_connectors = 0;
5307 intel_clock_t clock, reduced_clock;
5309 bool ok, has_reduced_clock = false;
5310 bool is_lvds = false, is_dsi = false;
5311 struct intel_encoder *encoder;
5312 const intel_limit_t *limit;
5315 for_each_encoder_on_crtc(dev, crtc, encoder) {
5316 switch (encoder->type) {
5317 case INTEL_OUTPUT_LVDS:
5320 case INTEL_OUTPUT_DSI:
5331 if (!intel_crtc->config.clock_set) {
5332 refclk = i9xx_get_refclk(crtc, num_connectors);
5335 * Returns a set of divisors for the desired target clock with
5336 * the given refclk, or FALSE. The returned values represent
5337 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5340 limit = intel_limit(crtc, refclk);
5341 ok = dev_priv->display.find_dpll(limit, crtc,
5342 intel_crtc->config.port_clock,
5343 refclk, NULL, &clock);
5345 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5349 if (is_lvds && dev_priv->lvds_downclock_avail) {
5351 * Ensure we match the reduced clock's P to the target
5352 * clock. If the clocks don't match, we can't switch
5353 * the display clock by using the FP0/FP1. In such case
5354 * we will disable the LVDS downclock feature.
5357 dev_priv->display.find_dpll(limit, crtc,
5358 dev_priv->lvds_downclock,
5362 /* Compat-code for transition, will disappear. */
5363 intel_crtc->config.dpll.n = clock.n;
5364 intel_crtc->config.dpll.m1 = clock.m1;
5365 intel_crtc->config.dpll.m2 = clock.m2;
5366 intel_crtc->config.dpll.p1 = clock.p1;
5367 intel_crtc->config.dpll.p2 = clock.p2;
5371 i8xx_update_pll(intel_crtc,
5372 has_reduced_clock ? &reduced_clock : NULL,
5374 } else if (IS_VALLEYVIEW(dev)) {
5375 vlv_update_pll(intel_crtc);
5377 i9xx_update_pll(intel_crtc,
5378 has_reduced_clock ? &reduced_clock : NULL,
5383 /* Set up the display plane register */
5384 dspcntr = DISPPLANE_GAMMA_ENABLE;
5386 if (!IS_VALLEYVIEW(dev)) {
5388 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5390 dspcntr |= DISPPLANE_SEL_PIPE_B;
5393 intel_set_pipe_timings(intel_crtc);
5395 /* pipesrc and dspsize control the size that is scaled from,
5396 * which should always be the user's requested size.
5398 I915_WRITE(DSPSIZE(plane),
5399 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5400 (intel_crtc->config.pipe_src_w - 1));
5401 I915_WRITE(DSPPOS(plane), 0);
5403 i9xx_set_pipeconf(intel_crtc);
5405 I915_WRITE(DSPCNTR(plane), dspcntr);
5406 POSTING_READ(DSPCNTR(plane));
5408 ret = intel_pipe_set_base(crtc, x, y, fb);
5413 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5414 struct intel_crtc_config *pipe_config)
5416 struct drm_device *dev = crtc->base.dev;
5417 struct drm_i915_private *dev_priv = dev->dev_private;
5420 tmp = I915_READ(PFIT_CONTROL);
5421 if (!(tmp & PFIT_ENABLE))
5424 /* Check whether the pfit is attached to our pipe. */
5425 if (INTEL_INFO(dev)->gen < 4) {
5426 if (crtc->pipe != PIPE_B)
5429 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5433 pipe_config->gmch_pfit.control = tmp;
5434 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5435 if (INTEL_INFO(dev)->gen < 5)
5436 pipe_config->gmch_pfit.lvds_border_bits =
5437 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5440 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5441 struct intel_crtc_config *pipe_config)
5443 struct drm_device *dev = crtc->base.dev;
5444 struct drm_i915_private *dev_priv = dev->dev_private;
5445 int pipe = pipe_config->cpu_transcoder;
5446 intel_clock_t clock;
5448 int refclk = 100000;
5450 mutex_lock(&dev_priv->dpio_lock);
5451 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5452 mutex_unlock(&dev_priv->dpio_lock);
5454 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5455 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5456 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5457 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5458 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5460 vlv_clock(refclk, &clock);
5462 /* clock.dot is the fast clock */
5463 pipe_config->port_clock = clock.dot / 5;
5466 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5467 struct intel_crtc_config *pipe_config)
5469 struct drm_device *dev = crtc->base.dev;
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5473 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5474 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5476 tmp = I915_READ(PIPECONF(crtc->pipe));
5477 if (!(tmp & PIPECONF_ENABLE))
5480 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5481 switch (tmp & PIPECONF_BPC_MASK) {
5483 pipe_config->pipe_bpp = 18;
5486 pipe_config->pipe_bpp = 24;
5488 case PIPECONF_10BPC:
5489 pipe_config->pipe_bpp = 30;
5496 if (INTEL_INFO(dev)->gen < 4)
5497 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5499 intel_get_pipe_timings(crtc, pipe_config);
5501 i9xx_get_pfit_config(crtc, pipe_config);
5503 if (INTEL_INFO(dev)->gen >= 4) {
5504 tmp = I915_READ(DPLL_MD(crtc->pipe));
5505 pipe_config->pixel_multiplier =
5506 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5507 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5508 pipe_config->dpll_hw_state.dpll_md = tmp;
5509 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5510 tmp = I915_READ(DPLL(crtc->pipe));
5511 pipe_config->pixel_multiplier =
5512 ((tmp & SDVO_MULTIPLIER_MASK)
5513 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5515 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5516 * port and will be fixed up in the encoder->get_config
5518 pipe_config->pixel_multiplier = 1;
5520 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5521 if (!IS_VALLEYVIEW(dev)) {
5522 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5523 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5525 /* Mask out read-only status bits. */
5526 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5527 DPLL_PORTC_READY_MASK |
5528 DPLL_PORTB_READY_MASK);
5531 if (IS_VALLEYVIEW(dev))
5532 vlv_crtc_clock_get(crtc, pipe_config);
5534 i9xx_crtc_clock_get(crtc, pipe_config);
5539 static void ironlake_init_pch_refclk(struct drm_device *dev)
5541 struct drm_i915_private *dev_priv = dev->dev_private;
5542 struct drm_mode_config *mode_config = &dev->mode_config;
5543 struct intel_encoder *encoder;
5545 bool has_lvds = false;
5546 bool has_cpu_edp = false;
5547 bool has_panel = false;
5548 bool has_ck505 = false;
5549 bool can_ssc = false;
5551 /* We need to take the global config into account */
5552 list_for_each_entry(encoder, &mode_config->encoder_list,
5554 switch (encoder->type) {
5555 case INTEL_OUTPUT_LVDS:
5559 case INTEL_OUTPUT_EDP:
5561 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5567 if (HAS_PCH_IBX(dev)) {
5568 has_ck505 = dev_priv->vbt.display_clock_mode;
5569 can_ssc = has_ck505;
5575 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5576 has_panel, has_lvds, has_ck505);
5578 /* Ironlake: try to setup display ref clock before DPLL
5579 * enabling. This is only under driver's control after
5580 * PCH B stepping, previous chipset stepping should be
5581 * ignoring this setting.
5583 val = I915_READ(PCH_DREF_CONTROL);
5585 /* As we must carefully and slowly disable/enable each source in turn,
5586 * compute the final state we want first and check if we need to
5587 * make any changes at all.
5590 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5592 final |= DREF_NONSPREAD_CK505_ENABLE;
5594 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5596 final &= ~DREF_SSC_SOURCE_MASK;
5597 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5598 final &= ~DREF_SSC1_ENABLE;
5601 final |= DREF_SSC_SOURCE_ENABLE;
5603 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5604 final |= DREF_SSC1_ENABLE;
5607 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5608 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5610 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5612 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5614 final |= DREF_SSC_SOURCE_DISABLE;
5615 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5621 /* Always enable nonspread source */
5622 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5625 val |= DREF_NONSPREAD_CK505_ENABLE;
5627 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5630 val &= ~DREF_SSC_SOURCE_MASK;
5631 val |= DREF_SSC_SOURCE_ENABLE;
5633 /* SSC must be turned on before enabling the CPU output */
5634 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5635 DRM_DEBUG_KMS("Using SSC on panel\n");
5636 val |= DREF_SSC1_ENABLE;
5638 val &= ~DREF_SSC1_ENABLE;
5640 /* Get SSC going before enabling the outputs */
5641 I915_WRITE(PCH_DREF_CONTROL, val);
5642 POSTING_READ(PCH_DREF_CONTROL);
5645 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5647 /* Enable CPU source on CPU attached eDP */
5649 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5650 DRM_DEBUG_KMS("Using SSC on eDP\n");
5651 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5654 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5656 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5658 I915_WRITE(PCH_DREF_CONTROL, val);
5659 POSTING_READ(PCH_DREF_CONTROL);
5662 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5664 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5666 /* Turn off CPU output */
5667 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5669 I915_WRITE(PCH_DREF_CONTROL, val);
5670 POSTING_READ(PCH_DREF_CONTROL);
5673 /* Turn off the SSC source */
5674 val &= ~DREF_SSC_SOURCE_MASK;
5675 val |= DREF_SSC_SOURCE_DISABLE;
5678 val &= ~DREF_SSC1_ENABLE;
5680 I915_WRITE(PCH_DREF_CONTROL, val);
5681 POSTING_READ(PCH_DREF_CONTROL);
5685 BUG_ON(val != final);
5688 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5692 tmp = I915_READ(SOUTH_CHICKEN2);
5693 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5694 I915_WRITE(SOUTH_CHICKEN2, tmp);
5696 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5697 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5698 DRM_ERROR("FDI mPHY reset assert timeout\n");
5700 tmp = I915_READ(SOUTH_CHICKEN2);
5701 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5702 I915_WRITE(SOUTH_CHICKEN2, tmp);
5704 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5705 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5706 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5709 /* WaMPhyProgramming:hsw */
5710 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5714 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5715 tmp &= ~(0xFF << 24);
5716 tmp |= (0x12 << 24);
5717 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5719 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5721 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5723 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5725 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5727 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5728 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5729 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5731 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5732 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5733 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5735 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5738 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5740 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5743 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5745 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5748 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5750 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5753 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5755 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5756 tmp &= ~(0xFF << 16);
5757 tmp |= (0x1C << 16);
5758 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5760 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5761 tmp &= ~(0xFF << 16);
5762 tmp |= (0x1C << 16);
5763 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5765 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5767 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5769 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5771 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5773 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5774 tmp &= ~(0xF << 28);
5776 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5778 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5779 tmp &= ~(0xF << 28);
5781 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5784 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5785 * Programming" based on the parameters passed:
5786 * - Sequence to enable CLKOUT_DP
5787 * - Sequence to enable CLKOUT_DP without spread
5788 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5790 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5793 struct drm_i915_private *dev_priv = dev->dev_private;
5796 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5798 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5799 with_fdi, "LP PCH doesn't have FDI\n"))
5802 mutex_lock(&dev_priv->dpio_lock);
5804 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5805 tmp &= ~SBI_SSCCTL_DISABLE;
5806 tmp |= SBI_SSCCTL_PATHALT;
5807 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5812 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5813 tmp &= ~SBI_SSCCTL_PATHALT;
5814 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5817 lpt_reset_fdi_mphy(dev_priv);
5818 lpt_program_fdi_mphy(dev_priv);
5822 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5823 SBI_GEN0 : SBI_DBUFF0;
5824 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5825 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5826 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5828 mutex_unlock(&dev_priv->dpio_lock);
5831 /* Sequence to disable CLKOUT_DP */
5832 static void lpt_disable_clkout_dp(struct drm_device *dev)
5834 struct drm_i915_private *dev_priv = dev->dev_private;
5837 mutex_lock(&dev_priv->dpio_lock);
5839 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5840 SBI_GEN0 : SBI_DBUFF0;
5841 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5842 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5843 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5845 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5846 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5847 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5848 tmp |= SBI_SSCCTL_PATHALT;
5849 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5852 tmp |= SBI_SSCCTL_DISABLE;
5853 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5856 mutex_unlock(&dev_priv->dpio_lock);
5859 static void lpt_init_pch_refclk(struct drm_device *dev)
5861 struct drm_mode_config *mode_config = &dev->mode_config;
5862 struct intel_encoder *encoder;
5863 bool has_vga = false;
5865 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5866 switch (encoder->type) {
5867 case INTEL_OUTPUT_ANALOG:
5874 lpt_enable_clkout_dp(dev, true, true);
5876 lpt_disable_clkout_dp(dev);
5880 * Initialize reference clocks when the driver loads
5882 void intel_init_pch_refclk(struct drm_device *dev)
5884 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5885 ironlake_init_pch_refclk(dev);
5886 else if (HAS_PCH_LPT(dev))
5887 lpt_init_pch_refclk(dev);
5890 static int ironlake_get_refclk(struct drm_crtc *crtc)
5892 struct drm_device *dev = crtc->dev;
5893 struct drm_i915_private *dev_priv = dev->dev_private;
5894 struct intel_encoder *encoder;
5895 int num_connectors = 0;
5896 bool is_lvds = false;
5898 for_each_encoder_on_crtc(dev, crtc, encoder) {
5899 switch (encoder->type) {
5900 case INTEL_OUTPUT_LVDS:
5907 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5908 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5909 dev_priv->vbt.lvds_ssc_freq);
5910 return dev_priv->vbt.lvds_ssc_freq * 1000;
5916 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5918 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5920 int pipe = intel_crtc->pipe;
5925 switch (intel_crtc->config.pipe_bpp) {
5927 val |= PIPECONF_6BPC;
5930 val |= PIPECONF_8BPC;
5933 val |= PIPECONF_10BPC;
5936 val |= PIPECONF_12BPC;
5939 /* Case prevented by intel_choose_pipe_bpp_dither. */
5943 if (intel_crtc->config.dither)
5944 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5946 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5947 val |= PIPECONF_INTERLACED_ILK;
5949 val |= PIPECONF_PROGRESSIVE;
5951 if (intel_crtc->config.limited_color_range)
5952 val |= PIPECONF_COLOR_RANGE_SELECT;
5954 I915_WRITE(PIPECONF(pipe), val);
5955 POSTING_READ(PIPECONF(pipe));
5959 * Set up the pipe CSC unit.
5961 * Currently only full range RGB to limited range RGB conversion
5962 * is supported, but eventually this should handle various
5963 * RGB<->YCbCr scenarios as well.
5965 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5967 struct drm_device *dev = crtc->dev;
5968 struct drm_i915_private *dev_priv = dev->dev_private;
5969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5970 int pipe = intel_crtc->pipe;
5971 uint16_t coeff = 0x7800; /* 1.0 */
5974 * TODO: Check what kind of values actually come out of the pipe
5975 * with these coeff/postoff values and adjust to get the best
5976 * accuracy. Perhaps we even need to take the bpc value into
5980 if (intel_crtc->config.limited_color_range)
5981 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5984 * GY/GU and RY/RU should be the other way around according
5985 * to BSpec, but reality doesn't agree. Just set them up in
5986 * a way that results in the correct picture.
5988 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5989 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5991 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5992 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5994 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5995 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5997 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5998 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5999 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6001 if (INTEL_INFO(dev)->gen > 6) {
6002 uint16_t postoff = 0;
6004 if (intel_crtc->config.limited_color_range)
6005 postoff = (16 * (1 << 13) / 255) & 0x1fff;
6007 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6008 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6009 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6011 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6013 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6015 if (intel_crtc->config.limited_color_range)
6016 mode |= CSC_BLACK_SCREEN_OFFSET;
6018 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6022 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6024 struct drm_device *dev = crtc->dev;
6025 struct drm_i915_private *dev_priv = dev->dev_private;
6026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6027 enum pipe pipe = intel_crtc->pipe;
6028 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6033 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6034 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6036 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6037 val |= PIPECONF_INTERLACED_ILK;
6039 val |= PIPECONF_PROGRESSIVE;
6041 I915_WRITE(PIPECONF(cpu_transcoder), val);
6042 POSTING_READ(PIPECONF(cpu_transcoder));
6044 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6045 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6047 if (IS_BROADWELL(dev)) {
6050 switch (intel_crtc->config.pipe_bpp) {
6052 val |= PIPEMISC_DITHER_6_BPC;
6055 val |= PIPEMISC_DITHER_8_BPC;
6058 val |= PIPEMISC_DITHER_10_BPC;
6061 val |= PIPEMISC_DITHER_12_BPC;
6064 /* Case prevented by pipe_config_set_bpp. */
6068 if (intel_crtc->config.dither)
6069 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6071 I915_WRITE(PIPEMISC(pipe), val);
6075 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6076 intel_clock_t *clock,
6077 bool *has_reduced_clock,
6078 intel_clock_t *reduced_clock)
6080 struct drm_device *dev = crtc->dev;
6081 struct drm_i915_private *dev_priv = dev->dev_private;
6082 struct intel_encoder *intel_encoder;
6084 const intel_limit_t *limit;
6085 bool ret, is_lvds = false;
6087 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6088 switch (intel_encoder->type) {
6089 case INTEL_OUTPUT_LVDS:
6095 refclk = ironlake_get_refclk(crtc);
6098 * Returns a set of divisors for the desired target clock with the given
6099 * refclk, or FALSE. The returned values represent the clock equation:
6100 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6102 limit = intel_limit(crtc, refclk);
6103 ret = dev_priv->display.find_dpll(limit, crtc,
6104 to_intel_crtc(crtc)->config.port_clock,
6105 refclk, NULL, clock);
6109 if (is_lvds && dev_priv->lvds_downclock_avail) {
6111 * Ensure we match the reduced clock's P to the target clock.
6112 * If the clocks don't match, we can't switch the display clock
6113 * by using the FP0/FP1. In such case we will disable the LVDS
6114 * downclock feature.
6116 *has_reduced_clock =
6117 dev_priv->display.find_dpll(limit, crtc,
6118 dev_priv->lvds_downclock,
6126 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6129 * Account for spread spectrum to avoid
6130 * oversubscribing the link. Max center spread
6131 * is 2.5%; use 5% for safety's sake.
6133 u32 bps = target_clock * bpp * 21 / 20;
6134 return bps / (link_bw * 8) + 1;
6137 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6139 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6142 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6144 intel_clock_t *reduced_clock, u32 *fp2)
6146 struct drm_crtc *crtc = &intel_crtc->base;
6147 struct drm_device *dev = crtc->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 struct intel_encoder *intel_encoder;
6151 int factor, num_connectors = 0;
6152 bool is_lvds = false, is_sdvo = false;
6154 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6155 switch (intel_encoder->type) {
6156 case INTEL_OUTPUT_LVDS:
6159 case INTEL_OUTPUT_SDVO:
6160 case INTEL_OUTPUT_HDMI:
6168 /* Enable autotuning of the PLL clock (if permissible) */
6171 if ((intel_panel_use_ssc(dev_priv) &&
6172 dev_priv->vbt.lvds_ssc_freq == 100) ||
6173 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6175 } else if (intel_crtc->config.sdvo_tv_clock)
6178 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6181 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6187 dpll |= DPLLB_MODE_LVDS;
6189 dpll |= DPLLB_MODE_DAC_SERIAL;
6191 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6192 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6195 dpll |= DPLL_SDVO_HIGH_SPEED;
6196 if (intel_crtc->config.has_dp_encoder)
6197 dpll |= DPLL_SDVO_HIGH_SPEED;
6199 /* compute bitmask from p1 value */
6200 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6202 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6204 switch (intel_crtc->config.dpll.p2) {
6206 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6209 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6212 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6215 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6219 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6220 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6222 dpll |= PLL_REF_INPUT_DREFCLK;
6224 return dpll | DPLL_VCO_ENABLE;
6227 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6229 struct drm_framebuffer *fb)
6231 struct drm_device *dev = crtc->dev;
6232 struct drm_i915_private *dev_priv = dev->dev_private;
6233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6234 int pipe = intel_crtc->pipe;
6235 int plane = intel_crtc->plane;
6236 int num_connectors = 0;
6237 intel_clock_t clock, reduced_clock;
6238 u32 dpll = 0, fp = 0, fp2 = 0;
6239 bool ok, has_reduced_clock = false;
6240 bool is_lvds = false;
6241 struct intel_encoder *encoder;
6242 struct intel_shared_dpll *pll;
6245 for_each_encoder_on_crtc(dev, crtc, encoder) {
6246 switch (encoder->type) {
6247 case INTEL_OUTPUT_LVDS:
6255 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6256 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6258 ok = ironlake_compute_clocks(crtc, &clock,
6259 &has_reduced_clock, &reduced_clock);
6260 if (!ok && !intel_crtc->config.clock_set) {
6261 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6264 /* Compat-code for transition, will disappear. */
6265 if (!intel_crtc->config.clock_set) {
6266 intel_crtc->config.dpll.n = clock.n;
6267 intel_crtc->config.dpll.m1 = clock.m1;
6268 intel_crtc->config.dpll.m2 = clock.m2;
6269 intel_crtc->config.dpll.p1 = clock.p1;
6270 intel_crtc->config.dpll.p2 = clock.p2;
6273 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6274 if (intel_crtc->config.has_pch_encoder) {
6275 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6276 if (has_reduced_clock)
6277 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6279 dpll = ironlake_compute_dpll(intel_crtc,
6280 &fp, &reduced_clock,
6281 has_reduced_clock ? &fp2 : NULL);
6283 intel_crtc->config.dpll_hw_state.dpll = dpll;
6284 intel_crtc->config.dpll_hw_state.fp0 = fp;
6285 if (has_reduced_clock)
6286 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6288 intel_crtc->config.dpll_hw_state.fp1 = fp;
6290 pll = intel_get_shared_dpll(intel_crtc);
6292 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6297 intel_put_shared_dpll(intel_crtc);
6299 if (intel_crtc->config.has_dp_encoder)
6300 intel_dp_set_m_n(intel_crtc);
6302 if (is_lvds && has_reduced_clock && i915_powersave)
6303 intel_crtc->lowfreq_avail = true;
6305 intel_crtc->lowfreq_avail = false;
6307 intel_set_pipe_timings(intel_crtc);
6309 if (intel_crtc->config.has_pch_encoder) {
6310 intel_cpu_transcoder_set_m_n(intel_crtc,
6311 &intel_crtc->config.fdi_m_n);
6314 ironlake_set_pipeconf(crtc);
6316 /* Set up the display plane register */
6317 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6318 POSTING_READ(DSPCNTR(plane));
6320 ret = intel_pipe_set_base(crtc, x, y, fb);
6325 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6326 struct intel_link_m_n *m_n)
6328 struct drm_device *dev = crtc->base.dev;
6329 struct drm_i915_private *dev_priv = dev->dev_private;
6330 enum pipe pipe = crtc->pipe;
6332 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6333 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6334 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6336 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6337 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6338 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6341 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6342 enum transcoder transcoder,
6343 struct intel_link_m_n *m_n)
6345 struct drm_device *dev = crtc->base.dev;
6346 struct drm_i915_private *dev_priv = dev->dev_private;
6347 enum pipe pipe = crtc->pipe;
6349 if (INTEL_INFO(dev)->gen >= 5) {
6350 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6351 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6352 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6354 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6355 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6356 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6358 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6359 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6360 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6362 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6363 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6364 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6368 void intel_dp_get_m_n(struct intel_crtc *crtc,
6369 struct intel_crtc_config *pipe_config)
6371 if (crtc->config.has_pch_encoder)
6372 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6374 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6375 &pipe_config->dp_m_n);
6378 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6379 struct intel_crtc_config *pipe_config)
6381 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6382 &pipe_config->fdi_m_n);
6385 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6386 struct intel_crtc_config *pipe_config)
6388 struct drm_device *dev = crtc->base.dev;
6389 struct drm_i915_private *dev_priv = dev->dev_private;
6392 tmp = I915_READ(PF_CTL(crtc->pipe));
6394 if (tmp & PF_ENABLE) {
6395 pipe_config->pch_pfit.enabled = true;
6396 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6397 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6399 /* We currently do not free assignements of panel fitters on
6400 * ivb/hsw (since we don't use the higher upscaling modes which
6401 * differentiates them) so just WARN about this case for now. */
6403 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6404 PF_PIPE_SEL_IVB(crtc->pipe));
6409 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6410 struct intel_crtc_config *pipe_config)
6412 struct drm_device *dev = crtc->base.dev;
6413 struct drm_i915_private *dev_priv = dev->dev_private;
6416 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6417 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6419 tmp = I915_READ(PIPECONF(crtc->pipe));
6420 if (!(tmp & PIPECONF_ENABLE))
6423 switch (tmp & PIPECONF_BPC_MASK) {
6425 pipe_config->pipe_bpp = 18;
6428 pipe_config->pipe_bpp = 24;
6430 case PIPECONF_10BPC:
6431 pipe_config->pipe_bpp = 30;
6433 case PIPECONF_12BPC:
6434 pipe_config->pipe_bpp = 36;
6440 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6441 struct intel_shared_dpll *pll;
6443 pipe_config->has_pch_encoder = true;
6445 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6446 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6447 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6449 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6451 if (HAS_PCH_IBX(dev_priv->dev)) {
6452 pipe_config->shared_dpll =
6453 (enum intel_dpll_id) crtc->pipe;
6455 tmp = I915_READ(PCH_DPLL_SEL);
6456 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6457 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6459 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6462 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6464 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6465 &pipe_config->dpll_hw_state));
6467 tmp = pipe_config->dpll_hw_state.dpll;
6468 pipe_config->pixel_multiplier =
6469 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6470 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6472 ironlake_pch_clock_get(crtc, pipe_config);
6474 pipe_config->pixel_multiplier = 1;
6477 intel_get_pipe_timings(crtc, pipe_config);
6479 ironlake_get_pfit_config(crtc, pipe_config);
6484 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6486 struct drm_device *dev = dev_priv->dev;
6487 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6488 struct intel_crtc *crtc;
6489 unsigned long irqflags;
6492 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6493 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6494 pipe_name(crtc->pipe));
6496 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6497 WARN(plls->spll_refcount, "SPLL enabled\n");
6498 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6499 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6500 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6501 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6502 "CPU PWM1 enabled\n");
6503 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6504 "CPU PWM2 enabled\n");
6505 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6506 "PCH PWM1 enabled\n");
6507 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6508 "Utility pin enabled\n");
6509 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6511 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6512 val = I915_READ(DEIMR);
6513 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6514 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6515 val = I915_READ(SDEIMR);
6516 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6517 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6518 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6522 * This function implements pieces of two sequences from BSpec:
6523 * - Sequence for display software to disable LCPLL
6524 * - Sequence for display software to allow package C8+
6525 * The steps implemented here are just the steps that actually touch the LCPLL
6526 * register. Callers should take care of disabling all the display engine
6527 * functions, doing the mode unset, fixing interrupts, etc.
6529 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6530 bool switch_to_fclk, bool allow_power_down)
6534 assert_can_disable_lcpll(dev_priv);
6536 val = I915_READ(LCPLL_CTL);
6538 if (switch_to_fclk) {
6539 val |= LCPLL_CD_SOURCE_FCLK;
6540 I915_WRITE(LCPLL_CTL, val);
6542 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6543 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6544 DRM_ERROR("Switching to FCLK failed\n");
6546 val = I915_READ(LCPLL_CTL);
6549 val |= LCPLL_PLL_DISABLE;
6550 I915_WRITE(LCPLL_CTL, val);
6551 POSTING_READ(LCPLL_CTL);
6553 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6554 DRM_ERROR("LCPLL still locked\n");
6556 val = I915_READ(D_COMP);
6557 val |= D_COMP_COMP_DISABLE;
6558 mutex_lock(&dev_priv->rps.hw_lock);
6559 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6560 DRM_ERROR("Failed to disable D_COMP\n");
6561 mutex_unlock(&dev_priv->rps.hw_lock);
6562 POSTING_READ(D_COMP);
6565 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6566 DRM_ERROR("D_COMP RCOMP still in progress\n");
6568 if (allow_power_down) {
6569 val = I915_READ(LCPLL_CTL);
6570 val |= LCPLL_POWER_DOWN_ALLOW;
6571 I915_WRITE(LCPLL_CTL, val);
6572 POSTING_READ(LCPLL_CTL);
6577 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6580 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6584 val = I915_READ(LCPLL_CTL);
6586 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6587 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6590 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6591 * we'll hang the machine! */
6592 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6594 if (val & LCPLL_POWER_DOWN_ALLOW) {
6595 val &= ~LCPLL_POWER_DOWN_ALLOW;
6596 I915_WRITE(LCPLL_CTL, val);
6597 POSTING_READ(LCPLL_CTL);
6600 val = I915_READ(D_COMP);
6601 val |= D_COMP_COMP_FORCE;
6602 val &= ~D_COMP_COMP_DISABLE;
6603 mutex_lock(&dev_priv->rps.hw_lock);
6604 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6605 DRM_ERROR("Failed to enable D_COMP\n");
6606 mutex_unlock(&dev_priv->rps.hw_lock);
6607 POSTING_READ(D_COMP);
6609 val = I915_READ(LCPLL_CTL);
6610 val &= ~LCPLL_PLL_DISABLE;
6611 I915_WRITE(LCPLL_CTL, val);
6613 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6614 DRM_ERROR("LCPLL not locked yet\n");
6616 if (val & LCPLL_CD_SOURCE_FCLK) {
6617 val = I915_READ(LCPLL_CTL);
6618 val &= ~LCPLL_CD_SOURCE_FCLK;
6619 I915_WRITE(LCPLL_CTL, val);
6621 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6622 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6623 DRM_ERROR("Switching back to LCPLL failed\n");
6626 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6629 void hsw_enable_pc8_work(struct work_struct *__work)
6631 struct drm_i915_private *dev_priv =
6632 container_of(to_delayed_work(__work), struct drm_i915_private,
6634 struct drm_device *dev = dev_priv->dev;
6637 if (dev_priv->pc8.enabled)
6640 DRM_DEBUG_KMS("Enabling package C8+\n");
6642 dev_priv->pc8.enabled = true;
6644 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6645 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6646 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6647 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6650 lpt_disable_clkout_dp(dev);
6651 hsw_pc8_disable_interrupts(dev);
6652 hsw_disable_lcpll(dev_priv, true, true);
6655 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6657 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6658 WARN(dev_priv->pc8.disable_count < 1,
6659 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6661 dev_priv->pc8.disable_count--;
6662 if (dev_priv->pc8.disable_count != 0)
6665 schedule_delayed_work(&dev_priv->pc8.enable_work,
6666 msecs_to_jiffies(i915_pc8_timeout));
6669 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6671 struct drm_device *dev = dev_priv->dev;
6674 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6675 WARN(dev_priv->pc8.disable_count < 0,
6676 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6678 dev_priv->pc8.disable_count++;
6679 if (dev_priv->pc8.disable_count != 1)
6682 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6683 if (!dev_priv->pc8.enabled)
6686 DRM_DEBUG_KMS("Disabling package C8+\n");
6688 hsw_restore_lcpll(dev_priv);
6689 hsw_pc8_restore_interrupts(dev);
6690 lpt_init_pch_refclk(dev);
6692 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6693 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6694 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6695 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6698 intel_prepare_ddi(dev);
6699 i915_gem_init_swizzling(dev);
6700 mutex_lock(&dev_priv->rps.hw_lock);
6701 gen6_update_ring_freq(dev);
6702 mutex_unlock(&dev_priv->rps.hw_lock);
6703 dev_priv->pc8.enabled = false;
6706 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6708 if (!HAS_PC8(dev_priv->dev))
6711 mutex_lock(&dev_priv->pc8.lock);
6712 __hsw_enable_package_c8(dev_priv);
6713 mutex_unlock(&dev_priv->pc8.lock);
6716 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6718 if (!HAS_PC8(dev_priv->dev))
6721 mutex_lock(&dev_priv->pc8.lock);
6722 __hsw_disable_package_c8(dev_priv);
6723 mutex_unlock(&dev_priv->pc8.lock);
6726 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6728 struct drm_device *dev = dev_priv->dev;
6729 struct intel_crtc *crtc;
6732 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6733 if (crtc->base.enabled)
6736 /* This case is still possible since we have the i915.disable_power_well
6737 * parameter and also the KVMr or something else might be requesting the
6739 val = I915_READ(HSW_PWR_WELL_DRIVER);
6741 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6748 /* Since we're called from modeset_global_resources there's no way to
6749 * symmetrically increase and decrease the refcount, so we use
6750 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6753 static void hsw_update_package_c8(struct drm_device *dev)
6755 struct drm_i915_private *dev_priv = dev->dev_private;
6758 if (!HAS_PC8(dev_priv->dev))
6761 if (!i915_enable_pc8)
6764 mutex_lock(&dev_priv->pc8.lock);
6766 allow = hsw_can_enable_package_c8(dev_priv);
6768 if (allow == dev_priv->pc8.requirements_met)
6771 dev_priv->pc8.requirements_met = allow;
6774 __hsw_enable_package_c8(dev_priv);
6776 __hsw_disable_package_c8(dev_priv);
6779 mutex_unlock(&dev_priv->pc8.lock);
6782 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6784 if (!HAS_PC8(dev_priv->dev))
6787 mutex_lock(&dev_priv->pc8.lock);
6788 if (!dev_priv->pc8.gpu_idle) {
6789 dev_priv->pc8.gpu_idle = true;
6790 __hsw_enable_package_c8(dev_priv);
6792 mutex_unlock(&dev_priv->pc8.lock);
6795 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6797 if (!HAS_PC8(dev_priv->dev))
6800 mutex_lock(&dev_priv->pc8.lock);
6801 if (dev_priv->pc8.gpu_idle) {
6802 dev_priv->pc8.gpu_idle = false;
6803 __hsw_disable_package_c8(dev_priv);
6805 mutex_unlock(&dev_priv->pc8.lock);
6808 #define for_each_power_domain(domain, mask) \
6809 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6810 if ((1 << (domain)) & (mask))
6812 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6813 enum pipe pipe, bool pfit_enabled)
6816 enum transcoder transcoder;
6818 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6820 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6821 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6823 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6828 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6830 struct drm_i915_private *dev_priv = dev->dev_private;
6832 if (dev_priv->power_domains.init_power_on == enable)
6836 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6838 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6840 dev_priv->power_domains.init_power_on = enable;
6843 static void modeset_update_power_wells(struct drm_device *dev)
6845 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6846 struct intel_crtc *crtc;
6849 * First get all needed power domains, then put all unneeded, to avoid
6850 * any unnecessary toggling of the power wells.
6852 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6853 enum intel_display_power_domain domain;
6855 if (!crtc->base.enabled)
6858 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6860 crtc->config.pch_pfit.enabled);
6862 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6863 intel_display_power_get(dev, domain);
6866 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6867 enum intel_display_power_domain domain;
6869 for_each_power_domain(domain, crtc->enabled_power_domains)
6870 intel_display_power_put(dev, domain);
6872 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6875 intel_display_set_init_power(dev, false);
6878 static void haswell_modeset_global_resources(struct drm_device *dev)
6880 modeset_update_power_wells(dev);
6881 hsw_update_package_c8(dev);
6884 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6886 struct drm_framebuffer *fb)
6888 struct drm_device *dev = crtc->dev;
6889 struct drm_i915_private *dev_priv = dev->dev_private;
6890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6891 int plane = intel_crtc->plane;
6894 if (!intel_ddi_pll_mode_set(crtc))
6897 if (intel_crtc->config.has_dp_encoder)
6898 intel_dp_set_m_n(intel_crtc);
6900 intel_crtc->lowfreq_avail = false;
6902 intel_set_pipe_timings(intel_crtc);
6904 if (intel_crtc->config.has_pch_encoder) {
6905 intel_cpu_transcoder_set_m_n(intel_crtc,
6906 &intel_crtc->config.fdi_m_n);
6909 haswell_set_pipeconf(crtc);
6911 intel_set_pipe_csc(crtc);
6913 /* Set up the display plane register */
6914 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6915 POSTING_READ(DSPCNTR(plane));
6917 ret = intel_pipe_set_base(crtc, x, y, fb);
6922 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6923 struct intel_crtc_config *pipe_config)
6925 struct drm_device *dev = crtc->base.dev;
6926 struct drm_i915_private *dev_priv = dev->dev_private;
6927 enum intel_display_power_domain pfit_domain;
6930 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6931 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6933 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6934 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6935 enum pipe trans_edp_pipe;
6936 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6938 WARN(1, "unknown pipe linked to edp transcoder\n");
6939 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6940 case TRANS_DDI_EDP_INPUT_A_ON:
6941 trans_edp_pipe = PIPE_A;
6943 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6944 trans_edp_pipe = PIPE_B;
6946 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6947 trans_edp_pipe = PIPE_C;
6951 if (trans_edp_pipe == crtc->pipe)
6952 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6955 if (!intel_display_power_enabled(dev,
6956 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6959 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6960 if (!(tmp & PIPECONF_ENABLE))
6964 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6965 * DDI E. So just check whether this pipe is wired to DDI E and whether
6966 * the PCH transcoder is on.
6968 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6969 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6970 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6971 pipe_config->has_pch_encoder = true;
6973 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6974 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6975 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6977 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6980 intel_get_pipe_timings(crtc, pipe_config);
6982 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6983 if (intel_display_power_enabled(dev, pfit_domain))
6984 ironlake_get_pfit_config(crtc, pipe_config);
6986 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6987 (I915_READ(IPS_CTL) & IPS_ENABLE);
6989 pipe_config->pixel_multiplier = 1;
6994 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6996 struct drm_framebuffer *fb)
6998 struct drm_device *dev = crtc->dev;
6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000 struct intel_encoder *encoder;
7001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7002 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7003 int pipe = intel_crtc->pipe;
7006 drm_vblank_pre_modeset(dev, pipe);
7008 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7010 drm_vblank_post_modeset(dev, pipe);
7015 for_each_encoder_on_crtc(dev, crtc, encoder) {
7016 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7017 encoder->base.base.id,
7018 drm_get_encoder_name(&encoder->base),
7019 mode->base.id, mode->name);
7020 encoder->mode_set(encoder);
7029 } hdmi_audio_clock[] = {
7030 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7031 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7032 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7033 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7034 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7035 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7036 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7037 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7038 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7039 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7042 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7043 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7047 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7048 if (mode->clock == hdmi_audio_clock[i].clock)
7052 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7053 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7057 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7058 hdmi_audio_clock[i].clock,
7059 hdmi_audio_clock[i].config);
7061 return hdmi_audio_clock[i].config;
7064 static bool intel_eld_uptodate(struct drm_connector *connector,
7065 int reg_eldv, uint32_t bits_eldv,
7066 int reg_elda, uint32_t bits_elda,
7069 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7070 uint8_t *eld = connector->eld;
7073 i = I915_READ(reg_eldv);
7082 i = I915_READ(reg_elda);
7084 I915_WRITE(reg_elda, i);
7086 for (i = 0; i < eld[2]; i++)
7087 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7093 static void g4x_write_eld(struct drm_connector *connector,
7094 struct drm_crtc *crtc,
7095 struct drm_display_mode *mode)
7097 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7098 uint8_t *eld = connector->eld;
7103 i = I915_READ(G4X_AUD_VID_DID);
7105 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7106 eldv = G4X_ELDV_DEVCL_DEVBLC;
7108 eldv = G4X_ELDV_DEVCTG;
7110 if (intel_eld_uptodate(connector,
7111 G4X_AUD_CNTL_ST, eldv,
7112 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7113 G4X_HDMIW_HDMIEDID))
7116 i = I915_READ(G4X_AUD_CNTL_ST);
7117 i &= ~(eldv | G4X_ELD_ADDR);
7118 len = (i >> 9) & 0x1f; /* ELD buffer size */
7119 I915_WRITE(G4X_AUD_CNTL_ST, i);
7124 len = min_t(uint8_t, eld[2], len);
7125 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7126 for (i = 0; i < len; i++)
7127 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7129 i = I915_READ(G4X_AUD_CNTL_ST);
7131 I915_WRITE(G4X_AUD_CNTL_ST, i);
7134 static void haswell_write_eld(struct drm_connector *connector,
7135 struct drm_crtc *crtc,
7136 struct drm_display_mode *mode)
7138 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7139 uint8_t *eld = connector->eld;
7140 struct drm_device *dev = crtc->dev;
7141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7145 int pipe = to_intel_crtc(crtc)->pipe;
7148 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7149 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7150 int aud_config = HSW_AUD_CFG(pipe);
7151 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7154 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7156 /* Audio output enable */
7157 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7158 tmp = I915_READ(aud_cntrl_st2);
7159 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7160 I915_WRITE(aud_cntrl_st2, tmp);
7162 /* Wait for 1 vertical blank */
7163 intel_wait_for_vblank(dev, pipe);
7165 /* Set ELD valid state */
7166 tmp = I915_READ(aud_cntrl_st2);
7167 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7168 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7169 I915_WRITE(aud_cntrl_st2, tmp);
7170 tmp = I915_READ(aud_cntrl_st2);
7171 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7173 /* Enable HDMI mode */
7174 tmp = I915_READ(aud_config);
7175 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7176 /* clear N_programing_enable and N_value_index */
7177 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7178 I915_WRITE(aud_config, tmp);
7180 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7182 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7183 intel_crtc->eld_vld = true;
7185 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7186 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7187 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7188 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7190 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7193 if (intel_eld_uptodate(connector,
7194 aud_cntrl_st2, eldv,
7195 aud_cntl_st, IBX_ELD_ADDRESS,
7199 i = I915_READ(aud_cntrl_st2);
7201 I915_WRITE(aud_cntrl_st2, i);
7206 i = I915_READ(aud_cntl_st);
7207 i &= ~IBX_ELD_ADDRESS;
7208 I915_WRITE(aud_cntl_st, i);
7209 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7210 DRM_DEBUG_DRIVER("port num:%d\n", i);
7212 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7213 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7214 for (i = 0; i < len; i++)
7215 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7217 i = I915_READ(aud_cntrl_st2);
7219 I915_WRITE(aud_cntrl_st2, i);
7223 static void ironlake_write_eld(struct drm_connector *connector,
7224 struct drm_crtc *crtc,
7225 struct drm_display_mode *mode)
7227 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7228 uint8_t *eld = connector->eld;
7236 int pipe = to_intel_crtc(crtc)->pipe;
7238 if (HAS_PCH_IBX(connector->dev)) {
7239 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7240 aud_config = IBX_AUD_CFG(pipe);
7241 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7242 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7243 } else if (IS_VALLEYVIEW(connector->dev)) {
7244 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7245 aud_config = VLV_AUD_CFG(pipe);
7246 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7247 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7249 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7250 aud_config = CPT_AUD_CFG(pipe);
7251 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7252 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7255 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7257 if (IS_VALLEYVIEW(connector->dev)) {
7258 struct intel_encoder *intel_encoder;
7259 struct intel_digital_port *intel_dig_port;
7261 intel_encoder = intel_attached_encoder(connector);
7262 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7263 i = intel_dig_port->port;
7265 i = I915_READ(aud_cntl_st);
7266 i = (i >> 29) & DIP_PORT_SEL_MASK;
7267 /* DIP_Port_Select, 0x1 = PortB */
7271 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7272 /* operate blindly on all ports */
7273 eldv = IBX_ELD_VALIDB;
7274 eldv |= IBX_ELD_VALIDB << 4;
7275 eldv |= IBX_ELD_VALIDB << 8;
7277 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7278 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7281 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7282 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7283 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7284 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7286 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7289 if (intel_eld_uptodate(connector,
7290 aud_cntrl_st2, eldv,
7291 aud_cntl_st, IBX_ELD_ADDRESS,
7295 i = I915_READ(aud_cntrl_st2);
7297 I915_WRITE(aud_cntrl_st2, i);
7302 i = I915_READ(aud_cntl_st);
7303 i &= ~IBX_ELD_ADDRESS;
7304 I915_WRITE(aud_cntl_st, i);
7306 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7307 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7308 for (i = 0; i < len; i++)
7309 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7311 i = I915_READ(aud_cntrl_st2);
7313 I915_WRITE(aud_cntrl_st2, i);
7316 void intel_write_eld(struct drm_encoder *encoder,
7317 struct drm_display_mode *mode)
7319 struct drm_crtc *crtc = encoder->crtc;
7320 struct drm_connector *connector;
7321 struct drm_device *dev = encoder->dev;
7322 struct drm_i915_private *dev_priv = dev->dev_private;
7324 connector = drm_select_eld(encoder, mode);
7328 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7330 drm_get_connector_name(connector),
7331 connector->encoder->base.id,
7332 drm_get_encoder_name(connector->encoder));
7334 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7336 if (dev_priv->display.write_eld)
7337 dev_priv->display.write_eld(connector, crtc, mode);
7340 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7342 struct drm_device *dev = crtc->dev;
7343 struct drm_i915_private *dev_priv = dev->dev_private;
7344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7345 bool visible = base != 0;
7348 if (intel_crtc->cursor_visible == visible)
7351 cntl = I915_READ(_CURACNTR);
7353 /* On these chipsets we can only modify the base whilst
7354 * the cursor is disabled.
7356 I915_WRITE(_CURABASE, base);
7358 cntl &= ~(CURSOR_FORMAT_MASK);
7359 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7360 cntl |= CURSOR_ENABLE |
7361 CURSOR_GAMMA_ENABLE |
7364 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7365 I915_WRITE(_CURACNTR, cntl);
7367 intel_crtc->cursor_visible = visible;
7370 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7372 struct drm_device *dev = crtc->dev;
7373 struct drm_i915_private *dev_priv = dev->dev_private;
7374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7375 int pipe = intel_crtc->pipe;
7376 bool visible = base != 0;
7378 if (intel_crtc->cursor_visible != visible) {
7379 uint32_t cntl = I915_READ(CURCNTR(pipe));
7381 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7382 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7383 cntl |= pipe << 28; /* Connect to correct pipe */
7385 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7386 cntl |= CURSOR_MODE_DISABLE;
7388 I915_WRITE(CURCNTR(pipe), cntl);
7390 intel_crtc->cursor_visible = visible;
7392 /* and commit changes on next vblank */
7393 POSTING_READ(CURCNTR(pipe));
7394 I915_WRITE(CURBASE(pipe), base);
7395 POSTING_READ(CURBASE(pipe));
7398 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7400 struct drm_device *dev = crtc->dev;
7401 struct drm_i915_private *dev_priv = dev->dev_private;
7402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7403 int pipe = intel_crtc->pipe;
7404 bool visible = base != 0;
7406 if (intel_crtc->cursor_visible != visible) {
7407 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7409 cntl &= ~CURSOR_MODE;
7410 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7412 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7413 cntl |= CURSOR_MODE_DISABLE;
7415 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7416 cntl |= CURSOR_PIPE_CSC_ENABLE;
7417 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7419 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7421 intel_crtc->cursor_visible = visible;
7423 /* and commit changes on next vblank */
7424 POSTING_READ(CURCNTR_IVB(pipe));
7425 I915_WRITE(CURBASE_IVB(pipe), base);
7426 POSTING_READ(CURBASE_IVB(pipe));
7429 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7430 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7433 struct drm_device *dev = crtc->dev;
7434 struct drm_i915_private *dev_priv = dev->dev_private;
7435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7436 int pipe = intel_crtc->pipe;
7437 int x = intel_crtc->cursor_x;
7438 int y = intel_crtc->cursor_y;
7439 u32 base = 0, pos = 0;
7443 base = intel_crtc->cursor_addr;
7445 if (x >= intel_crtc->config.pipe_src_w)
7448 if (y >= intel_crtc->config.pipe_src_h)
7452 if (x + intel_crtc->cursor_width <= 0)
7455 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7458 pos |= x << CURSOR_X_SHIFT;
7461 if (y + intel_crtc->cursor_height <= 0)
7464 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7467 pos |= y << CURSOR_Y_SHIFT;
7469 visible = base != 0;
7470 if (!visible && !intel_crtc->cursor_visible)
7473 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7474 I915_WRITE(CURPOS_IVB(pipe), pos);
7475 ivb_update_cursor(crtc, base);
7477 I915_WRITE(CURPOS(pipe), pos);
7478 if (IS_845G(dev) || IS_I865G(dev))
7479 i845_update_cursor(crtc, base);
7481 i9xx_update_cursor(crtc, base);
7485 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7486 struct drm_file *file,
7488 uint32_t width, uint32_t height)
7490 struct drm_device *dev = crtc->dev;
7491 struct drm_i915_private *dev_priv = dev->dev_private;
7492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7493 struct drm_i915_gem_object *obj;
7497 /* if we want to turn off the cursor ignore width and height */
7499 DRM_DEBUG_KMS("cursor off\n");
7502 mutex_lock(&dev->struct_mutex);
7506 /* Currently we only support 64x64 cursors */
7507 if (width != 64 || height != 64) {
7508 DRM_ERROR("we currently only support 64x64 cursors\n");
7512 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7513 if (&obj->base == NULL)
7516 if (obj->base.size < width * height * 4) {
7517 DRM_ERROR("buffer is to small\n");
7522 /* we only need to pin inside GTT if cursor is non-phy */
7523 mutex_lock(&dev->struct_mutex);
7524 if (!dev_priv->info->cursor_needs_physical) {
7527 if (obj->tiling_mode) {
7528 DRM_ERROR("cursor cannot be tiled\n");
7533 /* Note that the w/a also requires 2 PTE of padding following
7534 * the bo. We currently fill all unused PTE with the shadow
7535 * page and so we should always have valid PTE following the
7536 * cursor preventing the VT-d warning.
7539 if (need_vtd_wa(dev))
7540 alignment = 64*1024;
7542 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7544 DRM_ERROR("failed to move cursor bo into the GTT\n");
7548 ret = i915_gem_object_put_fence(obj);
7550 DRM_ERROR("failed to release fence for cursor");
7554 addr = i915_gem_obj_ggtt_offset(obj);
7556 int align = IS_I830(dev) ? 16 * 1024 : 256;
7557 ret = i915_gem_attach_phys_object(dev, obj,
7558 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7561 DRM_ERROR("failed to attach phys object\n");
7564 addr = obj->phys_obj->handle->busaddr;
7568 I915_WRITE(CURSIZE, (height << 12) | width);
7571 if (intel_crtc->cursor_bo) {
7572 if (dev_priv->info->cursor_needs_physical) {
7573 if (intel_crtc->cursor_bo != obj)
7574 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7576 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7577 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7580 mutex_unlock(&dev->struct_mutex);
7582 intel_crtc->cursor_addr = addr;
7583 intel_crtc->cursor_bo = obj;
7584 intel_crtc->cursor_width = width;
7585 intel_crtc->cursor_height = height;
7587 if (intel_crtc->active)
7588 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7592 i915_gem_object_unpin_from_display_plane(obj);
7594 mutex_unlock(&dev->struct_mutex);
7596 drm_gem_object_unreference_unlocked(&obj->base);
7600 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7604 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7605 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7607 if (intel_crtc->active)
7608 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7613 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7614 u16 *blue, uint32_t start, uint32_t size)
7616 int end = (start + size > 256) ? 256 : start + size, i;
7617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7619 for (i = start; i < end; i++) {
7620 intel_crtc->lut_r[i] = red[i] >> 8;
7621 intel_crtc->lut_g[i] = green[i] >> 8;
7622 intel_crtc->lut_b[i] = blue[i] >> 8;
7625 intel_crtc_load_lut(crtc);
7628 /* VESA 640x480x72Hz mode to set on the pipe */
7629 static struct drm_display_mode load_detect_mode = {
7630 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7631 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7634 static struct drm_framebuffer *
7635 intel_framebuffer_create(struct drm_device *dev,
7636 struct drm_mode_fb_cmd2 *mode_cmd,
7637 struct drm_i915_gem_object *obj)
7639 struct intel_framebuffer *intel_fb;
7642 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7644 drm_gem_object_unreference_unlocked(&obj->base);
7645 return ERR_PTR(-ENOMEM);
7648 ret = i915_mutex_lock_interruptible(dev);
7652 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7653 mutex_unlock(&dev->struct_mutex);
7657 return &intel_fb->base;
7659 drm_gem_object_unreference_unlocked(&obj->base);
7662 return ERR_PTR(ret);
7666 intel_framebuffer_pitch_for_width(int width, int bpp)
7668 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7669 return ALIGN(pitch, 64);
7673 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7675 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7676 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7679 static struct drm_framebuffer *
7680 intel_framebuffer_create_for_mode(struct drm_device *dev,
7681 struct drm_display_mode *mode,
7684 struct drm_i915_gem_object *obj;
7685 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7687 obj = i915_gem_alloc_object(dev,
7688 intel_framebuffer_size_for_mode(mode, bpp));
7690 return ERR_PTR(-ENOMEM);
7692 mode_cmd.width = mode->hdisplay;
7693 mode_cmd.height = mode->vdisplay;
7694 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7696 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7698 return intel_framebuffer_create(dev, &mode_cmd, obj);
7701 static struct drm_framebuffer *
7702 mode_fits_in_fbdev(struct drm_device *dev,
7703 struct drm_display_mode *mode)
7705 #ifdef CONFIG_DRM_I915_FBDEV
7706 struct drm_i915_private *dev_priv = dev->dev_private;
7707 struct drm_i915_gem_object *obj;
7708 struct drm_framebuffer *fb;
7710 if (dev_priv->fbdev == NULL)
7713 obj = dev_priv->fbdev->ifb.obj;
7717 fb = &dev_priv->fbdev->ifb.base;
7718 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7719 fb->bits_per_pixel))
7722 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7731 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7732 struct drm_display_mode *mode,
7733 struct intel_load_detect_pipe *old)
7735 struct intel_crtc *intel_crtc;
7736 struct intel_encoder *intel_encoder =
7737 intel_attached_encoder(connector);
7738 struct drm_crtc *possible_crtc;
7739 struct drm_encoder *encoder = &intel_encoder->base;
7740 struct drm_crtc *crtc = NULL;
7741 struct drm_device *dev = encoder->dev;
7742 struct drm_framebuffer *fb;
7745 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7746 connector->base.id, drm_get_connector_name(connector),
7747 encoder->base.id, drm_get_encoder_name(encoder));
7750 * Algorithm gets a little messy:
7752 * - if the connector already has an assigned crtc, use it (but make
7753 * sure it's on first)
7755 * - try to find the first unused crtc that can drive this connector,
7756 * and use that if we find one
7759 /* See if we already have a CRTC for this connector */
7760 if (encoder->crtc) {
7761 crtc = encoder->crtc;
7763 mutex_lock(&crtc->mutex);
7765 old->dpms_mode = connector->dpms;
7766 old->load_detect_temp = false;
7768 /* Make sure the crtc and connector are running */
7769 if (connector->dpms != DRM_MODE_DPMS_ON)
7770 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7775 /* Find an unused one (if possible) */
7776 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7778 if (!(encoder->possible_crtcs & (1 << i)))
7780 if (!possible_crtc->enabled) {
7781 crtc = possible_crtc;
7787 * If we didn't find an unused CRTC, don't use any.
7790 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7794 mutex_lock(&crtc->mutex);
7795 intel_encoder->new_crtc = to_intel_crtc(crtc);
7796 to_intel_connector(connector)->new_encoder = intel_encoder;
7798 intel_crtc = to_intel_crtc(crtc);
7799 old->dpms_mode = connector->dpms;
7800 old->load_detect_temp = true;
7801 old->release_fb = NULL;
7804 mode = &load_detect_mode;
7806 /* We need a framebuffer large enough to accommodate all accesses
7807 * that the plane may generate whilst we perform load detection.
7808 * We can not rely on the fbcon either being present (we get called
7809 * during its initialisation to detect all boot displays, or it may
7810 * not even exist) or that it is large enough to satisfy the
7813 fb = mode_fits_in_fbdev(dev, mode);
7815 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7816 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7817 old->release_fb = fb;
7819 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7821 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7822 mutex_unlock(&crtc->mutex);
7826 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7827 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7828 if (old->release_fb)
7829 old->release_fb->funcs->destroy(old->release_fb);
7830 mutex_unlock(&crtc->mutex);
7834 /* let the connector get through one full cycle before testing */
7835 intel_wait_for_vblank(dev, intel_crtc->pipe);
7839 void intel_release_load_detect_pipe(struct drm_connector *connector,
7840 struct intel_load_detect_pipe *old)
7842 struct intel_encoder *intel_encoder =
7843 intel_attached_encoder(connector);
7844 struct drm_encoder *encoder = &intel_encoder->base;
7845 struct drm_crtc *crtc = encoder->crtc;
7847 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7848 connector->base.id, drm_get_connector_name(connector),
7849 encoder->base.id, drm_get_encoder_name(encoder));
7851 if (old->load_detect_temp) {
7852 to_intel_connector(connector)->new_encoder = NULL;
7853 intel_encoder->new_crtc = NULL;
7854 intel_set_mode(crtc, NULL, 0, 0, NULL);
7856 if (old->release_fb) {
7857 drm_framebuffer_unregister_private(old->release_fb);
7858 drm_framebuffer_unreference(old->release_fb);
7861 mutex_unlock(&crtc->mutex);
7865 /* Switch crtc and encoder back off if necessary */
7866 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7867 connector->funcs->dpms(connector, old->dpms_mode);
7869 mutex_unlock(&crtc->mutex);
7872 static int i9xx_pll_refclk(struct drm_device *dev,
7873 const struct intel_crtc_config *pipe_config)
7875 struct drm_i915_private *dev_priv = dev->dev_private;
7876 u32 dpll = pipe_config->dpll_hw_state.dpll;
7878 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7879 return dev_priv->vbt.lvds_ssc_freq * 1000;
7880 else if (HAS_PCH_SPLIT(dev))
7882 else if (!IS_GEN2(dev))
7888 /* Returns the clock of the currently programmed mode of the given pipe. */
7889 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7890 struct intel_crtc_config *pipe_config)
7892 struct drm_device *dev = crtc->base.dev;
7893 struct drm_i915_private *dev_priv = dev->dev_private;
7894 int pipe = pipe_config->cpu_transcoder;
7895 u32 dpll = pipe_config->dpll_hw_state.dpll;
7897 intel_clock_t clock;
7898 int refclk = i9xx_pll_refclk(dev, pipe_config);
7900 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7901 fp = pipe_config->dpll_hw_state.fp0;
7903 fp = pipe_config->dpll_hw_state.fp1;
7905 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7906 if (IS_PINEVIEW(dev)) {
7907 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7908 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7910 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7911 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7914 if (!IS_GEN2(dev)) {
7915 if (IS_PINEVIEW(dev))
7916 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7917 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7919 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7920 DPLL_FPA01_P1_POST_DIV_SHIFT);
7922 switch (dpll & DPLL_MODE_MASK) {
7923 case DPLLB_MODE_DAC_SERIAL:
7924 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7927 case DPLLB_MODE_LVDS:
7928 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7932 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7933 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7937 if (IS_PINEVIEW(dev))
7938 pineview_clock(refclk, &clock);
7940 i9xx_clock(refclk, &clock);
7942 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7945 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7946 DPLL_FPA01_P1_POST_DIV_SHIFT);
7949 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7952 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7953 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7955 if (dpll & PLL_P2_DIVIDE_BY_4)
7961 i9xx_clock(refclk, &clock);
7965 * This value includes pixel_multiplier. We will use
7966 * port_clock to compute adjusted_mode.crtc_clock in the
7967 * encoder's get_config() function.
7969 pipe_config->port_clock = clock.dot;
7972 int intel_dotclock_calculate(int link_freq,
7973 const struct intel_link_m_n *m_n)
7976 * The calculation for the data clock is:
7977 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7978 * But we want to avoid losing precison if possible, so:
7979 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7981 * and the link clock is simpler:
7982 * link_clock = (m * link_clock) / n
7988 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7991 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7992 struct intel_crtc_config *pipe_config)
7994 struct drm_device *dev = crtc->base.dev;
7996 /* read out port_clock from the DPLL */
7997 i9xx_crtc_clock_get(crtc, pipe_config);
8000 * This value does not include pixel_multiplier.
8001 * We will check that port_clock and adjusted_mode.crtc_clock
8002 * agree once we know their relationship in the encoder's
8003 * get_config() function.
8005 pipe_config->adjusted_mode.crtc_clock =
8006 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8007 &pipe_config->fdi_m_n);
8010 /** Returns the currently programmed mode of the given pipe. */
8011 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8012 struct drm_crtc *crtc)
8014 struct drm_i915_private *dev_priv = dev->dev_private;
8015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8016 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8017 struct drm_display_mode *mode;
8018 struct intel_crtc_config pipe_config;
8019 int htot = I915_READ(HTOTAL(cpu_transcoder));
8020 int hsync = I915_READ(HSYNC(cpu_transcoder));
8021 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8022 int vsync = I915_READ(VSYNC(cpu_transcoder));
8023 enum pipe pipe = intel_crtc->pipe;
8025 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8030 * Construct a pipe_config sufficient for getting the clock info
8031 * back out of crtc_clock_get.
8033 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8034 * to use a real value here instead.
8036 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8037 pipe_config.pixel_multiplier = 1;
8038 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8039 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8040 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8041 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8043 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8044 mode->hdisplay = (htot & 0xffff) + 1;
8045 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8046 mode->hsync_start = (hsync & 0xffff) + 1;
8047 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8048 mode->vdisplay = (vtot & 0xffff) + 1;
8049 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8050 mode->vsync_start = (vsync & 0xffff) + 1;
8051 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8053 drm_mode_set_name(mode);
8058 static void intel_increase_pllclock(struct drm_crtc *crtc)
8060 struct drm_device *dev = crtc->dev;
8061 drm_i915_private_t *dev_priv = dev->dev_private;
8062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8063 int pipe = intel_crtc->pipe;
8064 int dpll_reg = DPLL(pipe);
8067 if (HAS_PCH_SPLIT(dev))
8070 if (!dev_priv->lvds_downclock_avail)
8073 dpll = I915_READ(dpll_reg);
8074 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8075 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8077 assert_panel_unlocked(dev_priv, pipe);
8079 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8080 I915_WRITE(dpll_reg, dpll);
8081 intel_wait_for_vblank(dev, pipe);
8083 dpll = I915_READ(dpll_reg);
8084 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8085 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8089 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8091 struct drm_device *dev = crtc->dev;
8092 drm_i915_private_t *dev_priv = dev->dev_private;
8093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8095 if (HAS_PCH_SPLIT(dev))
8098 if (!dev_priv->lvds_downclock_avail)
8102 * Since this is called by a timer, we should never get here in
8105 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8106 int pipe = intel_crtc->pipe;
8107 int dpll_reg = DPLL(pipe);
8110 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8112 assert_panel_unlocked(dev_priv, pipe);
8114 dpll = I915_READ(dpll_reg);
8115 dpll |= DISPLAY_RATE_SELECT_FPA1;
8116 I915_WRITE(dpll_reg, dpll);
8117 intel_wait_for_vblank(dev, pipe);
8118 dpll = I915_READ(dpll_reg);
8119 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8120 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8125 void intel_mark_busy(struct drm_device *dev)
8127 struct drm_i915_private *dev_priv = dev->dev_private;
8129 hsw_package_c8_gpu_busy(dev_priv);
8130 i915_update_gfx_val(dev_priv);
8133 void intel_mark_idle(struct drm_device *dev)
8135 struct drm_i915_private *dev_priv = dev->dev_private;
8136 struct drm_crtc *crtc;
8138 hsw_package_c8_gpu_idle(dev_priv);
8140 if (!i915_powersave)
8143 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8147 intel_decrease_pllclock(crtc);
8150 if (dev_priv->info->gen >= 6)
8151 gen6_rps_idle(dev->dev_private);
8154 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8155 struct intel_ring_buffer *ring)
8157 struct drm_device *dev = obj->base.dev;
8158 struct drm_crtc *crtc;
8160 if (!i915_powersave)
8163 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8167 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8170 intel_increase_pllclock(crtc);
8171 if (ring && intel_fbc_enabled(dev))
8172 ring->fbc_dirty = true;
8176 static void intel_crtc_destroy(struct drm_crtc *crtc)
8178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8179 struct drm_device *dev = crtc->dev;
8180 struct intel_unpin_work *work;
8181 unsigned long flags;
8183 spin_lock_irqsave(&dev->event_lock, flags);
8184 work = intel_crtc->unpin_work;
8185 intel_crtc->unpin_work = NULL;
8186 spin_unlock_irqrestore(&dev->event_lock, flags);
8189 cancel_work_sync(&work->work);
8193 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8195 drm_crtc_cleanup(crtc);
8200 static void intel_unpin_work_fn(struct work_struct *__work)
8202 struct intel_unpin_work *work =
8203 container_of(__work, struct intel_unpin_work, work);
8204 struct drm_device *dev = work->crtc->dev;
8206 mutex_lock(&dev->struct_mutex);
8207 intel_unpin_fb_obj(work->old_fb_obj);
8208 drm_gem_object_unreference(&work->pending_flip_obj->base);
8209 drm_gem_object_unreference(&work->old_fb_obj->base);
8211 intel_update_fbc(dev);
8212 mutex_unlock(&dev->struct_mutex);
8214 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8215 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8220 static void do_intel_finish_page_flip(struct drm_device *dev,
8221 struct drm_crtc *crtc)
8223 drm_i915_private_t *dev_priv = dev->dev_private;
8224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8225 struct intel_unpin_work *work;
8226 unsigned long flags;
8228 /* Ignore early vblank irqs */
8229 if (intel_crtc == NULL)
8232 spin_lock_irqsave(&dev->event_lock, flags);
8233 work = intel_crtc->unpin_work;
8235 /* Ensure we don't miss a work->pending update ... */
8238 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8239 spin_unlock_irqrestore(&dev->event_lock, flags);
8243 /* and that the unpin work is consistent wrt ->pending. */
8246 intel_crtc->unpin_work = NULL;
8249 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8251 drm_vblank_put(dev, intel_crtc->pipe);
8253 spin_unlock_irqrestore(&dev->event_lock, flags);
8255 wake_up_all(&dev_priv->pending_flip_queue);
8257 queue_work(dev_priv->wq, &work->work);
8259 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8262 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8264 drm_i915_private_t *dev_priv = dev->dev_private;
8265 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8267 do_intel_finish_page_flip(dev, crtc);
8270 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8272 drm_i915_private_t *dev_priv = dev->dev_private;
8273 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8275 do_intel_finish_page_flip(dev, crtc);
8278 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8280 drm_i915_private_t *dev_priv = dev->dev_private;
8281 struct intel_crtc *intel_crtc =
8282 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8283 unsigned long flags;
8285 /* NB: An MMIO update of the plane base pointer will also
8286 * generate a page-flip completion irq, i.e. every modeset
8287 * is also accompanied by a spurious intel_prepare_page_flip().
8289 spin_lock_irqsave(&dev->event_lock, flags);
8290 if (intel_crtc->unpin_work)
8291 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8292 spin_unlock_irqrestore(&dev->event_lock, flags);
8295 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8297 /* Ensure that the work item is consistent when activating it ... */
8299 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8300 /* and that it is marked active as soon as the irq could fire. */
8304 static int intel_gen2_queue_flip(struct drm_device *dev,
8305 struct drm_crtc *crtc,
8306 struct drm_framebuffer *fb,
8307 struct drm_i915_gem_object *obj,
8310 struct drm_i915_private *dev_priv = dev->dev_private;
8311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8313 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8316 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8320 ret = intel_ring_begin(ring, 6);
8324 /* Can't queue multiple flips, so wait for the previous
8325 * one to finish before executing the next.
8327 if (intel_crtc->plane)
8328 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8330 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8331 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8332 intel_ring_emit(ring, MI_NOOP);
8333 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8334 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8335 intel_ring_emit(ring, fb->pitches[0]);
8336 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8337 intel_ring_emit(ring, 0); /* aux display base address, unused */
8339 intel_mark_page_flip_active(intel_crtc);
8340 __intel_ring_advance(ring);
8344 intel_unpin_fb_obj(obj);
8349 static int intel_gen3_queue_flip(struct drm_device *dev,
8350 struct drm_crtc *crtc,
8351 struct drm_framebuffer *fb,
8352 struct drm_i915_gem_object *obj,
8355 struct drm_i915_private *dev_priv = dev->dev_private;
8356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8358 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8361 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8365 ret = intel_ring_begin(ring, 6);
8369 if (intel_crtc->plane)
8370 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8372 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8373 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8374 intel_ring_emit(ring, MI_NOOP);
8375 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8376 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8377 intel_ring_emit(ring, fb->pitches[0]);
8378 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8379 intel_ring_emit(ring, MI_NOOP);
8381 intel_mark_page_flip_active(intel_crtc);
8382 __intel_ring_advance(ring);
8386 intel_unpin_fb_obj(obj);
8391 static int intel_gen4_queue_flip(struct drm_device *dev,
8392 struct drm_crtc *crtc,
8393 struct drm_framebuffer *fb,
8394 struct drm_i915_gem_object *obj,
8397 struct drm_i915_private *dev_priv = dev->dev_private;
8398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8399 uint32_t pf, pipesrc;
8400 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8403 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8407 ret = intel_ring_begin(ring, 4);
8411 /* i965+ uses the linear or tiled offsets from the
8412 * Display Registers (which do not change across a page-flip)
8413 * so we need only reprogram the base address.
8415 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8416 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8417 intel_ring_emit(ring, fb->pitches[0]);
8418 intel_ring_emit(ring,
8419 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8422 /* XXX Enabling the panel-fitter across page-flip is so far
8423 * untested on non-native modes, so ignore it for now.
8424 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8427 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8428 intel_ring_emit(ring, pf | pipesrc);
8430 intel_mark_page_flip_active(intel_crtc);
8431 __intel_ring_advance(ring);
8435 intel_unpin_fb_obj(obj);
8440 static int intel_gen6_queue_flip(struct drm_device *dev,
8441 struct drm_crtc *crtc,
8442 struct drm_framebuffer *fb,
8443 struct drm_i915_gem_object *obj,
8446 struct drm_i915_private *dev_priv = dev->dev_private;
8447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8448 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8449 uint32_t pf, pipesrc;
8452 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8456 ret = intel_ring_begin(ring, 4);
8460 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8461 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8462 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8463 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8465 /* Contrary to the suggestions in the documentation,
8466 * "Enable Panel Fitter" does not seem to be required when page
8467 * flipping with a non-native mode, and worse causes a normal
8469 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8472 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8473 intel_ring_emit(ring, pf | pipesrc);
8475 intel_mark_page_flip_active(intel_crtc);
8476 __intel_ring_advance(ring);
8480 intel_unpin_fb_obj(obj);
8485 static int intel_gen7_queue_flip(struct drm_device *dev,
8486 struct drm_crtc *crtc,
8487 struct drm_framebuffer *fb,
8488 struct drm_i915_gem_object *obj,
8491 struct drm_i915_private *dev_priv = dev->dev_private;
8492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8493 struct intel_ring_buffer *ring;
8494 uint32_t plane_bit = 0;
8498 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8499 ring = &dev_priv->ring[BCS];
8501 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8505 switch(intel_crtc->plane) {
8507 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8510 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8513 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8516 WARN_ONCE(1, "unknown plane in flip command\n");
8522 if (ring->id == RCS)
8525 ret = intel_ring_begin(ring, len);
8529 /* Unmask the flip-done completion message. Note that the bspec says that
8530 * we should do this for both the BCS and RCS, and that we must not unmask
8531 * more than one flip event at any time (or ensure that one flip message
8532 * can be sent by waiting for flip-done prior to queueing new flips).
8533 * Experimentation says that BCS works despite DERRMR masking all
8534 * flip-done completion events and that unmasking all planes at once
8535 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8536 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8538 if (ring->id == RCS) {
8539 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8540 intel_ring_emit(ring, DERRMR);
8541 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8542 DERRMR_PIPEB_PRI_FLIP_DONE |
8543 DERRMR_PIPEC_PRI_FLIP_DONE));
8544 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8545 intel_ring_emit(ring, DERRMR);
8546 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8549 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8550 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8551 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8552 intel_ring_emit(ring, (MI_NOOP));
8554 intel_mark_page_flip_active(intel_crtc);
8555 __intel_ring_advance(ring);
8559 intel_unpin_fb_obj(obj);
8564 static int intel_default_queue_flip(struct drm_device *dev,
8565 struct drm_crtc *crtc,
8566 struct drm_framebuffer *fb,
8567 struct drm_i915_gem_object *obj,
8573 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8574 struct drm_framebuffer *fb,
8575 struct drm_pending_vblank_event *event,
8576 uint32_t page_flip_flags)
8578 struct drm_device *dev = crtc->dev;
8579 struct drm_i915_private *dev_priv = dev->dev_private;
8580 struct drm_framebuffer *old_fb = crtc->fb;
8581 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8583 struct intel_unpin_work *work;
8584 unsigned long flags;
8587 /* Can't change pixel format via MI display flips. */
8588 if (fb->pixel_format != crtc->fb->pixel_format)
8592 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8593 * Note that pitch changes could also affect these register.
8595 if (INTEL_INFO(dev)->gen > 3 &&
8596 (fb->offsets[0] != crtc->fb->offsets[0] ||
8597 fb->pitches[0] != crtc->fb->pitches[0]))
8600 work = kzalloc(sizeof(*work), GFP_KERNEL);
8604 work->event = event;
8606 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8607 INIT_WORK(&work->work, intel_unpin_work_fn);
8609 ret = drm_vblank_get(dev, intel_crtc->pipe);
8613 /* We borrow the event spin lock for protecting unpin_work */
8614 spin_lock_irqsave(&dev->event_lock, flags);
8615 if (intel_crtc->unpin_work) {
8616 spin_unlock_irqrestore(&dev->event_lock, flags);
8618 drm_vblank_put(dev, intel_crtc->pipe);
8620 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8623 intel_crtc->unpin_work = work;
8624 spin_unlock_irqrestore(&dev->event_lock, flags);
8626 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8627 flush_workqueue(dev_priv->wq);
8629 ret = i915_mutex_lock_interruptible(dev);
8633 /* Reference the objects for the scheduled work. */
8634 drm_gem_object_reference(&work->old_fb_obj->base);
8635 drm_gem_object_reference(&obj->base);
8639 work->pending_flip_obj = obj;
8641 work->enable_stall_check = true;
8643 atomic_inc(&intel_crtc->unpin_work_count);
8644 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8646 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8648 goto cleanup_pending;
8650 intel_disable_fbc(dev);
8651 intel_mark_fb_busy(obj, NULL);
8652 mutex_unlock(&dev->struct_mutex);
8654 trace_i915_flip_request(intel_crtc->plane, obj);
8659 atomic_dec(&intel_crtc->unpin_work_count);
8661 drm_gem_object_unreference(&work->old_fb_obj->base);
8662 drm_gem_object_unreference(&obj->base);
8663 mutex_unlock(&dev->struct_mutex);
8666 spin_lock_irqsave(&dev->event_lock, flags);
8667 intel_crtc->unpin_work = NULL;
8668 spin_unlock_irqrestore(&dev->event_lock, flags);
8670 drm_vblank_put(dev, intel_crtc->pipe);
8677 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8678 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8679 .load_lut = intel_crtc_load_lut,
8682 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8683 struct drm_crtc *crtc)
8685 struct drm_device *dev;
8686 struct drm_crtc *tmp;
8689 WARN(!crtc, "checking null crtc?\n");
8693 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8699 if (encoder->possible_crtcs & crtc_mask)
8705 * intel_modeset_update_staged_output_state
8707 * Updates the staged output configuration state, e.g. after we've read out the
8710 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8712 struct intel_encoder *encoder;
8713 struct intel_connector *connector;
8715 list_for_each_entry(connector, &dev->mode_config.connector_list,
8717 connector->new_encoder =
8718 to_intel_encoder(connector->base.encoder);
8721 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8724 to_intel_crtc(encoder->base.crtc);
8729 * intel_modeset_commit_output_state
8731 * This function copies the stage display pipe configuration to the real one.
8733 static void intel_modeset_commit_output_state(struct drm_device *dev)
8735 struct intel_encoder *encoder;
8736 struct intel_connector *connector;
8738 list_for_each_entry(connector, &dev->mode_config.connector_list,
8740 connector->base.encoder = &connector->new_encoder->base;
8743 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8745 encoder->base.crtc = &encoder->new_crtc->base;
8750 connected_sink_compute_bpp(struct intel_connector * connector,
8751 struct intel_crtc_config *pipe_config)
8753 int bpp = pipe_config->pipe_bpp;
8755 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8756 connector->base.base.id,
8757 drm_get_connector_name(&connector->base));
8759 /* Don't use an invalid EDID bpc value */
8760 if (connector->base.display_info.bpc &&
8761 connector->base.display_info.bpc * 3 < bpp) {
8762 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8763 bpp, connector->base.display_info.bpc*3);
8764 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8767 /* Clamp bpp to 8 on screens without EDID 1.4 */
8768 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8769 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8771 pipe_config->pipe_bpp = 24;
8776 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8777 struct drm_framebuffer *fb,
8778 struct intel_crtc_config *pipe_config)
8780 struct drm_device *dev = crtc->base.dev;
8781 struct intel_connector *connector;
8784 switch (fb->pixel_format) {
8786 bpp = 8*3; /* since we go through a colormap */
8788 case DRM_FORMAT_XRGB1555:
8789 case DRM_FORMAT_ARGB1555:
8790 /* checked in intel_framebuffer_init already */
8791 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8793 case DRM_FORMAT_RGB565:
8794 bpp = 6*3; /* min is 18bpp */
8796 case DRM_FORMAT_XBGR8888:
8797 case DRM_FORMAT_ABGR8888:
8798 /* checked in intel_framebuffer_init already */
8799 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8801 case DRM_FORMAT_XRGB8888:
8802 case DRM_FORMAT_ARGB8888:
8805 case DRM_FORMAT_XRGB2101010:
8806 case DRM_FORMAT_ARGB2101010:
8807 case DRM_FORMAT_XBGR2101010:
8808 case DRM_FORMAT_ABGR2101010:
8809 /* checked in intel_framebuffer_init already */
8810 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8814 /* TODO: gen4+ supports 16 bpc floating point, too. */
8816 DRM_DEBUG_KMS("unsupported depth\n");
8820 pipe_config->pipe_bpp = bpp;
8822 /* Clamp display bpp to EDID value */
8823 list_for_each_entry(connector, &dev->mode_config.connector_list,
8825 if (!connector->new_encoder ||
8826 connector->new_encoder->new_crtc != crtc)
8829 connected_sink_compute_bpp(connector, pipe_config);
8835 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8837 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8838 "type: 0x%x flags: 0x%x\n",
8840 mode->crtc_hdisplay, mode->crtc_hsync_start,
8841 mode->crtc_hsync_end, mode->crtc_htotal,
8842 mode->crtc_vdisplay, mode->crtc_vsync_start,
8843 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8846 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8847 struct intel_crtc_config *pipe_config,
8848 const char *context)
8850 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8851 context, pipe_name(crtc->pipe));
8853 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8854 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8855 pipe_config->pipe_bpp, pipe_config->dither);
8856 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8857 pipe_config->has_pch_encoder,
8858 pipe_config->fdi_lanes,
8859 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8860 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8861 pipe_config->fdi_m_n.tu);
8862 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8863 pipe_config->has_dp_encoder,
8864 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8865 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8866 pipe_config->dp_m_n.tu);
8867 DRM_DEBUG_KMS("requested mode:\n");
8868 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8869 DRM_DEBUG_KMS("adjusted mode:\n");
8870 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8871 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8872 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8873 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8874 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8875 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8876 pipe_config->gmch_pfit.control,
8877 pipe_config->gmch_pfit.pgm_ratios,
8878 pipe_config->gmch_pfit.lvds_border_bits);
8879 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8880 pipe_config->pch_pfit.pos,
8881 pipe_config->pch_pfit.size,
8882 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8883 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8884 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8887 static bool check_encoder_cloning(struct drm_crtc *crtc)
8889 int num_encoders = 0;
8890 bool uncloneable_encoders = false;
8891 struct intel_encoder *encoder;
8893 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8895 if (&encoder->new_crtc->base != crtc)
8899 if (!encoder->cloneable)
8900 uncloneable_encoders = true;
8903 return !(num_encoders > 1 && uncloneable_encoders);
8906 static struct intel_crtc_config *
8907 intel_modeset_pipe_config(struct drm_crtc *crtc,
8908 struct drm_framebuffer *fb,
8909 struct drm_display_mode *mode)
8911 struct drm_device *dev = crtc->dev;
8912 struct intel_encoder *encoder;
8913 struct intel_crtc_config *pipe_config;
8914 int plane_bpp, ret = -EINVAL;
8917 if (!check_encoder_cloning(crtc)) {
8918 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8919 return ERR_PTR(-EINVAL);
8922 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8924 return ERR_PTR(-ENOMEM);
8926 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8927 drm_mode_copy(&pipe_config->requested_mode, mode);
8929 pipe_config->cpu_transcoder =
8930 (enum transcoder) to_intel_crtc(crtc)->pipe;
8931 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8934 * Sanitize sync polarity flags based on requested ones. If neither
8935 * positive or negative polarity is requested, treat this as meaning
8936 * negative polarity.
8938 if (!(pipe_config->adjusted_mode.flags &
8939 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8940 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8942 if (!(pipe_config->adjusted_mode.flags &
8943 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8944 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8946 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8947 * plane pixel format and any sink constraints into account. Returns the
8948 * source plane bpp so that dithering can be selected on mismatches
8949 * after encoders and crtc also have had their say. */
8950 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8956 * Determine the real pipe dimensions. Note that stereo modes can
8957 * increase the actual pipe size due to the frame doubling and
8958 * insertion of additional space for blanks between the frame. This
8959 * is stored in the crtc timings. We use the requested mode to do this
8960 * computation to clearly distinguish it from the adjusted mode, which
8961 * can be changed by the connectors in the below retry loop.
8963 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8964 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8965 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8968 /* Ensure the port clock defaults are reset when retrying. */
8969 pipe_config->port_clock = 0;
8970 pipe_config->pixel_multiplier = 1;
8972 /* Fill in default crtc timings, allow encoders to overwrite them. */
8973 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8975 /* Pass our mode to the connectors and the CRTC to give them a chance to
8976 * adjust it according to limitations or connector properties, and also
8977 * a chance to reject the mode entirely.
8979 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8982 if (&encoder->new_crtc->base != crtc)
8985 if (!(encoder->compute_config(encoder, pipe_config))) {
8986 DRM_DEBUG_KMS("Encoder config failure\n");
8991 /* Set default port clock if not overwritten by the encoder. Needs to be
8992 * done afterwards in case the encoder adjusts the mode. */
8993 if (!pipe_config->port_clock)
8994 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8995 * pipe_config->pixel_multiplier;
8997 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8999 DRM_DEBUG_KMS("CRTC fixup failed\n");
9004 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9009 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9014 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9015 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9016 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9021 return ERR_PTR(ret);
9024 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9025 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9027 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9028 unsigned *prepare_pipes, unsigned *disable_pipes)
9030 struct intel_crtc *intel_crtc;
9031 struct drm_device *dev = crtc->dev;
9032 struct intel_encoder *encoder;
9033 struct intel_connector *connector;
9034 struct drm_crtc *tmp_crtc;
9036 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9038 /* Check which crtcs have changed outputs connected to them, these need
9039 * to be part of the prepare_pipes mask. We don't (yet) support global
9040 * modeset across multiple crtcs, so modeset_pipes will only have one
9041 * bit set at most. */
9042 list_for_each_entry(connector, &dev->mode_config.connector_list,
9044 if (connector->base.encoder == &connector->new_encoder->base)
9047 if (connector->base.encoder) {
9048 tmp_crtc = connector->base.encoder->crtc;
9050 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9053 if (connector->new_encoder)
9055 1 << connector->new_encoder->new_crtc->pipe;
9058 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9060 if (encoder->base.crtc == &encoder->new_crtc->base)
9063 if (encoder->base.crtc) {
9064 tmp_crtc = encoder->base.crtc;
9066 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9069 if (encoder->new_crtc)
9070 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9073 /* Check for any pipes that will be fully disabled ... */
9074 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9078 /* Don't try to disable disabled crtcs. */
9079 if (!intel_crtc->base.enabled)
9082 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9084 if (encoder->new_crtc == intel_crtc)
9089 *disable_pipes |= 1 << intel_crtc->pipe;
9093 /* set_mode is also used to update properties on life display pipes. */
9094 intel_crtc = to_intel_crtc(crtc);
9096 *prepare_pipes |= 1 << intel_crtc->pipe;
9099 * For simplicity do a full modeset on any pipe where the output routing
9100 * changed. We could be more clever, but that would require us to be
9101 * more careful with calling the relevant encoder->mode_set functions.
9104 *modeset_pipes = *prepare_pipes;
9106 /* ... and mask these out. */
9107 *modeset_pipes &= ~(*disable_pipes);
9108 *prepare_pipes &= ~(*disable_pipes);
9111 * HACK: We don't (yet) fully support global modesets. intel_set_config
9112 * obies this rule, but the modeset restore mode of
9113 * intel_modeset_setup_hw_state does not.
9115 *modeset_pipes &= 1 << intel_crtc->pipe;
9116 *prepare_pipes &= 1 << intel_crtc->pipe;
9118 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9119 *modeset_pipes, *prepare_pipes, *disable_pipes);
9122 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9124 struct drm_encoder *encoder;
9125 struct drm_device *dev = crtc->dev;
9127 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9128 if (encoder->crtc == crtc)
9135 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9137 struct intel_encoder *intel_encoder;
9138 struct intel_crtc *intel_crtc;
9139 struct drm_connector *connector;
9141 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9143 if (!intel_encoder->base.crtc)
9146 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9148 if (prepare_pipes & (1 << intel_crtc->pipe))
9149 intel_encoder->connectors_active = false;
9152 intel_modeset_commit_output_state(dev);
9154 /* Update computed state. */
9155 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9157 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9160 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9161 if (!connector->encoder || !connector->encoder->crtc)
9164 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9166 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9167 struct drm_property *dpms_property =
9168 dev->mode_config.dpms_property;
9170 connector->dpms = DRM_MODE_DPMS_ON;
9171 drm_object_property_set_value(&connector->base,
9175 intel_encoder = to_intel_encoder(connector->encoder);
9176 intel_encoder->connectors_active = true;
9182 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9186 if (clock1 == clock2)
9189 if (!clock1 || !clock2)
9192 diff = abs(clock1 - clock2);
9194 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9200 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9201 list_for_each_entry((intel_crtc), \
9202 &(dev)->mode_config.crtc_list, \
9204 if (mask & (1 <<(intel_crtc)->pipe))
9207 intel_pipe_config_compare(struct drm_device *dev,
9208 struct intel_crtc_config *current_config,
9209 struct intel_crtc_config *pipe_config)
9211 #define PIPE_CONF_CHECK_X(name) \
9212 if (current_config->name != pipe_config->name) { \
9213 DRM_ERROR("mismatch in " #name " " \
9214 "(expected 0x%08x, found 0x%08x)\n", \
9215 current_config->name, \
9216 pipe_config->name); \
9220 #define PIPE_CONF_CHECK_I(name) \
9221 if (current_config->name != pipe_config->name) { \
9222 DRM_ERROR("mismatch in " #name " " \
9223 "(expected %i, found %i)\n", \
9224 current_config->name, \
9225 pipe_config->name); \
9229 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9230 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9231 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9232 "(expected %i, found %i)\n", \
9233 current_config->name & (mask), \
9234 pipe_config->name & (mask)); \
9238 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9239 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9240 DRM_ERROR("mismatch in " #name " " \
9241 "(expected %i, found %i)\n", \
9242 current_config->name, \
9243 pipe_config->name); \
9247 #define PIPE_CONF_QUIRK(quirk) \
9248 ((current_config->quirks | pipe_config->quirks) & (quirk))
9250 PIPE_CONF_CHECK_I(cpu_transcoder);
9252 PIPE_CONF_CHECK_I(has_pch_encoder);
9253 PIPE_CONF_CHECK_I(fdi_lanes);
9254 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9255 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9256 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9257 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9258 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9260 PIPE_CONF_CHECK_I(has_dp_encoder);
9261 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9262 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9263 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9264 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9265 PIPE_CONF_CHECK_I(dp_m_n.tu);
9267 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9268 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9269 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9270 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9271 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9272 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9274 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9275 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9276 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9277 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9278 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9279 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9281 PIPE_CONF_CHECK_I(pixel_multiplier);
9283 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9284 DRM_MODE_FLAG_INTERLACE);
9286 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9287 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9288 DRM_MODE_FLAG_PHSYNC);
9289 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9290 DRM_MODE_FLAG_NHSYNC);
9291 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9292 DRM_MODE_FLAG_PVSYNC);
9293 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9294 DRM_MODE_FLAG_NVSYNC);
9297 PIPE_CONF_CHECK_I(pipe_src_w);
9298 PIPE_CONF_CHECK_I(pipe_src_h);
9300 PIPE_CONF_CHECK_I(gmch_pfit.control);
9301 /* pfit ratios are autocomputed by the hw on gen4+ */
9302 if (INTEL_INFO(dev)->gen < 4)
9303 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9304 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9305 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9306 if (current_config->pch_pfit.enabled) {
9307 PIPE_CONF_CHECK_I(pch_pfit.pos);
9308 PIPE_CONF_CHECK_I(pch_pfit.size);
9311 PIPE_CONF_CHECK_I(ips_enabled);
9313 PIPE_CONF_CHECK_I(double_wide);
9315 PIPE_CONF_CHECK_I(shared_dpll);
9316 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9317 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9318 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9319 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9321 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9322 PIPE_CONF_CHECK_I(pipe_bpp);
9324 if (!IS_HASWELL(dev)) {
9325 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9326 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9329 #undef PIPE_CONF_CHECK_X
9330 #undef PIPE_CONF_CHECK_I
9331 #undef PIPE_CONF_CHECK_FLAGS
9332 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9333 #undef PIPE_CONF_QUIRK
9339 check_connector_state(struct drm_device *dev)
9341 struct intel_connector *connector;
9343 list_for_each_entry(connector, &dev->mode_config.connector_list,
9345 /* This also checks the encoder/connector hw state with the
9346 * ->get_hw_state callbacks. */
9347 intel_connector_check_state(connector);
9349 WARN(&connector->new_encoder->base != connector->base.encoder,
9350 "connector's staged encoder doesn't match current encoder\n");
9355 check_encoder_state(struct drm_device *dev)
9357 struct intel_encoder *encoder;
9358 struct intel_connector *connector;
9360 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9362 bool enabled = false;
9363 bool active = false;
9364 enum pipe pipe, tracked_pipe;
9366 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9367 encoder->base.base.id,
9368 drm_get_encoder_name(&encoder->base));
9370 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9371 "encoder's stage crtc doesn't match current crtc\n");
9372 WARN(encoder->connectors_active && !encoder->base.crtc,
9373 "encoder's active_connectors set, but no crtc\n");
9375 list_for_each_entry(connector, &dev->mode_config.connector_list,
9377 if (connector->base.encoder != &encoder->base)
9380 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9383 WARN(!!encoder->base.crtc != enabled,
9384 "encoder's enabled state mismatch "
9385 "(expected %i, found %i)\n",
9386 !!encoder->base.crtc, enabled);
9387 WARN(active && !encoder->base.crtc,
9388 "active encoder with no crtc\n");
9390 WARN(encoder->connectors_active != active,
9391 "encoder's computed active state doesn't match tracked active state "
9392 "(expected %i, found %i)\n", active, encoder->connectors_active);
9394 active = encoder->get_hw_state(encoder, &pipe);
9395 WARN(active != encoder->connectors_active,
9396 "encoder's hw state doesn't match sw tracking "
9397 "(expected %i, found %i)\n",
9398 encoder->connectors_active, active);
9400 if (!encoder->base.crtc)
9403 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9404 WARN(active && pipe != tracked_pipe,
9405 "active encoder's pipe doesn't match"
9406 "(expected %i, found %i)\n",
9407 tracked_pipe, pipe);
9413 check_crtc_state(struct drm_device *dev)
9415 drm_i915_private_t *dev_priv = dev->dev_private;
9416 struct intel_crtc *crtc;
9417 struct intel_encoder *encoder;
9418 struct intel_crtc_config pipe_config;
9420 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9422 bool enabled = false;
9423 bool active = false;
9425 memset(&pipe_config, 0, sizeof(pipe_config));
9427 DRM_DEBUG_KMS("[CRTC:%d]\n",
9428 crtc->base.base.id);
9430 WARN(crtc->active && !crtc->base.enabled,
9431 "active crtc, but not enabled in sw tracking\n");
9433 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9435 if (encoder->base.crtc != &crtc->base)
9438 if (encoder->connectors_active)
9442 WARN(active != crtc->active,
9443 "crtc's computed active state doesn't match tracked active state "
9444 "(expected %i, found %i)\n", active, crtc->active);
9445 WARN(enabled != crtc->base.enabled,
9446 "crtc's computed enabled state doesn't match tracked enabled state "
9447 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9449 active = dev_priv->display.get_pipe_config(crtc,
9452 /* hw state is inconsistent with the pipe A quirk */
9453 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9454 active = crtc->active;
9456 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9459 if (encoder->base.crtc != &crtc->base)
9461 if (encoder->get_hw_state(encoder, &pipe))
9462 encoder->get_config(encoder, &pipe_config);
9465 WARN(crtc->active != active,
9466 "crtc active state doesn't match with hw state "
9467 "(expected %i, found %i)\n", crtc->active, active);
9470 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9471 WARN(1, "pipe state doesn't match!\n");
9472 intel_dump_pipe_config(crtc, &pipe_config,
9474 intel_dump_pipe_config(crtc, &crtc->config,
9481 check_shared_dpll_state(struct drm_device *dev)
9483 drm_i915_private_t *dev_priv = dev->dev_private;
9484 struct intel_crtc *crtc;
9485 struct intel_dpll_hw_state dpll_hw_state;
9488 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9489 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9490 int enabled_crtcs = 0, active_crtcs = 0;
9493 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9495 DRM_DEBUG_KMS("%s\n", pll->name);
9497 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9499 WARN(pll->active > pll->refcount,
9500 "more active pll users than references: %i vs %i\n",
9501 pll->active, pll->refcount);
9502 WARN(pll->active && !pll->on,
9503 "pll in active use but not on in sw tracking\n");
9504 WARN(pll->on && !pll->active,
9505 "pll in on but not on in use in sw tracking\n");
9506 WARN(pll->on != active,
9507 "pll on state mismatch (expected %i, found %i)\n",
9510 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9512 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9514 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9517 WARN(pll->active != active_crtcs,
9518 "pll active crtcs mismatch (expected %i, found %i)\n",
9519 pll->active, active_crtcs);
9520 WARN(pll->refcount != enabled_crtcs,
9521 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9522 pll->refcount, enabled_crtcs);
9524 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9525 sizeof(dpll_hw_state)),
9526 "pll hw state mismatch\n");
9531 intel_modeset_check_state(struct drm_device *dev)
9533 check_connector_state(dev);
9534 check_encoder_state(dev);
9535 check_crtc_state(dev);
9536 check_shared_dpll_state(dev);
9539 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9543 * FDI already provided one idea for the dotclock.
9544 * Yell if the encoder disagrees.
9546 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9547 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9548 pipe_config->adjusted_mode.crtc_clock, dotclock);
9551 static int __intel_set_mode(struct drm_crtc *crtc,
9552 struct drm_display_mode *mode,
9553 int x, int y, struct drm_framebuffer *fb)
9555 struct drm_device *dev = crtc->dev;
9556 drm_i915_private_t *dev_priv = dev->dev_private;
9557 struct drm_display_mode *saved_mode, *saved_hwmode;
9558 struct intel_crtc_config *pipe_config = NULL;
9559 struct intel_crtc *intel_crtc;
9560 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9563 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9566 saved_hwmode = saved_mode + 1;
9568 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9569 &prepare_pipes, &disable_pipes);
9571 *saved_hwmode = crtc->hwmode;
9572 *saved_mode = crtc->mode;
9574 /* Hack: Because we don't (yet) support global modeset on multiple
9575 * crtcs, we don't keep track of the new mode for more than one crtc.
9576 * Hence simply check whether any bit is set in modeset_pipes in all the
9577 * pieces of code that are not yet converted to deal with mutliple crtcs
9578 * changing their mode at the same time. */
9579 if (modeset_pipes) {
9580 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9581 if (IS_ERR(pipe_config)) {
9582 ret = PTR_ERR(pipe_config);
9587 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9592 * See if the config requires any additional preparation, e.g.
9593 * to adjust global state with pipes off. We need to do this
9594 * here so we can get the modeset_pipe updated config for the new
9595 * mode set on this crtc. For other crtcs we need to use the
9596 * adjusted_mode bits in the crtc directly.
9598 if (IS_VALLEYVIEW(dev)) {
9599 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9600 modeset_pipes, pipe_config);
9602 /* may have added more to prepare_pipes than we should */
9603 prepare_pipes &= ~disable_pipes;
9606 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9607 intel_crtc_disable(&intel_crtc->base);
9609 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9610 if (intel_crtc->base.enabled)
9611 dev_priv->display.crtc_disable(&intel_crtc->base);
9614 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9615 * to set it here already despite that we pass it down the callchain.
9617 if (modeset_pipes) {
9619 /* mode_set/enable/disable functions rely on a correct pipe
9621 to_intel_crtc(crtc)->config = *pipe_config;
9624 /* Only after disabling all output pipelines that will be changed can we
9625 * update the the output configuration. */
9626 intel_modeset_update_state(dev, prepare_pipes);
9628 if (dev_priv->display.modeset_global_resources)
9629 dev_priv->display.modeset_global_resources(dev);
9631 /* Set up the DPLL and any encoders state that needs to adjust or depend
9634 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9635 ret = intel_crtc_mode_set(&intel_crtc->base,
9641 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9642 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9643 dev_priv->display.crtc_enable(&intel_crtc->base);
9645 if (modeset_pipes) {
9646 /* Store real post-adjustment hardware mode. */
9647 crtc->hwmode = pipe_config->adjusted_mode;
9649 /* Calculate and store various constants which
9650 * are later needed by vblank and swap-completion
9651 * timestamping. They are derived from true hwmode.
9653 drm_calc_timestamping_constants(crtc);
9656 /* FIXME: add subpixel order */
9658 if (ret && crtc->enabled) {
9659 crtc->hwmode = *saved_hwmode;
9660 crtc->mode = *saved_mode;
9669 static int intel_set_mode(struct drm_crtc *crtc,
9670 struct drm_display_mode *mode,
9671 int x, int y, struct drm_framebuffer *fb)
9675 ret = __intel_set_mode(crtc, mode, x, y, fb);
9678 intel_modeset_check_state(crtc->dev);
9683 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9685 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9688 #undef for_each_intel_crtc_masked
9690 static void intel_set_config_free(struct intel_set_config *config)
9695 kfree(config->save_connector_encoders);
9696 kfree(config->save_encoder_crtcs);
9700 static int intel_set_config_save_state(struct drm_device *dev,
9701 struct intel_set_config *config)
9703 struct drm_encoder *encoder;
9704 struct drm_connector *connector;
9707 config->save_encoder_crtcs =
9708 kcalloc(dev->mode_config.num_encoder,
9709 sizeof(struct drm_crtc *), GFP_KERNEL);
9710 if (!config->save_encoder_crtcs)
9713 config->save_connector_encoders =
9714 kcalloc(dev->mode_config.num_connector,
9715 sizeof(struct drm_encoder *), GFP_KERNEL);
9716 if (!config->save_connector_encoders)
9719 /* Copy data. Note that driver private data is not affected.
9720 * Should anything bad happen only the expected state is
9721 * restored, not the drivers personal bookkeeping.
9724 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9725 config->save_encoder_crtcs[count++] = encoder->crtc;
9729 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9730 config->save_connector_encoders[count++] = connector->encoder;
9736 static void intel_set_config_restore_state(struct drm_device *dev,
9737 struct intel_set_config *config)
9739 struct intel_encoder *encoder;
9740 struct intel_connector *connector;
9744 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9746 to_intel_crtc(config->save_encoder_crtcs[count++]);
9750 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9751 connector->new_encoder =
9752 to_intel_encoder(config->save_connector_encoders[count++]);
9757 is_crtc_connector_off(struct drm_mode_set *set)
9761 if (set->num_connectors == 0)
9764 if (WARN_ON(set->connectors == NULL))
9767 for (i = 0; i < set->num_connectors; i++)
9768 if (set->connectors[i]->encoder &&
9769 set->connectors[i]->encoder->crtc == set->crtc &&
9770 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9777 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9778 struct intel_set_config *config)
9781 /* We should be able to check here if the fb has the same properties
9782 * and then just flip_or_move it */
9783 if (is_crtc_connector_off(set)) {
9784 config->mode_changed = true;
9785 } else if (set->crtc->fb != set->fb) {
9786 /* If we have no fb then treat it as a full mode set */
9787 if (set->crtc->fb == NULL) {
9788 struct intel_crtc *intel_crtc =
9789 to_intel_crtc(set->crtc);
9791 if (intel_crtc->active && i915_fastboot) {
9792 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9793 config->fb_changed = true;
9795 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9796 config->mode_changed = true;
9798 } else if (set->fb == NULL) {
9799 config->mode_changed = true;
9800 } else if (set->fb->pixel_format !=
9801 set->crtc->fb->pixel_format) {
9802 config->mode_changed = true;
9804 config->fb_changed = true;
9808 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9809 config->fb_changed = true;
9811 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9812 DRM_DEBUG_KMS("modes are different, full mode set\n");
9813 drm_mode_debug_printmodeline(&set->crtc->mode);
9814 drm_mode_debug_printmodeline(set->mode);
9815 config->mode_changed = true;
9818 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9819 set->crtc->base.id, config->mode_changed, config->fb_changed);
9823 intel_modeset_stage_output_state(struct drm_device *dev,
9824 struct drm_mode_set *set,
9825 struct intel_set_config *config)
9827 struct drm_crtc *new_crtc;
9828 struct intel_connector *connector;
9829 struct intel_encoder *encoder;
9832 /* The upper layers ensure that we either disable a crtc or have a list
9833 * of connectors. For paranoia, double-check this. */
9834 WARN_ON(!set->fb && (set->num_connectors != 0));
9835 WARN_ON(set->fb && (set->num_connectors == 0));
9837 list_for_each_entry(connector, &dev->mode_config.connector_list,
9839 /* Otherwise traverse passed in connector list and get encoders
9841 for (ro = 0; ro < set->num_connectors; ro++) {
9842 if (set->connectors[ro] == &connector->base) {
9843 connector->new_encoder = connector->encoder;
9848 /* If we disable the crtc, disable all its connectors. Also, if
9849 * the connector is on the changing crtc but not on the new
9850 * connector list, disable it. */
9851 if ((!set->fb || ro == set->num_connectors) &&
9852 connector->base.encoder &&
9853 connector->base.encoder->crtc == set->crtc) {
9854 connector->new_encoder = NULL;
9856 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9857 connector->base.base.id,
9858 drm_get_connector_name(&connector->base));
9862 if (&connector->new_encoder->base != connector->base.encoder) {
9863 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9864 config->mode_changed = true;
9867 /* connector->new_encoder is now updated for all connectors. */
9869 /* Update crtc of enabled connectors. */
9870 list_for_each_entry(connector, &dev->mode_config.connector_list,
9872 if (!connector->new_encoder)
9875 new_crtc = connector->new_encoder->base.crtc;
9877 for (ro = 0; ro < set->num_connectors; ro++) {
9878 if (set->connectors[ro] == &connector->base)
9879 new_crtc = set->crtc;
9882 /* Make sure the new CRTC will work with the encoder */
9883 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9887 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9889 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9890 connector->base.base.id,
9891 drm_get_connector_name(&connector->base),
9895 /* Check for any encoders that needs to be disabled. */
9896 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9898 list_for_each_entry(connector,
9899 &dev->mode_config.connector_list,
9901 if (connector->new_encoder == encoder) {
9902 WARN_ON(!connector->new_encoder->new_crtc);
9907 encoder->new_crtc = NULL;
9909 /* Only now check for crtc changes so we don't miss encoders
9910 * that will be disabled. */
9911 if (&encoder->new_crtc->base != encoder->base.crtc) {
9912 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9913 config->mode_changed = true;
9916 /* Now we've also updated encoder->new_crtc for all encoders. */
9921 static int intel_crtc_set_config(struct drm_mode_set *set)
9923 struct drm_device *dev;
9924 struct drm_mode_set save_set;
9925 struct intel_set_config *config;
9930 BUG_ON(!set->crtc->helper_private);
9932 /* Enforce sane interface api - has been abused by the fb helper. */
9933 BUG_ON(!set->mode && set->fb);
9934 BUG_ON(set->fb && set->num_connectors == 0);
9937 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9938 set->crtc->base.id, set->fb->base.id,
9939 (int)set->num_connectors, set->x, set->y);
9941 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9944 dev = set->crtc->dev;
9947 config = kzalloc(sizeof(*config), GFP_KERNEL);
9951 ret = intel_set_config_save_state(dev, config);
9955 save_set.crtc = set->crtc;
9956 save_set.mode = &set->crtc->mode;
9957 save_set.x = set->crtc->x;
9958 save_set.y = set->crtc->y;
9959 save_set.fb = set->crtc->fb;
9961 /* Compute whether we need a full modeset, only an fb base update or no
9962 * change at all. In the future we might also check whether only the
9963 * mode changed, e.g. for LVDS where we only change the panel fitter in
9965 intel_set_config_compute_mode_changes(set, config);
9967 ret = intel_modeset_stage_output_state(dev, set, config);
9971 if (config->mode_changed) {
9972 ret = intel_set_mode(set->crtc, set->mode,
9973 set->x, set->y, set->fb);
9974 } else if (config->fb_changed) {
9975 intel_crtc_wait_for_pending_flips(set->crtc);
9977 ret = intel_pipe_set_base(set->crtc,
9978 set->x, set->y, set->fb);
9982 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9983 set->crtc->base.id, ret);
9985 intel_set_config_restore_state(dev, config);
9987 /* Try to restore the config */
9988 if (config->mode_changed &&
9989 intel_set_mode(save_set.crtc, save_set.mode,
9990 save_set.x, save_set.y, save_set.fb))
9991 DRM_ERROR("failed to restore config after modeset failure\n");
9995 intel_set_config_free(config);
9999 static const struct drm_crtc_funcs intel_crtc_funcs = {
10000 .cursor_set = intel_crtc_cursor_set,
10001 .cursor_move = intel_crtc_cursor_move,
10002 .gamma_set = intel_crtc_gamma_set,
10003 .set_config = intel_crtc_set_config,
10004 .destroy = intel_crtc_destroy,
10005 .page_flip = intel_crtc_page_flip,
10008 static void intel_cpu_pll_init(struct drm_device *dev)
10011 intel_ddi_pll_init(dev);
10014 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10015 struct intel_shared_dpll *pll,
10016 struct intel_dpll_hw_state *hw_state)
10020 val = I915_READ(PCH_DPLL(pll->id));
10021 hw_state->dpll = val;
10022 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10023 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10025 return val & DPLL_VCO_ENABLE;
10028 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10029 struct intel_shared_dpll *pll)
10031 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10032 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10035 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10036 struct intel_shared_dpll *pll)
10038 /* PCH refclock must be enabled first */
10039 assert_pch_refclk_enabled(dev_priv);
10041 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10043 /* Wait for the clocks to stabilize. */
10044 POSTING_READ(PCH_DPLL(pll->id));
10047 /* The pixel multiplier can only be updated once the
10048 * DPLL is enabled and the clocks are stable.
10050 * So write it again.
10052 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10053 POSTING_READ(PCH_DPLL(pll->id));
10057 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10058 struct intel_shared_dpll *pll)
10060 struct drm_device *dev = dev_priv->dev;
10061 struct intel_crtc *crtc;
10063 /* Make sure no transcoder isn't still depending on us. */
10064 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10065 if (intel_crtc_to_shared_dpll(crtc) == pll)
10066 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10069 I915_WRITE(PCH_DPLL(pll->id), 0);
10070 POSTING_READ(PCH_DPLL(pll->id));
10074 static char *ibx_pch_dpll_names[] = {
10079 static void ibx_pch_dpll_init(struct drm_device *dev)
10081 struct drm_i915_private *dev_priv = dev->dev_private;
10084 dev_priv->num_shared_dpll = 2;
10086 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10087 dev_priv->shared_dplls[i].id = i;
10088 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10089 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10090 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10091 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10092 dev_priv->shared_dplls[i].get_hw_state =
10093 ibx_pch_dpll_get_hw_state;
10097 static void intel_shared_dpll_init(struct drm_device *dev)
10099 struct drm_i915_private *dev_priv = dev->dev_private;
10101 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10102 ibx_pch_dpll_init(dev);
10104 dev_priv->num_shared_dpll = 0;
10106 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10107 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
10108 dev_priv->num_shared_dpll);
10111 static void intel_crtc_init(struct drm_device *dev, int pipe)
10113 drm_i915_private_t *dev_priv = dev->dev_private;
10114 struct intel_crtc *intel_crtc;
10117 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10118 if (intel_crtc == NULL)
10121 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10123 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10124 for (i = 0; i < 256; i++) {
10125 intel_crtc->lut_r[i] = i;
10126 intel_crtc->lut_g[i] = i;
10127 intel_crtc->lut_b[i] = i;
10131 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10132 * is hooked to plane B. Hence we want plane A feeding pipe B.
10134 intel_crtc->pipe = pipe;
10135 intel_crtc->plane = pipe;
10136 if (IS_MOBILE(dev) && INTEL_INFO(dev)->gen < 4) {
10137 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10138 intel_crtc->plane = !pipe;
10141 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10142 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10143 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10144 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10146 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10149 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10151 struct drm_encoder *encoder = connector->base.encoder;
10153 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10156 return INVALID_PIPE;
10158 return to_intel_crtc(encoder->crtc)->pipe;
10161 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10162 struct drm_file *file)
10164 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10165 struct drm_mode_object *drmmode_obj;
10166 struct intel_crtc *crtc;
10168 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10171 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10172 DRM_MODE_OBJECT_CRTC);
10174 if (!drmmode_obj) {
10175 DRM_ERROR("no such CRTC id\n");
10179 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10180 pipe_from_crtc_id->pipe = crtc->pipe;
10185 static int intel_encoder_clones(struct intel_encoder *encoder)
10187 struct drm_device *dev = encoder->base.dev;
10188 struct intel_encoder *source_encoder;
10189 int index_mask = 0;
10192 list_for_each_entry(source_encoder,
10193 &dev->mode_config.encoder_list, base.head) {
10195 if (encoder == source_encoder)
10196 index_mask |= (1 << entry);
10198 /* Intel hw has only one MUX where enocoders could be cloned. */
10199 if (encoder->cloneable && source_encoder->cloneable)
10200 index_mask |= (1 << entry);
10208 static bool has_edp_a(struct drm_device *dev)
10210 struct drm_i915_private *dev_priv = dev->dev_private;
10212 if (!IS_MOBILE(dev))
10215 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10218 if (IS_GEN5(dev) &&
10219 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10225 static void intel_setup_outputs(struct drm_device *dev)
10227 struct drm_i915_private *dev_priv = dev->dev_private;
10228 struct intel_encoder *encoder;
10229 bool dpd_is_edp = false;
10231 intel_lvds_init(dev);
10234 intel_crt_init(dev);
10236 if (HAS_DDI(dev)) {
10239 /* Haswell uses DDI functions to detect digital outputs */
10240 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10241 /* DDI A only supports eDP */
10243 intel_ddi_init(dev, PORT_A);
10245 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10247 found = I915_READ(SFUSE_STRAP);
10249 if (found & SFUSE_STRAP_DDIB_DETECTED)
10250 intel_ddi_init(dev, PORT_B);
10251 if (found & SFUSE_STRAP_DDIC_DETECTED)
10252 intel_ddi_init(dev, PORT_C);
10253 if (found & SFUSE_STRAP_DDID_DETECTED)
10254 intel_ddi_init(dev, PORT_D);
10255 } else if (HAS_PCH_SPLIT(dev)) {
10257 dpd_is_edp = intel_dpd_is_edp(dev);
10259 if (has_edp_a(dev))
10260 intel_dp_init(dev, DP_A, PORT_A);
10262 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10263 /* PCH SDVOB multiplex with HDMIB */
10264 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10266 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10267 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10268 intel_dp_init(dev, PCH_DP_B, PORT_B);
10271 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10272 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10274 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10275 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10277 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10278 intel_dp_init(dev, PCH_DP_C, PORT_C);
10280 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10281 intel_dp_init(dev, PCH_DP_D, PORT_D);
10282 } else if (IS_VALLEYVIEW(dev)) {
10283 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10284 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10286 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10287 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10290 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10291 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10293 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10294 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10298 intel_dsi_init(dev);
10299 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10300 bool found = false;
10302 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10303 DRM_DEBUG_KMS("probing SDVOB\n");
10304 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10305 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10306 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10307 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10310 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10311 intel_dp_init(dev, DP_B, PORT_B);
10314 /* Before G4X SDVOC doesn't have its own detect register */
10316 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10317 DRM_DEBUG_KMS("probing SDVOC\n");
10318 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10321 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10323 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10324 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10325 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10327 if (SUPPORTS_INTEGRATED_DP(dev))
10328 intel_dp_init(dev, DP_C, PORT_C);
10331 if (SUPPORTS_INTEGRATED_DP(dev) &&
10332 (I915_READ(DP_D) & DP_DETECTED))
10333 intel_dp_init(dev, DP_D, PORT_D);
10334 } else if (IS_GEN2(dev))
10335 intel_dvo_init(dev);
10337 if (SUPPORTS_TV(dev))
10338 intel_tv_init(dev);
10340 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10341 encoder->base.possible_crtcs = encoder->crtc_mask;
10342 encoder->base.possible_clones =
10343 intel_encoder_clones(encoder);
10346 intel_init_pch_refclk(dev);
10348 drm_helper_move_panel_connectors_to_head(dev);
10351 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10353 drm_framebuffer_cleanup(&fb->base);
10354 WARN_ON(!fb->obj->framebuffer_references--);
10355 drm_gem_object_unreference_unlocked(&fb->obj->base);
10358 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10360 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10362 intel_framebuffer_fini(intel_fb);
10366 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10367 struct drm_file *file,
10368 unsigned int *handle)
10370 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10371 struct drm_i915_gem_object *obj = intel_fb->obj;
10373 return drm_gem_handle_create(file, &obj->base, handle);
10376 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10377 .destroy = intel_user_framebuffer_destroy,
10378 .create_handle = intel_user_framebuffer_create_handle,
10381 int intel_framebuffer_init(struct drm_device *dev,
10382 struct intel_framebuffer *intel_fb,
10383 struct drm_mode_fb_cmd2 *mode_cmd,
10384 struct drm_i915_gem_object *obj)
10386 int aligned_height, tile_height;
10390 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10392 if (obj->tiling_mode == I915_TILING_Y) {
10393 DRM_DEBUG("hardware does not support tiling Y\n");
10397 if (mode_cmd->pitches[0] & 63) {
10398 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10399 mode_cmd->pitches[0]);
10403 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10404 pitch_limit = 32*1024;
10405 } else if (INTEL_INFO(dev)->gen >= 4) {
10406 if (obj->tiling_mode)
10407 pitch_limit = 16*1024;
10409 pitch_limit = 32*1024;
10410 } else if (INTEL_INFO(dev)->gen >= 3) {
10411 if (obj->tiling_mode)
10412 pitch_limit = 8*1024;
10414 pitch_limit = 16*1024;
10416 /* XXX DSPC is limited to 4k tiled */
10417 pitch_limit = 8*1024;
10419 if (mode_cmd->pitches[0] > pitch_limit) {
10420 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10421 obj->tiling_mode ? "tiled" : "linear",
10422 mode_cmd->pitches[0], pitch_limit);
10426 if (obj->tiling_mode != I915_TILING_NONE &&
10427 mode_cmd->pitches[0] != obj->stride) {
10428 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10429 mode_cmd->pitches[0], obj->stride);
10433 /* Reject formats not supported by any plane early. */
10434 switch (mode_cmd->pixel_format) {
10435 case DRM_FORMAT_C8:
10436 case DRM_FORMAT_RGB565:
10437 case DRM_FORMAT_XRGB8888:
10438 case DRM_FORMAT_ARGB8888:
10440 case DRM_FORMAT_XRGB1555:
10441 case DRM_FORMAT_ARGB1555:
10442 if (INTEL_INFO(dev)->gen > 3) {
10443 DRM_DEBUG("unsupported pixel format: %s\n",
10444 drm_get_format_name(mode_cmd->pixel_format));
10448 case DRM_FORMAT_XBGR8888:
10449 case DRM_FORMAT_ABGR8888:
10450 case DRM_FORMAT_XRGB2101010:
10451 case DRM_FORMAT_ARGB2101010:
10452 case DRM_FORMAT_XBGR2101010:
10453 case DRM_FORMAT_ABGR2101010:
10454 if (INTEL_INFO(dev)->gen < 4) {
10455 DRM_DEBUG("unsupported pixel format: %s\n",
10456 drm_get_format_name(mode_cmd->pixel_format));
10460 case DRM_FORMAT_YUYV:
10461 case DRM_FORMAT_UYVY:
10462 case DRM_FORMAT_YVYU:
10463 case DRM_FORMAT_VYUY:
10464 if (INTEL_INFO(dev)->gen < 5) {
10465 DRM_DEBUG("unsupported pixel format: %s\n",
10466 drm_get_format_name(mode_cmd->pixel_format));
10471 DRM_DEBUG("unsupported pixel format: %s\n",
10472 drm_get_format_name(mode_cmd->pixel_format));
10476 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10477 if (mode_cmd->offsets[0] != 0)
10480 tile_height = IS_GEN2(dev) ? 16 : 8;
10481 aligned_height = ALIGN(mode_cmd->height,
10482 obj->tiling_mode ? tile_height : 1);
10483 /* FIXME drm helper for size checks (especially planar formats)? */
10484 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10487 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10488 intel_fb->obj = obj;
10489 intel_fb->obj->framebuffer_references++;
10491 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10493 DRM_ERROR("framebuffer init failed %d\n", ret);
10500 static struct drm_framebuffer *
10501 intel_user_framebuffer_create(struct drm_device *dev,
10502 struct drm_file *filp,
10503 struct drm_mode_fb_cmd2 *mode_cmd)
10505 struct drm_i915_gem_object *obj;
10507 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10508 mode_cmd->handles[0]));
10509 if (&obj->base == NULL)
10510 return ERR_PTR(-ENOENT);
10512 return intel_framebuffer_create(dev, mode_cmd, obj);
10515 #ifndef CONFIG_DRM_I915_FBDEV
10516 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10521 static const struct drm_mode_config_funcs intel_mode_funcs = {
10522 .fb_create = intel_user_framebuffer_create,
10523 .output_poll_changed = intel_fbdev_output_poll_changed,
10526 /* Set up chip specific display functions */
10527 static void intel_init_display(struct drm_device *dev)
10529 struct drm_i915_private *dev_priv = dev->dev_private;
10531 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10532 dev_priv->display.find_dpll = g4x_find_best_dpll;
10533 else if (IS_VALLEYVIEW(dev))
10534 dev_priv->display.find_dpll = vlv_find_best_dpll;
10535 else if (IS_PINEVIEW(dev))
10536 dev_priv->display.find_dpll = pnv_find_best_dpll;
10538 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10540 if (HAS_DDI(dev)) {
10541 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10542 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10543 dev_priv->display.crtc_enable = haswell_crtc_enable;
10544 dev_priv->display.crtc_disable = haswell_crtc_disable;
10545 dev_priv->display.off = haswell_crtc_off;
10546 dev_priv->display.update_plane = ironlake_update_plane;
10547 } else if (HAS_PCH_SPLIT(dev)) {
10548 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10549 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10550 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10551 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10552 dev_priv->display.off = ironlake_crtc_off;
10553 dev_priv->display.update_plane = ironlake_update_plane;
10554 } else if (IS_VALLEYVIEW(dev)) {
10555 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10556 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10557 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10558 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10559 dev_priv->display.off = i9xx_crtc_off;
10560 dev_priv->display.update_plane = i9xx_update_plane;
10562 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10563 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10564 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10565 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10566 dev_priv->display.off = i9xx_crtc_off;
10567 dev_priv->display.update_plane = i9xx_update_plane;
10570 /* Returns the core display clock speed */
10571 if (IS_VALLEYVIEW(dev))
10572 dev_priv->display.get_display_clock_speed =
10573 valleyview_get_display_clock_speed;
10574 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10575 dev_priv->display.get_display_clock_speed =
10576 i945_get_display_clock_speed;
10577 else if (IS_I915G(dev))
10578 dev_priv->display.get_display_clock_speed =
10579 i915_get_display_clock_speed;
10580 else if (IS_I945GM(dev) || IS_845G(dev))
10581 dev_priv->display.get_display_clock_speed =
10582 i9xx_misc_get_display_clock_speed;
10583 else if (IS_PINEVIEW(dev))
10584 dev_priv->display.get_display_clock_speed =
10585 pnv_get_display_clock_speed;
10586 else if (IS_I915GM(dev))
10587 dev_priv->display.get_display_clock_speed =
10588 i915gm_get_display_clock_speed;
10589 else if (IS_I865G(dev))
10590 dev_priv->display.get_display_clock_speed =
10591 i865_get_display_clock_speed;
10592 else if (IS_I85X(dev))
10593 dev_priv->display.get_display_clock_speed =
10594 i855_get_display_clock_speed;
10595 else /* 852, 830 */
10596 dev_priv->display.get_display_clock_speed =
10597 i830_get_display_clock_speed;
10599 if (HAS_PCH_SPLIT(dev)) {
10600 if (IS_GEN5(dev)) {
10601 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10602 dev_priv->display.write_eld = ironlake_write_eld;
10603 } else if (IS_GEN6(dev)) {
10604 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10605 dev_priv->display.write_eld = ironlake_write_eld;
10606 } else if (IS_IVYBRIDGE(dev)) {
10607 /* FIXME: detect B0+ stepping and use auto training */
10608 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10609 dev_priv->display.write_eld = ironlake_write_eld;
10610 dev_priv->display.modeset_global_resources =
10611 ivb_modeset_global_resources;
10612 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10613 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10614 dev_priv->display.write_eld = haswell_write_eld;
10615 dev_priv->display.modeset_global_resources =
10616 haswell_modeset_global_resources;
10618 } else if (IS_G4X(dev)) {
10619 dev_priv->display.write_eld = g4x_write_eld;
10620 } else if (IS_VALLEYVIEW(dev)) {
10621 dev_priv->display.modeset_global_resources =
10622 valleyview_modeset_global_resources;
10623 dev_priv->display.write_eld = ironlake_write_eld;
10626 /* Default just returns -ENODEV to indicate unsupported */
10627 dev_priv->display.queue_flip = intel_default_queue_flip;
10629 switch (INTEL_INFO(dev)->gen) {
10631 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10635 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10640 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10644 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10647 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10648 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10652 intel_panel_init_backlight_funcs(dev);
10656 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10657 * resume, or other times. This quirk makes sure that's the case for
10658 * affected systems.
10660 static void quirk_pipea_force(struct drm_device *dev)
10662 struct drm_i915_private *dev_priv = dev->dev_private;
10664 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10665 DRM_INFO("applying pipe a force quirk\n");
10669 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10671 static void quirk_ssc_force_disable(struct drm_device *dev)
10673 struct drm_i915_private *dev_priv = dev->dev_private;
10674 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10675 DRM_INFO("applying lvds SSC disable quirk\n");
10679 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10682 static void quirk_invert_brightness(struct drm_device *dev)
10684 struct drm_i915_private *dev_priv = dev->dev_private;
10685 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10686 DRM_INFO("applying inverted panel brightness quirk\n");
10689 struct intel_quirk {
10691 int subsystem_vendor;
10692 int subsystem_device;
10693 void (*hook)(struct drm_device *dev);
10696 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10697 struct intel_dmi_quirk {
10698 void (*hook)(struct drm_device *dev);
10699 const struct dmi_system_id (*dmi_id_list)[];
10702 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10704 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10708 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10710 .dmi_id_list = &(const struct dmi_system_id[]) {
10712 .callback = intel_dmi_reverse_brightness,
10713 .ident = "NCR Corporation",
10714 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10715 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10718 { } /* terminating entry */
10720 .hook = quirk_invert_brightness,
10724 static struct intel_quirk intel_quirks[] = {
10725 /* HP Mini needs pipe A force quirk (LP: #322104) */
10726 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10728 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10729 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10731 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10732 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10734 /* 830 needs to leave pipe A & dpll A up */
10735 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10737 /* Lenovo U160 cannot use SSC on LVDS */
10738 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10740 /* Sony Vaio Y cannot use SSC on LVDS */
10741 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10744 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10745 * seem to use inverted backlight PWM.
10747 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10750 static void intel_init_quirks(struct drm_device *dev)
10752 struct pci_dev *d = dev->pdev;
10755 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10756 struct intel_quirk *q = &intel_quirks[i];
10758 if (d->device == q->device &&
10759 (d->subsystem_vendor == q->subsystem_vendor ||
10760 q->subsystem_vendor == PCI_ANY_ID) &&
10761 (d->subsystem_device == q->subsystem_device ||
10762 q->subsystem_device == PCI_ANY_ID))
10765 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10766 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10767 intel_dmi_quirks[i].hook(dev);
10771 /* Disable the VGA plane that we never use */
10772 static void i915_disable_vga(struct drm_device *dev)
10774 struct drm_i915_private *dev_priv = dev->dev_private;
10776 u32 vga_reg = i915_vgacntrl_reg(dev);
10778 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10779 outb(SR01, VGA_SR_INDEX);
10780 sr1 = inb(VGA_SR_DATA);
10781 outb(sr1 | 1<<5, VGA_SR_DATA);
10782 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10785 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10786 POSTING_READ(vga_reg);
10789 void intel_modeset_init_hw(struct drm_device *dev)
10791 struct drm_i915_private *dev_priv = dev->dev_private;
10793 intel_prepare_ddi(dev);
10795 intel_init_clock_gating(dev);
10797 /* Enable the CRI clock source so we can get at the display */
10798 if (IS_VALLEYVIEW(dev))
10799 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10800 DPLL_INTEGRATED_CRI_CLK_VLV);
10802 intel_init_dpio(dev);
10804 mutex_lock(&dev->struct_mutex);
10805 intel_enable_gt_powersave(dev);
10806 mutex_unlock(&dev->struct_mutex);
10809 void intel_modeset_suspend_hw(struct drm_device *dev)
10811 intel_suspend_hw(dev);
10814 void intel_modeset_init(struct drm_device *dev)
10816 struct drm_i915_private *dev_priv = dev->dev_private;
10819 drm_mode_config_init(dev);
10821 dev->mode_config.min_width = 0;
10822 dev->mode_config.min_height = 0;
10824 dev->mode_config.preferred_depth = 24;
10825 dev->mode_config.prefer_shadow = 1;
10827 dev->mode_config.funcs = &intel_mode_funcs;
10829 intel_init_quirks(dev);
10831 intel_init_pm(dev);
10833 if (INTEL_INFO(dev)->num_pipes == 0)
10836 intel_init_display(dev);
10838 if (IS_GEN2(dev)) {
10839 dev->mode_config.max_width = 2048;
10840 dev->mode_config.max_height = 2048;
10841 } else if (IS_GEN3(dev)) {
10842 dev->mode_config.max_width = 4096;
10843 dev->mode_config.max_height = 4096;
10845 dev->mode_config.max_width = 8192;
10846 dev->mode_config.max_height = 8192;
10848 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10850 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10851 INTEL_INFO(dev)->num_pipes,
10852 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10855 intel_crtc_init(dev, i);
10856 for (j = 0; j < dev_priv->num_plane; j++) {
10857 ret = intel_plane_init(dev, i, j);
10859 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10860 pipe_name(i), sprite_name(i, j), ret);
10864 intel_cpu_pll_init(dev);
10865 intel_shared_dpll_init(dev);
10867 /* Just disable it once at startup */
10868 i915_disable_vga(dev);
10869 intel_setup_outputs(dev);
10871 /* Just in case the BIOS is doing something questionable. */
10872 intel_disable_fbc(dev);
10876 intel_connector_break_all_links(struct intel_connector *connector)
10878 connector->base.dpms = DRM_MODE_DPMS_OFF;
10879 connector->base.encoder = NULL;
10880 connector->encoder->connectors_active = false;
10881 connector->encoder->base.crtc = NULL;
10884 static void intel_enable_pipe_a(struct drm_device *dev)
10886 struct intel_connector *connector;
10887 struct drm_connector *crt = NULL;
10888 struct intel_load_detect_pipe load_detect_temp;
10890 /* We can't just switch on the pipe A, we need to set things up with a
10891 * proper mode and output configuration. As a gross hack, enable pipe A
10892 * by enabling the load detect pipe once. */
10893 list_for_each_entry(connector,
10894 &dev->mode_config.connector_list,
10896 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10897 crt = &connector->base;
10905 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10906 intel_release_load_detect_pipe(crt, &load_detect_temp);
10912 intel_check_plane_mapping(struct intel_crtc *crtc)
10914 struct drm_device *dev = crtc->base.dev;
10915 struct drm_i915_private *dev_priv = dev->dev_private;
10918 if (INTEL_INFO(dev)->num_pipes == 1)
10921 reg = DSPCNTR(!crtc->plane);
10922 val = I915_READ(reg);
10924 if ((val & DISPLAY_PLANE_ENABLE) &&
10925 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10931 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10933 struct drm_device *dev = crtc->base.dev;
10934 struct drm_i915_private *dev_priv = dev->dev_private;
10937 /* Clear any frame start delays used for debugging left by the BIOS */
10938 reg = PIPECONF(crtc->config.cpu_transcoder);
10939 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10941 /* We need to sanitize the plane -> pipe mapping first because this will
10942 * disable the crtc (and hence change the state) if it is wrong. Note
10943 * that gen4+ has a fixed plane -> pipe mapping. */
10944 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10945 struct intel_connector *connector;
10948 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10949 crtc->base.base.id);
10951 /* Pipe has the wrong plane attached and the plane is active.
10952 * Temporarily change the plane mapping and disable everything
10954 plane = crtc->plane;
10955 crtc->plane = !plane;
10956 dev_priv->display.crtc_disable(&crtc->base);
10957 crtc->plane = plane;
10959 /* ... and break all links. */
10960 list_for_each_entry(connector, &dev->mode_config.connector_list,
10962 if (connector->encoder->base.crtc != &crtc->base)
10965 intel_connector_break_all_links(connector);
10968 WARN_ON(crtc->active);
10969 crtc->base.enabled = false;
10972 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10973 crtc->pipe == PIPE_A && !crtc->active) {
10974 /* BIOS forgot to enable pipe A, this mostly happens after
10975 * resume. Force-enable the pipe to fix this, the update_dpms
10976 * call below we restore the pipe to the right state, but leave
10977 * the required bits on. */
10978 intel_enable_pipe_a(dev);
10981 /* Adjust the state of the output pipe according to whether we
10982 * have active connectors/encoders. */
10983 intel_crtc_update_dpms(&crtc->base);
10985 if (crtc->active != crtc->base.enabled) {
10986 struct intel_encoder *encoder;
10988 /* This can happen either due to bugs in the get_hw_state
10989 * functions or because the pipe is force-enabled due to the
10991 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10992 crtc->base.base.id,
10993 crtc->base.enabled ? "enabled" : "disabled",
10994 crtc->active ? "enabled" : "disabled");
10996 crtc->base.enabled = crtc->active;
10998 /* Because we only establish the connector -> encoder ->
10999 * crtc links if something is active, this means the
11000 * crtc is now deactivated. Break the links. connector
11001 * -> encoder links are only establish when things are
11002 * actually up, hence no need to break them. */
11003 WARN_ON(crtc->active);
11005 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11006 WARN_ON(encoder->connectors_active);
11007 encoder->base.crtc = NULL;
11012 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11014 struct intel_connector *connector;
11015 struct drm_device *dev = encoder->base.dev;
11017 /* We need to check both for a crtc link (meaning that the
11018 * encoder is active and trying to read from a pipe) and the
11019 * pipe itself being active. */
11020 bool has_active_crtc = encoder->base.crtc &&
11021 to_intel_crtc(encoder->base.crtc)->active;
11023 if (encoder->connectors_active && !has_active_crtc) {
11024 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11025 encoder->base.base.id,
11026 drm_get_encoder_name(&encoder->base));
11028 /* Connector is active, but has no active pipe. This is
11029 * fallout from our resume register restoring. Disable
11030 * the encoder manually again. */
11031 if (encoder->base.crtc) {
11032 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11033 encoder->base.base.id,
11034 drm_get_encoder_name(&encoder->base));
11035 encoder->disable(encoder);
11038 /* Inconsistent output/port/pipe state happens presumably due to
11039 * a bug in one of the get_hw_state functions. Or someplace else
11040 * in our code, like the register restore mess on resume. Clamp
11041 * things to off as a safer default. */
11042 list_for_each_entry(connector,
11043 &dev->mode_config.connector_list,
11045 if (connector->encoder != encoder)
11048 intel_connector_break_all_links(connector);
11051 /* Enabled encoders without active connectors will be fixed in
11052 * the crtc fixup. */
11055 void i915_redisable_vga(struct drm_device *dev)
11057 struct drm_i915_private *dev_priv = dev->dev_private;
11058 u32 vga_reg = i915_vgacntrl_reg(dev);
11060 /* This function can be called both from intel_modeset_setup_hw_state or
11061 * at a very early point in our resume sequence, where the power well
11062 * structures are not yet restored. Since this function is at a very
11063 * paranoid "someone might have enabled VGA while we were not looking"
11064 * level, just check if the power well is enabled instead of trying to
11065 * follow the "don't touch the power well if we don't need it" policy
11066 * the rest of the driver uses. */
11067 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11068 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11071 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11072 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11073 i915_disable_vga(dev);
11077 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11079 struct drm_i915_private *dev_priv = dev->dev_private;
11081 struct intel_crtc *crtc;
11082 struct intel_encoder *encoder;
11083 struct intel_connector *connector;
11086 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11088 memset(&crtc->config, 0, sizeof(crtc->config));
11090 crtc->active = dev_priv->display.get_pipe_config(crtc,
11093 crtc->base.enabled = crtc->active;
11094 crtc->primary_enabled = crtc->active;
11096 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11097 crtc->base.base.id,
11098 crtc->active ? "enabled" : "disabled");
11101 /* FIXME: Smash this into the new shared dpll infrastructure. */
11103 intel_ddi_setup_hw_pll_state(dev);
11105 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11106 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11108 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11110 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11112 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11115 pll->refcount = pll->active;
11117 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11118 pll->name, pll->refcount, pll->on);
11121 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11125 if (encoder->get_hw_state(encoder, &pipe)) {
11126 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11127 encoder->base.crtc = &crtc->base;
11128 encoder->get_config(encoder, &crtc->config);
11130 encoder->base.crtc = NULL;
11133 encoder->connectors_active = false;
11134 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11135 encoder->base.base.id,
11136 drm_get_encoder_name(&encoder->base),
11137 encoder->base.crtc ? "enabled" : "disabled",
11141 list_for_each_entry(connector, &dev->mode_config.connector_list,
11143 if (connector->get_hw_state(connector)) {
11144 connector->base.dpms = DRM_MODE_DPMS_ON;
11145 connector->encoder->connectors_active = true;
11146 connector->base.encoder = &connector->encoder->base;
11148 connector->base.dpms = DRM_MODE_DPMS_OFF;
11149 connector->base.encoder = NULL;
11151 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11152 connector->base.base.id,
11153 drm_get_connector_name(&connector->base),
11154 connector->base.encoder ? "enabled" : "disabled");
11158 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11159 * and i915 state tracking structures. */
11160 void intel_modeset_setup_hw_state(struct drm_device *dev,
11161 bool force_restore)
11163 struct drm_i915_private *dev_priv = dev->dev_private;
11165 struct intel_crtc *crtc;
11166 struct intel_encoder *encoder;
11169 intel_modeset_readout_hw_state(dev);
11172 * Now that we have the config, copy it to each CRTC struct
11173 * Note that this could go away if we move to using crtc_config
11174 * checking everywhere.
11176 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11178 if (crtc->active && i915_fastboot) {
11179 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11181 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11182 crtc->base.base.id);
11183 drm_mode_debug_printmodeline(&crtc->base.mode);
11187 /* HW state is read out, now we need to sanitize this mess. */
11188 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11190 intel_sanitize_encoder(encoder);
11193 for_each_pipe(pipe) {
11194 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11195 intel_sanitize_crtc(crtc);
11196 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11199 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11200 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11202 if (!pll->on || pll->active)
11205 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11207 pll->disable(dev_priv, pll);
11211 if (IS_HASWELL(dev))
11212 ilk_wm_get_hw_state(dev);
11214 if (force_restore) {
11215 i915_redisable_vga(dev);
11218 * We need to use raw interfaces for restoring state to avoid
11219 * checking (bogus) intermediate states.
11221 for_each_pipe(pipe) {
11222 struct drm_crtc *crtc =
11223 dev_priv->pipe_to_crtc_mapping[pipe];
11225 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11229 intel_modeset_update_staged_output_state(dev);
11232 intel_modeset_check_state(dev);
11234 drm_mode_config_reset(dev);
11237 void intel_modeset_gem_init(struct drm_device *dev)
11239 intel_modeset_init_hw(dev);
11241 intel_setup_overlay(dev);
11243 intel_modeset_setup_hw_state(dev, false);
11246 void intel_modeset_cleanup(struct drm_device *dev)
11248 struct drm_i915_private *dev_priv = dev->dev_private;
11249 struct drm_crtc *crtc;
11250 struct drm_connector *connector;
11253 * Interrupts and polling as the first thing to avoid creating havoc.
11254 * Too much stuff here (turning of rps, connectors, ...) would
11255 * experience fancy races otherwise.
11257 drm_irq_uninstall(dev);
11258 cancel_work_sync(&dev_priv->hotplug_work);
11260 * Due to the hpd irq storm handling the hotplug work can re-arm the
11261 * poll handlers. Hence disable polling after hpd handling is shut down.
11263 drm_kms_helper_poll_fini(dev);
11265 mutex_lock(&dev->struct_mutex);
11267 intel_unregister_dsm_handler();
11269 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11270 /* Skip inactive CRTCs */
11274 intel_increase_pllclock(crtc);
11277 intel_disable_fbc(dev);
11279 intel_disable_gt_powersave(dev);
11281 ironlake_teardown_rc6(dev);
11283 mutex_unlock(&dev->struct_mutex);
11285 /* flush any delayed tasks or pending work */
11286 flush_scheduled_work();
11288 /* destroy the backlight and sysfs files before encoders/connectors */
11289 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11290 intel_panel_destroy_backlight(connector);
11291 drm_sysfs_connector_remove(connector);
11294 drm_mode_config_cleanup(dev);
11296 intel_cleanup_overlay(dev);
11300 * Return which encoder is currently attached for connector.
11302 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11304 return &intel_attached_encoder(connector)->base;
11307 void intel_connector_attach_encoder(struct intel_connector *connector,
11308 struct intel_encoder *encoder)
11310 connector->encoder = encoder;
11311 drm_mode_connector_attach_encoder(&connector->base,
11316 * set vga decode state - true == enable VGA decode
11318 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11320 struct drm_i915_private *dev_priv = dev->dev_private;
11323 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11325 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11327 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11328 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11332 struct intel_display_error_state {
11334 u32 power_well_driver;
11336 int num_transcoders;
11338 struct intel_cursor_error_state {
11343 } cursor[I915_MAX_PIPES];
11345 struct intel_pipe_error_state {
11346 bool power_domain_on;
11348 } pipe[I915_MAX_PIPES];
11350 struct intel_plane_error_state {
11358 } plane[I915_MAX_PIPES];
11360 struct intel_transcoder_error_state {
11361 bool power_domain_on;
11362 enum transcoder cpu_transcoder;
11375 struct intel_display_error_state *
11376 intel_display_capture_error_state(struct drm_device *dev)
11378 drm_i915_private_t *dev_priv = dev->dev_private;
11379 struct intel_display_error_state *error;
11380 int transcoders[] = {
11388 if (INTEL_INFO(dev)->num_pipes == 0)
11391 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11395 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11396 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11399 error->pipe[i].power_domain_on =
11400 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11401 if (!error->pipe[i].power_domain_on)
11404 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11405 error->cursor[i].control = I915_READ(CURCNTR(i));
11406 error->cursor[i].position = I915_READ(CURPOS(i));
11407 error->cursor[i].base = I915_READ(CURBASE(i));
11409 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11410 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11411 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11414 error->plane[i].control = I915_READ(DSPCNTR(i));
11415 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11416 if (INTEL_INFO(dev)->gen <= 3) {
11417 error->plane[i].size = I915_READ(DSPSIZE(i));
11418 error->plane[i].pos = I915_READ(DSPPOS(i));
11420 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11421 error->plane[i].addr = I915_READ(DSPADDR(i));
11422 if (INTEL_INFO(dev)->gen >= 4) {
11423 error->plane[i].surface = I915_READ(DSPSURF(i));
11424 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11427 error->pipe[i].source = I915_READ(PIPESRC(i));
11430 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11431 if (HAS_DDI(dev_priv->dev))
11432 error->num_transcoders++; /* Account for eDP. */
11434 for (i = 0; i < error->num_transcoders; i++) {
11435 enum transcoder cpu_transcoder = transcoders[i];
11437 error->transcoder[i].power_domain_on =
11438 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11439 if (!error->transcoder[i].power_domain_on)
11442 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11444 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11445 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11446 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11447 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11448 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11449 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11450 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11456 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11459 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11460 struct drm_device *dev,
11461 struct intel_display_error_state *error)
11468 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11469 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11470 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11471 error->power_well_driver);
11473 err_printf(m, "Pipe [%d]:\n", i);
11474 err_printf(m, " Power: %s\n",
11475 error->pipe[i].power_domain_on ? "on" : "off");
11476 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11478 err_printf(m, "Plane [%d]:\n", i);
11479 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11480 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
11481 if (INTEL_INFO(dev)->gen <= 3) {
11482 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11483 err_printf(m, " POS: %08x\n", error->plane[i].pos);
11485 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11486 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
11487 if (INTEL_INFO(dev)->gen >= 4) {
11488 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11489 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
11492 err_printf(m, "Cursor [%d]:\n", i);
11493 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11494 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11495 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
11498 for (i = 0; i < error->num_transcoders; i++) {
11499 err_printf(m, "CPU transcoder: %c\n",
11500 transcoder_name(error->transcoder[i].cpu_transcoder));
11501 err_printf(m, " Power: %s\n",
11502 error->transcoder[i].power_domain_on ? "on" : "off");
11503 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11504 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11505 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11506 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11507 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11508 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11509 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);