drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                         int, int, intel_clock_t *, intel_clock_t *);
  76 };
  77
  78 /* FDI */
  79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  80
  81 int
  82 intel_pch_rawclk(struct drm_device *dev)
  83 {
  84         struct drm_i915_private *dev_priv = dev->dev_private;
  85
  86         WARN_ON(!HAS_PCH_SPLIT(dev));
  87
  88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  89 }
  90
  91 static bool
  92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  93                     int target, int refclk, intel_clock_t *match_clock,
  94                     intel_clock_t *best_clock);
  95 static bool
  96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                         int target, int refclk, intel_clock_t *match_clock,
  98                         intel_clock_t *best_clock);
  99
 100 static bool
 101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 102                       int target, int refclk, intel_clock_t *match_clock,
 103                       intel_clock_t *best_clock);
 104 static bool
 105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 106                            int target, int refclk, intel_clock_t *match_clock,
 107                            intel_clock_t *best_clock);
 108
 109 static bool
 110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 111                         int target, int refclk, intel_clock_t *match_clock,
 112                         intel_clock_t *best_clock);
 113
 114 static inline u32 /* units of 100MHz */
 115 intel_fdi_link_freq(struct drm_device *dev)
 116 {
 117         if (IS_GEN5(dev)) {
 118                 struct drm_i915_private *dev_priv = dev->dev_private;
 119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 120         } else
 121                 return 27;
 122 }
 123
 124 static const intel_limit_t intel_limits_i8xx_dvo = {
 125         .dot = { .min = 25000, .max = 350000 },
 126         .vco = { .min = 930000, .max = 1400000 },
 127         .n = { .min = 3, .max = 16 },
 128         .m = { .min = 96, .max = 140 },
 129         .m1 = { .min = 18, .max = 26 },
 130         .m2 = { .min = 6, .max = 16 },
 131         .p = { .min = 4, .max = 128 },
 132         .p1 = { .min = 2, .max = 33 },
 133         .p2 = { .dot_limit = 165000,
 134                 .p2_slow = 4, .p2_fast = 2 },
 135         .find_pll = intel_find_best_PLL,
 136 };
 137
 138 static const intel_limit_t intel_limits_i8xx_lvds = {
 139         .dot = { .min = 25000, .max = 350000 },
 140         .vco = { .min = 930000, .max = 1400000 },
 141         .n = { .min = 3, .max = 16 },
 142         .m = { .min = 96, .max = 140 },
 143         .m1 = { .min = 18, .max = 26 },
 144         .m2 = { .min = 6, .max = 16 },
 145         .p = { .min = 4, .max = 128 },
 146         .p1 = { .min = 1, .max = 6 },
 147         .p2 = { .dot_limit = 165000,
 148                 .p2_slow = 14, .p2_fast = 7 },
 149         .find_pll = intel_find_best_PLL,
 150 };
 151
 152 static const intel_limit_t intel_limits_i9xx_sdvo = {
 153         .dot = { .min = 20000, .max = 400000 },
 154         .vco = { .min = 1400000, .max = 2800000 },
 155         .n = { .min = 1, .max = 6 },
 156         .m = { .min = 70, .max = 120 },
 157         .m1 = { .min = 10, .max = 22 },
 158         .m2 = { .min = 5, .max = 9 },
 159         .p = { .min = 5, .max = 80 },
 160         .p1 = { .min = 1, .max = 8 },
 161         .p2 = { .dot_limit = 200000,
 162                 .p2_slow = 10, .p2_fast = 5 },
 163         .find_pll = intel_find_best_PLL,
 164 };
 165
 166 static const intel_limit_t intel_limits_i9xx_lvds = {
 167         .dot = { .min = 20000, .max = 400000 },
 168         .vco = { .min = 1400000, .max = 2800000 },
 169         .n = { .min = 1, .max = 6 },
 170         .m = { .min = 70, .max = 120 },
 171         .m1 = { .min = 10, .max = 22 },
 172         .m2 = { .min = 5, .max = 9 },
 173         .p = { .min = 7, .max = 98 },
 174         .p1 = { .min = 1, .max = 8 },
 175         .p2 = { .dot_limit = 112000,
 176                 .p2_slow = 14, .p2_fast = 7 },
 177         .find_pll = intel_find_best_PLL,
 178 };
 179
 180
 181 static const intel_limit_t intel_limits_g4x_sdvo = {
 182         .dot = { .min = 25000, .max = 270000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 17, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 10, .max = 30 },
 189         .p1 = { .min = 1, .max = 3},
 190         .p2 = { .dot_limit = 270000,
 191                 .p2_slow = 10,
 192                 .p2_fast = 10
 193         },
 194         .find_pll = intel_g4x_find_best_PLL,
 195 };
 196
 197 static const intel_limit_t intel_limits_g4x_hdmi = {
 198         .dot = { .min = 22000, .max = 400000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 16, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 5, .max = 80 },
 205         .p1 = { .min = 1, .max = 8},
 206         .p2 = { .dot_limit = 165000,
 207                 .p2_slow = 10, .p2_fast = 5 },
 208         .find_pll = intel_g4x_find_best_PLL,
 209 };
 210
 211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 212         .dot = { .min = 20000, .max = 115000 },
 213         .vco = { .min = 1750000, .max = 3500000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 28, .max = 112 },
 219         .p1 = { .min = 2, .max = 8 },
 220         .p2 = { .dot_limit = 0,
 221                 .p2_slow = 14, .p2_fast = 14
 222         },
 223         .find_pll = intel_g4x_find_best_PLL,
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 227         .dot = { .min = 80000, .max = 224000 },
 228         .vco = { .min = 1750000, .max = 3500000 },
 229         .n = { .min = 1, .max = 3 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 17, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 14, .max = 42 },
 234         .p1 = { .min = 2, .max = 6 },
 235         .p2 = { .dot_limit = 0,
 236                 .p2_slow = 7, .p2_fast = 7
 237         },
 238         .find_pll = intel_g4x_find_best_PLL,
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_display_port = {
 242         .dot = { .min = 161670, .max = 227000 },
 243         .vco = { .min = 1750000, .max = 3500000},
 244         .n = { .min = 1, .max = 2 },
 245         .m = { .min = 97, .max = 108 },
 246         .m1 = { .min = 0x10, .max = 0x12 },
 247         .m2 = { .min = 0x05, .max = 0x06 },
 248         .p = { .min = 10, .max = 20 },
 249         .p1 = { .min = 1, .max = 2},
 250         .p2 = { .dot_limit = 0,
 251                 .p2_slow = 10, .p2_fast = 10 },
 252         .find_pll = intel_find_pll_g4x_dp,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_sdvo = {
 256         .dot = { .min = 20000, .max = 400000},
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         /* Pineview's Ncounter is a ring counter */
 259         .n = { .min = 3, .max = 6 },
 260         .m = { .min = 2, .max = 256 },
 261         /* Pineview only has one combined m divider, which we treat as m2. */
 262         .m1 = { .min = 0, .max = 0 },
 263         .m2 = { .min = 0, .max = 254 },
 264         .p = { .min = 5, .max = 80 },
 265         .p1 = { .min = 1, .max = 8 },
 266         .p2 = { .dot_limit = 200000,
 267                 .p2_slow = 10, .p2_fast = 5 },
 268         .find_pll = intel_find_best_PLL,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_lvds = {
 272         .dot = { .min = 20000, .max = 400000 },
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         .m1 = { .min = 0, .max = 0 },
 277         .m2 = { .min = 0, .max = 254 },
 278         .p = { .min = 7, .max = 112 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 112000,
 281                 .p2_slow = 14, .p2_fast = 14 },
 282         .find_pll = intel_find_best_PLL,
 283 };
 284
 285 /* Ironlake / Sandybridge
 286  *
 287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 288  * the range value for them is (actual_value - 2).
 289  */
 290 static const intel_limit_t intel_limits_ironlake_dac = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 5 },
 294         .m = { .min = 79, .max = 127 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301         .find_pll = intel_g4x_find_best_PLL,
 302 };
 303
 304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 3 },
 308         .m = { .min = 79, .max = 118 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 28, .max = 112 },
 312         .p1 = { .min = 2, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 14, .p2_fast = 14 },
 315         .find_pll = intel_g4x_find_best_PLL,
 316 };
 317
 318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 3 },
 322         .m = { .min = 79, .max = 127 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 14, .max = 56 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 7, .p2_fast = 7 },
 329         .find_pll = intel_g4x_find_best_PLL,
 330 };
 331
 332 /* LVDS 100mhz refclk limits. */
 333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 334         .dot = { .min = 25000, .max = 350000 },
 335         .vco = { .min = 1760000, .max = 3510000 },
 336         .n = { .min = 1, .max = 2 },
 337         .m = { .min = 79, .max = 126 },
 338         .m1 = { .min = 12, .max = 22 },
 339         .m2 = { .min = 5, .max = 9 },
 340         .p = { .min = 28, .max = 112 },
 341         .p1 = { .min = 2, .max = 8 },
 342         .p2 = { .dot_limit = 225000,
 343                 .p2_slow = 14, .p2_fast = 14 },
 344         .find_pll = intel_g4x_find_best_PLL,
 345 };
 346
 347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 348         .dot = { .min = 25000, .max = 350000 },
 349         .vco = { .min = 1760000, .max = 3510000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 79, .max = 126 },
 352         .m1 = { .min = 12, .max = 22 },
 353         .m2 = { .min = 5, .max = 9 },
 354         .p = { .min = 14, .max = 42 },
 355         .p1 = { .min = 2, .max = 6 },
 356         .p2 = { .dot_limit = 225000,
 357                 .p2_slow = 7, .p2_fast = 7 },
 358         .find_pll = intel_g4x_find_best_PLL,
 359 };
 360
 361 static const intel_limit_t intel_limits_ironlake_display_port = {
 362         .dot = { .min = 25000, .max = 350000 },
 363         .vco = { .min = 1760000, .max = 3510000},
 364         .n = { .min = 1, .max = 2 },
 365         .m = { .min = 81, .max = 90 },
 366         .m1 = { .min = 12, .max = 22 },
 367         .m2 = { .min = 5, .max = 9 },
 368         .p = { .min = 10, .max = 20 },
 369         .p1 = { .min = 1, .max = 2},
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 10, .p2_fast = 10 },
 372         .find_pll = intel_find_pll_ironlake_dp,
 373 };
 374
 375 static const intel_limit_t intel_limits_vlv_dac = {
 376         .dot = { .min = 25000, .max = 270000 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m = { .min = 22, .max = 450 }, /* guess */
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p = { .min = 10, .max = 30 },
 383         .p1 = { .min = 2, .max = 3 },
 384         .p2 = { .dot_limit = 270000,
 385                 .p2_slow = 2, .p2_fast = 20 },
 386         .find_pll = intel_vlv_find_best_pll,
 387 };
 388
 389 static const intel_limit_t intel_limits_vlv_hdmi = {
 390         .dot = { .min = 20000, .max = 165000 },
 391         .vco = { .min = 4000000, .max = 5994000},
 392         .n = { .min = 1, .max = 7 },
 393         .m = { .min = 60, .max = 300 }, /* guess */
 394         .m1 = { .min = 2, .max = 3 },
 395         .m2 = { .min = 11, .max = 156 },
 396         .p = { .min = 10, .max = 30 },
 397         .p1 = { .min = 2, .max = 3 },
 398         .p2 = { .dot_limit = 270000,
 399                 .p2_slow = 2, .p2_fast = 20 },
 400         .find_pll = intel_vlv_find_best_pll,
 401 };
 402
 403 static const intel_limit_t intel_limits_vlv_dp = {
 404         .dot = { .min = 25000, .max = 270000 },
 405         .vco = { .min = 4000000, .max = 6000000 },
 406         .n = { .min = 1, .max = 7 },
 407         .m = { .min = 22, .max = 450 },
 408         .m1 = { .min = 2, .max = 3 },
 409         .m2 = { .min = 11, .max = 156 },
 410         .p = { .min = 10, .max = 30 },
 411         .p1 = { .min = 2, .max = 3 },
 412         .p2 = { .dot_limit = 270000,
 413                 .p2_slow = 2, .p2_fast = 20 },
 414         .find_pll = intel_vlv_find_best_pll,
 415 };
 416
 417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 418 {
 419         unsigned long flags;
 420         u32 val = 0;
 421
 422         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO idle wait timed out\n");
 425                 goto out_unlock;
 426         }
 427
 428         I915_WRITE(DPIO_REG, reg);
 429         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 430                    DPIO_BYTE);
 431         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 432                 DRM_ERROR("DPIO read wait timed out\n");
 433                 goto out_unlock;
 434         }
 435         val = I915_READ(DPIO_DATA);
 436
 437 out_unlock:
 438         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 439         return val;
 440 }
 441
 442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 443                              u32 val)
 444 {
 445         unsigned long flags;
 446
 447         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 448         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 449                 DRM_ERROR("DPIO idle wait timed out\n");
 450                 goto out_unlock;
 451         }
 452
 453         I915_WRITE(DPIO_DATA, val);
 454         I915_WRITE(DPIO_REG, reg);
 455         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 456                    DPIO_BYTE);
 457         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 458                 DRM_ERROR("DPIO write wait timed out\n");
 459
 460 out_unlock:
 461        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 462 }
 463
 464 static void vlv_init_dpio(struct drm_device *dev)
 465 {
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467
 468         /* Reset the DPIO config */
 469         I915_WRITE(DPIO_CTL, 0);
 470         POSTING_READ(DPIO_CTL);
 471         I915_WRITE(DPIO_CTL, 1);
 472         POSTING_READ(DPIO_CTL);
 473 }
 474
 475 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 476                                                 int refclk)
 477 {
 478         struct drm_device *dev = crtc->dev;
 479         const intel_limit_t *limit;
 480
 481         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 482                 if (intel_is_dual_link_lvds(dev)) {
 483                         /* LVDS dual channel */
 484                         if (refclk == 100000)
 485                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 486                         else
 487                                 limit = &intel_limits_ironlake_dual_lvds;
 488                 } else {
 489                         if (refclk == 100000)
 490                                 limit = &intel_limits_ironlake_single_lvds_100m;
 491                         else
 492                                 limit = &intel_limits_ironlake_single_lvds;
 493                 }
 494         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 495                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 496                 limit = &intel_limits_ironlake_display_port;
 497         else
 498                 limit = &intel_limits_ironlake_dac;
 499
 500         return limit;
 501 }
 502
 503 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         const intel_limit_t *limit;
 507
 508         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 509                 if (intel_is_dual_link_lvds(dev))
 510                         /* LVDS with dual channel */
 511                         limit = &intel_limits_g4x_dual_channel_lvds;
 512                 else
 513                         /* LVDS with dual channel */
 514                         limit = &intel_limits_g4x_single_channel_lvds;
 515         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 516                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 517                 limit = &intel_limits_g4x_hdmi;
 518         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 519                 limit = &intel_limits_g4x_sdvo;
 520         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 521                 limit = &intel_limits_g4x_display_port;
 522         } else /* The option is for other outputs */
 523                 limit = &intel_limits_i9xx_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         const intel_limit_t *limit;
 532
 533         if (HAS_PCH_SPLIT(dev))
 534                 limit = intel_ironlake_limit(crtc, refclk);
 535         else if (IS_G4X(dev)) {
 536                 limit = intel_g4x_limit(crtc);
 537         } else if (IS_PINEVIEW(dev)) {
 538                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 539                         limit = &intel_limits_pineview_lvds;
 540                 else
 541                         limit = &intel_limits_pineview_sdvo;
 542         } else if (IS_VALLEYVIEW(dev)) {
 543                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 544                         limit = &intel_limits_vlv_dac;
 545                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 546                         limit = &intel_limits_vlv_hdmi;
 547                 else
 548                         limit = &intel_limits_vlv_dp;
 549         } else if (!IS_GEN2(dev)) {
 550                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 551                         limit = &intel_limits_i9xx_lvds;
 552                 else
 553                         limit = &intel_limits_i9xx_sdvo;
 554         } else {
 555                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 556                         limit = &intel_limits_i8xx_lvds;
 557                 else
 558                         limit = &intel_limits_i8xx_dvo;
 559         }
 560         return limit;
 561 }
 562
 563 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 564 static void pineview_clock(int refclk, intel_clock_t *clock)
 565 {
 566         clock->m = clock->m2 + 2;
 567         clock->p = clock->p1 * clock->p2;
 568         clock->vco = refclk * clock->m / clock->n;
 569         clock->dot = clock->vco / clock->p;
 570 }
 571
 572 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 573 {
 574         if (IS_PINEVIEW(dev)) {
 575                 pineview_clock(refclk, clock);
 576                 return;
 577         }
 578         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 579         clock->p = clock->p1 * clock->p2;
 580         clock->vco = refclk * clock->m / (clock->n + 2);
 581         clock->dot = clock->vco / clock->p;
 582 }
 583
 584 /**
 585  * Returns whether any output on the specified pipe is of the specified type
 586  */
 587 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 588 {
 589         struct drm_device *dev = crtc->dev;
 590         struct intel_encoder *encoder;
 591
 592         for_each_encoder_on_crtc(dev, crtc, encoder)
 593                 if (encoder->type == type)
 594                         return true;
 595
 596         return false;
 597 }
 598
 599 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 600 /**
 601  * Returns whether the given set of divisors are valid for a given refclk with
 602  * the given connectors.
 603  */
 604
 605 static bool intel_PLL_is_valid(struct drm_device *dev,
 606                                const intel_limit_t *limit,
 607                                const intel_clock_t *clock)
 608 {
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 612                 INTELPllInvalid("p out of range\n");
 613         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 614                 INTELPllInvalid("m2 out of range\n");
 615         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 616                 INTELPllInvalid("m1 out of range\n");
 617         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 618                 INTELPllInvalid("m1 <= m2\n");
 619         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 620                 INTELPllInvalid("m out of range\n");
 621         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 622                 INTELPllInvalid("n out of range\n");
 623         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 624                 INTELPllInvalid("vco out of range\n");
 625         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 626          * connector, etc., rather than just a single range.
 627          */
 628         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 629                 INTELPllInvalid("dot out of range\n");
 630
 631         return true;
 632 }
 633
 634 static bool
 635 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 636                     int target, int refclk, intel_clock_t *match_clock,
 637                     intel_clock_t *best_clock)
 638
 639 {
 640         struct drm_device *dev = crtc->dev;
 641         intel_clock_t clock;
 642         int err = target;
 643
 644         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 645                 /*
 646                  * For LVDS just rely on its current settings for dual-channel.
 647                  * We haven't figured out how to reliably set up different
 648                  * single/dual channel state, if we even can.
 649                  */
 650                 if (intel_is_dual_link_lvds(dev))
 651                         clock.p2 = limit->p2.p2_fast;
 652                 else
 653                         clock.p2 = limit->p2.p2_slow;
 654         } else {
 655                 if (target < limit->p2.dot_limit)
 656                         clock.p2 = limit->p2.p2_slow;
 657                 else
 658                         clock.p2 = limit->p2.p2_fast;
 659         }
 660
 661         memset(best_clock, 0, sizeof(*best_clock));
 662
 663         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 664              clock.m1++) {
 665                 for (clock.m2 = limit->m2.min;
 666                      clock.m2 <= limit->m2.max; clock.m2++) {
 667                         /* m1 is always 0 in Pineview */
 668                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 669                                 break;
 670                         for (clock.n = limit->n.min;
 671                              clock.n <= limit->n.max; clock.n++) {
 672                                 for (clock.p1 = limit->p1.min;
 673                                         clock.p1 <= limit->p1.max; clock.p1++) {
 674                                         int this_err;
 675
 676                                         intel_clock(dev, refclk, &clock);
 677                                         if (!intel_PLL_is_valid(dev, limit,
 678                                                                 &clock))
 679                                                 continue;
 680                                         if (match_clock &&
 681                                             clock.p != match_clock->p)
 682                                                 continue;
 683
 684                                         this_err = abs(clock.dot - target);
 685                                         if (this_err < err) {
 686                                                 *best_clock = clock;
 687                                                 err = this_err;
 688                                         }
 689                                 }
 690                         }
 691                 }
 692         }
 693
 694         return (err != target);
 695 }
 696
 697 static bool
 698 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 699                         int target, int refclk, intel_clock_t *match_clock,
 700                         intel_clock_t *best_clock)
 701 {
 702         struct drm_device *dev = crtc->dev;
 703         intel_clock_t clock;
 704         int max_n;
 705         bool found;
 706         /* approximately equals target * 0.00585 */
 707         int err_most = (target >> 8) + (target >> 9);
 708         found = false;
 709
 710         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 711                 int lvds_reg;
 712
 713                 if (HAS_PCH_SPLIT(dev))
 714                         lvds_reg = PCH_LVDS;
 715                 else
 716                         lvds_reg = LVDS;
 717                 if (intel_is_dual_link_lvds(dev))
 718                         clock.p2 = limit->p2.p2_fast;
 719                 else
 720                         clock.p2 = limit->p2.p2_slow;
 721         } else {
 722                 if (target < limit->p2.dot_limit)
 723                         clock.p2 = limit->p2.p2_slow;
 724                 else
 725                         clock.p2 = limit->p2.p2_fast;
 726         }
 727
 728         memset(best_clock, 0, sizeof(*best_clock));
 729         max_n = limit->n.max;
 730         /* based on hardware requirement, prefer smaller n to precision */
 731         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 732                 /* based on hardware requirement, prefere larger m1,m2 */
 733                 for (clock.m1 = limit->m1.max;
 734                      clock.m1 >= limit->m1.min; clock.m1--) {
 735                         for (clock.m2 = limit->m2.max;
 736                              clock.m2 >= limit->m2.min; clock.m2--) {
 737                                 for (clock.p1 = limit->p1.max;
 738                                      clock.p1 >= limit->p1.min; clock.p1--) {
 739                                         int this_err;
 740
 741                                         intel_clock(dev, refclk, &clock);
 742                                         if (!intel_PLL_is_valid(dev, limit,
 743                                                                 &clock))
 744                                                 continue;
 745                                         if (match_clock &&
 746                                             clock.p != match_clock->p)
 747                                                 continue;
 748
 749                                         this_err = abs(clock.dot - target);
 750                                         if (this_err < err_most) {
 751                                                 *best_clock = clock;
 752                                                 err_most = this_err;
 753                                                 max_n = clock.n;
 754                                                 found = true;
 755                                         }
 756                                 }
 757                         }
 758                 }
 759         }
 760         return found;
 761 }
 762
 763 static bool
 764 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 765                            int target, int refclk, intel_clock_t *match_clock,
 766                            intel_clock_t *best_clock)
 767 {
 768         struct drm_device *dev = crtc->dev;
 769         intel_clock_t clock;
 770
 771         if (target < 200000) {
 772                 clock.n = 1;
 773                 clock.p1 = 2;
 774                 clock.p2 = 10;
 775                 clock.m1 = 12;
 776                 clock.m2 = 9;
 777         } else {
 778                 clock.n = 2;
 779                 clock.p1 = 1;
 780                 clock.p2 = 10;
 781                 clock.m1 = 14;
 782                 clock.m2 = 8;
 783         }
 784         intel_clock(dev, refclk, &clock);
 785         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 786         return true;
 787 }
 788
 789 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 790 static bool
 791 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 792                       int target, int refclk, intel_clock_t *match_clock,
 793                       intel_clock_t *best_clock)
 794 {
 795         intel_clock_t clock;
 796         if (target < 200000) {
 797                 clock.p1 = 2;
 798                 clock.p2 = 10;
 799                 clock.n = 2;
 800                 clock.m1 = 23;
 801                 clock.m2 = 8;
 802         } else {
 803                 clock.p1 = 1;
 804                 clock.p2 = 10;
 805                 clock.n = 1;
 806                 clock.m1 = 14;
 807                 clock.m2 = 2;
 808         }
 809         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 810         clock.p = (clock.p1 * clock.p2);
 811         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 812         clock.vco = 0;
 813         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 814         return true;
 815 }
 816 static bool
 817 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 818                         int target, int refclk, intel_clock_t *match_clock,
 819                         intel_clock_t *best_clock)
 820 {
 821         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 822         u32 m, n, fastclk;
 823         u32 updrate, minupdate, fracbits, p;
 824         unsigned long bestppm, ppm, absppm;
 825         int dotclk, flag;
 826
 827         flag = 0;
 828         dotclk = target * 1000;
 829         bestppm = 1000000;
 830         ppm = absppm = 0;
 831         fastclk = dotclk / (2*100);
 832         updrate = 0;
 833         minupdate = 19200;
 834         fracbits = 1;
 835         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 836         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 837
 838         /* based on hardware requirement, prefer smaller n to precision */
 839         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 840                 updrate = refclk / n;
 841                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 842                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 843                                 if (p2 > 10)
 844                                         p2 = p2 - 1;
 845                                 p = p1 * p2;
 846                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 847                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 848                                         m2 = (((2*(fastclk * p * n / m1 )) +
 849                                                refclk) / (2*refclk));
 850                                         m = m1 * m2;
 851                                         vco = updrate * m;
 852                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 853                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 854                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 855                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 856                                                         bestppm = 0;
 857                                                         flag = 1;
 858                                                 }
 859                                                 if (absppm < bestppm - 10) {
 860                                                         bestppm = absppm;
 861                                                         flag = 1;
 862                                                 }
 863                                                 if (flag) {
 864                                                         bestn = n;
 865                                                         bestm1 = m1;
 866                                                         bestm2 = m2;
 867                                                         bestp1 = p1;
 868                                                         bestp2 = p2;
 869                                                         flag = 0;
 870                                                 }
 871                                         }
 872                                 }
 873                         }
 874                 }
 875         }
 876         best_clock->n = bestn;
 877         best_clock->m1 = bestm1;
 878         best_clock->m2 = bestm2;
 879         best_clock->p1 = bestp1;
 880         best_clock->p2 = bestp2;
 881
 882         return true;
 883 }
 884
 885 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 886                                              enum pipe pipe)
 887 {
 888         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890
 891         return intel_crtc->cpu_transcoder;
 892 }
 893
 894 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 895 {
 896         struct drm_i915_private *dev_priv = dev->dev_private;
 897         u32 frame, frame_reg = PIPEFRAME(pipe);
 898
 899         frame = I915_READ(frame_reg);
 900
 901         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 902                 DRM_DEBUG_KMS("vblank wait timed out\n");
 903 }
 904
 905 /**
 906  * intel_wait_for_vblank - wait for vblank on a given pipe
 907  * @dev: drm device
 908  * @pipe: pipe to wait for
 909  *
 910  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 911  * mode setting code.
 912  */
 913 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         int pipestat_reg = PIPESTAT(pipe);
 917
 918         if (INTEL_INFO(dev)->gen >= 5) {
 919                 ironlake_wait_for_vblank(dev, pipe);
 920                 return;
 921         }
 922
 923         /* Clear existing vblank status. Note this will clear any other
 924          * sticky status fields as well.
 925          *
 926          * This races with i915_driver_irq_handler() with the result
 927          * that either function could miss a vblank event.  Here it is not
 928          * fatal, as we will either wait upon the next vblank interrupt or
 929          * timeout.  Generally speaking intel_wait_for_vblank() is only
 930          * called during modeset at which time the GPU should be idle and
 931          * should *not* be performing page flips and thus not waiting on
 932          * vblanks...
 933          * Currently, the result of us stealing a vblank from the irq
 934          * handler is that a single frame will be skipped during swapbuffers.
 935          */
 936         I915_WRITE(pipestat_reg,
 937                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 938
 939         /* Wait for vblank interrupt bit to set */
 940         if (wait_for(I915_READ(pipestat_reg) &
 941                      PIPE_VBLANK_INTERRUPT_STATUS,
 942                      50))
 943                 DRM_DEBUG_KMS("vblank wait timed out\n");
 944 }
 945
 946 /*
 947  * intel_wait_for_pipe_off - wait for pipe to turn off
 948  * @dev: drm device
 949  * @pipe: pipe to wait for
 950  *
 951  * After disabling a pipe, we can't wait for vblank in the usual way,
 952  * spinning on the vblank interrupt status bit, since we won't actually
 953  * see an interrupt when the pipe is disabled.
 954  *
 955  * On Gen4 and above:
 956  *   wait for the pipe register state bit to turn off
 957  *
 958  * Otherwise:
 959  *   wait for the display line value to settle (it usually
 960  *   ends up stopping at the start of the next frame).
 961  *
 962  */
 963 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 964 {
 965         struct drm_i915_private *dev_priv = dev->dev_private;
 966         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 967                                                                       pipe);
 968
 969         if (INTEL_INFO(dev)->gen >= 4) {
 970                 int reg = PIPECONF(cpu_transcoder);
 971
 972                 /* Wait for the Pipe State to go off */
 973                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 974                              100))
 975                         WARN(1, "pipe_off wait timed out\n");
 976         } else {
 977                 u32 last_line, line_mask;
 978                 int reg = PIPEDSL(pipe);
 979                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 980
 981                 if (IS_GEN2(dev))
 982                         line_mask = DSL_LINEMASK_GEN2;
 983                 else
 984                         line_mask = DSL_LINEMASK_GEN3;
 985
 986                 /* Wait for the display line to settle */
 987                 do {
 988                         last_line = I915_READ(reg) & line_mask;
 989                         mdelay(5);
 990                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 991                          time_after(timeout, jiffies));
 992                 if (time_after(jiffies, timeout))
 993                         WARN(1, "pipe_off wait timed out\n");
 994         }
 995 }
 996
 997 static const char *state_string(bool enabled)
 998 {
 999         return enabled ? "on" : "off";
1000 }
1001
1002 /* Only for pre-ILK configs */
1003 static void assert_pll(struct drm_i915_private *dev_priv,
1004                        enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = DPLL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & DPLL_VCO_ENABLE);
1013         WARN(cur_state != state,
1014              "PLL state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1018 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1019
1020 /* For ILK+ */
1021 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1022                            struct intel_pch_pll *pll,
1023                            struct intel_crtc *crtc,
1024                            bool state)
1025 {
1026         u32 val;
1027         bool cur_state;
1028
1029         if (HAS_PCH_LPT(dev_priv->dev)) {
1030                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1031                 return;
1032         }
1033
1034         if (WARN (!pll,
1035                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1036                 return;
1037
1038         val = I915_READ(pll->pll_reg);
1039         cur_state = !!(val & DPLL_VCO_ENABLE);
1040         WARN(cur_state != state,
1041              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1042              pll->pll_reg, state_string(state), state_string(cur_state), val);
1043
1044         /* Make sure the selected PLL is correctly attached to the transcoder */
1045         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1046                 u32 pch_dpll;
1047
1048                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1049                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1050                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1051                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1052                           cur_state, crtc->pipe, pch_dpll)) {
1053                         cur_state = !!(val >> (4*crtc->pipe + 3));
1054                         WARN(cur_state != state,
1055                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1056                              pll->pll_reg == _PCH_DPLL_B,
1057                              state_string(state),
1058                              crtc->pipe,
1059                              val);
1060                 }
1061         }
1062 }
1063 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1064 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1065
1066 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1067                           enum pipe pipe, bool state)
1068 {
1069         int reg;
1070         u32 val;
1071         bool cur_state;
1072         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1073                                                                       pipe);
1074
1075         if (HAS_DDI(dev_priv->dev)) {
1076                 /* DDI does not have a specific FDI_TX register */
1077                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1078                 val = I915_READ(reg);
1079                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1080         } else {
1081                 reg = FDI_TX_CTL(pipe);
1082                 val = I915_READ(reg);
1083                 cur_state = !!(val & FDI_TX_ENABLE);
1084         }
1085         WARN(cur_state != state,
1086              "FDI TX state assertion failure (expected %s, current %s)\n",
1087              state_string(state), state_string(cur_state));
1088 }
1089 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1090 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1091
1092 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         int reg;
1096         u32 val;
1097         bool cur_state;
1098
1099         reg = FDI_RX_CTL(pipe);
1100         val = I915_READ(reg);
1101         cur_state = !!(val & FDI_RX_ENABLE);
1102         WARN(cur_state != state,
1103              "FDI RX state assertion failure (expected %s, current %s)\n",
1104              state_string(state), state_string(cur_state));
1105 }
1106 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1107 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1108
1109 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1110                                       enum pipe pipe)
1111 {
1112         int reg;
1113         u32 val;
1114
1115         /* ILK FDI PLL is always enabled */
1116         if (dev_priv->info->gen == 5)
1117                 return;
1118
1119         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1120         if (HAS_DDI(dev_priv->dev))
1121                 return;
1122
1123         reg = FDI_TX_CTL(pipe);
1124         val = I915_READ(reg);
1125         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1126 }
1127
1128 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1129                                       enum pipe pipe)
1130 {
1131         int reg;
1132         u32 val;
1133
1134         reg = FDI_RX_CTL(pipe);
1135         val = I915_READ(reg);
1136         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1137 }
1138
1139 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1140                                   enum pipe pipe)
1141 {
1142         int pp_reg, lvds_reg;
1143         u32 val;
1144         enum pipe panel_pipe = PIPE_A;
1145         bool locked = true;
1146
1147         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1148                 pp_reg = PCH_PP_CONTROL;
1149                 lvds_reg = PCH_LVDS;
1150         } else {
1151                 pp_reg = PP_CONTROL;
1152                 lvds_reg = LVDS;
1153         }
1154
1155         val = I915_READ(pp_reg);
1156         if (!(val & PANEL_POWER_ON) ||
1157             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1158                 locked = false;
1159
1160         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1161                 panel_pipe = PIPE_B;
1162
1163         WARN(panel_pipe == pipe && locked,
1164              "panel assertion failure, pipe %c regs locked\n",
1165              pipe_name(pipe));
1166 }
1167
1168 void assert_pipe(struct drm_i915_private *dev_priv,
1169                  enum pipe pipe, bool state)
1170 {
1171         int reg;
1172         u32 val;
1173         bool cur_state;
1174         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1175                                                                       pipe);
1176
1177         /* if we need the pipe A quirk it must be always on */
1178         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1179                 state = true;
1180
1181         reg = PIPECONF(cpu_transcoder);
1182         val = I915_READ(reg);
1183         cur_state = !!(val & PIPECONF_ENABLE);
1184         WARN(cur_state != state,
1185              "pipe %c assertion failure (expected %s, current %s)\n",
1186              pipe_name(pipe), state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_plane(struct drm_i915_private *dev_priv,
1190                          enum plane plane, bool state)
1191 {
1192         int reg;
1193         u32 val;
1194         bool cur_state;
1195
1196         reg = DSPCNTR(plane);
1197         val = I915_READ(reg);
1198         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1199         WARN(cur_state != state,
1200              "plane %c assertion failure (expected %s, current %s)\n",
1201              plane_name(plane), state_string(state), state_string(cur_state));
1202 }
1203
1204 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1205 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1206
1207 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1208                                    enum pipe pipe)
1209 {
1210         int reg, i;
1211         u32 val;
1212         int cur_pipe;
1213
1214         /* Planes are fixed to pipes on ILK+ */
1215         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1216                 reg = DSPCNTR(pipe);
1217                 val = I915_READ(reg);
1218                 WARN((val & DISPLAY_PLANE_ENABLE),
1219                      "plane %c assertion failure, should be disabled but not\n",
1220                      plane_name(pipe));
1221                 return;
1222         }
1223
1224         /* Need to check both planes against the pipe */
1225         for (i = 0; i < 2; i++) {
1226                 reg = DSPCNTR(i);
1227                 val = I915_READ(reg);
1228                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1229                         DISPPLANE_SEL_PIPE_SHIFT;
1230                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1231                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1232                      plane_name(i), pipe_name(pipe));
1233         }
1234 }
1235
1236 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1237 {
1238         u32 val;
1239         bool enabled;
1240
1241         if (HAS_PCH_LPT(dev_priv->dev)) {
1242                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1243                 return;
1244         }
1245
1246         val = I915_READ(PCH_DREF_CONTROL);
1247         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1248                             DREF_SUPERSPREAD_SOURCE_MASK));
1249         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1250 }
1251
1252 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1253                                        enum pipe pipe)
1254 {
1255         int reg;
1256         u32 val;
1257         bool enabled;
1258
1259         reg = TRANSCONF(pipe);
1260         val = I915_READ(reg);
1261         enabled = !!(val & TRANS_ENABLE);
1262         WARN(enabled,
1263              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1264              pipe_name(pipe));
1265 }
1266
1267 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1268                             enum pipe pipe, u32 port_sel, u32 val)
1269 {
1270         if ((val & DP_PORT_EN) == 0)
1271                 return false;
1272
1273         if (HAS_PCH_CPT(dev_priv->dev)) {
1274                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1275                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1276                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1277                         return false;
1278         } else {
1279                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1280                         return false;
1281         }
1282         return true;
1283 }
1284
1285 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1286                               enum pipe pipe, u32 val)
1287 {
1288         if ((val & PORT_ENABLE) == 0)
1289                 return false;
1290
1291         if (HAS_PCH_CPT(dev_priv->dev)) {
1292                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1293                         return false;
1294         } else {
1295                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1296                         return false;
1297         }
1298         return true;
1299 }
1300
1301 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1302                               enum pipe pipe, u32 val)
1303 {
1304         if ((val & LVDS_PORT_EN) == 0)
1305                 return false;
1306
1307         if (HAS_PCH_CPT(dev_priv->dev)) {
1308                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1309                         return false;
1310         } else {
1311                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1312                         return false;
1313         }
1314         return true;
1315 }
1316
1317 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1318                               enum pipe pipe, u32 val)
1319 {
1320         if ((val & ADPA_DAC_ENABLE) == 0)
1321                 return false;
1322         if (HAS_PCH_CPT(dev_priv->dev)) {
1323                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1324                         return false;
1325         } else {
1326                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1327                         return false;
1328         }
1329         return true;
1330 }
1331
1332 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1333                                    enum pipe pipe, int reg, u32 port_sel)
1334 {
1335         u32 val = I915_READ(reg);
1336         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1337              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1338              reg, pipe_name(pipe));
1339
1340         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1341              && (val & DP_PIPEB_SELECT),
1342              "IBX PCH dp port still using transcoder B\n");
1343 }
1344
1345 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1346                                      enum pipe pipe, int reg)
1347 {
1348         u32 val = I915_READ(reg);
1349         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1350              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1351              reg, pipe_name(pipe));
1352
1353         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1354              && (val & SDVO_PIPE_B_SELECT),
1355              "IBX PCH hdmi port still using transcoder B\n");
1356 }
1357
1358 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1359                                       enum pipe pipe)
1360 {
1361         int reg;
1362         u32 val;
1363
1364         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1365         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1366         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1367
1368         reg = PCH_ADPA;
1369         val = I915_READ(reg);
1370         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1371              "PCH VGA enabled on transcoder %c, should be disabled\n",
1372              pipe_name(pipe));
1373
1374         reg = PCH_LVDS;
1375         val = I915_READ(reg);
1376         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1377              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1378              pipe_name(pipe));
1379
1380         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1381         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1382         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1383 }
1384
1385 /**
1386  * intel_enable_pll - enable a PLL
1387  * @dev_priv: i915 private structure
1388  * @pipe: pipe PLL to enable
1389  *
1390  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1391  * make sure the PLL reg is writable first though, since the panel write
1392  * protect mechanism may be enabled.
1393  *
1394  * Note!  This is for pre-ILK only.
1395  *
1396  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1397  */
1398 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1399 {
1400         int reg;
1401         u32 val;
1402
1403         /* No really, not for ILK+ */
1404         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1405
1406         /* PLL is protected by panel, make sure we can write it */
1407         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1408                 assert_panel_unlocked(dev_priv, pipe);
1409
1410         reg = DPLL(pipe);
1411         val = I915_READ(reg);
1412         val |= DPLL_VCO_ENABLE;
1413
1414         /* We do this three times for luck */
1415         I915_WRITE(reg, val);
1416         POSTING_READ(reg);
1417         udelay(150); /* wait for warmup */
1418         I915_WRITE(reg, val);
1419         POSTING_READ(reg);
1420         udelay(150); /* wait for warmup */
1421         I915_WRITE(reg, val);
1422         POSTING_READ(reg);
1423         udelay(150); /* wait for warmup */
1424 }
1425
1426 /**
1427  * intel_disable_pll - disable a PLL
1428  * @dev_priv: i915 private structure
1429  * @pipe: pipe PLL to disable
1430  *
1431  * Disable the PLL for @pipe, making sure the pipe is off first.
1432  *
1433  * Note!  This is for pre-ILK only.
1434  */
1435 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437         int reg;
1438         u32 val;
1439
1440         /* Don't disable pipe A or pipe A PLLs if needed */
1441         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1442                 return;
1443
1444         /* Make sure the pipe isn't still relying on us */
1445         assert_pipe_disabled(dev_priv, pipe);
1446
1447         reg = DPLL(pipe);
1448         val = I915_READ(reg);
1449         val &= ~DPLL_VCO_ENABLE;
1450         I915_WRITE(reg, val);
1451         POSTING_READ(reg);
1452 }
1453
1454 /* SBI access */
1455 static void
1456 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1457 {
1458         unsigned long flags;
1459
1460         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1461         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1462                                 100)) {
1463                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1464                 goto out_unlock;
1465         }
1466
1467         I915_WRITE(SBI_ADDR,
1468                         (reg << 16));
1469         I915_WRITE(SBI_DATA,
1470                         value);
1471         I915_WRITE(SBI_CTL_STAT,
1472                         SBI_BUSY |
1473                         SBI_CTL_OP_CRWR);
1474
1475         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1476                                 100)) {
1477                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1478                 goto out_unlock;
1479         }
1480
1481 out_unlock:
1482         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1483 }
1484
1485 static u32
1486 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1487 {
1488         unsigned long flags;
1489         u32 value = 0;
1490
1491         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1492         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1493                                 100)) {
1494                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1495                 goto out_unlock;
1496         }
1497
1498         I915_WRITE(SBI_ADDR,
1499                         (reg << 16));
1500         I915_WRITE(SBI_CTL_STAT,
1501                         SBI_BUSY |
1502                         SBI_CTL_OP_CRRD);
1503
1504         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1505                                 100)) {
1506                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1507                 goto out_unlock;
1508         }
1509
1510         value = I915_READ(SBI_DATA);
1511
1512 out_unlock:
1513         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1514         return value;
1515 }
1516
1517 /**
1518  * ironlake_enable_pch_pll - enable PCH PLL
1519  * @dev_priv: i915 private structure
1520  * @pipe: pipe PLL to enable
1521  *
1522  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1523  * drives the transcoder clock.
1524  */
1525 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1526 {
1527         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1528         struct intel_pch_pll *pll;
1529         int reg;
1530         u32 val;
1531
1532         /* PCH PLLs only available on ILK, SNB and IVB */
1533         BUG_ON(dev_priv->info->gen < 5);
1534         pll = intel_crtc->pch_pll;
1535         if (pll == NULL)
1536                 return;
1537
1538         if (WARN_ON(pll->refcount == 0))
1539                 return;
1540
1541         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1542                       pll->pll_reg, pll->active, pll->on,
1543                       intel_crtc->base.base.id);
1544
1545         /* PCH refclock must be enabled first */
1546         assert_pch_refclk_enabled(dev_priv);
1547
1548         if (pll->active++ && pll->on) {
1549                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1550                 return;
1551         }
1552
1553         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1554
1555         reg = pll->pll_reg;
1556         val = I915_READ(reg);
1557         val |= DPLL_VCO_ENABLE;
1558         I915_WRITE(reg, val);
1559         POSTING_READ(reg);
1560         udelay(200);
1561
1562         pll->on = true;
1563 }
1564
1565 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1566 {
1567         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1569         int reg;
1570         u32 val;
1571
1572         /* PCH only available on ILK+ */
1573         BUG_ON(dev_priv->info->gen < 5);
1574         if (pll == NULL)
1575                return;
1576
1577         if (WARN_ON(pll->refcount == 0))
1578                 return;
1579
1580         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1581                       pll->pll_reg, pll->active, pll->on,
1582                       intel_crtc->base.base.id);
1583
1584         if (WARN_ON(pll->active == 0)) {
1585                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1586                 return;
1587         }
1588
1589         if (--pll->active) {
1590                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1591                 return;
1592         }
1593
1594         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1595
1596         /* Make sure transcoder isn't still depending on us */
1597         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1598
1599         reg = pll->pll_reg;
1600         val = I915_READ(reg);
1601         val &= ~DPLL_VCO_ENABLE;
1602         I915_WRITE(reg, val);
1603         POSTING_READ(reg);
1604         udelay(200);
1605
1606         pll->on = false;
1607 }
1608
1609 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1610                                            enum pipe pipe)
1611 {
1612         struct drm_device *dev = dev_priv->dev;
1613         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1614         uint32_t reg, val, pipeconf_val;
1615
1616         /* PCH only available on ILK+ */
1617         BUG_ON(dev_priv->info->gen < 5);
1618
1619         /* Make sure PCH DPLL is enabled */
1620         assert_pch_pll_enabled(dev_priv,
1621                                to_intel_crtc(crtc)->pch_pll,
1622                                to_intel_crtc(crtc));
1623
1624         /* FDI must be feeding us bits for PCH ports */
1625         assert_fdi_tx_enabled(dev_priv, pipe);
1626         assert_fdi_rx_enabled(dev_priv, pipe);
1627
1628         if (HAS_PCH_CPT(dev)) {
1629                 /* Workaround: Set the timing override bit before enabling the
1630                  * pch transcoder. */
1631                 reg = TRANS_CHICKEN2(pipe);
1632                 val = I915_READ(reg);
1633                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1634                 I915_WRITE(reg, val);
1635         }
1636
1637         reg = TRANSCONF(pipe);
1638         val = I915_READ(reg);
1639         pipeconf_val = I915_READ(PIPECONF(pipe));
1640
1641         if (HAS_PCH_IBX(dev_priv->dev)) {
1642                 /*
1643                  * make the BPC in transcoder be consistent with
1644                  * that in pipeconf reg.
1645                  */
1646                 val &= ~PIPE_BPC_MASK;
1647                 val |= pipeconf_val & PIPE_BPC_MASK;
1648         }
1649
1650         val &= ~TRANS_INTERLACE_MASK;
1651         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1652                 if (HAS_PCH_IBX(dev_priv->dev) &&
1653                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1654                         val |= TRANS_LEGACY_INTERLACED_ILK;
1655                 else
1656                         val |= TRANS_INTERLACED;
1657         else
1658                 val |= TRANS_PROGRESSIVE;
1659
1660         I915_WRITE(reg, val | TRANS_ENABLE);
1661         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1662                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1663 }
1664
1665 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1666                                       enum transcoder cpu_transcoder)
1667 {
1668         u32 val, pipeconf_val;
1669
1670         /* PCH only available on ILK+ */
1671         BUG_ON(dev_priv->info->gen < 5);
1672
1673         /* FDI must be feeding us bits for PCH ports */
1674         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1675         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1676
1677         /* Workaround: set timing override bit. */
1678         val = I915_READ(_TRANSA_CHICKEN2);
1679         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1680         I915_WRITE(_TRANSA_CHICKEN2, val);
1681
1682         val = TRANS_ENABLE;
1683         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1684
1685         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1686             PIPECONF_INTERLACED_ILK)
1687                 val |= TRANS_INTERLACED;
1688         else
1689                 val |= TRANS_PROGRESSIVE;
1690
1691         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1692         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1693                 DRM_ERROR("Failed to enable PCH transcoder\n");
1694 }
1695
1696 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1697                                             enum pipe pipe)
1698 {
1699         struct drm_device *dev = dev_priv->dev;
1700         uint32_t reg, val;
1701
1702         /* FDI relies on the transcoder */
1703         assert_fdi_tx_disabled(dev_priv, pipe);
1704         assert_fdi_rx_disabled(dev_priv, pipe);
1705
1706         /* Ports must be off as well */
1707         assert_pch_ports_disabled(dev_priv, pipe);
1708
1709         reg = TRANSCONF(pipe);
1710         val = I915_READ(reg);
1711         val &= ~TRANS_ENABLE;
1712         I915_WRITE(reg, val);
1713         /* wait for PCH transcoder off, transcoder state */
1714         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1715                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1716
1717         if (!HAS_PCH_IBX(dev)) {
1718                 /* Workaround: Clear the timing override chicken bit again. */
1719                 reg = TRANS_CHICKEN2(pipe);
1720                 val = I915_READ(reg);
1721                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1722                 I915_WRITE(reg, val);
1723         }
1724 }
1725
1726 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1727 {
1728         u32 val;
1729
1730         val = I915_READ(_TRANSACONF);
1731         val &= ~TRANS_ENABLE;
1732         I915_WRITE(_TRANSACONF, val);
1733         /* wait for PCH transcoder off, transcoder state */
1734         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1735                 DRM_ERROR("Failed to disable PCH transcoder\n");
1736
1737         /* Workaround: clear timing override bit. */
1738         val = I915_READ(_TRANSA_CHICKEN2);
1739         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1740         I915_WRITE(_TRANSA_CHICKEN2, val);
1741 }
1742
1743 /**
1744  * intel_enable_pipe - enable a pipe, asserting requirements
1745  * @dev_priv: i915 private structure
1746  * @pipe: pipe to enable
1747  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1748  *
1749  * Enable @pipe, making sure that various hardware specific requirements
1750  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1751  *
1752  * @pipe should be %PIPE_A or %PIPE_B.
1753  *
1754  * Will wait until the pipe is actually running (i.e. first vblank) before
1755  * returning.
1756  */
1757 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1758                               bool pch_port)
1759 {
1760         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1761                                                                       pipe);
1762         enum pipe pch_transcoder;
1763         int reg;
1764         u32 val;
1765
1766         if (IS_HASWELL(dev_priv->dev))
1767                 pch_transcoder = TRANSCODER_A;
1768         else
1769                 pch_transcoder = pipe;
1770
1771         /*
1772          * A pipe without a PLL won't actually be able to drive bits from
1773          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1774          * need the check.
1775          */
1776         if (!HAS_PCH_SPLIT(dev_priv->dev))
1777                 assert_pll_enabled(dev_priv, pipe);
1778         else {
1779                 if (pch_port) {
1780                         /* if driving the PCH, we need FDI enabled */
1781                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1782                         assert_fdi_tx_pll_enabled(dev_priv,
1783                                                   (enum pipe) cpu_transcoder);
1784                 }
1785                 /* FIXME: assert CPU port conditions for SNB+ */
1786         }
1787
1788         reg = PIPECONF(cpu_transcoder);
1789         val = I915_READ(reg);
1790         if (val & PIPECONF_ENABLE)
1791                 return;
1792
1793         I915_WRITE(reg, val | PIPECONF_ENABLE);
1794         intel_wait_for_vblank(dev_priv->dev, pipe);
1795 }
1796
1797 /**
1798  * intel_disable_pipe - disable a pipe, asserting requirements
1799  * @dev_priv: i915 private structure
1800  * @pipe: pipe to disable
1801  *
1802  * Disable @pipe, making sure that various hardware specific requirements
1803  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1804  *
1805  * @pipe should be %PIPE_A or %PIPE_B.
1806  *
1807  * Will wait until the pipe has shut down before returning.
1808  */
1809 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1810                                enum pipe pipe)
1811 {
1812         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1813                                                                       pipe);
1814         int reg;
1815         u32 val;
1816
1817         /*
1818          * Make sure planes won't keep trying to pump pixels to us,
1819          * or we might hang the display.
1820          */
1821         assert_planes_disabled(dev_priv, pipe);
1822
1823         /* Don't disable pipe A or pipe A PLLs if needed */
1824         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1825                 return;
1826
1827         reg = PIPECONF(cpu_transcoder);
1828         val = I915_READ(reg);
1829         if ((val & PIPECONF_ENABLE) == 0)
1830                 return;
1831
1832         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1833         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1834 }
1835
1836 /*
1837  * Plane regs are double buffered, going from enabled->disabled needs a
1838  * trigger in order to latch.  The display address reg provides this.
1839  */
1840 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1841                                       enum plane plane)
1842 {
1843         if (dev_priv->info->gen >= 4)
1844                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1845         else
1846                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1847 }
1848
1849 /**
1850  * intel_enable_plane - enable a display plane on a given pipe
1851  * @dev_priv: i915 private structure
1852  * @plane: plane to enable
1853  * @pipe: pipe being fed
1854  *
1855  * Enable @plane on @pipe, making sure that @pipe is running first.
1856  */
1857 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1858                                enum plane plane, enum pipe pipe)
1859 {
1860         int reg;
1861         u32 val;
1862
1863         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1864         assert_pipe_enabled(dev_priv, pipe);
1865
1866         reg = DSPCNTR(plane);
1867         val = I915_READ(reg);
1868         if (val & DISPLAY_PLANE_ENABLE)
1869                 return;
1870
1871         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1872         intel_flush_display_plane(dev_priv, plane);
1873         intel_wait_for_vblank(dev_priv->dev, pipe);
1874 }
1875
1876 /**
1877  * intel_disable_plane - disable a display plane
1878  * @dev_priv: i915 private structure
1879  * @plane: plane to disable
1880  * @pipe: pipe consuming the data
1881  *
1882  * Disable @plane; should be an independent operation.
1883  */
1884 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1885                                 enum plane plane, enum pipe pipe)
1886 {
1887         int reg;
1888         u32 val;
1889
1890         reg = DSPCNTR(plane);
1891         val = I915_READ(reg);
1892         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1893                 return;
1894
1895         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1896         intel_flush_display_plane(dev_priv, plane);
1897         intel_wait_for_vblank(dev_priv->dev, pipe);
1898 }
1899
1900 int
1901 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1902                            struct drm_i915_gem_object *obj,
1903                            struct intel_ring_buffer *pipelined)
1904 {
1905         struct drm_i915_private *dev_priv = dev->dev_private;
1906         u32 alignment;
1907         int ret;
1908
1909         switch (obj->tiling_mode) {
1910         case I915_TILING_NONE:
1911                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1912                         alignment = 128 * 1024;
1913                 else if (INTEL_INFO(dev)->gen >= 4)
1914                         alignment = 4 * 1024;
1915                 else
1916                         alignment = 64 * 1024;
1917                 break;
1918         case I915_TILING_X:
1919                 /* pin() will align the object as required by fence */
1920                 alignment = 0;
1921                 break;
1922         case I915_TILING_Y:
1923                 /* FIXME: Is this true? */
1924                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1925                 return -EINVAL;
1926         default:
1927                 BUG();
1928         }
1929
1930         dev_priv->mm.interruptible = false;
1931         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1932         if (ret)
1933                 goto err_interruptible;
1934
1935         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1936          * fence, whereas 965+ only requires a fence if using
1937          * framebuffer compression.  For simplicity, we always install
1938          * a fence as the cost is not that onerous.
1939          */
1940         ret = i915_gem_object_get_fence(obj);
1941         if (ret)
1942                 goto err_unpin;
1943
1944         i915_gem_object_pin_fence(obj);
1945
1946         dev_priv->mm.interruptible = true;
1947         return 0;
1948
1949 err_unpin:
1950         i915_gem_object_unpin(obj);
1951 err_interruptible:
1952         dev_priv->mm.interruptible = true;
1953         return ret;
1954 }
1955
1956 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1957 {
1958         i915_gem_object_unpin_fence(obj);
1959         i915_gem_object_unpin(obj);
1960 }
1961
1962 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1963  * is assumed to be a power-of-two. */
1964 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1965                                                unsigned int bpp,
1966                                                unsigned int pitch)
1967 {
1968         int tile_rows, tiles;
1969
1970         tile_rows = *y / 8;
1971         *y %= 8;
1972         tiles = *x / (512/bpp);
1973         *x %= 512/bpp;
1974
1975         return tile_rows * pitch * 8 + tiles * 4096;
1976 }
1977
1978 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1979                              int x, int y)
1980 {
1981         struct drm_device *dev = crtc->dev;
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984         struct intel_framebuffer *intel_fb;
1985         struct drm_i915_gem_object *obj;
1986         int plane = intel_crtc->plane;
1987         unsigned long linear_offset;
1988         u32 dspcntr;
1989         u32 reg;
1990
1991         switch (plane) {
1992         case 0:
1993         case 1:
1994                 break;
1995         default:
1996                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1997                 return -EINVAL;
1998         }
1999
2000         intel_fb = to_intel_framebuffer(fb);
2001         obj = intel_fb->obj;
2002
2003         reg = DSPCNTR(plane);
2004         dspcntr = I915_READ(reg);
2005         /* Mask out pixel format bits in case we change it */
2006         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2007         switch (fb->pixel_format) {
2008         case DRM_FORMAT_C8:
2009                 dspcntr |= DISPPLANE_8BPP;
2010                 break;
2011         case DRM_FORMAT_XRGB1555:
2012         case DRM_FORMAT_ARGB1555:
2013                 dspcntr |= DISPPLANE_BGRX555;
2014                 break;
2015         case DRM_FORMAT_RGB565:
2016                 dspcntr |= DISPPLANE_BGRX565;
2017                 break;
2018         case DRM_FORMAT_XRGB8888:
2019         case DRM_FORMAT_ARGB8888:
2020                 dspcntr |= DISPPLANE_BGRX888;
2021                 break;
2022         case DRM_FORMAT_XBGR8888:
2023         case DRM_FORMAT_ABGR8888:
2024                 dspcntr |= DISPPLANE_RGBX888;
2025                 break;
2026         case DRM_FORMAT_XRGB2101010:
2027         case DRM_FORMAT_ARGB2101010:
2028                 dspcntr |= DISPPLANE_BGRX101010;
2029                 break;
2030         case DRM_FORMAT_XBGR2101010:
2031         case DRM_FORMAT_ABGR2101010:
2032                 dspcntr |= DISPPLANE_RGBX101010;
2033                 break;
2034         default:
2035                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2036                 return -EINVAL;
2037         }
2038
2039         if (INTEL_INFO(dev)->gen >= 4) {
2040                 if (obj->tiling_mode != I915_TILING_NONE)
2041                         dspcntr |= DISPPLANE_TILED;
2042                 else
2043                         dspcntr &= ~DISPPLANE_TILED;
2044         }
2045
2046         I915_WRITE(reg, dspcntr);
2047
2048         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2049
2050         if (INTEL_INFO(dev)->gen >= 4) {
2051                 intel_crtc->dspaddr_offset =
2052                         intel_gen4_compute_offset_xtiled(&x, &y,
2053                                                          fb->bits_per_pixel / 8,
2054                                                          fb->pitches[0]);
2055                 linear_offset -= intel_crtc->dspaddr_offset;
2056         } else {
2057                 intel_crtc->dspaddr_offset = linear_offset;
2058         }
2059
2060         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2061                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2062         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2063         if (INTEL_INFO(dev)->gen >= 4) {
2064                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2065                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2066                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2067                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2068         } else
2069                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2070         POSTING_READ(reg);
2071
2072         return 0;
2073 }
2074
2075 static int ironlake_update_plane(struct drm_crtc *crtc,
2076                                  struct drm_framebuffer *fb, int x, int y)
2077 {
2078         struct drm_device *dev = crtc->dev;
2079         struct drm_i915_private *dev_priv = dev->dev_private;
2080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2081         struct intel_framebuffer *intel_fb;
2082         struct drm_i915_gem_object *obj;
2083         int plane = intel_crtc->plane;
2084         unsigned long linear_offset;
2085         u32 dspcntr;
2086         u32 reg;
2087
2088         switch (plane) {
2089         case 0:
2090         case 1:
2091         case 2:
2092                 break;
2093         default:
2094                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2095                 return -EINVAL;
2096         }
2097
2098         intel_fb = to_intel_framebuffer(fb);
2099         obj = intel_fb->obj;
2100
2101         reg = DSPCNTR(plane);
2102         dspcntr = I915_READ(reg);
2103         /* Mask out pixel format bits in case we change it */
2104         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2105         switch (fb->pixel_format) {
2106         case DRM_FORMAT_C8:
2107                 dspcntr |= DISPPLANE_8BPP;
2108                 break;
2109         case DRM_FORMAT_RGB565:
2110                 dspcntr |= DISPPLANE_BGRX565;
2111                 break;
2112         case DRM_FORMAT_XRGB8888:
2113         case DRM_FORMAT_ARGB8888:
2114                 dspcntr |= DISPPLANE_BGRX888;
2115                 break;
2116         case DRM_FORMAT_XBGR8888:
2117         case DRM_FORMAT_ABGR8888:
2118                 dspcntr |= DISPPLANE_RGBX888;
2119                 break;
2120         case DRM_FORMAT_XRGB2101010:
2121         case DRM_FORMAT_ARGB2101010:
2122                 dspcntr |= DISPPLANE_BGRX101010;
2123                 break;
2124         case DRM_FORMAT_XBGR2101010:
2125         case DRM_FORMAT_ABGR2101010:
2126                 dspcntr |= DISPPLANE_RGBX101010;
2127                 break;
2128         default:
2129                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2130                 return -EINVAL;
2131         }
2132
2133         if (obj->tiling_mode != I915_TILING_NONE)
2134                 dspcntr |= DISPPLANE_TILED;
2135         else
2136                 dspcntr &= ~DISPPLANE_TILED;
2137
2138         /* must disable */
2139         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2140
2141         I915_WRITE(reg, dspcntr);
2142
2143         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2144         intel_crtc->dspaddr_offset =
2145                 intel_gen4_compute_offset_xtiled(&x, &y,
2146                                                  fb->bits_per_pixel / 8,
2147                                                  fb->pitches[0]);
2148         linear_offset -= intel_crtc->dspaddr_offset;
2149
2150         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2151                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2152         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2153         I915_MODIFY_DISPBASE(DSPSURF(plane),
2154                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2155         if (IS_HASWELL(dev)) {
2156                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2157         } else {
2158                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2159                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2160         }
2161         POSTING_READ(reg);
2162
2163         return 0;
2164 }
2165
2166 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2167 static int
2168 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2169                            int x, int y, enum mode_set_atomic state)
2170 {
2171         struct drm_device *dev = crtc->dev;
2172         struct drm_i915_private *dev_priv = dev->dev_private;
2173
2174         if (dev_priv->display.disable_fbc)
2175                 dev_priv->display.disable_fbc(dev);
2176         intel_increase_pllclock(crtc);
2177
2178         return dev_priv->display.update_plane(crtc, fb, x, y);
2179 }
2180
2181 static int
2182 intel_finish_fb(struct drm_framebuffer *old_fb)
2183 {
2184         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2185         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2186         bool was_interruptible = dev_priv->mm.interruptible;
2187         int ret;
2188
2189         wait_event(dev_priv->pending_flip_queue,
2190                    atomic_read(&dev_priv->mm.wedged) ||
2191                    atomic_read(&obj->pending_flip) == 0);
2192
2193         /* Big Hammer, we also need to ensure that any pending
2194          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2195          * current scanout is retired before unpinning the old
2196          * framebuffer.
2197          *
2198          * This should only fail upon a hung GPU, in which case we
2199          * can safely continue.
2200          */
2201         dev_priv->mm.interruptible = false;
2202         ret = i915_gem_object_finish_gpu(obj);
2203         dev_priv->mm.interruptible = was_interruptible;
2204
2205         return ret;
2206 }
2207
2208 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2209 {
2210         struct drm_device *dev = crtc->dev;
2211         struct drm_i915_master_private *master_priv;
2212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214         if (!dev->primary->master)
2215                 return;
2216
2217         master_priv = dev->primary->master->driver_priv;
2218         if (!master_priv->sarea_priv)
2219                 return;
2220
2221         switch (intel_crtc->pipe) {
2222         case 0:
2223                 master_priv->sarea_priv->pipeA_x = x;
2224                 master_priv->sarea_priv->pipeA_y = y;
2225                 break;
2226         case 1:
2227                 master_priv->sarea_priv->pipeB_x = x;
2228                 master_priv->sarea_priv->pipeB_y = y;
2229                 break;
2230         default:
2231                 break;
2232         }
2233 }
2234
2235 static int
2236 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2237                     struct drm_framebuffer *fb)
2238 {
2239         struct drm_device *dev = crtc->dev;
2240         struct drm_i915_private *dev_priv = dev->dev_private;
2241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2242         struct drm_framebuffer *old_fb;
2243         int ret;
2244
2245         /* no fb bound */
2246         if (!fb) {
2247                 DRM_ERROR("No FB bound\n");
2248                 return 0;
2249         }
2250
2251         if(intel_crtc->plane > dev_priv->num_pipe) {
2252                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2253                                 intel_crtc->plane,
2254                                 dev_priv->num_pipe);
2255                 return -EINVAL;
2256         }
2257
2258         mutex_lock(&dev->struct_mutex);
2259         ret = intel_pin_and_fence_fb_obj(dev,
2260                                          to_intel_framebuffer(fb)->obj,
2261                                          NULL);
2262         if (ret != 0) {
2263                 mutex_unlock(&dev->struct_mutex);
2264                 DRM_ERROR("pin & fence failed\n");
2265                 return ret;
2266         }
2267
2268         if (crtc->fb)
2269                 intel_finish_fb(crtc->fb);
2270
2271         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2272         if (ret) {
2273                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2274                 mutex_unlock(&dev->struct_mutex);
2275                 DRM_ERROR("failed to update base address\n");
2276                 return ret;
2277         }
2278
2279         old_fb = crtc->fb;
2280         crtc->fb = fb;
2281         crtc->x = x;
2282         crtc->y = y;
2283
2284         if (old_fb) {
2285                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2286                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2287         }
2288
2289         intel_update_fbc(dev);
2290         mutex_unlock(&dev->struct_mutex);
2291
2292         intel_crtc_update_sarea_pos(crtc, x, y);
2293
2294         return 0;
2295 }
2296
2297 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2298 {
2299         struct drm_device *dev = crtc->dev;
2300         struct drm_i915_private *dev_priv = dev->dev_private;
2301         u32 dpa_ctl;
2302
2303         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2304         dpa_ctl = I915_READ(DP_A);
2305         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2306
2307         if (clock < 200000) {
2308                 u32 temp;
2309                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2310                 /* workaround for 160Mhz:
2311                    1) program 0x4600c bits 15:0 = 0x8124
2312                    2) program 0x46010 bit 0 = 1
2313                    3) program 0x46034 bit 24 = 1
2314                    4) program 0x64000 bit 14 = 1
2315                    */
2316                 temp = I915_READ(0x4600c);
2317                 temp &= 0xffff0000;
2318                 I915_WRITE(0x4600c, temp | 0x8124);
2319
2320                 temp = I915_READ(0x46010);
2321                 I915_WRITE(0x46010, temp | 1);
2322
2323                 temp = I915_READ(0x46034);
2324                 I915_WRITE(0x46034, temp | (1 << 24));
2325         } else {
2326                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2327         }
2328         I915_WRITE(DP_A, dpa_ctl);
2329
2330         POSTING_READ(DP_A);
2331         udelay(500);
2332 }
2333
2334 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2335 {
2336         struct drm_device *dev = crtc->dev;
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2339         int pipe = intel_crtc->pipe;
2340         u32 reg, temp;
2341
2342         /* enable normal train */
2343         reg = FDI_TX_CTL(pipe);
2344         temp = I915_READ(reg);
2345         if (IS_IVYBRIDGE(dev)) {
2346                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2347                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2348         } else {
2349                 temp &= ~FDI_LINK_TRAIN_NONE;
2350                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2351         }
2352         I915_WRITE(reg, temp);
2353
2354         reg = FDI_RX_CTL(pipe);
2355         temp = I915_READ(reg);
2356         if (HAS_PCH_CPT(dev)) {
2357                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2358                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2359         } else {
2360                 temp &= ~FDI_LINK_TRAIN_NONE;
2361                 temp |= FDI_LINK_TRAIN_NONE;
2362         }
2363         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2364
2365         /* wait one idle pattern time */
2366         POSTING_READ(reg);
2367         udelay(1000);
2368
2369         /* IVB wants error correction enabled */
2370         if (IS_IVYBRIDGE(dev))
2371                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2372                            FDI_FE_ERRC_ENABLE);
2373 }
2374
2375 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2376 {
2377         struct drm_i915_private *dev_priv = dev->dev_private;
2378         u32 flags = I915_READ(SOUTH_CHICKEN1);
2379
2380         flags |= FDI_PHASE_SYNC_OVR(pipe);
2381         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2382         flags |= FDI_PHASE_SYNC_EN(pipe);
2383         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2384         POSTING_READ(SOUTH_CHICKEN1);
2385 }
2386
2387 static void ivb_modeset_global_resources(struct drm_device *dev)
2388 {
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         struct intel_crtc *pipe_B_crtc =
2391                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2392         struct intel_crtc *pipe_C_crtc =
2393                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2394         uint32_t temp;
2395
2396         /* When everything is off disable fdi C so that we could enable fdi B
2397          * with all lanes. XXX: This misses the case where a pipe is not using
2398          * any pch resources and so doesn't need any fdi lanes. */
2399         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2400                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2401                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2402
2403                 temp = I915_READ(SOUTH_CHICKEN1);
2404                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2405                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2406                 I915_WRITE(SOUTH_CHICKEN1, temp);
2407         }
2408 }
2409
2410 /* The FDI link training functions for ILK/Ibexpeak. */
2411 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2412 {
2413         struct drm_device *dev = crtc->dev;
2414         struct drm_i915_private *dev_priv = dev->dev_private;
2415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2416         int pipe = intel_crtc->pipe;
2417         int plane = intel_crtc->plane;
2418         u32 reg, temp, tries;
2419
2420         /* FDI needs bits from pipe & plane first */
2421         assert_pipe_enabled(dev_priv, pipe);
2422         assert_plane_enabled(dev_priv, plane);
2423
2424         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2425            for train result */
2426         reg = FDI_RX_IMR(pipe);
2427         temp = I915_READ(reg);
2428         temp &= ~FDI_RX_SYMBOL_LOCK;
2429         temp &= ~FDI_RX_BIT_LOCK;
2430         I915_WRITE(reg, temp);
2431         I915_READ(reg);
2432         udelay(150);
2433
2434         /* enable CPU FDI TX and PCH FDI RX */
2435         reg = FDI_TX_CTL(pipe);
2436         temp = I915_READ(reg);
2437         temp &= ~(7 << 19);
2438         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2439         temp &= ~FDI_LINK_TRAIN_NONE;
2440         temp |= FDI_LINK_TRAIN_PATTERN_1;
2441         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2442
2443         reg = FDI_RX_CTL(pipe);
2444         temp = I915_READ(reg);
2445         temp &= ~FDI_LINK_TRAIN_NONE;
2446         temp |= FDI_LINK_TRAIN_PATTERN_1;
2447         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2448
2449         POSTING_READ(reg);
2450         udelay(150);
2451
2452         /* Ironlake workaround, enable clock pointer after FDI enable*/
2453         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2454         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2455                    FDI_RX_PHASE_SYNC_POINTER_EN);
2456
2457         reg = FDI_RX_IIR(pipe);
2458         for (tries = 0; tries < 5; tries++) {
2459                 temp = I915_READ(reg);
2460                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2461
2462                 if ((temp & FDI_RX_BIT_LOCK)) {
2463                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2464                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2465                         break;
2466                 }
2467         }
2468         if (tries == 5)
2469                 DRM_ERROR("FDI train 1 fail!\n");
2470
2471         /* Train 2 */
2472         reg = FDI_TX_CTL(pipe);
2473         temp = I915_READ(reg);
2474         temp &= ~FDI_LINK_TRAIN_NONE;
2475         temp |= FDI_LINK_TRAIN_PATTERN_2;
2476         I915_WRITE(reg, temp);
2477
2478         reg = FDI_RX_CTL(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_LINK_TRAIN_NONE;
2481         temp |= FDI_LINK_TRAIN_PATTERN_2;
2482         I915_WRITE(reg, temp);
2483
2484         POSTING_READ(reg);
2485         udelay(150);
2486
2487         reg = FDI_RX_IIR(pipe);
2488         for (tries = 0; tries < 5; tries++) {
2489                 temp = I915_READ(reg);
2490                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2491
2492                 if (temp & FDI_RX_SYMBOL_LOCK) {
2493                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2494                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2495                         break;
2496                 }
2497         }
2498         if (tries == 5)
2499                 DRM_ERROR("FDI train 2 fail!\n");
2500
2501         DRM_DEBUG_KMS("FDI train done\n");
2502
2503 }
2504
2505 static const int snb_b_fdi_train_param[] = {
2506         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2507         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2508         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2509         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2510 };
2511
2512 /* The FDI link training functions for SNB/Cougarpoint. */
2513 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2514 {
2515         struct drm_device *dev = crtc->dev;
2516         struct drm_i915_private *dev_priv = dev->dev_private;
2517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2518         int pipe = intel_crtc->pipe;
2519         u32 reg, temp, i, retry;
2520
2521         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2522            for train result */
2523         reg = FDI_RX_IMR(pipe);
2524         temp = I915_READ(reg);
2525         temp &= ~FDI_RX_SYMBOL_LOCK;
2526         temp &= ~FDI_RX_BIT_LOCK;
2527         I915_WRITE(reg, temp);
2528
2529         POSTING_READ(reg);
2530         udelay(150);
2531
2532         /* enable CPU FDI TX and PCH FDI RX */
2533         reg = FDI_TX_CTL(pipe);
2534         temp = I915_READ(reg);
2535         temp &= ~(7 << 19);
2536         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2537         temp &= ~FDI_LINK_TRAIN_NONE;
2538         temp |= FDI_LINK_TRAIN_PATTERN_1;
2539         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2540         /* SNB-B */
2541         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2542         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2543
2544         I915_WRITE(FDI_RX_MISC(pipe),
2545                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2546
2547         reg = FDI_RX_CTL(pipe);
2548         temp = I915_READ(reg);
2549         if (HAS_PCH_CPT(dev)) {
2550                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2551                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2552         } else {
2553                 temp &= ~FDI_LINK_TRAIN_NONE;
2554                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2555         }
2556         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2557
2558         POSTING_READ(reg);
2559         udelay(150);
2560
2561         cpt_phase_pointer_enable(dev, pipe);
2562
2563         for (i = 0; i < 4; i++) {
2564                 reg = FDI_TX_CTL(pipe);
2565                 temp = I915_READ(reg);
2566                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567                 temp |= snb_b_fdi_train_param[i];
2568                 I915_WRITE(reg, temp);
2569
2570                 POSTING_READ(reg);
2571                 udelay(500);
2572
2573                 for (retry = 0; retry < 5; retry++) {
2574                         reg = FDI_RX_IIR(pipe);
2575                         temp = I915_READ(reg);
2576                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2577                         if (temp & FDI_RX_BIT_LOCK) {
2578                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2579                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2580                                 break;
2581                         }
2582                         udelay(50);
2583                 }
2584                 if (retry < 5)
2585                         break;
2586         }
2587         if (i == 4)
2588                 DRM_ERROR("FDI train 1 fail!\n");
2589
2590         /* Train 2 */
2591         reg = FDI_TX_CTL(pipe);
2592         temp = I915_READ(reg);
2593         temp &= ~FDI_LINK_TRAIN_NONE;
2594         temp |= FDI_LINK_TRAIN_PATTERN_2;
2595         if (IS_GEN6(dev)) {
2596                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2597                 /* SNB-B */
2598                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599         }
2600         I915_WRITE(reg, temp);
2601
2602         reg = FDI_RX_CTL(pipe);
2603         temp = I915_READ(reg);
2604         if (HAS_PCH_CPT(dev)) {
2605                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2606                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2607         } else {
2608                 temp &= ~FDI_LINK_TRAIN_NONE;
2609                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2610         }
2611         I915_WRITE(reg, temp);
2612
2613         POSTING_READ(reg);
2614         udelay(150);
2615
2616         for (i = 0; i < 4; i++) {
2617                 reg = FDI_TX_CTL(pipe);
2618                 temp = I915_READ(reg);
2619                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2620                 temp |= snb_b_fdi_train_param[i];
2621                 I915_WRITE(reg, temp);
2622
2623                 POSTING_READ(reg);
2624                 udelay(500);
2625
2626                 for (retry = 0; retry < 5; retry++) {
2627                         reg = FDI_RX_IIR(pipe);
2628                         temp = I915_READ(reg);
2629                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2630                         if (temp & FDI_RX_SYMBOL_LOCK) {
2631                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2632                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2633                                 break;
2634                         }
2635                         udelay(50);
2636                 }
2637                 if (retry < 5)
2638                         break;
2639         }
2640         if (i == 4)
2641                 DRM_ERROR("FDI train 2 fail!\n");
2642
2643         DRM_DEBUG_KMS("FDI train done.\n");
2644 }
2645
2646 /* Manual link training for Ivy Bridge A0 parts */
2647 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2648 {
2649         struct drm_device *dev = crtc->dev;
2650         struct drm_i915_private *dev_priv = dev->dev_private;
2651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2652         int pipe = intel_crtc->pipe;
2653         u32 reg, temp, i;
2654
2655         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2656            for train result */
2657         reg = FDI_RX_IMR(pipe);
2658         temp = I915_READ(reg);
2659         temp &= ~FDI_RX_SYMBOL_LOCK;
2660         temp &= ~FDI_RX_BIT_LOCK;
2661         I915_WRITE(reg, temp);
2662
2663         POSTING_READ(reg);
2664         udelay(150);
2665
2666         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2667                       I915_READ(FDI_RX_IIR(pipe)));
2668
2669         /* enable CPU FDI TX and PCH FDI RX */
2670         reg = FDI_TX_CTL(pipe);
2671         temp = I915_READ(reg);
2672         temp &= ~(7 << 19);
2673         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2674         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2675         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2676         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2677         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2678         temp |= FDI_COMPOSITE_SYNC;
2679         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2680
2681         I915_WRITE(FDI_RX_MISC(pipe),
2682                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2683
2684         reg = FDI_RX_CTL(pipe);
2685         temp = I915_READ(reg);
2686         temp &= ~FDI_LINK_TRAIN_AUTO;
2687         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2688         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2689         temp |= FDI_COMPOSITE_SYNC;
2690         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2691
2692         POSTING_READ(reg);
2693         udelay(150);
2694
2695         cpt_phase_pointer_enable(dev, pipe);
2696
2697         for (i = 0; i < 4; i++) {
2698                 reg = FDI_TX_CTL(pipe);
2699                 temp = I915_READ(reg);
2700                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701                 temp |= snb_b_fdi_train_param[i];
2702                 I915_WRITE(reg, temp);
2703
2704                 POSTING_READ(reg);
2705                 udelay(500);
2706
2707                 reg = FDI_RX_IIR(pipe);
2708                 temp = I915_READ(reg);
2709                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2710
2711                 if (temp & FDI_RX_BIT_LOCK ||
2712                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2713                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2714                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2715                         break;
2716                 }
2717         }
2718         if (i == 4)
2719                 DRM_ERROR("FDI train 1 fail!\n");
2720
2721         /* Train 2 */
2722         reg = FDI_TX_CTL(pipe);
2723         temp = I915_READ(reg);
2724         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2725         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2726         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2727         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2728         I915_WRITE(reg, temp);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2733         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2734         I915_WRITE(reg, temp);
2735
2736         POSTING_READ(reg);
2737         udelay(150);
2738
2739         for (i = 0; i < 4; i++) {
2740                 reg = FDI_TX_CTL(pipe);
2741                 temp = I915_READ(reg);
2742                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743                 temp |= snb_b_fdi_train_param[i];
2744                 I915_WRITE(reg, temp);
2745
2746                 POSTING_READ(reg);
2747                 udelay(500);
2748
2749                 reg = FDI_RX_IIR(pipe);
2750                 temp = I915_READ(reg);
2751                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753                 if (temp & FDI_RX_SYMBOL_LOCK) {
2754                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2755                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2756                         break;
2757                 }
2758         }
2759         if (i == 4)
2760                 DRM_ERROR("FDI train 2 fail!\n");
2761
2762         DRM_DEBUG_KMS("FDI train done.\n");
2763 }
2764
2765 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2766 {
2767         struct drm_device *dev = intel_crtc->base.dev;
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         int pipe = intel_crtc->pipe;
2770         u32 reg, temp;
2771
2772
2773         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2774         reg = FDI_RX_CTL(pipe);
2775         temp = I915_READ(reg);
2776         temp &= ~((0x7 << 19) | (0x7 << 16));
2777         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2778         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2779         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2780
2781         POSTING_READ(reg);
2782         udelay(200);
2783
2784         /* Switch from Rawclk to PCDclk */
2785         temp = I915_READ(reg);
2786         I915_WRITE(reg, temp | FDI_PCDCLK);
2787
2788         POSTING_READ(reg);
2789         udelay(200);
2790
2791         /* Enable CPU FDI TX PLL, always on for Ironlake */
2792         reg = FDI_TX_CTL(pipe);
2793         temp = I915_READ(reg);
2794         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2795                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2796
2797                 POSTING_READ(reg);
2798                 udelay(100);
2799         }
2800 }
2801
2802 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2803 {
2804         struct drm_device *dev = intel_crtc->base.dev;
2805         struct drm_i915_private *dev_priv = dev->dev_private;
2806         int pipe = intel_crtc->pipe;
2807         u32 reg, temp;
2808
2809         /* Switch from PCDclk to Rawclk */
2810         reg = FDI_RX_CTL(pipe);
2811         temp = I915_READ(reg);
2812         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2813
2814         /* Disable CPU FDI TX PLL */
2815         reg = FDI_TX_CTL(pipe);
2816         temp = I915_READ(reg);
2817         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2818
2819         POSTING_READ(reg);
2820         udelay(100);
2821
2822         reg = FDI_RX_CTL(pipe);
2823         temp = I915_READ(reg);
2824         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2825
2826         /* Wait for the clocks to turn off. */
2827         POSTING_READ(reg);
2828         udelay(100);
2829 }
2830
2831 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2832 {
2833         struct drm_i915_private *dev_priv = dev->dev_private;
2834         u32 flags = I915_READ(SOUTH_CHICKEN1);
2835
2836         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2837         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2838         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2839         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2840         POSTING_READ(SOUTH_CHICKEN1);
2841 }
2842 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2843 {
2844         struct drm_device *dev = crtc->dev;
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2847         int pipe = intel_crtc->pipe;
2848         u32 reg, temp;
2849
2850         /* disable CPU FDI tx and PCH FDI rx */
2851         reg = FDI_TX_CTL(pipe);
2852         temp = I915_READ(reg);
2853         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2854         POSTING_READ(reg);
2855
2856         reg = FDI_RX_CTL(pipe);
2857         temp = I915_READ(reg);
2858         temp &= ~(0x7 << 16);
2859         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2860         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2861
2862         POSTING_READ(reg);
2863         udelay(100);
2864
2865         /* Ironlake workaround, disable clock pointer after downing FDI */
2866         if (HAS_PCH_IBX(dev)) {
2867                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2868         } else if (HAS_PCH_CPT(dev)) {
2869                 cpt_phase_pointer_disable(dev, pipe);
2870         }
2871
2872         /* still set train pattern 1 */
2873         reg = FDI_TX_CTL(pipe);
2874         temp = I915_READ(reg);
2875         temp &= ~FDI_LINK_TRAIN_NONE;
2876         temp |= FDI_LINK_TRAIN_PATTERN_1;
2877         I915_WRITE(reg, temp);
2878
2879         reg = FDI_RX_CTL(pipe);
2880         temp = I915_READ(reg);
2881         if (HAS_PCH_CPT(dev)) {
2882                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2883                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2884         } else {
2885                 temp &= ~FDI_LINK_TRAIN_NONE;
2886                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2887         }
2888         /* BPC in FDI rx is consistent with that in PIPECONF */
2889         temp &= ~(0x07 << 16);
2890         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2891         I915_WRITE(reg, temp);
2892
2893         POSTING_READ(reg);
2894         udelay(100);
2895 }
2896
2897 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2898 {
2899         struct drm_device *dev = crtc->dev;
2900         struct drm_i915_private *dev_priv = dev->dev_private;
2901         unsigned long flags;
2902         bool pending;
2903
2904         if (atomic_read(&dev_priv->mm.wedged))
2905                 return false;
2906
2907         spin_lock_irqsave(&dev->event_lock, flags);
2908         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2909         spin_unlock_irqrestore(&dev->event_lock, flags);
2910
2911         return pending;
2912 }
2913
2914 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2915 {
2916         struct drm_device *dev = crtc->dev;
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918
2919         if (crtc->fb == NULL)
2920                 return;
2921
2922         wait_event(dev_priv->pending_flip_queue,
2923                    !intel_crtc_has_pending_flip(crtc));
2924
2925         mutex_lock(&dev->struct_mutex);
2926         intel_finish_fb(crtc->fb);
2927         mutex_unlock(&dev->struct_mutex);
2928 }
2929
2930 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2931 {
2932         struct drm_device *dev = crtc->dev;
2933         struct intel_encoder *intel_encoder;
2934
2935         /*
2936          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2937          * must be driven by its own crtc; no sharing is possible.
2938          */
2939         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2940                 switch (intel_encoder->type) {
2941                 case INTEL_OUTPUT_EDP:
2942                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2943                                 return false;
2944                         continue;
2945                 }
2946         }
2947
2948         return true;
2949 }
2950
2951 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2952 {
2953         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2954 }
2955
2956 /* Program iCLKIP clock to the desired frequency */
2957 static void lpt_program_iclkip(struct drm_crtc *crtc)
2958 {
2959         struct drm_device *dev = crtc->dev;
2960         struct drm_i915_private *dev_priv = dev->dev_private;
2961         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2962         u32 temp;
2963
2964         /* It is necessary to ungate the pixclk gate prior to programming
2965          * the divisors, and gate it back when it is done.
2966          */
2967         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2968
2969         /* Disable SSCCTL */
2970         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2971                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2972                                         SBI_SSCCTL_DISABLE);
2973
2974         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2975         if (crtc->mode.clock == 20000) {
2976                 auxdiv = 1;
2977                 divsel = 0x41;
2978                 phaseinc = 0x20;
2979         } else {
2980                 /* The iCLK virtual clock root frequency is in MHz,
2981                  * but the crtc->mode.clock in in KHz. To get the divisors,
2982                  * it is necessary to divide one by another, so we
2983                  * convert the virtual clock precision to KHz here for higher
2984                  * precision.
2985                  */
2986                 u32 iclk_virtual_root_freq = 172800 * 1000;
2987                 u32 iclk_pi_range = 64;
2988                 u32 desired_divisor, msb_divisor_value, pi_value;
2989
2990                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2991                 msb_divisor_value = desired_divisor / iclk_pi_range;
2992                 pi_value = desired_divisor % iclk_pi_range;
2993
2994                 auxdiv = 0;
2995                 divsel = msb_divisor_value - 2;
2996                 phaseinc = pi_value;
2997         }
2998
2999         /* This should not happen with any sane values */
3000         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3001                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3002         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3003                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3004
3005         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3006                         crtc->mode.clock,
3007                         auxdiv,
3008                         divsel,
3009                         phasedir,
3010                         phaseinc);
3011
3012         /* Program SSCDIVINTPHASE6 */
3013         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3014         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3015         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3016         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3017         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3018         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3019         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3020
3021         intel_sbi_write(dev_priv,
3022                         SBI_SSCDIVINTPHASE6,
3023                         temp);
3024
3025         /* Program SSCAUXDIV */
3026         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3027         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3028         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3029         intel_sbi_write(dev_priv,
3030                         SBI_SSCAUXDIV6,
3031                         temp);
3032
3033
3034         /* Enable modulator and associated divider */
3035         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3036         temp &= ~SBI_SSCCTL_DISABLE;
3037         intel_sbi_write(dev_priv,
3038                         SBI_SSCCTL6,
3039                         temp);
3040
3041         /* Wait for initialization time */
3042         udelay(24);
3043
3044         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3045 }
3046
3047 /*
3048  * Enable PCH resources required for PCH ports:
3049  *   - PCH PLLs
3050  *   - FDI training & RX/TX
3051  *   - update transcoder timings
3052  *   - DP transcoding bits
3053  *   - transcoder
3054  */
3055 static void ironlake_pch_enable(struct drm_crtc *crtc)
3056 {
3057         struct drm_device *dev = crtc->dev;
3058         struct drm_i915_private *dev_priv = dev->dev_private;
3059         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3060         int pipe = intel_crtc->pipe;
3061         u32 reg, temp;
3062
3063         assert_transcoder_disabled(dev_priv, pipe);
3064
3065         /* Write the TU size bits before fdi link training, so that error
3066          * detection works. */
3067         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3068                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3069
3070         /* For PCH output, training FDI link */
3071         dev_priv->display.fdi_link_train(crtc);
3072
3073         /* XXX: pch pll's can be enabled any time before we enable the PCH
3074          * transcoder, and we actually should do this to not upset any PCH
3075          * transcoder that already use the clock when we share it.
3076          *
3077          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3078          * unconditionally resets the pll - we need that to have the right LVDS
3079          * enable sequence. */
3080         ironlake_enable_pch_pll(intel_crtc);
3081
3082         if (HAS_PCH_CPT(dev)) {
3083                 u32 sel;
3084
3085                 temp = I915_READ(PCH_DPLL_SEL);
3086                 switch (pipe) {
3087                 default:
3088                 case 0:
3089                         temp |= TRANSA_DPLL_ENABLE;
3090                         sel = TRANSA_DPLLB_SEL;
3091                         break;
3092                 case 1:
3093                         temp |= TRANSB_DPLL_ENABLE;
3094                         sel = TRANSB_DPLLB_SEL;
3095                         break;
3096                 case 2:
3097                         temp |= TRANSC_DPLL_ENABLE;
3098                         sel = TRANSC_DPLLB_SEL;
3099                         break;
3100                 }
3101                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3102                         temp |= sel;
3103                 else
3104                         temp &= ~sel;
3105                 I915_WRITE(PCH_DPLL_SEL, temp);
3106         }
3107
3108         /* set transcoder timing, panel must allow it */
3109         assert_panel_unlocked(dev_priv, pipe);
3110         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3111         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3112         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3113
3114         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3115         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3116         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3117         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3118
3119         intel_fdi_normal_train(crtc);
3120
3121         /* For PCH DP, enable TRANS_DP_CTL */
3122         if (HAS_PCH_CPT(dev) &&
3123             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3124              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3125                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3126                 reg = TRANS_DP_CTL(pipe);
3127                 temp = I915_READ(reg);
3128                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3129                           TRANS_DP_SYNC_MASK |
3130                           TRANS_DP_BPC_MASK);
3131                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3132                          TRANS_DP_ENH_FRAMING);
3133                 temp |= bpc << 9; /* same format but at 11:9 */
3134
3135                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3136                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3137                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3138                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3139
3140                 switch (intel_trans_dp_port_sel(crtc)) {
3141                 case PCH_DP_B:
3142                         temp |= TRANS_DP_PORT_SEL_B;
3143                         break;
3144                 case PCH_DP_C:
3145                         temp |= TRANS_DP_PORT_SEL_C;
3146                         break;
3147                 case PCH_DP_D:
3148                         temp |= TRANS_DP_PORT_SEL_D;
3149                         break;
3150                 default:
3151                         BUG();
3152                 }
3153
3154                 I915_WRITE(reg, temp);
3155         }
3156
3157         ironlake_enable_pch_transcoder(dev_priv, pipe);
3158 }
3159
3160 static void lpt_pch_enable(struct drm_crtc *crtc)
3161 {
3162         struct drm_device *dev = crtc->dev;
3163         struct drm_i915_private *dev_priv = dev->dev_private;
3164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3165         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3166
3167         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3168
3169         lpt_program_iclkip(crtc);
3170
3171         /* Set transcoder timing. */
3172         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3173         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3174         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3175
3176         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3177         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3178         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3179         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3180
3181         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3182 }
3183
3184 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3185 {
3186         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3187
3188         if (pll == NULL)
3189                 return;
3190
3191         if (pll->refcount == 0) {
3192                 WARN(1, "bad PCH PLL refcount\n");
3193                 return;
3194         }
3195
3196         --pll->refcount;
3197         intel_crtc->pch_pll = NULL;
3198 }
3199
3200 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3201 {
3202         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3203         struct intel_pch_pll *pll;
3204         int i;
3205
3206         pll = intel_crtc->pch_pll;
3207         if (pll) {
3208                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3209                               intel_crtc->base.base.id, pll->pll_reg);
3210                 goto prepare;
3211         }
3212
3213         if (HAS_PCH_IBX(dev_priv->dev)) {
3214                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3215                 i = intel_crtc->pipe;
3216                 pll = &dev_priv->pch_plls[i];
3217
3218                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3219                               intel_crtc->base.base.id, pll->pll_reg);
3220
3221                 goto found;
3222         }
3223
3224         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3225                 pll = &dev_priv->pch_plls[i];
3226
3227                 /* Only want to check enabled timings first */
3228                 if (pll->refcount == 0)
3229                         continue;
3230
3231                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3232                     fp == I915_READ(pll->fp0_reg)) {
3233                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3234                                       intel_crtc->base.base.id,
3235                                       pll->pll_reg, pll->refcount, pll->active);
3236
3237                         goto found;
3238                 }
3239         }
3240
3241         /* Ok no matching timings, maybe there's a free one? */
3242         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3243                 pll = &dev_priv->pch_plls[i];
3244                 if (pll->refcount == 0) {
3245                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3246                                       intel_crtc->base.base.id, pll->pll_reg);
3247                         goto found;
3248                 }
3249         }
3250
3251         return NULL;
3252
3253 found:
3254         intel_crtc->pch_pll = pll;
3255         pll->refcount++;
3256         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3257 prepare: /* separate function? */
3258         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3259
3260         /* Wait for the clocks to stabilize before rewriting the regs */
3261         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3262         POSTING_READ(pll->pll_reg);
3263         udelay(150);
3264
3265         I915_WRITE(pll->fp0_reg, fp);
3266         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3267         pll->on = false;
3268         return pll;
3269 }
3270
3271 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3272 {
3273         struct drm_i915_private *dev_priv = dev->dev_private;
3274         int dslreg = PIPEDSL(pipe);
3275         u32 temp;
3276
3277         temp = I915_READ(dslreg);
3278         udelay(500);
3279         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3280                 if (wait_for(I915_READ(dslreg) != temp, 5))
3281                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3282         }
3283 }
3284
3285 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3286 {
3287         struct drm_device *dev = crtc->dev;
3288         struct drm_i915_private *dev_priv = dev->dev_private;
3289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290         struct intel_encoder *encoder;
3291         int pipe = intel_crtc->pipe;
3292         int plane = intel_crtc->plane;
3293         u32 temp;
3294         bool is_pch_port;
3295
3296         WARN_ON(!crtc->enabled);
3297
3298         if (intel_crtc->active)
3299                 return;
3300
3301         intel_crtc->active = true;
3302         intel_update_watermarks(dev);
3303
3304         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3305                 temp = I915_READ(PCH_LVDS);
3306                 if ((temp & LVDS_PORT_EN) == 0)
3307                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3308         }
3309
3310         is_pch_port = ironlake_crtc_driving_pch(crtc);
3311
3312         if (is_pch_port) {
3313                 /* Note: FDI PLL enabling _must_ be done before we enable the
3314                  * cpu pipes, hence this is separate from all the other fdi/pch
3315                  * enabling. */
3316                 ironlake_fdi_pll_enable(intel_crtc);
3317         } else {
3318                 assert_fdi_tx_disabled(dev_priv, pipe);
3319                 assert_fdi_rx_disabled(dev_priv, pipe);
3320         }
3321
3322         for_each_encoder_on_crtc(dev, crtc, encoder)
3323                 if (encoder->pre_enable)
3324                         encoder->pre_enable(encoder);
3325
3326         /* Enable panel fitting for LVDS */
3327         if (dev_priv->pch_pf_size &&
3328             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3329              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3330                 /* Force use of hard-coded filter coefficients
3331                  * as some pre-programmed values are broken,
3332                  * e.g. x201.
3333                  */
3334                 if (IS_IVYBRIDGE(dev))
3335                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3336                                                  PF_PIPE_SEL_IVB(pipe));
3337                 else
3338                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3339                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3340                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3341         }
3342
3343         /*
3344          * On ILK+ LUT must be loaded before the pipe is running but with
3345          * clocks enabled
3346          */
3347         intel_crtc_load_lut(crtc);
3348
3349         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3350         intel_enable_plane(dev_priv, plane, pipe);
3351
3352         if (is_pch_port)
3353                 ironlake_pch_enable(crtc);
3354
3355         mutex_lock(&dev->struct_mutex);
3356         intel_update_fbc(dev);
3357         mutex_unlock(&dev->struct_mutex);
3358
3359         intel_crtc_update_cursor(crtc, true);
3360
3361         for_each_encoder_on_crtc(dev, crtc, encoder)
3362                 encoder->enable(encoder);
3363
3364         if (HAS_PCH_CPT(dev))
3365                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3366
3367         /*
3368          * There seems to be a race in PCH platform hw (at least on some
3369          * outputs) where an enabled pipe still completes any pageflip right
3370          * away (as if the pipe is off) instead of waiting for vblank. As soon
3371          * as the first vblank happend, everything works as expected. Hence just
3372          * wait for one vblank before returning to avoid strange things
3373          * happening.
3374          */
3375         intel_wait_for_vblank(dev, intel_crtc->pipe);
3376 }
3377
3378 static void haswell_crtc_enable(struct drm_crtc *crtc)
3379 {
3380         struct drm_device *dev = crtc->dev;
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383         struct intel_encoder *encoder;
3384         int pipe = intel_crtc->pipe;
3385         int plane = intel_crtc->plane;
3386         bool is_pch_port;
3387
3388         WARN_ON(!crtc->enabled);
3389
3390         if (intel_crtc->active)
3391                 return;
3392
3393         intel_crtc->active = true;
3394         intel_update_watermarks(dev);
3395
3396         is_pch_port = haswell_crtc_driving_pch(crtc);
3397
3398         if (is_pch_port)
3399                 dev_priv->display.fdi_link_train(crtc);
3400
3401         for_each_encoder_on_crtc(dev, crtc, encoder)
3402                 if (encoder->pre_enable)
3403                         encoder->pre_enable(encoder);
3404
3405         intel_ddi_enable_pipe_clock(intel_crtc);
3406
3407         /* Enable panel fitting for eDP */
3408         if (dev_priv->pch_pf_size &&
3409             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3410                 /* Force use of hard-coded filter coefficients
3411                  * as some pre-programmed values are broken,
3412                  * e.g. x201.
3413                  */
3414                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3415                                          PF_PIPE_SEL_IVB(pipe));
3416                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3417                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3418         }
3419
3420         /*
3421          * On ILK+ LUT must be loaded before the pipe is running but with
3422          * clocks enabled
3423          */
3424         intel_crtc_load_lut(crtc);
3425
3426         intel_ddi_set_pipe_settings(crtc);
3427         intel_ddi_enable_pipe_func(crtc);
3428
3429         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3430         intel_enable_plane(dev_priv, plane, pipe);
3431
3432         if (is_pch_port)
3433                 lpt_pch_enable(crtc);
3434
3435         mutex_lock(&dev->struct_mutex);
3436         intel_update_fbc(dev);
3437         mutex_unlock(&dev->struct_mutex);
3438
3439         intel_crtc_update_cursor(crtc, true);
3440
3441         for_each_encoder_on_crtc(dev, crtc, encoder)
3442                 encoder->enable(encoder);
3443
3444         /*
3445          * There seems to be a race in PCH platform hw (at least on some
3446          * outputs) where an enabled pipe still completes any pageflip right
3447          * away (as if the pipe is off) instead of waiting for vblank. As soon
3448          * as the first vblank happend, everything works as expected. Hence just
3449          * wait for one vblank before returning to avoid strange things
3450          * happening.
3451          */
3452         intel_wait_for_vblank(dev, intel_crtc->pipe);
3453 }
3454
3455 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3456 {
3457         struct drm_device *dev = crtc->dev;
3458         struct drm_i915_private *dev_priv = dev->dev_private;
3459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3460         struct intel_encoder *encoder;
3461         int pipe = intel_crtc->pipe;
3462         int plane = intel_crtc->plane;
3463         u32 reg, temp;
3464
3465
3466         if (!intel_crtc->active)
3467                 return;
3468
3469         for_each_encoder_on_crtc(dev, crtc, encoder)
3470                 encoder->disable(encoder);
3471
3472         intel_crtc_wait_for_pending_flips(crtc);
3473         drm_vblank_off(dev, pipe);
3474         intel_crtc_update_cursor(crtc, false);
3475
3476         intel_disable_plane(dev_priv, plane, pipe);
3477
3478         if (dev_priv->cfb_plane == plane)
3479                 intel_disable_fbc(dev);
3480
3481         intel_disable_pipe(dev_priv, pipe);
3482
3483         /* Disable PF */
3484         I915_WRITE(PF_CTL(pipe), 0);
3485         I915_WRITE(PF_WIN_SZ(pipe), 0);
3486
3487         for_each_encoder_on_crtc(dev, crtc, encoder)
3488                 if (encoder->post_disable)
3489                         encoder->post_disable(encoder);
3490
3491         ironlake_fdi_disable(crtc);
3492
3493         ironlake_disable_pch_transcoder(dev_priv, pipe);
3494
3495         if (HAS_PCH_CPT(dev)) {
3496                 /* disable TRANS_DP_CTL */
3497                 reg = TRANS_DP_CTL(pipe);
3498                 temp = I915_READ(reg);
3499                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3500                 temp |= TRANS_DP_PORT_SEL_NONE;
3501                 I915_WRITE(reg, temp);
3502
3503                 /* disable DPLL_SEL */
3504                 temp = I915_READ(PCH_DPLL_SEL);
3505                 switch (pipe) {
3506                 case 0:
3507                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3508                         break;
3509                 case 1:
3510                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3511                         break;
3512                 case 2:
3513                         /* C shares PLL A or B */
3514                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3515                         break;
3516                 default:
3517                         BUG(); /* wtf */
3518                 }
3519                 I915_WRITE(PCH_DPLL_SEL, temp);
3520         }
3521
3522         /* disable PCH DPLL */
3523         intel_disable_pch_pll(intel_crtc);
3524
3525         ironlake_fdi_pll_disable(intel_crtc);
3526
3527         intel_crtc->active = false;
3528         intel_update_watermarks(dev);
3529
3530         mutex_lock(&dev->struct_mutex);
3531         intel_update_fbc(dev);
3532         mutex_unlock(&dev->struct_mutex);
3533 }
3534
3535 static void haswell_crtc_disable(struct drm_crtc *crtc)
3536 {
3537         struct drm_device *dev = crtc->dev;
3538         struct drm_i915_private *dev_priv = dev->dev_private;
3539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3540         struct intel_encoder *encoder;
3541         int pipe = intel_crtc->pipe;
3542         int plane = intel_crtc->plane;
3543         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3544         bool is_pch_port;
3545
3546         if (!intel_crtc->active)
3547                 return;
3548
3549         is_pch_port = haswell_crtc_driving_pch(crtc);
3550
3551         for_each_encoder_on_crtc(dev, crtc, encoder)
3552                 encoder->disable(encoder);
3553
3554         intel_crtc_wait_for_pending_flips(crtc);
3555         drm_vblank_off(dev, pipe);
3556         intel_crtc_update_cursor(crtc, false);
3557
3558         intel_disable_plane(dev_priv, plane, pipe);
3559
3560         if (dev_priv->cfb_plane == plane)
3561                 intel_disable_fbc(dev);
3562
3563         intel_disable_pipe(dev_priv, pipe);
3564
3565         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3566
3567         /* Disable PF */
3568         I915_WRITE(PF_CTL(pipe), 0);
3569         I915_WRITE(PF_WIN_SZ(pipe), 0);
3570
3571         intel_ddi_disable_pipe_clock(intel_crtc);
3572
3573         for_each_encoder_on_crtc(dev, crtc, encoder)
3574                 if (encoder->post_disable)
3575                         encoder->post_disable(encoder);
3576
3577         if (is_pch_port) {
3578                 lpt_disable_pch_transcoder(dev_priv);
3579                 intel_ddi_fdi_disable(crtc);
3580         }
3581
3582         intel_crtc->active = false;
3583         intel_update_watermarks(dev);
3584
3585         mutex_lock(&dev->struct_mutex);
3586         intel_update_fbc(dev);
3587         mutex_unlock(&dev->struct_mutex);
3588 }
3589
3590 static void ironlake_crtc_off(struct drm_crtc *crtc)
3591 {
3592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3593         intel_put_pch_pll(intel_crtc);
3594 }
3595
3596 static void haswell_crtc_off(struct drm_crtc *crtc)
3597 {
3598         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3599
3600         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3601          * start using it. */
3602         intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3603
3604         intel_ddi_put_crtc_pll(crtc);
3605 }
3606
3607 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3608 {
3609         if (!enable && intel_crtc->overlay) {
3610                 struct drm_device *dev = intel_crtc->base.dev;
3611                 struct drm_i915_private *dev_priv = dev->dev_private;
3612
3613                 mutex_lock(&dev->struct_mutex);
3614                 dev_priv->mm.interruptible = false;
3615                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3616                 dev_priv->mm.interruptible = true;
3617                 mutex_unlock(&dev->struct_mutex);
3618         }
3619
3620         /* Let userspace switch the overlay on again. In most cases userspace
3621          * has to recompute where to put it anyway.
3622          */
3623 }
3624
3625 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3626 {
3627         struct drm_device *dev = crtc->dev;
3628         struct drm_i915_private *dev_priv = dev->dev_private;
3629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630         struct intel_encoder *encoder;
3631         int pipe = intel_crtc->pipe;
3632         int plane = intel_crtc->plane;
3633
3634         WARN_ON(!crtc->enabled);
3635
3636         if (intel_crtc->active)
3637                 return;
3638
3639         intel_crtc->active = true;
3640         intel_update_watermarks(dev);
3641
3642         intel_enable_pll(dev_priv, pipe);
3643         intel_enable_pipe(dev_priv, pipe, false);
3644         intel_enable_plane(dev_priv, plane, pipe);
3645
3646         intel_crtc_load_lut(crtc);
3647         intel_update_fbc(dev);
3648
3649         /* Give the overlay scaler a chance to enable if it's on this pipe */
3650         intel_crtc_dpms_overlay(intel_crtc, true);
3651         intel_crtc_update_cursor(crtc, true);
3652
3653         for_each_encoder_on_crtc(dev, crtc, encoder)
3654                 encoder->enable(encoder);
3655 }
3656
3657 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3658 {
3659         struct drm_device *dev = crtc->dev;
3660         struct drm_i915_private *dev_priv = dev->dev_private;
3661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3662         struct intel_encoder *encoder;
3663         int pipe = intel_crtc->pipe;
3664         int plane = intel_crtc->plane;
3665
3666
3667         if (!intel_crtc->active)
3668                 return;
3669
3670         for_each_encoder_on_crtc(dev, crtc, encoder)
3671                 encoder->disable(encoder);
3672
3673         /* Give the overlay scaler a chance to disable if it's on this pipe */
3674         intel_crtc_wait_for_pending_flips(crtc);
3675         drm_vblank_off(dev, pipe);
3676         intel_crtc_dpms_overlay(intel_crtc, false);
3677         intel_crtc_update_cursor(crtc, false);
3678
3679         if (dev_priv->cfb_plane == plane)
3680                 intel_disable_fbc(dev);
3681
3682         intel_disable_plane(dev_priv, plane, pipe);
3683         intel_disable_pipe(dev_priv, pipe);
3684         intel_disable_pll(dev_priv, pipe);
3685
3686         intel_crtc->active = false;
3687         intel_update_fbc(dev);
3688         intel_update_watermarks(dev);
3689 }
3690
3691 static void i9xx_crtc_off(struct drm_crtc *crtc)
3692 {
3693 }
3694
3695 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3696                                     bool enabled)
3697 {
3698         struct drm_device *dev = crtc->dev;
3699         struct drm_i915_master_private *master_priv;
3700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3701         int pipe = intel_crtc->pipe;
3702
3703         if (!dev->primary->master)
3704                 return;
3705
3706         master_priv = dev->primary->master->driver_priv;
3707         if (!master_priv->sarea_priv)
3708                 return;
3709
3710         switch (pipe) {
3711         case 0:
3712                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3713                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3714                 break;
3715         case 1:
3716                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3717                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3718                 break;
3719         default:
3720                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3721                 break;
3722         }
3723 }
3724
3725 /**
3726  * Sets the power management mode of the pipe and plane.
3727  */
3728 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3729 {
3730         struct drm_device *dev = crtc->dev;
3731         struct drm_i915_private *dev_priv = dev->dev_private;
3732         struct intel_encoder *intel_encoder;
3733         bool enable = false;
3734
3735         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3736                 enable |= intel_encoder->connectors_active;
3737
3738         if (enable)
3739                 dev_priv->display.crtc_enable(crtc);
3740         else
3741                 dev_priv->display.crtc_disable(crtc);
3742
3743         intel_crtc_update_sarea(crtc, enable);
3744 }
3745
3746 static void intel_crtc_noop(struct drm_crtc *crtc)
3747 {
3748 }
3749
3750 static void intel_crtc_disable(struct drm_crtc *crtc)
3751 {
3752         struct drm_device *dev = crtc->dev;
3753         struct drm_connector *connector;
3754         struct drm_i915_private *dev_priv = dev->dev_private;
3755
3756         /* crtc should still be enabled when we disable it. */
3757         WARN_ON(!crtc->enabled);
3758
3759         dev_priv->display.crtc_disable(crtc);
3760         intel_crtc_update_sarea(crtc, false);
3761         dev_priv->display.off(crtc);
3762
3763         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3764         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3765
3766         if (crtc->fb) {
3767                 mutex_lock(&dev->struct_mutex);
3768                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3769                 mutex_unlock(&dev->struct_mutex);
3770                 crtc->fb = NULL;
3771         }
3772
3773         /* Update computed state. */
3774         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3775                 if (!connector->encoder || !connector->encoder->crtc)
3776                         continue;
3777
3778                 if (connector->encoder->crtc != crtc)
3779                         continue;
3780
3781                 connector->dpms = DRM_MODE_DPMS_OFF;
3782                 to_intel_encoder(connector->encoder)->connectors_active = false;
3783         }
3784 }
3785
3786 void intel_modeset_disable(struct drm_device *dev)
3787 {
3788         struct drm_crtc *crtc;
3789
3790         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3791                 if (crtc->enabled)
3792                         intel_crtc_disable(crtc);
3793         }
3794 }
3795
3796 void intel_encoder_noop(struct drm_encoder *encoder)
3797 {
3798 }
3799
3800 void intel_encoder_destroy(struct drm_encoder *encoder)
3801 {
3802         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3803
3804         drm_encoder_cleanup(encoder);
3805         kfree(intel_encoder);
3806 }
3807
3808 /* Simple dpms helper for encodres with just one connector, no cloning and only
3809  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3810  * state of the entire output pipe. */
3811 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3812 {
3813         if (mode == DRM_MODE_DPMS_ON) {
3814                 encoder->connectors_active = true;
3815
3816                 intel_crtc_update_dpms(encoder->base.crtc);
3817         } else {
3818                 encoder->connectors_active = false;
3819
3820                 intel_crtc_update_dpms(encoder->base.crtc);
3821         }
3822 }
3823
3824 /* Cross check the actual hw state with our own modeset state tracking (and it's
3825  * internal consistency). */
3826 static void intel_connector_check_state(struct intel_connector *connector)
3827 {
3828         if (connector->get_hw_state(connector)) {
3829                 struct intel_encoder *encoder = connector->encoder;
3830                 struct drm_crtc *crtc;
3831                 bool encoder_enabled;
3832                 enum pipe pipe;
3833
3834                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3835                               connector->base.base.id,
3836                               drm_get_connector_name(&connector->base));
3837
3838                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3839                      "wrong connector dpms state\n");
3840                 WARN(connector->base.encoder != &encoder->base,
3841                      "active connector not linked to encoder\n");
3842                 WARN(!encoder->connectors_active,
3843                      "encoder->connectors_active not set\n");
3844
3845                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3846                 WARN(!encoder_enabled, "encoder not enabled\n");
3847                 if (WARN_ON(!encoder->base.crtc))
3848                         return;
3849
3850                 crtc = encoder->base.crtc;
3851
3852                 WARN(!crtc->enabled, "crtc not enabled\n");
3853                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3854                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3855                      "encoder active on the wrong pipe\n");
3856         }
3857 }
3858
3859 /* Even simpler default implementation, if there's really no special case to
3860  * consider. */
3861 void intel_connector_dpms(struct drm_connector *connector, int mode)
3862 {
3863         struct intel_encoder *encoder = intel_attached_encoder(connector);
3864
3865         /* All the simple cases only support two dpms states. */
3866         if (mode != DRM_MODE_DPMS_ON)
3867                 mode = DRM_MODE_DPMS_OFF;
3868
3869         if (mode == connector->dpms)
3870                 return;
3871
3872         connector->dpms = mode;
3873
3874         /* Only need to change hw state when actually enabled */
3875         if (encoder->base.crtc)
3876                 intel_encoder_dpms(encoder, mode);
3877         else
3878                 WARN_ON(encoder->connectors_active != false);
3879
3880         intel_modeset_check_state(connector->dev);
3881 }
3882
3883 /* Simple connector->get_hw_state implementation for encoders that support only
3884  * one connector and no cloning and hence the encoder state determines the state
3885  * of the connector. */
3886 bool intel_connector_get_hw_state(struct intel_connector *connector)
3887 {
3888         enum pipe pipe = 0;
3889         struct intel_encoder *encoder = connector->encoder;
3890
3891         return encoder->get_hw_state(encoder, &pipe);
3892 }
3893
3894 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3895                                   const struct drm_display_mode *mode,
3896                                   struct drm_display_mode *adjusted_mode)
3897 {
3898         struct drm_device *dev = crtc->dev;
3899
3900         if (HAS_PCH_SPLIT(dev)) {
3901                 /* FDI link clock is fixed at 2.7G */
3902                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3903                         return false;
3904         }
3905
3906         /* All interlaced capable intel hw wants timings in frames. Note though
3907          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3908          * timings, so we need to be careful not to clobber these.*/
3909         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3910                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3911
3912         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3913          * with a hsync front porch of 0.
3914          */
3915         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3916                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3917                 return false;
3918
3919         return true;
3920 }
3921
3922 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3923 {
3924         return 400000; /* FIXME */
3925 }
3926
3927 static int i945_get_display_clock_speed(struct drm_device *dev)
3928 {
3929         return 400000;
3930 }
3931
3932 static int i915_get_display_clock_speed(struct drm_device *dev)
3933 {
3934         return 333000;
3935 }
3936
3937 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3938 {
3939         return 200000;
3940 }
3941
3942 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3943 {
3944         u16 gcfgc = 0;
3945
3946         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3947
3948         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3949                 return 133000;
3950         else {
3951                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3952                 case GC_DISPLAY_CLOCK_333_MHZ:
3953                         return 333000;
3954                 default:
3955                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3956                         return 190000;
3957                 }
3958         }
3959 }
3960
3961 static int i865_get_display_clock_speed(struct drm_device *dev)
3962 {
3963         return 266000;
3964 }
3965
3966 static int i855_get_display_clock_speed(struct drm_device *dev)
3967 {
3968         u16 hpllcc = 0;
3969         /* Assume that the hardware is in the high speed state.  This
3970          * should be the default.
3971          */
3972         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3973         case GC_CLOCK_133_200:
3974         case GC_CLOCK_100_200:
3975                 return 200000;
3976         case GC_CLOCK_166_250:
3977                 return 250000;
3978         case GC_CLOCK_100_133:
3979                 return 133000;
3980         }
3981
3982         /* Shouldn't happen */
3983         return 0;
3984 }
3985
3986 static int i830_get_display_clock_speed(struct drm_device *dev)
3987 {
3988         return 133000;
3989 }
3990
3991 struct fdi_m_n {
3992         u32        tu;
3993         u32        gmch_m;
3994         u32        gmch_n;
3995         u32        link_m;
3996         u32        link_n;
3997 };
3998
3999 static void
4000 fdi_reduce_ratio(u32 *num, u32 *den)
4001 {
4002         while (*num > 0xffffff || *den > 0xffffff) {
4003                 *num >>= 1;
4004                 *den >>= 1;
4005         }
4006 }
4007
4008 static void
4009 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4010                      int link_clock, struct fdi_m_n *m_n)
4011 {
4012         m_n->tu = 64; /* default size */
4013
4014         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4015         m_n->gmch_m = bits_per_pixel * pixel_clock;
4016         m_n->gmch_n = link_clock * nlanes * 8;
4017         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4018
4019         m_n->link_m = pixel_clock;
4020         m_n->link_n = link_clock;
4021         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4022 }
4023
4024 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4025 {
4026         if (i915_panel_use_ssc >= 0)
4027                 return i915_panel_use_ssc != 0;
4028         return dev_priv->lvds_use_ssc
4029                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4030 }
4031
4032 /**
4033  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4034  * @crtc: CRTC structure
4035  * @mode: requested mode
4036  *
4037  * A pipe may be connected to one or more outputs.  Based on the depth of the
4038  * attached framebuffer, choose a good color depth to use on the pipe.
4039  *
4040  * If possible, match the pipe depth to the fb depth.  In some cases, this
4041  * isn't ideal, because the connected output supports a lesser or restricted
4042  * set of depths.  Resolve that here:
4043  *    LVDS typically supports only 6bpc, so clamp down in that case
4044  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4045  *    Displays may support a restricted set as well, check EDID and clamp as
4046  *      appropriate.
4047  *    DP may want to dither down to 6bpc to fit larger modes
4048  *
4049  * RETURNS:
4050  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4051  * true if they don't match).
4052  */
4053 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4054                                          struct drm_framebuffer *fb,
4055                                          unsigned int *pipe_bpp,
4056                                          struct drm_display_mode *mode)
4057 {
4058         struct drm_device *dev = crtc->dev;
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         struct drm_connector *connector;
4061         struct intel_encoder *intel_encoder;
4062         unsigned int display_bpc = UINT_MAX, bpc;
4063
4064         /* Walk the encoders & connectors on this crtc, get min bpc */
4065         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4066
4067                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4068                         unsigned int lvds_bpc;
4069
4070                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4071                             LVDS_A3_POWER_UP)
4072                                 lvds_bpc = 8;
4073                         else
4074                                 lvds_bpc = 6;
4075
4076                         if (lvds_bpc < display_bpc) {
4077                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4078                                 display_bpc = lvds_bpc;
4079                         }
4080                         continue;
4081                 }
4082
4083                 /* Not one of the known troublemakers, check the EDID */
4084                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4085                                     head) {
4086                         if (connector->encoder != &intel_encoder->base)
4087                                 continue;
4088
4089                         /* Don't use an invalid EDID bpc value */
4090                         if (connector->display_info.bpc &&
4091                             connector->display_info.bpc < display_bpc) {
4092                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4093                                 display_bpc = connector->display_info.bpc;
4094                         }
4095                 }
4096
4097                 /*
4098                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4099                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4100                  */
4101                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4102                         if (display_bpc > 8 && display_bpc < 12) {
4103                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4104                                 display_bpc = 12;
4105                         } else {
4106                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4107                                 display_bpc = 8;
4108                         }
4109                 }
4110         }
4111
4112         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4113                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4114                 display_bpc = 6;
4115         }
4116
4117         /*
4118          * We could just drive the pipe at the highest bpc all the time and
4119          * enable dithering as needed, but that costs bandwidth.  So choose
4120          * the minimum value that expresses the full color range of the fb but
4121          * also stays within the max display bpc discovered above.
4122          */
4123
4124         switch (fb->depth) {
4125         case 8:
4126                 bpc = 8; /* since we go through a colormap */
4127                 break;
4128         case 15:
4129         case 16:
4130                 bpc = 6; /* min is 18bpp */
4131                 break;
4132         case 24:
4133                 bpc = 8;
4134                 break;
4135         case 30:
4136                 bpc = 10;
4137                 break;
4138         case 48:
4139                 bpc = 12;
4140                 break;
4141         default:
4142                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4143                 bpc = min((unsigned int)8, display_bpc);
4144                 break;
4145         }
4146
4147         display_bpc = min(display_bpc, bpc);
4148
4149         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4150                       bpc, display_bpc);
4151
4152         *pipe_bpp = display_bpc * 3;
4153
4154         return display_bpc != bpc;
4155 }
4156
4157 static int vlv_get_refclk(struct drm_crtc *crtc)
4158 {
4159         struct drm_device *dev = crtc->dev;
4160         struct drm_i915_private *dev_priv = dev->dev_private;
4161         int refclk = 27000; /* for DP & HDMI */
4162
4163         return 100000; /* only one validated so far */
4164
4165         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4166                 refclk = 96000;
4167         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4168                 if (intel_panel_use_ssc(dev_priv))
4169                         refclk = 100000;
4170                 else
4171                         refclk = 96000;
4172         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4173                 refclk = 100000;
4174         }
4175
4176         return refclk;
4177 }
4178
4179 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4180 {
4181         struct drm_device *dev = crtc->dev;
4182         struct drm_i915_private *dev_priv = dev->dev_private;
4183         int refclk;
4184
4185         if (IS_VALLEYVIEW(dev)) {
4186                 refclk = vlv_get_refclk(crtc);
4187         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4188             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4189                 refclk = dev_priv->lvds_ssc_freq * 1000;
4190                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4191                               refclk / 1000);
4192         } else if (!IS_GEN2(dev)) {
4193                 refclk = 96000;
4194         } else {
4195                 refclk = 48000;
4196         }
4197
4198         return refclk;
4199 }
4200
4201 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4202                                       intel_clock_t *clock)
4203 {
4204         /* SDVO TV has fixed PLL values depend on its clock range,
4205            this mirrors vbios setting. */
4206         if (adjusted_mode->clock >= 100000
4207             && adjusted_mode->clock < 140500) {
4208                 clock->p1 = 2;
4209                 clock->p2 = 10;
4210                 clock->n = 3;
4211                 clock->m1 = 16;
4212                 clock->m2 = 8;
4213         } else if (adjusted_mode->clock >= 140500
4214                    && adjusted_mode->clock <= 200000) {
4215                 clock->p1 = 1;
4216                 clock->p2 = 10;
4217                 clock->n = 6;
4218                 clock->m1 = 12;
4219                 clock->m2 = 8;
4220         }
4221 }
4222
4223 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4224                                      intel_clock_t *clock,
4225                                      intel_clock_t *reduced_clock)
4226 {
4227         struct drm_device *dev = crtc->dev;
4228         struct drm_i915_private *dev_priv = dev->dev_private;
4229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4230         int pipe = intel_crtc->pipe;
4231         u32 fp, fp2 = 0;
4232
4233         if (IS_PINEVIEW(dev)) {
4234                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4235                 if (reduced_clock)
4236                         fp2 = (1 << reduced_clock->n) << 16 |
4237                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4238         } else {
4239                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4240                 if (reduced_clock)
4241                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4242                                 reduced_clock->m2;
4243         }
4244
4245         I915_WRITE(FP0(pipe), fp);
4246
4247         intel_crtc->lowfreq_avail = false;
4248         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4249             reduced_clock && i915_powersave) {
4250                 I915_WRITE(FP1(pipe), fp2);
4251                 intel_crtc->lowfreq_avail = true;
4252         } else {
4253                 I915_WRITE(FP1(pipe), fp);
4254         }
4255 }
4256
4257 static void vlv_update_pll(struct drm_crtc *crtc,
4258                            struct drm_display_mode *mode,
4259                            struct drm_display_mode *adjusted_mode,
4260                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4261                            int num_connectors)
4262 {
4263         struct drm_device *dev = crtc->dev;
4264         struct drm_i915_private *dev_priv = dev->dev_private;
4265         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4266         int pipe = intel_crtc->pipe;
4267         u32 dpll, mdiv, pdiv;
4268         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4269         bool is_sdvo;
4270         u32 temp;
4271
4272         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4273                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4274
4275         dpll = DPLL_VGA_MODE_DIS;
4276         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4277         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4278         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4279
4280         I915_WRITE(DPLL(pipe), dpll);
4281         POSTING_READ(DPLL(pipe));
4282
4283         bestn = clock->n;
4284         bestm1 = clock->m1;
4285         bestm2 = clock->m2;
4286         bestp1 = clock->p1;
4287         bestp2 = clock->p2;
4288
4289         /*
4290          * In Valleyview PLL and program lane counter registers are exposed
4291          * through DPIO interface
4292          */
4293         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4294         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4295         mdiv |= ((bestn << DPIO_N_SHIFT));
4296         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4297         mdiv |= (1 << DPIO_K_SHIFT);
4298         mdiv |= DPIO_ENABLE_CALIBRATION;
4299         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4300
4301         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4302
4303         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4304                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4305                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4306                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4307         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4308
4309         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4310
4311         dpll |= DPLL_VCO_ENABLE;
4312         I915_WRITE(DPLL(pipe), dpll);
4313         POSTING_READ(DPLL(pipe));
4314         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4315                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4316
4317         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4318
4319         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4320                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4321
4322         I915_WRITE(DPLL(pipe), dpll);
4323
4324         /* Wait for the clocks to stabilize. */
4325         POSTING_READ(DPLL(pipe));
4326         udelay(150);
4327
4328         temp = 0;
4329         if (is_sdvo) {
4330                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4331                 if (temp > 1)
4332                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4333                 else
4334                         temp = 0;
4335         }
4336         I915_WRITE(DPLL_MD(pipe), temp);
4337         POSTING_READ(DPLL_MD(pipe));
4338
4339         /* Now program lane control registers */
4340         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4341                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4342         {
4343                 temp = 0x1000C4;
4344                 if(pipe == 1)
4345                         temp |= (1 << 21);
4346                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4347         }
4348         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4349         {
4350                 temp = 0x1000C4;
4351                 if(pipe == 1)
4352                         temp |= (1 << 21);
4353                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4354         }
4355 }
4356
4357 static void i9xx_update_pll(struct drm_crtc *crtc,
4358                             struct drm_display_mode *mode,
4359                             struct drm_display_mode *adjusted_mode,
4360                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4361                             int num_connectors)
4362 {
4363         struct drm_device *dev = crtc->dev;
4364         struct drm_i915_private *dev_priv = dev->dev_private;
4365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4366         struct intel_encoder *encoder;
4367         int pipe = intel_crtc->pipe;
4368         u32 dpll;
4369         bool is_sdvo;
4370
4371         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4372
4373         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4374                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4375
4376         dpll = DPLL_VGA_MODE_DIS;
4377
4378         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4379                 dpll |= DPLLB_MODE_LVDS;
4380         else
4381                 dpll |= DPLLB_MODE_DAC_SERIAL;
4382         if (is_sdvo) {
4383                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4384                 if (pixel_multiplier > 1) {
4385                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4386                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4387                 }
4388                 dpll |= DPLL_DVO_HIGH_SPEED;
4389         }
4390         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4391                 dpll |= DPLL_DVO_HIGH_SPEED;
4392
4393         /* compute bitmask from p1 value */
4394         if (IS_PINEVIEW(dev))
4395                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4396         else {
4397                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4398                 if (IS_G4X(dev) && reduced_clock)
4399                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4400         }
4401         switch (clock->p2) {
4402         case 5:
4403                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4404                 break;
4405         case 7:
4406                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4407                 break;
4408         case 10:
4409                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4410                 break;
4411         case 14:
4412                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4413                 break;
4414         }
4415         if (INTEL_INFO(dev)->gen >= 4)
4416                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4417
4418         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4419                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4420         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4421                 /* XXX: just matching BIOS for now */
4422                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4423                 dpll |= 3;
4424         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4425                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4426                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4427         else
4428                 dpll |= PLL_REF_INPUT_DREFCLK;
4429
4430         dpll |= DPLL_VCO_ENABLE;
4431         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4432         POSTING_READ(DPLL(pipe));
4433         udelay(150);
4434
4435         for_each_encoder_on_crtc(dev, crtc, encoder)
4436                 if (encoder->pre_pll_enable)
4437                         encoder->pre_pll_enable(encoder);
4438
4439         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4440                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4441
4442         I915_WRITE(DPLL(pipe), dpll);
4443
4444         /* Wait for the clocks to stabilize. */
4445         POSTING_READ(DPLL(pipe));
4446         udelay(150);
4447
4448         if (INTEL_INFO(dev)->gen >= 4) {
4449                 u32 temp = 0;
4450                 if (is_sdvo) {
4451                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4452                         if (temp > 1)
4453                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4454                         else
4455                                 temp = 0;
4456                 }
4457                 I915_WRITE(DPLL_MD(pipe), temp);
4458         } else {
4459                 /* The pixel multiplier can only be updated once the
4460                  * DPLL is enabled and the clocks are stable.
4461                  *
4462                  * So write it again.
4463                  */
4464                 I915_WRITE(DPLL(pipe), dpll);
4465         }
4466 }
4467
4468 static void i8xx_update_pll(struct drm_crtc *crtc,
4469                             struct drm_display_mode *adjusted_mode,
4470                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4471                             int num_connectors)
4472 {
4473         struct drm_device *dev = crtc->dev;
4474         struct drm_i915_private *dev_priv = dev->dev_private;
4475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4476         struct intel_encoder *encoder;
4477         int pipe = intel_crtc->pipe;
4478         u32 dpll;
4479
4480         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4481
4482         dpll = DPLL_VGA_MODE_DIS;
4483
4484         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4485                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4486         } else {
4487                 if (clock->p1 == 2)
4488                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4489                 else
4490                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4491                 if (clock->p2 == 4)
4492                         dpll |= PLL_P2_DIVIDE_BY_4;
4493         }
4494
4495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4496                 /* XXX: just matching BIOS for now */
4497                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4498                 dpll |= 3;
4499         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4500                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4501                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4502         else
4503                 dpll |= PLL_REF_INPUT_DREFCLK;
4504
4505         dpll |= DPLL_VCO_ENABLE;
4506         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4507         POSTING_READ(DPLL(pipe));
4508         udelay(150);
4509
4510         for_each_encoder_on_crtc(dev, crtc, encoder)
4511                 if (encoder->pre_pll_enable)
4512                         encoder->pre_pll_enable(encoder);
4513
4514         I915_WRITE(DPLL(pipe), dpll);
4515
4516         /* Wait for the clocks to stabilize. */
4517         POSTING_READ(DPLL(pipe));
4518         udelay(150);
4519
4520         /* The pixel multiplier can only be updated once the
4521          * DPLL is enabled and the clocks are stable.
4522          *
4523          * So write it again.
4524          */
4525         I915_WRITE(DPLL(pipe), dpll);
4526 }
4527
4528 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4529                                    struct drm_display_mode *mode,
4530                                    struct drm_display_mode *adjusted_mode)
4531 {
4532         struct drm_device *dev = intel_crtc->base.dev;
4533         struct drm_i915_private *dev_priv = dev->dev_private;
4534         enum pipe pipe = intel_crtc->pipe;
4535         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4536         uint32_t vsyncshift;
4537
4538         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4539                 /* the chip adds 2 halflines automatically */
4540                 adjusted_mode->crtc_vtotal -= 1;
4541                 adjusted_mode->crtc_vblank_end -= 1;
4542                 vsyncshift = adjusted_mode->crtc_hsync_start
4543                              - adjusted_mode->crtc_htotal / 2;
4544         } else {
4545                 vsyncshift = 0;
4546         }
4547
4548         if (INTEL_INFO(dev)->gen > 3)
4549                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4550
4551         I915_WRITE(HTOTAL(cpu_transcoder),
4552                    (adjusted_mode->crtc_hdisplay - 1) |
4553                    ((adjusted_mode->crtc_htotal - 1) << 16));
4554         I915_WRITE(HBLANK(cpu_transcoder),
4555                    (adjusted_mode->crtc_hblank_start - 1) |
4556                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4557         I915_WRITE(HSYNC(cpu_transcoder),
4558                    (adjusted_mode->crtc_hsync_start - 1) |
4559                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4560
4561         I915_WRITE(VTOTAL(cpu_transcoder),
4562                    (adjusted_mode->crtc_vdisplay - 1) |
4563                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4564         I915_WRITE(VBLANK(cpu_transcoder),
4565                    (adjusted_mode->crtc_vblank_start - 1) |
4566                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4567         I915_WRITE(VSYNC(cpu_transcoder),
4568                    (adjusted_mode->crtc_vsync_start - 1) |
4569                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4570
4571         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4572          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4573          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4574          * bits. */
4575         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4576             (pipe == PIPE_B || pipe == PIPE_C))
4577                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4578
4579         /* pipesrc controls the size that is scaled from, which should
4580          * always be the user's requested size.
4581          */
4582         I915_WRITE(PIPESRC(pipe),
4583                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4584 }
4585
4586 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4587                               struct drm_display_mode *mode,
4588                               struct drm_display_mode *adjusted_mode,
4589                               int x, int y,
4590                               struct drm_framebuffer *fb)
4591 {
4592         struct drm_device *dev = crtc->dev;
4593         struct drm_i915_private *dev_priv = dev->dev_private;
4594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4595         int pipe = intel_crtc->pipe;
4596         int plane = intel_crtc->plane;
4597         int refclk, num_connectors = 0;
4598         intel_clock_t clock, reduced_clock;
4599         u32 dspcntr, pipeconf;
4600         bool ok, has_reduced_clock = false, is_sdvo = false;
4601         bool is_lvds = false, is_tv = false, is_dp = false;
4602         struct intel_encoder *encoder;
4603         const intel_limit_t *limit;
4604         int ret;
4605
4606         for_each_encoder_on_crtc(dev, crtc, encoder) {
4607                 switch (encoder->type) {
4608                 case INTEL_OUTPUT_LVDS:
4609                         is_lvds = true;
4610                         break;
4611                 case INTEL_OUTPUT_SDVO:
4612                 case INTEL_OUTPUT_HDMI:
4613                         is_sdvo = true;
4614                         if (encoder->needs_tv_clock)
4615                                 is_tv = true;
4616                         break;
4617                 case INTEL_OUTPUT_TVOUT:
4618                         is_tv = true;
4619                         break;
4620                 case INTEL_OUTPUT_DISPLAYPORT:
4621                         is_dp = true;
4622                         break;
4623                 }
4624
4625                 num_connectors++;
4626         }
4627
4628         refclk = i9xx_get_refclk(crtc, num_connectors);
4629
4630         /*
4631          * Returns a set of divisors for the desired target clock with the given
4632          * refclk, or FALSE.  The returned values represent the clock equation:
4633          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4634          */
4635         limit = intel_limit(crtc, refclk);
4636         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4637                              &clock);
4638         if (!ok) {
4639                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4640                 return -EINVAL;
4641         }
4642
4643         /* Ensure that the cursor is valid for the new mode before changing... */
4644         intel_crtc_update_cursor(crtc, true);
4645
4646         if (is_lvds && dev_priv->lvds_downclock_avail) {
4647                 /*
4648                  * Ensure we match the reduced clock's P to the target clock.
4649                  * If the clocks don't match, we can't switch the display clock
4650                  * by using the FP0/FP1. In such case we will disable the LVDS
4651                  * downclock feature.
4652                 */
4653                 has_reduced_clock = limit->find_pll(limit, crtc,
4654                                                     dev_priv->lvds_downclock,
4655                                                     refclk,
4656                                                     &clock,
4657                                                     &reduced_clock);
4658         }
4659
4660         if (is_sdvo && is_tv)
4661                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4662
4663         if (IS_GEN2(dev))
4664                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4665                                 has_reduced_clock ? &reduced_clock : NULL,
4666                                 num_connectors);
4667         else if (IS_VALLEYVIEW(dev))
4668                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4669                                 has_reduced_clock ? &reduced_clock : NULL,
4670                                 num_connectors);
4671         else
4672                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4673                                 has_reduced_clock ? &reduced_clock : NULL,
4674                                 num_connectors);
4675
4676         /* setup pipeconf */
4677         pipeconf = I915_READ(PIPECONF(pipe));
4678
4679         /* Set up the display plane register */
4680         dspcntr = DISPPLANE_GAMMA_ENABLE;
4681
4682         if (pipe == 0)
4683                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4684         else
4685                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4686
4687         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4688                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4689                  * core speed.
4690                  *
4691                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4692                  * pipe == 0 check?
4693                  */
4694                 if (mode->clock >
4695                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4696                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4697                 else
4698                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4699         }
4700
4701         /* default to 8bpc */
4702         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4703         if (is_dp) {
4704                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4705                         pipeconf |= PIPECONF_BPP_6 |
4706                                     PIPECONF_DITHER_EN |
4707                                     PIPECONF_DITHER_TYPE_SP;
4708                 }
4709         }
4710
4711         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4712                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4713                         pipeconf |= PIPECONF_BPP_6 |
4714                                         PIPECONF_ENABLE |
4715                                         I965_PIPECONF_ACTIVE;
4716                 }
4717         }
4718
4719         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4720         drm_mode_debug_printmodeline(mode);
4721
4722         if (HAS_PIPE_CXSR(dev)) {
4723                 if (intel_crtc->lowfreq_avail) {
4724                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4725                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4726                 } else {
4727                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4728                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4729                 }
4730         }
4731
4732         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4733         if (!IS_GEN2(dev) &&
4734             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4735                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4736         else
4737                 pipeconf |= PIPECONF_PROGRESSIVE;
4738
4739         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4740
4741         /* pipesrc and dspsize control the size that is scaled from,
4742          * which should always be the user's requested size.
4743          */
4744         I915_WRITE(DSPSIZE(plane),
4745                    ((mode->vdisplay - 1) << 16) |
4746                    (mode->hdisplay - 1));
4747         I915_WRITE(DSPPOS(plane), 0);
4748
4749         I915_WRITE(PIPECONF(pipe), pipeconf);
4750         POSTING_READ(PIPECONF(pipe));
4751         intel_enable_pipe(dev_priv, pipe, false);
4752
4753         intel_wait_for_vblank(dev, pipe);
4754
4755         I915_WRITE(DSPCNTR(plane), dspcntr);
4756         POSTING_READ(DSPCNTR(plane));
4757
4758         ret = intel_pipe_set_base(crtc, x, y, fb);
4759
4760         intel_update_watermarks(dev);
4761
4762         return ret;
4763 }
4764
4765 /*
4766  * Initialize reference clocks when the driver loads
4767  */
4768 void ironlake_init_pch_refclk(struct drm_device *dev)
4769 {
4770         struct drm_i915_private *dev_priv = dev->dev_private;
4771         struct drm_mode_config *mode_config = &dev->mode_config;
4772         struct intel_encoder *encoder;
4773         u32 temp;
4774         bool has_lvds = false;
4775         bool has_cpu_edp = false;
4776         bool has_pch_edp = false;
4777         bool has_panel = false;
4778         bool has_ck505 = false;
4779         bool can_ssc = false;
4780
4781         /* We need to take the global config into account */
4782         list_for_each_entry(encoder, &mode_config->encoder_list,
4783                             base.head) {
4784                 switch (encoder->type) {
4785                 case INTEL_OUTPUT_LVDS:
4786                         has_panel = true;
4787                         has_lvds = true;
4788                         break;
4789                 case INTEL_OUTPUT_EDP:
4790                         has_panel = true;
4791                         if (intel_encoder_is_pch_edp(&encoder->base))
4792                                 has_pch_edp = true;
4793                         else
4794                                 has_cpu_edp = true;
4795                         break;
4796                 }
4797         }
4798
4799         if (HAS_PCH_IBX(dev)) {
4800                 has_ck505 = dev_priv->display_clock_mode;
4801                 can_ssc = has_ck505;
4802         } else {
4803                 has_ck505 = false;
4804                 can_ssc = true;
4805         }
4806
4807         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4808                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4809                       has_ck505);
4810
4811         /* Ironlake: try to setup display ref clock before DPLL
4812          * enabling. This is only under driver's control after
4813          * PCH B stepping, previous chipset stepping should be
4814          * ignoring this setting.
4815          */
4816         temp = I915_READ(PCH_DREF_CONTROL);
4817         /* Always enable nonspread source */
4818         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4819
4820         if (has_ck505)
4821                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4822         else
4823                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4824
4825         if (has_panel) {
4826                 temp &= ~DREF_SSC_SOURCE_MASK;
4827                 temp |= DREF_SSC_SOURCE_ENABLE;
4828
4829                 /* SSC must be turned on before enabling the CPU output  */
4830                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4831                         DRM_DEBUG_KMS("Using SSC on panel\n");
4832                         temp |= DREF_SSC1_ENABLE;
4833                 } else
4834                         temp &= ~DREF_SSC1_ENABLE;
4835
4836                 /* Get SSC going before enabling the outputs */
4837                 I915_WRITE(PCH_DREF_CONTROL, temp);
4838                 POSTING_READ(PCH_DREF_CONTROL);
4839                 udelay(200);
4840
4841                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4842
4843                 /* Enable CPU source on CPU attached eDP */
4844                 if (has_cpu_edp) {
4845                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4846                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4847                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4848                         }
4849                         else
4850                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4851                 } else
4852                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4853
4854                 I915_WRITE(PCH_DREF_CONTROL, temp);
4855                 POSTING_READ(PCH_DREF_CONTROL);
4856                 udelay(200);
4857         } else {
4858                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4859
4860                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4861
4862                 /* Turn off CPU output */
4863                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4864
4865                 I915_WRITE(PCH_DREF_CONTROL, temp);
4866                 POSTING_READ(PCH_DREF_CONTROL);
4867                 udelay(200);
4868
4869                 /* Turn off the SSC source */
4870                 temp &= ~DREF_SSC_SOURCE_MASK;
4871                 temp |= DREF_SSC_SOURCE_DISABLE;
4872
4873                 /* Turn off SSC1 */
4874                 temp &= ~ DREF_SSC1_ENABLE;
4875
4876                 I915_WRITE(PCH_DREF_CONTROL, temp);
4877                 POSTING_READ(PCH_DREF_CONTROL);
4878                 udelay(200);
4879         }
4880 }
4881
4882 static int ironlake_get_refclk(struct drm_crtc *crtc)
4883 {
4884         struct drm_device *dev = crtc->dev;
4885         struct drm_i915_private *dev_priv = dev->dev_private;
4886         struct intel_encoder *encoder;
4887         struct intel_encoder *edp_encoder = NULL;
4888         int num_connectors = 0;
4889         bool is_lvds = false;
4890
4891         for_each_encoder_on_crtc(dev, crtc, encoder) {
4892                 switch (encoder->type) {
4893                 case INTEL_OUTPUT_LVDS:
4894                         is_lvds = true;
4895                         break;
4896                 case INTEL_OUTPUT_EDP:
4897                         edp_encoder = encoder;
4898                         break;
4899                 }
4900                 num_connectors++;
4901         }
4902
4903         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4904                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4905                               dev_priv->lvds_ssc_freq);
4906                 return dev_priv->lvds_ssc_freq * 1000;
4907         }
4908
4909         return 120000;
4910 }
4911
4912 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4913                                   struct drm_display_mode *adjusted_mode,
4914                                   bool dither)
4915 {
4916         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4918         int pipe = intel_crtc->pipe;
4919         uint32_t val;
4920
4921         val = I915_READ(PIPECONF(pipe));
4922
4923         val &= ~PIPE_BPC_MASK;
4924         switch (intel_crtc->bpp) {
4925         case 18:
4926                 val |= PIPE_6BPC;
4927                 break;
4928         case 24:
4929                 val |= PIPE_8BPC;
4930                 break;
4931         case 30:
4932                 val |= PIPE_10BPC;
4933                 break;
4934         case 36:
4935                 val |= PIPE_12BPC;
4936                 break;
4937         default:
4938                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4939                 BUG();
4940         }
4941
4942         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4943         if (dither)
4944                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4945
4946         val &= ~PIPECONF_INTERLACE_MASK;
4947         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4948                 val |= PIPECONF_INTERLACED_ILK;
4949         else
4950                 val |= PIPECONF_PROGRESSIVE;
4951
4952         I915_WRITE(PIPECONF(pipe), val);
4953         POSTING_READ(PIPECONF(pipe));
4954 }
4955
4956 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4957                                  struct drm_display_mode *adjusted_mode,
4958                                  bool dither)
4959 {
4960         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4962         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4963         uint32_t val;
4964
4965         val = I915_READ(PIPECONF(cpu_transcoder));
4966
4967         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4968         if (dither)
4969                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4970
4971         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4972         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4973                 val |= PIPECONF_INTERLACED_ILK;
4974         else
4975                 val |= PIPECONF_PROGRESSIVE;
4976
4977         I915_WRITE(PIPECONF(cpu_transcoder), val);
4978         POSTING_READ(PIPECONF(cpu_transcoder));
4979 }
4980
4981 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4982                                     struct drm_display_mode *adjusted_mode,
4983                                     intel_clock_t *clock,
4984                                     bool *has_reduced_clock,
4985                                     intel_clock_t *reduced_clock)
4986 {
4987         struct drm_device *dev = crtc->dev;
4988         struct drm_i915_private *dev_priv = dev->dev_private;
4989         struct intel_encoder *intel_encoder;
4990         int refclk;
4991         const intel_limit_t *limit;
4992         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4993
4994         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4995                 switch (intel_encoder->type) {
4996                 case INTEL_OUTPUT_LVDS:
4997                         is_lvds = true;
4998                         break;
4999                 case INTEL_OUTPUT_SDVO:
5000                 case INTEL_OUTPUT_HDMI:
5001                         is_sdvo = true;
5002                         if (intel_encoder->needs_tv_clock)
5003                                 is_tv = true;
5004                         break;
5005                 case INTEL_OUTPUT_TVOUT:
5006                         is_tv = true;
5007                         break;
5008                 }
5009         }
5010
5011         refclk = ironlake_get_refclk(crtc);
5012
5013         /*
5014          * Returns a set of divisors for the desired target clock with the given
5015          * refclk, or FALSE.  The returned values represent the clock equation:
5016          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5017          */
5018         limit = intel_limit(crtc, refclk);
5019         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5020                               clock);
5021         if (!ret)
5022                 return false;
5023
5024         if (is_lvds && dev_priv->lvds_downclock_avail) {
5025                 /*
5026                  * Ensure we match the reduced clock's P to the target clock.
5027                  * If the clocks don't match, we can't switch the display clock
5028                  * by using the FP0/FP1. In such case we will disable the LVDS
5029                  * downclock feature.
5030                 */
5031                 *has_reduced_clock = limit->find_pll(limit, crtc,
5032                                                      dev_priv->lvds_downclock,
5033                                                      refclk,
5034                                                      clock,
5035                                                      reduced_clock);
5036         }
5037
5038         if (is_sdvo && is_tv)
5039                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5040
5041         return true;
5042 }
5043
5044 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5045 {
5046         struct drm_i915_private *dev_priv = dev->dev_private;
5047         uint32_t temp;
5048
5049         temp = I915_READ(SOUTH_CHICKEN1);
5050         if (temp & FDI_BC_BIFURCATION_SELECT)
5051                 return;
5052
5053         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5054         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5055
5056         temp |= FDI_BC_BIFURCATION_SELECT;
5057         DRM_DEBUG_KMS("enabling fdi C rx\n");
5058         I915_WRITE(SOUTH_CHICKEN1, temp);
5059         POSTING_READ(SOUTH_CHICKEN1);
5060 }
5061
5062 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5063 {
5064         struct drm_device *dev = intel_crtc->base.dev;
5065         struct drm_i915_private *dev_priv = dev->dev_private;
5066         struct intel_crtc *pipe_B_crtc =
5067                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5068
5069         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5070                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5071         if (intel_crtc->fdi_lanes > 4) {
5072                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5073                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5074                 /* Clamp lanes to avoid programming the hw with bogus values. */
5075                 intel_crtc->fdi_lanes = 4;
5076
5077                 return false;
5078         }
5079
5080         if (dev_priv->num_pipe == 2)
5081                 return true;
5082
5083         switch (intel_crtc->pipe) {
5084         case PIPE_A:
5085                 return true;
5086         case PIPE_B:
5087                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5088                     intel_crtc->fdi_lanes > 2) {
5089                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5090                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5091                         /* Clamp lanes to avoid programming the hw with bogus values. */
5092                         intel_crtc->fdi_lanes = 2;
5093
5094                         return false;
5095                 }
5096
5097                 if (intel_crtc->fdi_lanes > 2)
5098                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5099                 else
5100                         cpt_enable_fdi_bc_bifurcation(dev);
5101
5102                 return true;
5103         case PIPE_C:
5104                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5105                         if (intel_crtc->fdi_lanes > 2) {
5106                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5107                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5108                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5109                                 intel_crtc->fdi_lanes = 2;
5110
5111                                 return false;
5112                         }
5113                 } else {
5114                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5115                         return false;
5116                 }
5117
5118                 cpt_enable_fdi_bc_bifurcation(dev);
5119
5120                 return true;
5121         default:
5122                 BUG();
5123         }
5124 }
5125
5126 static void ironlake_set_m_n(struct drm_crtc *crtc,
5127                              struct drm_display_mode *mode,
5128                              struct drm_display_mode *adjusted_mode)
5129 {
5130         struct drm_device *dev = crtc->dev;
5131         struct drm_i915_private *dev_priv = dev->dev_private;
5132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5133         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5134         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5135         struct fdi_m_n m_n = {0};
5136         int target_clock, pixel_multiplier, lane, link_bw;
5137         bool is_dp = false, is_cpu_edp = false;
5138
5139         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5140                 switch (intel_encoder->type) {
5141                 case INTEL_OUTPUT_DISPLAYPORT:
5142                         is_dp = true;
5143                         break;
5144                 case INTEL_OUTPUT_EDP:
5145                         is_dp = true;
5146                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5147                                 is_cpu_edp = true;
5148                         edp_encoder = intel_encoder;
5149                         break;
5150                 }
5151         }
5152
5153         /* FDI link */
5154         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5155         lane = 0;
5156         /* CPU eDP doesn't require FDI link, so just set DP M/N
5157            according to current link config */
5158         if (is_cpu_edp) {
5159                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5160         } else {
5161                 /* FDI is a binary signal running at ~2.7GHz, encoding
5162                  * each output octet as 10 bits. The actual frequency
5163                  * is stored as a divider into a 100MHz clock, and the
5164                  * mode pixel clock is stored in units of 1KHz.
5165                  * Hence the bw of each lane in terms of the mode signal
5166                  * is:
5167                  */
5168                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5169         }
5170
5171         /* [e]DP over FDI requires target mode clock instead of link clock. */
5172         if (edp_encoder)
5173                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5174         else if (is_dp)
5175                 target_clock = mode->clock;
5176         else
5177                 target_clock = adjusted_mode->clock;
5178
5179         if (!lane) {
5180                 /*
5181                  * Account for spread spectrum to avoid
5182                  * oversubscribing the link. Max center spread
5183                  * is 2.5%; use 5% for safety's sake.
5184                  */
5185                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5186                 lane = bps / (link_bw * 8) + 1;
5187         }
5188
5189         intel_crtc->fdi_lanes = lane;
5190
5191         if (pixel_multiplier > 1)
5192                 link_bw *= pixel_multiplier;
5193         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5194                              &m_n);
5195
5196         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5197         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5198         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5199         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5200 }
5201
5202 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5203                                       struct drm_display_mode *adjusted_mode,
5204                                       intel_clock_t *clock, u32 fp)
5205 {
5206         struct drm_crtc *crtc = &intel_crtc->base;
5207         struct drm_device *dev = crtc->dev;
5208         struct drm_i915_private *dev_priv = dev->dev_private;
5209         struct intel_encoder *intel_encoder;
5210         uint32_t dpll;
5211         int factor, pixel_multiplier, num_connectors = 0;
5212         bool is_lvds = false, is_sdvo = false, is_tv = false;
5213         bool is_dp = false, is_cpu_edp = false;
5214
5215         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5216                 switch (intel_encoder->type) {
5217                 case INTEL_OUTPUT_LVDS:
5218                         is_lvds = true;
5219                         break;
5220                 case INTEL_OUTPUT_SDVO:
5221                 case INTEL_OUTPUT_HDMI:
5222                         is_sdvo = true;
5223                         if (intel_encoder->needs_tv_clock)
5224                                 is_tv = true;
5225                         break;
5226                 case INTEL_OUTPUT_TVOUT:
5227                         is_tv = true;
5228                         break;
5229                 case INTEL_OUTPUT_DISPLAYPORT:
5230                         is_dp = true;
5231                         break;
5232                 case INTEL_OUTPUT_EDP:
5233                         is_dp = true;
5234                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5235                                 is_cpu_edp = true;
5236                         break;
5237                 }
5238
5239                 num_connectors++;
5240         }
5241
5242         /* Enable autotuning of the PLL clock (if permissible) */
5243         factor = 21;
5244         if (is_lvds) {
5245                 if ((intel_panel_use_ssc(dev_priv) &&
5246                      dev_priv->lvds_ssc_freq == 100) ||
5247                     intel_is_dual_link_lvds(dev))
5248                         factor = 25;
5249         } else if (is_sdvo && is_tv)
5250                 factor = 20;
5251
5252         if (clock->m < factor * clock->n)
5253                 fp |= FP_CB_TUNE;
5254
5255         dpll = 0;
5256
5257         if (is_lvds)
5258                 dpll |= DPLLB_MODE_LVDS;
5259         else
5260                 dpll |= DPLLB_MODE_DAC_SERIAL;
5261         if (is_sdvo) {
5262                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5263                 if (pixel_multiplier > 1) {
5264                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5265                 }
5266                 dpll |= DPLL_DVO_HIGH_SPEED;
5267         }
5268         if (is_dp && !is_cpu_edp)
5269                 dpll |= DPLL_DVO_HIGH_SPEED;
5270
5271         /* compute bitmask from p1 value */
5272         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5273         /* also FPA1 */
5274         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5275
5276         switch (clock->p2) {
5277         case 5:
5278                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5279                 break;
5280         case 7:
5281                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5282                 break;
5283         case 10:
5284                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5285                 break;
5286         case 14:
5287                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5288                 break;
5289         }
5290
5291         if (is_sdvo && is_tv)
5292                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5293         else if (is_tv)
5294                 /* XXX: just matching BIOS for now */
5295                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5296                 dpll |= 3;
5297         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5298                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5299         else
5300                 dpll |= PLL_REF_INPUT_DREFCLK;
5301
5302         return dpll;
5303 }
5304
5305 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5306                                   struct drm_display_mode *mode,
5307                                   struct drm_display_mode *adjusted_mode,
5308                                   int x, int y,
5309                                   struct drm_framebuffer *fb)
5310 {
5311         struct drm_device *dev = crtc->dev;
5312         struct drm_i915_private *dev_priv = dev->dev_private;
5313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5314         int pipe = intel_crtc->pipe;
5315         int plane = intel_crtc->plane;
5316         int num_connectors = 0;
5317         intel_clock_t clock, reduced_clock;
5318         u32 dpll, fp = 0, fp2 = 0;
5319         bool ok, has_reduced_clock = false;
5320         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5321         struct intel_encoder *encoder;
5322         int ret;
5323         bool dither, fdi_config_ok;
5324
5325         for_each_encoder_on_crtc(dev, crtc, encoder) {
5326                 switch (encoder->type) {
5327                 case INTEL_OUTPUT_LVDS:
5328                         is_lvds = true;
5329                         break;
5330                 case INTEL_OUTPUT_DISPLAYPORT:
5331                         is_dp = true;
5332                         break;
5333                 case INTEL_OUTPUT_EDP:
5334                         is_dp = true;
5335                         if (!intel_encoder_is_pch_edp(&encoder->base))
5336                                 is_cpu_edp = true;
5337                         break;
5338                 }
5339
5340                 num_connectors++;
5341         }
5342
5343         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5344              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5345
5346         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5347                                      &has_reduced_clock, &reduced_clock);
5348         if (!ok) {
5349                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5350                 return -EINVAL;
5351         }
5352
5353         /* Ensure that the cursor is valid for the new mode before changing... */
5354         intel_crtc_update_cursor(crtc, true);
5355
5356         /* determine panel color depth */
5357         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5358                                               adjusted_mode);
5359         if (is_lvds && dev_priv->lvds_dither)
5360                 dither = true;
5361
5362         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5363         if (has_reduced_clock)
5364                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5365                         reduced_clock.m2;
5366
5367         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5368
5369         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5370         drm_mode_debug_printmodeline(mode);
5371
5372         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5373         if (!is_cpu_edp) {
5374                 struct intel_pch_pll *pll;
5375
5376                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5377                 if (pll == NULL) {
5378                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5379                                          pipe);
5380                         return -EINVAL;
5381                 }
5382         } else
5383                 intel_put_pch_pll(intel_crtc);
5384
5385         if (is_dp && !is_cpu_edp) {
5386                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5387         } else {
5388                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5389                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5390                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5391                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5392                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5393         }
5394
5395         for_each_encoder_on_crtc(dev, crtc, encoder)
5396                 if (encoder->pre_pll_enable)
5397                         encoder->pre_pll_enable(encoder);
5398
5399         if (intel_crtc->pch_pll) {
5400                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5401
5402                 /* Wait for the clocks to stabilize. */
5403                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5404                 udelay(150);
5405
5406                 /* The pixel multiplier can only be updated once the
5407                  * DPLL is enabled and the clocks are stable.
5408                  *
5409                  * So write it again.
5410                  */
5411                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5412         }
5413
5414         intel_crtc->lowfreq_avail = false;
5415         if (intel_crtc->pch_pll) {
5416                 if (is_lvds && has_reduced_clock && i915_powersave) {
5417                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5418                         intel_crtc->lowfreq_avail = true;
5419                 } else {
5420                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5421                 }
5422         }
5423
5424         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5425
5426         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5427          * ironlake_check_fdi_lanes. */
5428         ironlake_set_m_n(crtc, mode, adjusted_mode);
5429
5430         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5431
5432         if (is_cpu_edp)
5433                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5434
5435         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5436
5437         intel_wait_for_vblank(dev, pipe);
5438
5439         /* Set up the display plane register */
5440         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5441         POSTING_READ(DSPCNTR(plane));
5442
5443         ret = intel_pipe_set_base(crtc, x, y, fb);
5444
5445         intel_update_watermarks(dev);
5446
5447         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5448
5449         return fdi_config_ok ? ret : -EINVAL;
5450 }
5451
5452 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5453                                  struct drm_display_mode *mode,
5454                                  struct drm_display_mode *adjusted_mode,
5455                                  int x, int y,
5456                                  struct drm_framebuffer *fb)
5457 {
5458         struct drm_device *dev = crtc->dev;
5459         struct drm_i915_private *dev_priv = dev->dev_private;
5460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5461         int pipe = intel_crtc->pipe;
5462         int plane = intel_crtc->plane;
5463         int num_connectors = 0;
5464         bool is_dp = false, is_cpu_edp = false;
5465         struct intel_encoder *encoder;
5466         int ret;
5467         bool dither;
5468
5469         for_each_encoder_on_crtc(dev, crtc, encoder) {
5470                 switch (encoder->type) {
5471                 case INTEL_OUTPUT_DISPLAYPORT:
5472                         is_dp = true;
5473                         break;
5474                 case INTEL_OUTPUT_EDP:
5475                         is_dp = true;
5476                         if (!intel_encoder_is_pch_edp(&encoder->base))
5477                                 is_cpu_edp = true;
5478                         break;
5479                 }
5480
5481                 num_connectors++;
5482         }
5483
5484         if (is_cpu_edp)
5485                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5486         else
5487                 intel_crtc->cpu_transcoder = pipe;
5488
5489         /* We are not sure yet this won't happen. */
5490         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5491              INTEL_PCH_TYPE(dev));
5492
5493         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5494              num_connectors, pipe_name(pipe));
5495
5496         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5497                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5498
5499         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5500
5501         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5502                 return -EINVAL;
5503
5504         /* Ensure that the cursor is valid for the new mode before changing... */
5505         intel_crtc_update_cursor(crtc, true);
5506
5507         /* determine panel color depth */
5508         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5509                                               adjusted_mode);
5510
5511         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5512         drm_mode_debug_printmodeline(mode);
5513
5514         if (is_dp && !is_cpu_edp)
5515                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5516
5517         intel_crtc->lowfreq_avail = false;
5518
5519         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5520
5521         if (!is_dp || is_cpu_edp)
5522                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5523
5524         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5525
5526         /* Set up the display plane register */
5527         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5528         POSTING_READ(DSPCNTR(plane));
5529
5530         ret = intel_pipe_set_base(crtc, x, y, fb);
5531
5532         intel_update_watermarks(dev);
5533
5534         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5535
5536         return ret;
5537 }
5538
5539 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5540                                struct drm_display_mode *mode,
5541                                struct drm_display_mode *adjusted_mode,
5542                                int x, int y,
5543                                struct drm_framebuffer *fb)
5544 {
5545         struct drm_device *dev = crtc->dev;
5546         struct drm_i915_private *dev_priv = dev->dev_private;
5547         struct drm_encoder_helper_funcs *encoder_funcs;
5548         struct intel_encoder *encoder;
5549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5550         int pipe = intel_crtc->pipe;
5551         int ret;
5552
5553         drm_vblank_pre_modeset(dev, pipe);
5554
5555         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5556                                               x, y, fb);
5557         drm_vblank_post_modeset(dev, pipe);
5558
5559         if (ret != 0)
5560                 return ret;
5561
5562         for_each_encoder_on_crtc(dev, crtc, encoder) {
5563                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5564                         encoder->base.base.id,
5565                         drm_get_encoder_name(&encoder->base),
5566                         mode->base.id, mode->name);
5567                 encoder_funcs = encoder->base.helper_private;
5568                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5569         }
5570
5571         return 0;
5572 }
5573
5574 static bool intel_eld_uptodate(struct drm_connector *connector,
5575                                int reg_eldv, uint32_t bits_eldv,
5576                                int reg_elda, uint32_t bits_elda,
5577                                int reg_edid)
5578 {
5579         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5580         uint8_t *eld = connector->eld;
5581         uint32_t i;
5582
5583         i = I915_READ(reg_eldv);
5584         i &= bits_eldv;
5585
5586         if (!eld[0])
5587                 return !i;
5588
5589         if (!i)
5590                 return false;
5591
5592         i = I915_READ(reg_elda);
5593         i &= ~bits_elda;
5594         I915_WRITE(reg_elda, i);
5595
5596         for (i = 0; i < eld[2]; i++)
5597                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5598                         return false;
5599
5600         return true;
5601 }
5602
5603 static void g4x_write_eld(struct drm_connector *connector,
5604                           struct drm_crtc *crtc)
5605 {
5606         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5607         uint8_t *eld = connector->eld;
5608         uint32_t eldv;
5609         uint32_t len;
5610         uint32_t i;
5611
5612         i = I915_READ(G4X_AUD_VID_DID);
5613
5614         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5615                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5616         else
5617                 eldv = G4X_ELDV_DEVCTG;
5618
5619         if (intel_eld_uptodate(connector,
5620                                G4X_AUD_CNTL_ST, eldv,
5621                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5622                                G4X_HDMIW_HDMIEDID))
5623                 return;
5624
5625         i = I915_READ(G4X_AUD_CNTL_ST);
5626         i &= ~(eldv | G4X_ELD_ADDR);
5627         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5628         I915_WRITE(G4X_AUD_CNTL_ST, i);
5629
5630         if (!eld[0])
5631                 return;
5632
5633         len = min_t(uint8_t, eld[2], len);
5634         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5635         for (i = 0; i < len; i++)
5636                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5637
5638         i = I915_READ(G4X_AUD_CNTL_ST);
5639         i |= eldv;
5640         I915_WRITE(G4X_AUD_CNTL_ST, i);
5641 }
5642
5643 static void haswell_write_eld(struct drm_connector *connector,
5644                                      struct drm_crtc *crtc)
5645 {
5646         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5647         uint8_t *eld = connector->eld;
5648         struct drm_device *dev = crtc->dev;
5649         uint32_t eldv;
5650         uint32_t i;
5651         int len;
5652         int pipe = to_intel_crtc(crtc)->pipe;
5653         int tmp;
5654
5655         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5656         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5657         int aud_config = HSW_AUD_CFG(pipe);
5658         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5659
5660
5661         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5662
5663         /* Audio output enable */
5664         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5665         tmp = I915_READ(aud_cntrl_st2);
5666         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5667         I915_WRITE(aud_cntrl_st2, tmp);
5668
5669         /* Wait for 1 vertical blank */
5670         intel_wait_for_vblank(dev, pipe);
5671
5672         /* Set ELD valid state */
5673         tmp = I915_READ(aud_cntrl_st2);
5674         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5675         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5676         I915_WRITE(aud_cntrl_st2, tmp);
5677         tmp = I915_READ(aud_cntrl_st2);
5678         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5679
5680         /* Enable HDMI mode */
5681         tmp = I915_READ(aud_config);
5682         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5683         /* clear N_programing_enable and N_value_index */
5684         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5685         I915_WRITE(aud_config, tmp);
5686
5687         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5688
5689         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5690
5691         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5692                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5693                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5694                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5695         } else
5696                 I915_WRITE(aud_config, 0);
5697
5698         if (intel_eld_uptodate(connector,
5699                                aud_cntrl_st2, eldv,
5700                                aud_cntl_st, IBX_ELD_ADDRESS,
5701                                hdmiw_hdmiedid))
5702                 return;
5703
5704         i = I915_READ(aud_cntrl_st2);
5705         i &= ~eldv;
5706         I915_WRITE(aud_cntrl_st2, i);
5707
5708         if (!eld[0])
5709                 return;
5710
5711         i = I915_READ(aud_cntl_st);
5712         i &= ~IBX_ELD_ADDRESS;
5713         I915_WRITE(aud_cntl_st, i);
5714         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5715         DRM_DEBUG_DRIVER("port num:%d\n", i);
5716
5717         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5718         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5719         for (i = 0; i < len; i++)
5720                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5721
5722         i = I915_READ(aud_cntrl_st2);
5723         i |= eldv;
5724         I915_WRITE(aud_cntrl_st2, i);
5725
5726 }
5727
5728 static void ironlake_write_eld(struct drm_connector *connector,
5729                                      struct drm_crtc *crtc)
5730 {
5731         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5732         uint8_t *eld = connector->eld;
5733         uint32_t eldv;
5734         uint32_t i;
5735         int len;
5736         int hdmiw_hdmiedid;
5737         int aud_config;
5738         int aud_cntl_st;
5739         int aud_cntrl_st2;
5740         int pipe = to_intel_crtc(crtc)->pipe;
5741
5742         if (HAS_PCH_IBX(connector->dev)) {
5743                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5744                 aud_config = IBX_AUD_CFG(pipe);
5745                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5746                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5747         } else {
5748                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5749                 aud_config = CPT_AUD_CFG(pipe);
5750                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5751                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5752         }
5753
5754         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5755
5756         i = I915_READ(aud_cntl_st);
5757         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5758         if (!i) {
5759                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5760                 /* operate blindly on all ports */
5761                 eldv = IBX_ELD_VALIDB;
5762                 eldv |= IBX_ELD_VALIDB << 4;
5763                 eldv |= IBX_ELD_VALIDB << 8;
5764         } else {
5765                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5766                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5767         }
5768
5769         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5770                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5771                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5772                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5773         } else
5774                 I915_WRITE(aud_config, 0);
5775
5776         if (intel_eld_uptodate(connector,
5777                                aud_cntrl_st2, eldv,
5778                                aud_cntl_st, IBX_ELD_ADDRESS,
5779                                hdmiw_hdmiedid))
5780                 return;
5781
5782         i = I915_READ(aud_cntrl_st2);
5783         i &= ~eldv;
5784         I915_WRITE(aud_cntrl_st2, i);
5785
5786         if (!eld[0])
5787                 return;
5788
5789         i = I915_READ(aud_cntl_st);
5790         i &= ~IBX_ELD_ADDRESS;
5791         I915_WRITE(aud_cntl_st, i);
5792
5793         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5794         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5795         for (i = 0; i < len; i++)
5796                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5797
5798         i = I915_READ(aud_cntrl_st2);
5799         i |= eldv;
5800         I915_WRITE(aud_cntrl_st2, i);
5801 }
5802
5803 void intel_write_eld(struct drm_encoder *encoder,
5804                      struct drm_display_mode *mode)
5805 {
5806         struct drm_crtc *crtc = encoder->crtc;
5807         struct drm_connector *connector;
5808         struct drm_device *dev = encoder->dev;
5809         struct drm_i915_private *dev_priv = dev->dev_private;
5810
5811         connector = drm_select_eld(encoder, mode);
5812         if (!connector)
5813                 return;
5814
5815         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5816                          connector->base.id,
5817                          drm_get_connector_name(connector),
5818                          connector->encoder->base.id,
5819                          drm_get_encoder_name(connector->encoder));
5820
5821         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5822
5823         if (dev_priv->display.write_eld)
5824                 dev_priv->display.write_eld(connector, crtc);
5825 }
5826
5827 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5828 void intel_crtc_load_lut(struct drm_crtc *crtc)
5829 {
5830         struct drm_device *dev = crtc->dev;
5831         struct drm_i915_private *dev_priv = dev->dev_private;
5832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5833         int palreg = PALETTE(intel_crtc->pipe);
5834         int i;
5835
5836         /* The clocks have to be on to load the palette. */
5837         if (!crtc->enabled || !intel_crtc->active)
5838                 return;
5839
5840         /* use legacy palette for Ironlake */
5841         if (HAS_PCH_SPLIT(dev))
5842                 palreg = LGC_PALETTE(intel_crtc->pipe);
5843
5844         for (i = 0; i < 256; i++) {
5845                 I915_WRITE(palreg + 4 * i,
5846                            (intel_crtc->lut_r[i] << 16) |
5847                            (intel_crtc->lut_g[i] << 8) |
5848                            intel_crtc->lut_b[i]);
5849         }
5850 }
5851
5852 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5853 {
5854         struct drm_device *dev = crtc->dev;
5855         struct drm_i915_private *dev_priv = dev->dev_private;
5856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5857         bool visible = base != 0;
5858         u32 cntl;
5859
5860         if (intel_crtc->cursor_visible == visible)
5861                 return;
5862
5863         cntl = I915_READ(_CURACNTR);
5864         if (visible) {
5865                 /* On these chipsets we can only modify the base whilst
5866                  * the cursor is disabled.
5867                  */
5868                 I915_WRITE(_CURABASE, base);
5869
5870                 cntl &= ~(CURSOR_FORMAT_MASK);
5871                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5872                 cntl |= CURSOR_ENABLE |
5873                         CURSOR_GAMMA_ENABLE |
5874                         CURSOR_FORMAT_ARGB;
5875         } else
5876                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5877         I915_WRITE(_CURACNTR, cntl);
5878
5879         intel_crtc->cursor_visible = visible;
5880 }
5881
5882 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5883 {
5884         struct drm_device *dev = crtc->dev;
5885         struct drm_i915_private *dev_priv = dev->dev_private;
5886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5887         int pipe = intel_crtc->pipe;
5888         bool visible = base != 0;
5889
5890         if (intel_crtc->cursor_visible != visible) {
5891                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5892                 if (base) {
5893                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5894                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5895                         cntl |= pipe << 28; /* Connect to correct pipe */
5896                 } else {
5897                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5898                         cntl |= CURSOR_MODE_DISABLE;
5899                 }
5900                 I915_WRITE(CURCNTR(pipe), cntl);
5901
5902                 intel_crtc->cursor_visible = visible;
5903         }
5904         /* and commit changes on next vblank */
5905         I915_WRITE(CURBASE(pipe), base);
5906 }
5907
5908 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5909 {
5910         struct drm_device *dev = crtc->dev;
5911         struct drm_i915_private *dev_priv = dev->dev_private;
5912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5913         int pipe = intel_crtc->pipe;
5914         bool visible = base != 0;
5915
5916         if (intel_crtc->cursor_visible != visible) {
5917                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5918                 if (base) {
5919                         cntl &= ~CURSOR_MODE;
5920                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5921                 } else {
5922                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5923                         cntl |= CURSOR_MODE_DISABLE;
5924                 }
5925                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5926
5927                 intel_crtc->cursor_visible = visible;
5928         }
5929         /* and commit changes on next vblank */
5930         I915_WRITE(CURBASE_IVB(pipe), base);
5931 }
5932
5933 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5934 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5935                                      bool on)
5936 {
5937         struct drm_device *dev = crtc->dev;
5938         struct drm_i915_private *dev_priv = dev->dev_private;
5939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5940         int pipe = intel_crtc->pipe;
5941         int x = intel_crtc->cursor_x;
5942         int y = intel_crtc->cursor_y;
5943         u32 base, pos;
5944         bool visible;
5945
5946         pos = 0;
5947
5948         if (on && crtc->enabled && crtc->fb) {
5949                 base = intel_crtc->cursor_addr;
5950                 if (x > (int) crtc->fb->width)
5951                         base = 0;
5952
5953                 if (y > (int) crtc->fb->height)
5954                         base = 0;
5955         } else
5956                 base = 0;
5957
5958         if (x < 0) {
5959                 if (x + intel_crtc->cursor_width < 0)
5960                         base = 0;
5961
5962                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5963                 x = -x;
5964         }
5965         pos |= x << CURSOR_X_SHIFT;
5966
5967         if (y < 0) {
5968                 if (y + intel_crtc->cursor_height < 0)
5969                         base = 0;
5970
5971                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5972                 y = -y;
5973         }
5974         pos |= y << CURSOR_Y_SHIFT;
5975
5976         visible = base != 0;
5977         if (!visible && !intel_crtc->cursor_visible)
5978                 return;
5979
5980         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5981                 I915_WRITE(CURPOS_IVB(pipe), pos);
5982                 ivb_update_cursor(crtc, base);
5983         } else {
5984                 I915_WRITE(CURPOS(pipe), pos);
5985                 if (IS_845G(dev) || IS_I865G(dev))
5986                         i845_update_cursor(crtc, base);
5987                 else
5988                         i9xx_update_cursor(crtc, base);
5989         }
5990 }
5991
5992 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5993                                  struct drm_file *file,
5994                                  uint32_t handle,
5995                                  uint32_t width, uint32_t height)
5996 {
5997         struct drm_device *dev = crtc->dev;
5998         struct drm_i915_private *dev_priv = dev->dev_private;
5999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6000         struct drm_i915_gem_object *obj;
6001         uint32_t addr;
6002         int ret;
6003
6004         /* if we want to turn off the cursor ignore width and height */
6005         if (!handle) {
6006                 DRM_DEBUG_KMS("cursor off\n");
6007                 addr = 0;
6008                 obj = NULL;
6009                 mutex_lock(&dev->struct_mutex);
6010                 goto finish;
6011         }
6012
6013         /* Currently we only support 64x64 cursors */
6014         if (width != 64 || height != 64) {
6015                 DRM_ERROR("we currently only support 64x64 cursors\n");
6016                 return -EINVAL;
6017         }
6018
6019         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6020         if (&obj->base == NULL)
6021                 return -ENOENT;
6022
6023         if (obj->base.size < width * height * 4) {
6024                 DRM_ERROR("buffer is to small\n");
6025                 ret = -ENOMEM;
6026                 goto fail;
6027         }
6028
6029         /* we only need to pin inside GTT if cursor is non-phy */
6030         mutex_lock(&dev->struct_mutex);
6031         if (!dev_priv->info->cursor_needs_physical) {
6032                 if (obj->tiling_mode) {
6033                         DRM_ERROR("cursor cannot be tiled\n");
6034                         ret = -EINVAL;
6035                         goto fail_locked;
6036                 }
6037
6038                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6039                 if (ret) {
6040                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6041                         goto fail_locked;
6042                 }
6043
6044                 ret = i915_gem_object_put_fence(obj);
6045                 if (ret) {
6046                         DRM_ERROR("failed to release fence for cursor");
6047                         goto fail_unpin;
6048                 }
6049
6050                 addr = obj->gtt_offset;
6051         } else {
6052                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6053                 ret = i915_gem_attach_phys_object(dev, obj,
6054                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6055                                                   align);
6056                 if (ret) {
6057                         DRM_ERROR("failed to attach phys object\n");
6058                         goto fail_locked;
6059                 }
6060                 addr = obj->phys_obj->handle->busaddr;
6061         }
6062
6063         if (IS_GEN2(dev))
6064                 I915_WRITE(CURSIZE, (height << 12) | width);
6065
6066  finish:
6067         if (intel_crtc->cursor_bo) {
6068                 if (dev_priv->info->cursor_needs_physical) {
6069                         if (intel_crtc->cursor_bo != obj)
6070                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6071                 } else
6072                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6073                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6074         }
6075
6076         mutex_unlock(&dev->struct_mutex);
6077
6078         intel_crtc->cursor_addr = addr;
6079         intel_crtc->cursor_bo = obj;
6080         intel_crtc->cursor_width = width;
6081         intel_crtc->cursor_height = height;
6082
6083         intel_crtc_update_cursor(crtc, true);
6084
6085         return 0;
6086 fail_unpin:
6087         i915_gem_object_unpin(obj);
6088 fail_locked:
6089         mutex_unlock(&dev->struct_mutex);
6090 fail:
6091         drm_gem_object_unreference_unlocked(&obj->base);
6092         return ret;
6093 }
6094
6095 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6096 {
6097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6098
6099         intel_crtc->cursor_x = x;
6100         intel_crtc->cursor_y = y;
6101
6102         intel_crtc_update_cursor(crtc, true);
6103
6104         return 0;
6105 }
6106
6107 /** Sets the color ramps on behalf of RandR */
6108 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6109                                  u16 blue, int regno)
6110 {
6111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6112
6113         intel_crtc->lut_r[regno] = red >> 8;
6114         intel_crtc->lut_g[regno] = green >> 8;
6115         intel_crtc->lut_b[regno] = blue >> 8;
6116 }
6117
6118 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6119                              u16 *blue, int regno)
6120 {
6121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122
6123         *red = intel_crtc->lut_r[regno] << 8;
6124         *green = intel_crtc->lut_g[regno] << 8;
6125         *blue = intel_crtc->lut_b[regno] << 8;
6126 }
6127
6128 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6129                                  u16 *blue, uint32_t start, uint32_t size)
6130 {
6131         int end = (start + size > 256) ? 256 : start + size, i;
6132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6133
6134         for (i = start; i < end; i++) {
6135                 intel_crtc->lut_r[i] = red[i] >> 8;
6136                 intel_crtc->lut_g[i] = green[i] >> 8;
6137                 intel_crtc->lut_b[i] = blue[i] >> 8;
6138         }
6139
6140         intel_crtc_load_lut(crtc);
6141 }
6142
6143 /**
6144  * Get a pipe with a simple mode set on it for doing load-based monitor
6145  * detection.
6146  *
6147  * It will be up to the load-detect code to adjust the pipe as appropriate for
6148  * its requirements.  The pipe will be connected to no other encoders.
6149  *
6150  * Currently this code will only succeed if there is a pipe with no encoders
6151  * configured for it.  In the future, it could choose to temporarily disable
6152  * some outputs to free up a pipe for its use.
6153  *
6154  * \return crtc, or NULL if no pipes are available.
6155  */
6156
6157 /* VESA 640x480x72Hz mode to set on the pipe */
6158 static struct drm_display_mode load_detect_mode = {
6159         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6160                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6161 };
6162
6163 static struct drm_framebuffer *
6164 intel_framebuffer_create(struct drm_device *dev,
6165                          struct drm_mode_fb_cmd2 *mode_cmd,
6166                          struct drm_i915_gem_object *obj)
6167 {
6168         struct intel_framebuffer *intel_fb;
6169         int ret;
6170
6171         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6172         if (!intel_fb) {
6173                 drm_gem_object_unreference_unlocked(&obj->base);
6174                 return ERR_PTR(-ENOMEM);
6175         }
6176
6177         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6178         if (ret) {
6179                 drm_gem_object_unreference_unlocked(&obj->base);
6180                 kfree(intel_fb);
6181                 return ERR_PTR(ret);
6182         }
6183
6184         return &intel_fb->base;
6185 }
6186
6187 static u32
6188 intel_framebuffer_pitch_for_width(int width, int bpp)
6189 {
6190         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6191         return ALIGN(pitch, 64);
6192 }
6193
6194 static u32
6195 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6196 {
6197         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6198         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6199 }
6200
6201 static struct drm_framebuffer *
6202 intel_framebuffer_create_for_mode(struct drm_device *dev,
6203                                   struct drm_display_mode *mode,
6204                                   int depth, int bpp)
6205 {
6206         struct drm_i915_gem_object *obj;
6207         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6208
6209         obj = i915_gem_alloc_object(dev,
6210                                     intel_framebuffer_size_for_mode(mode, bpp));
6211         if (obj == NULL)
6212                 return ERR_PTR(-ENOMEM);
6213
6214         mode_cmd.width = mode->hdisplay;
6215         mode_cmd.height = mode->vdisplay;
6216         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6217                                                                 bpp);
6218         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6219
6220         return intel_framebuffer_create(dev, &mode_cmd, obj);
6221 }
6222
6223 static struct drm_framebuffer *
6224 mode_fits_in_fbdev(struct drm_device *dev,
6225                    struct drm_display_mode *mode)
6226 {
6227         struct drm_i915_private *dev_priv = dev->dev_private;
6228         struct drm_i915_gem_object *obj;
6229         struct drm_framebuffer *fb;
6230
6231         if (dev_priv->fbdev == NULL)
6232                 return NULL;
6233
6234         obj = dev_priv->fbdev->ifb.obj;
6235         if (obj == NULL)
6236                 return NULL;
6237
6238         fb = &dev_priv->fbdev->ifb.base;
6239         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6240                                                                fb->bits_per_pixel))
6241                 return NULL;
6242
6243         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6244                 return NULL;
6245
6246         return fb;
6247 }
6248
6249 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6250                                 struct drm_display_mode *mode,
6251                                 struct intel_load_detect_pipe *old)
6252 {
6253         struct intel_crtc *intel_crtc;
6254         struct intel_encoder *intel_encoder =
6255                 intel_attached_encoder(connector);
6256         struct drm_crtc *possible_crtc;
6257         struct drm_encoder *encoder = &intel_encoder->base;
6258         struct drm_crtc *crtc = NULL;
6259         struct drm_device *dev = encoder->dev;
6260         struct drm_framebuffer *fb;
6261         int i = -1;
6262
6263         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6264                       connector->base.id, drm_get_connector_name(connector),
6265                       encoder->base.id, drm_get_encoder_name(encoder));
6266
6267         /*
6268          * Algorithm gets a little messy:
6269          *
6270          *   - if the connector already has an assigned crtc, use it (but make
6271          *     sure it's on first)
6272          *
6273          *   - try to find the first unused crtc that can drive this connector,
6274          *     and use that if we find one
6275          */
6276
6277         /* See if we already have a CRTC for this connector */
6278         if (encoder->crtc) {
6279                 crtc = encoder->crtc;
6280
6281                 old->dpms_mode = connector->dpms;
6282                 old->load_detect_temp = false;
6283
6284                 /* Make sure the crtc and connector are running */
6285                 if (connector->dpms != DRM_MODE_DPMS_ON)
6286                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6287
6288                 return true;
6289         }
6290
6291         /* Find an unused one (if possible) */
6292         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6293                 i++;
6294                 if (!(encoder->possible_crtcs & (1 << i)))
6295                         continue;
6296                 if (!possible_crtc->enabled) {
6297                         crtc = possible_crtc;
6298                         break;
6299                 }
6300         }
6301
6302         /*
6303          * If we didn't find an unused CRTC, don't use any.
6304          */
6305         if (!crtc) {
6306                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6307                 return false;
6308         }
6309
6310         intel_encoder->new_crtc = to_intel_crtc(crtc);
6311         to_intel_connector(connector)->new_encoder = intel_encoder;
6312
6313         intel_crtc = to_intel_crtc(crtc);
6314         old->dpms_mode = connector->dpms;
6315         old->load_detect_temp = true;
6316         old->release_fb = NULL;
6317
6318         if (!mode)
6319                 mode = &load_detect_mode;
6320
6321         /* We need a framebuffer large enough to accommodate all accesses
6322          * that the plane may generate whilst we perform load detection.
6323          * We can not rely on the fbcon either being present (we get called
6324          * during its initialisation to detect all boot displays, or it may
6325          * not even exist) or that it is large enough to satisfy the
6326          * requested mode.
6327          */
6328         fb = mode_fits_in_fbdev(dev, mode);
6329         if (fb == NULL) {
6330                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6331                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6332                 old->release_fb = fb;
6333         } else
6334                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6335         if (IS_ERR(fb)) {
6336                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6337                 return false;
6338         }
6339
6340         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6341                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6342                 if (old->release_fb)
6343                         old->release_fb->funcs->destroy(old->release_fb);
6344                 return false;
6345         }
6346
6347         /* let the connector get through one full cycle before testing */
6348         intel_wait_for_vblank(dev, intel_crtc->pipe);
6349         return true;
6350 }
6351
6352 void intel_release_load_detect_pipe(struct drm_connector *connector,
6353                                     struct intel_load_detect_pipe *old)
6354 {
6355         struct intel_encoder *intel_encoder =
6356                 intel_attached_encoder(connector);
6357         struct drm_encoder *encoder = &intel_encoder->base;
6358
6359         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6360                       connector->base.id, drm_get_connector_name(connector),
6361                       encoder->base.id, drm_get_encoder_name(encoder));
6362
6363         if (old->load_detect_temp) {
6364                 struct drm_crtc *crtc = encoder->crtc;
6365
6366                 to_intel_connector(connector)->new_encoder = NULL;
6367                 intel_encoder->new_crtc = NULL;
6368                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6369
6370                 if (old->release_fb)
6371                         old->release_fb->funcs->destroy(old->release_fb);
6372
6373                 return;
6374         }
6375
6376         /* Switch crtc and encoder back off if necessary */
6377         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6378                 connector->funcs->dpms(connector, old->dpms_mode);
6379 }
6380
6381 /* Returns the clock of the currently programmed mode of the given pipe. */
6382 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6383 {
6384         struct drm_i915_private *dev_priv = dev->dev_private;
6385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386         int pipe = intel_crtc->pipe;
6387         u32 dpll = I915_READ(DPLL(pipe));
6388         u32 fp;
6389         intel_clock_t clock;
6390
6391         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6392                 fp = I915_READ(FP0(pipe));
6393         else
6394                 fp = I915_READ(FP1(pipe));
6395
6396         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6397         if (IS_PINEVIEW(dev)) {
6398                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6399                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6400         } else {
6401                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6402                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6403         }
6404
6405         if (!IS_GEN2(dev)) {
6406                 if (IS_PINEVIEW(dev))
6407                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6408                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6409                 else
6410                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6411                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6412
6413                 switch (dpll & DPLL_MODE_MASK) {
6414                 case DPLLB_MODE_DAC_SERIAL:
6415                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6416                                 5 : 10;
6417                         break;
6418                 case DPLLB_MODE_LVDS:
6419                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6420                                 7 : 14;
6421                         break;
6422                 default:
6423                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6424                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6425                         return 0;
6426                 }
6427
6428                 /* XXX: Handle the 100Mhz refclk */
6429                 intel_clock(dev, 96000, &clock);
6430         } else {
6431                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6432
6433                 if (is_lvds) {
6434                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6435                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6436                         clock.p2 = 14;
6437
6438                         if ((dpll & PLL_REF_INPUT_MASK) ==
6439                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6440                                 /* XXX: might not be 66MHz */
6441                                 intel_clock(dev, 66000, &clock);
6442                         } else
6443                                 intel_clock(dev, 48000, &clock);
6444                 } else {
6445                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6446                                 clock.p1 = 2;
6447                         else {
6448                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6449                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6450                         }
6451                         if (dpll & PLL_P2_DIVIDE_BY_4)
6452                                 clock.p2 = 4;
6453                         else
6454                                 clock.p2 = 2;
6455
6456                         intel_clock(dev, 48000, &clock);
6457                 }
6458         }
6459
6460         /* XXX: It would be nice to validate the clocks, but we can't reuse
6461          * i830PllIsValid() because it relies on the xf86_config connector
6462          * configuration being accurate, which it isn't necessarily.
6463          */
6464
6465         return clock.dot;
6466 }
6467
6468 /** Returns the currently programmed mode of the given pipe. */
6469 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6470                                              struct drm_crtc *crtc)
6471 {
6472         struct drm_i915_private *dev_priv = dev->dev_private;
6473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6474         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6475         struct drm_display_mode *mode;
6476         int htot = I915_READ(HTOTAL(cpu_transcoder));
6477         int hsync = I915_READ(HSYNC(cpu_transcoder));
6478         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6479         int vsync = I915_READ(VSYNC(cpu_transcoder));
6480
6481         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6482         if (!mode)
6483                 return NULL;
6484
6485         mode->clock = intel_crtc_clock_get(dev, crtc);
6486         mode->hdisplay = (htot & 0xffff) + 1;
6487         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6488         mode->hsync_start = (hsync & 0xffff) + 1;
6489         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6490         mode->vdisplay = (vtot & 0xffff) + 1;
6491         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6492         mode->vsync_start = (vsync & 0xffff) + 1;
6493         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6494
6495         drm_mode_set_name(mode);
6496
6497         return mode;
6498 }
6499
6500 static void intel_increase_pllclock(struct drm_crtc *crtc)
6501 {
6502         struct drm_device *dev = crtc->dev;
6503         drm_i915_private_t *dev_priv = dev->dev_private;
6504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6505         int pipe = intel_crtc->pipe;
6506         int dpll_reg = DPLL(pipe);
6507         int dpll;
6508
6509         if (HAS_PCH_SPLIT(dev))
6510                 return;
6511
6512         if (!dev_priv->lvds_downclock_avail)
6513                 return;
6514
6515         dpll = I915_READ(dpll_reg);
6516         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6517                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6518
6519                 assert_panel_unlocked(dev_priv, pipe);
6520
6521                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6522                 I915_WRITE(dpll_reg, dpll);
6523                 intel_wait_for_vblank(dev, pipe);
6524
6525                 dpll = I915_READ(dpll_reg);
6526                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6527                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6528         }
6529 }
6530
6531 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6532 {
6533         struct drm_device *dev = crtc->dev;
6534         drm_i915_private_t *dev_priv = dev->dev_private;
6535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6536
6537         if (HAS_PCH_SPLIT(dev))
6538                 return;
6539
6540         if (!dev_priv->lvds_downclock_avail)
6541                 return;
6542
6543         /*
6544          * Since this is called by a timer, we should never get here in
6545          * the manual case.
6546          */
6547         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6548                 int pipe = intel_crtc->pipe;
6549                 int dpll_reg = DPLL(pipe);
6550                 int dpll;
6551
6552                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6553
6554                 assert_panel_unlocked(dev_priv, pipe);
6555
6556                 dpll = I915_READ(dpll_reg);
6557                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6558                 I915_WRITE(dpll_reg, dpll);
6559                 intel_wait_for_vblank(dev, pipe);
6560                 dpll = I915_READ(dpll_reg);
6561                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6562                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6563         }
6564
6565 }
6566
6567 void intel_mark_busy(struct drm_device *dev)
6568 {
6569         i915_update_gfx_val(dev->dev_private);
6570 }
6571
6572 void intel_mark_idle(struct drm_device *dev)
6573 {
6574 }
6575
6576 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6577 {
6578         struct drm_device *dev = obj->base.dev;
6579         struct drm_crtc *crtc;
6580
6581         if (!i915_powersave)
6582                 return;
6583
6584         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6585                 if (!crtc->fb)
6586                         continue;
6587
6588                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6589                         intel_increase_pllclock(crtc);
6590         }
6591 }
6592
6593 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6594 {
6595         struct drm_device *dev = obj->base.dev;
6596         struct drm_crtc *crtc;
6597
6598         if (!i915_powersave)
6599                 return;
6600
6601         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6602                 if (!crtc->fb)
6603                         continue;
6604
6605                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6606                         intel_decrease_pllclock(crtc);
6607         }
6608 }
6609
6610 static void intel_crtc_destroy(struct drm_crtc *crtc)
6611 {
6612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6613         struct drm_device *dev = crtc->dev;
6614         struct intel_unpin_work *work;
6615         unsigned long flags;
6616
6617         spin_lock_irqsave(&dev->event_lock, flags);
6618         work = intel_crtc->unpin_work;
6619         intel_crtc->unpin_work = NULL;
6620         spin_unlock_irqrestore(&dev->event_lock, flags);
6621
6622         if (work) {
6623                 cancel_work_sync(&work->work);
6624                 kfree(work);
6625         }
6626
6627         drm_crtc_cleanup(crtc);
6628
6629         kfree(intel_crtc);
6630 }
6631
6632 static void intel_unpin_work_fn(struct work_struct *__work)
6633 {
6634         struct intel_unpin_work *work =
6635                 container_of(__work, struct intel_unpin_work, work);
6636         struct drm_device *dev = work->crtc->dev;
6637
6638         mutex_lock(&dev->struct_mutex);
6639         intel_unpin_fb_obj(work->old_fb_obj);
6640         drm_gem_object_unreference(&work->pending_flip_obj->base);
6641         drm_gem_object_unreference(&work->old_fb_obj->base);
6642
6643         intel_update_fbc(dev);
6644         mutex_unlock(&dev->struct_mutex);
6645
6646         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6647         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6648
6649         kfree(work);
6650 }
6651
6652 static void do_intel_finish_page_flip(struct drm_device *dev,
6653                                       struct drm_crtc *crtc)
6654 {
6655         drm_i915_private_t *dev_priv = dev->dev_private;
6656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6657         struct intel_unpin_work *work;
6658         struct drm_i915_gem_object *obj;
6659         unsigned long flags;
6660
6661         /* Ignore early vblank irqs */
6662         if (intel_crtc == NULL)
6663                 return;
6664
6665         spin_lock_irqsave(&dev->event_lock, flags);
6666         work = intel_crtc->unpin_work;
6667         if (work == NULL || !work->pending) {
6668                 spin_unlock_irqrestore(&dev->event_lock, flags);
6669                 return;
6670         }
6671
6672         intel_crtc->unpin_work = NULL;
6673
6674         if (work->event)
6675                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6676
6677         drm_vblank_put(dev, intel_crtc->pipe);
6678
6679         spin_unlock_irqrestore(&dev->event_lock, flags);
6680
6681         obj = work->old_fb_obj;
6682
6683         wake_up(&dev_priv->pending_flip_queue);
6684
6685         queue_work(dev_priv->wq, &work->work);
6686
6687         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6688 }
6689
6690 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6691 {
6692         drm_i915_private_t *dev_priv = dev->dev_private;
6693         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6694
6695         do_intel_finish_page_flip(dev, crtc);
6696 }
6697
6698 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6699 {
6700         drm_i915_private_t *dev_priv = dev->dev_private;
6701         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6702
6703         do_intel_finish_page_flip(dev, crtc);
6704 }
6705
6706 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6707 {
6708         drm_i915_private_t *dev_priv = dev->dev_private;
6709         struct intel_crtc *intel_crtc =
6710                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6711         unsigned long flags;
6712
6713         spin_lock_irqsave(&dev->event_lock, flags);
6714         if (intel_crtc->unpin_work) {
6715                 if ((++intel_crtc->unpin_work->pending) > 1)
6716                         DRM_ERROR("Prepared flip multiple times\n");
6717         } else {
6718                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6719         }
6720         spin_unlock_irqrestore(&dev->event_lock, flags);
6721 }
6722
6723 static int intel_gen2_queue_flip(struct drm_device *dev,
6724                                  struct drm_crtc *crtc,
6725                                  struct drm_framebuffer *fb,
6726                                  struct drm_i915_gem_object *obj)
6727 {
6728         struct drm_i915_private *dev_priv = dev->dev_private;
6729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6730         u32 flip_mask;
6731         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6732         int ret;
6733
6734         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6735         if (ret)
6736                 goto err;
6737
6738         ret = intel_ring_begin(ring, 6);
6739         if (ret)
6740                 goto err_unpin;
6741
6742         /* Can't queue multiple flips, so wait for the previous
6743          * one to finish before executing the next.
6744          */
6745         if (intel_crtc->plane)
6746                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6747         else
6748                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6749         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6750         intel_ring_emit(ring, MI_NOOP);
6751         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6752                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6753         intel_ring_emit(ring, fb->pitches[0]);
6754         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6755         intel_ring_emit(ring, 0); /* aux display base address, unused */
6756         intel_ring_advance(ring);
6757         return 0;
6758
6759 err_unpin:
6760         intel_unpin_fb_obj(obj);
6761 err:
6762         return ret;
6763 }
6764
6765 static int intel_gen3_queue_flip(struct drm_device *dev,
6766                                  struct drm_crtc *crtc,
6767                                  struct drm_framebuffer *fb,
6768                                  struct drm_i915_gem_object *obj)
6769 {
6770         struct drm_i915_private *dev_priv = dev->dev_private;
6771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6772         u32 flip_mask;
6773         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6774         int ret;
6775
6776         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6777         if (ret)
6778                 goto err;
6779
6780         ret = intel_ring_begin(ring, 6);
6781         if (ret)
6782                 goto err_unpin;
6783
6784         if (intel_crtc->plane)
6785                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6786         else
6787                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6788         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6789         intel_ring_emit(ring, MI_NOOP);
6790         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6791                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6792         intel_ring_emit(ring, fb->pitches[0]);
6793         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6794         intel_ring_emit(ring, MI_NOOP);
6795
6796         intel_ring_advance(ring);
6797         return 0;
6798
6799 err_unpin:
6800         intel_unpin_fb_obj(obj);
6801 err:
6802         return ret;
6803 }
6804
6805 static int intel_gen4_queue_flip(struct drm_device *dev,
6806                                  struct drm_crtc *crtc,
6807                                  struct drm_framebuffer *fb,
6808                                  struct drm_i915_gem_object *obj)
6809 {
6810         struct drm_i915_private *dev_priv = dev->dev_private;
6811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6812         uint32_t pf, pipesrc;
6813         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6814         int ret;
6815
6816         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6817         if (ret)
6818                 goto err;
6819
6820         ret = intel_ring_begin(ring, 4);
6821         if (ret)
6822                 goto err_unpin;
6823
6824         /* i965+ uses the linear or tiled offsets from the
6825          * Display Registers (which do not change across a page-flip)
6826          * so we need only reprogram the base address.
6827          */
6828         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6829                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6830         intel_ring_emit(ring, fb->pitches[0]);
6831         intel_ring_emit(ring,
6832                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6833                         obj->tiling_mode);
6834
6835         /* XXX Enabling the panel-fitter across page-flip is so far
6836          * untested on non-native modes, so ignore it for now.
6837          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6838          */
6839         pf = 0;
6840         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6841         intel_ring_emit(ring, pf | pipesrc);
6842         intel_ring_advance(ring);
6843         return 0;
6844
6845 err_unpin:
6846         intel_unpin_fb_obj(obj);
6847 err:
6848         return ret;
6849 }
6850
6851 static int intel_gen6_queue_flip(struct drm_device *dev,
6852                                  struct drm_crtc *crtc,
6853                                  struct drm_framebuffer *fb,
6854                                  struct drm_i915_gem_object *obj)
6855 {
6856         struct drm_i915_private *dev_priv = dev->dev_private;
6857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6858         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6859         uint32_t pf, pipesrc;
6860         int ret;
6861
6862         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6863         if (ret)
6864                 goto err;
6865
6866         ret = intel_ring_begin(ring, 4);
6867         if (ret)
6868                 goto err_unpin;
6869
6870         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6871                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6872         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6873         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6874
6875         /* Contrary to the suggestions in the documentation,
6876          * "Enable Panel Fitter" does not seem to be required when page
6877          * flipping with a non-native mode, and worse causes a normal
6878          * modeset to fail.
6879          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6880          */
6881         pf = 0;
6882         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6883         intel_ring_emit(ring, pf | pipesrc);
6884         intel_ring_advance(ring);
6885         return 0;
6886
6887 err_unpin:
6888         intel_unpin_fb_obj(obj);
6889 err:
6890         return ret;
6891 }
6892
6893 /*
6894  * On gen7 we currently use the blit ring because (in early silicon at least)
6895  * the render ring doesn't give us interrpts for page flip completion, which
6896  * means clients will hang after the first flip is queued.  Fortunately the
6897  * blit ring generates interrupts properly, so use it instead.
6898  */
6899 static int intel_gen7_queue_flip(struct drm_device *dev,
6900                                  struct drm_crtc *crtc,
6901                                  struct drm_framebuffer *fb,
6902                                  struct drm_i915_gem_object *obj)
6903 {
6904         struct drm_i915_private *dev_priv = dev->dev_private;
6905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6906         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6907         uint32_t plane_bit = 0;
6908         int ret;
6909
6910         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6911         if (ret)
6912                 goto err;
6913
6914         switch(intel_crtc->plane) {
6915         case PLANE_A:
6916                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6917                 break;
6918         case PLANE_B:
6919                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6920                 break;
6921         case PLANE_C:
6922                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6923                 break;
6924         default:
6925                 WARN_ONCE(1, "unknown plane in flip command\n");
6926                 ret = -ENODEV;
6927                 goto err_unpin;
6928         }
6929
6930         ret = intel_ring_begin(ring, 4);
6931         if (ret)
6932                 goto err_unpin;
6933
6934         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6935         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6936         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6937         intel_ring_emit(ring, (MI_NOOP));
6938         intel_ring_advance(ring);
6939         return 0;
6940
6941 err_unpin:
6942         intel_unpin_fb_obj(obj);
6943 err:
6944         return ret;
6945 }
6946
6947 static int intel_default_queue_flip(struct drm_device *dev,
6948                                     struct drm_crtc *crtc,
6949                                     struct drm_framebuffer *fb,
6950                                     struct drm_i915_gem_object *obj)
6951 {
6952         return -ENODEV;
6953 }
6954
6955 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6956                                 struct drm_framebuffer *fb,
6957                                 struct drm_pending_vblank_event *event)
6958 {
6959         struct drm_device *dev = crtc->dev;
6960         struct drm_i915_private *dev_priv = dev->dev_private;
6961         struct intel_framebuffer *intel_fb;
6962         struct drm_i915_gem_object *obj;
6963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6964         struct intel_unpin_work *work;
6965         unsigned long flags;
6966         int ret;
6967
6968         /* Can't change pixel format via MI display flips. */
6969         if (fb->pixel_format != crtc->fb->pixel_format)
6970                 return -EINVAL;
6971
6972         /*
6973          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6974          * Note that pitch changes could also affect these register.
6975          */
6976         if (INTEL_INFO(dev)->gen > 3 &&
6977             (fb->offsets[0] != crtc->fb->offsets[0] ||
6978              fb->pitches[0] != crtc->fb->pitches[0]))
6979                 return -EINVAL;
6980
6981         work = kzalloc(sizeof *work, GFP_KERNEL);
6982         if (work == NULL)
6983                 return -ENOMEM;
6984
6985         work->event = event;
6986         work->crtc = crtc;
6987         intel_fb = to_intel_framebuffer(crtc->fb);
6988         work->old_fb_obj = intel_fb->obj;
6989         INIT_WORK(&work->work, intel_unpin_work_fn);
6990
6991         ret = drm_vblank_get(dev, intel_crtc->pipe);
6992         if (ret)
6993                 goto free_work;
6994
6995         /* We borrow the event spin lock for protecting unpin_work */
6996         spin_lock_irqsave(&dev->event_lock, flags);
6997         if (intel_crtc->unpin_work) {
6998                 spin_unlock_irqrestore(&dev->event_lock, flags);
6999                 kfree(work);
7000                 drm_vblank_put(dev, intel_crtc->pipe);
7001
7002                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7003                 return -EBUSY;
7004         }
7005         intel_crtc->unpin_work = work;
7006         spin_unlock_irqrestore(&dev->event_lock, flags);
7007
7008         intel_fb = to_intel_framebuffer(fb);
7009         obj = intel_fb->obj;
7010
7011         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7012                 flush_workqueue(dev_priv->wq);
7013
7014         ret = i915_mutex_lock_interruptible(dev);
7015         if (ret)
7016                 goto cleanup;
7017
7018         /* Reference the objects for the scheduled work. */
7019         drm_gem_object_reference(&work->old_fb_obj->base);
7020         drm_gem_object_reference(&obj->base);
7021
7022         crtc->fb = fb;
7023
7024         work->pending_flip_obj = obj;
7025
7026         work->enable_stall_check = true;
7027
7028         atomic_inc(&intel_crtc->unpin_work_count);
7029
7030         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7031         if (ret)
7032                 goto cleanup_pending;
7033
7034         intel_disable_fbc(dev);
7035         intel_mark_fb_busy(obj);
7036         mutex_unlock(&dev->struct_mutex);
7037
7038         trace_i915_flip_request(intel_crtc->plane, obj);
7039
7040         return 0;
7041
7042 cleanup_pending:
7043         atomic_dec(&intel_crtc->unpin_work_count);
7044         drm_gem_object_unreference(&work->old_fb_obj->base);
7045         drm_gem_object_unreference(&obj->base);
7046         mutex_unlock(&dev->struct_mutex);
7047
7048 cleanup:
7049         spin_lock_irqsave(&dev->event_lock, flags);
7050         intel_crtc->unpin_work = NULL;
7051         spin_unlock_irqrestore(&dev->event_lock, flags);
7052
7053         drm_vblank_put(dev, intel_crtc->pipe);
7054 free_work:
7055         kfree(work);
7056
7057         return ret;
7058 }
7059
7060 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7061         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7062         .load_lut = intel_crtc_load_lut,
7063         .disable = intel_crtc_noop,
7064 };
7065
7066 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7067 {
7068         struct intel_encoder *other_encoder;
7069         struct drm_crtc *crtc = &encoder->new_crtc->base;
7070
7071         if (WARN_ON(!crtc))
7072                 return false;
7073
7074         list_for_each_entry(other_encoder,
7075                             &crtc->dev->mode_config.encoder_list,
7076                             base.head) {
7077
7078                 if (&other_encoder->new_crtc->base != crtc ||
7079                     encoder == other_encoder)
7080                         continue;
7081                 else
7082                         return true;
7083         }
7084
7085         return false;
7086 }
7087
7088 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7089                                   struct drm_crtc *crtc)
7090 {
7091         struct drm_device *dev;
7092         struct drm_crtc *tmp;
7093         int crtc_mask = 1;
7094
7095         WARN(!crtc, "checking null crtc?\n");
7096
7097         dev = crtc->dev;
7098
7099         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7100                 if (tmp == crtc)
7101                         break;
7102                 crtc_mask <<= 1;
7103         }
7104
7105         if (encoder->possible_crtcs & crtc_mask)
7106                 return true;
7107         return false;
7108 }
7109
7110 /**
7111  * intel_modeset_update_staged_output_state
7112  *
7113  * Updates the staged output configuration state, e.g. after we've read out the
7114  * current hw state.
7115  */
7116 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7117 {
7118         struct intel_encoder *encoder;
7119         struct intel_connector *connector;
7120
7121         list_for_each_entry(connector, &dev->mode_config.connector_list,
7122                             base.head) {
7123                 connector->new_encoder =
7124                         to_intel_encoder(connector->base.encoder);
7125         }
7126
7127         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7128                             base.head) {
7129                 encoder->new_crtc =
7130                         to_intel_crtc(encoder->base.crtc);
7131         }
7132 }
7133
7134 /**
7135  * intel_modeset_commit_output_state
7136  *
7137  * This function copies the stage display pipe configuration to the real one.
7138  */
7139 static void intel_modeset_commit_output_state(struct drm_device *dev)
7140 {
7141         struct intel_encoder *encoder;
7142         struct intel_connector *connector;
7143
7144         list_for_each_entry(connector, &dev->mode_config.connector_list,
7145                             base.head) {
7146                 connector->base.encoder = &connector->new_encoder->base;
7147         }
7148
7149         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7150                             base.head) {
7151                 encoder->base.crtc = &encoder->new_crtc->base;
7152         }
7153 }
7154
7155 static struct drm_display_mode *
7156 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7157                             struct drm_display_mode *mode)
7158 {
7159         struct drm_device *dev = crtc->dev;
7160         struct drm_display_mode *adjusted_mode;
7161         struct drm_encoder_helper_funcs *encoder_funcs;
7162         struct intel_encoder *encoder;
7163
7164         adjusted_mode = drm_mode_duplicate(dev, mode);
7165         if (!adjusted_mode)
7166                 return ERR_PTR(-ENOMEM);
7167
7168         /* Pass our mode to the connectors and the CRTC to give them a chance to
7169          * adjust it according to limitations or connector properties, and also
7170          * a chance to reject the mode entirely.
7171          */
7172         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7173                             base.head) {
7174
7175                 if (&encoder->new_crtc->base != crtc)
7176                         continue;
7177                 encoder_funcs = encoder->base.helper_private;
7178                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7179                                                 adjusted_mode))) {
7180                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7181                         goto fail;
7182                 }
7183         }
7184
7185         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7186                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7187                 goto fail;
7188         }
7189         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7190
7191         return adjusted_mode;
7192 fail:
7193         drm_mode_destroy(dev, adjusted_mode);
7194         return ERR_PTR(-EINVAL);
7195 }
7196
7197 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7198  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7199 static void
7200 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7201                              unsigned *prepare_pipes, unsigned *disable_pipes)
7202 {
7203         struct intel_crtc *intel_crtc;
7204         struct drm_device *dev = crtc->dev;
7205         struct intel_encoder *encoder;
7206         struct intel_connector *connector;
7207         struct drm_crtc *tmp_crtc;
7208
7209         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7210
7211         /* Check which crtcs have changed outputs connected to them, these need
7212          * to be part of the prepare_pipes mask. We don't (yet) support global
7213          * modeset across multiple crtcs, so modeset_pipes will only have one
7214          * bit set at most. */
7215         list_for_each_entry(connector, &dev->mode_config.connector_list,
7216                             base.head) {
7217                 if (connector->base.encoder == &connector->new_encoder->base)
7218                         continue;
7219
7220                 if (connector->base.encoder) {
7221                         tmp_crtc = connector->base.encoder->crtc;
7222
7223                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7224                 }
7225
7226                 if (connector->new_encoder)
7227                         *prepare_pipes |=
7228                                 1 << connector->new_encoder->new_crtc->pipe;
7229         }
7230
7231         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7232                             base.head) {
7233                 if (encoder->base.crtc == &encoder->new_crtc->base)
7234                         continue;
7235
7236                 if (encoder->base.crtc) {
7237                         tmp_crtc = encoder->base.crtc;
7238
7239                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7240                 }
7241
7242                 if (encoder->new_crtc)
7243                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7244         }
7245
7246         /* Check for any pipes that will be fully disabled ... */
7247         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7248                             base.head) {
7249                 bool used = false;
7250
7251                 /* Don't try to disable disabled crtcs. */
7252                 if (!intel_crtc->base.enabled)
7253                         continue;
7254
7255                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7256                                     base.head) {
7257                         if (encoder->new_crtc == intel_crtc)
7258                                 used = true;
7259                 }
7260
7261                 if (!used)
7262                         *disable_pipes |= 1 << intel_crtc->pipe;
7263         }
7264
7265
7266         /* set_mode is also used to update properties on life display pipes. */
7267         intel_crtc = to_intel_crtc(crtc);
7268         if (crtc->enabled)
7269                 *prepare_pipes |= 1 << intel_crtc->pipe;
7270
7271         /* We only support modeset on one single crtc, hence we need to do that
7272          * only for the passed in crtc iff we change anything else than just
7273          * disable crtcs.
7274          *
7275          * This is actually not true, to be fully compatible with the old crtc
7276          * helper we automatically disable _any_ output (i.e. doesn't need to be
7277          * connected to the crtc we're modesetting on) if it's disconnected.
7278          * Which is a rather nutty api (since changed the output configuration
7279          * without userspace's explicit request can lead to confusion), but
7280          * alas. Hence we currently need to modeset on all pipes we prepare. */
7281         if (*prepare_pipes)
7282                 *modeset_pipes = *prepare_pipes;
7283
7284         /* ... and mask these out. */
7285         *modeset_pipes &= ~(*disable_pipes);
7286         *prepare_pipes &= ~(*disable_pipes);
7287 }
7288
7289 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7290 {
7291         struct drm_encoder *encoder;
7292         struct drm_device *dev = crtc->dev;
7293
7294         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7295                 if (encoder->crtc == crtc)
7296                         return true;
7297
7298         return false;
7299 }
7300
7301 static void
7302 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7303 {
7304         struct intel_encoder *intel_encoder;
7305         struct intel_crtc *intel_crtc;
7306         struct drm_connector *connector;
7307
7308         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7309                             base.head) {
7310                 if (!intel_encoder->base.crtc)
7311                         continue;
7312
7313                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7314
7315                 if (prepare_pipes & (1 << intel_crtc->pipe))
7316                         intel_encoder->connectors_active = false;
7317         }
7318
7319         intel_modeset_commit_output_state(dev);
7320
7321         /* Update computed state. */
7322         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7323                             base.head) {
7324                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7325         }
7326
7327         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7328                 if (!connector->encoder || !connector->encoder->crtc)
7329                         continue;
7330
7331                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7332
7333                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7334                         struct drm_property *dpms_property =
7335                                 dev->mode_config.dpms_property;
7336
7337                         connector->dpms = DRM_MODE_DPMS_ON;
7338                         drm_object_property_set_value(&connector->base,
7339                                                          dpms_property,
7340                                                          DRM_MODE_DPMS_ON);
7341
7342                         intel_encoder = to_intel_encoder(connector->encoder);
7343                         intel_encoder->connectors_active = true;
7344                 }
7345         }
7346
7347 }
7348
7349 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7350         list_for_each_entry((intel_crtc), \
7351                             &(dev)->mode_config.crtc_list, \
7352                             base.head) \
7353                 if (mask & (1 <<(intel_crtc)->pipe)) \
7354
7355 void
7356 intel_modeset_check_state(struct drm_device *dev)
7357 {
7358         struct intel_crtc *crtc;
7359         struct intel_encoder *encoder;
7360         struct intel_connector *connector;
7361
7362         list_for_each_entry(connector, &dev->mode_config.connector_list,
7363                             base.head) {
7364                 /* This also checks the encoder/connector hw state with the
7365                  * ->get_hw_state callbacks. */
7366                 intel_connector_check_state(connector);
7367
7368                 WARN(&connector->new_encoder->base != connector->base.encoder,
7369                      "connector's staged encoder doesn't match current encoder\n");
7370         }
7371
7372         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7373                             base.head) {
7374                 bool enabled = false;
7375                 bool active = false;
7376                 enum pipe pipe, tracked_pipe;
7377
7378                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7379                               encoder->base.base.id,
7380                               drm_get_encoder_name(&encoder->base));
7381
7382                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7383                      "encoder's stage crtc doesn't match current crtc\n");
7384                 WARN(encoder->connectors_active && !encoder->base.crtc,
7385                      "encoder's active_connectors set, but no crtc\n");
7386
7387                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7388                                     base.head) {
7389                         if (connector->base.encoder != &encoder->base)
7390                                 continue;
7391                         enabled = true;
7392                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7393                                 active = true;
7394                 }
7395                 WARN(!!encoder->base.crtc != enabled,
7396                      "encoder's enabled state mismatch "
7397                      "(expected %i, found %i)\n",
7398                      !!encoder->base.crtc, enabled);
7399                 WARN(active && !encoder->base.crtc,
7400                      "active encoder with no crtc\n");
7401
7402                 WARN(encoder->connectors_active != active,
7403                      "encoder's computed active state doesn't match tracked active state "
7404                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7405
7406                 active = encoder->get_hw_state(encoder, &pipe);
7407                 WARN(active != encoder->connectors_active,
7408                      "encoder's hw state doesn't match sw tracking "
7409                      "(expected %i, found %i)\n",
7410                      encoder->connectors_active, active);
7411
7412                 if (!encoder->base.crtc)
7413                         continue;
7414
7415                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7416                 WARN(active && pipe != tracked_pipe,
7417                      "active encoder's pipe doesn't match"
7418                      "(expected %i, found %i)\n",
7419                      tracked_pipe, pipe);
7420
7421         }
7422
7423         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7424                             base.head) {
7425                 bool enabled = false;
7426                 bool active = false;
7427
7428                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7429                               crtc->base.base.id);
7430
7431                 WARN(crtc->active && !crtc->base.enabled,
7432                      "active crtc, but not enabled in sw tracking\n");
7433
7434                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7435                                     base.head) {
7436                         if (encoder->base.crtc != &crtc->base)
7437                                 continue;
7438                         enabled = true;
7439                         if (encoder->connectors_active)
7440                                 active = true;
7441                 }
7442                 WARN(active != crtc->active,
7443                      "crtc's computed active state doesn't match tracked active state "
7444                      "(expected %i, found %i)\n", active, crtc->active);
7445                 WARN(enabled != crtc->base.enabled,
7446                      "crtc's computed enabled state doesn't match tracked enabled state "
7447                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7448
7449                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7450         }
7451 }
7452
7453 bool intel_set_mode(struct drm_crtc *crtc,
7454                     struct drm_display_mode *mode,
7455                     int x, int y, struct drm_framebuffer *fb)
7456 {
7457         struct drm_device *dev = crtc->dev;
7458         drm_i915_private_t *dev_priv = dev->dev_private;
7459         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7460         struct intel_crtc *intel_crtc;
7461         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7462         bool ret = true;
7463
7464         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7465                                      &prepare_pipes, &disable_pipes);
7466
7467         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7468                       modeset_pipes, prepare_pipes, disable_pipes);
7469
7470         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7471                 intel_crtc_disable(&intel_crtc->base);
7472
7473         saved_hwmode = crtc->hwmode;
7474         saved_mode = crtc->mode;
7475
7476         /* Hack: Because we don't (yet) support global modeset on multiple
7477          * crtcs, we don't keep track of the new mode for more than one crtc.
7478          * Hence simply check whether any bit is set in modeset_pipes in all the
7479          * pieces of code that are not yet converted to deal with mutliple crtcs
7480          * changing their mode at the same time. */
7481         adjusted_mode = NULL;
7482         if (modeset_pipes) {
7483                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7484                 if (IS_ERR(adjusted_mode)) {
7485                         return false;
7486                 }
7487         }
7488
7489         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7490                 if (intel_crtc->base.enabled)
7491                         dev_priv->display.crtc_disable(&intel_crtc->base);
7492         }
7493
7494         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7495          * to set it here already despite that we pass it down the callchain.
7496          */
7497         if (modeset_pipes)
7498                 crtc->mode = *mode;
7499
7500         /* Only after disabling all output pipelines that will be changed can we
7501          * update the the output configuration. */
7502         intel_modeset_update_state(dev, prepare_pipes);
7503
7504         if (dev_priv->display.modeset_global_resources)
7505                 dev_priv->display.modeset_global_resources(dev);
7506
7507         /* Set up the DPLL and any encoders state that needs to adjust or depend
7508          * on the DPLL.
7509          */
7510         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7511                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7512                                            mode, adjusted_mode,
7513                                            x, y, fb);
7514                 if (!ret)
7515                     goto done;
7516         }
7517
7518         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7519         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7520                 dev_priv->display.crtc_enable(&intel_crtc->base);
7521
7522         if (modeset_pipes) {
7523                 /* Store real post-adjustment hardware mode. */
7524                 crtc->hwmode = *adjusted_mode;
7525
7526                 /* Calculate and store various constants which
7527                  * are later needed by vblank and swap-completion
7528                  * timestamping. They are derived from true hwmode.
7529                  */
7530                 drm_calc_timestamping_constants(crtc);
7531         }
7532
7533         /* FIXME: add subpixel order */
7534 done:
7535         drm_mode_destroy(dev, adjusted_mode);
7536         if (!ret && crtc->enabled) {
7537                 crtc->hwmode = saved_hwmode;
7538                 crtc->mode = saved_mode;
7539         } else {
7540                 intel_modeset_check_state(dev);
7541         }
7542
7543         return ret;
7544 }
7545
7546 #undef for_each_intel_crtc_masked
7547
7548 static void intel_set_config_free(struct intel_set_config *config)
7549 {
7550         if (!config)
7551                 return;
7552
7553         kfree(config->save_connector_encoders);
7554         kfree(config->save_encoder_crtcs);
7555         kfree(config);
7556 }
7557
7558 static int intel_set_config_save_state(struct drm_device *dev,
7559                                        struct intel_set_config *config)
7560 {
7561         struct drm_encoder *encoder;
7562         struct drm_connector *connector;
7563         int count;
7564
7565         config->save_encoder_crtcs =
7566                 kcalloc(dev->mode_config.num_encoder,
7567                         sizeof(struct drm_crtc *), GFP_KERNEL);
7568         if (!config->save_encoder_crtcs)
7569                 return -ENOMEM;
7570
7571         config->save_connector_encoders =
7572                 kcalloc(dev->mode_config.num_connector,
7573                         sizeof(struct drm_encoder *), GFP_KERNEL);
7574         if (!config->save_connector_encoders)
7575                 return -ENOMEM;
7576
7577         /* Copy data. Note that driver private data is not affected.
7578          * Should anything bad happen only the expected state is
7579          * restored, not the drivers personal bookkeeping.
7580          */
7581         count = 0;
7582         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7583                 config->save_encoder_crtcs[count++] = encoder->crtc;
7584         }
7585
7586         count = 0;
7587         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7588                 config->save_connector_encoders[count++] = connector->encoder;
7589         }
7590
7591         return 0;
7592 }
7593
7594 static void intel_set_config_restore_state(struct drm_device *dev,
7595                                            struct intel_set_config *config)
7596 {
7597         struct intel_encoder *encoder;
7598         struct intel_connector *connector;
7599         int count;
7600
7601         count = 0;
7602         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7603                 encoder->new_crtc =
7604                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7605         }
7606
7607         count = 0;
7608         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7609                 connector->new_encoder =
7610                         to_intel_encoder(config->save_connector_encoders[count++]);
7611         }
7612 }
7613
7614 static void
7615 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7616                                       struct intel_set_config *config)
7617 {
7618
7619         /* We should be able to check here if the fb has the same properties
7620          * and then just flip_or_move it */
7621         if (set->crtc->fb != set->fb) {
7622                 /* If we have no fb then treat it as a full mode set */
7623                 if (set->crtc->fb == NULL) {
7624                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7625                         config->mode_changed = true;
7626                 } else if (set->fb == NULL) {
7627                         config->mode_changed = true;
7628                 } else if (set->fb->depth != set->crtc->fb->depth) {
7629                         config->mode_changed = true;
7630                 } else if (set->fb->bits_per_pixel !=
7631                            set->crtc->fb->bits_per_pixel) {
7632                         config->mode_changed = true;
7633                 } else
7634                         config->fb_changed = true;
7635         }
7636
7637         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7638                 config->fb_changed = true;
7639
7640         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7641                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7642                 drm_mode_debug_printmodeline(&set->crtc->mode);
7643                 drm_mode_debug_printmodeline(set->mode);
7644                 config->mode_changed = true;
7645         }
7646 }
7647
7648 static int
7649 intel_modeset_stage_output_state(struct drm_device *dev,
7650                                  struct drm_mode_set *set,
7651                                  struct intel_set_config *config)
7652 {
7653         struct drm_crtc *new_crtc;
7654         struct intel_connector *connector;
7655         struct intel_encoder *encoder;
7656         int count, ro;
7657
7658         /* The upper layers ensure that we either disabl a crtc or have a list
7659          * of connectors. For paranoia, double-check this. */
7660         WARN_ON(!set->fb && (set->num_connectors != 0));
7661         WARN_ON(set->fb && (set->num_connectors == 0));
7662
7663         count = 0;
7664         list_for_each_entry(connector, &dev->mode_config.connector_list,
7665                             base.head) {
7666                 /* Otherwise traverse passed in connector list and get encoders
7667                  * for them. */
7668                 for (ro = 0; ro < set->num_connectors; ro++) {
7669                         if (set->connectors[ro] == &connector->base) {
7670                                 connector->new_encoder = connector->encoder;
7671                                 break;
7672                         }
7673                 }
7674
7675                 /* If we disable the crtc, disable all its connectors. Also, if
7676                  * the connector is on the changing crtc but not on the new
7677                  * connector list, disable it. */
7678                 if ((!set->fb || ro == set->num_connectors) &&
7679                     connector->base.encoder &&
7680                     connector->base.encoder->crtc == set->crtc) {
7681                         connector->new_encoder = NULL;
7682
7683                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7684                                 connector->base.base.id,
7685                                 drm_get_connector_name(&connector->base));
7686                 }
7687
7688
7689                 if (&connector->new_encoder->base != connector->base.encoder) {
7690                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7691                         config->mode_changed = true;
7692                 }
7693
7694                 /* Disable all disconnected encoders. */
7695                 if (connector->base.status == connector_status_disconnected)
7696                         connector->new_encoder = NULL;
7697         }
7698         /* connector->new_encoder is now updated for all connectors. */
7699
7700         /* Update crtc of enabled connectors. */
7701         count = 0;
7702         list_for_each_entry(connector, &dev->mode_config.connector_list,
7703                             base.head) {
7704                 if (!connector->new_encoder)
7705                         continue;
7706
7707                 new_crtc = connector->new_encoder->base.crtc;
7708
7709                 for (ro = 0; ro < set->num_connectors; ro++) {
7710                         if (set->connectors[ro] == &connector->base)
7711                                 new_crtc = set->crtc;
7712                 }
7713
7714                 /* Make sure the new CRTC will work with the encoder */
7715                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7716                                            new_crtc)) {
7717                         return -EINVAL;
7718                 }
7719                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7720
7721                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7722                         connector->base.base.id,
7723                         drm_get_connector_name(&connector->base),
7724                         new_crtc->base.id);
7725         }
7726
7727         /* Check for any encoders that needs to be disabled. */
7728         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7729                             base.head) {
7730                 list_for_each_entry(connector,
7731                                     &dev->mode_config.connector_list,
7732                                     base.head) {
7733                         if (connector->new_encoder == encoder) {
7734                                 WARN_ON(!connector->new_encoder->new_crtc);
7735
7736                                 goto next_encoder;
7737                         }
7738                 }
7739                 encoder->new_crtc = NULL;
7740 next_encoder:
7741                 /* Only now check for crtc changes so we don't miss encoders
7742                  * that will be disabled. */
7743                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7744                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7745                         config->mode_changed = true;
7746                 }
7747         }
7748         /* Now we've also updated encoder->new_crtc for all encoders. */
7749
7750         return 0;
7751 }
7752
7753 static int intel_crtc_set_config(struct drm_mode_set *set)
7754 {
7755         struct drm_device *dev;
7756         struct drm_mode_set save_set;
7757         struct intel_set_config *config;
7758         int ret;
7759
7760         BUG_ON(!set);
7761         BUG_ON(!set->crtc);
7762         BUG_ON(!set->crtc->helper_private);
7763
7764         if (!set->mode)
7765                 set->fb = NULL;
7766
7767         /* The fb helper likes to play gross jokes with ->mode_set_config.
7768          * Unfortunately the crtc helper doesn't do much at all for this case,
7769          * so we have to cope with this madness until the fb helper is fixed up. */
7770         if (set->fb && set->num_connectors == 0)
7771                 return 0;
7772
7773         if (set->fb) {
7774                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7775                                 set->crtc->base.id, set->fb->base.id,
7776                                 (int)set->num_connectors, set->x, set->y);
7777         } else {
7778                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7779         }
7780
7781         dev = set->crtc->dev;
7782
7783         ret = -ENOMEM;
7784         config = kzalloc(sizeof(*config), GFP_KERNEL);
7785         if (!config)
7786                 goto out_config;
7787
7788         ret = intel_set_config_save_state(dev, config);
7789         if (ret)
7790                 goto out_config;
7791
7792         save_set.crtc = set->crtc;
7793         save_set.mode = &set->crtc->mode;
7794         save_set.x = set->crtc->x;
7795         save_set.y = set->crtc->y;
7796         save_set.fb = set->crtc->fb;
7797
7798         /* Compute whether we need a full modeset, only an fb base update or no
7799          * change at all. In the future we might also check whether only the
7800          * mode changed, e.g. for LVDS where we only change the panel fitter in
7801          * such cases. */
7802         intel_set_config_compute_mode_changes(set, config);
7803
7804         ret = intel_modeset_stage_output_state(dev, set, config);
7805         if (ret)
7806                 goto fail;
7807
7808         if (config->mode_changed) {
7809                 if (set->mode) {
7810                         DRM_DEBUG_KMS("attempting to set mode from"
7811                                         " userspace\n");
7812                         drm_mode_debug_printmodeline(set->mode);
7813                 }
7814
7815                 if (!intel_set_mode(set->crtc, set->mode,
7816                                     set->x, set->y, set->fb)) {
7817                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7818                                   set->crtc->base.id);
7819                         ret = -EINVAL;
7820                         goto fail;
7821                 }
7822         } else if (config->fb_changed) {
7823                 ret = intel_pipe_set_base(set->crtc,
7824                                           set->x, set->y, set->fb);
7825         }
7826
7827         intel_set_config_free(config);
7828
7829         return 0;
7830
7831 fail:
7832         intel_set_config_restore_state(dev, config);
7833
7834         /* Try to restore the config */
7835         if (config->mode_changed &&
7836             !intel_set_mode(save_set.crtc, save_set.mode,
7837                             save_set.x, save_set.y, save_set.fb))
7838                 DRM_ERROR("failed to restore config after modeset failure\n");
7839
7840 out_config:
7841         intel_set_config_free(config);
7842         return ret;
7843 }
7844
7845 static const struct drm_crtc_funcs intel_crtc_funcs = {
7846         .cursor_set = intel_crtc_cursor_set,
7847         .cursor_move = intel_crtc_cursor_move,
7848         .gamma_set = intel_crtc_gamma_set,
7849         .set_config = intel_crtc_set_config,
7850         .destroy = intel_crtc_destroy,
7851         .page_flip = intel_crtc_page_flip,
7852 };
7853
7854 static void intel_cpu_pll_init(struct drm_device *dev)
7855 {
7856         if (HAS_DDI(dev))
7857                 intel_ddi_pll_init(dev);
7858 }
7859
7860 static void intel_pch_pll_init(struct drm_device *dev)
7861 {
7862         drm_i915_private_t *dev_priv = dev->dev_private;
7863         int i;
7864
7865         if (dev_priv->num_pch_pll == 0) {
7866                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7867                 return;
7868         }
7869
7870         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7871                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7872                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7873                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7874         }
7875 }
7876
7877 static void intel_crtc_init(struct drm_device *dev, int pipe)
7878 {
7879         drm_i915_private_t *dev_priv = dev->dev_private;
7880         struct intel_crtc *intel_crtc;
7881         int i;
7882
7883         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7884         if (intel_crtc == NULL)
7885                 return;
7886
7887         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7888
7889         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7890         for (i = 0; i < 256; i++) {
7891                 intel_crtc->lut_r[i] = i;
7892                 intel_crtc->lut_g[i] = i;
7893                 intel_crtc->lut_b[i] = i;
7894         }
7895
7896         /* Swap pipes & planes for FBC on pre-965 */
7897         intel_crtc->pipe = pipe;
7898         intel_crtc->plane = pipe;
7899         intel_crtc->cpu_transcoder = pipe;
7900         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7901                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7902                 intel_crtc->plane = !pipe;
7903         }
7904
7905         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7906                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7907         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7908         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7909
7910         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7911
7912         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7913 }
7914
7915 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7916                                 struct drm_file *file)
7917 {
7918         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7919         struct drm_mode_object *drmmode_obj;
7920         struct intel_crtc *crtc;
7921
7922         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7923                 return -ENODEV;
7924
7925         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7926                         DRM_MODE_OBJECT_CRTC);
7927
7928         if (!drmmode_obj) {
7929                 DRM_ERROR("no such CRTC id\n");
7930                 return -EINVAL;
7931         }
7932
7933         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7934         pipe_from_crtc_id->pipe = crtc->pipe;
7935
7936         return 0;
7937 }
7938
7939 static int intel_encoder_clones(struct intel_encoder *encoder)
7940 {
7941         struct drm_device *dev = encoder->base.dev;
7942         struct intel_encoder *source_encoder;
7943         int index_mask = 0;
7944         int entry = 0;
7945
7946         list_for_each_entry(source_encoder,
7947                             &dev->mode_config.encoder_list, base.head) {
7948
7949                 if (encoder == source_encoder)
7950                         index_mask |= (1 << entry);
7951
7952                 /* Intel hw has only one MUX where enocoders could be cloned. */
7953                 if (encoder->cloneable && source_encoder->cloneable)
7954                         index_mask |= (1 << entry);
7955
7956                 entry++;
7957         }
7958
7959         return index_mask;
7960 }
7961
7962 static bool has_edp_a(struct drm_device *dev)
7963 {
7964         struct drm_i915_private *dev_priv = dev->dev_private;
7965
7966         if (!IS_MOBILE(dev))
7967                 return false;
7968
7969         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7970                 return false;
7971
7972         if (IS_GEN5(dev) &&
7973             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7974                 return false;
7975
7976         return true;
7977 }
7978
7979 static void intel_setup_outputs(struct drm_device *dev)
7980 {
7981         struct drm_i915_private *dev_priv = dev->dev_private;
7982         struct intel_encoder *encoder;
7983         bool dpd_is_edp = false;
7984         bool has_lvds;
7985
7986         has_lvds = intel_lvds_init(dev);
7987         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7988                 /* disable the panel fitter on everything but LVDS */
7989                 I915_WRITE(PFIT_CONTROL, 0);
7990         }
7991
7992         if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
7993                 intel_crt_init(dev);
7994
7995         if (HAS_DDI(dev)) {
7996                 int found;
7997
7998                 /* Haswell uses DDI functions to detect digital outputs */
7999                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8000                 /* DDI A only supports eDP */
8001                 if (found)
8002                         intel_ddi_init(dev, PORT_A);
8003
8004                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8005                  * register */
8006                 found = I915_READ(SFUSE_STRAP);
8007
8008                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8009                         intel_ddi_init(dev, PORT_B);
8010                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8011                         intel_ddi_init(dev, PORT_C);
8012                 if (found & SFUSE_STRAP_DDID_DETECTED)
8013                         intel_ddi_init(dev, PORT_D);
8014         } else if (HAS_PCH_SPLIT(dev)) {
8015                 int found;
8016                 dpd_is_edp = intel_dpd_is_edp(dev);
8017
8018                 if (has_edp_a(dev))
8019                         intel_dp_init(dev, DP_A, PORT_A);
8020
8021                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8022                         /* PCH SDVOB multiplex with HDMIB */
8023                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8024                         if (!found)
8025                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8026                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8027                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8028                 }
8029
8030                 if (I915_READ(HDMIC) & PORT_DETECTED)
8031                         intel_hdmi_init(dev, HDMIC, PORT_C);
8032
8033                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8034                         intel_hdmi_init(dev, HDMID, PORT_D);
8035
8036                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8037                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8038
8039                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8040                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8041         } else if (IS_VALLEYVIEW(dev)) {
8042                 int found;
8043
8044                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8045                 if (I915_READ(DP_C) & DP_DETECTED)
8046                         intel_dp_init(dev, DP_C, PORT_C);
8047
8048                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8049                         /* SDVOB multiplex with HDMIB */
8050                         found = intel_sdvo_init(dev, SDVOB, true);
8051                         if (!found)
8052                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8053                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8054                                 intel_dp_init(dev, DP_B, PORT_B);
8055                 }
8056
8057                 if (I915_READ(SDVOC) & PORT_DETECTED)
8058                         intel_hdmi_init(dev, SDVOC, PORT_C);
8059
8060         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8061                 bool found = false;
8062
8063                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8064                         DRM_DEBUG_KMS("probing SDVOB\n");
8065                         found = intel_sdvo_init(dev, SDVOB, true);
8066                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8067                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8068                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8069                         }
8070
8071                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8072                                 DRM_DEBUG_KMS("probing DP_B\n");
8073                                 intel_dp_init(dev, DP_B, PORT_B);
8074                         }
8075                 }
8076
8077                 /* Before G4X SDVOC doesn't have its own detect register */
8078
8079                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8080                         DRM_DEBUG_KMS("probing SDVOC\n");
8081                         found = intel_sdvo_init(dev, SDVOC, false);
8082                 }
8083
8084                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8085
8086                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8087                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8088                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8089                         }
8090                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8091                                 DRM_DEBUG_KMS("probing DP_C\n");
8092                                 intel_dp_init(dev, DP_C, PORT_C);
8093                         }
8094                 }
8095
8096                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8097                     (I915_READ(DP_D) & DP_DETECTED)) {
8098                         DRM_DEBUG_KMS("probing DP_D\n");
8099                         intel_dp_init(dev, DP_D, PORT_D);
8100                 }
8101         } else if (IS_GEN2(dev))
8102                 intel_dvo_init(dev);
8103
8104         if (SUPPORTS_TV(dev))
8105                 intel_tv_init(dev);
8106
8107         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8108                 encoder->base.possible_crtcs = encoder->crtc_mask;
8109                 encoder->base.possible_clones =
8110                         intel_encoder_clones(encoder);
8111         }
8112
8113         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8114                 ironlake_init_pch_refclk(dev);
8115
8116         drm_helper_move_panel_connectors_to_head(dev);
8117 }
8118
8119 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8120 {
8121         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8122
8123         drm_framebuffer_cleanup(fb);
8124         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8125
8126         kfree(intel_fb);
8127 }
8128
8129 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8130                                                 struct drm_file *file,
8131                                                 unsigned int *handle)
8132 {
8133         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8134         struct drm_i915_gem_object *obj = intel_fb->obj;
8135
8136         return drm_gem_handle_create(file, &obj->base, handle);
8137 }
8138
8139 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8140         .destroy = intel_user_framebuffer_destroy,
8141         .create_handle = intel_user_framebuffer_create_handle,
8142 };
8143
8144 int intel_framebuffer_init(struct drm_device *dev,
8145                            struct intel_framebuffer *intel_fb,
8146                            struct drm_mode_fb_cmd2 *mode_cmd,
8147                            struct drm_i915_gem_object *obj)
8148 {
8149         int ret;
8150
8151         if (obj->tiling_mode == I915_TILING_Y)
8152                 return -EINVAL;
8153
8154         if (mode_cmd->pitches[0] & 63)
8155                 return -EINVAL;
8156
8157         /* FIXME <= Gen4 stride limits are bit unclear */
8158         if (mode_cmd->pitches[0] > 32768)
8159                 return -EINVAL;
8160
8161         if (obj->tiling_mode != I915_TILING_NONE &&
8162             mode_cmd->pitches[0] != obj->stride)
8163                 return -EINVAL;
8164
8165         /* Reject formats not supported by any plane early. */
8166         switch (mode_cmd->pixel_format) {
8167         case DRM_FORMAT_C8:
8168         case DRM_FORMAT_RGB565:
8169         case DRM_FORMAT_XRGB8888:
8170         case DRM_FORMAT_ARGB8888:
8171                 break;
8172         case DRM_FORMAT_XRGB1555:
8173         case DRM_FORMAT_ARGB1555:
8174                 if (INTEL_INFO(dev)->gen > 3)
8175                         return -EINVAL;
8176                 break;
8177         case DRM_FORMAT_XBGR8888:
8178         case DRM_FORMAT_ABGR8888:
8179         case DRM_FORMAT_XRGB2101010:
8180         case DRM_FORMAT_ARGB2101010:
8181         case DRM_FORMAT_XBGR2101010:
8182         case DRM_FORMAT_ABGR2101010:
8183                 if (INTEL_INFO(dev)->gen < 4)
8184                         return -EINVAL;
8185                 break;
8186         case DRM_FORMAT_YUYV:
8187         case DRM_FORMAT_UYVY:
8188         case DRM_FORMAT_YVYU:
8189         case DRM_FORMAT_VYUY:
8190                 if (INTEL_INFO(dev)->gen < 6)
8191                         return -EINVAL;
8192                 break;
8193         default:
8194                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8195                 return -EINVAL;
8196         }
8197
8198         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8199         if (mode_cmd->offsets[0] != 0)
8200                 return -EINVAL;
8201
8202         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8203         if (ret) {
8204                 DRM_ERROR("framebuffer init failed %d\n", ret);
8205                 return ret;
8206         }
8207
8208         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8209         intel_fb->obj = obj;
8210         return 0;
8211 }
8212
8213 static struct drm_framebuffer *
8214 intel_user_framebuffer_create(struct drm_device *dev,
8215                               struct drm_file *filp,
8216                               struct drm_mode_fb_cmd2 *mode_cmd)
8217 {
8218         struct drm_i915_gem_object *obj;
8219
8220         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8221                                                 mode_cmd->handles[0]));
8222         if (&obj->base == NULL)
8223                 return ERR_PTR(-ENOENT);
8224
8225         return intel_framebuffer_create(dev, mode_cmd, obj);
8226 }
8227
8228 static const struct drm_mode_config_funcs intel_mode_funcs = {
8229         .fb_create = intel_user_framebuffer_create,
8230         .output_poll_changed = intel_fb_output_poll_changed,
8231 };
8232
8233 /* Set up chip specific display functions */
8234 static void intel_init_display(struct drm_device *dev)
8235 {
8236         struct drm_i915_private *dev_priv = dev->dev_private;
8237
8238         /* We always want a DPMS function */
8239         if (HAS_DDI(dev)) {
8240                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8241                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8242                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8243                 dev_priv->display.off = haswell_crtc_off;
8244                 dev_priv->display.update_plane = ironlake_update_plane;
8245         } else if (HAS_PCH_SPLIT(dev)) {
8246                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8247                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8248                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8249                 dev_priv->display.off = ironlake_crtc_off;
8250                 dev_priv->display.update_plane = ironlake_update_plane;
8251         } else {
8252                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8253                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8254                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8255                 dev_priv->display.off = i9xx_crtc_off;
8256                 dev_priv->display.update_plane = i9xx_update_plane;
8257         }
8258
8259         /* Returns the core display clock speed */
8260         if (IS_VALLEYVIEW(dev))
8261                 dev_priv->display.get_display_clock_speed =
8262                         valleyview_get_display_clock_speed;
8263         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8264                 dev_priv->display.get_display_clock_speed =
8265                         i945_get_display_clock_speed;
8266         else if (IS_I915G(dev))
8267                 dev_priv->display.get_display_clock_speed =
8268                         i915_get_display_clock_speed;
8269         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8270                 dev_priv->display.get_display_clock_speed =
8271                         i9xx_misc_get_display_clock_speed;
8272         else if (IS_I915GM(dev))
8273                 dev_priv->display.get_display_clock_speed =
8274                         i915gm_get_display_clock_speed;
8275         else if (IS_I865G(dev))
8276                 dev_priv->display.get_display_clock_speed =
8277                         i865_get_display_clock_speed;
8278         else if (IS_I85X(dev))
8279                 dev_priv->display.get_display_clock_speed =
8280                         i855_get_display_clock_speed;
8281         else /* 852, 830 */
8282                 dev_priv->display.get_display_clock_speed =
8283                         i830_get_display_clock_speed;
8284
8285         if (HAS_PCH_SPLIT(dev)) {
8286                 if (IS_GEN5(dev)) {
8287                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8288                         dev_priv->display.write_eld = ironlake_write_eld;
8289                 } else if (IS_GEN6(dev)) {
8290                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8291                         dev_priv->display.write_eld = ironlake_write_eld;
8292                 } else if (IS_IVYBRIDGE(dev)) {
8293                         /* FIXME: detect B0+ stepping and use auto training */
8294                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8295                         dev_priv->display.write_eld = ironlake_write_eld;
8296                         dev_priv->display.modeset_global_resources =
8297                                 ivb_modeset_global_resources;
8298                 } else if (IS_HASWELL(dev)) {
8299                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8300                         dev_priv->display.write_eld = haswell_write_eld;
8301                 } else
8302                         dev_priv->display.update_wm = NULL;
8303         } else if (IS_G4X(dev)) {
8304                 dev_priv->display.write_eld = g4x_write_eld;
8305         }
8306
8307         /* Default just returns -ENODEV to indicate unsupported */
8308         dev_priv->display.queue_flip = intel_default_queue_flip;
8309
8310         switch (INTEL_INFO(dev)->gen) {
8311         case 2:
8312                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8313                 break;
8314
8315         case 3:
8316                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8317                 break;
8318
8319         case 4:
8320         case 5:
8321                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8322                 break;
8323
8324         case 6:
8325                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8326                 break;
8327         case 7:
8328                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8329                 break;
8330         }
8331 }
8332
8333 /*
8334  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8335  * resume, or other times.  This quirk makes sure that's the case for
8336  * affected systems.
8337  */
8338 static void quirk_pipea_force(struct drm_device *dev)
8339 {
8340         struct drm_i915_private *dev_priv = dev->dev_private;
8341
8342         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8343         DRM_INFO("applying pipe a force quirk\n");
8344 }
8345
8346 /*
8347  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8348  */
8349 static void quirk_ssc_force_disable(struct drm_device *dev)
8350 {
8351         struct drm_i915_private *dev_priv = dev->dev_private;
8352         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8353         DRM_INFO("applying lvds SSC disable quirk\n");
8354 }
8355
8356 /*
8357  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8358  * brightness value
8359  */
8360 static void quirk_invert_brightness(struct drm_device *dev)
8361 {
8362         struct drm_i915_private *dev_priv = dev->dev_private;
8363         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8364         DRM_INFO("applying inverted panel brightness quirk\n");
8365 }
8366
8367 struct intel_quirk {
8368         int device;
8369         int subsystem_vendor;
8370         int subsystem_device;
8371         void (*hook)(struct drm_device *dev);
8372 };
8373
8374 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8375 struct intel_dmi_quirk {
8376         void (*hook)(struct drm_device *dev);
8377         const struct dmi_system_id (*dmi_id_list)[];
8378 };
8379
8380 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8381 {
8382         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8383         return 1;
8384 }
8385
8386 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8387         {
8388                 .dmi_id_list = &(const struct dmi_system_id[]) {
8389                         {
8390                                 .callback = intel_dmi_reverse_brightness,
8391                                 .ident = "NCR Corporation",
8392                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8393                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8394                                 },
8395                         },
8396                         { }  /* terminating entry */
8397                 },
8398                 .hook = quirk_invert_brightness,
8399         },
8400 };
8401
8402 static struct intel_quirk intel_quirks[] = {
8403         /* HP Mini needs pipe A force quirk (LP: #322104) */
8404         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8405
8406         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8407         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8408
8409         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8410         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8411
8412         /* 830/845 need to leave pipe A & dpll A up */
8413         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8414         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8415
8416         /* Lenovo U160 cannot use SSC on LVDS */
8417         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8418
8419         /* Sony Vaio Y cannot use SSC on LVDS */
8420         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8421
8422         /* Acer Aspire 5734Z must invert backlight brightness */
8423         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8424 };
8425
8426 static void intel_init_quirks(struct drm_device *dev)
8427 {
8428         struct pci_dev *d = dev->pdev;
8429         int i;
8430
8431         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8432                 struct intel_quirk *q = &intel_quirks[i];
8433
8434                 if (d->device == q->device &&
8435                     (d->subsystem_vendor == q->subsystem_vendor ||
8436                      q->subsystem_vendor == PCI_ANY_ID) &&
8437                     (d->subsystem_device == q->subsystem_device ||
8438                      q->subsystem_device == PCI_ANY_ID))
8439                         q->hook(dev);
8440         }
8441         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8442                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8443                         intel_dmi_quirks[i].hook(dev);
8444         }
8445 }
8446
8447 /* Disable the VGA plane that we never use */
8448 static void i915_disable_vga(struct drm_device *dev)
8449 {
8450         struct drm_i915_private *dev_priv = dev->dev_private;
8451         u8 sr1;
8452         u32 vga_reg;
8453
8454         if (HAS_PCH_SPLIT(dev))
8455                 vga_reg = CPU_VGACNTRL;
8456         else
8457                 vga_reg = VGACNTRL;
8458
8459         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8460         outb(SR01, VGA_SR_INDEX);
8461         sr1 = inb(VGA_SR_DATA);
8462         outb(sr1 | 1<<5, VGA_SR_DATA);
8463         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8464         udelay(300);
8465
8466         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8467         POSTING_READ(vga_reg);
8468 }
8469
8470 void intel_modeset_init_hw(struct drm_device *dev)
8471 {
8472         /* We attempt to init the necessary power wells early in the initialization
8473          * time, so the subsystems that expect power to be enabled can work.
8474          */
8475         intel_init_power_wells(dev);
8476
8477         intel_prepare_ddi(dev);
8478
8479         intel_init_clock_gating(dev);
8480
8481         mutex_lock(&dev->struct_mutex);
8482         intel_enable_gt_powersave(dev);
8483         mutex_unlock(&dev->struct_mutex);
8484 }
8485
8486 void intel_modeset_init(struct drm_device *dev)
8487 {
8488         struct drm_i915_private *dev_priv = dev->dev_private;
8489         int i, ret;
8490
8491         drm_mode_config_init(dev);
8492
8493         dev->mode_config.min_width = 0;
8494         dev->mode_config.min_height = 0;
8495
8496         dev->mode_config.preferred_depth = 24;
8497         dev->mode_config.prefer_shadow = 1;
8498
8499         dev->mode_config.funcs = &intel_mode_funcs;
8500
8501         intel_init_quirks(dev);
8502
8503         intel_init_pm(dev);
8504
8505         intel_init_display(dev);
8506
8507         if (IS_GEN2(dev)) {
8508                 dev->mode_config.max_width = 2048;
8509                 dev->mode_config.max_height = 2048;
8510         } else if (IS_GEN3(dev)) {
8511                 dev->mode_config.max_width = 4096;
8512                 dev->mode_config.max_height = 4096;
8513         } else {
8514                 dev->mode_config.max_width = 8192;
8515                 dev->mode_config.max_height = 8192;
8516         }
8517         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8518
8519         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8520                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8521
8522         for (i = 0; i < dev_priv->num_pipe; i++) {
8523                 intel_crtc_init(dev, i);
8524                 ret = intel_plane_init(dev, i);
8525                 if (ret)
8526                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8527         }
8528
8529         intel_cpu_pll_init(dev);
8530         intel_pch_pll_init(dev);
8531
8532         /* Just disable it once at startup */
8533         i915_disable_vga(dev);
8534         intel_setup_outputs(dev);
8535
8536         /* Just in case the BIOS is doing something questionable. */
8537         intel_disable_fbc(dev);
8538 }
8539
8540 static void
8541 intel_connector_break_all_links(struct intel_connector *connector)
8542 {
8543         connector->base.dpms = DRM_MODE_DPMS_OFF;
8544         connector->base.encoder = NULL;
8545         connector->encoder->connectors_active = false;
8546         connector->encoder->base.crtc = NULL;
8547 }
8548
8549 static void intel_enable_pipe_a(struct drm_device *dev)
8550 {
8551         struct intel_connector *connector;
8552         struct drm_connector *crt = NULL;
8553         struct intel_load_detect_pipe load_detect_temp;
8554
8555         /* We can't just switch on the pipe A, we need to set things up with a
8556          * proper mode and output configuration. As a gross hack, enable pipe A
8557          * by enabling the load detect pipe once. */
8558         list_for_each_entry(connector,
8559                             &dev->mode_config.connector_list,
8560                             base.head) {
8561                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8562                         crt = &connector->base;
8563                         break;
8564                 }
8565         }
8566
8567         if (!crt)
8568                 return;
8569
8570         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8571                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8572
8573
8574 }
8575
8576 static bool
8577 intel_check_plane_mapping(struct intel_crtc *crtc)
8578 {
8579         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8580         u32 reg, val;
8581
8582         if (dev_priv->num_pipe == 1)
8583                 return true;
8584
8585         reg = DSPCNTR(!crtc->plane);
8586         val = I915_READ(reg);
8587
8588         if ((val & DISPLAY_PLANE_ENABLE) &&
8589             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8590                 return false;
8591
8592         return true;
8593 }
8594
8595 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8596 {
8597         struct drm_device *dev = crtc->base.dev;
8598         struct drm_i915_private *dev_priv = dev->dev_private;
8599         u32 reg;
8600
8601         /* Clear any frame start delays used for debugging left by the BIOS */
8602         reg = PIPECONF(crtc->cpu_transcoder);
8603         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8604
8605         /* We need to sanitize the plane -> pipe mapping first because this will
8606          * disable the crtc (and hence change the state) if it is wrong. Note
8607          * that gen4+ has a fixed plane -> pipe mapping.  */
8608         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8609                 struct intel_connector *connector;
8610                 bool plane;
8611
8612                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8613                               crtc->base.base.id);
8614
8615                 /* Pipe has the wrong plane attached and the plane is active.
8616                  * Temporarily change the plane mapping and disable everything
8617                  * ...  */
8618                 plane = crtc->plane;
8619                 crtc->plane = !plane;
8620                 dev_priv->display.crtc_disable(&crtc->base);
8621                 crtc->plane = plane;
8622
8623                 /* ... and break all links. */
8624                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8625                                     base.head) {
8626                         if (connector->encoder->base.crtc != &crtc->base)
8627                                 continue;
8628
8629                         intel_connector_break_all_links(connector);
8630                 }
8631
8632                 WARN_ON(crtc->active);
8633                 crtc->base.enabled = false;
8634         }
8635
8636         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8637             crtc->pipe == PIPE_A && !crtc->active) {
8638                 /* BIOS forgot to enable pipe A, this mostly happens after
8639                  * resume. Force-enable the pipe to fix this, the update_dpms
8640                  * call below we restore the pipe to the right state, but leave
8641                  * the required bits on. */
8642                 intel_enable_pipe_a(dev);
8643         }
8644
8645         /* Adjust the state of the output pipe according to whether we
8646          * have active connectors/encoders. */
8647         intel_crtc_update_dpms(&crtc->base);
8648
8649         if (crtc->active != crtc->base.enabled) {
8650                 struct intel_encoder *encoder;
8651
8652                 /* This can happen either due to bugs in the get_hw_state
8653                  * functions or because the pipe is force-enabled due to the
8654                  * pipe A quirk. */
8655                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8656                               crtc->base.base.id,
8657                               crtc->base.enabled ? "enabled" : "disabled",
8658                               crtc->active ? "enabled" : "disabled");
8659
8660                 crtc->base.enabled = crtc->active;
8661
8662                 /* Because we only establish the connector -> encoder ->
8663                  * crtc links if something is active, this means the
8664                  * crtc is now deactivated. Break the links. connector
8665                  * -> encoder links are only establish when things are
8666                  *  actually up, hence no need to break them. */
8667                 WARN_ON(crtc->active);
8668
8669                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8670                         WARN_ON(encoder->connectors_active);
8671                         encoder->base.crtc = NULL;
8672                 }
8673         }
8674 }
8675
8676 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8677 {
8678         struct intel_connector *connector;
8679         struct drm_device *dev = encoder->base.dev;
8680
8681         /* We need to check both for a crtc link (meaning that the
8682          * encoder is active and trying to read from a pipe) and the
8683          * pipe itself being active. */
8684         bool has_active_crtc = encoder->base.crtc &&
8685                 to_intel_crtc(encoder->base.crtc)->active;
8686
8687         if (encoder->connectors_active && !has_active_crtc) {
8688                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8689                               encoder->base.base.id,
8690                               drm_get_encoder_name(&encoder->base));
8691
8692                 /* Connector is active, but has no active pipe. This is
8693                  * fallout from our resume register restoring. Disable
8694                  * the encoder manually again. */
8695                 if (encoder->base.crtc) {
8696                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8697                                       encoder->base.base.id,
8698                                       drm_get_encoder_name(&encoder->base));
8699                         encoder->disable(encoder);
8700                 }
8701
8702                 /* Inconsistent output/port/pipe state happens presumably due to
8703                  * a bug in one of the get_hw_state functions. Or someplace else
8704                  * in our code, like the register restore mess on resume. Clamp
8705                  * things to off as a safer default. */
8706                 list_for_each_entry(connector,
8707                                     &dev->mode_config.connector_list,
8708                                     base.head) {
8709                         if (connector->encoder != encoder)
8710                                 continue;
8711
8712                         intel_connector_break_all_links(connector);
8713                 }
8714         }
8715         /* Enabled encoders without active connectors will be fixed in
8716          * the crtc fixup. */
8717 }
8718
8719 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8720  * and i915 state tracking structures. */
8721 void intel_modeset_setup_hw_state(struct drm_device *dev,
8722                                   bool force_restore)
8723 {
8724         struct drm_i915_private *dev_priv = dev->dev_private;
8725         enum pipe pipe;
8726         u32 tmp;
8727         struct intel_crtc *crtc;
8728         struct intel_encoder *encoder;
8729         struct intel_connector *connector;
8730
8731         if (HAS_DDI(dev)) {
8732                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8733
8734                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8735                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8736                         case TRANS_DDI_EDP_INPUT_A_ON:
8737                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8738                                 pipe = PIPE_A;
8739                                 break;
8740                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8741                                 pipe = PIPE_B;
8742                                 break;
8743                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8744                                 pipe = PIPE_C;
8745                                 break;
8746                         }
8747
8748                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8749                         crtc->cpu_transcoder = TRANSCODER_EDP;
8750
8751                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8752                                       pipe_name(pipe));
8753                 }
8754         }
8755
8756         for_each_pipe(pipe) {
8757                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8758
8759                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8760                 if (tmp & PIPECONF_ENABLE)
8761                         crtc->active = true;
8762                 else
8763                         crtc->active = false;
8764
8765                 crtc->base.enabled = crtc->active;
8766
8767                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8768                               crtc->base.base.id,
8769                               crtc->active ? "enabled" : "disabled");
8770         }
8771
8772         if (HAS_DDI(dev))
8773                 intel_ddi_setup_hw_pll_state(dev);
8774
8775         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8776                             base.head) {
8777                 pipe = 0;
8778
8779                 if (encoder->get_hw_state(encoder, &pipe)) {
8780                         encoder->base.crtc =
8781                                 dev_priv->pipe_to_crtc_mapping[pipe];
8782                 } else {
8783                         encoder->base.crtc = NULL;
8784                 }
8785
8786                 encoder->connectors_active = false;
8787                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8788                               encoder->base.base.id,
8789                               drm_get_encoder_name(&encoder->base),
8790                               encoder->base.crtc ? "enabled" : "disabled",
8791                               pipe);
8792         }
8793
8794         list_for_each_entry(connector, &dev->mode_config.connector_list,
8795                             base.head) {
8796                 if (connector->get_hw_state(connector)) {
8797                         connector->base.dpms = DRM_MODE_DPMS_ON;
8798                         connector->encoder->connectors_active = true;
8799                         connector->base.encoder = &connector->encoder->base;
8800                 } else {
8801                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8802                         connector->base.encoder = NULL;
8803                 }
8804                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8805                               connector->base.base.id,
8806                               drm_get_connector_name(&connector->base),
8807                               connector->base.encoder ? "enabled" : "disabled");
8808         }
8809
8810         /* HW state is read out, now we need to sanitize this mess. */
8811         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8812                             base.head) {
8813                 intel_sanitize_encoder(encoder);
8814         }
8815
8816         for_each_pipe(pipe) {
8817                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8818                 intel_sanitize_crtc(crtc);
8819         }
8820
8821         if (force_restore) {
8822                 for_each_pipe(pipe) {
8823                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8824                         intel_set_mode(&crtc->base, &crtc->base.mode,
8825                                        crtc->base.x, crtc->base.y, crtc->base.fb);
8826                 }
8827         } else {
8828                 intel_modeset_update_staged_output_state(dev);
8829         }
8830
8831         intel_modeset_check_state(dev);
8832
8833         drm_mode_config_reset(dev);
8834 }
8835
8836 void intel_modeset_gem_init(struct drm_device *dev)
8837 {
8838         intel_modeset_init_hw(dev);
8839
8840         intel_setup_overlay(dev);
8841
8842         intel_modeset_setup_hw_state(dev, false);
8843 }
8844
8845 void intel_modeset_cleanup(struct drm_device *dev)
8846 {
8847         struct drm_i915_private *dev_priv = dev->dev_private;
8848         struct drm_crtc *crtc;
8849         struct intel_crtc *intel_crtc;
8850
8851         drm_kms_helper_poll_fini(dev);
8852         mutex_lock(&dev->struct_mutex);
8853
8854         intel_unregister_dsm_handler();
8855
8856
8857         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8858                 /* Skip inactive CRTCs */
8859                 if (!crtc->fb)
8860                         continue;
8861
8862                 intel_crtc = to_intel_crtc(crtc);
8863                 intel_increase_pllclock(crtc);
8864         }
8865
8866         intel_disable_fbc(dev);
8867
8868         intel_disable_gt_powersave(dev);
8869
8870         ironlake_teardown_rc6(dev);
8871
8872         if (IS_VALLEYVIEW(dev))
8873                 vlv_init_dpio(dev);
8874
8875         mutex_unlock(&dev->struct_mutex);
8876
8877         /* Disable the irq before mode object teardown, for the irq might
8878          * enqueue unpin/hotplug work. */
8879         drm_irq_uninstall(dev);
8880         cancel_work_sync(&dev_priv->hotplug_work);
8881         cancel_work_sync(&dev_priv->rps.work);
8882
8883         /* flush any delayed tasks or pending work */
8884         flush_scheduled_work();
8885
8886         drm_mode_config_cleanup(dev);
8887 }
8888
8889 /*
8890  * Return which encoder is currently attached for connector.
8891  */
8892 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8893 {
8894         return &intel_attached_encoder(connector)->base;
8895 }
8896
8897 void intel_connector_attach_encoder(struct intel_connector *connector,
8898                                     struct intel_encoder *encoder)
8899 {
8900         connector->encoder = encoder;
8901         drm_mode_connector_attach_encoder(&connector->base,
8902                                           &encoder->base);
8903 }
8904
8905 /*
8906  * set vga decode state - true == enable VGA decode
8907  */
8908 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8909 {
8910         struct drm_i915_private *dev_priv = dev->dev_private;
8911         u16 gmch_ctrl;
8912
8913         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8914         if (state)
8915                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8916         else
8917                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8918         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8919         return 0;
8920 }
8921
8922 #ifdef CONFIG_DEBUG_FS
8923 #include <linux/seq_file.h>
8924
8925 struct intel_display_error_state {
8926         struct intel_cursor_error_state {
8927                 u32 control;
8928                 u32 position;
8929                 u32 base;
8930                 u32 size;
8931         } cursor[I915_MAX_PIPES];
8932
8933         struct intel_pipe_error_state {
8934                 u32 conf;
8935                 u32 source;
8936
8937                 u32 htotal;
8938                 u32 hblank;
8939                 u32 hsync;
8940                 u32 vtotal;
8941                 u32 vblank;
8942                 u32 vsync;
8943         } pipe[I915_MAX_PIPES];
8944
8945         struct intel_plane_error_state {
8946                 u32 control;
8947                 u32 stride;
8948                 u32 size;
8949                 u32 pos;
8950                 u32 addr;
8951                 u32 surface;
8952                 u32 tile_offset;
8953         } plane[I915_MAX_PIPES];
8954 };
8955
8956 struct intel_display_error_state *
8957 intel_display_capture_error_state(struct drm_device *dev)
8958 {
8959         drm_i915_private_t *dev_priv = dev->dev_private;
8960         struct intel_display_error_state *error;
8961         enum transcoder cpu_transcoder;
8962         int i;
8963
8964         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8965         if (error == NULL)
8966                 return NULL;
8967
8968         for_each_pipe(i) {
8969                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
8970
8971                 error->cursor[i].control = I915_READ(CURCNTR(i));
8972                 error->cursor[i].position = I915_READ(CURPOS(i));
8973                 error->cursor[i].base = I915_READ(CURBASE(i));
8974
8975                 error->plane[i].control = I915_READ(DSPCNTR(i));
8976                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8977                 error->plane[i].size = I915_READ(DSPSIZE(i));
8978                 error->plane[i].pos = I915_READ(DSPPOS(i));
8979                 error->plane[i].addr = I915_READ(DSPADDR(i));
8980                 if (INTEL_INFO(dev)->gen >= 4) {
8981                         error->plane[i].surface = I915_READ(DSPSURF(i));
8982                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8983                 }
8984
8985                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
8986                 error->pipe[i].source = I915_READ(PIPESRC(i));
8987                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
8988                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
8989                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
8990                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
8991                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
8992                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
8993         }
8994
8995         return error;
8996 }
8997
8998 void
8999 intel_display_print_error_state(struct seq_file *m,
9000                                 struct drm_device *dev,
9001                                 struct intel_display_error_state *error)
9002 {
9003         drm_i915_private_t *dev_priv = dev->dev_private;
9004         int i;
9005
9006         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9007         for_each_pipe(i) {
9008                 seq_printf(m, "Pipe [%d]:\n", i);
9009                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9010                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9011                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9012                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9013                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9014                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9015                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9016                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9017
9018                 seq_printf(m, "Plane [%d]:\n", i);
9019                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9020                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9021                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9022                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9023                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9024                 if (INTEL_INFO(dev)->gen >= 4) {
9025                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9026                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9027                 }
9028
9029                 seq_printf(m, "Cursor [%d]:\n", i);
9030                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9031                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9032                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9033         }
9034 }
9035 #endif