drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 908000, .max = 1512000 },
  94         .n = { .min = 2, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 908000, .max = 1512000 },
 107         .n = { .min = 2, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 908000, .max = 1512000 },
 120         .n = { .min = 2, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         if (WARN_ON(clock->n == 0 || clock->p == 0))
 333                 return;
 334         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 335         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 336 }
 337
 338 /**
 339  * Returns whether any output on the specified pipe is of the specified type
 340  */
 341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 342 {
 343         struct drm_device *dev = crtc->dev;
 344         struct intel_encoder *encoder;
 345
 346         for_each_encoder_on_crtc(dev, crtc, encoder)
 347                 if (encoder->type == type)
 348                         return true;
 349
 350         return false;
 351 }
 352
 353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 354                                                 int refclk)
 355 {
 356         struct drm_device *dev = crtc->dev;
 357         const intel_limit_t *limit;
 358
 359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 360                 if (intel_is_dual_link_lvds(dev)) {
 361                         if (refclk == 100000)
 362                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 363                         else
 364                                 limit = &intel_limits_ironlake_dual_lvds;
 365                 } else {
 366                         if (refclk == 100000)
 367                                 limit = &intel_limits_ironlake_single_lvds_100m;
 368                         else
 369                                 limit = &intel_limits_ironlake_single_lvds;
 370                 }
 371         } else
 372                 limit = &intel_limits_ironlake_dac;
 373
 374         return limit;
 375 }
 376
 377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 378 {
 379         struct drm_device *dev = crtc->dev;
 380         const intel_limit_t *limit;
 381
 382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 383                 if (intel_is_dual_link_lvds(dev))
 384                         limit = &intel_limits_g4x_dual_channel_lvds;
 385                 else
 386                         limit = &intel_limits_g4x_single_channel_lvds;
 387         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 388                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 389                 limit = &intel_limits_g4x_hdmi;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 391                 limit = &intel_limits_g4x_sdvo;
 392         } else /* The option is for other outputs */
 393                 limit = &intel_limits_i9xx_sdvo;
 394
 395         return limit;
 396 }
 397
 398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 399 {
 400         struct drm_device *dev = crtc->dev;
 401         const intel_limit_t *limit;
 402
 403         if (HAS_PCH_SPLIT(dev))
 404                 limit = intel_ironlake_limit(crtc, refclk);
 405         else if (IS_G4X(dev)) {
 406                 limit = intel_g4x_limit(crtc);
 407         } else if (IS_PINEVIEW(dev)) {
 408                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 409                         limit = &intel_limits_pineview_lvds;
 410                 else
 411                         limit = &intel_limits_pineview_sdvo;
 412         } else if (IS_VALLEYVIEW(dev)) {
 413                 limit = &intel_limits_vlv;
 414         } else if (!IS_GEN2(dev)) {
 415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 416                         limit = &intel_limits_i9xx_lvds;
 417                 else
 418                         limit = &intel_limits_i9xx_sdvo;
 419         } else {
 420                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 421                         limit = &intel_limits_i8xx_lvds;
 422                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 423                         limit = &intel_limits_i8xx_dvo;
 424                 else
 425                         limit = &intel_limits_i8xx_dac;
 426         }
 427         return limit;
 428 }
 429
 430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 431 static void pineview_clock(int refclk, intel_clock_t *clock)
 432 {
 433         clock->m = clock->m2 + 2;
 434         clock->p = clock->p1 * clock->p2;
 435         if (WARN_ON(clock->n == 0 || clock->p == 0))
 436                 return;
 437         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 438         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 439 }
 440
 441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 442 {
 443         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 444 }
 445
 446 static void i9xx_clock(int refclk, intel_clock_t *clock)
 447 {
 448         clock->m = i9xx_dpll_compute_m(clock);
 449         clock->p = clock->p1 * clock->p2;
 450         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 451                 return;
 452         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 453         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 467                 INTELPllInvalid("n out of range\n");
 468         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 469                 INTELPllInvalid("p1 out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474
 475         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 476                 if (clock->m1 <= clock->m2)
 477                         INTELPllInvalid("m1 <= m2\n");
 478
 479         if (!IS_VALLEYVIEW(dev)) {
 480                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 481                         INTELPllInvalid("p out of range\n");
 482                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 483                         INTELPllInvalid("m out of range\n");
 484         }
 485
 486         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 487                 INTELPllInvalid("vco out of range\n");
 488         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 489          * connector, etc., rather than just a single range.
 490          */
 491         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 492                 INTELPllInvalid("dot out of range\n");
 493
 494         return true;
 495 }
 496
 497 static bool
 498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 499                     int target, int refclk, intel_clock_t *match_clock,
 500                     intel_clock_t *best_clock)
 501 {
 502         struct drm_device *dev = crtc->dev;
 503         intel_clock_t clock;
 504         int err = target;
 505
 506         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 507                 /*
 508                  * For LVDS just rely on its current settings for dual-channel.
 509                  * We haven't figured out how to reliably set up different
 510                  * single/dual channel state, if we even can.
 511                  */
 512                 if (intel_is_dual_link_lvds(dev))
 513                         clock.p2 = limit->p2.p2_fast;
 514                 else
 515                         clock.p2 = limit->p2.p2_slow;
 516         } else {
 517                 if (target < limit->p2.dot_limit)
 518                         clock.p2 = limit->p2.p2_slow;
 519                 else
 520                         clock.p2 = limit->p2.p2_fast;
 521         }
 522
 523         memset(best_clock, 0, sizeof(*best_clock));
 524
 525         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 526              clock.m1++) {
 527                 for (clock.m2 = limit->m2.min;
 528                      clock.m2 <= limit->m2.max; clock.m2++) {
 529                         if (clock.m2 >= clock.m1)
 530                                 break;
 531                         for (clock.n = limit->n.min;
 532                              clock.n <= limit->n.max; clock.n++) {
 533                                 for (clock.p1 = limit->p1.min;
 534                                         clock.p1 <= limit->p1.max; clock.p1++) {
 535                                         int this_err;
 536
 537                                         i9xx_clock(refclk, &clock);
 538                                         if (!intel_PLL_is_valid(dev, limit,
 539                                                                 &clock))
 540                                                 continue;
 541                                         if (match_clock &&
 542                                             clock.p != match_clock->p)
 543                                                 continue;
 544
 545                                         this_err = abs(clock.dot - target);
 546                                         if (this_err < err) {
 547                                                 *best_clock = clock;
 548                                                 err = this_err;
 549                                         }
 550                                 }
 551                         }
 552                 }
 553         }
 554
 555         return (err != target);
 556 }
 557
 558 static bool
 559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 560                    int target, int refclk, intel_clock_t *match_clock,
 561                    intel_clock_t *best_clock)
 562 {
 563         struct drm_device *dev = crtc->dev;
 564         intel_clock_t clock;
 565         int err = target;
 566
 567         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 568                 /*
 569                  * For LVDS just rely on its current settings for dual-channel.
 570                  * We haven't figured out how to reliably set up different
 571                  * single/dual channel state, if we even can.
 572                  */
 573                 if (intel_is_dual_link_lvds(dev))
 574                         clock.p2 = limit->p2.p2_fast;
 575                 else
 576                         clock.p2 = limit->p2.p2_slow;
 577         } else {
 578                 if (target < limit->p2.dot_limit)
 579                         clock.p2 = limit->p2.p2_slow;
 580                 else
 581                         clock.p2 = limit->p2.p2_fast;
 582         }
 583
 584         memset(best_clock, 0, sizeof(*best_clock));
 585
 586         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 587              clock.m1++) {
 588                 for (clock.m2 = limit->m2.min;
 589                      clock.m2 <= limit->m2.max; clock.m2++) {
 590                         for (clock.n = limit->n.min;
 591                              clock.n <= limit->n.max; clock.n++) {
 592                                 for (clock.p1 = limit->p1.min;
 593                                         clock.p1 <= limit->p1.max; clock.p1++) {
 594                                         int this_err;
 595
 596                                         pineview_clock(refclk, &clock);
 597                                         if (!intel_PLL_is_valid(dev, limit,
 598                                                                 &clock))
 599                                                 continue;
 600                                         if (match_clock &&
 601                                             clock.p != match_clock->p)
 602                                                 continue;
 603
 604                                         this_err = abs(clock.dot - target);
 605                                         if (this_err < err) {
 606                                                 *best_clock = clock;
 607                                                 err = this_err;
 608                                         }
 609                                 }
 610                         }
 611                 }
 612         }
 613
 614         return (err != target);
 615 }
 616
 617 static bool
 618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 619                    int target, int refclk, intel_clock_t *match_clock,
 620                    intel_clock_t *best_clock)
 621 {
 622         struct drm_device *dev = crtc->dev;
 623         intel_clock_t clock;
 624         int max_n;
 625         bool found;
 626         /* approximately equals target * 0.00585 */
 627         int err_most = (target >> 8) + (target >> 9);
 628         found = false;
 629
 630         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 631                 if (intel_is_dual_link_lvds(dev))
 632                         clock.p2 = limit->p2.p2_fast;
 633                 else
 634                         clock.p2 = limit->p2.p2_slow;
 635         } else {
 636                 if (target < limit->p2.dot_limit)
 637                         clock.p2 = limit->p2.p2_slow;
 638                 else
 639                         clock.p2 = limit->p2.p2_fast;
 640         }
 641
 642         memset(best_clock, 0, sizeof(*best_clock));
 643         max_n = limit->n.max;
 644         /* based on hardware requirement, prefer smaller n to precision */
 645         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 646                 /* based on hardware requirement, prefere larger m1,m2 */
 647                 for (clock.m1 = limit->m1.max;
 648                      clock.m1 >= limit->m1.min; clock.m1--) {
 649                         for (clock.m2 = limit->m2.max;
 650                              clock.m2 >= limit->m2.min; clock.m2--) {
 651                                 for (clock.p1 = limit->p1.max;
 652                                      clock.p1 >= limit->p1.min; clock.p1--) {
 653                                         int this_err;
 654
 655                                         i9xx_clock(refclk, &clock);
 656                                         if (!intel_PLL_is_valid(dev, limit,
 657                                                                 &clock))
 658                                                 continue;
 659
 660                                         this_err = abs(clock.dot - target);
 661                                         if (this_err < err_most) {
 662                                                 *best_clock = clock;
 663                                                 err_most = this_err;
 664                                                 max_n = clock.n;
 665                                                 found = true;
 666                                         }
 667                                 }
 668                         }
 669                 }
 670         }
 671         return found;
 672 }
 673
 674 static bool
 675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                    int target, int refclk, intel_clock_t *match_clock,
 677                    intel_clock_t *best_clock)
 678 {
 679         struct drm_device *dev = crtc->dev;
 680         intel_clock_t clock;
 681         unsigned int bestppm = 1000000;
 682         /* min update 19.2 MHz */
 683         int max_n = min(limit->n.max, refclk / 19200);
 684         bool found = false;
 685
 686         target *= 5; /* fast clock */
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         /* based on hardware requirement, prefer smaller n to precision */
 691         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 692                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 693                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 694                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 695                                 clock.p = clock.p1 * clock.p2;
 696                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 697                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 698                                         unsigned int ppm, diff;
 699
 700                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 701                                                                      refclk * clock.m1);
 702
 703                                         vlv_clock(refclk, &clock);
 704
 705                                         if (!intel_PLL_is_valid(dev, limit,
 706                                                                 &clock))
 707                                                 continue;
 708
 709                                         diff = abs(clock.dot - target);
 710                                         ppm = div_u64(1000000ULL * diff, target);
 711
 712                                         if (ppm < 100 && clock.p > best_clock->p) {
 713                                                 bestppm = 0;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717
 718                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 719                                                 bestppm = ppm;
 720                                                 *best_clock = clock;
 721                                                 found = true;
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727
 728         return found;
 729 }
 730
 731 bool intel_crtc_active(struct drm_crtc *crtc)
 732 {
 733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 734
 735         /* Be paranoid as we can arrive here with only partial
 736          * state retrieved from the hardware during setup.
 737          *
 738          * We can ditch the adjusted_mode.crtc_clock check as soon
 739          * as Haswell has gained clock readout/fastboot support.
 740          *
 741          * We can ditch the crtc->fb check as soon as we can
 742          * properly reconstruct framebuffers.
 743          */
 744         return intel_crtc->active && crtc->fb &&
 745                 intel_crtc->config.adjusted_mode.crtc_clock;
 746 }
 747
 748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 749                                              enum pipe pipe)
 750 {
 751         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 753
 754         return intel_crtc->config.cpu_transcoder;
 755 }
 756
 757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 761
 762         frame = I915_READ(frame_reg);
 763
 764         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 765                 DRM_DEBUG_KMS("vblank wait timed out\n");
 766 }
 767
 768 /**
 769  * intel_wait_for_vblank - wait for vblank on a given pipe
 770  * @dev: drm device
 771  * @pipe: pipe to wait for
 772  *
 773  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 774  * mode setting code.
 775  */
 776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         int pipestat_reg = PIPESTAT(pipe);
 780
 781         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 782                 g4x_wait_for_vblank(dev, pipe);
 783                 return;
 784         }
 785
 786         /* Clear existing vblank status. Note this will clear any other
 787          * sticky status fields as well.
 788          *
 789          * This races with i915_driver_irq_handler() with the result
 790          * that either function could miss a vblank event.  Here it is not
 791          * fatal, as we will either wait upon the next vblank interrupt or
 792          * timeout.  Generally speaking intel_wait_for_vblank() is only
 793          * called during modeset at which time the GPU should be idle and
 794          * should *not* be performing page flips and thus not waiting on
 795          * vblanks...
 796          * Currently, the result of us stealing a vblank from the irq
 797          * handler is that a single frame will be skipped during swapbuffers.
 798          */
 799         I915_WRITE(pipestat_reg,
 800                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 801
 802         /* Wait for vblank interrupt bit to set */
 803         if (wait_for(I915_READ(pipestat_reg) &
 804                      PIPE_VBLANK_INTERRUPT_STATUS,
 805                      50))
 806                 DRM_DEBUG_KMS("vblank wait timed out\n");
 807 }
 808
 809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         u32 reg = PIPEDSL(pipe);
 813         u32 line1, line2;
 814         u32 line_mask;
 815
 816         if (IS_GEN2(dev))
 817                 line_mask = DSL_LINEMASK_GEN2;
 818         else
 819                 line_mask = DSL_LINEMASK_GEN3;
 820
 821         line1 = I915_READ(reg) & line_mask;
 822         mdelay(5);
 823         line2 = I915_READ(reg) & line_mask;
 824
 825         return line1 == line2;
 826 }
 827
 828 /*
 829  * intel_wait_for_pipe_off - wait for pipe to turn off
 830  * @dev: drm device
 831  * @pipe: pipe to wait for
 832  *
 833  * After disabling a pipe, we can't wait for vblank in the usual way,
 834  * spinning on the vblank interrupt status bit, since we won't actually
 835  * see an interrupt when the pipe is disabled.
 836  *
 837  * On Gen4 and above:
 838  *   wait for the pipe register state bit to turn off
 839  *
 840  * Otherwise:
 841  *   wait for the display line value to settle (it usually
 842  *   ends up stopping at the start of the next frame).
 843  *
 844  */
 845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 846 {
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 849                                                                       pipe);
 850
 851         if (INTEL_INFO(dev)->gen >= 4) {
 852                 int reg = PIPECONF(cpu_transcoder);
 853
 854                 /* Wait for the Pipe State to go off */
 855                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 856                              100))
 857                         WARN(1, "pipe_off wait timed out\n");
 858         } else {
 859                 /* Wait for the display line to settle */
 860                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097         else if (IS_845G(dev) || IS_I865G(dev))
1098                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099         else
1100                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < INTEL_INFO(dev)->num_sprites; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1220
1221         val = I915_READ(PCH_DREF_CONTROL);
1222         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1223                             DREF_SUPERSPREAD_SOURCE_MASK));
1224         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1225 }
1226
1227 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1228                                            enum pipe pipe)
1229 {
1230         int reg;
1231         u32 val;
1232         bool enabled;
1233
1234         reg = PCH_TRANSCONF(pipe);
1235         val = I915_READ(reg);
1236         enabled = !!(val & TRANS_ENABLE);
1237         WARN(enabled,
1238              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1239              pipe_name(pipe));
1240 }
1241
1242 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1243                             enum pipe pipe, u32 port_sel, u32 val)
1244 {
1245         if ((val & DP_PORT_EN) == 0)
1246                 return false;
1247
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1250                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1251                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1252                         return false;
1253         } else {
1254                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1255                         return false;
1256         }
1257         return true;
1258 }
1259
1260 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1261                               enum pipe pipe, u32 val)
1262 {
1263         if ((val & SDVO_ENABLE) == 0)
1264                 return false;
1265
1266         if (HAS_PCH_CPT(dev_priv->dev)) {
1267                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1268                         return false;
1269         } else {
1270                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1271                         return false;
1272         }
1273         return true;
1274 }
1275
1276 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1277                               enum pipe pipe, u32 val)
1278 {
1279         if ((val & LVDS_PORT_EN) == 0)
1280                 return false;
1281
1282         if (HAS_PCH_CPT(dev_priv->dev)) {
1283                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1284                         return false;
1285         } else {
1286                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1287                         return false;
1288         }
1289         return true;
1290 }
1291
1292 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1293                               enum pipe pipe, u32 val)
1294 {
1295         if ((val & ADPA_DAC_ENABLE) == 0)
1296                 return false;
1297         if (HAS_PCH_CPT(dev_priv->dev)) {
1298                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1299                         return false;
1300         } else {
1301                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1302                         return false;
1303         }
1304         return true;
1305 }
1306
1307 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1308                                    enum pipe pipe, int reg, u32 port_sel)
1309 {
1310         u32 val = I915_READ(reg);
1311         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1312              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1313              reg, pipe_name(pipe));
1314
1315         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1316              && (val & DP_PIPEB_SELECT),
1317              "IBX PCH dp port still using transcoder B\n");
1318 }
1319
1320 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1321                                      enum pipe pipe, int reg)
1322 {
1323         u32 val = I915_READ(reg);
1324         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1325              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1326              reg, pipe_name(pipe));
1327
1328         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1329              && (val & SDVO_PIPE_B_SELECT),
1330              "IBX PCH hdmi port still using transcoder B\n");
1331 }
1332
1333 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1334                                       enum pipe pipe)
1335 {
1336         int reg;
1337         u32 val;
1338
1339         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1340         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1341         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1342
1343         reg = PCH_ADPA;
1344         val = I915_READ(reg);
1345         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1346              "PCH VGA enabled on transcoder %c, should be disabled\n",
1347              pipe_name(pipe));
1348
1349         reg = PCH_LVDS;
1350         val = I915_READ(reg);
1351         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1352              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1353              pipe_name(pipe));
1354
1355         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1356         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1357         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1358 }
1359
1360 static void intel_init_dpio(struct drm_device *dev)
1361 {
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363
1364         if (!IS_VALLEYVIEW(dev))
1365                 return;
1366
1367         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1368 }
1369
1370 static void intel_reset_dpio(struct drm_device *dev)
1371 {
1372         struct drm_i915_private *dev_priv = dev->dev_private;
1373
1374         if (!IS_VALLEYVIEW(dev))
1375                 return;
1376
1377         /*
1378          * Enable the CRI clock source so we can get at the display and the
1379          * reference clock for VGA hotplug / manual detection.
1380          */
1381         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1382                    DPLL_REFA_CLK_ENABLE_VLV |
1383                    DPLL_INTEGRATED_CRI_CLK_VLV);
1384
1385         /*
1386          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1387          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1388          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1389          *   b. The other bits such as sfr settings / modesel may all be set
1390          *      to 0.
1391          *
1392          * This should only be done on init and resume from S3 with both
1393          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1394          */
1395         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1396 }
1397
1398 static void vlv_enable_pll(struct intel_crtc *crtc)
1399 {
1400         struct drm_device *dev = crtc->base.dev;
1401         struct drm_i915_private *dev_priv = dev->dev_private;
1402         int reg = DPLL(crtc->pipe);
1403         u32 dpll = crtc->config.dpll_hw_state.dpll;
1404
1405         assert_pipe_disabled(dev_priv, crtc->pipe);
1406
1407         /* No really, not for ILK+ */
1408         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1409
1410         /* PLL is protected by panel, make sure we can write it */
1411         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1412                 assert_panel_unlocked(dev_priv, crtc->pipe);
1413
1414         I915_WRITE(reg, dpll);
1415         POSTING_READ(reg);
1416         udelay(150);
1417
1418         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1419                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1420
1421         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1422         POSTING_READ(DPLL_MD(crtc->pipe));
1423
1424         /* We do this three times for luck */
1425         I915_WRITE(reg, dpll);
1426         POSTING_READ(reg);
1427         udelay(150); /* wait for warmup */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434 }
1435
1436 static void i9xx_enable_pll(struct intel_crtc *crtc)
1437 {
1438         struct drm_device *dev = crtc->base.dev;
1439         struct drm_i915_private *dev_priv = dev->dev_private;
1440         int reg = DPLL(crtc->pipe);
1441         u32 dpll = crtc->config.dpll_hw_state.dpll;
1442
1443         assert_pipe_disabled(dev_priv, crtc->pipe);
1444
1445         /* No really, not for ILK+ */
1446         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1447
1448         /* PLL is protected by panel, make sure we can write it */
1449         if (IS_MOBILE(dev) && !IS_I830(dev))
1450                 assert_panel_unlocked(dev_priv, crtc->pipe);
1451
1452         I915_WRITE(reg, dpll);
1453
1454         /* Wait for the clocks to stabilize. */
1455         POSTING_READ(reg);
1456         udelay(150);
1457
1458         if (INTEL_INFO(dev)->gen >= 4) {
1459                 I915_WRITE(DPLL_MD(crtc->pipe),
1460                            crtc->config.dpll_hw_state.dpll_md);
1461         } else {
1462                 /* The pixel multiplier can only be updated once the
1463                  * DPLL is enabled and the clocks are stable.
1464                  *
1465                  * So write it again.
1466                  */
1467                 I915_WRITE(reg, dpll);
1468         }
1469
1470         /* We do this three times for luck */
1471         I915_WRITE(reg, dpll);
1472         POSTING_READ(reg);
1473         udelay(150); /* wait for warmup */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480 }
1481
1482 /**
1483  * i9xx_disable_pll - disable a PLL
1484  * @dev_priv: i915 private structure
1485  * @pipe: pipe PLL to disable
1486  *
1487  * Disable the PLL for @pipe, making sure the pipe is off first.
1488  *
1489  * Note!  This is for pre-ILK only.
1490  */
1491 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1492 {
1493         /* Don't disable pipe A or pipe A PLLs if needed */
1494         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495                 return;
1496
1497         /* Make sure the pipe isn't still relying on us */
1498         assert_pipe_disabled(dev_priv, pipe);
1499
1500         I915_WRITE(DPLL(pipe), 0);
1501         POSTING_READ(DPLL(pipe));
1502 }
1503
1504 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1505 {
1506         u32 val = 0;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         /*
1512          * Leave integrated clock source and reference clock enabled for pipe B.
1513          * The latter is needed for VGA hotplug / manual detection.
1514          */
1515         if (pipe == PIPE_B)
1516                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1517         I915_WRITE(DPLL(pipe), val);
1518         POSTING_READ(DPLL(pipe));
1519 }
1520
1521 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1522                 struct intel_digital_port *dport)
1523 {
1524         u32 port_mask;
1525
1526         switch (dport->port) {
1527         case PORT_B:
1528                 port_mask = DPLL_PORTB_READY_MASK;
1529                 break;
1530         case PORT_C:
1531                 port_mask = DPLL_PORTC_READY_MASK;
1532                 break;
1533         default:
1534                 BUG();
1535         }
1536
1537         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1538                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1539                      port_name(dport->port), I915_READ(DPLL(0)));
1540 }
1541
1542 /**
1543  * ironlake_enable_shared_dpll - enable PCH PLL
1544  * @dev_priv: i915 private structure
1545  * @pipe: pipe PLL to enable
1546  *
1547  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1548  * drives the transcoder clock.
1549  */
1550 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1551 {
1552         struct drm_device *dev = crtc->base.dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1555
1556         /* PCH PLLs only available on ILK, SNB and IVB */
1557         BUG_ON(INTEL_INFO(dev)->gen < 5);
1558         if (WARN_ON(pll == NULL))
1559                 return;
1560
1561         if (WARN_ON(pll->refcount == 0))
1562                 return;
1563
1564         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1565                       pll->name, pll->active, pll->on,
1566                       crtc->base.base.id);
1567
1568         if (pll->active++) {
1569                 WARN_ON(!pll->on);
1570                 assert_shared_dpll_enabled(dev_priv, pll);
1571                 return;
1572         }
1573         WARN_ON(pll->on);
1574
1575         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1576         pll->enable(dev_priv, pll);
1577         pll->on = true;
1578 }
1579
1580 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1581 {
1582         struct drm_device *dev = crtc->base.dev;
1583         struct drm_i915_private *dev_priv = dev->dev_private;
1584         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1585
1586         /* PCH only available on ILK+ */
1587         BUG_ON(INTEL_INFO(dev)->gen < 5);
1588         if (WARN_ON(pll == NULL))
1589                return;
1590
1591         if (WARN_ON(pll->refcount == 0))
1592                 return;
1593
1594         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1595                       pll->name, pll->active, pll->on,
1596                       crtc->base.base.id);
1597
1598         if (WARN_ON(pll->active == 0)) {
1599                 assert_shared_dpll_disabled(dev_priv, pll);
1600                 return;
1601         }
1602
1603         assert_shared_dpll_enabled(dev_priv, pll);
1604         WARN_ON(!pll->on);
1605         if (--pll->active)
1606                 return;
1607
1608         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1609         pll->disable(dev_priv, pll);
1610         pll->on = false;
1611 }
1612
1613 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1614                                            enum pipe pipe)
1615 {
1616         struct drm_device *dev = dev_priv->dev;
1617         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1619         uint32_t reg, val, pipeconf_val;
1620
1621         /* PCH only available on ILK+ */
1622         BUG_ON(INTEL_INFO(dev)->gen < 5);
1623
1624         /* Make sure PCH DPLL is enabled */
1625         assert_shared_dpll_enabled(dev_priv,
1626                                    intel_crtc_to_shared_dpll(intel_crtc));
1627
1628         /* FDI must be feeding us bits for PCH ports */
1629         assert_fdi_tx_enabled(dev_priv, pipe);
1630         assert_fdi_rx_enabled(dev_priv, pipe);
1631
1632         if (HAS_PCH_CPT(dev)) {
1633                 /* Workaround: Set the timing override bit before enabling the
1634                  * pch transcoder. */
1635                 reg = TRANS_CHICKEN2(pipe);
1636                 val = I915_READ(reg);
1637                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1638                 I915_WRITE(reg, val);
1639         }
1640
1641         reg = PCH_TRANSCONF(pipe);
1642         val = I915_READ(reg);
1643         pipeconf_val = I915_READ(PIPECONF(pipe));
1644
1645         if (HAS_PCH_IBX(dev_priv->dev)) {
1646                 /*
1647                  * make the BPC in transcoder be consistent with
1648                  * that in pipeconf reg.
1649                  */
1650                 val &= ~PIPECONF_BPC_MASK;
1651                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1652         }
1653
1654         val &= ~TRANS_INTERLACE_MASK;
1655         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1656                 if (HAS_PCH_IBX(dev_priv->dev) &&
1657                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1658                         val |= TRANS_LEGACY_INTERLACED_ILK;
1659                 else
1660                         val |= TRANS_INTERLACED;
1661         else
1662                 val |= TRANS_PROGRESSIVE;
1663
1664         I915_WRITE(reg, val | TRANS_ENABLE);
1665         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1666                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1667 }
1668
1669 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1670                                       enum transcoder cpu_transcoder)
1671 {
1672         u32 val, pipeconf_val;
1673
1674         /* PCH only available on ILK+ */
1675         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1676
1677         /* FDI must be feeding us bits for PCH ports */
1678         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1679         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1680
1681         /* Workaround: set timing override bit. */
1682         val = I915_READ(_TRANSA_CHICKEN2);
1683         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1684         I915_WRITE(_TRANSA_CHICKEN2, val);
1685
1686         val = TRANS_ENABLE;
1687         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1688
1689         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1690             PIPECONF_INTERLACED_ILK)
1691                 val |= TRANS_INTERLACED;
1692         else
1693                 val |= TRANS_PROGRESSIVE;
1694
1695         I915_WRITE(LPT_TRANSCONF, val);
1696         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1697                 DRM_ERROR("Failed to enable PCH transcoder\n");
1698 }
1699
1700 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1701                                             enum pipe pipe)
1702 {
1703         struct drm_device *dev = dev_priv->dev;
1704         uint32_t reg, val;
1705
1706         /* FDI relies on the transcoder */
1707         assert_fdi_tx_disabled(dev_priv, pipe);
1708         assert_fdi_rx_disabled(dev_priv, pipe);
1709
1710         /* Ports must be off as well */
1711         assert_pch_ports_disabled(dev_priv, pipe);
1712
1713         reg = PCH_TRANSCONF(pipe);
1714         val = I915_READ(reg);
1715         val &= ~TRANS_ENABLE;
1716         I915_WRITE(reg, val);
1717         /* wait for PCH transcoder off, transcoder state */
1718         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1719                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1720
1721         if (!HAS_PCH_IBX(dev)) {
1722                 /* Workaround: Clear the timing override chicken bit again. */
1723                 reg = TRANS_CHICKEN2(pipe);
1724                 val = I915_READ(reg);
1725                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1726                 I915_WRITE(reg, val);
1727         }
1728 }
1729
1730 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1731 {
1732         u32 val;
1733
1734         val = I915_READ(LPT_TRANSCONF);
1735         val &= ~TRANS_ENABLE;
1736         I915_WRITE(LPT_TRANSCONF, val);
1737         /* wait for PCH transcoder off, transcoder state */
1738         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1739                 DRM_ERROR("Failed to disable PCH transcoder\n");
1740
1741         /* Workaround: clear timing override bit. */
1742         val = I915_READ(_TRANSA_CHICKEN2);
1743         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1744         I915_WRITE(_TRANSA_CHICKEN2, val);
1745 }
1746
1747 /**
1748  * intel_enable_pipe - enable a pipe, asserting requirements
1749  * @crtc: crtc responsible for the pipe
1750  * @dsi: output type is DSI
1751  * @wait_for_vblank: whether we should for a vblank or not after enabling it
1752  *
1753  * Enable @crtc's pipe, making sure that various hardware specific requirements
1754  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1755  */
1756 static void intel_enable_pipe(struct intel_crtc *crtc,
1757                               bool dsi, bool wait_for_vblank)
1758 {
1759         struct drm_device *dev = crtc->base.dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         enum pipe pipe = crtc->pipe;
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (dsi)
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (crtc->config.has_pch_encoder) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE)
1800                 return;
1801
1802         I915_WRITE(reg, val | PIPECONF_ENABLE);
1803         POSTING_READ(reg);
1804         if (wait_for_vblank)
1805                 intel_wait_for_vblank(dev_priv->dev, pipe);
1806 }
1807
1808 /**
1809  * intel_disable_pipe - disable a pipe, asserting requirements
1810  * @dev_priv: i915 private structure
1811  * @pipe: pipe to disable
1812  *
1813  * Disable @pipe, making sure that various hardware specific requirements
1814  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1815  *
1816  * @pipe should be %PIPE_A or %PIPE_B.
1817  *
1818  * Will wait until the pipe has shut down before returning.
1819  */
1820 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1821                                enum pipe pipe)
1822 {
1823         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1824                                                                       pipe);
1825         int reg;
1826         u32 val;
1827
1828         /*
1829          * Make sure planes won't keep trying to pump pixels to us,
1830          * or we might hang the display.
1831          */
1832         assert_planes_disabled(dev_priv, pipe);
1833         assert_cursor_disabled(dev_priv, pipe);
1834         assert_sprites_disabled(dev_priv, pipe);
1835
1836         /* Don't disable pipe A or pipe A PLLs if needed */
1837         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1838                 return;
1839
1840         reg = PIPECONF(cpu_transcoder);
1841         val = I915_READ(reg);
1842         if ((val & PIPECONF_ENABLE) == 0)
1843                 return;
1844
1845         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1846         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1847 }
1848
1849 /*
1850  * Plane regs are double buffered, going from enabled->disabled needs a
1851  * trigger in order to latch.  The display address reg provides this.
1852  */
1853 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1854                                enum plane plane)
1855 {
1856         struct drm_device *dev = dev_priv->dev;
1857         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1858
1859         I915_WRITE(reg, I915_READ(reg));
1860         POSTING_READ(reg);
1861 }
1862
1863 /**
1864  * intel_enable_primary_plane - enable the primary plane on a given pipe
1865  * @dev_priv: i915 private structure
1866  * @plane: plane to enable
1867  * @pipe: pipe being fed
1868  *
1869  * Enable @plane on @pipe, making sure that @pipe is running first.
1870  */
1871 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1872                                        enum plane plane, enum pipe pipe)
1873 {
1874         struct intel_crtc *intel_crtc =
1875                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1876         int reg;
1877         u32 val;
1878
1879         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1880         assert_pipe_enabled(dev_priv, pipe);
1881
1882         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1883
1884         intel_crtc->primary_enabled = true;
1885
1886         reg = DSPCNTR(plane);
1887         val = I915_READ(reg);
1888         if (val & DISPLAY_PLANE_ENABLE)
1889                 return;
1890
1891         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1892         intel_flush_primary_plane(dev_priv, plane);
1893         intel_wait_for_vblank(dev_priv->dev, pipe);
1894 }
1895
1896 /**
1897  * intel_disable_primary_plane - disable the primary plane
1898  * @dev_priv: i915 private structure
1899  * @plane: plane to disable
1900  * @pipe: pipe consuming the data
1901  *
1902  * Disable @plane; should be an independent operation.
1903  */
1904 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1905                                         enum plane plane, enum pipe pipe)
1906 {
1907         struct intel_crtc *intel_crtc =
1908                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1909         int reg;
1910         u32 val;
1911
1912         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1913
1914         intel_crtc->primary_enabled = false;
1915
1916         reg = DSPCNTR(plane);
1917         val = I915_READ(reg);
1918         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1919                 return;
1920
1921         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1922         intel_flush_primary_plane(dev_priv, plane);
1923         intel_wait_for_vblank(dev_priv->dev, pipe);
1924 }
1925
1926 static bool need_vtd_wa(struct drm_device *dev)
1927 {
1928 #ifdef CONFIG_INTEL_IOMMU
1929         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1930                 return true;
1931 #endif
1932         return false;
1933 }
1934
1935 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1936 {
1937         int tile_height;
1938
1939         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1940         return ALIGN(height, tile_height);
1941 }
1942
1943 int
1944 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1945                            struct drm_i915_gem_object *obj,
1946                            struct intel_ring_buffer *pipelined)
1947 {
1948         struct drm_i915_private *dev_priv = dev->dev_private;
1949         u32 alignment;
1950         int ret;
1951
1952         switch (obj->tiling_mode) {
1953         case I915_TILING_NONE:
1954                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1955                         alignment = 128 * 1024;
1956                 else if (INTEL_INFO(dev)->gen >= 4)
1957                         alignment = 4 * 1024;
1958                 else
1959                         alignment = 64 * 1024;
1960                 break;
1961         case I915_TILING_X:
1962                 /* pin() will align the object as required by fence */
1963                 alignment = 0;
1964                 break;
1965         case I915_TILING_Y:
1966                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1967                 return -EINVAL;
1968         default:
1969                 BUG();
1970         }
1971
1972         /* Note that the w/a also requires 64 PTE of padding following the
1973          * bo. We currently fill all unused PTE with the shadow page and so
1974          * we should always have valid PTE following the scanout preventing
1975          * the VT-d warning.
1976          */
1977         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1978                 alignment = 256 * 1024;
1979
1980         dev_priv->mm.interruptible = false;
1981         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1982         if (ret)
1983                 goto err_interruptible;
1984
1985         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1986          * fence, whereas 965+ only requires a fence if using
1987          * framebuffer compression.  For simplicity, we always install
1988          * a fence as the cost is not that onerous.
1989          */
1990         ret = i915_gem_object_get_fence(obj);
1991         if (ret)
1992                 goto err_unpin;
1993
1994         i915_gem_object_pin_fence(obj);
1995
1996         dev_priv->mm.interruptible = true;
1997         return 0;
1998
1999 err_unpin:
2000         i915_gem_object_unpin_from_display_plane(obj);
2001 err_interruptible:
2002         dev_priv->mm.interruptible = true;
2003         return ret;
2004 }
2005
2006 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2007 {
2008         i915_gem_object_unpin_fence(obj);
2009         i915_gem_object_unpin_from_display_plane(obj);
2010 }
2011
2012 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2013  * is assumed to be a power-of-two. */
2014 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2015                                              unsigned int tiling_mode,
2016                                              unsigned int cpp,
2017                                              unsigned int pitch)
2018 {
2019         if (tiling_mode != I915_TILING_NONE) {
2020                 unsigned int tile_rows, tiles;
2021
2022                 tile_rows = *y / 8;
2023                 *y %= 8;
2024
2025                 tiles = *x / (512/cpp);
2026                 *x %= 512/cpp;
2027
2028                 return tile_rows * pitch * 8 + tiles * 4096;
2029         } else {
2030                 unsigned int offset;
2031
2032                 offset = *y * pitch + *x * cpp;
2033                 *y = 0;
2034                 *x = (offset & 4095) / cpp;
2035                 return offset & -4096;
2036         }
2037 }
2038
2039 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2040                              int x, int y)
2041 {
2042         struct drm_device *dev = crtc->dev;
2043         struct drm_i915_private *dev_priv = dev->dev_private;
2044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2045         struct intel_framebuffer *intel_fb;
2046         struct drm_i915_gem_object *obj;
2047         int plane = intel_crtc->plane;
2048         unsigned long linear_offset;
2049         u32 dspcntr;
2050         u32 reg;
2051
2052         switch (plane) {
2053         case 0:
2054         case 1:
2055                 break;
2056         default:
2057                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2058                 return -EINVAL;
2059         }
2060
2061         intel_fb = to_intel_framebuffer(fb);
2062         obj = intel_fb->obj;
2063
2064         reg = DSPCNTR(plane);
2065         dspcntr = I915_READ(reg);
2066         /* Mask out pixel format bits in case we change it */
2067         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2068         switch (fb->pixel_format) {
2069         case DRM_FORMAT_C8:
2070                 dspcntr |= DISPPLANE_8BPP;
2071                 break;
2072         case DRM_FORMAT_XRGB1555:
2073         case DRM_FORMAT_ARGB1555:
2074                 dspcntr |= DISPPLANE_BGRX555;
2075                 break;
2076         case DRM_FORMAT_RGB565:
2077                 dspcntr |= DISPPLANE_BGRX565;
2078                 break;
2079         case DRM_FORMAT_XRGB8888:
2080         case DRM_FORMAT_ARGB8888:
2081                 dspcntr |= DISPPLANE_BGRX888;
2082                 break;
2083         case DRM_FORMAT_XBGR8888:
2084         case DRM_FORMAT_ABGR8888:
2085                 dspcntr |= DISPPLANE_RGBX888;
2086                 break;
2087         case DRM_FORMAT_XRGB2101010:
2088         case DRM_FORMAT_ARGB2101010:
2089                 dspcntr |= DISPPLANE_BGRX101010;
2090                 break;
2091         case DRM_FORMAT_XBGR2101010:
2092         case DRM_FORMAT_ABGR2101010:
2093                 dspcntr |= DISPPLANE_RGBX101010;
2094                 break;
2095         default:
2096                 BUG();
2097         }
2098
2099         if (INTEL_INFO(dev)->gen >= 4) {
2100                 if (obj->tiling_mode != I915_TILING_NONE)
2101                         dspcntr |= DISPPLANE_TILED;
2102                 else
2103                         dspcntr &= ~DISPPLANE_TILED;
2104         }
2105
2106         if (IS_G4X(dev))
2107                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2108
2109         I915_WRITE(reg, dspcntr);
2110
2111         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2112
2113         if (INTEL_INFO(dev)->gen >= 4) {
2114                 intel_crtc->dspaddr_offset =
2115                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2116                                                        fb->bits_per_pixel / 8,
2117                                                        fb->pitches[0]);
2118                 linear_offset -= intel_crtc->dspaddr_offset;
2119         } else {
2120                 intel_crtc->dspaddr_offset = linear_offset;
2121         }
2122
2123         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2124                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2125                       fb->pitches[0]);
2126         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2127         if (INTEL_INFO(dev)->gen >= 4) {
2128                 I915_WRITE(DSPSURF(plane),
2129                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2130                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2131                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2132         } else
2133                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2134         POSTING_READ(reg);
2135
2136         return 0;
2137 }
2138
2139 static int ironlake_update_plane(struct drm_crtc *crtc,
2140                                  struct drm_framebuffer *fb, int x, int y)
2141 {
2142         struct drm_device *dev = crtc->dev;
2143         struct drm_i915_private *dev_priv = dev->dev_private;
2144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145         struct intel_framebuffer *intel_fb;
2146         struct drm_i915_gem_object *obj;
2147         int plane = intel_crtc->plane;
2148         unsigned long linear_offset;
2149         u32 dspcntr;
2150         u32 reg;
2151
2152         switch (plane) {
2153         case 0:
2154         case 1:
2155         case 2:
2156                 break;
2157         default:
2158                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2159                 return -EINVAL;
2160         }
2161
2162         intel_fb = to_intel_framebuffer(fb);
2163         obj = intel_fb->obj;
2164
2165         reg = DSPCNTR(plane);
2166         dspcntr = I915_READ(reg);
2167         /* Mask out pixel format bits in case we change it */
2168         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2169         switch (fb->pixel_format) {
2170         case DRM_FORMAT_C8:
2171                 dspcntr |= DISPPLANE_8BPP;
2172                 break;
2173         case DRM_FORMAT_RGB565:
2174                 dspcntr |= DISPPLANE_BGRX565;
2175                 break;
2176         case DRM_FORMAT_XRGB8888:
2177         case DRM_FORMAT_ARGB8888:
2178                 dspcntr |= DISPPLANE_BGRX888;
2179                 break;
2180         case DRM_FORMAT_XBGR8888:
2181         case DRM_FORMAT_ABGR8888:
2182                 dspcntr |= DISPPLANE_RGBX888;
2183                 break;
2184         case DRM_FORMAT_XRGB2101010:
2185         case DRM_FORMAT_ARGB2101010:
2186                 dspcntr |= DISPPLANE_BGRX101010;
2187                 break;
2188         case DRM_FORMAT_XBGR2101010:
2189         case DRM_FORMAT_ABGR2101010:
2190                 dspcntr |= DISPPLANE_RGBX101010;
2191                 break;
2192         default:
2193                 BUG();
2194         }
2195
2196         if (obj->tiling_mode != I915_TILING_NONE)
2197                 dspcntr |= DISPPLANE_TILED;
2198         else
2199                 dspcntr &= ~DISPPLANE_TILED;
2200
2201         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2202                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2203         else
2204                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2205
2206         I915_WRITE(reg, dspcntr);
2207
2208         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2209         intel_crtc->dspaddr_offset =
2210                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2211                                                fb->bits_per_pixel / 8,
2212                                                fb->pitches[0]);
2213         linear_offset -= intel_crtc->dspaddr_offset;
2214
2215         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2216                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2217                       fb->pitches[0]);
2218         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2219         I915_WRITE(DSPSURF(plane),
2220                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2221         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2222                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2223         } else {
2224                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2225                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2226         }
2227         POSTING_READ(reg);
2228
2229         return 0;
2230 }
2231
2232 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2233 static int
2234 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2235                            int x, int y, enum mode_set_atomic state)
2236 {
2237         struct drm_device *dev = crtc->dev;
2238         struct drm_i915_private *dev_priv = dev->dev_private;
2239
2240         if (dev_priv->display.disable_fbc)
2241                 dev_priv->display.disable_fbc(dev);
2242         intel_increase_pllclock(crtc);
2243
2244         return dev_priv->display.update_plane(crtc, fb, x, y);
2245 }
2246
2247 void intel_display_handle_reset(struct drm_device *dev)
2248 {
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250         struct drm_crtc *crtc;
2251
2252         /*
2253          * Flips in the rings have been nuked by the reset,
2254          * so complete all pending flips so that user space
2255          * will get its events and not get stuck.
2256          *
2257          * Also update the base address of all primary
2258          * planes to the the last fb to make sure we're
2259          * showing the correct fb after a reset.
2260          *
2261          * Need to make two loops over the crtcs so that we
2262          * don't try to grab a crtc mutex before the
2263          * pending_flip_queue really got woken up.
2264          */
2265
2266         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2267                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2268                 enum plane plane = intel_crtc->plane;
2269
2270                 intel_prepare_page_flip(dev, plane);
2271                 intel_finish_page_flip_plane(dev, plane);
2272         }
2273
2274         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2275                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2276
2277                 mutex_lock(&crtc->mutex);
2278                 /*
2279                  * FIXME: Once we have proper support for primary planes (and
2280                  * disabling them without disabling the entire crtc) allow again
2281                  * a NULL crtc->fb.
2282                  */
2283                 if (intel_crtc->active && crtc->fb)
2284                         dev_priv->display.update_plane(crtc, crtc->fb,
2285                                                        crtc->x, crtc->y);
2286                 mutex_unlock(&crtc->mutex);
2287         }
2288 }
2289
2290 static int
2291 intel_finish_fb(struct drm_framebuffer *old_fb)
2292 {
2293         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2294         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2295         bool was_interruptible = dev_priv->mm.interruptible;
2296         int ret;
2297
2298         /* Big Hammer, we also need to ensure that any pending
2299          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2300          * current scanout is retired before unpinning the old
2301          * framebuffer.
2302          *
2303          * This should only fail upon a hung GPU, in which case we
2304          * can safely continue.
2305          */
2306         dev_priv->mm.interruptible = false;
2307         ret = i915_gem_object_finish_gpu(obj);
2308         dev_priv->mm.interruptible = was_interruptible;
2309
2310         return ret;
2311 }
2312
2313 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2314 {
2315         struct drm_device *dev = crtc->dev;
2316         struct drm_i915_master_private *master_priv;
2317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318
2319         if (!dev->primary->master)
2320                 return;
2321
2322         master_priv = dev->primary->master->driver_priv;
2323         if (!master_priv->sarea_priv)
2324                 return;
2325
2326         switch (intel_crtc->pipe) {
2327         case 0:
2328                 master_priv->sarea_priv->pipeA_x = x;
2329                 master_priv->sarea_priv->pipeA_y = y;
2330                 break;
2331         case 1:
2332                 master_priv->sarea_priv->pipeB_x = x;
2333                 master_priv->sarea_priv->pipeB_y = y;
2334                 break;
2335         default:
2336                 break;
2337         }
2338 }
2339
2340 static int
2341 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2342                     struct drm_framebuffer *fb)
2343 {
2344         struct drm_device *dev = crtc->dev;
2345         struct drm_i915_private *dev_priv = dev->dev_private;
2346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2347         struct drm_framebuffer *old_fb;
2348         int ret;
2349
2350         /* no fb bound */
2351         if (!fb) {
2352                 DRM_ERROR("No FB bound\n");
2353                 return 0;
2354         }
2355
2356         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2357                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2358                           plane_name(intel_crtc->plane),
2359                           INTEL_INFO(dev)->num_pipes);
2360                 return -EINVAL;
2361         }
2362
2363         mutex_lock(&dev->struct_mutex);
2364         ret = intel_pin_and_fence_fb_obj(dev,
2365                                          to_intel_framebuffer(fb)->obj,
2366                                          NULL);
2367         if (ret != 0) {
2368                 mutex_unlock(&dev->struct_mutex);
2369                 DRM_ERROR("pin & fence failed\n");
2370                 return ret;
2371         }
2372
2373         /*
2374          * Update pipe size and adjust fitter if needed: the reason for this is
2375          * that in compute_mode_changes we check the native mode (not the pfit
2376          * mode) to see if we can flip rather than do a full mode set. In the
2377          * fastboot case, we'll flip, but if we don't update the pipesrc and
2378          * pfit state, we'll end up with a big fb scanned out into the wrong
2379          * sized surface.
2380          *
2381          * To fix this properly, we need to hoist the checks up into
2382          * compute_mode_changes (or above), check the actual pfit state and
2383          * whether the platform allows pfit disable with pipe active, and only
2384          * then update the pipesrc and pfit state, even on the flip path.
2385          */
2386         if (i915.fastboot) {
2387                 const struct drm_display_mode *adjusted_mode =
2388                         &intel_crtc->config.adjusted_mode;
2389
2390                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2391                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2392                            (adjusted_mode->crtc_vdisplay - 1));
2393                 if (!intel_crtc->config.pch_pfit.enabled &&
2394                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2395                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2396                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2397                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2398                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2399                 }
2400                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2401                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2402         }
2403
2404         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2405         if (ret) {
2406                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2407                 mutex_unlock(&dev->struct_mutex);
2408                 DRM_ERROR("failed to update base address\n");
2409                 return ret;
2410         }
2411
2412         old_fb = crtc->fb;
2413         crtc->fb = fb;
2414         crtc->x = x;
2415         crtc->y = y;
2416
2417         if (old_fb) {
2418                 if (intel_crtc->active && old_fb != fb)
2419                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2420                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2421         }
2422
2423         intel_update_fbc(dev);
2424         intel_edp_psr_update(dev);
2425         mutex_unlock(&dev->struct_mutex);
2426
2427         intel_crtc_update_sarea_pos(crtc, x, y);
2428
2429         return 0;
2430 }
2431
2432 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2433 {
2434         struct drm_device *dev = crtc->dev;
2435         struct drm_i915_private *dev_priv = dev->dev_private;
2436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2437         int pipe = intel_crtc->pipe;
2438         u32 reg, temp;
2439
2440         /* enable normal train */
2441         reg = FDI_TX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         if (IS_IVYBRIDGE(dev)) {
2444                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2445                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2446         } else {
2447                 temp &= ~FDI_LINK_TRAIN_NONE;
2448                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2449         }
2450         I915_WRITE(reg, temp);
2451
2452         reg = FDI_RX_CTL(pipe);
2453         temp = I915_READ(reg);
2454         if (HAS_PCH_CPT(dev)) {
2455                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2456                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2457         } else {
2458                 temp &= ~FDI_LINK_TRAIN_NONE;
2459                 temp |= FDI_LINK_TRAIN_NONE;
2460         }
2461         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2462
2463         /* wait one idle pattern time */
2464         POSTING_READ(reg);
2465         udelay(1000);
2466
2467         /* IVB wants error correction enabled */
2468         if (IS_IVYBRIDGE(dev))
2469                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2470                            FDI_FE_ERRC_ENABLE);
2471 }
2472
2473 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2474 {
2475         return crtc->base.enabled && crtc->active &&
2476                 crtc->config.has_pch_encoder;
2477 }
2478
2479 static void ivb_modeset_global_resources(struct drm_device *dev)
2480 {
2481         struct drm_i915_private *dev_priv = dev->dev_private;
2482         struct intel_crtc *pipe_B_crtc =
2483                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2484         struct intel_crtc *pipe_C_crtc =
2485                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2486         uint32_t temp;
2487
2488         /*
2489          * When everything is off disable fdi C so that we could enable fdi B
2490          * with all lanes. Note that we don't care about enabled pipes without
2491          * an enabled pch encoder.
2492          */
2493         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2494             !pipe_has_enabled_pch(pipe_C_crtc)) {
2495                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2496                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2497
2498                 temp = I915_READ(SOUTH_CHICKEN1);
2499                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2500                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2501                 I915_WRITE(SOUTH_CHICKEN1, temp);
2502         }
2503 }
2504
2505 /* The FDI link training functions for ILK/Ibexpeak. */
2506 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2507 {
2508         struct drm_device *dev = crtc->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511         int pipe = intel_crtc->pipe;
2512         int plane = intel_crtc->plane;
2513         u32 reg, temp, tries;
2514
2515         /* FDI needs bits from pipe & plane first */
2516         assert_pipe_enabled(dev_priv, pipe);
2517         assert_plane_enabled(dev_priv, plane);
2518
2519         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520            for train result */
2521         reg = FDI_RX_IMR(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_RX_SYMBOL_LOCK;
2524         temp &= ~FDI_RX_BIT_LOCK;
2525         I915_WRITE(reg, temp);
2526         I915_READ(reg);
2527         udelay(150);
2528
2529         /* enable CPU FDI TX and PCH FDI RX */
2530         reg = FDI_TX_CTL(pipe);
2531         temp = I915_READ(reg);
2532         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2533         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2534         temp &= ~FDI_LINK_TRAIN_NONE;
2535         temp |= FDI_LINK_TRAIN_PATTERN_1;
2536         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2537
2538         reg = FDI_RX_CTL(pipe);
2539         temp = I915_READ(reg);
2540         temp &= ~FDI_LINK_TRAIN_NONE;
2541         temp |= FDI_LINK_TRAIN_PATTERN_1;
2542         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2543
2544         POSTING_READ(reg);
2545         udelay(150);
2546
2547         /* Ironlake workaround, enable clock pointer after FDI enable*/
2548         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2549         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2550                    FDI_RX_PHASE_SYNC_POINTER_EN);
2551
2552         reg = FDI_RX_IIR(pipe);
2553         for (tries = 0; tries < 5; tries++) {
2554                 temp = I915_READ(reg);
2555                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2556
2557                 if ((temp & FDI_RX_BIT_LOCK)) {
2558                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2559                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2560                         break;
2561                 }
2562         }
2563         if (tries == 5)
2564                 DRM_ERROR("FDI train 1 fail!\n");
2565
2566         /* Train 2 */
2567         reg = FDI_TX_CTL(pipe);
2568         temp = I915_READ(reg);
2569         temp &= ~FDI_LINK_TRAIN_NONE;
2570         temp |= FDI_LINK_TRAIN_PATTERN_2;
2571         I915_WRITE(reg, temp);
2572
2573         reg = FDI_RX_CTL(pipe);
2574         temp = I915_READ(reg);
2575         temp &= ~FDI_LINK_TRAIN_NONE;
2576         temp |= FDI_LINK_TRAIN_PATTERN_2;
2577         I915_WRITE(reg, temp);
2578
2579         POSTING_READ(reg);
2580         udelay(150);
2581
2582         reg = FDI_RX_IIR(pipe);
2583         for (tries = 0; tries < 5; tries++) {
2584                 temp = I915_READ(reg);
2585                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586
2587                 if (temp & FDI_RX_SYMBOL_LOCK) {
2588                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2589                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2590                         break;
2591                 }
2592         }
2593         if (tries == 5)
2594                 DRM_ERROR("FDI train 2 fail!\n");
2595
2596         DRM_DEBUG_KMS("FDI train done\n");
2597
2598 }
2599
2600 static const int snb_b_fdi_train_param[] = {
2601         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2602         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2603         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2604         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2605 };
2606
2607 /* The FDI link training functions for SNB/Cougarpoint. */
2608 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2609 {
2610         struct drm_device *dev = crtc->dev;
2611         struct drm_i915_private *dev_priv = dev->dev_private;
2612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2613         int pipe = intel_crtc->pipe;
2614         u32 reg, temp, i, retry;
2615
2616         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2617            for train result */
2618         reg = FDI_RX_IMR(pipe);
2619         temp = I915_READ(reg);
2620         temp &= ~FDI_RX_SYMBOL_LOCK;
2621         temp &= ~FDI_RX_BIT_LOCK;
2622         I915_WRITE(reg, temp);
2623
2624         POSTING_READ(reg);
2625         udelay(150);
2626
2627         /* enable CPU FDI TX and PCH FDI RX */
2628         reg = FDI_TX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2631         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2632         temp &= ~FDI_LINK_TRAIN_NONE;
2633         temp |= FDI_LINK_TRAIN_PATTERN_1;
2634         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2635         /* SNB-B */
2636         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2637         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2638
2639         I915_WRITE(FDI_RX_MISC(pipe),
2640                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         if (HAS_PCH_CPT(dev)) {
2645                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2647         } else {
2648                 temp &= ~FDI_LINK_TRAIN_NONE;
2649                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2650         }
2651         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2652
2653         POSTING_READ(reg);
2654         udelay(150);
2655
2656         for (i = 0; i < 4; i++) {
2657                 reg = FDI_TX_CTL(pipe);
2658                 temp = I915_READ(reg);
2659                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660                 temp |= snb_b_fdi_train_param[i];
2661                 I915_WRITE(reg, temp);
2662
2663                 POSTING_READ(reg);
2664                 udelay(500);
2665
2666                 for (retry = 0; retry < 5; retry++) {
2667                         reg = FDI_RX_IIR(pipe);
2668                         temp = I915_READ(reg);
2669                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2670                         if (temp & FDI_RX_BIT_LOCK) {
2671                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2672                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2673                                 break;
2674                         }
2675                         udelay(50);
2676                 }
2677                 if (retry < 5)
2678                         break;
2679         }
2680         if (i == 4)
2681                 DRM_ERROR("FDI train 1 fail!\n");
2682
2683         /* Train 2 */
2684         reg = FDI_TX_CTL(pipe);
2685         temp = I915_READ(reg);
2686         temp &= ~FDI_LINK_TRAIN_NONE;
2687         temp |= FDI_LINK_TRAIN_PATTERN_2;
2688         if (IS_GEN6(dev)) {
2689                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690                 /* SNB-B */
2691                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2692         }
2693         I915_WRITE(reg, temp);
2694
2695         reg = FDI_RX_CTL(pipe);
2696         temp = I915_READ(reg);
2697         if (HAS_PCH_CPT(dev)) {
2698                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2699                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2700         } else {
2701                 temp &= ~FDI_LINK_TRAIN_NONE;
2702                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2703         }
2704         I915_WRITE(reg, temp);
2705
2706         POSTING_READ(reg);
2707         udelay(150);
2708
2709         for (i = 0; i < 4; i++) {
2710                 reg = FDI_TX_CTL(pipe);
2711                 temp = I915_READ(reg);
2712                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2713                 temp |= snb_b_fdi_train_param[i];
2714                 I915_WRITE(reg, temp);
2715
2716                 POSTING_READ(reg);
2717                 udelay(500);
2718
2719                 for (retry = 0; retry < 5; retry++) {
2720                         reg = FDI_RX_IIR(pipe);
2721                         temp = I915_READ(reg);
2722                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2723                         if (temp & FDI_RX_SYMBOL_LOCK) {
2724                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2725                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2726                                 break;
2727                         }
2728                         udelay(50);
2729                 }
2730                 if (retry < 5)
2731                         break;
2732         }
2733         if (i == 4)
2734                 DRM_ERROR("FDI train 2 fail!\n");
2735
2736         DRM_DEBUG_KMS("FDI train done.\n");
2737 }
2738
2739 /* Manual link training for Ivy Bridge A0 parts */
2740 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2741 {
2742         struct drm_device *dev = crtc->dev;
2743         struct drm_i915_private *dev_priv = dev->dev_private;
2744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2745         int pipe = intel_crtc->pipe;
2746         u32 reg, temp, i, j;
2747
2748         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2749            for train result */
2750         reg = FDI_RX_IMR(pipe);
2751         temp = I915_READ(reg);
2752         temp &= ~FDI_RX_SYMBOL_LOCK;
2753         temp &= ~FDI_RX_BIT_LOCK;
2754         I915_WRITE(reg, temp);
2755
2756         POSTING_READ(reg);
2757         udelay(150);
2758
2759         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2760                       I915_READ(FDI_RX_IIR(pipe)));
2761
2762         /* Try each vswing and preemphasis setting twice before moving on */
2763         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2764                 /* disable first in case we need to retry */
2765                 reg = FDI_TX_CTL(pipe);
2766                 temp = I915_READ(reg);
2767                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2768                 temp &= ~FDI_TX_ENABLE;
2769                 I915_WRITE(reg, temp);
2770
2771                 reg = FDI_RX_CTL(pipe);
2772                 temp = I915_READ(reg);
2773                 temp &= ~FDI_LINK_TRAIN_AUTO;
2774                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2775                 temp &= ~FDI_RX_ENABLE;
2776                 I915_WRITE(reg, temp);
2777
2778                 /* enable CPU FDI TX and PCH FDI RX */
2779                 reg = FDI_TX_CTL(pipe);
2780                 temp = I915_READ(reg);
2781                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2782                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2783                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2784                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2785                 temp |= snb_b_fdi_train_param[j/2];
2786                 temp |= FDI_COMPOSITE_SYNC;
2787                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2788
2789                 I915_WRITE(FDI_RX_MISC(pipe),
2790                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2791
2792                 reg = FDI_RX_CTL(pipe);
2793                 temp = I915_READ(reg);
2794                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2795                 temp |= FDI_COMPOSITE_SYNC;
2796                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2797
2798                 POSTING_READ(reg);
2799                 udelay(1); /* should be 0.5us */
2800
2801                 for (i = 0; i < 4; i++) {
2802                         reg = FDI_RX_IIR(pipe);
2803                         temp = I915_READ(reg);
2804                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2805
2806                         if (temp & FDI_RX_BIT_LOCK ||
2807                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2808                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2809                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2810                                               i);
2811                                 break;
2812                         }
2813                         udelay(1); /* should be 0.5us */
2814                 }
2815                 if (i == 4) {
2816                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2817                         continue;
2818                 }
2819
2820                 /* Train 2 */
2821                 reg = FDI_TX_CTL(pipe);
2822                 temp = I915_READ(reg);
2823                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2824                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2825                 I915_WRITE(reg, temp);
2826
2827                 reg = FDI_RX_CTL(pipe);
2828                 temp = I915_READ(reg);
2829                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2830                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2831                 I915_WRITE(reg, temp);
2832
2833                 POSTING_READ(reg);
2834                 udelay(2); /* should be 1.5us */
2835
2836                 for (i = 0; i < 4; i++) {
2837                         reg = FDI_RX_IIR(pipe);
2838                         temp = I915_READ(reg);
2839                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2840
2841                         if (temp & FDI_RX_SYMBOL_LOCK ||
2842                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2843                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2844                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2845                                               i);
2846                                 goto train_done;
2847                         }
2848                         udelay(2); /* should be 1.5us */
2849                 }
2850                 if (i == 4)
2851                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2852         }
2853
2854 train_done:
2855         DRM_DEBUG_KMS("FDI train done.\n");
2856 }
2857
2858 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2859 {
2860         struct drm_device *dev = intel_crtc->base.dev;
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862         int pipe = intel_crtc->pipe;
2863         u32 reg, temp;
2864
2865
2866         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2867         reg = FDI_RX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2870         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2871         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2872         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2873
2874         POSTING_READ(reg);
2875         udelay(200);
2876
2877         /* Switch from Rawclk to PCDclk */
2878         temp = I915_READ(reg);
2879         I915_WRITE(reg, temp | FDI_PCDCLK);
2880
2881         POSTING_READ(reg);
2882         udelay(200);
2883
2884         /* Enable CPU FDI TX PLL, always on for Ironlake */
2885         reg = FDI_TX_CTL(pipe);
2886         temp = I915_READ(reg);
2887         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2888                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2889
2890                 POSTING_READ(reg);
2891                 udelay(100);
2892         }
2893 }
2894
2895 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2896 {
2897         struct drm_device *dev = intel_crtc->base.dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         int pipe = intel_crtc->pipe;
2900         u32 reg, temp;
2901
2902         /* Switch from PCDclk to Rawclk */
2903         reg = FDI_RX_CTL(pipe);
2904         temp = I915_READ(reg);
2905         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2906
2907         /* Disable CPU FDI TX PLL */
2908         reg = FDI_TX_CTL(pipe);
2909         temp = I915_READ(reg);
2910         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2911
2912         POSTING_READ(reg);
2913         udelay(100);
2914
2915         reg = FDI_RX_CTL(pipe);
2916         temp = I915_READ(reg);
2917         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2918
2919         /* Wait for the clocks to turn off. */
2920         POSTING_READ(reg);
2921         udelay(100);
2922 }
2923
2924 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2925 {
2926         struct drm_device *dev = crtc->dev;
2927         struct drm_i915_private *dev_priv = dev->dev_private;
2928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2929         int pipe = intel_crtc->pipe;
2930         u32 reg, temp;
2931
2932         /* disable CPU FDI tx and PCH FDI rx */
2933         reg = FDI_TX_CTL(pipe);
2934         temp = I915_READ(reg);
2935         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2936         POSTING_READ(reg);
2937
2938         reg = FDI_RX_CTL(pipe);
2939         temp = I915_READ(reg);
2940         temp &= ~(0x7 << 16);
2941         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2942         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2943
2944         POSTING_READ(reg);
2945         udelay(100);
2946
2947         /* Ironlake workaround, disable clock pointer after downing FDI */
2948         if (HAS_PCH_IBX(dev)) {
2949                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2950         }
2951
2952         /* still set train pattern 1 */
2953         reg = FDI_TX_CTL(pipe);
2954         temp = I915_READ(reg);
2955         temp &= ~FDI_LINK_TRAIN_NONE;
2956         temp |= FDI_LINK_TRAIN_PATTERN_1;
2957         I915_WRITE(reg, temp);
2958
2959         reg = FDI_RX_CTL(pipe);
2960         temp = I915_READ(reg);
2961         if (HAS_PCH_CPT(dev)) {
2962                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2963                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2964         } else {
2965                 temp &= ~FDI_LINK_TRAIN_NONE;
2966                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2967         }
2968         /* BPC in FDI rx is consistent with that in PIPECONF */
2969         temp &= ~(0x07 << 16);
2970         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2971         I915_WRITE(reg, temp);
2972
2973         POSTING_READ(reg);
2974         udelay(100);
2975 }
2976
2977 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2978 {
2979         struct drm_device *dev = crtc->dev;
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2982         unsigned long flags;
2983         bool pending;
2984
2985         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2986             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2987                 return false;
2988
2989         spin_lock_irqsave(&dev->event_lock, flags);
2990         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2991         spin_unlock_irqrestore(&dev->event_lock, flags);
2992
2993         return pending;
2994 }
2995
2996 bool intel_has_pending_fb_unpin(struct drm_device *dev)
2997 {
2998         struct intel_crtc *crtc;
2999
3000         /* Note that we don't need to be called with mode_config.lock here
3001          * as our list of CRTC objects is static for the lifetime of the
3002          * device and so cannot disappear as we iterate. Similarly, we can
3003          * happily treat the predicates as racy, atomic checks as userspace
3004          * cannot claim and pin a new fb without at least acquring the
3005          * struct_mutex and so serialising with us.
3006          */
3007         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3008                 if (atomic_read(&crtc->unpin_work_count) == 0)
3009                         continue;
3010
3011                 if (crtc->unpin_work)
3012                         intel_wait_for_vblank(dev, crtc->pipe);
3013
3014                 return true;
3015         }
3016
3017         return false;
3018 }
3019
3020 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3021 {
3022         struct drm_device *dev = crtc->dev;
3023         struct drm_i915_private *dev_priv = dev->dev_private;
3024
3025         if (crtc->fb == NULL)
3026                 return;
3027
3028         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3029
3030         wait_event(dev_priv->pending_flip_queue,
3031                    !intel_crtc_has_pending_flip(crtc));
3032
3033         mutex_lock(&dev->struct_mutex);
3034         intel_finish_fb(crtc->fb);
3035         mutex_unlock(&dev->struct_mutex);
3036 }
3037
3038 /* Program iCLKIP clock to the desired frequency */
3039 static void lpt_program_iclkip(struct drm_crtc *crtc)
3040 {
3041         struct drm_device *dev = crtc->dev;
3042         struct drm_i915_private *dev_priv = dev->dev_private;
3043         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3044         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3045         u32 temp;
3046
3047         mutex_lock(&dev_priv->dpio_lock);
3048
3049         /* It is necessary to ungate the pixclk gate prior to programming
3050          * the divisors, and gate it back when it is done.
3051          */
3052         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3053
3054         /* Disable SSCCTL */
3055         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3056                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3057                                 SBI_SSCCTL_DISABLE,
3058                         SBI_ICLK);
3059
3060         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3061         if (clock == 20000) {
3062                 auxdiv = 1;
3063                 divsel = 0x41;
3064                 phaseinc = 0x20;
3065         } else {
3066                 /* The iCLK virtual clock root frequency is in MHz,
3067                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3068                  * divisors, it is necessary to divide one by another, so we
3069                  * convert the virtual clock precision to KHz here for higher
3070                  * precision.
3071                  */
3072                 u32 iclk_virtual_root_freq = 172800 * 1000;
3073                 u32 iclk_pi_range = 64;
3074                 u32 desired_divisor, msb_divisor_value, pi_value;
3075
3076                 desired_divisor = (iclk_virtual_root_freq / clock);
3077                 msb_divisor_value = desired_divisor / iclk_pi_range;
3078                 pi_value = desired_divisor % iclk_pi_range;
3079
3080                 auxdiv = 0;
3081                 divsel = msb_divisor_value - 2;
3082                 phaseinc = pi_value;
3083         }
3084
3085         /* This should not happen with any sane values */
3086         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3087                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3088         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3089                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3090
3091         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3092                         clock,
3093                         auxdiv,
3094                         divsel,
3095                         phasedir,
3096                         phaseinc);
3097
3098         /* Program SSCDIVINTPHASE6 */
3099         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3100         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3101         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3102         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3103         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3104         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3105         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3106         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3107
3108         /* Program SSCAUXDIV */
3109         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3110         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3111         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3112         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3113
3114         /* Enable modulator and associated divider */
3115         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3116         temp &= ~SBI_SSCCTL_DISABLE;
3117         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3118
3119         /* Wait for initialization time */
3120         udelay(24);
3121
3122         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3123
3124         mutex_unlock(&dev_priv->dpio_lock);
3125 }
3126
3127 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3128                                                 enum pipe pch_transcoder)
3129 {
3130         struct drm_device *dev = crtc->base.dev;
3131         struct drm_i915_private *dev_priv = dev->dev_private;
3132         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3133
3134         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3135                    I915_READ(HTOTAL(cpu_transcoder)));
3136         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3137                    I915_READ(HBLANK(cpu_transcoder)));
3138         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3139                    I915_READ(HSYNC(cpu_transcoder)));
3140
3141         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3142                    I915_READ(VTOTAL(cpu_transcoder)));
3143         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3144                    I915_READ(VBLANK(cpu_transcoder)));
3145         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3146                    I915_READ(VSYNC(cpu_transcoder)));
3147         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3148                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3149 }
3150
3151 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3152 {
3153         struct drm_i915_private *dev_priv = dev->dev_private;
3154         uint32_t temp;
3155
3156         temp = I915_READ(SOUTH_CHICKEN1);
3157         if (temp & FDI_BC_BIFURCATION_SELECT)
3158                 return;
3159
3160         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3161         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3162
3163         temp |= FDI_BC_BIFURCATION_SELECT;
3164         DRM_DEBUG_KMS("enabling fdi C rx\n");
3165         I915_WRITE(SOUTH_CHICKEN1, temp);
3166         POSTING_READ(SOUTH_CHICKEN1);
3167 }
3168
3169 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3170 {
3171         struct drm_device *dev = intel_crtc->base.dev;
3172         struct drm_i915_private *dev_priv = dev->dev_private;
3173
3174         switch (intel_crtc->pipe) {
3175         case PIPE_A:
3176                 break;
3177         case PIPE_B:
3178                 if (intel_crtc->config.fdi_lanes > 2)
3179                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3180                 else
3181                         cpt_enable_fdi_bc_bifurcation(dev);
3182
3183                 break;
3184         case PIPE_C:
3185                 cpt_enable_fdi_bc_bifurcation(dev);
3186
3187                 break;
3188         default:
3189                 BUG();
3190         }
3191 }
3192
3193 /*
3194  * Enable PCH resources required for PCH ports:
3195  *   - PCH PLLs
3196  *   - FDI training & RX/TX
3197  *   - update transcoder timings
3198  *   - DP transcoding bits
3199  *   - transcoder
3200  */
3201 static void ironlake_pch_enable(struct drm_crtc *crtc)
3202 {
3203         struct drm_device *dev = crtc->dev;
3204         struct drm_i915_private *dev_priv = dev->dev_private;
3205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3206         int pipe = intel_crtc->pipe;
3207         u32 reg, temp;
3208
3209         assert_pch_transcoder_disabled(dev_priv, pipe);
3210
3211         if (IS_IVYBRIDGE(dev))
3212                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3213
3214         /* Write the TU size bits before fdi link training, so that error
3215          * detection works. */
3216         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3217                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3218
3219         /* For PCH output, training FDI link */
3220         dev_priv->display.fdi_link_train(crtc);
3221
3222         /* We need to program the right clock selection before writing the pixel
3223          * mutliplier into the DPLL. */
3224         if (HAS_PCH_CPT(dev)) {
3225                 u32 sel;
3226
3227                 temp = I915_READ(PCH_DPLL_SEL);
3228                 temp |= TRANS_DPLL_ENABLE(pipe);
3229                 sel = TRANS_DPLLB_SEL(pipe);
3230                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3231                         temp |= sel;
3232                 else
3233                         temp &= ~sel;
3234                 I915_WRITE(PCH_DPLL_SEL, temp);
3235         }
3236
3237         /* XXX: pch pll's can be enabled any time before we enable the PCH
3238          * transcoder, and we actually should do this to not upset any PCH
3239          * transcoder that already use the clock when we share it.
3240          *
3241          * Note that enable_shared_dpll tries to do the right thing, but
3242          * get_shared_dpll unconditionally resets the pll - we need that to have
3243          * the right LVDS enable sequence. */
3244         ironlake_enable_shared_dpll(intel_crtc);
3245
3246         /* set transcoder timing, panel must allow it */
3247         assert_panel_unlocked(dev_priv, pipe);
3248         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3249
3250         intel_fdi_normal_train(crtc);
3251
3252         /* For PCH DP, enable TRANS_DP_CTL */
3253         if (HAS_PCH_CPT(dev) &&
3254             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3255              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3256                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3257                 reg = TRANS_DP_CTL(pipe);
3258                 temp = I915_READ(reg);
3259                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3260                           TRANS_DP_SYNC_MASK |
3261                           TRANS_DP_BPC_MASK);
3262                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3263                          TRANS_DP_ENH_FRAMING);
3264                 temp |= bpc << 9; /* same format but at 11:9 */
3265
3266                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3267                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3268                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3269                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3270
3271                 switch (intel_trans_dp_port_sel(crtc)) {
3272                 case PCH_DP_B:
3273                         temp |= TRANS_DP_PORT_SEL_B;
3274                         break;
3275                 case PCH_DP_C:
3276                         temp |= TRANS_DP_PORT_SEL_C;
3277                         break;
3278                 case PCH_DP_D:
3279                         temp |= TRANS_DP_PORT_SEL_D;
3280                         break;
3281                 default:
3282                         BUG();
3283                 }
3284
3285                 I915_WRITE(reg, temp);
3286         }
3287
3288         ironlake_enable_pch_transcoder(dev_priv, pipe);
3289 }
3290
3291 static void lpt_pch_enable(struct drm_crtc *crtc)
3292 {
3293         struct drm_device *dev = crtc->dev;
3294         struct drm_i915_private *dev_priv = dev->dev_private;
3295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3297
3298         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3299
3300         lpt_program_iclkip(crtc);
3301
3302         /* Set transcoder timing. */
3303         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3304
3305         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3306 }
3307
3308 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3309 {
3310         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3311
3312         if (pll == NULL)
3313                 return;
3314
3315         if (pll->refcount == 0) {
3316                 WARN(1, "bad %s refcount\n", pll->name);
3317                 return;
3318         }
3319
3320         if (--pll->refcount == 0) {
3321                 WARN_ON(pll->on);
3322                 WARN_ON(pll->active);
3323         }
3324
3325         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3326 }
3327
3328 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3329 {
3330         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3331         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3332         enum intel_dpll_id i;
3333
3334         if (pll) {
3335                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3336                               crtc->base.base.id, pll->name);
3337                 intel_put_shared_dpll(crtc);
3338         }
3339
3340         if (HAS_PCH_IBX(dev_priv->dev)) {
3341                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3342                 i = (enum intel_dpll_id) crtc->pipe;
3343                 pll = &dev_priv->shared_dplls[i];
3344
3345                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3346                               crtc->base.base.id, pll->name);
3347
3348                 goto found;
3349         }
3350
3351         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3352                 pll = &dev_priv->shared_dplls[i];
3353
3354                 /* Only want to check enabled timings first */
3355                 if (pll->refcount == 0)
3356                         continue;
3357
3358                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3359                            sizeof(pll->hw_state)) == 0) {
3360                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3361                                       crtc->base.base.id,
3362                                       pll->name, pll->refcount, pll->active);
3363
3364                         goto found;
3365                 }
3366         }
3367
3368         /* Ok no matching timings, maybe there's a free one? */
3369         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3370                 pll = &dev_priv->shared_dplls[i];
3371                 if (pll->refcount == 0) {
3372                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3373                                       crtc->base.base.id, pll->name);
3374                         goto found;
3375                 }
3376         }
3377
3378         return NULL;
3379
3380 found:
3381         crtc->config.shared_dpll = i;
3382         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3383                          pipe_name(crtc->pipe));
3384
3385         if (pll->active == 0) {
3386                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3387                        sizeof(pll->hw_state));
3388
3389                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3390                 WARN_ON(pll->on);
3391                 assert_shared_dpll_disabled(dev_priv, pll);
3392
3393                 pll->mode_set(dev_priv, pll);
3394         }
3395         pll->refcount++;
3396
3397         return pll;
3398 }
3399
3400 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3401 {
3402         struct drm_i915_private *dev_priv = dev->dev_private;
3403         int dslreg = PIPEDSL(pipe);
3404         u32 temp;
3405
3406         temp = I915_READ(dslreg);
3407         udelay(500);
3408         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3409                 if (wait_for(I915_READ(dslreg) != temp, 5))
3410                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3411         }
3412 }
3413
3414 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3415 {
3416         struct drm_device *dev = crtc->base.dev;
3417         struct drm_i915_private *dev_priv = dev->dev_private;
3418         int pipe = crtc->pipe;
3419
3420         if (crtc->config.pch_pfit.enabled) {
3421                 /* Force use of hard-coded filter coefficients
3422                  * as some pre-programmed values are broken,
3423                  * e.g. x201.
3424                  */
3425                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3426                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3427                                                  PF_PIPE_SEL_IVB(pipe));
3428                 else
3429                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3430                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3431                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3432         }
3433 }
3434
3435 static void intel_enable_planes(struct drm_crtc *crtc)
3436 {
3437         struct drm_device *dev = crtc->dev;
3438         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3439         struct intel_plane *intel_plane;
3440
3441         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3442                 if (intel_plane->pipe == pipe)
3443                         intel_plane_restore(&intel_plane->base);
3444 }
3445
3446 static void intel_disable_planes(struct drm_crtc *crtc)
3447 {
3448         struct drm_device *dev = crtc->dev;
3449         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3450         struct intel_plane *intel_plane;
3451
3452         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3453                 if (intel_plane->pipe == pipe)
3454                         intel_plane_disable(&intel_plane->base);
3455 }
3456
3457 void hsw_enable_ips(struct intel_crtc *crtc)
3458 {
3459         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3460
3461         if (!crtc->config.ips_enabled)
3462                 return;
3463
3464         /* We can only enable IPS after we enable a plane and wait for a vblank.
3465          * We guarantee that the plane is enabled by calling intel_enable_ips
3466          * only after intel_enable_plane. And intel_enable_plane already waits
3467          * for a vblank, so all we need to do here is to enable the IPS bit. */
3468         assert_plane_enabled(dev_priv, crtc->plane);
3469         if (IS_BROADWELL(crtc->base.dev)) {
3470                 mutex_lock(&dev_priv->rps.hw_lock);
3471                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3472                 mutex_unlock(&dev_priv->rps.hw_lock);
3473                 /* Quoting Art Runyan: "its not safe to expect any particular
3474                  * value in IPS_CTL bit 31 after enabling IPS through the
3475                  * mailbox." Moreover, the mailbox may return a bogus state,
3476                  * so we need to just enable it and continue on.
3477                  */
3478         } else {
3479                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3480                 /* The bit only becomes 1 in the next vblank, so this wait here
3481                  * is essentially intel_wait_for_vblank. If we don't have this
3482                  * and don't wait for vblanks until the end of crtc_enable, then
3483                  * the HW state readout code will complain that the expected
3484                  * IPS_CTL value is not the one we read. */
3485                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3486                         DRM_ERROR("Timed out waiting for IPS enable\n");
3487         }
3488 }
3489
3490 void hsw_disable_ips(struct intel_crtc *crtc)
3491 {
3492         struct drm_device *dev = crtc->base.dev;
3493         struct drm_i915_private *dev_priv = dev->dev_private;
3494
3495         if (!crtc->config.ips_enabled)
3496                 return;
3497
3498         assert_plane_enabled(dev_priv, crtc->plane);
3499         if (IS_BROADWELL(crtc->base.dev)) {
3500                 mutex_lock(&dev_priv->rps.hw_lock);
3501                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3502                 mutex_unlock(&dev_priv->rps.hw_lock);
3503         } else {
3504                 I915_WRITE(IPS_CTL, 0);
3505                 POSTING_READ(IPS_CTL);
3506         }
3507
3508         /* We need to wait for a vblank before we can disable the plane. */
3509         intel_wait_for_vblank(dev, crtc->pipe);
3510 }
3511
3512 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3513 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3514 {
3515         struct drm_device *dev = crtc->dev;
3516         struct drm_i915_private *dev_priv = dev->dev_private;
3517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3518         enum pipe pipe = intel_crtc->pipe;
3519         int palreg = PALETTE(pipe);
3520         int i;
3521         bool reenable_ips = false;
3522
3523         /* The clocks have to be on to load the palette. */
3524         if (!crtc->enabled || !intel_crtc->active)
3525                 return;
3526
3527         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3528                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3529                         assert_dsi_pll_enabled(dev_priv);
3530                 else
3531                         assert_pll_enabled(dev_priv, pipe);
3532         }
3533
3534         /* use legacy palette for Ironlake */
3535         if (HAS_PCH_SPLIT(dev))
3536                 palreg = LGC_PALETTE(pipe);
3537
3538         /* Workaround : Do not read or write the pipe palette/gamma data while
3539          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3540          */
3541         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3542             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3543              GAMMA_MODE_MODE_SPLIT)) {
3544                 hsw_disable_ips(intel_crtc);
3545                 reenable_ips = true;
3546         }
3547
3548         for (i = 0; i < 256; i++) {
3549                 I915_WRITE(palreg + 4 * i,
3550                            (intel_crtc->lut_r[i] << 16) |
3551                            (intel_crtc->lut_g[i] << 8) |
3552                            intel_crtc->lut_b[i]);
3553         }
3554
3555         if (reenable_ips)
3556                 hsw_enable_ips(intel_crtc);
3557 }
3558
3559 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3560 {
3561         struct drm_device *dev = crtc->dev;
3562         struct drm_i915_private *dev_priv = dev->dev_private;
3563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564         struct intel_encoder *encoder;
3565         int pipe = intel_crtc->pipe;
3566         int plane = intel_crtc->plane;
3567
3568         WARN_ON(!crtc->enabled);
3569
3570         if (intel_crtc->active)
3571                 return;
3572
3573         intel_crtc->active = true;
3574
3575         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3576         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3577
3578         for_each_encoder_on_crtc(dev, crtc, encoder)
3579                 if (encoder->pre_enable)
3580                         encoder->pre_enable(encoder);
3581
3582         if (intel_crtc->config.has_pch_encoder) {
3583                 /* Note: FDI PLL enabling _must_ be done before we enable the
3584                  * cpu pipes, hence this is separate from all the other fdi/pch
3585                  * enabling. */
3586                 ironlake_fdi_pll_enable(intel_crtc);
3587         } else {
3588                 assert_fdi_tx_disabled(dev_priv, pipe);
3589                 assert_fdi_rx_disabled(dev_priv, pipe);
3590         }
3591
3592         ironlake_pfit_enable(intel_crtc);
3593
3594         /*
3595          * On ILK+ LUT must be loaded before the pipe is running but with
3596          * clocks enabled
3597          */
3598         intel_crtc_load_lut(crtc);
3599
3600         intel_update_watermarks(crtc);
3601         intel_enable_pipe(intel_crtc, false, true);
3602         intel_enable_primary_plane(dev_priv, plane, pipe);
3603         intel_enable_planes(crtc);
3604         intel_crtc_update_cursor(crtc, true);
3605
3606         if (intel_crtc->config.has_pch_encoder)
3607                 ironlake_pch_enable(crtc);
3608
3609         mutex_lock(&dev->struct_mutex);
3610         intel_update_fbc(dev);
3611         mutex_unlock(&dev->struct_mutex);
3612
3613         for_each_encoder_on_crtc(dev, crtc, encoder)
3614                 encoder->enable(encoder);
3615
3616         if (HAS_PCH_CPT(dev))
3617                 cpt_verify_modeset(dev, intel_crtc->pipe);
3618
3619         /*
3620          * There seems to be a race in PCH platform hw (at least on some
3621          * outputs) where an enabled pipe still completes any pageflip right
3622          * away (as if the pipe is off) instead of waiting for vblank. As soon
3623          * as the first vblank happend, everything works as expected. Hence just
3624          * wait for one vblank before returning to avoid strange things
3625          * happening.
3626          */
3627         intel_wait_for_vblank(dev, intel_crtc->pipe);
3628 }
3629
3630 /* IPS only exists on ULT machines and is tied to pipe A. */
3631 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3632 {
3633         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3634 }
3635
3636 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3637 {
3638         struct drm_device *dev = crtc->dev;
3639         struct drm_i915_private *dev_priv = dev->dev_private;
3640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3641         int pipe = intel_crtc->pipe;
3642         int plane = intel_crtc->plane;
3643
3644         intel_enable_primary_plane(dev_priv, plane, pipe);
3645         intel_enable_planes(crtc);
3646         intel_crtc_update_cursor(crtc, true);
3647
3648         hsw_enable_ips(intel_crtc);
3649
3650         mutex_lock(&dev->struct_mutex);
3651         intel_update_fbc(dev);
3652         mutex_unlock(&dev->struct_mutex);
3653 }
3654
3655 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3656 {
3657         struct drm_device *dev = crtc->dev;
3658         struct drm_i915_private *dev_priv = dev->dev_private;
3659         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3660         int pipe = intel_crtc->pipe;
3661         int plane = intel_crtc->plane;
3662
3663         intel_crtc_wait_for_pending_flips(crtc);
3664         drm_vblank_off(dev, pipe);
3665
3666         /* FBC must be disabled before disabling the plane on HSW. */
3667         if (dev_priv->fbc.plane == plane)
3668                 intel_disable_fbc(dev);
3669
3670         hsw_disable_ips(intel_crtc);
3671
3672         intel_crtc_update_cursor(crtc, false);
3673         intel_disable_planes(crtc);
3674         intel_disable_primary_plane(dev_priv, plane, pipe);
3675 }
3676
3677 /*
3678  * This implements the workaround described in the "notes" section of the mode
3679  * set sequence documentation. When going from no pipes or single pipe to
3680  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3681  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3682  */
3683 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3684 {
3685         struct drm_device *dev = crtc->base.dev;
3686         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3687
3688         /* We want to get the other_active_crtc only if there's only 1 other
3689          * active crtc. */
3690         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3691                 if (!crtc_it->active || crtc_it == crtc)
3692                         continue;
3693
3694                 if (other_active_crtc)
3695                         return;
3696
3697                 other_active_crtc = crtc_it;
3698         }
3699         if (!other_active_crtc)
3700                 return;
3701
3702         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3703         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3704 }
3705
3706 static void haswell_crtc_enable(struct drm_crtc *crtc)
3707 {
3708         struct drm_device *dev = crtc->dev;
3709         struct drm_i915_private *dev_priv = dev->dev_private;
3710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3711         struct intel_encoder *encoder;
3712         int pipe = intel_crtc->pipe;
3713
3714         WARN_ON(!crtc->enabled);
3715
3716         if (intel_crtc->active)
3717                 return;
3718
3719         intel_crtc->active = true;
3720
3721         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3722         if (intel_crtc->config.has_pch_encoder)
3723                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3724
3725         if (intel_crtc->config.has_pch_encoder)
3726                 dev_priv->display.fdi_link_train(crtc);
3727
3728         for_each_encoder_on_crtc(dev, crtc, encoder)
3729                 if (encoder->pre_enable)
3730                         encoder->pre_enable(encoder);
3731
3732         intel_ddi_enable_pipe_clock(intel_crtc);
3733
3734         ironlake_pfit_enable(intel_crtc);
3735
3736         /*
3737          * On ILK+ LUT must be loaded before the pipe is running but with
3738          * clocks enabled
3739          */
3740         intel_crtc_load_lut(crtc);
3741
3742         intel_ddi_set_pipe_settings(crtc);
3743         intel_ddi_enable_transcoder_func(crtc);
3744
3745         intel_update_watermarks(crtc);
3746         intel_enable_pipe(intel_crtc, false, false);
3747
3748         if (intel_crtc->config.has_pch_encoder)
3749                 lpt_pch_enable(crtc);
3750
3751         for_each_encoder_on_crtc(dev, crtc, encoder) {
3752                 encoder->enable(encoder);
3753                 intel_opregion_notify_encoder(encoder, true);
3754         }
3755
3756         /* If we change the relative order between pipe/planes enabling, we need
3757          * to change the workaround. */
3758         haswell_mode_set_planes_workaround(intel_crtc);
3759         haswell_crtc_enable_planes(crtc);
3760 }
3761
3762 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3763 {
3764         struct drm_device *dev = crtc->base.dev;
3765         struct drm_i915_private *dev_priv = dev->dev_private;
3766         int pipe = crtc->pipe;
3767
3768         /* To avoid upsetting the power well on haswell only disable the pfit if
3769          * it's in use. The hw state code will make sure we get this right. */
3770         if (crtc->config.pch_pfit.enabled) {
3771                 I915_WRITE(PF_CTL(pipe), 0);
3772                 I915_WRITE(PF_WIN_POS(pipe), 0);
3773                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3774         }
3775 }
3776
3777 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3778 {
3779         struct drm_device *dev = crtc->dev;
3780         struct drm_i915_private *dev_priv = dev->dev_private;
3781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3782         struct intel_encoder *encoder;
3783         int pipe = intel_crtc->pipe;
3784         int plane = intel_crtc->plane;
3785         u32 reg, temp;
3786
3787
3788         if (!intel_crtc->active)
3789                 return;
3790
3791         for_each_encoder_on_crtc(dev, crtc, encoder)
3792                 encoder->disable(encoder);
3793
3794         intel_crtc_wait_for_pending_flips(crtc);
3795         drm_vblank_off(dev, pipe);
3796
3797         if (dev_priv->fbc.plane == plane)
3798                 intel_disable_fbc(dev);
3799
3800         intel_crtc_update_cursor(crtc, false);
3801         intel_disable_planes(crtc);
3802         intel_disable_primary_plane(dev_priv, plane, pipe);
3803
3804         if (intel_crtc->config.has_pch_encoder)
3805                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3806
3807         intel_disable_pipe(dev_priv, pipe);
3808
3809         ironlake_pfit_disable(intel_crtc);
3810
3811         for_each_encoder_on_crtc(dev, crtc, encoder)
3812                 if (encoder->post_disable)
3813                         encoder->post_disable(encoder);
3814
3815         if (intel_crtc->config.has_pch_encoder) {
3816                 ironlake_fdi_disable(crtc);
3817
3818                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3819                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3820
3821                 if (HAS_PCH_CPT(dev)) {
3822                         /* disable TRANS_DP_CTL */
3823                         reg = TRANS_DP_CTL(pipe);
3824                         temp = I915_READ(reg);
3825                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3826                                   TRANS_DP_PORT_SEL_MASK);
3827                         temp |= TRANS_DP_PORT_SEL_NONE;
3828                         I915_WRITE(reg, temp);
3829
3830                         /* disable DPLL_SEL */
3831                         temp = I915_READ(PCH_DPLL_SEL);
3832                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3833                         I915_WRITE(PCH_DPLL_SEL, temp);
3834                 }
3835
3836                 /* disable PCH DPLL */
3837                 intel_disable_shared_dpll(intel_crtc);
3838
3839                 ironlake_fdi_pll_disable(intel_crtc);
3840         }
3841
3842         intel_crtc->active = false;
3843         intel_update_watermarks(crtc);
3844
3845         mutex_lock(&dev->struct_mutex);
3846         intel_update_fbc(dev);
3847         mutex_unlock(&dev->struct_mutex);
3848 }
3849
3850 static void haswell_crtc_disable(struct drm_crtc *crtc)
3851 {
3852         struct drm_device *dev = crtc->dev;
3853         struct drm_i915_private *dev_priv = dev->dev_private;
3854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3855         struct intel_encoder *encoder;
3856         int pipe = intel_crtc->pipe;
3857         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3858
3859         if (!intel_crtc->active)
3860                 return;
3861
3862         haswell_crtc_disable_planes(crtc);
3863
3864         for_each_encoder_on_crtc(dev, crtc, encoder) {
3865                 intel_opregion_notify_encoder(encoder, false);
3866                 encoder->disable(encoder);
3867         }
3868
3869         if (intel_crtc->config.has_pch_encoder)
3870                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3871         intel_disable_pipe(dev_priv, pipe);
3872
3873         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3874
3875         ironlake_pfit_disable(intel_crtc);
3876
3877         intel_ddi_disable_pipe_clock(intel_crtc);
3878
3879         for_each_encoder_on_crtc(dev, crtc, encoder)
3880                 if (encoder->post_disable)
3881                         encoder->post_disable(encoder);
3882
3883         if (intel_crtc->config.has_pch_encoder) {
3884                 lpt_disable_pch_transcoder(dev_priv);
3885                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3886                 intel_ddi_fdi_disable(crtc);
3887         }
3888
3889         intel_crtc->active = false;
3890         intel_update_watermarks(crtc);
3891
3892         mutex_lock(&dev->struct_mutex);
3893         intel_update_fbc(dev);
3894         mutex_unlock(&dev->struct_mutex);
3895 }
3896
3897 static void ironlake_crtc_off(struct drm_crtc *crtc)
3898 {
3899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3900         intel_put_shared_dpll(intel_crtc);
3901 }
3902
3903 static void haswell_crtc_off(struct drm_crtc *crtc)
3904 {
3905         intel_ddi_put_crtc_pll(crtc);
3906 }
3907
3908 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3909 {
3910         if (!enable && intel_crtc->overlay) {
3911                 struct drm_device *dev = intel_crtc->base.dev;
3912                 struct drm_i915_private *dev_priv = dev->dev_private;
3913
3914                 mutex_lock(&dev->struct_mutex);
3915                 dev_priv->mm.interruptible = false;
3916                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3917                 dev_priv->mm.interruptible = true;
3918                 mutex_unlock(&dev->struct_mutex);
3919         }
3920
3921         /* Let userspace switch the overlay on again. In most cases userspace
3922          * has to recompute where to put it anyway.
3923          */
3924 }
3925
3926 /**
3927  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3928  * cursor plane briefly if not already running after enabling the display
3929  * plane.
3930  * This workaround avoids occasional blank screens when self refresh is
3931  * enabled.
3932  */
3933 static void
3934 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3935 {
3936         u32 cntl = I915_READ(CURCNTR(pipe));
3937
3938         if ((cntl & CURSOR_MODE) == 0) {
3939                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3940
3941                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3942                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3943                 intel_wait_for_vblank(dev_priv->dev, pipe);
3944                 I915_WRITE(CURCNTR(pipe), cntl);
3945                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3946                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3947         }
3948 }
3949
3950 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3951 {
3952         struct drm_device *dev = crtc->base.dev;
3953         struct drm_i915_private *dev_priv = dev->dev_private;
3954         struct intel_crtc_config *pipe_config = &crtc->config;
3955
3956         if (!crtc->config.gmch_pfit.control)
3957                 return;
3958
3959         /*
3960          * The panel fitter should only be adjusted whilst the pipe is disabled,
3961          * according to register description and PRM.
3962          */
3963         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3964         assert_pipe_disabled(dev_priv, crtc->pipe);
3965
3966         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3967         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3968
3969         /* Border color in case we don't scale up to the full screen. Black by
3970          * default, change to something else for debugging. */
3971         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3972 }
3973
3974 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3975 {
3976         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3977
3978         /* Obtain SKU information */
3979         mutex_lock(&dev_priv->dpio_lock);
3980         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3981                 CCK_FUSE_HPLL_FREQ_MASK;
3982         mutex_unlock(&dev_priv->dpio_lock);
3983
3984         return vco_freq[hpll_freq];
3985 }
3986
3987 /* Adjust CDclk dividers to allow high res or save power if possible */
3988 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3989 {
3990         struct drm_i915_private *dev_priv = dev->dev_private;
3991         u32 val, cmd;
3992
3993         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3994                 cmd = 2;
3995         else if (cdclk == 266)
3996                 cmd = 1;
3997         else
3998                 cmd = 0;
3999
4000         mutex_lock(&dev_priv->rps.hw_lock);
4001         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4002         val &= ~DSPFREQGUAR_MASK;
4003         val |= (cmd << DSPFREQGUAR_SHIFT);
4004         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4005         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4006                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4007                      50)) {
4008                 DRM_ERROR("timed out waiting for CDclk change\n");
4009         }
4010         mutex_unlock(&dev_priv->rps.hw_lock);
4011
4012         if (cdclk == 400) {
4013                 u32 divider, vco;
4014
4015                 vco = valleyview_get_vco(dev_priv);
4016                 divider = ((vco << 1) / cdclk) - 1;
4017
4018                 mutex_lock(&dev_priv->dpio_lock);
4019                 /* adjust cdclk divider */
4020                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4021                 val &= ~0xf;
4022                 val |= divider;
4023                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4024                 mutex_unlock(&dev_priv->dpio_lock);
4025         }
4026
4027         mutex_lock(&dev_priv->dpio_lock);
4028         /* adjust self-refresh exit latency value */
4029         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4030         val &= ~0x7f;
4031
4032         /*
4033          * For high bandwidth configs, we set a higher latency in the bunit
4034          * so that the core display fetch happens in time to avoid underruns.
4035          */
4036         if (cdclk == 400)
4037                 val |= 4500 / 250; /* 4.5 usec */
4038         else
4039                 val |= 3000 / 250; /* 3.0 usec */
4040         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4041         mutex_unlock(&dev_priv->dpio_lock);
4042
4043         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4044         intel_i2c_reset(dev);
4045 }
4046
4047 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4048 {
4049         int cur_cdclk, vco;
4050         int divider;
4051
4052         vco = valleyview_get_vco(dev_priv);
4053
4054         mutex_lock(&dev_priv->dpio_lock);
4055         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4056         mutex_unlock(&dev_priv->dpio_lock);
4057
4058         divider &= 0xf;
4059
4060         cur_cdclk = (vco << 1) / (divider + 1);
4061
4062         return cur_cdclk;
4063 }
4064
4065 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4066                                  int max_pixclk)
4067 {
4068         int cur_cdclk;
4069
4070         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4071
4072         /*
4073          * Really only a few cases to deal with, as only 4 CDclks are supported:
4074          *   200MHz
4075          *   267MHz
4076          *   320MHz
4077          *   400MHz
4078          * So we check to see whether we're above 90% of the lower bin and
4079          * adjust if needed.
4080          */
4081         if (max_pixclk > 288000) {
4082                 return 400;
4083         } else if (max_pixclk > 240000) {
4084                 return 320;
4085         } else
4086                 return 266;
4087         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4088 }
4089
4090 /* compute the max pixel clock for new configuration */
4091 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4092 {
4093         struct drm_device *dev = dev_priv->dev;
4094         struct intel_crtc *intel_crtc;
4095         int max_pixclk = 0;
4096
4097         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4098                             base.head) {
4099                 if (intel_crtc->new_enabled)
4100                         max_pixclk = max(max_pixclk,
4101                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4102         }
4103
4104         return max_pixclk;
4105 }
4106
4107 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4108                                             unsigned *prepare_pipes)
4109 {
4110         struct drm_i915_private *dev_priv = dev->dev_private;
4111         struct intel_crtc *intel_crtc;
4112         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4113         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4114
4115         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4116                 return;
4117
4118         /* disable/enable all currently active pipes while we change cdclk */
4119         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4120                             base.head)
4121                 if (intel_crtc->base.enabled)
4122                         *prepare_pipes |= (1 << intel_crtc->pipe);
4123 }
4124
4125 static void valleyview_modeset_global_resources(struct drm_device *dev)
4126 {
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4129         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4130         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4131
4132         if (req_cdclk != cur_cdclk)
4133                 valleyview_set_cdclk(dev, req_cdclk);
4134 }
4135
4136 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4137 {
4138         struct drm_device *dev = crtc->dev;
4139         struct drm_i915_private *dev_priv = dev->dev_private;
4140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4141         struct intel_encoder *encoder;
4142         int pipe = intel_crtc->pipe;
4143         int plane = intel_crtc->plane;
4144         bool is_dsi;
4145
4146         WARN_ON(!crtc->enabled);
4147
4148         if (intel_crtc->active)
4149                 return;
4150
4151         intel_crtc->active = true;
4152
4153         for_each_encoder_on_crtc(dev, crtc, encoder)
4154                 if (encoder->pre_pll_enable)
4155                         encoder->pre_pll_enable(encoder);
4156
4157         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4158
4159         if (!is_dsi)
4160                 vlv_enable_pll(intel_crtc);
4161
4162         for_each_encoder_on_crtc(dev, crtc, encoder)
4163                 if (encoder->pre_enable)
4164                         encoder->pre_enable(encoder);
4165
4166         i9xx_pfit_enable(intel_crtc);
4167
4168         intel_crtc_load_lut(crtc);
4169
4170         intel_update_watermarks(crtc);
4171         intel_enable_pipe(intel_crtc, is_dsi, true);
4172         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4173         intel_enable_primary_plane(dev_priv, plane, pipe);
4174         intel_enable_planes(crtc);
4175         intel_crtc_update_cursor(crtc, true);
4176
4177         intel_update_fbc(dev);
4178
4179         for_each_encoder_on_crtc(dev, crtc, encoder)
4180                 encoder->enable(encoder);
4181 }
4182
4183 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4184 {
4185         struct drm_device *dev = crtc->dev;
4186         struct drm_i915_private *dev_priv = dev->dev_private;
4187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4188         struct intel_encoder *encoder;
4189         int pipe = intel_crtc->pipe;
4190         int plane = intel_crtc->plane;
4191
4192         WARN_ON(!crtc->enabled);
4193
4194         if (intel_crtc->active)
4195                 return;
4196
4197         intel_crtc->active = true;
4198
4199         for_each_encoder_on_crtc(dev, crtc, encoder)
4200                 if (encoder->pre_enable)
4201                         encoder->pre_enable(encoder);
4202
4203         i9xx_enable_pll(intel_crtc);
4204
4205         i9xx_pfit_enable(intel_crtc);
4206
4207         intel_crtc_load_lut(crtc);
4208
4209         intel_update_watermarks(crtc);
4210         intel_enable_pipe(intel_crtc, false, true);
4211         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4212         intel_enable_primary_plane(dev_priv, plane, pipe);
4213         intel_enable_planes(crtc);
4214         /* The fixup needs to happen before cursor is enabled */
4215         if (IS_G4X(dev))
4216                 g4x_fixup_plane(dev_priv, pipe);
4217         intel_crtc_update_cursor(crtc, true);
4218
4219         /* Give the overlay scaler a chance to enable if it's on this pipe */
4220         intel_crtc_dpms_overlay(intel_crtc, true);
4221
4222         intel_update_fbc(dev);
4223
4224         for_each_encoder_on_crtc(dev, crtc, encoder)
4225                 encoder->enable(encoder);
4226 }
4227
4228 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4229 {
4230         struct drm_device *dev = crtc->base.dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232
4233         if (!crtc->config.gmch_pfit.control)
4234                 return;
4235
4236         assert_pipe_disabled(dev_priv, crtc->pipe);
4237
4238         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4239                          I915_READ(PFIT_CONTROL));
4240         I915_WRITE(PFIT_CONTROL, 0);
4241 }
4242
4243 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4244 {
4245         struct drm_device *dev = crtc->dev;
4246         struct drm_i915_private *dev_priv = dev->dev_private;
4247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4248         struct intel_encoder *encoder;
4249         int pipe = intel_crtc->pipe;
4250         int plane = intel_crtc->plane;
4251
4252         if (!intel_crtc->active)
4253                 return;
4254
4255         for_each_encoder_on_crtc(dev, crtc, encoder)
4256                 encoder->disable(encoder);
4257
4258         /* Give the overlay scaler a chance to disable if it's on this pipe */
4259         intel_crtc_wait_for_pending_flips(crtc);
4260         drm_vblank_off(dev, pipe);
4261
4262         if (dev_priv->fbc.plane == plane)
4263                 intel_disable_fbc(dev);
4264
4265         intel_crtc_dpms_overlay(intel_crtc, false);
4266         intel_crtc_update_cursor(crtc, false);
4267         intel_disable_planes(crtc);
4268         intel_disable_primary_plane(dev_priv, plane, pipe);
4269
4270         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4271         intel_disable_pipe(dev_priv, pipe);
4272
4273         i9xx_pfit_disable(intel_crtc);
4274
4275         for_each_encoder_on_crtc(dev, crtc, encoder)
4276                 if (encoder->post_disable)
4277                         encoder->post_disable(encoder);
4278
4279         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4280                 vlv_disable_pll(dev_priv, pipe);
4281         else if (!IS_VALLEYVIEW(dev))
4282                 i9xx_disable_pll(dev_priv, pipe);
4283
4284         intel_crtc->active = false;
4285         intel_update_watermarks(crtc);
4286
4287         intel_update_fbc(dev);
4288 }
4289
4290 static void i9xx_crtc_off(struct drm_crtc *crtc)
4291 {
4292 }
4293
4294 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4295                                     bool enabled)
4296 {
4297         struct drm_device *dev = crtc->dev;
4298         struct drm_i915_master_private *master_priv;
4299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4300         int pipe = intel_crtc->pipe;
4301
4302         if (!dev->primary->master)
4303                 return;
4304
4305         master_priv = dev->primary->master->driver_priv;
4306         if (!master_priv->sarea_priv)
4307                 return;
4308
4309         switch (pipe) {
4310         case 0:
4311                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4312                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4313                 break;
4314         case 1:
4315                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4316                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4317                 break;
4318         default:
4319                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4320                 break;
4321         }
4322 }
4323
4324 /**
4325  * Sets the power management mode of the pipe and plane.
4326  */
4327 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4328 {
4329         struct drm_device *dev = crtc->dev;
4330         struct drm_i915_private *dev_priv = dev->dev_private;
4331         struct intel_encoder *intel_encoder;
4332         bool enable = false;
4333
4334         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4335                 enable |= intel_encoder->connectors_active;
4336
4337         if (enable)
4338                 dev_priv->display.crtc_enable(crtc);
4339         else
4340                 dev_priv->display.crtc_disable(crtc);
4341
4342         intel_crtc_update_sarea(crtc, enable);
4343 }
4344
4345 static void intel_crtc_disable(struct drm_crtc *crtc)
4346 {
4347         struct drm_device *dev = crtc->dev;
4348         struct drm_connector *connector;
4349         struct drm_i915_private *dev_priv = dev->dev_private;
4350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4351
4352         /* crtc should still be enabled when we disable it. */
4353         WARN_ON(!crtc->enabled);
4354
4355         dev_priv->display.crtc_disable(crtc);
4356         intel_crtc->eld_vld = false;
4357         intel_crtc_update_sarea(crtc, false);
4358         dev_priv->display.off(crtc);
4359
4360         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4361         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4362         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4363
4364         if (crtc->fb) {
4365                 mutex_lock(&dev->struct_mutex);
4366                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4367                 mutex_unlock(&dev->struct_mutex);
4368                 crtc->fb = NULL;
4369         }
4370
4371         /* Update computed state. */
4372         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4373                 if (!connector->encoder || !connector->encoder->crtc)
4374                         continue;
4375
4376                 if (connector->encoder->crtc != crtc)
4377                         continue;
4378
4379                 connector->dpms = DRM_MODE_DPMS_OFF;
4380                 to_intel_encoder(connector->encoder)->connectors_active = false;
4381         }
4382 }
4383
4384 void intel_encoder_destroy(struct drm_encoder *encoder)
4385 {
4386         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4387
4388         drm_encoder_cleanup(encoder);
4389         kfree(intel_encoder);
4390 }
4391
4392 /* Simple dpms helper for encoders with just one connector, no cloning and only
4393  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4394  * state of the entire output pipe. */
4395 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4396 {
4397         if (mode == DRM_MODE_DPMS_ON) {
4398                 encoder->connectors_active = true;
4399
4400                 intel_crtc_update_dpms(encoder->base.crtc);
4401         } else {
4402                 encoder->connectors_active = false;
4403
4404                 intel_crtc_update_dpms(encoder->base.crtc);
4405         }
4406 }
4407
4408 /* Cross check the actual hw state with our own modeset state tracking (and it's
4409  * internal consistency). */
4410 static void intel_connector_check_state(struct intel_connector *connector)
4411 {
4412         if (connector->get_hw_state(connector)) {
4413                 struct intel_encoder *encoder = connector->encoder;
4414                 struct drm_crtc *crtc;
4415                 bool encoder_enabled;
4416                 enum pipe pipe;
4417
4418                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4419                               connector->base.base.id,
4420                               drm_get_connector_name(&connector->base));
4421
4422                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4423                      "wrong connector dpms state\n");
4424                 WARN(connector->base.encoder != &encoder->base,
4425                      "active connector not linked to encoder\n");
4426                 WARN(!encoder->connectors_active,
4427                      "encoder->connectors_active not set\n");
4428
4429                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4430                 WARN(!encoder_enabled, "encoder not enabled\n");
4431                 if (WARN_ON(!encoder->base.crtc))
4432                         return;
4433
4434                 crtc = encoder->base.crtc;
4435
4436                 WARN(!crtc->enabled, "crtc not enabled\n");
4437                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4438                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4439                      "encoder active on the wrong pipe\n");
4440         }
4441 }
4442
4443 /* Even simpler default implementation, if there's really no special case to
4444  * consider. */
4445 void intel_connector_dpms(struct drm_connector *connector, int mode)
4446 {
4447         /* All the simple cases only support two dpms states. */
4448         if (mode != DRM_MODE_DPMS_ON)
4449                 mode = DRM_MODE_DPMS_OFF;
4450
4451         if (mode == connector->dpms)
4452                 return;
4453
4454         connector->dpms = mode;
4455
4456         /* Only need to change hw state when actually enabled */
4457         if (connector->encoder)
4458                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4459
4460         intel_modeset_check_state(connector->dev);
4461 }
4462
4463 /* Simple connector->get_hw_state implementation for encoders that support only
4464  * one connector and no cloning and hence the encoder state determines the state
4465  * of the connector. */
4466 bool intel_connector_get_hw_state(struct intel_connector *connector)
4467 {
4468         enum pipe pipe = 0;
4469         struct intel_encoder *encoder = connector->encoder;
4470
4471         return encoder->get_hw_state(encoder, &pipe);
4472 }
4473
4474 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4475                                      struct intel_crtc_config *pipe_config)
4476 {
4477         struct drm_i915_private *dev_priv = dev->dev_private;
4478         struct intel_crtc *pipe_B_crtc =
4479                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4480
4481         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4482                       pipe_name(pipe), pipe_config->fdi_lanes);
4483         if (pipe_config->fdi_lanes > 4) {
4484                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4485                               pipe_name(pipe), pipe_config->fdi_lanes);
4486                 return false;
4487         }
4488
4489         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4490                 if (pipe_config->fdi_lanes > 2) {
4491                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4492                                       pipe_config->fdi_lanes);
4493                         return false;
4494                 } else {
4495                         return true;
4496                 }
4497         }
4498
4499         if (INTEL_INFO(dev)->num_pipes == 2)
4500                 return true;
4501
4502         /* Ivybridge 3 pipe is really complicated */
4503         switch (pipe) {
4504         case PIPE_A:
4505                 return true;
4506         case PIPE_B:
4507                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4508                     pipe_config->fdi_lanes > 2) {
4509                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4510                                       pipe_name(pipe), pipe_config->fdi_lanes);
4511                         return false;
4512                 }
4513                 return true;
4514         case PIPE_C:
4515                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4516                     pipe_B_crtc->config.fdi_lanes <= 2) {
4517                         if (pipe_config->fdi_lanes > 2) {
4518                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4519                                               pipe_name(pipe), pipe_config->fdi_lanes);
4520                                 return false;
4521                         }
4522                 } else {
4523                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4524                         return false;
4525                 }
4526                 return true;
4527         default:
4528                 BUG();
4529         }
4530 }
4531
4532 #define RETRY 1
4533 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4534                                        struct intel_crtc_config *pipe_config)
4535 {
4536         struct drm_device *dev = intel_crtc->base.dev;
4537         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4538         int lane, link_bw, fdi_dotclock;
4539         bool setup_ok, needs_recompute = false;
4540
4541 retry:
4542         /* FDI is a binary signal running at ~2.7GHz, encoding
4543          * each output octet as 10 bits. The actual frequency
4544          * is stored as a divider into a 100MHz clock, and the
4545          * mode pixel clock is stored in units of 1KHz.
4546          * Hence the bw of each lane in terms of the mode signal
4547          * is:
4548          */
4549         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4550
4551         fdi_dotclock = adjusted_mode->crtc_clock;
4552
4553         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4554                                            pipe_config->pipe_bpp);
4555
4556         pipe_config->fdi_lanes = lane;
4557
4558         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4559                                link_bw, &pipe_config->fdi_m_n);
4560
4561         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4562                                             intel_crtc->pipe, pipe_config);
4563         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4564                 pipe_config->pipe_bpp -= 2*3;
4565                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4566                               pipe_config->pipe_bpp);
4567                 needs_recompute = true;
4568                 pipe_config->bw_constrained = true;
4569
4570                 goto retry;
4571         }
4572
4573         if (needs_recompute)
4574                 return RETRY;
4575
4576         return setup_ok ? 0 : -EINVAL;
4577 }
4578
4579 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4580                                    struct intel_crtc_config *pipe_config)
4581 {
4582         pipe_config->ips_enabled = i915.enable_ips &&
4583                                    hsw_crtc_supports_ips(crtc) &&
4584                                    pipe_config->pipe_bpp <= 24;
4585 }
4586
4587 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4588                                      struct intel_crtc_config *pipe_config)
4589 {
4590         struct drm_device *dev = crtc->base.dev;
4591         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4592
4593         /* FIXME should check pixel clock limits on all platforms */
4594         if (INTEL_INFO(dev)->gen < 4) {
4595                 struct drm_i915_private *dev_priv = dev->dev_private;
4596                 int clock_limit =
4597                         dev_priv->display.get_display_clock_speed(dev);
4598
4599                 /*
4600                  * Enable pixel doubling when the dot clock
4601                  * is > 90% of the (display) core speed.
4602                  *
4603                  * GDG double wide on either pipe,
4604                  * otherwise pipe A only.
4605                  */
4606                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4607                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4608                         clock_limit *= 2;
4609                         pipe_config->double_wide = true;
4610                 }
4611
4612                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4613                         return -EINVAL;
4614         }
4615
4616         /*
4617          * Pipe horizontal size must be even in:
4618          * - DVO ganged mode
4619          * - LVDS dual channel mode
4620          * - Double wide pipe
4621          */
4622         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4623              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4624                 pipe_config->pipe_src_w &= ~1;
4625
4626         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4627          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4628          */
4629         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4630                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4631                 return -EINVAL;
4632
4633         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4634                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4635         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4636                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4637                  * for lvds. */
4638                 pipe_config->pipe_bpp = 8*3;
4639         }
4640
4641         if (HAS_IPS(dev))
4642                 hsw_compute_ips_config(crtc, pipe_config);
4643
4644         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4645          * clock survives for now. */
4646         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4647                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4648
4649         if (pipe_config->has_pch_encoder)
4650                 return ironlake_fdi_compute_config(crtc, pipe_config);
4651
4652         return 0;
4653 }
4654
4655 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4656 {
4657         return 400000; /* FIXME */
4658 }
4659
4660 static int i945_get_display_clock_speed(struct drm_device *dev)
4661 {
4662         return 400000;
4663 }
4664
4665 static int i915_get_display_clock_speed(struct drm_device *dev)
4666 {
4667         return 333000;
4668 }
4669
4670 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4671 {
4672         return 200000;
4673 }
4674
4675 static int pnv_get_display_clock_speed(struct drm_device *dev)
4676 {
4677         u16 gcfgc = 0;
4678
4679         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4680
4681         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4682         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4683                 return 267000;
4684         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4685                 return 333000;
4686         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4687                 return 444000;
4688         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4689                 return 200000;
4690         default:
4691                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4692         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4693                 return 133000;
4694         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4695                 return 167000;
4696         }
4697 }
4698
4699 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4700 {
4701         u16 gcfgc = 0;
4702
4703         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4704
4705         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4706                 return 133000;
4707         else {
4708                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4709                 case GC_DISPLAY_CLOCK_333_MHZ:
4710                         return 333000;
4711                 default:
4712                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4713                         return 190000;
4714                 }
4715         }
4716 }
4717
4718 static int i865_get_display_clock_speed(struct drm_device *dev)
4719 {
4720         return 266000;
4721 }
4722
4723 static int i855_get_display_clock_speed(struct drm_device *dev)
4724 {
4725         u16 hpllcc = 0;
4726         /* Assume that the hardware is in the high speed state.  This
4727          * should be the default.
4728          */
4729         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4730         case GC_CLOCK_133_200:
4731         case GC_CLOCK_100_200:
4732                 return 200000;
4733         case GC_CLOCK_166_250:
4734                 return 250000;
4735         case GC_CLOCK_100_133:
4736                 return 133000;
4737         }
4738
4739         /* Shouldn't happen */
4740         return 0;
4741 }
4742
4743 static int i830_get_display_clock_speed(struct drm_device *dev)
4744 {
4745         return 133000;
4746 }
4747
4748 static void
4749 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4750 {
4751         while (*num > DATA_LINK_M_N_MASK ||
4752                *den > DATA_LINK_M_N_MASK) {
4753                 *num >>= 1;
4754                 *den >>= 1;
4755         }
4756 }
4757
4758 static void compute_m_n(unsigned int m, unsigned int n,
4759                         uint32_t *ret_m, uint32_t *ret_n)
4760 {
4761         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4762         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4763         intel_reduce_m_n_ratio(ret_m, ret_n);
4764 }
4765
4766 void
4767 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4768                        int pixel_clock, int link_clock,
4769                        struct intel_link_m_n *m_n)
4770 {
4771         m_n->tu = 64;
4772
4773         compute_m_n(bits_per_pixel * pixel_clock,
4774                     link_clock * nlanes * 8,
4775                     &m_n->gmch_m, &m_n->gmch_n);
4776
4777         compute_m_n(pixel_clock, link_clock,
4778                     &m_n->link_m, &m_n->link_n);
4779 }
4780
4781 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4782 {
4783         if (i915.panel_use_ssc >= 0)
4784                 return i915.panel_use_ssc != 0;
4785         return dev_priv->vbt.lvds_use_ssc
4786                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4787 }
4788
4789 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4790 {
4791         struct drm_device *dev = crtc->dev;
4792         struct drm_i915_private *dev_priv = dev->dev_private;
4793         int refclk;
4794
4795         if (IS_VALLEYVIEW(dev)) {
4796                 refclk = 100000;
4797         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4798             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4799                 refclk = dev_priv->vbt.lvds_ssc_freq;
4800                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4801         } else if (!IS_GEN2(dev)) {
4802                 refclk = 96000;
4803         } else {
4804                 refclk = 48000;
4805         }
4806
4807         return refclk;
4808 }
4809
4810 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4811 {
4812         return (1 << dpll->n) << 16 | dpll->m2;
4813 }
4814
4815 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4816 {
4817         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4818 }
4819
4820 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4821                                      intel_clock_t *reduced_clock)
4822 {
4823         struct drm_device *dev = crtc->base.dev;
4824         struct drm_i915_private *dev_priv = dev->dev_private;
4825         int pipe = crtc->pipe;
4826         u32 fp, fp2 = 0;
4827
4828         if (IS_PINEVIEW(dev)) {
4829                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4830                 if (reduced_clock)
4831                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4832         } else {
4833                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4834                 if (reduced_clock)
4835                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4836         }
4837
4838         I915_WRITE(FP0(pipe), fp);
4839         crtc->config.dpll_hw_state.fp0 = fp;
4840
4841         crtc->lowfreq_avail = false;
4842         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4843             reduced_clock && i915.powersave) {
4844                 I915_WRITE(FP1(pipe), fp2);
4845                 crtc->config.dpll_hw_state.fp1 = fp2;
4846                 crtc->lowfreq_avail = true;
4847         } else {
4848                 I915_WRITE(FP1(pipe), fp);
4849                 crtc->config.dpll_hw_state.fp1 = fp;
4850         }
4851 }
4852
4853 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4854                 pipe)
4855 {
4856         u32 reg_val;
4857
4858         /*
4859          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4860          * and set it to a reasonable value instead.
4861          */
4862         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4863         reg_val &= 0xffffff00;
4864         reg_val |= 0x00000030;
4865         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4866
4867         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4868         reg_val &= 0x8cffffff;
4869         reg_val = 0x8c000000;
4870         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4871
4872         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4873         reg_val &= 0xffffff00;
4874         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4875
4876         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4877         reg_val &= 0x00ffffff;
4878         reg_val |= 0xb0000000;
4879         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4880 }
4881
4882 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4883                                          struct intel_link_m_n *m_n)
4884 {
4885         struct drm_device *dev = crtc->base.dev;
4886         struct drm_i915_private *dev_priv = dev->dev_private;
4887         int pipe = crtc->pipe;
4888
4889         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4890         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4891         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4892         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4893 }
4894
4895 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4896                                          struct intel_link_m_n *m_n)
4897 {
4898         struct drm_device *dev = crtc->base.dev;
4899         struct drm_i915_private *dev_priv = dev->dev_private;
4900         int pipe = crtc->pipe;
4901         enum transcoder transcoder = crtc->config.cpu_transcoder;
4902
4903         if (INTEL_INFO(dev)->gen >= 5) {
4904                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4905                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4906                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4907                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4908         } else {
4909                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4910                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4911                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4912                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4913         }
4914 }
4915
4916 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4917 {
4918         if (crtc->config.has_pch_encoder)
4919                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4920         else
4921                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4922 }
4923
4924 static void vlv_update_pll(struct intel_crtc *crtc)
4925 {
4926         struct drm_device *dev = crtc->base.dev;
4927         struct drm_i915_private *dev_priv = dev->dev_private;
4928         int pipe = crtc->pipe;
4929         u32 dpll, mdiv;
4930         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4931         u32 coreclk, reg_val, dpll_md;
4932
4933         mutex_lock(&dev_priv->dpio_lock);
4934
4935         bestn = crtc->config.dpll.n;
4936         bestm1 = crtc->config.dpll.m1;
4937         bestm2 = crtc->config.dpll.m2;
4938         bestp1 = crtc->config.dpll.p1;
4939         bestp2 = crtc->config.dpll.p2;
4940
4941         /* See eDP HDMI DPIO driver vbios notes doc */
4942
4943         /* PLL B needs special handling */
4944         if (pipe)
4945                 vlv_pllb_recal_opamp(dev_priv, pipe);
4946
4947         /* Set up Tx target for periodic Rcomp update */
4948         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4949
4950         /* Disable target IRef on PLL */
4951         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4952         reg_val &= 0x00ffffff;
4953         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4954
4955         /* Disable fast lock */
4956         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4957
4958         /* Set idtafcrecal before PLL is enabled */
4959         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4960         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4961         mdiv |= ((bestn << DPIO_N_SHIFT));
4962         mdiv |= (1 << DPIO_K_SHIFT);
4963
4964         /*
4965          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4966          * but we don't support that).
4967          * Note: don't use the DAC post divider as it seems unstable.
4968          */
4969         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4970         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4971
4972         mdiv |= DPIO_ENABLE_CALIBRATION;
4973         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4974
4975         /* Set HBR and RBR LPF coefficients */
4976         if (crtc->config.port_clock == 162000 ||
4977             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4978             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4979                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4980                                  0x009f0003);
4981         else
4982                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4983                                  0x00d0000f);
4984
4985         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4986             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4987                 /* Use SSC source */
4988                 if (!pipe)
4989                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4990                                          0x0df40000);
4991                 else
4992                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4993                                          0x0df70000);
4994         } else { /* HDMI or VGA */
4995                 /* Use bend source */
4996                 if (!pipe)
4997                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4998                                          0x0df70000);
4999                 else
5000                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5001                                          0x0df40000);
5002         }
5003
5004         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5005         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5006         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5007             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5008                 coreclk |= 0x01000000;
5009         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5010
5011         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5012
5013         /*
5014          * Enable DPIO clock input. We should never disable the reference
5015          * clock for pipe B, since VGA hotplug / manual detection depends
5016          * on it.
5017          */
5018         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5019                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5020         /* We should never disable this, set it here for state tracking */
5021         if (pipe == PIPE_B)
5022                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5023         dpll |= DPLL_VCO_ENABLE;
5024         crtc->config.dpll_hw_state.dpll = dpll;
5025
5026         dpll_md = (crtc->config.pixel_multiplier - 1)
5027                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5028         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5029
5030         if (crtc->config.has_dp_encoder)
5031                 intel_dp_set_m_n(crtc);
5032
5033         mutex_unlock(&dev_priv->dpio_lock);
5034 }
5035
5036 static void i9xx_update_pll(struct intel_crtc *crtc,
5037                             intel_clock_t *reduced_clock,
5038                             int num_connectors)
5039 {
5040         struct drm_device *dev = crtc->base.dev;
5041         struct drm_i915_private *dev_priv = dev->dev_private;
5042         u32 dpll;
5043         bool is_sdvo;
5044         struct dpll *clock = &crtc->config.dpll;
5045
5046         i9xx_update_pll_dividers(crtc, reduced_clock);
5047
5048         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5049                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5050
5051         dpll = DPLL_VGA_MODE_DIS;
5052
5053         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5054                 dpll |= DPLLB_MODE_LVDS;
5055         else
5056                 dpll |= DPLLB_MODE_DAC_SERIAL;
5057
5058         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5059                 dpll |= (crtc->config.pixel_multiplier - 1)
5060                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5061         }
5062
5063         if (is_sdvo)
5064                 dpll |= DPLL_SDVO_HIGH_SPEED;
5065
5066         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5067                 dpll |= DPLL_SDVO_HIGH_SPEED;
5068
5069         /* compute bitmask from p1 value */
5070         if (IS_PINEVIEW(dev))
5071                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5072         else {
5073                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5074                 if (IS_G4X(dev) && reduced_clock)
5075                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5076         }
5077         switch (clock->p2) {
5078         case 5:
5079                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5080                 break;
5081         case 7:
5082                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5083                 break;
5084         case 10:
5085                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5086                 break;
5087         case 14:
5088                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5089                 break;
5090         }
5091         if (INTEL_INFO(dev)->gen >= 4)
5092                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5093
5094         if (crtc->config.sdvo_tv_clock)
5095                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5096         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5097                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5098                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5099         else
5100                 dpll |= PLL_REF_INPUT_DREFCLK;
5101
5102         dpll |= DPLL_VCO_ENABLE;
5103         crtc->config.dpll_hw_state.dpll = dpll;
5104
5105         if (INTEL_INFO(dev)->gen >= 4) {
5106                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5107                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5108                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5109         }
5110
5111         if (crtc->config.has_dp_encoder)
5112                 intel_dp_set_m_n(crtc);
5113 }
5114
5115 static void i8xx_update_pll(struct intel_crtc *crtc,
5116                             intel_clock_t *reduced_clock,
5117                             int num_connectors)
5118 {
5119         struct drm_device *dev = crtc->base.dev;
5120         struct drm_i915_private *dev_priv = dev->dev_private;
5121         u32 dpll;
5122         struct dpll *clock = &crtc->config.dpll;
5123
5124         i9xx_update_pll_dividers(crtc, reduced_clock);
5125
5126         dpll = DPLL_VGA_MODE_DIS;
5127
5128         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5129                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5130         } else {
5131                 if (clock->p1 == 2)
5132                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5133                 else
5134                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5135                 if (clock->p2 == 4)
5136                         dpll |= PLL_P2_DIVIDE_BY_4;
5137         }
5138
5139         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5140                 dpll |= DPLL_DVO_2X_MODE;
5141
5142         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5143                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5144                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5145         else
5146                 dpll |= PLL_REF_INPUT_DREFCLK;
5147
5148         dpll |= DPLL_VCO_ENABLE;
5149         crtc->config.dpll_hw_state.dpll = dpll;
5150 }
5151
5152 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5153 {
5154         struct drm_device *dev = intel_crtc->base.dev;
5155         struct drm_i915_private *dev_priv = dev->dev_private;
5156         enum pipe pipe = intel_crtc->pipe;
5157         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5158         struct drm_display_mode *adjusted_mode =
5159                 &intel_crtc->config.adjusted_mode;
5160         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5161
5162         /* We need to be careful not to changed the adjusted mode, for otherwise
5163          * the hw state checker will get angry at the mismatch. */
5164         crtc_vtotal = adjusted_mode->crtc_vtotal;
5165         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5166
5167         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5168                 /* the chip adds 2 halflines automatically */
5169                 crtc_vtotal -= 1;
5170                 crtc_vblank_end -= 1;
5171                 vsyncshift = adjusted_mode->crtc_hsync_start
5172                              - adjusted_mode->crtc_htotal / 2;
5173         } else {
5174                 vsyncshift = 0;
5175         }
5176
5177         if (INTEL_INFO(dev)->gen > 3)
5178                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5179
5180         I915_WRITE(HTOTAL(cpu_transcoder),
5181                    (adjusted_mode->crtc_hdisplay - 1) |
5182                    ((adjusted_mode->crtc_htotal - 1) << 16));
5183         I915_WRITE(HBLANK(cpu_transcoder),
5184                    (adjusted_mode->crtc_hblank_start - 1) |
5185                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5186         I915_WRITE(HSYNC(cpu_transcoder),
5187                    (adjusted_mode->crtc_hsync_start - 1) |
5188                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5189
5190         I915_WRITE(VTOTAL(cpu_transcoder),
5191                    (adjusted_mode->crtc_vdisplay - 1) |
5192                    ((crtc_vtotal - 1) << 16));
5193         I915_WRITE(VBLANK(cpu_transcoder),
5194                    (adjusted_mode->crtc_vblank_start - 1) |
5195                    ((crtc_vblank_end - 1) << 16));
5196         I915_WRITE(VSYNC(cpu_transcoder),
5197                    (adjusted_mode->crtc_vsync_start - 1) |
5198                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5199
5200         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5201          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5202          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5203          * bits. */
5204         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5205             (pipe == PIPE_B || pipe == PIPE_C))
5206                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5207
5208         /* pipesrc controls the size that is scaled from, which should
5209          * always be the user's requested size.
5210          */
5211         I915_WRITE(PIPESRC(pipe),
5212                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5213                    (intel_crtc->config.pipe_src_h - 1));
5214 }
5215
5216 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5217                                    struct intel_crtc_config *pipe_config)
5218 {
5219         struct drm_device *dev = crtc->base.dev;
5220         struct drm_i915_private *dev_priv = dev->dev_private;
5221         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5222         uint32_t tmp;
5223
5224         tmp = I915_READ(HTOTAL(cpu_transcoder));
5225         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5226         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5227         tmp = I915_READ(HBLANK(cpu_transcoder));
5228         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5229         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5230         tmp = I915_READ(HSYNC(cpu_transcoder));
5231         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5232         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5233
5234         tmp = I915_READ(VTOTAL(cpu_transcoder));
5235         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5236         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5237         tmp = I915_READ(VBLANK(cpu_transcoder));
5238         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5239         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5240         tmp = I915_READ(VSYNC(cpu_transcoder));
5241         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5242         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5243
5244         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5245                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5246                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5247                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5248         }
5249
5250         tmp = I915_READ(PIPESRC(crtc->pipe));
5251         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5252         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5253
5254         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5255         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5256 }
5257
5258 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5259                                              struct intel_crtc_config *pipe_config)
5260 {
5261         struct drm_crtc *crtc = &intel_crtc->base;
5262
5263         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5264         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5265         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5266         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5267
5268         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5269         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5270         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5271         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5272
5273         crtc->mode.flags = pipe_config->adjusted_mode.flags;
5274
5275         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5276         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5277 }
5278
5279 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5280 {
5281         struct drm_device *dev = intel_crtc->base.dev;
5282         struct drm_i915_private *dev_priv = dev->dev_private;
5283         uint32_t pipeconf;
5284
5285         pipeconf = 0;
5286
5287         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5288             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5289                 pipeconf |= PIPECONF_ENABLE;
5290
5291         if (intel_crtc->config.double_wide)
5292                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5293
5294         /* only g4x and later have fancy bpc/dither controls */
5295         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5296                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5297                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5298                         pipeconf |= PIPECONF_DITHER_EN |
5299                                     PIPECONF_DITHER_TYPE_SP;
5300
5301                 switch (intel_crtc->config.pipe_bpp) {
5302                 case 18:
5303                         pipeconf |= PIPECONF_6BPC;
5304                         break;
5305                 case 24:
5306                         pipeconf |= PIPECONF_8BPC;
5307                         break;
5308                 case 30:
5309                         pipeconf |= PIPECONF_10BPC;
5310                         break;
5311                 default:
5312                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5313                         BUG();
5314                 }
5315         }
5316
5317         if (HAS_PIPE_CXSR(dev)) {
5318                 if (intel_crtc->lowfreq_avail) {
5319                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5320                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5321                 } else {
5322                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5323                 }
5324         }
5325
5326         if (!IS_GEN2(dev) &&
5327             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5328                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5329         else
5330                 pipeconf |= PIPECONF_PROGRESSIVE;
5331
5332         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5333                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5334
5335         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5336         POSTING_READ(PIPECONF(intel_crtc->pipe));
5337 }
5338
5339 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5340                               int x, int y,
5341                               struct drm_framebuffer *fb)
5342 {
5343         struct drm_device *dev = crtc->dev;
5344         struct drm_i915_private *dev_priv = dev->dev_private;
5345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5346         int pipe = intel_crtc->pipe;
5347         int plane = intel_crtc->plane;
5348         int refclk, num_connectors = 0;
5349         intel_clock_t clock, reduced_clock;
5350         u32 dspcntr;
5351         bool ok, has_reduced_clock = false;
5352         bool is_lvds = false, is_dsi = false;
5353         struct intel_encoder *encoder;
5354         const intel_limit_t *limit;
5355         int ret;
5356
5357         for_each_encoder_on_crtc(dev, crtc, encoder) {
5358                 switch (encoder->type) {
5359                 case INTEL_OUTPUT_LVDS:
5360                         is_lvds = true;
5361                         break;
5362                 case INTEL_OUTPUT_DSI:
5363                         is_dsi = true;
5364                         break;
5365                 }
5366
5367                 num_connectors++;
5368         }
5369
5370         if (is_dsi)
5371                 goto skip_dpll;
5372
5373         if (!intel_crtc->config.clock_set) {
5374                 refclk = i9xx_get_refclk(crtc, num_connectors);
5375
5376                 /*
5377                  * Returns a set of divisors for the desired target clock with
5378                  * the given refclk, or FALSE.  The returned values represent
5379                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5380                  * 2) / p1 / p2.
5381                  */
5382                 limit = intel_limit(crtc, refclk);
5383                 ok = dev_priv->display.find_dpll(limit, crtc,
5384                                                  intel_crtc->config.port_clock,
5385                                                  refclk, NULL, &clock);
5386                 if (!ok) {
5387                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5388                         return -EINVAL;
5389                 }
5390
5391                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5392                         /*
5393                          * Ensure we match the reduced clock's P to the target
5394                          * clock.  If the clocks don't match, we can't switch
5395                          * the display clock by using the FP0/FP1. In such case
5396                          * we will disable the LVDS downclock feature.
5397                          */
5398                         has_reduced_clock =
5399                                 dev_priv->display.find_dpll(limit, crtc,
5400                                                             dev_priv->lvds_downclock,
5401                                                             refclk, &clock,
5402                                                             &reduced_clock);
5403                 }
5404                 /* Compat-code for transition, will disappear. */
5405                 intel_crtc->config.dpll.n = clock.n;
5406                 intel_crtc->config.dpll.m1 = clock.m1;
5407                 intel_crtc->config.dpll.m2 = clock.m2;
5408                 intel_crtc->config.dpll.p1 = clock.p1;
5409                 intel_crtc->config.dpll.p2 = clock.p2;
5410         }
5411
5412         if (IS_GEN2(dev)) {
5413                 i8xx_update_pll(intel_crtc,
5414                                 has_reduced_clock ? &reduced_clock : NULL,
5415                                 num_connectors);
5416         } else if (IS_VALLEYVIEW(dev)) {
5417                 vlv_update_pll(intel_crtc);
5418         } else {
5419                 i9xx_update_pll(intel_crtc,
5420                                 has_reduced_clock ? &reduced_clock : NULL,
5421                                 num_connectors);
5422         }
5423
5424 skip_dpll:
5425         /* Set up the display plane register */
5426         dspcntr = DISPPLANE_GAMMA_ENABLE;
5427
5428         if (!IS_VALLEYVIEW(dev)) {
5429                 if (pipe == 0)
5430                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5431                 else
5432                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5433         }
5434
5435         intel_set_pipe_timings(intel_crtc);
5436
5437         /* pipesrc and dspsize control the size that is scaled from,
5438          * which should always be the user's requested size.
5439          */
5440         I915_WRITE(DSPSIZE(plane),
5441                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5442                    (intel_crtc->config.pipe_src_w - 1));
5443         I915_WRITE(DSPPOS(plane), 0);
5444
5445         i9xx_set_pipeconf(intel_crtc);
5446
5447         I915_WRITE(DSPCNTR(plane), dspcntr);
5448         POSTING_READ(DSPCNTR(plane));
5449
5450         ret = intel_pipe_set_base(crtc, x, y, fb);
5451
5452         return ret;
5453 }
5454
5455 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5456                                  struct intel_crtc_config *pipe_config)
5457 {
5458         struct drm_device *dev = crtc->base.dev;
5459         struct drm_i915_private *dev_priv = dev->dev_private;
5460         uint32_t tmp;
5461
5462         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5463                 return;
5464
5465         tmp = I915_READ(PFIT_CONTROL);
5466         if (!(tmp & PFIT_ENABLE))
5467                 return;
5468
5469         /* Check whether the pfit is attached to our pipe. */
5470         if (INTEL_INFO(dev)->gen < 4) {
5471                 if (crtc->pipe != PIPE_B)
5472                         return;
5473         } else {
5474                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5475                         return;
5476         }
5477
5478         pipe_config->gmch_pfit.control = tmp;
5479         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5480         if (INTEL_INFO(dev)->gen < 5)
5481                 pipe_config->gmch_pfit.lvds_border_bits =
5482                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5483 }
5484
5485 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5486                                struct intel_crtc_config *pipe_config)
5487 {
5488         struct drm_device *dev = crtc->base.dev;
5489         struct drm_i915_private *dev_priv = dev->dev_private;
5490         int pipe = pipe_config->cpu_transcoder;
5491         intel_clock_t clock;
5492         u32 mdiv;
5493         int refclk = 100000;
5494
5495         mutex_lock(&dev_priv->dpio_lock);
5496         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5497         mutex_unlock(&dev_priv->dpio_lock);
5498
5499         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5500         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5501         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5502         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5503         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5504
5505         vlv_clock(refclk, &clock);
5506
5507         /* clock.dot is the fast clock */
5508         pipe_config->port_clock = clock.dot / 5;
5509 }
5510
5511 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5512                                  struct intel_crtc_config *pipe_config)
5513 {
5514         struct drm_device *dev = crtc->base.dev;
5515         struct drm_i915_private *dev_priv = dev->dev_private;
5516         uint32_t tmp;
5517
5518         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5519         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5520
5521         tmp = I915_READ(PIPECONF(crtc->pipe));
5522         if (!(tmp & PIPECONF_ENABLE))
5523                 return false;
5524
5525         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5526                 switch (tmp & PIPECONF_BPC_MASK) {
5527                 case PIPECONF_6BPC:
5528                         pipe_config->pipe_bpp = 18;
5529                         break;
5530                 case PIPECONF_8BPC:
5531                         pipe_config->pipe_bpp = 24;
5532                         break;
5533                 case PIPECONF_10BPC:
5534                         pipe_config->pipe_bpp = 30;
5535                         break;
5536                 default:
5537                         break;
5538                 }
5539         }
5540
5541         if (INTEL_INFO(dev)->gen < 4)
5542                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5543
5544         intel_get_pipe_timings(crtc, pipe_config);
5545
5546         i9xx_get_pfit_config(crtc, pipe_config);
5547
5548         if (INTEL_INFO(dev)->gen >= 4) {
5549                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5550                 pipe_config->pixel_multiplier =
5551                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5552                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5553                 pipe_config->dpll_hw_state.dpll_md = tmp;
5554         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5555                 tmp = I915_READ(DPLL(crtc->pipe));
5556                 pipe_config->pixel_multiplier =
5557                         ((tmp & SDVO_MULTIPLIER_MASK)
5558                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5559         } else {
5560                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5561                  * port and will be fixed up in the encoder->get_config
5562                  * function. */
5563                 pipe_config->pixel_multiplier = 1;
5564         }
5565         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5566         if (!IS_VALLEYVIEW(dev)) {
5567                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5568                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5569         } else {
5570                 /* Mask out read-only status bits. */
5571                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5572                                                      DPLL_PORTC_READY_MASK |
5573                                                      DPLL_PORTB_READY_MASK);
5574         }
5575
5576         if (IS_VALLEYVIEW(dev))
5577                 vlv_crtc_clock_get(crtc, pipe_config);
5578         else
5579                 i9xx_crtc_clock_get(crtc, pipe_config);
5580
5581         return true;
5582 }
5583
5584 static void ironlake_init_pch_refclk(struct drm_device *dev)
5585 {
5586         struct drm_i915_private *dev_priv = dev->dev_private;
5587         struct drm_mode_config *mode_config = &dev->mode_config;
5588         struct intel_encoder *encoder;
5589         u32 val, final;
5590         bool has_lvds = false;
5591         bool has_cpu_edp = false;
5592         bool has_panel = false;
5593         bool has_ck505 = false;
5594         bool can_ssc = false;
5595
5596         /* We need to take the global config into account */
5597         list_for_each_entry(encoder, &mode_config->encoder_list,
5598                             base.head) {
5599                 switch (encoder->type) {
5600                 case INTEL_OUTPUT_LVDS:
5601                         has_panel = true;
5602                         has_lvds = true;
5603                         break;
5604                 case INTEL_OUTPUT_EDP:
5605                         has_panel = true;
5606                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5607                                 has_cpu_edp = true;
5608                         break;
5609                 }
5610         }
5611
5612         if (HAS_PCH_IBX(dev)) {
5613                 has_ck505 = dev_priv->vbt.display_clock_mode;
5614                 can_ssc = has_ck505;
5615         } else {
5616                 has_ck505 = false;
5617                 can_ssc = true;
5618         }
5619
5620         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5621                       has_panel, has_lvds, has_ck505);
5622
5623         /* Ironlake: try to setup display ref clock before DPLL
5624          * enabling. This is only under driver's control after
5625          * PCH B stepping, previous chipset stepping should be
5626          * ignoring this setting.
5627          */
5628         val = I915_READ(PCH_DREF_CONTROL);
5629
5630         /* As we must carefully and slowly disable/enable each source in turn,
5631          * compute the final state we want first and check if we need to
5632          * make any changes at all.
5633          */
5634         final = val;
5635         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5636         if (has_ck505)
5637                 final |= DREF_NONSPREAD_CK505_ENABLE;
5638         else
5639                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5640
5641         final &= ~DREF_SSC_SOURCE_MASK;
5642         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5643         final &= ~DREF_SSC1_ENABLE;
5644
5645         if (has_panel) {
5646                 final |= DREF_SSC_SOURCE_ENABLE;
5647
5648                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5649                         final |= DREF_SSC1_ENABLE;
5650
5651                 if (has_cpu_edp) {
5652                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5653                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5654                         else
5655                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5656                 } else
5657                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5658         } else {
5659                 final |= DREF_SSC_SOURCE_DISABLE;
5660                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5661         }
5662
5663         if (final == val)
5664                 return;
5665
5666         /* Always enable nonspread source */
5667         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5668
5669         if (has_ck505)
5670                 val |= DREF_NONSPREAD_CK505_ENABLE;
5671         else
5672                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5673
5674         if (has_panel) {
5675                 val &= ~DREF_SSC_SOURCE_MASK;
5676                 val |= DREF_SSC_SOURCE_ENABLE;
5677
5678                 /* SSC must be turned on before enabling the CPU output  */
5679                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5680                         DRM_DEBUG_KMS("Using SSC on panel\n");
5681                         val |= DREF_SSC1_ENABLE;
5682                 } else
5683                         val &= ~DREF_SSC1_ENABLE;
5684
5685                 /* Get SSC going before enabling the outputs */
5686                 I915_WRITE(PCH_DREF_CONTROL, val);
5687                 POSTING_READ(PCH_DREF_CONTROL);
5688                 udelay(200);
5689
5690                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5691
5692                 /* Enable CPU source on CPU attached eDP */
5693                 if (has_cpu_edp) {
5694                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5695                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5696                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5697                         }
5698                         else
5699                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5700                 } else
5701                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5702
5703                 I915_WRITE(PCH_DREF_CONTROL, val);
5704                 POSTING_READ(PCH_DREF_CONTROL);
5705                 udelay(200);
5706         } else {
5707                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5708
5709                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5710
5711                 /* Turn off CPU output */
5712                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5713
5714                 I915_WRITE(PCH_DREF_CONTROL, val);
5715                 POSTING_READ(PCH_DREF_CONTROL);
5716                 udelay(200);
5717
5718                 /* Turn off the SSC source */
5719                 val &= ~DREF_SSC_SOURCE_MASK;
5720                 val |= DREF_SSC_SOURCE_DISABLE;
5721
5722                 /* Turn off SSC1 */
5723                 val &= ~DREF_SSC1_ENABLE;
5724
5725                 I915_WRITE(PCH_DREF_CONTROL, val);
5726                 POSTING_READ(PCH_DREF_CONTROL);
5727                 udelay(200);
5728         }
5729
5730         BUG_ON(val != final);
5731 }
5732
5733 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5734 {
5735         uint32_t tmp;
5736
5737         tmp = I915_READ(SOUTH_CHICKEN2);
5738         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5739         I915_WRITE(SOUTH_CHICKEN2, tmp);
5740
5741         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5742                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5743                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5744
5745         tmp = I915_READ(SOUTH_CHICKEN2);
5746         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5747         I915_WRITE(SOUTH_CHICKEN2, tmp);
5748
5749         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5750                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5751                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5752 }
5753
5754 /* WaMPhyProgramming:hsw */
5755 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5756 {
5757         uint32_t tmp;
5758
5759         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5760         tmp &= ~(0xFF << 24);
5761         tmp |= (0x12 << 24);
5762         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5763
5764         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5765         tmp |= (1 << 11);
5766         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5767
5768         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5769         tmp |= (1 << 11);
5770         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5771
5772         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5773         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5774         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5775
5776         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5777         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5778         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5779
5780         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5781         tmp &= ~(7 << 13);
5782         tmp |= (5 << 13);
5783         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5784
5785         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5786         tmp &= ~(7 << 13);
5787         tmp |= (5 << 13);
5788         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5789
5790         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5791         tmp &= ~0xFF;
5792         tmp |= 0x1C;
5793         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5794
5795         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5796         tmp &= ~0xFF;
5797         tmp |= 0x1C;
5798         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5799
5800         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5801         tmp &= ~(0xFF << 16);
5802         tmp |= (0x1C << 16);
5803         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5804
5805         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5806         tmp &= ~(0xFF << 16);
5807         tmp |= (0x1C << 16);
5808         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5809
5810         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5811         tmp |= (1 << 27);
5812         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5813
5814         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5815         tmp |= (1 << 27);
5816         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5817
5818         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5819         tmp &= ~(0xF << 28);
5820         tmp |= (4 << 28);
5821         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5822
5823         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5824         tmp &= ~(0xF << 28);
5825         tmp |= (4 << 28);
5826         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5827 }
5828
5829 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5830  * Programming" based on the parameters passed:
5831  * - Sequence to enable CLKOUT_DP
5832  * - Sequence to enable CLKOUT_DP without spread
5833  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5834  */
5835 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5836                                  bool with_fdi)
5837 {
5838         struct drm_i915_private *dev_priv = dev->dev_private;
5839         uint32_t reg, tmp;
5840
5841         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5842                 with_spread = true;
5843         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5844                  with_fdi, "LP PCH doesn't have FDI\n"))
5845                 with_fdi = false;
5846
5847         mutex_lock(&dev_priv->dpio_lock);
5848
5849         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5850         tmp &= ~SBI_SSCCTL_DISABLE;
5851         tmp |= SBI_SSCCTL_PATHALT;
5852         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5853
5854         udelay(24);
5855
5856         if (with_spread) {
5857                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5858                 tmp &= ~SBI_SSCCTL_PATHALT;
5859                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5860
5861                 if (with_fdi) {
5862                         lpt_reset_fdi_mphy(dev_priv);
5863                         lpt_program_fdi_mphy(dev_priv);
5864                 }
5865         }
5866
5867         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5868                SBI_GEN0 : SBI_DBUFF0;
5869         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5870         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5871         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5872
5873         mutex_unlock(&dev_priv->dpio_lock);
5874 }
5875
5876 /* Sequence to disable CLKOUT_DP */
5877 static void lpt_disable_clkout_dp(struct drm_device *dev)
5878 {
5879         struct drm_i915_private *dev_priv = dev->dev_private;
5880         uint32_t reg, tmp;
5881
5882         mutex_lock(&dev_priv->dpio_lock);
5883
5884         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5885                SBI_GEN0 : SBI_DBUFF0;
5886         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5887         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5888         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5889
5890         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5891         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5892                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5893                         tmp |= SBI_SSCCTL_PATHALT;
5894                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5895                         udelay(32);
5896                 }
5897                 tmp |= SBI_SSCCTL_DISABLE;
5898                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5899         }
5900
5901         mutex_unlock(&dev_priv->dpio_lock);
5902 }
5903
5904 static void lpt_init_pch_refclk(struct drm_device *dev)
5905 {
5906         struct drm_mode_config *mode_config = &dev->mode_config;
5907         struct intel_encoder *encoder;
5908         bool has_vga = false;
5909
5910         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5911                 switch (encoder->type) {
5912                 case INTEL_OUTPUT_ANALOG:
5913                         has_vga = true;
5914                         break;
5915                 }
5916         }
5917
5918         if (has_vga)
5919                 lpt_enable_clkout_dp(dev, true, true);
5920         else
5921                 lpt_disable_clkout_dp(dev);
5922 }
5923
5924 /*
5925  * Initialize reference clocks when the driver loads
5926  */
5927 void intel_init_pch_refclk(struct drm_device *dev)
5928 {
5929         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5930                 ironlake_init_pch_refclk(dev);
5931         else if (HAS_PCH_LPT(dev))
5932                 lpt_init_pch_refclk(dev);
5933 }
5934
5935 static int ironlake_get_refclk(struct drm_crtc *crtc)
5936 {
5937         struct drm_device *dev = crtc->dev;
5938         struct drm_i915_private *dev_priv = dev->dev_private;
5939         struct intel_encoder *encoder;
5940         int num_connectors = 0;
5941         bool is_lvds = false;
5942
5943         for_each_encoder_on_crtc(dev, crtc, encoder) {
5944                 switch (encoder->type) {
5945                 case INTEL_OUTPUT_LVDS:
5946                         is_lvds = true;
5947                         break;
5948                 }
5949                 num_connectors++;
5950         }
5951
5952         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5953                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5954                               dev_priv->vbt.lvds_ssc_freq);
5955                 return dev_priv->vbt.lvds_ssc_freq;
5956         }
5957
5958         return 120000;
5959 }
5960
5961 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5962 {
5963         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5965         int pipe = intel_crtc->pipe;
5966         uint32_t val;
5967
5968         val = 0;
5969
5970         switch (intel_crtc->config.pipe_bpp) {
5971         case 18:
5972                 val |= PIPECONF_6BPC;
5973                 break;
5974         case 24:
5975                 val |= PIPECONF_8BPC;
5976                 break;
5977         case 30:
5978                 val |= PIPECONF_10BPC;
5979                 break;
5980         case 36:
5981                 val |= PIPECONF_12BPC;
5982                 break;
5983         default:
5984                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5985                 BUG();
5986         }
5987
5988         if (intel_crtc->config.dither)
5989                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5990
5991         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5992                 val |= PIPECONF_INTERLACED_ILK;
5993         else
5994                 val |= PIPECONF_PROGRESSIVE;
5995
5996         if (intel_crtc->config.limited_color_range)
5997                 val |= PIPECONF_COLOR_RANGE_SELECT;
5998
5999         I915_WRITE(PIPECONF(pipe), val);
6000         POSTING_READ(PIPECONF(pipe));
6001 }
6002
6003 /*
6004  * Set up the pipe CSC unit.
6005  *
6006  * Currently only full range RGB to limited range RGB conversion
6007  * is supported, but eventually this should handle various
6008  * RGB<->YCbCr scenarios as well.
6009  */
6010 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6011 {
6012         struct drm_device *dev = crtc->dev;
6013         struct drm_i915_private *dev_priv = dev->dev_private;
6014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6015         int pipe = intel_crtc->pipe;
6016         uint16_t coeff = 0x7800; /* 1.0 */
6017
6018         /*
6019          * TODO: Check what kind of values actually come out of the pipe
6020          * with these coeff/postoff values and adjust to get the best
6021          * accuracy. Perhaps we even need to take the bpc value into
6022          * consideration.
6023          */
6024
6025         if (intel_crtc->config.limited_color_range)
6026                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6027
6028         /*
6029          * GY/GU and RY/RU should be the other way around according
6030          * to BSpec, but reality doesn't agree. Just set them up in
6031          * a way that results in the correct picture.
6032          */
6033         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6034         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6035
6036         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6037         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6038
6039         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6040         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6041
6042         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6043         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6044         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6045
6046         if (INTEL_INFO(dev)->gen > 6) {
6047                 uint16_t postoff = 0;
6048
6049                 if (intel_crtc->config.limited_color_range)
6050                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6051
6052                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6053                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6054                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6055
6056                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6057         } else {
6058                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6059
6060                 if (intel_crtc->config.limited_color_range)
6061                         mode |= CSC_BLACK_SCREEN_OFFSET;
6062
6063                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6064         }
6065 }
6066
6067 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6068 {
6069         struct drm_device *dev = crtc->dev;
6070         struct drm_i915_private *dev_priv = dev->dev_private;
6071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6072         enum pipe pipe = intel_crtc->pipe;
6073         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6074         uint32_t val;
6075
6076         val = 0;
6077
6078         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6079                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6080
6081         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6082                 val |= PIPECONF_INTERLACED_ILK;
6083         else
6084                 val |= PIPECONF_PROGRESSIVE;
6085
6086         I915_WRITE(PIPECONF(cpu_transcoder), val);
6087         POSTING_READ(PIPECONF(cpu_transcoder));
6088
6089         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6090         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6091
6092         if (IS_BROADWELL(dev)) {
6093                 val = 0;
6094
6095                 switch (intel_crtc->config.pipe_bpp) {
6096                 case 18:
6097                         val |= PIPEMISC_DITHER_6_BPC;
6098                         break;
6099                 case 24:
6100                         val |= PIPEMISC_DITHER_8_BPC;
6101                         break;
6102                 case 30:
6103                         val |= PIPEMISC_DITHER_10_BPC;
6104                         break;
6105                 case 36:
6106                         val |= PIPEMISC_DITHER_12_BPC;
6107                         break;
6108                 default:
6109                         /* Case prevented by pipe_config_set_bpp. */
6110                         BUG();
6111                 }
6112
6113                 if (intel_crtc->config.dither)
6114                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6115
6116                 I915_WRITE(PIPEMISC(pipe), val);
6117         }
6118 }
6119
6120 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6121                                     intel_clock_t *clock,
6122                                     bool *has_reduced_clock,
6123                                     intel_clock_t *reduced_clock)
6124 {
6125         struct drm_device *dev = crtc->dev;
6126         struct drm_i915_private *dev_priv = dev->dev_private;
6127         struct intel_encoder *intel_encoder;
6128         int refclk;
6129         const intel_limit_t *limit;
6130         bool ret, is_lvds = false;
6131
6132         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6133                 switch (intel_encoder->type) {
6134                 case INTEL_OUTPUT_LVDS:
6135                         is_lvds = true;
6136                         break;
6137                 }
6138         }
6139
6140         refclk = ironlake_get_refclk(crtc);
6141
6142         /*
6143          * Returns a set of divisors for the desired target clock with the given
6144          * refclk, or FALSE.  The returned values represent the clock equation:
6145          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6146          */
6147         limit = intel_limit(crtc, refclk);
6148         ret = dev_priv->display.find_dpll(limit, crtc,
6149                                           to_intel_crtc(crtc)->config.port_clock,
6150                                           refclk, NULL, clock);
6151         if (!ret)
6152                 return false;
6153
6154         if (is_lvds && dev_priv->lvds_downclock_avail) {
6155                 /*
6156                  * Ensure we match the reduced clock's P to the target clock.
6157                  * If the clocks don't match, we can't switch the display clock
6158                  * by using the FP0/FP1. In such case we will disable the LVDS
6159                  * downclock feature.
6160                 */
6161                 *has_reduced_clock =
6162                         dev_priv->display.find_dpll(limit, crtc,
6163                                                     dev_priv->lvds_downclock,
6164                                                     refclk, clock,
6165                                                     reduced_clock);
6166         }
6167
6168         return true;
6169 }
6170
6171 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6172 {
6173         /*
6174          * Account for spread spectrum to avoid
6175          * oversubscribing the link. Max center spread
6176          * is 2.5%; use 5% for safety's sake.
6177          */
6178         u32 bps = target_clock * bpp * 21 / 20;
6179         return bps / (link_bw * 8) + 1;
6180 }
6181
6182 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6183 {
6184         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6185 }
6186
6187 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6188                                       u32 *fp,
6189                                       intel_clock_t *reduced_clock, u32 *fp2)
6190 {
6191         struct drm_crtc *crtc = &intel_crtc->base;
6192         struct drm_device *dev = crtc->dev;
6193         struct drm_i915_private *dev_priv = dev->dev_private;
6194         struct intel_encoder *intel_encoder;
6195         uint32_t dpll;
6196         int factor, num_connectors = 0;
6197         bool is_lvds = false, is_sdvo = false;
6198
6199         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6200                 switch (intel_encoder->type) {
6201                 case INTEL_OUTPUT_LVDS:
6202                         is_lvds = true;
6203                         break;
6204                 case INTEL_OUTPUT_SDVO:
6205                 case INTEL_OUTPUT_HDMI:
6206                         is_sdvo = true;
6207                         break;
6208                 }
6209
6210                 num_connectors++;
6211         }
6212
6213         /* Enable autotuning of the PLL clock (if permissible) */
6214         factor = 21;
6215         if (is_lvds) {
6216                 if ((intel_panel_use_ssc(dev_priv) &&
6217                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6218                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6219                         factor = 25;
6220         } else if (intel_crtc->config.sdvo_tv_clock)
6221                 factor = 20;
6222
6223         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6224                 *fp |= FP_CB_TUNE;
6225
6226         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6227                 *fp2 |= FP_CB_TUNE;
6228
6229         dpll = 0;
6230
6231         if (is_lvds)
6232                 dpll |= DPLLB_MODE_LVDS;
6233         else
6234                 dpll |= DPLLB_MODE_DAC_SERIAL;
6235
6236         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6237                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6238
6239         if (is_sdvo)
6240                 dpll |= DPLL_SDVO_HIGH_SPEED;
6241         if (intel_crtc->config.has_dp_encoder)
6242                 dpll |= DPLL_SDVO_HIGH_SPEED;
6243
6244         /* compute bitmask from p1 value */
6245         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6246         /* also FPA1 */
6247         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6248
6249         switch (intel_crtc->config.dpll.p2) {
6250         case 5:
6251                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6252                 break;
6253         case 7:
6254                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6255                 break;
6256         case 10:
6257                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6258                 break;
6259         case 14:
6260                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6261                 break;
6262         }
6263
6264         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6265                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6266         else
6267                 dpll |= PLL_REF_INPUT_DREFCLK;
6268
6269         return dpll | DPLL_VCO_ENABLE;
6270 }
6271
6272 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6273                                   int x, int y,
6274                                   struct drm_framebuffer *fb)
6275 {
6276         struct drm_device *dev = crtc->dev;
6277         struct drm_i915_private *dev_priv = dev->dev_private;
6278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279         int pipe = intel_crtc->pipe;
6280         int plane = intel_crtc->plane;
6281         int num_connectors = 0;
6282         intel_clock_t clock, reduced_clock;
6283         u32 dpll = 0, fp = 0, fp2 = 0;
6284         bool ok, has_reduced_clock = false;
6285         bool is_lvds = false;
6286         struct intel_encoder *encoder;
6287         struct intel_shared_dpll *pll;
6288         int ret;
6289
6290         for_each_encoder_on_crtc(dev, crtc, encoder) {
6291                 switch (encoder->type) {
6292                 case INTEL_OUTPUT_LVDS:
6293                         is_lvds = true;
6294                         break;
6295                 }
6296
6297                 num_connectors++;
6298         }
6299
6300         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6301              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6302
6303         ok = ironlake_compute_clocks(crtc, &clock,
6304                                      &has_reduced_clock, &reduced_clock);
6305         if (!ok && !intel_crtc->config.clock_set) {
6306                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6307                 return -EINVAL;
6308         }
6309         /* Compat-code for transition, will disappear. */
6310         if (!intel_crtc->config.clock_set) {
6311                 intel_crtc->config.dpll.n = clock.n;
6312                 intel_crtc->config.dpll.m1 = clock.m1;
6313                 intel_crtc->config.dpll.m2 = clock.m2;
6314                 intel_crtc->config.dpll.p1 = clock.p1;
6315                 intel_crtc->config.dpll.p2 = clock.p2;
6316         }
6317
6318         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6319         if (intel_crtc->config.has_pch_encoder) {
6320                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6321                 if (has_reduced_clock)
6322                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6323
6324                 dpll = ironlake_compute_dpll(intel_crtc,
6325                                              &fp, &reduced_clock,
6326                                              has_reduced_clock ? &fp2 : NULL);
6327
6328                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6329                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6330                 if (has_reduced_clock)
6331                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6332                 else
6333                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6334
6335                 pll = intel_get_shared_dpll(intel_crtc);
6336                 if (pll == NULL) {
6337                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6338                                          pipe_name(pipe));
6339                         return -EINVAL;
6340                 }
6341         } else
6342                 intel_put_shared_dpll(intel_crtc);
6343
6344         if (intel_crtc->config.has_dp_encoder)
6345                 intel_dp_set_m_n(intel_crtc);
6346
6347         if (is_lvds && has_reduced_clock && i915.powersave)
6348                 intel_crtc->lowfreq_avail = true;
6349         else
6350                 intel_crtc->lowfreq_avail = false;
6351
6352         intel_set_pipe_timings(intel_crtc);
6353
6354         if (intel_crtc->config.has_pch_encoder) {
6355                 intel_cpu_transcoder_set_m_n(intel_crtc,
6356                                              &intel_crtc->config.fdi_m_n);
6357         }
6358
6359         ironlake_set_pipeconf(crtc);
6360
6361         /* Set up the display plane register */
6362         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6363         POSTING_READ(DSPCNTR(plane));
6364
6365         ret = intel_pipe_set_base(crtc, x, y, fb);
6366
6367         return ret;
6368 }
6369
6370 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6371                                          struct intel_link_m_n *m_n)
6372 {
6373         struct drm_device *dev = crtc->base.dev;
6374         struct drm_i915_private *dev_priv = dev->dev_private;
6375         enum pipe pipe = crtc->pipe;
6376
6377         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6378         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6379         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6380                 & ~TU_SIZE_MASK;
6381         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6382         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6383                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6384 }
6385
6386 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6387                                          enum transcoder transcoder,
6388                                          struct intel_link_m_n *m_n)
6389 {
6390         struct drm_device *dev = crtc->base.dev;
6391         struct drm_i915_private *dev_priv = dev->dev_private;
6392         enum pipe pipe = crtc->pipe;
6393
6394         if (INTEL_INFO(dev)->gen >= 5) {
6395                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6396                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6397                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6398                         & ~TU_SIZE_MASK;
6399                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6400                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6401                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6402         } else {
6403                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6404                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6405                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6406                         & ~TU_SIZE_MASK;
6407                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6408                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6409                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6410         }
6411 }
6412
6413 void intel_dp_get_m_n(struct intel_crtc *crtc,
6414                       struct intel_crtc_config *pipe_config)
6415 {
6416         if (crtc->config.has_pch_encoder)
6417                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6418         else
6419                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6420                                              &pipe_config->dp_m_n);
6421 }
6422
6423 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6424                                         struct intel_crtc_config *pipe_config)
6425 {
6426         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6427                                      &pipe_config->fdi_m_n);
6428 }
6429
6430 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6431                                      struct intel_crtc_config *pipe_config)
6432 {
6433         struct drm_device *dev = crtc->base.dev;
6434         struct drm_i915_private *dev_priv = dev->dev_private;
6435         uint32_t tmp;
6436
6437         tmp = I915_READ(PF_CTL(crtc->pipe));
6438
6439         if (tmp & PF_ENABLE) {
6440                 pipe_config->pch_pfit.enabled = true;
6441                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6442                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6443
6444                 /* We currently do not free assignements of panel fitters on
6445                  * ivb/hsw (since we don't use the higher upscaling modes which
6446                  * differentiates them) so just WARN about this case for now. */
6447                 if (IS_GEN7(dev)) {
6448                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6449                                 PF_PIPE_SEL_IVB(crtc->pipe));
6450                 }
6451         }
6452 }
6453
6454 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6455                                      struct intel_crtc_config *pipe_config)
6456 {
6457         struct drm_device *dev = crtc->base.dev;
6458         struct drm_i915_private *dev_priv = dev->dev_private;
6459         uint32_t tmp;
6460
6461         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6462         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6463
6464         tmp = I915_READ(PIPECONF(crtc->pipe));
6465         if (!(tmp & PIPECONF_ENABLE))
6466                 return false;
6467
6468         switch (tmp & PIPECONF_BPC_MASK) {
6469         case PIPECONF_6BPC:
6470                 pipe_config->pipe_bpp = 18;
6471                 break;
6472         case PIPECONF_8BPC:
6473                 pipe_config->pipe_bpp = 24;
6474                 break;
6475         case PIPECONF_10BPC:
6476                 pipe_config->pipe_bpp = 30;
6477                 break;
6478         case PIPECONF_12BPC:
6479                 pipe_config->pipe_bpp = 36;
6480                 break;
6481         default:
6482                 break;
6483         }
6484
6485         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6486                 struct intel_shared_dpll *pll;
6487
6488                 pipe_config->has_pch_encoder = true;
6489
6490                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6491                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6492                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6493
6494                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6495
6496                 if (HAS_PCH_IBX(dev_priv->dev)) {
6497                         pipe_config->shared_dpll =
6498                                 (enum intel_dpll_id) crtc->pipe;
6499                 } else {
6500                         tmp = I915_READ(PCH_DPLL_SEL);
6501                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6502                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6503                         else
6504                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6505                 }
6506
6507                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6508
6509                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6510                                            &pipe_config->dpll_hw_state));
6511
6512                 tmp = pipe_config->dpll_hw_state.dpll;
6513                 pipe_config->pixel_multiplier =
6514                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6515                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6516
6517                 ironlake_pch_clock_get(crtc, pipe_config);
6518         } else {
6519                 pipe_config->pixel_multiplier = 1;
6520         }
6521
6522         intel_get_pipe_timings(crtc, pipe_config);
6523
6524         ironlake_get_pfit_config(crtc, pipe_config);
6525
6526         return true;
6527 }
6528
6529 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6530 {
6531         struct drm_device *dev = dev_priv->dev;
6532         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6533         struct intel_crtc *crtc;
6534         unsigned long irqflags;
6535         uint32_t val;
6536
6537         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6538                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6539                      pipe_name(crtc->pipe));
6540
6541         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6542         WARN(plls->spll_refcount, "SPLL enabled\n");
6543         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6544         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6545         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6546         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6547              "CPU PWM1 enabled\n");
6548         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6549              "CPU PWM2 enabled\n");
6550         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6551              "PCH PWM1 enabled\n");
6552         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6553              "Utility pin enabled\n");
6554         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6555
6556         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6557         val = I915_READ(DEIMR);
6558         WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6559              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6560         val = I915_READ(SDEIMR);
6561         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6562              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6563         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6564 }
6565
6566 /*
6567  * This function implements pieces of two sequences from BSpec:
6568  * - Sequence for display software to disable LCPLL
6569  * - Sequence for display software to allow package C8+
6570  * The steps implemented here are just the steps that actually touch the LCPLL
6571  * register. Callers should take care of disabling all the display engine
6572  * functions, doing the mode unset, fixing interrupts, etc.
6573  */
6574 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6575                               bool switch_to_fclk, bool allow_power_down)
6576 {
6577         uint32_t val;
6578
6579         assert_can_disable_lcpll(dev_priv);
6580
6581         val = I915_READ(LCPLL_CTL);
6582
6583         if (switch_to_fclk) {
6584                 val |= LCPLL_CD_SOURCE_FCLK;
6585                 I915_WRITE(LCPLL_CTL, val);
6586
6587                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6588                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6589                         DRM_ERROR("Switching to FCLK failed\n");
6590
6591                 val = I915_READ(LCPLL_CTL);
6592         }
6593
6594         val |= LCPLL_PLL_DISABLE;
6595         I915_WRITE(LCPLL_CTL, val);
6596         POSTING_READ(LCPLL_CTL);
6597
6598         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6599                 DRM_ERROR("LCPLL still locked\n");
6600
6601         val = I915_READ(D_COMP);
6602         val |= D_COMP_COMP_DISABLE;
6603         mutex_lock(&dev_priv->rps.hw_lock);
6604         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6605                 DRM_ERROR("Failed to disable D_COMP\n");
6606         mutex_unlock(&dev_priv->rps.hw_lock);
6607         POSTING_READ(D_COMP);
6608         ndelay(100);
6609
6610         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6611                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6612
6613         if (allow_power_down) {
6614                 val = I915_READ(LCPLL_CTL);
6615                 val |= LCPLL_POWER_DOWN_ALLOW;
6616                 I915_WRITE(LCPLL_CTL, val);
6617                 POSTING_READ(LCPLL_CTL);
6618         }
6619 }
6620
6621 /*
6622  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6623  * source.
6624  */
6625 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6626 {
6627         uint32_t val;
6628
6629         val = I915_READ(LCPLL_CTL);
6630
6631         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6632                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6633                 return;
6634
6635         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6636          * we'll hang the machine! */
6637         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6638
6639         if (val & LCPLL_POWER_DOWN_ALLOW) {
6640                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6641                 I915_WRITE(LCPLL_CTL, val);
6642                 POSTING_READ(LCPLL_CTL);
6643         }
6644
6645         val = I915_READ(D_COMP);
6646         val |= D_COMP_COMP_FORCE;
6647         val &= ~D_COMP_COMP_DISABLE;
6648         mutex_lock(&dev_priv->rps.hw_lock);
6649         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6650                 DRM_ERROR("Failed to enable D_COMP\n");
6651         mutex_unlock(&dev_priv->rps.hw_lock);
6652         POSTING_READ(D_COMP);
6653
6654         val = I915_READ(LCPLL_CTL);
6655         val &= ~LCPLL_PLL_DISABLE;
6656         I915_WRITE(LCPLL_CTL, val);
6657
6658         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6659                 DRM_ERROR("LCPLL not locked yet\n");
6660
6661         if (val & LCPLL_CD_SOURCE_FCLK) {
6662                 val = I915_READ(LCPLL_CTL);
6663                 val &= ~LCPLL_CD_SOURCE_FCLK;
6664                 I915_WRITE(LCPLL_CTL, val);
6665
6666                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6667                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6668                         DRM_ERROR("Switching back to LCPLL failed\n");
6669         }
6670
6671         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6672 }
6673
6674 void hsw_enable_pc8_work(struct work_struct *__work)
6675 {
6676         struct drm_i915_private *dev_priv =
6677                 container_of(to_delayed_work(__work), struct drm_i915_private,
6678                              pc8.enable_work);
6679         struct drm_device *dev = dev_priv->dev;
6680         uint32_t val;
6681
6682         WARN_ON(!HAS_PC8(dev));
6683
6684         if (dev_priv->pc8.enabled)
6685                 return;
6686
6687         DRM_DEBUG_KMS("Enabling package C8+\n");
6688
6689         dev_priv->pc8.enabled = true;
6690
6691         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6692                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6693                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6694                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6695         }
6696
6697         lpt_disable_clkout_dp(dev);
6698         hsw_pc8_disable_interrupts(dev);
6699         hsw_disable_lcpll(dev_priv, true, true);
6700
6701         intel_runtime_pm_put(dev_priv);
6702 }
6703
6704 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6705 {
6706         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6707         WARN(dev_priv->pc8.disable_count < 1,
6708              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6709
6710         dev_priv->pc8.disable_count--;
6711         if (dev_priv->pc8.disable_count != 0)
6712                 return;
6713
6714         schedule_delayed_work(&dev_priv->pc8.enable_work,
6715                               msecs_to_jiffies(i915.pc8_timeout));
6716 }
6717
6718 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6719 {
6720         struct drm_device *dev = dev_priv->dev;
6721         uint32_t val;
6722
6723         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6724         WARN(dev_priv->pc8.disable_count < 0,
6725              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6726
6727         dev_priv->pc8.disable_count++;
6728         if (dev_priv->pc8.disable_count != 1)
6729                 return;
6730
6731         WARN_ON(!HAS_PC8(dev));
6732
6733         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6734         if (!dev_priv->pc8.enabled)
6735                 return;
6736
6737         DRM_DEBUG_KMS("Disabling package C8+\n");
6738
6739         intel_runtime_pm_get(dev_priv);
6740
6741         hsw_restore_lcpll(dev_priv);
6742         hsw_pc8_restore_interrupts(dev);
6743         lpt_init_pch_refclk(dev);
6744
6745         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6746                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6747                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6748                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6749         }
6750
6751         intel_prepare_ddi(dev);
6752         i915_gem_init_swizzling(dev);
6753         mutex_lock(&dev_priv->rps.hw_lock);
6754         gen6_update_ring_freq(dev);
6755         mutex_unlock(&dev_priv->rps.hw_lock);
6756         dev_priv->pc8.enabled = false;
6757 }
6758
6759 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6760 {
6761         if (!HAS_PC8(dev_priv->dev))
6762                 return;
6763
6764         mutex_lock(&dev_priv->pc8.lock);
6765         __hsw_enable_package_c8(dev_priv);
6766         mutex_unlock(&dev_priv->pc8.lock);
6767 }
6768
6769 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6770 {
6771         if (!HAS_PC8(dev_priv->dev))
6772                 return;
6773
6774         mutex_lock(&dev_priv->pc8.lock);
6775         __hsw_disable_package_c8(dev_priv);
6776         mutex_unlock(&dev_priv->pc8.lock);
6777 }
6778
6779 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6780 {
6781         struct drm_device *dev = dev_priv->dev;
6782         struct intel_crtc *crtc;
6783         uint32_t val;
6784
6785         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6786                 if (crtc->base.enabled)
6787                         return false;
6788
6789         /* This case is still possible since we have the i915.disable_power_well
6790          * parameter and also the KVMr or something else might be requesting the
6791          * power well. */
6792         val = I915_READ(HSW_PWR_WELL_DRIVER);
6793         if (val != 0) {
6794                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6795                 return false;
6796         }
6797
6798         return true;
6799 }
6800
6801 /* Since we're called from modeset_global_resources there's no way to
6802  * symmetrically increase and decrease the refcount, so we use
6803  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6804  * or not.
6805  */
6806 static void hsw_update_package_c8(struct drm_device *dev)
6807 {
6808         struct drm_i915_private *dev_priv = dev->dev_private;
6809         bool allow;
6810
6811         if (!HAS_PC8(dev_priv->dev))
6812                 return;
6813
6814         if (!i915.enable_pc8)
6815                 return;
6816
6817         mutex_lock(&dev_priv->pc8.lock);
6818
6819         allow = hsw_can_enable_package_c8(dev_priv);
6820
6821         if (allow == dev_priv->pc8.requirements_met)
6822                 goto done;
6823
6824         dev_priv->pc8.requirements_met = allow;
6825
6826         if (allow)
6827                 __hsw_enable_package_c8(dev_priv);
6828         else
6829                 __hsw_disable_package_c8(dev_priv);
6830
6831 done:
6832         mutex_unlock(&dev_priv->pc8.lock);
6833 }
6834
6835 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6836 {
6837         if (!HAS_PC8(dev_priv->dev))
6838                 return;
6839
6840         mutex_lock(&dev_priv->pc8.lock);
6841         if (!dev_priv->pc8.gpu_idle) {
6842                 dev_priv->pc8.gpu_idle = true;
6843                 __hsw_enable_package_c8(dev_priv);
6844         }
6845         mutex_unlock(&dev_priv->pc8.lock);
6846 }
6847
6848 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6849 {
6850         if (!HAS_PC8(dev_priv->dev))
6851                 return;
6852
6853         mutex_lock(&dev_priv->pc8.lock);
6854         if (dev_priv->pc8.gpu_idle) {
6855                 dev_priv->pc8.gpu_idle = false;
6856                 __hsw_disable_package_c8(dev_priv);
6857         }
6858         mutex_unlock(&dev_priv->pc8.lock);
6859 }
6860
6861 #define for_each_power_domain(domain, mask)                             \
6862         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
6863                 if ((1 << (domain)) & (mask))
6864
6865 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6866                                             enum pipe pipe, bool pfit_enabled)
6867 {
6868         unsigned long mask;
6869         enum transcoder transcoder;
6870
6871         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6872
6873         mask = BIT(POWER_DOMAIN_PIPE(pipe));
6874         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6875         if (pfit_enabled)
6876                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6877
6878         return mask;
6879 }
6880
6881 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6882 {
6883         struct drm_i915_private *dev_priv = dev->dev_private;
6884
6885         if (dev_priv->power_domains.init_power_on == enable)
6886                 return;
6887
6888         if (enable)
6889                 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6890         else
6891                 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6892
6893         dev_priv->power_domains.init_power_on = enable;
6894 }
6895
6896 static void modeset_update_power_wells(struct drm_device *dev)
6897 {
6898         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6899         struct intel_crtc *crtc;
6900
6901         /*
6902          * First get all needed power domains, then put all unneeded, to avoid
6903          * any unnecessary toggling of the power wells.
6904          */
6905         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6906                 enum intel_display_power_domain domain;
6907
6908                 if (!crtc->base.enabled)
6909                         continue;
6910
6911                 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6912                                                 crtc->pipe,
6913                                                 crtc->config.pch_pfit.enabled);
6914
6915                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6916                         intel_display_power_get(dev, domain);
6917         }
6918
6919         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6920                 enum intel_display_power_domain domain;
6921
6922                 for_each_power_domain(domain, crtc->enabled_power_domains)
6923                         intel_display_power_put(dev, domain);
6924
6925                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6926         }
6927
6928         intel_display_set_init_power(dev, false);
6929 }
6930
6931 static void haswell_modeset_global_resources(struct drm_device *dev)
6932 {
6933         modeset_update_power_wells(dev);
6934         hsw_update_package_c8(dev);
6935 }
6936
6937 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6938                                  int x, int y,
6939                                  struct drm_framebuffer *fb)
6940 {
6941         struct drm_device *dev = crtc->dev;
6942         struct drm_i915_private *dev_priv = dev->dev_private;
6943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6944         int plane = intel_crtc->plane;
6945         int ret;
6946
6947         if (!intel_ddi_pll_select(intel_crtc))
6948                 return -EINVAL;
6949         intel_ddi_pll_enable(intel_crtc);
6950
6951         if (intel_crtc->config.has_dp_encoder)
6952                 intel_dp_set_m_n(intel_crtc);
6953
6954         intel_crtc->lowfreq_avail = false;
6955
6956         intel_set_pipe_timings(intel_crtc);
6957
6958         if (intel_crtc->config.has_pch_encoder) {
6959                 intel_cpu_transcoder_set_m_n(intel_crtc,
6960                                              &intel_crtc->config.fdi_m_n);
6961         }
6962
6963         haswell_set_pipeconf(crtc);
6964
6965         intel_set_pipe_csc(crtc);
6966
6967         /* Set up the display plane register */
6968         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6969         POSTING_READ(DSPCNTR(plane));
6970
6971         ret = intel_pipe_set_base(crtc, x, y, fb);
6972
6973         return ret;
6974 }
6975
6976 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6977                                     struct intel_crtc_config *pipe_config)
6978 {
6979         struct drm_device *dev = crtc->base.dev;
6980         struct drm_i915_private *dev_priv = dev->dev_private;
6981         enum intel_display_power_domain pfit_domain;
6982         uint32_t tmp;
6983
6984         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6985         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6986
6987         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6988         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6989                 enum pipe trans_edp_pipe;
6990                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6991                 default:
6992                         WARN(1, "unknown pipe linked to edp transcoder\n");
6993                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6994                 case TRANS_DDI_EDP_INPUT_A_ON:
6995                         trans_edp_pipe = PIPE_A;
6996                         break;
6997                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6998                         trans_edp_pipe = PIPE_B;
6999                         break;
7000                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7001                         trans_edp_pipe = PIPE_C;
7002                         break;
7003                 }
7004
7005                 if (trans_edp_pipe == crtc->pipe)
7006                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7007         }
7008
7009         if (!intel_display_power_enabled(dev,
7010                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7011                 return false;
7012
7013         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7014         if (!(tmp & PIPECONF_ENABLE))
7015                 return false;
7016
7017         /*
7018          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7019          * DDI E. So just check whether this pipe is wired to DDI E and whether
7020          * the PCH transcoder is on.
7021          */
7022         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7023         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7024             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7025                 pipe_config->has_pch_encoder = true;
7026
7027                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7028                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7029                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7030
7031                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7032         }
7033
7034         intel_get_pipe_timings(crtc, pipe_config);
7035
7036         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7037         if (intel_display_power_enabled(dev, pfit_domain))
7038                 ironlake_get_pfit_config(crtc, pipe_config);
7039
7040         if (IS_HASWELL(dev))
7041                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7042                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7043
7044         pipe_config->pixel_multiplier = 1;
7045
7046         return true;
7047 }
7048
7049 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7050                                int x, int y,
7051                                struct drm_framebuffer *fb)
7052 {
7053         struct drm_device *dev = crtc->dev;
7054         struct drm_i915_private *dev_priv = dev->dev_private;
7055         struct intel_encoder *encoder;
7056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7057         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7058         int pipe = intel_crtc->pipe;
7059         int ret;
7060
7061         drm_vblank_pre_modeset(dev, pipe);
7062
7063         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7064
7065         drm_vblank_post_modeset(dev, pipe);
7066
7067         if (ret != 0)
7068                 return ret;
7069
7070         for_each_encoder_on_crtc(dev, crtc, encoder) {
7071                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7072                         encoder->base.base.id,
7073                         drm_get_encoder_name(&encoder->base),
7074                         mode->base.id, mode->name);
7075                 encoder->mode_set(encoder);
7076         }
7077
7078         return 0;
7079 }
7080
7081 static struct {
7082         int clock;
7083         u32 config;
7084 } hdmi_audio_clock[] = {
7085         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7086         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7087         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7088         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7089         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7090         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7091         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7092         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7093         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7094         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7095 };
7096
7097 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7098 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7099 {
7100         int i;
7101
7102         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7103                 if (mode->clock == hdmi_audio_clock[i].clock)
7104                         break;
7105         }
7106
7107         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7108                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7109                 i = 1;
7110         }
7111
7112         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7113                       hdmi_audio_clock[i].clock,
7114                       hdmi_audio_clock[i].config);
7115
7116         return hdmi_audio_clock[i].config;
7117 }
7118
7119 static bool intel_eld_uptodate(struct drm_connector *connector,
7120                                int reg_eldv, uint32_t bits_eldv,
7121                                int reg_elda, uint32_t bits_elda,
7122                                int reg_edid)
7123 {
7124         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7125         uint8_t *eld = connector->eld;
7126         uint32_t i;
7127
7128         i = I915_READ(reg_eldv);
7129         i &= bits_eldv;
7130
7131         if (!eld[0])
7132                 return !i;
7133
7134         if (!i)
7135                 return false;
7136
7137         i = I915_READ(reg_elda);
7138         i &= ~bits_elda;
7139         I915_WRITE(reg_elda, i);
7140
7141         for (i = 0; i < eld[2]; i++)
7142                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7143                         return false;
7144
7145         return true;
7146 }
7147
7148 static void g4x_write_eld(struct drm_connector *connector,
7149                           struct drm_crtc *crtc,
7150                           struct drm_display_mode *mode)
7151 {
7152         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7153         uint8_t *eld = connector->eld;
7154         uint32_t eldv;
7155         uint32_t len;
7156         uint32_t i;
7157
7158         i = I915_READ(G4X_AUD_VID_DID);
7159
7160         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7161                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7162         else
7163                 eldv = G4X_ELDV_DEVCTG;
7164
7165         if (intel_eld_uptodate(connector,
7166                                G4X_AUD_CNTL_ST, eldv,
7167                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7168                                G4X_HDMIW_HDMIEDID))
7169                 return;
7170
7171         i = I915_READ(G4X_AUD_CNTL_ST);
7172         i &= ~(eldv | G4X_ELD_ADDR);
7173         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7174         I915_WRITE(G4X_AUD_CNTL_ST, i);
7175
7176         if (!eld[0])
7177                 return;
7178
7179         len = min_t(uint8_t, eld[2], len);
7180         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7181         for (i = 0; i < len; i++)
7182                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7183
7184         i = I915_READ(G4X_AUD_CNTL_ST);
7185         i |= eldv;
7186         I915_WRITE(G4X_AUD_CNTL_ST, i);
7187 }
7188
7189 static void haswell_write_eld(struct drm_connector *connector,
7190                               struct drm_crtc *crtc,
7191                               struct drm_display_mode *mode)
7192 {
7193         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7194         uint8_t *eld = connector->eld;
7195         struct drm_device *dev = crtc->dev;
7196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7197         uint32_t eldv;
7198         uint32_t i;
7199         int len;
7200         int pipe = to_intel_crtc(crtc)->pipe;
7201         int tmp;
7202
7203         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7204         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7205         int aud_config = HSW_AUD_CFG(pipe);
7206         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7207
7208
7209         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7210
7211         /* Audio output enable */
7212         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7213         tmp = I915_READ(aud_cntrl_st2);
7214         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7215         I915_WRITE(aud_cntrl_st2, tmp);
7216
7217         /* Wait for 1 vertical blank */
7218         intel_wait_for_vblank(dev, pipe);
7219
7220         /* Set ELD valid state */
7221         tmp = I915_READ(aud_cntrl_st2);
7222         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7223         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7224         I915_WRITE(aud_cntrl_st2, tmp);
7225         tmp = I915_READ(aud_cntrl_st2);
7226         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7227
7228         /* Enable HDMI mode */
7229         tmp = I915_READ(aud_config);
7230         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7231         /* clear N_programing_enable and N_value_index */
7232         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7233         I915_WRITE(aud_config, tmp);
7234
7235         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7236
7237         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7238         intel_crtc->eld_vld = true;
7239
7240         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7241                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7242                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7243                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7244         } else {
7245                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7246         }
7247
7248         if (intel_eld_uptodate(connector,
7249                                aud_cntrl_st2, eldv,
7250                                aud_cntl_st, IBX_ELD_ADDRESS,
7251                                hdmiw_hdmiedid))
7252                 return;
7253
7254         i = I915_READ(aud_cntrl_st2);
7255         i &= ~eldv;
7256         I915_WRITE(aud_cntrl_st2, i);
7257
7258         if (!eld[0])
7259                 return;
7260
7261         i = I915_READ(aud_cntl_st);
7262         i &= ~IBX_ELD_ADDRESS;
7263         I915_WRITE(aud_cntl_st, i);
7264         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7265         DRM_DEBUG_DRIVER("port num:%d\n", i);
7266
7267         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7268         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7269         for (i = 0; i < len; i++)
7270                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7271
7272         i = I915_READ(aud_cntrl_st2);
7273         i |= eldv;
7274         I915_WRITE(aud_cntrl_st2, i);
7275
7276 }
7277
7278 static void ironlake_write_eld(struct drm_connector *connector,
7279                                struct drm_crtc *crtc,
7280                                struct drm_display_mode *mode)
7281 {
7282         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7283         uint8_t *eld = connector->eld;
7284         uint32_t eldv;
7285         uint32_t i;
7286         int len;
7287         int hdmiw_hdmiedid;
7288         int aud_config;
7289         int aud_cntl_st;
7290         int aud_cntrl_st2;
7291         int pipe = to_intel_crtc(crtc)->pipe;
7292
7293         if (HAS_PCH_IBX(connector->dev)) {
7294                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7295                 aud_config = IBX_AUD_CFG(pipe);
7296                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7297                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7298         } else if (IS_VALLEYVIEW(connector->dev)) {
7299                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7300                 aud_config = VLV_AUD_CFG(pipe);
7301                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7302                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7303         } else {
7304                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7305                 aud_config = CPT_AUD_CFG(pipe);
7306                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7307                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7308         }
7309
7310         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7311
7312         if (IS_VALLEYVIEW(connector->dev))  {
7313                 struct intel_encoder *intel_encoder;
7314                 struct intel_digital_port *intel_dig_port;
7315
7316                 intel_encoder = intel_attached_encoder(connector);
7317                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7318                 i = intel_dig_port->port;
7319         } else {
7320                 i = I915_READ(aud_cntl_st);
7321                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7322                 /* DIP_Port_Select, 0x1 = PortB */
7323         }
7324
7325         if (!i) {
7326                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7327                 /* operate blindly on all ports */
7328                 eldv = IBX_ELD_VALIDB;
7329                 eldv |= IBX_ELD_VALIDB << 4;
7330                 eldv |= IBX_ELD_VALIDB << 8;
7331         } else {
7332                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7333                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7334         }
7335
7336         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7337                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7338                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7339                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7340         } else {
7341                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7342         }
7343
7344         if (intel_eld_uptodate(connector,
7345                                aud_cntrl_st2, eldv,
7346                                aud_cntl_st, IBX_ELD_ADDRESS,
7347                                hdmiw_hdmiedid))
7348                 return;
7349
7350         i = I915_READ(aud_cntrl_st2);
7351         i &= ~eldv;
7352         I915_WRITE(aud_cntrl_st2, i);
7353
7354         if (!eld[0])
7355                 return;
7356
7357         i = I915_READ(aud_cntl_st);
7358         i &= ~IBX_ELD_ADDRESS;
7359         I915_WRITE(aud_cntl_st, i);
7360
7361         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7362         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7363         for (i = 0; i < len; i++)
7364                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7365
7366         i = I915_READ(aud_cntrl_st2);
7367         i |= eldv;
7368         I915_WRITE(aud_cntrl_st2, i);
7369 }
7370
7371 void intel_write_eld(struct drm_encoder *encoder,
7372                      struct drm_display_mode *mode)
7373 {
7374         struct drm_crtc *crtc = encoder->crtc;
7375         struct drm_connector *connector;
7376         struct drm_device *dev = encoder->dev;
7377         struct drm_i915_private *dev_priv = dev->dev_private;
7378
7379         connector = drm_select_eld(encoder, mode);
7380         if (!connector)
7381                 return;
7382
7383         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7384                          connector->base.id,
7385                          drm_get_connector_name(connector),
7386                          connector->encoder->base.id,
7387                          drm_get_encoder_name(connector->encoder));
7388
7389         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7390
7391         if (dev_priv->display.write_eld)
7392                 dev_priv->display.write_eld(connector, crtc, mode);
7393 }
7394
7395 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7396 {
7397         struct drm_device *dev = crtc->dev;
7398         struct drm_i915_private *dev_priv = dev->dev_private;
7399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7400         bool visible = base != 0;
7401         u32 cntl;
7402
7403         if (intel_crtc->cursor_visible == visible)
7404                 return;
7405
7406         cntl = I915_READ(_CURACNTR);
7407         if (visible) {
7408                 /* On these chipsets we can only modify the base whilst
7409                  * the cursor is disabled.
7410                  */
7411                 I915_WRITE(_CURABASE, base);
7412
7413                 cntl &= ~(CURSOR_FORMAT_MASK);
7414                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7415                 cntl |= CURSOR_ENABLE |
7416                         CURSOR_GAMMA_ENABLE |
7417                         CURSOR_FORMAT_ARGB;
7418         } else
7419                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7420         I915_WRITE(_CURACNTR, cntl);
7421
7422         intel_crtc->cursor_visible = visible;
7423 }
7424
7425 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7426 {
7427         struct drm_device *dev = crtc->dev;
7428         struct drm_i915_private *dev_priv = dev->dev_private;
7429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7430         int pipe = intel_crtc->pipe;
7431         bool visible = base != 0;
7432
7433         if (intel_crtc->cursor_visible != visible) {
7434                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7435                 if (base) {
7436                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7437                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7438                         cntl |= pipe << 28; /* Connect to correct pipe */
7439                 } else {
7440                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7441                         cntl |= CURSOR_MODE_DISABLE;
7442                 }
7443                 I915_WRITE(CURCNTR(pipe), cntl);
7444
7445                 intel_crtc->cursor_visible = visible;
7446         }
7447         /* and commit changes on next vblank */
7448         POSTING_READ(CURCNTR(pipe));
7449         I915_WRITE(CURBASE(pipe), base);
7450         POSTING_READ(CURBASE(pipe));
7451 }
7452
7453 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7454 {
7455         struct drm_device *dev = crtc->dev;
7456         struct drm_i915_private *dev_priv = dev->dev_private;
7457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7458         int pipe = intel_crtc->pipe;
7459         bool visible = base != 0;
7460
7461         if (intel_crtc->cursor_visible != visible) {
7462                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7463                 if (base) {
7464                         cntl &= ~CURSOR_MODE;
7465                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7466                 } else {
7467                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7468                         cntl |= CURSOR_MODE_DISABLE;
7469                 }
7470                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7471                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7472                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7473                 }
7474                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7475
7476                 intel_crtc->cursor_visible = visible;
7477         }
7478         /* and commit changes on next vblank */
7479         POSTING_READ(CURCNTR_IVB(pipe));
7480         I915_WRITE(CURBASE_IVB(pipe), base);
7481         POSTING_READ(CURBASE_IVB(pipe));
7482 }
7483
7484 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7485 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7486                                      bool on)
7487 {
7488         struct drm_device *dev = crtc->dev;
7489         struct drm_i915_private *dev_priv = dev->dev_private;
7490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7491         int pipe = intel_crtc->pipe;
7492         int x = intel_crtc->cursor_x;
7493         int y = intel_crtc->cursor_y;
7494         u32 base = 0, pos = 0;
7495         bool visible;
7496
7497         if (on)
7498                 base = intel_crtc->cursor_addr;
7499
7500         if (x >= intel_crtc->config.pipe_src_w)
7501                 base = 0;
7502
7503         if (y >= intel_crtc->config.pipe_src_h)
7504                 base = 0;
7505
7506         if (x < 0) {
7507                 if (x + intel_crtc->cursor_width <= 0)
7508                         base = 0;
7509
7510                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7511                 x = -x;
7512         }
7513         pos |= x << CURSOR_X_SHIFT;
7514
7515         if (y < 0) {
7516                 if (y + intel_crtc->cursor_height <= 0)
7517                         base = 0;
7518
7519                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7520                 y = -y;
7521         }
7522         pos |= y << CURSOR_Y_SHIFT;
7523
7524         visible = base != 0;
7525         if (!visible && !intel_crtc->cursor_visible)
7526                 return;
7527
7528         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7529                 I915_WRITE(CURPOS_IVB(pipe), pos);
7530                 ivb_update_cursor(crtc, base);
7531         } else {
7532                 I915_WRITE(CURPOS(pipe), pos);
7533                 if (IS_845G(dev) || IS_I865G(dev))
7534                         i845_update_cursor(crtc, base);
7535                 else
7536                         i9xx_update_cursor(crtc, base);
7537         }
7538 }
7539
7540 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7541                                  struct drm_file *file,
7542                                  uint32_t handle,
7543                                  uint32_t width, uint32_t height)
7544 {
7545         struct drm_device *dev = crtc->dev;
7546         struct drm_i915_private *dev_priv = dev->dev_private;
7547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7548         struct drm_i915_gem_object *obj;
7549         uint32_t addr;
7550         int ret;
7551
7552         /* if we want to turn off the cursor ignore width and height */
7553         if (!handle) {
7554                 DRM_DEBUG_KMS("cursor off\n");
7555                 addr = 0;
7556                 obj = NULL;
7557                 mutex_lock(&dev->struct_mutex);
7558                 goto finish;
7559         }
7560
7561         /* Currently we only support 64x64 cursors */
7562         if (width != 64 || height != 64) {
7563                 DRM_ERROR("we currently only support 64x64 cursors\n");
7564                 return -EINVAL;
7565         }
7566
7567         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7568         if (&obj->base == NULL)
7569                 return -ENOENT;
7570
7571         if (obj->base.size < width * height * 4) {
7572                 DRM_ERROR("buffer is to small\n");
7573                 ret = -ENOMEM;
7574                 goto fail;
7575         }
7576
7577         /* we only need to pin inside GTT if cursor is non-phy */
7578         mutex_lock(&dev->struct_mutex);
7579         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7580                 unsigned alignment;
7581
7582                 if (obj->tiling_mode) {
7583                         DRM_ERROR("cursor cannot be tiled\n");
7584                         ret = -EINVAL;
7585                         goto fail_locked;
7586                 }
7587
7588                 /* Note that the w/a also requires 2 PTE of padding following
7589                  * the bo. We currently fill all unused PTE with the shadow
7590                  * page and so we should always have valid PTE following the
7591                  * cursor preventing the VT-d warning.
7592                  */
7593                 alignment = 0;
7594                 if (need_vtd_wa(dev))
7595                         alignment = 64*1024;
7596
7597                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7598                 if (ret) {
7599                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7600                         goto fail_locked;
7601                 }
7602
7603                 ret = i915_gem_object_put_fence(obj);
7604                 if (ret) {
7605                         DRM_ERROR("failed to release fence for cursor");
7606                         goto fail_unpin;
7607                 }
7608
7609                 addr = i915_gem_obj_ggtt_offset(obj);
7610         } else {
7611                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7612                 ret = i915_gem_attach_phys_object(dev, obj,
7613                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7614                                                   align);
7615                 if (ret) {
7616                         DRM_ERROR("failed to attach phys object\n");
7617                         goto fail_locked;
7618                 }
7619                 addr = obj->phys_obj->handle->busaddr;
7620         }
7621
7622         if (IS_GEN2(dev))
7623                 I915_WRITE(CURSIZE, (height << 12) | width);
7624
7625  finish:
7626         if (intel_crtc->cursor_bo) {
7627                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7628                         if (intel_crtc->cursor_bo != obj)
7629                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7630                 } else
7631                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7632                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7633         }
7634
7635         mutex_unlock(&dev->struct_mutex);
7636
7637         intel_crtc->cursor_addr = addr;
7638         intel_crtc->cursor_bo = obj;
7639         intel_crtc->cursor_width = width;
7640         intel_crtc->cursor_height = height;
7641
7642         if (intel_crtc->active)
7643                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7644
7645         return 0;
7646 fail_unpin:
7647         i915_gem_object_unpin_from_display_plane(obj);
7648 fail_locked:
7649         mutex_unlock(&dev->struct_mutex);
7650 fail:
7651         drm_gem_object_unreference_unlocked(&obj->base);
7652         return ret;
7653 }
7654
7655 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7656 {
7657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7658
7659         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7660         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7661
7662         if (intel_crtc->active)
7663                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7664
7665         return 0;
7666 }
7667
7668 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7669                                  u16 *blue, uint32_t start, uint32_t size)
7670 {
7671         int end = (start + size > 256) ? 256 : start + size, i;
7672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7673
7674         for (i = start; i < end; i++) {
7675                 intel_crtc->lut_r[i] = red[i] >> 8;
7676                 intel_crtc->lut_g[i] = green[i] >> 8;
7677                 intel_crtc->lut_b[i] = blue[i] >> 8;
7678         }
7679
7680         intel_crtc_load_lut(crtc);
7681 }
7682
7683 /* VESA 640x480x72Hz mode to set on the pipe */
7684 static struct drm_display_mode load_detect_mode = {
7685         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7686                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7687 };
7688
7689 static int intel_framebuffer_init(struct drm_device *dev,
7690                                   struct intel_framebuffer *ifb,
7691                                   struct drm_mode_fb_cmd2 *mode_cmd,
7692                                   struct drm_i915_gem_object *obj);
7693
7694 struct drm_framebuffer *
7695 __intel_framebuffer_create(struct drm_device *dev,
7696                            struct drm_mode_fb_cmd2 *mode_cmd,
7697                            struct drm_i915_gem_object *obj)
7698 {
7699         struct intel_framebuffer *intel_fb;
7700         int ret;
7701
7702         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7703         if (!intel_fb) {
7704                 drm_gem_object_unreference_unlocked(&obj->base);
7705                 return ERR_PTR(-ENOMEM);
7706         }
7707
7708         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7709         if (ret)
7710                 goto err;
7711
7712         return &intel_fb->base;
7713 err:
7714         drm_gem_object_unreference_unlocked(&obj->base);
7715         kfree(intel_fb);
7716
7717         return ERR_PTR(ret);
7718 }
7719
7720 struct drm_framebuffer *
7721 intel_framebuffer_create(struct drm_device *dev,
7722                          struct drm_mode_fb_cmd2 *mode_cmd,
7723                          struct drm_i915_gem_object *obj)
7724 {
7725         struct drm_framebuffer *fb;
7726         int ret;
7727
7728         ret = i915_mutex_lock_interruptible(dev);
7729         if (ret)
7730                 return ERR_PTR(ret);
7731         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7732         mutex_unlock(&dev->struct_mutex);
7733
7734         return fb;
7735 }
7736
7737 static u32
7738 intel_framebuffer_pitch_for_width(int width, int bpp)
7739 {
7740         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7741         return ALIGN(pitch, 64);
7742 }
7743
7744 static u32
7745 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7746 {
7747         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7748         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7749 }
7750
7751 static struct drm_framebuffer *
7752 intel_framebuffer_create_for_mode(struct drm_device *dev,
7753                                   struct drm_display_mode *mode,
7754                                   int depth, int bpp)
7755 {
7756         struct drm_i915_gem_object *obj;
7757         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7758
7759         obj = i915_gem_alloc_object(dev,
7760                                     intel_framebuffer_size_for_mode(mode, bpp));
7761         if (obj == NULL)
7762                 return ERR_PTR(-ENOMEM);
7763
7764         mode_cmd.width = mode->hdisplay;
7765         mode_cmd.height = mode->vdisplay;
7766         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7767                                                                 bpp);
7768         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7769
7770         return intel_framebuffer_create(dev, &mode_cmd, obj);
7771 }
7772
7773 static struct drm_framebuffer *
7774 mode_fits_in_fbdev(struct drm_device *dev,
7775                    struct drm_display_mode *mode)
7776 {
7777 #ifdef CONFIG_DRM_I915_FBDEV
7778         struct drm_i915_private *dev_priv = dev->dev_private;
7779         struct drm_i915_gem_object *obj;
7780         struct drm_framebuffer *fb;
7781
7782         if (dev_priv->fbdev == NULL)
7783                 return NULL;
7784
7785         obj = dev_priv->fbdev->fb->obj;
7786         if (obj == NULL)
7787                 return NULL;
7788
7789         fb = &dev_priv->fbdev->fb->base;
7790         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7791                                                                fb->bits_per_pixel))
7792                 return NULL;
7793
7794         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7795                 return NULL;
7796
7797         return fb;
7798 #else
7799         return NULL;
7800 #endif
7801 }
7802
7803 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7804                                 struct drm_display_mode *mode,
7805                                 struct intel_load_detect_pipe *old)
7806 {
7807         struct intel_crtc *intel_crtc;
7808         struct intel_encoder *intel_encoder =
7809                 intel_attached_encoder(connector);
7810         struct drm_crtc *possible_crtc;
7811         struct drm_encoder *encoder = &intel_encoder->base;
7812         struct drm_crtc *crtc = NULL;
7813         struct drm_device *dev = encoder->dev;
7814         struct drm_framebuffer *fb;
7815         int i = -1;
7816
7817         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7818                       connector->base.id, drm_get_connector_name(connector),
7819                       encoder->base.id, drm_get_encoder_name(encoder));
7820
7821         /*
7822          * Algorithm gets a little messy:
7823          *
7824          *   - if the connector already has an assigned crtc, use it (but make
7825          *     sure it's on first)
7826          *
7827          *   - try to find the first unused crtc that can drive this connector,
7828          *     and use that if we find one
7829          */
7830
7831         /* See if we already have a CRTC for this connector */
7832         if (encoder->crtc) {
7833                 crtc = encoder->crtc;
7834
7835                 mutex_lock(&crtc->mutex);
7836
7837                 old->dpms_mode = connector->dpms;
7838                 old->load_detect_temp = false;
7839
7840                 /* Make sure the crtc and connector are running */
7841                 if (connector->dpms != DRM_MODE_DPMS_ON)
7842                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7843
7844                 return true;
7845         }
7846
7847         /* Find an unused one (if possible) */
7848         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7849                 i++;
7850                 if (!(encoder->possible_crtcs & (1 << i)))
7851                         continue;
7852                 if (!possible_crtc->enabled) {
7853                         crtc = possible_crtc;
7854                         break;
7855                 }
7856         }
7857
7858         /*
7859          * If we didn't find an unused CRTC, don't use any.
7860          */
7861         if (!crtc) {
7862                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7863                 return false;
7864         }
7865
7866         mutex_lock(&crtc->mutex);
7867         intel_encoder->new_crtc = to_intel_crtc(crtc);
7868         to_intel_connector(connector)->new_encoder = intel_encoder;
7869
7870         intel_crtc = to_intel_crtc(crtc);
7871         intel_crtc->new_enabled = true;
7872         intel_crtc->new_config = &intel_crtc->config;
7873         old->dpms_mode = connector->dpms;
7874         old->load_detect_temp = true;
7875         old->release_fb = NULL;
7876
7877         if (!mode)
7878                 mode = &load_detect_mode;
7879
7880         /* We need a framebuffer large enough to accommodate all accesses
7881          * that the plane may generate whilst we perform load detection.
7882          * We can not rely on the fbcon either being present (we get called
7883          * during its initialisation to detect all boot displays, or it may
7884          * not even exist) or that it is large enough to satisfy the
7885          * requested mode.
7886          */
7887         fb = mode_fits_in_fbdev(dev, mode);
7888         if (fb == NULL) {
7889                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7890                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7891                 old->release_fb = fb;
7892         } else
7893                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7894         if (IS_ERR(fb)) {
7895                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7896                 goto fail;
7897         }
7898
7899         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7900                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7901                 if (old->release_fb)
7902                         old->release_fb->funcs->destroy(old->release_fb);
7903                 goto fail;
7904         }
7905
7906         /* let the connector get through one full cycle before testing */
7907         intel_wait_for_vblank(dev, intel_crtc->pipe);
7908         return true;
7909
7910  fail:
7911         intel_crtc->new_enabled = crtc->enabled;
7912         if (intel_crtc->new_enabled)
7913                 intel_crtc->new_config = &intel_crtc->config;
7914         else
7915                 intel_crtc->new_config = NULL;
7916         mutex_unlock(&crtc->mutex);
7917         return false;
7918 }
7919
7920 void intel_release_load_detect_pipe(struct drm_connector *connector,
7921                                     struct intel_load_detect_pipe *old)
7922 {
7923         struct intel_encoder *intel_encoder =
7924                 intel_attached_encoder(connector);
7925         struct drm_encoder *encoder = &intel_encoder->base;
7926         struct drm_crtc *crtc = encoder->crtc;
7927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7928
7929         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7930                       connector->base.id, drm_get_connector_name(connector),
7931                       encoder->base.id, drm_get_encoder_name(encoder));
7932
7933         if (old->load_detect_temp) {
7934                 to_intel_connector(connector)->new_encoder = NULL;
7935                 intel_encoder->new_crtc = NULL;
7936                 intel_crtc->new_enabled = false;
7937                 intel_crtc->new_config = NULL;
7938                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7939
7940                 if (old->release_fb) {
7941                         drm_framebuffer_unregister_private(old->release_fb);
7942                         drm_framebuffer_unreference(old->release_fb);
7943                 }
7944
7945                 mutex_unlock(&crtc->mutex);
7946                 return;
7947         }
7948
7949         /* Switch crtc and encoder back off if necessary */
7950         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7951                 connector->funcs->dpms(connector, old->dpms_mode);
7952
7953         mutex_unlock(&crtc->mutex);
7954 }
7955
7956 static int i9xx_pll_refclk(struct drm_device *dev,
7957                            const struct intel_crtc_config *pipe_config)
7958 {
7959         struct drm_i915_private *dev_priv = dev->dev_private;
7960         u32 dpll = pipe_config->dpll_hw_state.dpll;
7961
7962         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7963                 return dev_priv->vbt.lvds_ssc_freq;
7964         else if (HAS_PCH_SPLIT(dev))
7965                 return 120000;
7966         else if (!IS_GEN2(dev))
7967                 return 96000;
7968         else
7969                 return 48000;
7970 }
7971
7972 /* Returns the clock of the currently programmed mode of the given pipe. */
7973 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7974                                 struct intel_crtc_config *pipe_config)
7975 {
7976         struct drm_device *dev = crtc->base.dev;
7977         struct drm_i915_private *dev_priv = dev->dev_private;
7978         int pipe = pipe_config->cpu_transcoder;
7979         u32 dpll = pipe_config->dpll_hw_state.dpll;
7980         u32 fp;
7981         intel_clock_t clock;
7982         int refclk = i9xx_pll_refclk(dev, pipe_config);
7983
7984         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7985                 fp = pipe_config->dpll_hw_state.fp0;
7986         else
7987                 fp = pipe_config->dpll_hw_state.fp1;
7988
7989         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7990         if (IS_PINEVIEW(dev)) {
7991                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7992                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7993         } else {
7994                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7995                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7996         }
7997
7998         if (!IS_GEN2(dev)) {
7999                 if (IS_PINEVIEW(dev))
8000                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8001                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8002                 else
8003                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8004                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8005
8006                 switch (dpll & DPLL_MODE_MASK) {
8007                 case DPLLB_MODE_DAC_SERIAL:
8008                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8009                                 5 : 10;
8010                         break;
8011                 case DPLLB_MODE_LVDS:
8012                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8013                                 7 : 14;
8014                         break;
8015                 default:
8016                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8017                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8018                         return;
8019                 }
8020
8021                 if (IS_PINEVIEW(dev))
8022                         pineview_clock(refclk, &clock);
8023                 else
8024                         i9xx_clock(refclk, &clock);
8025         } else {
8026                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8027                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8028
8029                 if (is_lvds) {
8030                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8031                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8032
8033                         if (lvds & LVDS_CLKB_POWER_UP)
8034                                 clock.p2 = 7;
8035                         else
8036                                 clock.p2 = 14;
8037                 } else {
8038                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8039                                 clock.p1 = 2;
8040                         else {
8041                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8042                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8043                         }
8044                         if (dpll & PLL_P2_DIVIDE_BY_4)
8045                                 clock.p2 = 4;
8046                         else
8047                                 clock.p2 = 2;
8048                 }
8049
8050                 i9xx_clock(refclk, &clock);
8051         }
8052
8053         /*
8054          * This value includes pixel_multiplier. We will use
8055          * port_clock to compute adjusted_mode.crtc_clock in the
8056          * encoder's get_config() function.
8057          */
8058         pipe_config->port_clock = clock.dot;
8059 }
8060
8061 int intel_dotclock_calculate(int link_freq,
8062                              const struct intel_link_m_n *m_n)
8063 {
8064         /*
8065          * The calculation for the data clock is:
8066          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8067          * But we want to avoid losing precison if possible, so:
8068          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8069          *
8070          * and the link clock is simpler:
8071          * link_clock = (m * link_clock) / n
8072          */
8073
8074         if (!m_n->link_n)
8075                 return 0;
8076
8077         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8078 }
8079
8080 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8081                                    struct intel_crtc_config *pipe_config)
8082 {
8083         struct drm_device *dev = crtc->base.dev;
8084
8085         /* read out port_clock from the DPLL */
8086         i9xx_crtc_clock_get(crtc, pipe_config);
8087
8088         /*
8089          * This value does not include pixel_multiplier.
8090          * We will check that port_clock and adjusted_mode.crtc_clock
8091          * agree once we know their relationship in the encoder's
8092          * get_config() function.
8093          */
8094         pipe_config->adjusted_mode.crtc_clock =
8095                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8096                                          &pipe_config->fdi_m_n);
8097 }
8098
8099 /** Returns the currently programmed mode of the given pipe. */
8100 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8101                                              struct drm_crtc *crtc)
8102 {
8103         struct drm_i915_private *dev_priv = dev->dev_private;
8104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8105         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8106         struct drm_display_mode *mode;
8107         struct intel_crtc_config pipe_config;
8108         int htot = I915_READ(HTOTAL(cpu_transcoder));
8109         int hsync = I915_READ(HSYNC(cpu_transcoder));
8110         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8111         int vsync = I915_READ(VSYNC(cpu_transcoder));
8112         enum pipe pipe = intel_crtc->pipe;
8113
8114         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8115         if (!mode)
8116                 return NULL;
8117
8118         /*
8119          * Construct a pipe_config sufficient for getting the clock info
8120          * back out of crtc_clock_get.
8121          *
8122          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8123          * to use a real value here instead.
8124          */
8125         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8126         pipe_config.pixel_multiplier = 1;
8127         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8128         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8129         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8130         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8131
8132         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8133         mode->hdisplay = (htot & 0xffff) + 1;
8134         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8135         mode->hsync_start = (hsync & 0xffff) + 1;
8136         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8137         mode->vdisplay = (vtot & 0xffff) + 1;
8138         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8139         mode->vsync_start = (vsync & 0xffff) + 1;
8140         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8141
8142         drm_mode_set_name(mode);
8143
8144         return mode;
8145 }
8146
8147 static void intel_increase_pllclock(struct drm_crtc *crtc)
8148 {
8149         struct drm_device *dev = crtc->dev;
8150         drm_i915_private_t *dev_priv = dev->dev_private;
8151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8152         int pipe = intel_crtc->pipe;
8153         int dpll_reg = DPLL(pipe);
8154         int dpll;
8155
8156         if (HAS_PCH_SPLIT(dev))
8157                 return;
8158
8159         if (!dev_priv->lvds_downclock_avail)
8160                 return;
8161
8162         dpll = I915_READ(dpll_reg);
8163         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8164                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8165
8166                 assert_panel_unlocked(dev_priv, pipe);
8167
8168                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8169                 I915_WRITE(dpll_reg, dpll);
8170                 intel_wait_for_vblank(dev, pipe);
8171
8172                 dpll = I915_READ(dpll_reg);
8173                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8174                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8175         }
8176 }
8177
8178 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8179 {
8180         struct drm_device *dev = crtc->dev;
8181         drm_i915_private_t *dev_priv = dev->dev_private;
8182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8183
8184         if (HAS_PCH_SPLIT(dev))
8185                 return;
8186
8187         if (!dev_priv->lvds_downclock_avail)
8188                 return;
8189
8190         /*
8191          * Since this is called by a timer, we should never get here in
8192          * the manual case.
8193          */
8194         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8195                 int pipe = intel_crtc->pipe;
8196                 int dpll_reg = DPLL(pipe);
8197                 int dpll;
8198
8199                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8200
8201                 assert_panel_unlocked(dev_priv, pipe);
8202
8203                 dpll = I915_READ(dpll_reg);
8204                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8205                 I915_WRITE(dpll_reg, dpll);
8206                 intel_wait_for_vblank(dev, pipe);
8207                 dpll = I915_READ(dpll_reg);
8208                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8209                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8210         }
8211
8212 }
8213
8214 void intel_mark_busy(struct drm_device *dev)
8215 {
8216         struct drm_i915_private *dev_priv = dev->dev_private;
8217
8218         hsw_package_c8_gpu_busy(dev_priv);
8219         i915_update_gfx_val(dev_priv);
8220 }
8221
8222 void intel_mark_idle(struct drm_device *dev)
8223 {
8224         struct drm_i915_private *dev_priv = dev->dev_private;
8225         struct drm_crtc *crtc;
8226
8227         hsw_package_c8_gpu_idle(dev_priv);
8228
8229         if (!i915.powersave)
8230                 return;
8231
8232         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8233                 if (!crtc->fb)
8234                         continue;
8235
8236                 intel_decrease_pllclock(crtc);
8237         }
8238
8239         if (INTEL_INFO(dev)->gen >= 6)
8240                 gen6_rps_idle(dev->dev_private);
8241 }
8242
8243 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8244                         struct intel_ring_buffer *ring)
8245 {
8246         struct drm_device *dev = obj->base.dev;
8247         struct drm_crtc *crtc;
8248
8249         if (!i915.powersave)
8250                 return;
8251
8252         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8253                 if (!crtc->fb)
8254                         continue;
8255
8256                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8257                         continue;
8258
8259                 intel_increase_pllclock(crtc);
8260                 if (ring && intel_fbc_enabled(dev))
8261                         ring->fbc_dirty = true;
8262         }
8263 }
8264
8265 static void intel_crtc_destroy(struct drm_crtc *crtc)
8266 {
8267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8268         struct drm_device *dev = crtc->dev;
8269         struct intel_unpin_work *work;
8270         unsigned long flags;
8271
8272         spin_lock_irqsave(&dev->event_lock, flags);
8273         work = intel_crtc->unpin_work;
8274         intel_crtc->unpin_work = NULL;
8275         spin_unlock_irqrestore(&dev->event_lock, flags);
8276
8277         if (work) {
8278                 cancel_work_sync(&work->work);
8279                 kfree(work);
8280         }
8281
8282         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8283
8284         drm_crtc_cleanup(crtc);
8285
8286         kfree(intel_crtc);
8287 }
8288
8289 static void intel_unpin_work_fn(struct work_struct *__work)
8290 {
8291         struct intel_unpin_work *work =
8292                 container_of(__work, struct intel_unpin_work, work);
8293         struct drm_device *dev = work->crtc->dev;
8294
8295         mutex_lock(&dev->struct_mutex);
8296         intel_unpin_fb_obj(work->old_fb_obj);
8297         drm_gem_object_unreference(&work->pending_flip_obj->base);
8298         drm_gem_object_unreference(&work->old_fb_obj->base);
8299
8300         intel_update_fbc(dev);
8301         mutex_unlock(&dev->struct_mutex);
8302
8303         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8304         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8305
8306         kfree(work);
8307 }
8308
8309 static void do_intel_finish_page_flip(struct drm_device *dev,
8310                                       struct drm_crtc *crtc)
8311 {
8312         drm_i915_private_t *dev_priv = dev->dev_private;
8313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8314         struct intel_unpin_work *work;
8315         unsigned long flags;
8316
8317         /* Ignore early vblank irqs */
8318         if (intel_crtc == NULL)
8319                 return;
8320
8321         spin_lock_irqsave(&dev->event_lock, flags);
8322         work = intel_crtc->unpin_work;
8323
8324         /* Ensure we don't miss a work->pending update ... */
8325         smp_rmb();
8326
8327         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8328                 spin_unlock_irqrestore(&dev->event_lock, flags);
8329                 return;
8330         }
8331
8332         /* and that the unpin work is consistent wrt ->pending. */
8333         smp_rmb();
8334
8335         intel_crtc->unpin_work = NULL;
8336
8337         if (work->event)
8338                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8339
8340         drm_vblank_put(dev, intel_crtc->pipe);
8341
8342         spin_unlock_irqrestore(&dev->event_lock, flags);
8343
8344         wake_up_all(&dev_priv->pending_flip_queue);
8345
8346         queue_work(dev_priv->wq, &work->work);
8347
8348         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8349 }
8350
8351 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8352 {
8353         drm_i915_private_t *dev_priv = dev->dev_private;
8354         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8355
8356         do_intel_finish_page_flip(dev, crtc);
8357 }
8358
8359 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8360 {
8361         drm_i915_private_t *dev_priv = dev->dev_private;
8362         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8363
8364         do_intel_finish_page_flip(dev, crtc);
8365 }
8366
8367 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8368 {
8369         drm_i915_private_t *dev_priv = dev->dev_private;
8370         struct intel_crtc *intel_crtc =
8371                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8372         unsigned long flags;
8373
8374         /* NB: An MMIO update of the plane base pointer will also
8375          * generate a page-flip completion irq, i.e. every modeset
8376          * is also accompanied by a spurious intel_prepare_page_flip().
8377          */
8378         spin_lock_irqsave(&dev->event_lock, flags);
8379         if (intel_crtc->unpin_work)
8380                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8381         spin_unlock_irqrestore(&dev->event_lock, flags);
8382 }
8383
8384 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8385 {
8386         /* Ensure that the work item is consistent when activating it ... */
8387         smp_wmb();
8388         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8389         /* and that it is marked active as soon as the irq could fire. */
8390         smp_wmb();
8391 }
8392
8393 static int intel_gen2_queue_flip(struct drm_device *dev,
8394                                  struct drm_crtc *crtc,
8395                                  struct drm_framebuffer *fb,
8396                                  struct drm_i915_gem_object *obj,
8397                                  uint32_t flags)
8398 {
8399         struct drm_i915_private *dev_priv = dev->dev_private;
8400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8401         u32 flip_mask;
8402         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8403         int ret;
8404
8405         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8406         if (ret)
8407                 goto err;
8408
8409         ret = intel_ring_begin(ring, 6);
8410         if (ret)
8411                 goto err_unpin;
8412
8413         /* Can't queue multiple flips, so wait for the previous
8414          * one to finish before executing the next.
8415          */
8416         if (intel_crtc->plane)
8417                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8418         else
8419                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8420         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8421         intel_ring_emit(ring, MI_NOOP);
8422         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8423                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8424         intel_ring_emit(ring, fb->pitches[0]);
8425         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8426         intel_ring_emit(ring, 0); /* aux display base address, unused */
8427
8428         intel_mark_page_flip_active(intel_crtc);
8429         __intel_ring_advance(ring);
8430         return 0;
8431
8432 err_unpin:
8433         intel_unpin_fb_obj(obj);
8434 err:
8435         return ret;
8436 }
8437
8438 static int intel_gen3_queue_flip(struct drm_device *dev,
8439                                  struct drm_crtc *crtc,
8440                                  struct drm_framebuffer *fb,
8441                                  struct drm_i915_gem_object *obj,
8442                                  uint32_t flags)
8443 {
8444         struct drm_i915_private *dev_priv = dev->dev_private;
8445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8446         u32 flip_mask;
8447         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8448         int ret;
8449
8450         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8451         if (ret)
8452                 goto err;
8453
8454         ret = intel_ring_begin(ring, 6);
8455         if (ret)
8456                 goto err_unpin;
8457
8458         if (intel_crtc->plane)
8459                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8460         else
8461                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8462         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8463         intel_ring_emit(ring, MI_NOOP);
8464         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8465                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8466         intel_ring_emit(ring, fb->pitches[0]);
8467         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8468         intel_ring_emit(ring, MI_NOOP);
8469
8470         intel_mark_page_flip_active(intel_crtc);
8471         __intel_ring_advance(ring);
8472         return 0;
8473
8474 err_unpin:
8475         intel_unpin_fb_obj(obj);
8476 err:
8477         return ret;
8478 }
8479
8480 static int intel_gen4_queue_flip(struct drm_device *dev,
8481                                  struct drm_crtc *crtc,
8482                                  struct drm_framebuffer *fb,
8483                                  struct drm_i915_gem_object *obj,
8484                                  uint32_t flags)
8485 {
8486         struct drm_i915_private *dev_priv = dev->dev_private;
8487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8488         uint32_t pf, pipesrc;
8489         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8490         int ret;
8491
8492         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8493         if (ret)
8494                 goto err;
8495
8496         ret = intel_ring_begin(ring, 4);
8497         if (ret)
8498                 goto err_unpin;
8499
8500         /* i965+ uses the linear or tiled offsets from the
8501          * Display Registers (which do not change across a page-flip)
8502          * so we need only reprogram the base address.
8503          */
8504         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8505                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8506         intel_ring_emit(ring, fb->pitches[0]);
8507         intel_ring_emit(ring,
8508                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8509                         obj->tiling_mode);
8510
8511         /* XXX Enabling the panel-fitter across page-flip is so far
8512          * untested on non-native modes, so ignore it for now.
8513          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8514          */
8515         pf = 0;
8516         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8517         intel_ring_emit(ring, pf | pipesrc);
8518
8519         intel_mark_page_flip_active(intel_crtc);
8520         __intel_ring_advance(ring);
8521         return 0;
8522
8523 err_unpin:
8524         intel_unpin_fb_obj(obj);
8525 err:
8526         return ret;
8527 }
8528
8529 static int intel_gen6_queue_flip(struct drm_device *dev,
8530                                  struct drm_crtc *crtc,
8531                                  struct drm_framebuffer *fb,
8532                                  struct drm_i915_gem_object *obj,
8533                                  uint32_t flags)
8534 {
8535         struct drm_i915_private *dev_priv = dev->dev_private;
8536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8537         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8538         uint32_t pf, pipesrc;
8539         int ret;
8540
8541         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8542         if (ret)
8543                 goto err;
8544
8545         ret = intel_ring_begin(ring, 4);
8546         if (ret)
8547                 goto err_unpin;
8548
8549         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8550                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8551         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8552         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8553
8554         /* Contrary to the suggestions in the documentation,
8555          * "Enable Panel Fitter" does not seem to be required when page
8556          * flipping with a non-native mode, and worse causes a normal
8557          * modeset to fail.
8558          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8559          */
8560         pf = 0;
8561         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8562         intel_ring_emit(ring, pf | pipesrc);
8563
8564         intel_mark_page_flip_active(intel_crtc);
8565         __intel_ring_advance(ring);
8566         return 0;
8567
8568 err_unpin:
8569         intel_unpin_fb_obj(obj);
8570 err:
8571         return ret;
8572 }
8573
8574 static int intel_gen7_queue_flip(struct drm_device *dev,
8575                                  struct drm_crtc *crtc,
8576                                  struct drm_framebuffer *fb,
8577                                  struct drm_i915_gem_object *obj,
8578                                  uint32_t flags)
8579 {
8580         struct drm_i915_private *dev_priv = dev->dev_private;
8581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8582         struct intel_ring_buffer *ring;
8583         uint32_t plane_bit = 0;
8584         int len, ret;
8585
8586         ring = obj->ring;
8587         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8588                 ring = &dev_priv->ring[BCS];
8589
8590         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8591         if (ret)
8592                 goto err;
8593
8594         switch(intel_crtc->plane) {
8595         case PLANE_A:
8596                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8597                 break;
8598         case PLANE_B:
8599                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8600                 break;
8601         case PLANE_C:
8602                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8603                 break;
8604         default:
8605                 WARN_ONCE(1, "unknown plane in flip command\n");
8606                 ret = -ENODEV;
8607                 goto err_unpin;
8608         }
8609
8610         len = 4;
8611         if (ring->id == RCS)
8612                 len += 6;
8613
8614         ret = intel_ring_begin(ring, len);
8615         if (ret)
8616                 goto err_unpin;
8617
8618         /* Unmask the flip-done completion message. Note that the bspec says that
8619          * we should do this for both the BCS and RCS, and that we must not unmask
8620          * more than one flip event at any time (or ensure that one flip message
8621          * can be sent by waiting for flip-done prior to queueing new flips).
8622          * Experimentation says that BCS works despite DERRMR masking all
8623          * flip-done completion events and that unmasking all planes at once
8624          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8625          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8626          */
8627         if (ring->id == RCS) {
8628                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8629                 intel_ring_emit(ring, DERRMR);
8630                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8631                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8632                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8633                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8634                                 MI_SRM_LRM_GLOBAL_GTT);
8635                 intel_ring_emit(ring, DERRMR);
8636                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8637         }
8638
8639         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8640         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8641         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8642         intel_ring_emit(ring, (MI_NOOP));
8643
8644         intel_mark_page_flip_active(intel_crtc);
8645         __intel_ring_advance(ring);
8646         return 0;
8647
8648 err_unpin:
8649         intel_unpin_fb_obj(obj);
8650 err:
8651         return ret;
8652 }
8653
8654 static int intel_default_queue_flip(struct drm_device *dev,
8655                                     struct drm_crtc *crtc,
8656                                     struct drm_framebuffer *fb,
8657                                     struct drm_i915_gem_object *obj,
8658                                     uint32_t flags)
8659 {
8660         return -ENODEV;
8661 }
8662
8663 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8664                                 struct drm_framebuffer *fb,
8665                                 struct drm_pending_vblank_event *event,
8666                                 uint32_t page_flip_flags)
8667 {
8668         struct drm_device *dev = crtc->dev;
8669         struct drm_i915_private *dev_priv = dev->dev_private;
8670         struct drm_framebuffer *old_fb = crtc->fb;
8671         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8673         struct intel_unpin_work *work;
8674         unsigned long flags;
8675         int ret;
8676
8677         /* Can't change pixel format via MI display flips. */
8678         if (fb->pixel_format != crtc->fb->pixel_format)
8679                 return -EINVAL;
8680
8681         /*
8682          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8683          * Note that pitch changes could also affect these register.
8684          */
8685         if (INTEL_INFO(dev)->gen > 3 &&
8686             (fb->offsets[0] != crtc->fb->offsets[0] ||
8687              fb->pitches[0] != crtc->fb->pitches[0]))
8688                 return -EINVAL;
8689
8690         work = kzalloc(sizeof(*work), GFP_KERNEL);
8691         if (work == NULL)
8692                 return -ENOMEM;
8693
8694         work->event = event;
8695         work->crtc = crtc;
8696         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8697         INIT_WORK(&work->work, intel_unpin_work_fn);
8698
8699         ret = drm_vblank_get(dev, intel_crtc->pipe);
8700         if (ret)
8701                 goto free_work;
8702
8703         /* We borrow the event spin lock for protecting unpin_work */
8704         spin_lock_irqsave(&dev->event_lock, flags);
8705         if (intel_crtc->unpin_work) {
8706                 spin_unlock_irqrestore(&dev->event_lock, flags);
8707                 kfree(work);
8708                 drm_vblank_put(dev, intel_crtc->pipe);
8709
8710                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8711                 return -EBUSY;
8712         }
8713         intel_crtc->unpin_work = work;
8714         spin_unlock_irqrestore(&dev->event_lock, flags);
8715
8716         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8717                 flush_workqueue(dev_priv->wq);
8718
8719         ret = i915_mutex_lock_interruptible(dev);
8720         if (ret)
8721                 goto cleanup;
8722
8723         /* Reference the objects for the scheduled work. */
8724         drm_gem_object_reference(&work->old_fb_obj->base);
8725         drm_gem_object_reference(&obj->base);
8726
8727         crtc->fb = fb;
8728
8729         work->pending_flip_obj = obj;
8730
8731         work->enable_stall_check = true;
8732
8733         atomic_inc(&intel_crtc->unpin_work_count);
8734         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8735
8736         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8737         if (ret)
8738                 goto cleanup_pending;
8739
8740         intel_disable_fbc(dev);
8741         intel_mark_fb_busy(obj, NULL);
8742         mutex_unlock(&dev->struct_mutex);
8743
8744         trace_i915_flip_request(intel_crtc->plane, obj);
8745
8746         return 0;
8747
8748 cleanup_pending:
8749         atomic_dec(&intel_crtc->unpin_work_count);
8750         crtc->fb = old_fb;
8751         drm_gem_object_unreference(&work->old_fb_obj->base);
8752         drm_gem_object_unreference(&obj->base);
8753         mutex_unlock(&dev->struct_mutex);
8754
8755 cleanup:
8756         spin_lock_irqsave(&dev->event_lock, flags);
8757         intel_crtc->unpin_work = NULL;
8758         spin_unlock_irqrestore(&dev->event_lock, flags);
8759
8760         drm_vblank_put(dev, intel_crtc->pipe);
8761 free_work:
8762         kfree(work);
8763
8764         return ret;
8765 }
8766
8767 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8768         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8769         .load_lut = intel_crtc_load_lut,
8770 };
8771
8772 /**
8773  * intel_modeset_update_staged_output_state
8774  *
8775  * Updates the staged output configuration state, e.g. after we've read out the
8776  * current hw state.
8777  */
8778 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8779 {
8780         struct intel_crtc *crtc;
8781         struct intel_encoder *encoder;
8782         struct intel_connector *connector;
8783
8784         list_for_each_entry(connector, &dev->mode_config.connector_list,
8785                             base.head) {
8786                 connector->new_encoder =
8787                         to_intel_encoder(connector->base.encoder);
8788         }
8789
8790         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8791                             base.head) {
8792                 encoder->new_crtc =
8793                         to_intel_crtc(encoder->base.crtc);
8794         }
8795
8796         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8797                             base.head) {
8798                 crtc->new_enabled = crtc->base.enabled;
8799
8800                 if (crtc->new_enabled)
8801                         crtc->new_config = &crtc->config;
8802                 else
8803                         crtc->new_config = NULL;
8804         }
8805 }
8806
8807 /**
8808  * intel_modeset_commit_output_state
8809  *
8810  * This function copies the stage display pipe configuration to the real one.
8811  */
8812 static void intel_modeset_commit_output_state(struct drm_device *dev)
8813 {
8814         struct intel_crtc *crtc;
8815         struct intel_encoder *encoder;
8816         struct intel_connector *connector;
8817
8818         list_for_each_entry(connector, &dev->mode_config.connector_list,
8819                             base.head) {
8820                 connector->base.encoder = &connector->new_encoder->base;
8821         }
8822
8823         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8824                             base.head) {
8825                 encoder->base.crtc = &encoder->new_crtc->base;
8826         }
8827
8828         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8829                             base.head) {
8830                 crtc->base.enabled = crtc->new_enabled;
8831         }
8832 }
8833
8834 static void
8835 connected_sink_compute_bpp(struct intel_connector * connector,
8836                            struct intel_crtc_config *pipe_config)
8837 {
8838         int bpp = pipe_config->pipe_bpp;
8839
8840         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8841                 connector->base.base.id,
8842                 drm_get_connector_name(&connector->base));
8843
8844         /* Don't use an invalid EDID bpc value */
8845         if (connector->base.display_info.bpc &&
8846             connector->base.display_info.bpc * 3 < bpp) {
8847                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8848                               bpp, connector->base.display_info.bpc*3);
8849                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8850         }
8851
8852         /* Clamp bpp to 8 on screens without EDID 1.4 */
8853         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8854                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8855                               bpp);
8856                 pipe_config->pipe_bpp = 24;
8857         }
8858 }
8859
8860 static int
8861 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8862                           struct drm_framebuffer *fb,
8863                           struct intel_crtc_config *pipe_config)
8864 {
8865         struct drm_device *dev = crtc->base.dev;
8866         struct intel_connector *connector;
8867         int bpp;
8868
8869         switch (fb->pixel_format) {
8870         case DRM_FORMAT_C8:
8871                 bpp = 8*3; /* since we go through a colormap */
8872                 break;
8873         case DRM_FORMAT_XRGB1555:
8874         case DRM_FORMAT_ARGB1555:
8875                 /* checked in intel_framebuffer_init already */
8876                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8877                         return -EINVAL;
8878         case DRM_FORMAT_RGB565:
8879                 bpp = 6*3; /* min is 18bpp */
8880                 break;
8881         case DRM_FORMAT_XBGR8888:
8882         case DRM_FORMAT_ABGR8888:
8883                 /* checked in intel_framebuffer_init already */
8884                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8885                         return -EINVAL;
8886         case DRM_FORMAT_XRGB8888:
8887         case DRM_FORMAT_ARGB8888:
8888                 bpp = 8*3;
8889                 break;
8890         case DRM_FORMAT_XRGB2101010:
8891         case DRM_FORMAT_ARGB2101010:
8892         case DRM_FORMAT_XBGR2101010:
8893         case DRM_FORMAT_ABGR2101010:
8894                 /* checked in intel_framebuffer_init already */
8895                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8896                         return -EINVAL;
8897                 bpp = 10*3;
8898                 break;
8899         /* TODO: gen4+ supports 16 bpc floating point, too. */
8900         default:
8901                 DRM_DEBUG_KMS("unsupported depth\n");
8902                 return -EINVAL;
8903         }
8904
8905         pipe_config->pipe_bpp = bpp;
8906
8907         /* Clamp display bpp to EDID value */
8908         list_for_each_entry(connector, &dev->mode_config.connector_list,
8909                             base.head) {
8910                 if (!connector->new_encoder ||
8911                     connector->new_encoder->new_crtc != crtc)
8912                         continue;
8913
8914                 connected_sink_compute_bpp(connector, pipe_config);
8915         }
8916
8917         return bpp;
8918 }
8919
8920 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8921 {
8922         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8923                         "type: 0x%x flags: 0x%x\n",
8924                 mode->crtc_clock,
8925                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8926                 mode->crtc_hsync_end, mode->crtc_htotal,
8927                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8928                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8929 }
8930
8931 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8932                                    struct intel_crtc_config *pipe_config,
8933                                    const char *context)
8934 {
8935         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8936                       context, pipe_name(crtc->pipe));
8937
8938         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8939         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8940                       pipe_config->pipe_bpp, pipe_config->dither);
8941         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8942                       pipe_config->has_pch_encoder,
8943                       pipe_config->fdi_lanes,
8944                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8945                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8946                       pipe_config->fdi_m_n.tu);
8947         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8948                       pipe_config->has_dp_encoder,
8949                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8950                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8951                       pipe_config->dp_m_n.tu);
8952         DRM_DEBUG_KMS("requested mode:\n");
8953         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8954         DRM_DEBUG_KMS("adjusted mode:\n");
8955         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8956         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8957         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8958         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8959                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8960         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8961                       pipe_config->gmch_pfit.control,
8962                       pipe_config->gmch_pfit.pgm_ratios,
8963                       pipe_config->gmch_pfit.lvds_border_bits);
8964         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8965                       pipe_config->pch_pfit.pos,
8966                       pipe_config->pch_pfit.size,
8967                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8968         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8969         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8970 }
8971
8972 static bool check_encoder_cloning(struct drm_crtc *crtc)
8973 {
8974         int num_encoders = 0;
8975         bool uncloneable_encoders = false;
8976         struct intel_encoder *encoder;
8977
8978         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8979                             base.head) {
8980                 if (&encoder->new_crtc->base != crtc)
8981                         continue;
8982
8983                 num_encoders++;
8984                 if (!encoder->cloneable)
8985                         uncloneable_encoders = true;
8986         }
8987
8988         return !(num_encoders > 1 && uncloneable_encoders);
8989 }
8990
8991 static struct intel_crtc_config *
8992 intel_modeset_pipe_config(struct drm_crtc *crtc,
8993                           struct drm_framebuffer *fb,
8994                           struct drm_display_mode *mode)
8995 {
8996         struct drm_device *dev = crtc->dev;
8997         struct intel_encoder *encoder;
8998         struct intel_crtc_config *pipe_config;
8999         int plane_bpp, ret = -EINVAL;
9000         bool retry = true;
9001
9002         if (!check_encoder_cloning(crtc)) {
9003                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9004                 return ERR_PTR(-EINVAL);
9005         }
9006
9007         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9008         if (!pipe_config)
9009                 return ERR_PTR(-ENOMEM);
9010
9011         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9012         drm_mode_copy(&pipe_config->requested_mode, mode);
9013
9014         pipe_config->cpu_transcoder =
9015                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9016         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9017
9018         /*
9019          * Sanitize sync polarity flags based on requested ones. If neither
9020          * positive or negative polarity is requested, treat this as meaning
9021          * negative polarity.
9022          */
9023         if (!(pipe_config->adjusted_mode.flags &
9024               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9025                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9026
9027         if (!(pipe_config->adjusted_mode.flags &
9028               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9029                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9030
9031         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9032          * plane pixel format and any sink constraints into account. Returns the
9033          * source plane bpp so that dithering can be selected on mismatches
9034          * after encoders and crtc also have had their say. */
9035         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9036                                               fb, pipe_config);
9037         if (plane_bpp < 0)
9038                 goto fail;
9039
9040         /*
9041          * Determine the real pipe dimensions. Note that stereo modes can
9042          * increase the actual pipe size due to the frame doubling and
9043          * insertion of additional space for blanks between the frame. This
9044          * is stored in the crtc timings. We use the requested mode to do this
9045          * computation to clearly distinguish it from the adjusted mode, which
9046          * can be changed by the connectors in the below retry loop.
9047          */
9048         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9049         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9050         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9051
9052 encoder_retry:
9053         /* Ensure the port clock defaults are reset when retrying. */
9054         pipe_config->port_clock = 0;
9055         pipe_config->pixel_multiplier = 1;
9056
9057         /* Fill in default crtc timings, allow encoders to overwrite them. */
9058         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9059
9060         /* Pass our mode to the connectors and the CRTC to give them a chance to
9061          * adjust it according to limitations or connector properties, and also
9062          * a chance to reject the mode entirely.
9063          */
9064         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9065                             base.head) {
9066
9067                 if (&encoder->new_crtc->base != crtc)
9068                         continue;
9069
9070                 if (!(encoder->compute_config(encoder, pipe_config))) {
9071                         DRM_DEBUG_KMS("Encoder config failure\n");
9072                         goto fail;
9073                 }
9074         }
9075
9076         /* Set default port clock if not overwritten by the encoder. Needs to be
9077          * done afterwards in case the encoder adjusts the mode. */
9078         if (!pipe_config->port_clock)
9079                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9080                         * pipe_config->pixel_multiplier;
9081
9082         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9083         if (ret < 0) {
9084                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9085                 goto fail;
9086         }
9087
9088         if (ret == RETRY) {
9089                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9090                         ret = -EINVAL;
9091                         goto fail;
9092                 }
9093
9094                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9095                 retry = false;
9096                 goto encoder_retry;
9097         }
9098
9099         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9100         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9101                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9102
9103         return pipe_config;
9104 fail:
9105         kfree(pipe_config);
9106         return ERR_PTR(ret);
9107 }
9108
9109 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9110  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9111 static void
9112 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9113                              unsigned *prepare_pipes, unsigned *disable_pipes)
9114 {
9115         struct intel_crtc *intel_crtc;
9116         struct drm_device *dev = crtc->dev;
9117         struct intel_encoder *encoder;
9118         struct intel_connector *connector;
9119         struct drm_crtc *tmp_crtc;
9120
9121         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9122
9123         /* Check which crtcs have changed outputs connected to them, these need
9124          * to be part of the prepare_pipes mask. We don't (yet) support global
9125          * modeset across multiple crtcs, so modeset_pipes will only have one
9126          * bit set at most. */
9127         list_for_each_entry(connector, &dev->mode_config.connector_list,
9128                             base.head) {
9129                 if (connector->base.encoder == &connector->new_encoder->base)
9130                         continue;
9131
9132                 if (connector->base.encoder) {
9133                         tmp_crtc = connector->base.encoder->crtc;
9134
9135                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9136                 }
9137
9138                 if (connector->new_encoder)
9139                         *prepare_pipes |=
9140                                 1 << connector->new_encoder->new_crtc->pipe;
9141         }
9142
9143         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9144                             base.head) {
9145                 if (encoder->base.crtc == &encoder->new_crtc->base)
9146                         continue;
9147
9148                 if (encoder->base.crtc) {
9149                         tmp_crtc = encoder->base.crtc;
9150
9151                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9152                 }
9153
9154                 if (encoder->new_crtc)
9155                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9156         }
9157
9158         /* Check for pipes that will be enabled/disabled ... */
9159         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9160                             base.head) {
9161                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9162                         continue;
9163
9164                 if (!intel_crtc->new_enabled)
9165                         *disable_pipes |= 1 << intel_crtc->pipe;
9166                 else
9167                         *prepare_pipes |= 1 << intel_crtc->pipe;
9168         }
9169
9170
9171         /* set_mode is also used to update properties on life display pipes. */
9172         intel_crtc = to_intel_crtc(crtc);
9173         if (intel_crtc->new_enabled)
9174                 *prepare_pipes |= 1 << intel_crtc->pipe;
9175
9176         /*
9177          * For simplicity do a full modeset on any pipe where the output routing
9178          * changed. We could be more clever, but that would require us to be
9179          * more careful with calling the relevant encoder->mode_set functions.
9180          */
9181         if (*prepare_pipes)
9182                 *modeset_pipes = *prepare_pipes;
9183
9184         /* ... and mask these out. */
9185         *modeset_pipes &= ~(*disable_pipes);
9186         *prepare_pipes &= ~(*disable_pipes);
9187
9188         /*
9189          * HACK: We don't (yet) fully support global modesets. intel_set_config
9190          * obies this rule, but the modeset restore mode of
9191          * intel_modeset_setup_hw_state does not.
9192          */
9193         *modeset_pipes &= 1 << intel_crtc->pipe;
9194         *prepare_pipes &= 1 << intel_crtc->pipe;
9195
9196         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9197                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9198 }
9199
9200 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9201 {
9202         struct drm_encoder *encoder;
9203         struct drm_device *dev = crtc->dev;
9204
9205         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9206                 if (encoder->crtc == crtc)
9207                         return true;
9208
9209         return false;
9210 }
9211
9212 static void
9213 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9214 {
9215         struct intel_encoder *intel_encoder;
9216         struct intel_crtc *intel_crtc;
9217         struct drm_connector *connector;
9218
9219         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9220                             base.head) {
9221                 if (!intel_encoder->base.crtc)
9222                         continue;
9223
9224                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9225
9226                 if (prepare_pipes & (1 << intel_crtc->pipe))
9227                         intel_encoder->connectors_active = false;
9228         }
9229
9230         intel_modeset_commit_output_state(dev);
9231
9232         /* Double check state. */
9233         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9234                             base.head) {
9235                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9236                 WARN_ON(intel_crtc->new_config &&
9237                         intel_crtc->new_config != &intel_crtc->config);
9238                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9239         }
9240
9241         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9242                 if (!connector->encoder || !connector->encoder->crtc)
9243                         continue;
9244
9245                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9246
9247                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9248                         struct drm_property *dpms_property =
9249                                 dev->mode_config.dpms_property;
9250
9251                         connector->dpms = DRM_MODE_DPMS_ON;
9252                         drm_object_property_set_value(&connector->base,
9253                                                          dpms_property,
9254                                                          DRM_MODE_DPMS_ON);
9255
9256                         intel_encoder = to_intel_encoder(connector->encoder);
9257                         intel_encoder->connectors_active = true;
9258                 }
9259         }
9260
9261 }
9262
9263 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9264 {
9265         int diff;
9266
9267         if (clock1 == clock2)
9268                 return true;
9269
9270         if (!clock1 || !clock2)
9271                 return false;
9272
9273         diff = abs(clock1 - clock2);
9274
9275         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9276                 return true;
9277
9278         return false;
9279 }
9280
9281 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9282         list_for_each_entry((intel_crtc), \
9283                             &(dev)->mode_config.crtc_list, \
9284                             base.head) \
9285                 if (mask & (1 <<(intel_crtc)->pipe))
9286
9287 static bool
9288 intel_pipe_config_compare(struct drm_device *dev,
9289                           struct intel_crtc_config *current_config,
9290                           struct intel_crtc_config *pipe_config)
9291 {
9292 #define PIPE_CONF_CHECK_X(name) \
9293         if (current_config->name != pipe_config->name) { \
9294                 DRM_ERROR("mismatch in " #name " " \
9295                           "(expected 0x%08x, found 0x%08x)\n", \
9296                           current_config->name, \
9297                           pipe_config->name); \
9298                 return false; \
9299         }
9300
9301 #define PIPE_CONF_CHECK_I(name) \
9302         if (current_config->name != pipe_config->name) { \
9303                 DRM_ERROR("mismatch in " #name " " \
9304                           "(expected %i, found %i)\n", \
9305                           current_config->name, \
9306                           pipe_config->name); \
9307                 return false; \
9308         }
9309
9310 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9311         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9312                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9313                           "(expected %i, found %i)\n", \
9314                           current_config->name & (mask), \
9315                           pipe_config->name & (mask)); \
9316                 return false; \
9317         }
9318
9319 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9320         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9321                 DRM_ERROR("mismatch in " #name " " \
9322                           "(expected %i, found %i)\n", \
9323                           current_config->name, \
9324                           pipe_config->name); \
9325                 return false; \
9326         }
9327
9328 #define PIPE_CONF_QUIRK(quirk)  \
9329         ((current_config->quirks | pipe_config->quirks) & (quirk))
9330
9331         PIPE_CONF_CHECK_I(cpu_transcoder);
9332
9333         PIPE_CONF_CHECK_I(has_pch_encoder);
9334         PIPE_CONF_CHECK_I(fdi_lanes);
9335         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9336         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9337         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9338         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9339         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9340
9341         PIPE_CONF_CHECK_I(has_dp_encoder);
9342         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9343         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9344         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9345         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9346         PIPE_CONF_CHECK_I(dp_m_n.tu);
9347
9348         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9349         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9350         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9351         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9352         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9353         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9354
9355         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9356         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9357         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9358         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9359         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9360         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9361
9362         PIPE_CONF_CHECK_I(pixel_multiplier);
9363
9364         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9365                               DRM_MODE_FLAG_INTERLACE);
9366
9367         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9368                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9369                                       DRM_MODE_FLAG_PHSYNC);
9370                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9371                                       DRM_MODE_FLAG_NHSYNC);
9372                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9373                                       DRM_MODE_FLAG_PVSYNC);
9374                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9375                                       DRM_MODE_FLAG_NVSYNC);
9376         }
9377
9378         PIPE_CONF_CHECK_I(pipe_src_w);
9379         PIPE_CONF_CHECK_I(pipe_src_h);
9380
9381         PIPE_CONF_CHECK_I(gmch_pfit.control);
9382         /* pfit ratios are autocomputed by the hw on gen4+ */
9383         if (INTEL_INFO(dev)->gen < 4)
9384                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9385         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9386         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9387         if (current_config->pch_pfit.enabled) {
9388                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9389                 PIPE_CONF_CHECK_I(pch_pfit.size);
9390         }
9391
9392         /* BDW+ don't expose a synchronous way to read the state */
9393         if (IS_HASWELL(dev))
9394                 PIPE_CONF_CHECK_I(ips_enabled);
9395
9396         PIPE_CONF_CHECK_I(double_wide);
9397
9398         PIPE_CONF_CHECK_I(shared_dpll);
9399         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9400         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9401         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9402         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9403
9404         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9405                 PIPE_CONF_CHECK_I(pipe_bpp);
9406
9407         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9408         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9409
9410 #undef PIPE_CONF_CHECK_X
9411 #undef PIPE_CONF_CHECK_I
9412 #undef PIPE_CONF_CHECK_FLAGS
9413 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9414 #undef PIPE_CONF_QUIRK
9415
9416         return true;
9417 }
9418
9419 static void
9420 check_connector_state(struct drm_device *dev)
9421 {
9422         struct intel_connector *connector;
9423
9424         list_for_each_entry(connector, &dev->mode_config.connector_list,
9425                             base.head) {
9426                 /* This also checks the encoder/connector hw state with the
9427                  * ->get_hw_state callbacks. */
9428                 intel_connector_check_state(connector);
9429
9430                 WARN(&connector->new_encoder->base != connector->base.encoder,
9431                      "connector's staged encoder doesn't match current encoder\n");
9432         }
9433 }
9434
9435 static void
9436 check_encoder_state(struct drm_device *dev)
9437 {
9438         struct intel_encoder *encoder;
9439         struct intel_connector *connector;
9440
9441         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9442                             base.head) {
9443                 bool enabled = false;
9444                 bool active = false;
9445                 enum pipe pipe, tracked_pipe;
9446
9447                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9448                               encoder->base.base.id,
9449                               drm_get_encoder_name(&encoder->base));
9450
9451                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9452                      "encoder's stage crtc doesn't match current crtc\n");
9453                 WARN(encoder->connectors_active && !encoder->base.crtc,
9454                      "encoder's active_connectors set, but no crtc\n");
9455
9456                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9457                                     base.head) {
9458                         if (connector->base.encoder != &encoder->base)
9459                                 continue;
9460                         enabled = true;
9461                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9462                                 active = true;
9463                 }
9464                 WARN(!!encoder->base.crtc != enabled,
9465                      "encoder's enabled state mismatch "
9466                      "(expected %i, found %i)\n",
9467                      !!encoder->base.crtc, enabled);
9468                 WARN(active && !encoder->base.crtc,
9469                      "active encoder with no crtc\n");
9470
9471                 WARN(encoder->connectors_active != active,
9472                      "encoder's computed active state doesn't match tracked active state "
9473                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9474
9475                 active = encoder->get_hw_state(encoder, &pipe);
9476                 WARN(active != encoder->connectors_active,
9477                      "encoder's hw state doesn't match sw tracking "
9478                      "(expected %i, found %i)\n",
9479                      encoder->connectors_active, active);
9480
9481                 if (!encoder->base.crtc)
9482                         continue;
9483
9484                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9485                 WARN(active && pipe != tracked_pipe,
9486                      "active encoder's pipe doesn't match"
9487                      "(expected %i, found %i)\n",
9488                      tracked_pipe, pipe);
9489
9490         }
9491 }
9492
9493 static void
9494 check_crtc_state(struct drm_device *dev)
9495 {
9496         drm_i915_private_t *dev_priv = dev->dev_private;
9497         struct intel_crtc *crtc;
9498         struct intel_encoder *encoder;
9499         struct intel_crtc_config pipe_config;
9500
9501         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9502                             base.head) {
9503                 bool enabled = false;
9504                 bool active = false;
9505
9506                 memset(&pipe_config, 0, sizeof(pipe_config));
9507
9508                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9509                               crtc->base.base.id);
9510
9511                 WARN(crtc->active && !crtc->base.enabled,
9512                      "active crtc, but not enabled in sw tracking\n");
9513
9514                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9515                                     base.head) {
9516                         if (encoder->base.crtc != &crtc->base)
9517                                 continue;
9518                         enabled = true;
9519                         if (encoder->connectors_active)
9520                                 active = true;
9521                 }
9522
9523                 WARN(active != crtc->active,
9524                      "crtc's computed active state doesn't match tracked active state "
9525                      "(expected %i, found %i)\n", active, crtc->active);
9526                 WARN(enabled != crtc->base.enabled,
9527                      "crtc's computed enabled state doesn't match tracked enabled state "
9528                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9529
9530                 active = dev_priv->display.get_pipe_config(crtc,
9531                                                            &pipe_config);
9532
9533                 /* hw state is inconsistent with the pipe A quirk */
9534                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9535                         active = crtc->active;
9536
9537                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9538                                     base.head) {
9539                         enum pipe pipe;
9540                         if (encoder->base.crtc != &crtc->base)
9541                                 continue;
9542                         if (encoder->get_hw_state(encoder, &pipe))
9543                                 encoder->get_config(encoder, &pipe_config);
9544                 }
9545
9546                 WARN(crtc->active != active,
9547                      "crtc active state doesn't match with hw state "
9548                      "(expected %i, found %i)\n", crtc->active, active);
9549
9550                 if (active &&
9551                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9552                         WARN(1, "pipe state doesn't match!\n");
9553                         intel_dump_pipe_config(crtc, &pipe_config,
9554                                                "[hw state]");
9555                         intel_dump_pipe_config(crtc, &crtc->config,
9556                                                "[sw state]");
9557                 }
9558         }
9559 }
9560
9561 static void
9562 check_shared_dpll_state(struct drm_device *dev)
9563 {
9564         drm_i915_private_t *dev_priv = dev->dev_private;
9565         struct intel_crtc *crtc;
9566         struct intel_dpll_hw_state dpll_hw_state;
9567         int i;
9568
9569         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9570                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9571                 int enabled_crtcs = 0, active_crtcs = 0;
9572                 bool active;
9573
9574                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9575
9576                 DRM_DEBUG_KMS("%s\n", pll->name);
9577
9578                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9579
9580                 WARN(pll->active > pll->refcount,
9581                      "more active pll users than references: %i vs %i\n",
9582                      pll->active, pll->refcount);
9583                 WARN(pll->active && !pll->on,
9584                      "pll in active use but not on in sw tracking\n");
9585                 WARN(pll->on && !pll->active,
9586                      "pll in on but not on in use in sw tracking\n");
9587                 WARN(pll->on != active,
9588                      "pll on state mismatch (expected %i, found %i)\n",
9589                      pll->on, active);
9590
9591                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9592                                     base.head) {
9593                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9594                                 enabled_crtcs++;
9595                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9596                                 active_crtcs++;
9597                 }
9598                 WARN(pll->active != active_crtcs,
9599                      "pll active crtcs mismatch (expected %i, found %i)\n",
9600                      pll->active, active_crtcs);
9601                 WARN(pll->refcount != enabled_crtcs,
9602                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9603                      pll->refcount, enabled_crtcs);
9604
9605                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9606                                        sizeof(dpll_hw_state)),
9607                      "pll hw state mismatch\n");
9608         }
9609 }
9610
9611 void
9612 intel_modeset_check_state(struct drm_device *dev)
9613 {
9614         check_connector_state(dev);
9615         check_encoder_state(dev);
9616         check_crtc_state(dev);
9617         check_shared_dpll_state(dev);
9618 }
9619
9620 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9621                                      int dotclock)
9622 {
9623         /*
9624          * FDI already provided one idea for the dotclock.
9625          * Yell if the encoder disagrees.
9626          */
9627         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9628              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9629              pipe_config->adjusted_mode.crtc_clock, dotclock);
9630 }
9631
9632 static int __intel_set_mode(struct drm_crtc *crtc,
9633                             struct drm_display_mode *mode,
9634                             int x, int y, struct drm_framebuffer *fb)
9635 {
9636         struct drm_device *dev = crtc->dev;
9637         drm_i915_private_t *dev_priv = dev->dev_private;
9638         struct drm_display_mode *saved_mode;
9639         struct intel_crtc_config *pipe_config = NULL;
9640         struct intel_crtc *intel_crtc;
9641         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9642         int ret = 0;
9643
9644         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9645         if (!saved_mode)
9646                 return -ENOMEM;
9647
9648         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9649                                      &prepare_pipes, &disable_pipes);
9650
9651         *saved_mode = crtc->mode;
9652
9653         /* Hack: Because we don't (yet) support global modeset on multiple
9654          * crtcs, we don't keep track of the new mode for more than one crtc.
9655          * Hence simply check whether any bit is set in modeset_pipes in all the
9656          * pieces of code that are not yet converted to deal with mutliple crtcs
9657          * changing their mode at the same time. */
9658         if (modeset_pipes) {
9659                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9660                 if (IS_ERR(pipe_config)) {
9661                         ret = PTR_ERR(pipe_config);
9662                         pipe_config = NULL;
9663
9664                         goto out;
9665                 }
9666                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9667                                        "[modeset]");
9668                 to_intel_crtc(crtc)->new_config = pipe_config;
9669         }
9670
9671         /*
9672          * See if the config requires any additional preparation, e.g.
9673          * to adjust global state with pipes off.  We need to do this
9674          * here so we can get the modeset_pipe updated config for the new
9675          * mode set on this crtc.  For other crtcs we need to use the
9676          * adjusted_mode bits in the crtc directly.
9677          */
9678         if (IS_VALLEYVIEW(dev)) {
9679                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9680
9681                 /* may have added more to prepare_pipes than we should */
9682                 prepare_pipes &= ~disable_pipes;
9683         }
9684
9685         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9686                 intel_crtc_disable(&intel_crtc->base);
9687
9688         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9689                 if (intel_crtc->base.enabled)
9690                         dev_priv->display.crtc_disable(&intel_crtc->base);
9691         }
9692
9693         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9694          * to set it here already despite that we pass it down the callchain.
9695          */
9696         if (modeset_pipes) {
9697                 crtc->mode = *mode;
9698                 /* mode_set/enable/disable functions rely on a correct pipe
9699                  * config. */
9700                 to_intel_crtc(crtc)->config = *pipe_config;
9701                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9702
9703                 /*
9704                  * Calculate and store various constants which
9705                  * are later needed by vblank and swap-completion
9706                  * timestamping. They are derived from true hwmode.
9707                  */
9708                 drm_calc_timestamping_constants(crtc,
9709                                                 &pipe_config->adjusted_mode);
9710         }
9711
9712         /* Only after disabling all output pipelines that will be changed can we
9713          * update the the output configuration. */
9714         intel_modeset_update_state(dev, prepare_pipes);
9715
9716         if (dev_priv->display.modeset_global_resources)
9717                 dev_priv->display.modeset_global_resources(dev);
9718
9719         /* Set up the DPLL and any encoders state that needs to adjust or depend
9720          * on the DPLL.
9721          */
9722         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9723                 ret = intel_crtc_mode_set(&intel_crtc->base,
9724                                           x, y, fb);
9725                 if (ret)
9726                         goto done;
9727         }
9728
9729         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9730         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9731                 dev_priv->display.crtc_enable(&intel_crtc->base);
9732
9733         /* FIXME: add subpixel order */
9734 done:
9735         if (ret && crtc->enabled)
9736                 crtc->mode = *saved_mode;
9737
9738 out:
9739         kfree(pipe_config);
9740         kfree(saved_mode);
9741         return ret;
9742 }
9743
9744 static int intel_set_mode(struct drm_crtc *crtc,
9745                           struct drm_display_mode *mode,
9746                           int x, int y, struct drm_framebuffer *fb)
9747 {
9748         int ret;
9749
9750         ret = __intel_set_mode(crtc, mode, x, y, fb);
9751
9752         if (ret == 0)
9753                 intel_modeset_check_state(crtc->dev);
9754
9755         return ret;
9756 }
9757
9758 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9759 {
9760         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9761 }
9762
9763 #undef for_each_intel_crtc_masked
9764
9765 static void intel_set_config_free(struct intel_set_config *config)
9766 {
9767         if (!config)
9768                 return;
9769
9770         kfree(config->save_connector_encoders);
9771         kfree(config->save_encoder_crtcs);
9772         kfree(config->save_crtc_enabled);
9773         kfree(config);
9774 }
9775
9776 static int intel_set_config_save_state(struct drm_device *dev,
9777                                        struct intel_set_config *config)
9778 {
9779         struct drm_crtc *crtc;
9780         struct drm_encoder *encoder;
9781         struct drm_connector *connector;
9782         int count;
9783
9784         config->save_crtc_enabled =
9785                 kcalloc(dev->mode_config.num_crtc,
9786                         sizeof(bool), GFP_KERNEL);
9787         if (!config->save_crtc_enabled)
9788                 return -ENOMEM;
9789
9790         config->save_encoder_crtcs =
9791                 kcalloc(dev->mode_config.num_encoder,
9792                         sizeof(struct drm_crtc *), GFP_KERNEL);
9793         if (!config->save_encoder_crtcs)
9794                 return -ENOMEM;
9795
9796         config->save_connector_encoders =
9797                 kcalloc(dev->mode_config.num_connector,
9798                         sizeof(struct drm_encoder *), GFP_KERNEL);
9799         if (!config->save_connector_encoders)
9800                 return -ENOMEM;
9801
9802         /* Copy data. Note that driver private data is not affected.
9803          * Should anything bad happen only the expected state is
9804          * restored, not the drivers personal bookkeeping.
9805          */
9806         count = 0;
9807         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9808                 config->save_crtc_enabled[count++] = crtc->enabled;
9809         }
9810
9811         count = 0;
9812         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9813                 config->save_encoder_crtcs[count++] = encoder->crtc;
9814         }
9815
9816         count = 0;
9817         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9818                 config->save_connector_encoders[count++] = connector->encoder;
9819         }
9820
9821         return 0;
9822 }
9823
9824 static void intel_set_config_restore_state(struct drm_device *dev,
9825                                            struct intel_set_config *config)
9826 {
9827         struct intel_crtc *crtc;
9828         struct intel_encoder *encoder;
9829         struct intel_connector *connector;
9830         int count;
9831
9832         count = 0;
9833         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9834                 crtc->new_enabled = config->save_crtc_enabled[count++];
9835
9836                 if (crtc->new_enabled)
9837                         crtc->new_config = &crtc->config;
9838                 else
9839                         crtc->new_config = NULL;
9840         }
9841
9842         count = 0;
9843         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9844                 encoder->new_crtc =
9845                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9846         }
9847
9848         count = 0;
9849         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9850                 connector->new_encoder =
9851                         to_intel_encoder(config->save_connector_encoders[count++]);
9852         }
9853 }
9854
9855 static bool
9856 is_crtc_connector_off(struct drm_mode_set *set)
9857 {
9858         int i;
9859
9860         if (set->num_connectors == 0)
9861                 return false;
9862
9863         if (WARN_ON(set->connectors == NULL))
9864                 return false;
9865
9866         for (i = 0; i < set->num_connectors; i++)
9867                 if (set->connectors[i]->encoder &&
9868                     set->connectors[i]->encoder->crtc == set->crtc &&
9869                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9870                         return true;
9871
9872         return false;
9873 }
9874
9875 static void
9876 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9877                                       struct intel_set_config *config)
9878 {
9879
9880         /* We should be able to check here if the fb has the same properties
9881          * and then just flip_or_move it */
9882         if (is_crtc_connector_off(set)) {
9883                 config->mode_changed = true;
9884         } else if (set->crtc->fb != set->fb) {
9885                 /* If we have no fb then treat it as a full mode set */
9886                 if (set->crtc->fb == NULL) {
9887                         struct intel_crtc *intel_crtc =
9888                                 to_intel_crtc(set->crtc);
9889
9890                         if (intel_crtc->active && i915.fastboot) {
9891                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9892                                 config->fb_changed = true;
9893                         } else {
9894                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9895                                 config->mode_changed = true;
9896                         }
9897                 } else if (set->fb == NULL) {
9898                         config->mode_changed = true;
9899                 } else if (set->fb->pixel_format !=
9900                            set->crtc->fb->pixel_format) {
9901                         config->mode_changed = true;
9902                 } else {
9903                         config->fb_changed = true;
9904                 }
9905         }
9906
9907         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9908                 config->fb_changed = true;
9909
9910         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9911                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9912                 drm_mode_debug_printmodeline(&set->crtc->mode);
9913                 drm_mode_debug_printmodeline(set->mode);
9914                 config->mode_changed = true;
9915         }
9916
9917         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9918                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9919 }
9920
9921 static int
9922 intel_modeset_stage_output_state(struct drm_device *dev,
9923                                  struct drm_mode_set *set,
9924                                  struct intel_set_config *config)
9925 {
9926         struct intel_connector *connector;
9927         struct intel_encoder *encoder;
9928         struct intel_crtc *crtc;
9929         int ro;
9930
9931         /* The upper layers ensure that we either disable a crtc or have a list
9932          * of connectors. For paranoia, double-check this. */
9933         WARN_ON(!set->fb && (set->num_connectors != 0));
9934         WARN_ON(set->fb && (set->num_connectors == 0));
9935
9936         list_for_each_entry(connector, &dev->mode_config.connector_list,
9937                             base.head) {
9938                 /* Otherwise traverse passed in connector list and get encoders
9939                  * for them. */
9940                 for (ro = 0; ro < set->num_connectors; ro++) {
9941                         if (set->connectors[ro] == &connector->base) {
9942                                 connector->new_encoder = connector->encoder;
9943                                 break;
9944                         }
9945                 }
9946
9947                 /* If we disable the crtc, disable all its connectors. Also, if
9948                  * the connector is on the changing crtc but not on the new
9949                  * connector list, disable it. */
9950                 if ((!set->fb || ro == set->num_connectors) &&
9951                     connector->base.encoder &&
9952                     connector->base.encoder->crtc == set->crtc) {
9953                         connector->new_encoder = NULL;
9954
9955                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9956                                 connector->base.base.id,
9957                                 drm_get_connector_name(&connector->base));
9958                 }
9959
9960
9961                 if (&connector->new_encoder->base != connector->base.encoder) {
9962                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9963                         config->mode_changed = true;
9964                 }
9965         }
9966         /* connector->new_encoder is now updated for all connectors. */
9967
9968         /* Update crtc of enabled connectors. */
9969         list_for_each_entry(connector, &dev->mode_config.connector_list,
9970                             base.head) {
9971                 struct drm_crtc *new_crtc;
9972
9973                 if (!connector->new_encoder)
9974                         continue;
9975
9976                 new_crtc = connector->new_encoder->base.crtc;
9977
9978                 for (ro = 0; ro < set->num_connectors; ro++) {
9979                         if (set->connectors[ro] == &connector->base)
9980                                 new_crtc = set->crtc;
9981                 }
9982
9983                 /* Make sure the new CRTC will work with the encoder */
9984                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
9985                                          new_crtc)) {
9986                         return -EINVAL;
9987                 }
9988                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9989
9990                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9991                         connector->base.base.id,
9992                         drm_get_connector_name(&connector->base),
9993                         new_crtc->base.id);
9994         }
9995
9996         /* Check for any encoders that needs to be disabled. */
9997         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9998                             base.head) {
9999                 int num_connectors = 0;
10000                 list_for_each_entry(connector,
10001                                     &dev->mode_config.connector_list,
10002                                     base.head) {
10003                         if (connector->new_encoder == encoder) {
10004                                 WARN_ON(!connector->new_encoder->new_crtc);
10005                                 num_connectors++;
10006                         }
10007                 }
10008
10009                 if (num_connectors == 0)
10010                         encoder->new_crtc = NULL;
10011                 else if (num_connectors > 1)
10012                         return -EINVAL;
10013
10014                 /* Only now check for crtc changes so we don't miss encoders
10015                  * that will be disabled. */
10016                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10017                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10018                         config->mode_changed = true;
10019                 }
10020         }
10021         /* Now we've also updated encoder->new_crtc for all encoders. */
10022
10023         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10024                             base.head) {
10025                 crtc->new_enabled = false;
10026
10027                 list_for_each_entry(encoder,
10028                                     &dev->mode_config.encoder_list,
10029                                     base.head) {
10030                         if (encoder->new_crtc == crtc) {
10031                                 crtc->new_enabled = true;
10032                                 break;
10033                         }
10034                 }
10035
10036                 if (crtc->new_enabled != crtc->base.enabled) {
10037                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10038                                       crtc->new_enabled ? "en" : "dis");
10039                         config->mode_changed = true;
10040                 }
10041
10042                 if (crtc->new_enabled)
10043                         crtc->new_config = &crtc->config;
10044                 else
10045                         crtc->new_config = NULL;
10046         }
10047
10048         return 0;
10049 }
10050
10051 static void disable_crtc_nofb(struct intel_crtc *crtc)
10052 {
10053         struct drm_device *dev = crtc->base.dev;
10054         struct intel_encoder *encoder;
10055         struct intel_connector *connector;
10056
10057         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10058                       pipe_name(crtc->pipe));
10059
10060         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10061                 if (connector->new_encoder &&
10062                     connector->new_encoder->new_crtc == crtc)
10063                         connector->new_encoder = NULL;
10064         }
10065
10066         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10067                 if (encoder->new_crtc == crtc)
10068                         encoder->new_crtc = NULL;
10069         }
10070
10071         crtc->new_enabled = false;
10072         crtc->new_config = NULL;
10073 }
10074
10075 static int intel_crtc_set_config(struct drm_mode_set *set)
10076 {
10077         struct drm_device *dev;
10078         struct drm_mode_set save_set;
10079         struct intel_set_config *config;
10080         int ret;
10081
10082         BUG_ON(!set);
10083         BUG_ON(!set->crtc);
10084         BUG_ON(!set->crtc->helper_private);
10085
10086         /* Enforce sane interface api - has been abused by the fb helper. */
10087         BUG_ON(!set->mode && set->fb);
10088         BUG_ON(set->fb && set->num_connectors == 0);
10089
10090         if (set->fb) {
10091                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10092                                 set->crtc->base.id, set->fb->base.id,
10093                                 (int)set->num_connectors, set->x, set->y);
10094         } else {
10095                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10096         }
10097
10098         dev = set->crtc->dev;
10099
10100         ret = -ENOMEM;
10101         config = kzalloc(sizeof(*config), GFP_KERNEL);
10102         if (!config)
10103                 goto out_config;
10104
10105         ret = intel_set_config_save_state(dev, config);
10106         if (ret)
10107                 goto out_config;
10108
10109         save_set.crtc = set->crtc;
10110         save_set.mode = &set->crtc->mode;
10111         save_set.x = set->crtc->x;
10112         save_set.y = set->crtc->y;
10113         save_set.fb = set->crtc->fb;
10114
10115         /* Compute whether we need a full modeset, only an fb base update or no
10116          * change at all. In the future we might also check whether only the
10117          * mode changed, e.g. for LVDS where we only change the panel fitter in
10118          * such cases. */
10119         intel_set_config_compute_mode_changes(set, config);
10120
10121         ret = intel_modeset_stage_output_state(dev, set, config);
10122         if (ret)
10123                 goto fail;
10124
10125         if (config->mode_changed) {
10126                 ret = intel_set_mode(set->crtc, set->mode,
10127                                      set->x, set->y, set->fb);
10128         } else if (config->fb_changed) {
10129                 intel_crtc_wait_for_pending_flips(set->crtc);
10130
10131                 ret = intel_pipe_set_base(set->crtc,
10132                                           set->x, set->y, set->fb);
10133                 /*
10134                  * In the fastboot case this may be our only check of the
10135                  * state after boot.  It would be better to only do it on
10136                  * the first update, but we don't have a nice way of doing that
10137                  * (and really, set_config isn't used much for high freq page
10138                  * flipping, so increasing its cost here shouldn't be a big
10139                  * deal).
10140                  */
10141                 if (i915.fastboot && ret == 0)
10142                         intel_modeset_check_state(set->crtc->dev);
10143         }
10144
10145         if (ret) {
10146                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10147                               set->crtc->base.id, ret);
10148 fail:
10149                 intel_set_config_restore_state(dev, config);
10150
10151                 /*
10152                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10153                  * force the pipe off to avoid oopsing in the modeset code
10154                  * due to fb==NULL. This should only happen during boot since
10155                  * we don't yet reconstruct the FB from the hardware state.
10156                  */
10157                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10158                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10159
10160                 /* Try to restore the config */
10161                 if (config->mode_changed &&
10162                     intel_set_mode(save_set.crtc, save_set.mode,
10163                                    save_set.x, save_set.y, save_set.fb))
10164                         DRM_ERROR("failed to restore config after modeset failure\n");
10165         }
10166
10167 out_config:
10168         intel_set_config_free(config);
10169         return ret;
10170 }
10171
10172 static const struct drm_crtc_funcs intel_crtc_funcs = {
10173         .cursor_set = intel_crtc_cursor_set,
10174         .cursor_move = intel_crtc_cursor_move,
10175         .gamma_set = intel_crtc_gamma_set,
10176         .set_config = intel_crtc_set_config,
10177         .destroy = intel_crtc_destroy,
10178         .page_flip = intel_crtc_page_flip,
10179 };
10180
10181 static void intel_cpu_pll_init(struct drm_device *dev)
10182 {
10183         if (HAS_DDI(dev))
10184                 intel_ddi_pll_init(dev);
10185 }
10186
10187 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10188                                       struct intel_shared_dpll *pll,
10189                                       struct intel_dpll_hw_state *hw_state)
10190 {
10191         uint32_t val;
10192
10193         val = I915_READ(PCH_DPLL(pll->id));
10194         hw_state->dpll = val;
10195         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10196         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10197
10198         return val & DPLL_VCO_ENABLE;
10199 }
10200
10201 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10202                                   struct intel_shared_dpll *pll)
10203 {
10204         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10205         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10206 }
10207
10208 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10209                                 struct intel_shared_dpll *pll)
10210 {
10211         /* PCH refclock must be enabled first */
10212         ibx_assert_pch_refclk_enabled(dev_priv);
10213
10214         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10215
10216         /* Wait for the clocks to stabilize. */
10217         POSTING_READ(PCH_DPLL(pll->id));
10218         udelay(150);
10219
10220         /* The pixel multiplier can only be updated once the
10221          * DPLL is enabled and the clocks are stable.
10222          *
10223          * So write it again.
10224          */
10225         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10226         POSTING_READ(PCH_DPLL(pll->id));
10227         udelay(200);
10228 }
10229
10230 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10231                                  struct intel_shared_dpll *pll)
10232 {
10233         struct drm_device *dev = dev_priv->dev;
10234         struct intel_crtc *crtc;
10235
10236         /* Make sure no transcoder isn't still depending on us. */
10237         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10238                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10239                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10240         }
10241
10242         I915_WRITE(PCH_DPLL(pll->id), 0);
10243         POSTING_READ(PCH_DPLL(pll->id));
10244         udelay(200);
10245 }
10246
10247 static char *ibx_pch_dpll_names[] = {
10248         "PCH DPLL A",
10249         "PCH DPLL B",
10250 };
10251
10252 static void ibx_pch_dpll_init(struct drm_device *dev)
10253 {
10254         struct drm_i915_private *dev_priv = dev->dev_private;
10255         int i;
10256
10257         dev_priv->num_shared_dpll = 2;
10258
10259         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10260                 dev_priv->shared_dplls[i].id = i;
10261                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10262                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10263                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10264                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10265                 dev_priv->shared_dplls[i].get_hw_state =
10266                         ibx_pch_dpll_get_hw_state;
10267         }
10268 }
10269
10270 static void intel_shared_dpll_init(struct drm_device *dev)
10271 {
10272         struct drm_i915_private *dev_priv = dev->dev_private;
10273
10274         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10275                 ibx_pch_dpll_init(dev);
10276         else
10277                 dev_priv->num_shared_dpll = 0;
10278
10279         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10280 }
10281
10282 static void intel_crtc_init(struct drm_device *dev, int pipe)
10283 {
10284         drm_i915_private_t *dev_priv = dev->dev_private;
10285         struct intel_crtc *intel_crtc;
10286         int i;
10287
10288         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10289         if (intel_crtc == NULL)
10290                 return;
10291
10292         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10293
10294         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10295         for (i = 0; i < 256; i++) {
10296                 intel_crtc->lut_r[i] = i;
10297                 intel_crtc->lut_g[i] = i;
10298                 intel_crtc->lut_b[i] = i;
10299         }
10300
10301         /*
10302          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10303          * is hooked to plane B. Hence we want plane A feeding pipe B.
10304          */
10305         intel_crtc->pipe = pipe;
10306         intel_crtc->plane = pipe;
10307         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10308                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10309                 intel_crtc->plane = !pipe;
10310         }
10311
10312         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10313                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10314         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10315         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10316
10317         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10318 }
10319
10320 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10321 {
10322         struct drm_encoder *encoder = connector->base.encoder;
10323
10324         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10325
10326         if (!encoder)
10327                 return INVALID_PIPE;
10328
10329         return to_intel_crtc(encoder->crtc)->pipe;
10330 }
10331
10332 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10333                                 struct drm_file *file)
10334 {
10335         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10336         struct drm_mode_object *drmmode_obj;
10337         struct intel_crtc *crtc;
10338
10339         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10340                 return -ENODEV;
10341
10342         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10343                         DRM_MODE_OBJECT_CRTC);
10344
10345         if (!drmmode_obj) {
10346                 DRM_ERROR("no such CRTC id\n");
10347                 return -ENOENT;
10348         }
10349
10350         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10351         pipe_from_crtc_id->pipe = crtc->pipe;
10352
10353         return 0;
10354 }
10355
10356 static int intel_encoder_clones(struct intel_encoder *encoder)
10357 {
10358         struct drm_device *dev = encoder->base.dev;
10359         struct intel_encoder *source_encoder;
10360         int index_mask = 0;
10361         int entry = 0;
10362
10363         list_for_each_entry(source_encoder,
10364                             &dev->mode_config.encoder_list, base.head) {
10365
10366                 if (encoder == source_encoder)
10367                         index_mask |= (1 << entry);
10368
10369                 /* Intel hw has only one MUX where enocoders could be cloned. */
10370                 if (encoder->cloneable && source_encoder->cloneable)
10371                         index_mask |= (1 << entry);
10372
10373                 entry++;
10374         }
10375
10376         return index_mask;
10377 }
10378
10379 static bool has_edp_a(struct drm_device *dev)
10380 {
10381         struct drm_i915_private *dev_priv = dev->dev_private;
10382
10383         if (!IS_MOBILE(dev))
10384                 return false;
10385
10386         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10387                 return false;
10388
10389         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10390                 return false;
10391
10392         return true;
10393 }
10394
10395 const char *intel_output_name(int output)
10396 {
10397         static const char *names[] = {
10398                 [INTEL_OUTPUT_UNUSED] = "Unused",
10399                 [INTEL_OUTPUT_ANALOG] = "Analog",
10400                 [INTEL_OUTPUT_DVO] = "DVO",
10401                 [INTEL_OUTPUT_SDVO] = "SDVO",
10402                 [INTEL_OUTPUT_LVDS] = "LVDS",
10403                 [INTEL_OUTPUT_TVOUT] = "TV",
10404                 [INTEL_OUTPUT_HDMI] = "HDMI",
10405                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10406                 [INTEL_OUTPUT_EDP] = "eDP",
10407                 [INTEL_OUTPUT_DSI] = "DSI",
10408                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10409         };
10410
10411         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10412                 return "Invalid";
10413
10414         return names[output];
10415 }
10416
10417 static void intel_setup_outputs(struct drm_device *dev)
10418 {
10419         struct drm_i915_private *dev_priv = dev->dev_private;
10420         struct intel_encoder *encoder;
10421         bool dpd_is_edp = false;
10422
10423         intel_lvds_init(dev);
10424
10425         if (!IS_ULT(dev))
10426                 intel_crt_init(dev);
10427
10428         if (HAS_DDI(dev)) {
10429                 int found;
10430
10431                 /* Haswell uses DDI functions to detect digital outputs */
10432                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10433                 /* DDI A only supports eDP */
10434                 if (found)
10435                         intel_ddi_init(dev, PORT_A);
10436
10437                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10438                  * register */
10439                 found = I915_READ(SFUSE_STRAP);
10440
10441                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10442                         intel_ddi_init(dev, PORT_B);
10443                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10444                         intel_ddi_init(dev, PORT_C);
10445                 if (found & SFUSE_STRAP_DDID_DETECTED)
10446                         intel_ddi_init(dev, PORT_D);
10447         } else if (HAS_PCH_SPLIT(dev)) {
10448                 int found;
10449                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10450
10451                 if (has_edp_a(dev))
10452                         intel_dp_init(dev, DP_A, PORT_A);
10453
10454                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10455                         /* PCH SDVOB multiplex with HDMIB */
10456                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10457                         if (!found)
10458                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10459                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10460                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10461                 }
10462
10463                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10464                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10465
10466                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10467                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10468
10469                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10470                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10471
10472                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10473                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10474         } else if (IS_VALLEYVIEW(dev)) {
10475                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10476                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10477                                         PORT_B);
10478                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10479                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10480                 }
10481
10482                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10483                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10484                                         PORT_C);
10485                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10486                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10487                 }
10488
10489                 intel_dsi_init(dev);
10490         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10491                 bool found = false;
10492
10493                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10494                         DRM_DEBUG_KMS("probing SDVOB\n");
10495                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10496                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10497                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10498                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10499                         }
10500
10501                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10502                                 intel_dp_init(dev, DP_B, PORT_B);
10503                 }
10504
10505                 /* Before G4X SDVOC doesn't have its own detect register */
10506
10507                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10508                         DRM_DEBUG_KMS("probing SDVOC\n");
10509                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10510                 }
10511
10512                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10513
10514                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10515                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10516                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10517                         }
10518                         if (SUPPORTS_INTEGRATED_DP(dev))
10519                                 intel_dp_init(dev, DP_C, PORT_C);
10520                 }
10521
10522                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10523                     (I915_READ(DP_D) & DP_DETECTED))
10524                         intel_dp_init(dev, DP_D, PORT_D);
10525         } else if (IS_GEN2(dev))
10526                 intel_dvo_init(dev);
10527
10528         if (SUPPORTS_TV(dev))
10529                 intel_tv_init(dev);
10530
10531         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10532                 encoder->base.possible_crtcs = encoder->crtc_mask;
10533                 encoder->base.possible_clones =
10534                         intel_encoder_clones(encoder);
10535         }
10536
10537         intel_init_pch_refclk(dev);
10538
10539         drm_helper_move_panel_connectors_to_head(dev);
10540 }
10541
10542 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10543 {
10544         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10545
10546         drm_framebuffer_cleanup(fb);
10547         WARN_ON(!intel_fb->obj->framebuffer_references--);
10548         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10549         kfree(intel_fb);
10550 }
10551
10552 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10553                                                 struct drm_file *file,
10554                                                 unsigned int *handle)
10555 {
10556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10557         struct drm_i915_gem_object *obj = intel_fb->obj;
10558
10559         return drm_gem_handle_create(file, &obj->base, handle);
10560 }
10561
10562 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10563         .destroy = intel_user_framebuffer_destroy,
10564         .create_handle = intel_user_framebuffer_create_handle,
10565 };
10566
10567 int intel_framebuffer_init(struct drm_device *dev,
10568                            struct intel_framebuffer *intel_fb,
10569                            struct drm_mode_fb_cmd2 *mode_cmd,
10570                            struct drm_i915_gem_object *obj)
10571 {
10572         int aligned_height;
10573         int pitch_limit;
10574         int ret;
10575
10576         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10577
10578         if (obj->tiling_mode == I915_TILING_Y) {
10579                 DRM_DEBUG("hardware does not support tiling Y\n");
10580                 return -EINVAL;
10581         }
10582
10583         if (mode_cmd->pitches[0] & 63) {
10584                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10585                           mode_cmd->pitches[0]);
10586                 return -EINVAL;
10587         }
10588
10589         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10590                 pitch_limit = 32*1024;
10591         } else if (INTEL_INFO(dev)->gen >= 4) {
10592                 if (obj->tiling_mode)
10593                         pitch_limit = 16*1024;
10594                 else
10595                         pitch_limit = 32*1024;
10596         } else if (INTEL_INFO(dev)->gen >= 3) {
10597                 if (obj->tiling_mode)
10598                         pitch_limit = 8*1024;
10599                 else
10600                         pitch_limit = 16*1024;
10601         } else
10602                 /* XXX DSPC is limited to 4k tiled */
10603                 pitch_limit = 8*1024;
10604
10605         if (mode_cmd->pitches[0] > pitch_limit) {
10606                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10607                           obj->tiling_mode ? "tiled" : "linear",
10608                           mode_cmd->pitches[0], pitch_limit);
10609                 return -EINVAL;
10610         }
10611
10612         if (obj->tiling_mode != I915_TILING_NONE &&
10613             mode_cmd->pitches[0] != obj->stride) {
10614                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10615                           mode_cmd->pitches[0], obj->stride);
10616                 return -EINVAL;
10617         }
10618
10619         /* Reject formats not supported by any plane early. */
10620         switch (mode_cmd->pixel_format) {
10621         case DRM_FORMAT_C8:
10622         case DRM_FORMAT_RGB565:
10623         case DRM_FORMAT_XRGB8888:
10624         case DRM_FORMAT_ARGB8888:
10625                 break;
10626         case DRM_FORMAT_XRGB1555:
10627         case DRM_FORMAT_ARGB1555:
10628                 if (INTEL_INFO(dev)->gen > 3) {
10629                         DRM_DEBUG("unsupported pixel format: %s\n",
10630                                   drm_get_format_name(mode_cmd->pixel_format));
10631                         return -EINVAL;
10632                 }
10633                 break;
10634         case DRM_FORMAT_XBGR8888:
10635         case DRM_FORMAT_ABGR8888:
10636         case DRM_FORMAT_XRGB2101010:
10637         case DRM_FORMAT_ARGB2101010:
10638         case DRM_FORMAT_XBGR2101010:
10639         case DRM_FORMAT_ABGR2101010:
10640                 if (INTEL_INFO(dev)->gen < 4) {
10641                         DRM_DEBUG("unsupported pixel format: %s\n",
10642                                   drm_get_format_name(mode_cmd->pixel_format));
10643                         return -EINVAL;
10644                 }
10645                 break;
10646         case DRM_FORMAT_YUYV:
10647         case DRM_FORMAT_UYVY:
10648         case DRM_FORMAT_YVYU:
10649         case DRM_FORMAT_VYUY:
10650                 if (INTEL_INFO(dev)->gen < 5) {
10651                         DRM_DEBUG("unsupported pixel format: %s\n",
10652                                   drm_get_format_name(mode_cmd->pixel_format));
10653                         return -EINVAL;
10654                 }
10655                 break;
10656         default:
10657                 DRM_DEBUG("unsupported pixel format: %s\n",
10658                           drm_get_format_name(mode_cmd->pixel_format));
10659                 return -EINVAL;
10660         }
10661
10662         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10663         if (mode_cmd->offsets[0] != 0)
10664                 return -EINVAL;
10665
10666         aligned_height = intel_align_height(dev, mode_cmd->height,
10667                                             obj->tiling_mode);
10668         /* FIXME drm helper for size checks (especially planar formats)? */
10669         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10670                 return -EINVAL;
10671
10672         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10673         intel_fb->obj = obj;
10674         intel_fb->obj->framebuffer_references++;
10675
10676         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10677         if (ret) {
10678                 DRM_ERROR("framebuffer init failed %d\n", ret);
10679                 return ret;
10680         }
10681
10682         return 0;
10683 }
10684
10685 static struct drm_framebuffer *
10686 intel_user_framebuffer_create(struct drm_device *dev,
10687                               struct drm_file *filp,
10688                               struct drm_mode_fb_cmd2 *mode_cmd)
10689 {
10690         struct drm_i915_gem_object *obj;
10691
10692         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10693                                                 mode_cmd->handles[0]));
10694         if (&obj->base == NULL)
10695                 return ERR_PTR(-ENOENT);
10696
10697         return intel_framebuffer_create(dev, mode_cmd, obj);
10698 }
10699
10700 #ifndef CONFIG_DRM_I915_FBDEV
10701 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10702 {
10703 }
10704 #endif
10705
10706 static const struct drm_mode_config_funcs intel_mode_funcs = {
10707         .fb_create = intel_user_framebuffer_create,
10708         .output_poll_changed = intel_fbdev_output_poll_changed,
10709 };
10710
10711 /* Set up chip specific display functions */
10712 static void intel_init_display(struct drm_device *dev)
10713 {
10714         struct drm_i915_private *dev_priv = dev->dev_private;
10715
10716         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10717                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10718         else if (IS_VALLEYVIEW(dev))
10719                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10720         else if (IS_PINEVIEW(dev))
10721                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10722         else
10723                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10724
10725         if (HAS_DDI(dev)) {
10726                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10727                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10728                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10729                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10730                 dev_priv->display.off = haswell_crtc_off;
10731                 dev_priv->display.update_plane = ironlake_update_plane;
10732         } else if (HAS_PCH_SPLIT(dev)) {
10733                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10734                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10735                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10736                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10737                 dev_priv->display.off = ironlake_crtc_off;
10738                 dev_priv->display.update_plane = ironlake_update_plane;
10739         } else if (IS_VALLEYVIEW(dev)) {
10740                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10741                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10742                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10743                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10744                 dev_priv->display.off = i9xx_crtc_off;
10745                 dev_priv->display.update_plane = i9xx_update_plane;
10746         } else {
10747                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10748                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10749                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10750                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10751                 dev_priv->display.off = i9xx_crtc_off;
10752                 dev_priv->display.update_plane = i9xx_update_plane;
10753         }
10754
10755         /* Returns the core display clock speed */
10756         if (IS_VALLEYVIEW(dev))
10757                 dev_priv->display.get_display_clock_speed =
10758                         valleyview_get_display_clock_speed;
10759         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10760                 dev_priv->display.get_display_clock_speed =
10761                         i945_get_display_clock_speed;
10762         else if (IS_I915G(dev))
10763                 dev_priv->display.get_display_clock_speed =
10764                         i915_get_display_clock_speed;
10765         else if (IS_I945GM(dev) || IS_845G(dev))
10766                 dev_priv->display.get_display_clock_speed =
10767                         i9xx_misc_get_display_clock_speed;
10768         else if (IS_PINEVIEW(dev))
10769                 dev_priv->display.get_display_clock_speed =
10770                         pnv_get_display_clock_speed;
10771         else if (IS_I915GM(dev))
10772                 dev_priv->display.get_display_clock_speed =
10773                         i915gm_get_display_clock_speed;
10774         else if (IS_I865G(dev))
10775                 dev_priv->display.get_display_clock_speed =
10776                         i865_get_display_clock_speed;
10777         else if (IS_I85X(dev))
10778                 dev_priv->display.get_display_clock_speed =
10779                         i855_get_display_clock_speed;
10780         else /* 852, 830 */
10781                 dev_priv->display.get_display_clock_speed =
10782                         i830_get_display_clock_speed;
10783
10784         if (HAS_PCH_SPLIT(dev)) {
10785                 if (IS_GEN5(dev)) {
10786                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10787                         dev_priv->display.write_eld = ironlake_write_eld;
10788                 } else if (IS_GEN6(dev)) {
10789                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10790                         dev_priv->display.write_eld = ironlake_write_eld;
10791                 } else if (IS_IVYBRIDGE(dev)) {
10792                         /* FIXME: detect B0+ stepping and use auto training */
10793                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10794                         dev_priv->display.write_eld = ironlake_write_eld;
10795                         dev_priv->display.modeset_global_resources =
10796                                 ivb_modeset_global_resources;
10797                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10798                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10799                         dev_priv->display.write_eld = haswell_write_eld;
10800                         dev_priv->display.modeset_global_resources =
10801                                 haswell_modeset_global_resources;
10802                 }
10803         } else if (IS_G4X(dev)) {
10804                 dev_priv->display.write_eld = g4x_write_eld;
10805         } else if (IS_VALLEYVIEW(dev)) {
10806                 dev_priv->display.modeset_global_resources =
10807                         valleyview_modeset_global_resources;
10808                 dev_priv->display.write_eld = ironlake_write_eld;
10809         }
10810
10811         /* Default just returns -ENODEV to indicate unsupported */
10812         dev_priv->display.queue_flip = intel_default_queue_flip;
10813
10814         switch (INTEL_INFO(dev)->gen) {
10815         case 2:
10816                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10817                 break;
10818
10819         case 3:
10820                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10821                 break;
10822
10823         case 4:
10824         case 5:
10825                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10826                 break;
10827
10828         case 6:
10829                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10830                 break;
10831         case 7:
10832         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10833                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10834                 break;
10835         }
10836
10837         intel_panel_init_backlight_funcs(dev);
10838 }
10839
10840 /*
10841  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10842  * resume, or other times.  This quirk makes sure that's the case for
10843  * affected systems.
10844  */
10845 static void quirk_pipea_force(struct drm_device *dev)
10846 {
10847         struct drm_i915_private *dev_priv = dev->dev_private;
10848
10849         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10850         DRM_INFO("applying pipe a force quirk\n");
10851 }
10852
10853 /*
10854  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10855  */
10856 static void quirk_ssc_force_disable(struct drm_device *dev)
10857 {
10858         struct drm_i915_private *dev_priv = dev->dev_private;
10859         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10860         DRM_INFO("applying lvds SSC disable quirk\n");
10861 }
10862
10863 /*
10864  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10865  * brightness value
10866  */
10867 static void quirk_invert_brightness(struct drm_device *dev)
10868 {
10869         struct drm_i915_private *dev_priv = dev->dev_private;
10870         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10871         DRM_INFO("applying inverted panel brightness quirk\n");
10872 }
10873
10874 struct intel_quirk {
10875         int device;
10876         int subsystem_vendor;
10877         int subsystem_device;
10878         void (*hook)(struct drm_device *dev);
10879 };
10880
10881 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10882 struct intel_dmi_quirk {
10883         void (*hook)(struct drm_device *dev);
10884         const struct dmi_system_id (*dmi_id_list)[];
10885 };
10886
10887 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10888 {
10889         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10890         return 1;
10891 }
10892
10893 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10894         {
10895                 .dmi_id_list = &(const struct dmi_system_id[]) {
10896                         {
10897                                 .callback = intel_dmi_reverse_brightness,
10898                                 .ident = "NCR Corporation",
10899                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10900                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10901                                 },
10902                         },
10903                         { }  /* terminating entry */
10904                 },
10905                 .hook = quirk_invert_brightness,
10906         },
10907 };
10908
10909 static struct intel_quirk intel_quirks[] = {
10910         /* HP Mini needs pipe A force quirk (LP: #322104) */
10911         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10912
10913         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10914         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10915
10916         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10917         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10918
10919         /* 830 needs to leave pipe A & dpll A up */
10920         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10921
10922         /* Lenovo U160 cannot use SSC on LVDS */
10923         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10924
10925         /* Sony Vaio Y cannot use SSC on LVDS */
10926         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10927
10928         /* Acer Aspire 5734Z must invert backlight brightness */
10929         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10930
10931         /* Acer/eMachines G725 */
10932         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10933
10934         /* Acer/eMachines e725 */
10935         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10936
10937         /* Acer/Packard Bell NCL20 */
10938         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10939
10940         /* Acer Aspire 4736Z */
10941         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10942
10943         /* Acer Aspire 5336 */
10944         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
10945 };
10946
10947 static void intel_init_quirks(struct drm_device *dev)
10948 {
10949         struct pci_dev *d = dev->pdev;
10950         int i;
10951
10952         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10953                 struct intel_quirk *q = &intel_quirks[i];
10954
10955                 if (d->device == q->device &&
10956                     (d->subsystem_vendor == q->subsystem_vendor ||
10957                      q->subsystem_vendor == PCI_ANY_ID) &&
10958                     (d->subsystem_device == q->subsystem_device ||
10959                      q->subsystem_device == PCI_ANY_ID))
10960                         q->hook(dev);
10961         }
10962         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10963                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10964                         intel_dmi_quirks[i].hook(dev);
10965         }
10966 }
10967
10968 /* Disable the VGA plane that we never use */
10969 static void i915_disable_vga(struct drm_device *dev)
10970 {
10971         struct drm_i915_private *dev_priv = dev->dev_private;
10972         u8 sr1;
10973         u32 vga_reg = i915_vgacntrl_reg(dev);
10974
10975         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
10976         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10977         outb(SR01, VGA_SR_INDEX);
10978         sr1 = inb(VGA_SR_DATA);
10979         outb(sr1 | 1<<5, VGA_SR_DATA);
10980         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10981         udelay(300);
10982
10983         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10984         POSTING_READ(vga_reg);
10985 }
10986
10987 void intel_modeset_init_hw(struct drm_device *dev)
10988 {
10989         intel_prepare_ddi(dev);
10990
10991         intel_init_clock_gating(dev);
10992
10993         intel_reset_dpio(dev);
10994
10995         mutex_lock(&dev->struct_mutex);
10996         intel_enable_gt_powersave(dev);
10997         mutex_unlock(&dev->struct_mutex);
10998 }
10999
11000 void intel_modeset_suspend_hw(struct drm_device *dev)
11001 {
11002         intel_suspend_hw(dev);
11003 }
11004
11005 void intel_modeset_init(struct drm_device *dev)
11006 {
11007         struct drm_i915_private *dev_priv = dev->dev_private;
11008         int i, j, ret;
11009
11010         drm_mode_config_init(dev);
11011
11012         dev->mode_config.min_width = 0;
11013         dev->mode_config.min_height = 0;
11014
11015         dev->mode_config.preferred_depth = 24;
11016         dev->mode_config.prefer_shadow = 1;
11017
11018         dev->mode_config.funcs = &intel_mode_funcs;
11019
11020         intel_init_quirks(dev);
11021
11022         intel_init_pm(dev);
11023
11024         if (INTEL_INFO(dev)->num_pipes == 0)
11025                 return;
11026
11027         intel_init_display(dev);
11028
11029         if (IS_GEN2(dev)) {
11030                 dev->mode_config.max_width = 2048;
11031                 dev->mode_config.max_height = 2048;
11032         } else if (IS_GEN3(dev)) {
11033                 dev->mode_config.max_width = 4096;
11034                 dev->mode_config.max_height = 4096;
11035         } else {
11036                 dev->mode_config.max_width = 8192;
11037                 dev->mode_config.max_height = 8192;
11038         }
11039         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11040
11041         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11042                       INTEL_INFO(dev)->num_pipes,
11043                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11044
11045         for_each_pipe(i) {
11046                 intel_crtc_init(dev, i);
11047                 for (j = 0; j < INTEL_INFO(dev)->num_sprites; j++) {
11048                         ret = intel_plane_init(dev, i, j);
11049                         if (ret)
11050                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11051                                               pipe_name(i), sprite_name(i, j), ret);
11052                 }
11053         }
11054
11055         intel_init_dpio(dev);
11056         intel_reset_dpio(dev);
11057
11058         intel_cpu_pll_init(dev);
11059         intel_shared_dpll_init(dev);
11060
11061         /* Just disable it once at startup */
11062         i915_disable_vga(dev);
11063         intel_setup_outputs(dev);
11064
11065         /* Just in case the BIOS is doing something questionable. */
11066         intel_disable_fbc(dev);
11067 }
11068
11069 static void
11070 intel_connector_break_all_links(struct intel_connector *connector)
11071 {
11072         connector->base.dpms = DRM_MODE_DPMS_OFF;
11073         connector->base.encoder = NULL;
11074         connector->encoder->connectors_active = false;
11075         connector->encoder->base.crtc = NULL;
11076 }
11077
11078 static void intel_enable_pipe_a(struct drm_device *dev)
11079 {
11080         struct intel_connector *connector;
11081         struct drm_connector *crt = NULL;
11082         struct intel_load_detect_pipe load_detect_temp;
11083
11084         /* We can't just switch on the pipe A, we need to set things up with a
11085          * proper mode and output configuration. As a gross hack, enable pipe A
11086          * by enabling the load detect pipe once. */
11087         list_for_each_entry(connector,
11088                             &dev->mode_config.connector_list,
11089                             base.head) {
11090                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11091                         crt = &connector->base;
11092                         break;
11093                 }
11094         }
11095
11096         if (!crt)
11097                 return;
11098
11099         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11100                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11101
11102
11103 }
11104
11105 static bool
11106 intel_check_plane_mapping(struct intel_crtc *crtc)
11107 {
11108         struct drm_device *dev = crtc->base.dev;
11109         struct drm_i915_private *dev_priv = dev->dev_private;
11110         u32 reg, val;
11111
11112         if (INTEL_INFO(dev)->num_pipes == 1)
11113                 return true;
11114
11115         reg = DSPCNTR(!crtc->plane);
11116         val = I915_READ(reg);
11117
11118         if ((val & DISPLAY_PLANE_ENABLE) &&
11119             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11120                 return false;
11121
11122         return true;
11123 }
11124
11125 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11126 {
11127         struct drm_device *dev = crtc->base.dev;
11128         struct drm_i915_private *dev_priv = dev->dev_private;
11129         u32 reg;
11130
11131         /* Clear any frame start delays used for debugging left by the BIOS */
11132         reg = PIPECONF(crtc->config.cpu_transcoder);
11133         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11134
11135         /* We need to sanitize the plane -> pipe mapping first because this will
11136          * disable the crtc (and hence change the state) if it is wrong. Note
11137          * that gen4+ has a fixed plane -> pipe mapping.  */
11138         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11139                 struct intel_connector *connector;
11140                 bool plane;
11141
11142                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11143                               crtc->base.base.id);
11144
11145                 /* Pipe has the wrong plane attached and the plane is active.
11146                  * Temporarily change the plane mapping and disable everything
11147                  * ...  */
11148                 plane = crtc->plane;
11149                 crtc->plane = !plane;
11150                 dev_priv->display.crtc_disable(&crtc->base);
11151                 crtc->plane = plane;
11152
11153                 /* ... and break all links. */
11154                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11155                                     base.head) {
11156                         if (connector->encoder->base.crtc != &crtc->base)
11157                                 continue;
11158
11159                         intel_connector_break_all_links(connector);
11160                 }
11161
11162                 WARN_ON(crtc->active);
11163                 crtc->base.enabled = false;
11164         }
11165
11166         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11167             crtc->pipe == PIPE_A && !crtc->active) {
11168                 /* BIOS forgot to enable pipe A, this mostly happens after
11169                  * resume. Force-enable the pipe to fix this, the update_dpms
11170                  * call below we restore the pipe to the right state, but leave
11171                  * the required bits on. */
11172                 intel_enable_pipe_a(dev);
11173         }
11174
11175         /* Adjust the state of the output pipe according to whether we
11176          * have active connectors/encoders. */
11177         intel_crtc_update_dpms(&crtc->base);
11178
11179         if (crtc->active != crtc->base.enabled) {
11180                 struct intel_encoder *encoder;
11181
11182                 /* This can happen either due to bugs in the get_hw_state
11183                  * functions or because the pipe is force-enabled due to the
11184                  * pipe A quirk. */
11185                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11186                               crtc->base.base.id,
11187                               crtc->base.enabled ? "enabled" : "disabled",
11188                               crtc->active ? "enabled" : "disabled");
11189
11190                 crtc->base.enabled = crtc->active;
11191
11192                 /* Because we only establish the connector -> encoder ->
11193                  * crtc links if something is active, this means the
11194                  * crtc is now deactivated. Break the links. connector
11195                  * -> encoder links are only establish when things are
11196                  *  actually up, hence no need to break them. */
11197                 WARN_ON(crtc->active);
11198
11199                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11200                         WARN_ON(encoder->connectors_active);
11201                         encoder->base.crtc = NULL;
11202                 }
11203         }
11204 }
11205
11206 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11207 {
11208         struct intel_connector *connector;
11209         struct drm_device *dev = encoder->base.dev;
11210
11211         /* We need to check both for a crtc link (meaning that the
11212          * encoder is active and trying to read from a pipe) and the
11213          * pipe itself being active. */
11214         bool has_active_crtc = encoder->base.crtc &&
11215                 to_intel_crtc(encoder->base.crtc)->active;
11216
11217         if (encoder->connectors_active && !has_active_crtc) {
11218                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11219                               encoder->base.base.id,
11220                               drm_get_encoder_name(&encoder->base));
11221
11222                 /* Connector is active, but has no active pipe. This is
11223                  * fallout from our resume register restoring. Disable
11224                  * the encoder manually again. */
11225                 if (encoder->base.crtc) {
11226                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11227                                       encoder->base.base.id,
11228                                       drm_get_encoder_name(&encoder->base));
11229                         encoder->disable(encoder);
11230                 }
11231
11232                 /* Inconsistent output/port/pipe state happens presumably due to
11233                  * a bug in one of the get_hw_state functions. Or someplace else
11234                  * in our code, like the register restore mess on resume. Clamp
11235                  * things to off as a safer default. */
11236                 list_for_each_entry(connector,
11237                                     &dev->mode_config.connector_list,
11238                                     base.head) {
11239                         if (connector->encoder != encoder)
11240                                 continue;
11241
11242                         intel_connector_break_all_links(connector);
11243                 }
11244         }
11245         /* Enabled encoders without active connectors will be fixed in
11246          * the crtc fixup. */
11247 }
11248
11249 void i915_redisable_vga(struct drm_device *dev)
11250 {
11251         struct drm_i915_private *dev_priv = dev->dev_private;
11252         u32 vga_reg = i915_vgacntrl_reg(dev);
11253
11254         /* This function can be called both from intel_modeset_setup_hw_state or
11255          * at a very early point in our resume sequence, where the power well
11256          * structures are not yet restored. Since this function is at a very
11257          * paranoid "someone might have enabled VGA while we were not looking"
11258          * level, just check if the power well is enabled instead of trying to
11259          * follow the "don't touch the power well if we don't need it" policy
11260          * the rest of the driver uses. */
11261         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11262             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11263                 return;
11264
11265         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11266                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11267                 i915_disable_vga(dev);
11268         }
11269 }
11270
11271 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11272 {
11273         struct drm_i915_private *dev_priv = dev->dev_private;
11274         enum pipe pipe;
11275         struct intel_crtc *crtc;
11276         struct intel_encoder *encoder;
11277         struct intel_connector *connector;
11278         int i;
11279
11280         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11281                             base.head) {
11282                 memset(&crtc->config, 0, sizeof(crtc->config));
11283
11284                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11285                                                                  &crtc->config);
11286
11287                 crtc->base.enabled = crtc->active;
11288                 crtc->primary_enabled = crtc->active;
11289
11290                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11291                               crtc->base.base.id,
11292                               crtc->active ? "enabled" : "disabled");
11293         }
11294
11295         /* FIXME: Smash this into the new shared dpll infrastructure. */
11296         if (HAS_DDI(dev))
11297                 intel_ddi_setup_hw_pll_state(dev);
11298
11299         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11300                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11301
11302                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11303                 pll->active = 0;
11304                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11305                                     base.head) {
11306                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11307                                 pll->active++;
11308                 }
11309                 pll->refcount = pll->active;
11310
11311                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11312                               pll->name, pll->refcount, pll->on);
11313         }
11314
11315         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11316                             base.head) {
11317                 pipe = 0;
11318
11319                 if (encoder->get_hw_state(encoder, &pipe)) {
11320                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11321                         encoder->base.crtc = &crtc->base;
11322                         encoder->get_config(encoder, &crtc->config);
11323                 } else {
11324                         encoder->base.crtc = NULL;
11325                 }
11326
11327                 encoder->connectors_active = false;
11328                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11329                               encoder->base.base.id,
11330                               drm_get_encoder_name(&encoder->base),
11331                               encoder->base.crtc ? "enabled" : "disabled",
11332                               pipe_name(pipe));
11333         }
11334
11335         list_for_each_entry(connector, &dev->mode_config.connector_list,
11336                             base.head) {
11337                 if (connector->get_hw_state(connector)) {
11338                         connector->base.dpms = DRM_MODE_DPMS_ON;
11339                         connector->encoder->connectors_active = true;
11340                         connector->base.encoder = &connector->encoder->base;
11341                 } else {
11342                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11343                         connector->base.encoder = NULL;
11344                 }
11345                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11346                               connector->base.base.id,
11347                               drm_get_connector_name(&connector->base),
11348                               connector->base.encoder ? "enabled" : "disabled");
11349         }
11350 }
11351
11352 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11353  * and i915 state tracking structures. */
11354 void intel_modeset_setup_hw_state(struct drm_device *dev,
11355                                   bool force_restore)
11356 {
11357         struct drm_i915_private *dev_priv = dev->dev_private;
11358         enum pipe pipe;
11359         struct intel_crtc *crtc;
11360         struct intel_encoder *encoder;
11361         int i;
11362
11363         intel_modeset_readout_hw_state(dev);
11364
11365         /*
11366          * Now that we have the config, copy it to each CRTC struct
11367          * Note that this could go away if we move to using crtc_config
11368          * checking everywhere.
11369          */
11370         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11371                             base.head) {
11372                 if (crtc->active && i915.fastboot) {
11373                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11374
11375                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11376                                       crtc->base.base.id);
11377                         drm_mode_debug_printmodeline(&crtc->base.mode);
11378                 }
11379         }
11380
11381         /* HW state is read out, now we need to sanitize this mess. */
11382         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11383                             base.head) {
11384                 intel_sanitize_encoder(encoder);
11385         }
11386
11387         for_each_pipe(pipe) {
11388                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11389                 intel_sanitize_crtc(crtc);
11390                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11391         }
11392
11393         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11394                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11395
11396                 if (!pll->on || pll->active)
11397                         continue;
11398
11399                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11400
11401                 pll->disable(dev_priv, pll);
11402                 pll->on = false;
11403         }
11404
11405         if (HAS_PCH_SPLIT(dev))
11406                 ilk_wm_get_hw_state(dev);
11407
11408         if (force_restore) {
11409                 i915_redisable_vga(dev);
11410
11411                 /*
11412                  * We need to use raw interfaces for restoring state to avoid
11413                  * checking (bogus) intermediate states.
11414                  */
11415                 for_each_pipe(pipe) {
11416                         struct drm_crtc *crtc =
11417                                 dev_priv->pipe_to_crtc_mapping[pipe];
11418
11419                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11420                                          crtc->fb);
11421                 }
11422         } else {
11423                 intel_modeset_update_staged_output_state(dev);
11424         }
11425
11426         intel_modeset_check_state(dev);
11427 }
11428
11429 void intel_modeset_gem_init(struct drm_device *dev)
11430 {
11431         intel_modeset_init_hw(dev);
11432
11433         intel_setup_overlay(dev);
11434
11435         mutex_lock(&dev->mode_config.mutex);
11436         intel_modeset_setup_hw_state(dev, false);
11437         mutex_unlock(&dev->mode_config.mutex);
11438 }
11439
11440 void intel_modeset_cleanup(struct drm_device *dev)
11441 {
11442         struct drm_i915_private *dev_priv = dev->dev_private;
11443         struct drm_crtc *crtc;
11444         struct drm_connector *connector;
11445
11446         /*
11447          * Interrupts and polling as the first thing to avoid creating havoc.
11448          * Too much stuff here (turning of rps, connectors, ...) would
11449          * experience fancy races otherwise.
11450          */
11451         drm_irq_uninstall(dev);
11452         cancel_work_sync(&dev_priv->hotplug_work);
11453         /*
11454          * Due to the hpd irq storm handling the hotplug work can re-arm the
11455          * poll handlers. Hence disable polling after hpd handling is shut down.
11456          */
11457         drm_kms_helper_poll_fini(dev);
11458
11459         mutex_lock(&dev->struct_mutex);
11460
11461         intel_unregister_dsm_handler();
11462
11463         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11464                 /* Skip inactive CRTCs */
11465                 if (!crtc->fb)
11466                         continue;
11467
11468                 intel_increase_pllclock(crtc);
11469         }
11470
11471         intel_disable_fbc(dev);
11472
11473         intel_disable_gt_powersave(dev);
11474
11475         ironlake_teardown_rc6(dev);
11476
11477         mutex_unlock(&dev->struct_mutex);
11478
11479         /* flush any delayed tasks or pending work */
11480         flush_scheduled_work();
11481
11482         /* destroy the backlight and sysfs files before encoders/connectors */
11483         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11484                 intel_panel_destroy_backlight(connector);
11485                 drm_sysfs_connector_remove(connector);
11486         }
11487
11488         drm_mode_config_cleanup(dev);
11489
11490         intel_cleanup_overlay(dev);
11491 }
11492
11493 /*
11494  * Return which encoder is currently attached for connector.
11495  */
11496 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11497 {
11498         return &intel_attached_encoder(connector)->base;
11499 }
11500
11501 void intel_connector_attach_encoder(struct intel_connector *connector,
11502                                     struct intel_encoder *encoder)
11503 {
11504         connector->encoder = encoder;
11505         drm_mode_connector_attach_encoder(&connector->base,
11506                                           &encoder->base);
11507 }
11508
11509 /*
11510  * set vga decode state - true == enable VGA decode
11511  */
11512 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11513 {
11514         struct drm_i915_private *dev_priv = dev->dev_private;
11515         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11516         u16 gmch_ctrl;
11517
11518         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11519                 DRM_ERROR("failed to read control word\n");
11520                 return -EIO;
11521         }
11522
11523         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11524                 return 0;
11525
11526         if (state)
11527                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11528         else
11529                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11530
11531         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11532                 DRM_ERROR("failed to write control word\n");
11533                 return -EIO;
11534         }
11535
11536         return 0;
11537 }
11538
11539 struct intel_display_error_state {
11540
11541         u32 power_well_driver;
11542
11543         int num_transcoders;
11544
11545         struct intel_cursor_error_state {
11546                 u32 control;
11547                 u32 position;
11548                 u32 base;
11549                 u32 size;
11550         } cursor[I915_MAX_PIPES];
11551
11552         struct intel_pipe_error_state {
11553                 bool power_domain_on;
11554                 u32 source;
11555         } pipe[I915_MAX_PIPES];
11556
11557         struct intel_plane_error_state {
11558                 u32 control;
11559                 u32 stride;
11560                 u32 size;
11561                 u32 pos;
11562                 u32 addr;
11563                 u32 surface;
11564                 u32 tile_offset;
11565         } plane[I915_MAX_PIPES];
11566
11567         struct intel_transcoder_error_state {
11568                 bool power_domain_on;
11569                 enum transcoder cpu_transcoder;
11570
11571                 u32 conf;
11572
11573                 u32 htotal;
11574                 u32 hblank;
11575                 u32 hsync;
11576                 u32 vtotal;
11577                 u32 vblank;
11578                 u32 vsync;
11579         } transcoder[4];
11580 };
11581
11582 struct intel_display_error_state *
11583 intel_display_capture_error_state(struct drm_device *dev)
11584 {
11585         drm_i915_private_t *dev_priv = dev->dev_private;
11586         struct intel_display_error_state *error;
11587         int transcoders[] = {
11588                 TRANSCODER_A,
11589                 TRANSCODER_B,
11590                 TRANSCODER_C,
11591                 TRANSCODER_EDP,
11592         };
11593         int i;
11594
11595         if (INTEL_INFO(dev)->num_pipes == 0)
11596                 return NULL;
11597
11598         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11599         if (error == NULL)
11600                 return NULL;
11601
11602         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11603                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11604
11605         for_each_pipe(i) {
11606                 error->pipe[i].power_domain_on =
11607                         intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11608                 if (!error->pipe[i].power_domain_on)
11609                         continue;
11610
11611                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11612                         error->cursor[i].control = I915_READ(CURCNTR(i));
11613                         error->cursor[i].position = I915_READ(CURPOS(i));
11614                         error->cursor[i].base = I915_READ(CURBASE(i));
11615                 } else {
11616                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11617                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11618                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11619                 }
11620
11621                 error->plane[i].control = I915_READ(DSPCNTR(i));
11622                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11623                 if (INTEL_INFO(dev)->gen <= 3) {
11624                         error->plane[i].size = I915_READ(DSPSIZE(i));
11625                         error->plane[i].pos = I915_READ(DSPPOS(i));
11626                 }
11627                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11628                         error->plane[i].addr = I915_READ(DSPADDR(i));
11629                 if (INTEL_INFO(dev)->gen >= 4) {
11630                         error->plane[i].surface = I915_READ(DSPSURF(i));
11631                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11632                 }
11633
11634                 error->pipe[i].source = I915_READ(PIPESRC(i));
11635         }
11636
11637         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11638         if (HAS_DDI(dev_priv->dev))
11639                 error->num_transcoders++; /* Account for eDP. */
11640
11641         for (i = 0; i < error->num_transcoders; i++) {
11642                 enum transcoder cpu_transcoder = transcoders[i];
11643
11644                 error->transcoder[i].power_domain_on =
11645                         intel_display_power_enabled_sw(dev,
11646                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
11647                 if (!error->transcoder[i].power_domain_on)
11648                         continue;
11649
11650                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11651
11652                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11653                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11654                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11655                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11656                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11657                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11658                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11659         }
11660
11661         return error;
11662 }
11663
11664 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11665
11666 void
11667 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11668                                 struct drm_device *dev,
11669                                 struct intel_display_error_state *error)
11670 {
11671         int i;
11672
11673         if (!error)
11674                 return;
11675
11676         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11677         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11678                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11679                            error->power_well_driver);
11680         for_each_pipe(i) {
11681                 err_printf(m, "Pipe [%d]:\n", i);
11682                 err_printf(m, "  Power: %s\n",
11683                            error->pipe[i].power_domain_on ? "on" : "off");
11684                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11685
11686                 err_printf(m, "Plane [%d]:\n", i);
11687                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11688                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11689                 if (INTEL_INFO(dev)->gen <= 3) {
11690                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11691                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11692                 }
11693                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11694                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11695                 if (INTEL_INFO(dev)->gen >= 4) {
11696                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11697                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11698                 }
11699
11700                 err_printf(m, "Cursor [%d]:\n", i);
11701                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11702                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11703                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11704         }
11705
11706         for (i = 0; i < error->num_transcoders; i++) {
11707                 err_printf(m, "CPU transcoder: %c\n",
11708                            transcoder_name(error->transcoder[i].cpu_transcoder));
11709                 err_printf(m, "  Power: %s\n",
11710                            error->transcoder[i].power_domain_on ? "on" : "off");
11711                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11712                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11713                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11714                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11715                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11716                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11717                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11718         }
11719 }