drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 /* returns HPLL frequency in kHz */
 137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         mutex_lock(&dev_priv->sb_lock);
 143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 144                 CCK_FUSE_HPLL_FREQ_MASK;
 145         mutex_unlock(&dev_priv->sb_lock);
 146
 147         return vco_freq[hpll_freq] * 1000;
 148 }
 149
 150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 151                                   const char *name, u32 reg)
 152 {
 153         u32 val;
 154         int divider;
 155
 156         if (dev_priv->hpll_freq == 0)
 157                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 158
 159         mutex_lock(&dev_priv->sb_lock);
 160         val = vlv_cck_read(dev_priv, reg);
 161         mutex_unlock(&dev_priv->sb_lock);
 162
 163         divider = val & CCK_FREQUENCY_VALUES;
 164
 165         WARN((val & CCK_FREQUENCY_STATUS) !=
 166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 167              "%s change in progress\n", name);
 168
 169         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 170 }
 171
 172 int
 173 intel_pch_rawclk(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176
 177         WARN_ON(!HAS_PCH_SPLIT(dev));
 178
 179         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 180 }
 181
 182 /* hrawclock is 1/4 the FSB frequency */
 183 int intel_hrawclk(struct drm_device *dev)
 184 {
 185         struct drm_i915_private *dev_priv = dev->dev_private;
 186         uint32_t clkcfg;
 187
 188         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 189         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 190                 return 200;
 191
 192         clkcfg = I915_READ(CLKCFG);
 193         switch (clkcfg & CLKCFG_FSB_MASK) {
 194         case CLKCFG_FSB_400:
 195                 return 100;
 196         case CLKCFG_FSB_533:
 197                 return 133;
 198         case CLKCFG_FSB_667:
 199                 return 166;
 200         case CLKCFG_FSB_800:
 201                 return 200;
 202         case CLKCFG_FSB_1067:
 203                 return 266;
 204         case CLKCFG_FSB_1333:
 205                 return 333;
 206         /* these two are just a guess; one of them might be right */
 207         case CLKCFG_FSB_1600:
 208         case CLKCFG_FSB_1600_ALT:
 209                 return 400;
 210         default:
 211                 return 133;
 212         }
 213 }
 214
 215 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 216 {
 217         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 218                 return;
 219
 220         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 221                                                       CCK_CZ_CLOCK_CONTROL);
 222
 223         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 224 }
 225
 226 static inline u32 /* units of 100MHz */
 227 intel_fdi_link_freq(struct drm_device *dev)
 228 {
 229         if (IS_GEN5(dev)) {
 230                 struct drm_i915_private *dev_priv = dev->dev_private;
 231                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 232         } else
 233                 return 27;
 234 }
 235
 236 static const intel_limit_t intel_limits_i8xx_dac = {
 237         .dot = { .min = 25000, .max = 350000 },
 238         .vco = { .min = 908000, .max = 1512000 },
 239         .n = { .min = 2, .max = 16 },
 240         .m = { .min = 96, .max = 140 },
 241         .m1 = { .min = 18, .max = 26 },
 242         .m2 = { .min = 6, .max = 16 },
 243         .p = { .min = 4, .max = 128 },
 244         .p1 = { .min = 2, .max = 33 },
 245         .p2 = { .dot_limit = 165000,
 246                 .p2_slow = 4, .p2_fast = 2 },
 247 };
 248
 249 static const intel_limit_t intel_limits_i8xx_dvo = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 908000, .max = 1512000 },
 252         .n = { .min = 2, .max = 16 },
 253         .m = { .min = 96, .max = 140 },
 254         .m1 = { .min = 18, .max = 26 },
 255         .m2 = { .min = 6, .max = 16 },
 256         .p = { .min = 4, .max = 128 },
 257         .p1 = { .min = 2, .max = 33 },
 258         .p2 = { .dot_limit = 165000,
 259                 .p2_slow = 4, .p2_fast = 4 },
 260 };
 261
 262 static const intel_limit_t intel_limits_i8xx_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 908000, .max = 1512000 },
 265         .n = { .min = 2, .max = 16 },
 266         .m = { .min = 96, .max = 140 },
 267         .m1 = { .min = 18, .max = 26 },
 268         .m2 = { .min = 6, .max = 16 },
 269         .p = { .min = 4, .max = 128 },
 270         .p1 = { .min = 1, .max = 6 },
 271         .p2 = { .dot_limit = 165000,
 272                 .p2_slow = 14, .p2_fast = 7 },
 273 };
 274
 275 static const intel_limit_t intel_limits_i9xx_sdvo = {
 276         .dot = { .min = 20000, .max = 400000 },
 277         .vco = { .min = 1400000, .max = 2800000 },
 278         .n = { .min = 1, .max = 6 },
 279         .m = { .min = 70, .max = 120 },
 280         .m1 = { .min = 8, .max = 18 },
 281         .m2 = { .min = 3, .max = 7 },
 282         .p = { .min = 5, .max = 80 },
 283         .p1 = { .min = 1, .max = 8 },
 284         .p2 = { .dot_limit = 200000,
 285                 .p2_slow = 10, .p2_fast = 5 },
 286 };
 287
 288 static const intel_limit_t intel_limits_i9xx_lvds = {
 289         .dot = { .min = 20000, .max = 400000 },
 290         .vco = { .min = 1400000, .max = 2800000 },
 291         .n = { .min = 1, .max = 6 },
 292         .m = { .min = 70, .max = 120 },
 293         .m1 = { .min = 8, .max = 18 },
 294         .m2 = { .min = 3, .max = 7 },
 295         .p = { .min = 7, .max = 98 },
 296         .p1 = { .min = 1, .max = 8 },
 297         .p2 = { .dot_limit = 112000,
 298                 .p2_slow = 14, .p2_fast = 7 },
 299 };
 300
 301
 302 static const intel_limit_t intel_limits_g4x_sdvo = {
 303         .dot = { .min = 25000, .max = 270000 },
 304         .vco = { .min = 1750000, .max = 3500000},
 305         .n = { .min = 1, .max = 4 },
 306         .m = { .min = 104, .max = 138 },
 307         .m1 = { .min = 17, .max = 23 },
 308         .m2 = { .min = 5, .max = 11 },
 309         .p = { .min = 10, .max = 30 },
 310         .p1 = { .min = 1, .max = 3},
 311         .p2 = { .dot_limit = 270000,
 312                 .p2_slow = 10,
 313                 .p2_fast = 10
 314         },
 315 };
 316
 317 static const intel_limit_t intel_limits_g4x_hdmi = {
 318         .dot = { .min = 22000, .max = 400000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 16, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 5, .max = 80 },
 325         .p1 = { .min = 1, .max = 8},
 326         .p2 = { .dot_limit = 165000,
 327                 .p2_slow = 10, .p2_fast = 5 },
 328 };
 329
 330 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 331         .dot = { .min = 20000, .max = 115000 },
 332         .vco = { .min = 1750000, .max = 3500000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 104, .max = 138 },
 335         .m1 = { .min = 17, .max = 23 },
 336         .m2 = { .min = 5, .max = 11 },
 337         .p = { .min = 28, .max = 112 },
 338         .p1 = { .min = 2, .max = 8 },
 339         .p2 = { .dot_limit = 0,
 340                 .p2_slow = 14, .p2_fast = 14
 341         },
 342 };
 343
 344 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 345         .dot = { .min = 80000, .max = 224000 },
 346         .vco = { .min = 1750000, .max = 3500000 },
 347         .n = { .min = 1, .max = 3 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 17, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 14, .max = 42 },
 352         .p1 = { .min = 2, .max = 6 },
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 7, .p2_fast = 7
 355         },
 356 };
 357
 358 static const intel_limit_t intel_limits_pineview_sdvo = {
 359         .dot = { .min = 20000, .max = 400000},
 360         .vco = { .min = 1700000, .max = 3500000 },
 361         /* Pineview's Ncounter is a ring counter */
 362         .n = { .min = 3, .max = 6 },
 363         .m = { .min = 2, .max = 256 },
 364         /* Pineview only has one combined m divider, which we treat as m2. */
 365         .m1 = { .min = 0, .max = 0 },
 366         .m2 = { .min = 0, .max = 254 },
 367         .p = { .min = 5, .max = 80 },
 368         .p1 = { .min = 1, .max = 8 },
 369         .p2 = { .dot_limit = 200000,
 370                 .p2_slow = 10, .p2_fast = 5 },
 371 };
 372
 373 static const intel_limit_t intel_limits_pineview_lvds = {
 374         .dot = { .min = 20000, .max = 400000 },
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         .n = { .min = 3, .max = 6 },
 377         .m = { .min = 2, .max = 256 },
 378         .m1 = { .min = 0, .max = 0 },
 379         .m2 = { .min = 0, .max = 254 },
 380         .p = { .min = 7, .max = 112 },
 381         .p1 = { .min = 1, .max = 8 },
 382         .p2 = { .dot_limit = 112000,
 383                 .p2_slow = 14, .p2_fast = 14 },
 384 };
 385
 386 /* Ironlake / Sandybridge
 387  *
 388  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 389  * the range value for them is (actual_value - 2).
 390  */
 391 static const intel_limit_t intel_limits_ironlake_dac = {
 392         .dot = { .min = 25000, .max = 350000 },
 393         .vco = { .min = 1760000, .max = 3510000 },
 394         .n = { .min = 1, .max = 5 },
 395         .m = { .min = 79, .max = 127 },
 396         .m1 = { .min = 12, .max = 22 },
 397         .m2 = { .min = 5, .max = 9 },
 398         .p = { .min = 5, .max = 80 },
 399         .p1 = { .min = 1, .max = 8 },
 400         .p2 = { .dot_limit = 225000,
 401                 .p2_slow = 10, .p2_fast = 5 },
 402 };
 403
 404 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 405         .dot = { .min = 25000, .max = 350000 },
 406         .vco = { .min = 1760000, .max = 3510000 },
 407         .n = { .min = 1, .max = 3 },
 408         .m = { .min = 79, .max = 118 },
 409         .m1 = { .min = 12, .max = 22 },
 410         .m2 = { .min = 5, .max = 9 },
 411         .p = { .min = 28, .max = 112 },
 412         .p1 = { .min = 2, .max = 8 },
 413         .p2 = { .dot_limit = 225000,
 414                 .p2_slow = 14, .p2_fast = 14 },
 415 };
 416
 417 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 418         .dot = { .min = 25000, .max = 350000 },
 419         .vco = { .min = 1760000, .max = 3510000 },
 420         .n = { .min = 1, .max = 3 },
 421         .m = { .min = 79, .max = 127 },
 422         .m1 = { .min = 12, .max = 22 },
 423         .m2 = { .min = 5, .max = 9 },
 424         .p = { .min = 14, .max = 56 },
 425         .p1 = { .min = 2, .max = 8 },
 426         .p2 = { .dot_limit = 225000,
 427                 .p2_slow = 7, .p2_fast = 7 },
 428 };
 429
 430 /* LVDS 100mhz refclk limits. */
 431 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 2 },
 435         .m = { .min = 79, .max = 126 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 126 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 42 },
 452         .p1 = { .min = 2, .max = 6 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 static const intel_limit_t intel_limits_vlv = {
 458          /*
 459           * These are the data rate limits (measured in fast clocks)
 460           * since those are the strictest limits we have. The fast
 461           * clock and actual rate limits are more relaxed, so checking
 462           * them would make no difference.
 463           */
 464         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 465         .vco = { .min = 4000000, .max = 6000000 },
 466         .n = { .min = 1, .max = 7 },
 467         .m1 = { .min = 2, .max = 3 },
 468         .m2 = { .min = 11, .max = 156 },
 469         .p1 = { .min = 2, .max = 3 },
 470         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 471 };
 472
 473 static const intel_limit_t intel_limits_chv = {
 474         /*
 475          * These are the data rate limits (measured in fast clocks)
 476          * since those are the strictest limits we have.  The fast
 477          * clock and actual rate limits are more relaxed, so checking
 478          * them would make no difference.
 479          */
 480         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 481         .vco = { .min = 4800000, .max = 6480000 },
 482         .n = { .min = 1, .max = 1 },
 483         .m1 = { .min = 2, .max = 2 },
 484         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 485         .p1 = { .min = 2, .max = 4 },
 486         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 487 };
 488
 489 static const intel_limit_t intel_limits_bxt = {
 490         /* FIXME: find real dot limits */
 491         .dot = { .min = 0, .max = INT_MAX },
 492         .vco = { .min = 4800000, .max = 6700000 },
 493         .n = { .min = 1, .max = 1 },
 494         .m1 = { .min = 2, .max = 2 },
 495         /* FIXME: find real m2 limits */
 496         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 497         .p1 = { .min = 2, .max = 4 },
 498         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 499 };
 500
 501 static bool
 502 needs_modeset(struct drm_crtc_state *state)
 503 {
 504         return drm_atomic_crtc_needs_modeset(state);
 505 }
 506
 507 /**
 508  * Returns whether any output on the specified pipe is of the specified type
 509  */
 510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 511 {
 512         struct drm_device *dev = crtc->base.dev;
 513         struct intel_encoder *encoder;
 514
 515         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 516                 if (encoder->type == type)
 517                         return true;
 518
 519         return false;
 520 }
 521
 522 /**
 523  * Returns whether any output on the specified pipe will have the specified
 524  * type after a staged modeset is complete, i.e., the same as
 525  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 526  * encoder->crtc.
 527  */
 528 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 529                                       int type)
 530 {
 531         struct drm_atomic_state *state = crtc_state->base.state;
 532         struct drm_connector *connector;
 533         struct drm_connector_state *connector_state;
 534         struct intel_encoder *encoder;
 535         int i, num_connectors = 0;
 536
 537         for_each_connector_in_state(state, connector, connector_state, i) {
 538                 if (connector_state->crtc != crtc_state->base.crtc)
 539                         continue;
 540
 541                 num_connectors++;
 542
 543                 encoder = to_intel_encoder(connector_state->best_encoder);
 544                 if (encoder->type == type)
 545                         return true;
 546         }
 547
 548         WARN_ON(num_connectors == 0);
 549
 550         return false;
 551 }
 552
 553 static const intel_limit_t *
 554 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 555 {
 556         struct drm_device *dev = crtc_state->base.crtc->dev;
 557         const intel_limit_t *limit;
 558
 559         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 560                 if (intel_is_dual_link_lvds(dev)) {
 561                         if (refclk == 100000)
 562                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 563                         else
 564                                 limit = &intel_limits_ironlake_dual_lvds;
 565                 } else {
 566                         if (refclk == 100000)
 567                                 limit = &intel_limits_ironlake_single_lvds_100m;
 568                         else
 569                                 limit = &intel_limits_ironlake_single_lvds;
 570                 }
 571         } else
 572                 limit = &intel_limits_ironlake_dac;
 573
 574         return limit;
 575 }
 576
 577 static const intel_limit_t *
 578 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 579 {
 580         struct drm_device *dev = crtc_state->base.crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 584                 if (intel_is_dual_link_lvds(dev))
 585                         limit = &intel_limits_g4x_dual_channel_lvds;
 586                 else
 587                         limit = &intel_limits_g4x_single_channel_lvds;
 588         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 589                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 590                 limit = &intel_limits_g4x_hdmi;
 591         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 592                 limit = &intel_limits_g4x_sdvo;
 593         } else /* The option is for other outputs */
 594                 limit = &intel_limits_i9xx_sdvo;
 595
 596         return limit;
 597 }
 598
 599 static const intel_limit_t *
 600 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 601 {
 602         struct drm_device *dev = crtc_state->base.crtc->dev;
 603         const intel_limit_t *limit;
 604
 605         if (IS_BROXTON(dev))
 606                 limit = &intel_limits_bxt;
 607         else if (HAS_PCH_SPLIT(dev))
 608                 limit = intel_ironlake_limit(crtc_state, refclk);
 609         else if (IS_G4X(dev)) {
 610                 limit = intel_g4x_limit(crtc_state);
 611         } else if (IS_PINEVIEW(dev)) {
 612                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 613                         limit = &intel_limits_pineview_lvds;
 614                 else
 615                         limit = &intel_limits_pineview_sdvo;
 616         } else if (IS_CHERRYVIEW(dev)) {
 617                 limit = &intel_limits_chv;
 618         } else if (IS_VALLEYVIEW(dev)) {
 619                 limit = &intel_limits_vlv;
 620         } else if (!IS_GEN2(dev)) {
 621                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 622                         limit = &intel_limits_i9xx_lvds;
 623                 else
 624                         limit = &intel_limits_i9xx_sdvo;
 625         } else {
 626                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 627                         limit = &intel_limits_i8xx_lvds;
 628                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 629                         limit = &intel_limits_i8xx_dvo;
 630                 else
 631                         limit = &intel_limits_i8xx_dac;
 632         }
 633         return limit;
 634 }
 635
 636 /*
 637  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 638  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 639  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 640  * The helpers' return value is the rate of the clock that is fed to the
 641  * display engine's pipe which can be the above fast dot clock rate or a
 642  * divided-down version of it.
 643  */
 644 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 645 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 646 {
 647         clock->m = clock->m2 + 2;
 648         clock->p = clock->p1 * clock->p2;
 649         if (WARN_ON(clock->n == 0 || clock->p == 0))
 650                 return 0;
 651         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 652         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 653
 654         return clock->dot;
 655 }
 656
 657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 658 {
 659         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 660 }
 661
 662 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 663 {
 664         clock->m = i9xx_dpll_compute_m(clock);
 665         clock->p = clock->p1 * clock->p2;
 666         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 667                 return 0;
 668         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 669         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 670
 671         return clock->dot;
 672 }
 673
 674 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 675 {
 676         clock->m = clock->m1 * clock->m2;
 677         clock->p = clock->p1 * clock->p2;
 678         if (WARN_ON(clock->n == 0 || clock->p == 0))
 679                 return 0;
 680         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 681         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 682
 683         return clock->dot / 5;
 684 }
 685
 686 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 687 {
 688         clock->m = clock->m1 * clock->m2;
 689         clock->p = clock->p1 * clock->p2;
 690         if (WARN_ON(clock->n == 0 || clock->p == 0))
 691                 return 0;
 692         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 693                         clock->n << 22);
 694         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 695
 696         return clock->dot / 5;
 697 }
 698
 699 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 700 /**
 701  * Returns whether the given set of divisors are valid for a given refclk with
 702  * the given connectors.
 703  */
 704
 705 static bool intel_PLL_is_valid(struct drm_device *dev,
 706                                const intel_limit_t *limit,
 707                                const intel_clock_t *clock)
 708 {
 709         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 710                 INTELPllInvalid("n out of range\n");
 711         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 712                 INTELPllInvalid("p1 out of range\n");
 713         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 714                 INTELPllInvalid("m2 out of range\n");
 715         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 716                 INTELPllInvalid("m1 out of range\n");
 717
 718         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 719             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 720                 if (clock->m1 <= clock->m2)
 721                         INTELPllInvalid("m1 <= m2\n");
 722
 723         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 724                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 725                         INTELPllInvalid("p out of range\n");
 726                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 727                         INTELPllInvalid("m out of range\n");
 728         }
 729
 730         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 731                 INTELPllInvalid("vco out of range\n");
 732         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 733          * connector, etc., rather than just a single range.
 734          */
 735         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 736                 INTELPllInvalid("dot out of range\n");
 737
 738         return true;
 739 }
 740
 741 static int
 742 i9xx_select_p2_div(const intel_limit_t *limit,
 743                    const struct intel_crtc_state *crtc_state,
 744                    int target)
 745 {
 746         struct drm_device *dev = crtc_state->base.crtc->dev;
 747
 748         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 749                 /*
 750                  * For LVDS just rely on its current settings for dual-channel.
 751                  * We haven't figured out how to reliably set up different
 752                  * single/dual channel state, if we even can.
 753                  */
 754                 if (intel_is_dual_link_lvds(dev))
 755                         return limit->p2.p2_fast;
 756                 else
 757                         return limit->p2.p2_slow;
 758         } else {
 759                 if (target < limit->p2.dot_limit)
 760                         return limit->p2.p2_slow;
 761                 else
 762                         return limit->p2.p2_fast;
 763         }
 764 }
 765
 766 static bool
 767 i9xx_find_best_dpll(const intel_limit_t *limit,
 768                     struct intel_crtc_state *crtc_state,
 769                     int target, int refclk, intel_clock_t *match_clock,
 770                     intel_clock_t *best_clock)
 771 {
 772         struct drm_device *dev = crtc_state->base.crtc->dev;
 773         intel_clock_t clock;
 774         int err = target;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 779
 780         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 781              clock.m1++) {
 782                 for (clock.m2 = limit->m2.min;
 783                      clock.m2 <= limit->m2.max; clock.m2++) {
 784                         if (clock.m2 >= clock.m1)
 785                                 break;
 786                         for (clock.n = limit->n.min;
 787                              clock.n <= limit->n.max; clock.n++) {
 788                                 for (clock.p1 = limit->p1.min;
 789                                         clock.p1 <= limit->p1.max; clock.p1++) {
 790                                         int this_err;
 791
 792                                         i9xx_calc_dpll_params(refclk, &clock);
 793                                         if (!intel_PLL_is_valid(dev, limit,
 794                                                                 &clock))
 795                                                 continue;
 796                                         if (match_clock &&
 797                                             clock.p != match_clock->p)
 798                                                 continue;
 799
 800                                         this_err = abs(clock.dot - target);
 801                                         if (this_err < err) {
 802                                                 *best_clock = clock;
 803                                                 err = this_err;
 804                                         }
 805                                 }
 806                         }
 807                 }
 808         }
 809
 810         return (err != target);
 811 }
 812
 813 static bool
 814 pnv_find_best_dpll(const intel_limit_t *limit,
 815                    struct intel_crtc_state *crtc_state,
 816                    int target, int refclk, intel_clock_t *match_clock,
 817                    intel_clock_t *best_clock)
 818 {
 819         struct drm_device *dev = crtc_state->base.crtc->dev;
 820         intel_clock_t clock;
 821         int err = target;
 822
 823         memset(best_clock, 0, sizeof(*best_clock));
 824
 825         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 826
 827         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 828              clock.m1++) {
 829                 for (clock.m2 = limit->m2.min;
 830                      clock.m2 <= limit->m2.max; clock.m2++) {
 831                         for (clock.n = limit->n.min;
 832                              clock.n <= limit->n.max; clock.n++) {
 833                                 for (clock.p1 = limit->p1.min;
 834                                         clock.p1 <= limit->p1.max; clock.p1++) {
 835                                         int this_err;
 836
 837                                         pnv_calc_dpll_params(refclk, &clock);
 838                                         if (!intel_PLL_is_valid(dev, limit,
 839                                                                 &clock))
 840                                                 continue;
 841                                         if (match_clock &&
 842                                             clock.p != match_clock->p)
 843                                                 continue;
 844
 845                                         this_err = abs(clock.dot - target);
 846                                         if (this_err < err) {
 847                                                 *best_clock = clock;
 848                                                 err = this_err;
 849                                         }
 850                                 }
 851                         }
 852                 }
 853         }
 854
 855         return (err != target);
 856 }
 857
 858 static bool
 859 g4x_find_best_dpll(const intel_limit_t *limit,
 860                    struct intel_crtc_state *crtc_state,
 861                    int target, int refclk, intel_clock_t *match_clock,
 862                    intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc_state->base.crtc->dev;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found = false;
 868         /* approximately equals target * 0.00585 */
 869         int err_most = (target >> 8) + (target >> 9);
 870
 871         memset(best_clock, 0, sizeof(*best_clock));
 872
 873         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 874
 875         max_n = limit->n.max;
 876         /* based on hardware requirement, prefer smaller n to precision */
 877         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 878                 /* based on hardware requirement, prefere larger m1,m2 */
 879                 for (clock.m1 = limit->m1.max;
 880                      clock.m1 >= limit->m1.min; clock.m1--) {
 881                         for (clock.m2 = limit->m2.max;
 882                              clock.m2 >= limit->m2.min; clock.m2--) {
 883                                 for (clock.p1 = limit->p1.max;
 884                                      clock.p1 >= limit->p1.min; clock.p1--) {
 885                                         int this_err;
 886
 887                                         i9xx_calc_dpll_params(refclk, &clock);
 888                                         if (!intel_PLL_is_valid(dev, limit,
 889                                                                 &clock))
 890                                                 continue;
 891
 892                                         this_err = abs(clock.dot - target);
 893                                         if (this_err < err_most) {
 894                                                 *best_clock = clock;
 895                                                 err_most = this_err;
 896                                                 max_n = clock.n;
 897                                                 found = true;
 898                                         }
 899                                 }
 900                         }
 901                 }
 902         }
 903         return found;
 904 }
 905
 906 /*
 907  * Check if the calculated PLL configuration is more optimal compared to the
 908  * best configuration and error found so far. Return the calculated error.
 909  */
 910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 911                                const intel_clock_t *calculated_clock,
 912                                const intel_clock_t *best_clock,
 913                                unsigned int best_error_ppm,
 914                                unsigned int *error_ppm)
 915 {
 916         /*
 917          * For CHV ignore the error and consider only the P value.
 918          * Prefer a bigger P value based on HW requirements.
 919          */
 920         if (IS_CHERRYVIEW(dev)) {
 921                 *error_ppm = 0;
 922
 923                 return calculated_clock->p > best_clock->p;
 924         }
 925
 926         if (WARN_ON_ONCE(!target_freq))
 927                 return false;
 928
 929         *error_ppm = div_u64(1000000ULL *
 930                                 abs(target_freq - calculated_clock->dot),
 931                              target_freq);
 932         /*
 933          * Prefer a better P value over a better (smaller) error if the error
 934          * is small. Ensure this preference for future configurations too by
 935          * setting the error to 0.
 936          */
 937         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 938                 *error_ppm = 0;
 939
 940                 return true;
 941         }
 942
 943         return *error_ppm + 10 < best_error_ppm;
 944 }
 945
 946 static bool
 947 vlv_find_best_dpll(const intel_limit_t *limit,
 948                    struct intel_crtc_state *crtc_state,
 949                    int target, int refclk, intel_clock_t *match_clock,
 950                    intel_clock_t *best_clock)
 951 {
 952         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 953         struct drm_device *dev = crtc->base.dev;
 954         intel_clock_t clock;
 955         unsigned int bestppm = 1000000;
 956         /* min update 19.2 MHz */
 957         int max_n = min(limit->n.max, refclk / 19200);
 958         bool found = false;
 959
 960         target *= 5; /* fast clock */
 961
 962         memset(best_clock, 0, sizeof(*best_clock));
 963
 964         /* based on hardware requirement, prefer smaller n to precision */
 965         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 966                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 967                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 968                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 969                                 clock.p = clock.p1 * clock.p2;
 970                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 971                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 972                                         unsigned int ppm;
 973
 974                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 975                                                                      refclk * clock.m1);
 976
 977                                         vlv_calc_dpll_params(refclk, &clock);
 978
 979                                         if (!intel_PLL_is_valid(dev, limit,
 980                                                                 &clock))
 981                                                 continue;
 982
 983                                         if (!vlv_PLL_is_optimal(dev, target,
 984                                                                 &clock,
 985                                                                 best_clock,
 986                                                                 bestppm, &ppm))
 987                                                 continue;
 988
 989                                         *best_clock = clock;
 990                                         bestppm = ppm;
 991                                         found = true;
 992                                 }
 993                         }
 994                 }
 995         }
 996
 997         return found;
 998 }
 999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002                    struct intel_crtc_state *crtc_state,
1003                    int target, int refclk, intel_clock_t *match_clock,
1004                    intel_clock_t *best_clock)
1005 {
1006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007         struct drm_device *dev = crtc->base.dev;
1008         unsigned int best_error_ppm;
1009         intel_clock_t clock;
1010         uint64_t m2;
1011         int found = false;
1012
1013         memset(best_clock, 0, sizeof(*best_clock));
1014         best_error_ppm = 1000000;
1015
1016         /*
1017          * Based on hardware doc, the n always set to 1, and m1 always
1018          * set to 2.  If requires to support 200Mhz refclk, we need to
1019          * revisit this because n may not 1 anymore.
1020          */
1021         clock.n = 1, clock.m1 = 2;
1022         target *= 5;    /* fast clock */
1023
1024         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025                 for (clock.p2 = limit->p2.p2_fast;
1026                                 clock.p2 >= limit->p2.p2_slow;
1027                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028                         unsigned int error_ppm;
1029
1030                         clock.p = clock.p1 * clock.p2;
1031
1032                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033                                         clock.n) << 22, refclk * clock.m1);
1034
1035                         if (m2 > INT_MAX/clock.m1)
1036                                 continue;
1037
1038                         clock.m2 = m2;
1039
1040                         chv_calc_dpll_params(refclk, &clock);
1041
1042                         if (!intel_PLL_is_valid(dev, limit, &clock))
1043                                 continue;
1044
1045                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046                                                 best_error_ppm, &error_ppm))
1047                                 continue;
1048
1049                         *best_clock = clock;
1050                         best_error_ppm = error_ppm;
1051                         found = true;
1052                 }
1053         }
1054
1055         return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059                         intel_clock_t *best_clock)
1060 {
1061         int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064                                   target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071         /* Be paranoid as we can arrive here with only partial
1072          * state retrieved from the hardware during setup.
1073          *
1074          * We can ditch the adjusted_mode.crtc_clock check as soon
1075          * as Haswell has gained clock readout/fastboot support.
1076          *
1077          * We can ditch the crtc->primary->fb check as soon as we can
1078          * properly reconstruct framebuffers.
1079          *
1080          * FIXME: The intel_crtc->active here should be switched to
1081          * crtc->state->active once we have proper CRTC states wired up
1082          * for atomic.
1083          */
1084         return intel_crtc->active && crtc->primary->state->fb &&
1085                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089                                              enum pipe pipe)
1090 {
1091         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094         return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         i915_reg_t reg = PIPEDSL(pipe);
1101         u32 line1, line2;
1102         u32 line_mask;
1103
1104         if (IS_GEN2(dev))
1105                 line_mask = DSL_LINEMASK_GEN2;
1106         else
1107                 line_mask = DSL_LINEMASK_GEN3;
1108
1109         line1 = I915_READ(reg) & line_mask;
1110         msleep(5);
1111         line2 = I915_READ(reg) & line_mask;
1112
1113         return line1 == line2;
1114 }
1115
1116 /*
1117  * intel_wait_for_pipe_off - wait for pipe to turn off
1118  * @crtc: crtc whose pipe to wait for
1119  *
1120  * After disabling a pipe, we can't wait for vblank in the usual way,
1121  * spinning on the vblank interrupt status bit, since we won't actually
1122  * see an interrupt when the pipe is disabled.
1123  *
1124  * On Gen4 and above:
1125  *   wait for the pipe register state bit to turn off
1126  *
1127  * Otherwise:
1128  *   wait for the display line value to settle (it usually
1129  *   ends up stopping at the start of the next frame).
1130  *
1131  */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134         struct drm_device *dev = crtc->base.dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137         enum pipe pipe = crtc->pipe;
1138
1139         if (INTEL_INFO(dev)->gen >= 4) {
1140                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142                 /* Wait for the Pipe State to go off */
1143                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144                              100))
1145                         WARN(1, "pipe_off wait timed out\n");
1146         } else {
1147                 /* Wait for the display line to settle */
1148                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149                         WARN(1, "pipe_off wait timed out\n");
1150         }
1151 }
1152
1153 static const char *state_string(bool enabled)
1154 {
1155         return enabled ? "on" : "off";
1156 }
1157
1158 /* Only for pre-ILK configs */
1159 void assert_pll(struct drm_i915_private *dev_priv,
1160                 enum pipe pipe, bool state)
1161 {
1162         u32 val;
1163         bool cur_state;
1164
1165         val = I915_READ(DPLL(pipe));
1166         cur_state = !!(val & DPLL_VCO_ENABLE);
1167         I915_STATE_WARN(cur_state != state,
1168              "PLL state assertion failure (expected %s, current %s)\n",
1169              state_string(state), state_string(cur_state));
1170 }
1171
1172 /* XXX: the dsi pll is shared between MIPI DSI ports */
1173 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174 {
1175         u32 val;
1176         bool cur_state;
1177
1178         mutex_lock(&dev_priv->sb_lock);
1179         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1180         mutex_unlock(&dev_priv->sb_lock);
1181
1182         cur_state = val & DSI_PLL_VCO_EN;
1183         I915_STATE_WARN(cur_state != state,
1184              "DSI PLL state assertion failure (expected %s, current %s)\n",
1185              state_string(state), state_string(cur_state));
1186 }
1187 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
1190 struct intel_shared_dpll *
1191 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192 {
1193         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
1195         if (crtc->config->shared_dpll < 0)
1196                 return NULL;
1197
1198         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1199 }
1200
1201 /* For ILK+ */
1202 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203                         struct intel_shared_dpll *pll,
1204                         bool state)
1205 {
1206         bool cur_state;
1207         struct intel_dpll_hw_state hw_state;
1208
1209         if (WARN (!pll,
1210                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1211                 return;
1212
1213         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1214         I915_STATE_WARN(cur_state != state,
1215              "%s assertion failure (expected %s, current %s)\n",
1216              pll->name, state_string(state), state_string(cur_state));
1217 }
1218
1219 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220                           enum pipe pipe, bool state)
1221 {
1222         bool cur_state;
1223         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224                                                                       pipe);
1225
1226         if (HAS_DDI(dev_priv->dev)) {
1227                 /* DDI does not have a specific FDI_TX register */
1228                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1229                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1230         } else {
1231                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1232                 cur_state = !!(val & FDI_TX_ENABLE);
1233         }
1234         I915_STATE_WARN(cur_state != state,
1235              "FDI TX state assertion failure (expected %s, current %s)\n",
1236              state_string(state), state_string(cur_state));
1237 }
1238 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1239 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1240
1241 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1242                           enum pipe pipe, bool state)
1243 {
1244         u32 val;
1245         bool cur_state;
1246
1247         val = I915_READ(FDI_RX_CTL(pipe));
1248         cur_state = !!(val & FDI_RX_ENABLE);
1249         I915_STATE_WARN(cur_state != state,
1250              "FDI RX state assertion failure (expected %s, current %s)\n",
1251              state_string(state), state_string(cur_state));
1252 }
1253 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1254 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1255
1256 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1257                                       enum pipe pipe)
1258 {
1259         u32 val;
1260
1261         /* ILK FDI PLL is always enabled */
1262         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1263                 return;
1264
1265         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1266         if (HAS_DDI(dev_priv->dev))
1267                 return;
1268
1269         val = I915_READ(FDI_TX_CTL(pipe));
1270         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1271 }
1272
1273 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1274                        enum pipe pipe, bool state)
1275 {
1276         u32 val;
1277         bool cur_state;
1278
1279         val = I915_READ(FDI_RX_CTL(pipe));
1280         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1281         I915_STATE_WARN(cur_state != state,
1282              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1283              state_string(state), state_string(cur_state));
1284 }
1285
1286 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1287                            enum pipe pipe)
1288 {
1289         struct drm_device *dev = dev_priv->dev;
1290         i915_reg_t pp_reg;
1291         u32 val;
1292         enum pipe panel_pipe = PIPE_A;
1293         bool locked = true;
1294
1295         if (WARN_ON(HAS_DDI(dev)))
1296                 return;
1297
1298         if (HAS_PCH_SPLIT(dev)) {
1299                 u32 port_sel;
1300
1301                 pp_reg = PCH_PP_CONTROL;
1302                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1303
1304                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1305                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1306                         panel_pipe = PIPE_B;
1307                 /* XXX: else fix for eDP */
1308         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1309                 /* presumably write lock depends on pipe, not port select */
1310                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1311                 panel_pipe = pipe;
1312         } else {
1313                 pp_reg = PP_CONTROL;
1314                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1315                         panel_pipe = PIPE_B;
1316         }
1317
1318         val = I915_READ(pp_reg);
1319         if (!(val & PANEL_POWER_ON) ||
1320             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1321                 locked = false;
1322
1323         I915_STATE_WARN(panel_pipe == pipe && locked,
1324              "panel assertion failure, pipe %c regs locked\n",
1325              pipe_name(pipe));
1326 }
1327
1328 static void assert_cursor(struct drm_i915_private *dev_priv,
1329                           enum pipe pipe, bool state)
1330 {
1331         struct drm_device *dev = dev_priv->dev;
1332         bool cur_state;
1333
1334         if (IS_845G(dev) || IS_I865G(dev))
1335                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1336         else
1337                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1338
1339         I915_STATE_WARN(cur_state != state,
1340              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1341              pipe_name(pipe), state_string(state), state_string(cur_state));
1342 }
1343 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1344 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1345
1346 void assert_pipe(struct drm_i915_private *dev_priv,
1347                  enum pipe pipe, bool state)
1348 {
1349         bool cur_state;
1350         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1351                                                                       pipe);
1352
1353         /* if we need the pipe quirk it must be always on */
1354         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1355             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1356                 state = true;
1357
1358         if (!intel_display_power_is_enabled(dev_priv,
1359                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1360                 cur_state = false;
1361         } else {
1362                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1363                 cur_state = !!(val & PIPECONF_ENABLE);
1364         }
1365
1366         I915_STATE_WARN(cur_state != state,
1367              "pipe %c assertion failure (expected %s, current %s)\n",
1368              pipe_name(pipe), state_string(state), state_string(cur_state));
1369 }
1370
1371 static void assert_plane(struct drm_i915_private *dev_priv,
1372                          enum plane plane, bool state)
1373 {
1374         u32 val;
1375         bool cur_state;
1376
1377         val = I915_READ(DSPCNTR(plane));
1378         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1379         I915_STATE_WARN(cur_state != state,
1380              "plane %c assertion failure (expected %s, current %s)\n",
1381              plane_name(plane), state_string(state), state_string(cur_state));
1382 }
1383
1384 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1385 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1386
1387 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1388                                    enum pipe pipe)
1389 {
1390         struct drm_device *dev = dev_priv->dev;
1391         int i;
1392
1393         /* Primary planes are fixed to pipes on gen4+ */
1394         if (INTEL_INFO(dev)->gen >= 4) {
1395                 u32 val = I915_READ(DSPCNTR(pipe));
1396                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1397                      "plane %c assertion failure, should be disabled but not\n",
1398                      plane_name(pipe));
1399                 return;
1400         }
1401
1402         /* Need to check both planes against the pipe */
1403         for_each_pipe(dev_priv, i) {
1404                 u32 val = I915_READ(DSPCNTR(i));
1405                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1406                         DISPPLANE_SEL_PIPE_SHIFT;
1407                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1408                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1409                      plane_name(i), pipe_name(pipe));
1410         }
1411 }
1412
1413 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1414                                     enum pipe pipe)
1415 {
1416         struct drm_device *dev = dev_priv->dev;
1417         int sprite;
1418
1419         if (INTEL_INFO(dev)->gen >= 9) {
1420                 for_each_sprite(dev_priv, pipe, sprite) {
1421                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1422                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1423                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1424                              sprite, pipe_name(pipe));
1425                 }
1426         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1427                 for_each_sprite(dev_priv, pipe, sprite) {
1428                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1429                         I915_STATE_WARN(val & SP_ENABLE,
1430                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431                              sprite_name(pipe, sprite), pipe_name(pipe));
1432                 }
1433         } else if (INTEL_INFO(dev)->gen >= 7) {
1434                 u32 val = I915_READ(SPRCTL(pipe));
1435                 I915_STATE_WARN(val & SPRITE_ENABLE,
1436                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1437                      plane_name(pipe), pipe_name(pipe));
1438         } else if (INTEL_INFO(dev)->gen >= 5) {
1439                 u32 val = I915_READ(DVSCNTR(pipe));
1440                 I915_STATE_WARN(val & DVS_ENABLE,
1441                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1442                      plane_name(pipe), pipe_name(pipe));
1443         }
1444 }
1445
1446 static void assert_vblank_disabled(struct drm_crtc *crtc)
1447 {
1448         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1449                 drm_crtc_vblank_put(crtc);
1450 }
1451
1452 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1453 {
1454         u32 val;
1455         bool enabled;
1456
1457         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1458
1459         val = I915_READ(PCH_DREF_CONTROL);
1460         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1461                             DREF_SUPERSPREAD_SOURCE_MASK));
1462         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1463 }
1464
1465 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1466                                            enum pipe pipe)
1467 {
1468         u32 val;
1469         bool enabled;
1470
1471         val = I915_READ(PCH_TRANSCONF(pipe));
1472         enabled = !!(val & TRANS_ENABLE);
1473         I915_STATE_WARN(enabled,
1474              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1475              pipe_name(pipe));
1476 }
1477
1478 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1479                             enum pipe pipe, u32 port_sel, u32 val)
1480 {
1481         if ((val & DP_PORT_EN) == 0)
1482                 return false;
1483
1484         if (HAS_PCH_CPT(dev_priv->dev)) {
1485                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1486                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1487                         return false;
1488         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1489                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1490                         return false;
1491         } else {
1492                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1493                         return false;
1494         }
1495         return true;
1496 }
1497
1498 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1499                               enum pipe pipe, u32 val)
1500 {
1501         if ((val & SDVO_ENABLE) == 0)
1502                 return false;
1503
1504         if (HAS_PCH_CPT(dev_priv->dev)) {
1505                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1506                         return false;
1507         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1508                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1509                         return false;
1510         } else {
1511                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1512                         return false;
1513         }
1514         return true;
1515 }
1516
1517 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1518                               enum pipe pipe, u32 val)
1519 {
1520         if ((val & LVDS_PORT_EN) == 0)
1521                 return false;
1522
1523         if (HAS_PCH_CPT(dev_priv->dev)) {
1524                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1525                         return false;
1526         } else {
1527                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1528                         return false;
1529         }
1530         return true;
1531 }
1532
1533 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1534                               enum pipe pipe, u32 val)
1535 {
1536         if ((val & ADPA_DAC_ENABLE) == 0)
1537                 return false;
1538         if (HAS_PCH_CPT(dev_priv->dev)) {
1539                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1540                         return false;
1541         } else {
1542                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1543                         return false;
1544         }
1545         return true;
1546 }
1547
1548 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1549                                    enum pipe pipe, i915_reg_t reg,
1550                                    u32 port_sel)
1551 {
1552         u32 val = I915_READ(reg);
1553         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1554              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1555              i915_mmio_reg_offset(reg), pipe_name(pipe));
1556
1557         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1558              && (val & DP_PIPEB_SELECT),
1559              "IBX PCH dp port still using transcoder B\n");
1560 }
1561
1562 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1563                                      enum pipe pipe, i915_reg_t reg)
1564 {
1565         u32 val = I915_READ(reg);
1566         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1567              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1568              i915_mmio_reg_offset(reg), pipe_name(pipe));
1569
1570         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1571              && (val & SDVO_PIPE_B_SELECT),
1572              "IBX PCH hdmi port still using transcoder B\n");
1573 }
1574
1575 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1576                                       enum pipe pipe)
1577 {
1578         u32 val;
1579
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1581         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1582         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1583
1584         val = I915_READ(PCH_ADPA);
1585         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1586              "PCH VGA enabled on transcoder %c, should be disabled\n",
1587              pipe_name(pipe));
1588
1589         val = I915_READ(PCH_LVDS);
1590         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1591              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1592              pipe_name(pipe));
1593
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1595         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1596         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1597 }
1598
1599 static void vlv_enable_pll(struct intel_crtc *crtc,
1600                            const struct intel_crtc_state *pipe_config)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         i915_reg_t reg = DPLL(crtc->pipe);
1605         u32 dpll = pipe_config->dpll_hw_state.dpll;
1606
1607         assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev_priv->dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         I915_WRITE(reg, dpll);
1614         POSTING_READ(reg);
1615         udelay(150);
1616
1617         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1618                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1619
1620         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1621         POSTING_READ(DPLL_MD(crtc->pipe));
1622
1623         /* We do this three times for luck */
1624         I915_WRITE(reg, dpll);
1625         POSTING_READ(reg);
1626         udelay(150); /* wait for warmup */
1627         I915_WRITE(reg, dpll);
1628         POSTING_READ(reg);
1629         udelay(150); /* wait for warmup */
1630         I915_WRITE(reg, dpll);
1631         POSTING_READ(reg);
1632         udelay(150); /* wait for warmup */
1633 }
1634
1635 static void chv_enable_pll(struct intel_crtc *crtc,
1636                            const struct intel_crtc_state *pipe_config)
1637 {
1638         struct drm_device *dev = crtc->base.dev;
1639         struct drm_i915_private *dev_priv = dev->dev_private;
1640         int pipe = crtc->pipe;
1641         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1642         u32 tmp;
1643
1644         assert_pipe_disabled(dev_priv, crtc->pipe);
1645
1646         mutex_lock(&dev_priv->sb_lock);
1647
1648         /* Enable back the 10bit clock to display controller */
1649         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1650         tmp |= DPIO_DCLKP_EN;
1651         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1652
1653         mutex_unlock(&dev_priv->sb_lock);
1654
1655         /*
1656          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1657          */
1658         udelay(1);
1659
1660         /* Enable PLL */
1661         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1662
1663         /* Check PLL is locked */
1664         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1665                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1666
1667         /* not sure when this should be written */
1668         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1669         POSTING_READ(DPLL_MD(pipe));
1670 }
1671
1672 static int intel_num_dvo_pipes(struct drm_device *dev)
1673 {
1674         struct intel_crtc *crtc;
1675         int count = 0;
1676
1677         for_each_intel_crtc(dev, crtc)
1678                 count += crtc->base.state->active &&
1679                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1680
1681         return count;
1682 }
1683
1684 static void i9xx_enable_pll(struct intel_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->base.dev;
1687         struct drm_i915_private *dev_priv = dev->dev_private;
1688         i915_reg_t reg = DPLL(crtc->pipe);
1689         u32 dpll = crtc->config->dpll_hw_state.dpll;
1690
1691         assert_pipe_disabled(dev_priv, crtc->pipe);
1692
1693         /* No really, not for ILK+ */
1694         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1695
1696         /* PLL is protected by panel, make sure we can write it */
1697         if (IS_MOBILE(dev) && !IS_I830(dev))
1698                 assert_panel_unlocked(dev_priv, crtc->pipe);
1699
1700         /* Enable DVO 2x clock on both PLLs if necessary */
1701         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1702                 /*
1703                  * It appears to be important that we don't enable this
1704                  * for the current pipe before otherwise configuring the
1705                  * PLL. No idea how this should be handled if multiple
1706                  * DVO outputs are enabled simultaneosly.
1707                  */
1708                 dpll |= DPLL_DVO_2X_MODE;
1709                 I915_WRITE(DPLL(!crtc->pipe),
1710                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1711         }
1712
1713         /*
1714          * Apparently we need to have VGA mode enabled prior to changing
1715          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1716          * dividers, even though the register value does change.
1717          */
1718         I915_WRITE(reg, 0);
1719
1720         I915_WRITE(reg, dpll);
1721
1722         /* Wait for the clocks to stabilize. */
1723         POSTING_READ(reg);
1724         udelay(150);
1725
1726         if (INTEL_INFO(dev)->gen >= 4) {
1727                 I915_WRITE(DPLL_MD(crtc->pipe),
1728                            crtc->config->dpll_hw_state.dpll_md);
1729         } else {
1730                 /* The pixel multiplier can only be updated once the
1731                  * DPLL is enabled and the clocks are stable.
1732                  *
1733                  * So write it again.
1734                  */
1735                 I915_WRITE(reg, dpll);
1736         }
1737
1738         /* We do this three times for luck */
1739         I915_WRITE(reg, dpll);
1740         POSTING_READ(reg);
1741         udelay(150); /* wait for warmup */
1742         I915_WRITE(reg, dpll);
1743         POSTING_READ(reg);
1744         udelay(150); /* wait for warmup */
1745         I915_WRITE(reg, dpll);
1746         POSTING_READ(reg);
1747         udelay(150); /* wait for warmup */
1748 }
1749
1750 /**
1751  * i9xx_disable_pll - disable a PLL
1752  * @dev_priv: i915 private structure
1753  * @pipe: pipe PLL to disable
1754  *
1755  * Disable the PLL for @pipe, making sure the pipe is off first.
1756  *
1757  * Note!  This is for pre-ILK only.
1758  */
1759 static void i9xx_disable_pll(struct intel_crtc *crtc)
1760 {
1761         struct drm_device *dev = crtc->base.dev;
1762         struct drm_i915_private *dev_priv = dev->dev_private;
1763         enum pipe pipe = crtc->pipe;
1764
1765         /* Disable DVO 2x clock on both PLLs if necessary */
1766         if (IS_I830(dev) &&
1767             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1768             !intel_num_dvo_pipes(dev)) {
1769                 I915_WRITE(DPLL(PIPE_B),
1770                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1771                 I915_WRITE(DPLL(PIPE_A),
1772                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1773         }
1774
1775         /* Don't disable pipe or pipe PLLs if needed */
1776         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1777             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1778                 return;
1779
1780         /* Make sure the pipe isn't still relying on us */
1781         assert_pipe_disabled(dev_priv, pipe);
1782
1783         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1784         POSTING_READ(DPLL(pipe));
1785 }
1786
1787 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1788 {
1789         u32 val;
1790
1791         /* Make sure the pipe isn't still relying on us */
1792         assert_pipe_disabled(dev_priv, pipe);
1793
1794         /*
1795          * Leave integrated clock source and reference clock enabled for pipe B.
1796          * The latter is needed for VGA hotplug / manual detection.
1797          */
1798         val = DPLL_VGA_MODE_DIS;
1799         if (pipe == PIPE_B)
1800                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1801         I915_WRITE(DPLL(pipe), val);
1802         POSTING_READ(DPLL(pipe));
1803
1804 }
1805
1806 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1807 {
1808         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1809         u32 val;
1810
1811         /* Make sure the pipe isn't still relying on us */
1812         assert_pipe_disabled(dev_priv, pipe);
1813
1814         /* Set PLL en = 0 */
1815         val = DPLL_SSC_REF_CLK_CHV |
1816                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1817         if (pipe != PIPE_A)
1818                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1819         I915_WRITE(DPLL(pipe), val);
1820         POSTING_READ(DPLL(pipe));
1821
1822         mutex_lock(&dev_priv->sb_lock);
1823
1824         /* Disable 10bit clock to display controller */
1825         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1826         val &= ~DPIO_DCLKP_EN;
1827         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1828
1829         mutex_unlock(&dev_priv->sb_lock);
1830 }
1831
1832 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1833                          struct intel_digital_port *dport,
1834                          unsigned int expected_mask)
1835 {
1836         u32 port_mask;
1837         i915_reg_t dpll_reg;
1838
1839         switch (dport->port) {
1840         case PORT_B:
1841                 port_mask = DPLL_PORTB_READY_MASK;
1842                 dpll_reg = DPLL(0);
1843                 break;
1844         case PORT_C:
1845                 port_mask = DPLL_PORTC_READY_MASK;
1846                 dpll_reg = DPLL(0);
1847                 expected_mask <<= 4;
1848                 break;
1849         case PORT_D:
1850                 port_mask = DPLL_PORTD_READY_MASK;
1851                 dpll_reg = DPIO_PHY_STATUS;
1852                 break;
1853         default:
1854                 BUG();
1855         }
1856
1857         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1858                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1859                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1860 }
1861
1862 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1863 {
1864         struct drm_device *dev = crtc->base.dev;
1865         struct drm_i915_private *dev_priv = dev->dev_private;
1866         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1867
1868         if (WARN_ON(pll == NULL))
1869                 return;
1870
1871         WARN_ON(!pll->config.crtc_mask);
1872         if (pll->active == 0) {
1873                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1874                 WARN_ON(pll->on);
1875                 assert_shared_dpll_disabled(dev_priv, pll);
1876
1877                 pll->mode_set(dev_priv, pll);
1878         }
1879 }
1880
1881 /**
1882  * intel_enable_shared_dpll - enable PCH PLL
1883  * @dev_priv: i915 private structure
1884  * @pipe: pipe PLL to enable
1885  *
1886  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1887  * drives the transcoder clock.
1888  */
1889 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1890 {
1891         struct drm_device *dev = crtc->base.dev;
1892         struct drm_i915_private *dev_priv = dev->dev_private;
1893         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1894
1895         if (WARN_ON(pll == NULL))
1896                 return;
1897
1898         if (WARN_ON(pll->config.crtc_mask == 0))
1899                 return;
1900
1901         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1902                       pll->name, pll->active, pll->on,
1903                       crtc->base.base.id);
1904
1905         if (pll->active++) {
1906                 WARN_ON(!pll->on);
1907                 assert_shared_dpll_enabled(dev_priv, pll);
1908                 return;
1909         }
1910         WARN_ON(pll->on);
1911
1912         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1913
1914         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1915         pll->enable(dev_priv, pll);
1916         pll->on = true;
1917 }
1918
1919 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1920 {
1921         struct drm_device *dev = crtc->base.dev;
1922         struct drm_i915_private *dev_priv = dev->dev_private;
1923         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1924
1925         /* PCH only available on ILK+ */
1926         if (INTEL_INFO(dev)->gen < 5)
1927                 return;
1928
1929         if (pll == NULL)
1930                 return;
1931
1932         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1933                 return;
1934
1935         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1936                       pll->name, pll->active, pll->on,
1937                       crtc->base.base.id);
1938
1939         if (WARN_ON(pll->active == 0)) {
1940                 assert_shared_dpll_disabled(dev_priv, pll);
1941                 return;
1942         }
1943
1944         assert_shared_dpll_enabled(dev_priv, pll);
1945         WARN_ON(!pll->on);
1946         if (--pll->active)
1947                 return;
1948
1949         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1950         pll->disable(dev_priv, pll);
1951         pll->on = false;
1952
1953         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1954 }
1955
1956 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1957                                            enum pipe pipe)
1958 {
1959         struct drm_device *dev = dev_priv->dev;
1960         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1962         i915_reg_t reg;
1963         uint32_t val, pipeconf_val;
1964
1965         /* PCH only available on ILK+ */
1966         BUG_ON(!HAS_PCH_SPLIT(dev));
1967
1968         /* Make sure PCH DPLL is enabled */
1969         assert_shared_dpll_enabled(dev_priv,
1970                                    intel_crtc_to_shared_dpll(intel_crtc));
1971
1972         /* FDI must be feeding us bits for PCH ports */
1973         assert_fdi_tx_enabled(dev_priv, pipe);
1974         assert_fdi_rx_enabled(dev_priv, pipe);
1975
1976         if (HAS_PCH_CPT(dev)) {
1977                 /* Workaround: Set the timing override bit before enabling the
1978                  * pch transcoder. */
1979                 reg = TRANS_CHICKEN2(pipe);
1980                 val = I915_READ(reg);
1981                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1982                 I915_WRITE(reg, val);
1983         }
1984
1985         reg = PCH_TRANSCONF(pipe);
1986         val = I915_READ(reg);
1987         pipeconf_val = I915_READ(PIPECONF(pipe));
1988
1989         if (HAS_PCH_IBX(dev_priv->dev)) {
1990                 /*
1991                  * Make the BPC in transcoder be consistent with
1992                  * that in pipeconf reg. For HDMI we must use 8bpc
1993                  * here for both 8bpc and 12bpc.
1994                  */
1995                 val &= ~PIPECONF_BPC_MASK;
1996                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1997                         val |= PIPECONF_8BPC;
1998                 else
1999                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2000         }
2001
2002         val &= ~TRANS_INTERLACE_MASK;
2003         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2004                 if (HAS_PCH_IBX(dev_priv->dev) &&
2005                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2006                         val |= TRANS_LEGACY_INTERLACED_ILK;
2007                 else
2008                         val |= TRANS_INTERLACED;
2009         else
2010                 val |= TRANS_PROGRESSIVE;
2011
2012         I915_WRITE(reg, val | TRANS_ENABLE);
2013         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2014                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2015 }
2016
2017 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2018                                       enum transcoder cpu_transcoder)
2019 {
2020         u32 val, pipeconf_val;
2021
2022         /* PCH only available on ILK+ */
2023         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2024
2025         /* FDI must be feeding us bits for PCH ports */
2026         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2027         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2028
2029         /* Workaround: set timing override bit. */
2030         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2031         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2032         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2033
2034         val = TRANS_ENABLE;
2035         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2036
2037         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2038             PIPECONF_INTERLACED_ILK)
2039                 val |= TRANS_INTERLACED;
2040         else
2041                 val |= TRANS_PROGRESSIVE;
2042
2043         I915_WRITE(LPT_TRANSCONF, val);
2044         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2045                 DRM_ERROR("Failed to enable PCH transcoder\n");
2046 }
2047
2048 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2049                                             enum pipe pipe)
2050 {
2051         struct drm_device *dev = dev_priv->dev;
2052         i915_reg_t reg;
2053         uint32_t val;
2054
2055         /* FDI relies on the transcoder */
2056         assert_fdi_tx_disabled(dev_priv, pipe);
2057         assert_fdi_rx_disabled(dev_priv, pipe);
2058
2059         /* Ports must be off as well */
2060         assert_pch_ports_disabled(dev_priv, pipe);
2061
2062         reg = PCH_TRANSCONF(pipe);
2063         val = I915_READ(reg);
2064         val &= ~TRANS_ENABLE;
2065         I915_WRITE(reg, val);
2066         /* wait for PCH transcoder off, transcoder state */
2067         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2068                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2069
2070         if (HAS_PCH_CPT(dev)) {
2071                 /* Workaround: Clear the timing override chicken bit again. */
2072                 reg = TRANS_CHICKEN2(pipe);
2073                 val = I915_READ(reg);
2074                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2075                 I915_WRITE(reg, val);
2076         }
2077 }
2078
2079 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2080 {
2081         u32 val;
2082
2083         val = I915_READ(LPT_TRANSCONF);
2084         val &= ~TRANS_ENABLE;
2085         I915_WRITE(LPT_TRANSCONF, val);
2086         /* wait for PCH transcoder off, transcoder state */
2087         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2088                 DRM_ERROR("Failed to disable PCH transcoder\n");
2089
2090         /* Workaround: clear timing override bit. */
2091         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2092         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2093         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2094 }
2095
2096 /**
2097  * intel_enable_pipe - enable a pipe, asserting requirements
2098  * @crtc: crtc responsible for the pipe
2099  *
2100  * Enable @crtc's pipe, making sure that various hardware specific requirements
2101  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2102  */
2103 static void intel_enable_pipe(struct intel_crtc *crtc)
2104 {
2105         struct drm_device *dev = crtc->base.dev;
2106         struct drm_i915_private *dev_priv = dev->dev_private;
2107         enum pipe pipe = crtc->pipe;
2108         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2109         enum pipe pch_transcoder;
2110         i915_reg_t reg;
2111         u32 val;
2112
2113         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2114
2115         assert_planes_disabled(dev_priv, pipe);
2116         assert_cursor_disabled(dev_priv, pipe);
2117         assert_sprites_disabled(dev_priv, pipe);
2118
2119         if (HAS_PCH_LPT(dev_priv->dev))
2120                 pch_transcoder = TRANSCODER_A;
2121         else
2122                 pch_transcoder = pipe;
2123
2124         /*
2125          * A pipe without a PLL won't actually be able to drive bits from
2126          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2127          * need the check.
2128          */
2129         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2130                 if (crtc->config->has_dsi_encoder)
2131                         assert_dsi_pll_enabled(dev_priv);
2132                 else
2133                         assert_pll_enabled(dev_priv, pipe);
2134         else {
2135                 if (crtc->config->has_pch_encoder) {
2136                         /* if driving the PCH, we need FDI enabled */
2137                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2138                         assert_fdi_tx_pll_enabled(dev_priv,
2139                                                   (enum pipe) cpu_transcoder);
2140                 }
2141                 /* FIXME: assert CPU port conditions for SNB+ */
2142         }
2143
2144         reg = PIPECONF(cpu_transcoder);
2145         val = I915_READ(reg);
2146         if (val & PIPECONF_ENABLE) {
2147                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2148                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2149                 return;
2150         }
2151
2152         I915_WRITE(reg, val | PIPECONF_ENABLE);
2153         POSTING_READ(reg);
2154 }
2155
2156 /**
2157  * intel_disable_pipe - disable a pipe, asserting requirements
2158  * @crtc: crtc whose pipes is to be disabled
2159  *
2160  * Disable the pipe of @crtc, making sure that various hardware
2161  * specific requirements are met, if applicable, e.g. plane
2162  * disabled, panel fitter off, etc.
2163  *
2164  * Will wait until the pipe has shut down before returning.
2165  */
2166 static void intel_disable_pipe(struct intel_crtc *crtc)
2167 {
2168         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2169         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2170         enum pipe pipe = crtc->pipe;
2171         i915_reg_t reg;
2172         u32 val;
2173
2174         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2175
2176         /*
2177          * Make sure planes won't keep trying to pump pixels to us,
2178          * or we might hang the display.
2179          */
2180         assert_planes_disabled(dev_priv, pipe);
2181         assert_cursor_disabled(dev_priv, pipe);
2182         assert_sprites_disabled(dev_priv, pipe);
2183
2184         reg = PIPECONF(cpu_transcoder);
2185         val = I915_READ(reg);
2186         if ((val & PIPECONF_ENABLE) == 0)
2187                 return;
2188
2189         /*
2190          * Double wide has implications for planes
2191          * so best keep it disabled when not needed.
2192          */
2193         if (crtc->config->double_wide)
2194                 val &= ~PIPECONF_DOUBLE_WIDE;
2195
2196         /* Don't disable pipe or pipe PLLs if needed */
2197         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2198             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2199                 val &= ~PIPECONF_ENABLE;
2200
2201         I915_WRITE(reg, val);
2202         if ((val & PIPECONF_ENABLE) == 0)
2203                 intel_wait_for_pipe_off(crtc);
2204 }
2205
2206 static bool need_vtd_wa(struct drm_device *dev)
2207 {
2208 #ifdef CONFIG_INTEL_IOMMU
2209         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2210                 return true;
2211 #endif
2212         return false;
2213 }
2214
2215 unsigned int
2216 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2217                   uint64_t fb_format_modifier, unsigned int plane)
2218 {
2219         unsigned int tile_height;
2220         uint32_t pixel_bytes;
2221
2222         switch (fb_format_modifier) {
2223         case DRM_FORMAT_MOD_NONE:
2224                 tile_height = 1;
2225                 break;
2226         case I915_FORMAT_MOD_X_TILED:
2227                 tile_height = IS_GEN2(dev) ? 16 : 8;
2228                 break;
2229         case I915_FORMAT_MOD_Y_TILED:
2230                 tile_height = 32;
2231                 break;
2232         case I915_FORMAT_MOD_Yf_TILED:
2233                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2234                 switch (pixel_bytes) {
2235                 default:
2236                 case 1:
2237                         tile_height = 64;
2238                         break;
2239                 case 2:
2240                 case 4:
2241                         tile_height = 32;
2242                         break;
2243                 case 8:
2244                         tile_height = 16;
2245                         break;
2246                 case 16:
2247                         WARN_ONCE(1,
2248                                   "128-bit pixels are not supported for display!");
2249                         tile_height = 16;
2250                         break;
2251                 }
2252                 break;
2253         default:
2254                 MISSING_CASE(fb_format_modifier);
2255                 tile_height = 1;
2256                 break;
2257         }
2258
2259         return tile_height;
2260 }
2261
2262 unsigned int
2263 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2264                       uint32_t pixel_format, uint64_t fb_format_modifier)
2265 {
2266         return ALIGN(height, intel_tile_height(dev, pixel_format,
2267                                                fb_format_modifier, 0));
2268 }
2269
2270 static void
2271 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2272                         const struct drm_plane_state *plane_state)
2273 {
2274         struct intel_rotation_info *info = &view->params.rotation_info;
2275         unsigned int tile_height, tile_pitch;
2276
2277         *view = i915_ggtt_view_normal;
2278
2279         if (!plane_state)
2280                 return;
2281
2282         if (!intel_rotation_90_or_270(plane_state->rotation))
2283                 return;
2284
2285         *view = i915_ggtt_view_rotated;
2286
2287         info->height = fb->height;
2288         info->pixel_format = fb->pixel_format;
2289         info->pitch = fb->pitches[0];
2290         info->uv_offset = fb->offsets[1];
2291         info->fb_modifier = fb->modifier[0];
2292
2293         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2294                                         fb->modifier[0], 0);
2295         tile_pitch = PAGE_SIZE / tile_height;
2296         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2297         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2298         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2299
2300         if (info->pixel_format == DRM_FORMAT_NV12) {
2301                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2302                                                 fb->modifier[0], 1);
2303                 tile_pitch = PAGE_SIZE / tile_height;
2304                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2305                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2306                                                      tile_height);
2307                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2308                                 PAGE_SIZE;
2309         }
2310 }
2311
2312 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2313 {
2314         if (INTEL_INFO(dev_priv)->gen >= 9)
2315                 return 256 * 1024;
2316         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2317                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2318                 return 128 * 1024;
2319         else if (INTEL_INFO(dev_priv)->gen >= 4)
2320                 return 4 * 1024;
2321         else
2322                 return 0;
2323 }
2324
2325 int
2326 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2327                            struct drm_framebuffer *fb,
2328                            const struct drm_plane_state *plane_state)
2329 {
2330         struct drm_device *dev = fb->dev;
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2333         struct i915_ggtt_view view;
2334         u32 alignment;
2335         int ret;
2336
2337         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2338
2339         switch (fb->modifier[0]) {
2340         case DRM_FORMAT_MOD_NONE:
2341                 alignment = intel_linear_alignment(dev_priv);
2342                 break;
2343         case I915_FORMAT_MOD_X_TILED:
2344                 if (INTEL_INFO(dev)->gen >= 9)
2345                         alignment = 256 * 1024;
2346                 else {
2347                         /* pin() will align the object as required by fence */
2348                         alignment = 0;
2349                 }
2350                 break;
2351         case I915_FORMAT_MOD_Y_TILED:
2352         case I915_FORMAT_MOD_Yf_TILED:
2353                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2354                           "Y tiling bo slipped through, driver bug!\n"))
2355                         return -EINVAL;
2356                 alignment = 1 * 1024 * 1024;
2357                 break;
2358         default:
2359                 MISSING_CASE(fb->modifier[0]);
2360                 return -EINVAL;
2361         }
2362
2363         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2364
2365         /* Note that the w/a also requires 64 PTE of padding following the
2366          * bo. We currently fill all unused PTE with the shadow page and so
2367          * we should always have valid PTE following the scanout preventing
2368          * the VT-d warning.
2369          */
2370         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2371                 alignment = 256 * 1024;
2372
2373         /*
2374          * Global gtt pte registers are special registers which actually forward
2375          * writes to a chunk of system memory. Which means that there is no risk
2376          * that the register values disappear as soon as we call
2377          * intel_runtime_pm_put(), so it is correct to wrap only the
2378          * pin/unpin/fence and not more.
2379          */
2380         intel_runtime_pm_get(dev_priv);
2381
2382         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2383                                                    &view);
2384         if (ret)
2385                 goto err_pm;
2386
2387         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2388          * fence, whereas 965+ only requires a fence if using
2389          * framebuffer compression.  For simplicity, we always install
2390          * a fence as the cost is not that onerous.
2391          */
2392         if (view.type == I915_GGTT_VIEW_NORMAL) {
2393                 ret = i915_gem_object_get_fence(obj);
2394                 if (ret == -EDEADLK) {
2395                         /*
2396                          * -EDEADLK means there are no free fences
2397                          * no pending flips.
2398                          *
2399                          * This is propagated to atomic, but it uses
2400                          * -EDEADLK to force a locking recovery, so
2401                          * change the returned error to -EBUSY.
2402                          */
2403                         ret = -EBUSY;
2404                         goto err_unpin;
2405                 } else if (ret)
2406                         goto err_unpin;
2407
2408                 i915_gem_object_pin_fence(obj);
2409         }
2410
2411         intel_runtime_pm_put(dev_priv);
2412         return 0;
2413
2414 err_unpin:
2415         i915_gem_object_unpin_from_display_plane(obj, &view);
2416 err_pm:
2417         intel_runtime_pm_put(dev_priv);
2418         return ret;
2419 }
2420
2421 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422                                const struct drm_plane_state *plane_state)
2423 {
2424         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2425         struct i915_ggtt_view view;
2426
2427         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2428
2429         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2430
2431         if (view.type == I915_GGTT_VIEW_NORMAL)
2432                 i915_gem_object_unpin_fence(obj);
2433
2434         i915_gem_object_unpin_from_display_plane(obj, &view);
2435 }
2436
2437 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438  * is assumed to be a power-of-two. */
2439 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2440                                              int *x, int *y,
2441                                              unsigned int tiling_mode,
2442                                              unsigned int cpp,
2443                                              unsigned int pitch)
2444 {
2445         if (tiling_mode != I915_TILING_NONE) {
2446                 unsigned int tile_rows, tiles;
2447
2448                 tile_rows = *y / 8;
2449                 *y %= 8;
2450
2451                 tiles = *x / (512/cpp);
2452                 *x %= 512/cpp;
2453
2454                 return tile_rows * pitch * 8 + tiles * 4096;
2455         } else {
2456                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2457                 unsigned int offset;
2458
2459                 offset = *y * pitch + *x * cpp;
2460                 *y = (offset & alignment) / pitch;
2461                 *x = ((offset & alignment) - *y * pitch) / cpp;
2462                 return offset & ~alignment;
2463         }
2464 }
2465
2466 static int i9xx_format_to_fourcc(int format)
2467 {
2468         switch (format) {
2469         case DISPPLANE_8BPP:
2470                 return DRM_FORMAT_C8;
2471         case DISPPLANE_BGRX555:
2472                 return DRM_FORMAT_XRGB1555;
2473         case DISPPLANE_BGRX565:
2474                 return DRM_FORMAT_RGB565;
2475         default:
2476         case DISPPLANE_BGRX888:
2477                 return DRM_FORMAT_XRGB8888;
2478         case DISPPLANE_RGBX888:
2479                 return DRM_FORMAT_XBGR8888;
2480         case DISPPLANE_BGRX101010:
2481                 return DRM_FORMAT_XRGB2101010;
2482         case DISPPLANE_RGBX101010:
2483                 return DRM_FORMAT_XBGR2101010;
2484         }
2485 }
2486
2487 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2488 {
2489         switch (format) {
2490         case PLANE_CTL_FORMAT_RGB_565:
2491                 return DRM_FORMAT_RGB565;
2492         default:
2493         case PLANE_CTL_FORMAT_XRGB_8888:
2494                 if (rgb_order) {
2495                         if (alpha)
2496                                 return DRM_FORMAT_ABGR8888;
2497                         else
2498                                 return DRM_FORMAT_XBGR8888;
2499                 } else {
2500                         if (alpha)
2501                                 return DRM_FORMAT_ARGB8888;
2502                         else
2503                                 return DRM_FORMAT_XRGB8888;
2504                 }
2505         case PLANE_CTL_FORMAT_XRGB_2101010:
2506                 if (rgb_order)
2507                         return DRM_FORMAT_XBGR2101010;
2508                 else
2509                         return DRM_FORMAT_XRGB2101010;
2510         }
2511 }
2512
2513 static bool
2514 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2515                               struct intel_initial_plane_config *plane_config)
2516 {
2517         struct drm_device *dev = crtc->base.dev;
2518         struct drm_i915_private *dev_priv = to_i915(dev);
2519         struct drm_i915_gem_object *obj = NULL;
2520         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2521         struct drm_framebuffer *fb = &plane_config->fb->base;
2522         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2523         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2524                                     PAGE_SIZE);
2525
2526         size_aligned -= base_aligned;
2527
2528         if (plane_config->size == 0)
2529                 return false;
2530
2531         /* If the FB is too big, just don't use it since fbdev is not very
2532          * important and we should probably use that space with FBC or other
2533          * features. */
2534         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2535                 return false;
2536
2537         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2538                                                              base_aligned,
2539                                                              base_aligned,
2540                                                              size_aligned);
2541         if (!obj)
2542                 return false;
2543
2544         obj->tiling_mode = plane_config->tiling;
2545         if (obj->tiling_mode == I915_TILING_X)
2546                 obj->stride = fb->pitches[0];
2547
2548         mode_cmd.pixel_format = fb->pixel_format;
2549         mode_cmd.width = fb->width;
2550         mode_cmd.height = fb->height;
2551         mode_cmd.pitches[0] = fb->pitches[0];
2552         mode_cmd.modifier[0] = fb->modifier[0];
2553         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2554
2555         mutex_lock(&dev->struct_mutex);
2556         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2557                                    &mode_cmd, obj)) {
2558                 DRM_DEBUG_KMS("intel fb init failed\n");
2559                 goto out_unref_obj;
2560         }
2561         mutex_unlock(&dev->struct_mutex);
2562
2563         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2564         return true;
2565
2566 out_unref_obj:
2567         drm_gem_object_unreference(&obj->base);
2568         mutex_unlock(&dev->struct_mutex);
2569         return false;
2570 }
2571
2572 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2573 static void
2574 update_state_fb(struct drm_plane *plane)
2575 {
2576         if (plane->fb == plane->state->fb)
2577                 return;
2578
2579         if (plane->state->fb)
2580                 drm_framebuffer_unreference(plane->state->fb);
2581         plane->state->fb = plane->fb;
2582         if (plane->state->fb)
2583                 drm_framebuffer_reference(plane->state->fb);
2584 }
2585
2586 static void
2587 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2588                              struct intel_initial_plane_config *plane_config)
2589 {
2590         struct drm_device *dev = intel_crtc->base.dev;
2591         struct drm_i915_private *dev_priv = dev->dev_private;
2592         struct drm_crtc *c;
2593         struct intel_crtc *i;
2594         struct drm_i915_gem_object *obj;
2595         struct drm_plane *primary = intel_crtc->base.primary;
2596         struct drm_plane_state *plane_state = primary->state;
2597         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2598         struct intel_plane *intel_plane = to_intel_plane(primary);
2599         struct intel_plane_state *intel_state =
2600                 to_intel_plane_state(plane_state);
2601         struct drm_framebuffer *fb;
2602
2603         if (!plane_config->fb)
2604                 return;
2605
2606         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2607                 fb = &plane_config->fb->base;
2608                 goto valid_fb;
2609         }
2610
2611         kfree(plane_config->fb);
2612
2613         /*
2614          * Failed to alloc the obj, check to see if we should share
2615          * an fb with another CRTC instead
2616          */
2617         for_each_crtc(dev, c) {
2618                 i = to_intel_crtc(c);
2619
2620                 if (c == &intel_crtc->base)
2621                         continue;
2622
2623                 if (!i->active)
2624                         continue;
2625
2626                 fb = c->primary->fb;
2627                 if (!fb)
2628                         continue;
2629
2630                 obj = intel_fb_obj(fb);
2631                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2632                         drm_framebuffer_reference(fb);
2633                         goto valid_fb;
2634                 }
2635         }
2636
2637         /*
2638          * We've failed to reconstruct the BIOS FB.  Current display state
2639          * indicates that the primary plane is visible, but has a NULL FB,
2640          * which will lead to problems later if we don't fix it up.  The
2641          * simplest solution is to just disable the primary plane now and
2642          * pretend the BIOS never had it enabled.
2643          */
2644         to_intel_plane_state(plane_state)->visible = false;
2645         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2646         intel_pre_disable_primary(&intel_crtc->base);
2647         intel_plane->disable_plane(primary, &intel_crtc->base);
2648
2649         return;
2650
2651 valid_fb:
2652         plane_state->src_x = 0;
2653         plane_state->src_y = 0;
2654         plane_state->src_w = fb->width << 16;
2655         plane_state->src_h = fb->height << 16;
2656
2657         plane_state->crtc_x = 0;
2658         plane_state->crtc_y = 0;
2659         plane_state->crtc_w = fb->width;
2660         plane_state->crtc_h = fb->height;
2661
2662         intel_state->src.x1 = plane_state->src_x;
2663         intel_state->src.y1 = plane_state->src_y;
2664         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2665         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2666         intel_state->dst.x1 = plane_state->crtc_x;
2667         intel_state->dst.y1 = plane_state->crtc_y;
2668         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2669         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2670
2671         obj = intel_fb_obj(fb);
2672         if (obj->tiling_mode != I915_TILING_NONE)
2673                 dev_priv->preserve_bios_swizzle = true;
2674
2675         drm_framebuffer_reference(fb);
2676         primary->fb = primary->state->fb = fb;
2677         primary->crtc = primary->state->crtc = &intel_crtc->base;
2678         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2679         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2680 }
2681
2682 static void i9xx_update_primary_plane(struct drm_plane *primary,
2683                                       const struct intel_crtc_state *crtc_state,
2684                                       const struct intel_plane_state *plane_state)
2685 {
2686         struct drm_device *dev = primary->dev;
2687         struct drm_i915_private *dev_priv = dev->dev_private;
2688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2689         struct drm_framebuffer *fb = plane_state->base.fb;
2690         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2691         int plane = intel_crtc->plane;
2692         unsigned long linear_offset;
2693         int x = plane_state->src.x1 >> 16;
2694         int y = plane_state->src.y1 >> 16;
2695         u32 dspcntr;
2696         i915_reg_t reg = DSPCNTR(plane);
2697         int pixel_size;
2698
2699         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2700
2701         dspcntr = DISPPLANE_GAMMA_ENABLE;
2702
2703         dspcntr |= DISPLAY_PLANE_ENABLE;
2704
2705         if (INTEL_INFO(dev)->gen < 4) {
2706                 if (intel_crtc->pipe == PIPE_B)
2707                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2708
2709                 /* pipesrc and dspsize control the size that is scaled from,
2710                  * which should always be the user's requested size.
2711                  */
2712                 I915_WRITE(DSPSIZE(plane),
2713                            ((crtc_state->pipe_src_h - 1) << 16) |
2714                            (crtc_state->pipe_src_w - 1));
2715                 I915_WRITE(DSPPOS(plane), 0);
2716         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2717                 I915_WRITE(PRIMSIZE(plane),
2718                            ((crtc_state->pipe_src_h - 1) << 16) |
2719                            (crtc_state->pipe_src_w - 1));
2720                 I915_WRITE(PRIMPOS(plane), 0);
2721                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2722         }
2723
2724         switch (fb->pixel_format) {
2725         case DRM_FORMAT_C8:
2726                 dspcntr |= DISPPLANE_8BPP;
2727                 break;
2728         case DRM_FORMAT_XRGB1555:
2729                 dspcntr |= DISPPLANE_BGRX555;
2730                 break;
2731         case DRM_FORMAT_RGB565:
2732                 dspcntr |= DISPPLANE_BGRX565;
2733                 break;
2734         case DRM_FORMAT_XRGB8888:
2735                 dspcntr |= DISPPLANE_BGRX888;
2736                 break;
2737         case DRM_FORMAT_XBGR8888:
2738                 dspcntr |= DISPPLANE_RGBX888;
2739                 break;
2740         case DRM_FORMAT_XRGB2101010:
2741                 dspcntr |= DISPPLANE_BGRX101010;
2742                 break;
2743         case DRM_FORMAT_XBGR2101010:
2744                 dspcntr |= DISPPLANE_RGBX101010;
2745                 break;
2746         default:
2747                 BUG();
2748         }
2749
2750         if (INTEL_INFO(dev)->gen >= 4 &&
2751             obj->tiling_mode != I915_TILING_NONE)
2752                 dspcntr |= DISPPLANE_TILED;
2753
2754         if (IS_G4X(dev))
2755                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2756
2757         linear_offset = y * fb->pitches[0] + x * pixel_size;
2758
2759         if (INTEL_INFO(dev)->gen >= 4) {
2760                 intel_crtc->dspaddr_offset =
2761                         intel_gen4_compute_page_offset(dev_priv,
2762                                                        &x, &y, obj->tiling_mode,
2763                                                        pixel_size,
2764                                                        fb->pitches[0]);
2765                 linear_offset -= intel_crtc->dspaddr_offset;
2766         } else {
2767                 intel_crtc->dspaddr_offset = linear_offset;
2768         }
2769
2770         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2771                 dspcntr |= DISPPLANE_ROTATE_180;
2772
2773                 x += (crtc_state->pipe_src_w - 1);
2774                 y += (crtc_state->pipe_src_h - 1);
2775
2776                 /* Finding the last pixel of the last line of the display
2777                 data and adding to linear_offset*/
2778                 linear_offset +=
2779                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2780                         (crtc_state->pipe_src_w - 1) * pixel_size;
2781         }
2782
2783         intel_crtc->adjusted_x = x;
2784         intel_crtc->adjusted_y = y;
2785
2786         I915_WRITE(reg, dspcntr);
2787
2788         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2789         if (INTEL_INFO(dev)->gen >= 4) {
2790                 I915_WRITE(DSPSURF(plane),
2791                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2792                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2793                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2794         } else
2795                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2796         POSTING_READ(reg);
2797 }
2798
2799 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2800                                        struct drm_crtc *crtc)
2801 {
2802         struct drm_device *dev = crtc->dev;
2803         struct drm_i915_private *dev_priv = dev->dev_private;
2804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805         int plane = intel_crtc->plane;
2806
2807         I915_WRITE(DSPCNTR(plane), 0);
2808         if (INTEL_INFO(dev_priv)->gen >= 4)
2809                 I915_WRITE(DSPSURF(plane), 0);
2810         else
2811                 I915_WRITE(DSPADDR(plane), 0);
2812         POSTING_READ(DSPCNTR(plane));
2813 }
2814
2815 static void ironlake_update_primary_plane(struct drm_plane *primary,
2816                                           const struct intel_crtc_state *crtc_state,
2817                                           const struct intel_plane_state *plane_state)
2818 {
2819         struct drm_device *dev = primary->dev;
2820         struct drm_i915_private *dev_priv = dev->dev_private;
2821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2822         struct drm_framebuffer *fb = plane_state->base.fb;
2823         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2824         int plane = intel_crtc->plane;
2825         unsigned long linear_offset;
2826         u32 dspcntr;
2827         i915_reg_t reg = DSPCNTR(plane);
2828         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2829         int x = plane_state->src.x1 >> 16;
2830         int y = plane_state->src.y1 >> 16;
2831
2832         dspcntr = DISPPLANE_GAMMA_ENABLE;
2833         dspcntr |= DISPLAY_PLANE_ENABLE;
2834
2835         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2836                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2837
2838         switch (fb->pixel_format) {
2839         case DRM_FORMAT_C8:
2840                 dspcntr |= DISPPLANE_8BPP;
2841                 break;
2842         case DRM_FORMAT_RGB565:
2843                 dspcntr |= DISPPLANE_BGRX565;
2844                 break;
2845         case DRM_FORMAT_XRGB8888:
2846                 dspcntr |= DISPPLANE_BGRX888;
2847                 break;
2848         case DRM_FORMAT_XBGR8888:
2849                 dspcntr |= DISPPLANE_RGBX888;
2850                 break;
2851         case DRM_FORMAT_XRGB2101010:
2852                 dspcntr |= DISPPLANE_BGRX101010;
2853                 break;
2854         case DRM_FORMAT_XBGR2101010:
2855                 dspcntr |= DISPPLANE_RGBX101010;
2856                 break;
2857         default:
2858                 BUG();
2859         }
2860
2861         if (obj->tiling_mode != I915_TILING_NONE)
2862                 dspcntr |= DISPPLANE_TILED;
2863
2864         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2865                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2866
2867         linear_offset = y * fb->pitches[0] + x * pixel_size;
2868         intel_crtc->dspaddr_offset =
2869                 intel_gen4_compute_page_offset(dev_priv,
2870                                                &x, &y, obj->tiling_mode,
2871                                                pixel_size,
2872                                                fb->pitches[0]);
2873         linear_offset -= intel_crtc->dspaddr_offset;
2874         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2875                 dspcntr |= DISPPLANE_ROTATE_180;
2876
2877                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2878                         x += (crtc_state->pipe_src_w - 1);
2879                         y += (crtc_state->pipe_src_h - 1);
2880
2881                         /* Finding the last pixel of the last line of the display
2882                         data and adding to linear_offset*/
2883                         linear_offset +=
2884                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2885                                 (crtc_state->pipe_src_w - 1) * pixel_size;
2886                 }
2887         }
2888
2889         intel_crtc->adjusted_x = x;
2890         intel_crtc->adjusted_y = y;
2891
2892         I915_WRITE(reg, dspcntr);
2893
2894         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2895         I915_WRITE(DSPSURF(plane),
2896                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2897         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2898                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2899         } else {
2900                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2901                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2902         }
2903         POSTING_READ(reg);
2904 }
2905
2906 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2907                               uint32_t pixel_format)
2908 {
2909         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2910
2911         /*
2912          * The stride is either expressed as a multiple of 64 bytes
2913          * chunks for linear buffers or in number of tiles for tiled
2914          * buffers.
2915          */
2916         switch (fb_modifier) {
2917         case DRM_FORMAT_MOD_NONE:
2918                 return 64;
2919         case I915_FORMAT_MOD_X_TILED:
2920                 if (INTEL_INFO(dev)->gen == 2)
2921                         return 128;
2922                 return 512;
2923         case I915_FORMAT_MOD_Y_TILED:
2924                 /* No need to check for old gens and Y tiling since this is
2925                  * about the display engine and those will be blocked before
2926                  * we get here.
2927                  */
2928                 return 128;
2929         case I915_FORMAT_MOD_Yf_TILED:
2930                 if (bits_per_pixel == 8)
2931                         return 64;
2932                 else
2933                         return 128;
2934         default:
2935                 MISSING_CASE(fb_modifier);
2936                 return 64;
2937         }
2938 }
2939
2940 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2941                            struct drm_i915_gem_object *obj,
2942                            unsigned int plane)
2943 {
2944         struct i915_ggtt_view view;
2945         struct i915_vma *vma;
2946         u64 offset;
2947
2948         intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2949                                 intel_plane->base.state);
2950
2951         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2952         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2953                 view.type))
2954                 return -1;
2955
2956         offset = vma->node.start;
2957
2958         if (plane == 1) {
2959                 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2960                           PAGE_SIZE;
2961         }
2962
2963         WARN_ON(upper_32_bits(offset));
2964
2965         return lower_32_bits(offset);
2966 }
2967
2968 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2969 {
2970         struct drm_device *dev = intel_crtc->base.dev;
2971         struct drm_i915_private *dev_priv = dev->dev_private;
2972
2973         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2974         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2975         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2976 }
2977
2978 /*
2979  * This function detaches (aka. unbinds) unused scalers in hardware
2980  */
2981 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2982 {
2983         struct intel_crtc_scaler_state *scaler_state;
2984         int i;
2985
2986         scaler_state = &intel_crtc->config->scaler_state;
2987
2988         /* loop through and disable scalers that aren't in use */
2989         for (i = 0; i < intel_crtc->num_scalers; i++) {
2990                 if (!scaler_state->scalers[i].in_use)
2991                         skl_detach_scaler(intel_crtc, i);
2992         }
2993 }
2994
2995 u32 skl_plane_ctl_format(uint32_t pixel_format)
2996 {
2997         switch (pixel_format) {
2998         case DRM_FORMAT_C8:
2999                 return PLANE_CTL_FORMAT_INDEXED;
3000         case DRM_FORMAT_RGB565:
3001                 return PLANE_CTL_FORMAT_RGB_565;
3002         case DRM_FORMAT_XBGR8888:
3003                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3004         case DRM_FORMAT_XRGB8888:
3005                 return PLANE_CTL_FORMAT_XRGB_8888;
3006         /*
3007          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3008          * to be already pre-multiplied. We need to add a knob (or a different
3009          * DRM_FORMAT) for user-space to configure that.
3010          */
3011         case DRM_FORMAT_ABGR8888:
3012                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3013                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3014         case DRM_FORMAT_ARGB8888:
3015                 return PLANE_CTL_FORMAT_XRGB_8888 |
3016                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3017         case DRM_FORMAT_XRGB2101010:
3018                 return PLANE_CTL_FORMAT_XRGB_2101010;
3019         case DRM_FORMAT_XBGR2101010:
3020                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3021         case DRM_FORMAT_YUYV:
3022                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3023         case DRM_FORMAT_YVYU:
3024                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3025         case DRM_FORMAT_UYVY:
3026                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3027         case DRM_FORMAT_VYUY:
3028                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3029         default:
3030                 MISSING_CASE(pixel_format);
3031         }
3032
3033         return 0;
3034 }
3035
3036 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3037 {
3038         switch (fb_modifier) {
3039         case DRM_FORMAT_MOD_NONE:
3040                 break;
3041         case I915_FORMAT_MOD_X_TILED:
3042                 return PLANE_CTL_TILED_X;
3043         case I915_FORMAT_MOD_Y_TILED:
3044                 return PLANE_CTL_TILED_Y;
3045         case I915_FORMAT_MOD_Yf_TILED:
3046                 return PLANE_CTL_TILED_YF;
3047         default:
3048                 MISSING_CASE(fb_modifier);
3049         }
3050
3051         return 0;
3052 }
3053
3054 u32 skl_plane_ctl_rotation(unsigned int rotation)
3055 {
3056         switch (rotation) {
3057         case BIT(DRM_ROTATE_0):
3058                 break;
3059         /*
3060          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3061          * while i915 HW rotation is clockwise, thats why this swapping.
3062          */
3063         case BIT(DRM_ROTATE_90):
3064                 return PLANE_CTL_ROTATE_270;
3065         case BIT(DRM_ROTATE_180):
3066                 return PLANE_CTL_ROTATE_180;
3067         case BIT(DRM_ROTATE_270):
3068                 return PLANE_CTL_ROTATE_90;
3069         default:
3070                 MISSING_CASE(rotation);
3071         }
3072
3073         return 0;
3074 }
3075
3076 static void skylake_update_primary_plane(struct drm_plane *plane,
3077                                          const struct intel_crtc_state *crtc_state,
3078                                          const struct intel_plane_state *plane_state)
3079 {
3080         struct drm_device *dev = plane->dev;
3081         struct drm_i915_private *dev_priv = dev->dev_private;
3082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3083         struct drm_framebuffer *fb = plane_state->base.fb;
3084         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3085         int pipe = intel_crtc->pipe;
3086         u32 plane_ctl, stride_div, stride;
3087         u32 tile_height, plane_offset, plane_size;
3088         unsigned int rotation = plane_state->base.rotation;
3089         int x_offset, y_offset;
3090         u32 surf_addr;
3091         int scaler_id = plane_state->scaler_id;
3092         int src_x = plane_state->src.x1 >> 16;
3093         int src_y = plane_state->src.y1 >> 16;
3094         int src_w = drm_rect_width(&plane_state->src) >> 16;
3095         int src_h = drm_rect_height(&plane_state->src) >> 16;
3096         int dst_x = plane_state->dst.x1;
3097         int dst_y = plane_state->dst.y1;
3098         int dst_w = drm_rect_width(&plane_state->dst);
3099         int dst_h = drm_rect_height(&plane_state->dst);
3100
3101         plane_ctl = PLANE_CTL_ENABLE |
3102                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3103                     PLANE_CTL_PIPE_CSC_ENABLE;
3104
3105         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3106         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3107         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3108         plane_ctl |= skl_plane_ctl_rotation(rotation);
3109
3110         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3111                                                fb->pixel_format);
3112         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3113
3114         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3115
3116         if (intel_rotation_90_or_270(rotation)) {
3117                 /* stride = Surface height in tiles */
3118                 tile_height = intel_tile_height(dev, fb->pixel_format,
3119                                                 fb->modifier[0], 0);
3120                 stride = DIV_ROUND_UP(fb->height, tile_height);
3121                 x_offset = stride * tile_height - src_y - src_h;
3122                 y_offset = src_x;
3123                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3124         } else {
3125                 stride = fb->pitches[0] / stride_div;
3126                 x_offset = src_x;
3127                 y_offset = src_y;
3128                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3129         }
3130         plane_offset = y_offset << 16 | x_offset;
3131
3132         intel_crtc->adjusted_x = x_offset;
3133         intel_crtc->adjusted_y = y_offset;
3134
3135         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3136         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3137         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3138         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3139
3140         if (scaler_id >= 0) {
3141                 uint32_t ps_ctrl = 0;
3142
3143                 WARN_ON(!dst_w || !dst_h);
3144                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3145                         crtc_state->scaler_state.scalers[scaler_id].mode;
3146                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3147                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3148                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3149                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3150                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3151         } else {
3152                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3153         }
3154
3155         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3156
3157         POSTING_READ(PLANE_SURF(pipe, 0));
3158 }
3159
3160 static void skylake_disable_primary_plane(struct drm_plane *primary,
3161                                           struct drm_crtc *crtc)
3162 {
3163         struct drm_device *dev = crtc->dev;
3164         struct drm_i915_private *dev_priv = dev->dev_private;
3165         int pipe = to_intel_crtc(crtc)->pipe;
3166
3167         if (dev_priv->fbc.deactivate)
3168                 dev_priv->fbc.deactivate(dev_priv);
3169
3170         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3171         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3172         POSTING_READ(PLANE_SURF(pipe, 0));
3173 }
3174
3175 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3176 static int
3177 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3178                            int x, int y, enum mode_set_atomic state)
3179 {
3180         /* Support for kgdboc is disabled, this needs a major rework. */
3181         DRM_ERROR("legacy panic handler not supported any more.\n");
3182
3183         return -ENODEV;
3184 }
3185
3186 static void intel_complete_page_flips(struct drm_device *dev)
3187 {
3188         struct drm_crtc *crtc;
3189
3190         for_each_crtc(dev, crtc) {
3191                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3192                 enum plane plane = intel_crtc->plane;
3193
3194                 intel_prepare_page_flip(dev, plane);
3195                 intel_finish_page_flip_plane(dev, plane);
3196         }
3197 }
3198
3199 static void intel_update_primary_planes(struct drm_device *dev)
3200 {
3201         struct drm_crtc *crtc;
3202
3203         for_each_crtc(dev, crtc) {
3204                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3205                 struct intel_plane_state *plane_state;
3206
3207                 drm_modeset_lock_crtc(crtc, &plane->base);
3208                 plane_state = to_intel_plane_state(plane->base.state);
3209
3210                 if (plane_state->visible)
3211                         plane->update_plane(&plane->base,
3212                                             to_intel_crtc_state(crtc->state),
3213                                             plane_state);
3214
3215                 drm_modeset_unlock_crtc(crtc);
3216         }
3217 }
3218
3219 void intel_prepare_reset(struct drm_device *dev)
3220 {
3221         /* no reset support for gen2 */
3222         if (IS_GEN2(dev))
3223                 return;
3224
3225         /* reset doesn't touch the display */
3226         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3227                 return;
3228
3229         drm_modeset_lock_all(dev);
3230         /*
3231          * Disabling the crtcs gracefully seems nicer. Also the
3232          * g33 docs say we should at least disable all the planes.
3233          */
3234         intel_display_suspend(dev);
3235 }
3236
3237 void intel_finish_reset(struct drm_device *dev)
3238 {
3239         struct drm_i915_private *dev_priv = to_i915(dev);
3240
3241         /*
3242          * Flips in the rings will be nuked by the reset,
3243          * so complete all pending flips so that user space
3244          * will get its events and not get stuck.
3245          */
3246         intel_complete_page_flips(dev);
3247
3248         /* no reset support for gen2 */
3249         if (IS_GEN2(dev))
3250                 return;
3251
3252         /* reset doesn't touch the display */
3253         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3254                 /*
3255                  * Flips in the rings have been nuked by the reset,
3256                  * so update the base address of all primary
3257                  * planes to the the last fb to make sure we're
3258                  * showing the correct fb after a reset.
3259                  *
3260                  * FIXME: Atomic will make this obsolete since we won't schedule
3261                  * CS-based flips (which might get lost in gpu resets) any more.
3262                  */
3263                 intel_update_primary_planes(dev);
3264                 return;
3265         }
3266
3267         /*
3268          * The display has been reset as well,
3269          * so need a full re-initialization.
3270          */
3271         intel_runtime_pm_disable_interrupts(dev_priv);
3272         intel_runtime_pm_enable_interrupts(dev_priv);
3273
3274         intel_modeset_init_hw(dev);
3275
3276         spin_lock_irq(&dev_priv->irq_lock);
3277         if (dev_priv->display.hpd_irq_setup)
3278                 dev_priv->display.hpd_irq_setup(dev);
3279         spin_unlock_irq(&dev_priv->irq_lock);
3280
3281         intel_display_resume(dev);
3282
3283         intel_hpd_init(dev_priv);
3284
3285         drm_modeset_unlock_all(dev);
3286 }
3287
3288 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3289 {
3290         struct drm_device *dev = crtc->dev;
3291         struct drm_i915_private *dev_priv = dev->dev_private;
3292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3293         bool pending;
3294
3295         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3296             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3297                 return false;
3298
3299         spin_lock_irq(&dev->event_lock);
3300         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3301         spin_unlock_irq(&dev->event_lock);
3302
3303         return pending;
3304 }
3305
3306 static void intel_update_pipe_config(struct intel_crtc *crtc,
3307                                      struct intel_crtc_state *old_crtc_state)
3308 {
3309         struct drm_device *dev = crtc->base.dev;
3310         struct drm_i915_private *dev_priv = dev->dev_private;
3311         struct intel_crtc_state *pipe_config =
3312                 to_intel_crtc_state(crtc->base.state);
3313
3314         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3315         crtc->base.mode = crtc->base.state->mode;
3316
3317         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3318                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3319                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3320
3321         if (HAS_DDI(dev))
3322                 intel_set_pipe_csc(&crtc->base);
3323
3324         /*
3325          * Update pipe size and adjust fitter if needed: the reason for this is
3326          * that in compute_mode_changes we check the native mode (not the pfit
3327          * mode) to see if we can flip rather than do a full mode set. In the
3328          * fastboot case, we'll flip, but if we don't update the pipesrc and
3329          * pfit state, we'll end up with a big fb scanned out into the wrong
3330          * sized surface.
3331          */
3332
3333         I915_WRITE(PIPESRC(crtc->pipe),
3334                    ((pipe_config->pipe_src_w - 1) << 16) |
3335                    (pipe_config->pipe_src_h - 1));
3336
3337         /* on skylake this is done by detaching scalers */
3338         if (INTEL_INFO(dev)->gen >= 9) {
3339                 skl_detach_scalers(crtc);
3340
3341                 if (pipe_config->pch_pfit.enabled)
3342                         skylake_pfit_enable(crtc);
3343         } else if (HAS_PCH_SPLIT(dev)) {
3344                 if (pipe_config->pch_pfit.enabled)
3345                         ironlake_pfit_enable(crtc);
3346                 else if (old_crtc_state->pch_pfit.enabled)
3347                         ironlake_pfit_disable(crtc, true);
3348         }
3349 }
3350
3351 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3352 {
3353         struct drm_device *dev = crtc->dev;
3354         struct drm_i915_private *dev_priv = dev->dev_private;
3355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356         int pipe = intel_crtc->pipe;
3357         i915_reg_t reg;
3358         u32 temp;
3359
3360         /* enable normal train */
3361         reg = FDI_TX_CTL(pipe);
3362         temp = I915_READ(reg);
3363         if (IS_IVYBRIDGE(dev)) {
3364                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3365                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3366         } else {
3367                 temp &= ~FDI_LINK_TRAIN_NONE;
3368                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3369         }
3370         I915_WRITE(reg, temp);
3371
3372         reg = FDI_RX_CTL(pipe);
3373         temp = I915_READ(reg);
3374         if (HAS_PCH_CPT(dev)) {
3375                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3376                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3377         } else {
3378                 temp &= ~FDI_LINK_TRAIN_NONE;
3379                 temp |= FDI_LINK_TRAIN_NONE;
3380         }
3381         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3382
3383         /* wait one idle pattern time */
3384         POSTING_READ(reg);
3385         udelay(1000);
3386
3387         /* IVB wants error correction enabled */
3388         if (IS_IVYBRIDGE(dev))
3389                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3390                            FDI_FE_ERRC_ENABLE);
3391 }
3392
3393 /* The FDI link training functions for ILK/Ibexpeak. */
3394 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3395 {
3396         struct drm_device *dev = crtc->dev;
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399         int pipe = intel_crtc->pipe;
3400         i915_reg_t reg;
3401         u32 temp, tries;
3402
3403         /* FDI needs bits from pipe first */
3404         assert_pipe_enabled(dev_priv, pipe);
3405
3406         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3407            for train result */
3408         reg = FDI_RX_IMR(pipe);
3409         temp = I915_READ(reg);
3410         temp &= ~FDI_RX_SYMBOL_LOCK;
3411         temp &= ~FDI_RX_BIT_LOCK;
3412         I915_WRITE(reg, temp);
3413         I915_READ(reg);
3414         udelay(150);
3415
3416         /* enable CPU FDI TX and PCH FDI RX */
3417         reg = FDI_TX_CTL(pipe);
3418         temp = I915_READ(reg);
3419         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3420         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3421         temp &= ~FDI_LINK_TRAIN_NONE;
3422         temp |= FDI_LINK_TRAIN_PATTERN_1;
3423         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3424
3425         reg = FDI_RX_CTL(pipe);
3426         temp = I915_READ(reg);
3427         temp &= ~FDI_LINK_TRAIN_NONE;
3428         temp |= FDI_LINK_TRAIN_PATTERN_1;
3429         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3430
3431         POSTING_READ(reg);
3432         udelay(150);
3433
3434         /* Ironlake workaround, enable clock pointer after FDI enable*/
3435         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3436         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3437                    FDI_RX_PHASE_SYNC_POINTER_EN);
3438
3439         reg = FDI_RX_IIR(pipe);
3440         for (tries = 0; tries < 5; tries++) {
3441                 temp = I915_READ(reg);
3442                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3443
3444                 if ((temp & FDI_RX_BIT_LOCK)) {
3445                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3446                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3447                         break;
3448                 }
3449         }
3450         if (tries == 5)
3451                 DRM_ERROR("FDI train 1 fail!\n");
3452
3453         /* Train 2 */
3454         reg = FDI_TX_CTL(pipe);
3455         temp = I915_READ(reg);
3456         temp &= ~FDI_LINK_TRAIN_NONE;
3457         temp |= FDI_LINK_TRAIN_PATTERN_2;
3458         I915_WRITE(reg, temp);
3459
3460         reg = FDI_RX_CTL(pipe);
3461         temp = I915_READ(reg);
3462         temp &= ~FDI_LINK_TRAIN_NONE;
3463         temp |= FDI_LINK_TRAIN_PATTERN_2;
3464         I915_WRITE(reg, temp);
3465
3466         POSTING_READ(reg);
3467         udelay(150);
3468
3469         reg = FDI_RX_IIR(pipe);
3470         for (tries = 0; tries < 5; tries++) {
3471                 temp = I915_READ(reg);
3472                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3473
3474                 if (temp & FDI_RX_SYMBOL_LOCK) {
3475                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3476                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3477                         break;
3478                 }
3479         }
3480         if (tries == 5)
3481                 DRM_ERROR("FDI train 2 fail!\n");
3482
3483         DRM_DEBUG_KMS("FDI train done\n");
3484
3485 }
3486
3487 static const int snb_b_fdi_train_param[] = {
3488         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3489         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3490         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3491         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3492 };
3493
3494 /* The FDI link training functions for SNB/Cougarpoint. */
3495 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3496 {
3497         struct drm_device *dev = crtc->dev;
3498         struct drm_i915_private *dev_priv = dev->dev_private;
3499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3500         int pipe = intel_crtc->pipe;
3501         i915_reg_t reg;
3502         u32 temp, i, retry;
3503
3504         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3505            for train result */
3506         reg = FDI_RX_IMR(pipe);
3507         temp = I915_READ(reg);
3508         temp &= ~FDI_RX_SYMBOL_LOCK;
3509         temp &= ~FDI_RX_BIT_LOCK;
3510         I915_WRITE(reg, temp);
3511
3512         POSTING_READ(reg);
3513         udelay(150);
3514
3515         /* enable CPU FDI TX and PCH FDI RX */
3516         reg = FDI_TX_CTL(pipe);
3517         temp = I915_READ(reg);
3518         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3519         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3520         temp &= ~FDI_LINK_TRAIN_NONE;
3521         temp |= FDI_LINK_TRAIN_PATTERN_1;
3522         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3523         /* SNB-B */
3524         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3525         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3526
3527         I915_WRITE(FDI_RX_MISC(pipe),
3528                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3529
3530         reg = FDI_RX_CTL(pipe);
3531         temp = I915_READ(reg);
3532         if (HAS_PCH_CPT(dev)) {
3533                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3534                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3535         } else {
3536                 temp &= ~FDI_LINK_TRAIN_NONE;
3537                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3538         }
3539         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3540
3541         POSTING_READ(reg);
3542         udelay(150);
3543
3544         for (i = 0; i < 4; i++) {
3545                 reg = FDI_TX_CTL(pipe);
3546                 temp = I915_READ(reg);
3547                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3548                 temp |= snb_b_fdi_train_param[i];
3549                 I915_WRITE(reg, temp);
3550
3551                 POSTING_READ(reg);
3552                 udelay(500);
3553
3554                 for (retry = 0; retry < 5; retry++) {
3555                         reg = FDI_RX_IIR(pipe);
3556                         temp = I915_READ(reg);
3557                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3558                         if (temp & FDI_RX_BIT_LOCK) {
3559                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3560                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3561                                 break;
3562                         }
3563                         udelay(50);
3564                 }
3565                 if (retry < 5)
3566                         break;
3567         }
3568         if (i == 4)
3569                 DRM_ERROR("FDI train 1 fail!\n");
3570
3571         /* Train 2 */
3572         reg = FDI_TX_CTL(pipe);
3573         temp = I915_READ(reg);
3574         temp &= ~FDI_LINK_TRAIN_NONE;
3575         temp |= FDI_LINK_TRAIN_PATTERN_2;
3576         if (IS_GEN6(dev)) {
3577                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3578                 /* SNB-B */
3579                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3580         }
3581         I915_WRITE(reg, temp);
3582
3583         reg = FDI_RX_CTL(pipe);
3584         temp = I915_READ(reg);
3585         if (HAS_PCH_CPT(dev)) {
3586                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3587                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3588         } else {
3589                 temp &= ~FDI_LINK_TRAIN_NONE;
3590                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3591         }
3592         I915_WRITE(reg, temp);
3593
3594         POSTING_READ(reg);
3595         udelay(150);
3596
3597         for (i = 0; i < 4; i++) {
3598                 reg = FDI_TX_CTL(pipe);
3599                 temp = I915_READ(reg);
3600                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3601                 temp |= snb_b_fdi_train_param[i];
3602                 I915_WRITE(reg, temp);
3603
3604                 POSTING_READ(reg);
3605                 udelay(500);
3606
3607                 for (retry = 0; retry < 5; retry++) {
3608                         reg = FDI_RX_IIR(pipe);
3609                         temp = I915_READ(reg);
3610                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3611                         if (temp & FDI_RX_SYMBOL_LOCK) {
3612                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3613                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3614                                 break;
3615                         }
3616                         udelay(50);
3617                 }
3618                 if (retry < 5)
3619                         break;
3620         }
3621         if (i == 4)
3622                 DRM_ERROR("FDI train 2 fail!\n");
3623
3624         DRM_DEBUG_KMS("FDI train done.\n");
3625 }
3626
3627 /* Manual link training for Ivy Bridge A0 parts */
3628 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3629 {
3630         struct drm_device *dev = crtc->dev;
3631         struct drm_i915_private *dev_priv = dev->dev_private;
3632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3633         int pipe = intel_crtc->pipe;
3634         i915_reg_t reg;
3635         u32 temp, i, j;
3636
3637         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3638            for train result */
3639         reg = FDI_RX_IMR(pipe);
3640         temp = I915_READ(reg);
3641         temp &= ~FDI_RX_SYMBOL_LOCK;
3642         temp &= ~FDI_RX_BIT_LOCK;
3643         I915_WRITE(reg, temp);
3644
3645         POSTING_READ(reg);
3646         udelay(150);
3647
3648         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3649                       I915_READ(FDI_RX_IIR(pipe)));
3650
3651         /* Try each vswing and preemphasis setting twice before moving on */
3652         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3653                 /* disable first in case we need to retry */
3654                 reg = FDI_TX_CTL(pipe);
3655                 temp = I915_READ(reg);
3656                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3657                 temp &= ~FDI_TX_ENABLE;
3658                 I915_WRITE(reg, temp);
3659
3660                 reg = FDI_RX_CTL(pipe);
3661                 temp = I915_READ(reg);
3662                 temp &= ~FDI_LINK_TRAIN_AUTO;
3663                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3664                 temp &= ~FDI_RX_ENABLE;
3665                 I915_WRITE(reg, temp);
3666
3667                 /* enable CPU FDI TX and PCH FDI RX */
3668                 reg = FDI_TX_CTL(pipe);
3669                 temp = I915_READ(reg);
3670                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3671                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3672                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3673                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3674                 temp |= snb_b_fdi_train_param[j/2];
3675                 temp |= FDI_COMPOSITE_SYNC;
3676                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3677
3678                 I915_WRITE(FDI_RX_MISC(pipe),
3679                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3680
3681                 reg = FDI_RX_CTL(pipe);
3682                 temp = I915_READ(reg);
3683                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3684                 temp |= FDI_COMPOSITE_SYNC;
3685                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3686
3687                 POSTING_READ(reg);
3688                 udelay(1); /* should be 0.5us */
3689
3690                 for (i = 0; i < 4; i++) {
3691                         reg = FDI_RX_IIR(pipe);
3692                         temp = I915_READ(reg);
3693                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3694
3695                         if (temp & FDI_RX_BIT_LOCK ||
3696                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3697                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3698                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3699                                               i);
3700                                 break;
3701                         }
3702                         udelay(1); /* should be 0.5us */
3703                 }
3704                 if (i == 4) {
3705                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3706                         continue;
3707                 }
3708
3709                 /* Train 2 */
3710                 reg = FDI_TX_CTL(pipe);
3711                 temp = I915_READ(reg);
3712                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3713                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3714                 I915_WRITE(reg, temp);
3715
3716                 reg = FDI_RX_CTL(pipe);
3717                 temp = I915_READ(reg);
3718                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3719                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3720                 I915_WRITE(reg, temp);
3721
3722                 POSTING_READ(reg);
3723                 udelay(2); /* should be 1.5us */
3724
3725                 for (i = 0; i < 4; i++) {
3726                         reg = FDI_RX_IIR(pipe);
3727                         temp = I915_READ(reg);
3728                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3729
3730                         if (temp & FDI_RX_SYMBOL_LOCK ||
3731                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3732                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3733                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3734                                               i);
3735                                 goto train_done;
3736                         }
3737                         udelay(2); /* should be 1.5us */
3738                 }
3739                 if (i == 4)
3740                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3741         }
3742
3743 train_done:
3744         DRM_DEBUG_KMS("FDI train done.\n");
3745 }
3746
3747 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3748 {
3749         struct drm_device *dev = intel_crtc->base.dev;
3750         struct drm_i915_private *dev_priv = dev->dev_private;
3751         int pipe = intel_crtc->pipe;
3752         i915_reg_t reg;
3753         u32 temp;
3754
3755         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3756         reg = FDI_RX_CTL(pipe);
3757         temp = I915_READ(reg);
3758         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3759         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3760         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3761         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3762
3763         POSTING_READ(reg);
3764         udelay(200);
3765
3766         /* Switch from Rawclk to PCDclk */
3767         temp = I915_READ(reg);
3768         I915_WRITE(reg, temp | FDI_PCDCLK);
3769
3770         POSTING_READ(reg);
3771         udelay(200);
3772
3773         /* Enable CPU FDI TX PLL, always on for Ironlake */
3774         reg = FDI_TX_CTL(pipe);
3775         temp = I915_READ(reg);
3776         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3777                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3778
3779                 POSTING_READ(reg);
3780                 udelay(100);
3781         }
3782 }
3783
3784 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3785 {
3786         struct drm_device *dev = intel_crtc->base.dev;
3787         struct drm_i915_private *dev_priv = dev->dev_private;
3788         int pipe = intel_crtc->pipe;
3789         i915_reg_t reg;
3790         u32 temp;
3791
3792         /* Switch from PCDclk to Rawclk */
3793         reg = FDI_RX_CTL(pipe);
3794         temp = I915_READ(reg);
3795         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3796
3797         /* Disable CPU FDI TX PLL */
3798         reg = FDI_TX_CTL(pipe);
3799         temp = I915_READ(reg);
3800         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3801
3802         POSTING_READ(reg);
3803         udelay(100);
3804
3805         reg = FDI_RX_CTL(pipe);
3806         temp = I915_READ(reg);
3807         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3808
3809         /* Wait for the clocks to turn off. */
3810         POSTING_READ(reg);
3811         udelay(100);
3812 }
3813
3814 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3815 {
3816         struct drm_device *dev = crtc->dev;
3817         struct drm_i915_private *dev_priv = dev->dev_private;
3818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3819         int pipe = intel_crtc->pipe;
3820         i915_reg_t reg;
3821         u32 temp;
3822
3823         /* disable CPU FDI tx and PCH FDI rx */
3824         reg = FDI_TX_CTL(pipe);
3825         temp = I915_READ(reg);
3826         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3827         POSTING_READ(reg);
3828
3829         reg = FDI_RX_CTL(pipe);
3830         temp = I915_READ(reg);
3831         temp &= ~(0x7 << 16);
3832         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3833         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3834
3835         POSTING_READ(reg);
3836         udelay(100);
3837
3838         /* Ironlake workaround, disable clock pointer after downing FDI */
3839         if (HAS_PCH_IBX(dev))
3840                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3841
3842         /* still set train pattern 1 */
3843         reg = FDI_TX_CTL(pipe);
3844         temp = I915_READ(reg);
3845         temp &= ~FDI_LINK_TRAIN_NONE;
3846         temp |= FDI_LINK_TRAIN_PATTERN_1;
3847         I915_WRITE(reg, temp);
3848
3849         reg = FDI_RX_CTL(pipe);
3850         temp = I915_READ(reg);
3851         if (HAS_PCH_CPT(dev)) {
3852                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3853                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3854         } else {
3855                 temp &= ~FDI_LINK_TRAIN_NONE;
3856                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3857         }
3858         /* BPC in FDI rx is consistent with that in PIPECONF */
3859         temp &= ~(0x07 << 16);
3860         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3861         I915_WRITE(reg, temp);
3862
3863         POSTING_READ(reg);
3864         udelay(100);
3865 }
3866
3867 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3868 {
3869         struct intel_crtc *crtc;
3870
3871         /* Note that we don't need to be called with mode_config.lock here
3872          * as our list of CRTC objects is static for the lifetime of the
3873          * device and so cannot disappear as we iterate. Similarly, we can
3874          * happily treat the predicates as racy, atomic checks as userspace
3875          * cannot claim and pin a new fb without at least acquring the
3876          * struct_mutex and so serialising with us.
3877          */
3878         for_each_intel_crtc(dev, crtc) {
3879                 if (atomic_read(&crtc->unpin_work_count) == 0)
3880                         continue;
3881
3882                 if (crtc->unpin_work)
3883                         intel_wait_for_vblank(dev, crtc->pipe);
3884
3885                 return true;
3886         }
3887
3888         return false;
3889 }
3890
3891 static void page_flip_completed(struct intel_crtc *intel_crtc)
3892 {
3893         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3894         struct intel_unpin_work *work = intel_crtc->unpin_work;
3895
3896         /* ensure that the unpin work is consistent wrt ->pending. */
3897         smp_rmb();
3898         intel_crtc->unpin_work = NULL;
3899
3900         if (work->event)
3901                 drm_send_vblank_event(intel_crtc->base.dev,
3902                                       intel_crtc->pipe,
3903                                       work->event);
3904
3905         drm_crtc_vblank_put(&intel_crtc->base);
3906
3907         wake_up_all(&dev_priv->pending_flip_queue);
3908         queue_work(dev_priv->wq, &work->work);
3909
3910         trace_i915_flip_complete(intel_crtc->plane,
3911                                  work->pending_flip_obj);
3912 }
3913
3914 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3915 {
3916         struct drm_device *dev = crtc->dev;
3917         struct drm_i915_private *dev_priv = dev->dev_private;
3918         long ret;
3919
3920         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3921
3922         ret = wait_event_interruptible_timeout(
3923                                         dev_priv->pending_flip_queue,
3924                                         !intel_crtc_has_pending_flip(crtc),
3925                                         60*HZ);
3926
3927         if (ret < 0)
3928                 return ret;
3929
3930         if (ret == 0) {
3931                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3932
3933                 spin_lock_irq(&dev->event_lock);
3934                 if (intel_crtc->unpin_work) {
3935                         WARN_ONCE(1, "Removing stuck page flip\n");
3936                         page_flip_completed(intel_crtc);
3937                 }
3938                 spin_unlock_irq(&dev->event_lock);
3939         }
3940
3941         return 0;
3942 }
3943
3944 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3945 {
3946         u32 temp;
3947
3948         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3949
3950         mutex_lock(&dev_priv->sb_lock);
3951
3952         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3953         temp |= SBI_SSCCTL_DISABLE;
3954         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3955
3956         mutex_unlock(&dev_priv->sb_lock);
3957 }
3958
3959 /* Program iCLKIP clock to the desired frequency */
3960 static void lpt_program_iclkip(struct drm_crtc *crtc)
3961 {
3962         struct drm_device *dev = crtc->dev;
3963         struct drm_i915_private *dev_priv = dev->dev_private;
3964         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3965         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3966         u32 temp;
3967
3968         lpt_disable_iclkip(dev_priv);
3969
3970         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3971         if (clock == 20000) {
3972                 auxdiv = 1;
3973                 divsel = 0x41;
3974                 phaseinc = 0x20;
3975         } else {
3976                 /* The iCLK virtual clock root frequency is in MHz,
3977                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3978                  * divisors, it is necessary to divide one by another, so we
3979                  * convert the virtual clock precision to KHz here for higher
3980                  * precision.
3981                  */
3982                 u32 iclk_virtual_root_freq = 172800 * 1000;
3983                 u32 iclk_pi_range = 64;
3984                 u32 desired_divisor, msb_divisor_value, pi_value;
3985
3986                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
3987                 msb_divisor_value = desired_divisor / iclk_pi_range;
3988                 pi_value = desired_divisor % iclk_pi_range;
3989
3990                 auxdiv = 0;
3991                 divsel = msb_divisor_value - 2;
3992                 phaseinc = pi_value;
3993         }
3994
3995         /* This should not happen with any sane values */
3996         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3997                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3998         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3999                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4000
4001         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4002                         clock,
4003                         auxdiv,
4004                         divsel,
4005                         phasedir,
4006                         phaseinc);
4007
4008         mutex_lock(&dev_priv->sb_lock);
4009
4010         /* Program SSCDIVINTPHASE6 */
4011         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4012         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4013         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4014         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4015         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4016         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4017         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4018         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4019
4020         /* Program SSCAUXDIV */
4021         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4022         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4023         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4024         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4025
4026         /* Enable modulator and associated divider */
4027         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4028         temp &= ~SBI_SSCCTL_DISABLE;
4029         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4030
4031         mutex_unlock(&dev_priv->sb_lock);
4032
4033         /* Wait for initialization time */
4034         udelay(24);
4035
4036         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4037 }
4038
4039 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4040                                                 enum pipe pch_transcoder)
4041 {
4042         struct drm_device *dev = crtc->base.dev;
4043         struct drm_i915_private *dev_priv = dev->dev_private;
4044         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4045
4046         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4047                    I915_READ(HTOTAL(cpu_transcoder)));
4048         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4049                    I915_READ(HBLANK(cpu_transcoder)));
4050         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4051                    I915_READ(HSYNC(cpu_transcoder)));
4052
4053         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4054                    I915_READ(VTOTAL(cpu_transcoder)));
4055         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4056                    I915_READ(VBLANK(cpu_transcoder)));
4057         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4058                    I915_READ(VSYNC(cpu_transcoder)));
4059         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4060                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4061 }
4062
4063 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4064 {
4065         struct drm_i915_private *dev_priv = dev->dev_private;
4066         uint32_t temp;
4067
4068         temp = I915_READ(SOUTH_CHICKEN1);
4069         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4070                 return;
4071
4072         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4073         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4074
4075         temp &= ~FDI_BC_BIFURCATION_SELECT;
4076         if (enable)
4077                 temp |= FDI_BC_BIFURCATION_SELECT;
4078
4079         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4080         I915_WRITE(SOUTH_CHICKEN1, temp);
4081         POSTING_READ(SOUTH_CHICKEN1);
4082 }
4083
4084 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4085 {
4086         struct drm_device *dev = intel_crtc->base.dev;
4087
4088         switch (intel_crtc->pipe) {
4089         case PIPE_A:
4090                 break;
4091         case PIPE_B:
4092                 if (intel_crtc->config->fdi_lanes > 2)
4093                         cpt_set_fdi_bc_bifurcation(dev, false);
4094                 else
4095                         cpt_set_fdi_bc_bifurcation(dev, true);
4096
4097                 break;
4098         case PIPE_C:
4099                 cpt_set_fdi_bc_bifurcation(dev, true);
4100
4101                 break;
4102         default:
4103                 BUG();
4104         }
4105 }
4106
4107 /* Return which DP Port should be selected for Transcoder DP control */
4108 static enum port
4109 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4110 {
4111         struct drm_device *dev = crtc->dev;
4112         struct intel_encoder *encoder;
4113
4114         for_each_encoder_on_crtc(dev, crtc, encoder) {
4115                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4116                     encoder->type == INTEL_OUTPUT_EDP)
4117                         return enc_to_dig_port(&encoder->base)->port;
4118         }
4119
4120         return -1;
4121 }
4122
4123 /*
4124  * Enable PCH resources required for PCH ports:
4125  *   - PCH PLLs
4126  *   - FDI training & RX/TX
4127  *   - update transcoder timings
4128  *   - DP transcoding bits
4129  *   - transcoder
4130  */
4131 static void ironlake_pch_enable(struct drm_crtc *crtc)
4132 {
4133         struct drm_device *dev = crtc->dev;
4134         struct drm_i915_private *dev_priv = dev->dev_private;
4135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4136         int pipe = intel_crtc->pipe;
4137         u32 temp;
4138
4139         assert_pch_transcoder_disabled(dev_priv, pipe);
4140
4141         if (IS_IVYBRIDGE(dev))
4142                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4143
4144         /* Write the TU size bits before fdi link training, so that error
4145          * detection works. */
4146         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4147                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4148
4149         /*
4150          * Sometimes spurious CPU pipe underruns happen during FDI
4151          * training, at least with VGA+HDMI cloning. Suppress them.
4152          */
4153         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4154
4155         /* For PCH output, training FDI link */
4156         dev_priv->display.fdi_link_train(crtc);
4157
4158         /* We need to program the right clock selection before writing the pixel
4159          * mutliplier into the DPLL. */
4160         if (HAS_PCH_CPT(dev)) {
4161                 u32 sel;
4162
4163                 temp = I915_READ(PCH_DPLL_SEL);
4164                 temp |= TRANS_DPLL_ENABLE(pipe);
4165                 sel = TRANS_DPLLB_SEL(pipe);
4166                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4167                         temp |= sel;
4168                 else
4169                         temp &= ~sel;
4170                 I915_WRITE(PCH_DPLL_SEL, temp);
4171         }
4172
4173         /* XXX: pch pll's can be enabled any time before we enable the PCH
4174          * transcoder, and we actually should do this to not upset any PCH
4175          * transcoder that already use the clock when we share it.
4176          *
4177          * Note that enable_shared_dpll tries to do the right thing, but
4178          * get_shared_dpll unconditionally resets the pll - we need that to have
4179          * the right LVDS enable sequence. */
4180         intel_enable_shared_dpll(intel_crtc);
4181
4182         /* set transcoder timing, panel must allow it */
4183         assert_panel_unlocked(dev_priv, pipe);
4184         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4185
4186         intel_fdi_normal_train(crtc);
4187
4188         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4189
4190         /* For PCH DP, enable TRANS_DP_CTL */
4191         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4192                 const struct drm_display_mode *adjusted_mode =
4193                         &intel_crtc->config->base.adjusted_mode;
4194                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4195                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4196                 temp = I915_READ(reg);
4197                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4198                           TRANS_DP_SYNC_MASK |
4199                           TRANS_DP_BPC_MASK);
4200                 temp |= TRANS_DP_OUTPUT_ENABLE;
4201                 temp |= bpc << 9; /* same format but at 11:9 */
4202
4203                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4204                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4205                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4206                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4207
4208                 switch (intel_trans_dp_port_sel(crtc)) {
4209                 case PORT_B:
4210                         temp |= TRANS_DP_PORT_SEL_B;
4211                         break;
4212                 case PORT_C:
4213                         temp |= TRANS_DP_PORT_SEL_C;
4214                         break;
4215                 case PORT_D:
4216                         temp |= TRANS_DP_PORT_SEL_D;
4217                         break;
4218                 default:
4219                         BUG();
4220                 }
4221
4222                 I915_WRITE(reg, temp);
4223         }
4224
4225         ironlake_enable_pch_transcoder(dev_priv, pipe);
4226 }
4227
4228 static void lpt_pch_enable(struct drm_crtc *crtc)
4229 {
4230         struct drm_device *dev = crtc->dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4234
4235         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4236
4237         lpt_program_iclkip(crtc);
4238
4239         /* Set transcoder timing. */
4240         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4241
4242         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4243 }
4244
4245 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4246                                                 struct intel_crtc_state *crtc_state)
4247 {
4248         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4249         struct intel_shared_dpll *pll;
4250         struct intel_shared_dpll_config *shared_dpll;
4251         enum intel_dpll_id i;
4252         int max = dev_priv->num_shared_dpll;
4253
4254         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4255
4256         if (HAS_PCH_IBX(dev_priv->dev)) {
4257                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4258                 i = (enum intel_dpll_id) crtc->pipe;
4259                 pll = &dev_priv->shared_dplls[i];
4260
4261                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4262                               crtc->base.base.id, pll->name);
4263
4264                 WARN_ON(shared_dpll[i].crtc_mask);
4265
4266                 goto found;
4267         }
4268
4269         if (IS_BROXTON(dev_priv->dev)) {
4270                 /* PLL is attached to port in bxt */
4271                 struct intel_encoder *encoder;
4272                 struct intel_digital_port *intel_dig_port;
4273
4274                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4275                 if (WARN_ON(!encoder))
4276                         return NULL;
4277
4278                 intel_dig_port = enc_to_dig_port(&encoder->base);
4279                 /* 1:1 mapping between ports and PLLs */
4280                 i = (enum intel_dpll_id)intel_dig_port->port;
4281                 pll = &dev_priv->shared_dplls[i];
4282                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4283                         crtc->base.base.id, pll->name);
4284                 WARN_ON(shared_dpll[i].crtc_mask);
4285
4286                 goto found;
4287         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4288                 /* Do not consider SPLL */
4289                 max = 2;
4290
4291         for (i = 0; i < max; i++) {
4292                 pll = &dev_priv->shared_dplls[i];
4293
4294                 /* Only want to check enabled timings first */
4295                 if (shared_dpll[i].crtc_mask == 0)
4296                         continue;
4297
4298                 if (memcmp(&crtc_state->dpll_hw_state,
4299                            &shared_dpll[i].hw_state,
4300                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4301                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4302                                       crtc->base.base.id, pll->name,
4303                                       shared_dpll[i].crtc_mask,
4304                                       pll->active);
4305                         goto found;
4306                 }
4307         }
4308
4309         /* Ok no matching timings, maybe there's a free one? */
4310         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4311                 pll = &dev_priv->shared_dplls[i];
4312                 if (shared_dpll[i].crtc_mask == 0) {
4313                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4314                                       crtc->base.base.id, pll->name);
4315                         goto found;
4316                 }
4317         }
4318
4319         return NULL;
4320
4321 found:
4322         if (shared_dpll[i].crtc_mask == 0)
4323                 shared_dpll[i].hw_state =
4324                         crtc_state->dpll_hw_state;
4325
4326         crtc_state->shared_dpll = i;
4327         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4328                          pipe_name(crtc->pipe));
4329
4330         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4331
4332         return pll;
4333 }
4334
4335 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4336 {
4337         struct drm_i915_private *dev_priv = to_i915(state->dev);
4338         struct intel_shared_dpll_config *shared_dpll;
4339         struct intel_shared_dpll *pll;
4340         enum intel_dpll_id i;
4341
4342         if (!to_intel_atomic_state(state)->dpll_set)
4343                 return;
4344
4345         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4346         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4347                 pll = &dev_priv->shared_dplls[i];
4348                 pll->config = shared_dpll[i];
4349         }
4350 }
4351
4352 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4353 {
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         i915_reg_t dslreg = PIPEDSL(pipe);
4356         u32 temp;
4357
4358         temp = I915_READ(dslreg);
4359         udelay(500);
4360         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4361                 if (wait_for(I915_READ(dslreg) != temp, 5))
4362                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4363         }
4364 }
4365
4366 static int
4367 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4368                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4369                   int src_w, int src_h, int dst_w, int dst_h)
4370 {
4371         struct intel_crtc_scaler_state *scaler_state =
4372                 &crtc_state->scaler_state;
4373         struct intel_crtc *intel_crtc =
4374                 to_intel_crtc(crtc_state->base.crtc);
4375         int need_scaling;
4376
4377         need_scaling = intel_rotation_90_or_270(rotation) ?
4378                 (src_h != dst_w || src_w != dst_h):
4379                 (src_w != dst_w || src_h != dst_h);
4380
4381         /*
4382          * if plane is being disabled or scaler is no more required or force detach
4383          *  - free scaler binded to this plane/crtc
4384          *  - in order to do this, update crtc->scaler_usage
4385          *
4386          * Here scaler state in crtc_state is set free so that
4387          * scaler can be assigned to other user. Actual register
4388          * update to free the scaler is done in plane/panel-fit programming.
4389          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4390          */
4391         if (force_detach || !need_scaling) {
4392                 if (*scaler_id >= 0) {
4393                         scaler_state->scaler_users &= ~(1 << scaler_user);
4394                         scaler_state->scalers[*scaler_id].in_use = 0;
4395
4396                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4397                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4398                                 intel_crtc->pipe, scaler_user, *scaler_id,
4399                                 scaler_state->scaler_users);
4400                         *scaler_id = -1;
4401                 }
4402                 return 0;
4403         }
4404
4405         /* range checks */
4406         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4407                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4408
4409                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4410                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4411                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4412                         "size is out of scaler range\n",
4413                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4414                 return -EINVAL;
4415         }
4416
4417         /* mark this plane as a scaler user in crtc_state */
4418         scaler_state->scaler_users |= (1 << scaler_user);
4419         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4420                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4421                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4422                 scaler_state->scaler_users);
4423
4424         return 0;
4425 }
4426
4427 /**
4428  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4429  *
4430  * @state: crtc's scaler state
4431  *
4432  * Return
4433  *     0 - scaler_usage updated successfully
4434  *    error - requested scaling cannot be supported or other error condition
4435  */
4436 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4437 {
4438         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4439         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4440
4441         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4442                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4443
4444         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4445                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4446                 state->pipe_src_w, state->pipe_src_h,
4447                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4448 }
4449
4450 /**
4451  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4452  *
4453  * @state: crtc's scaler state
4454  * @plane_state: atomic plane state to update
4455  *
4456  * Return
4457  *     0 - scaler_usage updated successfully
4458  *    error - requested scaling cannot be supported or other error condition
4459  */
4460 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4461                                    struct intel_plane_state *plane_state)
4462 {
4463
4464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4465         struct intel_plane *intel_plane =
4466                 to_intel_plane(plane_state->base.plane);
4467         struct drm_framebuffer *fb = plane_state->base.fb;
4468         int ret;
4469
4470         bool force_detach = !fb || !plane_state->visible;
4471
4472         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4473                       intel_plane->base.base.id, intel_crtc->pipe,
4474                       drm_plane_index(&intel_plane->base));
4475
4476         ret = skl_update_scaler(crtc_state, force_detach,
4477                                 drm_plane_index(&intel_plane->base),
4478                                 &plane_state->scaler_id,
4479                                 plane_state->base.rotation,
4480                                 drm_rect_width(&plane_state->src) >> 16,
4481                                 drm_rect_height(&plane_state->src) >> 16,
4482                                 drm_rect_width(&plane_state->dst),
4483                                 drm_rect_height(&plane_state->dst));
4484
4485         if (ret || plane_state->scaler_id < 0)
4486                 return ret;
4487
4488         /* check colorkey */
4489         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4490                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4491                               intel_plane->base.base.id);
4492                 return -EINVAL;
4493         }
4494
4495         /* Check src format */
4496         switch (fb->pixel_format) {
4497         case DRM_FORMAT_RGB565:
4498         case DRM_FORMAT_XBGR8888:
4499         case DRM_FORMAT_XRGB8888:
4500         case DRM_FORMAT_ABGR8888:
4501         case DRM_FORMAT_ARGB8888:
4502         case DRM_FORMAT_XRGB2101010:
4503         case DRM_FORMAT_XBGR2101010:
4504         case DRM_FORMAT_YUYV:
4505         case DRM_FORMAT_YVYU:
4506         case DRM_FORMAT_UYVY:
4507         case DRM_FORMAT_VYUY:
4508                 break;
4509         default:
4510                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4511                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4512                 return -EINVAL;
4513         }
4514
4515         return 0;
4516 }
4517
4518 static void skylake_scaler_disable(struct intel_crtc *crtc)
4519 {
4520         int i;
4521
4522         for (i = 0; i < crtc->num_scalers; i++)
4523                 skl_detach_scaler(crtc, i);
4524 }
4525
4526 static void skylake_pfit_enable(struct intel_crtc *crtc)
4527 {
4528         struct drm_device *dev = crtc->base.dev;
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530         int pipe = crtc->pipe;
4531         struct intel_crtc_scaler_state *scaler_state =
4532                 &crtc->config->scaler_state;
4533
4534         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4535
4536         if (crtc->config->pch_pfit.enabled) {
4537                 int id;
4538
4539                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4540                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4541                         return;
4542                 }
4543
4544                 id = scaler_state->scaler_id;
4545                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4546                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4547                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4548                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4549
4550                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4551         }
4552 }
4553
4554 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4555 {
4556         struct drm_device *dev = crtc->base.dev;
4557         struct drm_i915_private *dev_priv = dev->dev_private;
4558         int pipe = crtc->pipe;
4559
4560         if (crtc->config->pch_pfit.enabled) {
4561                 /* Force use of hard-coded filter coefficients
4562                  * as some pre-programmed values are broken,
4563                  * e.g. x201.
4564                  */
4565                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4566                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4567                                                  PF_PIPE_SEL_IVB(pipe));
4568                 else
4569                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4570                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4571                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4572         }
4573 }
4574
4575 void hsw_enable_ips(struct intel_crtc *crtc)
4576 {
4577         struct drm_device *dev = crtc->base.dev;
4578         struct drm_i915_private *dev_priv = dev->dev_private;
4579
4580         if (!crtc->config->ips_enabled)
4581                 return;
4582
4583         /* We can only enable IPS after we enable a plane and wait for a vblank */
4584         intel_wait_for_vblank(dev, crtc->pipe);
4585
4586         assert_plane_enabled(dev_priv, crtc->plane);
4587         if (IS_BROADWELL(dev)) {
4588                 mutex_lock(&dev_priv->rps.hw_lock);
4589                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4590                 mutex_unlock(&dev_priv->rps.hw_lock);
4591                 /* Quoting Art Runyan: "its not safe to expect any particular
4592                  * value in IPS_CTL bit 31 after enabling IPS through the
4593                  * mailbox." Moreover, the mailbox may return a bogus state,
4594                  * so we need to just enable it and continue on.
4595                  */
4596         } else {
4597                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4598                 /* The bit only becomes 1 in the next vblank, so this wait here
4599                  * is essentially intel_wait_for_vblank. If we don't have this
4600                  * and don't wait for vblanks until the end of crtc_enable, then
4601                  * the HW state readout code will complain that the expected
4602                  * IPS_CTL value is not the one we read. */
4603                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4604                         DRM_ERROR("Timed out waiting for IPS enable\n");
4605         }
4606 }
4607
4608 void hsw_disable_ips(struct intel_crtc *crtc)
4609 {
4610         struct drm_device *dev = crtc->base.dev;
4611         struct drm_i915_private *dev_priv = dev->dev_private;
4612
4613         if (!crtc->config->ips_enabled)
4614                 return;
4615
4616         assert_plane_enabled(dev_priv, crtc->plane);
4617         if (IS_BROADWELL(dev)) {
4618                 mutex_lock(&dev_priv->rps.hw_lock);
4619                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4620                 mutex_unlock(&dev_priv->rps.hw_lock);
4621                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4622                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4623                         DRM_ERROR("Timed out waiting for IPS disable\n");
4624         } else {
4625                 I915_WRITE(IPS_CTL, 0);
4626                 POSTING_READ(IPS_CTL);
4627         }
4628
4629         /* We need to wait for a vblank before we can disable the plane. */
4630         intel_wait_for_vblank(dev, crtc->pipe);
4631 }
4632
4633 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4634 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4635 {
4636         struct drm_device *dev = crtc->dev;
4637         struct drm_i915_private *dev_priv = dev->dev_private;
4638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4639         enum pipe pipe = intel_crtc->pipe;
4640         int i;
4641         bool reenable_ips = false;
4642
4643         /* The clocks have to be on to load the palette. */
4644         if (!crtc->state->active)
4645                 return;
4646
4647         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4648                 if (intel_crtc->config->has_dsi_encoder)
4649                         assert_dsi_pll_enabled(dev_priv);
4650                 else
4651                         assert_pll_enabled(dev_priv, pipe);
4652         }
4653
4654         /* Workaround : Do not read or write the pipe palette/gamma data while
4655          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4656          */
4657         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4658             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4659              GAMMA_MODE_MODE_SPLIT)) {
4660                 hsw_disable_ips(intel_crtc);
4661                 reenable_ips = true;
4662         }
4663
4664         for (i = 0; i < 256; i++) {
4665                 i915_reg_t palreg;
4666
4667                 if (HAS_GMCH_DISPLAY(dev))
4668                         palreg = PALETTE(pipe, i);
4669                 else
4670                         palreg = LGC_PALETTE(pipe, i);
4671
4672                 I915_WRITE(palreg,
4673                            (intel_crtc->lut_r[i] << 16) |
4674                            (intel_crtc->lut_g[i] << 8) |
4675                            intel_crtc->lut_b[i]);
4676         }
4677
4678         if (reenable_ips)
4679                 hsw_enable_ips(intel_crtc);
4680 }
4681
4682 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4683 {
4684         if (intel_crtc->overlay) {
4685                 struct drm_device *dev = intel_crtc->base.dev;
4686                 struct drm_i915_private *dev_priv = dev->dev_private;
4687
4688                 mutex_lock(&dev->struct_mutex);
4689                 dev_priv->mm.interruptible = false;
4690                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4691                 dev_priv->mm.interruptible = true;
4692                 mutex_unlock(&dev->struct_mutex);
4693         }
4694
4695         /* Let userspace switch the overlay on again. In most cases userspace
4696          * has to recompute where to put it anyway.
4697          */
4698 }
4699
4700 /**
4701  * intel_post_enable_primary - Perform operations after enabling primary plane
4702  * @crtc: the CRTC whose primary plane was just enabled
4703  *
4704  * Performs potentially sleeping operations that must be done after the primary
4705  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4706  * called due to an explicit primary plane update, or due to an implicit
4707  * re-enable that is caused when a sprite plane is updated to no longer
4708  * completely hide the primary plane.
4709  */
4710 static void
4711 intel_post_enable_primary(struct drm_crtc *crtc)
4712 {
4713         struct drm_device *dev = crtc->dev;
4714         struct drm_i915_private *dev_priv = dev->dev_private;
4715         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4716         int pipe = intel_crtc->pipe;
4717
4718         /*
4719          * FIXME IPS should be fine as long as one plane is
4720          * enabled, but in practice it seems to have problems
4721          * when going from primary only to sprite only and vice
4722          * versa.
4723          */
4724         hsw_enable_ips(intel_crtc);
4725
4726         /*
4727          * Gen2 reports pipe underruns whenever all planes are disabled.
4728          * So don't enable underrun reporting before at least some planes
4729          * are enabled.
4730          * FIXME: Need to fix the logic to work when we turn off all planes
4731          * but leave the pipe running.
4732          */
4733         if (IS_GEN2(dev))
4734                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4735
4736         /* Underruns don't always raise interrupts, so check manually. */
4737         intel_check_cpu_fifo_underruns(dev_priv);
4738         intel_check_pch_fifo_underruns(dev_priv);
4739 }
4740
4741 /**
4742  * intel_pre_disable_primary - Perform operations before disabling primary plane
4743  * @crtc: the CRTC whose primary plane is to be disabled
4744  *
4745  * Performs potentially sleeping operations that must be done before the
4746  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4747  * be called due to an explicit primary plane update, or due to an implicit
4748  * disable that is caused when a sprite plane completely hides the primary
4749  * plane.
4750  */
4751 static void
4752 intel_pre_disable_primary(struct drm_crtc *crtc)
4753 {
4754         struct drm_device *dev = crtc->dev;
4755         struct drm_i915_private *dev_priv = dev->dev_private;
4756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4757         int pipe = intel_crtc->pipe;
4758
4759         /*
4760          * Gen2 reports pipe underruns whenever all planes are disabled.
4761          * So diasble underrun reporting before all the planes get disabled.
4762          * FIXME: Need to fix the logic to work when we turn off all planes
4763          * but leave the pipe running.
4764          */
4765         if (IS_GEN2(dev))
4766                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4767
4768         /*
4769          * Vblank time updates from the shadow to live plane control register
4770          * are blocked if the memory self-refresh mode is active at that
4771          * moment. So to make sure the plane gets truly disabled, disable
4772          * first the self-refresh mode. The self-refresh enable bit in turn
4773          * will be checked/applied by the HW only at the next frame start
4774          * event which is after the vblank start event, so we need to have a
4775          * wait-for-vblank between disabling the plane and the pipe.
4776          */
4777         if (HAS_GMCH_DISPLAY(dev)) {
4778                 intel_set_memory_cxsr(dev_priv, false);
4779                 dev_priv->wm.vlv.cxsr = false;
4780                 intel_wait_for_vblank(dev, pipe);
4781         }
4782
4783         /*
4784          * FIXME IPS should be fine as long as one plane is
4785          * enabled, but in practice it seems to have problems
4786          * when going from primary only to sprite only and vice
4787          * versa.
4788          */
4789         hsw_disable_ips(intel_crtc);
4790 }
4791
4792 static void intel_post_plane_update(struct intel_crtc *crtc)
4793 {
4794         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4795         struct intel_crtc_state *pipe_config =
4796                 to_intel_crtc_state(crtc->base.state);
4797         struct drm_device *dev = crtc->base.dev;
4798
4799         if (atomic->wait_vblank)
4800                 intel_wait_for_vblank(dev, crtc->pipe);
4801
4802         intel_frontbuffer_flip(dev, atomic->fb_bits);
4803
4804         crtc->wm.cxsr_allowed = true;
4805
4806         if (pipe_config->wm_changed && pipe_config->base.active)
4807                 intel_update_watermarks(&crtc->base);
4808
4809         if (atomic->update_fbc)
4810                 intel_fbc_update(crtc);
4811
4812         if (atomic->post_enable_primary)
4813                 intel_post_enable_primary(&crtc->base);
4814
4815         memset(atomic, 0, sizeof(*atomic));
4816 }
4817
4818 static void intel_pre_plane_update(struct intel_crtc *crtc)
4819 {
4820         struct drm_device *dev = crtc->base.dev;
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4823         struct intel_crtc_state *pipe_config =
4824                 to_intel_crtc_state(crtc->base.state);
4825
4826         if (atomic->disable_fbc)
4827                 intel_fbc_deactivate(crtc);
4828
4829         if (crtc->atomic.disable_ips)
4830                 hsw_disable_ips(crtc);
4831
4832         if (atomic->pre_disable_primary)
4833                 intel_pre_disable_primary(&crtc->base);
4834
4835         if (pipe_config->disable_cxsr) {
4836                 crtc->wm.cxsr_allowed = false;
4837                 intel_set_memory_cxsr(dev_priv, false);
4838         }
4839
4840         /*
4841          * IVB workaround: must disable low power watermarks for at least
4842          * one frame before enabling scaling.  LP watermarks can be re-enabled
4843          * when scaling is disabled.
4844          *
4845          * WaCxSRDisabledForSpriteScaling:ivb
4846          */
4847         if (pipe_config->disable_lp_wm) {
4848                 ilk_disable_lp_wm(dev);
4849                 intel_wait_for_vblank(dev, crtc->pipe);
4850         }
4851
4852         /*
4853          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4854          * watermark programming here.
4855          */
4856         if (needs_modeset(&pipe_config->base))
4857                 return;
4858
4859         /*
4860          * For platforms that support atomic watermarks, program the
4861          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4862          * will be the intermediate values that are safe for both pre- and
4863          * post- vblank; when vblank happens, the 'active' values will be set
4864          * to the final 'target' values and we'll do this again to get the
4865          * optimal watermarks.  For gen9+ platforms, the values we program here
4866          * will be the final target values which will get automatically latched
4867          * at vblank time; no further programming will be necessary.
4868          *
4869          * If a platform hasn't been transitioned to atomic watermarks yet,
4870          * we'll continue to update watermarks the old way, if flags tell
4871          * us to.
4872          */
4873         if (dev_priv->display.initial_watermarks != NULL)
4874                 dev_priv->display.initial_watermarks(pipe_config);
4875         else if (pipe_config->wm_changed)
4876                 intel_update_watermarks(&crtc->base);
4877 }
4878
4879 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4880 {
4881         struct drm_device *dev = crtc->dev;
4882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4883         struct drm_plane *p;
4884         int pipe = intel_crtc->pipe;
4885
4886         intel_crtc_dpms_overlay_disable(intel_crtc);
4887
4888         drm_for_each_plane_mask(p, dev, plane_mask)
4889                 to_intel_plane(p)->disable_plane(p, crtc);
4890
4891         /*
4892          * FIXME: Once we grow proper nuclear flip support out of this we need
4893          * to compute the mask of flip planes precisely. For the time being
4894          * consider this a flip to a NULL plane.
4895          */
4896         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4897 }
4898
4899 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4900 {
4901         struct drm_device *dev = crtc->dev;
4902         struct drm_i915_private *dev_priv = dev->dev_private;
4903         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4904         struct intel_encoder *encoder;
4905         int pipe = intel_crtc->pipe;
4906
4907         if (WARN_ON(intel_crtc->active))
4908                 return;
4909
4910         if (intel_crtc->config->has_pch_encoder)
4911                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4912
4913         if (intel_crtc->config->has_pch_encoder)
4914                 intel_prepare_shared_dpll(intel_crtc);
4915
4916         if (intel_crtc->config->has_dp_encoder)
4917                 intel_dp_set_m_n(intel_crtc, M1_N1);
4918
4919         intel_set_pipe_timings(intel_crtc);
4920
4921         if (intel_crtc->config->has_pch_encoder) {
4922                 intel_cpu_transcoder_set_m_n(intel_crtc,
4923                                      &intel_crtc->config->fdi_m_n, NULL);
4924         }
4925
4926         ironlake_set_pipeconf(crtc);
4927
4928         intel_crtc->active = true;
4929
4930         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4931
4932         for_each_encoder_on_crtc(dev, crtc, encoder)
4933                 if (encoder->pre_enable)
4934                         encoder->pre_enable(encoder);
4935
4936         if (intel_crtc->config->has_pch_encoder) {
4937                 /* Note: FDI PLL enabling _must_ be done before we enable the
4938                  * cpu pipes, hence this is separate from all the other fdi/pch
4939                  * enabling. */
4940                 ironlake_fdi_pll_enable(intel_crtc);
4941         } else {
4942                 assert_fdi_tx_disabled(dev_priv, pipe);
4943                 assert_fdi_rx_disabled(dev_priv, pipe);
4944         }
4945
4946         ironlake_pfit_enable(intel_crtc);
4947
4948         /*
4949          * On ILK+ LUT must be loaded before the pipe is running but with
4950          * clocks enabled
4951          */
4952         intel_crtc_load_lut(crtc);
4953
4954         intel_update_watermarks(crtc);
4955         intel_enable_pipe(intel_crtc);
4956
4957         if (intel_crtc->config->has_pch_encoder)
4958                 ironlake_pch_enable(crtc);
4959
4960         assert_vblank_disabled(crtc);
4961         drm_crtc_vblank_on(crtc);
4962
4963         for_each_encoder_on_crtc(dev, crtc, encoder)
4964                 encoder->enable(encoder);
4965
4966         if (HAS_PCH_CPT(dev))
4967                 cpt_verify_modeset(dev, intel_crtc->pipe);
4968
4969         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4970         if (intel_crtc->config->has_pch_encoder)
4971                 intel_wait_for_vblank(dev, pipe);
4972         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4973
4974         intel_fbc_enable(intel_crtc);
4975 }
4976
4977 /* IPS only exists on ULT machines and is tied to pipe A. */
4978 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4979 {
4980         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4981 }
4982
4983 static void haswell_crtc_enable(struct drm_crtc *crtc)
4984 {
4985         struct drm_device *dev = crtc->dev;
4986         struct drm_i915_private *dev_priv = dev->dev_private;
4987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4988         struct intel_encoder *encoder;
4989         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4990         struct intel_crtc_state *pipe_config =
4991                 to_intel_crtc_state(crtc->state);
4992
4993         if (WARN_ON(intel_crtc->active))
4994                 return;
4995
4996         if (intel_crtc->config->has_pch_encoder)
4997                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4998                                                       false);
4999
5000         if (intel_crtc_to_shared_dpll(intel_crtc))
5001                 intel_enable_shared_dpll(intel_crtc);
5002
5003         if (intel_crtc->config->has_dp_encoder)
5004                 intel_dp_set_m_n(intel_crtc, M1_N1);
5005
5006         intel_set_pipe_timings(intel_crtc);
5007
5008         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5009                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5010                            intel_crtc->config->pixel_multiplier - 1);
5011         }
5012
5013         if (intel_crtc->config->has_pch_encoder) {
5014                 intel_cpu_transcoder_set_m_n(intel_crtc,
5015                                      &intel_crtc->config->fdi_m_n, NULL);
5016         }
5017
5018         haswell_set_pipeconf(crtc);
5019
5020         intel_set_pipe_csc(crtc);
5021
5022         intel_crtc->active = true;
5023
5024         if (intel_crtc->config->has_pch_encoder)
5025                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5026         else
5027                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5028
5029         for_each_encoder_on_crtc(dev, crtc, encoder) {
5030                 if (encoder->pre_enable)
5031                         encoder->pre_enable(encoder);
5032         }
5033
5034         if (intel_crtc->config->has_pch_encoder)
5035                 dev_priv->display.fdi_link_train(crtc);
5036
5037         if (!intel_crtc->config->has_dsi_encoder)
5038                 intel_ddi_enable_pipe_clock(intel_crtc);
5039
5040         if (INTEL_INFO(dev)->gen >= 9)
5041                 skylake_pfit_enable(intel_crtc);
5042         else
5043                 ironlake_pfit_enable(intel_crtc);
5044
5045         /*
5046          * On ILK+ LUT must be loaded before the pipe is running but with
5047          * clocks enabled
5048          */
5049         intel_crtc_load_lut(crtc);
5050
5051         intel_ddi_set_pipe_settings(crtc);
5052         if (!intel_crtc->config->has_dsi_encoder)
5053                 intel_ddi_enable_transcoder_func(crtc);
5054
5055         intel_update_watermarks(crtc);
5056         intel_enable_pipe(intel_crtc);
5057
5058         if (intel_crtc->config->has_pch_encoder)
5059                 lpt_pch_enable(crtc);
5060
5061         if (intel_crtc->config->dp_encoder_is_mst)
5062                 intel_ddi_set_vc_payload_alloc(crtc, true);
5063
5064         assert_vblank_disabled(crtc);
5065         drm_crtc_vblank_on(crtc);
5066
5067         for_each_encoder_on_crtc(dev, crtc, encoder) {
5068                 encoder->enable(encoder);
5069                 intel_opregion_notify_encoder(encoder, true);
5070         }
5071
5072         if (intel_crtc->config->has_pch_encoder) {
5073                 intel_wait_for_vblank(dev, pipe);
5074                 intel_wait_for_vblank(dev, pipe);
5075                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5076                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5077                                                       true);
5078         }
5079
5080         /* If we change the relative order between pipe/planes enabling, we need
5081          * to change the workaround. */
5082         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5083         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5084                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5085                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5086         }
5087
5088         intel_fbc_enable(intel_crtc);
5089 }
5090
5091 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5092 {
5093         struct drm_device *dev = crtc->base.dev;
5094         struct drm_i915_private *dev_priv = dev->dev_private;
5095         int pipe = crtc->pipe;
5096
5097         /* To avoid upsetting the power well on haswell only disable the pfit if
5098          * it's in use. The hw state code will make sure we get this right. */
5099         if (force || crtc->config->pch_pfit.enabled) {
5100                 I915_WRITE(PF_CTL(pipe), 0);
5101                 I915_WRITE(PF_WIN_POS(pipe), 0);
5102                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5103         }
5104 }
5105
5106 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5107 {
5108         struct drm_device *dev = crtc->dev;
5109         struct drm_i915_private *dev_priv = dev->dev_private;
5110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5111         struct intel_encoder *encoder;
5112         int pipe = intel_crtc->pipe;
5113
5114         if (intel_crtc->config->has_pch_encoder)
5115                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5116
5117         for_each_encoder_on_crtc(dev, crtc, encoder)
5118                 encoder->disable(encoder);
5119
5120         drm_crtc_vblank_off(crtc);
5121         assert_vblank_disabled(crtc);
5122
5123         /*
5124          * Sometimes spurious CPU pipe underruns happen when the
5125          * pipe is already disabled, but FDI RX/TX is still enabled.
5126          * Happens at least with VGA+HDMI cloning. Suppress them.
5127          */
5128         if (intel_crtc->config->has_pch_encoder)
5129                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5130
5131         intel_disable_pipe(intel_crtc);
5132
5133         ironlake_pfit_disable(intel_crtc, false);
5134
5135         if (intel_crtc->config->has_pch_encoder) {
5136                 ironlake_fdi_disable(crtc);
5137                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5138         }
5139
5140         for_each_encoder_on_crtc(dev, crtc, encoder)
5141                 if (encoder->post_disable)
5142                         encoder->post_disable(encoder);
5143
5144         if (intel_crtc->config->has_pch_encoder) {
5145                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5146
5147                 if (HAS_PCH_CPT(dev)) {
5148                         i915_reg_t reg;
5149                         u32 temp;
5150
5151                         /* disable TRANS_DP_CTL */
5152                         reg = TRANS_DP_CTL(pipe);
5153                         temp = I915_READ(reg);
5154                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5155                                   TRANS_DP_PORT_SEL_MASK);
5156                         temp |= TRANS_DP_PORT_SEL_NONE;
5157                         I915_WRITE(reg, temp);
5158
5159                         /* disable DPLL_SEL */
5160                         temp = I915_READ(PCH_DPLL_SEL);
5161                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5162                         I915_WRITE(PCH_DPLL_SEL, temp);
5163                 }
5164
5165                 ironlake_fdi_pll_disable(intel_crtc);
5166         }
5167
5168         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5169
5170         intel_fbc_disable_crtc(intel_crtc);
5171 }
5172
5173 static void haswell_crtc_disable(struct drm_crtc *crtc)
5174 {
5175         struct drm_device *dev = crtc->dev;
5176         struct drm_i915_private *dev_priv = dev->dev_private;
5177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5178         struct intel_encoder *encoder;
5179         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5180
5181         if (intel_crtc->config->has_pch_encoder)
5182                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5183                                                       false);
5184
5185         for_each_encoder_on_crtc(dev, crtc, encoder) {
5186                 intel_opregion_notify_encoder(encoder, false);
5187                 encoder->disable(encoder);
5188         }
5189
5190         drm_crtc_vblank_off(crtc);
5191         assert_vblank_disabled(crtc);
5192
5193         intel_disable_pipe(intel_crtc);
5194
5195         if (intel_crtc->config->dp_encoder_is_mst)
5196                 intel_ddi_set_vc_payload_alloc(crtc, false);
5197
5198         if (!intel_crtc->config->has_dsi_encoder)
5199                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5200
5201         if (INTEL_INFO(dev)->gen >= 9)
5202                 skylake_scaler_disable(intel_crtc);
5203         else
5204                 ironlake_pfit_disable(intel_crtc, false);
5205
5206         if (!intel_crtc->config->has_dsi_encoder)
5207                 intel_ddi_disable_pipe_clock(intel_crtc);
5208
5209         for_each_encoder_on_crtc(dev, crtc, encoder)
5210                 if (encoder->post_disable)
5211                         encoder->post_disable(encoder);
5212
5213         if (intel_crtc->config->has_pch_encoder) {
5214                 lpt_disable_pch_transcoder(dev_priv);
5215                 lpt_disable_iclkip(dev_priv);
5216                 intel_ddi_fdi_disable(crtc);
5217
5218                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5219                                                       true);
5220         }
5221
5222         intel_fbc_disable_crtc(intel_crtc);
5223 }
5224
5225 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5226 {
5227         struct drm_device *dev = crtc->base.dev;
5228         struct drm_i915_private *dev_priv = dev->dev_private;
5229         struct intel_crtc_state *pipe_config = crtc->config;
5230
5231         if (!pipe_config->gmch_pfit.control)
5232                 return;
5233
5234         /*
5235          * The panel fitter should only be adjusted whilst the pipe is disabled,
5236          * according to register description and PRM.
5237          */
5238         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5239         assert_pipe_disabled(dev_priv, crtc->pipe);
5240
5241         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5242         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5243
5244         /* Border color in case we don't scale up to the full screen. Black by
5245          * default, change to something else for debugging. */
5246         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5247 }
5248
5249 static enum intel_display_power_domain port_to_power_domain(enum port port)
5250 {
5251         switch (port) {
5252         case PORT_A:
5253                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5254         case PORT_B:
5255                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5256         case PORT_C:
5257                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5258         case PORT_D:
5259                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5260         case PORT_E:
5261                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5262         default:
5263                 MISSING_CASE(port);
5264                 return POWER_DOMAIN_PORT_OTHER;
5265         }
5266 }
5267
5268 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5269 {
5270         switch (port) {
5271         case PORT_A:
5272                 return POWER_DOMAIN_AUX_A;
5273         case PORT_B:
5274                 return POWER_DOMAIN_AUX_B;
5275         case PORT_C:
5276                 return POWER_DOMAIN_AUX_C;
5277         case PORT_D:
5278                 return POWER_DOMAIN_AUX_D;
5279         case PORT_E:
5280                 /* FIXME: Check VBT for actual wiring of PORT E */
5281                 return POWER_DOMAIN_AUX_D;
5282         default:
5283                 MISSING_CASE(port);
5284                 return POWER_DOMAIN_AUX_A;
5285         }
5286 }
5287
5288 enum intel_display_power_domain
5289 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5290 {
5291         struct drm_device *dev = intel_encoder->base.dev;
5292         struct intel_digital_port *intel_dig_port;
5293
5294         switch (intel_encoder->type) {
5295         case INTEL_OUTPUT_UNKNOWN:
5296                 /* Only DDI platforms should ever use this output type */
5297                 WARN_ON_ONCE(!HAS_DDI(dev));
5298         case INTEL_OUTPUT_DISPLAYPORT:
5299         case INTEL_OUTPUT_HDMI:
5300         case INTEL_OUTPUT_EDP:
5301                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5302                 return port_to_power_domain(intel_dig_port->port);
5303         case INTEL_OUTPUT_DP_MST:
5304                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5305                 return port_to_power_domain(intel_dig_port->port);
5306         case INTEL_OUTPUT_ANALOG:
5307                 return POWER_DOMAIN_PORT_CRT;
5308         case INTEL_OUTPUT_DSI:
5309                 return POWER_DOMAIN_PORT_DSI;
5310         default:
5311                 return POWER_DOMAIN_PORT_OTHER;
5312         }
5313 }
5314
5315 enum intel_display_power_domain
5316 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5317 {
5318         struct drm_device *dev = intel_encoder->base.dev;
5319         struct intel_digital_port *intel_dig_port;
5320
5321         switch (intel_encoder->type) {
5322         case INTEL_OUTPUT_UNKNOWN:
5323         case INTEL_OUTPUT_HDMI:
5324                 /*
5325                  * Only DDI platforms should ever use these output types.
5326                  * We can get here after the HDMI detect code has already set
5327                  * the type of the shared encoder. Since we can't be sure
5328                  * what's the status of the given connectors, play safe and
5329                  * run the DP detection too.
5330                  */
5331                 WARN_ON_ONCE(!HAS_DDI(dev));
5332         case INTEL_OUTPUT_DISPLAYPORT:
5333         case INTEL_OUTPUT_EDP:
5334                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5335                 return port_to_aux_power_domain(intel_dig_port->port);
5336         case INTEL_OUTPUT_DP_MST:
5337                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5338                 return port_to_aux_power_domain(intel_dig_port->port);
5339         default:
5340                 MISSING_CASE(intel_encoder->type);
5341                 return POWER_DOMAIN_AUX_A;
5342         }
5343 }
5344
5345 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5346 {
5347         struct drm_device *dev = crtc->dev;
5348         struct intel_encoder *intel_encoder;
5349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5350         enum pipe pipe = intel_crtc->pipe;
5351         unsigned long mask;
5352         enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5353
5354         if (!crtc->state->active)
5355                 return 0;
5356
5357         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5358         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5359         if (intel_crtc->config->pch_pfit.enabled ||
5360             intel_crtc->config->pch_pfit.force_thru)
5361                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5362
5363         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5364                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5365
5366         return mask;
5367 }
5368
5369 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5370 {
5371         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5373         enum intel_display_power_domain domain;
5374         unsigned long domains, new_domains, old_domains;
5375
5376         old_domains = intel_crtc->enabled_power_domains;
5377         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5378
5379         domains = new_domains & ~old_domains;
5380
5381         for_each_power_domain(domain, domains)
5382                 intel_display_power_get(dev_priv, domain);
5383
5384         return old_domains & ~new_domains;
5385 }
5386
5387 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5388                                       unsigned long domains)
5389 {
5390         enum intel_display_power_domain domain;
5391
5392         for_each_power_domain(domain, domains)
5393                 intel_display_power_put(dev_priv, domain);
5394 }
5395
5396 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5397 {
5398         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5399         struct drm_device *dev = state->dev;
5400         struct drm_i915_private *dev_priv = dev->dev_private;
5401         unsigned long put_domains[I915_MAX_PIPES] = {};
5402         struct drm_crtc_state *crtc_state;
5403         struct drm_crtc *crtc;
5404         int i;
5405
5406         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5407                 if (needs_modeset(crtc->state))
5408                         put_domains[to_intel_crtc(crtc)->pipe] =
5409                                 modeset_get_crtc_power_domains(crtc);
5410         }
5411
5412         if (dev_priv->display.modeset_commit_cdclk &&
5413             intel_state->dev_cdclk != dev_priv->cdclk_freq)
5414                 dev_priv->display.modeset_commit_cdclk(state);
5415
5416         for (i = 0; i < I915_MAX_PIPES; i++)
5417                 if (put_domains[i])
5418                         modeset_put_power_domains(dev_priv, put_domains[i]);
5419 }
5420
5421 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5422 {
5423         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5424
5425         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5426             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5427                 return max_cdclk_freq;
5428         else if (IS_CHERRYVIEW(dev_priv))
5429                 return max_cdclk_freq*95/100;
5430         else if (INTEL_INFO(dev_priv)->gen < 4)
5431                 return 2*max_cdclk_freq*90/100;
5432         else
5433                 return max_cdclk_freq*90/100;
5434 }
5435
5436 static void intel_update_max_cdclk(struct drm_device *dev)
5437 {
5438         struct drm_i915_private *dev_priv = dev->dev_private;
5439
5440         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5441                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5442
5443                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5444                         dev_priv->max_cdclk_freq = 675000;
5445                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5446                         dev_priv->max_cdclk_freq = 540000;
5447                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5448                         dev_priv->max_cdclk_freq = 450000;
5449                 else
5450                         dev_priv->max_cdclk_freq = 337500;
5451         } else if (IS_BROADWELL(dev))  {
5452                 /*
5453                  * FIXME with extra cooling we can allow
5454                  * 540 MHz for ULX and 675 Mhz for ULT.
5455                  * How can we know if extra cooling is
5456                  * available? PCI ID, VTB, something else?
5457                  */
5458                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5459                         dev_priv->max_cdclk_freq = 450000;
5460                 else if (IS_BDW_ULX(dev))
5461                         dev_priv->max_cdclk_freq = 450000;
5462                 else if (IS_BDW_ULT(dev))
5463                         dev_priv->max_cdclk_freq = 540000;
5464                 else
5465                         dev_priv->max_cdclk_freq = 675000;
5466         } else if (IS_CHERRYVIEW(dev)) {
5467                 dev_priv->max_cdclk_freq = 320000;
5468         } else if (IS_VALLEYVIEW(dev)) {
5469                 dev_priv->max_cdclk_freq = 400000;
5470         } else {
5471                 /* otherwise assume cdclk is fixed */
5472                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5473         }
5474
5475         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5476
5477         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5478                          dev_priv->max_cdclk_freq);
5479
5480         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5481                          dev_priv->max_dotclk_freq);
5482 }
5483
5484 static void intel_update_cdclk(struct drm_device *dev)
5485 {
5486         struct drm_i915_private *dev_priv = dev->dev_private;
5487
5488         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5489         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5490                          dev_priv->cdclk_freq);
5491
5492         /*
5493          * Program the gmbus_freq based on the cdclk frequency.
5494          * BSpec erroneously claims we should aim for 4MHz, but
5495          * in fact 1MHz is the correct frequency.
5496          */
5497         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5498                 /*
5499                  * Program the gmbus_freq based on the cdclk frequency.
5500                  * BSpec erroneously claims we should aim for 4MHz, but
5501                  * in fact 1MHz is the correct frequency.
5502                  */
5503                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5504         }
5505
5506         if (dev_priv->max_cdclk_freq == 0)
5507                 intel_update_max_cdclk(dev);
5508 }
5509
5510 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5511 {
5512         struct drm_i915_private *dev_priv = dev->dev_private;
5513         uint32_t divider;
5514         uint32_t ratio;
5515         uint32_t current_freq;
5516         int ret;
5517
5518         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5519         switch (frequency) {
5520         case 144000:
5521                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5522                 ratio = BXT_DE_PLL_RATIO(60);
5523                 break;
5524         case 288000:
5525                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5526                 ratio = BXT_DE_PLL_RATIO(60);
5527                 break;
5528         case 384000:
5529                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5530                 ratio = BXT_DE_PLL_RATIO(60);
5531                 break;
5532         case 576000:
5533                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5534                 ratio = BXT_DE_PLL_RATIO(60);
5535                 break;
5536         case 624000:
5537                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5538                 ratio = BXT_DE_PLL_RATIO(65);
5539                 break;
5540         case 19200:
5541                 /*
5542                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5543                  * to suppress GCC warning.
5544                  */
5545                 ratio = 0;
5546                 divider = 0;
5547                 break;
5548         default:
5549                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5550
5551                 return;
5552         }
5553
5554         mutex_lock(&dev_priv->rps.hw_lock);
5555         /* Inform power controller of upcoming frequency change */
5556         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5557                                       0x80000000);
5558         mutex_unlock(&dev_priv->rps.hw_lock);
5559
5560         if (ret) {
5561                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5562                           ret, frequency);
5563                 return;
5564         }
5565
5566         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5567         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5568         current_freq = current_freq * 500 + 1000;
5569
5570         /*
5571          * DE PLL has to be disabled when
5572          * - setting to 19.2MHz (bypass, PLL isn't used)
5573          * - before setting to 624MHz (PLL needs toggling)
5574          * - before setting to any frequency from 624MHz (PLL needs toggling)
5575          */
5576         if (frequency == 19200 || frequency == 624000 ||
5577             current_freq == 624000) {
5578                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5579                 /* Timeout 200us */
5580                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5581                              1))
5582                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5583         }
5584
5585         if (frequency != 19200) {
5586                 uint32_t val;
5587
5588                 val = I915_READ(BXT_DE_PLL_CTL);
5589                 val &= ~BXT_DE_PLL_RATIO_MASK;
5590                 val |= ratio;
5591                 I915_WRITE(BXT_DE_PLL_CTL, val);
5592
5593                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5594                 /* Timeout 200us */
5595                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5596                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5597
5598                 val = I915_READ(CDCLK_CTL);
5599                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5600                 val |= divider;
5601                 /*
5602                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5603                  * enable otherwise.
5604                  */
5605                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5606                 if (frequency >= 500000)
5607                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5608
5609                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5610                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5611                 val |= (frequency - 1000) / 500;
5612                 I915_WRITE(CDCLK_CTL, val);
5613         }
5614
5615         mutex_lock(&dev_priv->rps.hw_lock);
5616         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5617                                       DIV_ROUND_UP(frequency, 25000));
5618         mutex_unlock(&dev_priv->rps.hw_lock);
5619
5620         if (ret) {
5621                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5622                           ret, frequency);
5623                 return;
5624         }
5625
5626         intel_update_cdclk(dev);
5627 }
5628
5629 void broxton_init_cdclk(struct drm_device *dev)
5630 {
5631         struct drm_i915_private *dev_priv = dev->dev_private;
5632         uint32_t val;
5633
5634         /*
5635          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5636          * or else the reset will hang because there is no PCH to respond.
5637          * Move the handshake programming to initialization sequence.
5638          * Previously was left up to BIOS.
5639          */
5640         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5641         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5642         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5643
5644         /* Enable PG1 for cdclk */
5645         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5646
5647         /* check if cd clock is enabled */
5648         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5649                 DRM_DEBUG_KMS("Display already initialized\n");
5650                 return;
5651         }
5652
5653         /*
5654          * FIXME:
5655          * - The initial CDCLK needs to be read from VBT.
5656          *   Need to make this change after VBT has changes for BXT.
5657          * - check if setting the max (or any) cdclk freq is really necessary
5658          *   here, it belongs to modeset time
5659          */
5660         broxton_set_cdclk(dev, 624000);
5661
5662         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5663         POSTING_READ(DBUF_CTL);
5664
5665         udelay(10);
5666
5667         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5668                 DRM_ERROR("DBuf power enable timeout!\n");
5669 }
5670
5671 void broxton_uninit_cdclk(struct drm_device *dev)
5672 {
5673         struct drm_i915_private *dev_priv = dev->dev_private;
5674
5675         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5676         POSTING_READ(DBUF_CTL);
5677
5678         udelay(10);
5679
5680         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5681                 DRM_ERROR("DBuf power disable timeout!\n");
5682
5683         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5684         broxton_set_cdclk(dev, 19200);
5685
5686         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5687 }
5688
5689 static const struct skl_cdclk_entry {
5690         unsigned int freq;
5691         unsigned int vco;
5692 } skl_cdclk_frequencies[] = {
5693         { .freq = 308570, .vco = 8640 },
5694         { .freq = 337500, .vco = 8100 },
5695         { .freq = 432000, .vco = 8640 },
5696         { .freq = 450000, .vco = 8100 },
5697         { .freq = 540000, .vco = 8100 },
5698         { .freq = 617140, .vco = 8640 },
5699         { .freq = 675000, .vco = 8100 },
5700 };
5701
5702 static unsigned int skl_cdclk_decimal(unsigned int freq)
5703 {
5704         return (freq - 1000) / 500;
5705 }
5706
5707 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5708 {
5709         unsigned int i;
5710
5711         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5712                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5713
5714                 if (e->freq == freq)
5715                         return e->vco;
5716         }
5717
5718         return 8100;
5719 }
5720
5721 static void
5722 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5723 {
5724         unsigned int min_freq;
5725         u32 val;
5726
5727         /* select the minimum CDCLK before enabling DPLL 0 */
5728         val = I915_READ(CDCLK_CTL);
5729         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5730         val |= CDCLK_FREQ_337_308;
5731
5732         if (required_vco == 8640)
5733                 min_freq = 308570;
5734         else
5735                 min_freq = 337500;
5736
5737         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5738
5739         I915_WRITE(CDCLK_CTL, val);
5740         POSTING_READ(CDCLK_CTL);
5741
5742         /*
5743          * We always enable DPLL0 with the lowest link rate possible, but still
5744          * taking into account the VCO required to operate the eDP panel at the
5745          * desired frequency. The usual DP link rates operate with a VCO of
5746          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5747          * The modeset code is responsible for the selection of the exact link
5748          * rate later on, with the constraint of choosing a frequency that
5749          * works with required_vco.
5750          */
5751         val = I915_READ(DPLL_CTRL1);
5752
5753         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5754                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5755         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5756         if (required_vco == 8640)
5757                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5758                                             SKL_DPLL0);
5759         else
5760                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5761                                             SKL_DPLL0);
5762
5763         I915_WRITE(DPLL_CTRL1, val);
5764         POSTING_READ(DPLL_CTRL1);
5765
5766         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5767
5768         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5769                 DRM_ERROR("DPLL0 not locked\n");
5770 }
5771
5772 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5773 {
5774         int ret;
5775         u32 val;
5776
5777         /* inform PCU we want to change CDCLK */
5778         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5779         mutex_lock(&dev_priv->rps.hw_lock);
5780         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5781         mutex_unlock(&dev_priv->rps.hw_lock);
5782
5783         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5784 }
5785
5786 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5787 {
5788         unsigned int i;
5789
5790         for (i = 0; i < 15; i++) {
5791                 if (skl_cdclk_pcu_ready(dev_priv))
5792                         return true;
5793                 udelay(10);
5794         }
5795
5796         return false;
5797 }
5798
5799 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5800 {
5801         struct drm_device *dev = dev_priv->dev;
5802         u32 freq_select, pcu_ack;
5803
5804         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5805
5806         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5807                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5808                 return;
5809         }
5810
5811         /* set CDCLK_CTL */
5812         switch(freq) {
5813         case 450000:
5814         case 432000:
5815                 freq_select = CDCLK_FREQ_450_432;
5816                 pcu_ack = 1;
5817                 break;
5818         case 540000:
5819                 freq_select = CDCLK_FREQ_540;
5820                 pcu_ack = 2;
5821                 break;
5822         case 308570:
5823         case 337500:
5824         default:
5825                 freq_select = CDCLK_FREQ_337_308;
5826                 pcu_ack = 0;
5827                 break;
5828         case 617140:
5829         case 675000:
5830                 freq_select = CDCLK_FREQ_675_617;
5831                 pcu_ack = 3;
5832                 break;
5833         }
5834
5835         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5836         POSTING_READ(CDCLK_CTL);
5837
5838         /* inform PCU of the change */
5839         mutex_lock(&dev_priv->rps.hw_lock);
5840         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5841         mutex_unlock(&dev_priv->rps.hw_lock);
5842
5843         intel_update_cdclk(dev);
5844 }
5845
5846 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5847 {
5848         /* disable DBUF power */
5849         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5850         POSTING_READ(DBUF_CTL);
5851
5852         udelay(10);
5853
5854         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5855                 DRM_ERROR("DBuf power disable timeout\n");
5856
5857         /* disable DPLL0 */
5858         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5859         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5860                 DRM_ERROR("Couldn't disable DPLL0\n");
5861 }
5862
5863 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5864 {
5865         unsigned int required_vco;
5866
5867         /* DPLL0 not enabled (happens on early BIOS versions) */
5868         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5869                 /* enable DPLL0 */
5870                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5871                 skl_dpll0_enable(dev_priv, required_vco);
5872         }
5873
5874         /* set CDCLK to the frequency the BIOS chose */
5875         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5876
5877         /* enable DBUF power */
5878         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5879         POSTING_READ(DBUF_CTL);
5880
5881         udelay(10);
5882
5883         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5884                 DRM_ERROR("DBuf power enable timeout\n");
5885 }
5886
5887 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5888 {
5889         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5890         uint32_t cdctl = I915_READ(CDCLK_CTL);
5891         int freq = dev_priv->skl_boot_cdclk;
5892
5893         /*
5894          * check if the pre-os intialized the display
5895          * There is SWF18 scratchpad register defined which is set by the
5896          * pre-os which can be used by the OS drivers to check the status
5897          */
5898         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5899                 goto sanitize;
5900
5901         /* Is PLL enabled and locked ? */
5902         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5903                 goto sanitize;
5904
5905         /* DPLL okay; verify the cdclock
5906          *
5907          * Noticed in some instances that the freq selection is correct but
5908          * decimal part is programmed wrong from BIOS where pre-os does not
5909          * enable display. Verify the same as well.
5910          */
5911         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5912                 /* All well; nothing to sanitize */
5913                 return false;
5914 sanitize:
5915         /*
5916          * As of now initialize with max cdclk till
5917          * we get dynamic cdclk support
5918          * */
5919         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5920         skl_init_cdclk(dev_priv);
5921
5922         /* we did have to sanitize */
5923         return true;
5924 }
5925
5926 /* Adjust CDclk dividers to allow high res or save power if possible */
5927 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5928 {
5929         struct drm_i915_private *dev_priv = dev->dev_private;
5930         u32 val, cmd;
5931
5932         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5933                                         != dev_priv->cdclk_freq);
5934
5935         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5936                 cmd = 2;
5937         else if (cdclk == 266667)
5938                 cmd = 1;
5939         else
5940                 cmd = 0;
5941
5942         mutex_lock(&dev_priv->rps.hw_lock);
5943         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5944         val &= ~DSPFREQGUAR_MASK;
5945         val |= (cmd << DSPFREQGUAR_SHIFT);
5946         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5947         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5948                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5949                      50)) {
5950                 DRM_ERROR("timed out waiting for CDclk change\n");
5951         }
5952         mutex_unlock(&dev_priv->rps.hw_lock);
5953
5954         mutex_lock(&dev_priv->sb_lock);
5955
5956         if (cdclk == 400000) {
5957                 u32 divider;
5958
5959                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5960
5961                 /* adjust cdclk divider */
5962                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5963                 val &= ~CCK_FREQUENCY_VALUES;
5964                 val |= divider;
5965                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5966
5967                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5968                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5969                              50))
5970                         DRM_ERROR("timed out waiting for CDclk change\n");
5971         }
5972
5973         /* adjust self-refresh exit latency value */
5974         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5975         val &= ~0x7f;
5976
5977         /*
5978          * For high bandwidth configs, we set a higher latency in the bunit
5979          * so that the core display fetch happens in time to avoid underruns.
5980          */
5981         if (cdclk == 400000)
5982                 val |= 4500 / 250; /* 4.5 usec */
5983         else
5984                 val |= 3000 / 250; /* 3.0 usec */
5985         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5986
5987         mutex_unlock(&dev_priv->sb_lock);
5988
5989         intel_update_cdclk(dev);
5990 }
5991
5992 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5993 {
5994         struct drm_i915_private *dev_priv = dev->dev_private;
5995         u32 val, cmd;
5996
5997         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5998                                                 != dev_priv->cdclk_freq);
5999
6000         switch (cdclk) {
6001         case 333333:
6002         case 320000:
6003         case 266667:
6004         case 200000:
6005                 break;
6006         default:
6007                 MISSING_CASE(cdclk);
6008                 return;
6009         }
6010
6011         /*
6012          * Specs are full of misinformation, but testing on actual
6013          * hardware has shown that we just need to write the desired
6014          * CCK divider into the Punit register.
6015          */
6016         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6017
6018         mutex_lock(&dev_priv->rps.hw_lock);
6019         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6020         val &= ~DSPFREQGUAR_MASK_CHV;
6021         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6022         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6023         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6024                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6025                      50)) {
6026                 DRM_ERROR("timed out waiting for CDclk change\n");
6027         }
6028         mutex_unlock(&dev_priv->rps.hw_lock);
6029
6030         intel_update_cdclk(dev);
6031 }
6032
6033 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6034                                  int max_pixclk)
6035 {
6036         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6037         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6038
6039         /*
6040          * Really only a few cases to deal with, as only 4 CDclks are supported:
6041          *   200MHz
6042          *   267MHz
6043          *   320/333MHz (depends on HPLL freq)
6044          *   400MHz (VLV only)
6045          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6046          * of the lower bin and adjust if needed.
6047          *
6048          * We seem to get an unstable or solid color picture at 200MHz.
6049          * Not sure what's wrong. For now use 200MHz only when all pipes
6050          * are off.
6051          */
6052         if (!IS_CHERRYVIEW(dev_priv) &&
6053             max_pixclk > freq_320*limit/100)
6054                 return 400000;
6055         else if (max_pixclk > 266667*limit/100)
6056                 return freq_320;
6057         else if (max_pixclk > 0)
6058                 return 266667;
6059         else
6060                 return 200000;
6061 }
6062
6063 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6064                               int max_pixclk)
6065 {
6066         /*
6067          * FIXME:
6068          * - remove the guardband, it's not needed on BXT
6069          * - set 19.2MHz bypass frequency if there are no active pipes
6070          */
6071         if (max_pixclk > 576000*9/10)
6072                 return 624000;
6073         else if (max_pixclk > 384000*9/10)
6074                 return 576000;
6075         else if (max_pixclk > 288000*9/10)
6076                 return 384000;
6077         else if (max_pixclk > 144000*9/10)
6078                 return 288000;
6079         else
6080                 return 144000;
6081 }
6082
6083 /* Compute the max pixel clock for new configuration. Uses atomic state if
6084  * that's non-NULL, look at current state otherwise. */
6085 static int intel_mode_max_pixclk(struct drm_device *dev,
6086                                  struct drm_atomic_state *state)
6087 {
6088         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6089         struct drm_i915_private *dev_priv = dev->dev_private;
6090         struct drm_crtc *crtc;
6091         struct drm_crtc_state *crtc_state;
6092         unsigned max_pixclk = 0, i;
6093         enum pipe pipe;
6094
6095         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6096                sizeof(intel_state->min_pixclk));
6097
6098         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6099                 int pixclk = 0;
6100
6101                 if (crtc_state->enable)
6102                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6103
6104                 intel_state->min_pixclk[i] = pixclk;
6105         }
6106
6107         if (!intel_state->active_crtcs)
6108                 return 0;
6109
6110         for_each_pipe(dev_priv, pipe)
6111                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6112
6113         return max_pixclk;
6114 }
6115
6116 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6117 {
6118         struct drm_device *dev = state->dev;
6119         struct drm_i915_private *dev_priv = dev->dev_private;
6120         int max_pixclk = intel_mode_max_pixclk(dev, state);
6121         struct intel_atomic_state *intel_state =
6122                 to_intel_atomic_state(state);
6123
6124         if (max_pixclk < 0)
6125                 return max_pixclk;
6126
6127         intel_state->cdclk = intel_state->dev_cdclk =
6128                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6129
6130         if (!intel_state->active_crtcs)
6131                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6132
6133         return 0;
6134 }
6135
6136 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6137 {
6138         struct drm_device *dev = state->dev;
6139         struct drm_i915_private *dev_priv = dev->dev_private;
6140         int max_pixclk = intel_mode_max_pixclk(dev, state);
6141         struct intel_atomic_state *intel_state =
6142                 to_intel_atomic_state(state);
6143
6144         if (max_pixclk < 0)
6145                 return max_pixclk;
6146
6147         intel_state->cdclk = intel_state->dev_cdclk =
6148                 broxton_calc_cdclk(dev_priv, max_pixclk);
6149
6150         if (!intel_state->active_crtcs)
6151                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6152
6153         return 0;
6154 }
6155
6156 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6157 {
6158         unsigned int credits, default_credits;
6159
6160         if (IS_CHERRYVIEW(dev_priv))
6161                 default_credits = PFI_CREDIT(12);
6162         else
6163                 default_credits = PFI_CREDIT(8);
6164
6165         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6166                 /* CHV suggested value is 31 or 63 */
6167                 if (IS_CHERRYVIEW(dev_priv))
6168                         credits = PFI_CREDIT_63;
6169                 else
6170                         credits = PFI_CREDIT(15);
6171         } else {
6172                 credits = default_credits;
6173         }
6174
6175         /*
6176          * WA - write default credits before re-programming
6177          * FIXME: should we also set the resend bit here?
6178          */
6179         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6180                    default_credits);
6181
6182         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6183                    credits | PFI_CREDIT_RESEND);
6184
6185         /*
6186          * FIXME is this guaranteed to clear
6187          * immediately or should we poll for it?
6188          */
6189         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6190 }
6191
6192 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6193 {
6194         struct drm_device *dev = old_state->dev;
6195         struct drm_i915_private *dev_priv = dev->dev_private;
6196         struct intel_atomic_state *old_intel_state =
6197                 to_intel_atomic_state(old_state);
6198         unsigned req_cdclk = old_intel_state->dev_cdclk;
6199
6200         /*
6201          * FIXME: We can end up here with all power domains off, yet
6202          * with a CDCLK frequency other than the minimum. To account
6203          * for this take the PIPE-A power domain, which covers the HW
6204          * blocks needed for the following programming. This can be
6205          * removed once it's guaranteed that we get here either with
6206          * the minimum CDCLK set, or the required power domains
6207          * enabled.
6208          */
6209         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6210
6211         if (IS_CHERRYVIEW(dev))
6212                 cherryview_set_cdclk(dev, req_cdclk);
6213         else
6214                 valleyview_set_cdclk(dev, req_cdclk);
6215
6216         vlv_program_pfi_credits(dev_priv);
6217
6218         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6219 }
6220
6221 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6222 {
6223         struct drm_device *dev = crtc->dev;
6224         struct drm_i915_private *dev_priv = to_i915(dev);
6225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6226         struct intel_encoder *encoder;
6227         int pipe = intel_crtc->pipe;
6228
6229         if (WARN_ON(intel_crtc->active))
6230                 return;
6231
6232         if (intel_crtc->config->has_dp_encoder)
6233                 intel_dp_set_m_n(intel_crtc, M1_N1);
6234
6235         intel_set_pipe_timings(intel_crtc);
6236
6237         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6238                 struct drm_i915_private *dev_priv = dev->dev_private;
6239
6240                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6241                 I915_WRITE(CHV_CANVAS(pipe), 0);
6242         }
6243
6244         i9xx_set_pipeconf(intel_crtc);
6245
6246         intel_crtc->active = true;
6247
6248         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6249
6250         for_each_encoder_on_crtc(dev, crtc, encoder)
6251                 if (encoder->pre_pll_enable)
6252                         encoder->pre_pll_enable(encoder);
6253
6254         if (!intel_crtc->config->has_dsi_encoder) {
6255                 if (IS_CHERRYVIEW(dev)) {
6256                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6257                         chv_enable_pll(intel_crtc, intel_crtc->config);
6258                 } else {
6259                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6260                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6261                 }
6262         }
6263
6264         for_each_encoder_on_crtc(dev, crtc, encoder)
6265                 if (encoder->pre_enable)
6266                         encoder->pre_enable(encoder);
6267
6268         i9xx_pfit_enable(intel_crtc);
6269
6270         intel_crtc_load_lut(crtc);
6271
6272         intel_enable_pipe(intel_crtc);
6273
6274         assert_vblank_disabled(crtc);
6275         drm_crtc_vblank_on(crtc);
6276
6277         for_each_encoder_on_crtc(dev, crtc, encoder)
6278                 encoder->enable(encoder);
6279 }
6280
6281 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6282 {
6283         struct drm_device *dev = crtc->base.dev;
6284         struct drm_i915_private *dev_priv = dev->dev_private;
6285
6286         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6287         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6288 }
6289
6290 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6291 {
6292         struct drm_device *dev = crtc->dev;
6293         struct drm_i915_private *dev_priv = to_i915(dev);
6294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6295         struct intel_encoder *encoder;
6296         int pipe = intel_crtc->pipe;
6297
6298         if (WARN_ON(intel_crtc->active))
6299                 return;
6300
6301         i9xx_set_pll_dividers(intel_crtc);
6302
6303         if (intel_crtc->config->has_dp_encoder)
6304                 intel_dp_set_m_n(intel_crtc, M1_N1);
6305
6306         intel_set_pipe_timings(intel_crtc);
6307
6308         i9xx_set_pipeconf(intel_crtc);
6309
6310         intel_crtc->active = true;
6311
6312         if (!IS_GEN2(dev))
6313                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6314
6315         for_each_encoder_on_crtc(dev, crtc, encoder)
6316                 if (encoder->pre_enable)
6317                         encoder->pre_enable(encoder);
6318
6319         i9xx_enable_pll(intel_crtc);
6320
6321         i9xx_pfit_enable(intel_crtc);
6322
6323         intel_crtc_load_lut(crtc);
6324
6325         intel_update_watermarks(crtc);
6326         intel_enable_pipe(intel_crtc);
6327
6328         assert_vblank_disabled(crtc);
6329         drm_crtc_vblank_on(crtc);
6330
6331         for_each_encoder_on_crtc(dev, crtc, encoder)
6332                 encoder->enable(encoder);
6333
6334         intel_fbc_enable(intel_crtc);
6335 }
6336
6337 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6338 {
6339         struct drm_device *dev = crtc->base.dev;
6340         struct drm_i915_private *dev_priv = dev->dev_private;
6341
6342         if (!crtc->config->gmch_pfit.control)
6343                 return;
6344
6345         assert_pipe_disabled(dev_priv, crtc->pipe);
6346
6347         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6348                          I915_READ(PFIT_CONTROL));
6349         I915_WRITE(PFIT_CONTROL, 0);
6350 }
6351
6352 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6353 {
6354         struct drm_device *dev = crtc->dev;
6355         struct drm_i915_private *dev_priv = dev->dev_private;
6356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6357         struct intel_encoder *encoder;
6358         int pipe = intel_crtc->pipe;
6359
6360         /*
6361          * On gen2 planes are double buffered but the pipe isn't, so we must
6362          * wait for planes to fully turn off before disabling the pipe.
6363          * We also need to wait on all gmch platforms because of the
6364          * self-refresh mode constraint explained above.
6365          */
6366         intel_wait_for_vblank(dev, pipe);
6367
6368         for_each_encoder_on_crtc(dev, crtc, encoder)
6369                 encoder->disable(encoder);
6370
6371         drm_crtc_vblank_off(crtc);
6372         assert_vblank_disabled(crtc);
6373
6374         intel_disable_pipe(intel_crtc);
6375
6376         i9xx_pfit_disable(intel_crtc);
6377
6378         for_each_encoder_on_crtc(dev, crtc, encoder)
6379                 if (encoder->post_disable)
6380                         encoder->post_disable(encoder);
6381
6382         if (!intel_crtc->config->has_dsi_encoder) {
6383                 if (IS_CHERRYVIEW(dev))
6384                         chv_disable_pll(dev_priv, pipe);
6385                 else if (IS_VALLEYVIEW(dev))
6386                         vlv_disable_pll(dev_priv, pipe);
6387                 else
6388                         i9xx_disable_pll(intel_crtc);
6389         }
6390
6391         for_each_encoder_on_crtc(dev, crtc, encoder)
6392                 if (encoder->post_pll_disable)
6393                         encoder->post_pll_disable(encoder);
6394
6395         if (!IS_GEN2(dev))
6396                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6397
6398         intel_fbc_disable_crtc(intel_crtc);
6399 }
6400
6401 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6402 {
6403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6404         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6405         enum intel_display_power_domain domain;
6406         unsigned long domains;
6407
6408         if (!intel_crtc->active)
6409                 return;
6410
6411         if (to_intel_plane_state(crtc->primary->state)->visible) {
6412                 WARN_ON(intel_crtc->unpin_work);
6413
6414                 intel_pre_disable_primary(crtc);
6415
6416                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6417                 to_intel_plane_state(crtc->primary->state)->visible = false;
6418         }
6419
6420         dev_priv->display.crtc_disable(crtc);
6421         intel_crtc->active = false;
6422         intel_update_watermarks(crtc);
6423         intel_disable_shared_dpll(intel_crtc);
6424
6425         domains = intel_crtc->enabled_power_domains;
6426         for_each_power_domain(domain, domains)
6427                 intel_display_power_put(dev_priv, domain);
6428         intel_crtc->enabled_power_domains = 0;
6429
6430         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6431         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6432 }
6433
6434 /*
6435  * turn all crtc's off, but do not adjust state
6436  * This has to be paired with a call to intel_modeset_setup_hw_state.
6437  */
6438 int intel_display_suspend(struct drm_device *dev)
6439 {
6440         struct drm_mode_config *config = &dev->mode_config;
6441         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6442         struct drm_atomic_state *state;
6443         struct drm_crtc *crtc;
6444         unsigned crtc_mask = 0;
6445         int ret = 0;
6446
6447         if (WARN_ON(!ctx))
6448                 return 0;
6449
6450         lockdep_assert_held(&ctx->ww_ctx);
6451         state = drm_atomic_state_alloc(dev);
6452         if (WARN_ON(!state))
6453                 return -ENOMEM;
6454
6455         state->acquire_ctx = ctx;
6456         state->allow_modeset = true;
6457
6458         for_each_crtc(dev, crtc) {
6459                 struct drm_crtc_state *crtc_state =
6460                         drm_atomic_get_crtc_state(state, crtc);
6461
6462                 ret = PTR_ERR_OR_ZERO(crtc_state);
6463                 if (ret)
6464                         goto free;
6465
6466                 if (!crtc_state->active)
6467                         continue;
6468
6469                 crtc_state->active = false;
6470                 crtc_mask |= 1 << drm_crtc_index(crtc);
6471         }
6472
6473         if (crtc_mask) {
6474                 ret = drm_atomic_commit(state);
6475
6476                 if (!ret) {
6477                         for_each_crtc(dev, crtc)
6478                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6479                                         crtc->state->active = true;
6480
6481                         return ret;
6482                 }
6483         }
6484
6485 free:
6486         if (ret)
6487                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6488         drm_atomic_state_free(state);
6489         return ret;
6490 }
6491
6492 void intel_encoder_destroy(struct drm_encoder *encoder)
6493 {
6494         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6495
6496         drm_encoder_cleanup(encoder);
6497         kfree(intel_encoder);
6498 }
6499
6500 /* Cross check the actual hw state with our own modeset state tracking (and it's
6501  * internal consistency). */
6502 static void intel_connector_check_state(struct intel_connector *connector)
6503 {
6504         struct drm_crtc *crtc = connector->base.state->crtc;
6505
6506         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6507                       connector->base.base.id,
6508                       connector->base.name);
6509
6510         if (connector->get_hw_state(connector)) {
6511                 struct intel_encoder *encoder = connector->encoder;
6512                 struct drm_connector_state *conn_state = connector->base.state;
6513
6514                 I915_STATE_WARN(!crtc,
6515                          "connector enabled without attached crtc\n");
6516
6517                 if (!crtc)
6518                         return;
6519
6520                 I915_STATE_WARN(!crtc->state->active,
6521                       "connector is active, but attached crtc isn't\n");
6522
6523                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6524                         return;
6525
6526                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6527                         "atomic encoder doesn't match attached encoder\n");
6528
6529                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6530                         "attached encoder crtc differs from connector crtc\n");
6531         } else {
6532                 I915_STATE_WARN(crtc && crtc->state->active,
6533                         "attached crtc is active, but connector isn't\n");
6534                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6535                         "best encoder set without crtc!\n");
6536         }
6537 }
6538
6539 int intel_connector_init(struct intel_connector *connector)
6540 {
6541         struct drm_connector_state *connector_state;
6542
6543         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6544         if (!connector_state)
6545                 return -ENOMEM;
6546
6547         connector->base.state = connector_state;
6548         return 0;
6549 }
6550
6551 struct intel_connector *intel_connector_alloc(void)
6552 {
6553         struct intel_connector *connector;
6554
6555         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6556         if (!connector)
6557                 return NULL;
6558
6559         if (intel_connector_init(connector) < 0) {
6560                 kfree(connector);
6561                 return NULL;
6562         }
6563
6564         return connector;
6565 }
6566
6567 /* Simple connector->get_hw_state implementation for encoders that support only
6568  * one connector and no cloning and hence the encoder state determines the state
6569  * of the connector. */
6570 bool intel_connector_get_hw_state(struct intel_connector *connector)
6571 {
6572         enum pipe pipe = 0;
6573         struct intel_encoder *encoder = connector->encoder;
6574
6575         return encoder->get_hw_state(encoder, &pipe);
6576 }
6577
6578 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6579 {
6580         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6581                 return crtc_state->fdi_lanes;
6582
6583         return 0;
6584 }
6585
6586 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6587                                      struct intel_crtc_state *pipe_config)
6588 {
6589         struct drm_atomic_state *state = pipe_config->base.state;
6590         struct intel_crtc *other_crtc;
6591         struct intel_crtc_state *other_crtc_state;
6592
6593         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6594                       pipe_name(pipe), pipe_config->fdi_lanes);
6595         if (pipe_config->fdi_lanes > 4) {
6596                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6597                               pipe_name(pipe), pipe_config->fdi_lanes);
6598                 return -EINVAL;
6599         }
6600
6601         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6602                 if (pipe_config->fdi_lanes > 2) {
6603                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6604                                       pipe_config->fdi_lanes);
6605                         return -EINVAL;
6606                 } else {
6607                         return 0;
6608                 }
6609         }
6610
6611         if (INTEL_INFO(dev)->num_pipes == 2)
6612                 return 0;
6613
6614         /* Ivybridge 3 pipe is really complicated */
6615         switch (pipe) {
6616         case PIPE_A:
6617                 return 0;
6618         case PIPE_B:
6619                 if (pipe_config->fdi_lanes <= 2)
6620                         return 0;
6621
6622                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6623                 other_crtc_state =
6624                         intel_atomic_get_crtc_state(state, other_crtc);
6625                 if (IS_ERR(other_crtc_state))
6626                         return PTR_ERR(other_crtc_state);
6627
6628                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6629                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6630                                       pipe_name(pipe), pipe_config->fdi_lanes);
6631                         return -EINVAL;
6632                 }
6633                 return 0;
6634         case PIPE_C:
6635                 if (pipe_config->fdi_lanes > 2) {
6636                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6637                                       pipe_name(pipe), pipe_config->fdi_lanes);
6638                         return -EINVAL;
6639                 }
6640
6641                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6642                 other_crtc_state =
6643                         intel_atomic_get_crtc_state(state, other_crtc);
6644                 if (IS_ERR(other_crtc_state))
6645                         return PTR_ERR(other_crtc_state);
6646
6647                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6648                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6649                         return -EINVAL;
6650                 }
6651                 return 0;
6652         default:
6653                 BUG();
6654         }
6655 }
6656
6657 #define RETRY 1
6658 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6659                                        struct intel_crtc_state *pipe_config)
6660 {
6661         struct drm_device *dev = intel_crtc->base.dev;
6662         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6663         int lane, link_bw, fdi_dotclock, ret;
6664         bool needs_recompute = false;
6665
6666 retry:
6667         /* FDI is a binary signal running at ~2.7GHz, encoding
6668          * each output octet as 10 bits. The actual frequency
6669          * is stored as a divider into a 100MHz clock, and the
6670          * mode pixel clock is stored in units of 1KHz.
6671          * Hence the bw of each lane in terms of the mode signal
6672          * is:
6673          */
6674         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6675
6676         fdi_dotclock = adjusted_mode->crtc_clock;
6677
6678         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6679                                            pipe_config->pipe_bpp);
6680
6681         pipe_config->fdi_lanes = lane;
6682
6683         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6684                                link_bw, &pipe_config->fdi_m_n);
6685
6686         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6687                                        intel_crtc->pipe, pipe_config);
6688         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6689                 pipe_config->pipe_bpp -= 2*3;
6690                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6691                               pipe_config->pipe_bpp);
6692                 needs_recompute = true;
6693                 pipe_config->bw_constrained = true;
6694
6695                 goto retry;
6696         }
6697
6698         if (needs_recompute)
6699                 return RETRY;
6700
6701         return ret;
6702 }
6703
6704 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6705                                      struct intel_crtc_state *pipe_config)
6706 {
6707         if (pipe_config->pipe_bpp > 24)
6708                 return false;
6709
6710         /* HSW can handle pixel rate up to cdclk? */
6711         if (IS_HASWELL(dev_priv->dev))
6712                 return true;
6713
6714         /*
6715          * We compare against max which means we must take
6716          * the increased cdclk requirement into account when
6717          * calculating the new cdclk.
6718          *
6719          * Should measure whether using a lower cdclk w/o IPS
6720          */
6721         return ilk_pipe_pixel_rate(pipe_config) <=
6722                 dev_priv->max_cdclk_freq * 95 / 100;
6723 }
6724
6725 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6726                                    struct intel_crtc_state *pipe_config)
6727 {
6728         struct drm_device *dev = crtc->base.dev;
6729         struct drm_i915_private *dev_priv = dev->dev_private;
6730
6731         pipe_config->ips_enabled = i915.enable_ips &&
6732                 hsw_crtc_supports_ips(crtc) &&
6733                 pipe_config_supports_ips(dev_priv, pipe_config);
6734 }
6735
6736 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6737 {
6738         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6739
6740         /* GDG double wide on either pipe, otherwise pipe A only */
6741         return INTEL_INFO(dev_priv)->gen < 4 &&
6742                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6743 }
6744
6745 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6746                                      struct intel_crtc_state *pipe_config)
6747 {
6748         struct drm_device *dev = crtc->base.dev;
6749         struct drm_i915_private *dev_priv = dev->dev_private;
6750         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6751
6752         /* FIXME should check pixel clock limits on all platforms */
6753         if (INTEL_INFO(dev)->gen < 4) {
6754                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6755
6756                 /*
6757                  * Enable double wide mode when the dot clock
6758                  * is > 90% of the (display) core speed.
6759                  */
6760                 if (intel_crtc_supports_double_wide(crtc) &&
6761                     adjusted_mode->crtc_clock > clock_limit) {
6762                         clock_limit *= 2;
6763                         pipe_config->double_wide = true;
6764                 }
6765
6766                 if (adjusted_mode->crtc_clock > clock_limit) {
6767                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6768                                       adjusted_mode->crtc_clock, clock_limit,
6769                                       yesno(pipe_config->double_wide));
6770                         return -EINVAL;
6771                 }
6772         }
6773
6774         /*
6775          * Pipe horizontal size must be even in:
6776          * - DVO ganged mode
6777          * - LVDS dual channel mode
6778          * - Double wide pipe
6779          */
6780         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6781              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6782                 pipe_config->pipe_src_w &= ~1;
6783
6784         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6785          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6786          */
6787         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6788                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6789                 return -EINVAL;
6790
6791         if (HAS_IPS(dev))
6792                 hsw_compute_ips_config(crtc, pipe_config);
6793
6794         if (pipe_config->has_pch_encoder)
6795                 return ironlake_fdi_compute_config(crtc, pipe_config);
6796
6797         return 0;
6798 }
6799
6800 static int skylake_get_display_clock_speed(struct drm_device *dev)
6801 {
6802         struct drm_i915_private *dev_priv = to_i915(dev);
6803         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6804         uint32_t cdctl = I915_READ(CDCLK_CTL);
6805         uint32_t linkrate;
6806
6807         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6808                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6809
6810         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6811                 return 540000;
6812
6813         linkrate = (I915_READ(DPLL_CTRL1) &
6814                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6815
6816         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6817             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6818                 /* vco 8640 */
6819                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6820                 case CDCLK_FREQ_450_432:
6821                         return 432000;
6822                 case CDCLK_FREQ_337_308:
6823                         return 308570;
6824                 case CDCLK_FREQ_675_617:
6825                         return 617140;
6826                 default:
6827                         WARN(1, "Unknown cd freq selection\n");
6828                 }
6829         } else {
6830                 /* vco 8100 */
6831                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6832                 case CDCLK_FREQ_450_432:
6833                         return 450000;
6834                 case CDCLK_FREQ_337_308:
6835                         return 337500;
6836                 case CDCLK_FREQ_675_617:
6837                         return 675000;
6838                 default:
6839                         WARN(1, "Unknown cd freq selection\n");
6840                 }
6841         }
6842
6843         /* error case, do as if DPLL0 isn't enabled */
6844         return 24000;
6845 }
6846
6847 static int broxton_get_display_clock_speed(struct drm_device *dev)
6848 {
6849         struct drm_i915_private *dev_priv = to_i915(dev);
6850         uint32_t cdctl = I915_READ(CDCLK_CTL);
6851         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6852         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6853         int cdclk;
6854
6855         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6856                 return 19200;
6857
6858         cdclk = 19200 * pll_ratio / 2;
6859
6860         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6861         case BXT_CDCLK_CD2X_DIV_SEL_1:
6862                 return cdclk;  /* 576MHz or 624MHz */
6863         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6864                 return cdclk * 2 / 3; /* 384MHz */
6865         case BXT_CDCLK_CD2X_DIV_SEL_2:
6866                 return cdclk / 2; /* 288MHz */
6867         case BXT_CDCLK_CD2X_DIV_SEL_4:
6868                 return cdclk / 4; /* 144MHz */
6869         }
6870
6871         /* error case, do as if DE PLL isn't enabled */
6872         return 19200;
6873 }
6874
6875 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6876 {
6877         struct drm_i915_private *dev_priv = dev->dev_private;
6878         uint32_t lcpll = I915_READ(LCPLL_CTL);
6879         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6880
6881         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6882                 return 800000;
6883         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6884                 return 450000;
6885         else if (freq == LCPLL_CLK_FREQ_450)
6886                 return 450000;
6887         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6888                 return 540000;
6889         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6890                 return 337500;
6891         else
6892                 return 675000;
6893 }
6894
6895 static int haswell_get_display_clock_speed(struct drm_device *dev)
6896 {
6897         struct drm_i915_private *dev_priv = dev->dev_private;
6898         uint32_t lcpll = I915_READ(LCPLL_CTL);
6899         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6900
6901         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6902                 return 800000;
6903         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6904                 return 450000;
6905         else if (freq == LCPLL_CLK_FREQ_450)
6906                 return 450000;
6907         else if (IS_HSW_ULT(dev))
6908                 return 337500;
6909         else
6910                 return 540000;
6911 }
6912
6913 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6914 {
6915         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6916                                       CCK_DISPLAY_CLOCK_CONTROL);
6917 }
6918
6919 static int ilk_get_display_clock_speed(struct drm_device *dev)
6920 {
6921         return 450000;
6922 }
6923
6924 static int i945_get_display_clock_speed(struct drm_device *dev)
6925 {
6926         return 400000;
6927 }
6928
6929 static int i915_get_display_clock_speed(struct drm_device *dev)
6930 {
6931         return 333333;
6932 }
6933
6934 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6935 {
6936         return 200000;
6937 }
6938
6939 static int pnv_get_display_clock_speed(struct drm_device *dev)
6940 {
6941         u16 gcfgc = 0;
6942
6943         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6944
6945         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6946         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6947                 return 266667;
6948         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6949                 return 333333;
6950         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6951                 return 444444;
6952         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6953                 return 200000;
6954         default:
6955                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6956         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6957                 return 133333;
6958         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6959                 return 166667;
6960         }
6961 }
6962
6963 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6964 {
6965         u16 gcfgc = 0;
6966
6967         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6968
6969         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6970                 return 133333;
6971         else {
6972                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6973                 case GC_DISPLAY_CLOCK_333_MHZ:
6974                         return 333333;
6975                 default:
6976                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6977                         return 190000;
6978                 }
6979         }
6980 }
6981
6982 static int i865_get_display_clock_speed(struct drm_device *dev)
6983 {
6984         return 266667;
6985 }
6986
6987 static int i85x_get_display_clock_speed(struct drm_device *dev)
6988 {
6989         u16 hpllcc = 0;
6990
6991         /*
6992          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6993          * encoding is different :(
6994          * FIXME is this the right way to detect 852GM/852GMV?
6995          */
6996         if (dev->pdev->revision == 0x1)
6997                 return 133333;
6998
6999         pci_bus_read_config_word(dev->pdev->bus,
7000                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7001
7002         /* Assume that the hardware is in the high speed state.  This
7003          * should be the default.
7004          */
7005         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7006         case GC_CLOCK_133_200:
7007         case GC_CLOCK_133_200_2:
7008         case GC_CLOCK_100_200:
7009                 return 200000;
7010         case GC_CLOCK_166_250:
7011                 return 250000;
7012         case GC_CLOCK_100_133:
7013                 return 133333;
7014         case GC_CLOCK_133_266:
7015         case GC_CLOCK_133_266_2:
7016         case GC_CLOCK_166_266:
7017                 return 266667;
7018         }
7019
7020         /* Shouldn't happen */
7021         return 0;
7022 }
7023
7024 static int i830_get_display_clock_speed(struct drm_device *dev)
7025 {
7026         return 133333;
7027 }
7028
7029 static unsigned int intel_hpll_vco(struct drm_device *dev)
7030 {
7031         struct drm_i915_private *dev_priv = dev->dev_private;
7032         static const unsigned int blb_vco[8] = {
7033                 [0] = 3200000,
7034                 [1] = 4000000,
7035                 [2] = 5333333,
7036                 [3] = 4800000,
7037                 [4] = 6400000,
7038         };
7039         static const unsigned int pnv_vco[8] = {
7040                 [0] = 3200000,
7041                 [1] = 4000000,
7042                 [2] = 5333333,
7043                 [3] = 4800000,
7044                 [4] = 2666667,
7045         };
7046         static const unsigned int cl_vco[8] = {
7047                 [0] = 3200000,
7048                 [1] = 4000000,
7049                 [2] = 5333333,
7050                 [3] = 6400000,
7051                 [4] = 3333333,
7052                 [5] = 3566667,
7053                 [6] = 4266667,
7054         };
7055         static const unsigned int elk_vco[8] = {
7056                 [0] = 3200000,
7057                 [1] = 4000000,
7058                 [2] = 5333333,
7059                 [3] = 4800000,
7060         };
7061         static const unsigned int ctg_vco[8] = {
7062                 [0] = 3200000,
7063                 [1] = 4000000,
7064                 [2] = 5333333,
7065                 [3] = 6400000,
7066                 [4] = 2666667,
7067                 [5] = 4266667,
7068         };
7069         const unsigned int *vco_table;
7070         unsigned int vco;
7071         uint8_t tmp = 0;
7072
7073         /* FIXME other chipsets? */
7074         if (IS_GM45(dev))
7075                 vco_table = ctg_vco;
7076         else if (IS_G4X(dev))
7077                 vco_table = elk_vco;
7078         else if (IS_CRESTLINE(dev))
7079                 vco_table = cl_vco;
7080         else if (IS_PINEVIEW(dev))
7081                 vco_table = pnv_vco;
7082         else if (IS_G33(dev))
7083                 vco_table = blb_vco;
7084         else
7085                 return 0;
7086
7087         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7088
7089         vco = vco_table[tmp & 0x7];
7090         if (vco == 0)
7091                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7092         else
7093                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7094
7095         return vco;
7096 }
7097
7098 static int gm45_get_display_clock_speed(struct drm_device *dev)
7099 {
7100         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7101         uint16_t tmp = 0;
7102
7103         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7104
7105         cdclk_sel = (tmp >> 12) & 0x1;
7106
7107         switch (vco) {
7108         case 2666667:
7109         case 4000000:
7110         case 5333333:
7111                 return cdclk_sel ? 333333 : 222222;
7112         case 3200000:
7113                 return cdclk_sel ? 320000 : 228571;
7114         default:
7115                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7116                 return 222222;
7117         }
7118 }
7119
7120 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7121 {
7122         static const uint8_t div_3200[] = { 16, 10,  8 };
7123         static const uint8_t div_4000[] = { 20, 12, 10 };
7124         static const uint8_t div_5333[] = { 24, 16, 14 };
7125         const uint8_t *div_table;
7126         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7127         uint16_t tmp = 0;
7128
7129         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7130
7131         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7132
7133         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7134                 goto fail;
7135
7136         switch (vco) {
7137         case 3200000:
7138                 div_table = div_3200;
7139                 break;
7140         case 4000000:
7141                 div_table = div_4000;
7142                 break;
7143         case 5333333:
7144                 div_table = div_5333;
7145                 break;
7146         default:
7147                 goto fail;
7148         }
7149
7150         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7151
7152 fail:
7153         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7154         return 200000;
7155 }
7156
7157 static int g33_get_display_clock_speed(struct drm_device *dev)
7158 {
7159         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7160         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7161         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7162         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7163         const uint8_t *div_table;
7164         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7165         uint16_t tmp = 0;
7166
7167         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7168
7169         cdclk_sel = (tmp >> 4) & 0x7;
7170
7171         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7172                 goto fail;
7173
7174         switch (vco) {
7175         case 3200000:
7176                 div_table = div_3200;
7177                 break;
7178         case 4000000:
7179                 div_table = div_4000;
7180                 break;
7181         case 4800000:
7182                 div_table = div_4800;
7183                 break;
7184         case 5333333:
7185                 div_table = div_5333;
7186                 break;
7187         default:
7188                 goto fail;
7189         }
7190
7191         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7192
7193 fail:
7194         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7195         return 190476;
7196 }
7197
7198 static void
7199 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7200 {
7201         while (*num > DATA_LINK_M_N_MASK ||
7202                *den > DATA_LINK_M_N_MASK) {
7203                 *num >>= 1;
7204                 *den >>= 1;
7205         }
7206 }
7207
7208 static void compute_m_n(unsigned int m, unsigned int n,
7209                         uint32_t *ret_m, uint32_t *ret_n)
7210 {
7211         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7212         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7213         intel_reduce_m_n_ratio(ret_m, ret_n);
7214 }
7215
7216 void
7217 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7218                        int pixel_clock, int link_clock,
7219                        struct intel_link_m_n *m_n)
7220 {
7221         m_n->tu = 64;
7222
7223         compute_m_n(bits_per_pixel * pixel_clock,
7224                     link_clock * nlanes * 8,
7225                     &m_n->gmch_m, &m_n->gmch_n);
7226
7227         compute_m_n(pixel_clock, link_clock,
7228                     &m_n->link_m, &m_n->link_n);
7229 }
7230
7231 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7232 {
7233         if (i915.panel_use_ssc >= 0)
7234                 return i915.panel_use_ssc != 0;
7235         return dev_priv->vbt.lvds_use_ssc
7236                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7237 }
7238
7239 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7240                            int num_connectors)
7241 {
7242         struct drm_device *dev = crtc_state->base.crtc->dev;
7243         struct drm_i915_private *dev_priv = dev->dev_private;
7244         int refclk;
7245
7246         WARN_ON(!crtc_state->base.state);
7247
7248         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7249                 refclk = 100000;
7250         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7251             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7252                 refclk = dev_priv->vbt.lvds_ssc_freq;
7253                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7254         } else if (!IS_GEN2(dev)) {
7255                 refclk = 96000;
7256         } else {
7257                 refclk = 48000;
7258         }
7259
7260         return refclk;
7261 }
7262
7263 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7264 {
7265         return (1 << dpll->n) << 16 | dpll->m2;
7266 }
7267
7268 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7269 {
7270         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7271 }
7272
7273 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7274                                      struct intel_crtc_state *crtc_state,
7275                                      intel_clock_t *reduced_clock)
7276 {
7277         struct drm_device *dev = crtc->base.dev;
7278         u32 fp, fp2 = 0;
7279
7280         if (IS_PINEVIEW(dev)) {
7281                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7282                 if (reduced_clock)
7283                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7284         } else {
7285                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7286                 if (reduced_clock)
7287                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7288         }
7289
7290         crtc_state->dpll_hw_state.fp0 = fp;
7291
7292         crtc->lowfreq_avail = false;
7293         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7294             reduced_clock) {
7295                 crtc_state->dpll_hw_state.fp1 = fp2;
7296                 crtc->lowfreq_avail = true;
7297         } else {
7298                 crtc_state->dpll_hw_state.fp1 = fp;
7299         }
7300 }
7301
7302 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7303                 pipe)
7304 {
7305         u32 reg_val;
7306
7307         /*
7308          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7309          * and set it to a reasonable value instead.
7310          */
7311         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7312         reg_val &= 0xffffff00;
7313         reg_val |= 0x00000030;
7314         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7315
7316         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7317         reg_val &= 0x8cffffff;
7318         reg_val = 0x8c000000;
7319         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7320
7321         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7322         reg_val &= 0xffffff00;
7323         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7324
7325         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7326         reg_val &= 0x00ffffff;
7327         reg_val |= 0xb0000000;
7328         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7329 }
7330
7331 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7332                                          struct intel_link_m_n *m_n)
7333 {
7334         struct drm_device *dev = crtc->base.dev;
7335         struct drm_i915_private *dev_priv = dev->dev_private;
7336         int pipe = crtc->pipe;
7337
7338         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7339         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7340         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7341         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7342 }
7343
7344 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7345                                          struct intel_link_m_n *m_n,
7346                                          struct intel_link_m_n *m2_n2)
7347 {
7348         struct drm_device *dev = crtc->base.dev;
7349         struct drm_i915_private *dev_priv = dev->dev_private;
7350         int pipe = crtc->pipe;
7351         enum transcoder transcoder = crtc->config->cpu_transcoder;
7352
7353         if (INTEL_INFO(dev)->gen >= 5) {
7354                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7355                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7356                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7357                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7358                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7359                  * for gen < 8) and if DRRS is supported (to make sure the
7360                  * registers are not unnecessarily accessed).
7361                  */
7362                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7363                         crtc->config->has_drrs) {
7364                         I915_WRITE(PIPE_DATA_M2(transcoder),
7365                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7366                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7367                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7368                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7369                 }
7370         } else {
7371                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7372                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7373                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7374                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7375         }
7376 }
7377
7378 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7379 {
7380         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7381
7382         if (m_n == M1_N1) {
7383                 dp_m_n = &crtc->config->dp_m_n;
7384                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7385         } else if (m_n == M2_N2) {
7386
7387                 /*
7388                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7389                  * needs to be programmed into M1_N1.
7390                  */
7391                 dp_m_n = &crtc->config->dp_m2_n2;
7392         } else {
7393                 DRM_ERROR("Unsupported divider value\n");
7394                 return;
7395         }
7396
7397         if (crtc->config->has_pch_encoder)
7398                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7399         else
7400                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7401 }
7402
7403 static void vlv_compute_dpll(struct intel_crtc *crtc,
7404                              struct intel_crtc_state *pipe_config)
7405 {
7406         u32 dpll, dpll_md;
7407
7408         /*
7409          * Enable DPIO clock input. We should never disable the reference
7410          * clock for pipe B, since VGA hotplug / manual detection depends
7411          * on it.
7412          */
7413         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7414                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7415         /* We should never disable this, set it here for state tracking */
7416         if (crtc->pipe == PIPE_B)
7417                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7418         dpll |= DPLL_VCO_ENABLE;
7419         pipe_config->dpll_hw_state.dpll = dpll;
7420
7421         dpll_md = (pipe_config->pixel_multiplier - 1)
7422                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7423         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7424 }
7425
7426 static void vlv_prepare_pll(struct intel_crtc *crtc,
7427                             const struct intel_crtc_state *pipe_config)
7428 {
7429         struct drm_device *dev = crtc->base.dev;
7430         struct drm_i915_private *dev_priv = dev->dev_private;
7431         int pipe = crtc->pipe;
7432         u32 mdiv;
7433         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7434         u32 coreclk, reg_val;
7435
7436         mutex_lock(&dev_priv->sb_lock);
7437
7438         bestn = pipe_config->dpll.n;
7439         bestm1 = pipe_config->dpll.m1;
7440         bestm2 = pipe_config->dpll.m2;
7441         bestp1 = pipe_config->dpll.p1;
7442         bestp2 = pipe_config->dpll.p2;
7443
7444         /* See eDP HDMI DPIO driver vbios notes doc */
7445
7446         /* PLL B needs special handling */
7447         if (pipe == PIPE_B)
7448                 vlv_pllb_recal_opamp(dev_priv, pipe);
7449
7450         /* Set up Tx target for periodic Rcomp update */
7451         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7452
7453         /* Disable target IRef on PLL */
7454         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7455         reg_val &= 0x00ffffff;
7456         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7457
7458         /* Disable fast lock */
7459         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7460
7461         /* Set idtafcrecal before PLL is enabled */
7462         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7463         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7464         mdiv |= ((bestn << DPIO_N_SHIFT));
7465         mdiv |= (1 << DPIO_K_SHIFT);
7466
7467         /*
7468          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7469          * but we don't support that).
7470          * Note: don't use the DAC post divider as it seems unstable.
7471          */
7472         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7473         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7474
7475         mdiv |= DPIO_ENABLE_CALIBRATION;
7476         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7477
7478         /* Set HBR and RBR LPF coefficients */
7479         if (pipe_config->port_clock == 162000 ||
7480             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7481             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7482                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7483                                  0x009f0003);
7484         else
7485                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7486                                  0x00d0000f);
7487
7488         if (pipe_config->has_dp_encoder) {
7489                 /* Use SSC source */
7490                 if (pipe == PIPE_A)
7491                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7492                                          0x0df40000);
7493                 else
7494                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7495                                          0x0df70000);
7496         } else { /* HDMI or VGA */
7497                 /* Use bend source */
7498                 if (pipe == PIPE_A)
7499                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7500                                          0x0df70000);
7501                 else
7502                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7503                                          0x0df40000);
7504         }
7505
7506         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7507         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7508         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7509             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7510                 coreclk |= 0x01000000;
7511         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7512
7513         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7514         mutex_unlock(&dev_priv->sb_lock);
7515 }
7516
7517 static void chv_compute_dpll(struct intel_crtc *crtc,
7518                              struct intel_crtc_state *pipe_config)
7519 {
7520         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7521                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7522                 DPLL_VCO_ENABLE;
7523         if (crtc->pipe != PIPE_A)
7524                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7525
7526         pipe_config->dpll_hw_state.dpll_md =
7527                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7528 }
7529
7530 static void chv_prepare_pll(struct intel_crtc *crtc,
7531                             const struct intel_crtc_state *pipe_config)
7532 {
7533         struct drm_device *dev = crtc->base.dev;
7534         struct drm_i915_private *dev_priv = dev->dev_private;
7535         int pipe = crtc->pipe;
7536         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7537         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7538         u32 loopfilter, tribuf_calcntr;
7539         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7540         u32 dpio_val;
7541         int vco;
7542
7543         bestn = pipe_config->dpll.n;
7544         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7545         bestm1 = pipe_config->dpll.m1;
7546         bestm2 = pipe_config->dpll.m2 >> 22;
7547         bestp1 = pipe_config->dpll.p1;
7548         bestp2 = pipe_config->dpll.p2;
7549         vco = pipe_config->dpll.vco;
7550         dpio_val = 0;
7551         loopfilter = 0;
7552
7553         /*
7554          * Enable Refclk and SSC
7555          */
7556         I915_WRITE(dpll_reg,
7557                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7558
7559         mutex_lock(&dev_priv->sb_lock);
7560
7561         /* p1 and p2 divider */
7562         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7563                         5 << DPIO_CHV_S1_DIV_SHIFT |
7564                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7565                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7566                         1 << DPIO_CHV_K_DIV_SHIFT);
7567
7568         /* Feedback post-divider - m2 */
7569         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7570
7571         /* Feedback refclk divider - n and m1 */
7572         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7573                         DPIO_CHV_M1_DIV_BY_2 |
7574                         1 << DPIO_CHV_N_DIV_SHIFT);
7575
7576         /* M2 fraction division */
7577         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7578
7579         /* M2 fraction division enable */
7580         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7581         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7582         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7583         if (bestm2_frac)
7584                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7585         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7586
7587         /* Program digital lock detect threshold */
7588         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7589         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7590                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7591         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7592         if (!bestm2_frac)
7593                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7594         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7595
7596         /* Loop filter */
7597         if (vco == 5400000) {
7598                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7599                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7600                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7601                 tribuf_calcntr = 0x9;
7602         } else if (vco <= 6200000) {
7603                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7604                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7605                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7606                 tribuf_calcntr = 0x9;
7607         } else if (vco <= 6480000) {
7608                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7609                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7610                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7611                 tribuf_calcntr = 0x8;
7612         } else {
7613                 /* Not supported. Apply the same limits as in the max case */
7614                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7615                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7616                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7617                 tribuf_calcntr = 0;
7618         }
7619         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7620
7621         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7622         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7623         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7624         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7625
7626         /* AFC Recal */
7627         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7628                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7629                         DPIO_AFC_RECAL);
7630
7631         mutex_unlock(&dev_priv->sb_lock);
7632 }
7633
7634 /**
7635  * vlv_force_pll_on - forcibly enable just the PLL
7636  * @dev_priv: i915 private structure
7637  * @pipe: pipe PLL to enable
7638  * @dpll: PLL configuration
7639  *
7640  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7641  * in cases where we need the PLL enabled even when @pipe is not going to
7642  * be enabled.
7643  */
7644 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7645                       const struct dpll *dpll)
7646 {
7647         struct intel_crtc *crtc =
7648                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7649         struct intel_crtc_state pipe_config = {
7650                 .base.crtc = &crtc->base,
7651                 .pixel_multiplier = 1,
7652                 .dpll = *dpll,
7653         };
7654
7655         if (IS_CHERRYVIEW(dev)) {
7656                 chv_compute_dpll(crtc, &pipe_config);
7657                 chv_prepare_pll(crtc, &pipe_config);
7658                 chv_enable_pll(crtc, &pipe_config);
7659         } else {
7660                 vlv_compute_dpll(crtc, &pipe_config);
7661                 vlv_prepare_pll(crtc, &pipe_config);
7662                 vlv_enable_pll(crtc, &pipe_config);
7663         }
7664 }
7665
7666 /**
7667  * vlv_force_pll_off - forcibly disable just the PLL
7668  * @dev_priv: i915 private structure
7669  * @pipe: pipe PLL to disable
7670  *
7671  * Disable the PLL for @pipe. To be used in cases where we need
7672  * the PLL enabled even when @pipe is not going to be enabled.
7673  */
7674 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7675 {
7676         if (IS_CHERRYVIEW(dev))
7677                 chv_disable_pll(to_i915(dev), pipe);
7678         else
7679                 vlv_disable_pll(to_i915(dev), pipe);
7680 }
7681
7682 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7683                               struct intel_crtc_state *crtc_state,
7684                               intel_clock_t *reduced_clock,
7685                               int num_connectors)
7686 {
7687         struct drm_device *dev = crtc->base.dev;
7688         struct drm_i915_private *dev_priv = dev->dev_private;
7689         u32 dpll;
7690         bool is_sdvo;
7691         struct dpll *clock = &crtc_state->dpll;
7692
7693         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7694
7695         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7696                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7697
7698         dpll = DPLL_VGA_MODE_DIS;
7699
7700         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7701                 dpll |= DPLLB_MODE_LVDS;
7702         else
7703                 dpll |= DPLLB_MODE_DAC_SERIAL;
7704
7705         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7706                 dpll |= (crtc_state->pixel_multiplier - 1)
7707                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7708         }
7709
7710         if (is_sdvo)
7711                 dpll |= DPLL_SDVO_HIGH_SPEED;
7712
7713         if (crtc_state->has_dp_encoder)
7714                 dpll |= DPLL_SDVO_HIGH_SPEED;
7715
7716         /* compute bitmask from p1 value */
7717         if (IS_PINEVIEW(dev))
7718                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7719         else {
7720                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7721                 if (IS_G4X(dev) && reduced_clock)
7722                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7723         }
7724         switch (clock->p2) {
7725         case 5:
7726                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7727                 break;
7728         case 7:
7729                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7730                 break;
7731         case 10:
7732                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7733                 break;
7734         case 14:
7735                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7736                 break;
7737         }
7738         if (INTEL_INFO(dev)->gen >= 4)
7739                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7740
7741         if (crtc_state->sdvo_tv_clock)
7742                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7743         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7744                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7745                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7746         else
7747                 dpll |= PLL_REF_INPUT_DREFCLK;
7748
7749         dpll |= DPLL_VCO_ENABLE;
7750         crtc_state->dpll_hw_state.dpll = dpll;
7751
7752         if (INTEL_INFO(dev)->gen >= 4) {
7753                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7754                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7755                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7756         }
7757 }
7758
7759 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7760                               struct intel_crtc_state *crtc_state,
7761                               intel_clock_t *reduced_clock,
7762                               int num_connectors)
7763 {
7764         struct drm_device *dev = crtc->base.dev;
7765         struct drm_i915_private *dev_priv = dev->dev_private;
7766         u32 dpll;
7767         struct dpll *clock = &crtc_state->dpll;
7768
7769         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7770
7771         dpll = DPLL_VGA_MODE_DIS;
7772
7773         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7774                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7775         } else {
7776                 if (clock->p1 == 2)
7777                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7778                 else
7779                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7780                 if (clock->p2 == 4)
7781                         dpll |= PLL_P2_DIVIDE_BY_4;
7782         }
7783
7784         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7785                 dpll |= DPLL_DVO_2X_MODE;
7786
7787         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7788                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7789                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7790         else
7791                 dpll |= PLL_REF_INPUT_DREFCLK;
7792
7793         dpll |= DPLL_VCO_ENABLE;
7794         crtc_state->dpll_hw_state.dpll = dpll;
7795 }
7796
7797 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7798 {
7799         struct drm_device *dev = intel_crtc->base.dev;
7800         struct drm_i915_private *dev_priv = dev->dev_private;
7801         enum pipe pipe = intel_crtc->pipe;
7802         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7803         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7804         uint32_t crtc_vtotal, crtc_vblank_end;
7805         int vsyncshift = 0;
7806
7807         /* We need to be careful not to changed the adjusted mode, for otherwise
7808          * the hw state checker will get angry at the mismatch. */
7809         crtc_vtotal = adjusted_mode->crtc_vtotal;
7810         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7811
7812         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7813                 /* the chip adds 2 halflines automatically */
7814                 crtc_vtotal -= 1;
7815                 crtc_vblank_end -= 1;
7816
7817                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7818                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7819                 else
7820                         vsyncshift = adjusted_mode->crtc_hsync_start -
7821                                 adjusted_mode->crtc_htotal / 2;
7822                 if (vsyncshift < 0)
7823                         vsyncshift += adjusted_mode->crtc_htotal;
7824         }
7825
7826         if (INTEL_INFO(dev)->gen > 3)
7827                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7828
7829         I915_WRITE(HTOTAL(cpu_transcoder),
7830                    (adjusted_mode->crtc_hdisplay - 1) |
7831                    ((adjusted_mode->crtc_htotal - 1) << 16));
7832         I915_WRITE(HBLANK(cpu_transcoder),
7833                    (adjusted_mode->crtc_hblank_start - 1) |
7834                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7835         I915_WRITE(HSYNC(cpu_transcoder),
7836                    (adjusted_mode->crtc_hsync_start - 1) |
7837                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7838
7839         I915_WRITE(VTOTAL(cpu_transcoder),
7840                    (adjusted_mode->crtc_vdisplay - 1) |
7841                    ((crtc_vtotal - 1) << 16));
7842         I915_WRITE(VBLANK(cpu_transcoder),
7843                    (adjusted_mode->crtc_vblank_start - 1) |
7844                    ((crtc_vblank_end - 1) << 16));
7845         I915_WRITE(VSYNC(cpu_transcoder),
7846                    (adjusted_mode->crtc_vsync_start - 1) |
7847                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7848
7849         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7850          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7851          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7852          * bits. */
7853         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7854             (pipe == PIPE_B || pipe == PIPE_C))
7855                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7856
7857         /* pipesrc controls the size that is scaled from, which should
7858          * always be the user's requested size.
7859          */
7860         I915_WRITE(PIPESRC(pipe),
7861                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7862                    (intel_crtc->config->pipe_src_h - 1));
7863 }
7864
7865 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7866                                    struct intel_crtc_state *pipe_config)
7867 {
7868         struct drm_device *dev = crtc->base.dev;
7869         struct drm_i915_private *dev_priv = dev->dev_private;
7870         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7871         uint32_t tmp;
7872
7873         tmp = I915_READ(HTOTAL(cpu_transcoder));
7874         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7875         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7876         tmp = I915_READ(HBLANK(cpu_transcoder));
7877         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7878         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7879         tmp = I915_READ(HSYNC(cpu_transcoder));
7880         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7881         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7882
7883         tmp = I915_READ(VTOTAL(cpu_transcoder));
7884         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7885         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7886         tmp = I915_READ(VBLANK(cpu_transcoder));
7887         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7888         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7889         tmp = I915_READ(VSYNC(cpu_transcoder));
7890         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7891         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7892
7893         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7894                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7895                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7896                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7897         }
7898
7899         tmp = I915_READ(PIPESRC(crtc->pipe));
7900         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7901         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7902
7903         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7904         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7905 }
7906
7907 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7908                                  struct intel_crtc_state *pipe_config)
7909 {
7910         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7911         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7912         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7913         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7914
7915         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7916         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7917         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7918         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7919
7920         mode->flags = pipe_config->base.adjusted_mode.flags;
7921         mode->type = DRM_MODE_TYPE_DRIVER;
7922
7923         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7924         mode->flags |= pipe_config->base.adjusted_mode.flags;
7925
7926         mode->hsync = drm_mode_hsync(mode);
7927         mode->vrefresh = drm_mode_vrefresh(mode);
7928         drm_mode_set_name(mode);
7929 }
7930
7931 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7932 {
7933         struct drm_device *dev = intel_crtc->base.dev;
7934         struct drm_i915_private *dev_priv = dev->dev_private;
7935         uint32_t pipeconf;
7936
7937         pipeconf = 0;
7938
7939         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7940             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7941                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7942
7943         if (intel_crtc->config->double_wide)
7944                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7945
7946         /* only g4x and later have fancy bpc/dither controls */
7947         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7948                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7949                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7950                         pipeconf |= PIPECONF_DITHER_EN |
7951                                     PIPECONF_DITHER_TYPE_SP;
7952
7953                 switch (intel_crtc->config->pipe_bpp) {
7954                 case 18:
7955                         pipeconf |= PIPECONF_6BPC;
7956                         break;
7957                 case 24:
7958                         pipeconf |= PIPECONF_8BPC;
7959                         break;
7960                 case 30:
7961                         pipeconf |= PIPECONF_10BPC;
7962                         break;
7963                 default:
7964                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7965                         BUG();
7966                 }
7967         }
7968
7969         if (HAS_PIPE_CXSR(dev)) {
7970                 if (intel_crtc->lowfreq_avail) {
7971                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7972                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7973                 } else {
7974                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7975                 }
7976         }
7977
7978         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7979                 if (INTEL_INFO(dev)->gen < 4 ||
7980                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7981                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7982                 else
7983                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7984         } else
7985                 pipeconf |= PIPECONF_PROGRESSIVE;
7986
7987         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7988              intel_crtc->config->limited_color_range)
7989                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7990
7991         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7992         POSTING_READ(PIPECONF(intel_crtc->pipe));
7993 }
7994
7995 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7996                                    struct intel_crtc_state *crtc_state)
7997 {
7998         struct drm_device *dev = crtc->base.dev;
7999         struct drm_i915_private *dev_priv = dev->dev_private;
8000         int refclk, num_connectors = 0;
8001         intel_clock_t clock;
8002         bool ok;
8003         const intel_limit_t *limit;
8004         struct drm_atomic_state *state = crtc_state->base.state;
8005         struct drm_connector *connector;
8006         struct drm_connector_state *connector_state;
8007         int i;
8008
8009         memset(&crtc_state->dpll_hw_state, 0,
8010                sizeof(crtc_state->dpll_hw_state));
8011
8012         if (crtc_state->has_dsi_encoder)
8013                 return 0;
8014
8015         for_each_connector_in_state(state, connector, connector_state, i) {
8016                 if (connector_state->crtc == &crtc->base)
8017                         num_connectors++;
8018         }
8019
8020         if (!crtc_state->clock_set) {
8021                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
8022
8023                 /*
8024                  * Returns a set of divisors for the desired target clock with
8025                  * the given refclk, or FALSE.  The returned values represent
8026                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
8027                  * 2) / p1 / p2.
8028                  */
8029                 limit = intel_limit(crtc_state, refclk);
8030                 ok = dev_priv->display.find_dpll(limit, crtc_state,
8031                                                  crtc_state->port_clock,
8032                                                  refclk, NULL, &clock);
8033                 if (!ok) {
8034                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
8035                         return -EINVAL;
8036                 }
8037
8038                 /* Compat-code for transition, will disappear. */
8039                 crtc_state->dpll.n = clock.n;
8040                 crtc_state->dpll.m1 = clock.m1;
8041                 crtc_state->dpll.m2 = clock.m2;
8042                 crtc_state->dpll.p1 = clock.p1;
8043                 crtc_state->dpll.p2 = clock.p2;
8044         }
8045
8046         if (IS_GEN2(dev)) {
8047                 i8xx_compute_dpll(crtc, crtc_state, NULL,
8048                                   num_connectors);
8049         } else if (IS_CHERRYVIEW(dev)) {
8050                 chv_compute_dpll(crtc, crtc_state);
8051         } else if (IS_VALLEYVIEW(dev)) {
8052                 vlv_compute_dpll(crtc, crtc_state);
8053         } else {
8054                 i9xx_compute_dpll(crtc, crtc_state, NULL,
8055                                   num_connectors);
8056         }
8057
8058         return 0;
8059 }
8060
8061 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8062                                  struct intel_crtc_state *pipe_config)
8063 {
8064         struct drm_device *dev = crtc->base.dev;
8065         struct drm_i915_private *dev_priv = dev->dev_private;
8066         uint32_t tmp;
8067
8068         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8069                 return;
8070
8071         tmp = I915_READ(PFIT_CONTROL);
8072         if (!(tmp & PFIT_ENABLE))
8073                 return;
8074
8075         /* Check whether the pfit is attached to our pipe. */
8076         if (INTEL_INFO(dev)->gen < 4) {
8077                 if (crtc->pipe != PIPE_B)
8078                         return;
8079         } else {
8080                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8081                         return;
8082         }
8083
8084         pipe_config->gmch_pfit.control = tmp;
8085         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8086         if (INTEL_INFO(dev)->gen < 5)
8087                 pipe_config->gmch_pfit.lvds_border_bits =
8088                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8089 }
8090
8091 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8092                                struct intel_crtc_state *pipe_config)
8093 {
8094         struct drm_device *dev = crtc->base.dev;
8095         struct drm_i915_private *dev_priv = dev->dev_private;
8096         int pipe = pipe_config->cpu_transcoder;
8097         intel_clock_t clock;
8098         u32 mdiv;
8099         int refclk = 100000;
8100
8101         /* In case of MIPI DPLL will not even be used */
8102         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8103                 return;
8104
8105         mutex_lock(&dev_priv->sb_lock);
8106         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8107         mutex_unlock(&dev_priv->sb_lock);
8108
8109         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8110         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8111         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8112         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8113         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8114
8115         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8116 }
8117
8118 static void
8119 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8120                               struct intel_initial_plane_config *plane_config)
8121 {
8122         struct drm_device *dev = crtc->base.dev;
8123         struct drm_i915_private *dev_priv = dev->dev_private;
8124         u32 val, base, offset;
8125         int pipe = crtc->pipe, plane = crtc->plane;
8126         int fourcc, pixel_format;
8127         unsigned int aligned_height;
8128         struct drm_framebuffer *fb;
8129         struct intel_framebuffer *intel_fb;
8130
8131         val = I915_READ(DSPCNTR(plane));
8132         if (!(val & DISPLAY_PLANE_ENABLE))
8133                 return;
8134
8135         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8136         if (!intel_fb) {
8137                 DRM_DEBUG_KMS("failed to alloc fb\n");
8138                 return;
8139         }
8140
8141         fb = &intel_fb->base;
8142
8143         if (INTEL_INFO(dev)->gen >= 4) {
8144                 if (val & DISPPLANE_TILED) {
8145                         plane_config->tiling = I915_TILING_X;
8146                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8147                 }
8148         }
8149
8150         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8151         fourcc = i9xx_format_to_fourcc(pixel_format);
8152         fb->pixel_format = fourcc;
8153         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8154
8155         if (INTEL_INFO(dev)->gen >= 4) {
8156                 if (plane_config->tiling)
8157                         offset = I915_READ(DSPTILEOFF(plane));
8158                 else
8159                         offset = I915_READ(DSPLINOFF(plane));
8160                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8161         } else {
8162                 base = I915_READ(DSPADDR(plane));
8163         }
8164         plane_config->base = base;
8165
8166         val = I915_READ(PIPESRC(pipe));
8167         fb->width = ((val >> 16) & 0xfff) + 1;
8168         fb->height = ((val >> 0) & 0xfff) + 1;
8169
8170         val = I915_READ(DSPSTRIDE(pipe));
8171         fb->pitches[0] = val & 0xffffffc0;
8172
8173         aligned_height = intel_fb_align_height(dev, fb->height,
8174                                                fb->pixel_format,
8175                                                fb->modifier[0]);
8176
8177         plane_config->size = fb->pitches[0] * aligned_height;
8178
8179         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8180                       pipe_name(pipe), plane, fb->width, fb->height,
8181                       fb->bits_per_pixel, base, fb->pitches[0],
8182                       plane_config->size);
8183
8184         plane_config->fb = intel_fb;
8185 }
8186
8187 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8188                                struct intel_crtc_state *pipe_config)
8189 {
8190         struct drm_device *dev = crtc->base.dev;
8191         struct drm_i915_private *dev_priv = dev->dev_private;
8192         int pipe = pipe_config->cpu_transcoder;
8193         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8194         intel_clock_t clock;
8195         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8196         int refclk = 100000;
8197
8198         mutex_lock(&dev_priv->sb_lock);
8199         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8200         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8201         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8202         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8203         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8204         mutex_unlock(&dev_priv->sb_lock);
8205
8206         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8207         clock.m2 = (pll_dw0 & 0xff) << 22;
8208         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8209                 clock.m2 |= pll_dw2 & 0x3fffff;
8210         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8211         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8212         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8213
8214         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8215 }
8216
8217 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8218                                  struct intel_crtc_state *pipe_config)
8219 {
8220         struct drm_device *dev = crtc->base.dev;
8221         struct drm_i915_private *dev_priv = dev->dev_private;
8222         uint32_t tmp;
8223
8224         if (!intel_display_power_is_enabled(dev_priv,
8225                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8226                 return false;
8227
8228         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8229         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8230
8231         tmp = I915_READ(PIPECONF(crtc->pipe));
8232         if (!(tmp & PIPECONF_ENABLE))
8233                 return false;
8234
8235         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8236                 switch (tmp & PIPECONF_BPC_MASK) {
8237                 case PIPECONF_6BPC:
8238                         pipe_config->pipe_bpp = 18;
8239                         break;
8240                 case PIPECONF_8BPC:
8241                         pipe_config->pipe_bpp = 24;
8242                         break;
8243                 case PIPECONF_10BPC:
8244                         pipe_config->pipe_bpp = 30;
8245                         break;
8246                 default:
8247                         break;
8248                 }
8249         }
8250
8251         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8252             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8253                 pipe_config->limited_color_range = true;
8254
8255         if (INTEL_INFO(dev)->gen < 4)
8256                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8257
8258         intel_get_pipe_timings(crtc, pipe_config);
8259
8260         i9xx_get_pfit_config(crtc, pipe_config);
8261
8262         if (INTEL_INFO(dev)->gen >= 4) {
8263                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8264                 pipe_config->pixel_multiplier =
8265                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8266                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8267                 pipe_config->dpll_hw_state.dpll_md = tmp;
8268         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8269                 tmp = I915_READ(DPLL(crtc->pipe));
8270                 pipe_config->pixel_multiplier =
8271                         ((tmp & SDVO_MULTIPLIER_MASK)
8272                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8273         } else {
8274                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8275                  * port and will be fixed up in the encoder->get_config
8276                  * function. */
8277                 pipe_config->pixel_multiplier = 1;
8278         }
8279         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8280         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8281                 /*
8282                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8283                  * on 830. Filter it out here so that we don't
8284                  * report errors due to that.
8285                  */
8286                 if (IS_I830(dev))
8287                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8288
8289                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8290                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8291         } else {
8292                 /* Mask out read-only status bits. */
8293                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8294                                                      DPLL_PORTC_READY_MASK |
8295                                                      DPLL_PORTB_READY_MASK);
8296         }
8297
8298         if (IS_CHERRYVIEW(dev))
8299                 chv_crtc_clock_get(crtc, pipe_config);
8300         else if (IS_VALLEYVIEW(dev))
8301                 vlv_crtc_clock_get(crtc, pipe_config);
8302         else
8303                 i9xx_crtc_clock_get(crtc, pipe_config);
8304
8305         /*
8306          * Normally the dotclock is filled in by the encoder .get_config()
8307          * but in case the pipe is enabled w/o any ports we need a sane
8308          * default.
8309          */
8310         pipe_config->base.adjusted_mode.crtc_clock =
8311                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8312
8313         return true;
8314 }
8315
8316 static void ironlake_init_pch_refclk(struct drm_device *dev)
8317 {
8318         struct drm_i915_private *dev_priv = dev->dev_private;
8319         struct intel_encoder *encoder;
8320         u32 val, final;
8321         bool has_lvds = false;
8322         bool has_cpu_edp = false;
8323         bool has_panel = false;
8324         bool has_ck505 = false;
8325         bool can_ssc = false;
8326
8327         /* We need to take the global config into account */
8328         for_each_intel_encoder(dev, encoder) {
8329                 switch (encoder->type) {
8330                 case INTEL_OUTPUT_LVDS:
8331                         has_panel = true;
8332                         has_lvds = true;
8333                         break;
8334                 case INTEL_OUTPUT_EDP:
8335                         has_panel = true;
8336                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8337                                 has_cpu_edp = true;
8338                         break;
8339                 default:
8340                         break;
8341                 }
8342         }
8343
8344         if (HAS_PCH_IBX(dev)) {
8345                 has_ck505 = dev_priv->vbt.display_clock_mode;
8346                 can_ssc = has_ck505;
8347         } else {
8348                 has_ck505 = false;
8349                 can_ssc = true;
8350         }
8351
8352         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8353                       has_panel, has_lvds, has_ck505);
8354
8355         /* Ironlake: try to setup display ref clock before DPLL
8356          * enabling. This is only under driver's control after
8357          * PCH B stepping, previous chipset stepping should be
8358          * ignoring this setting.
8359          */
8360         val = I915_READ(PCH_DREF_CONTROL);
8361
8362         /* As we must carefully and slowly disable/enable each source in turn,
8363          * compute the final state we want first and check if we need to
8364          * make any changes at all.
8365          */
8366         final = val;
8367         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8368         if (has_ck505)
8369                 final |= DREF_NONSPREAD_CK505_ENABLE;
8370         else
8371                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8372
8373         final &= ~DREF_SSC_SOURCE_MASK;
8374         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8375         final &= ~DREF_SSC1_ENABLE;
8376
8377         if (has_panel) {
8378                 final |= DREF_SSC_SOURCE_ENABLE;
8379
8380                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8381                         final |= DREF_SSC1_ENABLE;
8382
8383                 if (has_cpu_edp) {
8384                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8385                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8386                         else
8387                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8388                 } else
8389                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8390         } else {
8391                 final |= DREF_SSC_SOURCE_DISABLE;
8392                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8393         }
8394
8395         if (final == val)
8396                 return;
8397
8398         /* Always enable nonspread source */
8399         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8400
8401         if (has_ck505)
8402                 val |= DREF_NONSPREAD_CK505_ENABLE;
8403         else
8404                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8405
8406         if (has_panel) {
8407                 val &= ~DREF_SSC_SOURCE_MASK;
8408                 val |= DREF_SSC_SOURCE_ENABLE;
8409
8410                 /* SSC must be turned on before enabling the CPU output  */
8411                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8412                         DRM_DEBUG_KMS("Using SSC on panel\n");
8413                         val |= DREF_SSC1_ENABLE;
8414                 } else
8415                         val &= ~DREF_SSC1_ENABLE;
8416
8417                 /* Get SSC going before enabling the outputs */
8418                 I915_WRITE(PCH_DREF_CONTROL, val);
8419                 POSTING_READ(PCH_DREF_CONTROL);
8420                 udelay(200);
8421
8422                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8423
8424                 /* Enable CPU source on CPU attached eDP */
8425                 if (has_cpu_edp) {
8426                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8427                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8428                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8429                         } else
8430                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8431                 } else
8432                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8433
8434                 I915_WRITE(PCH_DREF_CONTROL, val);
8435                 POSTING_READ(PCH_DREF_CONTROL);
8436                 udelay(200);
8437         } else {
8438                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8439
8440                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8441
8442                 /* Turn off CPU output */
8443                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8444
8445                 I915_WRITE(PCH_DREF_CONTROL, val);
8446                 POSTING_READ(PCH_DREF_CONTROL);
8447                 udelay(200);
8448
8449                 /* Turn off the SSC source */
8450                 val &= ~DREF_SSC_SOURCE_MASK;
8451                 val |= DREF_SSC_SOURCE_DISABLE;
8452
8453                 /* Turn off SSC1 */
8454                 val &= ~DREF_SSC1_ENABLE;
8455
8456                 I915_WRITE(PCH_DREF_CONTROL, val);
8457                 POSTING_READ(PCH_DREF_CONTROL);
8458                 udelay(200);
8459         }
8460
8461         BUG_ON(val != final);
8462 }
8463
8464 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8465 {
8466         uint32_t tmp;
8467
8468         tmp = I915_READ(SOUTH_CHICKEN2);
8469         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8470         I915_WRITE(SOUTH_CHICKEN2, tmp);
8471
8472         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8473                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8474                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8475
8476         tmp = I915_READ(SOUTH_CHICKEN2);
8477         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8478         I915_WRITE(SOUTH_CHICKEN2, tmp);
8479
8480         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8481                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8482                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8483 }
8484
8485 /* WaMPhyProgramming:hsw */
8486 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8487 {
8488         uint32_t tmp;
8489
8490         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8491         tmp &= ~(0xFF << 24);
8492         tmp |= (0x12 << 24);
8493         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8494
8495         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8496         tmp |= (1 << 11);
8497         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8498
8499         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8500         tmp |= (1 << 11);
8501         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8502
8503         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8504         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8505         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8506
8507         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8508         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8509         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8510
8511         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8512         tmp &= ~(7 << 13);
8513         tmp |= (5 << 13);
8514         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8515
8516         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8517         tmp &= ~(7 << 13);
8518         tmp |= (5 << 13);
8519         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8520
8521         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8522         tmp &= ~0xFF;
8523         tmp |= 0x1C;
8524         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8525
8526         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8527         tmp &= ~0xFF;
8528         tmp |= 0x1C;
8529         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8530
8531         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8532         tmp &= ~(0xFF << 16);
8533         tmp |= (0x1C << 16);
8534         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8535
8536         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8537         tmp &= ~(0xFF << 16);
8538         tmp |= (0x1C << 16);
8539         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8540
8541         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8542         tmp |= (1 << 27);
8543         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8544
8545         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8546         tmp |= (1 << 27);
8547         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8548
8549         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8550         tmp &= ~(0xF << 28);
8551         tmp |= (4 << 28);
8552         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8553
8554         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8555         tmp &= ~(0xF << 28);
8556         tmp |= (4 << 28);
8557         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8558 }
8559
8560 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8561  * Programming" based on the parameters passed:
8562  * - Sequence to enable CLKOUT_DP
8563  * - Sequence to enable CLKOUT_DP without spread
8564  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8565  */
8566 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8567                                  bool with_fdi)
8568 {
8569         struct drm_i915_private *dev_priv = dev->dev_private;
8570         uint32_t reg, tmp;
8571
8572         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8573                 with_spread = true;
8574         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8575                 with_fdi = false;
8576
8577         mutex_lock(&dev_priv->sb_lock);
8578
8579         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8580         tmp &= ~SBI_SSCCTL_DISABLE;
8581         tmp |= SBI_SSCCTL_PATHALT;
8582         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8583
8584         udelay(24);
8585
8586         if (with_spread) {
8587                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8588                 tmp &= ~SBI_SSCCTL_PATHALT;
8589                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8590
8591                 if (with_fdi) {
8592                         lpt_reset_fdi_mphy(dev_priv);
8593                         lpt_program_fdi_mphy(dev_priv);
8594                 }
8595         }
8596
8597         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8598         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8599         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8600         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8601
8602         mutex_unlock(&dev_priv->sb_lock);
8603 }
8604
8605 /* Sequence to disable CLKOUT_DP */
8606 static void lpt_disable_clkout_dp(struct drm_device *dev)
8607 {
8608         struct drm_i915_private *dev_priv = dev->dev_private;
8609         uint32_t reg, tmp;
8610
8611         mutex_lock(&dev_priv->sb_lock);
8612
8613         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8614         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8615         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8616         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8617
8618         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8619         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8620                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8621                         tmp |= SBI_SSCCTL_PATHALT;
8622                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8623                         udelay(32);
8624                 }
8625                 tmp |= SBI_SSCCTL_DISABLE;
8626                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8627         }
8628
8629         mutex_unlock(&dev_priv->sb_lock);
8630 }
8631
8632 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8633
8634 static const uint16_t sscdivintphase[] = {
8635         [BEND_IDX( 50)] = 0x3B23,
8636         [BEND_IDX( 45)] = 0x3B23,
8637         [BEND_IDX( 40)] = 0x3C23,
8638         [BEND_IDX( 35)] = 0x3C23,
8639         [BEND_IDX( 30)] = 0x3D23,
8640         [BEND_IDX( 25)] = 0x3D23,
8641         [BEND_IDX( 20)] = 0x3E23,
8642         [BEND_IDX( 15)] = 0x3E23,
8643         [BEND_IDX( 10)] = 0x3F23,
8644         [BEND_IDX(  5)] = 0x3F23,
8645         [BEND_IDX(  0)] = 0x0025,
8646         [BEND_IDX( -5)] = 0x0025,
8647         [BEND_IDX(-10)] = 0x0125,
8648         [BEND_IDX(-15)] = 0x0125,
8649         [BEND_IDX(-20)] = 0x0225,
8650         [BEND_IDX(-25)] = 0x0225,
8651         [BEND_IDX(-30)] = 0x0325,
8652         [BEND_IDX(-35)] = 0x0325,
8653         [BEND_IDX(-40)] = 0x0425,
8654         [BEND_IDX(-45)] = 0x0425,
8655         [BEND_IDX(-50)] = 0x0525,
8656 };
8657
8658 /*
8659  * Bend CLKOUT_DP
8660  * steps -50 to 50 inclusive, in steps of 5
8661  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8662  * change in clock period = -(steps / 10) * 5.787 ps
8663  */
8664 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8665 {
8666         uint32_t tmp;
8667         int idx = BEND_IDX(steps);
8668
8669         if (WARN_ON(steps % 5 != 0))
8670                 return;
8671
8672         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8673                 return;
8674
8675         mutex_lock(&dev_priv->sb_lock);
8676
8677         if (steps % 10 != 0)
8678                 tmp = 0xAAAAAAAB;
8679         else
8680                 tmp = 0x00000000;
8681         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8682
8683         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8684         tmp &= 0xffff0000;
8685         tmp |= sscdivintphase[idx];
8686         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8687
8688         mutex_unlock(&dev_priv->sb_lock);
8689 }
8690
8691 #undef BEND_IDX
8692
8693 static void lpt_init_pch_refclk(struct drm_device *dev)
8694 {
8695         struct intel_encoder *encoder;
8696         bool has_vga = false;
8697
8698         for_each_intel_encoder(dev, encoder) {
8699                 switch (encoder->type) {
8700                 case INTEL_OUTPUT_ANALOG:
8701                         has_vga = true;
8702                         break;
8703                 default:
8704                         break;
8705                 }
8706         }
8707
8708         if (has_vga) {
8709                 lpt_bend_clkout_dp(to_i915(dev), 0);
8710                 lpt_enable_clkout_dp(dev, true, true);
8711         } else {
8712                 lpt_disable_clkout_dp(dev);
8713         }
8714 }
8715
8716 /*
8717  * Initialize reference clocks when the driver loads
8718  */
8719 void intel_init_pch_refclk(struct drm_device *dev)
8720 {
8721         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8722                 ironlake_init_pch_refclk(dev);
8723         else if (HAS_PCH_LPT(dev))
8724                 lpt_init_pch_refclk(dev);
8725 }
8726
8727 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8728 {
8729         struct drm_device *dev = crtc_state->base.crtc->dev;
8730         struct drm_i915_private *dev_priv = dev->dev_private;
8731         struct drm_atomic_state *state = crtc_state->base.state;
8732         struct drm_connector *connector;
8733         struct drm_connector_state *connector_state;
8734         struct intel_encoder *encoder;
8735         int num_connectors = 0, i;
8736         bool is_lvds = false;
8737
8738         for_each_connector_in_state(state, connector, connector_state, i) {
8739                 if (connector_state->crtc != crtc_state->base.crtc)
8740                         continue;
8741
8742                 encoder = to_intel_encoder(connector_state->best_encoder);
8743
8744                 switch (encoder->type) {
8745                 case INTEL_OUTPUT_LVDS:
8746                         is_lvds = true;
8747                         break;
8748                 default:
8749                         break;
8750                 }
8751                 num_connectors++;
8752         }
8753
8754         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8755                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8756                               dev_priv->vbt.lvds_ssc_freq);
8757                 return dev_priv->vbt.lvds_ssc_freq;
8758         }
8759
8760         return 120000;
8761 }
8762
8763 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8764 {
8765         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8767         int pipe = intel_crtc->pipe;
8768         uint32_t val;
8769
8770         val = 0;
8771
8772         switch (intel_crtc->config->pipe_bpp) {
8773         case 18:
8774                 val |= PIPECONF_6BPC;
8775                 break;
8776         case 24:
8777                 val |= PIPECONF_8BPC;
8778                 break;
8779         case 30:
8780                 val |= PIPECONF_10BPC;
8781                 break;
8782         case 36:
8783                 val |= PIPECONF_12BPC;
8784                 break;
8785         default:
8786                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8787                 BUG();
8788         }
8789
8790         if (intel_crtc->config->dither)
8791                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8792
8793         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8794                 val |= PIPECONF_INTERLACED_ILK;
8795         else
8796                 val |= PIPECONF_PROGRESSIVE;
8797
8798         if (intel_crtc->config->limited_color_range)
8799                 val |= PIPECONF_COLOR_RANGE_SELECT;
8800
8801         I915_WRITE(PIPECONF(pipe), val);
8802         POSTING_READ(PIPECONF(pipe));
8803 }
8804
8805 /*
8806  * Set up the pipe CSC unit.
8807  *
8808  * Currently only full range RGB to limited range RGB conversion
8809  * is supported, but eventually this should handle various
8810  * RGB<->YCbCr scenarios as well.
8811  */
8812 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8813 {
8814         struct drm_device *dev = crtc->dev;
8815         struct drm_i915_private *dev_priv = dev->dev_private;
8816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8817         int pipe = intel_crtc->pipe;
8818         uint16_t coeff = 0x7800; /* 1.0 */
8819
8820         /*
8821          * TODO: Check what kind of values actually come out of the pipe
8822          * with these coeff/postoff values and adjust to get the best
8823          * accuracy. Perhaps we even need to take the bpc value into
8824          * consideration.
8825          */
8826
8827         if (intel_crtc->config->limited_color_range)
8828                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8829
8830         /*
8831          * GY/GU and RY/RU should be the other way around according
8832          * to BSpec, but reality doesn't agree. Just set them up in
8833          * a way that results in the correct picture.
8834          */
8835         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8836         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8837
8838         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8839         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8840
8841         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8842         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8843
8844         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8845         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8846         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8847
8848         if (INTEL_INFO(dev)->gen > 6) {
8849                 uint16_t postoff = 0;
8850
8851                 if (intel_crtc->config->limited_color_range)
8852                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8853
8854                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8855                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8856                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8857
8858                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8859         } else {
8860                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8861
8862                 if (intel_crtc->config->limited_color_range)
8863                         mode |= CSC_BLACK_SCREEN_OFFSET;
8864
8865                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8866         }
8867 }
8868
8869 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8870 {
8871         struct drm_device *dev = crtc->dev;
8872         struct drm_i915_private *dev_priv = dev->dev_private;
8873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8874         enum pipe pipe = intel_crtc->pipe;
8875         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8876         uint32_t val;
8877
8878         val = 0;
8879
8880         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8881                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8882
8883         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8884                 val |= PIPECONF_INTERLACED_ILK;
8885         else
8886                 val |= PIPECONF_PROGRESSIVE;
8887
8888         I915_WRITE(PIPECONF(cpu_transcoder), val);
8889         POSTING_READ(PIPECONF(cpu_transcoder));
8890
8891         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8892         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8893
8894         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8895                 val = 0;
8896
8897                 switch (intel_crtc->config->pipe_bpp) {
8898                 case 18:
8899                         val |= PIPEMISC_DITHER_6_BPC;
8900                         break;
8901                 case 24:
8902                         val |= PIPEMISC_DITHER_8_BPC;
8903                         break;
8904                 case 30:
8905                         val |= PIPEMISC_DITHER_10_BPC;
8906                         break;
8907                 case 36:
8908                         val |= PIPEMISC_DITHER_12_BPC;
8909                         break;
8910                 default:
8911                         /* Case prevented by pipe_config_set_bpp. */
8912                         BUG();
8913                 }
8914
8915                 if (intel_crtc->config->dither)
8916                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8917
8918                 I915_WRITE(PIPEMISC(pipe), val);
8919         }
8920 }
8921
8922 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8923                                     struct intel_crtc_state *crtc_state,
8924                                     intel_clock_t *clock,
8925                                     bool *has_reduced_clock,
8926                                     intel_clock_t *reduced_clock)
8927 {
8928         struct drm_device *dev = crtc->dev;
8929         struct drm_i915_private *dev_priv = dev->dev_private;
8930         int refclk;
8931         const intel_limit_t *limit;
8932         bool ret;
8933
8934         refclk = ironlake_get_refclk(crtc_state);
8935
8936         /*
8937          * Returns a set of divisors for the desired target clock with the given
8938          * refclk, or FALSE.  The returned values represent the clock equation:
8939          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8940          */
8941         limit = intel_limit(crtc_state, refclk);
8942         ret = dev_priv->display.find_dpll(limit, crtc_state,
8943                                           crtc_state->port_clock,
8944                                           refclk, NULL, clock);
8945         if (!ret)
8946                 return false;
8947
8948         return true;
8949 }
8950
8951 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8952 {
8953         /*
8954          * Account for spread spectrum to avoid
8955          * oversubscribing the link. Max center spread
8956          * is 2.5%; use 5% for safety's sake.
8957          */
8958         u32 bps = target_clock * bpp * 21 / 20;
8959         return DIV_ROUND_UP(bps, link_bw * 8);
8960 }
8961
8962 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8963 {
8964         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8965 }
8966
8967 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8968                                       struct intel_crtc_state *crtc_state,
8969                                       u32 *fp,
8970                                       intel_clock_t *reduced_clock, u32 *fp2)
8971 {
8972         struct drm_crtc *crtc = &intel_crtc->base;
8973         struct drm_device *dev = crtc->dev;
8974         struct drm_i915_private *dev_priv = dev->dev_private;
8975         struct drm_atomic_state *state = crtc_state->base.state;
8976         struct drm_connector *connector;
8977         struct drm_connector_state *connector_state;
8978         struct intel_encoder *encoder;
8979         uint32_t dpll;
8980         int factor, num_connectors = 0, i;
8981         bool is_lvds = false, is_sdvo = false;
8982
8983         for_each_connector_in_state(state, connector, connector_state, i) {
8984                 if (connector_state->crtc != crtc_state->base.crtc)
8985                         continue;
8986
8987                 encoder = to_intel_encoder(connector_state->best_encoder);
8988
8989                 switch (encoder->type) {
8990                 case INTEL_OUTPUT_LVDS:
8991                         is_lvds = true;
8992                         break;
8993                 case INTEL_OUTPUT_SDVO:
8994                 case INTEL_OUTPUT_HDMI:
8995                         is_sdvo = true;
8996                         break;
8997                 default:
8998                         break;
8999                 }
9000
9001                 num_connectors++;
9002         }
9003
9004         /* Enable autotuning of the PLL clock (if permissible) */
9005         factor = 21;
9006         if (is_lvds) {
9007                 if ((intel_panel_use_ssc(dev_priv) &&
9008                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9009                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9010                         factor = 25;
9011         } else if (crtc_state->sdvo_tv_clock)
9012                 factor = 20;
9013
9014         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9015                 *fp |= FP_CB_TUNE;
9016
9017         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
9018                 *fp2 |= FP_CB_TUNE;
9019
9020         dpll = 0;
9021
9022         if (is_lvds)
9023                 dpll |= DPLLB_MODE_LVDS;
9024         else
9025                 dpll |= DPLLB_MODE_DAC_SERIAL;
9026
9027         dpll |= (crtc_state->pixel_multiplier - 1)
9028                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9029
9030         if (is_sdvo)
9031                 dpll |= DPLL_SDVO_HIGH_SPEED;
9032         if (crtc_state->has_dp_encoder)
9033                 dpll |= DPLL_SDVO_HIGH_SPEED;
9034
9035         /* compute bitmask from p1 value */
9036         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9037         /* also FPA1 */
9038         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9039
9040         switch (crtc_state->dpll.p2) {
9041         case 5:
9042                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9043                 break;
9044         case 7:
9045                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9046                 break;
9047         case 10:
9048                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9049                 break;
9050         case 14:
9051                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9052                 break;
9053         }
9054
9055         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
9056                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9057         else
9058                 dpll |= PLL_REF_INPUT_DREFCLK;
9059
9060         return dpll | DPLL_VCO_ENABLE;
9061 }
9062
9063 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9064                                        struct intel_crtc_state *crtc_state)
9065 {
9066         struct drm_device *dev = crtc->base.dev;
9067         intel_clock_t clock, reduced_clock;
9068         u32 dpll = 0, fp = 0, fp2 = 0;
9069         bool ok, has_reduced_clock = false;
9070         bool is_lvds = false;
9071         struct intel_shared_dpll *pll;
9072
9073         memset(&crtc_state->dpll_hw_state, 0,
9074                sizeof(crtc_state->dpll_hw_state));
9075
9076         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9077
9078         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9079              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9080
9081         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9082                                      &has_reduced_clock, &reduced_clock);
9083         if (!ok && !crtc_state->clock_set) {
9084                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9085                 return -EINVAL;
9086         }
9087         /* Compat-code for transition, will disappear. */
9088         if (!crtc_state->clock_set) {
9089                 crtc_state->dpll.n = clock.n;
9090                 crtc_state->dpll.m1 = clock.m1;
9091                 crtc_state->dpll.m2 = clock.m2;
9092                 crtc_state->dpll.p1 = clock.p1;
9093                 crtc_state->dpll.p2 = clock.p2;
9094         }
9095
9096         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9097         if (crtc_state->has_pch_encoder) {
9098                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9099                 if (has_reduced_clock)
9100                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9101
9102                 dpll = ironlake_compute_dpll(crtc, crtc_state,
9103                                              &fp, &reduced_clock,
9104                                              has_reduced_clock ? &fp2 : NULL);
9105
9106                 crtc_state->dpll_hw_state.dpll = dpll;
9107                 crtc_state->dpll_hw_state.fp0 = fp;
9108                 if (has_reduced_clock)
9109                         crtc_state->dpll_hw_state.fp1 = fp2;
9110                 else
9111                         crtc_state->dpll_hw_state.fp1 = fp;
9112
9113                 pll = intel_get_shared_dpll(crtc, crtc_state);
9114                 if (pll == NULL) {
9115                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9116                                          pipe_name(crtc->pipe));
9117                         return -EINVAL;
9118                 }
9119         }
9120
9121         if (is_lvds && has_reduced_clock)
9122                 crtc->lowfreq_avail = true;
9123         else
9124                 crtc->lowfreq_avail = false;
9125
9126         return 0;
9127 }
9128
9129 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9130                                          struct intel_link_m_n *m_n)
9131 {
9132         struct drm_device *dev = crtc->base.dev;
9133         struct drm_i915_private *dev_priv = dev->dev_private;
9134         enum pipe pipe = crtc->pipe;
9135
9136         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9137         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9138         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9139                 & ~TU_SIZE_MASK;
9140         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9141         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9142                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9143 }
9144
9145 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9146                                          enum transcoder transcoder,
9147                                          struct intel_link_m_n *m_n,
9148                                          struct intel_link_m_n *m2_n2)
9149 {
9150         struct drm_device *dev = crtc->base.dev;
9151         struct drm_i915_private *dev_priv = dev->dev_private;
9152         enum pipe pipe = crtc->pipe;
9153
9154         if (INTEL_INFO(dev)->gen >= 5) {
9155                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9156                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9157                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9158                         & ~TU_SIZE_MASK;
9159                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9160                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9161                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9162                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9163                  * gen < 8) and if DRRS is supported (to make sure the
9164                  * registers are not unnecessarily read).
9165                  */
9166                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9167                         crtc->config->has_drrs) {
9168                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9169                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9170                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9171                                         & ~TU_SIZE_MASK;
9172                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9173                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9174                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9175                 }
9176         } else {
9177                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9178                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9179                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9180                         & ~TU_SIZE_MASK;
9181                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9182                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9183                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9184         }
9185 }
9186
9187 void intel_dp_get_m_n(struct intel_crtc *crtc,
9188                       struct intel_crtc_state *pipe_config)
9189 {
9190         if (pipe_config->has_pch_encoder)
9191                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9192         else
9193                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9194                                              &pipe_config->dp_m_n,
9195                                              &pipe_config->dp_m2_n2);
9196 }
9197
9198 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9199                                         struct intel_crtc_state *pipe_config)
9200 {
9201         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9202                                      &pipe_config->fdi_m_n, NULL);
9203 }
9204
9205 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9206                                     struct intel_crtc_state *pipe_config)
9207 {
9208         struct drm_device *dev = crtc->base.dev;
9209         struct drm_i915_private *dev_priv = dev->dev_private;
9210         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9211         uint32_t ps_ctrl = 0;
9212         int id = -1;
9213         int i;
9214
9215         /* find scaler attached to this pipe */
9216         for (i = 0; i < crtc->num_scalers; i++) {
9217                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9218                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9219                         id = i;
9220                         pipe_config->pch_pfit.enabled = true;
9221                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9222                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9223                         break;
9224                 }
9225         }
9226
9227         scaler_state->scaler_id = id;
9228         if (id >= 0) {
9229                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9230         } else {
9231                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9232         }
9233 }
9234
9235 static void
9236 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9237                                  struct intel_initial_plane_config *plane_config)
9238 {
9239         struct drm_device *dev = crtc->base.dev;
9240         struct drm_i915_private *dev_priv = dev->dev_private;
9241         u32 val, base, offset, stride_mult, tiling;
9242         int pipe = crtc->pipe;
9243         int fourcc, pixel_format;
9244         unsigned int aligned_height;
9245         struct drm_framebuffer *fb;
9246         struct intel_framebuffer *intel_fb;
9247
9248         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9249         if (!intel_fb) {
9250                 DRM_DEBUG_KMS("failed to alloc fb\n");
9251                 return;
9252         }
9253
9254         fb = &intel_fb->base;
9255
9256         val = I915_READ(PLANE_CTL(pipe, 0));
9257         if (!(val & PLANE_CTL_ENABLE))
9258                 goto error;
9259
9260         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9261         fourcc = skl_format_to_fourcc(pixel_format,
9262                                       val & PLANE_CTL_ORDER_RGBX,
9263                                       val & PLANE_CTL_ALPHA_MASK);
9264         fb->pixel_format = fourcc;
9265         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9266
9267         tiling = val & PLANE_CTL_TILED_MASK;
9268         switch (tiling) {
9269         case PLANE_CTL_TILED_LINEAR:
9270                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9271                 break;
9272         case PLANE_CTL_TILED_X:
9273                 plane_config->tiling = I915_TILING_X;
9274                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9275                 break;
9276         case PLANE_CTL_TILED_Y:
9277                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9278                 break;
9279         case PLANE_CTL_TILED_YF:
9280                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9281                 break;
9282         default:
9283                 MISSING_CASE(tiling);
9284                 goto error;
9285         }
9286
9287         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9288         plane_config->base = base;
9289
9290         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9291
9292         val = I915_READ(PLANE_SIZE(pipe, 0));
9293         fb->height = ((val >> 16) & 0xfff) + 1;
9294         fb->width = ((val >> 0) & 0x1fff) + 1;
9295
9296         val = I915_READ(PLANE_STRIDE(pipe, 0));
9297         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9298                                                 fb->pixel_format);
9299         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9300
9301         aligned_height = intel_fb_align_height(dev, fb->height,
9302                                                fb->pixel_format,
9303                                                fb->modifier[0]);
9304
9305         plane_config->size = fb->pitches[0] * aligned_height;
9306
9307         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9308                       pipe_name(pipe), fb->width, fb->height,
9309                       fb->bits_per_pixel, base, fb->pitches[0],
9310                       plane_config->size);
9311
9312         plane_config->fb = intel_fb;
9313         return;
9314
9315 error:
9316         kfree(fb);
9317 }
9318
9319 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9320                                      struct intel_crtc_state *pipe_config)
9321 {
9322         struct drm_device *dev = crtc->base.dev;
9323         struct drm_i915_private *dev_priv = dev->dev_private;
9324         uint32_t tmp;
9325
9326         tmp = I915_READ(PF_CTL(crtc->pipe));
9327
9328         if (tmp & PF_ENABLE) {
9329                 pipe_config->pch_pfit.enabled = true;
9330                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9331                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9332
9333                 /* We currently do not free assignements of panel fitters on
9334                  * ivb/hsw (since we don't use the higher upscaling modes which
9335                  * differentiates them) so just WARN about this case for now. */
9336                 if (IS_GEN7(dev)) {
9337                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9338                                 PF_PIPE_SEL_IVB(crtc->pipe));
9339                 }
9340         }
9341 }
9342
9343 static void
9344 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9345                                   struct intel_initial_plane_config *plane_config)
9346 {
9347         struct drm_device *dev = crtc->base.dev;
9348         struct drm_i915_private *dev_priv = dev->dev_private;
9349         u32 val, base, offset;
9350         int pipe = crtc->pipe;
9351         int fourcc, pixel_format;
9352         unsigned int aligned_height;
9353         struct drm_framebuffer *fb;
9354         struct intel_framebuffer *intel_fb;
9355
9356         val = I915_READ(DSPCNTR(pipe));
9357         if (!(val & DISPLAY_PLANE_ENABLE))
9358                 return;
9359
9360         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9361         if (!intel_fb) {
9362                 DRM_DEBUG_KMS("failed to alloc fb\n");
9363                 return;
9364         }
9365
9366         fb = &intel_fb->base;
9367
9368         if (INTEL_INFO(dev)->gen >= 4) {
9369                 if (val & DISPPLANE_TILED) {
9370                         plane_config->tiling = I915_TILING_X;
9371                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9372                 }
9373         }
9374
9375         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9376         fourcc = i9xx_format_to_fourcc(pixel_format);
9377         fb->pixel_format = fourcc;
9378         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9379
9380         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9381         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9382                 offset = I915_READ(DSPOFFSET(pipe));
9383         } else {
9384                 if (plane_config->tiling)
9385                         offset = I915_READ(DSPTILEOFF(pipe));
9386                 else
9387                         offset = I915_READ(DSPLINOFF(pipe));
9388         }
9389         plane_config->base = base;
9390
9391         val = I915_READ(PIPESRC(pipe));
9392         fb->width = ((val >> 16) & 0xfff) + 1;
9393         fb->height = ((val >> 0) & 0xfff) + 1;
9394
9395         val = I915_READ(DSPSTRIDE(pipe));
9396         fb->pitches[0] = val & 0xffffffc0;
9397
9398         aligned_height = intel_fb_align_height(dev, fb->height,
9399                                                fb->pixel_format,
9400                                                fb->modifier[0]);
9401
9402         plane_config->size = fb->pitches[0] * aligned_height;
9403
9404         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9405                       pipe_name(pipe), fb->width, fb->height,
9406                       fb->bits_per_pixel, base, fb->pitches[0],
9407                       plane_config->size);
9408
9409         plane_config->fb = intel_fb;
9410 }
9411
9412 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9413                                      struct intel_crtc_state *pipe_config)
9414 {
9415         struct drm_device *dev = crtc->base.dev;
9416         struct drm_i915_private *dev_priv = dev->dev_private;
9417         uint32_t tmp;
9418
9419         if (!intel_display_power_is_enabled(dev_priv,
9420                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9421                 return false;
9422
9423         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9424         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9425
9426         tmp = I915_READ(PIPECONF(crtc->pipe));
9427         if (!(tmp & PIPECONF_ENABLE))
9428                 return false;
9429
9430         switch (tmp & PIPECONF_BPC_MASK) {
9431         case PIPECONF_6BPC:
9432                 pipe_config->pipe_bpp = 18;
9433                 break;
9434         case PIPECONF_8BPC:
9435                 pipe_config->pipe_bpp = 24;
9436                 break;
9437         case PIPECONF_10BPC:
9438                 pipe_config->pipe_bpp = 30;
9439                 break;
9440         case PIPECONF_12BPC:
9441                 pipe_config->pipe_bpp = 36;
9442                 break;
9443         default:
9444                 break;
9445         }
9446
9447         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9448                 pipe_config->limited_color_range = true;
9449
9450         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9451                 struct intel_shared_dpll *pll;
9452
9453                 pipe_config->has_pch_encoder = true;
9454
9455                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9456                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9457                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9458
9459                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9460
9461                 if (HAS_PCH_IBX(dev_priv->dev)) {
9462                         pipe_config->shared_dpll =
9463                                 (enum intel_dpll_id) crtc->pipe;
9464                 } else {
9465                         tmp = I915_READ(PCH_DPLL_SEL);
9466                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9467                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9468                         else
9469                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9470                 }
9471
9472                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9473
9474                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9475                                            &pipe_config->dpll_hw_state));
9476
9477                 tmp = pipe_config->dpll_hw_state.dpll;
9478                 pipe_config->pixel_multiplier =
9479                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9480                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9481
9482                 ironlake_pch_clock_get(crtc, pipe_config);
9483         } else {
9484                 pipe_config->pixel_multiplier = 1;
9485         }
9486
9487         intel_get_pipe_timings(crtc, pipe_config);
9488
9489         ironlake_get_pfit_config(crtc, pipe_config);
9490
9491         return true;
9492 }
9493
9494 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9495 {
9496         struct drm_device *dev = dev_priv->dev;
9497         struct intel_crtc *crtc;
9498
9499         for_each_intel_crtc(dev, crtc)
9500                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9501                      pipe_name(crtc->pipe));
9502
9503         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9504         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9505         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9506         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9507         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9508         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9509              "CPU PWM1 enabled\n");
9510         if (IS_HASWELL(dev))
9511                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9512                      "CPU PWM2 enabled\n");
9513         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9514              "PCH PWM1 enabled\n");
9515         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9516              "Utility pin enabled\n");
9517         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9518
9519         /*
9520          * In theory we can still leave IRQs enabled, as long as only the HPD
9521          * interrupts remain enabled. We used to check for that, but since it's
9522          * gen-specific and since we only disable LCPLL after we fully disable
9523          * the interrupts, the check below should be enough.
9524          */
9525         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9526 }
9527
9528 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9529 {
9530         struct drm_device *dev = dev_priv->dev;
9531
9532         if (IS_HASWELL(dev))
9533                 return I915_READ(D_COMP_HSW);
9534         else
9535                 return I915_READ(D_COMP_BDW);
9536 }
9537
9538 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9539 {
9540         struct drm_device *dev = dev_priv->dev;
9541
9542         if (IS_HASWELL(dev)) {
9543                 mutex_lock(&dev_priv->rps.hw_lock);
9544                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9545                                             val))
9546                         DRM_ERROR("Failed to write to D_COMP\n");
9547                 mutex_unlock(&dev_priv->rps.hw_lock);
9548         } else {
9549                 I915_WRITE(D_COMP_BDW, val);
9550                 POSTING_READ(D_COMP_BDW);
9551         }
9552 }
9553
9554 /*
9555  * This function implements pieces of two sequences from BSpec:
9556  * - Sequence for display software to disable LCPLL
9557  * - Sequence for display software to allow package C8+
9558  * The steps implemented here are just the steps that actually touch the LCPLL
9559  * register. Callers should take care of disabling all the display engine
9560  * functions, doing the mode unset, fixing interrupts, etc.
9561  */
9562 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9563                               bool switch_to_fclk, bool allow_power_down)
9564 {
9565         uint32_t val;
9566
9567         assert_can_disable_lcpll(dev_priv);
9568
9569         val = I915_READ(LCPLL_CTL);
9570
9571         if (switch_to_fclk) {
9572                 val |= LCPLL_CD_SOURCE_FCLK;
9573                 I915_WRITE(LCPLL_CTL, val);
9574
9575                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9576                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9577                         DRM_ERROR("Switching to FCLK failed\n");
9578
9579                 val = I915_READ(LCPLL_CTL);
9580         }
9581
9582         val |= LCPLL_PLL_DISABLE;
9583         I915_WRITE(LCPLL_CTL, val);
9584         POSTING_READ(LCPLL_CTL);
9585
9586         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9587                 DRM_ERROR("LCPLL still locked\n");
9588
9589         val = hsw_read_dcomp(dev_priv);
9590         val |= D_COMP_COMP_DISABLE;
9591         hsw_write_dcomp(dev_priv, val);
9592         ndelay(100);
9593
9594         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9595                      1))
9596                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9597
9598         if (allow_power_down) {
9599                 val = I915_READ(LCPLL_CTL);
9600                 val |= LCPLL_POWER_DOWN_ALLOW;
9601                 I915_WRITE(LCPLL_CTL, val);
9602                 POSTING_READ(LCPLL_CTL);
9603         }
9604 }
9605
9606 /*
9607  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9608  * source.
9609  */
9610 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9611 {
9612         uint32_t val;
9613
9614         val = I915_READ(LCPLL_CTL);
9615
9616         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9617                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9618                 return;
9619
9620         /*
9621          * Make sure we're not on PC8 state before disabling PC8, otherwise
9622          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9623          */
9624         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9625
9626         if (val & LCPLL_POWER_DOWN_ALLOW) {
9627                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9628                 I915_WRITE(LCPLL_CTL, val);
9629                 POSTING_READ(LCPLL_CTL);
9630         }
9631
9632         val = hsw_read_dcomp(dev_priv);
9633         val |= D_COMP_COMP_FORCE;
9634         val &= ~D_COMP_COMP_DISABLE;
9635         hsw_write_dcomp(dev_priv, val);
9636
9637         val = I915_READ(LCPLL_CTL);
9638         val &= ~LCPLL_PLL_DISABLE;
9639         I915_WRITE(LCPLL_CTL, val);
9640
9641         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9642                 DRM_ERROR("LCPLL not locked yet\n");
9643
9644         if (val & LCPLL_CD_SOURCE_FCLK) {
9645                 val = I915_READ(LCPLL_CTL);
9646                 val &= ~LCPLL_CD_SOURCE_FCLK;
9647                 I915_WRITE(LCPLL_CTL, val);
9648
9649                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9650                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9651                         DRM_ERROR("Switching back to LCPLL failed\n");
9652         }
9653
9654         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9655         intel_update_cdclk(dev_priv->dev);
9656 }
9657
9658 /*
9659  * Package states C8 and deeper are really deep PC states that can only be
9660  * reached when all the devices on the system allow it, so even if the graphics
9661  * device allows PC8+, it doesn't mean the system will actually get to these
9662  * states. Our driver only allows PC8+ when going into runtime PM.
9663  *
9664  * The requirements for PC8+ are that all the outputs are disabled, the power
9665  * well is disabled and most interrupts are disabled, and these are also
9666  * requirements for runtime PM. When these conditions are met, we manually do
9667  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9668  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9669  * hang the machine.
9670  *
9671  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9672  * the state of some registers, so when we come back from PC8+ we need to
9673  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9674  * need to take care of the registers kept by RC6. Notice that this happens even
9675  * if we don't put the device in PCI D3 state (which is what currently happens
9676  * because of the runtime PM support).
9677  *
9678  * For more, read "Display Sequences for Package C8" on the hardware
9679  * documentation.
9680  */
9681 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9682 {
9683         struct drm_device *dev = dev_priv->dev;
9684         uint32_t val;
9685
9686         DRM_DEBUG_KMS("Enabling package C8+\n");
9687
9688         if (HAS_PCH_LPT_LP(dev)) {
9689                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9690                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9691                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9692         }
9693
9694         lpt_disable_clkout_dp(dev);
9695         hsw_disable_lcpll(dev_priv, true, true);
9696 }
9697
9698 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9699 {
9700         struct drm_device *dev = dev_priv->dev;
9701         uint32_t val;
9702
9703         DRM_DEBUG_KMS("Disabling package C8+\n");
9704
9705         hsw_restore_lcpll(dev_priv);
9706         lpt_init_pch_refclk(dev);
9707
9708         if (HAS_PCH_LPT_LP(dev)) {
9709                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9710                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9711                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9712         }
9713
9714         intel_prepare_ddi(dev);
9715 }
9716
9717 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9718 {
9719         struct drm_device *dev = old_state->dev;
9720         struct intel_atomic_state *old_intel_state =
9721                 to_intel_atomic_state(old_state);
9722         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9723
9724         broxton_set_cdclk(dev, req_cdclk);
9725 }
9726
9727 /* compute the max rate for new configuration */
9728 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9729 {
9730         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9731         struct drm_i915_private *dev_priv = state->dev->dev_private;
9732         struct drm_crtc *crtc;
9733         struct drm_crtc_state *cstate;
9734         struct intel_crtc_state *crtc_state;
9735         unsigned max_pixel_rate = 0, i;
9736         enum pipe pipe;
9737
9738         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9739                sizeof(intel_state->min_pixclk));
9740
9741         for_each_crtc_in_state(state, crtc, cstate, i) {
9742                 int pixel_rate;
9743
9744                 crtc_state = to_intel_crtc_state(cstate);
9745                 if (!crtc_state->base.enable) {
9746                         intel_state->min_pixclk[i] = 0;
9747                         continue;
9748                 }
9749
9750                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9751
9752                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9753                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9754                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9755
9756                 intel_state->min_pixclk[i] = pixel_rate;
9757         }
9758
9759         if (!intel_state->active_crtcs)
9760                 return 0;
9761
9762         for_each_pipe(dev_priv, pipe)
9763                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9764
9765         return max_pixel_rate;
9766 }
9767
9768 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9769 {
9770         struct drm_i915_private *dev_priv = dev->dev_private;
9771         uint32_t val, data;
9772         int ret;
9773
9774         if (WARN((I915_READ(LCPLL_CTL) &
9775                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9776                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9777                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9778                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9779                  "trying to change cdclk frequency with cdclk not enabled\n"))
9780                 return;
9781
9782         mutex_lock(&dev_priv->rps.hw_lock);
9783         ret = sandybridge_pcode_write(dev_priv,
9784                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9785         mutex_unlock(&dev_priv->rps.hw_lock);
9786         if (ret) {
9787                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9788                 return;
9789         }
9790
9791         val = I915_READ(LCPLL_CTL);
9792         val |= LCPLL_CD_SOURCE_FCLK;
9793         I915_WRITE(LCPLL_CTL, val);
9794
9795         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9796                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9797                 DRM_ERROR("Switching to FCLK failed\n");
9798
9799         val = I915_READ(LCPLL_CTL);
9800         val &= ~LCPLL_CLK_FREQ_MASK;
9801
9802         switch (cdclk) {
9803         case 450000:
9804                 val |= LCPLL_CLK_FREQ_450;
9805                 data = 0;
9806                 break;
9807         case 540000:
9808                 val |= LCPLL_CLK_FREQ_54O_BDW;
9809                 data = 1;
9810                 break;
9811         case 337500:
9812                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9813                 data = 2;
9814                 break;
9815         case 675000:
9816                 val |= LCPLL_CLK_FREQ_675_BDW;
9817                 data = 3;
9818                 break;
9819         default:
9820                 WARN(1, "invalid cdclk frequency\n");
9821                 return;
9822         }
9823
9824         I915_WRITE(LCPLL_CTL, val);
9825
9826         val = I915_READ(LCPLL_CTL);
9827         val &= ~LCPLL_CD_SOURCE_FCLK;
9828         I915_WRITE(LCPLL_CTL, val);
9829
9830         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9831                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9832                 DRM_ERROR("Switching back to LCPLL failed\n");
9833
9834         mutex_lock(&dev_priv->rps.hw_lock);
9835         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9836         mutex_unlock(&dev_priv->rps.hw_lock);
9837
9838         intel_update_cdclk(dev);
9839
9840         WARN(cdclk != dev_priv->cdclk_freq,
9841              "cdclk requested %d kHz but got %d kHz\n",
9842              cdclk, dev_priv->cdclk_freq);
9843 }
9844
9845 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9846 {
9847         struct drm_i915_private *dev_priv = to_i915(state->dev);
9848         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9849         int max_pixclk = ilk_max_pixel_rate(state);
9850         int cdclk;
9851
9852         /*
9853          * FIXME should also account for plane ratio
9854          * once 64bpp pixel formats are supported.
9855          */
9856         if (max_pixclk > 540000)
9857                 cdclk = 675000;
9858         else if (max_pixclk > 450000)
9859                 cdclk = 540000;
9860         else if (max_pixclk > 337500)
9861                 cdclk = 450000;
9862         else
9863                 cdclk = 337500;
9864
9865         if (cdclk > dev_priv->max_cdclk_freq) {
9866                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9867                               cdclk, dev_priv->max_cdclk_freq);
9868                 return -EINVAL;
9869         }
9870
9871         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9872         if (!intel_state->active_crtcs)
9873                 intel_state->dev_cdclk = 337500;
9874
9875         return 0;
9876 }
9877
9878 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9879 {
9880         struct drm_device *dev = old_state->dev;
9881         struct intel_atomic_state *old_intel_state =
9882                 to_intel_atomic_state(old_state);
9883         unsigned req_cdclk = old_intel_state->dev_cdclk;
9884
9885         broadwell_set_cdclk(dev, req_cdclk);
9886 }
9887
9888 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9889                                       struct intel_crtc_state *crtc_state)
9890 {
9891         if (!intel_ddi_pll_select(crtc, crtc_state))
9892                 return -EINVAL;
9893
9894         crtc->lowfreq_avail = false;
9895
9896         return 0;
9897 }
9898
9899 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9900                                 enum port port,
9901                                 struct intel_crtc_state *pipe_config)
9902 {
9903         switch (port) {
9904         case PORT_A:
9905                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9906                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9907                 break;
9908         case PORT_B:
9909                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9910                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9911                 break;
9912         case PORT_C:
9913                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9914                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9915                 break;
9916         default:
9917                 DRM_ERROR("Incorrect port type\n");
9918         }
9919 }
9920
9921 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9922                                 enum port port,
9923                                 struct intel_crtc_state *pipe_config)
9924 {
9925         u32 temp, dpll_ctl1;
9926
9927         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9928         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9929
9930         switch (pipe_config->ddi_pll_sel) {
9931         case SKL_DPLL0:
9932                 /*
9933                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9934                  * of the shared DPLL framework and thus needs to be read out
9935                  * separately
9936                  */
9937                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9938                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9939                 break;
9940         case SKL_DPLL1:
9941                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9942                 break;
9943         case SKL_DPLL2:
9944                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9945                 break;
9946         case SKL_DPLL3:
9947                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9948                 break;
9949         }
9950 }
9951
9952 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9953                                 enum port port,
9954                                 struct intel_crtc_state *pipe_config)
9955 {
9956         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9957
9958         switch (pipe_config->ddi_pll_sel) {
9959         case PORT_CLK_SEL_WRPLL1:
9960                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9961                 break;
9962         case PORT_CLK_SEL_WRPLL2:
9963                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9964                 break;
9965         case PORT_CLK_SEL_SPLL:
9966                 pipe_config->shared_dpll = DPLL_ID_SPLL;
9967                 break;
9968         }
9969 }
9970
9971 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9972                                        struct intel_crtc_state *pipe_config)
9973 {
9974         struct drm_device *dev = crtc->base.dev;
9975         struct drm_i915_private *dev_priv = dev->dev_private;
9976         struct intel_shared_dpll *pll;
9977         enum port port;
9978         uint32_t tmp;
9979
9980         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9981
9982         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9983
9984         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9985                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9986         else if (IS_BROXTON(dev))
9987                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9988         else
9989                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9990
9991         if (pipe_config->shared_dpll >= 0) {
9992                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9993
9994                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9995                                            &pipe_config->dpll_hw_state));
9996         }
9997
9998         /*
9999          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10000          * DDI E. So just check whether this pipe is wired to DDI E and whether
10001          * the PCH transcoder is on.
10002          */
10003         if (INTEL_INFO(dev)->gen < 9 &&
10004             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10005                 pipe_config->has_pch_encoder = true;
10006
10007                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10008                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10009                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10010
10011                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10012         }
10013 }
10014
10015 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10016                                     struct intel_crtc_state *pipe_config)
10017 {
10018         struct drm_device *dev = crtc->base.dev;
10019         struct drm_i915_private *dev_priv = dev->dev_private;
10020         enum intel_display_power_domain pfit_domain;
10021         uint32_t tmp;
10022
10023         if (!intel_display_power_is_enabled(dev_priv,
10024                                          POWER_DOMAIN_PIPE(crtc->pipe)))
10025                 return false;
10026
10027         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10028         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10029
10030         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10031         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10032                 enum pipe trans_edp_pipe;
10033                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10034                 default:
10035                         WARN(1, "unknown pipe linked to edp transcoder\n");
10036                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10037                 case TRANS_DDI_EDP_INPUT_A_ON:
10038                         trans_edp_pipe = PIPE_A;
10039                         break;
10040                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10041                         trans_edp_pipe = PIPE_B;
10042                         break;
10043                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10044                         trans_edp_pipe = PIPE_C;
10045                         break;
10046                 }
10047
10048                 if (trans_edp_pipe == crtc->pipe)
10049                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10050         }
10051
10052         if (!intel_display_power_is_enabled(dev_priv,
10053                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
10054                 return false;
10055
10056         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10057         if (!(tmp & PIPECONF_ENABLE))
10058                 return false;
10059
10060         haswell_get_ddi_port_state(crtc, pipe_config);
10061
10062         intel_get_pipe_timings(crtc, pipe_config);
10063
10064         if (INTEL_INFO(dev)->gen >= 9) {
10065                 skl_init_scalers(dev, crtc, pipe_config);
10066         }
10067
10068         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10069
10070         if (INTEL_INFO(dev)->gen >= 9) {
10071                 pipe_config->scaler_state.scaler_id = -1;
10072                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10073         }
10074
10075         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
10076                 if (INTEL_INFO(dev)->gen >= 9)
10077                         skylake_get_pfit_config(crtc, pipe_config);
10078                 else
10079                         ironlake_get_pfit_config(crtc, pipe_config);
10080         }
10081
10082         if (IS_HASWELL(dev))
10083                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10084                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10085
10086         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10087                 pipe_config->pixel_multiplier =
10088                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10089         } else {
10090                 pipe_config->pixel_multiplier = 1;
10091         }
10092
10093         return true;
10094 }
10095
10096 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10097                                const struct intel_plane_state *plane_state)
10098 {
10099         struct drm_device *dev = crtc->dev;
10100         struct drm_i915_private *dev_priv = dev->dev_private;
10101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10102         uint32_t cntl = 0, size = 0;
10103
10104         if (plane_state && plane_state->visible) {
10105                 unsigned int width = plane_state->base.crtc_w;
10106                 unsigned int height = plane_state->base.crtc_h;
10107                 unsigned int stride = roundup_pow_of_two(width) * 4;
10108
10109                 switch (stride) {
10110                 default:
10111                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10112                                   width, stride);
10113                         stride = 256;
10114                         /* fallthrough */
10115                 case 256:
10116                 case 512:
10117                 case 1024:
10118                 case 2048:
10119                         break;
10120                 }
10121
10122                 cntl |= CURSOR_ENABLE |
10123                         CURSOR_GAMMA_ENABLE |
10124                         CURSOR_FORMAT_ARGB |
10125                         CURSOR_STRIDE(stride);
10126
10127                 size = (height << 12) | width;
10128         }
10129
10130         if (intel_crtc->cursor_cntl != 0 &&
10131             (intel_crtc->cursor_base != base ||
10132              intel_crtc->cursor_size != size ||
10133              intel_crtc->cursor_cntl != cntl)) {
10134                 /* On these chipsets we can only modify the base/size/stride
10135                  * whilst the cursor is disabled.
10136                  */
10137                 I915_WRITE(CURCNTR(PIPE_A), 0);
10138                 POSTING_READ(CURCNTR(PIPE_A));
10139                 intel_crtc->cursor_cntl = 0;
10140         }
10141
10142         if (intel_crtc->cursor_base != base) {
10143                 I915_WRITE(CURBASE(PIPE_A), base);
10144                 intel_crtc->cursor_base = base;
10145         }
10146
10147         if (intel_crtc->cursor_size != size) {
10148                 I915_WRITE(CURSIZE, size);
10149                 intel_crtc->cursor_size = size;
10150         }
10151
10152         if (intel_crtc->cursor_cntl != cntl) {
10153                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10154                 POSTING_READ(CURCNTR(PIPE_A));
10155                 intel_crtc->cursor_cntl = cntl;
10156         }
10157 }
10158
10159 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10160                                const struct intel_plane_state *plane_state)
10161 {
10162         struct drm_device *dev = crtc->dev;
10163         struct drm_i915_private *dev_priv = dev->dev_private;
10164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10165         int pipe = intel_crtc->pipe;
10166         uint32_t cntl = 0;
10167
10168         if (plane_state && plane_state->visible) {
10169                 cntl = MCURSOR_GAMMA_ENABLE;
10170                 switch (plane_state->base.crtc_w) {
10171                         case 64:
10172                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10173                                 break;
10174                         case 128:
10175                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10176                                 break;
10177                         case 256:
10178                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10179                                 break;
10180                         default:
10181                                 MISSING_CASE(plane_state->base.crtc_w);
10182                                 return;
10183                 }
10184                 cntl |= pipe << 28; /* Connect to correct pipe */
10185
10186                 if (HAS_DDI(dev))
10187                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10188
10189                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10190                         cntl |= CURSOR_ROTATE_180;
10191         }
10192
10193         if (intel_crtc->cursor_cntl != cntl) {
10194                 I915_WRITE(CURCNTR(pipe), cntl);
10195                 POSTING_READ(CURCNTR(pipe));
10196                 intel_crtc->cursor_cntl = cntl;
10197         }
10198
10199         /* and commit changes on next vblank */
10200         I915_WRITE(CURBASE(pipe), base);
10201         POSTING_READ(CURBASE(pipe));
10202
10203         intel_crtc->cursor_base = base;
10204 }
10205
10206 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10207 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10208                                      const struct intel_plane_state *plane_state)
10209 {
10210         struct drm_device *dev = crtc->dev;
10211         struct drm_i915_private *dev_priv = dev->dev_private;
10212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10213         int pipe = intel_crtc->pipe;
10214         u32 base = intel_crtc->cursor_addr;
10215         u32 pos = 0;
10216
10217         if (plane_state) {
10218                 int x = plane_state->base.crtc_x;
10219                 int y = plane_state->base.crtc_y;
10220
10221                 if (x < 0) {
10222                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10223                         x = -x;
10224                 }
10225                 pos |= x << CURSOR_X_SHIFT;
10226
10227                 if (y < 0) {
10228                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10229                         y = -y;
10230                 }
10231                 pos |= y << CURSOR_Y_SHIFT;
10232
10233                 /* ILK+ do this automagically */
10234                 if (HAS_GMCH_DISPLAY(dev) &&
10235                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10236                         base += (plane_state->base.crtc_h *
10237                                  plane_state->base.crtc_w - 1) * 4;
10238                 }
10239         }
10240
10241         I915_WRITE(CURPOS(pipe), pos);
10242
10243         if (IS_845G(dev) || IS_I865G(dev))
10244                 i845_update_cursor(crtc, base, plane_state);
10245         else
10246                 i9xx_update_cursor(crtc, base, plane_state);
10247 }
10248
10249 static bool cursor_size_ok(struct drm_device *dev,
10250                            uint32_t width, uint32_t height)
10251 {
10252         if (width == 0 || height == 0)
10253                 return false;
10254
10255         /*
10256          * 845g/865g are special in that they are only limited by
10257          * the width of their cursors, the height is arbitrary up to
10258          * the precision of the register. Everything else requires
10259          * square cursors, limited to a few power-of-two sizes.
10260          */
10261         if (IS_845G(dev) || IS_I865G(dev)) {
10262                 if ((width & 63) != 0)
10263                         return false;
10264
10265                 if (width > (IS_845G(dev) ? 64 : 512))
10266                         return false;
10267
10268                 if (height > 1023)
10269                         return false;
10270         } else {
10271                 switch (width | height) {
10272                 case 256:
10273                 case 128:
10274                         if (IS_GEN2(dev))
10275                                 return false;
10276                 case 64:
10277                         break;
10278                 default:
10279                         return false;
10280                 }
10281         }
10282
10283         return true;
10284 }
10285
10286 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10287                                  u16 *blue, uint32_t start, uint32_t size)
10288 {
10289         int end = (start + size > 256) ? 256 : start + size, i;
10290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10291
10292         for (i = start; i < end; i++) {
10293                 intel_crtc->lut_r[i] = red[i] >> 8;
10294                 intel_crtc->lut_g[i] = green[i] >> 8;
10295                 intel_crtc->lut_b[i] = blue[i] >> 8;
10296         }
10297
10298         intel_crtc_load_lut(crtc);
10299 }
10300
10301 /* VESA 640x480x72Hz mode to set on the pipe */
10302 static struct drm_display_mode load_detect_mode = {
10303         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10304                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10305 };
10306
10307 struct drm_framebuffer *
10308 __intel_framebuffer_create(struct drm_device *dev,
10309                            struct drm_mode_fb_cmd2 *mode_cmd,
10310                            struct drm_i915_gem_object *obj)
10311 {
10312         struct intel_framebuffer *intel_fb;
10313         int ret;
10314
10315         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10316         if (!intel_fb)
10317                 return ERR_PTR(-ENOMEM);
10318
10319         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10320         if (ret)
10321                 goto err;
10322
10323         return &intel_fb->base;
10324
10325 err:
10326         kfree(intel_fb);
10327         return ERR_PTR(ret);
10328 }
10329
10330 static struct drm_framebuffer *
10331 intel_framebuffer_create(struct drm_device *dev,
10332                          struct drm_mode_fb_cmd2 *mode_cmd,
10333                          struct drm_i915_gem_object *obj)
10334 {
10335         struct drm_framebuffer *fb;
10336         int ret;
10337
10338         ret = i915_mutex_lock_interruptible(dev);
10339         if (ret)
10340                 return ERR_PTR(ret);
10341         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10342         mutex_unlock(&dev->struct_mutex);
10343
10344         return fb;
10345 }
10346
10347 static u32
10348 intel_framebuffer_pitch_for_width(int width, int bpp)
10349 {
10350         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10351         return ALIGN(pitch, 64);
10352 }
10353
10354 static u32
10355 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10356 {
10357         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10358         return PAGE_ALIGN(pitch * mode->vdisplay);
10359 }
10360
10361 static struct drm_framebuffer *
10362 intel_framebuffer_create_for_mode(struct drm_device *dev,
10363                                   struct drm_display_mode *mode,
10364                                   int depth, int bpp)
10365 {
10366         struct drm_framebuffer *fb;
10367         struct drm_i915_gem_object *obj;
10368         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10369
10370         obj = i915_gem_alloc_object(dev,
10371                                     intel_framebuffer_size_for_mode(mode, bpp));
10372         if (obj == NULL)
10373                 return ERR_PTR(-ENOMEM);
10374
10375         mode_cmd.width = mode->hdisplay;
10376         mode_cmd.height = mode->vdisplay;
10377         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10378                                                                 bpp);
10379         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10380
10381         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10382         if (IS_ERR(fb))
10383                 drm_gem_object_unreference_unlocked(&obj->base);
10384
10385         return fb;
10386 }
10387
10388 static struct drm_framebuffer *
10389 mode_fits_in_fbdev(struct drm_device *dev,
10390                    struct drm_display_mode *mode)
10391 {
10392 #ifdef CONFIG_DRM_FBDEV_EMULATION
10393         struct drm_i915_private *dev_priv = dev->dev_private;
10394         struct drm_i915_gem_object *obj;
10395         struct drm_framebuffer *fb;
10396
10397         if (!dev_priv->fbdev)
10398                 return NULL;
10399
10400         if (!dev_priv->fbdev->fb)
10401                 return NULL;
10402
10403         obj = dev_priv->fbdev->fb->obj;
10404         BUG_ON(!obj);
10405
10406         fb = &dev_priv->fbdev->fb->base;
10407         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10408                                                                fb->bits_per_pixel))
10409                 return NULL;
10410
10411         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10412                 return NULL;
10413
10414         return fb;
10415 #else
10416         return NULL;
10417 #endif
10418 }
10419
10420 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10421                                            struct drm_crtc *crtc,
10422                                            struct drm_display_mode *mode,
10423                                            struct drm_framebuffer *fb,
10424                                            int x, int y)
10425 {
10426         struct drm_plane_state *plane_state;
10427         int hdisplay, vdisplay;
10428         int ret;
10429
10430         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10431         if (IS_ERR(plane_state))
10432                 return PTR_ERR(plane_state);
10433
10434         if (mode)
10435                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10436         else
10437                 hdisplay = vdisplay = 0;
10438
10439         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10440         if (ret)
10441                 return ret;
10442         drm_atomic_set_fb_for_plane(plane_state, fb);
10443         plane_state->crtc_x = 0;
10444         plane_state->crtc_y = 0;
10445         plane_state->crtc_w = hdisplay;
10446         plane_state->crtc_h = vdisplay;
10447         plane_state->src_x = x << 16;
10448         plane_state->src_y = y << 16;
10449         plane_state->src_w = hdisplay << 16;
10450         plane_state->src_h = vdisplay << 16;
10451
10452         return 0;
10453 }
10454
10455 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10456                                 struct drm_display_mode *mode,
10457                                 struct intel_load_detect_pipe *old,
10458                                 struct drm_modeset_acquire_ctx *ctx)
10459 {
10460         struct intel_crtc *intel_crtc;
10461         struct intel_encoder *intel_encoder =
10462                 intel_attached_encoder(connector);
10463         struct drm_crtc *possible_crtc;
10464         struct drm_encoder *encoder = &intel_encoder->base;
10465         struct drm_crtc *crtc = NULL;
10466         struct drm_device *dev = encoder->dev;
10467         struct drm_framebuffer *fb;
10468         struct drm_mode_config *config = &dev->mode_config;
10469         struct drm_atomic_state *state = NULL;
10470         struct drm_connector_state *connector_state;
10471         struct intel_crtc_state *crtc_state;
10472         int ret, i = -1;
10473
10474         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10475                       connector->base.id, connector->name,
10476                       encoder->base.id, encoder->name);
10477
10478 retry:
10479         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10480         if (ret)
10481                 goto fail;
10482
10483         /*
10484          * Algorithm gets a little messy:
10485          *
10486          *   - if the connector already has an assigned crtc, use it (but make
10487          *     sure it's on first)
10488          *
10489          *   - try to find the first unused crtc that can drive this connector,
10490          *     and use that if we find one
10491          */
10492
10493         /* See if we already have a CRTC for this connector */
10494         if (encoder->crtc) {
10495                 crtc = encoder->crtc;
10496
10497                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10498                 if (ret)
10499                         goto fail;
10500                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10501                 if (ret)
10502                         goto fail;
10503
10504                 old->dpms_mode = connector->dpms;
10505                 old->load_detect_temp = false;
10506
10507                 /* Make sure the crtc and connector are running */
10508                 if (connector->dpms != DRM_MODE_DPMS_ON)
10509                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10510
10511                 return true;
10512         }
10513
10514         /* Find an unused one (if possible) */
10515         for_each_crtc(dev, possible_crtc) {
10516                 i++;
10517                 if (!(encoder->possible_crtcs & (1 << i)))
10518                         continue;
10519                 if (possible_crtc->state->enable)
10520                         continue;
10521
10522                 crtc = possible_crtc;
10523                 break;
10524         }
10525
10526         /*
10527          * If we didn't find an unused CRTC, don't use any.
10528          */
10529         if (!crtc) {
10530                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10531                 goto fail;
10532         }
10533
10534         ret = drm_modeset_lock(&crtc->mutex, ctx);
10535         if (ret)
10536                 goto fail;
10537         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10538         if (ret)
10539                 goto fail;
10540
10541         intel_crtc = to_intel_crtc(crtc);
10542         old->dpms_mode = connector->dpms;
10543         old->load_detect_temp = true;
10544         old->release_fb = NULL;
10545
10546         state = drm_atomic_state_alloc(dev);
10547         if (!state)
10548                 return false;
10549
10550         state->acquire_ctx = ctx;
10551
10552         connector_state = drm_atomic_get_connector_state(state, connector);
10553         if (IS_ERR(connector_state)) {
10554                 ret = PTR_ERR(connector_state);
10555                 goto fail;
10556         }
10557
10558         connector_state->crtc = crtc;
10559         connector_state->best_encoder = &intel_encoder->base;
10560
10561         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10562         if (IS_ERR(crtc_state)) {
10563                 ret = PTR_ERR(crtc_state);
10564                 goto fail;
10565         }
10566
10567         crtc_state->base.active = crtc_state->base.enable = true;
10568
10569         if (!mode)
10570                 mode = &load_detect_mode;
10571
10572         /* We need a framebuffer large enough to accommodate all accesses
10573          * that the plane may generate whilst we perform load detection.
10574          * We can not rely on the fbcon either being present (we get called
10575          * during its initialisation to detect all boot displays, or it may
10576          * not even exist) or that it is large enough to satisfy the
10577          * requested mode.
10578          */
10579         fb = mode_fits_in_fbdev(dev, mode);
10580         if (fb == NULL) {
10581                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10582                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10583                 old->release_fb = fb;
10584         } else
10585                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10586         if (IS_ERR(fb)) {
10587                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10588                 goto fail;
10589         }
10590
10591         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10592         if (ret)
10593                 goto fail;
10594
10595         drm_mode_copy(&crtc_state->base.mode, mode);
10596
10597         if (drm_atomic_commit(state)) {
10598                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10599                 if (old->release_fb)
10600                         old->release_fb->funcs->destroy(old->release_fb);
10601                 goto fail;
10602         }
10603         crtc->primary->crtc = crtc;
10604
10605         /* let the connector get through one full cycle before testing */
10606         intel_wait_for_vblank(dev, intel_crtc->pipe);
10607         return true;
10608
10609 fail:
10610         drm_atomic_state_free(state);
10611         state = NULL;
10612
10613         if (ret == -EDEADLK) {
10614                 drm_modeset_backoff(ctx);
10615                 goto retry;
10616         }
10617
10618         return false;
10619 }
10620
10621 void intel_release_load_detect_pipe(struct drm_connector *connector,
10622                                     struct intel_load_detect_pipe *old,
10623                                     struct drm_modeset_acquire_ctx *ctx)
10624 {
10625         struct drm_device *dev = connector->dev;
10626         struct intel_encoder *intel_encoder =
10627                 intel_attached_encoder(connector);
10628         struct drm_encoder *encoder = &intel_encoder->base;
10629         struct drm_crtc *crtc = encoder->crtc;
10630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10631         struct drm_atomic_state *state;
10632         struct drm_connector_state *connector_state;
10633         struct intel_crtc_state *crtc_state;
10634         int ret;
10635
10636         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10637                       connector->base.id, connector->name,
10638                       encoder->base.id, encoder->name);
10639
10640         if (old->load_detect_temp) {
10641                 state = drm_atomic_state_alloc(dev);
10642                 if (!state)
10643                         goto fail;
10644
10645                 state->acquire_ctx = ctx;
10646
10647                 connector_state = drm_atomic_get_connector_state(state, connector);
10648                 if (IS_ERR(connector_state))
10649                         goto fail;
10650
10651                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10652                 if (IS_ERR(crtc_state))
10653                         goto fail;
10654
10655                 connector_state->best_encoder = NULL;
10656                 connector_state->crtc = NULL;
10657
10658                 crtc_state->base.enable = crtc_state->base.active = false;
10659
10660                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10661                                                       0, 0);
10662                 if (ret)
10663                         goto fail;
10664
10665                 ret = drm_atomic_commit(state);
10666                 if (ret)
10667                         goto fail;
10668
10669                 if (old->release_fb) {
10670                         drm_framebuffer_unregister_private(old->release_fb);
10671                         drm_framebuffer_unreference(old->release_fb);
10672                 }
10673
10674                 return;
10675         }
10676
10677         /* Switch crtc and encoder back off if necessary */
10678         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10679                 connector->funcs->dpms(connector, old->dpms_mode);
10680
10681         return;
10682 fail:
10683         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10684         drm_atomic_state_free(state);
10685 }
10686
10687 static int i9xx_pll_refclk(struct drm_device *dev,
10688                            const struct intel_crtc_state *pipe_config)
10689 {
10690         struct drm_i915_private *dev_priv = dev->dev_private;
10691         u32 dpll = pipe_config->dpll_hw_state.dpll;
10692
10693         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10694                 return dev_priv->vbt.lvds_ssc_freq;
10695         else if (HAS_PCH_SPLIT(dev))
10696                 return 120000;
10697         else if (!IS_GEN2(dev))
10698                 return 96000;
10699         else
10700                 return 48000;
10701 }
10702
10703 /* Returns the clock of the currently programmed mode of the given pipe. */
10704 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10705                                 struct intel_crtc_state *pipe_config)
10706 {
10707         struct drm_device *dev = crtc->base.dev;
10708         struct drm_i915_private *dev_priv = dev->dev_private;
10709         int pipe = pipe_config->cpu_transcoder;
10710         u32 dpll = pipe_config->dpll_hw_state.dpll;
10711         u32 fp;
10712         intel_clock_t clock;
10713         int port_clock;
10714         int refclk = i9xx_pll_refclk(dev, pipe_config);
10715
10716         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10717                 fp = pipe_config->dpll_hw_state.fp0;
10718         else
10719                 fp = pipe_config->dpll_hw_state.fp1;
10720
10721         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10722         if (IS_PINEVIEW(dev)) {
10723                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10724                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10725         } else {
10726                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10727                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10728         }
10729
10730         if (!IS_GEN2(dev)) {
10731                 if (IS_PINEVIEW(dev))
10732                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10733                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10734                 else
10735                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10736                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10737
10738                 switch (dpll & DPLL_MODE_MASK) {
10739                 case DPLLB_MODE_DAC_SERIAL:
10740                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10741                                 5 : 10;
10742                         break;
10743                 case DPLLB_MODE_LVDS:
10744                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10745                                 7 : 14;
10746                         break;
10747                 default:
10748                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10749                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10750                         return;
10751                 }
10752
10753                 if (IS_PINEVIEW(dev))
10754                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10755                 else
10756                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10757         } else {
10758                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10759                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10760
10761                 if (is_lvds) {
10762                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10763                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10764
10765                         if (lvds & LVDS_CLKB_POWER_UP)
10766                                 clock.p2 = 7;
10767                         else
10768                                 clock.p2 = 14;
10769                 } else {
10770                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10771                                 clock.p1 = 2;
10772                         else {
10773                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10774                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10775                         }
10776                         if (dpll & PLL_P2_DIVIDE_BY_4)
10777                                 clock.p2 = 4;
10778                         else
10779                                 clock.p2 = 2;
10780                 }
10781
10782                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10783         }
10784
10785         /*
10786          * This value includes pixel_multiplier. We will use
10787          * port_clock to compute adjusted_mode.crtc_clock in the
10788          * encoder's get_config() function.
10789          */
10790         pipe_config->port_clock = port_clock;
10791 }
10792
10793 int intel_dotclock_calculate(int link_freq,
10794                              const struct intel_link_m_n *m_n)
10795 {
10796         /*
10797          * The calculation for the data clock is:
10798          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10799          * But we want to avoid losing precison if possible, so:
10800          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10801          *
10802          * and the link clock is simpler:
10803          * link_clock = (m * link_clock) / n
10804          */
10805
10806         if (!m_n->link_n)
10807                 return 0;
10808
10809         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10810 }
10811
10812 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10813                                    struct intel_crtc_state *pipe_config)
10814 {
10815         struct drm_device *dev = crtc->base.dev;
10816
10817         /* read out port_clock from the DPLL */
10818         i9xx_crtc_clock_get(crtc, pipe_config);
10819
10820         /*
10821          * This value does not include pixel_multiplier.
10822          * We will check that port_clock and adjusted_mode.crtc_clock
10823          * agree once we know their relationship in the encoder's
10824          * get_config() function.
10825          */
10826         pipe_config->base.adjusted_mode.crtc_clock =
10827                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10828                                          &pipe_config->fdi_m_n);
10829 }
10830
10831 /** Returns the currently programmed mode of the given pipe. */
10832 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10833                                              struct drm_crtc *crtc)
10834 {
10835         struct drm_i915_private *dev_priv = dev->dev_private;
10836         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10837         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10838         struct drm_display_mode *mode;
10839         struct intel_crtc_state pipe_config;
10840         int htot = I915_READ(HTOTAL(cpu_transcoder));
10841         int hsync = I915_READ(HSYNC(cpu_transcoder));
10842         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10843         int vsync = I915_READ(VSYNC(cpu_transcoder));
10844         enum pipe pipe = intel_crtc->pipe;
10845
10846         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10847         if (!mode)
10848                 return NULL;
10849
10850         /*
10851          * Construct a pipe_config sufficient for getting the clock info
10852          * back out of crtc_clock_get.
10853          *
10854          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10855          * to use a real value here instead.
10856          */
10857         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10858         pipe_config.pixel_multiplier = 1;
10859         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10860         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10861         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10862         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10863
10864         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10865         mode->hdisplay = (htot & 0xffff) + 1;
10866         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10867         mode->hsync_start = (hsync & 0xffff) + 1;
10868         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10869         mode->vdisplay = (vtot & 0xffff) + 1;
10870         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10871         mode->vsync_start = (vsync & 0xffff) + 1;
10872         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10873
10874         drm_mode_set_name(mode);
10875
10876         return mode;
10877 }
10878
10879 void intel_mark_busy(struct drm_device *dev)
10880 {
10881         struct drm_i915_private *dev_priv = dev->dev_private;
10882
10883         if (dev_priv->mm.busy)
10884                 return;
10885
10886         intel_runtime_pm_get(dev_priv);
10887         i915_update_gfx_val(dev_priv);
10888         if (INTEL_INFO(dev)->gen >= 6)
10889                 gen6_rps_busy(dev_priv);
10890         dev_priv->mm.busy = true;
10891 }
10892
10893 void intel_mark_idle(struct drm_device *dev)
10894 {
10895         struct drm_i915_private *dev_priv = dev->dev_private;
10896
10897         if (!dev_priv->mm.busy)
10898                 return;
10899
10900         dev_priv->mm.busy = false;
10901
10902         if (INTEL_INFO(dev)->gen >= 6)
10903                 gen6_rps_idle(dev->dev_private);
10904
10905         intel_runtime_pm_put(dev_priv);
10906 }
10907
10908 static void intel_crtc_destroy(struct drm_crtc *crtc)
10909 {
10910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10911         struct drm_device *dev = crtc->dev;
10912         struct intel_unpin_work *work;
10913
10914         spin_lock_irq(&dev->event_lock);
10915         work = intel_crtc->unpin_work;
10916         intel_crtc->unpin_work = NULL;
10917         spin_unlock_irq(&dev->event_lock);
10918
10919         if (work) {
10920                 cancel_work_sync(&work->work);
10921                 kfree(work);
10922         }
10923
10924         drm_crtc_cleanup(crtc);
10925
10926         kfree(intel_crtc);
10927 }
10928
10929 static void intel_unpin_work_fn(struct work_struct *__work)
10930 {
10931         struct intel_unpin_work *work =
10932                 container_of(__work, struct intel_unpin_work, work);
10933         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10934         struct drm_device *dev = crtc->base.dev;
10935         struct drm_plane *primary = crtc->base.primary;
10936
10937         mutex_lock(&dev->struct_mutex);
10938         intel_unpin_fb_obj(work->old_fb, primary->state);
10939         drm_gem_object_unreference(&work->pending_flip_obj->base);
10940
10941         if (work->flip_queued_req)
10942                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10943         mutex_unlock(&dev->struct_mutex);
10944
10945         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10946         drm_framebuffer_unreference(work->old_fb);
10947
10948         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10949         atomic_dec(&crtc->unpin_work_count);
10950
10951         kfree(work);
10952 }
10953
10954 static void do_intel_finish_page_flip(struct drm_device *dev,
10955                                       struct drm_crtc *crtc)
10956 {
10957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10958         struct intel_unpin_work *work;
10959         unsigned long flags;
10960
10961         /* Ignore early vblank irqs */
10962         if (intel_crtc == NULL)
10963                 return;
10964
10965         /*
10966          * This is called both by irq handlers and the reset code (to complete
10967          * lost pageflips) so needs the full irqsave spinlocks.
10968          */
10969         spin_lock_irqsave(&dev->event_lock, flags);
10970         work = intel_crtc->unpin_work;
10971
10972         /* Ensure we don't miss a work->pending update ... */
10973         smp_rmb();
10974
10975         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10976                 spin_unlock_irqrestore(&dev->event_lock, flags);
10977                 return;
10978         }
10979
10980         page_flip_completed(intel_crtc);
10981
10982         spin_unlock_irqrestore(&dev->event_lock, flags);
10983 }
10984
10985 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10986 {
10987         struct drm_i915_private *dev_priv = dev->dev_private;
10988         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10989
10990         do_intel_finish_page_flip(dev, crtc);
10991 }
10992
10993 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10994 {
10995         struct drm_i915_private *dev_priv = dev->dev_private;
10996         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10997
10998         do_intel_finish_page_flip(dev, crtc);
10999 }
11000
11001 /* Is 'a' after or equal to 'b'? */
11002 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11003 {
11004         return !((a - b) & 0x80000000);
11005 }
11006
11007 static bool page_flip_finished(struct intel_crtc *crtc)
11008 {
11009         struct drm_device *dev = crtc->base.dev;
11010         struct drm_i915_private *dev_priv = dev->dev_private;
11011
11012         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
11013             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
11014                 return true;
11015
11016         /*
11017          * The relevant registers doen't exist on pre-ctg.
11018          * As the flip done interrupt doesn't trigger for mmio
11019          * flips on gmch platforms, a flip count check isn't
11020          * really needed there. But since ctg has the registers,
11021          * include it in the check anyway.
11022          */
11023         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11024                 return true;
11025
11026         /*
11027          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11028          * used the same base address. In that case the mmio flip might
11029          * have completed, but the CS hasn't even executed the flip yet.
11030          *
11031          * A flip count check isn't enough as the CS might have updated
11032          * the base address just after start of vblank, but before we
11033          * managed to process the interrupt. This means we'd complete the
11034          * CS flip too soon.
11035          *
11036          * Combining both checks should get us a good enough result. It may
11037          * still happen that the CS flip has been executed, but has not
11038          * yet actually completed. But in case the base address is the same
11039          * anyway, we don't really care.
11040          */
11041         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11042                 crtc->unpin_work->gtt_offset &&
11043                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11044                                     crtc->unpin_work->flip_count);
11045 }
11046
11047 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11048 {
11049         struct drm_i915_private *dev_priv = dev->dev_private;
11050         struct intel_crtc *intel_crtc =
11051                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11052         unsigned long flags;
11053
11054
11055         /*
11056          * This is called both by irq handlers and the reset code (to complete
11057          * lost pageflips) so needs the full irqsave spinlocks.
11058          *
11059          * NB: An MMIO update of the plane base pointer will also
11060          * generate a page-flip completion irq, i.e. every modeset
11061          * is also accompanied by a spurious intel_prepare_page_flip().
11062          */
11063         spin_lock_irqsave(&dev->event_lock, flags);
11064         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11065                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11066         spin_unlock_irqrestore(&dev->event_lock, flags);
11067 }
11068
11069 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11070 {
11071         /* Ensure that the work item is consistent when activating it ... */
11072         smp_wmb();
11073         atomic_set(&work->pending, INTEL_FLIP_PENDING);
11074         /* and that it is marked active as soon as the irq could fire. */
11075         smp_wmb();
11076 }
11077
11078 static int intel_gen2_queue_flip(struct drm_device *dev,
11079                                  struct drm_crtc *crtc,
11080                                  struct drm_framebuffer *fb,
11081                                  struct drm_i915_gem_object *obj,
11082                                  struct drm_i915_gem_request *req,
11083                                  uint32_t flags)
11084 {
11085         struct intel_engine_cs *ring = req->ring;
11086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11087         u32 flip_mask;
11088         int ret;
11089
11090         ret = intel_ring_begin(req, 6);
11091         if (ret)
11092                 return ret;
11093
11094         /* Can't queue multiple flips, so wait for the previous
11095          * one to finish before executing the next.
11096          */
11097         if (intel_crtc->plane)
11098                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11099         else
11100                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11101         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11102         intel_ring_emit(ring, MI_NOOP);
11103         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11104                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11105         intel_ring_emit(ring, fb->pitches[0]);
11106         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11107         intel_ring_emit(ring, 0); /* aux display base address, unused */
11108
11109         intel_mark_page_flip_active(intel_crtc->unpin_work);
11110         return 0;
11111 }
11112
11113 static int intel_gen3_queue_flip(struct drm_device *dev,
11114                                  struct drm_crtc *crtc,
11115                                  struct drm_framebuffer *fb,
11116                                  struct drm_i915_gem_object *obj,
11117                                  struct drm_i915_gem_request *req,
11118                                  uint32_t flags)
11119 {
11120         struct intel_engine_cs *ring = req->ring;
11121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11122         u32 flip_mask;
11123         int ret;
11124
11125         ret = intel_ring_begin(req, 6);
11126         if (ret)
11127                 return ret;
11128
11129         if (intel_crtc->plane)
11130                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11131         else
11132                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11133         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11134         intel_ring_emit(ring, MI_NOOP);
11135         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11136                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11137         intel_ring_emit(ring, fb->pitches[0]);
11138         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11139         intel_ring_emit(ring, MI_NOOP);
11140
11141         intel_mark_page_flip_active(intel_crtc->unpin_work);
11142         return 0;
11143 }
11144
11145 static int intel_gen4_queue_flip(struct drm_device *dev,
11146                                  struct drm_crtc *crtc,
11147                                  struct drm_framebuffer *fb,
11148                                  struct drm_i915_gem_object *obj,
11149                                  struct drm_i915_gem_request *req,
11150                                  uint32_t flags)
11151 {
11152         struct intel_engine_cs *ring = req->ring;
11153         struct drm_i915_private *dev_priv = dev->dev_private;
11154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11155         uint32_t pf, pipesrc;
11156         int ret;
11157
11158         ret = intel_ring_begin(req, 4);
11159         if (ret)
11160                 return ret;
11161
11162         /* i965+ uses the linear or tiled offsets from the
11163          * Display Registers (which do not change across a page-flip)
11164          * so we need only reprogram the base address.
11165          */
11166         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11167                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11168         intel_ring_emit(ring, fb->pitches[0]);
11169         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11170                         obj->tiling_mode);
11171
11172         /* XXX Enabling the panel-fitter across page-flip is so far
11173          * untested on non-native modes, so ignore it for now.
11174          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11175          */
11176         pf = 0;
11177         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11178         intel_ring_emit(ring, pf | pipesrc);
11179
11180         intel_mark_page_flip_active(intel_crtc->unpin_work);
11181         return 0;
11182 }
11183
11184 static int intel_gen6_queue_flip(struct drm_device *dev,
11185                                  struct drm_crtc *crtc,
11186                                  struct drm_framebuffer *fb,
11187                                  struct drm_i915_gem_object *obj,
11188                                  struct drm_i915_gem_request *req,
11189                                  uint32_t flags)
11190 {
11191         struct intel_engine_cs *ring = req->ring;
11192         struct drm_i915_private *dev_priv = dev->dev_private;
11193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11194         uint32_t pf, pipesrc;
11195         int ret;
11196
11197         ret = intel_ring_begin(req, 4);
11198         if (ret)
11199                 return ret;
11200
11201         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11202                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11203         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11204         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11205
11206         /* Contrary to the suggestions in the documentation,
11207          * "Enable Panel Fitter" does not seem to be required when page
11208          * flipping with a non-native mode, and worse causes a normal
11209          * modeset to fail.
11210          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11211          */
11212         pf = 0;
11213         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11214         intel_ring_emit(ring, pf | pipesrc);
11215
11216         intel_mark_page_flip_active(intel_crtc->unpin_work);
11217         return 0;
11218 }
11219
11220 static int intel_gen7_queue_flip(struct drm_device *dev,
11221                                  struct drm_crtc *crtc,
11222                                  struct drm_framebuffer *fb,
11223                                  struct drm_i915_gem_object *obj,
11224                                  struct drm_i915_gem_request *req,
11225                                  uint32_t flags)
11226 {
11227         struct intel_engine_cs *ring = req->ring;
11228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11229         uint32_t plane_bit = 0;
11230         int len, ret;
11231
11232         switch (intel_crtc->plane) {
11233         case PLANE_A:
11234                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11235                 break;
11236         case PLANE_B:
11237                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11238                 break;
11239         case PLANE_C:
11240                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11241                 break;
11242         default:
11243                 WARN_ONCE(1, "unknown plane in flip command\n");
11244                 return -ENODEV;
11245         }
11246
11247         len = 4;
11248         if (ring->id == RCS) {
11249                 len += 6;
11250                 /*
11251                  * On Gen 8, SRM is now taking an extra dword to accommodate
11252                  * 48bits addresses, and we need a NOOP for the batch size to
11253                  * stay even.
11254                  */
11255                 if (IS_GEN8(dev))
11256                         len += 2;
11257         }
11258
11259         /*
11260          * BSpec MI_DISPLAY_FLIP for IVB:
11261          * "The full packet must be contained within the same cache line."
11262          *
11263          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11264          * cacheline, if we ever start emitting more commands before
11265          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11266          * then do the cacheline alignment, and finally emit the
11267          * MI_DISPLAY_FLIP.
11268          */
11269         ret = intel_ring_cacheline_align(req);
11270         if (ret)
11271                 return ret;
11272
11273         ret = intel_ring_begin(req, len);
11274         if (ret)
11275                 return ret;
11276
11277         /* Unmask the flip-done completion message. Note that the bspec says that
11278          * we should do this for both the BCS and RCS, and that we must not unmask
11279          * more than one flip event at any time (or ensure that one flip message
11280          * can be sent by waiting for flip-done prior to queueing new flips).
11281          * Experimentation says that BCS works despite DERRMR masking all
11282          * flip-done completion events and that unmasking all planes at once
11283          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11284          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11285          */
11286         if (ring->id == RCS) {
11287                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11288                 intel_ring_emit_reg(ring, DERRMR);
11289                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11290                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11291                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11292                 if (IS_GEN8(dev))
11293                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11294                                               MI_SRM_LRM_GLOBAL_GTT);
11295                 else
11296                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11297                                               MI_SRM_LRM_GLOBAL_GTT);
11298                 intel_ring_emit_reg(ring, DERRMR);
11299                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11300                 if (IS_GEN8(dev)) {
11301                         intel_ring_emit(ring, 0);
11302                         intel_ring_emit(ring, MI_NOOP);
11303                 }
11304         }
11305
11306         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11307         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11308         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11309         intel_ring_emit(ring, (MI_NOOP));
11310
11311         intel_mark_page_flip_active(intel_crtc->unpin_work);
11312         return 0;
11313 }
11314
11315 static bool use_mmio_flip(struct intel_engine_cs *ring,
11316                           struct drm_i915_gem_object *obj)
11317 {
11318         /*
11319          * This is not being used for older platforms, because
11320          * non-availability of flip done interrupt forces us to use
11321          * CS flips. Older platforms derive flip done using some clever
11322          * tricks involving the flip_pending status bits and vblank irqs.
11323          * So using MMIO flips there would disrupt this mechanism.
11324          */
11325
11326         if (ring == NULL)
11327                 return true;
11328
11329         if (INTEL_INFO(ring->dev)->gen < 5)
11330                 return false;
11331
11332         if (i915.use_mmio_flip < 0)
11333                 return false;
11334         else if (i915.use_mmio_flip > 0)
11335                 return true;
11336         else if (i915.enable_execlists)
11337                 return true;
11338         else if (obj->base.dma_buf &&
11339                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11340                                                        false))
11341                 return true;
11342         else
11343                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11344 }
11345
11346 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11347                              unsigned int rotation,
11348                              struct intel_unpin_work *work)
11349 {
11350         struct drm_device *dev = intel_crtc->base.dev;
11351         struct drm_i915_private *dev_priv = dev->dev_private;
11352         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11353         const enum pipe pipe = intel_crtc->pipe;
11354         u32 ctl, stride, tile_height;
11355
11356         ctl = I915_READ(PLANE_CTL(pipe, 0));
11357         ctl &= ~PLANE_CTL_TILED_MASK;
11358         switch (fb->modifier[0]) {
11359         case DRM_FORMAT_MOD_NONE:
11360                 break;
11361         case I915_FORMAT_MOD_X_TILED:
11362                 ctl |= PLANE_CTL_TILED_X;
11363                 break;
11364         case I915_FORMAT_MOD_Y_TILED:
11365                 ctl |= PLANE_CTL_TILED_Y;
11366                 break;
11367         case I915_FORMAT_MOD_Yf_TILED:
11368                 ctl |= PLANE_CTL_TILED_YF;
11369                 break;
11370         default:
11371                 MISSING_CASE(fb->modifier[0]);
11372         }
11373
11374         /*
11375          * The stride is either expressed as a multiple of 64 bytes chunks for
11376          * linear buffers or in number of tiles for tiled buffers.
11377          */
11378         if (intel_rotation_90_or_270(rotation)) {
11379                 /* stride = Surface height in tiles */
11380                 tile_height = intel_tile_height(dev, fb->pixel_format,
11381                                                 fb->modifier[0], 0);
11382                 stride = DIV_ROUND_UP(fb->height, tile_height);
11383         } else {
11384                 stride = fb->pitches[0] /
11385                                 intel_fb_stride_alignment(dev, fb->modifier[0],
11386                                                           fb->pixel_format);
11387         }
11388
11389         /*
11390          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11391          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11392          */
11393         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11394         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11395
11396         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11397         POSTING_READ(PLANE_SURF(pipe, 0));
11398 }
11399
11400 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11401                              struct intel_unpin_work *work)
11402 {
11403         struct drm_device *dev = intel_crtc->base.dev;
11404         struct drm_i915_private *dev_priv = dev->dev_private;
11405         struct intel_framebuffer *intel_fb =
11406                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11407         struct drm_i915_gem_object *obj = intel_fb->obj;
11408         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11409         u32 dspcntr;
11410
11411         dspcntr = I915_READ(reg);
11412
11413         if (obj->tiling_mode != I915_TILING_NONE)
11414                 dspcntr |= DISPPLANE_TILED;
11415         else
11416                 dspcntr &= ~DISPPLANE_TILED;
11417
11418         I915_WRITE(reg, dspcntr);
11419
11420         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11421         POSTING_READ(DSPSURF(intel_crtc->plane));
11422 }
11423
11424 /*
11425  * XXX: This is the temporary way to update the plane registers until we get
11426  * around to using the usual plane update functions for MMIO flips
11427  */
11428 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11429 {
11430         struct intel_crtc *crtc = mmio_flip->crtc;
11431         struct intel_unpin_work *work;
11432
11433         spin_lock_irq(&crtc->base.dev->event_lock);
11434         work = crtc->unpin_work;
11435         spin_unlock_irq(&crtc->base.dev->event_lock);
11436         if (work == NULL)
11437                 return;
11438
11439         intel_mark_page_flip_active(work);
11440
11441         intel_pipe_update_start(crtc);
11442
11443         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11444                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11445         else
11446                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11447                 ilk_do_mmio_flip(crtc, work);
11448
11449         intel_pipe_update_end(crtc);
11450 }
11451
11452 static void intel_mmio_flip_work_func(struct work_struct *work)
11453 {
11454         struct intel_mmio_flip *mmio_flip =
11455                 container_of(work, struct intel_mmio_flip, work);
11456         struct intel_framebuffer *intel_fb =
11457                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11458         struct drm_i915_gem_object *obj = intel_fb->obj;
11459
11460         if (mmio_flip->req) {
11461                 WARN_ON(__i915_wait_request(mmio_flip->req,
11462                                             mmio_flip->crtc->reset_counter,
11463                                             false, NULL,
11464                                             &mmio_flip->i915->rps.mmioflips));
11465                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11466         }
11467
11468         /* For framebuffer backed by dmabuf, wait for fence */
11469         if (obj->base.dma_buf)
11470                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11471                                                             false, false,
11472                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11473
11474         intel_do_mmio_flip(mmio_flip);
11475         kfree(mmio_flip);
11476 }
11477
11478 static int intel_queue_mmio_flip(struct drm_device *dev,
11479                                  struct drm_crtc *crtc,
11480                                  struct drm_i915_gem_object *obj)
11481 {
11482         struct intel_mmio_flip *mmio_flip;
11483
11484         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11485         if (mmio_flip == NULL)
11486                 return -ENOMEM;
11487
11488         mmio_flip->i915 = to_i915(dev);
11489         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11490         mmio_flip->crtc = to_intel_crtc(crtc);
11491         mmio_flip->rotation = crtc->primary->state->rotation;
11492
11493         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11494         schedule_work(&mmio_flip->work);
11495
11496         return 0;
11497 }
11498
11499 static int intel_default_queue_flip(struct drm_device *dev,
11500                                     struct drm_crtc *crtc,
11501                                     struct drm_framebuffer *fb,
11502                                     struct drm_i915_gem_object *obj,
11503                                     struct drm_i915_gem_request *req,
11504                                     uint32_t flags)
11505 {
11506         return -ENODEV;
11507 }
11508
11509 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11510                                          struct drm_crtc *crtc)
11511 {
11512         struct drm_i915_private *dev_priv = dev->dev_private;
11513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11514         struct intel_unpin_work *work = intel_crtc->unpin_work;
11515         u32 addr;
11516
11517         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11518                 return true;
11519
11520         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11521                 return false;
11522
11523         if (!work->enable_stall_check)
11524                 return false;
11525
11526         if (work->flip_ready_vblank == 0) {
11527                 if (work->flip_queued_req &&
11528                     !i915_gem_request_completed(work->flip_queued_req, true))
11529                         return false;
11530
11531                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11532         }
11533
11534         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11535                 return false;
11536
11537         /* Potential stall - if we see that the flip has happened,
11538          * assume a missed interrupt. */
11539         if (INTEL_INFO(dev)->gen >= 4)
11540                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11541         else
11542                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11543
11544         /* There is a potential issue here with a false positive after a flip
11545          * to the same address. We could address this by checking for a
11546          * non-incrementing frame counter.
11547          */
11548         return addr == work->gtt_offset;
11549 }
11550
11551 void intel_check_page_flip(struct drm_device *dev, int pipe)
11552 {
11553         struct drm_i915_private *dev_priv = dev->dev_private;
11554         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11556         struct intel_unpin_work *work;
11557
11558         WARN_ON(!in_interrupt());
11559
11560         if (crtc == NULL)
11561                 return;
11562
11563         spin_lock(&dev->event_lock);
11564         work = intel_crtc->unpin_work;
11565         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11566                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11567                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11568                 page_flip_completed(intel_crtc);
11569                 work = NULL;
11570         }
11571         if (work != NULL &&
11572             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11573                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11574         spin_unlock(&dev->event_lock);
11575 }
11576
11577 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11578                                 struct drm_framebuffer *fb,
11579                                 struct drm_pending_vblank_event *event,
11580                                 uint32_t page_flip_flags)
11581 {
11582         struct drm_device *dev = crtc->dev;
11583         struct drm_i915_private *dev_priv = dev->dev_private;
11584         struct drm_framebuffer *old_fb = crtc->primary->fb;
11585         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11587         struct drm_plane *primary = crtc->primary;
11588         enum pipe pipe = intel_crtc->pipe;
11589         struct intel_unpin_work *work;
11590         struct intel_engine_cs *ring;
11591         bool mmio_flip;
11592         struct drm_i915_gem_request *request = NULL;
11593         int ret;
11594
11595         /*
11596          * drm_mode_page_flip_ioctl() should already catch this, but double
11597          * check to be safe.  In the future we may enable pageflipping from
11598          * a disabled primary plane.
11599          */
11600         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11601                 return -EBUSY;
11602
11603         /* Can't change pixel format via MI display flips. */
11604         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11605                 return -EINVAL;
11606
11607         /*
11608          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11609          * Note that pitch changes could also affect these register.
11610          */
11611         if (INTEL_INFO(dev)->gen > 3 &&
11612             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11613              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11614                 return -EINVAL;
11615
11616         if (i915_terminally_wedged(&dev_priv->gpu_error))
11617                 goto out_hang;
11618
11619         work = kzalloc(sizeof(*work), GFP_KERNEL);
11620         if (work == NULL)
11621                 return -ENOMEM;
11622
11623         work->event = event;
11624         work->crtc = crtc;
11625         work->old_fb = old_fb;
11626         INIT_WORK(&work->work, intel_unpin_work_fn);
11627
11628         ret = drm_crtc_vblank_get(crtc);
11629         if (ret)
11630                 goto free_work;
11631
11632         /* We borrow the event spin lock for protecting unpin_work */
11633         spin_lock_irq(&dev->event_lock);
11634         if (intel_crtc->unpin_work) {
11635                 /* Before declaring the flip queue wedged, check if
11636                  * the hardware completed the operation behind our backs.
11637                  */
11638                 if (__intel_pageflip_stall_check(dev, crtc)) {
11639                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11640                         page_flip_completed(intel_crtc);
11641                 } else {
11642                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11643                         spin_unlock_irq(&dev->event_lock);
11644
11645                         drm_crtc_vblank_put(crtc);
11646                         kfree(work);
11647                         return -EBUSY;
11648                 }
11649         }
11650         intel_crtc->unpin_work = work;
11651         spin_unlock_irq(&dev->event_lock);
11652
11653         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11654                 flush_workqueue(dev_priv->wq);
11655
11656         /* Reference the objects for the scheduled work. */
11657         drm_framebuffer_reference(work->old_fb);
11658         drm_gem_object_reference(&obj->base);
11659
11660         crtc->primary->fb = fb;
11661         update_state_fb(crtc->primary);
11662
11663         work->pending_flip_obj = obj;
11664
11665         ret = i915_mutex_lock_interruptible(dev);
11666         if (ret)
11667                 goto cleanup;
11668
11669         atomic_inc(&intel_crtc->unpin_work_count);
11670         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11671
11672         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11673                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11674
11675         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11676                 ring = &dev_priv->ring[BCS];
11677                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11678                         /* vlv: DISPLAY_FLIP fails to change tiling */
11679                         ring = NULL;
11680         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11681                 ring = &dev_priv->ring[BCS];
11682         } else if (INTEL_INFO(dev)->gen >= 7) {
11683                 ring = i915_gem_request_get_ring(obj->last_write_req);
11684                 if (ring == NULL || ring->id != RCS)
11685                         ring = &dev_priv->ring[BCS];
11686         } else {
11687                 ring = &dev_priv->ring[RCS];
11688         }
11689
11690         mmio_flip = use_mmio_flip(ring, obj);
11691
11692         /* When using CS flips, we want to emit semaphores between rings.
11693          * However, when using mmio flips we will create a task to do the
11694          * synchronisation, so all we want here is to pin the framebuffer
11695          * into the display plane and skip any waits.
11696          */
11697         if (!mmio_flip) {
11698                 ret = i915_gem_object_sync(obj, ring, &request);
11699                 if (ret)
11700                         goto cleanup_pending;
11701         }
11702
11703         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11704                                          crtc->primary->state);
11705         if (ret)
11706                 goto cleanup_pending;
11707
11708         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11709                                                   obj, 0);
11710         work->gtt_offset += intel_crtc->dspaddr_offset;
11711
11712         if (mmio_flip) {
11713                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11714                 if (ret)
11715                         goto cleanup_unpin;
11716
11717                 i915_gem_request_assign(&work->flip_queued_req,
11718                                         obj->last_write_req);
11719         } else {
11720                 if (!request) {
11721                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11722                         if (ret)
11723                                 goto cleanup_unpin;
11724                 }
11725
11726                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11727                                                    page_flip_flags);
11728                 if (ret)
11729                         goto cleanup_unpin;
11730
11731                 i915_gem_request_assign(&work->flip_queued_req, request);
11732         }
11733
11734         if (request)
11735                 i915_add_request_no_flush(request);
11736
11737         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11738         work->enable_stall_check = true;
11739
11740         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11741                           to_intel_plane(primary)->frontbuffer_bit);
11742         mutex_unlock(&dev->struct_mutex);
11743
11744         intel_fbc_deactivate(intel_crtc);
11745         intel_frontbuffer_flip_prepare(dev,
11746                                        to_intel_plane(primary)->frontbuffer_bit);
11747
11748         trace_i915_flip_request(intel_crtc->plane, obj);
11749
11750         return 0;
11751
11752 cleanup_unpin:
11753         intel_unpin_fb_obj(fb, crtc->primary->state);
11754 cleanup_pending:
11755         if (request)
11756                 i915_gem_request_cancel(request);
11757         atomic_dec(&intel_crtc->unpin_work_count);
11758         mutex_unlock(&dev->struct_mutex);
11759 cleanup:
11760         crtc->primary->fb = old_fb;
11761         update_state_fb(crtc->primary);
11762
11763         drm_gem_object_unreference_unlocked(&obj->base);
11764         drm_framebuffer_unreference(work->old_fb);
11765
11766         spin_lock_irq(&dev->event_lock);
11767         intel_crtc->unpin_work = NULL;
11768         spin_unlock_irq(&dev->event_lock);
11769
11770         drm_crtc_vblank_put(crtc);
11771 free_work:
11772         kfree(work);
11773
11774         if (ret == -EIO) {
11775                 struct drm_atomic_state *state;
11776                 struct drm_plane_state *plane_state;
11777
11778 out_hang:
11779                 state = drm_atomic_state_alloc(dev);
11780                 if (!state)
11781                         return -ENOMEM;
11782                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11783
11784 retry:
11785                 plane_state = drm_atomic_get_plane_state(state, primary);
11786                 ret = PTR_ERR_OR_ZERO(plane_state);
11787                 if (!ret) {
11788                         drm_atomic_set_fb_for_plane(plane_state, fb);
11789
11790                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11791                         if (!ret)
11792                                 ret = drm_atomic_commit(state);
11793                 }
11794
11795                 if (ret == -EDEADLK) {
11796                         drm_modeset_backoff(state->acquire_ctx);
11797                         drm_atomic_state_clear(state);
11798                         goto retry;
11799                 }
11800
11801                 if (ret)
11802                         drm_atomic_state_free(state);
11803
11804                 if (ret == 0 && event) {
11805                         spin_lock_irq(&dev->event_lock);
11806                         drm_send_vblank_event(dev, pipe, event);
11807                         spin_unlock_irq(&dev->event_lock);
11808                 }
11809         }
11810         return ret;
11811 }
11812
11813
11814 /**
11815  * intel_wm_need_update - Check whether watermarks need updating
11816  * @plane: drm plane
11817  * @state: new plane state
11818  *
11819  * Check current plane state versus the new one to determine whether
11820  * watermarks need to be recalculated.
11821  *
11822  * Returns true or false.
11823  */
11824 static bool intel_wm_need_update(struct drm_plane *plane,
11825                                  struct drm_plane_state *state)
11826 {
11827         struct intel_plane_state *new = to_intel_plane_state(state);
11828         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11829
11830         /* Update watermarks on tiling or size changes. */
11831         if (new->visible != cur->visible)
11832                 return true;
11833
11834         if (!cur->base.fb || !new->base.fb)
11835                 return false;
11836
11837         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11838             cur->base.rotation != new->base.rotation ||
11839             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11840             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11841             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11842             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11843                 return true;
11844
11845         return false;
11846 }
11847
11848 static bool needs_scaling(struct intel_plane_state *state)
11849 {
11850         int src_w = drm_rect_width(&state->src) >> 16;
11851         int src_h = drm_rect_height(&state->src) >> 16;
11852         int dst_w = drm_rect_width(&state->dst);
11853         int dst_h = drm_rect_height(&state->dst);
11854
11855         return (src_w != dst_w || src_h != dst_h);
11856 }
11857
11858 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11859                                     struct drm_plane_state *plane_state)
11860 {
11861         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11862         struct drm_crtc *crtc = crtc_state->crtc;
11863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11864         struct drm_plane *plane = plane_state->plane;
11865         struct drm_device *dev = crtc->dev;
11866         struct drm_i915_private *dev_priv = dev->dev_private;
11867         struct intel_plane_state *old_plane_state =
11868                 to_intel_plane_state(plane->state);
11869         int idx = intel_crtc->base.base.id, ret;
11870         int i = drm_plane_index(plane);
11871         bool mode_changed = needs_modeset(crtc_state);
11872         bool was_crtc_enabled = crtc->state->active;
11873         bool is_crtc_enabled = crtc_state->active;
11874         bool turn_off, turn_on, visible, was_visible;
11875         struct drm_framebuffer *fb = plane_state->fb;
11876
11877         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11878             plane->type != DRM_PLANE_TYPE_CURSOR) {
11879                 ret = skl_update_scaler_plane(
11880                         to_intel_crtc_state(crtc_state),
11881                         to_intel_plane_state(plane_state));
11882                 if (ret)
11883                         return ret;
11884         }
11885
11886         was_visible = old_plane_state->visible;
11887         visible = to_intel_plane_state(plane_state)->visible;
11888
11889         if (!was_crtc_enabled && WARN_ON(was_visible))
11890                 was_visible = false;
11891
11892         /*
11893          * Visibility is calculated as if the crtc was on, but
11894          * after scaler setup everything depends on it being off
11895          * when the crtc isn't active.
11896          */
11897         if (!is_crtc_enabled)
11898                 to_intel_plane_state(plane_state)->visible = visible = false;
11899
11900         if (!was_visible && !visible)
11901                 return 0;
11902
11903         turn_off = was_visible && (!visible || mode_changed);
11904         turn_on = visible && (!was_visible || mode_changed);
11905
11906         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11907                          plane->base.id, fb ? fb->base.id : -1);
11908
11909         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11910                          plane->base.id, was_visible, visible,
11911                          turn_off, turn_on, mode_changed);
11912
11913         if (turn_on || turn_off) {
11914                 pipe_config->wm_changed = true;
11915
11916                 /* must disable cxsr around plane enable/disable */
11917                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11918                         if (is_crtc_enabled)
11919                                 intel_crtc->atomic.wait_vblank = true;
11920                         pipe_config->disable_cxsr = true;
11921                 }
11922         } else if (intel_wm_need_update(plane, plane_state)) {
11923                 pipe_config->wm_changed = true;
11924         }
11925
11926         /* Pre-gen9 platforms need two-step watermark updates */
11927         if (pipe_config->wm_changed && INTEL_INFO(dev)->gen < 9 &&
11928             dev_priv->display.optimize_watermarks)
11929                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11930
11931         if (visible || was_visible)
11932                 intel_crtc->atomic.fb_bits |=
11933                         to_intel_plane(plane)->frontbuffer_bit;
11934
11935         switch (plane->type) {
11936         case DRM_PLANE_TYPE_PRIMARY:
11937                 intel_crtc->atomic.pre_disable_primary = turn_off;
11938                 intel_crtc->atomic.post_enable_primary = turn_on;
11939
11940                 if (turn_off) {
11941                         /*
11942                          * FIXME: Actually if we will still have any other
11943                          * plane enabled on the pipe we could let IPS enabled
11944                          * still, but for now lets consider that when we make
11945                          * primary invisible by setting DSPCNTR to 0 on
11946                          * update_primary_plane function IPS needs to be
11947                          * disable.
11948                          */
11949                         intel_crtc->atomic.disable_ips = true;
11950
11951                         intel_crtc->atomic.disable_fbc = true;
11952                 }
11953
11954                 /*
11955                  * FBC does not work on some platforms for rotated
11956                  * planes, so disable it when rotation is not 0 and
11957                  * update it when rotation is set back to 0.
11958                  *
11959                  * FIXME: This is redundant with the fbc update done in
11960                  * the primary plane enable function except that that
11961                  * one is done too late. We eventually need to unify
11962                  * this.
11963                  */
11964
11965                 if (visible &&
11966                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11967                     dev_priv->fbc.crtc == intel_crtc &&
11968                     plane_state->rotation != BIT(DRM_ROTATE_0))
11969                         intel_crtc->atomic.disable_fbc = true;
11970
11971                 /*
11972                  * BDW signals flip done immediately if the plane
11973                  * is disabled, even if the plane enable is already
11974                  * armed to occur at the next vblank :(
11975                  */
11976                 if (turn_on && IS_BROADWELL(dev))
11977                         intel_crtc->atomic.wait_vblank = true;
11978
11979                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11980                 break;
11981         case DRM_PLANE_TYPE_CURSOR:
11982                 break;
11983         case DRM_PLANE_TYPE_OVERLAY:
11984                 /*
11985                  * WaCxSRDisabledForSpriteScaling:ivb
11986                  *
11987                  * cstate->update_wm was already set above, so this flag will
11988                  * take effect when we commit and program watermarks.
11989                  */
11990                 if (IS_IVYBRIDGE(dev) &&
11991                     needs_scaling(to_intel_plane_state(plane_state)) &&
11992                     !needs_scaling(old_plane_state)) {
11993                         to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11994                 } else if (turn_off && !mode_changed) {
11995                         intel_crtc->atomic.wait_vblank = true;
11996                         intel_crtc->atomic.update_sprite_watermarks |=
11997                                 1 << i;
11998                 }
11999
12000                 break;
12001         }
12002         return 0;
12003 }
12004
12005 static bool encoders_cloneable(const struct intel_encoder *a,
12006                                const struct intel_encoder *b)
12007 {
12008         /* masks could be asymmetric, so check both ways */
12009         return a == b || (a->cloneable & (1 << b->type) &&
12010                           b->cloneable & (1 << a->type));
12011 }
12012
12013 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12014                                          struct intel_crtc *crtc,
12015                                          struct intel_encoder *encoder)
12016 {
12017         struct intel_encoder *source_encoder;
12018         struct drm_connector *connector;
12019         struct drm_connector_state *connector_state;
12020         int i;
12021
12022         for_each_connector_in_state(state, connector, connector_state, i) {
12023                 if (connector_state->crtc != &crtc->base)
12024                         continue;
12025
12026                 source_encoder =
12027                         to_intel_encoder(connector_state->best_encoder);
12028                 if (!encoders_cloneable(encoder, source_encoder))
12029                         return false;
12030         }
12031
12032         return true;
12033 }
12034
12035 static bool check_encoder_cloning(struct drm_atomic_state *state,
12036                                   struct intel_crtc *crtc)
12037 {
12038         struct intel_encoder *encoder;
12039         struct drm_connector *connector;
12040         struct drm_connector_state *connector_state;
12041         int i;
12042
12043         for_each_connector_in_state(state, connector, connector_state, i) {
12044                 if (connector_state->crtc != &crtc->base)
12045                         continue;
12046
12047                 encoder = to_intel_encoder(connector_state->best_encoder);
12048                 if (!check_single_encoder_cloning(state, crtc, encoder))
12049                         return false;
12050         }
12051
12052         return true;
12053 }
12054
12055 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12056                                    struct drm_crtc_state *crtc_state)
12057 {
12058         struct drm_device *dev = crtc->dev;
12059         struct drm_i915_private *dev_priv = dev->dev_private;
12060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12061         struct intel_crtc_state *pipe_config =
12062                 to_intel_crtc_state(crtc_state);
12063         struct drm_atomic_state *state = crtc_state->state;
12064         int ret;
12065         bool mode_changed = needs_modeset(crtc_state);
12066
12067         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12068                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12069                 return -EINVAL;
12070         }
12071
12072         if (mode_changed && !crtc_state->active)
12073                 pipe_config->wm_changed = true;
12074
12075         if (mode_changed && crtc_state->enable &&
12076             dev_priv->display.crtc_compute_clock &&
12077             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12078                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12079                                                            pipe_config);
12080                 if (ret)
12081                         return ret;
12082         }
12083
12084         ret = 0;
12085         if (dev_priv->display.compute_pipe_wm) {
12086                 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12087                 if (ret) {
12088                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12089                         return ret;
12090                 }
12091         }
12092
12093         if (dev_priv->display.compute_intermediate_wm &&
12094             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12095                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12096                         return 0;
12097
12098                 /*
12099                  * Calculate 'intermediate' watermarks that satisfy both the
12100                  * old state and the new state.  We can program these
12101                  * immediately.
12102                  */
12103                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12104                                                                 intel_crtc,
12105                                                                 pipe_config);
12106                 if (ret) {
12107                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12108                         return ret;
12109                 }
12110         }
12111
12112         if (INTEL_INFO(dev)->gen >= 9) {
12113                 if (mode_changed)
12114                         ret = skl_update_scaler_crtc(pipe_config);
12115
12116                 if (!ret)
12117                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12118                                                          pipe_config);
12119         }
12120
12121         return ret;
12122 }
12123
12124 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12125         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12126         .load_lut = intel_crtc_load_lut,
12127         .atomic_begin = intel_begin_crtc_commit,
12128         .atomic_flush = intel_finish_crtc_commit,
12129         .atomic_check = intel_crtc_atomic_check,
12130 };
12131
12132 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12133 {
12134         struct intel_connector *connector;
12135
12136         for_each_intel_connector(dev, connector) {
12137                 if (connector->base.encoder) {
12138                         connector->base.state->best_encoder =
12139                                 connector->base.encoder;
12140                         connector->base.state->crtc =
12141                                 connector->base.encoder->crtc;
12142                 } else {
12143                         connector->base.state->best_encoder = NULL;
12144                         connector->base.state->crtc = NULL;
12145                 }
12146         }
12147 }
12148
12149 static void
12150 connected_sink_compute_bpp(struct intel_connector *connector,
12151                            struct intel_crtc_state *pipe_config)
12152 {
12153         int bpp = pipe_config->pipe_bpp;
12154
12155         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12156                 connector->base.base.id,
12157                 connector->base.name);
12158
12159         /* Don't use an invalid EDID bpc value */
12160         if (connector->base.display_info.bpc &&
12161             connector->base.display_info.bpc * 3 < bpp) {
12162                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12163                               bpp, connector->base.display_info.bpc*3);
12164                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12165         }
12166
12167         /* Clamp bpp to 8 on screens without EDID 1.4 */
12168         if (connector->base.display_info.bpc == 0 && bpp > 24) {
12169                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12170                               bpp);
12171                 pipe_config->pipe_bpp = 24;
12172         }
12173 }
12174
12175 static int
12176 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12177                           struct intel_crtc_state *pipe_config)
12178 {
12179         struct drm_device *dev = crtc->base.dev;
12180         struct drm_atomic_state *state;
12181         struct drm_connector *connector;
12182         struct drm_connector_state *connector_state;
12183         int bpp, i;
12184
12185         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12186                 bpp = 10*3;
12187         else if (INTEL_INFO(dev)->gen >= 5)
12188                 bpp = 12*3;
12189         else
12190                 bpp = 8*3;
12191
12192
12193         pipe_config->pipe_bpp = bpp;
12194
12195         state = pipe_config->base.state;
12196
12197         /* Clamp display bpp to EDID value */
12198         for_each_connector_in_state(state, connector, connector_state, i) {
12199                 if (connector_state->crtc != &crtc->base)
12200                         continue;
12201
12202                 connected_sink_compute_bpp(to_intel_connector(connector),
12203                                            pipe_config);
12204         }
12205
12206         return bpp;
12207 }
12208
12209 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12210 {
12211         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12212                         "type: 0x%x flags: 0x%x\n",
12213                 mode->crtc_clock,
12214                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12215                 mode->crtc_hsync_end, mode->crtc_htotal,
12216                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12217                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12218 }
12219
12220 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12221                                    struct intel_crtc_state *pipe_config,
12222                                    const char *context)
12223 {
12224         struct drm_device *dev = crtc->base.dev;
12225         struct drm_plane *plane;
12226         struct intel_plane *intel_plane;
12227         struct intel_plane_state *state;
12228         struct drm_framebuffer *fb;
12229
12230         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12231                       context, pipe_config, pipe_name(crtc->pipe));
12232
12233         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12234         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12235                       pipe_config->pipe_bpp, pipe_config->dither);
12236         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12237                       pipe_config->has_pch_encoder,
12238                       pipe_config->fdi_lanes,
12239                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12240                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12241                       pipe_config->fdi_m_n.tu);
12242         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12243                       pipe_config->has_dp_encoder,
12244                       pipe_config->lane_count,
12245                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12246                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12247                       pipe_config->dp_m_n.tu);
12248
12249         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12250                       pipe_config->has_dp_encoder,
12251                       pipe_config->lane_count,
12252                       pipe_config->dp_m2_n2.gmch_m,
12253                       pipe_config->dp_m2_n2.gmch_n,
12254                       pipe_config->dp_m2_n2.link_m,
12255                       pipe_config->dp_m2_n2.link_n,
12256                       pipe_config->dp_m2_n2.tu);
12257
12258         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12259                       pipe_config->has_audio,
12260                       pipe_config->has_infoframe);
12261
12262         DRM_DEBUG_KMS("requested mode:\n");
12263         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12264         DRM_DEBUG_KMS("adjusted mode:\n");
12265         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12266         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12267         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12268         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12269                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12270         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12271                       crtc->num_scalers,
12272                       pipe_config->scaler_state.scaler_users,
12273                       pipe_config->scaler_state.scaler_id);
12274         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12275                       pipe_config->gmch_pfit.control,
12276                       pipe_config->gmch_pfit.pgm_ratios,
12277                       pipe_config->gmch_pfit.lvds_border_bits);
12278         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12279                       pipe_config->pch_pfit.pos,
12280                       pipe_config->pch_pfit.size,
12281                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12282         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12283         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12284
12285         if (IS_BROXTON(dev)) {
12286                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12287                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12288                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12289                               pipe_config->ddi_pll_sel,
12290                               pipe_config->dpll_hw_state.ebb0,
12291                               pipe_config->dpll_hw_state.ebb4,
12292                               pipe_config->dpll_hw_state.pll0,
12293                               pipe_config->dpll_hw_state.pll1,
12294                               pipe_config->dpll_hw_state.pll2,
12295                               pipe_config->dpll_hw_state.pll3,
12296                               pipe_config->dpll_hw_state.pll6,
12297                               pipe_config->dpll_hw_state.pll8,
12298                               pipe_config->dpll_hw_state.pll9,
12299                               pipe_config->dpll_hw_state.pll10,
12300                               pipe_config->dpll_hw_state.pcsdw12);
12301         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12302                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12303                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12304                               pipe_config->ddi_pll_sel,
12305                               pipe_config->dpll_hw_state.ctrl1,
12306                               pipe_config->dpll_hw_state.cfgcr1,
12307                               pipe_config->dpll_hw_state.cfgcr2);
12308         } else if (HAS_DDI(dev)) {
12309                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12310                               pipe_config->ddi_pll_sel,
12311                               pipe_config->dpll_hw_state.wrpll,
12312                               pipe_config->dpll_hw_state.spll);
12313         } else {
12314                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12315                               "fp0: 0x%x, fp1: 0x%x\n",
12316                               pipe_config->dpll_hw_state.dpll,
12317                               pipe_config->dpll_hw_state.dpll_md,
12318                               pipe_config->dpll_hw_state.fp0,
12319                               pipe_config->dpll_hw_state.fp1);
12320         }
12321
12322         DRM_DEBUG_KMS("planes on this crtc\n");
12323         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12324                 intel_plane = to_intel_plane(plane);
12325                 if (intel_plane->pipe != crtc->pipe)
12326                         continue;
12327
12328                 state = to_intel_plane_state(plane->state);
12329                 fb = state->base.fb;
12330                 if (!fb) {
12331                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12332                                 "disabled, scaler_id = %d\n",
12333                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12334                                 plane->base.id, intel_plane->pipe,
12335                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12336                                 drm_plane_index(plane), state->scaler_id);
12337                         continue;
12338                 }
12339
12340                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12341                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12342                         plane->base.id, intel_plane->pipe,
12343                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12344                         drm_plane_index(plane));
12345                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12346                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12347                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12348                         state->scaler_id,
12349                         state->src.x1 >> 16, state->src.y1 >> 16,
12350                         drm_rect_width(&state->src) >> 16,
12351                         drm_rect_height(&state->src) >> 16,
12352                         state->dst.x1, state->dst.y1,
12353                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12354         }
12355 }
12356
12357 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12358 {
12359         struct drm_device *dev = state->dev;
12360         struct drm_connector *connector;
12361         unsigned int used_ports = 0;
12362
12363         /*
12364          * Walk the connector list instead of the encoder
12365          * list to detect the problem on ddi platforms
12366          * where there's just one encoder per digital port.
12367          */
12368         drm_for_each_connector(connector, dev) {
12369                 struct drm_connector_state *connector_state;
12370                 struct intel_encoder *encoder;
12371
12372                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12373                 if (!connector_state)
12374                         connector_state = connector->state;
12375
12376                 if (!connector_state->best_encoder)
12377                         continue;
12378
12379                 encoder = to_intel_encoder(connector_state->best_encoder);
12380
12381                 WARN_ON(!connector_state->crtc);
12382
12383                 switch (encoder->type) {
12384                         unsigned int port_mask;
12385                 case INTEL_OUTPUT_UNKNOWN:
12386                         if (WARN_ON(!HAS_DDI(dev)))
12387                                 break;
12388                 case INTEL_OUTPUT_DISPLAYPORT:
12389                 case INTEL_OUTPUT_HDMI:
12390                 case INTEL_OUTPUT_EDP:
12391                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12392
12393                         /* the same port mustn't appear more than once */
12394                         if (used_ports & port_mask)
12395                                 return false;
12396
12397                         used_ports |= port_mask;
12398                 default:
12399                         break;
12400                 }
12401         }
12402
12403         return true;
12404 }
12405
12406 static void
12407 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12408 {
12409         struct drm_crtc_state tmp_state;
12410         struct intel_crtc_scaler_state scaler_state;
12411         struct intel_dpll_hw_state dpll_hw_state;
12412         enum intel_dpll_id shared_dpll;
12413         uint32_t ddi_pll_sel;
12414         bool force_thru;
12415
12416         /* FIXME: before the switch to atomic started, a new pipe_config was
12417          * kzalloc'd. Code that depends on any field being zero should be
12418          * fixed, so that the crtc_state can be safely duplicated. For now,
12419          * only fields that are know to not cause problems are preserved. */
12420
12421         tmp_state = crtc_state->base;
12422         scaler_state = crtc_state->scaler_state;
12423         shared_dpll = crtc_state->shared_dpll;
12424         dpll_hw_state = crtc_state->dpll_hw_state;
12425         ddi_pll_sel = crtc_state->ddi_pll_sel;
12426         force_thru = crtc_state->pch_pfit.force_thru;
12427
12428         memset(crtc_state, 0, sizeof *crtc_state);
12429
12430         crtc_state->base = tmp_state;
12431         crtc_state->scaler_state = scaler_state;
12432         crtc_state->shared_dpll = shared_dpll;
12433         crtc_state->dpll_hw_state = dpll_hw_state;
12434         crtc_state->ddi_pll_sel = ddi_pll_sel;
12435         crtc_state->pch_pfit.force_thru = force_thru;
12436 }
12437
12438 static int
12439 intel_modeset_pipe_config(struct drm_crtc *crtc,
12440                           struct intel_crtc_state *pipe_config)
12441 {
12442         struct drm_atomic_state *state = pipe_config->base.state;
12443         struct intel_encoder *encoder;
12444         struct drm_connector *connector;
12445         struct drm_connector_state *connector_state;
12446         int base_bpp, ret = -EINVAL;
12447         int i;
12448         bool retry = true;
12449
12450         clear_intel_crtc_state(pipe_config);
12451
12452         pipe_config->cpu_transcoder =
12453                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12454
12455         /*
12456          * Sanitize sync polarity flags based on requested ones. If neither
12457          * positive or negative polarity is requested, treat this as meaning
12458          * negative polarity.
12459          */
12460         if (!(pipe_config->base.adjusted_mode.flags &
12461               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12462                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12463
12464         if (!(pipe_config->base.adjusted_mode.flags &
12465               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12466                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12467
12468         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12469                                              pipe_config);
12470         if (base_bpp < 0)
12471                 goto fail;
12472
12473         /*
12474          * Determine the real pipe dimensions. Note that stereo modes can
12475          * increase the actual pipe size due to the frame doubling and
12476          * insertion of additional space for blanks between the frame. This
12477          * is stored in the crtc timings. We use the requested mode to do this
12478          * computation to clearly distinguish it from the adjusted mode, which
12479          * can be changed by the connectors in the below retry loop.
12480          */
12481         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12482                                &pipe_config->pipe_src_w,
12483                                &pipe_config->pipe_src_h);
12484
12485 encoder_retry:
12486         /* Ensure the port clock defaults are reset when retrying. */
12487         pipe_config->port_clock = 0;
12488         pipe_config->pixel_multiplier = 1;
12489
12490         /* Fill in default crtc timings, allow encoders to overwrite them. */
12491         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12492                               CRTC_STEREO_DOUBLE);
12493
12494         /* Pass our mode to the connectors and the CRTC to give them a chance to
12495          * adjust it according to limitations or connector properties, and also
12496          * a chance to reject the mode entirely.
12497          */
12498         for_each_connector_in_state(state, connector, connector_state, i) {
12499                 if (connector_state->crtc != crtc)
12500                         continue;
12501
12502                 encoder = to_intel_encoder(connector_state->best_encoder);
12503
12504                 if (!(encoder->compute_config(encoder, pipe_config))) {
12505                         DRM_DEBUG_KMS("Encoder config failure\n");
12506                         goto fail;
12507                 }
12508         }
12509
12510         /* Set default port clock if not overwritten by the encoder. Needs to be
12511          * done afterwards in case the encoder adjusts the mode. */
12512         if (!pipe_config->port_clock)
12513                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12514                         * pipe_config->pixel_multiplier;
12515
12516         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12517         if (ret < 0) {
12518                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12519                 goto fail;
12520         }
12521
12522         if (ret == RETRY) {
12523                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12524                         ret = -EINVAL;
12525                         goto fail;
12526                 }
12527
12528                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12529                 retry = false;
12530                 goto encoder_retry;
12531         }
12532
12533         /* Dithering seems to not pass-through bits correctly when it should, so
12534          * only enable it on 6bpc panels. */
12535         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12536         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12537                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12538
12539 fail:
12540         return ret;
12541 }
12542
12543 static void
12544 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12545 {
12546         struct drm_crtc *crtc;
12547         struct drm_crtc_state *crtc_state;
12548         int i;
12549
12550         /* Double check state. */
12551         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12552                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12553
12554                 /* Update hwmode for vblank functions */
12555                 if (crtc->state->active)
12556                         crtc->hwmode = crtc->state->adjusted_mode;
12557                 else
12558                         crtc->hwmode.crtc_clock = 0;
12559
12560                 /*
12561                  * Update legacy state to satisfy fbc code. This can
12562                  * be removed when fbc uses the atomic state.
12563                  */
12564                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12565                         struct drm_plane_state *plane_state = crtc->primary->state;
12566
12567                         crtc->primary->fb = plane_state->fb;
12568                         crtc->x = plane_state->src_x >> 16;
12569                         crtc->y = plane_state->src_y >> 16;
12570                 }
12571         }
12572 }
12573
12574 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12575 {
12576         int diff;
12577
12578         if (clock1 == clock2)
12579                 return true;
12580
12581         if (!clock1 || !clock2)
12582                 return false;
12583
12584         diff = abs(clock1 - clock2);
12585
12586         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12587                 return true;
12588
12589         return false;
12590 }
12591
12592 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12593         list_for_each_entry((intel_crtc), \
12594                             &(dev)->mode_config.crtc_list, \
12595                             base.head) \
12596                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12597
12598 static bool
12599 intel_compare_m_n(unsigned int m, unsigned int n,
12600                   unsigned int m2, unsigned int n2,
12601                   bool exact)
12602 {
12603         if (m == m2 && n == n2)
12604                 return true;
12605
12606         if (exact || !m || !n || !m2 || !n2)
12607                 return false;
12608
12609         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12610
12611         if (n > n2) {
12612                 while (n > n2) {
12613                         m2 <<= 1;
12614                         n2 <<= 1;
12615                 }
12616         } else if (n < n2) {
12617                 while (n < n2) {
12618                         m <<= 1;
12619                         n <<= 1;
12620                 }
12621         }
12622
12623         if (n != n2)
12624                 return false;
12625
12626         return intel_fuzzy_clock_check(m, m2);
12627 }
12628
12629 static bool
12630 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12631                        struct intel_link_m_n *m2_n2,
12632                        bool adjust)
12633 {
12634         if (m_n->tu == m2_n2->tu &&
12635             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12636                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12637             intel_compare_m_n(m_n->link_m, m_n->link_n,
12638                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12639                 if (adjust)
12640                         *m2_n2 = *m_n;
12641
12642                 return true;
12643         }
12644
12645         return false;
12646 }
12647
12648 static bool
12649 intel_pipe_config_compare(struct drm_device *dev,
12650                           struct intel_crtc_state *current_config,
12651                           struct intel_crtc_state *pipe_config,
12652                           bool adjust)
12653 {
12654         bool ret = true;
12655
12656 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12657         do { \
12658                 if (!adjust) \
12659                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12660                 else \
12661                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12662         } while (0)
12663
12664 #define PIPE_CONF_CHECK_X(name) \
12665         if (current_config->name != pipe_config->name) { \
12666                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12667                           "(expected 0x%08x, found 0x%08x)\n", \
12668                           current_config->name, \
12669                           pipe_config->name); \
12670                 ret = false; \
12671         }
12672
12673 #define PIPE_CONF_CHECK_I(name) \
12674         if (current_config->name != pipe_config->name) { \
12675                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12676                           "(expected %i, found %i)\n", \
12677                           current_config->name, \
12678                           pipe_config->name); \
12679                 ret = false; \
12680         }
12681
12682 #define PIPE_CONF_CHECK_M_N(name) \
12683         if (!intel_compare_link_m_n(&current_config->name, \
12684                                     &pipe_config->name,\
12685                                     adjust)) { \
12686                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12687                           "(expected tu %i gmch %i/%i link %i/%i, " \
12688                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12689                           current_config->name.tu, \
12690                           current_config->name.gmch_m, \
12691                           current_config->name.gmch_n, \
12692                           current_config->name.link_m, \
12693                           current_config->name.link_n, \
12694                           pipe_config->name.tu, \
12695                           pipe_config->name.gmch_m, \
12696                           pipe_config->name.gmch_n, \
12697                           pipe_config->name.link_m, \
12698                           pipe_config->name.link_n); \
12699                 ret = false; \
12700         }
12701
12702 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12703         if (!intel_compare_link_m_n(&current_config->name, \
12704                                     &pipe_config->name, adjust) && \
12705             !intel_compare_link_m_n(&current_config->alt_name, \
12706                                     &pipe_config->name, adjust)) { \
12707                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12708                           "(expected tu %i gmch %i/%i link %i/%i, " \
12709                           "or tu %i gmch %i/%i link %i/%i, " \
12710                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12711                           current_config->name.tu, \
12712                           current_config->name.gmch_m, \
12713                           current_config->name.gmch_n, \
12714                           current_config->name.link_m, \
12715                           current_config->name.link_n, \
12716                           current_config->alt_name.tu, \
12717                           current_config->alt_name.gmch_m, \
12718                           current_config->alt_name.gmch_n, \
12719                           current_config->alt_name.link_m, \
12720                           current_config->alt_name.link_n, \
12721                           pipe_config->name.tu, \
12722                           pipe_config->name.gmch_m, \
12723                           pipe_config->name.gmch_n, \
12724                           pipe_config->name.link_m, \
12725                           pipe_config->name.link_n); \
12726                 ret = false; \
12727         }
12728
12729 /* This is required for BDW+ where there is only one set of registers for
12730  * switching between high and low RR.
12731  * This macro can be used whenever a comparison has to be made between one
12732  * hw state and multiple sw state variables.
12733  */
12734 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12735         if ((current_config->name != pipe_config->name) && \
12736                 (current_config->alt_name != pipe_config->name)) { \
12737                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12738                                   "(expected %i or %i, found %i)\n", \
12739                                   current_config->name, \
12740                                   current_config->alt_name, \
12741                                   pipe_config->name); \
12742                         ret = false; \
12743         }
12744
12745 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12746         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12747                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12748                           "(expected %i, found %i)\n", \
12749                           current_config->name & (mask), \
12750                           pipe_config->name & (mask)); \
12751                 ret = false; \
12752         }
12753
12754 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12755         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12756                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12757                           "(expected %i, found %i)\n", \
12758                           current_config->name, \
12759                           pipe_config->name); \
12760                 ret = false; \
12761         }
12762
12763 #define PIPE_CONF_QUIRK(quirk)  \
12764         ((current_config->quirks | pipe_config->quirks) & (quirk))
12765
12766         PIPE_CONF_CHECK_I(cpu_transcoder);
12767
12768         PIPE_CONF_CHECK_I(has_pch_encoder);
12769         PIPE_CONF_CHECK_I(fdi_lanes);
12770         PIPE_CONF_CHECK_M_N(fdi_m_n);
12771
12772         PIPE_CONF_CHECK_I(has_dp_encoder);
12773         PIPE_CONF_CHECK_I(lane_count);
12774
12775         if (INTEL_INFO(dev)->gen < 8) {
12776                 PIPE_CONF_CHECK_M_N(dp_m_n);
12777
12778                 if (current_config->has_drrs)
12779                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12780         } else
12781                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12782
12783         PIPE_CONF_CHECK_I(has_dsi_encoder);
12784
12785         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12786         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12787         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12788         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12789         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12790         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12791
12792         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12793         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12794         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12795         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12796         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12797         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12798
12799         PIPE_CONF_CHECK_I(pixel_multiplier);
12800         PIPE_CONF_CHECK_I(has_hdmi_sink);
12801         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12802             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12803                 PIPE_CONF_CHECK_I(limited_color_range);
12804         PIPE_CONF_CHECK_I(has_infoframe);
12805
12806         PIPE_CONF_CHECK_I(has_audio);
12807
12808         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12809                               DRM_MODE_FLAG_INTERLACE);
12810
12811         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12812                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12813                                       DRM_MODE_FLAG_PHSYNC);
12814                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12815                                       DRM_MODE_FLAG_NHSYNC);
12816                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12817                                       DRM_MODE_FLAG_PVSYNC);
12818                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12819                                       DRM_MODE_FLAG_NVSYNC);
12820         }
12821
12822         PIPE_CONF_CHECK_X(gmch_pfit.control);
12823         /* pfit ratios are autocomputed by the hw on gen4+ */
12824         if (INTEL_INFO(dev)->gen < 4)
12825                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12826         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12827
12828         if (!adjust) {
12829                 PIPE_CONF_CHECK_I(pipe_src_w);
12830                 PIPE_CONF_CHECK_I(pipe_src_h);
12831
12832                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12833                 if (current_config->pch_pfit.enabled) {
12834                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12835                         PIPE_CONF_CHECK_X(pch_pfit.size);
12836                 }
12837
12838                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12839         }
12840
12841         /* BDW+ don't expose a synchronous way to read the state */
12842         if (IS_HASWELL(dev))
12843                 PIPE_CONF_CHECK_I(ips_enabled);
12844
12845         PIPE_CONF_CHECK_I(double_wide);
12846
12847         PIPE_CONF_CHECK_X(ddi_pll_sel);
12848
12849         PIPE_CONF_CHECK_I(shared_dpll);
12850         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12851         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12852         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12853         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12854         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12855         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12856         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12857         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12858         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12859
12860         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12861                 PIPE_CONF_CHECK_I(pipe_bpp);
12862
12863         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12864         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12865
12866 #undef PIPE_CONF_CHECK_X
12867 #undef PIPE_CONF_CHECK_I
12868 #undef PIPE_CONF_CHECK_I_ALT
12869 #undef PIPE_CONF_CHECK_FLAGS
12870 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12871 #undef PIPE_CONF_QUIRK
12872 #undef INTEL_ERR_OR_DBG_KMS
12873
12874         return ret;
12875 }
12876
12877 static void check_wm_state(struct drm_device *dev)
12878 {
12879         struct drm_i915_private *dev_priv = dev->dev_private;
12880         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12881         struct intel_crtc *intel_crtc;
12882         int plane;
12883
12884         if (INTEL_INFO(dev)->gen < 9)
12885                 return;
12886
12887         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12888         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12889
12890         for_each_intel_crtc(dev, intel_crtc) {
12891                 struct skl_ddb_entry *hw_entry, *sw_entry;
12892                 const enum pipe pipe = intel_crtc->pipe;
12893
12894                 if (!intel_crtc->active)
12895                         continue;
12896
12897                 /* planes */
12898                 for_each_plane(dev_priv, pipe, plane) {
12899                         hw_entry = &hw_ddb.plane[pipe][plane];
12900                         sw_entry = &sw_ddb->plane[pipe][plane];
12901
12902                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12903                                 continue;
12904
12905                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12906                                   "(expected (%u,%u), found (%u,%u))\n",
12907                                   pipe_name(pipe), plane + 1,
12908                                   sw_entry->start, sw_entry->end,
12909                                   hw_entry->start, hw_entry->end);
12910                 }
12911
12912                 /* cursor */
12913                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12914                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12915
12916                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12917                         continue;
12918
12919                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12920                           "(expected (%u,%u), found (%u,%u))\n",
12921                           pipe_name(pipe),
12922                           sw_entry->start, sw_entry->end,
12923                           hw_entry->start, hw_entry->end);
12924         }
12925 }
12926
12927 static void
12928 check_connector_state(struct drm_device *dev,
12929                       struct drm_atomic_state *old_state)
12930 {
12931         struct drm_connector_state *old_conn_state;
12932         struct drm_connector *connector;
12933         int i;
12934
12935         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12936                 struct drm_encoder *encoder = connector->encoder;
12937                 struct drm_connector_state *state = connector->state;
12938
12939                 /* This also checks the encoder/connector hw state with the
12940                  * ->get_hw_state callbacks. */
12941                 intel_connector_check_state(to_intel_connector(connector));
12942
12943                 I915_STATE_WARN(state->best_encoder != encoder,
12944                      "connector's atomic encoder doesn't match legacy encoder\n");
12945         }
12946 }
12947
12948 static void
12949 check_encoder_state(struct drm_device *dev)
12950 {
12951         struct intel_encoder *encoder;
12952         struct intel_connector *connector;
12953
12954         for_each_intel_encoder(dev, encoder) {
12955                 bool enabled = false;
12956                 enum pipe pipe;
12957
12958                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12959                               encoder->base.base.id,
12960                               encoder->base.name);
12961
12962                 for_each_intel_connector(dev, connector) {
12963                         if (connector->base.state->best_encoder != &encoder->base)
12964                                 continue;
12965                         enabled = true;
12966
12967                         I915_STATE_WARN(connector->base.state->crtc !=
12968                                         encoder->base.crtc,
12969                              "connector's crtc doesn't match encoder crtc\n");
12970                 }
12971
12972                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12973                      "encoder's enabled state mismatch "
12974                      "(expected %i, found %i)\n",
12975                      !!encoder->base.crtc, enabled);
12976
12977                 if (!encoder->base.crtc) {
12978                         bool active;
12979
12980                         active = encoder->get_hw_state(encoder, &pipe);
12981                         I915_STATE_WARN(active,
12982                              "encoder detached but still enabled on pipe %c.\n",
12983                              pipe_name(pipe));
12984                 }
12985         }
12986 }
12987
12988 static void
12989 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12990 {
12991         struct drm_i915_private *dev_priv = dev->dev_private;
12992         struct intel_encoder *encoder;
12993         struct drm_crtc_state *old_crtc_state;
12994         struct drm_crtc *crtc;
12995         int i;
12996
12997         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12998                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12999                 struct intel_crtc_state *pipe_config, *sw_config;
13000                 bool active;
13001
13002                 if (!needs_modeset(crtc->state) &&
13003                     !to_intel_crtc_state(crtc->state)->update_pipe)
13004                         continue;
13005
13006                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
13007                 pipe_config = to_intel_crtc_state(old_crtc_state);
13008                 memset(pipe_config, 0, sizeof(*pipe_config));
13009                 pipe_config->base.crtc = crtc;
13010                 pipe_config->base.state = old_state;
13011
13012                 DRM_DEBUG_KMS("[CRTC:%d]\n",
13013                               crtc->base.id);
13014
13015                 active = dev_priv->display.get_pipe_config(intel_crtc,
13016                                                            pipe_config);
13017
13018                 /* hw state is inconsistent with the pipe quirk */
13019                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13020                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13021                         active = crtc->state->active;
13022
13023                 I915_STATE_WARN(crtc->state->active != active,
13024                      "crtc active state doesn't match with hw state "
13025                      "(expected %i, found %i)\n", crtc->state->active, active);
13026
13027                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
13028                      "transitional active state does not match atomic hw state "
13029                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
13030
13031                 for_each_encoder_on_crtc(dev, crtc, encoder) {
13032                         enum pipe pipe;
13033
13034                         active = encoder->get_hw_state(encoder, &pipe);
13035                         I915_STATE_WARN(active != crtc->state->active,
13036                                 "[ENCODER:%i] active %i with crtc active %i\n",
13037                                 encoder->base.base.id, active, crtc->state->active);
13038
13039                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13040                                         "Encoder connected to wrong pipe %c\n",
13041                                         pipe_name(pipe));
13042
13043                         if (active)
13044                                 encoder->get_config(encoder, pipe_config);
13045                 }
13046
13047                 if (!crtc->state->active)
13048                         continue;
13049
13050                 sw_config = to_intel_crtc_state(crtc->state);
13051                 if (!intel_pipe_config_compare(dev, sw_config,
13052                                                pipe_config, false)) {
13053                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
13054                         intel_dump_pipe_config(intel_crtc, pipe_config,
13055                                                "[hw state]");
13056                         intel_dump_pipe_config(intel_crtc, sw_config,
13057                                                "[sw state]");
13058                 }
13059         }
13060 }
13061
13062 static void
13063 check_shared_dpll_state(struct drm_device *dev)
13064 {
13065         struct drm_i915_private *dev_priv = dev->dev_private;
13066         struct intel_crtc *crtc;
13067         struct intel_dpll_hw_state dpll_hw_state;
13068         int i;
13069
13070         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13071                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13072                 int enabled_crtcs = 0, active_crtcs = 0;
13073                 bool active;
13074
13075                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13076
13077                 DRM_DEBUG_KMS("%s\n", pll->name);
13078
13079                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
13080
13081                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
13082                      "more active pll users than references: %i vs %i\n",
13083                      pll->active, hweight32(pll->config.crtc_mask));
13084                 I915_STATE_WARN(pll->active && !pll->on,
13085                      "pll in active use but not on in sw tracking\n");
13086                 I915_STATE_WARN(pll->on && !pll->active,
13087                      "pll in on but not on in use in sw tracking\n");
13088                 I915_STATE_WARN(pll->on != active,
13089                      "pll on state mismatch (expected %i, found %i)\n",
13090                      pll->on, active);
13091
13092                 for_each_intel_crtc(dev, crtc) {
13093                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
13094                                 enabled_crtcs++;
13095                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13096                                 active_crtcs++;
13097                 }
13098                 I915_STATE_WARN(pll->active != active_crtcs,
13099                      "pll active crtcs mismatch (expected %i, found %i)\n",
13100                      pll->active, active_crtcs);
13101                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
13102                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
13103                      hweight32(pll->config.crtc_mask), enabled_crtcs);
13104
13105                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13106                                        sizeof(dpll_hw_state)),
13107                      "pll hw state mismatch\n");
13108         }
13109 }
13110
13111 static void
13112 intel_modeset_check_state(struct drm_device *dev,
13113                           struct drm_atomic_state *old_state)
13114 {
13115         check_wm_state(dev);
13116         check_connector_state(dev, old_state);
13117         check_encoder_state(dev);
13118         check_crtc_state(dev, old_state);
13119         check_shared_dpll_state(dev);
13120 }
13121
13122 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13123                                      int dotclock)
13124 {
13125         /*
13126          * FDI already provided one idea for the dotclock.
13127          * Yell if the encoder disagrees.
13128          */
13129         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13130              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13131              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13132 }
13133
13134 static void update_scanline_offset(struct intel_crtc *crtc)
13135 {
13136         struct drm_device *dev = crtc->base.dev;
13137
13138         /*
13139          * The scanline counter increments at the leading edge of hsync.
13140          *
13141          * On most platforms it starts counting from vtotal-1 on the
13142          * first active line. That means the scanline counter value is
13143          * always one less than what we would expect. Ie. just after
13144          * start of vblank, which also occurs at start of hsync (on the
13145          * last active line), the scanline counter will read vblank_start-1.
13146          *
13147          * On gen2 the scanline counter starts counting from 1 instead
13148          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13149          * to keep the value positive), instead of adding one.
13150          *
13151          * On HSW+ the behaviour of the scanline counter depends on the output
13152          * type. For DP ports it behaves like most other platforms, but on HDMI
13153          * there's an extra 1 line difference. So we need to add two instead of
13154          * one to the value.
13155          */
13156         if (IS_GEN2(dev)) {
13157                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13158                 int vtotal;
13159
13160                 vtotal = adjusted_mode->crtc_vtotal;
13161                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13162                         vtotal /= 2;
13163
13164                 crtc->scanline_offset = vtotal - 1;
13165         } else if (HAS_DDI(dev) &&
13166                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13167                 crtc->scanline_offset = 2;
13168         } else
13169                 crtc->scanline_offset = 1;
13170 }
13171
13172 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13173 {
13174         struct drm_device *dev = state->dev;
13175         struct drm_i915_private *dev_priv = to_i915(dev);
13176         struct intel_shared_dpll_config *shared_dpll = NULL;
13177         struct intel_crtc *intel_crtc;
13178         struct intel_crtc_state *intel_crtc_state;
13179         struct drm_crtc *crtc;
13180         struct drm_crtc_state *crtc_state;
13181         int i;
13182
13183         if (!dev_priv->display.crtc_compute_clock)
13184                 return;
13185
13186         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13187                 int dpll;
13188
13189                 intel_crtc = to_intel_crtc(crtc);
13190                 intel_crtc_state = to_intel_crtc_state(crtc_state);
13191                 dpll = intel_crtc_state->shared_dpll;
13192
13193                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13194                         continue;
13195
13196                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13197
13198                 if (!shared_dpll)
13199                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13200
13201                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13202         }
13203 }
13204
13205 /*
13206  * This implements the workaround described in the "notes" section of the mode
13207  * set sequence documentation. When going from no pipes or single pipe to
13208  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13209  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13210  */
13211 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13212 {
13213         struct drm_crtc_state *crtc_state;
13214         struct intel_crtc *intel_crtc;
13215         struct drm_crtc *crtc;
13216         struct intel_crtc_state *first_crtc_state = NULL;
13217         struct intel_crtc_state *other_crtc_state = NULL;
13218         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13219         int i;
13220
13221         /* look at all crtc's that are going to be enabled in during modeset */
13222         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13223                 intel_crtc = to_intel_crtc(crtc);
13224
13225                 if (!crtc_state->active || !needs_modeset(crtc_state))
13226                         continue;
13227
13228                 if (first_crtc_state) {
13229                         other_crtc_state = to_intel_crtc_state(crtc_state);
13230                         break;
13231                 } else {
13232                         first_crtc_state = to_intel_crtc_state(crtc_state);
13233                         first_pipe = intel_crtc->pipe;
13234                 }
13235         }
13236
13237         /* No workaround needed? */
13238         if (!first_crtc_state)
13239                 return 0;
13240
13241         /* w/a possibly needed, check how many crtc's are already enabled. */
13242         for_each_intel_crtc(state->dev, intel_crtc) {
13243                 struct intel_crtc_state *pipe_config;
13244
13245                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13246                 if (IS_ERR(pipe_config))
13247                         return PTR_ERR(pipe_config);
13248
13249                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13250
13251                 if (!pipe_config->base.active ||
13252                     needs_modeset(&pipe_config->base))
13253                         continue;
13254
13255                 /* 2 or more enabled crtcs means no need for w/a */
13256                 if (enabled_pipe != INVALID_PIPE)
13257                         return 0;
13258
13259                 enabled_pipe = intel_crtc->pipe;
13260         }
13261
13262         if (enabled_pipe != INVALID_PIPE)
13263                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13264         else if (other_crtc_state)
13265                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13266
13267         return 0;
13268 }
13269
13270 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13271 {
13272         struct drm_crtc *crtc;
13273         struct drm_crtc_state *crtc_state;
13274         int ret = 0;
13275
13276         /* add all active pipes to the state */
13277         for_each_crtc(state->dev, crtc) {
13278                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13279                 if (IS_ERR(crtc_state))
13280                         return PTR_ERR(crtc_state);
13281
13282                 if (!crtc_state->active || needs_modeset(crtc_state))
13283                         continue;
13284
13285                 crtc_state->mode_changed = true;
13286
13287                 ret = drm_atomic_add_affected_connectors(state, crtc);
13288                 if (ret)
13289                         break;
13290
13291                 ret = drm_atomic_add_affected_planes(state, crtc);
13292                 if (ret)
13293                         break;
13294         }
13295
13296         return ret;
13297 }
13298
13299 static int intel_modeset_checks(struct drm_atomic_state *state)
13300 {
13301         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13302         struct drm_i915_private *dev_priv = state->dev->dev_private;
13303         struct drm_crtc *crtc;
13304         struct drm_crtc_state *crtc_state;
13305         int ret = 0, i;
13306
13307         if (!check_digital_port_conflicts(state)) {
13308                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13309                 return -EINVAL;
13310         }
13311
13312         intel_state->modeset = true;
13313         intel_state->active_crtcs = dev_priv->active_crtcs;
13314
13315         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13316                 if (crtc_state->active)
13317                         intel_state->active_crtcs |= 1 << i;
13318                 else
13319                         intel_state->active_crtcs &= ~(1 << i);
13320         }
13321
13322         /*
13323          * See if the config requires any additional preparation, e.g.
13324          * to adjust global state with pipes off.  We need to do this
13325          * here so we can get the modeset_pipe updated config for the new
13326          * mode set on this crtc.  For other crtcs we need to use the
13327          * adjusted_mode bits in the crtc directly.
13328          */
13329         if (dev_priv->display.modeset_calc_cdclk) {
13330                 ret = dev_priv->display.modeset_calc_cdclk(state);
13331
13332                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13333                         ret = intel_modeset_all_pipes(state);
13334
13335                 if (ret < 0)
13336                         return ret;
13337         } else
13338                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13339
13340         intel_modeset_clear_plls(state);
13341
13342         if (IS_HASWELL(dev_priv))
13343                 return haswell_mode_set_planes_workaround(state);
13344
13345         return 0;
13346 }
13347
13348 /*
13349  * Handle calculation of various watermark data at the end of the atomic check
13350  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13351  * handlers to ensure that all derived state has been updated.
13352  */
13353 static void calc_watermark_data(struct drm_atomic_state *state)
13354 {
13355         struct drm_device *dev = state->dev;
13356         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13357         struct drm_crtc *crtc;
13358         struct drm_crtc_state *cstate;
13359         struct drm_plane *plane;
13360         struct drm_plane_state *pstate;
13361
13362         /*
13363          * Calculate watermark configuration details now that derived
13364          * plane/crtc state is all properly updated.
13365          */
13366         drm_for_each_crtc(crtc, dev) {
13367                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13368                         crtc->state;
13369
13370                 if (cstate->active)
13371                         intel_state->wm_config.num_pipes_active++;
13372         }
13373         drm_for_each_legacy_plane(plane, dev) {
13374                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13375                         plane->state;
13376
13377                 if (!to_intel_plane_state(pstate)->visible)
13378                         continue;
13379
13380                 intel_state->wm_config.sprites_enabled = true;
13381                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13382                     pstate->crtc_h != pstate->src_h >> 16)
13383                         intel_state->wm_config.sprites_scaled = true;
13384         }
13385 }
13386
13387 /**
13388  * intel_atomic_check - validate state object
13389  * @dev: drm device
13390  * @state: state to validate
13391  */
13392 static int intel_atomic_check(struct drm_device *dev,
13393                               struct drm_atomic_state *state)
13394 {
13395         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13396         struct drm_crtc *crtc;
13397         struct drm_crtc_state *crtc_state;
13398         int ret, i;
13399         bool any_ms = false;
13400
13401         ret = drm_atomic_helper_check_modeset(dev, state);
13402         if (ret)
13403                 return ret;
13404
13405         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13406                 struct intel_crtc_state *pipe_config =
13407                         to_intel_crtc_state(crtc_state);
13408
13409                 memset(&to_intel_crtc(crtc)->atomic, 0,
13410                        sizeof(struct intel_crtc_atomic_commit));
13411
13412                 /* Catch I915_MODE_FLAG_INHERITED */
13413                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13414                         crtc_state->mode_changed = true;
13415
13416                 if (!crtc_state->enable) {
13417                         if (needs_modeset(crtc_state))
13418                                 any_ms = true;
13419                         continue;
13420                 }
13421
13422                 if (!needs_modeset(crtc_state))
13423                         continue;
13424
13425                 /* FIXME: For only active_changed we shouldn't need to do any
13426                  * state recomputation at all. */
13427
13428                 ret = drm_atomic_add_affected_connectors(state, crtc);
13429                 if (ret)
13430                         return ret;
13431
13432                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13433                 if (ret)
13434                         return ret;
13435
13436                 if (i915.fastboot &&
13437                     intel_pipe_config_compare(state->dev,
13438                                         to_intel_crtc_state(crtc->state),
13439                                         pipe_config, true)) {
13440                         crtc_state->mode_changed = false;
13441                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13442                 }
13443
13444                 if (needs_modeset(crtc_state)) {
13445                         any_ms = true;
13446
13447                         ret = drm_atomic_add_affected_planes(state, crtc);
13448                         if (ret)
13449                                 return ret;
13450                 }
13451
13452                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13453                                        needs_modeset(crtc_state) ?
13454                                        "[modeset]" : "[fastset]");
13455         }
13456
13457         if (any_ms) {
13458                 ret = intel_modeset_checks(state);
13459
13460                 if (ret)
13461                         return ret;
13462         } else
13463                 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13464
13465         ret = drm_atomic_helper_check_planes(state->dev, state);
13466         if (ret)
13467                 return ret;
13468
13469         calc_watermark_data(state);
13470
13471         return 0;
13472 }
13473
13474 static int intel_atomic_prepare_commit(struct drm_device *dev,
13475                                        struct drm_atomic_state *state,
13476                                        bool async)
13477 {
13478         struct drm_i915_private *dev_priv = dev->dev_private;
13479         struct drm_plane_state *plane_state;
13480         struct drm_crtc_state *crtc_state;
13481         struct drm_plane *plane;
13482         struct drm_crtc *crtc;
13483         int i, ret;
13484
13485         if (async) {
13486                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13487                 return -EINVAL;
13488         }
13489
13490         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13491                 ret = intel_crtc_wait_for_pending_flips(crtc);
13492                 if (ret)
13493                         return ret;
13494
13495                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13496                         flush_workqueue(dev_priv->wq);
13497         }
13498
13499         ret = mutex_lock_interruptible(&dev->struct_mutex);
13500         if (ret)
13501                 return ret;
13502
13503         ret = drm_atomic_helper_prepare_planes(dev, state);
13504         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13505                 u32 reset_counter;
13506
13507                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13508                 mutex_unlock(&dev->struct_mutex);
13509
13510                 for_each_plane_in_state(state, plane, plane_state, i) {
13511                         struct intel_plane_state *intel_plane_state =
13512                                 to_intel_plane_state(plane_state);
13513
13514                         if (!intel_plane_state->wait_req)
13515                                 continue;
13516
13517                         ret = __i915_wait_request(intel_plane_state->wait_req,
13518                                                   reset_counter, true,
13519                                                   NULL, NULL);
13520
13521                         /* Swallow -EIO errors to allow updates during hw lockup. */
13522                         if (ret == -EIO)
13523                                 ret = 0;
13524
13525                         if (ret)
13526                                 break;
13527                 }
13528
13529                 if (!ret)
13530                         return 0;
13531
13532                 mutex_lock(&dev->struct_mutex);
13533                 drm_atomic_helper_cleanup_planes(dev, state);
13534         }
13535
13536         mutex_unlock(&dev->struct_mutex);
13537         return ret;
13538 }
13539
13540 /**
13541  * intel_atomic_commit - commit validated state object
13542  * @dev: DRM device
13543  * @state: the top-level driver state object
13544  * @async: asynchronous commit
13545  *
13546  * This function commits a top-level state object that has been validated
13547  * with drm_atomic_helper_check().
13548  *
13549  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13550  * we can only handle plane-related operations and do not yet support
13551  * asynchronous commit.
13552  *
13553  * RETURNS
13554  * Zero for success or -errno.
13555  */
13556 static int intel_atomic_commit(struct drm_device *dev,
13557                                struct drm_atomic_state *state,
13558                                bool async)
13559 {
13560         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13561         struct drm_i915_private *dev_priv = dev->dev_private;
13562         struct drm_crtc_state *crtc_state;
13563         struct drm_crtc *crtc;
13564         struct intel_crtc_state *intel_cstate;
13565         int ret = 0, i;
13566         bool hw_check = intel_state->modeset;
13567
13568         ret = intel_atomic_prepare_commit(dev, state, async);
13569         if (ret) {
13570                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13571                 return ret;
13572         }
13573
13574         drm_atomic_helper_swap_state(dev, state);
13575         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13576
13577         if (intel_state->modeset) {
13578                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13579                        sizeof(intel_state->min_pixclk));
13580                 dev_priv->active_crtcs = intel_state->active_crtcs;
13581                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13582         }
13583
13584         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13585                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13586
13587                 if (!needs_modeset(crtc->state))
13588                         continue;
13589
13590                 intel_pre_plane_update(intel_crtc);
13591
13592                 if (crtc_state->active) {
13593                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13594                         dev_priv->display.crtc_disable(crtc);
13595                         intel_crtc->active = false;
13596                         intel_disable_shared_dpll(intel_crtc);
13597
13598                         /*
13599                          * Underruns don't always raise
13600                          * interrupts, so check manually.
13601                          */
13602                         intel_check_cpu_fifo_underruns(dev_priv);
13603                         intel_check_pch_fifo_underruns(dev_priv);
13604
13605                         if (!crtc->state->active)
13606                                 intel_update_watermarks(crtc);
13607                 }
13608         }
13609
13610         /* Only after disabling all output pipelines that will be changed can we
13611          * update the the output configuration. */
13612         intel_modeset_update_crtc_state(state);
13613
13614         if (intel_state->modeset) {
13615                 intel_shared_dpll_commit(state);
13616
13617                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13618                 modeset_update_crtc_power_domains(state);
13619         }
13620
13621         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13622         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13623                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13624                 bool modeset = needs_modeset(crtc->state);
13625                 bool update_pipe = !modeset &&
13626                         to_intel_crtc_state(crtc->state)->update_pipe;
13627                 unsigned long put_domains = 0;
13628
13629                 if (modeset)
13630                         intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13631
13632                 if (modeset && crtc->state->active) {
13633                         update_scanline_offset(to_intel_crtc(crtc));
13634                         dev_priv->display.crtc_enable(crtc);
13635                 }
13636
13637                 if (update_pipe) {
13638                         put_domains = modeset_get_crtc_power_domains(crtc);
13639
13640                         /* make sure intel_modeset_check_state runs */
13641                         hw_check = true;
13642                 }
13643
13644                 if (!modeset)
13645                         intel_pre_plane_update(intel_crtc);
13646
13647                 if (crtc->state->active &&
13648                     (crtc->state->planes_changed || update_pipe))
13649                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13650
13651                 if (put_domains)
13652                         modeset_put_power_domains(dev_priv, put_domains);
13653
13654                 intel_post_plane_update(intel_crtc);
13655
13656                 if (modeset)
13657                         intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13658         }
13659
13660         /* FIXME: add subpixel order */
13661
13662         drm_atomic_helper_wait_for_vblanks(dev, state);
13663
13664         /*
13665          * Now that the vblank has passed, we can go ahead and program the
13666          * optimal watermarks on platforms that need two-step watermark
13667          * programming.
13668          *
13669          * TODO: Move this (and other cleanup) to an async worker eventually.
13670          */
13671         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13672                 intel_cstate = to_intel_crtc_state(crtc->state);
13673
13674                 if (dev_priv->display.optimize_watermarks)
13675                         dev_priv->display.optimize_watermarks(intel_cstate);
13676         }
13677
13678         mutex_lock(&dev->struct_mutex);
13679         drm_atomic_helper_cleanup_planes(dev, state);
13680         mutex_unlock(&dev->struct_mutex);
13681
13682         if (hw_check)
13683                 intel_modeset_check_state(dev, state);
13684
13685         drm_atomic_state_free(state);
13686
13687         /* As one of the primary mmio accessors, KMS has a high likelihood
13688          * of triggering bugs in unclaimed access. After we finish
13689          * modesetting, see if an error has been flagged, and if so
13690          * enable debugging for the next modeset - and hope we catch
13691          * the culprit.
13692          *
13693          * XXX note that we assume display power is on at this point.
13694          * This might hold true now but we need to add pm helper to check
13695          * unclaimed only when the hardware is on, as atomic commits
13696          * can happen also when the device is completely off.
13697          */
13698         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13699
13700         return 0;
13701 }
13702
13703 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13704 {
13705         struct drm_device *dev = crtc->dev;
13706         struct drm_atomic_state *state;
13707         struct drm_crtc_state *crtc_state;
13708         int ret;
13709
13710         state = drm_atomic_state_alloc(dev);
13711         if (!state) {
13712                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13713                               crtc->base.id);
13714                 return;
13715         }
13716
13717         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13718
13719 retry:
13720         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13721         ret = PTR_ERR_OR_ZERO(crtc_state);
13722         if (!ret) {
13723                 if (!crtc_state->active)
13724                         goto out;
13725
13726                 crtc_state->mode_changed = true;
13727                 ret = drm_atomic_commit(state);
13728         }
13729
13730         if (ret == -EDEADLK) {
13731                 drm_atomic_state_clear(state);
13732                 drm_modeset_backoff(state->acquire_ctx);
13733                 goto retry;
13734         }
13735
13736         if (ret)
13737 out:
13738                 drm_atomic_state_free(state);
13739 }
13740
13741 #undef for_each_intel_crtc_masked
13742
13743 static const struct drm_crtc_funcs intel_crtc_funcs = {
13744         .gamma_set = intel_crtc_gamma_set,
13745         .set_config = drm_atomic_helper_set_config,
13746         .destroy = intel_crtc_destroy,
13747         .page_flip = intel_crtc_page_flip,
13748         .atomic_duplicate_state = intel_crtc_duplicate_state,
13749         .atomic_destroy_state = intel_crtc_destroy_state,
13750 };
13751
13752 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13753                                       struct intel_shared_dpll *pll,
13754                                       struct intel_dpll_hw_state *hw_state)
13755 {
13756         uint32_t val;
13757
13758         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13759                 return false;
13760
13761         val = I915_READ(PCH_DPLL(pll->id));
13762         hw_state->dpll = val;
13763         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13764         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13765
13766         return val & DPLL_VCO_ENABLE;
13767 }
13768
13769 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13770                                   struct intel_shared_dpll *pll)
13771 {
13772         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13773         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13774 }
13775
13776 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13777                                 struct intel_shared_dpll *pll)
13778 {
13779         /* PCH refclock must be enabled first */
13780         ibx_assert_pch_refclk_enabled(dev_priv);
13781
13782         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13783
13784         /* Wait for the clocks to stabilize. */
13785         POSTING_READ(PCH_DPLL(pll->id));
13786         udelay(150);
13787
13788         /* The pixel multiplier can only be updated once the
13789          * DPLL is enabled and the clocks are stable.
13790          *
13791          * So write it again.
13792          */
13793         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13794         POSTING_READ(PCH_DPLL(pll->id));
13795         udelay(200);
13796 }
13797
13798 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13799                                  struct intel_shared_dpll *pll)
13800 {
13801         struct drm_device *dev = dev_priv->dev;
13802         struct intel_crtc *crtc;
13803
13804         /* Make sure no transcoder isn't still depending on us. */
13805         for_each_intel_crtc(dev, crtc) {
13806                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13807                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13808         }
13809
13810         I915_WRITE(PCH_DPLL(pll->id), 0);
13811         POSTING_READ(PCH_DPLL(pll->id));
13812         udelay(200);
13813 }
13814
13815 static char *ibx_pch_dpll_names[] = {
13816         "PCH DPLL A",
13817         "PCH DPLL B",
13818 };
13819
13820 static void ibx_pch_dpll_init(struct drm_device *dev)
13821 {
13822         struct drm_i915_private *dev_priv = dev->dev_private;
13823         int i;
13824
13825         dev_priv->num_shared_dpll = 2;
13826
13827         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13828                 dev_priv->shared_dplls[i].id = i;
13829                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13830                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13831                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13832                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13833                 dev_priv->shared_dplls[i].get_hw_state =
13834                         ibx_pch_dpll_get_hw_state;
13835         }
13836 }
13837
13838 static void intel_shared_dpll_init(struct drm_device *dev)
13839 {
13840         struct drm_i915_private *dev_priv = dev->dev_private;
13841
13842         if (HAS_DDI(dev))
13843                 intel_ddi_pll_init(dev);
13844         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13845                 ibx_pch_dpll_init(dev);
13846         else
13847                 dev_priv->num_shared_dpll = 0;
13848
13849         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13850 }
13851
13852 /**
13853  * intel_prepare_plane_fb - Prepare fb for usage on plane
13854  * @plane: drm plane to prepare for
13855  * @fb: framebuffer to prepare for presentation
13856  *
13857  * Prepares a framebuffer for usage on a display plane.  Generally this
13858  * involves pinning the underlying object and updating the frontbuffer tracking
13859  * bits.  Some older platforms need special physical address handling for
13860  * cursor planes.
13861  *
13862  * Must be called with struct_mutex held.
13863  *
13864  * Returns 0 on success, negative error code on failure.
13865  */
13866 int
13867 intel_prepare_plane_fb(struct drm_plane *plane,
13868                        const struct drm_plane_state *new_state)
13869 {
13870         struct drm_device *dev = plane->dev;
13871         struct drm_framebuffer *fb = new_state->fb;
13872         struct intel_plane *intel_plane = to_intel_plane(plane);
13873         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13874         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13875         int ret = 0;
13876
13877         if (!obj && !old_obj)
13878                 return 0;
13879
13880         if (old_obj) {
13881                 struct drm_crtc_state *crtc_state =
13882                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13883
13884                 /* Big Hammer, we also need to ensure that any pending
13885                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13886                  * current scanout is retired before unpinning the old
13887                  * framebuffer. Note that we rely on userspace rendering
13888                  * into the buffer attached to the pipe they are waiting
13889                  * on. If not, userspace generates a GPU hang with IPEHR
13890                  * point to the MI_WAIT_FOR_EVENT.
13891                  *
13892                  * This should only fail upon a hung GPU, in which case we
13893                  * can safely continue.
13894                  */
13895                 if (needs_modeset(crtc_state))
13896                         ret = i915_gem_object_wait_rendering(old_obj, true);
13897
13898                 /* Swallow -EIO errors to allow updates during hw lockup. */
13899                 if (ret && ret != -EIO)
13900                         return ret;
13901         }
13902
13903         /* For framebuffer backed by dmabuf, wait for fence */
13904         if (obj && obj->base.dma_buf) {
13905                 ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13906                                                           false, true,
13907                                                           MAX_SCHEDULE_TIMEOUT);
13908                 if (ret == -ERESTARTSYS)
13909                         return ret;
13910
13911                 WARN_ON(ret < 0);
13912         }
13913
13914         if (!obj) {
13915                 ret = 0;
13916         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13917             INTEL_INFO(dev)->cursor_needs_physical) {
13918                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13919                 ret = i915_gem_object_attach_phys(obj, align);
13920                 if (ret)
13921                         DRM_DEBUG_KMS("failed to attach phys object\n");
13922         } else {
13923                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13924         }
13925
13926         if (ret == 0) {
13927                 if (obj) {
13928                         struct intel_plane_state *plane_state =
13929                                 to_intel_plane_state(new_state);
13930
13931                         i915_gem_request_assign(&plane_state->wait_req,
13932                                                 obj->last_write_req);
13933                 }
13934
13935                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13936         }
13937
13938         return ret;
13939 }
13940
13941 /**
13942  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13943  * @plane: drm plane to clean up for
13944  * @fb: old framebuffer that was on plane
13945  *
13946  * Cleans up a framebuffer that has just been removed from a plane.
13947  *
13948  * Must be called with struct_mutex held.
13949  */
13950 void
13951 intel_cleanup_plane_fb(struct drm_plane *plane,
13952                        const struct drm_plane_state *old_state)
13953 {
13954         struct drm_device *dev = plane->dev;
13955         struct intel_plane *intel_plane = to_intel_plane(plane);
13956         struct intel_plane_state *old_intel_state;
13957         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13958         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13959
13960         old_intel_state = to_intel_plane_state(old_state);
13961
13962         if (!obj && !old_obj)
13963                 return;
13964
13965         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13966             !INTEL_INFO(dev)->cursor_needs_physical))
13967                 intel_unpin_fb_obj(old_state->fb, old_state);
13968
13969         /* prepare_fb aborted? */
13970         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13971             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13972                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13973
13974         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13975
13976 }
13977
13978 int
13979 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13980 {
13981         int max_scale;
13982         struct drm_device *dev;
13983         struct drm_i915_private *dev_priv;
13984         int crtc_clock, cdclk;
13985
13986         if (!intel_crtc || !crtc_state->base.enable)
13987                 return DRM_PLANE_HELPER_NO_SCALING;
13988
13989         dev = intel_crtc->base.dev;
13990         dev_priv = dev->dev_private;
13991         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13992         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13993
13994         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13995                 return DRM_PLANE_HELPER_NO_SCALING;
13996
13997         /*
13998          * skl max scale is lower of:
13999          *    close to 3 but not 3, -1 is for that purpose
14000          *            or
14001          *    cdclk/crtc_clock
14002          */
14003         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14004
14005         return max_scale;
14006 }
14007
14008 static int
14009 intel_check_primary_plane(struct drm_plane *plane,
14010                           struct intel_crtc_state *crtc_state,
14011                           struct intel_plane_state *state)
14012 {
14013         struct drm_crtc *crtc = state->base.crtc;
14014         struct drm_framebuffer *fb = state->base.fb;
14015         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14016         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14017         bool can_position = false;
14018
14019         /* use scaler when colorkey is not required */
14020         if (INTEL_INFO(plane->dev)->gen >= 9 &&
14021             state->ckey.flags == I915_SET_COLORKEY_NONE) {
14022                 min_scale = 1;
14023                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14024                 can_position = true;
14025         }
14026
14027         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14028                                              &state->dst, &state->clip,
14029                                              min_scale, max_scale,
14030                                              can_position, true,
14031                                              &state->visible);
14032 }
14033
14034 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14035                                     struct drm_crtc_state *old_crtc_state)
14036 {
14037         struct drm_device *dev = crtc->dev;
14038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14039         struct intel_crtc_state *old_intel_state =
14040                 to_intel_crtc_state(old_crtc_state);
14041         bool modeset = needs_modeset(crtc->state);
14042
14043         /* Perform vblank evasion around commit operation */
14044         intel_pipe_update_start(intel_crtc);
14045
14046         if (modeset)
14047                 return;
14048
14049         if (to_intel_crtc_state(crtc->state)->update_pipe)
14050                 intel_update_pipe_config(intel_crtc, old_intel_state);
14051         else if (INTEL_INFO(dev)->gen >= 9)
14052                 skl_detach_scalers(intel_crtc);
14053 }
14054
14055 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14056                                      struct drm_crtc_state *old_crtc_state)
14057 {
14058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14059
14060         intel_pipe_update_end(intel_crtc);
14061 }
14062
14063 /**
14064  * intel_plane_destroy - destroy a plane
14065  * @plane: plane to destroy
14066  *
14067  * Common destruction function for all types of planes (primary, cursor,
14068  * sprite).
14069  */
14070 void intel_plane_destroy(struct drm_plane *plane)
14071 {
14072         struct intel_plane *intel_plane = to_intel_plane(plane);
14073         drm_plane_cleanup(plane);
14074         kfree(intel_plane);
14075 }
14076
14077 const struct drm_plane_funcs intel_plane_funcs = {
14078         .update_plane = drm_atomic_helper_update_plane,
14079         .disable_plane = drm_atomic_helper_disable_plane,
14080         .destroy = intel_plane_destroy,
14081         .set_property = drm_atomic_helper_plane_set_property,
14082         .atomic_get_property = intel_plane_atomic_get_property,
14083         .atomic_set_property = intel_plane_atomic_set_property,
14084         .atomic_duplicate_state = intel_plane_duplicate_state,
14085         .atomic_destroy_state = intel_plane_destroy_state,
14086
14087 };
14088
14089 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14090                                                     int pipe)
14091 {
14092         struct intel_plane *primary;
14093         struct intel_plane_state *state;
14094         const uint32_t *intel_primary_formats;
14095         unsigned int num_formats;
14096
14097         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14098         if (primary == NULL)
14099                 return NULL;
14100
14101         state = intel_create_plane_state(&primary->base);
14102         if (!state) {
14103                 kfree(primary);
14104                 return NULL;
14105         }
14106         primary->base.state = &state->base;
14107
14108         primary->can_scale = false;
14109         primary->max_downscale = 1;
14110         if (INTEL_INFO(dev)->gen >= 9) {
14111                 primary->can_scale = true;
14112                 state->scaler_id = -1;
14113         }
14114         primary->pipe = pipe;
14115         primary->plane = pipe;
14116         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14117         primary->check_plane = intel_check_primary_plane;
14118         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14119                 primary->plane = !pipe;
14120
14121         if (INTEL_INFO(dev)->gen >= 9) {
14122                 intel_primary_formats = skl_primary_formats;
14123                 num_formats = ARRAY_SIZE(skl_primary_formats);
14124
14125                 primary->update_plane = skylake_update_primary_plane;
14126                 primary->disable_plane = skylake_disable_primary_plane;
14127         } else if (HAS_PCH_SPLIT(dev)) {
14128                 intel_primary_formats = i965_primary_formats;
14129                 num_formats = ARRAY_SIZE(i965_primary_formats);
14130
14131                 primary->update_plane = ironlake_update_primary_plane;
14132                 primary->disable_plane = i9xx_disable_primary_plane;
14133         } else if (INTEL_INFO(dev)->gen >= 4) {
14134                 intel_primary_formats = i965_primary_formats;
14135                 num_formats = ARRAY_SIZE(i965_primary_formats);
14136
14137                 primary->update_plane = i9xx_update_primary_plane;
14138                 primary->disable_plane = i9xx_disable_primary_plane;
14139         } else {
14140                 intel_primary_formats = i8xx_primary_formats;
14141                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14142
14143                 primary->update_plane = i9xx_update_primary_plane;
14144                 primary->disable_plane = i9xx_disable_primary_plane;
14145         }
14146
14147         drm_universal_plane_init(dev, &primary->base, 0,
14148                                  &intel_plane_funcs,
14149                                  intel_primary_formats, num_formats,
14150                                  DRM_PLANE_TYPE_PRIMARY);
14151
14152         if (INTEL_INFO(dev)->gen >= 4)
14153                 intel_create_rotation_property(dev, primary);
14154
14155         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14156
14157         return &primary->base;
14158 }
14159
14160 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14161 {
14162         if (!dev->mode_config.rotation_property) {
14163                 unsigned long flags = BIT(DRM_ROTATE_0) |
14164                         BIT(DRM_ROTATE_180);
14165
14166                 if (INTEL_INFO(dev)->gen >= 9)
14167                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14168
14169                 dev->mode_config.rotation_property =
14170                         drm_mode_create_rotation_property(dev, flags);
14171         }
14172         if (dev->mode_config.rotation_property)
14173                 drm_object_attach_property(&plane->base.base,
14174                                 dev->mode_config.rotation_property,
14175                                 plane->base.state->rotation);
14176 }
14177
14178 static int
14179 intel_check_cursor_plane(struct drm_plane *plane,
14180                          struct intel_crtc_state *crtc_state,
14181                          struct intel_plane_state *state)
14182 {
14183         struct drm_crtc *crtc = crtc_state->base.crtc;
14184         struct drm_framebuffer *fb = state->base.fb;
14185         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14186         enum pipe pipe = to_intel_plane(plane)->pipe;
14187         unsigned stride;
14188         int ret;
14189
14190         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14191                                             &state->dst, &state->clip,
14192                                             DRM_PLANE_HELPER_NO_SCALING,
14193                                             DRM_PLANE_HELPER_NO_SCALING,
14194                                             true, true, &state->visible);
14195         if (ret)
14196                 return ret;
14197
14198         /* if we want to turn off the cursor ignore width and height */
14199         if (!obj)
14200                 return 0;
14201
14202         /* Check for which cursor types we support */
14203         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14204                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14205                           state->base.crtc_w, state->base.crtc_h);
14206                 return -EINVAL;
14207         }
14208
14209         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14210         if (obj->base.size < stride * state->base.crtc_h) {
14211                 DRM_DEBUG_KMS("buffer is too small\n");
14212                 return -ENOMEM;
14213         }
14214
14215         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14216                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14217                 return -EINVAL;
14218         }
14219
14220         /*
14221          * There's something wrong with the cursor on CHV pipe C.
14222          * If it straddles the left edge of the screen then
14223          * moving it away from the edge or disabling it often
14224          * results in a pipe underrun, and often that can lead to
14225          * dead pipe (constant underrun reported, and it scans
14226          * out just a solid color). To recover from that, the
14227          * display power well must be turned off and on again.
14228          * Refuse the put the cursor into that compromised position.
14229          */
14230         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14231             state->visible && state->base.crtc_x < 0) {
14232                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14233                 return -EINVAL;
14234         }
14235
14236         return 0;
14237 }
14238
14239 static void
14240 intel_disable_cursor_plane(struct drm_plane *plane,
14241                            struct drm_crtc *crtc)
14242 {
14243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14244
14245         intel_crtc->cursor_addr = 0;
14246         intel_crtc_update_cursor(crtc, NULL);
14247 }
14248
14249 static void
14250 intel_update_cursor_plane(struct drm_plane *plane,
14251                           const struct intel_crtc_state *crtc_state,
14252                           const struct intel_plane_state *state)
14253 {
14254         struct drm_crtc *crtc = crtc_state->base.crtc;
14255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14256         struct drm_device *dev = plane->dev;
14257         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14258         uint32_t addr;
14259
14260         if (!obj)
14261                 addr = 0;
14262         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14263                 addr = i915_gem_obj_ggtt_offset(obj);
14264         else
14265                 addr = obj->phys_handle->busaddr;
14266
14267         intel_crtc->cursor_addr = addr;
14268         intel_crtc_update_cursor(crtc, state);
14269 }
14270
14271 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14272                                                    int pipe)
14273 {
14274         struct intel_plane *cursor;
14275         struct intel_plane_state *state;
14276
14277         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14278         if (cursor == NULL)
14279                 return NULL;
14280
14281         state = intel_create_plane_state(&cursor->base);
14282         if (!state) {
14283                 kfree(cursor);
14284                 return NULL;
14285         }
14286         cursor->base.state = &state->base;
14287
14288         cursor->can_scale = false;
14289         cursor->max_downscale = 1;
14290         cursor->pipe = pipe;
14291         cursor->plane = pipe;
14292         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14293         cursor->check_plane = intel_check_cursor_plane;
14294         cursor->update_plane = intel_update_cursor_plane;
14295         cursor->disable_plane = intel_disable_cursor_plane;
14296
14297         drm_universal_plane_init(dev, &cursor->base, 0,
14298                                  &intel_plane_funcs,
14299                                  intel_cursor_formats,
14300                                  ARRAY_SIZE(intel_cursor_formats),
14301                                  DRM_PLANE_TYPE_CURSOR);
14302
14303         if (INTEL_INFO(dev)->gen >= 4) {
14304                 if (!dev->mode_config.rotation_property)
14305                         dev->mode_config.rotation_property =
14306                                 drm_mode_create_rotation_property(dev,
14307                                                         BIT(DRM_ROTATE_0) |
14308                                                         BIT(DRM_ROTATE_180));
14309                 if (dev->mode_config.rotation_property)
14310                         drm_object_attach_property(&cursor->base.base,
14311                                 dev->mode_config.rotation_property,
14312                                 state->base.rotation);
14313         }
14314
14315         if (INTEL_INFO(dev)->gen >=9)
14316                 state->scaler_id = -1;
14317
14318         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14319
14320         return &cursor->base;
14321 }
14322
14323 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14324         struct intel_crtc_state *crtc_state)
14325 {
14326         int i;
14327         struct intel_scaler *intel_scaler;
14328         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14329
14330         for (i = 0; i < intel_crtc->num_scalers; i++) {
14331                 intel_scaler = &scaler_state->scalers[i];
14332                 intel_scaler->in_use = 0;
14333                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14334         }
14335
14336         scaler_state->scaler_id = -1;
14337 }
14338
14339 static void intel_crtc_init(struct drm_device *dev, int pipe)
14340 {
14341         struct drm_i915_private *dev_priv = dev->dev_private;
14342         struct intel_crtc *intel_crtc;
14343         struct intel_crtc_state *crtc_state = NULL;
14344         struct drm_plane *primary = NULL;
14345         struct drm_plane *cursor = NULL;
14346         int i, ret;
14347
14348         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14349         if (intel_crtc == NULL)
14350                 return;
14351
14352         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14353         if (!crtc_state)
14354                 goto fail;
14355         intel_crtc->config = crtc_state;
14356         intel_crtc->base.state = &crtc_state->base;
14357         crtc_state->base.crtc = &intel_crtc->base;
14358
14359         /* initialize shared scalers */
14360         if (INTEL_INFO(dev)->gen >= 9) {
14361                 if (pipe == PIPE_C)
14362                         intel_crtc->num_scalers = 1;
14363                 else
14364                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14365
14366                 skl_init_scalers(dev, intel_crtc, crtc_state);
14367         }
14368
14369         primary = intel_primary_plane_create(dev, pipe);
14370         if (!primary)
14371                 goto fail;
14372
14373         cursor = intel_cursor_plane_create(dev, pipe);
14374         if (!cursor)
14375                 goto fail;
14376
14377         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14378                                         cursor, &intel_crtc_funcs);
14379         if (ret)
14380                 goto fail;
14381
14382         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14383         for (i = 0; i < 256; i++) {
14384                 intel_crtc->lut_r[i] = i;
14385                 intel_crtc->lut_g[i] = i;
14386                 intel_crtc->lut_b[i] = i;
14387         }
14388
14389         /*
14390          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14391          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14392          */
14393         intel_crtc->pipe = pipe;
14394         intel_crtc->plane = pipe;
14395         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14396                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14397                 intel_crtc->plane = !pipe;
14398         }
14399
14400         intel_crtc->cursor_base = ~0;
14401         intel_crtc->cursor_cntl = ~0;
14402         intel_crtc->cursor_size = ~0;
14403
14404         intel_crtc->wm.cxsr_allowed = true;
14405
14406         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14407                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14408         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14409         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14410
14411         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14412
14413         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14414         return;
14415
14416 fail:
14417         if (primary)
14418                 drm_plane_cleanup(primary);
14419         if (cursor)
14420                 drm_plane_cleanup(cursor);
14421         kfree(crtc_state);
14422         kfree(intel_crtc);
14423 }
14424
14425 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14426 {
14427         struct drm_encoder *encoder = connector->base.encoder;
14428         struct drm_device *dev = connector->base.dev;
14429
14430         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14431
14432         if (!encoder || WARN_ON(!encoder->crtc))
14433                 return INVALID_PIPE;
14434
14435         return to_intel_crtc(encoder->crtc)->pipe;
14436 }
14437
14438 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14439                                 struct drm_file *file)
14440 {
14441         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14442         struct drm_crtc *drmmode_crtc;
14443         struct intel_crtc *crtc;
14444
14445         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14446
14447         if (!drmmode_crtc) {
14448                 DRM_ERROR("no such CRTC id\n");
14449                 return -ENOENT;
14450         }
14451
14452         crtc = to_intel_crtc(drmmode_crtc);
14453         pipe_from_crtc_id->pipe = crtc->pipe;
14454
14455         return 0;
14456 }
14457
14458 static int intel_encoder_clones(struct intel_encoder *encoder)
14459 {
14460         struct drm_device *dev = encoder->base.dev;
14461         struct intel_encoder *source_encoder;
14462         int index_mask = 0;
14463         int entry = 0;
14464
14465         for_each_intel_encoder(dev, source_encoder) {
14466                 if (encoders_cloneable(encoder, source_encoder))
14467                         index_mask |= (1 << entry);
14468
14469                 entry++;
14470         }
14471
14472         return index_mask;
14473 }
14474
14475 static bool has_edp_a(struct drm_device *dev)
14476 {
14477         struct drm_i915_private *dev_priv = dev->dev_private;
14478
14479         if (!IS_MOBILE(dev))
14480                 return false;
14481
14482         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14483                 return false;
14484
14485         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14486                 return false;
14487
14488         return true;
14489 }
14490
14491 static bool intel_crt_present(struct drm_device *dev)
14492 {
14493         struct drm_i915_private *dev_priv = dev->dev_private;
14494
14495         if (INTEL_INFO(dev)->gen >= 9)
14496                 return false;
14497
14498         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14499                 return false;
14500
14501         if (IS_CHERRYVIEW(dev))
14502                 return false;
14503
14504         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14505                 return false;
14506
14507         /* DDI E can't be used if DDI A requires 4 lanes */
14508         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14509                 return false;
14510
14511         if (!dev_priv->vbt.int_crt_support)
14512                 return false;
14513
14514         return true;
14515 }
14516
14517 static void intel_setup_outputs(struct drm_device *dev)
14518 {
14519         struct drm_i915_private *dev_priv = dev->dev_private;
14520         struct intel_encoder *encoder;
14521         bool dpd_is_edp = false;
14522
14523         intel_lvds_init(dev);
14524
14525         if (intel_crt_present(dev))
14526                 intel_crt_init(dev);
14527
14528         if (IS_BROXTON(dev)) {
14529                 /*
14530                  * FIXME: Broxton doesn't support port detection via the
14531                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14532                  * detect the ports.
14533                  */
14534                 intel_ddi_init(dev, PORT_A);
14535                 intel_ddi_init(dev, PORT_B);
14536                 intel_ddi_init(dev, PORT_C);
14537         } else if (HAS_DDI(dev)) {
14538                 int found;
14539
14540                 /*
14541                  * Haswell uses DDI functions to detect digital outputs.
14542                  * On SKL pre-D0 the strap isn't connected, so we assume
14543                  * it's there.
14544                  */
14545                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14546                 /* WaIgnoreDDIAStrap: skl */
14547                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14548                         intel_ddi_init(dev, PORT_A);
14549
14550                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14551                  * register */
14552                 found = I915_READ(SFUSE_STRAP);
14553
14554                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14555                         intel_ddi_init(dev, PORT_B);
14556                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14557                         intel_ddi_init(dev, PORT_C);
14558                 if (found & SFUSE_STRAP_DDID_DETECTED)
14559                         intel_ddi_init(dev, PORT_D);
14560                 /*
14561                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14562                  */
14563                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14564                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14565                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14566                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14567                         intel_ddi_init(dev, PORT_E);
14568
14569         } else if (HAS_PCH_SPLIT(dev)) {
14570                 int found;
14571                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14572
14573                 if (has_edp_a(dev))
14574                         intel_dp_init(dev, DP_A, PORT_A);
14575
14576                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14577                         /* PCH SDVOB multiplex with HDMIB */
14578                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14579                         if (!found)
14580                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14581                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14582                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14583                 }
14584
14585                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14586                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14587
14588                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14589                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14590
14591                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14592                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14593
14594                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14595                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14596         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14597                 /*
14598                  * The DP_DETECTED bit is the latched state of the DDC
14599                  * SDA pin at boot. However since eDP doesn't require DDC
14600                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14601                  * eDP ports may have been muxed to an alternate function.
14602                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14603                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14604                  * detect eDP ports.
14605                  */
14606                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14607                     !intel_dp_is_edp(dev, PORT_B))
14608                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14609                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14610                     intel_dp_is_edp(dev, PORT_B))
14611                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14612
14613                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14614                     !intel_dp_is_edp(dev, PORT_C))
14615                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14616                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14617                     intel_dp_is_edp(dev, PORT_C))
14618                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14619
14620                 if (IS_CHERRYVIEW(dev)) {
14621                         /* eDP not supported on port D, so don't check VBT */
14622                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14623                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14624                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14625                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14626                 }
14627
14628                 intel_dsi_init(dev);
14629         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14630                 bool found = false;
14631
14632                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14633                         DRM_DEBUG_KMS("probing SDVOB\n");
14634                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14635                         if (!found && IS_G4X(dev)) {
14636                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14637                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14638                         }
14639
14640                         if (!found && IS_G4X(dev))
14641                                 intel_dp_init(dev, DP_B, PORT_B);
14642                 }
14643
14644                 /* Before G4X SDVOC doesn't have its own detect register */
14645
14646                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14647                         DRM_DEBUG_KMS("probing SDVOC\n");
14648                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14649                 }
14650
14651                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14652
14653                         if (IS_G4X(dev)) {
14654                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14655                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14656                         }
14657                         if (IS_G4X(dev))
14658                                 intel_dp_init(dev, DP_C, PORT_C);
14659                 }
14660
14661                 if (IS_G4X(dev) &&
14662                     (I915_READ(DP_D) & DP_DETECTED))
14663                         intel_dp_init(dev, DP_D, PORT_D);
14664         } else if (IS_GEN2(dev))
14665                 intel_dvo_init(dev);
14666
14667         if (SUPPORTS_TV(dev))
14668                 intel_tv_init(dev);
14669
14670         intel_psr_init(dev);
14671
14672         for_each_intel_encoder(dev, encoder) {
14673                 encoder->base.possible_crtcs = encoder->crtc_mask;
14674                 encoder->base.possible_clones =
14675                         intel_encoder_clones(encoder);
14676         }
14677
14678         intel_init_pch_refclk(dev);
14679
14680         drm_helper_move_panel_connectors_to_head(dev);
14681 }
14682
14683 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14684 {
14685         struct drm_device *dev = fb->dev;
14686         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14687
14688         drm_framebuffer_cleanup(fb);
14689         mutex_lock(&dev->struct_mutex);
14690         WARN_ON(!intel_fb->obj->framebuffer_references--);
14691         drm_gem_object_unreference(&intel_fb->obj->base);
14692         mutex_unlock(&dev->struct_mutex);
14693         kfree(intel_fb);
14694 }
14695
14696 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14697                                                 struct drm_file *file,
14698                                                 unsigned int *handle)
14699 {
14700         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14701         struct drm_i915_gem_object *obj = intel_fb->obj;
14702
14703         if (obj->userptr.mm) {
14704                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14705                 return -EINVAL;
14706         }
14707
14708         return drm_gem_handle_create(file, &obj->base, handle);
14709 }
14710
14711 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14712                                         struct drm_file *file,
14713                                         unsigned flags, unsigned color,
14714                                         struct drm_clip_rect *clips,
14715                                         unsigned num_clips)
14716 {
14717         struct drm_device *dev = fb->dev;
14718         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14719         struct drm_i915_gem_object *obj = intel_fb->obj;
14720
14721         mutex_lock(&dev->struct_mutex);
14722         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14723         mutex_unlock(&dev->struct_mutex);
14724
14725         return 0;
14726 }
14727
14728 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14729         .destroy = intel_user_framebuffer_destroy,
14730         .create_handle = intel_user_framebuffer_create_handle,
14731         .dirty = intel_user_framebuffer_dirty,
14732 };
14733
14734 static
14735 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14736                          uint32_t pixel_format)
14737 {
14738         u32 gen = INTEL_INFO(dev)->gen;
14739
14740         if (gen >= 9) {
14741                 /* "The stride in bytes must not exceed the of the size of 8K
14742                  *  pixels and 32K bytes."
14743                  */
14744                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14745         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14746                 return 32*1024;
14747         } else if (gen >= 4) {
14748                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14749                         return 16*1024;
14750                 else
14751                         return 32*1024;
14752         } else if (gen >= 3) {
14753                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14754                         return 8*1024;
14755                 else
14756                         return 16*1024;
14757         } else {
14758                 /* XXX DSPC is limited to 4k tiled */
14759                 return 8*1024;
14760         }
14761 }
14762
14763 static int intel_framebuffer_init(struct drm_device *dev,
14764                                   struct intel_framebuffer *intel_fb,
14765                                   struct drm_mode_fb_cmd2 *mode_cmd,
14766                                   struct drm_i915_gem_object *obj)
14767 {
14768         unsigned int aligned_height;
14769         int ret;
14770         u32 pitch_limit, stride_alignment;
14771
14772         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14773
14774         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14775                 /* Enforce that fb modifier and tiling mode match, but only for
14776                  * X-tiled. This is needed for FBC. */
14777                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14778                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14779                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14780                         return -EINVAL;
14781                 }
14782         } else {
14783                 if (obj->tiling_mode == I915_TILING_X)
14784                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14785                 else if (obj->tiling_mode == I915_TILING_Y) {
14786                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14787                         return -EINVAL;
14788                 }
14789         }
14790
14791         /* Passed in modifier sanity checking. */
14792         switch (mode_cmd->modifier[0]) {
14793         case I915_FORMAT_MOD_Y_TILED:
14794         case I915_FORMAT_MOD_Yf_TILED:
14795                 if (INTEL_INFO(dev)->gen < 9) {
14796                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14797                                   mode_cmd->modifier[0]);
14798                         return -EINVAL;
14799                 }
14800         case DRM_FORMAT_MOD_NONE:
14801         case I915_FORMAT_MOD_X_TILED:
14802                 break;
14803         default:
14804                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14805                           mode_cmd->modifier[0]);
14806                 return -EINVAL;
14807         }
14808
14809         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14810                                                      mode_cmd->pixel_format);
14811         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14812                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14813                           mode_cmd->pitches[0], stride_alignment);
14814                 return -EINVAL;
14815         }
14816
14817         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14818                                            mode_cmd->pixel_format);
14819         if (mode_cmd->pitches[0] > pitch_limit) {
14820                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14821                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14822                           "tiled" : "linear",
14823                           mode_cmd->pitches[0], pitch_limit);
14824                 return -EINVAL;
14825         }
14826
14827         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14828             mode_cmd->pitches[0] != obj->stride) {
14829                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14830                           mode_cmd->pitches[0], obj->stride);
14831                 return -EINVAL;
14832         }
14833
14834         /* Reject formats not supported by any plane early. */
14835         switch (mode_cmd->pixel_format) {
14836         case DRM_FORMAT_C8:
14837         case DRM_FORMAT_RGB565:
14838         case DRM_FORMAT_XRGB8888:
14839         case DRM_FORMAT_ARGB8888:
14840                 break;
14841         case DRM_FORMAT_XRGB1555:
14842                 if (INTEL_INFO(dev)->gen > 3) {
14843                         DRM_DEBUG("unsupported pixel format: %s\n",
14844                                   drm_get_format_name(mode_cmd->pixel_format));
14845                         return -EINVAL;
14846                 }
14847                 break;
14848         case DRM_FORMAT_ABGR8888:
14849                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14850                     INTEL_INFO(dev)->gen < 9) {
14851                         DRM_DEBUG("unsupported pixel format: %s\n",
14852                                   drm_get_format_name(mode_cmd->pixel_format));
14853                         return -EINVAL;
14854                 }
14855                 break;
14856         case DRM_FORMAT_XBGR8888:
14857         case DRM_FORMAT_XRGB2101010:
14858         case DRM_FORMAT_XBGR2101010:
14859                 if (INTEL_INFO(dev)->gen < 4) {
14860                         DRM_DEBUG("unsupported pixel format: %s\n",
14861                                   drm_get_format_name(mode_cmd->pixel_format));
14862                         return -EINVAL;
14863                 }
14864                 break;
14865         case DRM_FORMAT_ABGR2101010:
14866                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14867                         DRM_DEBUG("unsupported pixel format: %s\n",
14868                                   drm_get_format_name(mode_cmd->pixel_format));
14869                         return -EINVAL;
14870                 }
14871                 break;
14872         case DRM_FORMAT_YUYV:
14873         case DRM_FORMAT_UYVY:
14874         case DRM_FORMAT_YVYU:
14875         case DRM_FORMAT_VYUY:
14876                 if (INTEL_INFO(dev)->gen < 5) {
14877                         DRM_DEBUG("unsupported pixel format: %s\n",
14878                                   drm_get_format_name(mode_cmd->pixel_format));
14879                         return -EINVAL;
14880                 }
14881                 break;
14882         default:
14883                 DRM_DEBUG("unsupported pixel format: %s\n",
14884                           drm_get_format_name(mode_cmd->pixel_format));
14885                 return -EINVAL;
14886         }
14887
14888         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14889         if (mode_cmd->offsets[0] != 0)
14890                 return -EINVAL;
14891
14892         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14893                                                mode_cmd->pixel_format,
14894                                                mode_cmd->modifier[0]);
14895         /* FIXME drm helper for size checks (especially planar formats)? */
14896         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14897                 return -EINVAL;
14898
14899         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14900         intel_fb->obj = obj;
14901         intel_fb->obj->framebuffer_references++;
14902
14903         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14904         if (ret) {
14905                 DRM_ERROR("framebuffer init failed %d\n", ret);
14906                 return ret;
14907         }
14908
14909         return 0;
14910 }
14911
14912 static struct drm_framebuffer *
14913 intel_user_framebuffer_create(struct drm_device *dev,
14914                               struct drm_file *filp,
14915                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14916 {
14917         struct drm_framebuffer *fb;
14918         struct drm_i915_gem_object *obj;
14919         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14920
14921         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14922                                                 mode_cmd.handles[0]));
14923         if (&obj->base == NULL)
14924                 return ERR_PTR(-ENOENT);
14925
14926         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14927         if (IS_ERR(fb))
14928                 drm_gem_object_unreference_unlocked(&obj->base);
14929
14930         return fb;
14931 }
14932
14933 #ifndef CONFIG_DRM_FBDEV_EMULATION
14934 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14935 {
14936 }
14937 #endif
14938
14939 static const struct drm_mode_config_funcs intel_mode_funcs = {
14940         .fb_create = intel_user_framebuffer_create,
14941         .output_poll_changed = intel_fbdev_output_poll_changed,
14942         .atomic_check = intel_atomic_check,
14943         .atomic_commit = intel_atomic_commit,
14944         .atomic_state_alloc = intel_atomic_state_alloc,
14945         .atomic_state_clear = intel_atomic_state_clear,
14946 };
14947
14948 /* Set up chip specific display functions */
14949 static void intel_init_display(struct drm_device *dev)
14950 {
14951         struct drm_i915_private *dev_priv = dev->dev_private;
14952
14953         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14954                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14955         else if (IS_CHERRYVIEW(dev))
14956                 dev_priv->display.find_dpll = chv_find_best_dpll;
14957         else if (IS_VALLEYVIEW(dev))
14958                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14959         else if (IS_PINEVIEW(dev))
14960                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14961         else
14962                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14963
14964         if (INTEL_INFO(dev)->gen >= 9) {
14965                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14966                 dev_priv->display.get_initial_plane_config =
14967                         skylake_get_initial_plane_config;
14968                 dev_priv->display.crtc_compute_clock =
14969                         haswell_crtc_compute_clock;
14970                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14971                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14972         } else if (HAS_DDI(dev)) {
14973                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14974                 dev_priv->display.get_initial_plane_config =
14975                         ironlake_get_initial_plane_config;
14976                 dev_priv->display.crtc_compute_clock =
14977                         haswell_crtc_compute_clock;
14978                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14979                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14980         } else if (HAS_PCH_SPLIT(dev)) {
14981                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14982                 dev_priv->display.get_initial_plane_config =
14983                         ironlake_get_initial_plane_config;
14984                 dev_priv->display.crtc_compute_clock =
14985                         ironlake_crtc_compute_clock;
14986                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14987                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14988         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14989                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14990                 dev_priv->display.get_initial_plane_config =
14991                         i9xx_get_initial_plane_config;
14992                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14993                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14994                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14995         } else {
14996                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14997                 dev_priv->display.get_initial_plane_config =
14998                         i9xx_get_initial_plane_config;
14999                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15000                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15001                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15002         }
15003
15004         /* Returns the core display clock speed */
15005         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15006                 dev_priv->display.get_display_clock_speed =
15007                         skylake_get_display_clock_speed;
15008         else if (IS_BROXTON(dev))
15009                 dev_priv->display.get_display_clock_speed =
15010                         broxton_get_display_clock_speed;
15011         else if (IS_BROADWELL(dev))
15012                 dev_priv->display.get_display_clock_speed =
15013                         broadwell_get_display_clock_speed;
15014         else if (IS_HASWELL(dev))
15015                 dev_priv->display.get_display_clock_speed =
15016                         haswell_get_display_clock_speed;
15017         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15018                 dev_priv->display.get_display_clock_speed =
15019                         valleyview_get_display_clock_speed;
15020         else if (IS_GEN5(dev))
15021                 dev_priv->display.get_display_clock_speed =
15022                         ilk_get_display_clock_speed;
15023         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
15024                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
15025                 dev_priv->display.get_display_clock_speed =
15026                         i945_get_display_clock_speed;
15027         else if (IS_GM45(dev))
15028                 dev_priv->display.get_display_clock_speed =
15029                         gm45_get_display_clock_speed;
15030         else if (IS_CRESTLINE(dev))
15031                 dev_priv->display.get_display_clock_speed =
15032                         i965gm_get_display_clock_speed;
15033         else if (IS_PINEVIEW(dev))
15034                 dev_priv->display.get_display_clock_speed =
15035                         pnv_get_display_clock_speed;
15036         else if (IS_G33(dev) || IS_G4X(dev))
15037                 dev_priv->display.get_display_clock_speed =
15038                         g33_get_display_clock_speed;
15039         else if (IS_I915G(dev))
15040                 dev_priv->display.get_display_clock_speed =
15041                         i915_get_display_clock_speed;
15042         else if (IS_I945GM(dev) || IS_845G(dev))
15043                 dev_priv->display.get_display_clock_speed =
15044                         i9xx_misc_get_display_clock_speed;
15045         else if (IS_I915GM(dev))
15046                 dev_priv->display.get_display_clock_speed =
15047                         i915gm_get_display_clock_speed;
15048         else if (IS_I865G(dev))
15049                 dev_priv->display.get_display_clock_speed =
15050                         i865_get_display_clock_speed;
15051         else if (IS_I85X(dev))
15052                 dev_priv->display.get_display_clock_speed =
15053                         i85x_get_display_clock_speed;
15054         else { /* 830 */
15055                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
15056                 dev_priv->display.get_display_clock_speed =
15057                         i830_get_display_clock_speed;
15058         }
15059
15060         if (IS_GEN5(dev)) {
15061                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15062         } else if (IS_GEN6(dev)) {
15063                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15064         } else if (IS_IVYBRIDGE(dev)) {
15065                 /* FIXME: detect B0+ stepping and use auto training */
15066                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15067         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
15068                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15069                 if (IS_BROADWELL(dev)) {
15070                         dev_priv->display.modeset_commit_cdclk =
15071                                 broadwell_modeset_commit_cdclk;
15072                         dev_priv->display.modeset_calc_cdclk =
15073                                 broadwell_modeset_calc_cdclk;
15074                 }
15075         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15076                 dev_priv->display.modeset_commit_cdclk =
15077                         valleyview_modeset_commit_cdclk;
15078                 dev_priv->display.modeset_calc_cdclk =
15079                         valleyview_modeset_calc_cdclk;
15080         } else if (IS_BROXTON(dev)) {
15081                 dev_priv->display.modeset_commit_cdclk =
15082                         broxton_modeset_commit_cdclk;
15083                 dev_priv->display.modeset_calc_cdclk =
15084                         broxton_modeset_calc_cdclk;
15085         }
15086
15087         switch (INTEL_INFO(dev)->gen) {
15088         case 2:
15089                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15090                 break;
15091
15092         case 3:
15093                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15094                 break;
15095
15096         case 4:
15097         case 5:
15098                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15099                 break;
15100
15101         case 6:
15102                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15103                 break;
15104         case 7:
15105         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15106                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15107                 break;
15108         case 9:
15109                 /* Drop through - unsupported since execlist only. */
15110         default:
15111                 /* Default just returns -ENODEV to indicate unsupported */
15112                 dev_priv->display.queue_flip = intel_default_queue_flip;
15113         }
15114
15115         mutex_init(&dev_priv->pps_mutex);
15116 }
15117
15118 /*
15119  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15120  * resume, or other times.  This quirk makes sure that's the case for
15121  * affected systems.
15122  */
15123 static void quirk_pipea_force(struct drm_device *dev)
15124 {
15125         struct drm_i915_private *dev_priv = dev->dev_private;
15126
15127         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15128         DRM_INFO("applying pipe a force quirk\n");
15129 }
15130
15131 static void quirk_pipeb_force(struct drm_device *dev)
15132 {
15133         struct drm_i915_private *dev_priv = dev->dev_private;
15134
15135         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15136         DRM_INFO("applying pipe b force quirk\n");
15137 }
15138
15139 /*
15140  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15141  */
15142 static void quirk_ssc_force_disable(struct drm_device *dev)
15143 {
15144         struct drm_i915_private *dev_priv = dev->dev_private;
15145         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15146         DRM_INFO("applying lvds SSC disable quirk\n");
15147 }
15148
15149 /*
15150  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15151  * brightness value
15152  */
15153 static void quirk_invert_brightness(struct drm_device *dev)
15154 {
15155         struct drm_i915_private *dev_priv = dev->dev_private;
15156         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15157         DRM_INFO("applying inverted panel brightness quirk\n");
15158 }
15159
15160 /* Some VBT's incorrectly indicate no backlight is present */
15161 static void quirk_backlight_present(struct drm_device *dev)
15162 {
15163         struct drm_i915_private *dev_priv = dev->dev_private;
15164         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15165         DRM_INFO("applying backlight present quirk\n");
15166 }
15167
15168 struct intel_quirk {
15169         int device;
15170         int subsystem_vendor;
15171         int subsystem_device;
15172         void (*hook)(struct drm_device *dev);
15173 };
15174
15175 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15176 struct intel_dmi_quirk {
15177         void (*hook)(struct drm_device *dev);
15178         const struct dmi_system_id (*dmi_id_list)[];
15179 };
15180
15181 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15182 {
15183         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15184         return 1;
15185 }
15186
15187 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15188         {
15189                 .dmi_id_list = &(const struct dmi_system_id[]) {
15190                         {
15191                                 .callback = intel_dmi_reverse_brightness,
15192                                 .ident = "NCR Corporation",
15193                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15194                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15195                                 },
15196                         },
15197                         { }  /* terminating entry */
15198                 },
15199                 .hook = quirk_invert_brightness,
15200         },
15201 };
15202
15203 static struct intel_quirk intel_quirks[] = {
15204         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15205         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15206
15207         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15208         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15209
15210         /* 830 needs to leave pipe A & dpll A up */
15211         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15212
15213         /* 830 needs to leave pipe B & dpll B up */
15214         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15215
15216         /* Lenovo U160 cannot use SSC on LVDS */
15217         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15218
15219         /* Sony Vaio Y cannot use SSC on LVDS */
15220         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15221
15222         /* Acer Aspire 5734Z must invert backlight brightness */
15223         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15224
15225         /* Acer/eMachines G725 */
15226         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15227
15228         /* Acer/eMachines e725 */
15229         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15230
15231         /* Acer/Packard Bell NCL20 */
15232         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15233
15234         /* Acer Aspire 4736Z */
15235         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15236
15237         /* Acer Aspire 5336 */
15238         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15239
15240         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15241         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15242
15243         /* Acer C720 Chromebook (Core i3 4005U) */
15244         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15245
15246         /* Apple Macbook 2,1 (Core 2 T7400) */
15247         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15248
15249         /* Apple Macbook 4,1 */
15250         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15251
15252         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15253         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15254
15255         /* HP Chromebook 14 (Celeron 2955U) */
15256         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15257
15258         /* Dell Chromebook 11 */
15259         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15260
15261         /* Dell Chromebook 11 (2015 version) */
15262         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15263 };
15264
15265 static void intel_init_quirks(struct drm_device *dev)
15266 {
15267         struct pci_dev *d = dev->pdev;
15268         int i;
15269
15270         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15271                 struct intel_quirk *q = &intel_quirks[i];
15272
15273                 if (d->device == q->device &&
15274                     (d->subsystem_vendor == q->subsystem_vendor ||
15275                      q->subsystem_vendor == PCI_ANY_ID) &&
15276                     (d->subsystem_device == q->subsystem_device ||
15277                      q->subsystem_device == PCI_ANY_ID))
15278                         q->hook(dev);
15279         }
15280         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15281                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15282                         intel_dmi_quirks[i].hook(dev);
15283         }
15284 }
15285
15286 /* Disable the VGA plane that we never use */
15287 static void i915_disable_vga(struct drm_device *dev)
15288 {
15289         struct drm_i915_private *dev_priv = dev->dev_private;
15290         u8 sr1;
15291         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15292
15293         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15294         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15295         outb(SR01, VGA_SR_INDEX);
15296         sr1 = inb(VGA_SR_DATA);
15297         outb(sr1 | 1<<5, VGA_SR_DATA);
15298         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15299         udelay(300);
15300
15301         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15302         POSTING_READ(vga_reg);
15303 }
15304
15305 void intel_modeset_init_hw(struct drm_device *dev)
15306 {
15307         struct drm_i915_private *dev_priv = dev->dev_private;
15308
15309         intel_update_cdclk(dev);
15310
15311         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15312
15313         intel_prepare_ddi(dev);
15314         intel_init_clock_gating(dev);
15315         intel_enable_gt_powersave(dev);
15316 }
15317
15318 /*
15319  * Calculate what we think the watermarks should be for the state we've read
15320  * out of the hardware and then immediately program those watermarks so that
15321  * we ensure the hardware settings match our internal state.
15322  *
15323  * We can calculate what we think WM's should be by creating a duplicate of the
15324  * current state (which was constructed during hardware readout) and running it
15325  * through the atomic check code to calculate new watermark values in the
15326  * state object.
15327  */
15328 static void sanitize_watermarks(struct drm_device *dev)
15329 {
15330         struct drm_i915_private *dev_priv = to_i915(dev);
15331         struct drm_atomic_state *state;
15332         struct drm_crtc *crtc;
15333         struct drm_crtc_state *cstate;
15334         struct drm_modeset_acquire_ctx ctx;
15335         int ret;
15336         int i;
15337
15338         /* Only supported on platforms that use atomic watermark design */
15339         if (!dev_priv->display.optimize_watermarks)
15340                 return;
15341
15342         /*
15343          * We need to hold connection_mutex before calling duplicate_state so
15344          * that the connector loop is protected.
15345          */
15346         drm_modeset_acquire_init(&ctx, 0);
15347 retry:
15348         ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
15349         if (ret == -EDEADLK) {
15350                 drm_modeset_backoff(&ctx);
15351                 goto retry;
15352         } else if (WARN_ON(ret)) {
15353                 return;
15354         }
15355
15356         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15357         if (WARN_ON(IS_ERR(state)))
15358                 return;
15359
15360         /*
15361          * Hardware readout is the only time we don't want to calculate
15362          * intermediate watermarks (since we don't trust the current
15363          * watermarks).
15364          */
15365         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15366
15367         ret = intel_atomic_check(dev, state);
15368         if (ret) {
15369                 /*
15370                  * If we fail here, it means that the hardware appears to be
15371                  * programmed in a way that shouldn't be possible, given our
15372                  * understanding of watermark requirements.  This might mean a
15373                  * mistake in the hardware readout code or a mistake in the
15374                  * watermark calculations for a given platform.  Raise a WARN
15375                  * so that this is noticeable.
15376                  *
15377                  * If this actually happens, we'll have to just leave the
15378                  * BIOS-programmed watermarks untouched and hope for the best.
15379                  */
15380                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15381                 return;
15382         }
15383
15384         /* Write calculated watermark values back */
15385         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15386         for_each_crtc_in_state(state, crtc, cstate, i) {
15387                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15388
15389                 cs->wm.need_postvbl_update = true;
15390                 dev_priv->display.optimize_watermarks(cs);
15391         }
15392
15393         drm_atomic_state_free(state);
15394         drm_modeset_drop_locks(&ctx);
15395         drm_modeset_acquire_fini(&ctx);
15396 }
15397
15398 void intel_modeset_init(struct drm_device *dev)
15399 {
15400         struct drm_i915_private *dev_priv = dev->dev_private;
15401         int sprite, ret;
15402         enum pipe pipe;
15403         struct intel_crtc *crtc;
15404
15405         drm_mode_config_init(dev);
15406
15407         dev->mode_config.min_width = 0;
15408         dev->mode_config.min_height = 0;
15409
15410         dev->mode_config.preferred_depth = 24;
15411         dev->mode_config.prefer_shadow = 1;
15412
15413         dev->mode_config.allow_fb_modifiers = true;
15414
15415         dev->mode_config.funcs = &intel_mode_funcs;
15416
15417         intel_init_quirks(dev);
15418
15419         intel_init_pm(dev);
15420
15421         if (INTEL_INFO(dev)->num_pipes == 0)
15422                 return;
15423
15424         /*
15425          * There may be no VBT; and if the BIOS enabled SSC we can
15426          * just keep using it to avoid unnecessary flicker.  Whereas if the
15427          * BIOS isn't using it, don't assume it will work even if the VBT
15428          * indicates as much.
15429          */
15430         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15431                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15432                                             DREF_SSC1_ENABLE);
15433
15434                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15435                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15436                                      bios_lvds_use_ssc ? "en" : "dis",
15437                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15438                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15439                 }
15440         }
15441
15442         intel_init_display(dev);
15443         intel_init_audio(dev);
15444
15445         if (IS_GEN2(dev)) {
15446                 dev->mode_config.max_width = 2048;
15447                 dev->mode_config.max_height = 2048;
15448         } else if (IS_GEN3(dev)) {
15449                 dev->mode_config.max_width = 4096;
15450                 dev->mode_config.max_height = 4096;
15451         } else {
15452                 dev->mode_config.max_width = 8192;
15453                 dev->mode_config.max_height = 8192;
15454         }
15455
15456         if (IS_845G(dev) || IS_I865G(dev)) {
15457                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15458                 dev->mode_config.cursor_height = 1023;
15459         } else if (IS_GEN2(dev)) {
15460                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15461                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15462         } else {
15463                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15464                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15465         }
15466
15467         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15468
15469         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15470                       INTEL_INFO(dev)->num_pipes,
15471                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15472
15473         for_each_pipe(dev_priv, pipe) {
15474                 intel_crtc_init(dev, pipe);
15475                 for_each_sprite(dev_priv, pipe, sprite) {
15476                         ret = intel_plane_init(dev, pipe, sprite);
15477                         if (ret)
15478                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15479                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15480                 }
15481         }
15482
15483         intel_update_czclk(dev_priv);
15484         intel_update_cdclk(dev);
15485
15486         intel_shared_dpll_init(dev);
15487
15488         /* Just disable it once at startup */
15489         i915_disable_vga(dev);
15490         intel_setup_outputs(dev);
15491
15492         drm_modeset_lock_all(dev);
15493         intel_modeset_setup_hw_state(dev);
15494         drm_modeset_unlock_all(dev);
15495
15496         for_each_intel_crtc(dev, crtc) {
15497                 struct intel_initial_plane_config plane_config = {};
15498
15499                 if (!crtc->active)
15500                         continue;
15501
15502                 /*
15503                  * Note that reserving the BIOS fb up front prevents us
15504                  * from stuffing other stolen allocations like the ring
15505                  * on top.  This prevents some ugliness at boot time, and
15506                  * can even allow for smooth boot transitions if the BIOS
15507                  * fb is large enough for the active pipe configuration.
15508                  */
15509                 dev_priv->display.get_initial_plane_config(crtc,
15510                                                            &plane_config);
15511
15512                 /*
15513                  * If the fb is shared between multiple heads, we'll
15514                  * just get the first one.
15515                  */
15516                 intel_find_initial_plane_obj(crtc, &plane_config);
15517         }
15518
15519         /*
15520          * Make sure hardware watermarks really match the state we read out.
15521          * Note that we need to do this after reconstructing the BIOS fb's
15522          * since the watermark calculation done here will use pstate->fb.
15523          */
15524         sanitize_watermarks(dev);
15525 }
15526
15527 static void intel_enable_pipe_a(struct drm_device *dev)
15528 {
15529         struct intel_connector *connector;
15530         struct drm_connector *crt = NULL;
15531         struct intel_load_detect_pipe load_detect_temp;
15532         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15533
15534         /* We can't just switch on the pipe A, we need to set things up with a
15535          * proper mode and output configuration. As a gross hack, enable pipe A
15536          * by enabling the load detect pipe once. */
15537         for_each_intel_connector(dev, connector) {
15538                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15539                         crt = &connector->base;
15540                         break;
15541                 }
15542         }
15543
15544         if (!crt)
15545                 return;
15546
15547         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15548                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15549 }
15550
15551 static bool
15552 intel_check_plane_mapping(struct intel_crtc *crtc)
15553 {
15554         struct drm_device *dev = crtc->base.dev;
15555         struct drm_i915_private *dev_priv = dev->dev_private;
15556         u32 val;
15557
15558         if (INTEL_INFO(dev)->num_pipes == 1)
15559                 return true;
15560
15561         val = I915_READ(DSPCNTR(!crtc->plane));
15562
15563         if ((val & DISPLAY_PLANE_ENABLE) &&
15564             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15565                 return false;
15566
15567         return true;
15568 }
15569
15570 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15571 {
15572         struct drm_device *dev = crtc->base.dev;
15573         struct intel_encoder *encoder;
15574
15575         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15576                 return true;
15577
15578         return false;
15579 }
15580
15581 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15582 {
15583         struct drm_device *dev = crtc->base.dev;
15584         struct drm_i915_private *dev_priv = dev->dev_private;
15585         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15586
15587         /* Clear any frame start delays used for debugging left by the BIOS */
15588         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15589
15590         /* restore vblank interrupts to correct state */
15591         drm_crtc_vblank_reset(&crtc->base);
15592         if (crtc->active) {
15593                 struct intel_plane *plane;
15594
15595                 drm_crtc_vblank_on(&crtc->base);
15596
15597                 /* Disable everything but the primary plane */
15598                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15599                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15600                                 continue;
15601
15602                         plane->disable_plane(&plane->base, &crtc->base);
15603                 }
15604         }
15605
15606         /* We need to sanitize the plane -> pipe mapping first because this will
15607          * disable the crtc (and hence change the state) if it is wrong. Note
15608          * that gen4+ has a fixed plane -> pipe mapping.  */
15609         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15610                 bool plane;
15611
15612                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15613                               crtc->base.base.id);
15614
15615                 /* Pipe has the wrong plane attached and the plane is active.
15616                  * Temporarily change the plane mapping and disable everything
15617                  * ...  */
15618                 plane = crtc->plane;
15619                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15620                 crtc->plane = !plane;
15621                 intel_crtc_disable_noatomic(&crtc->base);
15622                 crtc->plane = plane;
15623         }
15624
15625         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15626             crtc->pipe == PIPE_A && !crtc->active) {
15627                 /* BIOS forgot to enable pipe A, this mostly happens after
15628                  * resume. Force-enable the pipe to fix this, the update_dpms
15629                  * call below we restore the pipe to the right state, but leave
15630                  * the required bits on. */
15631                 intel_enable_pipe_a(dev);
15632         }
15633
15634         /* Adjust the state of the output pipe according to whether we
15635          * have active connectors/encoders. */
15636         if (!intel_crtc_has_encoders(crtc))
15637                 intel_crtc_disable_noatomic(&crtc->base);
15638
15639         if (crtc->active != crtc->base.state->active) {
15640                 struct intel_encoder *encoder;
15641
15642                 /* This can happen either due to bugs in the get_hw_state
15643                  * functions or because of calls to intel_crtc_disable_noatomic,
15644                  * or because the pipe is force-enabled due to the
15645                  * pipe A quirk. */
15646                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15647                               crtc->base.base.id,
15648                               crtc->base.state->enable ? "enabled" : "disabled",
15649                               crtc->active ? "enabled" : "disabled");
15650
15651                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15652                 crtc->base.state->active = crtc->active;
15653                 crtc->base.enabled = crtc->active;
15654
15655                 /* Because we only establish the connector -> encoder ->
15656                  * crtc links if something is active, this means the
15657                  * crtc is now deactivated. Break the links. connector
15658                  * -> encoder links are only establish when things are
15659                  *  actually up, hence no need to break them. */
15660                 WARN_ON(crtc->active);
15661
15662                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15663                         encoder->base.crtc = NULL;
15664         }
15665
15666         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15667                 /*
15668                  * We start out with underrun reporting disabled to avoid races.
15669                  * For correct bookkeeping mark this on active crtcs.
15670                  *
15671                  * Also on gmch platforms we dont have any hardware bits to
15672                  * disable the underrun reporting. Which means we need to start
15673                  * out with underrun reporting disabled also on inactive pipes,
15674                  * since otherwise we'll complain about the garbage we read when
15675                  * e.g. coming up after runtime pm.
15676                  *
15677                  * No protection against concurrent access is required - at
15678                  * worst a fifo underrun happens which also sets this to false.
15679                  */
15680                 crtc->cpu_fifo_underrun_disabled = true;
15681                 crtc->pch_fifo_underrun_disabled = true;
15682         }
15683 }
15684
15685 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15686 {
15687         struct intel_connector *connector;
15688         struct drm_device *dev = encoder->base.dev;
15689         bool active = false;
15690
15691         /* We need to check both for a crtc link (meaning that the
15692          * encoder is active and trying to read from a pipe) and the
15693          * pipe itself being active. */
15694         bool has_active_crtc = encoder->base.crtc &&
15695                 to_intel_crtc(encoder->base.crtc)->active;
15696
15697         for_each_intel_connector(dev, connector) {
15698                 if (connector->base.encoder != &encoder->base)
15699                         continue;
15700
15701                 active = true;
15702                 break;
15703         }
15704
15705         if (active && !has_active_crtc) {
15706                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15707                               encoder->base.base.id,
15708                               encoder->base.name);
15709
15710                 /* Connector is active, but has no active pipe. This is
15711                  * fallout from our resume register restoring. Disable
15712                  * the encoder manually again. */
15713                 if (encoder->base.crtc) {
15714                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15715                                       encoder->base.base.id,
15716                                       encoder->base.name);
15717                         encoder->disable(encoder);
15718                         if (encoder->post_disable)
15719                                 encoder->post_disable(encoder);
15720                 }
15721                 encoder->base.crtc = NULL;
15722
15723                 /* Inconsistent output/port/pipe state happens presumably due to
15724                  * a bug in one of the get_hw_state functions. Or someplace else
15725                  * in our code, like the register restore mess on resume. Clamp
15726                  * things to off as a safer default. */
15727                 for_each_intel_connector(dev, connector) {
15728                         if (connector->encoder != encoder)
15729                                 continue;
15730                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15731                         connector->base.encoder = NULL;
15732                 }
15733         }
15734         /* Enabled encoders without active connectors will be fixed in
15735          * the crtc fixup. */
15736 }
15737
15738 void i915_redisable_vga_power_on(struct drm_device *dev)
15739 {
15740         struct drm_i915_private *dev_priv = dev->dev_private;
15741         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15742
15743         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15744                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15745                 i915_disable_vga(dev);
15746         }
15747 }
15748
15749 void i915_redisable_vga(struct drm_device *dev)
15750 {
15751         struct drm_i915_private *dev_priv = dev->dev_private;
15752
15753         /* This function can be called both from intel_modeset_setup_hw_state or
15754          * at a very early point in our resume sequence, where the power well
15755          * structures are not yet restored. Since this function is at a very
15756          * paranoid "someone might have enabled VGA while we were not looking"
15757          * level, just check if the power well is enabled instead of trying to
15758          * follow the "don't touch the power well if we don't need it" policy
15759          * the rest of the driver uses. */
15760         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15761                 return;
15762
15763         i915_redisable_vga_power_on(dev);
15764 }
15765
15766 static bool primary_get_hw_state(struct intel_plane *plane)
15767 {
15768         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15769
15770         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15771 }
15772
15773 /* FIXME read out full plane state for all planes */
15774 static void readout_plane_state(struct intel_crtc *crtc)
15775 {
15776         struct drm_plane *primary = crtc->base.primary;
15777         struct intel_plane_state *plane_state =
15778                 to_intel_plane_state(primary->state);
15779
15780         plane_state->visible = crtc->active &&
15781                 primary_get_hw_state(to_intel_plane(primary));
15782
15783         if (plane_state->visible)
15784                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15785 }
15786
15787 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15788 {
15789         struct drm_i915_private *dev_priv = dev->dev_private;
15790         enum pipe pipe;
15791         struct intel_crtc *crtc;
15792         struct intel_encoder *encoder;
15793         struct intel_connector *connector;
15794         int i;
15795
15796         dev_priv->active_crtcs = 0;
15797
15798         for_each_intel_crtc(dev, crtc) {
15799                 struct intel_crtc_state *crtc_state = crtc->config;
15800                 int pixclk = 0;
15801
15802                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15803                 memset(crtc_state, 0, sizeof(*crtc_state));
15804                 crtc_state->base.crtc = &crtc->base;
15805
15806                 crtc_state->base.active = crtc_state->base.enable =
15807                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15808
15809                 crtc->base.enabled = crtc_state->base.enable;
15810                 crtc->active = crtc_state->base.active;
15811
15812                 if (crtc_state->base.active) {
15813                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15814
15815                         if (IS_BROADWELL(dev_priv)) {
15816                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15817
15818                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15819                                 if (crtc_state->ips_enabled)
15820                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15821                         } else if (IS_VALLEYVIEW(dev_priv) ||
15822                                    IS_CHERRYVIEW(dev_priv) ||
15823                                    IS_BROXTON(dev_priv))
15824                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15825                         else
15826                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15827                 }
15828
15829                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15830
15831                 readout_plane_state(crtc);
15832
15833                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15834                               crtc->base.base.id,
15835                               crtc->active ? "enabled" : "disabled");
15836         }
15837
15838         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15839                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15840
15841                 pll->on = pll->get_hw_state(dev_priv, pll,
15842                                             &pll->config.hw_state);
15843                 pll->active = 0;
15844                 pll->config.crtc_mask = 0;
15845                 for_each_intel_crtc(dev, crtc) {
15846                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15847                                 pll->active++;
15848                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15849                         }
15850                 }
15851
15852                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15853                               pll->name, pll->config.crtc_mask, pll->on);
15854
15855                 if (pll->config.crtc_mask)
15856                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15857         }
15858
15859         for_each_intel_encoder(dev, encoder) {
15860                 pipe = 0;
15861
15862                 if (encoder->get_hw_state(encoder, &pipe)) {
15863                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15864                         encoder->base.crtc = &crtc->base;
15865                         encoder->get_config(encoder, crtc->config);
15866                 } else {
15867                         encoder->base.crtc = NULL;
15868                 }
15869
15870                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15871                               encoder->base.base.id,
15872                               encoder->base.name,
15873                               encoder->base.crtc ? "enabled" : "disabled",
15874                               pipe_name(pipe));
15875         }
15876
15877         for_each_intel_connector(dev, connector) {
15878                 if (connector->get_hw_state(connector)) {
15879                         connector->base.dpms = DRM_MODE_DPMS_ON;
15880                         connector->base.encoder = &connector->encoder->base;
15881                 } else {
15882                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15883                         connector->base.encoder = NULL;
15884                 }
15885                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15886                               connector->base.base.id,
15887                               connector->base.name,
15888                               connector->base.encoder ? "enabled" : "disabled");
15889         }
15890
15891         for_each_intel_crtc(dev, crtc) {
15892                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15893
15894                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15895                 if (crtc->base.state->active) {
15896                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15897                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15898                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15899
15900                         /*
15901                          * The initial mode needs to be set in order to keep
15902                          * the atomic core happy. It wants a valid mode if the
15903                          * crtc's enabled, so we do the above call.
15904                          *
15905                          * At this point some state updated by the connectors
15906                          * in their ->detect() callback has not run yet, so
15907                          * no recalculation can be done yet.
15908                          *
15909                          * Even if we could do a recalculation and modeset
15910                          * right now it would cause a double modeset if
15911                          * fbdev or userspace chooses a different initial mode.
15912                          *
15913                          * If that happens, someone indicated they wanted a
15914                          * mode change, which means it's safe to do a full
15915                          * recalculation.
15916                          */
15917                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15918
15919                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15920                         update_scanline_offset(crtc);
15921                 }
15922         }
15923 }
15924
15925 /* Scan out the current hw modeset state,
15926  * and sanitizes it to the current state
15927  */
15928 static void
15929 intel_modeset_setup_hw_state(struct drm_device *dev)
15930 {
15931         struct drm_i915_private *dev_priv = dev->dev_private;
15932         enum pipe pipe;
15933         struct intel_crtc *crtc;
15934         struct intel_encoder *encoder;
15935         int i;
15936
15937         intel_modeset_readout_hw_state(dev);
15938
15939         /* HW state is read out, now we need to sanitize this mess. */
15940         for_each_intel_encoder(dev, encoder) {
15941                 intel_sanitize_encoder(encoder);
15942         }
15943
15944         for_each_pipe(dev_priv, pipe) {
15945                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15946                 intel_sanitize_crtc(crtc);
15947                 intel_dump_pipe_config(crtc, crtc->config,
15948                                        "[setup_hw_state]");
15949         }
15950
15951         intel_modeset_update_connector_atomic_state(dev);
15952
15953         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15954                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15955
15956                 if (!pll->on || pll->active)
15957                         continue;
15958
15959                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15960
15961                 pll->disable(dev_priv, pll);
15962                 pll->on = false;
15963         }
15964
15965         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15966                 vlv_wm_get_hw_state(dev);
15967         else if (IS_GEN9(dev))
15968                 skl_wm_get_hw_state(dev);
15969         else if (HAS_PCH_SPLIT(dev))
15970                 ilk_wm_get_hw_state(dev);
15971
15972         for_each_intel_crtc(dev, crtc) {
15973                 unsigned long put_domains;
15974
15975                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15976                 if (WARN_ON(put_domains))
15977                         modeset_put_power_domains(dev_priv, put_domains);
15978         }
15979         intel_display_set_init_power(dev_priv, false);
15980 }
15981
15982 void intel_display_resume(struct drm_device *dev)
15983 {
15984         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15985         struct intel_connector *conn;
15986         struct intel_plane *plane;
15987         struct drm_crtc *crtc;
15988         int ret;
15989
15990         if (!state)
15991                 return;
15992
15993         state->acquire_ctx = dev->mode_config.acquire_ctx;
15994
15995         /* preserve complete old state, including dpll */
15996         intel_atomic_get_shared_dpll_state(state);
15997
15998         for_each_crtc(dev, crtc) {
15999                 struct drm_crtc_state *crtc_state =
16000                         drm_atomic_get_crtc_state(state, crtc);
16001
16002                 ret = PTR_ERR_OR_ZERO(crtc_state);
16003                 if (ret)
16004                         goto err;
16005
16006                 /* force a restore */
16007                 crtc_state->mode_changed = true;
16008         }
16009
16010         for_each_intel_plane(dev, plane) {
16011                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
16012                 if (ret)
16013                         goto err;
16014         }
16015
16016         for_each_intel_connector(dev, conn) {
16017                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
16018                 if (ret)
16019                         goto err;
16020         }
16021
16022         intel_modeset_setup_hw_state(dev);
16023
16024         i915_redisable_vga(dev);
16025         ret = drm_atomic_commit(state);
16026         if (!ret)
16027                 return;
16028
16029 err:
16030         DRM_ERROR("Restoring old state failed with %i\n", ret);
16031         drm_atomic_state_free(state);
16032 }
16033
16034 void intel_modeset_gem_init(struct drm_device *dev)
16035 {
16036         struct drm_crtc *c;
16037         struct drm_i915_gem_object *obj;
16038         int ret;
16039
16040         mutex_lock(&dev->struct_mutex);
16041         intel_init_gt_powersave(dev);
16042         mutex_unlock(&dev->struct_mutex);
16043
16044         intel_modeset_init_hw(dev);
16045
16046         intel_setup_overlay(dev);
16047
16048         /*
16049          * Make sure any fbs we allocated at startup are properly
16050          * pinned & fenced.  When we do the allocation it's too early
16051          * for this.
16052          */
16053         for_each_crtc(dev, c) {
16054                 obj = intel_fb_obj(c->primary->fb);
16055                 if (obj == NULL)
16056                         continue;
16057
16058                 mutex_lock(&dev->struct_mutex);
16059                 ret = intel_pin_and_fence_fb_obj(c->primary,
16060                                                  c->primary->fb,
16061                                                  c->primary->state);
16062                 mutex_unlock(&dev->struct_mutex);
16063                 if (ret) {
16064                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16065                                   to_intel_crtc(c)->pipe);
16066                         drm_framebuffer_unreference(c->primary->fb);
16067                         c->primary->fb = NULL;
16068                         c->primary->crtc = c->primary->state->crtc = NULL;
16069                         update_state_fb(c->primary);
16070                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16071                 }
16072         }
16073
16074         intel_backlight_register(dev);
16075 }
16076
16077 void intel_connector_unregister(struct intel_connector *intel_connector)
16078 {
16079         struct drm_connector *connector = &intel_connector->base;
16080
16081         intel_panel_destroy_backlight(connector);
16082         drm_connector_unregister(connector);
16083 }
16084
16085 void intel_modeset_cleanup(struct drm_device *dev)
16086 {
16087         struct drm_i915_private *dev_priv = dev->dev_private;
16088         struct intel_connector *connector;
16089
16090         intel_disable_gt_powersave(dev);
16091
16092         intel_backlight_unregister(dev);
16093
16094         /*
16095          * Interrupts and polling as the first thing to avoid creating havoc.
16096          * Too much stuff here (turning of connectors, ...) would
16097          * experience fancy races otherwise.
16098          */
16099         intel_irq_uninstall(dev_priv);
16100
16101         /*
16102          * Due to the hpd irq storm handling the hotplug work can re-arm the
16103          * poll handlers. Hence disable polling after hpd handling is shut down.
16104          */
16105         drm_kms_helper_poll_fini(dev);
16106
16107         intel_unregister_dsm_handler();
16108
16109         intel_fbc_disable(dev_priv);
16110
16111         /* flush any delayed tasks or pending work */
16112         flush_scheduled_work();
16113
16114         /* destroy the backlight and sysfs files before encoders/connectors */
16115         for_each_intel_connector(dev, connector)
16116                 connector->unregister(connector);
16117
16118         drm_mode_config_cleanup(dev);
16119
16120         intel_cleanup_overlay(dev);
16121
16122         mutex_lock(&dev->struct_mutex);
16123         intel_cleanup_gt_powersave(dev);
16124         mutex_unlock(&dev->struct_mutex);
16125 }
16126
16127 /*
16128  * Return which encoder is currently attached for connector.
16129  */
16130 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16131 {
16132         return &intel_attached_encoder(connector)->base;
16133 }
16134
16135 void intel_connector_attach_encoder(struct intel_connector *connector,
16136                                     struct intel_encoder *encoder)
16137 {
16138         connector->encoder = encoder;
16139         drm_mode_connector_attach_encoder(&connector->base,
16140                                           &encoder->base);
16141 }
16142
16143 /*
16144  * set vga decode state - true == enable VGA decode
16145  */
16146 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16147 {
16148         struct drm_i915_private *dev_priv = dev->dev_private;
16149         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16150         u16 gmch_ctrl;
16151
16152         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16153                 DRM_ERROR("failed to read control word\n");
16154                 return -EIO;
16155         }
16156
16157         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16158                 return 0;
16159
16160         if (state)
16161                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16162         else
16163                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16164
16165         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16166                 DRM_ERROR("failed to write control word\n");
16167                 return -EIO;
16168         }
16169
16170         return 0;
16171 }
16172
16173 struct intel_display_error_state {
16174
16175         u32 power_well_driver;
16176
16177         int num_transcoders;
16178
16179         struct intel_cursor_error_state {
16180                 u32 control;
16181                 u32 position;
16182                 u32 base;
16183                 u32 size;
16184         } cursor[I915_MAX_PIPES];
16185
16186         struct intel_pipe_error_state {
16187                 bool power_domain_on;
16188                 u32 source;
16189                 u32 stat;
16190         } pipe[I915_MAX_PIPES];
16191
16192         struct intel_plane_error_state {
16193                 u32 control;
16194                 u32 stride;
16195                 u32 size;
16196                 u32 pos;
16197                 u32 addr;
16198                 u32 surface;
16199                 u32 tile_offset;
16200         } plane[I915_MAX_PIPES];
16201
16202         struct intel_transcoder_error_state {
16203                 bool power_domain_on;
16204                 enum transcoder cpu_transcoder;
16205
16206                 u32 conf;
16207
16208                 u32 htotal;
16209                 u32 hblank;
16210                 u32 hsync;
16211                 u32 vtotal;
16212                 u32 vblank;
16213                 u32 vsync;
16214         } transcoder[4];
16215 };
16216
16217 struct intel_display_error_state *
16218 intel_display_capture_error_state(struct drm_device *dev)
16219 {
16220         struct drm_i915_private *dev_priv = dev->dev_private;
16221         struct intel_display_error_state *error;
16222         int transcoders[] = {
16223                 TRANSCODER_A,
16224                 TRANSCODER_B,
16225                 TRANSCODER_C,
16226                 TRANSCODER_EDP,
16227         };
16228         int i;
16229
16230         if (INTEL_INFO(dev)->num_pipes == 0)
16231                 return NULL;
16232
16233         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16234         if (error == NULL)
16235                 return NULL;
16236
16237         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16238                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16239
16240         for_each_pipe(dev_priv, i) {
16241                 error->pipe[i].power_domain_on =
16242                         __intel_display_power_is_enabled(dev_priv,
16243                                                          POWER_DOMAIN_PIPE(i));
16244                 if (!error->pipe[i].power_domain_on)
16245                         continue;
16246
16247                 error->cursor[i].control = I915_READ(CURCNTR(i));
16248                 error->cursor[i].position = I915_READ(CURPOS(i));
16249                 error->cursor[i].base = I915_READ(CURBASE(i));
16250
16251                 error->plane[i].control = I915_READ(DSPCNTR(i));
16252                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16253                 if (INTEL_INFO(dev)->gen <= 3) {
16254                         error->plane[i].size = I915_READ(DSPSIZE(i));
16255                         error->plane[i].pos = I915_READ(DSPPOS(i));
16256                 }
16257                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16258                         error->plane[i].addr = I915_READ(DSPADDR(i));
16259                 if (INTEL_INFO(dev)->gen >= 4) {
16260                         error->plane[i].surface = I915_READ(DSPSURF(i));
16261                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16262                 }
16263
16264                 error->pipe[i].source = I915_READ(PIPESRC(i));
16265
16266                 if (HAS_GMCH_DISPLAY(dev))
16267                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16268         }
16269
16270         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16271         if (HAS_DDI(dev_priv->dev))
16272                 error->num_transcoders++; /* Account for eDP. */
16273
16274         for (i = 0; i < error->num_transcoders; i++) {
16275                 enum transcoder cpu_transcoder = transcoders[i];
16276
16277                 error->transcoder[i].power_domain_on =
16278                         __intel_display_power_is_enabled(dev_priv,
16279                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16280                 if (!error->transcoder[i].power_domain_on)
16281                         continue;
16282
16283                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16284
16285                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16286                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16287                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16288                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16289                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16290                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16291                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16292         }
16293
16294         return error;
16295 }
16296
16297 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16298
16299 void
16300 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16301                                 struct drm_device *dev,
16302                                 struct intel_display_error_state *error)
16303 {
16304         struct drm_i915_private *dev_priv = dev->dev_private;
16305         int i;
16306
16307         if (!error)
16308                 return;
16309
16310         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16311         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16312                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16313                            error->power_well_driver);
16314         for_each_pipe(dev_priv, i) {
16315                 err_printf(m, "Pipe [%d]:\n", i);
16316                 err_printf(m, "  Power: %s\n",
16317                            error->pipe[i].power_domain_on ? "on" : "off");
16318                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16319                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16320
16321                 err_printf(m, "Plane [%d]:\n", i);
16322                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16323                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16324                 if (INTEL_INFO(dev)->gen <= 3) {
16325                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16326                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16327                 }
16328                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16329                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16330                 if (INTEL_INFO(dev)->gen >= 4) {
16331                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16332                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16333                 }
16334
16335                 err_printf(m, "Cursor [%d]:\n", i);
16336                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16337                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16338                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16339         }
16340
16341         for (i = 0; i < error->num_transcoders; i++) {
16342                 err_printf(m, "CPU transcoder: %c\n",
16343                            transcoder_name(error->transcoder[i].cpu_transcoder));
16344                 err_printf(m, "  Power: %s\n",
16345                            error->transcoder[i].power_domain_on ? "on" : "off");
16346                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16347                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16348                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16349                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16350                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16351                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16352                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16353         }
16354 }
16355
16356 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16357 {
16358         struct intel_crtc *crtc;
16359
16360         for_each_intel_crtc(dev, crtc) {
16361                 struct intel_unpin_work *work;
16362
16363                 spin_lock_irq(&dev->event_lock);
16364
16365                 work = crtc->unpin_work;
16366
16367                 if (work && work->event &&
16368                     work->event->base.file_priv == file) {
16369                         kfree(work->event);
16370                         work->event = NULL;
16371                 }
16372
16373                 spin_unlock_irq(&dev->event_lock);
16374         }
16375 }