2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
85 * Returns true on success, false on failure.
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
98 intel_pch_rawclk(struct drm_device *dev)
100 struct drm_i915_private *dev_priv = dev->dev_private;
102 WARN_ON(!HAS_PCH_SPLIT(dev));
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
130 static inline u32 /* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device *dev)
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
140 static const intel_limit_t intel_limits_i8xx_dvo = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
151 .find_pll = intel_find_best_PLL,
154 static const intel_limit_t intel_limits_i8xx_lvds = {
155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
168 static const intel_limit_t intel_limits_i9xx_sdvo = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
179 .find_pll = intel_find_best_PLL,
182 static const intel_limit_t intel_limits_i9xx_lvds = {
183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
193 .find_pll = intel_find_best_PLL,
197 static const intel_limit_t intel_limits_g4x_sdvo = {
198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
210 .find_pll = intel_g4x_find_best_PLL,
213 static const intel_limit_t intel_limits_g4x_hdmi = {
214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
224 .find_pll = intel_g4x_find_best_PLL,
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
239 .find_pll = intel_g4x_find_best_PLL,
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
254 .find_pll = intel_g4x_find_best_PLL,
257 static const intel_limit_t intel_limits_g4x_display_port = {
258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 10, .p2_fast = 10 },
268 .find_pll = intel_find_pll_g4x_dp,
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_find_best_PLL,
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_find_best_PLL,
301 /* Ironlake / Sandybridge
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
306 static const intel_limit_t intel_limits_ironlake_dac = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
317 .find_pll = intel_g4x_find_best_PLL,
320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
357 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
360 .find_pll = intel_g4x_find_best_PLL,
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 .find_pll = intel_g4x_find_best_PLL,
377 static const intel_limit_t intel_limits_ironlake_display_port = {
378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
387 .p2_slow = 10, .p2_fast = 10 },
388 .find_pll = intel_find_pll_ironlake_dp,
391 static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
405 static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
407 .vco = { .min = 4000000, .max = 5994000},
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
419 static const intel_limit_t intel_limits_vlv_dp = {
420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
422 .n = { .min = 1, .max = 7 },
423 .m = { .min = 22, .max = 450 },
424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
450 return I915_READ(DPIO_DATA);
453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
471 static void vlv_init_dpio(struct drm_device *dev)
473 struct drm_i915_private *dev_priv = dev->dev_private;
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
485 struct drm_device *dev = crtc->dev;
486 const intel_limit_t *limit;
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
489 if (intel_is_dual_link_lvds(dev)) {
490 if (refclk == 100000)
491 limit = &intel_limits_ironlake_dual_lvds_100m;
493 limit = &intel_limits_ironlake_dual_lvds;
495 if (refclk == 100000)
496 limit = &intel_limits_ironlake_single_lvds_100m;
498 limit = &intel_limits_ironlake_single_lvds;
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
502 limit = &intel_limits_ironlake_display_port;
504 limit = &intel_limits_ironlake_dac;
509 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
511 struct drm_device *dev = crtc->dev;
512 const intel_limit_t *limit;
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
515 if (intel_is_dual_link_lvds(dev))
516 limit = &intel_limits_g4x_dual_channel_lvds;
518 limit = &intel_limits_g4x_single_channel_lvds;
519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
521 limit = &intel_limits_g4x_hdmi;
522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
523 limit = &intel_limits_g4x_sdvo;
524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
525 limit = &intel_limits_g4x_display_port;
526 } else /* The option is for other outputs */
527 limit = &intel_limits_i9xx_sdvo;
532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
537 if (HAS_PCH_SPLIT(dev))
538 limit = intel_ironlake_limit(crtc, refclk);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc);
541 } else if (IS_PINEVIEW(dev)) {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_pineview_lvds;
545 limit = &intel_limits_pineview_sdvo;
546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
552 limit = &intel_limits_vlv_dp;
553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
557 limit = &intel_limits_i9xx_sdvo;
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
560 limit = &intel_limits_i8xx_lvds;
562 limit = &intel_limits_i8xx_dvo;
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk, intel_clock_t *clock)
570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
576 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
589 * Returns whether any output on the specified pipe is of the specified type
591 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
593 struct drm_device *dev = crtc->dev;
594 struct intel_encoder *encoder;
596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
609 static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock->p < limit->p.min || limit->p.max < clock->p)
616 INTELPllInvalid("p out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock->m < limit->m.min || limit->m.max < clock->m)
624 INTELPllInvalid("m out of range\n");
625 if (clock->n < limit->n.min || limit->n.max < clock->n)
626 INTELPllInvalid("n out of range\n");
627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
633 INTELPllInvalid("dot out of range\n");
639 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
644 struct drm_device *dev = crtc->dev;
648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
657 clock.p2 = limit->p2.p2_slow;
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
662 clock.p2 = limit->p2.p2_fast;
665 memset(best_clock, 0, sizeof(*best_clock));
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
680 intel_clock(dev, refclk, &clock);
681 if (!intel_PLL_is_valid(dev, limit,
685 clock.p != match_clock->p)
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
698 return (err != target);
702 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
706 struct drm_device *dev = crtc->dev;
710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (HAS_PCH_SPLIT(dev))
721 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast;
724 clock.p2 = limit->p2.p2_slow;
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
729 clock.p2 = limit->p2.p2_fast;
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
745 intel_clock(dev, refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
750 clock.p != match_clock->p)
753 this_err = abs(clock.dot - target);
754 if (this_err < err_most) {
768 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
772 struct drm_device *dev = crtc->dev;
775 if (target < 200000) {
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
795 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
800 if (target < 200000) {
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
821 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
832 dotclk = target * 1000;
835 fastclk = dotclk / (2*100);
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
863 if (absppm < bestppm - 10) {
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
889 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
895 return intel_crtc->cpu_transcoder;
898 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
903 frame = I915_READ(frame_reg);
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
910 * intel_wait_for_vblank - wait for vblank on a given pipe
912 * @pipe: pipe to wait for
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
917 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 int pipestat_reg = PIPESTAT(pipe);
922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
947 DRM_DEBUG_KMS("vblank wait timed out\n");
951 * intel_wait_for_pipe_off - wait for pipe to turn off
953 * @pipe: pipe to wait for
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
960 * wait for the pipe register state bit to turn off
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
967 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
973 if (INTEL_INFO(dev)->gen >= 4) {
974 int reg = PIPECONF(cpu_transcoder);
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
979 WARN(1, "pipe_off wait timed out\n");
981 u32 last_line, line_mask;
982 int reg = PIPEDSL(pipe);
983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
986 line_mask = DSL_LINEMASK_GEN2;
988 line_mask = DSL_LINEMASK_GEN3;
990 /* Wait for the display line to settle */
992 last_line = I915_READ(reg) & line_mask;
994 } while (((I915_READ(reg) & line_mask) != last_line) &&
995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
997 WARN(1, "pipe_off wait timed out\n");
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1006 * Returns true if @port is connected, false otherwise.
1008 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1016 bit = SDE_PORTB_HOTPLUG;
1019 bit = SDE_PORTC_HOTPLUG;
1022 bit = SDE_PORTD_HOTPLUG;
1028 switch(port->port) {
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1043 return I915_READ(SDEISR) & bit;
1046 static const char *state_string(bool enabled)
1048 return enabled ? "on" : "off";
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1070 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv->dev))
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191 int pp_reg, lvds_reg;
1193 enum pipe panel_pipe = PIPE_A;
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1200 pp_reg = PP_CONTROL;
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
1217 void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
1291 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1296 if (HAS_PCH_LPT(dev_priv->dev)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1301 val = I915_READ(PCH_DREF_CONTROL);
1302 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303 DREF_SUPERSPREAD_SOURCE_MASK));
1304 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1307 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1314 reg = TRANSCONF(pipe);
1315 val = I915_READ(reg);
1316 enabled = !!(val & TRANS_ENABLE);
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1322 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 port_sel, u32 val)
1325 if ((val & DP_PORT_EN) == 0)
1328 if (HAS_PCH_CPT(dev_priv->dev)) {
1329 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1334 if ((val & DP_PIPE_MASK) != (pipe << 30))
1340 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1343 if ((val & SDVO_ENABLE) == 0)
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1350 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1356 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1359 if ((val & LVDS_PORT_EN) == 0)
1362 if (HAS_PCH_CPT(dev_priv->dev)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1372 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 val)
1375 if ((val & ADPA_DAC_ENABLE) == 0)
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1381 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1387 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, int reg, u32 port_sel)
1390 u32 val = I915_READ(reg);
1391 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1393 reg, pipe_name(pipe));
1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396 && (val & DP_PIPEB_SELECT),
1397 "IBX PCH dp port still using transcoder B\n");
1400 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg)
1403 u32 val = I915_READ(reg);
1404 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1406 reg, pipe_name(pipe));
1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1409 && (val & SDVO_PIPE_B_SELECT),
1410 "IBX PCH hdmi port still using transcoder B\n");
1413 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1424 val = I915_READ(reg);
1425 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
1430 val = I915_READ(reg);
1431 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1435 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1449 * Note! This is for pre-ILK only.
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1453 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1458 /* No really, not for ILK+ */
1459 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1463 assert_panel_unlocked(dev_priv, pipe);
1466 val = I915_READ(reg);
1467 val |= DPLL_VCO_ENABLE;
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, val);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, val);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, val);
1478 udelay(150); /* wait for warmup */
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1488 * Note! This is for pre-ILK only.
1490 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv, pipe);
1503 val = I915_READ(reg);
1504 val &= ~DPLL_VCO_ENABLE;
1505 I915_WRITE(reg, val);
1511 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1512 enum intel_sbi_destination destination)
1516 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1518 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
1524 I915_WRITE(SBI_ADDR, (reg << 16));
1525 I915_WRITE(SBI_DATA, value);
1527 if (destination == SBI_ICLK)
1528 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1530 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1531 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1533 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1541 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
1545 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1547 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
1553 I915_WRITE(SBI_ADDR, (reg << 16));
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1567 return I915_READ(SBI_DATA);
1571 * ironlake_enable_pch_pll - enable PCH PLL
1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1578 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1581 struct intel_pch_pll *pll;
1585 /* PCH PLLs only available on ILK, SNB and IVB */
1586 BUG_ON(dev_priv->info->gen < 5);
1587 pll = intel_crtc->pch_pll;
1591 if (WARN_ON(pll->refcount == 0))
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1601 if (pll->active++ && pll->on) {
1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1618 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
1630 if (WARN_ON(pll->refcount == 0))
1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
1637 if (WARN_ON(pll->active == 0)) {
1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
1642 if (--pll->active) {
1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1665 struct drm_device *dev = dev_priv->dev;
1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1667 uint32_t reg, val, pipeconf_val;
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1672 /* Make sure PCH DPLL is enabled */
1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
1692 pipeconf_val = I915_READ(PIPECONF(pipe));
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1699 val &= ~PIPECONF_BPC_MASK;
1700 val |= pipeconf_val & PIPECONF_BPC_MASK;
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1709 val |= TRANS_INTERLACED;
1711 val |= TRANS_PROGRESSIVE;
1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1719 enum transcoder cpu_transcoder)
1721 u32 val, pipeconf_val;
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
1740 val |= TRANS_INTERLACED;
1742 val |= TRANS_PROGRESSIVE;
1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1752 struct drm_device *dev = dev_priv->dev;
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1783 val = I915_READ(_TRANSACONF);
1784 val &= ~TRANS_ENABLE;
1785 I915_WRITE(_TRANSACONF, val);
1786 /* wait for PCH transcoder off, transcoder state */
1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1793 I915_WRITE(_TRANSA_CHICKEN2, val);
1797 * intel_enable_pipe - enable a pipe, asserting requirements
1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1805 * @pipe should be %PIPE_A or %PIPE_B.
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1810 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1815 enum pipe pch_transcoder;
1819 if (HAS_PCH_LPT(dev_priv->dev))
1820 pch_transcoder = TRANSCODER_A;
1822 pch_transcoder = pipe;
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
1833 /* if driving the PCH, we need FDI enabled */
1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1835 assert_fdi_tx_pll_enabled(dev_priv,
1836 (enum pipe) cpu_transcoder);
1838 /* FIXME: assert CPU port conditions for SNB+ */
1841 reg = PIPECONF(cpu_transcoder);
1842 val = I915_READ(reg);
1843 if (val & PIPECONF_ENABLE)
1846 I915_WRITE(reg, val | PIPECONF_ENABLE);
1847 intel_wait_for_vblank(dev_priv->dev, pipe);
1851 * intel_disable_pipe - disable a pipe, asserting requirements
1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1858 * @pipe should be %PIPE_A or %PIPE_B.
1860 * Will wait until the pipe has shut down before returning.
1862 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1865 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1874 assert_planes_disabled(dev_priv, pipe);
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1880 reg = PIPECONF(cpu_transcoder);
1881 val = I915_READ(reg);
1882 if ((val & PIPECONF_ENABLE) == 0)
1885 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1886 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1893 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1896 if (dev_priv->info->gen >= 4)
1897 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1899 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1910 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1911 enum plane plane, enum pipe pipe)
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv, pipe);
1919 reg = DSPCNTR(plane);
1920 val = I915_READ(reg);
1921 if (val & DISPLAY_PLANE_ENABLE)
1924 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1925 intel_flush_display_plane(dev_priv, plane);
1926 intel_wait_for_vblank(dev_priv->dev, pipe);
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1935 * Disable @plane; should be an independent operation.
1937 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1943 reg = DSPCNTR(plane);
1944 val = I915_READ(reg);
1945 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1948 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1949 intel_flush_display_plane(dev_priv, plane);
1950 intel_wait_for_vblank(dev_priv->dev, pipe);
1953 static bool need_vtd_wa(struct drm_device *dev)
1955 #ifdef CONFIG_INTEL_IOMMU
1956 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1963 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1964 struct drm_i915_gem_object *obj,
1965 struct intel_ring_buffer *pipelined)
1967 struct drm_i915_private *dev_priv = dev->dev_private;
1971 switch (obj->tiling_mode) {
1972 case I915_TILING_NONE:
1973 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1974 alignment = 128 * 1024;
1975 else if (INTEL_INFO(dev)->gen >= 4)
1976 alignment = 4 * 1024;
1978 alignment = 64 * 1024;
1981 /* pin() will align the object as required by fence */
1985 /* FIXME: Is this true? */
1986 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1992 /* Note that the w/a also requires 64 PTE of padding following the
1993 * bo. We currently fill all unused PTE with the shadow page and so
1994 * we should always have valid PTE following the scanout preventing
1997 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1998 alignment = 256 * 1024;
2000 dev_priv->mm.interruptible = false;
2001 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2003 goto err_interruptible;
2005 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2006 * fence, whereas 965+ only requires a fence if using
2007 * framebuffer compression. For simplicity, we always install
2008 * a fence as the cost is not that onerous.
2010 ret = i915_gem_object_get_fence(obj);
2014 i915_gem_object_pin_fence(obj);
2016 dev_priv->mm.interruptible = true;
2020 i915_gem_object_unpin(obj);
2022 dev_priv->mm.interruptible = true;
2026 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2028 i915_gem_object_unpin_fence(obj);
2029 i915_gem_object_unpin(obj);
2032 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2033 * is assumed to be a power-of-two. */
2034 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2035 unsigned int tiling_mode,
2039 if (tiling_mode != I915_TILING_NONE) {
2040 unsigned int tile_rows, tiles;
2045 tiles = *x / (512/cpp);
2048 return tile_rows * pitch * 8 + tiles * 4096;
2050 unsigned int offset;
2052 offset = *y * pitch + *x * cpp;
2054 *x = (offset & 4095) / cpp;
2055 return offset & -4096;
2059 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2062 struct drm_device *dev = crtc->dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2065 struct intel_framebuffer *intel_fb;
2066 struct drm_i915_gem_object *obj;
2067 int plane = intel_crtc->plane;
2068 unsigned long linear_offset;
2077 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2081 intel_fb = to_intel_framebuffer(fb);
2082 obj = intel_fb->obj;
2084 reg = DSPCNTR(plane);
2085 dspcntr = I915_READ(reg);
2086 /* Mask out pixel format bits in case we change it */
2087 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2088 switch (fb->pixel_format) {
2090 dspcntr |= DISPPLANE_8BPP;
2092 case DRM_FORMAT_XRGB1555:
2093 case DRM_FORMAT_ARGB1555:
2094 dspcntr |= DISPPLANE_BGRX555;
2096 case DRM_FORMAT_RGB565:
2097 dspcntr |= DISPPLANE_BGRX565;
2099 case DRM_FORMAT_XRGB8888:
2100 case DRM_FORMAT_ARGB8888:
2101 dspcntr |= DISPPLANE_BGRX888;
2103 case DRM_FORMAT_XBGR8888:
2104 case DRM_FORMAT_ABGR8888:
2105 dspcntr |= DISPPLANE_RGBX888;
2107 case DRM_FORMAT_XRGB2101010:
2108 case DRM_FORMAT_ARGB2101010:
2109 dspcntr |= DISPPLANE_BGRX101010;
2111 case DRM_FORMAT_XBGR2101010:
2112 case DRM_FORMAT_ABGR2101010:
2113 dspcntr |= DISPPLANE_RGBX101010;
2119 if (INTEL_INFO(dev)->gen >= 4) {
2120 if (obj->tiling_mode != I915_TILING_NONE)
2121 dspcntr |= DISPPLANE_TILED;
2123 dspcntr &= ~DISPPLANE_TILED;
2126 I915_WRITE(reg, dspcntr);
2128 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2130 if (INTEL_INFO(dev)->gen >= 4) {
2131 intel_crtc->dspaddr_offset =
2132 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2133 fb->bits_per_pixel / 8,
2135 linear_offset -= intel_crtc->dspaddr_offset;
2137 intel_crtc->dspaddr_offset = linear_offset;
2140 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2141 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2142 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2143 if (INTEL_INFO(dev)->gen >= 4) {
2144 I915_MODIFY_DISPBASE(DSPSURF(plane),
2145 obj->gtt_offset + intel_crtc->dspaddr_offset);
2146 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2147 I915_WRITE(DSPLINOFF(plane), linear_offset);
2149 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2155 static int ironlake_update_plane(struct drm_crtc *crtc,
2156 struct drm_framebuffer *fb, int x, int y)
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2161 struct intel_framebuffer *intel_fb;
2162 struct drm_i915_gem_object *obj;
2163 int plane = intel_crtc->plane;
2164 unsigned long linear_offset;
2174 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2178 intel_fb = to_intel_framebuffer(fb);
2179 obj = intel_fb->obj;
2181 reg = DSPCNTR(plane);
2182 dspcntr = I915_READ(reg);
2183 /* Mask out pixel format bits in case we change it */
2184 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2185 switch (fb->pixel_format) {
2187 dspcntr |= DISPPLANE_8BPP;
2189 case DRM_FORMAT_RGB565:
2190 dspcntr |= DISPPLANE_BGRX565;
2192 case DRM_FORMAT_XRGB8888:
2193 case DRM_FORMAT_ARGB8888:
2194 dspcntr |= DISPPLANE_BGRX888;
2196 case DRM_FORMAT_XBGR8888:
2197 case DRM_FORMAT_ABGR8888:
2198 dspcntr |= DISPPLANE_RGBX888;
2200 case DRM_FORMAT_XRGB2101010:
2201 case DRM_FORMAT_ARGB2101010:
2202 dspcntr |= DISPPLANE_BGRX101010;
2204 case DRM_FORMAT_XBGR2101010:
2205 case DRM_FORMAT_ABGR2101010:
2206 dspcntr |= DISPPLANE_RGBX101010;
2212 if (obj->tiling_mode != I915_TILING_NONE)
2213 dspcntr |= DISPPLANE_TILED;
2215 dspcntr &= ~DISPPLANE_TILED;
2218 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2220 I915_WRITE(reg, dspcntr);
2222 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2223 intel_crtc->dspaddr_offset =
2224 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2225 fb->bits_per_pixel / 8,
2227 linear_offset -= intel_crtc->dspaddr_offset;
2229 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2230 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2231 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2232 I915_MODIFY_DISPBASE(DSPSURF(plane),
2233 obj->gtt_offset + intel_crtc->dspaddr_offset);
2234 if (IS_HASWELL(dev)) {
2235 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2237 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2238 I915_WRITE(DSPLINOFF(plane), linear_offset);
2245 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2247 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2248 int x, int y, enum mode_set_atomic state)
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2253 if (dev_priv->display.disable_fbc)
2254 dev_priv->display.disable_fbc(dev);
2255 intel_increase_pllclock(crtc);
2257 return dev_priv->display.update_plane(crtc, fb, x, y);
2260 void intel_display_handle_reset(struct drm_device *dev)
2262 struct drm_i915_private *dev_priv = dev->dev_private;
2263 struct drm_crtc *crtc;
2266 * Flips in the rings have been nuked by the reset,
2267 * so complete all pending flips so that user space
2268 * will get its events and not get stuck.
2270 * Also update the base address of all primary
2271 * planes to the the last fb to make sure we're
2272 * showing the correct fb after a reset.
2274 * Need to make two loops over the crtcs so that we
2275 * don't try to grab a crtc mutex before the
2276 * pending_flip_queue really got woken up.
2279 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281 enum plane plane = intel_crtc->plane;
2283 intel_prepare_page_flip(dev, plane);
2284 intel_finish_page_flip_plane(dev, plane);
2287 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290 mutex_lock(&crtc->mutex);
2291 if (intel_crtc->active)
2292 dev_priv->display.update_plane(crtc, crtc->fb,
2294 mutex_unlock(&crtc->mutex);
2299 intel_finish_fb(struct drm_framebuffer *old_fb)
2301 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2302 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2303 bool was_interruptible = dev_priv->mm.interruptible;
2306 /* Big Hammer, we also need to ensure that any pending
2307 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2308 * current scanout is retired before unpinning the old
2311 * This should only fail upon a hung GPU, in which case we
2312 * can safely continue.
2314 dev_priv->mm.interruptible = false;
2315 ret = i915_gem_object_finish_gpu(obj);
2316 dev_priv->mm.interruptible = was_interruptible;
2321 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2323 struct drm_device *dev = crtc->dev;
2324 struct drm_i915_master_private *master_priv;
2325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327 if (!dev->primary->master)
2330 master_priv = dev->primary->master->driver_priv;
2331 if (!master_priv->sarea_priv)
2334 switch (intel_crtc->pipe) {
2336 master_priv->sarea_priv->pipeA_x = x;
2337 master_priv->sarea_priv->pipeA_y = y;
2340 master_priv->sarea_priv->pipeB_x = x;
2341 master_priv->sarea_priv->pipeB_y = y;
2349 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2350 struct drm_framebuffer *fb)
2352 struct drm_device *dev = crtc->dev;
2353 struct drm_i915_private *dev_priv = dev->dev_private;
2354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2355 struct drm_framebuffer *old_fb;
2360 DRM_ERROR("No FB bound\n");
2364 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2365 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2367 INTEL_INFO(dev)->num_pipes);
2371 mutex_lock(&dev->struct_mutex);
2372 ret = intel_pin_and_fence_fb_obj(dev,
2373 to_intel_framebuffer(fb)->obj,
2376 mutex_unlock(&dev->struct_mutex);
2377 DRM_ERROR("pin & fence failed\n");
2381 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2383 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2384 mutex_unlock(&dev->struct_mutex);
2385 DRM_ERROR("failed to update base address\n");
2395 intel_wait_for_vblank(dev, intel_crtc->pipe);
2396 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2399 intel_update_fbc(dev);
2400 mutex_unlock(&dev->struct_mutex);
2402 intel_crtc_update_sarea_pos(crtc, x, y);
2407 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2409 struct drm_device *dev = crtc->dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412 int pipe = intel_crtc->pipe;
2415 /* enable normal train */
2416 reg = FDI_TX_CTL(pipe);
2417 temp = I915_READ(reg);
2418 if (IS_IVYBRIDGE(dev)) {
2419 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2420 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2422 temp &= ~FDI_LINK_TRAIN_NONE;
2423 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2425 I915_WRITE(reg, temp);
2427 reg = FDI_RX_CTL(pipe);
2428 temp = I915_READ(reg);
2429 if (HAS_PCH_CPT(dev)) {
2430 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2431 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_NONE;
2436 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2438 /* wait one idle pattern time */
2442 /* IVB wants error correction enabled */
2443 if (IS_IVYBRIDGE(dev))
2444 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2445 FDI_FE_ERRC_ENABLE);
2448 static void ivb_modeset_global_resources(struct drm_device *dev)
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 struct intel_crtc *pipe_B_crtc =
2452 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2453 struct intel_crtc *pipe_C_crtc =
2454 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2457 /* When everything is off disable fdi C so that we could enable fdi B
2458 * with all lanes. XXX: This misses the case where a pipe is not using
2459 * any pch resources and so doesn't need any fdi lanes. */
2460 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2461 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2462 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2464 temp = I915_READ(SOUTH_CHICKEN1);
2465 temp &= ~FDI_BC_BIFURCATION_SELECT;
2466 DRM_DEBUG_KMS("disabling fdi C rx\n");
2467 I915_WRITE(SOUTH_CHICKEN1, temp);
2471 /* The FDI link training functions for ILK/Ibexpeak. */
2472 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2474 struct drm_device *dev = crtc->dev;
2475 struct drm_i915_private *dev_priv = dev->dev_private;
2476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2477 int pipe = intel_crtc->pipe;
2478 int plane = intel_crtc->plane;
2479 u32 reg, temp, tries;
2481 /* FDI needs bits from pipe & plane first */
2482 assert_pipe_enabled(dev_priv, pipe);
2483 assert_plane_enabled(dev_priv, plane);
2485 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2487 reg = FDI_RX_IMR(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~FDI_RX_SYMBOL_LOCK;
2490 temp &= ~FDI_RX_BIT_LOCK;
2491 I915_WRITE(reg, temp);
2495 /* enable CPU FDI TX and PCH FDI RX */
2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
2499 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2504 reg = FDI_RX_CTL(pipe);
2505 temp = I915_READ(reg);
2506 temp &= ~FDI_LINK_TRAIN_NONE;
2507 temp |= FDI_LINK_TRAIN_PATTERN_1;
2508 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2513 /* Ironlake workaround, enable clock pointer after FDI enable*/
2514 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2515 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2516 FDI_RX_PHASE_SYNC_POINTER_EN);
2518 reg = FDI_RX_IIR(pipe);
2519 for (tries = 0; tries < 5; tries++) {
2520 temp = I915_READ(reg);
2521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2523 if ((temp & FDI_RX_BIT_LOCK)) {
2524 DRM_DEBUG_KMS("FDI train 1 done.\n");
2525 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2530 DRM_ERROR("FDI train 1 fail!\n");
2533 reg = FDI_TX_CTL(pipe);
2534 temp = I915_READ(reg);
2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
2537 I915_WRITE(reg, temp);
2539 reg = FDI_RX_CTL(pipe);
2540 temp = I915_READ(reg);
2541 temp &= ~FDI_LINK_TRAIN_NONE;
2542 temp |= FDI_LINK_TRAIN_PATTERN_2;
2543 I915_WRITE(reg, temp);
2548 reg = FDI_RX_IIR(pipe);
2549 for (tries = 0; tries < 5; tries++) {
2550 temp = I915_READ(reg);
2551 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2553 if (temp & FDI_RX_SYMBOL_LOCK) {
2554 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2555 DRM_DEBUG_KMS("FDI train 2 done.\n");
2560 DRM_ERROR("FDI train 2 fail!\n");
2562 DRM_DEBUG_KMS("FDI train done\n");
2566 static const int snb_b_fdi_train_param[] = {
2567 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2568 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2569 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2570 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2573 /* The FDI link training functions for SNB/Cougarpoint. */
2574 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2576 struct drm_device *dev = crtc->dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2579 int pipe = intel_crtc->pipe;
2580 u32 reg, temp, i, retry;
2582 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2584 reg = FDI_RX_IMR(pipe);
2585 temp = I915_READ(reg);
2586 temp &= ~FDI_RX_SYMBOL_LOCK;
2587 temp &= ~FDI_RX_BIT_LOCK;
2588 I915_WRITE(reg, temp);
2593 /* enable CPU FDI TX and PCH FDI RX */
2594 reg = FDI_TX_CTL(pipe);
2595 temp = I915_READ(reg);
2597 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_1;
2600 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2603 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2605 I915_WRITE(FDI_RX_MISC(pipe),
2606 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2608 reg = FDI_RX_CTL(pipe);
2609 temp = I915_READ(reg);
2610 if (HAS_PCH_CPT(dev)) {
2611 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2612 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2614 temp &= ~FDI_LINK_TRAIN_NONE;
2615 temp |= FDI_LINK_TRAIN_PATTERN_1;
2617 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2622 for (i = 0; i < 4; i++) {
2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= snb_b_fdi_train_param[i];
2627 I915_WRITE(reg, temp);
2632 for (retry = 0; retry < 5; retry++) {
2633 reg = FDI_RX_IIR(pipe);
2634 temp = I915_READ(reg);
2635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2636 if (temp & FDI_RX_BIT_LOCK) {
2637 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2638 DRM_DEBUG_KMS("FDI train 1 done.\n");
2647 DRM_ERROR("FDI train 1 fail!\n");
2650 reg = FDI_TX_CTL(pipe);
2651 temp = I915_READ(reg);
2652 temp &= ~FDI_LINK_TRAIN_NONE;
2653 temp |= FDI_LINK_TRAIN_PATTERN_2;
2655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2659 I915_WRITE(reg, temp);
2661 reg = FDI_RX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 if (HAS_PCH_CPT(dev)) {
2664 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2665 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2667 temp &= ~FDI_LINK_TRAIN_NONE;
2668 temp |= FDI_LINK_TRAIN_PATTERN_2;
2670 I915_WRITE(reg, temp);
2675 for (i = 0; i < 4; i++) {
2676 reg = FDI_TX_CTL(pipe);
2677 temp = I915_READ(reg);
2678 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2679 temp |= snb_b_fdi_train_param[i];
2680 I915_WRITE(reg, temp);
2685 for (retry = 0; retry < 5; retry++) {
2686 reg = FDI_RX_IIR(pipe);
2687 temp = I915_READ(reg);
2688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2689 if (temp & FDI_RX_SYMBOL_LOCK) {
2690 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2691 DRM_DEBUG_KMS("FDI train 2 done.\n");
2700 DRM_ERROR("FDI train 2 fail!\n");
2702 DRM_DEBUG_KMS("FDI train done.\n");
2705 /* Manual link training for Ivy Bridge A0 parts */
2706 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2708 struct drm_device *dev = crtc->dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2711 int pipe = intel_crtc->pipe;
2714 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2716 reg = FDI_RX_IMR(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~FDI_RX_SYMBOL_LOCK;
2719 temp &= ~FDI_RX_BIT_LOCK;
2720 I915_WRITE(reg, temp);
2725 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2726 I915_READ(FDI_RX_IIR(pipe)));
2728 /* enable CPU FDI TX and PCH FDI RX */
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2732 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2733 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2737 temp |= FDI_COMPOSITE_SYNC;
2738 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2740 I915_WRITE(FDI_RX_MISC(pipe),
2741 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2743 reg = FDI_RX_CTL(pipe);
2744 temp = I915_READ(reg);
2745 temp &= ~FDI_LINK_TRAIN_AUTO;
2746 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2747 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2748 temp |= FDI_COMPOSITE_SYNC;
2749 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2754 for (i = 0; i < 4; i++) {
2755 reg = FDI_TX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758 temp |= snb_b_fdi_train_param[i];
2759 I915_WRITE(reg, temp);
2764 reg = FDI_RX_IIR(pipe);
2765 temp = I915_READ(reg);
2766 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2768 if (temp & FDI_RX_BIT_LOCK ||
2769 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2770 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2771 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2776 DRM_ERROR("FDI train 1 fail!\n");
2779 reg = FDI_TX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2782 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2783 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2784 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2785 I915_WRITE(reg, temp);
2787 reg = FDI_RX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2790 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2791 I915_WRITE(reg, temp);
2796 for (i = 0; i < 4; i++) {
2797 reg = FDI_TX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2800 temp |= snb_b_fdi_train_param[i];
2801 I915_WRITE(reg, temp);
2806 reg = FDI_RX_IIR(pipe);
2807 temp = I915_READ(reg);
2808 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2810 if (temp & FDI_RX_SYMBOL_LOCK) {
2811 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2812 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2817 DRM_ERROR("FDI train 2 fail!\n");
2819 DRM_DEBUG_KMS("FDI train done.\n");
2822 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2824 struct drm_device *dev = intel_crtc->base.dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 int pipe = intel_crtc->pipe;
2830 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2831 reg = FDI_RX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 temp &= ~((0x7 << 19) | (0x7 << 16));
2834 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2835 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2836 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2841 /* Switch from Rawclk to PCDclk */
2842 temp = I915_READ(reg);
2843 I915_WRITE(reg, temp | FDI_PCDCLK);
2848 /* Enable CPU FDI TX PLL, always on for Ironlake */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2852 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2859 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2861 struct drm_device *dev = intel_crtc->base.dev;
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 int pipe = intel_crtc->pipe;
2866 /* Switch from PCDclk to Rawclk */
2867 reg = FDI_RX_CTL(pipe);
2868 temp = I915_READ(reg);
2869 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2871 /* Disable CPU FDI TX PLL */
2872 reg = FDI_TX_CTL(pipe);
2873 temp = I915_READ(reg);
2874 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2879 reg = FDI_RX_CTL(pipe);
2880 temp = I915_READ(reg);
2881 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2883 /* Wait for the clocks to turn off. */
2888 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2890 struct drm_device *dev = crtc->dev;
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2893 int pipe = intel_crtc->pipe;
2896 /* disable CPU FDI tx and PCH FDI rx */
2897 reg = FDI_TX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2902 reg = FDI_RX_CTL(pipe);
2903 temp = I915_READ(reg);
2904 temp &= ~(0x7 << 16);
2905 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2906 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2911 /* Ironlake workaround, disable clock pointer after downing FDI */
2912 if (HAS_PCH_IBX(dev)) {
2913 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2916 /* still set train pattern 1 */
2917 reg = FDI_TX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 temp &= ~FDI_LINK_TRAIN_NONE;
2920 temp |= FDI_LINK_TRAIN_PATTERN_1;
2921 I915_WRITE(reg, temp);
2923 reg = FDI_RX_CTL(pipe);
2924 temp = I915_READ(reg);
2925 if (HAS_PCH_CPT(dev)) {
2926 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2927 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2929 temp &= ~FDI_LINK_TRAIN_NONE;
2930 temp |= FDI_LINK_TRAIN_PATTERN_1;
2932 /* BPC in FDI rx is consistent with that in PIPECONF */
2933 temp &= ~(0x07 << 16);
2934 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2935 I915_WRITE(reg, temp);
2941 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2943 struct drm_device *dev = crtc->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2946 unsigned long flags;
2949 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2950 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2953 spin_lock_irqsave(&dev->event_lock, flags);
2954 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2955 spin_unlock_irqrestore(&dev->event_lock, flags);
2960 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2962 struct drm_device *dev = crtc->dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2965 if (crtc->fb == NULL)
2968 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2970 wait_event(dev_priv->pending_flip_queue,
2971 !intel_crtc_has_pending_flip(crtc));
2973 mutex_lock(&dev->struct_mutex);
2974 intel_finish_fb(crtc->fb);
2975 mutex_unlock(&dev->struct_mutex);
2978 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2980 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2983 /* Program iCLKIP clock to the desired frequency */
2984 static void lpt_program_iclkip(struct drm_crtc *crtc)
2986 struct drm_device *dev = crtc->dev;
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2991 mutex_lock(&dev_priv->dpio_lock);
2993 /* It is necessary to ungate the pixclk gate prior to programming
2994 * the divisors, and gate it back when it is done.
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2998 /* Disable SSCCTL */
2999 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3000 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3004 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3005 if (crtc->mode.clock == 20000) {
3010 /* The iCLK virtual clock root frequency is in MHz,
3011 * but the crtc->mode.clock in in KHz. To get the divisors,
3012 * it is necessary to divide one by another, so we
3013 * convert the virtual clock precision to KHz here for higher
3016 u32 iclk_virtual_root_freq = 172800 * 1000;
3017 u32 iclk_pi_range = 64;
3018 u32 desired_divisor, msb_divisor_value, pi_value;
3020 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3021 msb_divisor_value = desired_divisor / iclk_pi_range;
3022 pi_value = desired_divisor % iclk_pi_range;
3025 divsel = msb_divisor_value - 2;
3026 phaseinc = pi_value;
3029 /* This should not happen with any sane values */
3030 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3031 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3033 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3035 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3042 /* Program SSCDIVINTPHASE6 */
3043 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3044 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3045 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3046 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3048 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3049 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3050 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3052 /* Program SSCAUXDIV */
3053 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3054 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3055 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3056 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3058 /* Enable modulator and associated divider */
3059 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3060 temp &= ~SBI_SSCCTL_DISABLE;
3061 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3063 /* Wait for initialization time */
3066 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3068 mutex_unlock(&dev_priv->dpio_lock);
3072 * Enable PCH resources required for PCH ports:
3074 * - FDI training & RX/TX
3075 * - update transcoder timings
3076 * - DP transcoding bits
3079 static void ironlake_pch_enable(struct drm_crtc *crtc)
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 int pipe = intel_crtc->pipe;
3087 assert_transcoder_disabled(dev_priv, pipe);
3089 /* Write the TU size bits before fdi link training, so that error
3090 * detection works. */
3091 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3094 /* For PCH output, training FDI link */
3095 dev_priv->display.fdi_link_train(crtc);
3097 /* XXX: pch pll's can be enabled any time before we enable the PCH
3098 * transcoder, and we actually should do this to not upset any PCH
3099 * transcoder that already use the clock when we share it.
3101 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3102 * unconditionally resets the pll - we need that to have the right LVDS
3103 * enable sequence. */
3104 ironlake_enable_pch_pll(intel_crtc);
3106 if (HAS_PCH_CPT(dev)) {
3109 temp = I915_READ(PCH_DPLL_SEL);
3113 temp |= TRANSA_DPLL_ENABLE;
3114 sel = TRANSA_DPLLB_SEL;
3117 temp |= TRANSB_DPLL_ENABLE;
3118 sel = TRANSB_DPLLB_SEL;
3121 temp |= TRANSC_DPLL_ENABLE;
3122 sel = TRANSC_DPLLB_SEL;
3125 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3129 I915_WRITE(PCH_DPLL_SEL, temp);
3132 /* set transcoder timing, panel must allow it */
3133 assert_panel_unlocked(dev_priv, pipe);
3134 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3135 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3136 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3138 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3139 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3140 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3141 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3143 intel_fdi_normal_train(crtc);
3145 /* For PCH DP, enable TRANS_DP_CTL */
3146 if (HAS_PCH_CPT(dev) &&
3147 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3148 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3149 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3150 reg = TRANS_DP_CTL(pipe);
3151 temp = I915_READ(reg);
3152 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3153 TRANS_DP_SYNC_MASK |
3155 temp |= (TRANS_DP_OUTPUT_ENABLE |
3156 TRANS_DP_ENH_FRAMING);
3157 temp |= bpc << 9; /* same format but at 11:9 */
3159 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3160 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3161 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3162 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3164 switch (intel_trans_dp_port_sel(crtc)) {
3166 temp |= TRANS_DP_PORT_SEL_B;
3169 temp |= TRANS_DP_PORT_SEL_C;
3172 temp |= TRANS_DP_PORT_SEL_D;
3178 I915_WRITE(reg, temp);
3181 ironlake_enable_pch_transcoder(dev_priv, pipe);
3184 static void lpt_pch_enable(struct drm_crtc *crtc)
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3191 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3193 lpt_program_iclkip(crtc);
3195 /* Set transcoder timing. */
3196 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3197 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3198 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3200 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3201 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3202 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3203 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3205 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3208 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3210 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3215 if (pll->refcount == 0) {
3216 WARN(1, "bad PCH PLL refcount\n");
3221 intel_crtc->pch_pll = NULL;
3224 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3226 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3227 struct intel_pch_pll *pll;
3230 pll = intel_crtc->pch_pll;
3232 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3233 intel_crtc->base.base.id, pll->pll_reg);
3237 if (HAS_PCH_IBX(dev_priv->dev)) {
3238 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3239 i = intel_crtc->pipe;
3240 pll = &dev_priv->pch_plls[i];
3242 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3243 intel_crtc->base.base.id, pll->pll_reg);
3248 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249 pll = &dev_priv->pch_plls[i];
3251 /* Only want to check enabled timings first */
3252 if (pll->refcount == 0)
3255 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3256 fp == I915_READ(pll->fp0_reg)) {
3257 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3258 intel_crtc->base.base.id,
3259 pll->pll_reg, pll->refcount, pll->active);
3265 /* Ok no matching timings, maybe there's a free one? */
3266 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3267 pll = &dev_priv->pch_plls[i];
3268 if (pll->refcount == 0) {
3269 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3270 intel_crtc->base.base.id, pll->pll_reg);
3278 intel_crtc->pch_pll = pll;
3280 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3281 prepare: /* separate function? */
3282 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3284 /* Wait for the clocks to stabilize before rewriting the regs */
3285 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3286 POSTING_READ(pll->pll_reg);
3289 I915_WRITE(pll->fp0_reg, fp);
3290 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3295 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 int dslreg = PIPEDSL(pipe);
3301 temp = I915_READ(dslreg);
3303 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3304 if (wait_for(I915_READ(dslreg) != temp, 5))
3305 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3309 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3311 struct drm_device *dev = crtc->dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314 struct intel_encoder *encoder;
3315 int pipe = intel_crtc->pipe;
3316 int plane = intel_crtc->plane;
3319 WARN_ON(!crtc->enabled);
3321 if (intel_crtc->active)
3324 intel_crtc->active = true;
3325 intel_update_watermarks(dev);
3327 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3328 temp = I915_READ(PCH_LVDS);
3329 if ((temp & LVDS_PORT_EN) == 0)
3330 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3334 if (intel_crtc->config.has_pch_encoder) {
3335 /* Note: FDI PLL enabling _must_ be done before we enable the
3336 * cpu pipes, hence this is separate from all the other fdi/pch
3338 ironlake_fdi_pll_enable(intel_crtc);
3340 assert_fdi_tx_disabled(dev_priv, pipe);
3341 assert_fdi_rx_disabled(dev_priv, pipe);
3344 for_each_encoder_on_crtc(dev, crtc, encoder)
3345 if (encoder->pre_enable)
3346 encoder->pre_enable(encoder);
3348 /* Enable panel fitting for LVDS */
3349 if (dev_priv->pch_pf_size &&
3350 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3351 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3352 /* Force use of hard-coded filter coefficients
3353 * as some pre-programmed values are broken,
3356 if (IS_IVYBRIDGE(dev))
3357 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3358 PF_PIPE_SEL_IVB(pipe));
3360 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3361 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3362 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3366 * On ILK+ LUT must be loaded before the pipe is running but with
3369 intel_crtc_load_lut(crtc);
3371 intel_enable_pipe(dev_priv, pipe,
3372 intel_crtc->config.has_pch_encoder);
3373 intel_enable_plane(dev_priv, plane, pipe);
3375 if (intel_crtc->config.has_pch_encoder)
3376 ironlake_pch_enable(crtc);
3378 mutex_lock(&dev->struct_mutex);
3379 intel_update_fbc(dev);
3380 mutex_unlock(&dev->struct_mutex);
3382 intel_crtc_update_cursor(crtc, true);
3384 for_each_encoder_on_crtc(dev, crtc, encoder)
3385 encoder->enable(encoder);
3387 if (HAS_PCH_CPT(dev))
3388 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3391 * There seems to be a race in PCH platform hw (at least on some
3392 * outputs) where an enabled pipe still completes any pageflip right
3393 * away (as if the pipe is off) instead of waiting for vblank. As soon
3394 * as the first vblank happend, everything works as expected. Hence just
3395 * wait for one vblank before returning to avoid strange things
3398 intel_wait_for_vblank(dev, intel_crtc->pipe);
3401 static void haswell_crtc_enable(struct drm_crtc *crtc)
3403 struct drm_device *dev = crtc->dev;
3404 struct drm_i915_private *dev_priv = dev->dev_private;
3405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3406 struct intel_encoder *encoder;
3407 int pipe = intel_crtc->pipe;
3408 int plane = intel_crtc->plane;
3410 WARN_ON(!crtc->enabled);
3412 if (intel_crtc->active)
3415 intel_crtc->active = true;
3416 intel_update_watermarks(dev);
3418 if (intel_crtc->config.has_pch_encoder)
3419 dev_priv->display.fdi_link_train(crtc);
3421 for_each_encoder_on_crtc(dev, crtc, encoder)
3422 if (encoder->pre_enable)
3423 encoder->pre_enable(encoder);
3425 intel_ddi_enable_pipe_clock(intel_crtc);
3427 /* Enable panel fitting for eDP */
3428 if (dev_priv->pch_pf_size &&
3429 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3430 /* Force use of hard-coded filter coefficients
3431 * as some pre-programmed values are broken,
3434 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3435 PF_PIPE_SEL_IVB(pipe));
3436 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3437 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3441 * On ILK+ LUT must be loaded before the pipe is running but with
3444 intel_crtc_load_lut(crtc);
3446 intel_ddi_set_pipe_settings(crtc);
3447 intel_ddi_enable_transcoder_func(crtc);
3449 intel_enable_pipe(dev_priv, pipe,
3450 intel_crtc->config.has_pch_encoder);
3451 intel_enable_plane(dev_priv, plane, pipe);
3453 if (intel_crtc->config.has_pch_encoder)
3454 lpt_pch_enable(crtc);
3456 mutex_lock(&dev->struct_mutex);
3457 intel_update_fbc(dev);
3458 mutex_unlock(&dev->struct_mutex);
3460 intel_crtc_update_cursor(crtc, true);
3462 for_each_encoder_on_crtc(dev, crtc, encoder)
3463 encoder->enable(encoder);
3466 * There seems to be a race in PCH platform hw (at least on some
3467 * outputs) where an enabled pipe still completes any pageflip right
3468 * away (as if the pipe is off) instead of waiting for vblank. As soon
3469 * as the first vblank happend, everything works as expected. Hence just
3470 * wait for one vblank before returning to avoid strange things
3473 intel_wait_for_vblank(dev, intel_crtc->pipe);
3476 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3478 struct drm_device *dev = crtc->dev;
3479 struct drm_i915_private *dev_priv = dev->dev_private;
3480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3481 struct intel_encoder *encoder;
3482 int pipe = intel_crtc->pipe;
3483 int plane = intel_crtc->plane;
3487 if (!intel_crtc->active)
3490 for_each_encoder_on_crtc(dev, crtc, encoder)
3491 encoder->disable(encoder);
3493 intel_crtc_wait_for_pending_flips(crtc);
3494 drm_vblank_off(dev, pipe);
3495 intel_crtc_update_cursor(crtc, false);
3497 intel_disable_plane(dev_priv, plane, pipe);
3499 if (dev_priv->cfb_plane == plane)
3500 intel_disable_fbc(dev);
3502 intel_disable_pipe(dev_priv, pipe);
3505 I915_WRITE(PF_CTL(pipe), 0);
3506 I915_WRITE(PF_WIN_SZ(pipe), 0);
3508 for_each_encoder_on_crtc(dev, crtc, encoder)
3509 if (encoder->post_disable)
3510 encoder->post_disable(encoder);
3512 ironlake_fdi_disable(crtc);
3514 ironlake_disable_pch_transcoder(dev_priv, pipe);
3516 if (HAS_PCH_CPT(dev)) {
3517 /* disable TRANS_DP_CTL */
3518 reg = TRANS_DP_CTL(pipe);
3519 temp = I915_READ(reg);
3520 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3521 temp |= TRANS_DP_PORT_SEL_NONE;
3522 I915_WRITE(reg, temp);
3524 /* disable DPLL_SEL */
3525 temp = I915_READ(PCH_DPLL_SEL);
3528 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3531 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3534 /* C shares PLL A or B */
3535 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3540 I915_WRITE(PCH_DPLL_SEL, temp);
3543 /* disable PCH DPLL */
3544 intel_disable_pch_pll(intel_crtc);
3546 ironlake_fdi_pll_disable(intel_crtc);
3548 intel_crtc->active = false;
3549 intel_update_watermarks(dev);
3551 mutex_lock(&dev->struct_mutex);
3552 intel_update_fbc(dev);
3553 mutex_unlock(&dev->struct_mutex);
3556 static void haswell_crtc_disable(struct drm_crtc *crtc)
3558 struct drm_device *dev = crtc->dev;
3559 struct drm_i915_private *dev_priv = dev->dev_private;
3560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3561 struct intel_encoder *encoder;
3562 int pipe = intel_crtc->pipe;
3563 int plane = intel_crtc->plane;
3564 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3567 if (!intel_crtc->active)
3570 is_pch_port = haswell_crtc_driving_pch(crtc);
3572 for_each_encoder_on_crtc(dev, crtc, encoder)
3573 encoder->disable(encoder);
3575 intel_crtc_wait_for_pending_flips(crtc);
3576 drm_vblank_off(dev, pipe);
3577 intel_crtc_update_cursor(crtc, false);
3579 intel_disable_plane(dev_priv, plane, pipe);
3581 if (dev_priv->cfb_plane == plane)
3582 intel_disable_fbc(dev);
3584 intel_disable_pipe(dev_priv, pipe);
3586 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3589 I915_WRITE(PF_CTL(pipe), 0);
3590 I915_WRITE(PF_WIN_SZ(pipe), 0);
3592 intel_ddi_disable_pipe_clock(intel_crtc);
3594 for_each_encoder_on_crtc(dev, crtc, encoder)
3595 if (encoder->post_disable)
3596 encoder->post_disable(encoder);
3599 lpt_disable_pch_transcoder(dev_priv);
3600 intel_ddi_fdi_disable(crtc);
3603 intel_crtc->active = false;
3604 intel_update_watermarks(dev);
3606 mutex_lock(&dev->struct_mutex);
3607 intel_update_fbc(dev);
3608 mutex_unlock(&dev->struct_mutex);
3611 static void ironlake_crtc_off(struct drm_crtc *crtc)
3613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614 intel_put_pch_pll(intel_crtc);
3617 static void haswell_crtc_off(struct drm_crtc *crtc)
3619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3622 * start using it. */
3623 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3625 intel_ddi_put_crtc_pll(crtc);
3628 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3630 if (!enable && intel_crtc->overlay) {
3631 struct drm_device *dev = intel_crtc->base.dev;
3632 struct drm_i915_private *dev_priv = dev->dev_private;
3634 mutex_lock(&dev->struct_mutex);
3635 dev_priv->mm.interruptible = false;
3636 (void) intel_overlay_switch_off(intel_crtc->overlay);
3637 dev_priv->mm.interruptible = true;
3638 mutex_unlock(&dev->struct_mutex);
3641 /* Let userspace switch the overlay on again. In most cases userspace
3642 * has to recompute where to put it anyway.
3647 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3648 * cursor plane briefly if not already running after enabling the display
3650 * This workaround avoids occasional blank screens when self refresh is
3654 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3656 u32 cntl = I915_READ(CURCNTR(pipe));
3658 if ((cntl & CURSOR_MODE) == 0) {
3659 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3661 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3662 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3663 intel_wait_for_vblank(dev_priv->dev, pipe);
3664 I915_WRITE(CURCNTR(pipe), cntl);
3665 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3666 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3670 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3672 struct drm_device *dev = crtc->dev;
3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3675 struct intel_encoder *encoder;
3676 int pipe = intel_crtc->pipe;
3677 int plane = intel_crtc->plane;
3679 WARN_ON(!crtc->enabled);
3681 if (intel_crtc->active)
3684 intel_crtc->active = true;
3685 intel_update_watermarks(dev);
3687 intel_enable_pll(dev_priv, pipe);
3689 for_each_encoder_on_crtc(dev, crtc, encoder)
3690 if (encoder->pre_enable)
3691 encoder->pre_enable(encoder);
3693 intel_enable_pipe(dev_priv, pipe, false);
3694 intel_enable_plane(dev_priv, plane, pipe);
3696 g4x_fixup_plane(dev_priv, pipe);
3698 intel_crtc_load_lut(crtc);
3699 intel_update_fbc(dev);
3701 /* Give the overlay scaler a chance to enable if it's on this pipe */
3702 intel_crtc_dpms_overlay(intel_crtc, true);
3703 intel_crtc_update_cursor(crtc, true);
3705 for_each_encoder_on_crtc(dev, crtc, encoder)
3706 encoder->enable(encoder);
3709 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3714 struct intel_encoder *encoder;
3715 int pipe = intel_crtc->pipe;
3716 int plane = intel_crtc->plane;
3720 if (!intel_crtc->active)
3723 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->disable(encoder);
3726 /* Give the overlay scaler a chance to disable if it's on this pipe */
3727 intel_crtc_wait_for_pending_flips(crtc);
3728 drm_vblank_off(dev, pipe);
3729 intel_crtc_dpms_overlay(intel_crtc, false);
3730 intel_crtc_update_cursor(crtc, false);
3732 if (dev_priv->cfb_plane == plane)
3733 intel_disable_fbc(dev);
3735 intel_disable_plane(dev_priv, plane, pipe);
3736 intel_disable_pipe(dev_priv, pipe);
3738 /* Disable pannel fitter if it is on this pipe. */
3739 pctl = I915_READ(PFIT_CONTROL);
3740 if ((pctl & PFIT_ENABLE) &&
3741 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3742 I915_WRITE(PFIT_CONTROL, 0);
3744 intel_disable_pll(dev_priv, pipe);
3746 intel_crtc->active = false;
3747 intel_update_fbc(dev);
3748 intel_update_watermarks(dev);
3751 static void i9xx_crtc_off(struct drm_crtc *crtc)
3755 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3758 struct drm_device *dev = crtc->dev;
3759 struct drm_i915_master_private *master_priv;
3760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3761 int pipe = intel_crtc->pipe;
3763 if (!dev->primary->master)
3766 master_priv = dev->primary->master->driver_priv;
3767 if (!master_priv->sarea_priv)
3772 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3773 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3776 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3777 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3780 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3786 * Sets the power management mode of the pipe and plane.
3788 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct intel_encoder *intel_encoder;
3793 bool enable = false;
3795 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3796 enable |= intel_encoder->connectors_active;
3799 dev_priv->display.crtc_enable(crtc);
3801 dev_priv->display.crtc_disable(crtc);
3803 intel_crtc_update_sarea(crtc, enable);
3806 static void intel_crtc_disable(struct drm_crtc *crtc)
3808 struct drm_device *dev = crtc->dev;
3809 struct drm_connector *connector;
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 /* crtc should still be enabled when we disable it. */
3814 WARN_ON(!crtc->enabled);
3816 intel_crtc->eld_vld = false;
3817 dev_priv->display.crtc_disable(crtc);
3818 intel_crtc_update_sarea(crtc, false);
3819 dev_priv->display.off(crtc);
3821 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3822 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3825 mutex_lock(&dev->struct_mutex);
3826 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3827 mutex_unlock(&dev->struct_mutex);
3831 /* Update computed state. */
3832 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3833 if (!connector->encoder || !connector->encoder->crtc)
3836 if (connector->encoder->crtc != crtc)
3839 connector->dpms = DRM_MODE_DPMS_OFF;
3840 to_intel_encoder(connector->encoder)->connectors_active = false;
3844 void intel_modeset_disable(struct drm_device *dev)
3846 struct drm_crtc *crtc;
3848 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3850 intel_crtc_disable(crtc);
3854 void intel_encoder_destroy(struct drm_encoder *encoder)
3856 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3858 drm_encoder_cleanup(encoder);
3859 kfree(intel_encoder);
3862 /* Simple dpms helper for encodres with just one connector, no cloning and only
3863 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864 * state of the entire output pipe. */
3865 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3867 if (mode == DRM_MODE_DPMS_ON) {
3868 encoder->connectors_active = true;
3870 intel_crtc_update_dpms(encoder->base.crtc);
3872 encoder->connectors_active = false;
3874 intel_crtc_update_dpms(encoder->base.crtc);
3878 /* Cross check the actual hw state with our own modeset state tracking (and it's
3879 * internal consistency). */
3880 static void intel_connector_check_state(struct intel_connector *connector)
3882 if (connector->get_hw_state(connector)) {
3883 struct intel_encoder *encoder = connector->encoder;
3884 struct drm_crtc *crtc;
3885 bool encoder_enabled;
3888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889 connector->base.base.id,
3890 drm_get_connector_name(&connector->base));
3892 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893 "wrong connector dpms state\n");
3894 WARN(connector->base.encoder != &encoder->base,
3895 "active connector not linked to encoder\n");
3896 WARN(!encoder->connectors_active,
3897 "encoder->connectors_active not set\n");
3899 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900 WARN(!encoder_enabled, "encoder not enabled\n");
3901 if (WARN_ON(!encoder->base.crtc))
3904 crtc = encoder->base.crtc;
3906 WARN(!crtc->enabled, "crtc not enabled\n");
3907 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909 "encoder active on the wrong pipe\n");
3913 /* Even simpler default implementation, if there's really no special case to
3915 void intel_connector_dpms(struct drm_connector *connector, int mode)
3917 struct intel_encoder *encoder = intel_attached_encoder(connector);
3919 /* All the simple cases only support two dpms states. */
3920 if (mode != DRM_MODE_DPMS_ON)
3921 mode = DRM_MODE_DPMS_OFF;
3923 if (mode == connector->dpms)
3926 connector->dpms = mode;
3928 /* Only need to change hw state when actually enabled */
3929 if (encoder->base.crtc)
3930 intel_encoder_dpms(encoder, mode);
3932 WARN_ON(encoder->connectors_active != false);
3934 intel_modeset_check_state(connector->dev);
3937 /* Simple connector->get_hw_state implementation for encoders that support only
3938 * one connector and no cloning and hence the encoder state determines the state
3939 * of the connector. */
3940 bool intel_connector_get_hw_state(struct intel_connector *connector)
3943 struct intel_encoder *encoder = connector->encoder;
3945 return encoder->get_hw_state(encoder, &pipe);
3948 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3949 struct intel_crtc_config *pipe_config)
3951 struct drm_device *dev = crtc->dev;
3952 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3954 if (HAS_PCH_SPLIT(dev)) {
3955 /* FDI link clock is fixed at 2.7G */
3956 if (pipe_config->requested_mode.clock * 3
3957 > IRONLAKE_FDI_FREQ * 4)
3961 /* All interlaced capable intel hw wants timings in frames. Note though
3962 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3963 * timings, so we need to be careful not to clobber these.*/
3964 if (!pipe_config->timings_set)
3965 drm_mode_set_crtcinfo(adjusted_mode, 0);
3967 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3968 * with a hsync front porch of 0.
3970 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3971 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3974 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3975 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3976 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3977 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3979 pipe_config->pipe_bpp = 8*3;
3985 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3987 return 400000; /* FIXME */
3990 static int i945_get_display_clock_speed(struct drm_device *dev)
3995 static int i915_get_display_clock_speed(struct drm_device *dev)
4000 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4005 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4009 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4011 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4014 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4015 case GC_DISPLAY_CLOCK_333_MHZ:
4018 case GC_DISPLAY_CLOCK_190_200_MHZ:
4024 static int i865_get_display_clock_speed(struct drm_device *dev)
4029 static int i855_get_display_clock_speed(struct drm_device *dev)
4032 /* Assume that the hardware is in the high speed state. This
4033 * should be the default.
4035 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4036 case GC_CLOCK_133_200:
4037 case GC_CLOCK_100_200:
4039 case GC_CLOCK_166_250:
4041 case GC_CLOCK_100_133:
4045 /* Shouldn't happen */
4049 static int i830_get_display_clock_speed(struct drm_device *dev)
4055 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4057 while (*num > 0xffffff || *den > 0xffffff) {
4064 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4065 int pixel_clock, int link_clock,
4066 struct intel_link_m_n *m_n)
4069 m_n->gmch_m = bits_per_pixel * pixel_clock;
4070 m_n->gmch_n = link_clock * nlanes * 8;
4071 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4072 m_n->link_m = pixel_clock;
4073 m_n->link_n = link_clock;
4074 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4077 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4079 if (i915_panel_use_ssc >= 0)
4080 return i915_panel_use_ssc != 0;
4081 return dev_priv->lvds_use_ssc
4082 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4085 static int vlv_get_refclk(struct drm_crtc *crtc)
4087 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 int refclk = 27000; /* for DP & HDMI */
4091 return 100000; /* only one validated so far */
4093 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4095 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4096 if (intel_panel_use_ssc(dev_priv))
4100 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4107 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4109 struct drm_device *dev = crtc->dev;
4110 struct drm_i915_private *dev_priv = dev->dev_private;
4113 if (IS_VALLEYVIEW(dev)) {
4114 refclk = vlv_get_refclk(crtc);
4115 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4116 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4117 refclk = dev_priv->lvds_ssc_freq * 1000;
4118 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4120 } else if (!IS_GEN2(dev)) {
4129 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4130 intel_clock_t *clock)
4132 /* SDVO TV has fixed PLL values depend on its clock range,
4133 this mirrors vbios setting. */
4134 if (adjusted_mode->clock >= 100000
4135 && adjusted_mode->clock < 140500) {
4141 } else if (adjusted_mode->clock >= 140500
4142 && adjusted_mode->clock <= 200000) {
4151 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4152 intel_clock_t *clock,
4153 intel_clock_t *reduced_clock)
4155 struct drm_device *dev = crtc->dev;
4156 struct drm_i915_private *dev_priv = dev->dev_private;
4157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4158 int pipe = intel_crtc->pipe;
4161 if (IS_PINEVIEW(dev)) {
4162 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4164 fp2 = (1 << reduced_clock->n) << 16 |
4165 reduced_clock->m1 << 8 | reduced_clock->m2;
4167 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4169 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4173 I915_WRITE(FP0(pipe), fp);
4175 intel_crtc->lowfreq_avail = false;
4176 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4177 reduced_clock && i915_powersave) {
4178 I915_WRITE(FP1(pipe), fp2);
4179 intel_crtc->lowfreq_avail = true;
4181 I915_WRITE(FP1(pipe), fp);
4185 static void vlv_update_pll(struct drm_crtc *crtc,
4186 intel_clock_t *clock, intel_clock_t *reduced_clock,
4189 struct drm_device *dev = crtc->dev;
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192 struct drm_display_mode *adjusted_mode =
4193 &intel_crtc->config.adjusted_mode;
4194 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4195 int pipe = intel_crtc->pipe;
4196 u32 dpll, mdiv, pdiv;
4197 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4201 mutex_lock(&dev_priv->dpio_lock);
4203 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4204 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4206 dpll = DPLL_VGA_MODE_DIS;
4207 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4208 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4209 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4211 I915_WRITE(DPLL(pipe), dpll);
4212 POSTING_READ(DPLL(pipe));
4221 * In Valleyview PLL and program lane counter registers are exposed
4222 * through DPIO interface
4224 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4225 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4226 mdiv |= ((bestn << DPIO_N_SHIFT));
4227 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4228 mdiv |= (1 << DPIO_K_SHIFT);
4229 mdiv |= DPIO_ENABLE_CALIBRATION;
4230 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4232 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4234 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4235 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4236 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4237 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4238 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4240 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4242 dpll |= DPLL_VCO_ENABLE;
4243 I915_WRITE(DPLL(pipe), dpll);
4244 POSTING_READ(DPLL(pipe));
4245 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4246 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4248 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4250 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4251 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4253 I915_WRITE(DPLL(pipe), dpll);
4255 /* Wait for the clocks to stabilize. */
4256 POSTING_READ(DPLL(pipe));
4262 if (intel_crtc->config.pixel_multiplier > 1) {
4263 temp = (intel_crtc->config.pixel_multiplier - 1)
4264 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4267 I915_WRITE(DPLL_MD(pipe), temp);
4268 POSTING_READ(DPLL_MD(pipe));
4270 /* Now program lane control registers */
4271 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4272 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4277 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4279 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4284 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4287 mutex_unlock(&dev_priv->dpio_lock);
4290 static void i9xx_update_pll(struct drm_crtc *crtc,
4291 intel_clock_t *clock, intel_clock_t *reduced_clock,
4294 struct drm_device *dev = crtc->dev;
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4297 struct drm_display_mode *adjusted_mode =
4298 &intel_crtc->config.adjusted_mode;
4299 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4300 struct intel_encoder *encoder;
4301 int pipe = intel_crtc->pipe;
4305 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4307 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4308 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4310 dpll = DPLL_VGA_MODE_DIS;
4312 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4313 dpll |= DPLLB_MODE_LVDS;
4315 dpll |= DPLLB_MODE_DAC_SERIAL;
4318 if ((intel_crtc->config.pixel_multiplier > 1) &&
4319 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4320 dpll |= (intel_crtc->config.pixel_multiplier - 1)
4321 << SDVO_MULTIPLIER_SHIFT_HIRES;
4323 dpll |= DPLL_DVO_HIGH_SPEED;
4325 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4326 dpll |= DPLL_DVO_HIGH_SPEED;
4328 /* compute bitmask from p1 value */
4329 if (IS_PINEVIEW(dev))
4330 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4332 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4333 if (IS_G4X(dev) && reduced_clock)
4334 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4336 switch (clock->p2) {
4338 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4341 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4344 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4347 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4350 if (INTEL_INFO(dev)->gen >= 4)
4351 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4353 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4354 dpll |= PLL_REF_INPUT_TVCLKINBC;
4355 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4356 /* XXX: just matching BIOS for now */
4357 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4359 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4360 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4361 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4363 dpll |= PLL_REF_INPUT_DREFCLK;
4365 dpll |= DPLL_VCO_ENABLE;
4366 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4367 POSTING_READ(DPLL(pipe));
4370 for_each_encoder_on_crtc(dev, crtc, encoder)
4371 if (encoder->pre_pll_enable)
4372 encoder->pre_pll_enable(encoder);
4374 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4375 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4377 I915_WRITE(DPLL(pipe), dpll);
4379 /* Wait for the clocks to stabilize. */
4380 POSTING_READ(DPLL(pipe));
4383 if (INTEL_INFO(dev)->gen >= 4) {
4387 if (intel_crtc->config.pixel_multiplier > 1) {
4388 temp = (intel_crtc->config.pixel_multiplier - 1)
4389 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4392 I915_WRITE(DPLL_MD(pipe), temp);
4394 /* The pixel multiplier can only be updated once the
4395 * DPLL is enabled and the clocks are stable.
4397 * So write it again.
4399 I915_WRITE(DPLL(pipe), dpll);
4403 static void i8xx_update_pll(struct drm_crtc *crtc,
4404 struct drm_display_mode *adjusted_mode,
4405 intel_clock_t *clock, intel_clock_t *reduced_clock,
4408 struct drm_device *dev = crtc->dev;
4409 struct drm_i915_private *dev_priv = dev->dev_private;
4410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4411 struct intel_encoder *encoder;
4412 int pipe = intel_crtc->pipe;
4415 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4417 dpll = DPLL_VGA_MODE_DIS;
4419 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4420 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4423 dpll |= PLL_P1_DIVIDE_BY_TWO;
4425 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4427 dpll |= PLL_P2_DIVIDE_BY_4;
4430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4431 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4432 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4434 dpll |= PLL_REF_INPUT_DREFCLK;
4436 dpll |= DPLL_VCO_ENABLE;
4437 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4438 POSTING_READ(DPLL(pipe));
4441 for_each_encoder_on_crtc(dev, crtc, encoder)
4442 if (encoder->pre_pll_enable)
4443 encoder->pre_pll_enable(encoder);
4445 I915_WRITE(DPLL(pipe), dpll);
4447 /* Wait for the clocks to stabilize. */
4448 POSTING_READ(DPLL(pipe));
4451 /* The pixel multiplier can only be updated once the
4452 * DPLL is enabled and the clocks are stable.
4454 * So write it again.
4456 I915_WRITE(DPLL(pipe), dpll);
4459 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4460 struct drm_display_mode *mode,
4461 struct drm_display_mode *adjusted_mode)
4463 struct drm_device *dev = intel_crtc->base.dev;
4464 struct drm_i915_private *dev_priv = dev->dev_private;
4465 enum pipe pipe = intel_crtc->pipe;
4466 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4467 uint32_t vsyncshift;
4469 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4470 /* the chip adds 2 halflines automatically */
4471 adjusted_mode->crtc_vtotal -= 1;
4472 adjusted_mode->crtc_vblank_end -= 1;
4473 vsyncshift = adjusted_mode->crtc_hsync_start
4474 - adjusted_mode->crtc_htotal / 2;
4479 if (INTEL_INFO(dev)->gen > 3)
4480 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4482 I915_WRITE(HTOTAL(cpu_transcoder),
4483 (adjusted_mode->crtc_hdisplay - 1) |
4484 ((adjusted_mode->crtc_htotal - 1) << 16));
4485 I915_WRITE(HBLANK(cpu_transcoder),
4486 (adjusted_mode->crtc_hblank_start - 1) |
4487 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4488 I915_WRITE(HSYNC(cpu_transcoder),
4489 (adjusted_mode->crtc_hsync_start - 1) |
4490 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4492 I915_WRITE(VTOTAL(cpu_transcoder),
4493 (adjusted_mode->crtc_vdisplay - 1) |
4494 ((adjusted_mode->crtc_vtotal - 1) << 16));
4495 I915_WRITE(VBLANK(cpu_transcoder),
4496 (adjusted_mode->crtc_vblank_start - 1) |
4497 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4498 I915_WRITE(VSYNC(cpu_transcoder),
4499 (adjusted_mode->crtc_vsync_start - 1) |
4500 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4502 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4503 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4504 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4506 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4507 (pipe == PIPE_B || pipe == PIPE_C))
4508 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4510 /* pipesrc controls the size that is scaled from, which should
4511 * always be the user's requested size.
4513 I915_WRITE(PIPESRC(pipe),
4514 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4517 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4519 struct drm_framebuffer *fb)
4521 struct drm_device *dev = crtc->dev;
4522 struct drm_i915_private *dev_priv = dev->dev_private;
4523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4524 struct drm_display_mode *adjusted_mode =
4525 &intel_crtc->config.adjusted_mode;
4526 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4527 int pipe = intel_crtc->pipe;
4528 int plane = intel_crtc->plane;
4529 int refclk, num_connectors = 0;
4530 intel_clock_t clock, reduced_clock;
4531 u32 dspcntr, pipeconf;
4532 bool ok, has_reduced_clock = false, is_sdvo = false;
4533 bool is_lvds = false, is_tv = false, is_dp = false;
4534 struct intel_encoder *encoder;
4535 const intel_limit_t *limit;
4538 for_each_encoder_on_crtc(dev, crtc, encoder) {
4539 switch (encoder->type) {
4540 case INTEL_OUTPUT_LVDS:
4543 case INTEL_OUTPUT_SDVO:
4544 case INTEL_OUTPUT_HDMI:
4546 if (encoder->needs_tv_clock)
4549 case INTEL_OUTPUT_TVOUT:
4552 case INTEL_OUTPUT_DISPLAYPORT:
4560 refclk = i9xx_get_refclk(crtc, num_connectors);
4563 * Returns a set of divisors for the desired target clock with the given
4564 * refclk, or FALSE. The returned values represent the clock equation:
4565 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4567 limit = intel_limit(crtc, refclk);
4568 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4571 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4575 /* Ensure that the cursor is valid for the new mode before changing... */
4576 intel_crtc_update_cursor(crtc, true);
4578 if (is_lvds && dev_priv->lvds_downclock_avail) {
4580 * Ensure we match the reduced clock's P to the target clock.
4581 * If the clocks don't match, we can't switch the display clock
4582 * by using the FP0/FP1. In such case we will disable the LVDS
4583 * downclock feature.
4585 has_reduced_clock = limit->find_pll(limit, crtc,
4586 dev_priv->lvds_downclock,
4592 if (is_sdvo && is_tv)
4593 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4596 i8xx_update_pll(crtc, adjusted_mode, &clock,
4597 has_reduced_clock ? &reduced_clock : NULL,
4599 else if (IS_VALLEYVIEW(dev))
4600 vlv_update_pll(crtc, &clock,
4601 has_reduced_clock ? &reduced_clock : NULL,
4604 i9xx_update_pll(crtc, &clock,
4605 has_reduced_clock ? &reduced_clock : NULL,
4608 /* setup pipeconf */
4609 pipeconf = I915_READ(PIPECONF(pipe));
4611 /* Set up the display plane register */
4612 dspcntr = DISPPLANE_GAMMA_ENABLE;
4614 if (!IS_VALLEYVIEW(dev)) {
4616 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4618 dspcntr |= DISPPLANE_SEL_PIPE_B;
4621 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4622 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4625 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4629 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4630 pipeconf |= PIPECONF_DOUBLE_WIDE;
4632 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4635 /* default to 8bpc */
4636 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4638 if (intel_crtc->config.dither) {
4639 pipeconf |= PIPECONF_6BPC |
4640 PIPECONF_DITHER_EN |
4641 PIPECONF_DITHER_TYPE_SP;
4645 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4646 if (intel_crtc->config.dither) {
4647 pipeconf |= PIPECONF_6BPC |
4649 I965_PIPECONF_ACTIVE;
4653 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4654 drm_mode_debug_printmodeline(mode);
4656 if (HAS_PIPE_CXSR(dev)) {
4657 if (intel_crtc->lowfreq_avail) {
4658 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4659 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4661 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4662 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4666 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4667 if (!IS_GEN2(dev) &&
4668 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4669 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4671 pipeconf |= PIPECONF_PROGRESSIVE;
4673 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4675 /* pipesrc and dspsize control the size that is scaled from,
4676 * which should always be the user's requested size.
4678 I915_WRITE(DSPSIZE(plane),
4679 ((mode->vdisplay - 1) << 16) |
4680 (mode->hdisplay - 1));
4681 I915_WRITE(DSPPOS(plane), 0);
4683 I915_WRITE(PIPECONF(pipe), pipeconf);
4684 POSTING_READ(PIPECONF(pipe));
4685 intel_enable_pipe(dev_priv, pipe, false);
4687 intel_wait_for_vblank(dev, pipe);
4689 I915_WRITE(DSPCNTR(plane), dspcntr);
4690 POSTING_READ(DSPCNTR(plane));
4692 ret = intel_pipe_set_base(crtc, x, y, fb);
4694 intel_update_watermarks(dev);
4699 static void ironlake_init_pch_refclk(struct drm_device *dev)
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 struct drm_mode_config *mode_config = &dev->mode_config;
4703 struct intel_encoder *encoder;
4705 bool has_lvds = false;
4706 bool has_cpu_edp = false;
4707 bool has_pch_edp = false;
4708 bool has_panel = false;
4709 bool has_ck505 = false;
4710 bool can_ssc = false;
4712 /* We need to take the global config into account */
4713 list_for_each_entry(encoder, &mode_config->encoder_list,
4715 switch (encoder->type) {
4716 case INTEL_OUTPUT_LVDS:
4720 case INTEL_OUTPUT_EDP:
4722 if (intel_encoder_is_pch_edp(&encoder->base))
4730 if (HAS_PCH_IBX(dev)) {
4731 has_ck505 = dev_priv->display_clock_mode;
4732 can_ssc = has_ck505;
4738 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4739 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4742 /* Ironlake: try to setup display ref clock before DPLL
4743 * enabling. This is only under driver's control after
4744 * PCH B stepping, previous chipset stepping should be
4745 * ignoring this setting.
4747 val = I915_READ(PCH_DREF_CONTROL);
4749 /* As we must carefully and slowly disable/enable each source in turn,
4750 * compute the final state we want first and check if we need to
4751 * make any changes at all.
4754 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4756 final |= DREF_NONSPREAD_CK505_ENABLE;
4758 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4760 final &= ~DREF_SSC_SOURCE_MASK;
4761 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4762 final &= ~DREF_SSC1_ENABLE;
4765 final |= DREF_SSC_SOURCE_ENABLE;
4767 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4768 final |= DREF_SSC1_ENABLE;
4771 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4772 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4774 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4776 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4778 final |= DREF_SSC_SOURCE_DISABLE;
4779 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4785 /* Always enable nonspread source */
4786 val &= ~DREF_NONSPREAD_SOURCE_MASK;
4789 val |= DREF_NONSPREAD_CK505_ENABLE;
4791 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4794 val &= ~DREF_SSC_SOURCE_MASK;
4795 val |= DREF_SSC_SOURCE_ENABLE;
4797 /* SSC must be turned on before enabling the CPU output */
4798 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4799 DRM_DEBUG_KMS("Using SSC on panel\n");
4800 val |= DREF_SSC1_ENABLE;
4802 val &= ~DREF_SSC1_ENABLE;
4804 /* Get SSC going before enabling the outputs */
4805 I915_WRITE(PCH_DREF_CONTROL, val);
4806 POSTING_READ(PCH_DREF_CONTROL);
4809 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4811 /* Enable CPU source on CPU attached eDP */
4813 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4814 DRM_DEBUG_KMS("Using SSC on eDP\n");
4815 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4818 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4820 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4822 I915_WRITE(PCH_DREF_CONTROL, val);
4823 POSTING_READ(PCH_DREF_CONTROL);
4826 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4828 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4830 /* Turn off CPU output */
4831 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4833 I915_WRITE(PCH_DREF_CONTROL, val);
4834 POSTING_READ(PCH_DREF_CONTROL);
4837 /* Turn off the SSC source */
4838 val &= ~DREF_SSC_SOURCE_MASK;
4839 val |= DREF_SSC_SOURCE_DISABLE;
4842 val &= ~DREF_SSC1_ENABLE;
4844 I915_WRITE(PCH_DREF_CONTROL, val);
4845 POSTING_READ(PCH_DREF_CONTROL);
4849 BUG_ON(val != final);
4852 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4853 static void lpt_init_pch_refclk(struct drm_device *dev)
4855 struct drm_i915_private *dev_priv = dev->dev_private;
4856 struct drm_mode_config *mode_config = &dev->mode_config;
4857 struct intel_encoder *encoder;
4858 bool has_vga = false;
4859 bool is_sdv = false;
4862 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4863 switch (encoder->type) {
4864 case INTEL_OUTPUT_ANALOG:
4873 mutex_lock(&dev_priv->dpio_lock);
4875 /* XXX: Rip out SDV support once Haswell ships for real. */
4876 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4879 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4880 tmp &= ~SBI_SSCCTL_DISABLE;
4881 tmp |= SBI_SSCCTL_PATHALT;
4882 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4886 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4887 tmp &= ~SBI_SSCCTL_PATHALT;
4888 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4891 tmp = I915_READ(SOUTH_CHICKEN2);
4892 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4893 I915_WRITE(SOUTH_CHICKEN2, tmp);
4895 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4896 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4897 DRM_ERROR("FDI mPHY reset assert timeout\n");
4899 tmp = I915_READ(SOUTH_CHICKEN2);
4900 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4901 I915_WRITE(SOUTH_CHICKEN2, tmp);
4903 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4904 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4906 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4909 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4910 tmp &= ~(0xFF << 24);
4911 tmp |= (0x12 << 24);
4912 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4915 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4917 tmp |= (1 << 6) | (1 << 0);
4918 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4922 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4924 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4927 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4929 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4931 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4933 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4936 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4937 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4938 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4940 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4941 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4942 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4944 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4946 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4948 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4950 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4953 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4954 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4955 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4957 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4958 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4959 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4962 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4965 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4967 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4970 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4973 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4976 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4978 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4981 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4983 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4984 tmp &= ~(0xFF << 16);
4985 tmp |= (0x1C << 16);
4986 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
4988 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
4989 tmp &= ~(0xFF << 16);
4990 tmp |= (0x1C << 16);
4991 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
4994 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
4996 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
4998 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5000 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5002 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5003 tmp &= ~(0xF << 28);
5005 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5007 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5008 tmp &= ~(0xF << 28);
5010 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5013 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5014 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5015 tmp |= SBI_DBUFF0_ENABLE;
5016 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5018 mutex_unlock(&dev_priv->dpio_lock);
5022 * Initialize reference clocks when the driver loads
5024 void intel_init_pch_refclk(struct drm_device *dev)
5026 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5027 ironlake_init_pch_refclk(dev);
5028 else if (HAS_PCH_LPT(dev))
5029 lpt_init_pch_refclk(dev);
5032 static int ironlake_get_refclk(struct drm_crtc *crtc)
5034 struct drm_device *dev = crtc->dev;
5035 struct drm_i915_private *dev_priv = dev->dev_private;
5036 struct intel_encoder *encoder;
5037 struct intel_encoder *edp_encoder = NULL;
5038 int num_connectors = 0;
5039 bool is_lvds = false;
5041 for_each_encoder_on_crtc(dev, crtc, encoder) {
5042 switch (encoder->type) {
5043 case INTEL_OUTPUT_LVDS:
5046 case INTEL_OUTPUT_EDP:
5047 edp_encoder = encoder;
5053 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5054 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5055 dev_priv->lvds_ssc_freq);
5056 return dev_priv->lvds_ssc_freq * 1000;
5062 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5063 struct drm_display_mode *adjusted_mode,
5066 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5068 int pipe = intel_crtc->pipe;
5071 val = I915_READ(PIPECONF(pipe));
5073 val &= ~PIPECONF_BPC_MASK;
5074 switch (intel_crtc->config.pipe_bpp) {
5076 val |= PIPECONF_6BPC;
5079 val |= PIPECONF_8BPC;
5082 val |= PIPECONF_10BPC;
5085 val |= PIPECONF_12BPC;
5088 /* Case prevented by intel_choose_pipe_bpp_dither. */
5092 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5094 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5096 val &= ~PIPECONF_INTERLACE_MASK;
5097 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5098 val |= PIPECONF_INTERLACED_ILK;
5100 val |= PIPECONF_PROGRESSIVE;
5102 if (intel_crtc->config.limited_color_range)
5103 val |= PIPECONF_COLOR_RANGE_SELECT;
5105 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5107 I915_WRITE(PIPECONF(pipe), val);
5108 POSTING_READ(PIPECONF(pipe));
5112 * Set up the pipe CSC unit.
5114 * Currently only full range RGB to limited range RGB conversion
5115 * is supported, but eventually this should handle various
5116 * RGB<->YCbCr scenarios as well.
5118 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5120 struct drm_device *dev = crtc->dev;
5121 struct drm_i915_private *dev_priv = dev->dev_private;
5122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5123 int pipe = intel_crtc->pipe;
5124 uint16_t coeff = 0x7800; /* 1.0 */
5127 * TODO: Check what kind of values actually come out of the pipe
5128 * with these coeff/postoff values and adjust to get the best
5129 * accuracy. Perhaps we even need to take the bpc value into
5133 if (intel_crtc->config.limited_color_range)
5134 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5137 * GY/GU and RY/RU should be the other way around according
5138 * to BSpec, but reality doesn't agree. Just set them up in
5139 * a way that results in the correct picture.
5141 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5142 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5144 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5145 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5147 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5148 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5150 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5151 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5152 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5154 if (INTEL_INFO(dev)->gen > 6) {
5155 uint16_t postoff = 0;
5157 if (intel_crtc->config.limited_color_range)
5158 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5160 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5161 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5162 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5164 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5166 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5168 if (intel_crtc->config.limited_color_range)
5169 mode |= CSC_BLACK_SCREEN_OFFSET;
5171 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5175 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5176 struct drm_display_mode *adjusted_mode,
5179 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5181 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5184 val = I915_READ(PIPECONF(cpu_transcoder));
5186 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5188 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5190 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5191 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5192 val |= PIPECONF_INTERLACED_ILK;
5194 val |= PIPECONF_PROGRESSIVE;
5196 I915_WRITE(PIPECONF(cpu_transcoder), val);
5197 POSTING_READ(PIPECONF(cpu_transcoder));
5200 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5201 struct drm_display_mode *adjusted_mode,
5202 intel_clock_t *clock,
5203 bool *has_reduced_clock,
5204 intel_clock_t *reduced_clock)
5206 struct drm_device *dev = crtc->dev;
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5208 struct intel_encoder *intel_encoder;
5210 const intel_limit_t *limit;
5211 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5213 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5214 switch (intel_encoder->type) {
5215 case INTEL_OUTPUT_LVDS:
5218 case INTEL_OUTPUT_SDVO:
5219 case INTEL_OUTPUT_HDMI:
5221 if (intel_encoder->needs_tv_clock)
5224 case INTEL_OUTPUT_TVOUT:
5230 refclk = ironlake_get_refclk(crtc);
5233 * Returns a set of divisors for the desired target clock with the given
5234 * refclk, or FALSE. The returned values represent the clock equation:
5235 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5237 limit = intel_limit(crtc, refclk);
5238 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5243 if (is_lvds && dev_priv->lvds_downclock_avail) {
5245 * Ensure we match the reduced clock's P to the target clock.
5246 * If the clocks don't match, we can't switch the display clock
5247 * by using the FP0/FP1. In such case we will disable the LVDS
5248 * downclock feature.
5250 *has_reduced_clock = limit->find_pll(limit, crtc,
5251 dev_priv->lvds_downclock,
5257 if (is_sdvo && is_tv)
5258 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5263 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5265 struct drm_i915_private *dev_priv = dev->dev_private;
5268 temp = I915_READ(SOUTH_CHICKEN1);
5269 if (temp & FDI_BC_BIFURCATION_SELECT)
5272 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5273 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5275 temp |= FDI_BC_BIFURCATION_SELECT;
5276 DRM_DEBUG_KMS("enabling fdi C rx\n");
5277 I915_WRITE(SOUTH_CHICKEN1, temp);
5278 POSTING_READ(SOUTH_CHICKEN1);
5281 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5283 struct drm_device *dev = intel_crtc->base.dev;
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285 struct intel_crtc *pipe_B_crtc =
5286 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5288 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5289 intel_crtc->pipe, intel_crtc->fdi_lanes);
5290 if (intel_crtc->fdi_lanes > 4) {
5291 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5292 intel_crtc->pipe, intel_crtc->fdi_lanes);
5293 /* Clamp lanes to avoid programming the hw with bogus values. */
5294 intel_crtc->fdi_lanes = 4;
5299 if (INTEL_INFO(dev)->num_pipes == 2)
5302 switch (intel_crtc->pipe) {
5306 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5307 intel_crtc->fdi_lanes > 2) {
5308 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5309 intel_crtc->pipe, intel_crtc->fdi_lanes);
5310 /* Clamp lanes to avoid programming the hw with bogus values. */
5311 intel_crtc->fdi_lanes = 2;
5316 if (intel_crtc->fdi_lanes > 2)
5317 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5319 cpt_enable_fdi_bc_bifurcation(dev);
5323 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5324 if (intel_crtc->fdi_lanes > 2) {
5325 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5326 intel_crtc->pipe, intel_crtc->fdi_lanes);
5327 /* Clamp lanes to avoid programming the hw with bogus values. */
5328 intel_crtc->fdi_lanes = 2;
5333 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5337 cpt_enable_fdi_bc_bifurcation(dev);
5345 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5348 * Account for spread spectrum to avoid
5349 * oversubscribing the link. Max center spread
5350 * is 2.5%; use 5% for safety's sake.
5352 u32 bps = target_clock * bpp * 21 / 20;
5353 return bps / (link_bw * 8) + 1;
5356 static void ironlake_set_m_n(struct drm_crtc *crtc)
5358 struct drm_device *dev = crtc->dev;
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5361 struct drm_display_mode *adjusted_mode =
5362 &intel_crtc->config.adjusted_mode;
5363 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5364 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5365 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5366 struct intel_link_m_n m_n = {0};
5367 int target_clock, lane, link_bw;
5368 bool is_dp = false, is_cpu_edp = false;
5370 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5371 switch (intel_encoder->type) {
5372 case INTEL_OUTPUT_DISPLAYPORT:
5375 case INTEL_OUTPUT_EDP:
5377 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5379 edp_encoder = intel_encoder;
5386 /* CPU eDP doesn't require FDI link, so just set DP M/N
5387 according to current link config */
5389 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5391 /* FDI is a binary signal running at ~2.7GHz, encoding
5392 * each output octet as 10 bits. The actual frequency
5393 * is stored as a divider into a 100MHz clock, and the
5394 * mode pixel clock is stored in units of 1KHz.
5395 * Hence the bw of each lane in terms of the mode signal
5398 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5401 /* [e]DP over FDI requires target mode clock instead of link clock. */
5403 target_clock = intel_edp_target_clock(edp_encoder, mode);
5405 target_clock = mode->clock;
5407 target_clock = adjusted_mode->clock;
5410 lane = ironlake_get_lanes_required(target_clock, link_bw,
5411 intel_crtc->config.pipe_bpp);
5413 intel_crtc->fdi_lanes = lane;
5415 if (intel_crtc->config.pixel_multiplier > 1)
5416 link_bw *= intel_crtc->config.pixel_multiplier;
5417 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5420 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5421 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5422 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5423 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5426 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5427 intel_clock_t *clock, u32 fp)
5429 struct drm_crtc *crtc = &intel_crtc->base;
5430 struct drm_device *dev = crtc->dev;
5431 struct drm_i915_private *dev_priv = dev->dev_private;
5432 struct intel_encoder *intel_encoder;
5434 int factor, num_connectors = 0;
5435 bool is_lvds = false, is_sdvo = false, is_tv = false;
5436 bool is_dp = false, is_cpu_edp = false;
5438 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5439 switch (intel_encoder->type) {
5440 case INTEL_OUTPUT_LVDS:
5443 case INTEL_OUTPUT_SDVO:
5444 case INTEL_OUTPUT_HDMI:
5446 if (intel_encoder->needs_tv_clock)
5449 case INTEL_OUTPUT_TVOUT:
5452 case INTEL_OUTPUT_DISPLAYPORT:
5455 case INTEL_OUTPUT_EDP:
5457 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5465 /* Enable autotuning of the PLL clock (if permissible) */
5468 if ((intel_panel_use_ssc(dev_priv) &&
5469 dev_priv->lvds_ssc_freq == 100) ||
5470 intel_is_dual_link_lvds(dev))
5472 } else if (is_sdvo && is_tv)
5475 if (clock->m < factor * clock->n)
5481 dpll |= DPLLB_MODE_LVDS;
5483 dpll |= DPLLB_MODE_DAC_SERIAL;
5485 if (intel_crtc->config.pixel_multiplier > 1) {
5486 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5487 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5489 dpll |= DPLL_DVO_HIGH_SPEED;
5491 if (is_dp && !is_cpu_edp)
5492 dpll |= DPLL_DVO_HIGH_SPEED;
5494 /* compute bitmask from p1 value */
5495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5497 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5499 switch (clock->p2) {
5501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5514 if (is_sdvo && is_tv)
5515 dpll |= PLL_REF_INPUT_TVCLKINBC;
5517 /* XXX: just matching BIOS for now */
5518 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5520 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5521 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5523 dpll |= PLL_REF_INPUT_DREFCLK;
5528 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5530 struct drm_framebuffer *fb)
5532 struct drm_device *dev = crtc->dev;
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5535 struct drm_display_mode *adjusted_mode =
5536 &intel_crtc->config.adjusted_mode;
5537 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5538 int pipe = intel_crtc->pipe;
5539 int plane = intel_crtc->plane;
5540 int num_connectors = 0;
5541 intel_clock_t clock, reduced_clock;
5542 u32 dpll, fp = 0, fp2 = 0;
5543 bool ok, has_reduced_clock = false;
5544 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5545 struct intel_encoder *encoder;
5547 bool dither, fdi_config_ok;
5549 for_each_encoder_on_crtc(dev, crtc, encoder) {
5550 switch (encoder->type) {
5551 case INTEL_OUTPUT_LVDS:
5554 case INTEL_OUTPUT_DISPLAYPORT:
5557 case INTEL_OUTPUT_EDP:
5559 if (!intel_encoder_is_pch_edp(&encoder->base))
5567 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5568 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5570 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5571 &has_reduced_clock, &reduced_clock);
5573 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5577 /* Ensure that the cursor is valid for the new mode before changing... */
5578 intel_crtc_update_cursor(crtc, true);
5580 /* determine panel color depth */
5581 dither = intel_crtc->config.dither;
5582 if (is_lvds && dev_priv->lvds_dither)
5585 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5586 if (has_reduced_clock)
5587 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5590 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
5592 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5593 drm_mode_debug_printmodeline(mode);
5595 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5597 struct intel_pch_pll *pll;
5599 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5601 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5606 intel_put_pch_pll(intel_crtc);
5608 if (is_dp && !is_cpu_edp)
5609 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5611 for_each_encoder_on_crtc(dev, crtc, encoder)
5612 if (encoder->pre_pll_enable)
5613 encoder->pre_pll_enable(encoder);
5615 if (intel_crtc->pch_pll) {
5616 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5618 /* Wait for the clocks to stabilize. */
5619 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5622 /* The pixel multiplier can only be updated once the
5623 * DPLL is enabled and the clocks are stable.
5625 * So write it again.
5627 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5630 intel_crtc->lowfreq_avail = false;
5631 if (intel_crtc->pch_pll) {
5632 if (is_lvds && has_reduced_clock && i915_powersave) {
5633 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5634 intel_crtc->lowfreq_avail = true;
5636 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5640 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5642 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5643 * ironlake_check_fdi_lanes. */
5644 ironlake_set_m_n(crtc);
5646 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5648 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5650 intel_wait_for_vblank(dev, pipe);
5652 /* Set up the display plane register */
5653 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5654 POSTING_READ(DSPCNTR(plane));
5656 ret = intel_pipe_set_base(crtc, x, y, fb);
5658 intel_update_watermarks(dev);
5660 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5662 return fdi_config_ok ? ret : -EINVAL;
5665 static void haswell_modeset_global_resources(struct drm_device *dev)
5667 struct drm_i915_private *dev_priv = dev->dev_private;
5668 bool enable = false;
5669 struct intel_crtc *crtc;
5670 struct intel_encoder *encoder;
5672 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5673 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5675 /* XXX: Should check for edp transcoder here, but thanks to init
5676 * sequence that's not yet available. Just in case desktop eDP
5677 * on PORT D is possible on haswell, too. */
5680 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5682 if (encoder->type != INTEL_OUTPUT_EDP &&
5683 encoder->connectors_active)
5687 /* Even the eDP panel fitter is outside the always-on well. */
5688 if (dev_priv->pch_pf_size)
5691 intel_set_power_well(dev, enable);
5694 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5696 struct drm_framebuffer *fb)
5698 struct drm_device *dev = crtc->dev;
5699 struct drm_i915_private *dev_priv = dev->dev_private;
5700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5701 struct drm_display_mode *adjusted_mode =
5702 &intel_crtc->config.adjusted_mode;
5703 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5704 int pipe = intel_crtc->pipe;
5705 int plane = intel_crtc->plane;
5706 int num_connectors = 0;
5707 bool is_dp = false, is_cpu_edp = false;
5708 struct intel_encoder *encoder;
5712 for_each_encoder_on_crtc(dev, crtc, encoder) {
5713 switch (encoder->type) {
5714 case INTEL_OUTPUT_DISPLAYPORT:
5717 case INTEL_OUTPUT_EDP:
5719 if (!intel_encoder_is_pch_edp(&encoder->base))
5727 /* We are not sure yet this won't happen. */
5728 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5729 INTEL_PCH_TYPE(dev));
5731 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5732 num_connectors, pipe_name(pipe));
5734 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5735 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5737 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5739 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5742 /* Ensure that the cursor is valid for the new mode before changing... */
5743 intel_crtc_update_cursor(crtc, true);
5745 /* determine panel color depth */
5746 dither = intel_crtc->config.dither;
5748 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5749 drm_mode_debug_printmodeline(mode);
5751 if (is_dp && !is_cpu_edp)
5752 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5754 intel_crtc->lowfreq_avail = false;
5756 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5758 if (!is_dp || is_cpu_edp)
5759 ironlake_set_m_n(crtc);
5761 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5763 intel_set_pipe_csc(crtc);
5765 /* Set up the display plane register */
5766 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5767 POSTING_READ(DSPCNTR(plane));
5769 ret = intel_pipe_set_base(crtc, x, y, fb);
5771 intel_update_watermarks(dev);
5773 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5778 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5780 struct drm_framebuffer *fb)
5782 struct drm_device *dev = crtc->dev;
5783 struct drm_i915_private *dev_priv = dev->dev_private;
5784 struct drm_encoder_helper_funcs *encoder_funcs;
5785 struct intel_encoder *encoder;
5786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5787 struct drm_display_mode *adjusted_mode =
5788 &intel_crtc->config.adjusted_mode;
5789 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5790 int pipe = intel_crtc->pipe;
5793 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5794 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5796 intel_crtc->cpu_transcoder = pipe;
5798 drm_vblank_pre_modeset(dev, pipe);
5800 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5802 drm_vblank_post_modeset(dev, pipe);
5807 for_each_encoder_on_crtc(dev, crtc, encoder) {
5808 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5809 encoder->base.base.id,
5810 drm_get_encoder_name(&encoder->base),
5811 mode->base.id, mode->name);
5812 if (encoder->mode_set) {
5813 encoder->mode_set(encoder);
5815 encoder_funcs = encoder->base.helper_private;
5816 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5823 static bool intel_eld_uptodate(struct drm_connector *connector,
5824 int reg_eldv, uint32_t bits_eldv,
5825 int reg_elda, uint32_t bits_elda,
5828 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5829 uint8_t *eld = connector->eld;
5832 i = I915_READ(reg_eldv);
5841 i = I915_READ(reg_elda);
5843 I915_WRITE(reg_elda, i);
5845 for (i = 0; i < eld[2]; i++)
5846 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5852 static void g4x_write_eld(struct drm_connector *connector,
5853 struct drm_crtc *crtc)
5855 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5856 uint8_t *eld = connector->eld;
5861 i = I915_READ(G4X_AUD_VID_DID);
5863 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5864 eldv = G4X_ELDV_DEVCL_DEVBLC;
5866 eldv = G4X_ELDV_DEVCTG;
5868 if (intel_eld_uptodate(connector,
5869 G4X_AUD_CNTL_ST, eldv,
5870 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5871 G4X_HDMIW_HDMIEDID))
5874 i = I915_READ(G4X_AUD_CNTL_ST);
5875 i &= ~(eldv | G4X_ELD_ADDR);
5876 len = (i >> 9) & 0x1f; /* ELD buffer size */
5877 I915_WRITE(G4X_AUD_CNTL_ST, i);
5882 len = min_t(uint8_t, eld[2], len);
5883 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5884 for (i = 0; i < len; i++)
5885 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5887 i = I915_READ(G4X_AUD_CNTL_ST);
5889 I915_WRITE(G4X_AUD_CNTL_ST, i);
5892 static void haswell_write_eld(struct drm_connector *connector,
5893 struct drm_crtc *crtc)
5895 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5896 uint8_t *eld = connector->eld;
5897 struct drm_device *dev = crtc->dev;
5898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5902 int pipe = to_intel_crtc(crtc)->pipe;
5905 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5906 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5907 int aud_config = HSW_AUD_CFG(pipe);
5908 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5911 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5913 /* Audio output enable */
5914 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5915 tmp = I915_READ(aud_cntrl_st2);
5916 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5917 I915_WRITE(aud_cntrl_st2, tmp);
5919 /* Wait for 1 vertical blank */
5920 intel_wait_for_vblank(dev, pipe);
5922 /* Set ELD valid state */
5923 tmp = I915_READ(aud_cntrl_st2);
5924 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5925 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5926 I915_WRITE(aud_cntrl_st2, tmp);
5927 tmp = I915_READ(aud_cntrl_st2);
5928 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5930 /* Enable HDMI mode */
5931 tmp = I915_READ(aud_config);
5932 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5933 /* clear N_programing_enable and N_value_index */
5934 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5935 I915_WRITE(aud_config, tmp);
5937 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5939 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5940 intel_crtc->eld_vld = true;
5942 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5943 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5944 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5945 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5947 I915_WRITE(aud_config, 0);
5949 if (intel_eld_uptodate(connector,
5950 aud_cntrl_st2, eldv,
5951 aud_cntl_st, IBX_ELD_ADDRESS,
5955 i = I915_READ(aud_cntrl_st2);
5957 I915_WRITE(aud_cntrl_st2, i);
5962 i = I915_READ(aud_cntl_st);
5963 i &= ~IBX_ELD_ADDRESS;
5964 I915_WRITE(aud_cntl_st, i);
5965 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5966 DRM_DEBUG_DRIVER("port num:%d\n", i);
5968 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5969 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5970 for (i = 0; i < len; i++)
5971 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5973 i = I915_READ(aud_cntrl_st2);
5975 I915_WRITE(aud_cntrl_st2, i);
5979 static void ironlake_write_eld(struct drm_connector *connector,
5980 struct drm_crtc *crtc)
5982 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5983 uint8_t *eld = connector->eld;
5991 int pipe = to_intel_crtc(crtc)->pipe;
5993 if (HAS_PCH_IBX(connector->dev)) {
5994 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5995 aud_config = IBX_AUD_CFG(pipe);
5996 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5997 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5999 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6000 aud_config = CPT_AUD_CFG(pipe);
6001 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6002 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6005 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6007 i = I915_READ(aud_cntl_st);
6008 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6010 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6011 /* operate blindly on all ports */
6012 eldv = IBX_ELD_VALIDB;
6013 eldv |= IBX_ELD_VALIDB << 4;
6014 eldv |= IBX_ELD_VALIDB << 8;
6016 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6017 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6020 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6021 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6022 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6023 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6025 I915_WRITE(aud_config, 0);
6027 if (intel_eld_uptodate(connector,
6028 aud_cntrl_st2, eldv,
6029 aud_cntl_st, IBX_ELD_ADDRESS,
6033 i = I915_READ(aud_cntrl_st2);
6035 I915_WRITE(aud_cntrl_st2, i);
6040 i = I915_READ(aud_cntl_st);
6041 i &= ~IBX_ELD_ADDRESS;
6042 I915_WRITE(aud_cntl_st, i);
6044 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6045 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6046 for (i = 0; i < len; i++)
6047 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6049 i = I915_READ(aud_cntrl_st2);
6051 I915_WRITE(aud_cntrl_st2, i);
6054 void intel_write_eld(struct drm_encoder *encoder,
6055 struct drm_display_mode *mode)
6057 struct drm_crtc *crtc = encoder->crtc;
6058 struct drm_connector *connector;
6059 struct drm_device *dev = encoder->dev;
6060 struct drm_i915_private *dev_priv = dev->dev_private;
6062 connector = drm_select_eld(encoder, mode);
6066 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6068 drm_get_connector_name(connector),
6069 connector->encoder->base.id,
6070 drm_get_encoder_name(connector->encoder));
6072 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6074 if (dev_priv->display.write_eld)
6075 dev_priv->display.write_eld(connector, crtc);
6078 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6079 void intel_crtc_load_lut(struct drm_crtc *crtc)
6081 struct drm_device *dev = crtc->dev;
6082 struct drm_i915_private *dev_priv = dev->dev_private;
6083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084 int palreg = PALETTE(intel_crtc->pipe);
6087 /* The clocks have to be on to load the palette. */
6088 if (!crtc->enabled || !intel_crtc->active)
6091 /* use legacy palette for Ironlake */
6092 if (HAS_PCH_SPLIT(dev))
6093 palreg = LGC_PALETTE(intel_crtc->pipe);
6095 for (i = 0; i < 256; i++) {
6096 I915_WRITE(palreg + 4 * i,
6097 (intel_crtc->lut_r[i] << 16) |
6098 (intel_crtc->lut_g[i] << 8) |
6099 intel_crtc->lut_b[i]);
6103 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6105 struct drm_device *dev = crtc->dev;
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6108 bool visible = base != 0;
6111 if (intel_crtc->cursor_visible == visible)
6114 cntl = I915_READ(_CURACNTR);
6116 /* On these chipsets we can only modify the base whilst
6117 * the cursor is disabled.
6119 I915_WRITE(_CURABASE, base);
6121 cntl &= ~(CURSOR_FORMAT_MASK);
6122 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6123 cntl |= CURSOR_ENABLE |
6124 CURSOR_GAMMA_ENABLE |
6127 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6128 I915_WRITE(_CURACNTR, cntl);
6130 intel_crtc->cursor_visible = visible;
6133 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6135 struct drm_device *dev = crtc->dev;
6136 struct drm_i915_private *dev_priv = dev->dev_private;
6137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6138 int pipe = intel_crtc->pipe;
6139 bool visible = base != 0;
6141 if (intel_crtc->cursor_visible != visible) {
6142 uint32_t cntl = I915_READ(CURCNTR(pipe));
6144 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6145 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6146 cntl |= pipe << 28; /* Connect to correct pipe */
6148 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6149 cntl |= CURSOR_MODE_DISABLE;
6151 I915_WRITE(CURCNTR(pipe), cntl);
6153 intel_crtc->cursor_visible = visible;
6155 /* and commit changes on next vblank */
6156 I915_WRITE(CURBASE(pipe), base);
6159 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6161 struct drm_device *dev = crtc->dev;
6162 struct drm_i915_private *dev_priv = dev->dev_private;
6163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6164 int pipe = intel_crtc->pipe;
6165 bool visible = base != 0;
6167 if (intel_crtc->cursor_visible != visible) {
6168 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6170 cntl &= ~CURSOR_MODE;
6171 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6173 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6174 cntl |= CURSOR_MODE_DISABLE;
6176 if (IS_HASWELL(dev))
6177 cntl |= CURSOR_PIPE_CSC_ENABLE;
6178 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6180 intel_crtc->cursor_visible = visible;
6182 /* and commit changes on next vblank */
6183 I915_WRITE(CURBASE_IVB(pipe), base);
6186 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6187 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6190 struct drm_device *dev = crtc->dev;
6191 struct drm_i915_private *dev_priv = dev->dev_private;
6192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6193 int pipe = intel_crtc->pipe;
6194 int x = intel_crtc->cursor_x;
6195 int y = intel_crtc->cursor_y;
6201 if (on && crtc->enabled && crtc->fb) {
6202 base = intel_crtc->cursor_addr;
6203 if (x > (int) crtc->fb->width)
6206 if (y > (int) crtc->fb->height)
6212 if (x + intel_crtc->cursor_width < 0)
6215 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6218 pos |= x << CURSOR_X_SHIFT;
6221 if (y + intel_crtc->cursor_height < 0)
6224 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6227 pos |= y << CURSOR_Y_SHIFT;
6229 visible = base != 0;
6230 if (!visible && !intel_crtc->cursor_visible)
6233 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6234 I915_WRITE(CURPOS_IVB(pipe), pos);
6235 ivb_update_cursor(crtc, base);
6237 I915_WRITE(CURPOS(pipe), pos);
6238 if (IS_845G(dev) || IS_I865G(dev))
6239 i845_update_cursor(crtc, base);
6241 i9xx_update_cursor(crtc, base);
6245 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6246 struct drm_file *file,
6248 uint32_t width, uint32_t height)
6250 struct drm_device *dev = crtc->dev;
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6253 struct drm_i915_gem_object *obj;
6257 /* if we want to turn off the cursor ignore width and height */
6259 DRM_DEBUG_KMS("cursor off\n");
6262 mutex_lock(&dev->struct_mutex);
6266 /* Currently we only support 64x64 cursors */
6267 if (width != 64 || height != 64) {
6268 DRM_ERROR("we currently only support 64x64 cursors\n");
6272 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6273 if (&obj->base == NULL)
6276 if (obj->base.size < width * height * 4) {
6277 DRM_ERROR("buffer is to small\n");
6282 /* we only need to pin inside GTT if cursor is non-phy */
6283 mutex_lock(&dev->struct_mutex);
6284 if (!dev_priv->info->cursor_needs_physical) {
6287 if (obj->tiling_mode) {
6288 DRM_ERROR("cursor cannot be tiled\n");
6293 /* Note that the w/a also requires 2 PTE of padding following
6294 * the bo. We currently fill all unused PTE with the shadow
6295 * page and so we should always have valid PTE following the
6296 * cursor preventing the VT-d warning.
6299 if (need_vtd_wa(dev))
6300 alignment = 64*1024;
6302 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6304 DRM_ERROR("failed to move cursor bo into the GTT\n");
6308 ret = i915_gem_object_put_fence(obj);
6310 DRM_ERROR("failed to release fence for cursor");
6314 addr = obj->gtt_offset;
6316 int align = IS_I830(dev) ? 16 * 1024 : 256;
6317 ret = i915_gem_attach_phys_object(dev, obj,
6318 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6321 DRM_ERROR("failed to attach phys object\n");
6324 addr = obj->phys_obj->handle->busaddr;
6328 I915_WRITE(CURSIZE, (height << 12) | width);
6331 if (intel_crtc->cursor_bo) {
6332 if (dev_priv->info->cursor_needs_physical) {
6333 if (intel_crtc->cursor_bo != obj)
6334 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6336 i915_gem_object_unpin(intel_crtc->cursor_bo);
6337 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6340 mutex_unlock(&dev->struct_mutex);
6342 intel_crtc->cursor_addr = addr;
6343 intel_crtc->cursor_bo = obj;
6344 intel_crtc->cursor_width = width;
6345 intel_crtc->cursor_height = height;
6347 intel_crtc_update_cursor(crtc, true);
6351 i915_gem_object_unpin(obj);
6353 mutex_unlock(&dev->struct_mutex);
6355 drm_gem_object_unreference_unlocked(&obj->base);
6359 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6363 intel_crtc->cursor_x = x;
6364 intel_crtc->cursor_y = y;
6366 intel_crtc_update_cursor(crtc, true);
6371 /** Sets the color ramps on behalf of RandR */
6372 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6373 u16 blue, int regno)
6375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6377 intel_crtc->lut_r[regno] = red >> 8;
6378 intel_crtc->lut_g[regno] = green >> 8;
6379 intel_crtc->lut_b[regno] = blue >> 8;
6382 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6383 u16 *blue, int regno)
6385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387 *red = intel_crtc->lut_r[regno] << 8;
6388 *green = intel_crtc->lut_g[regno] << 8;
6389 *blue = intel_crtc->lut_b[regno] << 8;
6392 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6393 u16 *blue, uint32_t start, uint32_t size)
6395 int end = (start + size > 256) ? 256 : start + size, i;
6396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6398 for (i = start; i < end; i++) {
6399 intel_crtc->lut_r[i] = red[i] >> 8;
6400 intel_crtc->lut_g[i] = green[i] >> 8;
6401 intel_crtc->lut_b[i] = blue[i] >> 8;
6404 intel_crtc_load_lut(crtc);
6407 /* VESA 640x480x72Hz mode to set on the pipe */
6408 static struct drm_display_mode load_detect_mode = {
6409 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6410 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6413 static struct drm_framebuffer *
6414 intel_framebuffer_create(struct drm_device *dev,
6415 struct drm_mode_fb_cmd2 *mode_cmd,
6416 struct drm_i915_gem_object *obj)
6418 struct intel_framebuffer *intel_fb;
6421 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6423 drm_gem_object_unreference_unlocked(&obj->base);
6424 return ERR_PTR(-ENOMEM);
6427 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6429 drm_gem_object_unreference_unlocked(&obj->base);
6431 return ERR_PTR(ret);
6434 return &intel_fb->base;
6438 intel_framebuffer_pitch_for_width(int width, int bpp)
6440 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6441 return ALIGN(pitch, 64);
6445 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6447 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6448 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6451 static struct drm_framebuffer *
6452 intel_framebuffer_create_for_mode(struct drm_device *dev,
6453 struct drm_display_mode *mode,
6456 struct drm_i915_gem_object *obj;
6457 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6459 obj = i915_gem_alloc_object(dev,
6460 intel_framebuffer_size_for_mode(mode, bpp));
6462 return ERR_PTR(-ENOMEM);
6464 mode_cmd.width = mode->hdisplay;
6465 mode_cmd.height = mode->vdisplay;
6466 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6468 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6470 return intel_framebuffer_create(dev, &mode_cmd, obj);
6473 static struct drm_framebuffer *
6474 mode_fits_in_fbdev(struct drm_device *dev,
6475 struct drm_display_mode *mode)
6477 struct drm_i915_private *dev_priv = dev->dev_private;
6478 struct drm_i915_gem_object *obj;
6479 struct drm_framebuffer *fb;
6481 if (dev_priv->fbdev == NULL)
6484 obj = dev_priv->fbdev->ifb.obj;
6488 fb = &dev_priv->fbdev->ifb.base;
6489 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6490 fb->bits_per_pixel))
6493 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6499 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6500 struct drm_display_mode *mode,
6501 struct intel_load_detect_pipe *old)
6503 struct intel_crtc *intel_crtc;
6504 struct intel_encoder *intel_encoder =
6505 intel_attached_encoder(connector);
6506 struct drm_crtc *possible_crtc;
6507 struct drm_encoder *encoder = &intel_encoder->base;
6508 struct drm_crtc *crtc = NULL;
6509 struct drm_device *dev = encoder->dev;
6510 struct drm_framebuffer *fb;
6513 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6514 connector->base.id, drm_get_connector_name(connector),
6515 encoder->base.id, drm_get_encoder_name(encoder));
6518 * Algorithm gets a little messy:
6520 * - if the connector already has an assigned crtc, use it (but make
6521 * sure it's on first)
6523 * - try to find the first unused crtc that can drive this connector,
6524 * and use that if we find one
6527 /* See if we already have a CRTC for this connector */
6528 if (encoder->crtc) {
6529 crtc = encoder->crtc;
6531 mutex_lock(&crtc->mutex);
6533 old->dpms_mode = connector->dpms;
6534 old->load_detect_temp = false;
6536 /* Make sure the crtc and connector are running */
6537 if (connector->dpms != DRM_MODE_DPMS_ON)
6538 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6543 /* Find an unused one (if possible) */
6544 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6546 if (!(encoder->possible_crtcs & (1 << i)))
6548 if (!possible_crtc->enabled) {
6549 crtc = possible_crtc;
6555 * If we didn't find an unused CRTC, don't use any.
6558 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6562 mutex_lock(&crtc->mutex);
6563 intel_encoder->new_crtc = to_intel_crtc(crtc);
6564 to_intel_connector(connector)->new_encoder = intel_encoder;
6566 intel_crtc = to_intel_crtc(crtc);
6567 old->dpms_mode = connector->dpms;
6568 old->load_detect_temp = true;
6569 old->release_fb = NULL;
6572 mode = &load_detect_mode;
6574 /* We need a framebuffer large enough to accommodate all accesses
6575 * that the plane may generate whilst we perform load detection.
6576 * We can not rely on the fbcon either being present (we get called
6577 * during its initialisation to detect all boot displays, or it may
6578 * not even exist) or that it is large enough to satisfy the
6581 fb = mode_fits_in_fbdev(dev, mode);
6583 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6584 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6585 old->release_fb = fb;
6587 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6589 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6590 mutex_unlock(&crtc->mutex);
6594 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6595 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6596 if (old->release_fb)
6597 old->release_fb->funcs->destroy(old->release_fb);
6598 mutex_unlock(&crtc->mutex);
6602 /* let the connector get through one full cycle before testing */
6603 intel_wait_for_vblank(dev, intel_crtc->pipe);
6607 void intel_release_load_detect_pipe(struct drm_connector *connector,
6608 struct intel_load_detect_pipe *old)
6610 struct intel_encoder *intel_encoder =
6611 intel_attached_encoder(connector);
6612 struct drm_encoder *encoder = &intel_encoder->base;
6613 struct drm_crtc *crtc = encoder->crtc;
6615 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6616 connector->base.id, drm_get_connector_name(connector),
6617 encoder->base.id, drm_get_encoder_name(encoder));
6619 if (old->load_detect_temp) {
6620 to_intel_connector(connector)->new_encoder = NULL;
6621 intel_encoder->new_crtc = NULL;
6622 intel_set_mode(crtc, NULL, 0, 0, NULL);
6624 if (old->release_fb) {
6625 drm_framebuffer_unregister_private(old->release_fb);
6626 drm_framebuffer_unreference(old->release_fb);
6629 mutex_unlock(&crtc->mutex);
6633 /* Switch crtc and encoder back off if necessary */
6634 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6635 connector->funcs->dpms(connector, old->dpms_mode);
6637 mutex_unlock(&crtc->mutex);
6640 /* Returns the clock of the currently programmed mode of the given pipe. */
6641 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6645 int pipe = intel_crtc->pipe;
6646 u32 dpll = I915_READ(DPLL(pipe));
6648 intel_clock_t clock;
6650 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6651 fp = I915_READ(FP0(pipe));
6653 fp = I915_READ(FP1(pipe));
6655 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6656 if (IS_PINEVIEW(dev)) {
6657 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6658 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6660 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6661 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6664 if (!IS_GEN2(dev)) {
6665 if (IS_PINEVIEW(dev))
6666 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6667 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6669 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6670 DPLL_FPA01_P1_POST_DIV_SHIFT);
6672 switch (dpll & DPLL_MODE_MASK) {
6673 case DPLLB_MODE_DAC_SERIAL:
6674 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6677 case DPLLB_MODE_LVDS:
6678 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6682 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6683 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6687 /* XXX: Handle the 100Mhz refclk */
6688 intel_clock(dev, 96000, &clock);
6690 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6693 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6694 DPLL_FPA01_P1_POST_DIV_SHIFT);
6697 if ((dpll & PLL_REF_INPUT_MASK) ==
6698 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6699 /* XXX: might not be 66MHz */
6700 intel_clock(dev, 66000, &clock);
6702 intel_clock(dev, 48000, &clock);
6704 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6707 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6708 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6710 if (dpll & PLL_P2_DIVIDE_BY_4)
6715 intel_clock(dev, 48000, &clock);
6719 /* XXX: It would be nice to validate the clocks, but we can't reuse
6720 * i830PllIsValid() because it relies on the xf86_config connector
6721 * configuration being accurate, which it isn't necessarily.
6727 /** Returns the currently programmed mode of the given pipe. */
6728 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6729 struct drm_crtc *crtc)
6731 struct drm_i915_private *dev_priv = dev->dev_private;
6732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6733 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6734 struct drm_display_mode *mode;
6735 int htot = I915_READ(HTOTAL(cpu_transcoder));
6736 int hsync = I915_READ(HSYNC(cpu_transcoder));
6737 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6738 int vsync = I915_READ(VSYNC(cpu_transcoder));
6740 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6744 mode->clock = intel_crtc_clock_get(dev, crtc);
6745 mode->hdisplay = (htot & 0xffff) + 1;
6746 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6747 mode->hsync_start = (hsync & 0xffff) + 1;
6748 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6749 mode->vdisplay = (vtot & 0xffff) + 1;
6750 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6751 mode->vsync_start = (vsync & 0xffff) + 1;
6752 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6754 drm_mode_set_name(mode);
6759 static void intel_increase_pllclock(struct drm_crtc *crtc)
6761 struct drm_device *dev = crtc->dev;
6762 drm_i915_private_t *dev_priv = dev->dev_private;
6763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6764 int pipe = intel_crtc->pipe;
6765 int dpll_reg = DPLL(pipe);
6768 if (HAS_PCH_SPLIT(dev))
6771 if (!dev_priv->lvds_downclock_avail)
6774 dpll = I915_READ(dpll_reg);
6775 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6776 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6778 assert_panel_unlocked(dev_priv, pipe);
6780 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6781 I915_WRITE(dpll_reg, dpll);
6782 intel_wait_for_vblank(dev, pipe);
6784 dpll = I915_READ(dpll_reg);
6785 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6786 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6790 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6792 struct drm_device *dev = crtc->dev;
6793 drm_i915_private_t *dev_priv = dev->dev_private;
6794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6796 if (HAS_PCH_SPLIT(dev))
6799 if (!dev_priv->lvds_downclock_avail)
6803 * Since this is called by a timer, we should never get here in
6806 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6807 int pipe = intel_crtc->pipe;
6808 int dpll_reg = DPLL(pipe);
6811 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6813 assert_panel_unlocked(dev_priv, pipe);
6815 dpll = I915_READ(dpll_reg);
6816 dpll |= DISPLAY_RATE_SELECT_FPA1;
6817 I915_WRITE(dpll_reg, dpll);
6818 intel_wait_for_vblank(dev, pipe);
6819 dpll = I915_READ(dpll_reg);
6820 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6821 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6826 void intel_mark_busy(struct drm_device *dev)
6828 i915_update_gfx_val(dev->dev_private);
6831 void intel_mark_idle(struct drm_device *dev)
6833 struct drm_crtc *crtc;
6835 if (!i915_powersave)
6838 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6842 intel_decrease_pllclock(crtc);
6846 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6848 struct drm_device *dev = obj->base.dev;
6849 struct drm_crtc *crtc;
6851 if (!i915_powersave)
6854 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6858 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6859 intel_increase_pllclock(crtc);
6863 static void intel_crtc_destroy(struct drm_crtc *crtc)
6865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6866 struct drm_device *dev = crtc->dev;
6867 struct intel_unpin_work *work;
6868 unsigned long flags;
6870 spin_lock_irqsave(&dev->event_lock, flags);
6871 work = intel_crtc->unpin_work;
6872 intel_crtc->unpin_work = NULL;
6873 spin_unlock_irqrestore(&dev->event_lock, flags);
6876 cancel_work_sync(&work->work);
6880 drm_crtc_cleanup(crtc);
6885 static void intel_unpin_work_fn(struct work_struct *__work)
6887 struct intel_unpin_work *work =
6888 container_of(__work, struct intel_unpin_work, work);
6889 struct drm_device *dev = work->crtc->dev;
6891 mutex_lock(&dev->struct_mutex);
6892 intel_unpin_fb_obj(work->old_fb_obj);
6893 drm_gem_object_unreference(&work->pending_flip_obj->base);
6894 drm_gem_object_unreference(&work->old_fb_obj->base);
6896 intel_update_fbc(dev);
6897 mutex_unlock(&dev->struct_mutex);
6899 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6900 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6905 static void do_intel_finish_page_flip(struct drm_device *dev,
6906 struct drm_crtc *crtc)
6908 drm_i915_private_t *dev_priv = dev->dev_private;
6909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6910 struct intel_unpin_work *work;
6911 unsigned long flags;
6913 /* Ignore early vblank irqs */
6914 if (intel_crtc == NULL)
6917 spin_lock_irqsave(&dev->event_lock, flags);
6918 work = intel_crtc->unpin_work;
6920 /* Ensure we don't miss a work->pending update ... */
6923 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6924 spin_unlock_irqrestore(&dev->event_lock, flags);
6928 /* and that the unpin work is consistent wrt ->pending. */
6931 intel_crtc->unpin_work = NULL;
6934 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6936 drm_vblank_put(dev, intel_crtc->pipe);
6938 spin_unlock_irqrestore(&dev->event_lock, flags);
6940 wake_up_all(&dev_priv->pending_flip_queue);
6942 queue_work(dev_priv->wq, &work->work);
6944 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6947 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6949 drm_i915_private_t *dev_priv = dev->dev_private;
6950 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6952 do_intel_finish_page_flip(dev, crtc);
6955 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6957 drm_i915_private_t *dev_priv = dev->dev_private;
6958 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6960 do_intel_finish_page_flip(dev, crtc);
6963 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6965 drm_i915_private_t *dev_priv = dev->dev_private;
6966 struct intel_crtc *intel_crtc =
6967 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6968 unsigned long flags;
6970 /* NB: An MMIO update of the plane base pointer will also
6971 * generate a page-flip completion irq, i.e. every modeset
6972 * is also accompanied by a spurious intel_prepare_page_flip().
6974 spin_lock_irqsave(&dev->event_lock, flags);
6975 if (intel_crtc->unpin_work)
6976 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6977 spin_unlock_irqrestore(&dev->event_lock, flags);
6980 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6982 /* Ensure that the work item is consistent when activating it ... */
6984 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6985 /* and that it is marked active as soon as the irq could fire. */
6989 static int intel_gen2_queue_flip(struct drm_device *dev,
6990 struct drm_crtc *crtc,
6991 struct drm_framebuffer *fb,
6992 struct drm_i915_gem_object *obj)
6994 struct drm_i915_private *dev_priv = dev->dev_private;
6995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6997 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7000 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7004 ret = intel_ring_begin(ring, 6);
7008 /* Can't queue multiple flips, so wait for the previous
7009 * one to finish before executing the next.
7011 if (intel_crtc->plane)
7012 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7014 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7015 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7016 intel_ring_emit(ring, MI_NOOP);
7017 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7018 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7019 intel_ring_emit(ring, fb->pitches[0]);
7020 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7021 intel_ring_emit(ring, 0); /* aux display base address, unused */
7023 intel_mark_page_flip_active(intel_crtc);
7024 intel_ring_advance(ring);
7028 intel_unpin_fb_obj(obj);
7033 static int intel_gen3_queue_flip(struct drm_device *dev,
7034 struct drm_crtc *crtc,
7035 struct drm_framebuffer *fb,
7036 struct drm_i915_gem_object *obj)
7038 struct drm_i915_private *dev_priv = dev->dev_private;
7039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7041 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7044 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7048 ret = intel_ring_begin(ring, 6);
7052 if (intel_crtc->plane)
7053 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7055 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7056 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7057 intel_ring_emit(ring, MI_NOOP);
7058 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7059 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7060 intel_ring_emit(ring, fb->pitches[0]);
7061 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7062 intel_ring_emit(ring, MI_NOOP);
7064 intel_mark_page_flip_active(intel_crtc);
7065 intel_ring_advance(ring);
7069 intel_unpin_fb_obj(obj);
7074 static int intel_gen4_queue_flip(struct drm_device *dev,
7075 struct drm_crtc *crtc,
7076 struct drm_framebuffer *fb,
7077 struct drm_i915_gem_object *obj)
7079 struct drm_i915_private *dev_priv = dev->dev_private;
7080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7081 uint32_t pf, pipesrc;
7082 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7085 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7089 ret = intel_ring_begin(ring, 4);
7093 /* i965+ uses the linear or tiled offsets from the
7094 * Display Registers (which do not change across a page-flip)
7095 * so we need only reprogram the base address.
7097 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7098 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7099 intel_ring_emit(ring, fb->pitches[0]);
7100 intel_ring_emit(ring,
7101 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7104 /* XXX Enabling the panel-fitter across page-flip is so far
7105 * untested on non-native modes, so ignore it for now.
7106 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7109 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7110 intel_ring_emit(ring, pf | pipesrc);
7112 intel_mark_page_flip_active(intel_crtc);
7113 intel_ring_advance(ring);
7117 intel_unpin_fb_obj(obj);
7122 static int intel_gen6_queue_flip(struct drm_device *dev,
7123 struct drm_crtc *crtc,
7124 struct drm_framebuffer *fb,
7125 struct drm_i915_gem_object *obj)
7127 struct drm_i915_private *dev_priv = dev->dev_private;
7128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7129 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7130 uint32_t pf, pipesrc;
7133 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7137 ret = intel_ring_begin(ring, 4);
7141 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7142 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7143 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7144 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7146 /* Contrary to the suggestions in the documentation,
7147 * "Enable Panel Fitter" does not seem to be required when page
7148 * flipping with a non-native mode, and worse causes a normal
7150 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7153 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7154 intel_ring_emit(ring, pf | pipesrc);
7156 intel_mark_page_flip_active(intel_crtc);
7157 intel_ring_advance(ring);
7161 intel_unpin_fb_obj(obj);
7167 * On gen7 we currently use the blit ring because (in early silicon at least)
7168 * the render ring doesn't give us interrpts for page flip completion, which
7169 * means clients will hang after the first flip is queued. Fortunately the
7170 * blit ring generates interrupts properly, so use it instead.
7172 static int intel_gen7_queue_flip(struct drm_device *dev,
7173 struct drm_crtc *crtc,
7174 struct drm_framebuffer *fb,
7175 struct drm_i915_gem_object *obj)
7177 struct drm_i915_private *dev_priv = dev->dev_private;
7178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7179 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7180 uint32_t plane_bit = 0;
7183 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7187 switch(intel_crtc->plane) {
7189 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7192 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7195 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7198 WARN_ONCE(1, "unknown plane in flip command\n");
7203 ret = intel_ring_begin(ring, 4);
7207 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7208 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7209 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7210 intel_ring_emit(ring, (MI_NOOP));
7212 intel_mark_page_flip_active(intel_crtc);
7213 intel_ring_advance(ring);
7217 intel_unpin_fb_obj(obj);
7222 static int intel_default_queue_flip(struct drm_device *dev,
7223 struct drm_crtc *crtc,
7224 struct drm_framebuffer *fb,
7225 struct drm_i915_gem_object *obj)
7230 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7231 struct drm_framebuffer *fb,
7232 struct drm_pending_vblank_event *event)
7234 struct drm_device *dev = crtc->dev;
7235 struct drm_i915_private *dev_priv = dev->dev_private;
7236 struct drm_framebuffer *old_fb = crtc->fb;
7237 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7239 struct intel_unpin_work *work;
7240 unsigned long flags;
7243 /* Can't change pixel format via MI display flips. */
7244 if (fb->pixel_format != crtc->fb->pixel_format)
7248 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7249 * Note that pitch changes could also affect these register.
7251 if (INTEL_INFO(dev)->gen > 3 &&
7252 (fb->offsets[0] != crtc->fb->offsets[0] ||
7253 fb->pitches[0] != crtc->fb->pitches[0]))
7256 work = kzalloc(sizeof *work, GFP_KERNEL);
7260 work->event = event;
7262 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7263 INIT_WORK(&work->work, intel_unpin_work_fn);
7265 ret = drm_vblank_get(dev, intel_crtc->pipe);
7269 /* We borrow the event spin lock for protecting unpin_work */
7270 spin_lock_irqsave(&dev->event_lock, flags);
7271 if (intel_crtc->unpin_work) {
7272 spin_unlock_irqrestore(&dev->event_lock, flags);
7274 drm_vblank_put(dev, intel_crtc->pipe);
7276 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7279 intel_crtc->unpin_work = work;
7280 spin_unlock_irqrestore(&dev->event_lock, flags);
7282 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7283 flush_workqueue(dev_priv->wq);
7285 ret = i915_mutex_lock_interruptible(dev);
7289 /* Reference the objects for the scheduled work. */
7290 drm_gem_object_reference(&work->old_fb_obj->base);
7291 drm_gem_object_reference(&obj->base);
7295 work->pending_flip_obj = obj;
7297 work->enable_stall_check = true;
7299 atomic_inc(&intel_crtc->unpin_work_count);
7300 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7302 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7304 goto cleanup_pending;
7306 intel_disable_fbc(dev);
7307 intel_mark_fb_busy(obj);
7308 mutex_unlock(&dev->struct_mutex);
7310 trace_i915_flip_request(intel_crtc->plane, obj);
7315 atomic_dec(&intel_crtc->unpin_work_count);
7317 drm_gem_object_unreference(&work->old_fb_obj->base);
7318 drm_gem_object_unreference(&obj->base);
7319 mutex_unlock(&dev->struct_mutex);
7322 spin_lock_irqsave(&dev->event_lock, flags);
7323 intel_crtc->unpin_work = NULL;
7324 spin_unlock_irqrestore(&dev->event_lock, flags);
7326 drm_vblank_put(dev, intel_crtc->pipe);
7333 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7334 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7335 .load_lut = intel_crtc_load_lut,
7338 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7340 struct intel_encoder *other_encoder;
7341 struct drm_crtc *crtc = &encoder->new_crtc->base;
7346 list_for_each_entry(other_encoder,
7347 &crtc->dev->mode_config.encoder_list,
7350 if (&other_encoder->new_crtc->base != crtc ||
7351 encoder == other_encoder)
7360 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7361 struct drm_crtc *crtc)
7363 struct drm_device *dev;
7364 struct drm_crtc *tmp;
7367 WARN(!crtc, "checking null crtc?\n");
7371 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7377 if (encoder->possible_crtcs & crtc_mask)
7383 * intel_modeset_update_staged_output_state
7385 * Updates the staged output configuration state, e.g. after we've read out the
7388 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7390 struct intel_encoder *encoder;
7391 struct intel_connector *connector;
7393 list_for_each_entry(connector, &dev->mode_config.connector_list,
7395 connector->new_encoder =
7396 to_intel_encoder(connector->base.encoder);
7399 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7402 to_intel_crtc(encoder->base.crtc);
7407 * intel_modeset_commit_output_state
7409 * This function copies the stage display pipe configuration to the real one.
7411 static void intel_modeset_commit_output_state(struct drm_device *dev)
7413 struct intel_encoder *encoder;
7414 struct intel_connector *connector;
7416 list_for_each_entry(connector, &dev->mode_config.connector_list,
7418 connector->base.encoder = &connector->new_encoder->base;
7421 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7423 encoder->base.crtc = &encoder->new_crtc->base;
7428 pipe_config_set_bpp(struct drm_crtc *crtc,
7429 struct drm_framebuffer *fb,
7430 struct intel_crtc_config *pipe_config)
7432 struct drm_device *dev = crtc->dev;
7433 struct drm_connector *connector;
7436 switch (fb->pixel_format) {
7438 bpp = 8*3; /* since we go through a colormap */
7440 case DRM_FORMAT_XRGB1555:
7441 case DRM_FORMAT_ARGB1555:
7442 /* checked in intel_framebuffer_init already */
7443 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7445 case DRM_FORMAT_RGB565:
7446 bpp = 6*3; /* min is 18bpp */
7448 case DRM_FORMAT_XBGR8888:
7449 case DRM_FORMAT_ABGR8888:
7450 /* checked in intel_framebuffer_init already */
7451 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7453 case DRM_FORMAT_XRGB8888:
7454 case DRM_FORMAT_ARGB8888:
7457 case DRM_FORMAT_XRGB2101010:
7458 case DRM_FORMAT_ARGB2101010:
7459 case DRM_FORMAT_XBGR2101010:
7460 case DRM_FORMAT_ABGR2101010:
7461 /* checked in intel_framebuffer_init already */
7462 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7466 /* TODO: gen4+ supports 16 bpc floating point, too. */
7468 DRM_DEBUG_KMS("unsupported depth\n");
7472 pipe_config->pipe_bpp = bpp;
7474 /* Clamp display bpp to EDID value */
7475 list_for_each_entry(connector, &dev->mode_config.connector_list,
7477 if (connector->encoder && connector->encoder->crtc != crtc)
7480 /* Don't use an invalid EDID bpc value */
7481 if (connector->display_info.bpc &&
7482 connector->display_info.bpc * 3 < bpp) {
7483 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7484 bpp, connector->display_info.bpc*3);
7485 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7492 static struct intel_crtc_config *
7493 intel_modeset_pipe_config(struct drm_crtc *crtc,
7494 struct drm_framebuffer *fb,
7495 struct drm_display_mode *mode)
7497 struct drm_device *dev = crtc->dev;
7498 struct drm_encoder_helper_funcs *encoder_funcs;
7499 struct intel_encoder *encoder;
7500 struct intel_crtc_config *pipe_config;
7503 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7505 return ERR_PTR(-ENOMEM);
7507 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7508 drm_mode_copy(&pipe_config->requested_mode, mode);
7510 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7514 /* Pass our mode to the connectors and the CRTC to give them a chance to
7515 * adjust it according to limitations or connector properties, and also
7516 * a chance to reject the mode entirely.
7518 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7521 if (&encoder->new_crtc->base != crtc)
7524 if (encoder->compute_config) {
7525 if (!(encoder->compute_config(encoder, pipe_config))) {
7526 DRM_DEBUG_KMS("Encoder config failure\n");
7533 encoder_funcs = encoder->base.helper_private;
7534 if (!(encoder_funcs->mode_fixup(&encoder->base,
7535 &pipe_config->requested_mode,
7536 &pipe_config->adjusted_mode))) {
7537 DRM_DEBUG_KMS("Encoder fixup failed\n");
7542 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7543 DRM_DEBUG_KMS("CRTC fixup failed\n");
7546 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7548 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7549 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7550 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7555 return ERR_PTR(-EINVAL);
7558 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7559 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7561 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7562 unsigned *prepare_pipes, unsigned *disable_pipes)
7564 struct intel_crtc *intel_crtc;
7565 struct drm_device *dev = crtc->dev;
7566 struct intel_encoder *encoder;
7567 struct intel_connector *connector;
7568 struct drm_crtc *tmp_crtc;
7570 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7572 /* Check which crtcs have changed outputs connected to them, these need
7573 * to be part of the prepare_pipes mask. We don't (yet) support global
7574 * modeset across multiple crtcs, so modeset_pipes will only have one
7575 * bit set at most. */
7576 list_for_each_entry(connector, &dev->mode_config.connector_list,
7578 if (connector->base.encoder == &connector->new_encoder->base)
7581 if (connector->base.encoder) {
7582 tmp_crtc = connector->base.encoder->crtc;
7584 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7587 if (connector->new_encoder)
7589 1 << connector->new_encoder->new_crtc->pipe;
7592 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7594 if (encoder->base.crtc == &encoder->new_crtc->base)
7597 if (encoder->base.crtc) {
7598 tmp_crtc = encoder->base.crtc;
7600 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7603 if (encoder->new_crtc)
7604 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7607 /* Check for any pipes that will be fully disabled ... */
7608 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7612 /* Don't try to disable disabled crtcs. */
7613 if (!intel_crtc->base.enabled)
7616 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7618 if (encoder->new_crtc == intel_crtc)
7623 *disable_pipes |= 1 << intel_crtc->pipe;
7627 /* set_mode is also used to update properties on life display pipes. */
7628 intel_crtc = to_intel_crtc(crtc);
7630 *prepare_pipes |= 1 << intel_crtc->pipe;
7632 /* We only support modeset on one single crtc, hence we need to do that
7633 * only for the passed in crtc iff we change anything else than just
7636 * This is actually not true, to be fully compatible with the old crtc
7637 * helper we automatically disable _any_ output (i.e. doesn't need to be
7638 * connected to the crtc we're modesetting on) if it's disconnected.
7639 * Which is a rather nutty api (since changed the output configuration
7640 * without userspace's explicit request can lead to confusion), but
7641 * alas. Hence we currently need to modeset on all pipes we prepare. */
7643 *modeset_pipes = *prepare_pipes;
7645 /* ... and mask these out. */
7646 *modeset_pipes &= ~(*disable_pipes);
7647 *prepare_pipes &= ~(*disable_pipes);
7650 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7652 struct drm_encoder *encoder;
7653 struct drm_device *dev = crtc->dev;
7655 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7656 if (encoder->crtc == crtc)
7663 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7665 struct intel_encoder *intel_encoder;
7666 struct intel_crtc *intel_crtc;
7667 struct drm_connector *connector;
7669 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7671 if (!intel_encoder->base.crtc)
7674 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7676 if (prepare_pipes & (1 << intel_crtc->pipe))
7677 intel_encoder->connectors_active = false;
7680 intel_modeset_commit_output_state(dev);
7682 /* Update computed state. */
7683 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7685 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7688 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7689 if (!connector->encoder || !connector->encoder->crtc)
7692 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7694 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7695 struct drm_property *dpms_property =
7696 dev->mode_config.dpms_property;
7698 connector->dpms = DRM_MODE_DPMS_ON;
7699 drm_object_property_set_value(&connector->base,
7703 intel_encoder = to_intel_encoder(connector->encoder);
7704 intel_encoder->connectors_active = true;
7710 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7711 list_for_each_entry((intel_crtc), \
7712 &(dev)->mode_config.crtc_list, \
7714 if (mask & (1 <<(intel_crtc)->pipe)) \
7717 intel_modeset_check_state(struct drm_device *dev)
7719 struct intel_crtc *crtc;
7720 struct intel_encoder *encoder;
7721 struct intel_connector *connector;
7723 list_for_each_entry(connector, &dev->mode_config.connector_list,
7725 /* This also checks the encoder/connector hw state with the
7726 * ->get_hw_state callbacks. */
7727 intel_connector_check_state(connector);
7729 WARN(&connector->new_encoder->base != connector->base.encoder,
7730 "connector's staged encoder doesn't match current encoder\n");
7733 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7735 bool enabled = false;
7736 bool active = false;
7737 enum pipe pipe, tracked_pipe;
7739 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7740 encoder->base.base.id,
7741 drm_get_encoder_name(&encoder->base));
7743 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7744 "encoder's stage crtc doesn't match current crtc\n");
7745 WARN(encoder->connectors_active && !encoder->base.crtc,
7746 "encoder's active_connectors set, but no crtc\n");
7748 list_for_each_entry(connector, &dev->mode_config.connector_list,
7750 if (connector->base.encoder != &encoder->base)
7753 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7756 WARN(!!encoder->base.crtc != enabled,
7757 "encoder's enabled state mismatch "
7758 "(expected %i, found %i)\n",
7759 !!encoder->base.crtc, enabled);
7760 WARN(active && !encoder->base.crtc,
7761 "active encoder with no crtc\n");
7763 WARN(encoder->connectors_active != active,
7764 "encoder's computed active state doesn't match tracked active state "
7765 "(expected %i, found %i)\n", active, encoder->connectors_active);
7767 active = encoder->get_hw_state(encoder, &pipe);
7768 WARN(active != encoder->connectors_active,
7769 "encoder's hw state doesn't match sw tracking "
7770 "(expected %i, found %i)\n",
7771 encoder->connectors_active, active);
7773 if (!encoder->base.crtc)
7776 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7777 WARN(active && pipe != tracked_pipe,
7778 "active encoder's pipe doesn't match"
7779 "(expected %i, found %i)\n",
7780 tracked_pipe, pipe);
7784 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7786 bool enabled = false;
7787 bool active = false;
7789 DRM_DEBUG_KMS("[CRTC:%d]\n",
7790 crtc->base.base.id);
7792 WARN(crtc->active && !crtc->base.enabled,
7793 "active crtc, but not enabled in sw tracking\n");
7795 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7797 if (encoder->base.crtc != &crtc->base)
7800 if (encoder->connectors_active)
7803 WARN(active != crtc->active,
7804 "crtc's computed active state doesn't match tracked active state "
7805 "(expected %i, found %i)\n", active, crtc->active);
7806 WARN(enabled != crtc->base.enabled,
7807 "crtc's computed enabled state doesn't match tracked enabled state "
7808 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7810 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7814 int intel_set_mode(struct drm_crtc *crtc,
7815 struct drm_display_mode *mode,
7816 int x, int y, struct drm_framebuffer *fb)
7818 struct drm_device *dev = crtc->dev;
7819 drm_i915_private_t *dev_priv = dev->dev_private;
7820 struct drm_display_mode *saved_mode, *saved_hwmode;
7821 struct intel_crtc_config *pipe_config = NULL;
7822 struct intel_crtc *intel_crtc;
7823 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7826 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7829 saved_hwmode = saved_mode + 1;
7831 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7832 &prepare_pipes, &disable_pipes);
7834 *saved_hwmode = crtc->hwmode;
7835 *saved_mode = crtc->mode;
7837 /* Hack: Because we don't (yet) support global modeset on multiple
7838 * crtcs, we don't keep track of the new mode for more than one crtc.
7839 * Hence simply check whether any bit is set in modeset_pipes in all the
7840 * pieces of code that are not yet converted to deal with mutliple crtcs
7841 * changing their mode at the same time. */
7842 if (modeset_pipes) {
7843 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
7844 if (IS_ERR(pipe_config)) {
7845 ret = PTR_ERR(pipe_config);
7852 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7853 modeset_pipes, prepare_pipes, disable_pipes);
7855 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7856 intel_crtc_disable(&intel_crtc->base);
7858 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7859 if (intel_crtc->base.enabled)
7860 dev_priv->display.crtc_disable(&intel_crtc->base);
7863 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7864 * to set it here already despite that we pass it down the callchain.
7866 if (modeset_pipes) {
7868 /* mode_set/enable/disable functions rely on a correct pipe
7870 to_intel_crtc(crtc)->config = *pipe_config;
7873 /* Only after disabling all output pipelines that will be changed can we
7874 * update the the output configuration. */
7875 intel_modeset_update_state(dev, prepare_pipes);
7877 if (dev_priv->display.modeset_global_resources)
7878 dev_priv->display.modeset_global_resources(dev);
7880 /* Set up the DPLL and any encoders state that needs to adjust or depend
7883 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7884 ret = intel_crtc_mode_set(&intel_crtc->base,
7890 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7891 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7892 dev_priv->display.crtc_enable(&intel_crtc->base);
7894 if (modeset_pipes) {
7895 /* Store real post-adjustment hardware mode. */
7896 crtc->hwmode = pipe_config->adjusted_mode;
7898 /* Calculate and store various constants which
7899 * are later needed by vblank and swap-completion
7900 * timestamping. They are derived from true hwmode.
7902 drm_calc_timestamping_constants(crtc);
7905 /* FIXME: add subpixel order */
7907 if (ret && crtc->enabled) {
7908 crtc->hwmode = *saved_hwmode;
7909 crtc->mode = *saved_mode;
7911 intel_modeset_check_state(dev);
7920 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7922 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7925 #undef for_each_intel_crtc_masked
7927 static void intel_set_config_free(struct intel_set_config *config)
7932 kfree(config->save_connector_encoders);
7933 kfree(config->save_encoder_crtcs);
7937 static int intel_set_config_save_state(struct drm_device *dev,
7938 struct intel_set_config *config)
7940 struct drm_encoder *encoder;
7941 struct drm_connector *connector;
7944 config->save_encoder_crtcs =
7945 kcalloc(dev->mode_config.num_encoder,
7946 sizeof(struct drm_crtc *), GFP_KERNEL);
7947 if (!config->save_encoder_crtcs)
7950 config->save_connector_encoders =
7951 kcalloc(dev->mode_config.num_connector,
7952 sizeof(struct drm_encoder *), GFP_KERNEL);
7953 if (!config->save_connector_encoders)
7956 /* Copy data. Note that driver private data is not affected.
7957 * Should anything bad happen only the expected state is
7958 * restored, not the drivers personal bookkeeping.
7961 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7962 config->save_encoder_crtcs[count++] = encoder->crtc;
7966 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7967 config->save_connector_encoders[count++] = connector->encoder;
7973 static void intel_set_config_restore_state(struct drm_device *dev,
7974 struct intel_set_config *config)
7976 struct intel_encoder *encoder;
7977 struct intel_connector *connector;
7981 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7983 to_intel_crtc(config->save_encoder_crtcs[count++]);
7987 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7988 connector->new_encoder =
7989 to_intel_encoder(config->save_connector_encoders[count++]);
7994 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7995 struct intel_set_config *config)
7998 /* We should be able to check here if the fb has the same properties
7999 * and then just flip_or_move it */
8000 if (set->crtc->fb != set->fb) {
8001 /* If we have no fb then treat it as a full mode set */
8002 if (set->crtc->fb == NULL) {
8003 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8004 config->mode_changed = true;
8005 } else if (set->fb == NULL) {
8006 config->mode_changed = true;
8007 } else if (set->fb->pixel_format !=
8008 set->crtc->fb->pixel_format) {
8009 config->mode_changed = true;
8011 config->fb_changed = true;
8014 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8015 config->fb_changed = true;
8017 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8018 DRM_DEBUG_KMS("modes are different, full mode set\n");
8019 drm_mode_debug_printmodeline(&set->crtc->mode);
8020 drm_mode_debug_printmodeline(set->mode);
8021 config->mode_changed = true;
8026 intel_modeset_stage_output_state(struct drm_device *dev,
8027 struct drm_mode_set *set,
8028 struct intel_set_config *config)
8030 struct drm_crtc *new_crtc;
8031 struct intel_connector *connector;
8032 struct intel_encoder *encoder;
8035 /* The upper layers ensure that we either disable a crtc or have a list
8036 * of connectors. For paranoia, double-check this. */
8037 WARN_ON(!set->fb && (set->num_connectors != 0));
8038 WARN_ON(set->fb && (set->num_connectors == 0));
8041 list_for_each_entry(connector, &dev->mode_config.connector_list,
8043 /* Otherwise traverse passed in connector list and get encoders
8045 for (ro = 0; ro < set->num_connectors; ro++) {
8046 if (set->connectors[ro] == &connector->base) {
8047 connector->new_encoder = connector->encoder;
8052 /* If we disable the crtc, disable all its connectors. Also, if
8053 * the connector is on the changing crtc but not on the new
8054 * connector list, disable it. */
8055 if ((!set->fb || ro == set->num_connectors) &&
8056 connector->base.encoder &&
8057 connector->base.encoder->crtc == set->crtc) {
8058 connector->new_encoder = NULL;
8060 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8061 connector->base.base.id,
8062 drm_get_connector_name(&connector->base));
8066 if (&connector->new_encoder->base != connector->base.encoder) {
8067 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8068 config->mode_changed = true;
8071 /* connector->new_encoder is now updated for all connectors. */
8073 /* Update crtc of enabled connectors. */
8075 list_for_each_entry(connector, &dev->mode_config.connector_list,
8077 if (!connector->new_encoder)
8080 new_crtc = connector->new_encoder->base.crtc;
8082 for (ro = 0; ro < set->num_connectors; ro++) {
8083 if (set->connectors[ro] == &connector->base)
8084 new_crtc = set->crtc;
8087 /* Make sure the new CRTC will work with the encoder */
8088 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8092 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8094 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8095 connector->base.base.id,
8096 drm_get_connector_name(&connector->base),
8100 /* Check for any encoders that needs to be disabled. */
8101 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8103 list_for_each_entry(connector,
8104 &dev->mode_config.connector_list,
8106 if (connector->new_encoder == encoder) {
8107 WARN_ON(!connector->new_encoder->new_crtc);
8112 encoder->new_crtc = NULL;
8114 /* Only now check for crtc changes so we don't miss encoders
8115 * that will be disabled. */
8116 if (&encoder->new_crtc->base != encoder->base.crtc) {
8117 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8118 config->mode_changed = true;
8121 /* Now we've also updated encoder->new_crtc for all encoders. */
8126 static int intel_crtc_set_config(struct drm_mode_set *set)
8128 struct drm_device *dev;
8129 struct drm_mode_set save_set;
8130 struct intel_set_config *config;
8135 BUG_ON(!set->crtc->helper_private);
8137 /* Enforce sane interface api - has been abused by the fb helper. */
8138 BUG_ON(!set->mode && set->fb);
8139 BUG_ON(set->fb && set->num_connectors == 0);
8142 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8143 set->crtc->base.id, set->fb->base.id,
8144 (int)set->num_connectors, set->x, set->y);
8146 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8149 dev = set->crtc->dev;
8152 config = kzalloc(sizeof(*config), GFP_KERNEL);
8156 ret = intel_set_config_save_state(dev, config);
8160 save_set.crtc = set->crtc;
8161 save_set.mode = &set->crtc->mode;
8162 save_set.x = set->crtc->x;
8163 save_set.y = set->crtc->y;
8164 save_set.fb = set->crtc->fb;
8166 /* Compute whether we need a full modeset, only an fb base update or no
8167 * change at all. In the future we might also check whether only the
8168 * mode changed, e.g. for LVDS where we only change the panel fitter in
8170 intel_set_config_compute_mode_changes(set, config);
8172 ret = intel_modeset_stage_output_state(dev, set, config);
8176 if (config->mode_changed) {
8178 DRM_DEBUG_KMS("attempting to set mode from"
8180 drm_mode_debug_printmodeline(set->mode);
8183 ret = intel_set_mode(set->crtc, set->mode,
8184 set->x, set->y, set->fb);
8186 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8187 set->crtc->base.id, ret);
8190 } else if (config->fb_changed) {
8191 intel_crtc_wait_for_pending_flips(set->crtc);
8193 ret = intel_pipe_set_base(set->crtc,
8194 set->x, set->y, set->fb);
8197 intel_set_config_free(config);
8202 intel_set_config_restore_state(dev, config);
8204 /* Try to restore the config */
8205 if (config->mode_changed &&
8206 intel_set_mode(save_set.crtc, save_set.mode,
8207 save_set.x, save_set.y, save_set.fb))
8208 DRM_ERROR("failed to restore config after modeset failure\n");
8211 intel_set_config_free(config);
8215 static const struct drm_crtc_funcs intel_crtc_funcs = {
8216 .cursor_set = intel_crtc_cursor_set,
8217 .cursor_move = intel_crtc_cursor_move,
8218 .gamma_set = intel_crtc_gamma_set,
8219 .set_config = intel_crtc_set_config,
8220 .destroy = intel_crtc_destroy,
8221 .page_flip = intel_crtc_page_flip,
8224 static void intel_cpu_pll_init(struct drm_device *dev)
8227 intel_ddi_pll_init(dev);
8230 static void intel_pch_pll_init(struct drm_device *dev)
8232 drm_i915_private_t *dev_priv = dev->dev_private;
8235 if (dev_priv->num_pch_pll == 0) {
8236 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8240 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8241 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8242 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8243 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8247 static void intel_crtc_init(struct drm_device *dev, int pipe)
8249 drm_i915_private_t *dev_priv = dev->dev_private;
8250 struct intel_crtc *intel_crtc;
8253 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8254 if (intel_crtc == NULL)
8257 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8259 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8260 for (i = 0; i < 256; i++) {
8261 intel_crtc->lut_r[i] = i;
8262 intel_crtc->lut_g[i] = i;
8263 intel_crtc->lut_b[i] = i;
8266 /* Swap pipes & planes for FBC on pre-965 */
8267 intel_crtc->pipe = pipe;
8268 intel_crtc->plane = pipe;
8269 intel_crtc->cpu_transcoder = pipe;
8270 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8271 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8272 intel_crtc->plane = !pipe;
8275 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8276 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8277 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8278 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8280 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8283 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8284 struct drm_file *file)
8286 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8287 struct drm_mode_object *drmmode_obj;
8288 struct intel_crtc *crtc;
8290 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8293 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8294 DRM_MODE_OBJECT_CRTC);
8297 DRM_ERROR("no such CRTC id\n");
8301 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8302 pipe_from_crtc_id->pipe = crtc->pipe;
8307 static int intel_encoder_clones(struct intel_encoder *encoder)
8309 struct drm_device *dev = encoder->base.dev;
8310 struct intel_encoder *source_encoder;
8314 list_for_each_entry(source_encoder,
8315 &dev->mode_config.encoder_list, base.head) {
8317 if (encoder == source_encoder)
8318 index_mask |= (1 << entry);
8320 /* Intel hw has only one MUX where enocoders could be cloned. */
8321 if (encoder->cloneable && source_encoder->cloneable)
8322 index_mask |= (1 << entry);
8330 static bool has_edp_a(struct drm_device *dev)
8332 struct drm_i915_private *dev_priv = dev->dev_private;
8334 if (!IS_MOBILE(dev))
8337 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8341 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8347 static void intel_setup_outputs(struct drm_device *dev)
8349 struct drm_i915_private *dev_priv = dev->dev_private;
8350 struct intel_encoder *encoder;
8351 bool dpd_is_edp = false;
8354 has_lvds = intel_lvds_init(dev);
8355 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8356 /* disable the panel fitter on everything but LVDS */
8357 I915_WRITE(PFIT_CONTROL, 0);
8360 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8361 intel_crt_init(dev);
8366 /* Haswell uses DDI functions to detect digital outputs */
8367 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8368 /* DDI A only supports eDP */
8370 intel_ddi_init(dev, PORT_A);
8372 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8374 found = I915_READ(SFUSE_STRAP);
8376 if (found & SFUSE_STRAP_DDIB_DETECTED)
8377 intel_ddi_init(dev, PORT_B);
8378 if (found & SFUSE_STRAP_DDIC_DETECTED)
8379 intel_ddi_init(dev, PORT_C);
8380 if (found & SFUSE_STRAP_DDID_DETECTED)
8381 intel_ddi_init(dev, PORT_D);
8382 } else if (HAS_PCH_SPLIT(dev)) {
8384 dpd_is_edp = intel_dpd_is_edp(dev);
8387 intel_dp_init(dev, DP_A, PORT_A);
8389 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8390 /* PCH SDVOB multiplex with HDMIB */
8391 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8393 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8394 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8395 intel_dp_init(dev, PCH_DP_B, PORT_B);
8398 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8399 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8401 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8402 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8404 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8405 intel_dp_init(dev, PCH_DP_C, PORT_C);
8407 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8408 intel_dp_init(dev, PCH_DP_D, PORT_D);
8409 } else if (IS_VALLEYVIEW(dev)) {
8410 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8411 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8412 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8414 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8415 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8417 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8418 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8420 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8423 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8424 DRM_DEBUG_KMS("probing SDVOB\n");
8425 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8426 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8427 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8428 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8431 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8432 DRM_DEBUG_KMS("probing DP_B\n");
8433 intel_dp_init(dev, DP_B, PORT_B);
8437 /* Before G4X SDVOC doesn't have its own detect register */
8439 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8440 DRM_DEBUG_KMS("probing SDVOC\n");
8441 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8444 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8446 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8447 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8448 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8450 if (SUPPORTS_INTEGRATED_DP(dev)) {
8451 DRM_DEBUG_KMS("probing DP_C\n");
8452 intel_dp_init(dev, DP_C, PORT_C);
8456 if (SUPPORTS_INTEGRATED_DP(dev) &&
8457 (I915_READ(DP_D) & DP_DETECTED)) {
8458 DRM_DEBUG_KMS("probing DP_D\n");
8459 intel_dp_init(dev, DP_D, PORT_D);
8461 } else if (IS_GEN2(dev))
8462 intel_dvo_init(dev);
8464 if (SUPPORTS_TV(dev))
8467 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8468 encoder->base.possible_crtcs = encoder->crtc_mask;
8469 encoder->base.possible_clones =
8470 intel_encoder_clones(encoder);
8473 intel_init_pch_refclk(dev);
8475 drm_helper_move_panel_connectors_to_head(dev);
8478 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8480 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8482 drm_framebuffer_cleanup(fb);
8483 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8488 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8489 struct drm_file *file,
8490 unsigned int *handle)
8492 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8493 struct drm_i915_gem_object *obj = intel_fb->obj;
8495 return drm_gem_handle_create(file, &obj->base, handle);
8498 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8499 .destroy = intel_user_framebuffer_destroy,
8500 .create_handle = intel_user_framebuffer_create_handle,
8503 int intel_framebuffer_init(struct drm_device *dev,
8504 struct intel_framebuffer *intel_fb,
8505 struct drm_mode_fb_cmd2 *mode_cmd,
8506 struct drm_i915_gem_object *obj)
8510 if (obj->tiling_mode == I915_TILING_Y) {
8511 DRM_DEBUG("hardware does not support tiling Y\n");
8515 if (mode_cmd->pitches[0] & 63) {
8516 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8517 mode_cmd->pitches[0]);
8521 /* FIXME <= Gen4 stride limits are bit unclear */
8522 if (mode_cmd->pitches[0] > 32768) {
8523 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8524 mode_cmd->pitches[0]);
8528 if (obj->tiling_mode != I915_TILING_NONE &&
8529 mode_cmd->pitches[0] != obj->stride) {
8530 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8531 mode_cmd->pitches[0], obj->stride);
8535 /* Reject formats not supported by any plane early. */
8536 switch (mode_cmd->pixel_format) {
8538 case DRM_FORMAT_RGB565:
8539 case DRM_FORMAT_XRGB8888:
8540 case DRM_FORMAT_ARGB8888:
8542 case DRM_FORMAT_XRGB1555:
8543 case DRM_FORMAT_ARGB1555:
8544 if (INTEL_INFO(dev)->gen > 3) {
8545 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8549 case DRM_FORMAT_XBGR8888:
8550 case DRM_FORMAT_ABGR8888:
8551 case DRM_FORMAT_XRGB2101010:
8552 case DRM_FORMAT_ARGB2101010:
8553 case DRM_FORMAT_XBGR2101010:
8554 case DRM_FORMAT_ABGR2101010:
8555 if (INTEL_INFO(dev)->gen < 4) {
8556 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8560 case DRM_FORMAT_YUYV:
8561 case DRM_FORMAT_UYVY:
8562 case DRM_FORMAT_YVYU:
8563 case DRM_FORMAT_VYUY:
8564 if (INTEL_INFO(dev)->gen < 5) {
8565 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8570 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8574 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8575 if (mode_cmd->offsets[0] != 0)
8578 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8579 intel_fb->obj = obj;
8581 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8583 DRM_ERROR("framebuffer init failed %d\n", ret);
8590 static struct drm_framebuffer *
8591 intel_user_framebuffer_create(struct drm_device *dev,
8592 struct drm_file *filp,
8593 struct drm_mode_fb_cmd2 *mode_cmd)
8595 struct drm_i915_gem_object *obj;
8597 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8598 mode_cmd->handles[0]));
8599 if (&obj->base == NULL)
8600 return ERR_PTR(-ENOENT);
8602 return intel_framebuffer_create(dev, mode_cmd, obj);
8605 static const struct drm_mode_config_funcs intel_mode_funcs = {
8606 .fb_create = intel_user_framebuffer_create,
8607 .output_poll_changed = intel_fb_output_poll_changed,
8610 /* Set up chip specific display functions */
8611 static void intel_init_display(struct drm_device *dev)
8613 struct drm_i915_private *dev_priv = dev->dev_private;
8616 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8617 dev_priv->display.crtc_enable = haswell_crtc_enable;
8618 dev_priv->display.crtc_disable = haswell_crtc_disable;
8619 dev_priv->display.off = haswell_crtc_off;
8620 dev_priv->display.update_plane = ironlake_update_plane;
8621 } else if (HAS_PCH_SPLIT(dev)) {
8622 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8623 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8624 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8625 dev_priv->display.off = ironlake_crtc_off;
8626 dev_priv->display.update_plane = ironlake_update_plane;
8628 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8629 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8630 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8631 dev_priv->display.off = i9xx_crtc_off;
8632 dev_priv->display.update_plane = i9xx_update_plane;
8635 /* Returns the core display clock speed */
8636 if (IS_VALLEYVIEW(dev))
8637 dev_priv->display.get_display_clock_speed =
8638 valleyview_get_display_clock_speed;
8639 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8640 dev_priv->display.get_display_clock_speed =
8641 i945_get_display_clock_speed;
8642 else if (IS_I915G(dev))
8643 dev_priv->display.get_display_clock_speed =
8644 i915_get_display_clock_speed;
8645 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8646 dev_priv->display.get_display_clock_speed =
8647 i9xx_misc_get_display_clock_speed;
8648 else if (IS_I915GM(dev))
8649 dev_priv->display.get_display_clock_speed =
8650 i915gm_get_display_clock_speed;
8651 else if (IS_I865G(dev))
8652 dev_priv->display.get_display_clock_speed =
8653 i865_get_display_clock_speed;
8654 else if (IS_I85X(dev))
8655 dev_priv->display.get_display_clock_speed =
8656 i855_get_display_clock_speed;
8658 dev_priv->display.get_display_clock_speed =
8659 i830_get_display_clock_speed;
8661 if (HAS_PCH_SPLIT(dev)) {
8663 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8664 dev_priv->display.write_eld = ironlake_write_eld;
8665 } else if (IS_GEN6(dev)) {
8666 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8667 dev_priv->display.write_eld = ironlake_write_eld;
8668 } else if (IS_IVYBRIDGE(dev)) {
8669 /* FIXME: detect B0+ stepping and use auto training */
8670 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8671 dev_priv->display.write_eld = ironlake_write_eld;
8672 dev_priv->display.modeset_global_resources =
8673 ivb_modeset_global_resources;
8674 } else if (IS_HASWELL(dev)) {
8675 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8676 dev_priv->display.write_eld = haswell_write_eld;
8677 dev_priv->display.modeset_global_resources =
8678 haswell_modeset_global_resources;
8680 } else if (IS_G4X(dev)) {
8681 dev_priv->display.write_eld = g4x_write_eld;
8684 /* Default just returns -ENODEV to indicate unsupported */
8685 dev_priv->display.queue_flip = intel_default_queue_flip;
8687 switch (INTEL_INFO(dev)->gen) {
8689 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8693 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8698 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8702 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8705 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8711 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8712 * resume, or other times. This quirk makes sure that's the case for
8715 static void quirk_pipea_force(struct drm_device *dev)
8717 struct drm_i915_private *dev_priv = dev->dev_private;
8719 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8720 DRM_INFO("applying pipe a force quirk\n");
8724 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8726 static void quirk_ssc_force_disable(struct drm_device *dev)
8728 struct drm_i915_private *dev_priv = dev->dev_private;
8729 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8730 DRM_INFO("applying lvds SSC disable quirk\n");
8734 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8737 static void quirk_invert_brightness(struct drm_device *dev)
8739 struct drm_i915_private *dev_priv = dev->dev_private;
8740 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8741 DRM_INFO("applying inverted panel brightness quirk\n");
8744 struct intel_quirk {
8746 int subsystem_vendor;
8747 int subsystem_device;
8748 void (*hook)(struct drm_device *dev);
8751 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8752 struct intel_dmi_quirk {
8753 void (*hook)(struct drm_device *dev);
8754 const struct dmi_system_id (*dmi_id_list)[];
8757 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8759 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8763 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8765 .dmi_id_list = &(const struct dmi_system_id[]) {
8767 .callback = intel_dmi_reverse_brightness,
8768 .ident = "NCR Corporation",
8769 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8770 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8773 { } /* terminating entry */
8775 .hook = quirk_invert_brightness,
8779 static struct intel_quirk intel_quirks[] = {
8780 /* HP Mini needs pipe A force quirk (LP: #322104) */
8781 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8783 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8784 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8786 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8787 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8789 /* 830/845 need to leave pipe A & dpll A up */
8790 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8791 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8793 /* Lenovo U160 cannot use SSC on LVDS */
8794 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8796 /* Sony Vaio Y cannot use SSC on LVDS */
8797 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8799 /* Acer Aspire 5734Z must invert backlight brightness */
8800 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8802 /* Acer/eMachines G725 */
8803 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8805 /* Acer/eMachines e725 */
8806 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8808 /* Acer/Packard Bell NCL20 */
8809 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8811 /* Acer Aspire 4736Z */
8812 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8815 static void intel_init_quirks(struct drm_device *dev)
8817 struct pci_dev *d = dev->pdev;
8820 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8821 struct intel_quirk *q = &intel_quirks[i];
8823 if (d->device == q->device &&
8824 (d->subsystem_vendor == q->subsystem_vendor ||
8825 q->subsystem_vendor == PCI_ANY_ID) &&
8826 (d->subsystem_device == q->subsystem_device ||
8827 q->subsystem_device == PCI_ANY_ID))
8830 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8831 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8832 intel_dmi_quirks[i].hook(dev);
8836 /* Disable the VGA plane that we never use */
8837 static void i915_disable_vga(struct drm_device *dev)
8839 struct drm_i915_private *dev_priv = dev->dev_private;
8841 u32 vga_reg = i915_vgacntrl_reg(dev);
8843 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8844 outb(SR01, VGA_SR_INDEX);
8845 sr1 = inb(VGA_SR_DATA);
8846 outb(sr1 | 1<<5, VGA_SR_DATA);
8847 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8850 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8851 POSTING_READ(vga_reg);
8854 void intel_modeset_init_hw(struct drm_device *dev)
8856 intel_init_power_well(dev);
8858 intel_prepare_ddi(dev);
8860 intel_init_clock_gating(dev);
8862 mutex_lock(&dev->struct_mutex);
8863 intel_enable_gt_powersave(dev);
8864 mutex_unlock(&dev->struct_mutex);
8867 void intel_modeset_init(struct drm_device *dev)
8869 struct drm_i915_private *dev_priv = dev->dev_private;
8872 drm_mode_config_init(dev);
8874 dev->mode_config.min_width = 0;
8875 dev->mode_config.min_height = 0;
8877 dev->mode_config.preferred_depth = 24;
8878 dev->mode_config.prefer_shadow = 1;
8880 dev->mode_config.funcs = &intel_mode_funcs;
8882 intel_init_quirks(dev);
8886 intel_init_display(dev);
8889 dev->mode_config.max_width = 2048;
8890 dev->mode_config.max_height = 2048;
8891 } else if (IS_GEN3(dev)) {
8892 dev->mode_config.max_width = 4096;
8893 dev->mode_config.max_height = 4096;
8895 dev->mode_config.max_width = 8192;
8896 dev->mode_config.max_height = 8192;
8898 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8900 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8901 INTEL_INFO(dev)->num_pipes,
8902 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
8904 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
8905 intel_crtc_init(dev, i);
8906 for (j = 0; j < dev_priv->num_plane; j++) {
8907 ret = intel_plane_init(dev, i, j);
8909 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
8914 intel_cpu_pll_init(dev);
8915 intel_pch_pll_init(dev);
8917 /* Just disable it once at startup */
8918 i915_disable_vga(dev);
8919 intel_setup_outputs(dev);
8921 /* Just in case the BIOS is doing something questionable. */
8922 intel_disable_fbc(dev);
8926 intel_connector_break_all_links(struct intel_connector *connector)
8928 connector->base.dpms = DRM_MODE_DPMS_OFF;
8929 connector->base.encoder = NULL;
8930 connector->encoder->connectors_active = false;
8931 connector->encoder->base.crtc = NULL;
8934 static void intel_enable_pipe_a(struct drm_device *dev)
8936 struct intel_connector *connector;
8937 struct drm_connector *crt = NULL;
8938 struct intel_load_detect_pipe load_detect_temp;
8940 /* We can't just switch on the pipe A, we need to set things up with a
8941 * proper mode and output configuration. As a gross hack, enable pipe A
8942 * by enabling the load detect pipe once. */
8943 list_for_each_entry(connector,
8944 &dev->mode_config.connector_list,
8946 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8947 crt = &connector->base;
8955 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8956 intel_release_load_detect_pipe(crt, &load_detect_temp);
8962 intel_check_plane_mapping(struct intel_crtc *crtc)
8964 struct drm_device *dev = crtc->base.dev;
8965 struct drm_i915_private *dev_priv = dev->dev_private;
8968 if (INTEL_INFO(dev)->num_pipes == 1)
8971 reg = DSPCNTR(!crtc->plane);
8972 val = I915_READ(reg);
8974 if ((val & DISPLAY_PLANE_ENABLE) &&
8975 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8981 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8983 struct drm_device *dev = crtc->base.dev;
8984 struct drm_i915_private *dev_priv = dev->dev_private;
8987 /* Clear any frame start delays used for debugging left by the BIOS */
8988 reg = PIPECONF(crtc->cpu_transcoder);
8989 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8991 /* We need to sanitize the plane -> pipe mapping first because this will
8992 * disable the crtc (and hence change the state) if it is wrong. Note
8993 * that gen4+ has a fixed plane -> pipe mapping. */
8994 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8995 struct intel_connector *connector;
8998 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8999 crtc->base.base.id);
9001 /* Pipe has the wrong plane attached and the plane is active.
9002 * Temporarily change the plane mapping and disable everything
9004 plane = crtc->plane;
9005 crtc->plane = !plane;
9006 dev_priv->display.crtc_disable(&crtc->base);
9007 crtc->plane = plane;
9009 /* ... and break all links. */
9010 list_for_each_entry(connector, &dev->mode_config.connector_list,
9012 if (connector->encoder->base.crtc != &crtc->base)
9015 intel_connector_break_all_links(connector);
9018 WARN_ON(crtc->active);
9019 crtc->base.enabled = false;
9022 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9023 crtc->pipe == PIPE_A && !crtc->active) {
9024 /* BIOS forgot to enable pipe A, this mostly happens after
9025 * resume. Force-enable the pipe to fix this, the update_dpms
9026 * call below we restore the pipe to the right state, but leave
9027 * the required bits on. */
9028 intel_enable_pipe_a(dev);
9031 /* Adjust the state of the output pipe according to whether we
9032 * have active connectors/encoders. */
9033 intel_crtc_update_dpms(&crtc->base);
9035 if (crtc->active != crtc->base.enabled) {
9036 struct intel_encoder *encoder;
9038 /* This can happen either due to bugs in the get_hw_state
9039 * functions or because the pipe is force-enabled due to the
9041 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9043 crtc->base.enabled ? "enabled" : "disabled",
9044 crtc->active ? "enabled" : "disabled");
9046 crtc->base.enabled = crtc->active;
9048 /* Because we only establish the connector -> encoder ->
9049 * crtc links if something is active, this means the
9050 * crtc is now deactivated. Break the links. connector
9051 * -> encoder links are only establish when things are
9052 * actually up, hence no need to break them. */
9053 WARN_ON(crtc->active);
9055 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9056 WARN_ON(encoder->connectors_active);
9057 encoder->base.crtc = NULL;
9062 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9064 struct intel_connector *connector;
9065 struct drm_device *dev = encoder->base.dev;
9067 /* We need to check both for a crtc link (meaning that the
9068 * encoder is active and trying to read from a pipe) and the
9069 * pipe itself being active. */
9070 bool has_active_crtc = encoder->base.crtc &&
9071 to_intel_crtc(encoder->base.crtc)->active;
9073 if (encoder->connectors_active && !has_active_crtc) {
9074 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9075 encoder->base.base.id,
9076 drm_get_encoder_name(&encoder->base));
9078 /* Connector is active, but has no active pipe. This is
9079 * fallout from our resume register restoring. Disable
9080 * the encoder manually again. */
9081 if (encoder->base.crtc) {
9082 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9083 encoder->base.base.id,
9084 drm_get_encoder_name(&encoder->base));
9085 encoder->disable(encoder);
9088 /* Inconsistent output/port/pipe state happens presumably due to
9089 * a bug in one of the get_hw_state functions. Or someplace else
9090 * in our code, like the register restore mess on resume. Clamp
9091 * things to off as a safer default. */
9092 list_for_each_entry(connector,
9093 &dev->mode_config.connector_list,
9095 if (connector->encoder != encoder)
9098 intel_connector_break_all_links(connector);
9101 /* Enabled encoders without active connectors will be fixed in
9102 * the crtc fixup. */
9105 void i915_redisable_vga(struct drm_device *dev)
9107 struct drm_i915_private *dev_priv = dev->dev_private;
9108 u32 vga_reg = i915_vgacntrl_reg(dev);
9110 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9111 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9112 i915_disable_vga(dev);
9116 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9117 * and i915 state tracking structures. */
9118 void intel_modeset_setup_hw_state(struct drm_device *dev,
9121 struct drm_i915_private *dev_priv = dev->dev_private;
9124 struct drm_plane *plane;
9125 struct intel_crtc *crtc;
9126 struct intel_encoder *encoder;
9127 struct intel_connector *connector;
9130 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9132 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9133 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9134 case TRANS_DDI_EDP_INPUT_A_ON:
9135 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9138 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9141 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9145 /* A bogus value has been programmed, disable
9147 WARN(1, "Bogus eDP source %08x\n", tmp);
9148 intel_ddi_disable_transcoder_func(dev_priv,
9153 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9154 crtc->cpu_transcoder = TRANSCODER_EDP;
9156 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9162 for_each_pipe(pipe) {
9163 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9165 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9166 if (tmp & PIPECONF_ENABLE)
9167 crtc->active = true;
9169 crtc->active = false;
9171 crtc->base.enabled = crtc->active;
9173 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9175 crtc->active ? "enabled" : "disabled");
9179 intel_ddi_setup_hw_pll_state(dev);
9181 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9185 if (encoder->get_hw_state(encoder, &pipe)) {
9186 encoder->base.crtc =
9187 dev_priv->pipe_to_crtc_mapping[pipe];
9189 encoder->base.crtc = NULL;
9192 encoder->connectors_active = false;
9193 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9194 encoder->base.base.id,
9195 drm_get_encoder_name(&encoder->base),
9196 encoder->base.crtc ? "enabled" : "disabled",
9200 list_for_each_entry(connector, &dev->mode_config.connector_list,
9202 if (connector->get_hw_state(connector)) {
9203 connector->base.dpms = DRM_MODE_DPMS_ON;
9204 connector->encoder->connectors_active = true;
9205 connector->base.encoder = &connector->encoder->base;
9207 connector->base.dpms = DRM_MODE_DPMS_OFF;
9208 connector->base.encoder = NULL;
9210 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9211 connector->base.base.id,
9212 drm_get_connector_name(&connector->base),
9213 connector->base.encoder ? "enabled" : "disabled");
9216 /* HW state is read out, now we need to sanitize this mess. */
9217 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9219 intel_sanitize_encoder(encoder);
9222 for_each_pipe(pipe) {
9223 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9224 intel_sanitize_crtc(crtc);
9227 if (force_restore) {
9228 for_each_pipe(pipe) {
9229 struct drm_crtc *crtc =
9230 dev_priv->pipe_to_crtc_mapping[pipe];
9231 intel_crtc_restore_mode(crtc);
9233 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9234 intel_plane_restore(plane);
9236 i915_redisable_vga(dev);
9238 intel_modeset_update_staged_output_state(dev);
9241 intel_modeset_check_state(dev);
9243 drm_mode_config_reset(dev);
9246 void intel_modeset_gem_init(struct drm_device *dev)
9248 intel_modeset_init_hw(dev);
9250 intel_setup_overlay(dev);
9252 intel_modeset_setup_hw_state(dev, false);
9255 void intel_modeset_cleanup(struct drm_device *dev)
9257 struct drm_i915_private *dev_priv = dev->dev_private;
9258 struct drm_crtc *crtc;
9259 struct intel_crtc *intel_crtc;
9261 drm_kms_helper_poll_fini(dev);
9262 mutex_lock(&dev->struct_mutex);
9264 intel_unregister_dsm_handler();
9267 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9268 /* Skip inactive CRTCs */
9272 intel_crtc = to_intel_crtc(crtc);
9273 intel_increase_pllclock(crtc);
9276 intel_disable_fbc(dev);
9278 intel_disable_gt_powersave(dev);
9280 ironlake_teardown_rc6(dev);
9282 if (IS_VALLEYVIEW(dev))
9285 mutex_unlock(&dev->struct_mutex);
9287 /* Disable the irq before mode object teardown, for the irq might
9288 * enqueue unpin/hotplug work. */
9289 drm_irq_uninstall(dev);
9290 cancel_work_sync(&dev_priv->hotplug_work);
9291 cancel_work_sync(&dev_priv->rps.work);
9293 /* flush any delayed tasks or pending work */
9294 flush_scheduled_work();
9296 drm_mode_config_cleanup(dev);
9298 intel_cleanup_overlay(dev);
9302 * Return which encoder is currently attached for connector.
9304 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9306 return &intel_attached_encoder(connector)->base;
9309 void intel_connector_attach_encoder(struct intel_connector *connector,
9310 struct intel_encoder *encoder)
9312 connector->encoder = encoder;
9313 drm_mode_connector_attach_encoder(&connector->base,
9318 * set vga decode state - true == enable VGA decode
9320 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9322 struct drm_i915_private *dev_priv = dev->dev_private;
9325 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9327 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9329 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9330 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9334 #ifdef CONFIG_DEBUG_FS
9335 #include <linux/seq_file.h>
9337 struct intel_display_error_state {
9338 struct intel_cursor_error_state {
9343 } cursor[I915_MAX_PIPES];
9345 struct intel_pipe_error_state {
9355 } pipe[I915_MAX_PIPES];
9357 struct intel_plane_error_state {
9365 } plane[I915_MAX_PIPES];
9368 struct intel_display_error_state *
9369 intel_display_capture_error_state(struct drm_device *dev)
9371 drm_i915_private_t *dev_priv = dev->dev_private;
9372 struct intel_display_error_state *error;
9373 enum transcoder cpu_transcoder;
9376 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9381 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9383 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9384 error->cursor[i].control = I915_READ(CURCNTR(i));
9385 error->cursor[i].position = I915_READ(CURPOS(i));
9386 error->cursor[i].base = I915_READ(CURBASE(i));
9388 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9389 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9390 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9393 error->plane[i].control = I915_READ(DSPCNTR(i));
9394 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9395 if (INTEL_INFO(dev)->gen <= 3) {
9396 error->plane[i].size = I915_READ(DSPSIZE(i));
9397 error->plane[i].pos = I915_READ(DSPPOS(i));
9399 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9400 error->plane[i].addr = I915_READ(DSPADDR(i));
9401 if (INTEL_INFO(dev)->gen >= 4) {
9402 error->plane[i].surface = I915_READ(DSPSURF(i));
9403 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9406 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9407 error->pipe[i].source = I915_READ(PIPESRC(i));
9408 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9409 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9410 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9411 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9412 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9413 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9420 intel_display_print_error_state(struct seq_file *m,
9421 struct drm_device *dev,
9422 struct intel_display_error_state *error)
9426 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9428 seq_printf(m, "Pipe [%d]:\n", i);
9429 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9430 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9431 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9432 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9433 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9434 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9435 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9436 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9438 seq_printf(m, "Plane [%d]:\n", i);
9439 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9440 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9441 if (INTEL_INFO(dev)->gen <= 3) {
9442 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9443 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9445 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9446 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9447 if (INTEL_INFO(dev)->gen >= 4) {
9448 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9449 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9452 seq_printf(m, "Cursor [%d]:\n", i);
9453 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9454 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9455 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);