2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/reservation.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
45 #include <drm/i915_drm.h>
48 #include "i915_gem_clflush.h"
49 #include "i915_reset.h"
50 #include "i915_trace.h"
51 #include "intel_atomic_plane.h"
52 #include "intel_color.h"
53 #include "intel_cdclk.h"
54 #include "intel_crt.h"
55 #include "intel_ddi.h"
57 #include "intel_drv.h"
58 #include "intel_dsi.h"
59 #include "intel_dvo.h"
60 #include "intel_fbc.h"
61 #include "intel_fbdev.h"
62 #include "intel_frontbuffer.h"
63 #include "intel_hdcp.h"
64 #include "intel_hdmi.h"
65 #include "intel_lvds.h"
66 #include "intel_pipe_crc.h"
68 #include "intel_psr.h"
69 #include "intel_sdvo.h"
70 #include "intel_sprite.h"
73 /* Primary plane formats for gen <= 3 */
74 static const u32 i8xx_primary_formats[] = {
81 /* Primary plane formats for gen >= 4 */
82 static const u32 i965_primary_formats[] = {
87 DRM_FORMAT_XRGB2101010,
88 DRM_FORMAT_XBGR2101010,
91 static const u64 i9xx_format_modifiers[] = {
92 I915_FORMAT_MOD_X_TILED,
93 DRM_FORMAT_MOD_LINEAR,
94 DRM_FORMAT_MOD_INVALID
98 static const u32 intel_cursor_formats[] = {
102 static const u64 cursor_format_modifiers[] = {
103 DRM_FORMAT_MOD_LINEAR,
104 DRM_FORMAT_MOD_INVALID
107 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
108 struct intel_crtc_state *pipe_config);
109 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
110 struct intel_crtc_state *pipe_config);
112 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
113 struct drm_i915_gem_object *obj,
114 struct drm_mode_fb_cmd2 *mode_cmd);
115 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
116 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
117 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
118 const struct intel_link_m_n *m_n,
119 const struct intel_link_m_n *m2_n2);
120 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
121 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
122 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
123 static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state);
124 static void vlv_prepare_pll(struct intel_crtc *crtc,
125 const struct intel_crtc_state *pipe_config);
126 static void chv_prepare_pll(struct intel_crtc *crtc,
127 const struct intel_crtc_state *pipe_config);
128 static void intel_begin_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
129 static void intel_finish_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
130 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
131 struct intel_crtc_state *crtc_state);
132 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
133 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
134 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
135 static void intel_modeset_setup_hw_state(struct drm_device *dev,
136 struct drm_modeset_acquire_ctx *ctx);
137 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
142 } dot, vco, n, m, m1, m2, p, p1;
146 int p2_slow, p2_fast;
150 /* returns HPLL frequency in kHz */
151 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
153 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
155 /* Obtain SKU information */
156 mutex_lock(&dev_priv->sb_lock);
157 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
158 CCK_FUSE_HPLL_FREQ_MASK;
159 mutex_unlock(&dev_priv->sb_lock);
161 return vco_freq[hpll_freq] * 1000;
164 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
165 const char *name, u32 reg, int ref_freq)
170 mutex_lock(&dev_priv->sb_lock);
171 val = vlv_cck_read(dev_priv, reg);
172 mutex_unlock(&dev_priv->sb_lock);
174 divider = val & CCK_FREQUENCY_VALUES;
176 WARN((val & CCK_FREQUENCY_STATUS) !=
177 (divider << CCK_FREQUENCY_STATUS_SHIFT),
178 "%s change in progress\n", name);
180 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
183 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
184 const char *name, u32 reg)
186 if (dev_priv->hpll_freq == 0)
187 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
189 return vlv_get_cck_clock(dev_priv, name, reg,
190 dev_priv->hpll_freq);
193 static void intel_update_czclk(struct drm_i915_private *dev_priv)
195 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
198 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
199 CCK_CZ_CLOCK_CONTROL);
201 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
204 static inline u32 /* units of 100MHz */
205 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
206 const struct intel_crtc_state *pipe_config)
208 if (HAS_DDI(dev_priv))
209 return pipe_config->port_clock; /* SPLL */
211 return dev_priv->fdi_pll_freq;
214 static const struct intel_limit intel_limits_i8xx_dac = {
215 .dot = { .min = 25000, .max = 350000 },
216 .vco = { .min = 908000, .max = 1512000 },
217 .n = { .min = 2, .max = 16 },
218 .m = { .min = 96, .max = 140 },
219 .m1 = { .min = 18, .max = 26 },
220 .m2 = { .min = 6, .max = 16 },
221 .p = { .min = 4, .max = 128 },
222 .p1 = { .min = 2, .max = 33 },
223 .p2 = { .dot_limit = 165000,
224 .p2_slow = 4, .p2_fast = 2 },
227 static const struct intel_limit intel_limits_i8xx_dvo = {
228 .dot = { .min = 25000, .max = 350000 },
229 .vco = { .min = 908000, .max = 1512000 },
230 .n = { .min = 2, .max = 16 },
231 .m = { .min = 96, .max = 140 },
232 .m1 = { .min = 18, .max = 26 },
233 .m2 = { .min = 6, .max = 16 },
234 .p = { .min = 4, .max = 128 },
235 .p1 = { .min = 2, .max = 33 },
236 .p2 = { .dot_limit = 165000,
237 .p2_slow = 4, .p2_fast = 4 },
240 static const struct intel_limit intel_limits_i8xx_lvds = {
241 .dot = { .min = 25000, .max = 350000 },
242 .vco = { .min = 908000, .max = 1512000 },
243 .n = { .min = 2, .max = 16 },
244 .m = { .min = 96, .max = 140 },
245 .m1 = { .min = 18, .max = 26 },
246 .m2 = { .min = 6, .max = 16 },
247 .p = { .min = 4, .max = 128 },
248 .p1 = { .min = 1, .max = 6 },
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 14, .p2_fast = 7 },
253 static const struct intel_limit intel_limits_i9xx_sdvo = {
254 .dot = { .min = 20000, .max = 400000 },
255 .vco = { .min = 1400000, .max = 2800000 },
256 .n = { .min = 1, .max = 6 },
257 .m = { .min = 70, .max = 120 },
258 .m1 = { .min = 8, .max = 18 },
259 .m2 = { .min = 3, .max = 7 },
260 .p = { .min = 5, .max = 80 },
261 .p1 = { .min = 1, .max = 8 },
262 .p2 = { .dot_limit = 200000,
263 .p2_slow = 10, .p2_fast = 5 },
266 static const struct intel_limit intel_limits_i9xx_lvds = {
267 .dot = { .min = 20000, .max = 400000 },
268 .vco = { .min = 1400000, .max = 2800000 },
269 .n = { .min = 1, .max = 6 },
270 .m = { .min = 70, .max = 120 },
271 .m1 = { .min = 8, .max = 18 },
272 .m2 = { .min = 3, .max = 7 },
273 .p = { .min = 7, .max = 98 },
274 .p1 = { .min = 1, .max = 8 },
275 .p2 = { .dot_limit = 112000,
276 .p2_slow = 14, .p2_fast = 7 },
280 static const struct intel_limit intel_limits_g4x_sdvo = {
281 .dot = { .min = 25000, .max = 270000 },
282 .vco = { .min = 1750000, .max = 3500000},
283 .n = { .min = 1, .max = 4 },
284 .m = { .min = 104, .max = 138 },
285 .m1 = { .min = 17, .max = 23 },
286 .m2 = { .min = 5, .max = 11 },
287 .p = { .min = 10, .max = 30 },
288 .p1 = { .min = 1, .max = 3},
289 .p2 = { .dot_limit = 270000,
295 static const struct intel_limit intel_limits_g4x_hdmi = {
296 .dot = { .min = 22000, .max = 400000 },
297 .vco = { .min = 1750000, .max = 3500000},
298 .n = { .min = 1, .max = 4 },
299 .m = { .min = 104, .max = 138 },
300 .m1 = { .min = 16, .max = 23 },
301 .m2 = { .min = 5, .max = 11 },
302 .p = { .min = 5, .max = 80 },
303 .p1 = { .min = 1, .max = 8},
304 .p2 = { .dot_limit = 165000,
305 .p2_slow = 10, .p2_fast = 5 },
308 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
309 .dot = { .min = 20000, .max = 115000 },
310 .vco = { .min = 1750000, .max = 3500000 },
311 .n = { .min = 1, .max = 3 },
312 .m = { .min = 104, .max = 138 },
313 .m1 = { .min = 17, .max = 23 },
314 .m2 = { .min = 5, .max = 11 },
315 .p = { .min = 28, .max = 112 },
316 .p1 = { .min = 2, .max = 8 },
317 .p2 = { .dot_limit = 0,
318 .p2_slow = 14, .p2_fast = 14
322 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
323 .dot = { .min = 80000, .max = 224000 },
324 .vco = { .min = 1750000, .max = 3500000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 104, .max = 138 },
327 .m1 = { .min = 17, .max = 23 },
328 .m2 = { .min = 5, .max = 11 },
329 .p = { .min = 14, .max = 42 },
330 .p1 = { .min = 2, .max = 6 },
331 .p2 = { .dot_limit = 0,
332 .p2_slow = 7, .p2_fast = 7
336 static const struct intel_limit intel_limits_pineview_sdvo = {
337 .dot = { .min = 20000, .max = 400000},
338 .vco = { .min = 1700000, .max = 3500000 },
339 /* Pineview's Ncounter is a ring counter */
340 .n = { .min = 3, .max = 6 },
341 .m = { .min = 2, .max = 256 },
342 /* Pineview only has one combined m divider, which we treat as m2. */
343 .m1 = { .min = 0, .max = 0 },
344 .m2 = { .min = 0, .max = 254 },
345 .p = { .min = 5, .max = 80 },
346 .p1 = { .min = 1, .max = 8 },
347 .p2 = { .dot_limit = 200000,
348 .p2_slow = 10, .p2_fast = 5 },
351 static const struct intel_limit intel_limits_pineview_lvds = {
352 .dot = { .min = 20000, .max = 400000 },
353 .vco = { .min = 1700000, .max = 3500000 },
354 .n = { .min = 3, .max = 6 },
355 .m = { .min = 2, .max = 256 },
356 .m1 = { .min = 0, .max = 0 },
357 .m2 = { .min = 0, .max = 254 },
358 .p = { .min = 7, .max = 112 },
359 .p1 = { .min = 1, .max = 8 },
360 .p2 = { .dot_limit = 112000,
361 .p2_slow = 14, .p2_fast = 14 },
364 /* Ironlake / Sandybridge
366 * We calculate clock using (register_value + 2) for N/M1/M2, so here
367 * the range value for them is (actual_value - 2).
369 static const struct intel_limit intel_limits_ironlake_dac = {
370 .dot = { .min = 25000, .max = 350000 },
371 .vco = { .min = 1760000, .max = 3510000 },
372 .n = { .min = 1, .max = 5 },
373 .m = { .min = 79, .max = 127 },
374 .m1 = { .min = 12, .max = 22 },
375 .m2 = { .min = 5, .max = 9 },
376 .p = { .min = 5, .max = 80 },
377 .p1 = { .min = 1, .max = 8 },
378 .p2 = { .dot_limit = 225000,
379 .p2_slow = 10, .p2_fast = 5 },
382 static const struct intel_limit intel_limits_ironlake_single_lvds = {
383 .dot = { .min = 25000, .max = 350000 },
384 .vco = { .min = 1760000, .max = 3510000 },
385 .n = { .min = 1, .max = 3 },
386 .m = { .min = 79, .max = 118 },
387 .m1 = { .min = 12, .max = 22 },
388 .m2 = { .min = 5, .max = 9 },
389 .p = { .min = 28, .max = 112 },
390 .p1 = { .min = 2, .max = 8 },
391 .p2 = { .dot_limit = 225000,
392 .p2_slow = 14, .p2_fast = 14 },
395 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
396 .dot = { .min = 25000, .max = 350000 },
397 .vco = { .min = 1760000, .max = 3510000 },
398 .n = { .min = 1, .max = 3 },
399 .m = { .min = 79, .max = 127 },
400 .m1 = { .min = 12, .max = 22 },
401 .m2 = { .min = 5, .max = 9 },
402 .p = { .min = 14, .max = 56 },
403 .p1 = { .min = 2, .max = 8 },
404 .p2 = { .dot_limit = 225000,
405 .p2_slow = 7, .p2_fast = 7 },
408 /* LVDS 100mhz refclk limits. */
409 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 2 },
413 .m = { .min = 79, .max = 126 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 28, .max = 112 },
417 .p1 = { .min = 2, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 14, .p2_fast = 14 },
422 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
423 .dot = { .min = 25000, .max = 350000 },
424 .vco = { .min = 1760000, .max = 3510000 },
425 .n = { .min = 1, .max = 3 },
426 .m = { .min = 79, .max = 126 },
427 .m1 = { .min = 12, .max = 22 },
428 .m2 = { .min = 5, .max = 9 },
429 .p = { .min = 14, .max = 42 },
430 .p1 = { .min = 2, .max = 6 },
431 .p2 = { .dot_limit = 225000,
432 .p2_slow = 7, .p2_fast = 7 },
435 static const struct intel_limit intel_limits_vlv = {
437 * These are the data rate limits (measured in fast clocks)
438 * since those are the strictest limits we have. The fast
439 * clock and actual rate limits are more relaxed, so checking
440 * them would make no difference.
442 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
443 .vco = { .min = 4000000, .max = 6000000 },
444 .n = { .min = 1, .max = 7 },
445 .m1 = { .min = 2, .max = 3 },
446 .m2 = { .min = 11, .max = 156 },
447 .p1 = { .min = 2, .max = 3 },
448 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
451 static const struct intel_limit intel_limits_chv = {
453 * These are the data rate limits (measured in fast clocks)
454 * since those are the strictest limits we have. The fast
455 * clock and actual rate limits are more relaxed, so checking
456 * them would make no difference.
458 .dot = { .min = 25000 * 5, .max = 540000 * 5},
459 .vco = { .min = 4800000, .max = 6480000 },
460 .n = { .min = 1, .max = 1 },
461 .m1 = { .min = 2, .max = 2 },
462 .m2 = { .min = 24 << 22, .max = 175 << 22 },
463 .p1 = { .min = 2, .max = 4 },
464 .p2 = { .p2_slow = 1, .p2_fast = 14 },
467 static const struct intel_limit intel_limits_bxt = {
468 /* FIXME: find real dot limits */
469 .dot = { .min = 0, .max = INT_MAX },
470 .vco = { .min = 4800000, .max = 6700000 },
471 .n = { .min = 1, .max = 1 },
472 .m1 = { .min = 2, .max = 2 },
473 /* FIXME: find real m2 limits */
474 .m2 = { .min = 2 << 22, .max = 255 << 22 },
475 .p1 = { .min = 2, .max = 4 },
476 .p2 = { .p2_slow = 1, .p2_fast = 20 },
480 skl_wa_827(struct drm_i915_private *dev_priv, int pipe, bool enable)
483 I915_WRITE(CLKGATE_DIS_PSL(pipe),
484 I915_READ(CLKGATE_DIS_PSL(pipe)) |
485 DUPS1_GATING_DIS | DUPS2_GATING_DIS);
487 I915_WRITE(CLKGATE_DIS_PSL(pipe),
488 I915_READ(CLKGATE_DIS_PSL(pipe)) &
489 ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
493 needs_modeset(const struct drm_crtc_state *state)
495 return drm_atomic_crtc_needs_modeset(state);
499 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
500 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
501 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
502 * The helpers' return value is the rate of the clock that is fed to the
503 * display engine's pipe which can be the above fast dot clock rate or a
504 * divided-down version of it.
506 /* m1 is reserved as 0 in Pineview, n is a ring counter */
507 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
509 clock->m = clock->m2 + 2;
510 clock->p = clock->p1 * clock->p2;
511 if (WARN_ON(clock->n == 0 || clock->p == 0))
513 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
514 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
519 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
521 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
524 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
526 clock->m = i9xx_dpll_compute_m(clock);
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
536 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
538 clock->m = clock->m1 * clock->m2;
539 clock->p = clock->p1 * clock->p2;
540 if (WARN_ON(clock->n == 0 || clock->p == 0))
542 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
543 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
545 return clock->dot / 5;
548 int chv_calc_dpll_params(int refclk, struct dpll *clock)
550 clock->m = clock->m1 * clock->m2;
551 clock->p = clock->p1 * clock->p2;
552 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 clock->vco = DIV_ROUND_CLOSEST_ULL((u64)refclk * clock->m,
556 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 return clock->dot / 5;
561 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
564 * Returns whether the given set of divisors are valid for a given refclk with
565 * the given connectors.
567 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
568 const struct intel_limit *limit,
569 const struct dpll *clock)
571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
578 INTELPllInvalid("m1 out of range\n");
580 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
581 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
582 if (clock->m1 <= clock->m2)
583 INTELPllInvalid("m1 <= m2\n");
585 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
586 !IS_GEN9_LP(dev_priv)) {
587 if (clock->p < limit->p.min || limit->p.max < clock->p)
588 INTELPllInvalid("p out of range\n");
589 if (clock->m < limit->m.min || limit->m.max < clock->m)
590 INTELPllInvalid("m out of range\n");
593 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
594 INTELPllInvalid("vco out of range\n");
595 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
596 * connector, etc., rather than just a single range.
598 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
599 INTELPllInvalid("dot out of range\n");
605 i9xx_select_p2_div(const struct intel_limit *limit,
606 const struct intel_crtc_state *crtc_state,
609 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
611 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
617 if (intel_is_dual_link_lvds(dev_priv))
618 return limit->p2.p2_fast;
620 return limit->p2.p2_slow;
622 if (target < limit->p2.dot_limit)
623 return limit->p2.p2_slow;
625 return limit->p2.p2_fast;
630 * Returns a set of divisors for the desired target clock with the given
631 * refclk, or FALSE. The returned values represent the clock equation:
632 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
634 * Target and reference clocks are specified in kHz.
636 * If match_clock is provided, then best_clock P divider must match the P
637 * divider from @match_clock used for LVDS downclocking.
640 i9xx_find_best_dpll(const struct intel_limit *limit,
641 struct intel_crtc_state *crtc_state,
642 int target, int refclk, struct dpll *match_clock,
643 struct dpll *best_clock)
645 struct drm_device *dev = crtc_state->base.crtc->dev;
649 memset(best_clock, 0, sizeof(*best_clock));
651 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
653 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 for (clock.m2 = limit->m2.min;
656 clock.m2 <= limit->m2.max; clock.m2++) {
657 if (clock.m2 >= clock.m1)
659 for (clock.n = limit->n.min;
660 clock.n <= limit->n.max; clock.n++) {
661 for (clock.p1 = limit->p1.min;
662 clock.p1 <= limit->p1.max; clock.p1++) {
665 i9xx_calc_dpll_params(refclk, &clock);
666 if (!intel_PLL_is_valid(to_i915(dev),
671 clock.p != match_clock->p)
674 this_err = abs(clock.dot - target);
675 if (this_err < err) {
684 return (err != target);
688 * Returns a set of divisors for the desired target clock with the given
689 * refclk, or FALSE. The returned values represent the clock equation:
690 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
692 * Target and reference clocks are specified in kHz.
694 * If match_clock is provided, then best_clock P divider must match the P
695 * divider from @match_clock used for LVDS downclocking.
698 pnv_find_best_dpll(const struct intel_limit *limit,
699 struct intel_crtc_state *crtc_state,
700 int target, int refclk, struct dpll *match_clock,
701 struct dpll *best_clock)
703 struct drm_device *dev = crtc_state->base.crtc->dev;
707 memset(best_clock, 0, sizeof(*best_clock));
709 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
711 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
713 for (clock.m2 = limit->m2.min;
714 clock.m2 <= limit->m2.max; clock.m2++) {
715 for (clock.n = limit->n.min;
716 clock.n <= limit->n.max; clock.n++) {
717 for (clock.p1 = limit->p1.min;
718 clock.p1 <= limit->p1.max; clock.p1++) {
721 pnv_calc_dpll_params(refclk, &clock);
722 if (!intel_PLL_is_valid(to_i915(dev),
727 clock.p != match_clock->p)
730 this_err = abs(clock.dot - target);
731 if (this_err < err) {
740 return (err != target);
744 * Returns a set of divisors for the desired target clock with the given
745 * refclk, or FALSE. The returned values represent the clock equation:
746 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
748 * Target and reference clocks are specified in kHz.
750 * If match_clock is provided, then best_clock P divider must match the P
751 * divider from @match_clock used for LVDS downclocking.
754 g4x_find_best_dpll(const struct intel_limit *limit,
755 struct intel_crtc_state *crtc_state,
756 int target, int refclk, struct dpll *match_clock,
757 struct dpll *best_clock)
759 struct drm_device *dev = crtc_state->base.crtc->dev;
763 /* approximately equals target * 0.00585 */
764 int err_most = (target >> 8) + (target >> 9);
766 memset(best_clock, 0, sizeof(*best_clock));
768 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
770 max_n = limit->n.max;
771 /* based on hardware requirement, prefer smaller n to precision */
772 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
773 /* based on hardware requirement, prefere larger m1,m2 */
774 for (clock.m1 = limit->m1.max;
775 clock.m1 >= limit->m1.min; clock.m1--) {
776 for (clock.m2 = limit->m2.max;
777 clock.m2 >= limit->m2.min; clock.m2--) {
778 for (clock.p1 = limit->p1.max;
779 clock.p1 >= limit->p1.min; clock.p1--) {
782 i9xx_calc_dpll_params(refclk, &clock);
783 if (!intel_PLL_is_valid(to_i915(dev),
788 this_err = abs(clock.dot - target);
789 if (this_err < err_most) {
803 * Check if the calculated PLL configuration is more optimal compared to the
804 * best configuration and error found so far. Return the calculated error.
806 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
807 const struct dpll *calculated_clock,
808 const struct dpll *best_clock,
809 unsigned int best_error_ppm,
810 unsigned int *error_ppm)
813 * For CHV ignore the error and consider only the P value.
814 * Prefer a bigger P value based on HW requirements.
816 if (IS_CHERRYVIEW(to_i915(dev))) {
819 return calculated_clock->p > best_clock->p;
822 if (WARN_ON_ONCE(!target_freq))
825 *error_ppm = div_u64(1000000ULL *
826 abs(target_freq - calculated_clock->dot),
829 * Prefer a better P value over a better (smaller) error if the error
830 * is small. Ensure this preference for future configurations too by
831 * setting the error to 0.
833 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
839 return *error_ppm + 10 < best_error_ppm;
843 * Returns a set of divisors for the desired target clock with the given
844 * refclk, or FALSE. The returned values represent the clock equation:
845 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
848 vlv_find_best_dpll(const struct intel_limit *limit,
849 struct intel_crtc_state *crtc_state,
850 int target, int refclk, struct dpll *match_clock,
851 struct dpll *best_clock)
853 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
854 struct drm_device *dev = crtc->base.dev;
856 unsigned int bestppm = 1000000;
857 /* min update 19.2 MHz */
858 int max_n = min(limit->n.max, refclk / 19200);
861 target *= 5; /* fast clock */
863 memset(best_clock, 0, sizeof(*best_clock));
865 /* based on hardware requirement, prefer smaller n to precision */
866 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
867 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
868 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
869 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
870 clock.p = clock.p1 * clock.p2;
871 /* based on hardware requirement, prefer bigger m1,m2 values */
872 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
875 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
878 vlv_calc_dpll_params(refclk, &clock);
880 if (!intel_PLL_is_valid(to_i915(dev),
885 if (!vlv_PLL_is_optimal(dev, target,
903 * Returns a set of divisors for the desired target clock with the given
904 * refclk, or FALSE. The returned values represent the clock equation:
905 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
908 chv_find_best_dpll(const struct intel_limit *limit,
909 struct intel_crtc_state *crtc_state,
910 int target, int refclk, struct dpll *match_clock,
911 struct dpll *best_clock)
913 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
914 struct drm_device *dev = crtc->base.dev;
915 unsigned int best_error_ppm;
920 memset(best_clock, 0, sizeof(*best_clock));
921 best_error_ppm = 1000000;
924 * Based on hardware doc, the n always set to 1, and m1 always
925 * set to 2. If requires to support 200Mhz refclk, we need to
926 * revisit this because n may not 1 anymore.
928 clock.n = 1, clock.m1 = 2;
929 target *= 5; /* fast clock */
931 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
932 for (clock.p2 = limit->p2.p2_fast;
933 clock.p2 >= limit->p2.p2_slow;
934 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
935 unsigned int error_ppm;
937 clock.p = clock.p1 * clock.p2;
939 m2 = DIV_ROUND_CLOSEST_ULL(((u64)target * clock.p *
940 clock.n) << 22, refclk * clock.m1);
942 if (m2 > INT_MAX/clock.m1)
947 chv_calc_dpll_params(refclk, &clock);
949 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
952 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
953 best_error_ppm, &error_ppm))
957 best_error_ppm = error_ppm;
965 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
966 struct dpll *best_clock)
969 const struct intel_limit *limit = &intel_limits_bxt;
971 return chv_find_best_dpll(limit, crtc_state,
972 crtc_state->port_clock, refclk,
976 bool intel_crtc_active(struct intel_crtc *crtc)
978 /* Be paranoid as we can arrive here with only partial
979 * state retrieved from the hardware during setup.
981 * We can ditch the adjusted_mode.crtc_clock check as soon
982 * as Haswell has gained clock readout/fastboot support.
984 * We can ditch the crtc->primary->state->fb check as soon as we can
985 * properly reconstruct framebuffers.
987 * FIXME: The intel_crtc->active here should be switched to
988 * crtc->state->active once we have proper CRTC states wired up
991 return crtc->active && crtc->base.primary->state->fb &&
992 crtc->config->base.adjusted_mode.crtc_clock;
995 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
998 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1000 return crtc->config->cpu_transcoder;
1003 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1006 i915_reg_t reg = PIPEDSL(pipe);
1010 if (IS_GEN(dev_priv, 2))
1011 line_mask = DSL_LINEMASK_GEN2;
1013 line_mask = DSL_LINEMASK_GEN3;
1015 line1 = I915_READ(reg) & line_mask;
1017 line2 = I915_READ(reg) & line_mask;
1019 return line1 != line2;
1022 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1024 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1025 enum pipe pipe = crtc->pipe;
1027 /* Wait for the display line to settle/start moving */
1028 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1029 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1030 pipe_name(pipe), onoff(state));
1033 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1035 wait_for_pipe_scanline_moving(crtc, false);
1038 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1040 wait_for_pipe_scanline_moving(crtc, true);
1044 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1046 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1047 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1049 if (INTEL_GEN(dev_priv) >= 4) {
1050 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1051 i915_reg_t reg = PIPECONF(cpu_transcoder);
1053 /* Wait for the Pipe State to go off */
1054 if (intel_wait_for_register(&dev_priv->uncore,
1055 reg, I965_PIPECONF_ACTIVE, 0,
1057 WARN(1, "pipe_off wait timed out\n");
1059 intel_wait_for_pipe_scanline_stopped(crtc);
1063 /* Only for pre-ILK configs */
1064 void assert_pll(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1070 val = I915_READ(DPLL(pipe));
1071 cur_state = !!(val & DPLL_VCO_ENABLE);
1072 I915_STATE_WARN(cur_state != state,
1073 "PLL state assertion failure (expected %s, current %s)\n",
1074 onoff(state), onoff(cur_state));
1077 /* XXX: the dsi pll is shared between MIPI DSI ports */
1078 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1083 mutex_lock(&dev_priv->sb_lock);
1084 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1085 mutex_unlock(&dev_priv->sb_lock);
1087 cur_state = val & DSI_PLL_VCO_EN;
1088 I915_STATE_WARN(cur_state != state,
1089 "DSI PLL state assertion failure (expected %s, current %s)\n",
1090 onoff(state), onoff(cur_state));
1093 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1094 enum pipe pipe, bool state)
1097 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1100 if (HAS_DDI(dev_priv)) {
1101 /* DDI does not have a specific FDI_TX register */
1102 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1103 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1105 u32 val = I915_READ(FDI_TX_CTL(pipe));
1106 cur_state = !!(val & FDI_TX_ENABLE);
1108 I915_STATE_WARN(cur_state != state,
1109 "FDI TX state assertion failure (expected %s, current %s)\n",
1110 onoff(state), onoff(cur_state));
1112 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1113 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1115 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1121 val = I915_READ(FDI_RX_CTL(pipe));
1122 cur_state = !!(val & FDI_RX_ENABLE);
1123 I915_STATE_WARN(cur_state != state,
1124 "FDI RX state assertion failure (expected %s, current %s)\n",
1125 onoff(state), onoff(cur_state));
1127 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1128 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1130 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1135 /* ILK FDI PLL is always enabled */
1136 if (IS_GEN(dev_priv, 5))
1139 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1140 if (HAS_DDI(dev_priv))
1143 val = I915_READ(FDI_TX_CTL(pipe));
1144 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1147 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1153 val = I915_READ(FDI_RX_CTL(pipe));
1154 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1155 I915_STATE_WARN(cur_state != state,
1156 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1157 onoff(state), onoff(cur_state));
1160 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1164 enum pipe panel_pipe = INVALID_PIPE;
1167 if (WARN_ON(HAS_DDI(dev_priv)))
1170 if (HAS_PCH_SPLIT(dev_priv)) {
1173 pp_reg = PP_CONTROL(0);
1174 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1177 case PANEL_PORT_SELECT_LVDS:
1178 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1180 case PANEL_PORT_SELECT_DPA:
1181 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1183 case PANEL_PORT_SELECT_DPC:
1184 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1186 case PANEL_PORT_SELECT_DPD:
1187 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1190 MISSING_CASE(port_sel);
1193 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1194 /* presumably write lock depends on pipe, not port select */
1195 pp_reg = PP_CONTROL(pipe);
1200 pp_reg = PP_CONTROL(0);
1201 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1203 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1204 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1207 val = I915_READ(pp_reg);
1208 if (!(val & PANEL_POWER_ON) ||
1209 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1212 I915_STATE_WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
1217 void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223 enum intel_display_power_domain power_domain;
1224 intel_wakeref_t wakeref;
1226 /* we keep both pipes enabled on 830 */
1227 if (IS_I830(dev_priv))
1230 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1231 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1233 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1234 cur_state = !!(val & PIPECONF_ENABLE);
1236 intel_display_power_put(dev_priv, power_domain, wakeref);
1241 I915_STATE_WARN(cur_state != state,
1242 "pipe %c assertion failure (expected %s, current %s)\n",
1243 pipe_name(pipe), onoff(state), onoff(cur_state));
1246 static void assert_plane(struct intel_plane *plane, bool state)
1251 cur_state = plane->get_hw_state(plane, &pipe);
1253 I915_STATE_WARN(cur_state != state,
1254 "%s assertion failure (expected %s, current %s)\n",
1255 plane->base.name, onoff(state), onoff(cur_state));
1258 #define assert_plane_enabled(p) assert_plane(p, true)
1259 #define assert_plane_disabled(p) assert_plane(p, false)
1261 static void assert_planes_disabled(struct intel_crtc *crtc)
1263 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1264 struct intel_plane *plane;
1266 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1267 assert_plane_disabled(plane);
1270 static void assert_vblank_disabled(struct drm_crtc *crtc)
1272 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1273 drm_crtc_vblank_put(crtc);
1276 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1282 val = I915_READ(PCH_TRANSCONF(pipe));
1283 enabled = !!(val & TRANS_ENABLE);
1284 I915_STATE_WARN(enabled,
1285 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1289 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, enum port port,
1293 enum pipe port_pipe;
1296 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1298 I915_STATE_WARN(state && port_pipe == pipe,
1299 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1300 port_name(port), pipe_name(pipe));
1302 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1303 "IBX PCH DP %c still using transcoder B\n",
1307 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, enum port port,
1309 i915_reg_t hdmi_reg)
1311 enum pipe port_pipe;
1314 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1316 I915_STATE_WARN(state && port_pipe == pipe,
1317 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1318 port_name(port), pipe_name(pipe));
1320 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1321 "IBX PCH HDMI %c still using transcoder B\n",
1325 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1328 enum pipe port_pipe;
1330 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1331 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1332 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1334 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1336 "PCH VGA enabled on transcoder %c, should be disabled\n",
1339 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1341 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1344 /* PCH SDVOB multiplex with HDMIB */
1345 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1346 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1347 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1350 static void _vlv_enable_pll(struct intel_crtc *crtc,
1351 const struct intel_crtc_state *pipe_config)
1353 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1354 enum pipe pipe = crtc->pipe;
1356 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1357 POSTING_READ(DPLL(pipe));
1360 if (intel_wait_for_register(&dev_priv->uncore,
1365 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1368 static void vlv_enable_pll(struct intel_crtc *crtc,
1369 const struct intel_crtc_state *pipe_config)
1371 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1372 enum pipe pipe = crtc->pipe;
1374 assert_pipe_disabled(dev_priv, pipe);
1376 /* PLL is protected by panel, make sure we can write it */
1377 assert_panel_unlocked(dev_priv, pipe);
1379 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1380 _vlv_enable_pll(crtc, pipe_config);
1382 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1383 POSTING_READ(DPLL_MD(pipe));
1387 static void _chv_enable_pll(struct intel_crtc *crtc,
1388 const struct intel_crtc_state *pipe_config)
1390 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1391 enum pipe pipe = crtc->pipe;
1392 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1395 mutex_lock(&dev_priv->sb_lock);
1397 /* Enable back the 10bit clock to display controller */
1398 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1399 tmp |= DPIO_DCLKP_EN;
1400 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1402 mutex_unlock(&dev_priv->sb_lock);
1405 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1410 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1412 /* Check PLL is locked */
1413 if (intel_wait_for_register(&dev_priv->uncore,
1414 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1416 DRM_ERROR("PLL %d failed to lock\n", pipe);
1419 static void chv_enable_pll(struct intel_crtc *crtc,
1420 const struct intel_crtc_state *pipe_config)
1422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1423 enum pipe pipe = crtc->pipe;
1425 assert_pipe_disabled(dev_priv, pipe);
1427 /* PLL is protected by panel, make sure we can write it */
1428 assert_panel_unlocked(dev_priv, pipe);
1430 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1431 _chv_enable_pll(crtc, pipe_config);
1433 if (pipe != PIPE_A) {
1435 * WaPixelRepeatModeFixForC0:chv
1437 * DPLLCMD is AWOL. Use chicken bits to propagate
1438 * the value from DPLLBMD to either pipe B or C.
1440 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1441 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1442 I915_WRITE(CBR4_VLV, 0);
1443 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1446 * DPLLB VGA mode also seems to cause problems.
1447 * We should always have it disabled.
1449 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1451 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1452 POSTING_READ(DPLL_MD(pipe));
1456 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1458 if (IS_I830(dev_priv))
1461 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1464 static void i9xx_enable_pll(struct intel_crtc *crtc,
1465 const struct intel_crtc_state *crtc_state)
1467 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1468 i915_reg_t reg = DPLL(crtc->pipe);
1469 u32 dpll = crtc_state->dpll_hw_state.dpll;
1472 assert_pipe_disabled(dev_priv, crtc->pipe);
1474 /* PLL is protected by panel, make sure we can write it */
1475 if (i9xx_has_pps(dev_priv))
1476 assert_panel_unlocked(dev_priv, crtc->pipe);
1479 * Apparently we need to have VGA mode enabled prior to changing
1480 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1481 * dividers, even though the register value does change.
1483 I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1484 I915_WRITE(reg, dpll);
1486 /* Wait for the clocks to stabilize. */
1490 if (INTEL_GEN(dev_priv) >= 4) {
1491 I915_WRITE(DPLL_MD(crtc->pipe),
1492 crtc_state->dpll_hw_state.dpll_md);
1494 /* The pixel multiplier can only be updated once the
1495 * DPLL is enabled and the clocks are stable.
1497 * So write it again.
1499 I915_WRITE(reg, dpll);
1502 /* We do this three times for luck */
1503 for (i = 0; i < 3; i++) {
1504 I915_WRITE(reg, dpll);
1506 udelay(150); /* wait for warmup */
1510 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1512 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1513 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1514 enum pipe pipe = crtc->pipe;
1516 /* Don't disable pipe or pipe PLLs if needed */
1517 if (IS_I830(dev_priv))
1520 /* Make sure the pipe isn't still relying on us */
1521 assert_pipe_disabled(dev_priv, pipe);
1523 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1524 POSTING_READ(DPLL(pipe));
1527 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1531 /* Make sure the pipe isn't still relying on us */
1532 assert_pipe_disabled(dev_priv, pipe);
1534 val = DPLL_INTEGRATED_REF_CLK_VLV |
1535 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1537 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1539 I915_WRITE(DPLL(pipe), val);
1540 POSTING_READ(DPLL(pipe));
1543 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1545 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1548 /* Make sure the pipe isn't still relying on us */
1549 assert_pipe_disabled(dev_priv, pipe);
1551 val = DPLL_SSC_REF_CLK_CHV |
1552 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1554 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1556 I915_WRITE(DPLL(pipe), val);
1557 POSTING_READ(DPLL(pipe));
1559 mutex_lock(&dev_priv->sb_lock);
1561 /* Disable 10bit clock to display controller */
1562 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563 val &= ~DPIO_DCLKP_EN;
1564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1566 mutex_unlock(&dev_priv->sb_lock);
1569 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1570 struct intel_digital_port *dport,
1571 unsigned int expected_mask)
1574 i915_reg_t dpll_reg;
1576 switch (dport->base.port) {
1578 port_mask = DPLL_PORTB_READY_MASK;
1582 port_mask = DPLL_PORTC_READY_MASK;
1584 expected_mask <<= 4;
1587 port_mask = DPLL_PORTD_READY_MASK;
1588 dpll_reg = DPIO_PHY_STATUS;
1594 if (intel_wait_for_register(&dev_priv->uncore,
1595 dpll_reg, port_mask, expected_mask,
1597 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1598 port_name(dport->base.port),
1599 I915_READ(dpll_reg) & port_mask, expected_mask);
1602 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1604 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1605 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1606 enum pipe pipe = crtc->pipe;
1608 u32 val, pipeconf_val;
1610 /* Make sure PCH DPLL is enabled */
1611 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1613 /* FDI must be feeding us bits for PCH ports */
1614 assert_fdi_tx_enabled(dev_priv, pipe);
1615 assert_fdi_rx_enabled(dev_priv, pipe);
1617 if (HAS_PCH_CPT(dev_priv)) {
1618 /* Workaround: Set the timing override bit before enabling the
1619 * pch transcoder. */
1620 reg = TRANS_CHICKEN2(pipe);
1621 val = I915_READ(reg);
1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1623 I915_WRITE(reg, val);
1626 reg = PCH_TRANSCONF(pipe);
1627 val = I915_READ(reg);
1628 pipeconf_val = I915_READ(PIPECONF(pipe));
1630 if (HAS_PCH_IBX(dev_priv)) {
1632 * Make the BPC in transcoder be consistent with
1633 * that in pipeconf reg. For HDMI we must use 8bpc
1634 * here for both 8bpc and 12bpc.
1636 val &= ~PIPECONF_BPC_MASK;
1637 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1638 val |= PIPECONF_8BPC;
1640 val |= pipeconf_val & PIPECONF_BPC_MASK;
1643 val &= ~TRANS_INTERLACE_MASK;
1644 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1645 if (HAS_PCH_IBX(dev_priv) &&
1646 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1647 val |= TRANS_LEGACY_INTERLACED_ILK;
1649 val |= TRANS_INTERLACED;
1651 val |= TRANS_PROGRESSIVE;
1654 I915_WRITE(reg, val | TRANS_ENABLE);
1655 if (intel_wait_for_register(&dev_priv->uncore,
1656 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1658 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1661 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1662 enum transcoder cpu_transcoder)
1664 u32 val, pipeconf_val;
1666 /* FDI must be feeding us bits for PCH ports */
1667 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1668 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1670 /* Workaround: set timing override bit. */
1671 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1672 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1673 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1676 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1678 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1679 PIPECONF_INTERLACED_ILK)
1680 val |= TRANS_INTERLACED;
1682 val |= TRANS_PROGRESSIVE;
1684 I915_WRITE(LPT_TRANSCONF, val);
1685 if (intel_wait_for_register(&dev_priv->uncore,
1690 DRM_ERROR("Failed to enable PCH transcoder\n");
1693 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1699 /* FDI relies on the transcoder */
1700 assert_fdi_tx_disabled(dev_priv, pipe);
1701 assert_fdi_rx_disabled(dev_priv, pipe);
1703 /* Ports must be off as well */
1704 assert_pch_ports_disabled(dev_priv, pipe);
1706 reg = PCH_TRANSCONF(pipe);
1707 val = I915_READ(reg);
1708 val &= ~TRANS_ENABLE;
1709 I915_WRITE(reg, val);
1710 /* wait for PCH transcoder off, transcoder state */
1711 if (intel_wait_for_register(&dev_priv->uncore,
1712 reg, TRANS_STATE_ENABLE, 0,
1714 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1716 if (HAS_PCH_CPT(dev_priv)) {
1717 /* Workaround: Clear the timing override chicken bit again. */
1718 reg = TRANS_CHICKEN2(pipe);
1719 val = I915_READ(reg);
1720 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1721 I915_WRITE(reg, val);
1725 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1729 val = I915_READ(LPT_TRANSCONF);
1730 val &= ~TRANS_ENABLE;
1731 I915_WRITE(LPT_TRANSCONF, val);
1732 /* wait for PCH transcoder off, transcoder state */
1733 if (intel_wait_for_register(&dev_priv->uncore,
1734 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1736 DRM_ERROR("Failed to disable PCH transcoder\n");
1738 /* Workaround: clear timing override bit. */
1739 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1740 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1741 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1744 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1746 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1748 if (HAS_PCH_LPT(dev_priv))
1754 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1756 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1759 * On i965gm the hardware frame counter reads
1760 * zero when the TV encoder is enabled :(
1762 if (IS_I965GM(dev_priv) &&
1763 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1766 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1767 return 0xffffffff; /* full 32 bit counter */
1768 else if (INTEL_GEN(dev_priv) >= 3)
1769 return 0xffffff; /* only 24 bits of frame count */
1771 return 0; /* Gen2 doesn't have a hardware frame counter */
1774 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1778 drm_crtc_set_max_vblank_count(&crtc->base,
1779 intel_crtc_max_vblank_count(crtc_state));
1780 drm_crtc_vblank_on(&crtc->base);
1783 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1785 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1786 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1787 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1788 enum pipe pipe = crtc->pipe;
1792 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1794 assert_planes_disabled(crtc);
1797 * A pipe without a PLL won't actually be able to drive bits from
1798 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1801 if (HAS_GMCH(dev_priv)) {
1802 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1803 assert_dsi_pll_enabled(dev_priv);
1805 assert_pll_enabled(dev_priv, pipe);
1807 if (new_crtc_state->has_pch_encoder) {
1808 /* if driving the PCH, we need FDI enabled */
1809 assert_fdi_rx_pll_enabled(dev_priv,
1810 intel_crtc_pch_transcoder(crtc));
1811 assert_fdi_tx_pll_enabled(dev_priv,
1812 (enum pipe) cpu_transcoder);
1814 /* FIXME: assert CPU port conditions for SNB+ */
1817 trace_intel_pipe_enable(dev_priv, pipe);
1819 reg = PIPECONF(cpu_transcoder);
1820 val = I915_READ(reg);
1821 if (val & PIPECONF_ENABLE) {
1822 /* we keep both pipes enabled on 830 */
1823 WARN_ON(!IS_I830(dev_priv));
1827 I915_WRITE(reg, val | PIPECONF_ENABLE);
1831 * Until the pipe starts PIPEDSL reads will return a stale value,
1832 * which causes an apparent vblank timestamp jump when PIPEDSL
1833 * resets to its proper value. That also messes up the frame count
1834 * when it's derived from the timestamps. So let's wait for the
1835 * pipe to start properly before we call drm_crtc_vblank_on()
1837 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1838 intel_wait_for_pipe_scanline_moving(crtc);
1841 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1843 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1845 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1846 enum pipe pipe = crtc->pipe;
1850 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1853 * Make sure planes won't keep trying to pump pixels to us,
1854 * or we might hang the display.
1856 assert_planes_disabled(crtc);
1858 trace_intel_pipe_disable(dev_priv, pipe);
1860 reg = PIPECONF(cpu_transcoder);
1861 val = I915_READ(reg);
1862 if ((val & PIPECONF_ENABLE) == 0)
1866 * Double wide has implications for planes
1867 * so best keep it disabled when not needed.
1869 if (old_crtc_state->double_wide)
1870 val &= ~PIPECONF_DOUBLE_WIDE;
1872 /* Don't disable pipe or pipe PLLs if needed */
1873 if (!IS_I830(dev_priv))
1874 val &= ~PIPECONF_ENABLE;
1876 I915_WRITE(reg, val);
1877 if ((val & PIPECONF_ENABLE) == 0)
1878 intel_wait_for_pipe_off(old_crtc_state);
1881 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1883 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1887 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1889 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1890 unsigned int cpp = fb->format->cpp[color_plane];
1892 switch (fb->modifier) {
1893 case DRM_FORMAT_MOD_LINEAR:
1895 case I915_FORMAT_MOD_X_TILED:
1896 if (IS_GEN(dev_priv, 2))
1900 case I915_FORMAT_MOD_Y_TILED_CCS:
1901 if (color_plane == 1)
1904 case I915_FORMAT_MOD_Y_TILED:
1905 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1909 case I915_FORMAT_MOD_Yf_TILED_CCS:
1910 if (color_plane == 1)
1913 case I915_FORMAT_MOD_Yf_TILED:
1929 MISSING_CASE(fb->modifier);
1935 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1937 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1940 return intel_tile_size(to_i915(fb->dev)) /
1941 intel_tile_width_bytes(fb, color_plane);
1944 /* Return the tile dimensions in pixel units */
1945 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1946 unsigned int *tile_width,
1947 unsigned int *tile_height)
1949 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1950 unsigned int cpp = fb->format->cpp[color_plane];
1952 *tile_width = tile_width_bytes / cpp;
1953 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1957 intel_fb_align_height(const struct drm_framebuffer *fb,
1958 int color_plane, unsigned int height)
1960 unsigned int tile_height = intel_tile_height(fb, color_plane);
1962 return ALIGN(height, tile_height);
1965 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1967 unsigned int size = 0;
1970 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
1971 size += rot_info->plane[i].width * rot_info->plane[i].height;
1977 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
1978 const struct drm_framebuffer *fb,
1979 unsigned int rotation)
1981 view->type = I915_GGTT_VIEW_NORMAL;
1982 if (drm_rotation_90_or_270(rotation)) {
1983 view->type = I915_GGTT_VIEW_ROTATED;
1984 view->rotated = to_intel_framebuffer(fb)->rot_info;
1988 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
1990 if (IS_I830(dev_priv))
1992 else if (IS_I85X(dev_priv))
1994 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2000 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2002 if (INTEL_GEN(dev_priv) >= 9)
2004 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2005 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2007 else if (INTEL_GEN(dev_priv) >= 4)
2013 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2016 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2018 /* AUX_DIST needs only 4K alignment */
2019 if (color_plane == 1)
2022 switch (fb->modifier) {
2023 case DRM_FORMAT_MOD_LINEAR:
2024 return intel_linear_alignment(dev_priv);
2025 case I915_FORMAT_MOD_X_TILED:
2026 if (INTEL_GEN(dev_priv) >= 9)
2029 case I915_FORMAT_MOD_Y_TILED_CCS:
2030 case I915_FORMAT_MOD_Yf_TILED_CCS:
2031 case I915_FORMAT_MOD_Y_TILED:
2032 case I915_FORMAT_MOD_Yf_TILED:
2033 return 1 * 1024 * 1024;
2035 MISSING_CASE(fb->modifier);
2040 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2042 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2043 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2045 return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2049 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2050 const struct i915_ggtt_view *view,
2052 unsigned long *out_flags)
2054 struct drm_device *dev = fb->dev;
2055 struct drm_i915_private *dev_priv = to_i915(dev);
2056 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2057 intel_wakeref_t wakeref;
2058 struct i915_vma *vma;
2059 unsigned int pinctl;
2062 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2064 alignment = intel_surf_alignment(fb, 0);
2066 /* Note that the w/a also requires 64 PTE of padding following the
2067 * bo. We currently fill all unused PTE with the shadow page and so
2068 * we should always have valid PTE following the scanout preventing
2071 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2072 alignment = 256 * 1024;
2075 * Global gtt pte registers are special registers which actually forward
2076 * writes to a chunk of system memory. Which means that there is no risk
2077 * that the register values disappear as soon as we call
2078 * intel_runtime_pm_put(), so it is correct to wrap only the
2079 * pin/unpin/fence and not more.
2081 wakeref = intel_runtime_pm_get(dev_priv);
2083 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2087 /* Valleyview is definitely limited to scanning out the first
2088 * 512MiB. Lets presume this behaviour was inherited from the
2089 * g4x display engine and that all earlier gen are similarly
2090 * limited. Testing suggests that it is a little more
2091 * complicated than this. For example, Cherryview appears quite
2092 * happy to scanout from anywhere within its global aperture.
2094 if (HAS_GMCH(dev_priv))
2095 pinctl |= PIN_MAPPABLE;
2097 vma = i915_gem_object_pin_to_display_plane(obj,
2098 alignment, view, pinctl);
2102 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2105 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2106 * fence, whereas 965+ only requires a fence if using
2107 * framebuffer compression. For simplicity, we always, when
2108 * possible, install a fence as the cost is not that onerous.
2110 * If we fail to fence the tiled scanout, then either the
2111 * modeset will reject the change (which is highly unlikely as
2112 * the affected systems, all but one, do not have unmappable
2113 * space) or we will not be able to enable full powersaving
2114 * techniques (also likely not to apply due to various limits
2115 * FBC and the like impose on the size of the buffer, which
2116 * presumably we violated anyway with this unmappable buffer).
2117 * Anyway, it is presumably better to stumble onwards with
2118 * something and try to run the system in a "less than optimal"
2119 * mode that matches the user configuration.
2121 ret = i915_vma_pin_fence(vma);
2122 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2123 i915_gem_object_unpin_from_display_plane(vma);
2128 if (ret == 0 && vma->fence)
2129 *out_flags |= PLANE_HAS_FENCE;
2134 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2136 intel_runtime_pm_put(dev_priv, wakeref);
2140 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2142 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2144 if (flags & PLANE_HAS_FENCE)
2145 i915_vma_unpin_fence(vma);
2146 i915_gem_object_unpin_from_display_plane(vma);
2150 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2151 unsigned int rotation)
2153 if (drm_rotation_90_or_270(rotation))
2154 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2156 return fb->pitches[color_plane];
2160 * Convert the x/y offsets into a linear offset.
2161 * Only valid with 0/180 degree rotation, which is fine since linear
2162 * offset is only used with linear buffers on pre-hsw and tiled buffers
2163 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2165 u32 intel_fb_xy_to_linear(int x, int y,
2166 const struct intel_plane_state *state,
2169 const struct drm_framebuffer *fb = state->base.fb;
2170 unsigned int cpp = fb->format->cpp[color_plane];
2171 unsigned int pitch = state->color_plane[color_plane].stride;
2173 return y * pitch + x * cpp;
2177 * Add the x/y offsets derived from fb->offsets[] to the user
2178 * specified plane src x/y offsets. The resulting x/y offsets
2179 * specify the start of scanout from the beginning of the gtt mapping.
2181 void intel_add_fb_offsets(int *x, int *y,
2182 const struct intel_plane_state *state,
2186 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2187 unsigned int rotation = state->base.rotation;
2189 if (drm_rotation_90_or_270(rotation)) {
2190 *x += intel_fb->rotated[color_plane].x;
2191 *y += intel_fb->rotated[color_plane].y;
2193 *x += intel_fb->normal[color_plane].x;
2194 *y += intel_fb->normal[color_plane].y;
2198 static u32 intel_adjust_tile_offset(int *x, int *y,
2199 unsigned int tile_width,
2200 unsigned int tile_height,
2201 unsigned int tile_size,
2202 unsigned int pitch_tiles,
2206 unsigned int pitch_pixels = pitch_tiles * tile_width;
2209 WARN_ON(old_offset & (tile_size - 1));
2210 WARN_ON(new_offset & (tile_size - 1));
2211 WARN_ON(new_offset > old_offset);
2213 tiles = (old_offset - new_offset) / tile_size;
2215 *y += tiles / pitch_tiles * tile_height;
2216 *x += tiles % pitch_tiles * tile_width;
2218 /* minimize x in case it got needlessly big */
2219 *y += *x / pitch_pixels * tile_height;
2225 static bool is_surface_linear(u64 modifier, int color_plane)
2227 return modifier == DRM_FORMAT_MOD_LINEAR;
2230 static u32 intel_adjust_aligned_offset(int *x, int *y,
2231 const struct drm_framebuffer *fb,
2233 unsigned int rotation,
2235 u32 old_offset, u32 new_offset)
2237 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2238 unsigned int cpp = fb->format->cpp[color_plane];
2240 WARN_ON(new_offset > old_offset);
2242 if (!is_surface_linear(fb->modifier, color_plane)) {
2243 unsigned int tile_size, tile_width, tile_height;
2244 unsigned int pitch_tiles;
2246 tile_size = intel_tile_size(dev_priv);
2247 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2249 if (drm_rotation_90_or_270(rotation)) {
2250 pitch_tiles = pitch / tile_height;
2251 swap(tile_width, tile_height);
2253 pitch_tiles = pitch / (tile_width * cpp);
2256 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2257 tile_size, pitch_tiles,
2258 old_offset, new_offset);
2260 old_offset += *y * pitch + *x * cpp;
2262 *y = (old_offset - new_offset) / pitch;
2263 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2270 * Adjust the tile offset by moving the difference into
2273 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2274 const struct intel_plane_state *state,
2276 u32 old_offset, u32 new_offset)
2278 return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
2279 state->base.rotation,
2280 state->color_plane[color_plane].stride,
2281 old_offset, new_offset);
2285 * Computes the aligned offset to the base tile and adjusts
2286 * x, y. bytes per pixel is assumed to be a power-of-two.
2288 * In the 90/270 rotated case, x and y are assumed
2289 * to be already rotated to match the rotated GTT view, and
2290 * pitch is the tile_height aligned framebuffer height.
2292 * This function is used when computing the derived information
2293 * under intel_framebuffer, so using any of that information
2294 * here is not allowed. Anything under drm_framebuffer can be
2295 * used. This is why the user has to pass in the pitch since it
2296 * is specified in the rotated orientation.
2298 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2300 const struct drm_framebuffer *fb,
2303 unsigned int rotation,
2306 unsigned int cpp = fb->format->cpp[color_plane];
2307 u32 offset, offset_aligned;
2312 if (!is_surface_linear(fb->modifier, color_plane)) {
2313 unsigned int tile_size, tile_width, tile_height;
2314 unsigned int tile_rows, tiles, pitch_tiles;
2316 tile_size = intel_tile_size(dev_priv);
2317 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2319 if (drm_rotation_90_or_270(rotation)) {
2320 pitch_tiles = pitch / tile_height;
2321 swap(tile_width, tile_height);
2323 pitch_tiles = pitch / (tile_width * cpp);
2326 tile_rows = *y / tile_height;
2329 tiles = *x / tile_width;
2332 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2333 offset_aligned = offset & ~alignment;
2335 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2336 tile_size, pitch_tiles,
2337 offset, offset_aligned);
2339 offset = *y * pitch + *x * cpp;
2340 offset_aligned = offset & ~alignment;
2342 *y = (offset & alignment) / pitch;
2343 *x = ((offset & alignment) - *y * pitch) / cpp;
2346 return offset_aligned;
2349 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2350 const struct intel_plane_state *state,
2353 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2354 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2355 const struct drm_framebuffer *fb = state->base.fb;
2356 unsigned int rotation = state->base.rotation;
2357 int pitch = state->color_plane[color_plane].stride;
2360 if (intel_plane->id == PLANE_CURSOR)
2361 alignment = intel_cursor_alignment(dev_priv);
2363 alignment = intel_surf_alignment(fb, color_plane);
2365 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2366 pitch, rotation, alignment);
2369 /* Convert the fb->offset[] into x/y offsets */
2370 static int intel_fb_offset_to_xy(int *x, int *y,
2371 const struct drm_framebuffer *fb,
2374 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2375 unsigned int height;
2377 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2378 fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2379 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2380 fb->offsets[color_plane], color_plane);
2384 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2385 height = ALIGN(height, intel_tile_height(fb, color_plane));
2387 /* Catch potential overflows early */
2388 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2389 fb->offsets[color_plane])) {
2390 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2391 fb->offsets[color_plane], fb->pitches[color_plane],
2399 intel_adjust_aligned_offset(x, y,
2400 fb, color_plane, DRM_MODE_ROTATE_0,
2401 fb->pitches[color_plane],
2402 fb->offsets[color_plane], 0);
2407 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2409 switch (fb_modifier) {
2410 case I915_FORMAT_MOD_X_TILED:
2411 return I915_TILING_X;
2412 case I915_FORMAT_MOD_Y_TILED:
2413 case I915_FORMAT_MOD_Y_TILED_CCS:
2414 return I915_TILING_Y;
2416 return I915_TILING_NONE;
2421 * From the Sky Lake PRM:
2422 * "The Color Control Surface (CCS) contains the compression status of
2423 * the cache-line pairs. The compression state of the cache-line pair
2424 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2425 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2426 * cache-line-pairs. CCS is always Y tiled."
2428 * Since cache line pairs refers to horizontally adjacent cache lines,
2429 * each cache line in the CCS corresponds to an area of 32x16 cache
2430 * lines on the main surface. Since each pixel is 4 bytes, this gives
2431 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2434 static const struct drm_format_info ccs_formats[] = {
2435 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2436 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2437 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2438 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2441 static const struct drm_format_info *
2442 lookup_format_info(const struct drm_format_info formats[],
2443 int num_formats, u32 format)
2447 for (i = 0; i < num_formats; i++) {
2448 if (formats[i].format == format)
2455 static const struct drm_format_info *
2456 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2458 switch (cmd->modifier[0]) {
2459 case I915_FORMAT_MOD_Y_TILED_CCS:
2460 case I915_FORMAT_MOD_Yf_TILED_CCS:
2461 return lookup_format_info(ccs_formats,
2462 ARRAY_SIZE(ccs_formats),
2469 bool is_ccs_modifier(u64 modifier)
2471 return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2472 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2476 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2477 struct drm_framebuffer *fb)
2479 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2480 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2481 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2482 u32 gtt_offset_rotated = 0;
2483 unsigned int max_size = 0;
2484 int i, num_planes = fb->format->num_planes;
2485 unsigned int tile_size = intel_tile_size(dev_priv);
2487 for (i = 0; i < num_planes; i++) {
2488 unsigned int width, height;
2489 unsigned int cpp, size;
2494 cpp = fb->format->cpp[i];
2495 width = drm_framebuffer_plane_width(fb->width, fb, i);
2496 height = drm_framebuffer_plane_height(fb->height, fb, i);
2498 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2500 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2505 if (is_ccs_modifier(fb->modifier) && i == 1) {
2506 int hsub = fb->format->hsub;
2507 int vsub = fb->format->vsub;
2508 int tile_width, tile_height;
2512 intel_tile_dims(fb, i, &tile_width, &tile_height);
2514 tile_height *= vsub;
2516 ccs_x = (x * hsub) % tile_width;
2517 ccs_y = (y * vsub) % tile_height;
2518 main_x = intel_fb->normal[0].x % tile_width;
2519 main_y = intel_fb->normal[0].y % tile_height;
2522 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2523 * x/y offsets must match between CCS and the main surface.
2525 if (main_x != ccs_x || main_y != ccs_y) {
2526 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2529 intel_fb->normal[0].x,
2530 intel_fb->normal[0].y,
2537 * The fence (if used) is aligned to the start of the object
2538 * so having the framebuffer wrap around across the edge of the
2539 * fenced region doesn't really work. We have no API to configure
2540 * the fence start offset within the object (nor could we probably
2541 * on gen2/3). So it's just easier if we just require that the
2542 * fb layout agrees with the fence layout. We already check that the
2543 * fb stride matches the fence stride elsewhere.
2545 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2546 (x + width) * cpp > fb->pitches[i]) {
2547 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2553 * First pixel of the framebuffer from
2554 * the start of the normal gtt mapping.
2556 intel_fb->normal[i].x = x;
2557 intel_fb->normal[i].y = y;
2559 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2563 offset /= tile_size;
2565 if (!is_surface_linear(fb->modifier, i)) {
2566 unsigned int tile_width, tile_height;
2567 unsigned int pitch_tiles;
2570 intel_tile_dims(fb, i, &tile_width, &tile_height);
2572 rot_info->plane[i].offset = offset;
2573 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2574 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2575 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2577 intel_fb->rotated[i].pitch =
2578 rot_info->plane[i].height * tile_height;
2580 /* how many tiles does this plane need */
2581 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2583 * If the plane isn't horizontally tile aligned,
2584 * we need one more tile.
2589 /* rotate the x/y offsets to match the GTT view */
2595 rot_info->plane[i].width * tile_width,
2596 rot_info->plane[i].height * tile_height,
2597 DRM_MODE_ROTATE_270);
2601 /* rotate the tile dimensions to match the GTT view */
2602 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2603 swap(tile_width, tile_height);
2606 * We only keep the x/y offsets, so push all of the
2607 * gtt offset into the x/y offsets.
2609 intel_adjust_tile_offset(&x, &y,
2610 tile_width, tile_height,
2611 tile_size, pitch_tiles,
2612 gtt_offset_rotated * tile_size, 0);
2614 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2617 * First pixel of the framebuffer from
2618 * the start of the rotated gtt mapping.
2620 intel_fb->rotated[i].x = x;
2621 intel_fb->rotated[i].y = y;
2623 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2624 x * cpp, tile_size);
2627 /* how many tiles in total needed in the bo */
2628 max_size = max(max_size, offset + size);
2631 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2632 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2633 mul_u32_u32(max_size, tile_size), obj->base.size);
2640 static int i9xx_format_to_fourcc(int format)
2643 case DISPPLANE_8BPP:
2644 return DRM_FORMAT_C8;
2645 case DISPPLANE_BGRX555:
2646 return DRM_FORMAT_XRGB1555;
2647 case DISPPLANE_BGRX565:
2648 return DRM_FORMAT_RGB565;
2650 case DISPPLANE_BGRX888:
2651 return DRM_FORMAT_XRGB8888;
2652 case DISPPLANE_RGBX888:
2653 return DRM_FORMAT_XBGR8888;
2654 case DISPPLANE_BGRX101010:
2655 return DRM_FORMAT_XRGB2101010;
2656 case DISPPLANE_RGBX101010:
2657 return DRM_FORMAT_XBGR2101010;
2661 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2664 case PLANE_CTL_FORMAT_RGB_565:
2665 return DRM_FORMAT_RGB565;
2666 case PLANE_CTL_FORMAT_NV12:
2667 return DRM_FORMAT_NV12;
2668 case PLANE_CTL_FORMAT_P010:
2669 return DRM_FORMAT_P010;
2670 case PLANE_CTL_FORMAT_P012:
2671 return DRM_FORMAT_P012;
2672 case PLANE_CTL_FORMAT_P016:
2673 return DRM_FORMAT_P016;
2674 case PLANE_CTL_FORMAT_Y210:
2675 return DRM_FORMAT_Y210;
2676 case PLANE_CTL_FORMAT_Y212:
2677 return DRM_FORMAT_Y212;
2678 case PLANE_CTL_FORMAT_Y216:
2679 return DRM_FORMAT_Y216;
2680 case PLANE_CTL_FORMAT_Y410:
2681 return DRM_FORMAT_XVYU2101010;
2682 case PLANE_CTL_FORMAT_Y412:
2683 return DRM_FORMAT_XVYU12_16161616;
2684 case PLANE_CTL_FORMAT_Y416:
2685 return DRM_FORMAT_XVYU16161616;
2687 case PLANE_CTL_FORMAT_XRGB_8888:
2690 return DRM_FORMAT_ABGR8888;
2692 return DRM_FORMAT_XBGR8888;
2695 return DRM_FORMAT_ARGB8888;
2697 return DRM_FORMAT_XRGB8888;
2699 case PLANE_CTL_FORMAT_XRGB_2101010:
2701 return DRM_FORMAT_XBGR2101010;
2703 return DRM_FORMAT_XRGB2101010;
2704 case PLANE_CTL_FORMAT_XRGB_16161616F:
2707 return DRM_FORMAT_ABGR16161616F;
2709 return DRM_FORMAT_XBGR16161616F;
2712 return DRM_FORMAT_ARGB16161616F;
2714 return DRM_FORMAT_XRGB16161616F;
2720 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2721 struct intel_initial_plane_config *plane_config)
2723 struct drm_device *dev = crtc->base.dev;
2724 struct drm_i915_private *dev_priv = to_i915(dev);
2725 struct drm_i915_gem_object *obj = NULL;
2726 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2727 struct drm_framebuffer *fb = &plane_config->fb->base;
2728 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2729 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2732 size_aligned -= base_aligned;
2734 if (plane_config->size == 0)
2737 /* If the FB is too big, just don't use it since fbdev is not very
2738 * important and we should probably use that space with FBC or other
2740 if (size_aligned * 2 > dev_priv->stolen_usable_size)
2743 switch (fb->modifier) {
2744 case DRM_FORMAT_MOD_LINEAR:
2745 case I915_FORMAT_MOD_X_TILED:
2746 case I915_FORMAT_MOD_Y_TILED:
2749 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2754 mutex_lock(&dev->struct_mutex);
2755 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2759 mutex_unlock(&dev->struct_mutex);
2763 switch (plane_config->tiling) {
2764 case I915_TILING_NONE:
2768 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
2771 MISSING_CASE(plane_config->tiling);
2775 mode_cmd.pixel_format = fb->format->format;
2776 mode_cmd.width = fb->width;
2777 mode_cmd.height = fb->height;
2778 mode_cmd.pitches[0] = fb->pitches[0];
2779 mode_cmd.modifier[0] = fb->modifier;
2780 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2782 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2783 DRM_DEBUG_KMS("intel fb init failed\n");
2788 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2792 i915_gem_object_put(obj);
2797 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2798 struct intel_plane_state *plane_state,
2801 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2803 plane_state->base.visible = visible;
2806 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2808 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2811 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
2813 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2814 struct drm_plane *plane;
2817 * Active_planes aliases if multiple "primary" or cursor planes
2818 * have been used on the same (or wrong) pipe. plane_mask uses
2819 * unique ids, hence we can use that to reconstruct active_planes.
2821 crtc_state->active_planes = 0;
2823 drm_for_each_plane_mask(plane, &dev_priv->drm,
2824 crtc_state->base.plane_mask)
2825 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2828 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2829 struct intel_plane *plane)
2831 struct intel_crtc_state *crtc_state =
2832 to_intel_crtc_state(crtc->base.state);
2833 struct intel_plane_state *plane_state =
2834 to_intel_plane_state(plane->base.state);
2836 DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
2837 plane->base.base.id, plane->base.name,
2838 crtc->base.base.id, crtc->base.name);
2840 intel_set_plane_visible(crtc_state, plane_state, false);
2841 fixup_active_planes(crtc_state);
2843 if (plane->id == PLANE_PRIMARY)
2844 intel_pre_disable_primary_noatomic(&crtc->base);
2846 intel_disable_plane(plane, crtc_state);
2850 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2851 struct intel_initial_plane_config *plane_config)
2853 struct drm_device *dev = intel_crtc->base.dev;
2854 struct drm_i915_private *dev_priv = to_i915(dev);
2856 struct drm_i915_gem_object *obj;
2857 struct drm_plane *primary = intel_crtc->base.primary;
2858 struct drm_plane_state *plane_state = primary->state;
2859 struct intel_plane *intel_plane = to_intel_plane(primary);
2860 struct intel_plane_state *intel_state =
2861 to_intel_plane_state(plane_state);
2862 struct drm_framebuffer *fb;
2864 if (!plane_config->fb)
2867 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2868 fb = &plane_config->fb->base;
2872 kfree(plane_config->fb);
2875 * Failed to alloc the obj, check to see if we should share
2876 * an fb with another CRTC instead
2878 for_each_crtc(dev, c) {
2879 struct intel_plane_state *state;
2881 if (c == &intel_crtc->base)
2884 if (!to_intel_crtc(c)->active)
2887 state = to_intel_plane_state(c->primary->state);
2891 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2892 fb = state->base.fb;
2893 drm_framebuffer_get(fb);
2899 * We've failed to reconstruct the BIOS FB. Current display state
2900 * indicates that the primary plane is visible, but has a NULL FB,
2901 * which will lead to problems later if we don't fix it up. The
2902 * simplest solution is to just disable the primary plane now and
2903 * pretend the BIOS never had it enabled.
2905 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2910 intel_state->base.rotation = plane_config->rotation;
2911 intel_fill_fb_ggtt_view(&intel_state->view, fb,
2912 intel_state->base.rotation);
2913 intel_state->color_plane[0].stride =
2914 intel_fb_pitch(fb, 0, intel_state->base.rotation);
2916 mutex_lock(&dev->struct_mutex);
2918 intel_pin_and_fence_fb_obj(fb,
2920 intel_plane_uses_fence(intel_state),
2921 &intel_state->flags);
2922 mutex_unlock(&dev->struct_mutex);
2923 if (IS_ERR(intel_state->vma)) {
2924 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2925 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2927 intel_state->vma = NULL;
2928 drm_framebuffer_put(fb);
2932 obj = intel_fb_obj(fb);
2933 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2935 plane_state->src_x = 0;
2936 plane_state->src_y = 0;
2937 plane_state->src_w = fb->width << 16;
2938 plane_state->src_h = fb->height << 16;
2940 plane_state->crtc_x = 0;
2941 plane_state->crtc_y = 0;
2942 plane_state->crtc_w = fb->width;
2943 plane_state->crtc_h = fb->height;
2945 intel_state->base.src = drm_plane_state_src(plane_state);
2946 intel_state->base.dst = drm_plane_state_dest(plane_state);
2948 if (i915_gem_object_is_tiled(obj))
2949 dev_priv->preserve_bios_swizzle = true;
2951 plane_state->fb = fb;
2952 plane_state->crtc = &intel_crtc->base;
2954 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2955 &obj->frontbuffer_bits);
2958 static int skl_max_plane_width(const struct drm_framebuffer *fb,
2960 unsigned int rotation)
2962 int cpp = fb->format->cpp[color_plane];
2964 switch (fb->modifier) {
2965 case DRM_FORMAT_MOD_LINEAR:
2966 case I915_FORMAT_MOD_X_TILED:
2979 case I915_FORMAT_MOD_Y_TILED_CCS:
2980 case I915_FORMAT_MOD_Yf_TILED_CCS:
2981 /* FIXME AUX plane? */
2982 case I915_FORMAT_MOD_Y_TILED:
2983 case I915_FORMAT_MOD_Yf_TILED:
2998 MISSING_CASE(fb->modifier);
3004 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3005 int main_x, int main_y, u32 main_offset)
3007 const struct drm_framebuffer *fb = plane_state->base.fb;
3008 int hsub = fb->format->hsub;
3009 int vsub = fb->format->vsub;
3010 int aux_x = plane_state->color_plane[1].x;
3011 int aux_y = plane_state->color_plane[1].y;
3012 u32 aux_offset = plane_state->color_plane[1].offset;
3013 u32 alignment = intel_surf_alignment(fb, 1);
3015 while (aux_offset >= main_offset && aux_y <= main_y) {
3018 if (aux_x == main_x && aux_y == main_y)
3021 if (aux_offset == 0)
3026 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3027 aux_offset, aux_offset - alignment);
3028 aux_x = x * hsub + aux_x % hsub;
3029 aux_y = y * vsub + aux_y % vsub;
3032 if (aux_x != main_x || aux_y != main_y)
3035 plane_state->color_plane[1].offset = aux_offset;
3036 plane_state->color_plane[1].x = aux_x;
3037 plane_state->color_plane[1].y = aux_y;
3042 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3044 const struct drm_framebuffer *fb = plane_state->base.fb;
3045 unsigned int rotation = plane_state->base.rotation;
3046 int x = plane_state->base.src.x1 >> 16;
3047 int y = plane_state->base.src.y1 >> 16;
3048 int w = drm_rect_width(&plane_state->base.src) >> 16;
3049 int h = drm_rect_height(&plane_state->base.src) >> 16;
3050 int max_width = skl_max_plane_width(fb, 0, rotation);
3051 int max_height = 4096;
3052 u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3054 if (w > max_width || h > max_height) {
3055 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3056 w, h, max_width, max_height);
3060 intel_add_fb_offsets(&x, &y, plane_state, 0);
3061 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3062 alignment = intel_surf_alignment(fb, 0);
3065 * AUX surface offset is specified as the distance from the
3066 * main surface offset, and it must be non-negative. Make
3067 * sure that is what we will get.
3069 if (offset > aux_offset)
3070 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3071 offset, aux_offset & ~(alignment - 1));
3074 * When using an X-tiled surface, the plane blows up
3075 * if the x offset + width exceed the stride.
3077 * TODO: linear and Y-tiled seem fine, Yf untested,
3079 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3080 int cpp = fb->format->cpp[0];
3082 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3084 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3088 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3089 offset, offset - alignment);
3094 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3095 * they match with the main surface x/y offsets.
3097 if (is_ccs_modifier(fb->modifier)) {
3098 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3102 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3103 offset, offset - alignment);
3106 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3107 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3112 plane_state->color_plane[0].offset = offset;
3113 plane_state->color_plane[0].x = x;
3114 plane_state->color_plane[0].y = y;
3119 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3121 const struct drm_framebuffer *fb = plane_state->base.fb;
3122 unsigned int rotation = plane_state->base.rotation;
3123 int max_width = skl_max_plane_width(fb, 1, rotation);
3124 int max_height = 4096;
3125 int x = plane_state->base.src.x1 >> 17;
3126 int y = plane_state->base.src.y1 >> 17;
3127 int w = drm_rect_width(&plane_state->base.src) >> 17;
3128 int h = drm_rect_height(&plane_state->base.src) >> 17;
3131 intel_add_fb_offsets(&x, &y, plane_state, 1);
3132 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3134 /* FIXME not quite sure how/if these apply to the chroma plane */
3135 if (w > max_width || h > max_height) {
3136 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3137 w, h, max_width, max_height);
3141 plane_state->color_plane[1].offset = offset;
3142 plane_state->color_plane[1].x = x;
3143 plane_state->color_plane[1].y = y;
3148 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3150 const struct drm_framebuffer *fb = plane_state->base.fb;
3151 int src_x = plane_state->base.src.x1 >> 16;
3152 int src_y = plane_state->base.src.y1 >> 16;
3153 int hsub = fb->format->hsub;
3154 int vsub = fb->format->vsub;
3155 int x = src_x / hsub;
3156 int y = src_y / vsub;
3159 intel_add_fb_offsets(&x, &y, plane_state, 1);
3160 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3162 plane_state->color_plane[1].offset = offset;
3163 plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3164 plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3169 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3171 const struct drm_framebuffer *fb = plane_state->base.fb;
3172 unsigned int rotation = plane_state->base.rotation;
3175 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3176 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3177 plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
3179 ret = intel_plane_check_stride(plane_state);
3183 if (!plane_state->base.visible)
3186 /* Rotate src coordinates to match rotated GTT view */
3187 if (drm_rotation_90_or_270(rotation))
3188 drm_rect_rotate(&plane_state->base.src,
3189 fb->width << 16, fb->height << 16,
3190 DRM_MODE_ROTATE_270);
3193 * Handle the AUX surface first since
3194 * the main surface setup depends on it.
3196 if (is_planar_yuv_format(fb->format->format)) {
3197 ret = skl_check_nv12_aux_surface(plane_state);
3200 } else if (is_ccs_modifier(fb->modifier)) {
3201 ret = skl_check_ccs_aux_surface(plane_state);
3205 plane_state->color_plane[1].offset = ~0xfff;
3206 plane_state->color_plane[1].x = 0;
3207 plane_state->color_plane[1].y = 0;
3210 ret = skl_check_main_surface(plane_state);
3218 i9xx_plane_max_stride(struct intel_plane *plane,
3219 u32 pixel_format, u64 modifier,
3220 unsigned int rotation)
3222 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3224 if (!HAS_GMCH(dev_priv)) {
3226 } else if (INTEL_GEN(dev_priv) >= 4) {
3227 if (modifier == I915_FORMAT_MOD_X_TILED)
3231 } else if (INTEL_GEN(dev_priv) >= 3) {
3232 if (modifier == I915_FORMAT_MOD_X_TILED)
3237 if (plane->i9xx_plane == PLANE_C)
3244 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3246 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3247 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3250 if (crtc_state->gamma_enable)
3251 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3253 if (crtc_state->csc_enable)
3254 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3256 if (INTEL_GEN(dev_priv) < 5)
3257 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3262 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3263 const struct intel_plane_state *plane_state)
3265 struct drm_i915_private *dev_priv =
3266 to_i915(plane_state->base.plane->dev);
3267 const struct drm_framebuffer *fb = plane_state->base.fb;
3268 unsigned int rotation = plane_state->base.rotation;
3271 dspcntr = DISPLAY_PLANE_ENABLE;
3273 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3274 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3275 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3277 switch (fb->format->format) {
3279 dspcntr |= DISPPLANE_8BPP;
3281 case DRM_FORMAT_XRGB1555:
3282 dspcntr |= DISPPLANE_BGRX555;
3284 case DRM_FORMAT_RGB565:
3285 dspcntr |= DISPPLANE_BGRX565;
3287 case DRM_FORMAT_XRGB8888:
3288 dspcntr |= DISPPLANE_BGRX888;
3290 case DRM_FORMAT_XBGR8888:
3291 dspcntr |= DISPPLANE_RGBX888;
3293 case DRM_FORMAT_XRGB2101010:
3294 dspcntr |= DISPPLANE_BGRX101010;
3296 case DRM_FORMAT_XBGR2101010:
3297 dspcntr |= DISPPLANE_RGBX101010;
3300 MISSING_CASE(fb->format->format);
3304 if (INTEL_GEN(dev_priv) >= 4 &&
3305 fb->modifier == I915_FORMAT_MOD_X_TILED)
3306 dspcntr |= DISPPLANE_TILED;
3308 if (rotation & DRM_MODE_ROTATE_180)
3309 dspcntr |= DISPPLANE_ROTATE_180;
3311 if (rotation & DRM_MODE_REFLECT_X)
3312 dspcntr |= DISPPLANE_MIRROR;
3317 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3319 struct drm_i915_private *dev_priv =
3320 to_i915(plane_state->base.plane->dev);
3321 const struct drm_framebuffer *fb = plane_state->base.fb;
3322 unsigned int rotation = plane_state->base.rotation;
3323 int src_x = plane_state->base.src.x1 >> 16;
3324 int src_y = plane_state->base.src.y1 >> 16;
3328 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3329 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3331 ret = intel_plane_check_stride(plane_state);
3335 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3337 if (INTEL_GEN(dev_priv) >= 4)
3338 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3343 /* HSW/BDW do this automagically in hardware */
3344 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3345 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3346 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3348 if (rotation & DRM_MODE_ROTATE_180) {
3351 } else if (rotation & DRM_MODE_REFLECT_X) {
3356 plane_state->color_plane[0].offset = offset;
3357 plane_state->color_plane[0].x = src_x;
3358 plane_state->color_plane[0].y = src_y;
3364 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3365 struct intel_plane_state *plane_state)
3369 ret = chv_plane_check_rotation(plane_state);
3373 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
3375 DRM_PLANE_HELPER_NO_SCALING,
3376 DRM_PLANE_HELPER_NO_SCALING,
3381 if (!plane_state->base.visible)
3384 ret = intel_plane_check_src_coordinates(plane_state);
3388 ret = i9xx_check_plane_surface(plane_state);
3392 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3397 static void i9xx_update_plane(struct intel_plane *plane,
3398 const struct intel_crtc_state *crtc_state,
3399 const struct intel_plane_state *plane_state)
3401 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3402 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3404 int x = plane_state->color_plane[0].x;
3405 int y = plane_state->color_plane[0].y;
3406 unsigned long irqflags;
3410 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3412 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3414 if (INTEL_GEN(dev_priv) >= 4)
3415 dspaddr_offset = plane_state->color_plane[0].offset;
3417 dspaddr_offset = linear_offset;
3419 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3421 I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3423 if (INTEL_GEN(dev_priv) < 4) {
3424 /* pipesrc and dspsize control the size that is scaled from,
3425 * which should always be the user's requested size.
3427 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3428 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3429 ((crtc_state->pipe_src_h - 1) << 16) |
3430 (crtc_state->pipe_src_w - 1));
3431 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3432 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3433 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3434 ((crtc_state->pipe_src_h - 1) << 16) |
3435 (crtc_state->pipe_src_w - 1));
3436 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3439 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3440 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3441 } else if (INTEL_GEN(dev_priv) >= 4) {
3442 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3443 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3447 * The control register self-arms if the plane was previously
3448 * disabled. Try to make the plane enable atomic by writing
3449 * the control register just before the surface register.
3451 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3452 if (INTEL_GEN(dev_priv) >= 4)
3453 I915_WRITE_FW(DSPSURF(i9xx_plane),
3454 intel_plane_ggtt_offset(plane_state) +
3457 I915_WRITE_FW(DSPADDR(i9xx_plane),
3458 intel_plane_ggtt_offset(plane_state) +
3461 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3464 static void i9xx_disable_plane(struct intel_plane *plane,
3465 const struct intel_crtc_state *crtc_state)
3467 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3468 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3469 unsigned long irqflags;
3473 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3474 * enable on ilk+ affect the pipe bottom color as
3475 * well, so we must configure them even if the plane
3478 * On pre-g4x there is no way to gamma correct the
3479 * pipe bottom color but we'll keep on doing this
3480 * anyway so that the crtc state readout works correctly.
3482 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
3484 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3486 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3487 if (INTEL_GEN(dev_priv) >= 4)
3488 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3490 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3492 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3495 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3498 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3499 enum intel_display_power_domain power_domain;
3500 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3501 intel_wakeref_t wakeref;
3506 * Not 100% correct for planes that can move between pipes,
3507 * but that's only the case for gen2-4 which don't have any
3508 * display power wells.
3510 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3511 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3515 val = I915_READ(DSPCNTR(i9xx_plane));
3517 ret = val & DISPLAY_PLANE_ENABLE;
3519 if (INTEL_GEN(dev_priv) >= 5)
3520 *pipe = plane->pipe;
3522 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3523 DISPPLANE_SEL_PIPE_SHIFT;
3525 intel_display_power_put(dev_priv, power_domain, wakeref);
3531 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
3533 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3536 return intel_tile_width_bytes(fb, color_plane);
3539 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3541 struct drm_device *dev = intel_crtc->base.dev;
3542 struct drm_i915_private *dev_priv = to_i915(dev);
3544 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3545 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3546 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3550 * This function detaches (aka. unbinds) unused scalers in hardware
3552 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
3554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3555 const struct intel_crtc_scaler_state *scaler_state =
3556 &crtc_state->scaler_state;
3559 /* loop through and disable scalers that aren't in use */
3560 for (i = 0; i < intel_crtc->num_scalers; i++) {
3561 if (!scaler_state->scalers[i].in_use)
3562 skl_detach_scaler(intel_crtc, i);
3566 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
3567 int color_plane, unsigned int rotation)
3570 * The stride is either expressed as a multiple of 64 bytes chunks for
3571 * linear buffers or in number of tiles for tiled buffers.
3573 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3575 else if (drm_rotation_90_or_270(rotation))
3576 return intel_tile_height(fb, color_plane);
3578 return intel_tile_width_bytes(fb, color_plane);
3581 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
3584 const struct drm_framebuffer *fb = plane_state->base.fb;
3585 unsigned int rotation = plane_state->base.rotation;
3586 u32 stride = plane_state->color_plane[color_plane].stride;
3588 if (color_plane >= fb->format->num_planes)
3591 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
3594 static u32 skl_plane_ctl_format(u32 pixel_format)
3596 switch (pixel_format) {
3598 return PLANE_CTL_FORMAT_INDEXED;
3599 case DRM_FORMAT_RGB565:
3600 return PLANE_CTL_FORMAT_RGB_565;
3601 case DRM_FORMAT_XBGR8888:
3602 case DRM_FORMAT_ABGR8888:
3603 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3604 case DRM_FORMAT_XRGB8888:
3605 case DRM_FORMAT_ARGB8888:
3606 return PLANE_CTL_FORMAT_XRGB_8888;
3607 case DRM_FORMAT_XRGB2101010:
3608 return PLANE_CTL_FORMAT_XRGB_2101010;
3609 case DRM_FORMAT_XBGR2101010:
3610 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3611 case DRM_FORMAT_XBGR16161616F:
3612 case DRM_FORMAT_ABGR16161616F:
3613 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
3614 case DRM_FORMAT_XRGB16161616F:
3615 case DRM_FORMAT_ARGB16161616F:
3616 return PLANE_CTL_FORMAT_XRGB_16161616F;
3617 case DRM_FORMAT_YUYV:
3618 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3619 case DRM_FORMAT_YVYU:
3620 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3621 case DRM_FORMAT_UYVY:
3622 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3623 case DRM_FORMAT_VYUY:
3624 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3625 case DRM_FORMAT_NV12:
3626 return PLANE_CTL_FORMAT_NV12;
3627 case DRM_FORMAT_P010:
3628 return PLANE_CTL_FORMAT_P010;
3629 case DRM_FORMAT_P012:
3630 return PLANE_CTL_FORMAT_P012;
3631 case DRM_FORMAT_P016:
3632 return PLANE_CTL_FORMAT_P016;
3633 case DRM_FORMAT_Y210:
3634 return PLANE_CTL_FORMAT_Y210;
3635 case DRM_FORMAT_Y212:
3636 return PLANE_CTL_FORMAT_Y212;
3637 case DRM_FORMAT_Y216:
3638 return PLANE_CTL_FORMAT_Y216;
3639 case DRM_FORMAT_XVYU2101010:
3640 return PLANE_CTL_FORMAT_Y410;
3641 case DRM_FORMAT_XVYU12_16161616:
3642 return PLANE_CTL_FORMAT_Y412;
3643 case DRM_FORMAT_XVYU16161616:
3644 return PLANE_CTL_FORMAT_Y416;
3646 MISSING_CASE(pixel_format);
3652 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
3654 if (!plane_state->base.fb->format->has_alpha)
3655 return PLANE_CTL_ALPHA_DISABLE;
3657 switch (plane_state->base.pixel_blend_mode) {
3658 case DRM_MODE_BLEND_PIXEL_NONE:
3659 return PLANE_CTL_ALPHA_DISABLE;
3660 case DRM_MODE_BLEND_PREMULTI:
3661 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3662 case DRM_MODE_BLEND_COVERAGE:
3663 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
3665 MISSING_CASE(plane_state->base.pixel_blend_mode);
3666 return PLANE_CTL_ALPHA_DISABLE;
3670 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
3672 if (!plane_state->base.fb->format->has_alpha)
3673 return PLANE_COLOR_ALPHA_DISABLE;
3675 switch (plane_state->base.pixel_blend_mode) {
3676 case DRM_MODE_BLEND_PIXEL_NONE:
3677 return PLANE_COLOR_ALPHA_DISABLE;
3678 case DRM_MODE_BLEND_PREMULTI:
3679 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3680 case DRM_MODE_BLEND_COVERAGE:
3681 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
3683 MISSING_CASE(plane_state->base.pixel_blend_mode);
3684 return PLANE_COLOR_ALPHA_DISABLE;
3688 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
3690 switch (fb_modifier) {
3691 case DRM_FORMAT_MOD_LINEAR:
3693 case I915_FORMAT_MOD_X_TILED:
3694 return PLANE_CTL_TILED_X;
3695 case I915_FORMAT_MOD_Y_TILED:
3696 return PLANE_CTL_TILED_Y;
3697 case I915_FORMAT_MOD_Y_TILED_CCS:
3698 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3699 case I915_FORMAT_MOD_Yf_TILED:
3700 return PLANE_CTL_TILED_YF;
3701 case I915_FORMAT_MOD_Yf_TILED_CCS:
3702 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3704 MISSING_CASE(fb_modifier);
3710 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3713 case DRM_MODE_ROTATE_0:
3716 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3717 * while i915 HW rotation is clockwise, thats why this swapping.
3719 case DRM_MODE_ROTATE_90:
3720 return PLANE_CTL_ROTATE_270;
3721 case DRM_MODE_ROTATE_180:
3722 return PLANE_CTL_ROTATE_180;
3723 case DRM_MODE_ROTATE_270:
3724 return PLANE_CTL_ROTATE_90;
3726 MISSING_CASE(rotate);
3732 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3737 case DRM_MODE_REFLECT_X:
3738 return PLANE_CTL_FLIP_HORIZONTAL;
3739 case DRM_MODE_REFLECT_Y:
3741 MISSING_CASE(reflect);
3747 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3749 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3752 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3755 if (crtc_state->gamma_enable)
3756 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
3758 if (crtc_state->csc_enable)
3759 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
3764 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3765 const struct intel_plane_state *plane_state)
3767 struct drm_i915_private *dev_priv =
3768 to_i915(plane_state->base.plane->dev);
3769 const struct drm_framebuffer *fb = plane_state->base.fb;
3770 unsigned int rotation = plane_state->base.rotation;
3771 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3774 plane_ctl = PLANE_CTL_ENABLE;
3776 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3777 plane_ctl |= skl_plane_ctl_alpha(plane_state);
3778 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3780 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3781 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3783 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3784 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3787 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3788 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3789 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3791 if (INTEL_GEN(dev_priv) >= 10)
3792 plane_ctl |= cnl_plane_ctl_flip(rotation &
3793 DRM_MODE_REFLECT_MASK);
3795 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3796 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3797 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3798 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3803 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
3805 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3806 u32 plane_color_ctl = 0;
3808 if (INTEL_GEN(dev_priv) >= 11)
3809 return plane_color_ctl;
3811 if (crtc_state->gamma_enable)
3812 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3814 if (crtc_state->csc_enable)
3815 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3817 return plane_color_ctl;
3820 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3821 const struct intel_plane_state *plane_state)
3823 struct drm_i915_private *dev_priv =
3824 to_i915(plane_state->base.plane->dev);
3825 const struct drm_framebuffer *fb = plane_state->base.fb;
3826 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3827 u32 plane_color_ctl = 0;
3829 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3830 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
3832 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
3833 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3834 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3836 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3838 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3839 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3840 } else if (fb->format->is_yuv) {
3841 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
3844 return plane_color_ctl;
3848 __intel_display_resume(struct drm_device *dev,
3849 struct drm_atomic_state *state,
3850 struct drm_modeset_acquire_ctx *ctx)
3852 struct drm_crtc_state *crtc_state;
3853 struct drm_crtc *crtc;
3856 intel_modeset_setup_hw_state(dev, ctx);
3857 i915_redisable_vga(to_i915(dev));
3863 * We've duplicated the state, pointers to the old state are invalid.
3865 * Don't attempt to use the old state until we commit the duplicated state.
3867 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3869 * Force recalculation even if we restore
3870 * current state. With fast modeset this may not result
3871 * in a modeset when the state is compatible.
3873 crtc_state->mode_changed = true;
3876 /* ignore any reset values/BIOS leftovers in the WM registers */
3877 if (!HAS_GMCH(to_i915(dev)))
3878 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3880 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3882 WARN_ON(ret == -EDEADLK);
3886 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3888 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
3889 intel_has_gpu_reset(dev_priv));
3892 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3894 struct drm_device *dev = &dev_priv->drm;
3895 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3896 struct drm_atomic_state *state;
3899 /* reset doesn't touch the display */
3900 if (!i915_modparams.force_reset_modeset_test &&
3901 !gpu_reset_clobbers_display(dev_priv))
3904 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3905 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3906 wake_up_all(&dev_priv->gpu_error.wait_queue);
3908 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3909 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3910 i915_gem_set_wedged(dev_priv);
3914 * Need mode_config.mutex so that we don't
3915 * trample ongoing ->detect() and whatnot.
3917 mutex_lock(&dev->mode_config.mutex);
3918 drm_modeset_acquire_init(ctx, 0);
3920 ret = drm_modeset_lock_all_ctx(dev, ctx);
3921 if (ret != -EDEADLK)
3924 drm_modeset_backoff(ctx);
3927 * Disabling the crtcs gracefully seems nicer. Also the
3928 * g33 docs say we should at least disable all the planes.
3930 state = drm_atomic_helper_duplicate_state(dev, ctx);
3931 if (IS_ERR(state)) {
3932 ret = PTR_ERR(state);
3933 DRM_ERROR("Duplicating state failed with %i\n", ret);
3937 ret = drm_atomic_helper_disable_all(dev, ctx);
3939 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3940 drm_atomic_state_put(state);
3944 dev_priv->modeset_restore_state = state;
3945 state->acquire_ctx = ctx;
3948 void intel_finish_reset(struct drm_i915_private *dev_priv)
3950 struct drm_device *dev = &dev_priv->drm;
3951 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3952 struct drm_atomic_state *state;
3955 /* reset doesn't touch the display */
3956 if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
3959 state = fetch_and_zero(&dev_priv->modeset_restore_state);
3963 /* reset doesn't touch the display */
3964 if (!gpu_reset_clobbers_display(dev_priv)) {
3965 /* for testing only restore the display */
3966 ret = __intel_display_resume(dev, state, ctx);
3968 DRM_ERROR("Restoring old state failed with %i\n", ret);
3971 * The display has been reset as well,
3972 * so need a full re-initialization.
3974 intel_pps_unlock_regs_wa(dev_priv);
3975 intel_modeset_init_hw(dev);
3976 intel_init_clock_gating(dev_priv);
3978 spin_lock_irq(&dev_priv->irq_lock);
3979 if (dev_priv->display.hpd_irq_setup)
3980 dev_priv->display.hpd_irq_setup(dev_priv);
3981 spin_unlock_irq(&dev_priv->irq_lock);
3983 ret = __intel_display_resume(dev, state, ctx);
3985 DRM_ERROR("Restoring old state failed with %i\n", ret);
3987 intel_hpd_init(dev_priv);
3990 drm_atomic_state_put(state);
3992 drm_modeset_drop_locks(ctx);
3993 drm_modeset_acquire_fini(ctx);
3994 mutex_unlock(&dev->mode_config.mutex);
3996 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3999 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4001 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4002 enum pipe pipe = crtc->pipe;
4005 tmp = I915_READ(PIPE_CHICKEN(pipe));
4008 * Display WA #1153: icl
4009 * enable hardware to bypass the alpha math
4010 * and rounding for per-pixel values 00 and 0xff
4012 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4014 * Display WA # 1605353570: icl
4015 * Set the pixel rounding bit to 1 for allowing
4016 * passthrough of Frame buffer pixels unmodified
4019 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4020 I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4023 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
4024 const struct intel_crtc_state *new_crtc_state)
4026 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
4027 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4029 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
4030 crtc->base.mode = new_crtc_state->base.mode;
4033 * Update pipe size and adjust fitter if needed: the reason for this is
4034 * that in compute_mode_changes we check the native mode (not the pfit
4035 * mode) to see if we can flip rather than do a full mode set. In the
4036 * fastboot case, we'll flip, but if we don't update the pipesrc and
4037 * pfit state, we'll end up with a big fb scanned out into the wrong
4041 I915_WRITE(PIPESRC(crtc->pipe),
4042 ((new_crtc_state->pipe_src_w - 1) << 16) |
4043 (new_crtc_state->pipe_src_h - 1));
4045 /* on skylake this is done by detaching scalers */
4046 if (INTEL_GEN(dev_priv) >= 9) {
4047 skl_detach_scalers(new_crtc_state);
4049 if (new_crtc_state->pch_pfit.enabled)
4050 skylake_pfit_enable(new_crtc_state);
4051 } else if (HAS_PCH_SPLIT(dev_priv)) {
4052 if (new_crtc_state->pch_pfit.enabled)
4053 ironlake_pfit_enable(new_crtc_state);
4054 else if (old_crtc_state->pch_pfit.enabled)
4055 ironlake_pfit_disable(old_crtc_state);
4058 if (INTEL_GEN(dev_priv) >= 11)
4059 icl_set_pipe_chicken(crtc);
4062 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4064 struct drm_device *dev = crtc->base.dev;
4065 struct drm_i915_private *dev_priv = to_i915(dev);
4066 int pipe = crtc->pipe;
4070 /* enable normal train */
4071 reg = FDI_TX_CTL(pipe);
4072 temp = I915_READ(reg);
4073 if (IS_IVYBRIDGE(dev_priv)) {
4074 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4075 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4077 temp &= ~FDI_LINK_TRAIN_NONE;
4078 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4080 I915_WRITE(reg, temp);
4082 reg = FDI_RX_CTL(pipe);
4083 temp = I915_READ(reg);
4084 if (HAS_PCH_CPT(dev_priv)) {
4085 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4086 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4088 temp &= ~FDI_LINK_TRAIN_NONE;
4089 temp |= FDI_LINK_TRAIN_NONE;
4091 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4093 /* wait one idle pattern time */
4097 /* IVB wants error correction enabled */
4098 if (IS_IVYBRIDGE(dev_priv))
4099 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4100 FDI_FE_ERRC_ENABLE);
4103 /* The FDI link training functions for ILK/Ibexpeak. */
4104 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4105 const struct intel_crtc_state *crtc_state)
4107 struct drm_device *dev = crtc->base.dev;
4108 struct drm_i915_private *dev_priv = to_i915(dev);
4109 int pipe = crtc->pipe;
4113 /* FDI needs bits from pipe first */
4114 assert_pipe_enabled(dev_priv, pipe);
4116 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4118 reg = FDI_RX_IMR(pipe);
4119 temp = I915_READ(reg);
4120 temp &= ~FDI_RX_SYMBOL_LOCK;
4121 temp &= ~FDI_RX_BIT_LOCK;
4122 I915_WRITE(reg, temp);
4126 /* enable CPU FDI TX and PCH FDI RX */
4127 reg = FDI_TX_CTL(pipe);
4128 temp = I915_READ(reg);
4129 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4130 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4131 temp &= ~FDI_LINK_TRAIN_NONE;
4132 temp |= FDI_LINK_TRAIN_PATTERN_1;
4133 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4135 reg = FDI_RX_CTL(pipe);
4136 temp = I915_READ(reg);
4137 temp &= ~FDI_LINK_TRAIN_NONE;
4138 temp |= FDI_LINK_TRAIN_PATTERN_1;
4139 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4144 /* Ironlake workaround, enable clock pointer after FDI enable*/
4145 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4146 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4147 FDI_RX_PHASE_SYNC_POINTER_EN);
4149 reg = FDI_RX_IIR(pipe);
4150 for (tries = 0; tries < 5; tries++) {
4151 temp = I915_READ(reg);
4152 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4154 if ((temp & FDI_RX_BIT_LOCK)) {
4155 DRM_DEBUG_KMS("FDI train 1 done.\n");
4156 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4161 DRM_ERROR("FDI train 1 fail!\n");
4164 reg = FDI_TX_CTL(pipe);
4165 temp = I915_READ(reg);
4166 temp &= ~FDI_LINK_TRAIN_NONE;
4167 temp |= FDI_LINK_TRAIN_PATTERN_2;
4168 I915_WRITE(reg, temp);
4170 reg = FDI_RX_CTL(pipe);
4171 temp = I915_READ(reg);
4172 temp &= ~FDI_LINK_TRAIN_NONE;
4173 temp |= FDI_LINK_TRAIN_PATTERN_2;
4174 I915_WRITE(reg, temp);
4179 reg = FDI_RX_IIR(pipe);
4180 for (tries = 0; tries < 5; tries++) {
4181 temp = I915_READ(reg);
4182 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4184 if (temp & FDI_RX_SYMBOL_LOCK) {
4185 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4186 DRM_DEBUG_KMS("FDI train 2 done.\n");
4191 DRM_ERROR("FDI train 2 fail!\n");
4193 DRM_DEBUG_KMS("FDI train done\n");
4197 static const int snb_b_fdi_train_param[] = {
4198 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4199 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4200 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4201 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4204 /* The FDI link training functions for SNB/Cougarpoint. */
4205 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4206 const struct intel_crtc_state *crtc_state)
4208 struct drm_device *dev = crtc->base.dev;
4209 struct drm_i915_private *dev_priv = to_i915(dev);
4210 int pipe = crtc->pipe;
4214 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4216 reg = FDI_RX_IMR(pipe);
4217 temp = I915_READ(reg);
4218 temp &= ~FDI_RX_SYMBOL_LOCK;
4219 temp &= ~FDI_RX_BIT_LOCK;
4220 I915_WRITE(reg, temp);
4225 /* enable CPU FDI TX and PCH FDI RX */
4226 reg = FDI_TX_CTL(pipe);
4227 temp = I915_READ(reg);
4228 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4229 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4230 temp &= ~FDI_LINK_TRAIN_NONE;
4231 temp |= FDI_LINK_TRAIN_PATTERN_1;
4232 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4234 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4235 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4237 I915_WRITE(FDI_RX_MISC(pipe),
4238 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4240 reg = FDI_RX_CTL(pipe);
4241 temp = I915_READ(reg);
4242 if (HAS_PCH_CPT(dev_priv)) {
4243 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4244 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4246 temp &= ~FDI_LINK_TRAIN_NONE;
4247 temp |= FDI_LINK_TRAIN_PATTERN_1;
4249 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4254 for (i = 0; i < 4; i++) {
4255 reg = FDI_TX_CTL(pipe);
4256 temp = I915_READ(reg);
4257 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4258 temp |= snb_b_fdi_train_param[i];
4259 I915_WRITE(reg, temp);
4264 for (retry = 0; retry < 5; retry++) {
4265 reg = FDI_RX_IIR(pipe);
4266 temp = I915_READ(reg);
4267 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4268 if (temp & FDI_RX_BIT_LOCK) {
4269 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4270 DRM_DEBUG_KMS("FDI train 1 done.\n");
4279 DRM_ERROR("FDI train 1 fail!\n");
4282 reg = FDI_TX_CTL(pipe);
4283 temp = I915_READ(reg);
4284 temp &= ~FDI_LINK_TRAIN_NONE;
4285 temp |= FDI_LINK_TRAIN_PATTERN_2;
4286 if (IS_GEN(dev_priv, 6)) {
4287 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4289 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4291 I915_WRITE(reg, temp);
4293 reg = FDI_RX_CTL(pipe);
4294 temp = I915_READ(reg);
4295 if (HAS_PCH_CPT(dev_priv)) {
4296 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4297 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4299 temp &= ~FDI_LINK_TRAIN_NONE;
4300 temp |= FDI_LINK_TRAIN_PATTERN_2;
4302 I915_WRITE(reg, temp);
4307 for (i = 0; i < 4; i++) {
4308 reg = FDI_TX_CTL(pipe);
4309 temp = I915_READ(reg);
4310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4311 temp |= snb_b_fdi_train_param[i];
4312 I915_WRITE(reg, temp);
4317 for (retry = 0; retry < 5; retry++) {
4318 reg = FDI_RX_IIR(pipe);
4319 temp = I915_READ(reg);
4320 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4321 if (temp & FDI_RX_SYMBOL_LOCK) {
4322 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4323 DRM_DEBUG_KMS("FDI train 2 done.\n");
4332 DRM_ERROR("FDI train 2 fail!\n");
4334 DRM_DEBUG_KMS("FDI train done.\n");
4337 /* Manual link training for Ivy Bridge A0 parts */
4338 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4339 const struct intel_crtc_state *crtc_state)
4341 struct drm_device *dev = crtc->base.dev;
4342 struct drm_i915_private *dev_priv = to_i915(dev);
4343 int pipe = crtc->pipe;
4347 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4349 reg = FDI_RX_IMR(pipe);
4350 temp = I915_READ(reg);
4351 temp &= ~FDI_RX_SYMBOL_LOCK;
4352 temp &= ~FDI_RX_BIT_LOCK;
4353 I915_WRITE(reg, temp);
4358 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4359 I915_READ(FDI_RX_IIR(pipe)));
4361 /* Try each vswing and preemphasis setting twice before moving on */
4362 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4363 /* disable first in case we need to retry */
4364 reg = FDI_TX_CTL(pipe);
4365 temp = I915_READ(reg);
4366 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4367 temp &= ~FDI_TX_ENABLE;
4368 I915_WRITE(reg, temp);
4370 reg = FDI_RX_CTL(pipe);
4371 temp = I915_READ(reg);
4372 temp &= ~FDI_LINK_TRAIN_AUTO;
4373 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4374 temp &= ~FDI_RX_ENABLE;
4375 I915_WRITE(reg, temp);
4377 /* enable CPU FDI TX and PCH FDI RX */
4378 reg = FDI_TX_CTL(pipe);
4379 temp = I915_READ(reg);
4380 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4381 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4382 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4383 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4384 temp |= snb_b_fdi_train_param[j/2];
4385 temp |= FDI_COMPOSITE_SYNC;
4386 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4388 I915_WRITE(FDI_RX_MISC(pipe),
4389 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4391 reg = FDI_RX_CTL(pipe);
4392 temp = I915_READ(reg);
4393 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4394 temp |= FDI_COMPOSITE_SYNC;
4395 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4398 udelay(1); /* should be 0.5us */
4400 for (i = 0; i < 4; i++) {
4401 reg = FDI_RX_IIR(pipe);
4402 temp = I915_READ(reg);
4403 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4405 if (temp & FDI_RX_BIT_LOCK ||
4406 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4407 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4408 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4412 udelay(1); /* should be 0.5us */
4415 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4420 reg = FDI_TX_CTL(pipe);
4421 temp = I915_READ(reg);
4422 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4423 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4424 I915_WRITE(reg, temp);
4426 reg = FDI_RX_CTL(pipe);
4427 temp = I915_READ(reg);
4428 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4429 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4430 I915_WRITE(reg, temp);
4433 udelay(2); /* should be 1.5us */
4435 for (i = 0; i < 4; i++) {
4436 reg = FDI_RX_IIR(pipe);
4437 temp = I915_READ(reg);
4438 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4440 if (temp & FDI_RX_SYMBOL_LOCK ||
4441 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4442 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4443 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4447 udelay(2); /* should be 1.5us */
4450 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4454 DRM_DEBUG_KMS("FDI train done.\n");
4457 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4460 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4461 int pipe = intel_crtc->pipe;
4465 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4466 reg = FDI_RX_CTL(pipe);
4467 temp = I915_READ(reg);
4468 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4469 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4470 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4471 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4476 /* Switch from Rawclk to PCDclk */
4477 temp = I915_READ(reg);
4478 I915_WRITE(reg, temp | FDI_PCDCLK);
4483 /* Enable CPU FDI TX PLL, always on for Ironlake */
4484 reg = FDI_TX_CTL(pipe);
4485 temp = I915_READ(reg);
4486 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4487 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4494 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4496 struct drm_device *dev = intel_crtc->base.dev;
4497 struct drm_i915_private *dev_priv = to_i915(dev);
4498 int pipe = intel_crtc->pipe;
4502 /* Switch from PCDclk to Rawclk */
4503 reg = FDI_RX_CTL(pipe);
4504 temp = I915_READ(reg);
4505 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4507 /* Disable CPU FDI TX PLL */
4508 reg = FDI_TX_CTL(pipe);
4509 temp = I915_READ(reg);
4510 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4515 reg = FDI_RX_CTL(pipe);
4516 temp = I915_READ(reg);
4517 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4519 /* Wait for the clocks to turn off. */
4524 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4526 struct drm_device *dev = crtc->dev;
4527 struct drm_i915_private *dev_priv = to_i915(dev);
4528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4529 int pipe = intel_crtc->pipe;
4533 /* disable CPU FDI tx and PCH FDI rx */
4534 reg = FDI_TX_CTL(pipe);
4535 temp = I915_READ(reg);
4536 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4539 reg = FDI_RX_CTL(pipe);
4540 temp = I915_READ(reg);
4541 temp &= ~(0x7 << 16);
4542 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4543 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4548 /* Ironlake workaround, disable clock pointer after downing FDI */
4549 if (HAS_PCH_IBX(dev_priv))
4550 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4552 /* still set train pattern 1 */
4553 reg = FDI_TX_CTL(pipe);
4554 temp = I915_READ(reg);
4555 temp &= ~FDI_LINK_TRAIN_NONE;
4556 temp |= FDI_LINK_TRAIN_PATTERN_1;
4557 I915_WRITE(reg, temp);
4559 reg = FDI_RX_CTL(pipe);
4560 temp = I915_READ(reg);
4561 if (HAS_PCH_CPT(dev_priv)) {
4562 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4563 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4565 temp &= ~FDI_LINK_TRAIN_NONE;
4566 temp |= FDI_LINK_TRAIN_PATTERN_1;
4568 /* BPC in FDI rx is consistent with that in PIPECONF */
4569 temp &= ~(0x07 << 16);
4570 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4571 I915_WRITE(reg, temp);
4577 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4579 struct drm_crtc *crtc;
4582 drm_for_each_crtc(crtc, &dev_priv->drm) {
4583 struct drm_crtc_commit *commit;
4584 spin_lock(&crtc->commit_lock);
4585 commit = list_first_entry_or_null(&crtc->commit_list,
4586 struct drm_crtc_commit, commit_entry);
4587 cleanup_done = commit ?
4588 try_wait_for_completion(&commit->cleanup_done) : true;
4589 spin_unlock(&crtc->commit_lock);
4594 drm_crtc_wait_one_vblank(crtc);
4602 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4606 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4608 mutex_lock(&dev_priv->sb_lock);
4610 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4611 temp |= SBI_SSCCTL_DISABLE;
4612 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4614 mutex_unlock(&dev_priv->sb_lock);
4617 /* Program iCLKIP clock to the desired frequency */
4618 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
4620 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4621 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4622 int clock = crtc_state->base.adjusted_mode.crtc_clock;
4623 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4626 lpt_disable_iclkip(dev_priv);
4628 /* The iCLK virtual clock root frequency is in MHz,
4629 * but the adjusted_mode->crtc_clock in in KHz. To get the
4630 * divisors, it is necessary to divide one by another, so we
4631 * convert the virtual clock precision to KHz here for higher
4634 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4635 u32 iclk_virtual_root_freq = 172800 * 1000;
4636 u32 iclk_pi_range = 64;
4637 u32 desired_divisor;
4639 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4641 divsel = (desired_divisor / iclk_pi_range) - 2;
4642 phaseinc = desired_divisor % iclk_pi_range;
4645 * Near 20MHz is a corner case which is
4646 * out of range for the 7-bit divisor
4652 /* This should not happen with any sane values */
4653 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4654 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4655 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4656 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4658 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4665 mutex_lock(&dev_priv->sb_lock);
4667 /* Program SSCDIVINTPHASE6 */
4668 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4669 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4670 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4671 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4672 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4673 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4674 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4675 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4677 /* Program SSCAUXDIV */
4678 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4679 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4680 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4681 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4683 /* Enable modulator and associated divider */
4684 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4685 temp &= ~SBI_SSCCTL_DISABLE;
4686 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4688 mutex_unlock(&dev_priv->sb_lock);
4690 /* Wait for initialization time */
4693 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4696 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4698 u32 divsel, phaseinc, auxdiv;
4699 u32 iclk_virtual_root_freq = 172800 * 1000;
4700 u32 iclk_pi_range = 64;
4701 u32 desired_divisor;
4704 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4707 mutex_lock(&dev_priv->sb_lock);
4709 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4710 if (temp & SBI_SSCCTL_DISABLE) {
4711 mutex_unlock(&dev_priv->sb_lock);
4715 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4716 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4717 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4718 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4719 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4721 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4722 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4723 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4725 mutex_unlock(&dev_priv->sb_lock);
4727 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4729 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4730 desired_divisor << auxdiv);
4733 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
4734 enum pipe pch_transcoder)
4736 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4737 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4738 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4740 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4741 I915_READ(HTOTAL(cpu_transcoder)));
4742 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4743 I915_READ(HBLANK(cpu_transcoder)));
4744 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4745 I915_READ(HSYNC(cpu_transcoder)));
4747 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4748 I915_READ(VTOTAL(cpu_transcoder)));
4749 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4750 I915_READ(VBLANK(cpu_transcoder)));
4751 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4752 I915_READ(VSYNC(cpu_transcoder)));
4753 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4754 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4757 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
4761 temp = I915_READ(SOUTH_CHICKEN1);
4762 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4765 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4766 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4768 temp &= ~FDI_BC_BIFURCATION_SELECT;
4770 temp |= FDI_BC_BIFURCATION_SELECT;
4772 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4773 I915_WRITE(SOUTH_CHICKEN1, temp);
4774 POSTING_READ(SOUTH_CHICKEN1);
4777 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
4779 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4780 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4782 switch (crtc->pipe) {
4786 if (crtc_state->fdi_lanes > 2)
4787 cpt_set_fdi_bc_bifurcation(dev_priv, false);
4789 cpt_set_fdi_bc_bifurcation(dev_priv, true);
4793 cpt_set_fdi_bc_bifurcation(dev_priv, true);
4802 * Finds the encoder associated with the given CRTC. This can only be
4803 * used when we know that the CRTC isn't feeding multiple encoders!
4805 static struct intel_encoder *
4806 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
4807 const struct intel_crtc_state *crtc_state)
4809 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4810 const struct drm_connector_state *connector_state;
4811 const struct drm_connector *connector;
4812 struct intel_encoder *encoder = NULL;
4813 int num_encoders = 0;
4816 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4817 if (connector_state->crtc != &crtc->base)
4820 encoder = to_intel_encoder(connector_state->best_encoder);
4824 WARN(num_encoders != 1, "%d encoders for pipe %c\n",
4825 num_encoders, pipe_name(crtc->pipe));
4831 * Enable PCH resources required for PCH ports:
4833 * - FDI training & RX/TX
4834 * - update transcoder timings
4835 * - DP transcoding bits
4838 static void ironlake_pch_enable(const struct intel_atomic_state *state,
4839 const struct intel_crtc_state *crtc_state)
4841 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4842 struct drm_device *dev = crtc->base.dev;
4843 struct drm_i915_private *dev_priv = to_i915(dev);
4844 int pipe = crtc->pipe;
4847 assert_pch_transcoder_disabled(dev_priv, pipe);
4849 if (IS_IVYBRIDGE(dev_priv))
4850 ivybridge_update_fdi_bc_bifurcation(crtc_state);
4852 /* Write the TU size bits before fdi link training, so that error
4853 * detection works. */
4854 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4855 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4857 /* For PCH output, training FDI link */
4858 dev_priv->display.fdi_link_train(crtc, crtc_state);
4860 /* We need to program the right clock selection before writing the pixel
4861 * mutliplier into the DPLL. */
4862 if (HAS_PCH_CPT(dev_priv)) {
4865 temp = I915_READ(PCH_DPLL_SEL);
4866 temp |= TRANS_DPLL_ENABLE(pipe);
4867 sel = TRANS_DPLLB_SEL(pipe);
4868 if (crtc_state->shared_dpll ==
4869 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4873 I915_WRITE(PCH_DPLL_SEL, temp);
4876 /* XXX: pch pll's can be enabled any time before we enable the PCH
4877 * transcoder, and we actually should do this to not upset any PCH
4878 * transcoder that already use the clock when we share it.
4880 * Note that enable_shared_dpll tries to do the right thing, but
4881 * get_shared_dpll unconditionally resets the pll - we need that to have
4882 * the right LVDS enable sequence. */
4883 intel_enable_shared_dpll(crtc_state);
4885 /* set transcoder timing, panel must allow it */
4886 assert_panel_unlocked(dev_priv, pipe);
4887 ironlake_pch_transcoder_set_timings(crtc_state, pipe);
4889 intel_fdi_normal_train(crtc);
4891 /* For PCH DP, enable TRANS_DP_CTL */
4892 if (HAS_PCH_CPT(dev_priv) &&
4893 intel_crtc_has_dp_encoder(crtc_state)) {
4894 const struct drm_display_mode *adjusted_mode =
4895 &crtc_state->base.adjusted_mode;
4896 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4897 i915_reg_t reg = TRANS_DP_CTL(pipe);
4900 temp = I915_READ(reg);
4901 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4902 TRANS_DP_SYNC_MASK |
4904 temp |= TRANS_DP_OUTPUT_ENABLE;
4905 temp |= bpc << 9; /* same format but at 11:9 */
4907 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4908 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4909 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4910 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4912 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
4913 WARN_ON(port < PORT_B || port > PORT_D);
4914 temp |= TRANS_DP_PORT_SEL(port);
4916 I915_WRITE(reg, temp);
4919 ironlake_enable_pch_transcoder(crtc_state);
4922 static void lpt_pch_enable(const struct intel_atomic_state *state,
4923 const struct intel_crtc_state *crtc_state)
4925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4926 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4927 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4929 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4931 lpt_program_iclkip(crtc_state);
4933 /* Set transcoder timing. */
4934 ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
4936 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4939 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4941 struct drm_i915_private *dev_priv = to_i915(dev);
4942 i915_reg_t dslreg = PIPEDSL(pipe);
4945 temp = I915_READ(dslreg);
4947 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4948 if (wait_for(I915_READ(dslreg) != temp, 5))
4949 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4954 * The hardware phase 0.0 refers to the center of the pixel.
4955 * We want to start from the top/left edge which is phase
4956 * -0.5. That matches how the hardware calculates the scaling
4957 * factors (from top-left of the first pixel to bottom-right
4958 * of the last pixel, as opposed to the pixel centers).
4960 * For 4:2:0 subsampled chroma planes we obviously have to
4961 * adjust that so that the chroma sample position lands in
4964 * Note that for packed YCbCr 4:2:2 formats there is no way to
4965 * control chroma siting. The hardware simply replicates the
4966 * chroma samples for both of the luma samples, and thus we don't
4967 * actually get the expected MPEG2 chroma siting convention :(
4968 * The same behaviour is observed on pre-SKL platforms as well.
4970 * Theory behind the formula (note that we ignore sub-pixel
4971 * source coordinates):
4972 * s = source sample position
4973 * d = destination sample position
4978 * | | 1.5 (initial phase)
4986 * | -0.375 (initial phase)
4993 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
4995 int phase = -0x8000;
4999 phase += (sub - 1) * 0x8000 / sub;
5001 phase += scale / (2 * sub);
5004 * Hardware initial phase limited to [-0.5:1.5].
5005 * Since the max hardware scale factor is 3.0, we
5006 * should never actually excdeed 1.0 here.
5008 WARN_ON(phase < -0x8000 || phase > 0x18000);
5011 phase = 0x10000 + phase;
5013 trip = PS_PHASE_TRIP;
5015 return ((phase >> 2) & PS_PHASE_MASK) | trip;
5019 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5020 unsigned int scaler_user, int *scaler_id,
5021 int src_w, int src_h, int dst_w, int dst_h,
5022 const struct drm_format_info *format, bool need_scaler)
5024 struct intel_crtc_scaler_state *scaler_state =
5025 &crtc_state->scaler_state;
5026 struct intel_crtc *intel_crtc =
5027 to_intel_crtc(crtc_state->base.crtc);
5028 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5029 const struct drm_display_mode *adjusted_mode =
5030 &crtc_state->base.adjusted_mode;
5033 * Src coordinates are already rotated by 270 degrees for
5034 * the 90/270 degree plane rotation cases (to match the
5035 * GTT mapping), hence no need to account for rotation here.
5037 if (src_w != dst_w || src_h != dst_h)
5041 * Scaling/fitting not supported in IF-ID mode in GEN9+
5042 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5043 * Once NV12 is enabled, handle it here while allocating scaler
5046 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
5047 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5048 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5053 * if plane is being disabled or scaler is no more required or force detach
5054 * - free scaler binded to this plane/crtc
5055 * - in order to do this, update crtc->scaler_usage
5057 * Here scaler state in crtc_state is set free so that
5058 * scaler can be assigned to other user. Actual register
5059 * update to free the scaler is done in plane/panel-fit programming.
5060 * For this purpose crtc/plane_state->scaler_id isn't reset here.
5062 if (force_detach || !need_scaler) {
5063 if (*scaler_id >= 0) {
5064 scaler_state->scaler_users &= ~(1 << scaler_user);
5065 scaler_state->scalers[*scaler_id].in_use = 0;
5067 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5068 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5069 intel_crtc->pipe, scaler_user, *scaler_id,
5070 scaler_state->scaler_users);
5076 if (format && is_planar_yuv_format(format->format) &&
5077 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5078 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5083 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5084 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5085 (INTEL_GEN(dev_priv) >= 11 &&
5086 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5087 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5088 (INTEL_GEN(dev_priv) < 11 &&
5089 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5090 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5091 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5092 "size is out of scaler range\n",
5093 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5097 /* mark this plane as a scaler user in crtc_state */
5098 scaler_state->scaler_users |= (1 << scaler_user);
5099 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5100 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5101 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5102 scaler_state->scaler_users);
5108 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5110 * @state: crtc's scaler state
5113 * 0 - scaler_usage updated successfully
5114 * error - requested scaling cannot be supported or other error condition
5116 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5118 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
5119 bool need_scaler = false;
5121 if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5124 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
5125 &state->scaler_state.scaler_id,
5126 state->pipe_src_w, state->pipe_src_h,
5127 adjusted_mode->crtc_hdisplay,
5128 adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5132 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5133 * @crtc_state: crtc's scaler state
5134 * @plane_state: atomic plane state to update
5137 * 0 - scaler_usage updated successfully
5138 * error - requested scaling cannot be supported or other error condition
5140 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5141 struct intel_plane_state *plane_state)
5143 struct intel_plane *intel_plane =
5144 to_intel_plane(plane_state->base.plane);
5145 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5146 struct drm_framebuffer *fb = plane_state->base.fb;
5148 bool force_detach = !fb || !plane_state->base.visible;
5149 bool need_scaler = false;
5151 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5152 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5153 fb && is_planar_yuv_format(fb->format->format))
5156 ret = skl_update_scaler(crtc_state, force_detach,
5157 drm_plane_index(&intel_plane->base),
5158 &plane_state->scaler_id,
5159 drm_rect_width(&plane_state->base.src) >> 16,
5160 drm_rect_height(&plane_state->base.src) >> 16,
5161 drm_rect_width(&plane_state->base.dst),
5162 drm_rect_height(&plane_state->base.dst),
5163 fb ? fb->format : NULL, need_scaler);
5165 if (ret || plane_state->scaler_id < 0)
5168 /* check colorkey */
5169 if (plane_state->ckey.flags) {
5170 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5171 intel_plane->base.base.id,
5172 intel_plane->base.name);
5176 /* Check src format */
5177 switch (fb->format->format) {
5178 case DRM_FORMAT_RGB565:
5179 case DRM_FORMAT_XBGR8888:
5180 case DRM_FORMAT_XRGB8888:
5181 case DRM_FORMAT_ABGR8888:
5182 case DRM_FORMAT_ARGB8888:
5183 case DRM_FORMAT_XRGB2101010:
5184 case DRM_FORMAT_XBGR2101010:
5185 case DRM_FORMAT_XBGR16161616F:
5186 case DRM_FORMAT_ABGR16161616F:
5187 case DRM_FORMAT_XRGB16161616F:
5188 case DRM_FORMAT_ARGB16161616F:
5189 case DRM_FORMAT_YUYV:
5190 case DRM_FORMAT_YVYU:
5191 case DRM_FORMAT_UYVY:
5192 case DRM_FORMAT_VYUY:
5193 case DRM_FORMAT_NV12:
5194 case DRM_FORMAT_P010:
5195 case DRM_FORMAT_P012:
5196 case DRM_FORMAT_P016:
5197 case DRM_FORMAT_Y210:
5198 case DRM_FORMAT_Y212:
5199 case DRM_FORMAT_Y216:
5200 case DRM_FORMAT_XVYU2101010:
5201 case DRM_FORMAT_XVYU12_16161616:
5202 case DRM_FORMAT_XVYU16161616:
5205 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5206 intel_plane->base.base.id, intel_plane->base.name,
5207 fb->base.id, fb->format->format);
5214 static void skylake_scaler_disable(struct intel_crtc *crtc)
5218 for (i = 0; i < crtc->num_scalers; i++)
5219 skl_detach_scaler(crtc, i);
5222 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5224 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5225 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5226 enum pipe pipe = crtc->pipe;
5227 const struct intel_crtc_scaler_state *scaler_state =
5228 &crtc_state->scaler_state;
5230 if (crtc_state->pch_pfit.enabled) {
5231 u16 uv_rgb_hphase, uv_rgb_vphase;
5232 int pfit_w, pfit_h, hscale, vscale;
5235 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5238 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5239 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5241 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5242 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5244 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5245 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5247 id = scaler_state->scaler_id;
5248 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5249 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5250 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5251 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5252 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5253 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5254 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5255 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5259 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5261 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5263 int pipe = crtc->pipe;
5265 if (crtc_state->pch_pfit.enabled) {
5266 /* Force use of hard-coded filter coefficients
5267 * as some pre-programmed values are broken,
5270 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5271 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5272 PF_PIPE_SEL_IVB(pipe));
5274 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5275 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5276 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5280 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5282 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5283 struct drm_device *dev = crtc->base.dev;
5284 struct drm_i915_private *dev_priv = to_i915(dev);
5286 if (!crtc_state->ips_enabled)
5290 * We can only enable IPS after we enable a plane and wait for a vblank
5291 * This function is called from post_plane_update, which is run after
5294 WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5296 if (IS_BROADWELL(dev_priv)) {
5297 mutex_lock(&dev_priv->pcu_lock);
5298 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5299 IPS_ENABLE | IPS_PCODE_CONTROL));
5300 mutex_unlock(&dev_priv->pcu_lock);
5301 /* Quoting Art Runyan: "its not safe to expect any particular
5302 * value in IPS_CTL bit 31 after enabling IPS through the
5303 * mailbox." Moreover, the mailbox may return a bogus state,
5304 * so we need to just enable it and continue on.
5307 I915_WRITE(IPS_CTL, IPS_ENABLE);
5308 /* The bit only becomes 1 in the next vblank, so this wait here
5309 * is essentially intel_wait_for_vblank. If we don't have this
5310 * and don't wait for vblanks until the end of crtc_enable, then
5311 * the HW state readout code will complain that the expected
5312 * IPS_CTL value is not the one we read. */
5313 if (intel_wait_for_register(&dev_priv->uncore,
5314 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
5316 DRM_ERROR("Timed out waiting for IPS enable\n");
5320 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5323 struct drm_device *dev = crtc->base.dev;
5324 struct drm_i915_private *dev_priv = to_i915(dev);
5326 if (!crtc_state->ips_enabled)
5329 if (IS_BROADWELL(dev_priv)) {
5330 mutex_lock(&dev_priv->pcu_lock);
5331 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5332 mutex_unlock(&dev_priv->pcu_lock);
5334 * Wait for PCODE to finish disabling IPS. The BSpec specified
5335 * 42ms timeout value leads to occasional timeouts so use 100ms
5338 if (intel_wait_for_register(&dev_priv->uncore,
5339 IPS_CTL, IPS_ENABLE, 0,
5341 DRM_ERROR("Timed out waiting for IPS disable\n");
5343 I915_WRITE(IPS_CTL, 0);
5344 POSTING_READ(IPS_CTL);
5347 /* We need to wait for a vblank before we can disable the plane. */
5348 intel_wait_for_vblank(dev_priv, crtc->pipe);
5351 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5353 if (intel_crtc->overlay) {
5354 struct drm_device *dev = intel_crtc->base.dev;
5356 mutex_lock(&dev->struct_mutex);
5357 (void) intel_overlay_switch_off(intel_crtc->overlay);
5358 mutex_unlock(&dev->struct_mutex);
5361 /* Let userspace switch the overlay on again. In most cases userspace
5362 * has to recompute where to put it anyway.
5367 * intel_post_enable_primary - Perform operations after enabling primary plane
5368 * @crtc: the CRTC whose primary plane was just enabled
5369 * @new_crtc_state: the enabling state
5371 * Performs potentially sleeping operations that must be done after the primary
5372 * plane is enabled, such as updating FBC and IPS. Note that this may be
5373 * called due to an explicit primary plane update, or due to an implicit
5374 * re-enable that is caused when a sprite plane is updated to no longer
5375 * completely hide the primary plane.
5378 intel_post_enable_primary(struct drm_crtc *crtc,
5379 const struct intel_crtc_state *new_crtc_state)
5381 struct drm_device *dev = crtc->dev;
5382 struct drm_i915_private *dev_priv = to_i915(dev);
5383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5384 int pipe = intel_crtc->pipe;
5387 * Gen2 reports pipe underruns whenever all planes are disabled.
5388 * So don't enable underrun reporting before at least some planes
5390 * FIXME: Need to fix the logic to work when we turn off all planes
5391 * but leave the pipe running.
5393 if (IS_GEN(dev_priv, 2))
5394 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5396 /* Underruns don't always raise interrupts, so check manually. */
5397 intel_check_cpu_fifo_underruns(dev_priv);
5398 intel_check_pch_fifo_underruns(dev_priv);
5401 /* FIXME get rid of this and use pre_plane_update */
5403 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5405 struct drm_device *dev = crtc->dev;
5406 struct drm_i915_private *dev_priv = to_i915(dev);
5407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5408 int pipe = intel_crtc->pipe;
5411 * Gen2 reports pipe underruns whenever all planes are disabled.
5412 * So disable underrun reporting before all the planes get disabled.
5414 if (IS_GEN(dev_priv, 2))
5415 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5417 hsw_disable_ips(to_intel_crtc_state(crtc->state));
5420 * Vblank time updates from the shadow to live plane control register
5421 * are blocked if the memory self-refresh mode is active at that
5422 * moment. So to make sure the plane gets truly disabled, disable
5423 * first the self-refresh mode. The self-refresh enable bit in turn
5424 * will be checked/applied by the HW only at the next frame start
5425 * event which is after the vblank start event, so we need to have a
5426 * wait-for-vblank between disabling the plane and the pipe.
5428 if (HAS_GMCH(dev_priv) &&
5429 intel_set_memory_cxsr(dev_priv, false))
5430 intel_wait_for_vblank(dev_priv, pipe);
5433 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5434 const struct intel_crtc_state *new_crtc_state)
5436 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5437 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5439 if (!old_crtc_state->ips_enabled)
5442 if (needs_modeset(&new_crtc_state->base))
5446 * Workaround : Do not read or write the pipe palette/gamma data while
5447 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5449 * Disable IPS before we program the LUT.
5451 if (IS_HASWELL(dev_priv) &&
5452 (new_crtc_state->base.color_mgmt_changed ||
5453 new_crtc_state->update_pipe) &&
5454 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5457 return !new_crtc_state->ips_enabled;
5460 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5461 const struct intel_crtc_state *new_crtc_state)
5463 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5466 if (!new_crtc_state->ips_enabled)
5469 if (needs_modeset(&new_crtc_state->base))
5473 * Workaround : Do not read or write the pipe palette/gamma data while
5474 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5476 * Re-enable IPS after the LUT has been programmed.
5478 if (IS_HASWELL(dev_priv) &&
5479 (new_crtc_state->base.color_mgmt_changed ||
5480 new_crtc_state->update_pipe) &&
5481 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5485 * We can't read out IPS on broadwell, assume the worst and
5486 * forcibly enable IPS on the first fastset.
5488 if (new_crtc_state->update_pipe &&
5489 old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5492 return !old_crtc_state->ips_enabled;
5495 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5496 const struct intel_crtc_state *crtc_state)
5498 if (!crtc_state->nv12_planes)
5501 /* WA Display #0827: Gen9:all */
5502 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
5508 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5510 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5511 struct drm_device *dev = crtc->base.dev;
5512 struct drm_i915_private *dev_priv = to_i915(dev);
5513 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5514 struct intel_crtc_state *pipe_config =
5515 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5517 struct drm_plane *primary = crtc->base.primary;
5518 struct drm_plane_state *old_primary_state =
5519 drm_atomic_get_old_plane_state(old_state, primary);
5521 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5523 if (pipe_config->update_wm_post && pipe_config->base.active)
5524 intel_update_watermarks(crtc);
5526 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5527 hsw_enable_ips(pipe_config);
5529 if (old_primary_state) {
5530 struct drm_plane_state *new_primary_state =
5531 drm_atomic_get_new_plane_state(old_state, primary);
5533 intel_fbc_post_update(crtc);
5535 if (new_primary_state->visible &&
5536 (needs_modeset(&pipe_config->base) ||
5537 !old_primary_state->visible))
5538 intel_post_enable_primary(&crtc->base, pipe_config);
5541 /* Display WA 827 */
5542 if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5543 !needs_nv12_wa(dev_priv, pipe_config)) {
5544 skl_wa_827(dev_priv, crtc->pipe, false);
5548 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5549 struct intel_crtc_state *pipe_config)
5551 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5552 struct drm_device *dev = crtc->base.dev;
5553 struct drm_i915_private *dev_priv = to_i915(dev);
5554 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5555 struct drm_plane *primary = crtc->base.primary;
5556 struct drm_plane_state *old_primary_state =
5557 drm_atomic_get_old_plane_state(old_state, primary);
5558 bool modeset = needs_modeset(&pipe_config->base);
5559 struct intel_atomic_state *old_intel_state =
5560 to_intel_atomic_state(old_state);
5562 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5563 hsw_disable_ips(old_crtc_state);
5565 if (old_primary_state) {
5566 struct intel_plane_state *new_primary_state =
5567 intel_atomic_get_new_plane_state(old_intel_state,
5568 to_intel_plane(primary));
5570 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5572 * Gen2 reports pipe underruns whenever all planes are disabled.
5573 * So disable underrun reporting before all the planes get disabled.
5575 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
5576 (modeset || !new_primary_state->base.visible))
5577 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5580 /* Display WA 827 */
5581 if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5582 needs_nv12_wa(dev_priv, pipe_config)) {
5583 skl_wa_827(dev_priv, crtc->pipe, true);
5587 * Vblank time updates from the shadow to live plane control register
5588 * are blocked if the memory self-refresh mode is active at that
5589 * moment. So to make sure the plane gets truly disabled, disable
5590 * first the self-refresh mode. The self-refresh enable bit in turn
5591 * will be checked/applied by the HW only at the next frame start
5592 * event which is after the vblank start event, so we need to have a
5593 * wait-for-vblank between disabling the plane and the pipe.
5595 if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
5596 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5597 intel_wait_for_vblank(dev_priv, crtc->pipe);
5600 * IVB workaround: must disable low power watermarks for at least
5601 * one frame before enabling scaling. LP watermarks can be re-enabled
5602 * when scaling is disabled.
5604 * WaCxSRDisabledForSpriteScaling:ivb
5606 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
5607 old_crtc_state->base.active)
5608 intel_wait_for_vblank(dev_priv, crtc->pipe);
5611 * If we're doing a modeset, we're done. No need to do any pre-vblank
5612 * watermark programming here.
5614 if (needs_modeset(&pipe_config->base))
5618 * For platforms that support atomic watermarks, program the
5619 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5620 * will be the intermediate values that are safe for both pre- and
5621 * post- vblank; when vblank happens, the 'active' values will be set
5622 * to the final 'target' values and we'll do this again to get the
5623 * optimal watermarks. For gen9+ platforms, the values we program here
5624 * will be the final target values which will get automatically latched
5625 * at vblank time; no further programming will be necessary.
5627 * If a platform hasn't been transitioned to atomic watermarks yet,
5628 * we'll continue to update watermarks the old way, if flags tell
5631 if (dev_priv->display.initial_watermarks != NULL)
5632 dev_priv->display.initial_watermarks(old_intel_state,
5634 else if (pipe_config->update_wm_pre)
5635 intel_update_watermarks(crtc);
5638 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
5639 struct intel_crtc *crtc)
5641 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5642 const struct intel_crtc_state *new_crtc_state =
5643 intel_atomic_get_new_crtc_state(state, crtc);
5644 unsigned int update_mask = new_crtc_state->update_planes;
5645 const struct intel_plane_state *old_plane_state;
5646 struct intel_plane *plane;
5647 unsigned fb_bits = 0;
5650 intel_crtc_dpms_overlay_disable(crtc);
5652 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
5653 if (crtc->pipe != plane->pipe ||
5654 !(update_mask & BIT(plane->id)))
5657 intel_disable_plane(plane, new_crtc_state);
5659 if (old_plane_state->base.visible)
5660 fb_bits |= plane->frontbuffer_bit;
5663 intel_frontbuffer_flip(dev_priv, fb_bits);
5666 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5667 struct intel_crtc_state *crtc_state,
5668 struct drm_atomic_state *old_state)
5670 struct drm_connector_state *conn_state;
5671 struct drm_connector *conn;
5674 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5675 struct intel_encoder *encoder =
5676 to_intel_encoder(conn_state->best_encoder);
5678 if (conn_state->crtc != crtc)
5681 if (encoder->pre_pll_enable)
5682 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5686 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5687 struct intel_crtc_state *crtc_state,
5688 struct drm_atomic_state *old_state)
5690 struct drm_connector_state *conn_state;
5691 struct drm_connector *conn;
5694 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5695 struct intel_encoder *encoder =
5696 to_intel_encoder(conn_state->best_encoder);
5698 if (conn_state->crtc != crtc)
5701 if (encoder->pre_enable)
5702 encoder->pre_enable(encoder, crtc_state, conn_state);
5706 static void intel_encoders_enable(struct drm_crtc *crtc,
5707 struct intel_crtc_state *crtc_state,
5708 struct drm_atomic_state *old_state)
5710 struct drm_connector_state *conn_state;
5711 struct drm_connector *conn;
5714 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5715 struct intel_encoder *encoder =
5716 to_intel_encoder(conn_state->best_encoder);
5718 if (conn_state->crtc != crtc)
5721 if (encoder->enable)
5722 encoder->enable(encoder, crtc_state, conn_state);
5723 intel_opregion_notify_encoder(encoder, true);
5727 static void intel_encoders_disable(struct drm_crtc *crtc,
5728 struct intel_crtc_state *old_crtc_state,
5729 struct drm_atomic_state *old_state)
5731 struct drm_connector_state *old_conn_state;
5732 struct drm_connector *conn;
5735 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5736 struct intel_encoder *encoder =
5737 to_intel_encoder(old_conn_state->best_encoder);
5739 if (old_conn_state->crtc != crtc)
5742 intel_opregion_notify_encoder(encoder, false);
5743 if (encoder->disable)
5744 encoder->disable(encoder, old_crtc_state, old_conn_state);
5748 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5749 struct intel_crtc_state *old_crtc_state,
5750 struct drm_atomic_state *old_state)
5752 struct drm_connector_state *old_conn_state;
5753 struct drm_connector *conn;
5756 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5757 struct intel_encoder *encoder =
5758 to_intel_encoder(old_conn_state->best_encoder);
5760 if (old_conn_state->crtc != crtc)
5763 if (encoder->post_disable)
5764 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5768 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5769 struct intel_crtc_state *old_crtc_state,
5770 struct drm_atomic_state *old_state)
5772 struct drm_connector_state *old_conn_state;
5773 struct drm_connector *conn;
5776 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5777 struct intel_encoder *encoder =
5778 to_intel_encoder(old_conn_state->best_encoder);
5780 if (old_conn_state->crtc != crtc)
5783 if (encoder->post_pll_disable)
5784 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5788 static void intel_encoders_update_pipe(struct drm_crtc *crtc,
5789 struct intel_crtc_state *crtc_state,
5790 struct drm_atomic_state *old_state)
5792 struct drm_connector_state *conn_state;
5793 struct drm_connector *conn;
5796 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5797 struct intel_encoder *encoder =
5798 to_intel_encoder(conn_state->best_encoder);
5800 if (conn_state->crtc != crtc)
5803 if (encoder->update_pipe)
5804 encoder->update_pipe(encoder, crtc_state, conn_state);
5808 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
5810 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5811 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
5813 plane->disable_plane(plane, crtc_state);
5816 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5817 struct drm_atomic_state *old_state)
5819 struct drm_crtc *crtc = pipe_config->base.crtc;
5820 struct drm_device *dev = crtc->dev;
5821 struct drm_i915_private *dev_priv = to_i915(dev);
5822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5823 int pipe = intel_crtc->pipe;
5824 struct intel_atomic_state *old_intel_state =
5825 to_intel_atomic_state(old_state);
5827 if (WARN_ON(intel_crtc->active))
5831 * Sometimes spurious CPU pipe underruns happen during FDI
5832 * training, at least with VGA+HDMI cloning. Suppress them.
5834 * On ILK we get an occasional spurious CPU pipe underruns
5835 * between eDP port A enable and vdd enable. Also PCH port
5836 * enable seems to result in the occasional CPU pipe underrun.
5838 * Spurious PCH underruns also occur during PCH enabling.
5840 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5841 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5843 if (pipe_config->has_pch_encoder)
5844 intel_prepare_shared_dpll(pipe_config);
5846 if (intel_crtc_has_dp_encoder(pipe_config))
5847 intel_dp_set_m_n(pipe_config, M1_N1);
5849 intel_set_pipe_timings(pipe_config);
5850 intel_set_pipe_src_size(pipe_config);
5852 if (pipe_config->has_pch_encoder) {
5853 intel_cpu_transcoder_set_m_n(pipe_config,
5854 &pipe_config->fdi_m_n, NULL);
5857 ironlake_set_pipeconf(pipe_config);
5859 intel_crtc->active = true;
5861 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5863 if (pipe_config->has_pch_encoder) {
5864 /* Note: FDI PLL enabling _must_ be done before we enable the
5865 * cpu pipes, hence this is separate from all the other fdi/pch
5867 ironlake_fdi_pll_enable(pipe_config);
5869 assert_fdi_tx_disabled(dev_priv, pipe);
5870 assert_fdi_rx_disabled(dev_priv, pipe);
5873 ironlake_pfit_enable(pipe_config);
5876 * On ILK+ LUT must be loaded before the pipe is running but with
5879 intel_color_load_luts(pipe_config);
5880 intel_color_commit(pipe_config);
5881 /* update DSPCNTR to configure gamma for pipe bottom color */
5882 intel_disable_primary_plane(pipe_config);
5884 if (dev_priv->display.initial_watermarks != NULL)
5885 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5886 intel_enable_pipe(pipe_config);
5888 if (pipe_config->has_pch_encoder)
5889 ironlake_pch_enable(old_intel_state, pipe_config);
5891 assert_vblank_disabled(crtc);
5892 intel_crtc_vblank_on(pipe_config);
5894 intel_encoders_enable(crtc, pipe_config, old_state);
5896 if (HAS_PCH_CPT(dev_priv))
5897 cpt_verify_modeset(dev, intel_crtc->pipe);
5900 * Must wait for vblank to avoid spurious PCH FIFO underruns.
5901 * And a second vblank wait is needed at least on ILK with
5902 * some interlaced HDMI modes. Let's do the double wait always
5903 * in case there are more corner cases we don't know about.
5905 if (pipe_config->has_pch_encoder) {
5906 intel_wait_for_vblank(dev_priv, pipe);
5907 intel_wait_for_vblank(dev_priv, pipe);
5909 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5910 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5913 /* IPS only exists on ULT machines and is tied to pipe A. */
5914 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5916 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5919 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5920 enum pipe pipe, bool apply)
5922 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5923 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5930 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5933 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5935 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5936 enum pipe pipe = crtc->pipe;
5939 val = MBUS_DBOX_A_CREDIT(2);
5940 val |= MBUS_DBOX_BW_CREDIT(1);
5941 val |= MBUS_DBOX_B_CREDIT(8);
5943 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5946 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5947 struct drm_atomic_state *old_state)
5949 struct drm_crtc *crtc = pipe_config->base.crtc;
5950 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5952 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5953 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5954 struct intel_atomic_state *old_intel_state =
5955 to_intel_atomic_state(old_state);
5956 bool psl_clkgate_wa;
5958 if (WARN_ON(intel_crtc->active))
5961 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5963 if (pipe_config->shared_dpll)
5964 intel_enable_shared_dpll(pipe_config);
5966 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5968 if (intel_crtc_has_dp_encoder(pipe_config))
5969 intel_dp_set_m_n(pipe_config, M1_N1);
5971 if (!transcoder_is_dsi(cpu_transcoder))
5972 intel_set_pipe_timings(pipe_config);
5974 intel_set_pipe_src_size(pipe_config);
5976 if (cpu_transcoder != TRANSCODER_EDP &&
5977 !transcoder_is_dsi(cpu_transcoder)) {
5978 I915_WRITE(PIPE_MULT(cpu_transcoder),
5979 pipe_config->pixel_multiplier - 1);
5982 if (pipe_config->has_pch_encoder) {
5983 intel_cpu_transcoder_set_m_n(pipe_config,
5984 &pipe_config->fdi_m_n, NULL);
5987 if (!transcoder_is_dsi(cpu_transcoder))
5988 haswell_set_pipeconf(pipe_config);
5990 haswell_set_pipemisc(pipe_config);
5992 intel_crtc->active = true;
5994 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5995 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5996 pipe_config->pch_pfit.enabled;
5998 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6000 if (INTEL_GEN(dev_priv) >= 9)
6001 skylake_pfit_enable(pipe_config);
6003 ironlake_pfit_enable(pipe_config);
6006 * On ILK+ LUT must be loaded before the pipe is running but with
6009 intel_color_load_luts(pipe_config);
6010 intel_color_commit(pipe_config);
6011 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6012 if (INTEL_GEN(dev_priv) < 9)
6013 intel_disable_primary_plane(pipe_config);
6015 if (INTEL_GEN(dev_priv) >= 11)
6016 icl_set_pipe_chicken(intel_crtc);
6018 intel_ddi_set_pipe_settings(pipe_config);
6019 if (!transcoder_is_dsi(cpu_transcoder))
6020 intel_ddi_enable_transcoder_func(pipe_config);
6022 if (dev_priv->display.initial_watermarks != NULL)
6023 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
6025 if (INTEL_GEN(dev_priv) >= 11)
6026 icl_pipe_mbus_enable(intel_crtc);
6028 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6029 if (!transcoder_is_dsi(cpu_transcoder))
6030 intel_enable_pipe(pipe_config);
6032 if (pipe_config->has_pch_encoder)
6033 lpt_pch_enable(old_intel_state, pipe_config);
6035 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
6036 intel_ddi_set_vc_payload_alloc(pipe_config, true);
6038 assert_vblank_disabled(crtc);
6039 intel_crtc_vblank_on(pipe_config);
6041 intel_encoders_enable(crtc, pipe_config, old_state);
6043 if (psl_clkgate_wa) {
6044 intel_wait_for_vblank(dev_priv, pipe);
6045 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6048 /* If we change the relative order between pipe/planes enabling, we need
6049 * to change the workaround. */
6050 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
6051 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6052 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6053 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6057 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6059 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6060 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6061 enum pipe pipe = crtc->pipe;
6063 /* To avoid upsetting the power well on haswell only disable the pfit if
6064 * it's in use. The hw state code will make sure we get this right. */
6065 if (old_crtc_state->pch_pfit.enabled) {
6066 I915_WRITE(PF_CTL(pipe), 0);
6067 I915_WRITE(PF_WIN_POS(pipe), 0);
6068 I915_WRITE(PF_WIN_SZ(pipe), 0);
6072 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
6073 struct drm_atomic_state *old_state)
6075 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6076 struct drm_device *dev = crtc->dev;
6077 struct drm_i915_private *dev_priv = to_i915(dev);
6078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6079 int pipe = intel_crtc->pipe;
6082 * Sometimes spurious CPU pipe underruns happen when the
6083 * pipe is already disabled, but FDI RX/TX is still enabled.
6084 * Happens at least with VGA+HDMI cloning. Suppress them.
6086 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6087 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6089 intel_encoders_disable(crtc, old_crtc_state, old_state);
6091 drm_crtc_vblank_off(crtc);
6092 assert_vblank_disabled(crtc);
6094 intel_disable_pipe(old_crtc_state);
6096 ironlake_pfit_disable(old_crtc_state);
6098 if (old_crtc_state->has_pch_encoder)
6099 ironlake_fdi_disable(crtc);
6101 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6103 if (old_crtc_state->has_pch_encoder) {
6104 ironlake_disable_pch_transcoder(dev_priv, pipe);
6106 if (HAS_PCH_CPT(dev_priv)) {
6110 /* disable TRANS_DP_CTL */
6111 reg = TRANS_DP_CTL(pipe);
6112 temp = I915_READ(reg);
6113 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6114 TRANS_DP_PORT_SEL_MASK);
6115 temp |= TRANS_DP_PORT_SEL_NONE;
6116 I915_WRITE(reg, temp);
6118 /* disable DPLL_SEL */
6119 temp = I915_READ(PCH_DPLL_SEL);
6120 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6121 I915_WRITE(PCH_DPLL_SEL, temp);
6124 ironlake_fdi_pll_disable(intel_crtc);
6127 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6128 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6131 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
6132 struct drm_atomic_state *old_state)
6134 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6135 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6137 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6139 intel_encoders_disable(crtc, old_crtc_state, old_state);
6141 drm_crtc_vblank_off(crtc);
6142 assert_vblank_disabled(crtc);
6144 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6145 if (!transcoder_is_dsi(cpu_transcoder))
6146 intel_disable_pipe(old_crtc_state);
6148 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
6149 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
6151 if (!transcoder_is_dsi(cpu_transcoder))
6152 intel_ddi_disable_transcoder_func(old_crtc_state);
6154 intel_dsc_disable(old_crtc_state);
6156 if (INTEL_GEN(dev_priv) >= 9)
6157 skylake_scaler_disable(intel_crtc);
6159 ironlake_pfit_disable(old_crtc_state);
6161 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6163 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6166 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6168 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6169 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6171 if (!crtc_state->gmch_pfit.control)
6175 * The panel fitter should only be adjusted whilst the pipe is disabled,
6176 * according to register description and PRM.
6178 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6179 assert_pipe_disabled(dev_priv, crtc->pipe);
6181 I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6182 I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6184 /* Border color in case we don't scale up to the full screen. Black by
6185 * default, change to something else for debugging. */
6186 I915_WRITE(BCLRPAT(crtc->pipe), 0);
6189 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
6191 if (port == PORT_NONE)
6194 if (IS_ELKHARTLAKE(dev_priv))
6195 return port <= PORT_C;
6197 if (INTEL_GEN(dev_priv) >= 11)
6198 return port <= PORT_B;
6203 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
6205 if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6206 return port >= PORT_C && port <= PORT_F;
6211 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6213 if (!intel_port_is_tc(dev_priv, port))
6214 return PORT_TC_NONE;
6216 return port - PORT_C;
6219 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6223 return POWER_DOMAIN_PORT_DDI_A_LANES;
6225 return POWER_DOMAIN_PORT_DDI_B_LANES;
6227 return POWER_DOMAIN_PORT_DDI_C_LANES;
6229 return POWER_DOMAIN_PORT_DDI_D_LANES;
6231 return POWER_DOMAIN_PORT_DDI_E_LANES;
6233 return POWER_DOMAIN_PORT_DDI_F_LANES;
6236 return POWER_DOMAIN_PORT_OTHER;
6240 enum intel_display_power_domain
6241 intel_aux_power_domain(struct intel_digital_port *dig_port)
6243 switch (dig_port->aux_ch) {
6245 return POWER_DOMAIN_AUX_A;
6247 return POWER_DOMAIN_AUX_B;
6249 return POWER_DOMAIN_AUX_C;
6251 return POWER_DOMAIN_AUX_D;
6253 return POWER_DOMAIN_AUX_E;
6255 return POWER_DOMAIN_AUX_F;
6257 MISSING_CASE(dig_port->aux_ch);
6258 return POWER_DOMAIN_AUX_A;
6262 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
6263 struct intel_crtc_state *crtc_state)
6265 struct drm_device *dev = crtc->dev;
6266 struct drm_i915_private *dev_priv = to_i915(dev);
6267 struct drm_encoder *encoder;
6268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6269 enum pipe pipe = intel_crtc->pipe;
6271 enum transcoder transcoder = crtc_state->cpu_transcoder;
6273 if (!crtc_state->base.active)
6276 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6277 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6278 if (crtc_state->pch_pfit.enabled ||
6279 crtc_state->pch_pfit.force_thru)
6280 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6282 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
6283 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6285 mask |= BIT_ULL(intel_encoder->power_domain);
6288 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6289 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6291 if (crtc_state->shared_dpll)
6292 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
6298 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
6299 struct intel_crtc_state *crtc_state)
6301 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6303 enum intel_display_power_domain domain;
6304 u64 domains, new_domains, old_domains;
6306 old_domains = intel_crtc->enabled_power_domains;
6307 intel_crtc->enabled_power_domains = new_domains =
6308 get_crtc_power_domains(crtc, crtc_state);
6310 domains = new_domains & ~old_domains;
6312 for_each_power_domain(domain, domains)
6313 intel_display_power_get(dev_priv, domain);
6315 return old_domains & ~new_domains;
6318 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6321 enum intel_display_power_domain domain;
6323 for_each_power_domain(domain, domains)
6324 intel_display_power_put_unchecked(dev_priv, domain);
6327 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6328 struct drm_atomic_state *old_state)
6330 struct intel_atomic_state *old_intel_state =
6331 to_intel_atomic_state(old_state);
6332 struct drm_crtc *crtc = pipe_config->base.crtc;
6333 struct drm_device *dev = crtc->dev;
6334 struct drm_i915_private *dev_priv = to_i915(dev);
6335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6336 int pipe = intel_crtc->pipe;
6338 if (WARN_ON(intel_crtc->active))
6341 if (intel_crtc_has_dp_encoder(pipe_config))
6342 intel_dp_set_m_n(pipe_config, M1_N1);
6344 intel_set_pipe_timings(pipe_config);
6345 intel_set_pipe_src_size(pipe_config);
6347 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6348 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6349 I915_WRITE(CHV_CANVAS(pipe), 0);
6352 i9xx_set_pipeconf(pipe_config);
6354 intel_crtc->active = true;
6356 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6358 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6360 if (IS_CHERRYVIEW(dev_priv)) {
6361 chv_prepare_pll(intel_crtc, pipe_config);
6362 chv_enable_pll(intel_crtc, pipe_config);
6364 vlv_prepare_pll(intel_crtc, pipe_config);
6365 vlv_enable_pll(intel_crtc, pipe_config);
6368 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6370 i9xx_pfit_enable(pipe_config);
6372 intel_color_load_luts(pipe_config);
6373 intel_color_commit(pipe_config);
6374 /* update DSPCNTR to configure gamma for pipe bottom color */
6375 intel_disable_primary_plane(pipe_config);
6377 dev_priv->display.initial_watermarks(old_intel_state,
6379 intel_enable_pipe(pipe_config);
6381 assert_vblank_disabled(crtc);
6382 intel_crtc_vblank_on(pipe_config);
6384 intel_encoders_enable(crtc, pipe_config, old_state);
6387 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
6389 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6390 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6392 I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
6393 I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
6396 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6397 struct drm_atomic_state *old_state)
6399 struct intel_atomic_state *old_intel_state =
6400 to_intel_atomic_state(old_state);
6401 struct drm_crtc *crtc = pipe_config->base.crtc;
6402 struct drm_device *dev = crtc->dev;
6403 struct drm_i915_private *dev_priv = to_i915(dev);
6404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6405 enum pipe pipe = intel_crtc->pipe;
6407 if (WARN_ON(intel_crtc->active))
6410 i9xx_set_pll_dividers(pipe_config);
6412 if (intel_crtc_has_dp_encoder(pipe_config))
6413 intel_dp_set_m_n(pipe_config, M1_N1);
6415 intel_set_pipe_timings(pipe_config);
6416 intel_set_pipe_src_size(pipe_config);
6418 i9xx_set_pipeconf(pipe_config);
6420 intel_crtc->active = true;
6422 if (!IS_GEN(dev_priv, 2))
6423 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6425 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6427 i9xx_enable_pll(intel_crtc, pipe_config);
6429 i9xx_pfit_enable(pipe_config);
6431 intel_color_load_luts(pipe_config);
6432 intel_color_commit(pipe_config);
6433 /* update DSPCNTR to configure gamma for pipe bottom color */
6434 intel_disable_primary_plane(pipe_config);
6436 if (dev_priv->display.initial_watermarks != NULL)
6437 dev_priv->display.initial_watermarks(old_intel_state,
6440 intel_update_watermarks(intel_crtc);
6441 intel_enable_pipe(pipe_config);
6443 assert_vblank_disabled(crtc);
6444 intel_crtc_vblank_on(pipe_config);
6446 intel_encoders_enable(crtc, pipe_config, old_state);
6449 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6451 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6452 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6454 if (!old_crtc_state->gmch_pfit.control)
6457 assert_pipe_disabled(dev_priv, crtc->pipe);
6459 DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
6460 I915_READ(PFIT_CONTROL));
6461 I915_WRITE(PFIT_CONTROL, 0);
6464 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6465 struct drm_atomic_state *old_state)
6467 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6468 struct drm_device *dev = crtc->dev;
6469 struct drm_i915_private *dev_priv = to_i915(dev);
6470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6471 int pipe = intel_crtc->pipe;
6474 * On gen2 planes are double buffered but the pipe isn't, so we must
6475 * wait for planes to fully turn off before disabling the pipe.
6477 if (IS_GEN(dev_priv, 2))
6478 intel_wait_for_vblank(dev_priv, pipe);
6480 intel_encoders_disable(crtc, old_crtc_state, old_state);
6482 drm_crtc_vblank_off(crtc);
6483 assert_vblank_disabled(crtc);
6485 intel_disable_pipe(old_crtc_state);
6487 i9xx_pfit_disable(old_crtc_state);
6489 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6491 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
6492 if (IS_CHERRYVIEW(dev_priv))
6493 chv_disable_pll(dev_priv, pipe);
6494 else if (IS_VALLEYVIEW(dev_priv))
6495 vlv_disable_pll(dev_priv, pipe);
6497 i9xx_disable_pll(old_crtc_state);
6500 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6502 if (!IS_GEN(dev_priv, 2))
6503 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6505 if (!dev_priv->display.initial_watermarks)
6506 intel_update_watermarks(intel_crtc);
6508 /* clock the pipe down to 640x480@60 to potentially save power */
6509 if (IS_I830(dev_priv))
6510 i830_enable_pipe(dev_priv, pipe);
6513 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6514 struct drm_modeset_acquire_ctx *ctx)
6516 struct intel_encoder *encoder;
6517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6518 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6519 enum intel_display_power_domain domain;
6520 struct intel_plane *plane;
6522 struct drm_atomic_state *state;
6523 struct intel_crtc_state *crtc_state;
6526 if (!intel_crtc->active)
6529 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6530 const struct intel_plane_state *plane_state =
6531 to_intel_plane_state(plane->base.state);
6533 if (plane_state->base.visible)
6534 intel_plane_disable_noatomic(intel_crtc, plane);
6537 state = drm_atomic_state_alloc(crtc->dev);
6539 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6540 crtc->base.id, crtc->name);
6544 state->acquire_ctx = ctx;
6546 /* Everything's already locked, -EDEADLK can't happen. */
6547 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6548 ret = drm_atomic_add_affected_connectors(state, crtc);
6550 WARN_ON(IS_ERR(crtc_state) || ret);
6552 dev_priv->display.crtc_disable(crtc_state, state);
6554 drm_atomic_state_put(state);
6556 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6557 crtc->base.id, crtc->name);
6559 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6560 crtc->state->active = false;
6561 intel_crtc->active = false;
6562 crtc->enabled = false;
6563 crtc->state->connector_mask = 0;
6564 crtc->state->encoder_mask = 0;
6566 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6567 encoder->base.crtc = NULL;
6569 intel_fbc_disable(intel_crtc);
6570 intel_update_watermarks(intel_crtc);
6571 intel_disable_shared_dpll(to_intel_crtc_state(crtc->state));
6573 domains = intel_crtc->enabled_power_domains;
6574 for_each_power_domain(domain, domains)
6575 intel_display_power_put_unchecked(dev_priv, domain);
6576 intel_crtc->enabled_power_domains = 0;
6578 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6579 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6580 dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6584 * turn all crtc's off, but do not adjust state
6585 * This has to be paired with a call to intel_modeset_setup_hw_state.
6587 int intel_display_suspend(struct drm_device *dev)
6589 struct drm_i915_private *dev_priv = to_i915(dev);
6590 struct drm_atomic_state *state;
6593 state = drm_atomic_helper_suspend(dev);
6594 ret = PTR_ERR_OR_ZERO(state);
6596 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6598 dev_priv->modeset_restore_state = state;
6602 void intel_encoder_destroy(struct drm_encoder *encoder)
6604 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6606 drm_encoder_cleanup(encoder);
6607 kfree(intel_encoder);
6610 /* Cross check the actual hw state with our own modeset state tracking (and it's
6611 * internal consistency). */
6612 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6613 struct drm_connector_state *conn_state)
6615 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6617 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6618 connector->base.base.id,
6619 connector->base.name);
6621 if (connector->get_hw_state(connector)) {
6622 struct intel_encoder *encoder = connector->encoder;
6624 I915_STATE_WARN(!crtc_state,
6625 "connector enabled without attached crtc\n");
6630 I915_STATE_WARN(!crtc_state->active,
6631 "connector is active, but attached crtc isn't\n");
6633 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6636 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6637 "atomic encoder doesn't match attached encoder\n");
6639 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6640 "attached encoder crtc differs from connector crtc\n");
6642 I915_STATE_WARN(crtc_state && crtc_state->active,
6643 "attached crtc is active, but connector isn't\n");
6644 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6645 "best encoder set without crtc!\n");
6649 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6651 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6652 return crtc_state->fdi_lanes;
6657 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6658 struct intel_crtc_state *pipe_config)
6660 struct drm_i915_private *dev_priv = to_i915(dev);
6661 struct drm_atomic_state *state = pipe_config->base.state;
6662 struct intel_crtc *other_crtc;
6663 struct intel_crtc_state *other_crtc_state;
6665 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6666 pipe_name(pipe), pipe_config->fdi_lanes);
6667 if (pipe_config->fdi_lanes > 4) {
6668 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6669 pipe_name(pipe), pipe_config->fdi_lanes);
6673 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6674 if (pipe_config->fdi_lanes > 2) {
6675 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6676 pipe_config->fdi_lanes);
6683 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6686 /* Ivybridge 3 pipe is really complicated */
6691 if (pipe_config->fdi_lanes <= 2)
6694 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6696 intel_atomic_get_crtc_state(state, other_crtc);
6697 if (IS_ERR(other_crtc_state))
6698 return PTR_ERR(other_crtc_state);
6700 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6701 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6702 pipe_name(pipe), pipe_config->fdi_lanes);
6707 if (pipe_config->fdi_lanes > 2) {
6708 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6709 pipe_name(pipe), pipe_config->fdi_lanes);
6713 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6715 intel_atomic_get_crtc_state(state, other_crtc);
6716 if (IS_ERR(other_crtc_state))
6717 return PTR_ERR(other_crtc_state);
6719 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6720 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6730 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6731 struct intel_crtc_state *pipe_config)
6733 struct drm_device *dev = intel_crtc->base.dev;
6734 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6735 int lane, link_bw, fdi_dotclock, ret;
6736 bool needs_recompute = false;
6739 /* FDI is a binary signal running at ~2.7GHz, encoding
6740 * each output octet as 10 bits. The actual frequency
6741 * is stored as a divider into a 100MHz clock, and the
6742 * mode pixel clock is stored in units of 1KHz.
6743 * Hence the bw of each lane in terms of the mode signal
6746 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6748 fdi_dotclock = adjusted_mode->crtc_clock;
6750 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6751 pipe_config->pipe_bpp);
6753 pipe_config->fdi_lanes = lane;
6755 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6756 link_bw, &pipe_config->fdi_m_n, false);
6758 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6759 if (ret == -EDEADLK)
6762 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6763 pipe_config->pipe_bpp -= 2*3;
6764 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6765 pipe_config->pipe_bpp);
6766 needs_recompute = true;
6767 pipe_config->bw_constrained = true;
6772 if (needs_recompute)
6778 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6780 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6781 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6783 /* IPS only exists on ULT machines and is tied to pipe A. */
6784 if (!hsw_crtc_supports_ips(crtc))
6787 if (!i915_modparams.enable_ips)
6790 if (crtc_state->pipe_bpp > 24)
6794 * We compare against max which means we must take
6795 * the increased cdclk requirement into account when
6796 * calculating the new cdclk.
6798 * Should measure whether using a lower cdclk w/o IPS
6800 if (IS_BROADWELL(dev_priv) &&
6801 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6807 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6809 struct drm_i915_private *dev_priv =
6810 to_i915(crtc_state->base.crtc->dev);
6811 struct intel_atomic_state *intel_state =
6812 to_intel_atomic_state(crtc_state->base.state);
6814 if (!hsw_crtc_state_ips_capable(crtc_state))
6818 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
6819 * enabled and disabled dynamically based on package C states,
6820 * user space can't make reliable use of the CRCs, so let's just
6821 * completely disable it.
6823 if (crtc_state->crc_enabled)
6826 /* IPS should be fine as long as at least one plane is enabled. */
6827 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6830 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6831 if (IS_BROADWELL(dev_priv) &&
6832 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6838 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6840 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6842 /* GDG double wide on either pipe, otherwise pipe A only */
6843 return INTEL_GEN(dev_priv) < 4 &&
6844 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6847 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6851 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6854 * We only use IF-ID interlacing. If we ever use
6855 * PF-ID we'll need to adjust the pixel_rate here.
6858 if (pipe_config->pch_pfit.enabled) {
6859 u64 pipe_w, pipe_h, pfit_w, pfit_h;
6860 u32 pfit_size = pipe_config->pch_pfit.size;
6862 pipe_w = pipe_config->pipe_src_w;
6863 pipe_h = pipe_config->pipe_src_h;
6865 pfit_w = (pfit_size >> 16) & 0xFFFF;
6866 pfit_h = pfit_size & 0xFFFF;
6867 if (pipe_w < pfit_w)
6869 if (pipe_h < pfit_h)
6872 if (WARN_ON(!pfit_w || !pfit_h))
6875 pixel_rate = div_u64((u64)pixel_rate * pipe_w * pipe_h,
6882 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6884 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6886 if (HAS_GMCH(dev_priv))
6887 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6888 crtc_state->pixel_rate =
6889 crtc_state->base.adjusted_mode.crtc_clock;
6891 crtc_state->pixel_rate =
6892 ilk_pipe_pixel_rate(crtc_state);
6895 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6896 struct intel_crtc_state *pipe_config)
6898 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6899 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6900 int clock_limit = dev_priv->max_dotclk_freq;
6902 if (INTEL_GEN(dev_priv) < 4) {
6903 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6906 * Enable double wide mode when the dot clock
6907 * is > 90% of the (display) core speed.
6909 if (intel_crtc_supports_double_wide(crtc) &&
6910 adjusted_mode->crtc_clock > clock_limit) {
6911 clock_limit = dev_priv->max_dotclk_freq;
6912 pipe_config->double_wide = true;
6916 if (adjusted_mode->crtc_clock > clock_limit) {
6917 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6918 adjusted_mode->crtc_clock, clock_limit,
6919 yesno(pipe_config->double_wide));
6923 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
6924 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
6925 pipe_config->base.ctm) {
6927 * There is only one pipe CSC unit per pipe, and we need that
6928 * for output conversion from RGB->YCBCR. So if CTM is already
6929 * applied we can't support YCBCR420 output.
6931 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6936 * Pipe horizontal size must be even in:
6938 * - LVDS dual channel mode
6939 * - Double wide pipe
6941 if (pipe_config->pipe_src_w & 1) {
6942 if (pipe_config->double_wide) {
6943 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6947 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6948 intel_is_dual_link_lvds(dev_priv)) {
6949 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6954 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6955 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6957 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6958 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6961 intel_crtc_compute_pixel_rate(pipe_config);
6963 if (pipe_config->has_pch_encoder)
6964 return ironlake_fdi_compute_config(crtc, pipe_config);
6970 intel_reduce_m_n_ratio(u32 *num, u32 *den)
6972 while (*num > DATA_LINK_M_N_MASK ||
6973 *den > DATA_LINK_M_N_MASK) {
6979 static void compute_m_n(unsigned int m, unsigned int n,
6980 u32 *ret_m, u32 *ret_n,
6984 * Several DP dongles in particular seem to be fussy about
6985 * too large link M/N values. Give N value as 0x8000 that
6986 * should be acceptable by specific devices. 0x8000 is the
6987 * specified fixed N value for asynchronous clock mode,
6988 * which the devices expect also in synchronous clock mode.
6993 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6995 *ret_m = div_u64((u64)m * *ret_n, n);
6996 intel_reduce_m_n_ratio(ret_m, ret_n);
7000 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7001 int pixel_clock, int link_clock,
7002 struct intel_link_m_n *m_n,
7007 compute_m_n(bits_per_pixel * pixel_clock,
7008 link_clock * nlanes * 8,
7009 &m_n->gmch_m, &m_n->gmch_n,
7012 compute_m_n(pixel_clock, link_clock,
7013 &m_n->link_m, &m_n->link_n,
7017 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7019 if (i915_modparams.panel_use_ssc >= 0)
7020 return i915_modparams.panel_use_ssc != 0;
7021 return dev_priv->vbt.lvds_use_ssc
7022 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7025 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7027 return (1 << dpll->n) << 16 | dpll->m2;
7030 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7032 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7035 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7036 struct intel_crtc_state *crtc_state,
7037 struct dpll *reduced_clock)
7039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7042 if (IS_PINEVIEW(dev_priv)) {
7043 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7045 fp2 = pnv_dpll_compute_fp(reduced_clock);
7047 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7049 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7052 crtc_state->dpll_hw_state.fp0 = fp;
7054 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7056 crtc_state->dpll_hw_state.fp1 = fp2;
7058 crtc_state->dpll_hw_state.fp1 = fp;
7062 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7068 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7069 * and set it to a reasonable value instead.
7071 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7072 reg_val &= 0xffffff00;
7073 reg_val |= 0x00000030;
7074 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7076 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7077 reg_val &= 0x00ffffff;
7078 reg_val |= 0x8c000000;
7079 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7081 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7082 reg_val &= 0xffffff00;
7083 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7085 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7086 reg_val &= 0x00ffffff;
7087 reg_val |= 0xb0000000;
7088 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7091 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7092 const struct intel_link_m_n *m_n)
7094 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7095 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7096 enum pipe pipe = crtc->pipe;
7098 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7099 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7100 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7101 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7104 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7105 enum transcoder transcoder)
7107 if (IS_HASWELL(dev_priv))
7108 return transcoder == TRANSCODER_EDP;
7111 * Strictly speaking some registers are available before
7112 * gen7, but we only support DRRS on gen7+
7114 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7117 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7118 const struct intel_link_m_n *m_n,
7119 const struct intel_link_m_n *m2_n2)
7121 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7122 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7123 enum pipe pipe = crtc->pipe;
7124 enum transcoder transcoder = crtc_state->cpu_transcoder;
7126 if (INTEL_GEN(dev_priv) >= 5) {
7127 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7128 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7129 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7130 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7132 * M2_N2 registers are set only if DRRS is supported
7133 * (to make sure the registers are not unnecessarily accessed).
7135 if (m2_n2 && crtc_state->has_drrs &&
7136 transcoder_has_m2_n2(dev_priv, transcoder)) {
7137 I915_WRITE(PIPE_DATA_M2(transcoder),
7138 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7139 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7140 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7141 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7144 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7145 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7146 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7147 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7151 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7153 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7156 dp_m_n = &crtc_state->dp_m_n;
7157 dp_m2_n2 = &crtc_state->dp_m2_n2;
7158 } else if (m_n == M2_N2) {
7161 * M2_N2 registers are not supported. Hence m2_n2 divider value
7162 * needs to be programmed into M1_N1.
7164 dp_m_n = &crtc_state->dp_m2_n2;
7166 DRM_ERROR("Unsupported divider value\n");
7170 if (crtc_state->has_pch_encoder)
7171 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7173 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7176 static void vlv_compute_dpll(struct intel_crtc *crtc,
7177 struct intel_crtc_state *pipe_config)
7179 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7180 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7181 if (crtc->pipe != PIPE_A)
7182 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7184 /* DPLL not used with DSI, but still need the rest set up */
7185 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7186 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7187 DPLL_EXT_BUFFER_ENABLE_VLV;
7189 pipe_config->dpll_hw_state.dpll_md =
7190 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7193 static void chv_compute_dpll(struct intel_crtc *crtc,
7194 struct intel_crtc_state *pipe_config)
7196 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7197 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7198 if (crtc->pipe != PIPE_A)
7199 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7201 /* DPLL not used with DSI, but still need the rest set up */
7202 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7203 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7205 pipe_config->dpll_hw_state.dpll_md =
7206 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7209 static void vlv_prepare_pll(struct intel_crtc *crtc,
7210 const struct intel_crtc_state *pipe_config)
7212 struct drm_device *dev = crtc->base.dev;
7213 struct drm_i915_private *dev_priv = to_i915(dev);
7214 enum pipe pipe = crtc->pipe;
7216 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7217 u32 coreclk, reg_val;
7220 I915_WRITE(DPLL(pipe),
7221 pipe_config->dpll_hw_state.dpll &
7222 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7224 /* No need to actually set up the DPLL with DSI */
7225 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7228 mutex_lock(&dev_priv->sb_lock);
7230 bestn = pipe_config->dpll.n;
7231 bestm1 = pipe_config->dpll.m1;
7232 bestm2 = pipe_config->dpll.m2;
7233 bestp1 = pipe_config->dpll.p1;
7234 bestp2 = pipe_config->dpll.p2;
7236 /* See eDP HDMI DPIO driver vbios notes doc */
7238 /* PLL B needs special handling */
7240 vlv_pllb_recal_opamp(dev_priv, pipe);
7242 /* Set up Tx target for periodic Rcomp update */
7243 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7245 /* Disable target IRef on PLL */
7246 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7247 reg_val &= 0x00ffffff;
7248 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7250 /* Disable fast lock */
7251 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7253 /* Set idtafcrecal before PLL is enabled */
7254 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7255 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7256 mdiv |= ((bestn << DPIO_N_SHIFT));
7257 mdiv |= (1 << DPIO_K_SHIFT);
7260 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7261 * but we don't support that).
7262 * Note: don't use the DAC post divider as it seems unstable.
7264 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7265 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7267 mdiv |= DPIO_ENABLE_CALIBRATION;
7268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7270 /* Set HBR and RBR LPF coefficients */
7271 if (pipe_config->port_clock == 162000 ||
7272 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7273 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7280 if (intel_crtc_has_dp_encoder(pipe_config)) {
7281 /* Use SSC source */
7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7288 } else { /* HDMI or VGA */
7289 /* Use bend source */
7291 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7298 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7299 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7300 if (intel_crtc_has_dp_encoder(pipe_config))
7301 coreclk |= 0x01000000;
7302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7304 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7305 mutex_unlock(&dev_priv->sb_lock);
7308 static void chv_prepare_pll(struct intel_crtc *crtc,
7309 const struct intel_crtc_state *pipe_config)
7311 struct drm_device *dev = crtc->base.dev;
7312 struct drm_i915_private *dev_priv = to_i915(dev);
7313 enum pipe pipe = crtc->pipe;
7314 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7315 u32 loopfilter, tribuf_calcntr;
7316 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7320 /* Enable Refclk and SSC */
7321 I915_WRITE(DPLL(pipe),
7322 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7324 /* No need to actually set up the DPLL with DSI */
7325 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7328 bestn = pipe_config->dpll.n;
7329 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7330 bestm1 = pipe_config->dpll.m1;
7331 bestm2 = pipe_config->dpll.m2 >> 22;
7332 bestp1 = pipe_config->dpll.p1;
7333 bestp2 = pipe_config->dpll.p2;
7334 vco = pipe_config->dpll.vco;
7338 mutex_lock(&dev_priv->sb_lock);
7340 /* p1 and p2 divider */
7341 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7342 5 << DPIO_CHV_S1_DIV_SHIFT |
7343 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7344 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7345 1 << DPIO_CHV_K_DIV_SHIFT);
7347 /* Feedback post-divider - m2 */
7348 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7350 /* Feedback refclk divider - n and m1 */
7351 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7352 DPIO_CHV_M1_DIV_BY_2 |
7353 1 << DPIO_CHV_N_DIV_SHIFT);
7355 /* M2 fraction division */
7356 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7358 /* M2 fraction division enable */
7359 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7360 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7361 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7363 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7364 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7366 /* Program digital lock detect threshold */
7367 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7368 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7369 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7370 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7372 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7373 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7376 if (vco == 5400000) {
7377 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7378 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7379 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7380 tribuf_calcntr = 0x9;
7381 } else if (vco <= 6200000) {
7382 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7383 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7384 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7385 tribuf_calcntr = 0x9;
7386 } else if (vco <= 6480000) {
7387 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7388 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7389 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7390 tribuf_calcntr = 0x8;
7392 /* Not supported. Apply the same limits as in the max case */
7393 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7394 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7395 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7398 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7400 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7401 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7402 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7403 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7406 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7407 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7410 mutex_unlock(&dev_priv->sb_lock);
7414 * vlv_force_pll_on - forcibly enable just the PLL
7415 * @dev_priv: i915 private structure
7416 * @pipe: pipe PLL to enable
7417 * @dpll: PLL configuration
7419 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7420 * in cases where we need the PLL enabled even when @pipe is not going to
7423 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7424 const struct dpll *dpll)
7426 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7427 struct intel_crtc_state *pipe_config;
7429 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7433 pipe_config->base.crtc = &crtc->base;
7434 pipe_config->pixel_multiplier = 1;
7435 pipe_config->dpll = *dpll;
7437 if (IS_CHERRYVIEW(dev_priv)) {
7438 chv_compute_dpll(crtc, pipe_config);
7439 chv_prepare_pll(crtc, pipe_config);
7440 chv_enable_pll(crtc, pipe_config);
7442 vlv_compute_dpll(crtc, pipe_config);
7443 vlv_prepare_pll(crtc, pipe_config);
7444 vlv_enable_pll(crtc, pipe_config);
7453 * vlv_force_pll_off - forcibly disable just the PLL
7454 * @dev_priv: i915 private structure
7455 * @pipe: pipe PLL to disable
7457 * Disable the PLL for @pipe. To be used in cases where we need
7458 * the PLL enabled even when @pipe is not going to be enabled.
7460 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7462 if (IS_CHERRYVIEW(dev_priv))
7463 chv_disable_pll(dev_priv, pipe);
7465 vlv_disable_pll(dev_priv, pipe);
7468 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7469 struct intel_crtc_state *crtc_state,
7470 struct dpll *reduced_clock)
7472 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7474 struct dpll *clock = &crtc_state->dpll;
7476 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7478 dpll = DPLL_VGA_MODE_DIS;
7480 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7481 dpll |= DPLLB_MODE_LVDS;
7483 dpll |= DPLLB_MODE_DAC_SERIAL;
7485 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7486 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7487 dpll |= (crtc_state->pixel_multiplier - 1)
7488 << SDVO_MULTIPLIER_SHIFT_HIRES;
7491 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7492 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7493 dpll |= DPLL_SDVO_HIGH_SPEED;
7495 if (intel_crtc_has_dp_encoder(crtc_state))
7496 dpll |= DPLL_SDVO_HIGH_SPEED;
7498 /* compute bitmask from p1 value */
7499 if (IS_PINEVIEW(dev_priv))
7500 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7502 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7503 if (IS_G4X(dev_priv) && reduced_clock)
7504 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7506 switch (clock->p2) {
7508 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7511 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7514 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7517 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7520 if (INTEL_GEN(dev_priv) >= 4)
7521 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7523 if (crtc_state->sdvo_tv_clock)
7524 dpll |= PLL_REF_INPUT_TVCLKINBC;
7525 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7526 intel_panel_use_ssc(dev_priv))
7527 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7529 dpll |= PLL_REF_INPUT_DREFCLK;
7531 dpll |= DPLL_VCO_ENABLE;
7532 crtc_state->dpll_hw_state.dpll = dpll;
7534 if (INTEL_GEN(dev_priv) >= 4) {
7535 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7536 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7537 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7541 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7542 struct intel_crtc_state *crtc_state,
7543 struct dpll *reduced_clock)
7545 struct drm_device *dev = crtc->base.dev;
7546 struct drm_i915_private *dev_priv = to_i915(dev);
7548 struct dpll *clock = &crtc_state->dpll;
7550 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7552 dpll = DPLL_VGA_MODE_DIS;
7554 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7555 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7558 dpll |= PLL_P1_DIVIDE_BY_TWO;
7560 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7562 dpll |= PLL_P2_DIVIDE_BY_4;
7567 * "[Almador Errata}: For the correct operation of the muxed DVO pins
7568 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
7569 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
7570 * Enable) must be set to “1” in both the DPLL A Control Register
7571 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
7573 * For simplicity We simply keep both bits always enabled in
7574 * both DPLLS. The spec says we should disable the DVO 2X clock
7575 * when not needed, but this seems to work fine in practice.
7577 if (IS_I830(dev_priv) ||
7578 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7579 dpll |= DPLL_DVO_2X_MODE;
7581 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7582 intel_panel_use_ssc(dev_priv))
7583 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7585 dpll |= PLL_REF_INPUT_DREFCLK;
7587 dpll |= DPLL_VCO_ENABLE;
7588 crtc_state->dpll_hw_state.dpll = dpll;
7591 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
7593 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7594 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7595 enum pipe pipe = crtc->pipe;
7596 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
7597 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
7598 u32 crtc_vtotal, crtc_vblank_end;
7601 /* We need to be careful not to changed the adjusted mode, for otherwise
7602 * the hw state checker will get angry at the mismatch. */
7603 crtc_vtotal = adjusted_mode->crtc_vtotal;
7604 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7606 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7607 /* the chip adds 2 halflines automatically */
7609 crtc_vblank_end -= 1;
7611 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7612 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7614 vsyncshift = adjusted_mode->crtc_hsync_start -
7615 adjusted_mode->crtc_htotal / 2;
7617 vsyncshift += adjusted_mode->crtc_htotal;
7620 if (INTEL_GEN(dev_priv) > 3)
7621 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7623 I915_WRITE(HTOTAL(cpu_transcoder),
7624 (adjusted_mode->crtc_hdisplay - 1) |
7625 ((adjusted_mode->crtc_htotal - 1) << 16));
7626 I915_WRITE(HBLANK(cpu_transcoder),
7627 (adjusted_mode->crtc_hblank_start - 1) |
7628 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7629 I915_WRITE(HSYNC(cpu_transcoder),
7630 (adjusted_mode->crtc_hsync_start - 1) |
7631 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7633 I915_WRITE(VTOTAL(cpu_transcoder),
7634 (adjusted_mode->crtc_vdisplay - 1) |
7635 ((crtc_vtotal - 1) << 16));
7636 I915_WRITE(VBLANK(cpu_transcoder),
7637 (adjusted_mode->crtc_vblank_start - 1) |
7638 ((crtc_vblank_end - 1) << 16));
7639 I915_WRITE(VSYNC(cpu_transcoder),
7640 (adjusted_mode->crtc_vsync_start - 1) |
7641 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7643 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7644 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7645 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7647 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7648 (pipe == PIPE_B || pipe == PIPE_C))
7649 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7653 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
7655 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7656 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7657 enum pipe pipe = crtc->pipe;
7659 /* pipesrc controls the size that is scaled from, which should
7660 * always be the user's requested size.
7662 I915_WRITE(PIPESRC(pipe),
7663 ((crtc_state->pipe_src_w - 1) << 16) |
7664 (crtc_state->pipe_src_h - 1));
7667 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7668 struct intel_crtc_state *pipe_config)
7670 struct drm_device *dev = crtc->base.dev;
7671 struct drm_i915_private *dev_priv = to_i915(dev);
7672 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7675 tmp = I915_READ(HTOTAL(cpu_transcoder));
7676 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7677 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7678 tmp = I915_READ(HBLANK(cpu_transcoder));
7679 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7680 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7681 tmp = I915_READ(HSYNC(cpu_transcoder));
7682 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7683 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7685 tmp = I915_READ(VTOTAL(cpu_transcoder));
7686 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7687 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7688 tmp = I915_READ(VBLANK(cpu_transcoder));
7689 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7690 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7691 tmp = I915_READ(VSYNC(cpu_transcoder));
7692 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7693 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7695 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7696 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7697 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7698 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7702 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7703 struct intel_crtc_state *pipe_config)
7705 struct drm_device *dev = crtc->base.dev;
7706 struct drm_i915_private *dev_priv = to_i915(dev);
7709 tmp = I915_READ(PIPESRC(crtc->pipe));
7710 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7711 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7713 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7714 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7717 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7718 struct intel_crtc_state *pipe_config)
7720 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7721 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7722 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7723 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7725 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7726 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7727 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7728 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7730 mode->flags = pipe_config->base.adjusted_mode.flags;
7731 mode->type = DRM_MODE_TYPE_DRIVER;
7733 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7735 mode->hsync = drm_mode_hsync(mode);
7736 mode->vrefresh = drm_mode_vrefresh(mode);
7737 drm_mode_set_name(mode);
7740 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
7742 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7748 /* we keep both pipes enabled on 830 */
7749 if (IS_I830(dev_priv))
7750 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
7752 if (crtc_state->double_wide)
7753 pipeconf |= PIPECONF_DOUBLE_WIDE;
7755 /* only g4x and later have fancy bpc/dither controls */
7756 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7757 IS_CHERRYVIEW(dev_priv)) {
7758 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7759 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
7760 pipeconf |= PIPECONF_DITHER_EN |
7761 PIPECONF_DITHER_TYPE_SP;
7763 switch (crtc_state->pipe_bpp) {
7765 pipeconf |= PIPECONF_6BPC;
7768 pipeconf |= PIPECONF_8BPC;
7771 pipeconf |= PIPECONF_10BPC;
7774 /* Case prevented by intel_choose_pipe_bpp_dither. */
7779 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7780 if (INTEL_GEN(dev_priv) < 4 ||
7781 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7782 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7784 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7786 pipeconf |= PIPECONF_PROGRESSIVE;
7789 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7790 crtc_state->limited_color_range)
7791 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7793 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
7795 I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
7796 POSTING_READ(PIPECONF(crtc->pipe));
7799 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7800 struct intel_crtc_state *crtc_state)
7802 struct drm_device *dev = crtc->base.dev;
7803 struct drm_i915_private *dev_priv = to_i915(dev);
7804 const struct intel_limit *limit;
7807 memset(&crtc_state->dpll_hw_state, 0,
7808 sizeof(crtc_state->dpll_hw_state));
7810 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7811 if (intel_panel_use_ssc(dev_priv)) {
7812 refclk = dev_priv->vbt.lvds_ssc_freq;
7813 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7816 limit = &intel_limits_i8xx_lvds;
7817 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7818 limit = &intel_limits_i8xx_dvo;
7820 limit = &intel_limits_i8xx_dac;
7823 if (!crtc_state->clock_set &&
7824 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7825 refclk, NULL, &crtc_state->dpll)) {
7826 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7830 i8xx_compute_dpll(crtc, crtc_state, NULL);
7835 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7836 struct intel_crtc_state *crtc_state)
7838 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7839 const struct intel_limit *limit;
7842 memset(&crtc_state->dpll_hw_state, 0,
7843 sizeof(crtc_state->dpll_hw_state));
7845 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7846 if (intel_panel_use_ssc(dev_priv)) {
7847 refclk = dev_priv->vbt.lvds_ssc_freq;
7848 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7851 if (intel_is_dual_link_lvds(dev_priv))
7852 limit = &intel_limits_g4x_dual_channel_lvds;
7854 limit = &intel_limits_g4x_single_channel_lvds;
7855 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7856 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7857 limit = &intel_limits_g4x_hdmi;
7858 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7859 limit = &intel_limits_g4x_sdvo;
7861 /* The option is for other outputs */
7862 limit = &intel_limits_i9xx_sdvo;
7865 if (!crtc_state->clock_set &&
7866 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7867 refclk, NULL, &crtc_state->dpll)) {
7868 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7872 i9xx_compute_dpll(crtc, crtc_state, NULL);
7877 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7878 struct intel_crtc_state *crtc_state)
7880 struct drm_device *dev = crtc->base.dev;
7881 struct drm_i915_private *dev_priv = to_i915(dev);
7882 const struct intel_limit *limit;
7885 memset(&crtc_state->dpll_hw_state, 0,
7886 sizeof(crtc_state->dpll_hw_state));
7888 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7889 if (intel_panel_use_ssc(dev_priv)) {
7890 refclk = dev_priv->vbt.lvds_ssc_freq;
7891 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7894 limit = &intel_limits_pineview_lvds;
7896 limit = &intel_limits_pineview_sdvo;
7899 if (!crtc_state->clock_set &&
7900 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7901 refclk, NULL, &crtc_state->dpll)) {
7902 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7906 i9xx_compute_dpll(crtc, crtc_state, NULL);
7911 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7912 struct intel_crtc_state *crtc_state)
7914 struct drm_device *dev = crtc->base.dev;
7915 struct drm_i915_private *dev_priv = to_i915(dev);
7916 const struct intel_limit *limit;
7919 memset(&crtc_state->dpll_hw_state, 0,
7920 sizeof(crtc_state->dpll_hw_state));
7922 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7923 if (intel_panel_use_ssc(dev_priv)) {
7924 refclk = dev_priv->vbt.lvds_ssc_freq;
7925 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7928 limit = &intel_limits_i9xx_lvds;
7930 limit = &intel_limits_i9xx_sdvo;
7933 if (!crtc_state->clock_set &&
7934 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7935 refclk, NULL, &crtc_state->dpll)) {
7936 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7940 i9xx_compute_dpll(crtc, crtc_state, NULL);
7945 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7946 struct intel_crtc_state *crtc_state)
7948 int refclk = 100000;
7949 const struct intel_limit *limit = &intel_limits_chv;
7951 memset(&crtc_state->dpll_hw_state, 0,
7952 sizeof(crtc_state->dpll_hw_state));
7954 if (!crtc_state->clock_set &&
7955 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7956 refclk, NULL, &crtc_state->dpll)) {
7957 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7961 chv_compute_dpll(crtc, crtc_state);
7966 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7967 struct intel_crtc_state *crtc_state)
7969 int refclk = 100000;
7970 const struct intel_limit *limit = &intel_limits_vlv;
7972 memset(&crtc_state->dpll_hw_state, 0,
7973 sizeof(crtc_state->dpll_hw_state));
7975 if (!crtc_state->clock_set &&
7976 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7977 refclk, NULL, &crtc_state->dpll)) {
7978 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7982 vlv_compute_dpll(crtc, crtc_state);
7987 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
7989 if (IS_I830(dev_priv))
7992 return INTEL_GEN(dev_priv) >= 4 ||
7993 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
7996 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7997 struct intel_crtc_state *pipe_config)
7999 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8002 if (!i9xx_has_pfit(dev_priv))
8005 tmp = I915_READ(PFIT_CONTROL);
8006 if (!(tmp & PFIT_ENABLE))
8009 /* Check whether the pfit is attached to our pipe. */
8010 if (INTEL_GEN(dev_priv) < 4) {
8011 if (crtc->pipe != PIPE_B)
8014 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8018 pipe_config->gmch_pfit.control = tmp;
8019 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8022 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8023 struct intel_crtc_state *pipe_config)
8025 struct drm_device *dev = crtc->base.dev;
8026 struct drm_i915_private *dev_priv = to_i915(dev);
8027 int pipe = pipe_config->cpu_transcoder;
8030 int refclk = 100000;
8032 /* In case of DSI, DPLL will not be used */
8033 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8036 mutex_lock(&dev_priv->sb_lock);
8037 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8038 mutex_unlock(&dev_priv->sb_lock);
8040 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8041 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8042 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8043 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8044 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8046 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8050 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8051 struct intel_initial_plane_config *plane_config)
8053 struct drm_device *dev = crtc->base.dev;
8054 struct drm_i915_private *dev_priv = to_i915(dev);
8055 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8056 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8058 u32 val, base, offset;
8059 int fourcc, pixel_format;
8060 unsigned int aligned_height;
8061 struct drm_framebuffer *fb;
8062 struct intel_framebuffer *intel_fb;
8064 if (!plane->get_hw_state(plane, &pipe))
8067 WARN_ON(pipe != crtc->pipe);
8069 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8071 DRM_DEBUG_KMS("failed to alloc fb\n");
8075 fb = &intel_fb->base;
8079 val = I915_READ(DSPCNTR(i9xx_plane));
8081 if (INTEL_GEN(dev_priv) >= 4) {
8082 if (val & DISPPLANE_TILED) {
8083 plane_config->tiling = I915_TILING_X;
8084 fb->modifier = I915_FORMAT_MOD_X_TILED;
8087 if (val & DISPPLANE_ROTATE_180)
8088 plane_config->rotation = DRM_MODE_ROTATE_180;
8091 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8092 val & DISPPLANE_MIRROR)
8093 plane_config->rotation |= DRM_MODE_REFLECT_X;
8095 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8096 fourcc = i9xx_format_to_fourcc(pixel_format);
8097 fb->format = drm_format_info(fourcc);
8099 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8100 offset = I915_READ(DSPOFFSET(i9xx_plane));
8101 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8102 } else if (INTEL_GEN(dev_priv) >= 4) {
8103 if (plane_config->tiling)
8104 offset = I915_READ(DSPTILEOFF(i9xx_plane));
8106 offset = I915_READ(DSPLINOFF(i9xx_plane));
8107 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8109 base = I915_READ(DSPADDR(i9xx_plane));
8111 plane_config->base = base;
8113 val = I915_READ(PIPESRC(pipe));
8114 fb->width = ((val >> 16) & 0xfff) + 1;
8115 fb->height = ((val >> 0) & 0xfff) + 1;
8117 val = I915_READ(DSPSTRIDE(i9xx_plane));
8118 fb->pitches[0] = val & 0xffffffc0;
8120 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8122 plane_config->size = fb->pitches[0] * aligned_height;
8124 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8125 crtc->base.name, plane->base.name, fb->width, fb->height,
8126 fb->format->cpp[0] * 8, base, fb->pitches[0],
8127 plane_config->size);
8129 plane_config->fb = intel_fb;
8132 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8133 struct intel_crtc_state *pipe_config)
8135 struct drm_device *dev = crtc->base.dev;
8136 struct drm_i915_private *dev_priv = to_i915(dev);
8137 int pipe = pipe_config->cpu_transcoder;
8138 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8140 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8141 int refclk = 100000;
8143 /* In case of DSI, DPLL will not be used */
8144 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8147 mutex_lock(&dev_priv->sb_lock);
8148 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8149 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8150 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8151 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8152 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8153 mutex_unlock(&dev_priv->sb_lock);
8155 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8156 clock.m2 = (pll_dw0 & 0xff) << 22;
8157 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8158 clock.m2 |= pll_dw2 & 0x3fffff;
8159 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8160 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8161 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8163 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8166 static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
8167 struct intel_crtc_state *pipe_config)
8169 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8170 enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
8172 pipe_config->lspcon_downsampling = false;
8174 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8175 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
8177 if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8178 bool ycbcr420_enabled = tmp & PIPEMISC_YUV420_ENABLE;
8179 bool blend = tmp & PIPEMISC_YUV420_MODE_FULL_BLEND;
8181 if (ycbcr420_enabled) {
8182 /* We support 4:2:0 in full blend mode only */
8184 output = INTEL_OUTPUT_FORMAT_INVALID;
8185 else if (!(IS_GEMINILAKE(dev_priv) ||
8186 INTEL_GEN(dev_priv) >= 10))
8187 output = INTEL_OUTPUT_FORMAT_INVALID;
8189 output = INTEL_OUTPUT_FORMAT_YCBCR420;
8192 * Currently there is no interface defined to
8193 * check user preference between RGB/YCBCR444
8194 * or YCBCR420. So the only possible case for
8195 * YCBCR444 usage is driving YCBCR420 output
8196 * with LSPCON, when pipe is configured for
8197 * YCBCR444 output and LSPCON takes care of
8200 pipe_config->lspcon_downsampling = true;
8201 output = INTEL_OUTPUT_FORMAT_YCBCR444;
8206 pipe_config->output_format = output;
8209 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8211 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8212 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8213 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8214 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8217 tmp = I915_READ(DSPCNTR(i9xx_plane));
8219 if (tmp & DISPPLANE_GAMMA_ENABLE)
8220 crtc_state->gamma_enable = true;
8222 if (!HAS_GMCH(dev_priv) &&
8223 tmp & DISPPLANE_PIPE_CSC_ENABLE)
8224 crtc_state->csc_enable = true;
8227 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8228 struct intel_crtc_state *pipe_config)
8230 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8231 enum intel_display_power_domain power_domain;
8232 intel_wakeref_t wakeref;
8236 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8237 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8241 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8242 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8243 pipe_config->shared_dpll = NULL;
8247 tmp = I915_READ(PIPECONF(crtc->pipe));
8248 if (!(tmp & PIPECONF_ENABLE))
8251 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8252 IS_CHERRYVIEW(dev_priv)) {
8253 switch (tmp & PIPECONF_BPC_MASK) {
8255 pipe_config->pipe_bpp = 18;
8258 pipe_config->pipe_bpp = 24;
8260 case PIPECONF_10BPC:
8261 pipe_config->pipe_bpp = 30;
8268 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8269 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8270 pipe_config->limited_color_range = true;
8272 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
8273 PIPECONF_GAMMA_MODE_SHIFT;
8275 if (IS_CHERRYVIEW(dev_priv))
8276 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
8278 i9xx_get_pipe_color_config(pipe_config);
8280 if (INTEL_GEN(dev_priv) < 4)
8281 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8283 intel_get_pipe_timings(crtc, pipe_config);
8284 intel_get_pipe_src_size(crtc, pipe_config);
8286 i9xx_get_pfit_config(crtc, pipe_config);
8288 if (INTEL_GEN(dev_priv) >= 4) {
8289 /* No way to read it out on pipes B and C */
8290 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8291 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8293 tmp = I915_READ(DPLL_MD(crtc->pipe));
8294 pipe_config->pixel_multiplier =
8295 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8296 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8297 pipe_config->dpll_hw_state.dpll_md = tmp;
8298 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8299 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8300 tmp = I915_READ(DPLL(crtc->pipe));
8301 pipe_config->pixel_multiplier =
8302 ((tmp & SDVO_MULTIPLIER_MASK)
8303 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8305 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8306 * port and will be fixed up in the encoder->get_config
8308 pipe_config->pixel_multiplier = 1;
8310 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8311 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8312 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8313 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8315 /* Mask out read-only status bits. */
8316 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8317 DPLL_PORTC_READY_MASK |
8318 DPLL_PORTB_READY_MASK);
8321 if (IS_CHERRYVIEW(dev_priv))
8322 chv_crtc_clock_get(crtc, pipe_config);
8323 else if (IS_VALLEYVIEW(dev_priv))
8324 vlv_crtc_clock_get(crtc, pipe_config);
8326 i9xx_crtc_clock_get(crtc, pipe_config);
8329 * Normally the dotclock is filled in by the encoder .get_config()
8330 * but in case the pipe is enabled w/o any ports we need a sane
8333 pipe_config->base.adjusted_mode.crtc_clock =
8334 pipe_config->port_clock / pipe_config->pixel_multiplier;
8339 intel_display_power_put(dev_priv, power_domain, wakeref);
8344 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
8346 struct intel_encoder *encoder;
8349 bool has_lvds = false;
8350 bool has_cpu_edp = false;
8351 bool has_panel = false;
8352 bool has_ck505 = false;
8353 bool can_ssc = false;
8354 bool using_ssc_source = false;
8356 /* We need to take the global config into account */
8357 for_each_intel_encoder(&dev_priv->drm, encoder) {
8358 switch (encoder->type) {
8359 case INTEL_OUTPUT_LVDS:
8363 case INTEL_OUTPUT_EDP:
8365 if (encoder->port == PORT_A)
8373 if (HAS_PCH_IBX(dev_priv)) {
8374 has_ck505 = dev_priv->vbt.display_clock_mode;
8375 can_ssc = has_ck505;
8381 /* Check if any DPLLs are using the SSC source */
8382 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8383 u32 temp = I915_READ(PCH_DPLL(i));
8385 if (!(temp & DPLL_VCO_ENABLE))
8388 if ((temp & PLL_REF_INPUT_MASK) ==
8389 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8390 using_ssc_source = true;
8395 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8396 has_panel, has_lvds, has_ck505, using_ssc_source);
8398 /* Ironlake: try to setup display ref clock before DPLL
8399 * enabling. This is only under driver's control after
8400 * PCH B stepping, previous chipset stepping should be
8401 * ignoring this setting.
8403 val = I915_READ(PCH_DREF_CONTROL);
8405 /* As we must carefully and slowly disable/enable each source in turn,
8406 * compute the final state we want first and check if we need to
8407 * make any changes at all.
8410 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8412 final |= DREF_NONSPREAD_CK505_ENABLE;
8414 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8416 final &= ~DREF_SSC_SOURCE_MASK;
8417 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8418 final &= ~DREF_SSC1_ENABLE;
8421 final |= DREF_SSC_SOURCE_ENABLE;
8423 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8424 final |= DREF_SSC1_ENABLE;
8427 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8428 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8430 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8432 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8433 } else if (using_ssc_source) {
8434 final |= DREF_SSC_SOURCE_ENABLE;
8435 final |= DREF_SSC1_ENABLE;
8441 /* Always enable nonspread source */
8442 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8445 val |= DREF_NONSPREAD_CK505_ENABLE;
8447 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8450 val &= ~DREF_SSC_SOURCE_MASK;
8451 val |= DREF_SSC_SOURCE_ENABLE;
8453 /* SSC must be turned on before enabling the CPU output */
8454 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8455 DRM_DEBUG_KMS("Using SSC on panel\n");
8456 val |= DREF_SSC1_ENABLE;
8458 val &= ~DREF_SSC1_ENABLE;
8460 /* Get SSC going before enabling the outputs */
8461 I915_WRITE(PCH_DREF_CONTROL, val);
8462 POSTING_READ(PCH_DREF_CONTROL);
8465 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8467 /* Enable CPU source on CPU attached eDP */
8469 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8470 DRM_DEBUG_KMS("Using SSC on eDP\n");
8471 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8473 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8475 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8477 I915_WRITE(PCH_DREF_CONTROL, val);
8478 POSTING_READ(PCH_DREF_CONTROL);
8481 DRM_DEBUG_KMS("Disabling CPU source output\n");
8483 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8485 /* Turn off CPU output */
8486 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8488 I915_WRITE(PCH_DREF_CONTROL, val);
8489 POSTING_READ(PCH_DREF_CONTROL);
8492 if (!using_ssc_source) {
8493 DRM_DEBUG_KMS("Disabling SSC source\n");
8495 /* Turn off the SSC source */
8496 val &= ~DREF_SSC_SOURCE_MASK;
8497 val |= DREF_SSC_SOURCE_DISABLE;
8500 val &= ~DREF_SSC1_ENABLE;
8502 I915_WRITE(PCH_DREF_CONTROL, val);
8503 POSTING_READ(PCH_DREF_CONTROL);
8508 BUG_ON(val != final);
8511 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8515 tmp = I915_READ(SOUTH_CHICKEN2);
8516 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8517 I915_WRITE(SOUTH_CHICKEN2, tmp);
8519 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8520 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8521 DRM_ERROR("FDI mPHY reset assert timeout\n");
8523 tmp = I915_READ(SOUTH_CHICKEN2);
8524 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8525 I915_WRITE(SOUTH_CHICKEN2, tmp);
8527 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8528 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8529 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8532 /* WaMPhyProgramming:hsw */
8533 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8537 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8538 tmp &= ~(0xFF << 24);
8539 tmp |= (0x12 << 24);
8540 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8542 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8544 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8546 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8548 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8550 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8551 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8552 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8554 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8555 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8556 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8558 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8561 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8563 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8566 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8568 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8571 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8573 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8576 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8578 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8579 tmp &= ~(0xFF << 16);
8580 tmp |= (0x1C << 16);
8581 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8583 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8584 tmp &= ~(0xFF << 16);
8585 tmp |= (0x1C << 16);
8586 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8588 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8590 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8592 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8594 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8596 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8597 tmp &= ~(0xF << 28);
8599 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8601 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8602 tmp &= ~(0xF << 28);
8604 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8607 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8608 * Programming" based on the parameters passed:
8609 * - Sequence to enable CLKOUT_DP
8610 * - Sequence to enable CLKOUT_DP without spread
8611 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8613 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8614 bool with_spread, bool with_fdi)
8618 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8620 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8621 with_fdi, "LP PCH doesn't have FDI\n"))
8624 mutex_lock(&dev_priv->sb_lock);
8626 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8627 tmp &= ~SBI_SSCCTL_DISABLE;
8628 tmp |= SBI_SSCCTL_PATHALT;
8629 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8634 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8635 tmp &= ~SBI_SSCCTL_PATHALT;
8636 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8639 lpt_reset_fdi_mphy(dev_priv);
8640 lpt_program_fdi_mphy(dev_priv);
8644 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8645 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8646 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8647 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8649 mutex_unlock(&dev_priv->sb_lock);
8652 /* Sequence to disable CLKOUT_DP */
8653 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8657 mutex_lock(&dev_priv->sb_lock);
8659 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8660 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8661 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8662 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8664 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8665 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8666 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8667 tmp |= SBI_SSCCTL_PATHALT;
8668 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8671 tmp |= SBI_SSCCTL_DISABLE;
8672 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8675 mutex_unlock(&dev_priv->sb_lock);
8678 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8680 static const u16 sscdivintphase[] = {
8681 [BEND_IDX( 50)] = 0x3B23,
8682 [BEND_IDX( 45)] = 0x3B23,
8683 [BEND_IDX( 40)] = 0x3C23,
8684 [BEND_IDX( 35)] = 0x3C23,
8685 [BEND_IDX( 30)] = 0x3D23,
8686 [BEND_IDX( 25)] = 0x3D23,
8687 [BEND_IDX( 20)] = 0x3E23,
8688 [BEND_IDX( 15)] = 0x3E23,
8689 [BEND_IDX( 10)] = 0x3F23,
8690 [BEND_IDX( 5)] = 0x3F23,
8691 [BEND_IDX( 0)] = 0x0025,
8692 [BEND_IDX( -5)] = 0x0025,
8693 [BEND_IDX(-10)] = 0x0125,
8694 [BEND_IDX(-15)] = 0x0125,
8695 [BEND_IDX(-20)] = 0x0225,
8696 [BEND_IDX(-25)] = 0x0225,
8697 [BEND_IDX(-30)] = 0x0325,
8698 [BEND_IDX(-35)] = 0x0325,
8699 [BEND_IDX(-40)] = 0x0425,
8700 [BEND_IDX(-45)] = 0x0425,
8701 [BEND_IDX(-50)] = 0x0525,
8706 * steps -50 to 50 inclusive, in steps of 5
8707 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8708 * change in clock period = -(steps / 10) * 5.787 ps
8710 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8713 int idx = BEND_IDX(steps);
8715 if (WARN_ON(steps % 5 != 0))
8718 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8721 mutex_lock(&dev_priv->sb_lock);
8723 if (steps % 10 != 0)
8727 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8729 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8731 tmp |= sscdivintphase[idx];
8732 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8734 mutex_unlock(&dev_priv->sb_lock);
8739 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8741 struct intel_encoder *encoder;
8742 bool has_vga = false;
8744 for_each_intel_encoder(&dev_priv->drm, encoder) {
8745 switch (encoder->type) {
8746 case INTEL_OUTPUT_ANALOG:
8755 lpt_bend_clkout_dp(dev_priv, 0);
8756 lpt_enable_clkout_dp(dev_priv, true, true);
8758 lpt_disable_clkout_dp(dev_priv);
8763 * Initialize reference clocks when the driver loads
8765 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8767 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8768 ironlake_init_pch_refclk(dev_priv);
8769 else if (HAS_PCH_LPT(dev_priv))
8770 lpt_init_pch_refclk(dev_priv);
8773 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
8775 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8776 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8777 enum pipe pipe = crtc->pipe;
8782 switch (crtc_state->pipe_bpp) {
8784 val |= PIPECONF_6BPC;
8787 val |= PIPECONF_8BPC;
8790 val |= PIPECONF_10BPC;
8793 val |= PIPECONF_12BPC;
8796 /* Case prevented by intel_choose_pipe_bpp_dither. */
8800 if (crtc_state->dither)
8801 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8803 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8804 val |= PIPECONF_INTERLACED_ILK;
8806 val |= PIPECONF_PROGRESSIVE;
8808 if (crtc_state->limited_color_range)
8809 val |= PIPECONF_COLOR_RANGE_SELECT;
8811 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8813 I915_WRITE(PIPECONF(pipe), val);
8814 POSTING_READ(PIPECONF(pipe));
8817 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
8819 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8820 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8821 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8824 if (IS_HASWELL(dev_priv) && crtc_state->dither)
8825 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8827 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8828 val |= PIPECONF_INTERLACED_ILK;
8830 val |= PIPECONF_PROGRESSIVE;
8832 I915_WRITE(PIPECONF(cpu_transcoder), val);
8833 POSTING_READ(PIPECONF(cpu_transcoder));
8836 static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state)
8838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
8839 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8841 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8844 switch (crtc_state->pipe_bpp) {
8846 val |= PIPEMISC_DITHER_6_BPC;
8849 val |= PIPEMISC_DITHER_8_BPC;
8852 val |= PIPEMISC_DITHER_10_BPC;
8855 val |= PIPEMISC_DITHER_12_BPC;
8858 /* Case prevented by pipe_config_set_bpp. */
8862 if (crtc_state->dither)
8863 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8865 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8866 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
8867 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
8869 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
8870 val |= PIPEMISC_YUV420_ENABLE |
8871 PIPEMISC_YUV420_MODE_FULL_BLEND;
8873 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8877 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8880 * Account for spread spectrum to avoid
8881 * oversubscribing the link. Max center spread
8882 * is 2.5%; use 5% for safety's sake.
8884 u32 bps = target_clock * bpp * 21 / 20;
8885 return DIV_ROUND_UP(bps, link_bw * 8);
8888 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8890 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8893 static void ironlake_compute_dpll(struct intel_crtc *crtc,
8894 struct intel_crtc_state *crtc_state,
8895 struct dpll *reduced_clock)
8897 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8901 /* Enable autotuning of the PLL clock (if permissible) */
8903 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8904 if ((intel_panel_use_ssc(dev_priv) &&
8905 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8906 (HAS_PCH_IBX(dev_priv) &&
8907 intel_is_dual_link_lvds(dev_priv)))
8909 } else if (crtc_state->sdvo_tv_clock) {
8913 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8915 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8918 if (reduced_clock) {
8919 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8921 if (reduced_clock->m < factor * reduced_clock->n)
8929 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8930 dpll |= DPLLB_MODE_LVDS;
8932 dpll |= DPLLB_MODE_DAC_SERIAL;
8934 dpll |= (crtc_state->pixel_multiplier - 1)
8935 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8937 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8938 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8939 dpll |= DPLL_SDVO_HIGH_SPEED;
8941 if (intel_crtc_has_dp_encoder(crtc_state))
8942 dpll |= DPLL_SDVO_HIGH_SPEED;
8945 * The high speed IO clock is only really required for
8946 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8947 * possible to share the DPLL between CRT and HDMI. Enabling
8948 * the clock needlessly does no real harm, except use up a
8949 * bit of power potentially.
8951 * We'll limit this to IVB with 3 pipes, since it has only two
8952 * DPLLs and so DPLL sharing is the only way to get three pipes
8953 * driving PCH ports at the same time. On SNB we could do this,
8954 * and potentially avoid enabling the second DPLL, but it's not
8955 * clear if it''s a win or loss power wise. No point in doing
8956 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8958 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8959 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8960 dpll |= DPLL_SDVO_HIGH_SPEED;
8962 /* compute bitmask from p1 value */
8963 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8965 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8967 switch (crtc_state->dpll.p2) {
8969 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8972 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8975 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8978 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8982 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8983 intel_panel_use_ssc(dev_priv))
8984 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8986 dpll |= PLL_REF_INPUT_DREFCLK;
8988 dpll |= DPLL_VCO_ENABLE;
8990 crtc_state->dpll_hw_state.dpll = dpll;
8991 crtc_state->dpll_hw_state.fp0 = fp;
8992 crtc_state->dpll_hw_state.fp1 = fp2;
8995 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8996 struct intel_crtc_state *crtc_state)
8998 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8999 const struct intel_limit *limit;
9000 int refclk = 120000;
9002 memset(&crtc_state->dpll_hw_state, 0,
9003 sizeof(crtc_state->dpll_hw_state));
9005 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9006 if (!crtc_state->has_pch_encoder)
9009 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9010 if (intel_panel_use_ssc(dev_priv)) {
9011 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9012 dev_priv->vbt.lvds_ssc_freq);
9013 refclk = dev_priv->vbt.lvds_ssc_freq;
9016 if (intel_is_dual_link_lvds(dev_priv)) {
9017 if (refclk == 100000)
9018 limit = &intel_limits_ironlake_dual_lvds_100m;
9020 limit = &intel_limits_ironlake_dual_lvds;
9022 if (refclk == 100000)
9023 limit = &intel_limits_ironlake_single_lvds_100m;
9025 limit = &intel_limits_ironlake_single_lvds;
9028 limit = &intel_limits_ironlake_dac;
9031 if (!crtc_state->clock_set &&
9032 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9033 refclk, NULL, &crtc_state->dpll)) {
9034 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9038 ironlake_compute_dpll(crtc, crtc_state, NULL);
9040 if (!intel_get_shared_dpll(crtc_state, NULL)) {
9041 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9042 pipe_name(crtc->pipe));
9049 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9050 struct intel_link_m_n *m_n)
9052 struct drm_device *dev = crtc->base.dev;
9053 struct drm_i915_private *dev_priv = to_i915(dev);
9054 enum pipe pipe = crtc->pipe;
9056 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9057 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9058 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9060 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9061 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9062 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9065 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9066 enum transcoder transcoder,
9067 struct intel_link_m_n *m_n,
9068 struct intel_link_m_n *m2_n2)
9070 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9071 enum pipe pipe = crtc->pipe;
9073 if (INTEL_GEN(dev_priv) >= 5) {
9074 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9075 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9076 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9078 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9079 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9080 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9082 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9083 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9084 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9085 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9087 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9088 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9089 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9092 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9093 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9094 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9096 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9097 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9098 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9102 void intel_dp_get_m_n(struct intel_crtc *crtc,
9103 struct intel_crtc_state *pipe_config)
9105 if (pipe_config->has_pch_encoder)
9106 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9108 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9109 &pipe_config->dp_m_n,
9110 &pipe_config->dp_m2_n2);
9113 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9114 struct intel_crtc_state *pipe_config)
9116 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9117 &pipe_config->fdi_m_n, NULL);
9120 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9121 struct intel_crtc_state *pipe_config)
9123 struct drm_device *dev = crtc->base.dev;
9124 struct drm_i915_private *dev_priv = to_i915(dev);
9125 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9130 /* find scaler attached to this pipe */
9131 for (i = 0; i < crtc->num_scalers; i++) {
9132 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9133 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9135 pipe_config->pch_pfit.enabled = true;
9136 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9137 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9138 scaler_state->scalers[i].in_use = true;
9143 scaler_state->scaler_id = id;
9145 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9147 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9152 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9153 struct intel_initial_plane_config *plane_config)
9155 struct drm_device *dev = crtc->base.dev;
9156 struct drm_i915_private *dev_priv = to_i915(dev);
9157 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9158 enum plane_id plane_id = plane->id;
9160 u32 val, base, offset, stride_mult, tiling, alpha;
9161 int fourcc, pixel_format;
9162 unsigned int aligned_height;
9163 struct drm_framebuffer *fb;
9164 struct intel_framebuffer *intel_fb;
9166 if (!plane->get_hw_state(plane, &pipe))
9169 WARN_ON(pipe != crtc->pipe);
9171 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9173 DRM_DEBUG_KMS("failed to alloc fb\n");
9177 fb = &intel_fb->base;
9181 val = I915_READ(PLANE_CTL(pipe, plane_id));
9183 if (INTEL_GEN(dev_priv) >= 11)
9184 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
9186 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9188 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
9189 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
9190 alpha &= PLANE_COLOR_ALPHA_MASK;
9192 alpha = val & PLANE_CTL_ALPHA_MASK;
9195 fourcc = skl_format_to_fourcc(pixel_format,
9196 val & PLANE_CTL_ORDER_RGBX, alpha);
9197 fb->format = drm_format_info(fourcc);
9199 tiling = val & PLANE_CTL_TILED_MASK;
9201 case PLANE_CTL_TILED_LINEAR:
9202 fb->modifier = DRM_FORMAT_MOD_LINEAR;
9204 case PLANE_CTL_TILED_X:
9205 plane_config->tiling = I915_TILING_X;
9206 fb->modifier = I915_FORMAT_MOD_X_TILED;
9208 case PLANE_CTL_TILED_Y:
9209 plane_config->tiling = I915_TILING_Y;
9210 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9211 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
9213 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9215 case PLANE_CTL_TILED_YF:
9216 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9217 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
9219 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9222 MISSING_CASE(tiling);
9227 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
9228 * while i915 HW rotation is clockwise, thats why this swapping.
9230 switch (val & PLANE_CTL_ROTATE_MASK) {
9231 case PLANE_CTL_ROTATE_0:
9232 plane_config->rotation = DRM_MODE_ROTATE_0;
9234 case PLANE_CTL_ROTATE_90:
9235 plane_config->rotation = DRM_MODE_ROTATE_270;
9237 case PLANE_CTL_ROTATE_180:
9238 plane_config->rotation = DRM_MODE_ROTATE_180;
9240 case PLANE_CTL_ROTATE_270:
9241 plane_config->rotation = DRM_MODE_ROTATE_90;
9245 if (INTEL_GEN(dev_priv) >= 10 &&
9246 val & PLANE_CTL_FLIP_HORIZONTAL)
9247 plane_config->rotation |= DRM_MODE_REFLECT_X;
9249 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
9250 plane_config->base = base;
9252 offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
9254 val = I915_READ(PLANE_SIZE(pipe, plane_id));
9255 fb->height = ((val >> 16) & 0xfff) + 1;
9256 fb->width = ((val >> 0) & 0x1fff) + 1;
9258 val = I915_READ(PLANE_STRIDE(pipe, plane_id));
9259 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
9260 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9262 aligned_height = intel_fb_align_height(fb, 0, fb->height);
9264 plane_config->size = fb->pitches[0] * aligned_height;
9266 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9267 crtc->base.name, plane->base.name, fb->width, fb->height,
9268 fb->format->cpp[0] * 8, base, fb->pitches[0],
9269 plane_config->size);
9271 plane_config->fb = intel_fb;
9278 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9279 struct intel_crtc_state *pipe_config)
9281 struct drm_device *dev = crtc->base.dev;
9282 struct drm_i915_private *dev_priv = to_i915(dev);
9285 tmp = I915_READ(PF_CTL(crtc->pipe));
9287 if (tmp & PF_ENABLE) {
9288 pipe_config->pch_pfit.enabled = true;
9289 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9290 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9292 /* We currently do not free assignements of panel fitters on
9293 * ivb/hsw (since we don't use the higher upscaling modes which
9294 * differentiates them) so just WARN about this case for now. */
9295 if (IS_GEN(dev_priv, 7)) {
9296 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9297 PF_PIPE_SEL_IVB(crtc->pipe));
9302 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9303 struct intel_crtc_state *pipe_config)
9305 struct drm_device *dev = crtc->base.dev;
9306 struct drm_i915_private *dev_priv = to_i915(dev);
9307 enum intel_display_power_domain power_domain;
9308 intel_wakeref_t wakeref;
9312 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9313 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9317 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9318 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9319 pipe_config->shared_dpll = NULL;
9322 tmp = I915_READ(PIPECONF(crtc->pipe));
9323 if (!(tmp & PIPECONF_ENABLE))
9326 switch (tmp & PIPECONF_BPC_MASK) {
9328 pipe_config->pipe_bpp = 18;
9331 pipe_config->pipe_bpp = 24;
9333 case PIPECONF_10BPC:
9334 pipe_config->pipe_bpp = 30;
9336 case PIPECONF_12BPC:
9337 pipe_config->pipe_bpp = 36;
9343 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9344 pipe_config->limited_color_range = true;
9346 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
9347 PIPECONF_GAMMA_MODE_SHIFT;
9349 pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
9351 i9xx_get_pipe_color_config(pipe_config);
9353 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9354 struct intel_shared_dpll *pll;
9355 enum intel_dpll_id pll_id;
9357 pipe_config->has_pch_encoder = true;
9359 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9360 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9361 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9363 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9365 if (HAS_PCH_IBX(dev_priv)) {
9367 * The pipe->pch transcoder and pch transcoder->pll
9370 pll_id = (enum intel_dpll_id) crtc->pipe;
9372 tmp = I915_READ(PCH_DPLL_SEL);
9373 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9374 pll_id = DPLL_ID_PCH_PLL_B;
9376 pll_id= DPLL_ID_PCH_PLL_A;
9379 pipe_config->shared_dpll =
9380 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9381 pll = pipe_config->shared_dpll;
9383 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9384 &pipe_config->dpll_hw_state));
9386 tmp = pipe_config->dpll_hw_state.dpll;
9387 pipe_config->pixel_multiplier =
9388 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9389 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9391 ironlake_pch_clock_get(crtc, pipe_config);
9393 pipe_config->pixel_multiplier = 1;
9396 intel_get_pipe_timings(crtc, pipe_config);
9397 intel_get_pipe_src_size(crtc, pipe_config);
9399 ironlake_get_pfit_config(crtc, pipe_config);
9404 intel_display_power_put(dev_priv, power_domain, wakeref);
9409 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9411 struct drm_device *dev = &dev_priv->drm;
9412 struct intel_crtc *crtc;
9414 for_each_intel_crtc(dev, crtc)
9415 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9416 pipe_name(crtc->pipe));
9418 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
9419 "Display power well on\n");
9420 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9421 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9422 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9423 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9424 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9425 "CPU PWM1 enabled\n");
9426 if (IS_HASWELL(dev_priv))
9427 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9428 "CPU PWM2 enabled\n");
9429 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9430 "PCH PWM1 enabled\n");
9431 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9432 "Utility pin enabled\n");
9433 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9436 * In theory we can still leave IRQs enabled, as long as only the HPD
9437 * interrupts remain enabled. We used to check for that, but since it's
9438 * gen-specific and since we only disable LCPLL after we fully disable
9439 * the interrupts, the check below should be enough.
9441 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9444 static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
9446 if (IS_HASWELL(dev_priv))
9447 return I915_READ(D_COMP_HSW);
9449 return I915_READ(D_COMP_BDW);
9452 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
9454 if (IS_HASWELL(dev_priv)) {
9455 mutex_lock(&dev_priv->pcu_lock);
9456 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9458 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
9459 mutex_unlock(&dev_priv->pcu_lock);
9461 I915_WRITE(D_COMP_BDW, val);
9462 POSTING_READ(D_COMP_BDW);
9467 * This function implements pieces of two sequences from BSpec:
9468 * - Sequence for display software to disable LCPLL
9469 * - Sequence for display software to allow package C8+
9470 * The steps implemented here are just the steps that actually touch the LCPLL
9471 * register. Callers should take care of disabling all the display engine
9472 * functions, doing the mode unset, fixing interrupts, etc.
9474 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9475 bool switch_to_fclk, bool allow_power_down)
9479 assert_can_disable_lcpll(dev_priv);
9481 val = I915_READ(LCPLL_CTL);
9483 if (switch_to_fclk) {
9484 val |= LCPLL_CD_SOURCE_FCLK;
9485 I915_WRITE(LCPLL_CTL, val);
9487 if (wait_for_us(I915_READ(LCPLL_CTL) &
9488 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9489 DRM_ERROR("Switching to FCLK failed\n");
9491 val = I915_READ(LCPLL_CTL);
9494 val |= LCPLL_PLL_DISABLE;
9495 I915_WRITE(LCPLL_CTL, val);
9496 POSTING_READ(LCPLL_CTL);
9498 if (intel_wait_for_register(&dev_priv->uncore,
9499 LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9500 DRM_ERROR("LCPLL still locked\n");
9502 val = hsw_read_dcomp(dev_priv);
9503 val |= D_COMP_COMP_DISABLE;
9504 hsw_write_dcomp(dev_priv, val);
9507 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9509 DRM_ERROR("D_COMP RCOMP still in progress\n");
9511 if (allow_power_down) {
9512 val = I915_READ(LCPLL_CTL);
9513 val |= LCPLL_POWER_DOWN_ALLOW;
9514 I915_WRITE(LCPLL_CTL, val);
9515 POSTING_READ(LCPLL_CTL);
9520 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9523 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9527 val = I915_READ(LCPLL_CTL);
9529 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9530 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9534 * Make sure we're not on PC8 state before disabling PC8, otherwise
9535 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9537 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
9539 if (val & LCPLL_POWER_DOWN_ALLOW) {
9540 val &= ~LCPLL_POWER_DOWN_ALLOW;
9541 I915_WRITE(LCPLL_CTL, val);
9542 POSTING_READ(LCPLL_CTL);
9545 val = hsw_read_dcomp(dev_priv);
9546 val |= D_COMP_COMP_FORCE;
9547 val &= ~D_COMP_COMP_DISABLE;
9548 hsw_write_dcomp(dev_priv, val);
9550 val = I915_READ(LCPLL_CTL);
9551 val &= ~LCPLL_PLL_DISABLE;
9552 I915_WRITE(LCPLL_CTL, val);
9554 if (intel_wait_for_register(&dev_priv->uncore,
9555 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9557 DRM_ERROR("LCPLL not locked yet\n");
9559 if (val & LCPLL_CD_SOURCE_FCLK) {
9560 val = I915_READ(LCPLL_CTL);
9561 val &= ~LCPLL_CD_SOURCE_FCLK;
9562 I915_WRITE(LCPLL_CTL, val);
9564 if (wait_for_us((I915_READ(LCPLL_CTL) &
9565 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9566 DRM_ERROR("Switching back to LCPLL failed\n");
9569 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
9571 intel_update_cdclk(dev_priv);
9572 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
9576 * Package states C8 and deeper are really deep PC states that can only be
9577 * reached when all the devices on the system allow it, so even if the graphics
9578 * device allows PC8+, it doesn't mean the system will actually get to these
9579 * states. Our driver only allows PC8+ when going into runtime PM.
9581 * The requirements for PC8+ are that all the outputs are disabled, the power
9582 * well is disabled and most interrupts are disabled, and these are also
9583 * requirements for runtime PM. When these conditions are met, we manually do
9584 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9585 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9588 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9589 * the state of some registers, so when we come back from PC8+ we need to
9590 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9591 * need to take care of the registers kept by RC6. Notice that this happens even
9592 * if we don't put the device in PCI D3 state (which is what currently happens
9593 * because of the runtime PM support).
9595 * For more, read "Display Sequences for Package C8" on the hardware
9598 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9602 DRM_DEBUG_KMS("Enabling package C8+\n");
9604 if (HAS_PCH_LPT_LP(dev_priv)) {
9605 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9606 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9607 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9610 lpt_disable_clkout_dp(dev_priv);
9611 hsw_disable_lcpll(dev_priv, true, true);
9614 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9618 DRM_DEBUG_KMS("Disabling package C8+\n");
9620 hsw_restore_lcpll(dev_priv);
9621 lpt_init_pch_refclk(dev_priv);
9623 if (HAS_PCH_LPT_LP(dev_priv)) {
9624 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9625 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9626 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9630 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9631 struct intel_crtc_state *crtc_state)
9633 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9634 struct intel_atomic_state *state =
9635 to_intel_atomic_state(crtc_state->base.state);
9637 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
9638 INTEL_GEN(dev_priv) >= 11) {
9639 struct intel_encoder *encoder =
9640 intel_get_crtc_new_encoder(state, crtc_state);
9642 if (!intel_get_shared_dpll(crtc_state, encoder)) {
9643 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9644 pipe_name(crtc->pipe));
9652 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9654 struct intel_crtc_state *pipe_config)
9656 enum intel_dpll_id id;
9659 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9660 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9662 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9665 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9668 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
9670 struct intel_crtc_state *pipe_config)
9672 enum intel_dpll_id id;
9675 /* TODO: TBT pll not implemented. */
9676 if (intel_port_is_combophy(dev_priv, port)) {
9677 temp = I915_READ(DPCLKA_CFGCR0_ICL) &
9678 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9679 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9680 } else if (intel_port_is_tc(dev_priv, port)) {
9681 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
9683 WARN(1, "Invalid port %x\n", port);
9687 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9690 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9692 struct intel_crtc_state *pipe_config)
9694 enum intel_dpll_id id;
9698 id = DPLL_ID_SKL_DPLL0;
9701 id = DPLL_ID_SKL_DPLL1;
9704 id = DPLL_ID_SKL_DPLL2;
9707 DRM_ERROR("Incorrect port type\n");
9711 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9714 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9716 struct intel_crtc_state *pipe_config)
9718 enum intel_dpll_id id;
9721 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9722 id = temp >> (port * 3 + 1);
9724 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9727 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9730 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9732 struct intel_crtc_state *pipe_config)
9734 enum intel_dpll_id id;
9735 u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9737 switch (ddi_pll_sel) {
9738 case PORT_CLK_SEL_WRPLL1:
9739 id = DPLL_ID_WRPLL1;
9741 case PORT_CLK_SEL_WRPLL2:
9742 id = DPLL_ID_WRPLL2;
9744 case PORT_CLK_SEL_SPLL:
9747 case PORT_CLK_SEL_LCPLL_810:
9748 id = DPLL_ID_LCPLL_810;
9750 case PORT_CLK_SEL_LCPLL_1350:
9751 id = DPLL_ID_LCPLL_1350;
9753 case PORT_CLK_SEL_LCPLL_2700:
9754 id = DPLL_ID_LCPLL_2700;
9757 MISSING_CASE(ddi_pll_sel);
9759 case PORT_CLK_SEL_NONE:
9763 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9766 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9767 struct intel_crtc_state *pipe_config,
9768 u64 *power_domain_mask,
9769 intel_wakeref_t *wakerefs)
9771 struct drm_device *dev = crtc->base.dev;
9772 struct drm_i915_private *dev_priv = to_i915(dev);
9773 enum intel_display_power_domain power_domain;
9774 unsigned long panel_transcoder_mask = 0;
9775 unsigned long enabled_panel_transcoders = 0;
9776 enum transcoder panel_transcoder;
9780 if (INTEL_GEN(dev_priv) >= 11)
9781 panel_transcoder_mask |=
9782 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
9784 if (HAS_TRANSCODER_EDP(dev_priv))
9785 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
9788 * The pipe->transcoder mapping is fixed with the exception of the eDP
9789 * and DSI transcoders handled below.
9791 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9794 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9795 * consistency and less surprising code; it's in always on power).
9797 for_each_set_bit(panel_transcoder,
9798 &panel_transcoder_mask,
9799 ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
9800 enum pipe trans_pipe;
9802 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
9803 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
9807 * Log all enabled ones, only use the first one.
9809 * FIXME: This won't work for two separate DSI displays.
9811 enabled_panel_transcoders |= BIT(panel_transcoder);
9812 if (enabled_panel_transcoders != BIT(panel_transcoder))
9815 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9817 WARN(1, "unknown pipe linked to transcoder %s\n",
9818 transcoder_name(panel_transcoder));
9820 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9821 case TRANS_DDI_EDP_INPUT_A_ON:
9822 trans_pipe = PIPE_A;
9824 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9825 trans_pipe = PIPE_B;
9827 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9828 trans_pipe = PIPE_C;
9832 if (trans_pipe == crtc->pipe)
9833 pipe_config->cpu_transcoder = panel_transcoder;
9837 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
9839 WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
9840 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
9842 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9843 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
9845 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
9849 wakerefs[power_domain] = wf;
9850 *power_domain_mask |= BIT_ULL(power_domain);
9852 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9854 return tmp & PIPECONF_ENABLE;
9857 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9858 struct intel_crtc_state *pipe_config,
9859 u64 *power_domain_mask,
9860 intel_wakeref_t *wakerefs)
9862 struct drm_device *dev = crtc->base.dev;
9863 struct drm_i915_private *dev_priv = to_i915(dev);
9864 enum intel_display_power_domain power_domain;
9865 enum transcoder cpu_transcoder;
9870 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9872 cpu_transcoder = TRANSCODER_DSI_A;
9874 cpu_transcoder = TRANSCODER_DSI_C;
9876 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9877 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
9879 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
9883 wakerefs[power_domain] = wf;
9884 *power_domain_mask |= BIT_ULL(power_domain);
9887 * The PLL needs to be enabled with a valid divider
9888 * configuration, otherwise accessing DSI registers will hang
9889 * the machine. See BSpec North Display Engine
9890 * registers/MIPI[BXT]. We can break out here early, since we
9891 * need the same DSI PLL to be enabled for both DSI ports.
9893 if (!bxt_dsi_pll_is_enabled(dev_priv))
9896 /* XXX: this works for video mode only */
9897 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9898 if (!(tmp & DPI_ENABLE))
9901 tmp = I915_READ(MIPI_CTRL(port));
9902 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9905 pipe_config->cpu_transcoder = cpu_transcoder;
9909 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9912 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9913 struct intel_crtc_state *pipe_config)
9915 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9916 struct intel_shared_dpll *pll;
9920 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9922 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9924 if (INTEL_GEN(dev_priv) >= 11)
9925 icelake_get_ddi_pll(dev_priv, port, pipe_config);
9926 else if (IS_CANNONLAKE(dev_priv))
9927 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9928 else if (IS_GEN9_BC(dev_priv))
9929 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9930 else if (IS_GEN9_LP(dev_priv))
9931 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9933 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9935 pll = pipe_config->shared_dpll;
9937 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9938 &pipe_config->dpll_hw_state));
9942 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9943 * DDI E. So just check whether this pipe is wired to DDI E and whether
9944 * the PCH transcoder is on.
9946 if (INTEL_GEN(dev_priv) < 9 &&
9947 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9948 pipe_config->has_pch_encoder = true;
9950 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9951 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9952 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9954 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9958 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9959 struct intel_crtc_state *pipe_config)
9961 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9962 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
9963 enum intel_display_power_domain power_domain;
9964 u64 power_domain_mask;
9967 intel_crtc_init_scalers(crtc, pipe_config);
9969 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9970 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
9974 wakerefs[power_domain] = wf;
9975 power_domain_mask = BIT_ULL(power_domain);
9977 pipe_config->shared_dpll = NULL;
9979 active = hsw_get_transcoder_state(crtc, pipe_config,
9980 &power_domain_mask, wakerefs);
9982 if (IS_GEN9_LP(dev_priv) &&
9983 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9984 &power_domain_mask, wakerefs)) {
9992 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
9993 INTEL_GEN(dev_priv) >= 11) {
9994 haswell_get_ddi_port_state(crtc, pipe_config);
9995 intel_get_pipe_timings(crtc, pipe_config);
9998 intel_get_pipe_src_size(crtc, pipe_config);
9999 intel_get_crtc_ycbcr_config(crtc, pipe_config);
10001 pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
10003 pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10005 if (INTEL_GEN(dev_priv) >= 9) {
10006 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
10008 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
10009 pipe_config->gamma_enable = true;
10011 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
10012 pipe_config->csc_enable = true;
10014 i9xx_get_pipe_color_config(pipe_config);
10017 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10018 WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10020 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10022 wakerefs[power_domain] = wf;
10023 power_domain_mask |= BIT_ULL(power_domain);
10025 if (INTEL_GEN(dev_priv) >= 9)
10026 skylake_get_pfit_config(crtc, pipe_config);
10028 ironlake_get_pfit_config(crtc, pipe_config);
10031 if (hsw_crtc_supports_ips(crtc)) {
10032 if (IS_HASWELL(dev_priv))
10033 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10036 * We cannot readout IPS state on broadwell, set to
10037 * true so we can set it to a defined state on first
10040 pipe_config->ips_enabled = true;
10044 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10045 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10046 pipe_config->pixel_multiplier =
10047 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10049 pipe_config->pixel_multiplier = 1;
10053 for_each_power_domain(power_domain, power_domain_mask)
10054 intel_display_power_put(dev_priv,
10055 power_domain, wakerefs[power_domain]);
10060 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10062 struct drm_i915_private *dev_priv =
10063 to_i915(plane_state->base.plane->dev);
10064 const struct drm_framebuffer *fb = plane_state->base.fb;
10065 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10068 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10069 base = obj->phys_handle->busaddr;
10071 base = intel_plane_ggtt_offset(plane_state);
10073 base += plane_state->color_plane[0].offset;
10075 /* ILK+ do this automagically */
10076 if (HAS_GMCH(dev_priv) &&
10077 plane_state->base.rotation & DRM_MODE_ROTATE_180)
10078 base += (plane_state->base.crtc_h *
10079 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
10084 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10086 int x = plane_state->base.crtc_x;
10087 int y = plane_state->base.crtc_y;
10091 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10094 pos |= x << CURSOR_X_SHIFT;
10097 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10100 pos |= y << CURSOR_Y_SHIFT;
10105 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10107 const struct drm_mode_config *config =
10108 &plane_state->base.plane->dev->mode_config;
10109 int width = plane_state->base.crtc_w;
10110 int height = plane_state->base.crtc_h;
10112 return width > 0 && width <= config->cursor_width &&
10113 height > 0 && height <= config->cursor_height;
10116 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10118 const struct drm_framebuffer *fb = plane_state->base.fb;
10119 unsigned int rotation = plane_state->base.rotation;
10124 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
10125 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
10127 ret = intel_plane_check_stride(plane_state);
10131 src_x = plane_state->base.src_x >> 16;
10132 src_y = plane_state->base.src_y >> 16;
10134 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10135 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10138 if (src_x != 0 || src_y != 0) {
10139 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10143 plane_state->color_plane[0].offset = offset;
10148 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10149 struct intel_plane_state *plane_state)
10151 const struct drm_framebuffer *fb = plane_state->base.fb;
10154 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10155 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10159 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
10161 DRM_PLANE_HELPER_NO_SCALING,
10162 DRM_PLANE_HELPER_NO_SCALING,
10167 if (!plane_state->base.visible)
10170 ret = intel_plane_check_src_coordinates(plane_state);
10174 ret = intel_cursor_check_surface(plane_state);
10181 static unsigned int
10182 i845_cursor_max_stride(struct intel_plane *plane,
10183 u32 pixel_format, u64 modifier,
10184 unsigned int rotation)
10189 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10193 if (crtc_state->gamma_enable)
10194 cntl |= CURSOR_GAMMA_ENABLE;
10199 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10200 const struct intel_plane_state *plane_state)
10202 return CURSOR_ENABLE |
10203 CURSOR_FORMAT_ARGB |
10204 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10207 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10209 int width = plane_state->base.crtc_w;
10212 * 845g/865g are only limited by the width of their cursors,
10213 * the height is arbitrary up to the precision of the register.
10215 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10218 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10219 struct intel_plane_state *plane_state)
10221 const struct drm_framebuffer *fb = plane_state->base.fb;
10224 ret = intel_check_cursor(crtc_state, plane_state);
10228 /* if we want to turn off the cursor ignore width and height */
10232 /* Check for which cursor types we support */
10233 if (!i845_cursor_size_ok(plane_state)) {
10234 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10235 plane_state->base.crtc_w,
10236 plane_state->base.crtc_h);
10240 WARN_ON(plane_state->base.visible &&
10241 plane_state->color_plane[0].stride != fb->pitches[0]);
10243 switch (fb->pitches[0]) {
10250 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10255 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
10260 static void i845_update_cursor(struct intel_plane *plane,
10261 const struct intel_crtc_state *crtc_state,
10262 const struct intel_plane_state *plane_state)
10264 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10265 u32 cntl = 0, base = 0, pos = 0, size = 0;
10266 unsigned long irqflags;
10268 if (plane_state && plane_state->base.visible) {
10269 unsigned int width = plane_state->base.crtc_w;
10270 unsigned int height = plane_state->base.crtc_h;
10272 cntl = plane_state->ctl |
10273 i845_cursor_ctl_crtc(crtc_state);
10275 size = (height << 12) | width;
10277 base = intel_cursor_base(plane_state);
10278 pos = intel_cursor_position(plane_state);
10281 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10283 /* On these chipsets we can only modify the base/size/stride
10284 * whilst the cursor is disabled.
10286 if (plane->cursor.base != base ||
10287 plane->cursor.size != size ||
10288 plane->cursor.cntl != cntl) {
10289 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
10290 I915_WRITE_FW(CURBASE(PIPE_A), base);
10291 I915_WRITE_FW(CURSIZE, size);
10292 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10293 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
10295 plane->cursor.base = base;
10296 plane->cursor.size = size;
10297 plane->cursor.cntl = cntl;
10299 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10302 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10305 static void i845_disable_cursor(struct intel_plane *plane,
10306 const struct intel_crtc_state *crtc_state)
10308 i845_update_cursor(plane, crtc_state, NULL);
10311 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
10314 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10315 enum intel_display_power_domain power_domain;
10316 intel_wakeref_t wakeref;
10319 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
10320 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10324 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
10328 intel_display_power_put(dev_priv, power_domain, wakeref);
10333 static unsigned int
10334 i9xx_cursor_max_stride(struct intel_plane *plane,
10335 u32 pixel_format, u64 modifier,
10336 unsigned int rotation)
10338 return plane->base.dev->mode_config.cursor_width * 4;
10341 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10343 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
10344 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10347 if (INTEL_GEN(dev_priv) >= 11)
10350 if (crtc_state->gamma_enable)
10351 cntl = MCURSOR_GAMMA_ENABLE;
10353 if (crtc_state->csc_enable)
10354 cntl |= MCURSOR_PIPE_CSC_ENABLE;
10356 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10357 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
10362 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
10363 const struct intel_plane_state *plane_state)
10365 struct drm_i915_private *dev_priv =
10366 to_i915(plane_state->base.plane->dev);
10369 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
10370 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
10372 switch (plane_state->base.crtc_w) {
10374 cntl |= MCURSOR_MODE_64_ARGB_AX;
10377 cntl |= MCURSOR_MODE_128_ARGB_AX;
10380 cntl |= MCURSOR_MODE_256_ARGB_AX;
10383 MISSING_CASE(plane_state->base.crtc_w);
10387 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
10388 cntl |= MCURSOR_ROTATE_180;
10393 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
10395 struct drm_i915_private *dev_priv =
10396 to_i915(plane_state->base.plane->dev);
10397 int width = plane_state->base.crtc_w;
10398 int height = plane_state->base.crtc_h;
10400 if (!intel_cursor_size_ok(plane_state))
10403 /* Cursor width is limited to a few power-of-two sizes */
10414 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
10415 * height from 8 lines up to the cursor width, when the
10416 * cursor is not rotated. Everything else requires square
10419 if (HAS_CUR_FBC(dev_priv) &&
10420 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
10421 if (height < 8 || height > width)
10424 if (height != width)
10431 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
10432 struct intel_plane_state *plane_state)
10434 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
10435 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10436 const struct drm_framebuffer *fb = plane_state->base.fb;
10437 enum pipe pipe = plane->pipe;
10440 ret = intel_check_cursor(crtc_state, plane_state);
10444 /* if we want to turn off the cursor ignore width and height */
10448 /* Check for which cursor types we support */
10449 if (!i9xx_cursor_size_ok(plane_state)) {
10450 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10451 plane_state->base.crtc_w,
10452 plane_state->base.crtc_h);
10456 WARN_ON(plane_state->base.visible &&
10457 plane_state->color_plane[0].stride != fb->pitches[0]);
10459 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
10460 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
10461 fb->pitches[0], plane_state->base.crtc_w);
10466 * There's something wrong with the cursor on CHV pipe C.
10467 * If it straddles the left edge of the screen then
10468 * moving it away from the edge or disabling it often
10469 * results in a pipe underrun, and often that can lead to
10470 * dead pipe (constant underrun reported, and it scans
10471 * out just a solid color). To recover from that, the
10472 * display power well must be turned off and on again.
10473 * Refuse the put the cursor into that compromised position.
10475 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
10476 plane_state->base.visible && plane_state->base.crtc_x < 0) {
10477 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
10481 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
10486 static void i9xx_update_cursor(struct intel_plane *plane,
10487 const struct intel_crtc_state *crtc_state,
10488 const struct intel_plane_state *plane_state)
10490 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10491 enum pipe pipe = plane->pipe;
10492 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
10493 unsigned long irqflags;
10495 if (plane_state && plane_state->base.visible) {
10496 cntl = plane_state->ctl |
10497 i9xx_cursor_ctl_crtc(crtc_state);
10499 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
10500 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
10502 base = intel_cursor_base(plane_state);
10503 pos = intel_cursor_position(plane_state);
10506 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10509 * On some platforms writing CURCNTR first will also
10510 * cause CURPOS to be armed by the CURBASE write.
10511 * Without the CURCNTR write the CURPOS write would
10512 * arm itself. Thus we always update CURCNTR before
10515 * On other platforms CURPOS always requires the
10516 * CURBASE write to arm the update. Additonally
10517 * a write to any of the cursor register will cancel
10518 * an already armed cursor update. Thus leaving out
10519 * the CURBASE write after CURPOS could lead to a
10520 * cursor that doesn't appear to move, or even change
10521 * shape. Thus we always write CURBASE.
10523 * The other registers are armed by by the CURBASE write
10524 * except when the plane is getting enabled at which time
10525 * the CURCNTR write arms the update.
10528 if (INTEL_GEN(dev_priv) >= 9)
10529 skl_write_cursor_wm(plane, crtc_state);
10531 if (plane->cursor.base != base ||
10532 plane->cursor.size != fbc_ctl ||
10533 plane->cursor.cntl != cntl) {
10534 if (HAS_CUR_FBC(dev_priv))
10535 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
10536 I915_WRITE_FW(CURCNTR(pipe), cntl);
10537 I915_WRITE_FW(CURPOS(pipe), pos);
10538 I915_WRITE_FW(CURBASE(pipe), base);
10540 plane->cursor.base = base;
10541 plane->cursor.size = fbc_ctl;
10542 plane->cursor.cntl = cntl;
10544 I915_WRITE_FW(CURPOS(pipe), pos);
10545 I915_WRITE_FW(CURBASE(pipe), base);
10548 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10551 static void i9xx_disable_cursor(struct intel_plane *plane,
10552 const struct intel_crtc_state *crtc_state)
10554 i9xx_update_cursor(plane, crtc_state, NULL);
10557 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
10560 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10561 enum intel_display_power_domain power_domain;
10562 intel_wakeref_t wakeref;
10567 * Not 100% correct for planes that can move between pipes,
10568 * but that's only the case for gen2-3 which don't have any
10569 * display power wells.
10571 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
10572 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10576 val = I915_READ(CURCNTR(plane->pipe));
10578 ret = val & MCURSOR_MODE;
10580 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10581 *pipe = plane->pipe;
10583 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
10584 MCURSOR_PIPE_SELECT_SHIFT;
10586 intel_display_power_put(dev_priv, power_domain, wakeref);
10591 /* VESA 640x480x72Hz mode to set on the pipe */
10592 static const struct drm_display_mode load_detect_mode = {
10593 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10594 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10597 struct drm_framebuffer *
10598 intel_framebuffer_create(struct drm_i915_gem_object *obj,
10599 struct drm_mode_fb_cmd2 *mode_cmd)
10601 struct intel_framebuffer *intel_fb;
10604 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10606 return ERR_PTR(-ENOMEM);
10608 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
10612 return &intel_fb->base;
10616 return ERR_PTR(ret);
10619 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
10620 struct drm_crtc *crtc)
10622 struct drm_plane *plane;
10623 struct drm_plane_state *plane_state;
10626 ret = drm_atomic_add_affected_planes(state, crtc);
10630 for_each_new_plane_in_state(state, plane, plane_state, i) {
10631 if (plane_state->crtc != crtc)
10634 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
10638 drm_atomic_set_fb_for_plane(plane_state, NULL);
10644 int intel_get_load_detect_pipe(struct drm_connector *connector,
10645 const struct drm_display_mode *mode,
10646 struct intel_load_detect_pipe *old,
10647 struct drm_modeset_acquire_ctx *ctx)
10649 struct intel_crtc *intel_crtc;
10650 struct intel_encoder *intel_encoder =
10651 intel_attached_encoder(connector);
10652 struct drm_crtc *possible_crtc;
10653 struct drm_encoder *encoder = &intel_encoder->base;
10654 struct drm_crtc *crtc = NULL;
10655 struct drm_device *dev = encoder->dev;
10656 struct drm_i915_private *dev_priv = to_i915(dev);
10657 struct drm_mode_config *config = &dev->mode_config;
10658 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10659 struct drm_connector_state *connector_state;
10660 struct intel_crtc_state *crtc_state;
10663 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10664 connector->base.id, connector->name,
10665 encoder->base.id, encoder->name);
10667 old->restore_state = NULL;
10669 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
10672 * Algorithm gets a little messy:
10674 * - if the connector already has an assigned crtc, use it (but make
10675 * sure it's on first)
10677 * - try to find the first unused crtc that can drive this connector,
10678 * and use that if we find one
10681 /* See if we already have a CRTC for this connector */
10682 if (connector->state->crtc) {
10683 crtc = connector->state->crtc;
10685 ret = drm_modeset_lock(&crtc->mutex, ctx);
10689 /* Make sure the crtc and connector are running */
10693 /* Find an unused one (if possible) */
10694 for_each_crtc(dev, possible_crtc) {
10696 if (!(encoder->possible_crtcs & (1 << i)))
10699 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10703 if (possible_crtc->state->enable) {
10704 drm_modeset_unlock(&possible_crtc->mutex);
10708 crtc = possible_crtc;
10713 * If we didn't find an unused CRTC, don't use any.
10716 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10722 intel_crtc = to_intel_crtc(crtc);
10724 state = drm_atomic_state_alloc(dev);
10725 restore_state = drm_atomic_state_alloc(dev);
10726 if (!state || !restore_state) {
10731 state->acquire_ctx = ctx;
10732 restore_state->acquire_ctx = ctx;
10734 connector_state = drm_atomic_get_connector_state(state, connector);
10735 if (IS_ERR(connector_state)) {
10736 ret = PTR_ERR(connector_state);
10740 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10744 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10745 if (IS_ERR(crtc_state)) {
10746 ret = PTR_ERR(crtc_state);
10750 crtc_state->base.active = crtc_state->base.enable = true;
10753 mode = &load_detect_mode;
10755 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10759 ret = intel_modeset_disable_planes(state, crtc);
10763 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10765 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10767 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10769 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10773 ret = drm_atomic_commit(state);
10775 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10779 old->restore_state = restore_state;
10780 drm_atomic_state_put(state);
10782 /* let the connector get through one full cycle before testing */
10783 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10788 drm_atomic_state_put(state);
10791 if (restore_state) {
10792 drm_atomic_state_put(restore_state);
10793 restore_state = NULL;
10796 if (ret == -EDEADLK)
10802 void intel_release_load_detect_pipe(struct drm_connector *connector,
10803 struct intel_load_detect_pipe *old,
10804 struct drm_modeset_acquire_ctx *ctx)
10806 struct intel_encoder *intel_encoder =
10807 intel_attached_encoder(connector);
10808 struct drm_encoder *encoder = &intel_encoder->base;
10809 struct drm_atomic_state *state = old->restore_state;
10812 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10813 connector->base.id, connector->name,
10814 encoder->base.id, encoder->name);
10819 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10821 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10822 drm_atomic_state_put(state);
10825 static int i9xx_pll_refclk(struct drm_device *dev,
10826 const struct intel_crtc_state *pipe_config)
10828 struct drm_i915_private *dev_priv = to_i915(dev);
10829 u32 dpll = pipe_config->dpll_hw_state.dpll;
10831 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10832 return dev_priv->vbt.lvds_ssc_freq;
10833 else if (HAS_PCH_SPLIT(dev_priv))
10835 else if (!IS_GEN(dev_priv, 2))
10841 /* Returns the clock of the currently programmed mode of the given pipe. */
10842 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10843 struct intel_crtc_state *pipe_config)
10845 struct drm_device *dev = crtc->base.dev;
10846 struct drm_i915_private *dev_priv = to_i915(dev);
10847 int pipe = pipe_config->cpu_transcoder;
10848 u32 dpll = pipe_config->dpll_hw_state.dpll;
10852 int refclk = i9xx_pll_refclk(dev, pipe_config);
10854 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10855 fp = pipe_config->dpll_hw_state.fp0;
10857 fp = pipe_config->dpll_hw_state.fp1;
10859 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10860 if (IS_PINEVIEW(dev_priv)) {
10861 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10862 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10864 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10865 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10868 if (!IS_GEN(dev_priv, 2)) {
10869 if (IS_PINEVIEW(dev_priv))
10870 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10871 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10873 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10874 DPLL_FPA01_P1_POST_DIV_SHIFT);
10876 switch (dpll & DPLL_MODE_MASK) {
10877 case DPLLB_MODE_DAC_SERIAL:
10878 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10881 case DPLLB_MODE_LVDS:
10882 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10886 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10887 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10891 if (IS_PINEVIEW(dev_priv))
10892 port_clock = pnv_calc_dpll_params(refclk, &clock);
10894 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10896 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10897 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10900 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10901 DPLL_FPA01_P1_POST_DIV_SHIFT);
10903 if (lvds & LVDS_CLKB_POWER_UP)
10908 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10911 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10912 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10914 if (dpll & PLL_P2_DIVIDE_BY_4)
10920 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10924 * This value includes pixel_multiplier. We will use
10925 * port_clock to compute adjusted_mode.crtc_clock in the
10926 * encoder's get_config() function.
10928 pipe_config->port_clock = port_clock;
10931 int intel_dotclock_calculate(int link_freq,
10932 const struct intel_link_m_n *m_n)
10935 * The calculation for the data clock is:
10936 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10937 * But we want to avoid losing precison if possible, so:
10938 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10940 * and the link clock is simpler:
10941 * link_clock = (m * link_clock) / n
10947 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10950 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10951 struct intel_crtc_state *pipe_config)
10953 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10955 /* read out port_clock from the DPLL */
10956 i9xx_crtc_clock_get(crtc, pipe_config);
10959 * In case there is an active pipe without active ports,
10960 * we may need some idea for the dotclock anyway.
10961 * Calculate one based on the FDI configuration.
10963 pipe_config->base.adjusted_mode.crtc_clock =
10964 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10965 &pipe_config->fdi_m_n);
10968 /* Returns the currently programmed mode of the given encoder. */
10969 struct drm_display_mode *
10970 intel_encoder_current_mode(struct intel_encoder *encoder)
10972 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10973 struct intel_crtc_state *crtc_state;
10974 struct drm_display_mode *mode;
10975 struct intel_crtc *crtc;
10978 if (!encoder->get_hw_state(encoder, &pipe))
10981 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10983 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10987 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10993 crtc_state->base.crtc = &crtc->base;
10995 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
11001 encoder->get_config(encoder, crtc_state);
11003 intel_mode_from_pipe_config(mode, crtc_state);
11010 static void intel_crtc_destroy(struct drm_crtc *crtc)
11012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11014 drm_crtc_cleanup(crtc);
11019 * intel_wm_need_update - Check whether watermarks need updating
11020 * @cur: current plane state
11021 * @new: new plane state
11023 * Check current plane state versus the new one to determine whether
11024 * watermarks need to be recalculated.
11026 * Returns true or false.
11028 static bool intel_wm_need_update(struct intel_plane_state *cur,
11029 struct intel_plane_state *new)
11031 /* Update watermarks on tiling or size changes. */
11032 if (new->base.visible != cur->base.visible)
11035 if (!cur->base.fb || !new->base.fb)
11038 if (cur->base.fb->modifier != new->base.fb->modifier ||
11039 cur->base.rotation != new->base.rotation ||
11040 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
11041 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
11042 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
11043 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
11049 static bool needs_scaling(const struct intel_plane_state *state)
11051 int src_w = drm_rect_width(&state->base.src) >> 16;
11052 int src_h = drm_rect_height(&state->base.src) >> 16;
11053 int dst_w = drm_rect_width(&state->base.dst);
11054 int dst_h = drm_rect_height(&state->base.dst);
11056 return (src_w != dst_w || src_h != dst_h);
11059 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11060 struct drm_crtc_state *crtc_state,
11061 const struct intel_plane_state *old_plane_state,
11062 struct drm_plane_state *plane_state)
11064 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11065 struct drm_crtc *crtc = crtc_state->crtc;
11066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11067 struct intel_plane *plane = to_intel_plane(plane_state->plane);
11068 struct drm_device *dev = crtc->dev;
11069 struct drm_i915_private *dev_priv = to_i915(dev);
11070 bool mode_changed = needs_modeset(crtc_state);
11071 bool was_crtc_enabled = old_crtc_state->base.active;
11072 bool is_crtc_enabled = crtc_state->active;
11073 bool turn_off, turn_on, visible, was_visible;
11074 struct drm_framebuffer *fb = plane_state->fb;
11077 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11078 ret = skl_update_scaler_plane(
11079 to_intel_crtc_state(crtc_state),
11080 to_intel_plane_state(plane_state));
11085 was_visible = old_plane_state->base.visible;
11086 visible = plane_state->visible;
11088 if (!was_crtc_enabled && WARN_ON(was_visible))
11089 was_visible = false;
11092 * Visibility is calculated as if the crtc was on, but
11093 * after scaler setup everything depends on it being off
11094 * when the crtc isn't active.
11096 * FIXME this is wrong for watermarks. Watermarks should also
11097 * be computed as if the pipe would be active. Perhaps move
11098 * per-plane wm computation to the .check_plane() hook, and
11099 * only combine the results from all planes in the current place?
11101 if (!is_crtc_enabled) {
11102 plane_state->visible = visible = false;
11103 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
11106 if (!was_visible && !visible)
11109 if (fb != old_plane_state->base.fb)
11110 pipe_config->fb_changed = true;
11112 turn_off = was_visible && (!visible || mode_changed);
11113 turn_on = visible && (!was_visible || mode_changed);
11115 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11116 intel_crtc->base.base.id, intel_crtc->base.name,
11117 plane->base.base.id, plane->base.name,
11118 fb ? fb->base.id : -1);
11120 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11121 plane->base.base.id, plane->base.name,
11122 was_visible, visible,
11123 turn_off, turn_on, mode_changed);
11126 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11127 pipe_config->update_wm_pre = true;
11129 /* must disable cxsr around plane enable/disable */
11130 if (plane->id != PLANE_CURSOR)
11131 pipe_config->disable_cxsr = true;
11132 } else if (turn_off) {
11133 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11134 pipe_config->update_wm_post = true;
11136 /* must disable cxsr around plane enable/disable */
11137 if (plane->id != PLANE_CURSOR)
11138 pipe_config->disable_cxsr = true;
11139 } else if (intel_wm_need_update(to_intel_plane_state(plane->base.state),
11140 to_intel_plane_state(plane_state))) {
11141 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11142 /* FIXME bollocks */
11143 pipe_config->update_wm_pre = true;
11144 pipe_config->update_wm_post = true;
11148 if (visible || was_visible)
11149 pipe_config->fb_bits |= plane->frontbuffer_bit;
11152 * ILK/SNB DVSACNTR/Sprite Enable
11153 * IVB SPR_CTL/Sprite Enable
11154 * "When in Self Refresh Big FIFO mode, a write to enable the
11155 * plane will be internally buffered and delayed while Big FIFO
11156 * mode is exiting."
11158 * Which means that enabling the sprite can take an extra frame
11159 * when we start in big FIFO mode (LP1+). Thus we need to drop
11160 * down to LP0 and wait for vblank in order to make sure the
11161 * sprite gets enabled on the next vblank after the register write.
11162 * Doing otherwise would risk enabling the sprite one frame after
11163 * we've already signalled flip completion. We can resume LP1+
11164 * once the sprite has been enabled.
11167 * WaCxSRDisabledForSpriteScaling:ivb
11168 * IVB SPR_SCALE/Scaling Enable
11169 * "Low Power watermarks must be disabled for at least one
11170 * frame before enabling sprite scaling, and kept disabled
11171 * until sprite scaling is disabled."
11173 * ILK/SNB DVSASCALE/Scaling Enable
11174 * "When in Self Refresh Big FIFO mode, scaling enable will be
11175 * masked off while Big FIFO mode is exiting."
11177 * Despite the w/a only being listed for IVB we assume that
11178 * the ILK/SNB note has similar ramifications, hence we apply
11179 * the w/a on all three platforms.
11181 * With experimental results seems this is needed also for primary
11182 * plane, not only sprite plane.
11184 if (plane->id != PLANE_CURSOR &&
11185 (IS_GEN_RANGE(dev_priv, 5, 6) ||
11186 IS_IVYBRIDGE(dev_priv)) &&
11187 (turn_on || (!needs_scaling(old_plane_state) &&
11188 needs_scaling(to_intel_plane_state(plane_state)))))
11189 pipe_config->disable_lp_wm = true;
11194 static bool encoders_cloneable(const struct intel_encoder *a,
11195 const struct intel_encoder *b)
11197 /* masks could be asymmetric, so check both ways */
11198 return a == b || (a->cloneable & (1 << b->type) &&
11199 b->cloneable & (1 << a->type));
11202 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11203 struct intel_crtc *crtc,
11204 struct intel_encoder *encoder)
11206 struct intel_encoder *source_encoder;
11207 struct drm_connector *connector;
11208 struct drm_connector_state *connector_state;
11211 for_each_new_connector_in_state(state, connector, connector_state, i) {
11212 if (connector_state->crtc != &crtc->base)
11216 to_intel_encoder(connector_state->best_encoder);
11217 if (!encoders_cloneable(encoder, source_encoder))
11224 static int icl_add_linked_planes(struct intel_atomic_state *state)
11226 struct intel_plane *plane, *linked;
11227 struct intel_plane_state *plane_state, *linked_plane_state;
11230 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11231 linked = plane_state->linked_plane;
11236 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11237 if (IS_ERR(linked_plane_state))
11238 return PTR_ERR(linked_plane_state);
11240 WARN_ON(linked_plane_state->linked_plane != plane);
11241 WARN_ON(linked_plane_state->slave == plane_state->slave);
11247 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
11249 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
11250 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11251 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
11252 struct intel_plane *plane, *linked;
11253 struct intel_plane_state *plane_state;
11256 if (INTEL_GEN(dev_priv) < 11)
11260 * Destroy all old plane links and make the slave plane invisible
11261 * in the crtc_state->active_planes mask.
11263 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11264 if (plane->pipe != crtc->pipe || !plane_state->linked_plane)
11267 plane_state->linked_plane = NULL;
11268 if (plane_state->slave && !plane_state->base.visible) {
11269 crtc_state->active_planes &= ~BIT(plane->id);
11270 crtc_state->update_planes |= BIT(plane->id);
11273 plane_state->slave = false;
11276 if (!crtc_state->nv12_planes)
11279 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11280 struct intel_plane_state *linked_state = NULL;
11282 if (plane->pipe != crtc->pipe ||
11283 !(crtc_state->nv12_planes & BIT(plane->id)))
11286 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
11287 if (!icl_is_nv12_y_plane(linked->id))
11290 if (crtc_state->active_planes & BIT(linked->id))
11293 linked_state = intel_atomic_get_plane_state(state, linked);
11294 if (IS_ERR(linked_state))
11295 return PTR_ERR(linked_state);
11300 if (!linked_state) {
11301 DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11302 hweight8(crtc_state->nv12_planes));
11307 plane_state->linked_plane = linked;
11309 linked_state->slave = true;
11310 linked_state->linked_plane = plane;
11311 crtc_state->active_planes |= BIT(linked->id);
11312 crtc_state->update_planes |= BIT(linked->id);
11313 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
11319 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11320 struct drm_crtc_state *crtc_state)
11322 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11324 struct intel_crtc_state *pipe_config =
11325 to_intel_crtc_state(crtc_state);
11327 bool mode_changed = needs_modeset(crtc_state);
11329 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
11330 mode_changed && !crtc_state->active)
11331 pipe_config->update_wm_post = true;
11333 if (mode_changed && crtc_state->enable &&
11334 dev_priv->display.crtc_compute_clock &&
11335 !WARN_ON(pipe_config->shared_dpll)) {
11336 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11342 if (mode_changed || pipe_config->update_pipe ||
11343 crtc_state->color_mgmt_changed) {
11344 ret = intel_color_check(pipe_config);
11350 if (dev_priv->display.compute_pipe_wm) {
11351 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11353 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11358 if (dev_priv->display.compute_intermediate_wm) {
11359 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11363 * Calculate 'intermediate' watermarks that satisfy both the
11364 * old state and the new state. We can program these
11367 ret = dev_priv->display.compute_intermediate_wm(pipe_config);
11369 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11374 if (INTEL_GEN(dev_priv) >= 9) {
11375 if (mode_changed || pipe_config->update_pipe)
11376 ret = skl_update_scaler_crtc(pipe_config);
11379 ret = icl_check_nv12_planes(pipe_config);
11381 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
11384 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11388 if (HAS_IPS(dev_priv))
11389 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
11394 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11395 .atomic_check = intel_crtc_atomic_check,
11398 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11400 struct intel_connector *connector;
11401 struct drm_connector_list_iter conn_iter;
11403 drm_connector_list_iter_begin(dev, &conn_iter);
11404 for_each_intel_connector_iter(connector, &conn_iter) {
11405 if (connector->base.state->crtc)
11406 drm_connector_put(&connector->base);
11408 if (connector->base.encoder) {
11409 connector->base.state->best_encoder =
11410 connector->base.encoder;
11411 connector->base.state->crtc =
11412 connector->base.encoder->crtc;
11414 drm_connector_get(&connector->base);
11416 connector->base.state->best_encoder = NULL;
11417 connector->base.state->crtc = NULL;
11420 drm_connector_list_iter_end(&conn_iter);
11424 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
11425 struct intel_crtc_state *pipe_config)
11427 struct drm_connector *connector = conn_state->connector;
11428 const struct drm_display_info *info = &connector->display_info;
11431 switch (conn_state->max_bpc) {
11448 if (bpp < pipe_config->pipe_bpp) {
11449 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
11450 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
11451 connector->base.id, connector->name,
11452 bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
11453 pipe_config->pipe_bpp);
11455 pipe_config->pipe_bpp = bpp;
11462 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11463 struct intel_crtc_state *pipe_config)
11465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11466 struct drm_atomic_state *state = pipe_config->base.state;
11467 struct drm_connector *connector;
11468 struct drm_connector_state *connector_state;
11471 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11472 IS_CHERRYVIEW(dev_priv)))
11474 else if (INTEL_GEN(dev_priv) >= 5)
11479 pipe_config->pipe_bpp = bpp;
11481 /* Clamp display bpp to connector max bpp */
11482 for_each_new_connector_in_state(state, connector, connector_state, i) {
11485 if (connector_state->crtc != &crtc->base)
11488 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
11496 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11498 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11499 "type: 0x%x flags: 0x%x\n",
11501 mode->crtc_hdisplay, mode->crtc_hsync_start,
11502 mode->crtc_hsync_end, mode->crtc_htotal,
11503 mode->crtc_vdisplay, mode->crtc_vsync_start,
11504 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11508 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11509 unsigned int lane_count, struct intel_link_m_n *m_n)
11511 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11513 m_n->gmch_m, m_n->gmch_n,
11514 m_n->link_m, m_n->link_n, m_n->tu);
11518 intel_dump_infoframe(struct drm_i915_private *dev_priv,
11519 const union hdmi_infoframe *frame)
11521 if ((drm_debug & DRM_UT_KMS) == 0)
11524 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
11527 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
11529 static const char * const output_type_str[] = {
11530 OUTPUT_TYPE(UNUSED),
11531 OUTPUT_TYPE(ANALOG),
11535 OUTPUT_TYPE(TVOUT),
11541 OUTPUT_TYPE(DP_MST),
11546 static void snprintf_output_types(char *buf, size_t len,
11547 unsigned int output_types)
11554 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
11557 if ((output_types & BIT(i)) == 0)
11560 r = snprintf(str, len, "%s%s",
11561 str != buf ? "," : "", output_type_str[i]);
11567 output_types &= ~BIT(i);
11570 WARN_ON_ONCE(output_types != 0);
11573 static const char * const output_format_str[] = {
11574 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
11575 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
11576 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
11577 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
11580 static const char *output_formats(enum intel_output_format format)
11582 if (format >= ARRAY_SIZE(output_format_str))
11583 format = INTEL_OUTPUT_FORMAT_INVALID;
11584 return output_format_str[format];
11587 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11588 struct intel_crtc_state *pipe_config,
11589 const char *context)
11591 struct drm_device *dev = crtc->base.dev;
11592 struct drm_i915_private *dev_priv = to_i915(dev);
11593 struct drm_plane *plane;
11594 struct intel_plane *intel_plane;
11595 struct intel_plane_state *state;
11596 struct drm_framebuffer *fb;
11599 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11600 crtc->base.base.id, crtc->base.name, context);
11602 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
11603 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
11604 buf, pipe_config->output_types);
11606 DRM_DEBUG_KMS("output format: %s\n",
11607 output_formats(pipe_config->output_format));
11609 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11610 transcoder_name(pipe_config->cpu_transcoder),
11611 pipe_config->pipe_bpp, pipe_config->dither);
11613 if (pipe_config->has_pch_encoder)
11614 intel_dump_m_n_config(pipe_config, "fdi",
11615 pipe_config->fdi_lanes,
11616 &pipe_config->fdi_m_n);
11618 if (intel_crtc_has_dp_encoder(pipe_config)) {
11619 intel_dump_m_n_config(pipe_config, "dp m_n",
11620 pipe_config->lane_count, &pipe_config->dp_m_n);
11621 if (pipe_config->has_drrs)
11622 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11623 pipe_config->lane_count,
11624 &pipe_config->dp_m2_n2);
11627 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11628 pipe_config->has_audio, pipe_config->has_infoframe);
11630 DRM_DEBUG_KMS("infoframes enabled: 0x%x\n",
11631 pipe_config->infoframes.enable);
11633 if (pipe_config->infoframes.enable &
11634 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
11635 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
11636 if (pipe_config->infoframes.enable &
11637 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
11638 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
11639 if (pipe_config->infoframes.enable &
11640 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
11641 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
11642 if (pipe_config->infoframes.enable &
11643 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
11644 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
11646 DRM_DEBUG_KMS("requested mode:\n");
11647 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11648 DRM_DEBUG_KMS("adjusted mode:\n");
11649 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11650 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11651 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11652 pipe_config->port_clock,
11653 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11654 pipe_config->pixel_rate);
11656 if (INTEL_GEN(dev_priv) >= 9)
11657 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11659 pipe_config->scaler_state.scaler_users,
11660 pipe_config->scaler_state.scaler_id);
11662 if (HAS_GMCH(dev_priv))
11663 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11664 pipe_config->gmch_pfit.control,
11665 pipe_config->gmch_pfit.pgm_ratios,
11666 pipe_config->gmch_pfit.lvds_border_bits);
11668 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11669 pipe_config->pch_pfit.pos,
11670 pipe_config->pch_pfit.size,
11671 enableddisabled(pipe_config->pch_pfit.enabled));
11673 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11674 pipe_config->ips_enabled, pipe_config->double_wide);
11676 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11678 DRM_DEBUG_KMS("planes on this crtc\n");
11679 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11680 struct drm_format_name_buf format_name;
11681 intel_plane = to_intel_plane(plane);
11682 if (intel_plane->pipe != crtc->pipe)
11685 state = to_intel_plane_state(plane->state);
11686 fb = state->base.fb;
11688 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11689 plane->base.id, plane->name, state->scaler_id);
11693 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11694 plane->base.id, plane->name,
11695 fb->base.id, fb->width, fb->height,
11696 drm_get_format_name(fb->format->format, &format_name));
11697 if (INTEL_GEN(dev_priv) >= 9)
11698 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11700 state->base.src.x1 >> 16,
11701 state->base.src.y1 >> 16,
11702 drm_rect_width(&state->base.src) >> 16,
11703 drm_rect_height(&state->base.src) >> 16,
11704 state->base.dst.x1, state->base.dst.y1,
11705 drm_rect_width(&state->base.dst),
11706 drm_rect_height(&state->base.dst));
11710 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11712 struct drm_device *dev = state->dev;
11713 struct drm_connector *connector;
11714 struct drm_connector_list_iter conn_iter;
11715 unsigned int used_ports = 0;
11716 unsigned int used_mst_ports = 0;
11720 * Walk the connector list instead of the encoder
11721 * list to detect the problem on ddi platforms
11722 * where there's just one encoder per digital port.
11724 drm_connector_list_iter_begin(dev, &conn_iter);
11725 drm_for_each_connector_iter(connector, &conn_iter) {
11726 struct drm_connector_state *connector_state;
11727 struct intel_encoder *encoder;
11729 connector_state = drm_atomic_get_new_connector_state(state, connector);
11730 if (!connector_state)
11731 connector_state = connector->state;
11733 if (!connector_state->best_encoder)
11736 encoder = to_intel_encoder(connector_state->best_encoder);
11738 WARN_ON(!connector_state->crtc);
11740 switch (encoder->type) {
11741 unsigned int port_mask;
11742 case INTEL_OUTPUT_DDI:
11743 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11745 /* else: fall through */
11746 case INTEL_OUTPUT_DP:
11747 case INTEL_OUTPUT_HDMI:
11748 case INTEL_OUTPUT_EDP:
11749 port_mask = 1 << encoder->port;
11751 /* the same port mustn't appear more than once */
11752 if (used_ports & port_mask)
11755 used_ports |= port_mask;
11757 case INTEL_OUTPUT_DP_MST:
11759 1 << encoder->port;
11765 drm_connector_list_iter_end(&conn_iter);
11767 /* can't mix MST and SST/HDMI on the same port */
11768 if (used_ports & used_mst_ports)
11775 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11777 struct drm_i915_private *dev_priv =
11778 to_i915(crtc_state->base.crtc->dev);
11779 struct intel_crtc_state *saved_state;
11781 saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
11785 /* FIXME: before the switch to atomic started, a new pipe_config was
11786 * kzalloc'd. Code that depends on any field being zero should be
11787 * fixed, so that the crtc_state can be safely duplicated. For now,
11788 * only fields that are know to not cause problems are preserved. */
11790 saved_state->scaler_state = crtc_state->scaler_state;
11791 saved_state->shared_dpll = crtc_state->shared_dpll;
11792 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
11793 saved_state->pch_pfit.force_thru = crtc_state->pch_pfit.force_thru;
11794 saved_state->crc_enabled = crtc_state->crc_enabled;
11795 if (IS_G4X(dev_priv) ||
11796 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11797 saved_state->wm = crtc_state->wm;
11799 /* Keep base drm_crtc_state intact, only clear our extended struct */
11800 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11801 memcpy(&crtc_state->base + 1, &saved_state->base + 1,
11802 sizeof(*crtc_state) - sizeof(crtc_state->base));
11804 kfree(saved_state);
11809 intel_modeset_pipe_config(struct drm_crtc *crtc,
11810 struct intel_crtc_state *pipe_config)
11812 struct drm_atomic_state *state = pipe_config->base.state;
11813 struct intel_encoder *encoder;
11814 struct drm_connector *connector;
11815 struct drm_connector_state *connector_state;
11820 ret = clear_intel_crtc_state(pipe_config);
11824 pipe_config->cpu_transcoder =
11825 (enum transcoder) to_intel_crtc(crtc)->pipe;
11828 * Sanitize sync polarity flags based on requested ones. If neither
11829 * positive or negative polarity is requested, treat this as meaning
11830 * negative polarity.
11832 if (!(pipe_config->base.adjusted_mode.flags &
11833 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11834 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11836 if (!(pipe_config->base.adjusted_mode.flags &
11837 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11838 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11840 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11845 base_bpp = pipe_config->pipe_bpp;
11848 * Determine the real pipe dimensions. Note that stereo modes can
11849 * increase the actual pipe size due to the frame doubling and
11850 * insertion of additional space for blanks between the frame. This
11851 * is stored in the crtc timings. We use the requested mode to do this
11852 * computation to clearly distinguish it from the adjusted mode, which
11853 * can be changed by the connectors in the below retry loop.
11855 drm_mode_get_hv_timing(&pipe_config->base.mode,
11856 &pipe_config->pipe_src_w,
11857 &pipe_config->pipe_src_h);
11859 for_each_new_connector_in_state(state, connector, connector_state, i) {
11860 if (connector_state->crtc != crtc)
11863 encoder = to_intel_encoder(connector_state->best_encoder);
11865 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11866 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11871 * Determine output_types before calling the .compute_config()
11872 * hooks so that the hooks can use this information safely.
11874 if (encoder->compute_output_type)
11875 pipe_config->output_types |=
11876 BIT(encoder->compute_output_type(encoder, pipe_config,
11879 pipe_config->output_types |= BIT(encoder->type);
11883 /* Ensure the port clock defaults are reset when retrying. */
11884 pipe_config->port_clock = 0;
11885 pipe_config->pixel_multiplier = 1;
11887 /* Fill in default crtc timings, allow encoders to overwrite them. */
11888 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11889 CRTC_STEREO_DOUBLE);
11891 /* Pass our mode to the connectors and the CRTC to give them a chance to
11892 * adjust it according to limitations or connector properties, and also
11893 * a chance to reject the mode entirely.
11895 for_each_new_connector_in_state(state, connector, connector_state, i) {
11896 if (connector_state->crtc != crtc)
11899 encoder = to_intel_encoder(connector_state->best_encoder);
11900 ret = encoder->compute_config(encoder, pipe_config,
11903 if (ret != -EDEADLK)
11904 DRM_DEBUG_KMS("Encoder config failure: %d\n",
11910 /* Set default port clock if not overwritten by the encoder. Needs to be
11911 * done afterwards in case the encoder adjusts the mode. */
11912 if (!pipe_config->port_clock)
11913 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11914 * pipe_config->pixel_multiplier;
11916 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11917 if (ret == -EDEADLK)
11920 DRM_DEBUG_KMS("CRTC fixup failed\n");
11924 if (ret == RETRY) {
11925 if (WARN(!retry, "loop in pipe configuration computation\n"))
11928 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11930 goto encoder_retry;
11933 /* Dithering seems to not pass-through bits correctly when it should, so
11934 * only enable it on 6bpc panels and when its not a compliance
11935 * test requesting 6bpc video pattern.
11937 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11938 !pipe_config->dither_force_disable;
11939 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11940 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11945 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11949 if (clock1 == clock2)
11952 if (!clock1 || !clock2)
11955 diff = abs(clock1 - clock2);
11957 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11964 intel_compare_m_n(unsigned int m, unsigned int n,
11965 unsigned int m2, unsigned int n2,
11968 if (m == m2 && n == n2)
11971 if (exact || !m || !n || !m2 || !n2)
11974 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11981 } else if (n < n2) {
11991 return intel_fuzzy_clock_check(m, m2);
11995 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11996 struct intel_link_m_n *m2_n2,
11999 if (m_n->tu == m2_n2->tu &&
12000 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12001 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12002 intel_compare_m_n(m_n->link_m, m_n->link_n,
12003 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12014 intel_compare_infoframe(const union hdmi_infoframe *a,
12015 const union hdmi_infoframe *b)
12017 return memcmp(a, b, sizeof(*a)) == 0;
12021 pipe_config_infoframe_err(struct drm_i915_private *dev_priv,
12022 bool adjust, const char *name,
12023 const union hdmi_infoframe *a,
12024 const union hdmi_infoframe *b)
12027 if ((drm_debug & DRM_UT_KMS) == 0)
12030 drm_dbg(DRM_UT_KMS, "mismatch in %s infoframe", name);
12031 drm_dbg(DRM_UT_KMS, "expected:");
12032 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12033 drm_dbg(DRM_UT_KMS, "found");
12034 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12036 drm_err("mismatch in %s infoframe", name);
12037 drm_err("expected:");
12038 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12040 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12044 static void __printf(3, 4)
12045 pipe_config_err(bool adjust, const char *name, const char *format, ...)
12047 struct va_format vaf;
12050 va_start(args, format);
12055 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
12057 drm_err("mismatch in %s %pV", name, &vaf);
12062 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
12064 if (i915_modparams.fastboot != -1)
12065 return i915_modparams.fastboot;
12067 /* Enable fastboot by default on Skylake and newer */
12068 if (INTEL_GEN(dev_priv) >= 9)
12071 /* Enable fastboot by default on VLV and CHV */
12072 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12075 /* Disabled by default on all others */
12080 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
12081 struct intel_crtc_state *current_config,
12082 struct intel_crtc_state *pipe_config,
12085 struct intel_crtc *crtc = to_intel_crtc(current_config->base.crtc);
12087 bool fixup_inherited = adjust &&
12088 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
12089 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
12091 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
12092 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12096 #define PIPE_CONF_CHECK_X(name) do { \
12097 if (current_config->name != pipe_config->name) { \
12098 pipe_config_err(adjust, __stringify(name), \
12099 "(expected 0x%08x, found 0x%08x)\n", \
12100 current_config->name, \
12101 pipe_config->name); \
12106 #define PIPE_CONF_CHECK_I(name) do { \
12107 if (current_config->name != pipe_config->name) { \
12108 pipe_config_err(adjust, __stringify(name), \
12109 "(expected %i, found %i)\n", \
12110 current_config->name, \
12111 pipe_config->name); \
12116 #define PIPE_CONF_CHECK_BOOL(name) do { \
12117 if (current_config->name != pipe_config->name) { \
12118 pipe_config_err(adjust, __stringify(name), \
12119 "(expected %s, found %s)\n", \
12120 yesno(current_config->name), \
12121 yesno(pipe_config->name)); \
12127 * Checks state where we only read out the enabling, but not the entire
12128 * state itself (like full infoframes or ELD for audio). These states
12129 * require a full modeset on bootup to fix up.
12131 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12132 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12133 PIPE_CONF_CHECK_BOOL(name); \
12135 pipe_config_err(adjust, __stringify(name), \
12136 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
12137 yesno(current_config->name), \
12138 yesno(pipe_config->name)); \
12143 #define PIPE_CONF_CHECK_P(name) do { \
12144 if (current_config->name != pipe_config->name) { \
12145 pipe_config_err(adjust, __stringify(name), \
12146 "(expected %p, found %p)\n", \
12147 current_config->name, \
12148 pipe_config->name); \
12153 #define PIPE_CONF_CHECK_M_N(name) do { \
12154 if (!intel_compare_link_m_n(¤t_config->name, \
12155 &pipe_config->name,\
12157 pipe_config_err(adjust, __stringify(name), \
12158 "(expected tu %i gmch %i/%i link %i/%i, " \
12159 "found tu %i, gmch %i/%i link %i/%i)\n", \
12160 current_config->name.tu, \
12161 current_config->name.gmch_m, \
12162 current_config->name.gmch_n, \
12163 current_config->name.link_m, \
12164 current_config->name.link_n, \
12165 pipe_config->name.tu, \
12166 pipe_config->name.gmch_m, \
12167 pipe_config->name.gmch_n, \
12168 pipe_config->name.link_m, \
12169 pipe_config->name.link_n); \
12174 /* This is required for BDW+ where there is only one set of registers for
12175 * switching between high and low RR.
12176 * This macro can be used whenever a comparison has to be made between one
12177 * hw state and multiple sw state variables.
12179 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
12180 if (!intel_compare_link_m_n(¤t_config->name, \
12181 &pipe_config->name, adjust) && \
12182 !intel_compare_link_m_n(¤t_config->alt_name, \
12183 &pipe_config->name, adjust)) { \
12184 pipe_config_err(adjust, __stringify(name), \
12185 "(expected tu %i gmch %i/%i link %i/%i, " \
12186 "or tu %i gmch %i/%i link %i/%i, " \
12187 "found tu %i, gmch %i/%i link %i/%i)\n", \
12188 current_config->name.tu, \
12189 current_config->name.gmch_m, \
12190 current_config->name.gmch_n, \
12191 current_config->name.link_m, \
12192 current_config->name.link_n, \
12193 current_config->alt_name.tu, \
12194 current_config->alt_name.gmch_m, \
12195 current_config->alt_name.gmch_n, \
12196 current_config->alt_name.link_m, \
12197 current_config->alt_name.link_n, \
12198 pipe_config->name.tu, \
12199 pipe_config->name.gmch_m, \
12200 pipe_config->name.gmch_n, \
12201 pipe_config->name.link_m, \
12202 pipe_config->name.link_n); \
12207 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
12208 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12209 pipe_config_err(adjust, __stringify(name), \
12210 "(%x) (expected %i, found %i)\n", \
12212 current_config->name & (mask), \
12213 pipe_config->name & (mask)); \
12218 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
12219 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12220 pipe_config_err(adjust, __stringify(name), \
12221 "(expected %i, found %i)\n", \
12222 current_config->name, \
12223 pipe_config->name); \
12228 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
12229 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
12230 &pipe_config->infoframes.name)) { \
12231 pipe_config_infoframe_err(dev_priv, adjust, __stringify(name), \
12232 ¤t_config->infoframes.name, \
12233 &pipe_config->infoframes.name); \
12238 #define PIPE_CONF_QUIRK(quirk) \
12239 ((current_config->quirks | pipe_config->quirks) & (quirk))
12241 PIPE_CONF_CHECK_I(cpu_transcoder);
12243 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
12244 PIPE_CONF_CHECK_I(fdi_lanes);
12245 PIPE_CONF_CHECK_M_N(fdi_m_n);
12247 PIPE_CONF_CHECK_I(lane_count);
12248 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12250 if (INTEL_GEN(dev_priv) < 8) {
12251 PIPE_CONF_CHECK_M_N(dp_m_n);
12253 if (current_config->has_drrs)
12254 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12256 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12258 PIPE_CONF_CHECK_X(output_types);
12260 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12261 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12262 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12263 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12264 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12265 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12267 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12268 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12269 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12270 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12271 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12272 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12274 PIPE_CONF_CHECK_I(pixel_multiplier);
12275 PIPE_CONF_CHECK_I(output_format);
12276 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
12277 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
12278 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12279 PIPE_CONF_CHECK_BOOL(limited_color_range);
12281 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
12282 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
12283 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
12285 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
12287 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12288 DRM_MODE_FLAG_INTERLACE);
12290 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12291 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12292 DRM_MODE_FLAG_PHSYNC);
12293 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12294 DRM_MODE_FLAG_NHSYNC);
12295 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12296 DRM_MODE_FLAG_PVSYNC);
12297 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12298 DRM_MODE_FLAG_NVSYNC);
12301 PIPE_CONF_CHECK_X(gmch_pfit.control);
12302 /* pfit ratios are autocomputed by the hw on gen4+ */
12303 if (INTEL_GEN(dev_priv) < 4)
12304 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12305 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12308 * Changing the EDP transcoder input mux
12309 * (A_ONOFF vs. A_ON) requires a full modeset.
12311 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
12312 current_config->cpu_transcoder == TRANSCODER_EDP)
12313 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
12316 PIPE_CONF_CHECK_I(pipe_src_w);
12317 PIPE_CONF_CHECK_I(pipe_src_h);
12319 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
12320 if (current_config->pch_pfit.enabled) {
12321 PIPE_CONF_CHECK_X(pch_pfit.pos);
12322 PIPE_CONF_CHECK_X(pch_pfit.size);
12325 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12326 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
12328 PIPE_CONF_CHECK_X(gamma_mode);
12329 if (IS_CHERRYVIEW(dev_priv))
12330 PIPE_CONF_CHECK_X(cgm_mode);
12332 PIPE_CONF_CHECK_X(csc_mode);
12333 PIPE_CONF_CHECK_BOOL(gamma_enable);
12334 PIPE_CONF_CHECK_BOOL(csc_enable);
12337 PIPE_CONF_CHECK_BOOL(double_wide);
12339 PIPE_CONF_CHECK_P(shared_dpll);
12340 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12341 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12342 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12343 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12344 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12345 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12346 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12347 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12348 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12349 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
12350 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
12351 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
12352 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
12353 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
12354 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
12355 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
12356 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
12357 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
12358 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
12359 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
12360 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
12361 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
12362 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
12363 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
12364 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
12365 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
12366 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
12367 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
12368 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
12369 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
12370 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
12372 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12373 PIPE_CONF_CHECK_X(dsi_pll.div);
12375 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
12376 PIPE_CONF_CHECK_I(pipe_bpp);
12378 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12379 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12381 PIPE_CONF_CHECK_I(min_voltage_level);
12383 PIPE_CONF_CHECK_X(infoframes.enable);
12384 PIPE_CONF_CHECK_X(infoframes.gcp);
12385 PIPE_CONF_CHECK_INFOFRAME(avi);
12386 PIPE_CONF_CHECK_INFOFRAME(spd);
12387 PIPE_CONF_CHECK_INFOFRAME(hdmi);
12389 #undef PIPE_CONF_CHECK_X
12390 #undef PIPE_CONF_CHECK_I
12391 #undef PIPE_CONF_CHECK_BOOL
12392 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
12393 #undef PIPE_CONF_CHECK_P
12394 #undef PIPE_CONF_CHECK_FLAGS
12395 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12396 #undef PIPE_CONF_QUIRK
12401 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12402 const struct intel_crtc_state *pipe_config)
12404 if (pipe_config->has_pch_encoder) {
12405 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12406 &pipe_config->fdi_m_n);
12407 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12410 * FDI already provided one idea for the dotclock.
12411 * Yell if the encoder disagrees.
12413 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12414 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12415 fdi_dotclock, dotclock);
12419 static void verify_wm_state(struct drm_crtc *crtc,
12420 struct drm_crtc_state *new_state)
12422 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12423 struct skl_hw_state {
12424 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
12425 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
12426 struct skl_ddb_allocation ddb;
12427 struct skl_pipe_wm wm;
12429 struct skl_ddb_allocation *sw_ddb;
12430 struct skl_pipe_wm *sw_wm;
12431 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
12432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12433 const enum pipe pipe = intel_crtc->pipe;
12434 int plane, level, max_level = ilk_wm_max_level(dev_priv);
12436 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
12439 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
12443 skl_pipe_wm_get_hw_state(intel_crtc, &hw->wm);
12444 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
12446 skl_pipe_ddb_get_hw_state(intel_crtc, hw->ddb_y, hw->ddb_uv);
12448 skl_ddb_get_hw_state(dev_priv, &hw->ddb);
12449 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12451 if (INTEL_GEN(dev_priv) >= 11 &&
12452 hw->ddb.enabled_slices != sw_ddb->enabled_slices)
12453 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
12454 sw_ddb->enabled_slices,
12455 hw->ddb.enabled_slices);
12458 for_each_universal_plane(dev_priv, pipe, plane) {
12459 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12461 hw_plane_wm = &hw->wm.planes[plane];
12462 sw_plane_wm = &sw_wm->planes[plane];
12465 for (level = 0; level <= max_level; level++) {
12466 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12467 &sw_plane_wm->wm[level]))
12470 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12471 pipe_name(pipe), plane + 1, level,
12472 sw_plane_wm->wm[level].plane_en,
12473 sw_plane_wm->wm[level].plane_res_b,
12474 sw_plane_wm->wm[level].plane_res_l,
12475 hw_plane_wm->wm[level].plane_en,
12476 hw_plane_wm->wm[level].plane_res_b,
12477 hw_plane_wm->wm[level].plane_res_l);
12480 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12481 &sw_plane_wm->trans_wm)) {
12482 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12483 pipe_name(pipe), plane + 1,
12484 sw_plane_wm->trans_wm.plane_en,
12485 sw_plane_wm->trans_wm.plane_res_b,
12486 sw_plane_wm->trans_wm.plane_res_l,
12487 hw_plane_wm->trans_wm.plane_en,
12488 hw_plane_wm->trans_wm.plane_res_b,
12489 hw_plane_wm->trans_wm.plane_res_l);
12493 hw_ddb_entry = &hw->ddb_y[plane];
12494 sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
12496 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12497 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12498 pipe_name(pipe), plane + 1,
12499 sw_ddb_entry->start, sw_ddb_entry->end,
12500 hw_ddb_entry->start, hw_ddb_entry->end);
12506 * If the cursor plane isn't active, we may not have updated it's ddb
12507 * allocation. In that case since the ddb allocation will be updated
12508 * once the plane becomes visible, we can skip this check
12511 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12513 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
12514 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12517 for (level = 0; level <= max_level; level++) {
12518 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12519 &sw_plane_wm->wm[level]))
12522 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12523 pipe_name(pipe), level,
12524 sw_plane_wm->wm[level].plane_en,
12525 sw_plane_wm->wm[level].plane_res_b,
12526 sw_plane_wm->wm[level].plane_res_l,
12527 hw_plane_wm->wm[level].plane_en,
12528 hw_plane_wm->wm[level].plane_res_b,
12529 hw_plane_wm->wm[level].plane_res_l);
12532 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12533 &sw_plane_wm->trans_wm)) {
12534 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12536 sw_plane_wm->trans_wm.plane_en,
12537 sw_plane_wm->trans_wm.plane_res_b,
12538 sw_plane_wm->trans_wm.plane_res_l,
12539 hw_plane_wm->trans_wm.plane_en,
12540 hw_plane_wm->trans_wm.plane_res_b,
12541 hw_plane_wm->trans_wm.plane_res_l);
12545 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
12546 sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
12548 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12549 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12551 sw_ddb_entry->start, sw_ddb_entry->end,
12552 hw_ddb_entry->start, hw_ddb_entry->end);
12560 verify_connector_state(struct drm_device *dev,
12561 struct drm_atomic_state *state,
12562 struct drm_crtc *crtc)
12564 struct drm_connector *connector;
12565 struct drm_connector_state *new_conn_state;
12568 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12569 struct drm_encoder *encoder = connector->encoder;
12570 struct drm_crtc_state *crtc_state = NULL;
12572 if (new_conn_state->crtc != crtc)
12576 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
12578 intel_connector_verify_state(crtc_state, new_conn_state);
12580 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12581 "connector's atomic encoder doesn't match legacy encoder\n");
12586 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12588 struct intel_encoder *encoder;
12589 struct drm_connector *connector;
12590 struct drm_connector_state *old_conn_state, *new_conn_state;
12593 for_each_intel_encoder(dev, encoder) {
12594 bool enabled = false, found = false;
12597 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12598 encoder->base.base.id,
12599 encoder->base.name);
12601 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12602 new_conn_state, i) {
12603 if (old_conn_state->best_encoder == &encoder->base)
12606 if (new_conn_state->best_encoder != &encoder->base)
12608 found = enabled = true;
12610 I915_STATE_WARN(new_conn_state->crtc !=
12611 encoder->base.crtc,
12612 "connector's crtc doesn't match encoder crtc\n");
12618 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12619 "encoder's enabled state mismatch "
12620 "(expected %i, found %i)\n",
12621 !!encoder->base.crtc, enabled);
12623 if (!encoder->base.crtc) {
12626 active = encoder->get_hw_state(encoder, &pipe);
12627 I915_STATE_WARN(active,
12628 "encoder detached but still enabled on pipe %c.\n",
12635 verify_crtc_state(struct drm_crtc *crtc,
12636 struct drm_crtc_state *old_crtc_state,
12637 struct drm_crtc_state *new_crtc_state)
12639 struct drm_device *dev = crtc->dev;
12640 struct drm_i915_private *dev_priv = to_i915(dev);
12641 struct intel_encoder *encoder;
12642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12643 struct intel_crtc_state *pipe_config, *sw_config;
12644 struct drm_atomic_state *old_state;
12647 old_state = old_crtc_state->state;
12648 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12649 pipe_config = to_intel_crtc_state(old_crtc_state);
12650 memset(pipe_config, 0, sizeof(*pipe_config));
12651 pipe_config->base.crtc = crtc;
12652 pipe_config->base.state = old_state;
12654 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12656 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12658 /* we keep both pipes enabled on 830 */
12659 if (IS_I830(dev_priv))
12660 active = new_crtc_state->active;
12662 I915_STATE_WARN(new_crtc_state->active != active,
12663 "crtc active state doesn't match with hw state "
12664 "(expected %i, found %i)\n", new_crtc_state->active, active);
12666 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12667 "transitional active state does not match atomic hw state "
12668 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12670 for_each_encoder_on_crtc(dev, crtc, encoder) {
12673 active = encoder->get_hw_state(encoder, &pipe);
12674 I915_STATE_WARN(active != new_crtc_state->active,
12675 "[ENCODER:%i] active %i with crtc active %i\n",
12676 encoder->base.base.id, active, new_crtc_state->active);
12678 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12679 "Encoder connected to wrong pipe %c\n",
12683 encoder->get_config(encoder, pipe_config);
12686 intel_crtc_compute_pixel_rate(pipe_config);
12688 if (!new_crtc_state->active)
12691 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12693 sw_config = to_intel_crtc_state(new_crtc_state);
12694 if (!intel_pipe_config_compare(dev_priv, sw_config,
12695 pipe_config, false)) {
12696 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12697 intel_dump_pipe_config(intel_crtc, pipe_config,
12699 intel_dump_pipe_config(intel_crtc, sw_config,
12705 intel_verify_planes(struct intel_atomic_state *state)
12707 struct intel_plane *plane;
12708 const struct intel_plane_state *plane_state;
12711 for_each_new_intel_plane_in_state(state, plane,
12713 assert_plane(plane, plane_state->slave ||
12714 plane_state->base.visible);
12718 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12719 struct intel_shared_dpll *pll,
12720 struct drm_crtc *crtc,
12721 struct drm_crtc_state *new_state)
12723 struct intel_dpll_hw_state dpll_hw_state;
12724 unsigned int crtc_mask;
12727 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12729 DRM_DEBUG_KMS("%s\n", pll->info->name);
12731 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
12733 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
12734 I915_STATE_WARN(!pll->on && pll->active_mask,
12735 "pll in active use but not on in sw tracking\n");
12736 I915_STATE_WARN(pll->on && !pll->active_mask,
12737 "pll is on but not used by any active crtc\n");
12738 I915_STATE_WARN(pll->on != active,
12739 "pll on state mismatch (expected %i, found %i)\n",
12744 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12745 "more active pll users than references: %x vs %x\n",
12746 pll->active_mask, pll->state.crtc_mask);
12751 crtc_mask = drm_crtc_mask(crtc);
12753 if (new_state->active)
12754 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12755 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12756 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12758 I915_STATE_WARN(pll->active_mask & crtc_mask,
12759 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12760 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12762 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12763 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12764 crtc_mask, pll->state.crtc_mask);
12766 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12768 sizeof(dpll_hw_state)),
12769 "pll hw state mismatch\n");
12773 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12774 struct drm_crtc_state *old_crtc_state,
12775 struct drm_crtc_state *new_crtc_state)
12777 struct drm_i915_private *dev_priv = to_i915(dev);
12778 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12779 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12781 if (new_state->shared_dpll)
12782 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12784 if (old_state->shared_dpll &&
12785 old_state->shared_dpll != new_state->shared_dpll) {
12786 unsigned int crtc_mask = drm_crtc_mask(crtc);
12787 struct intel_shared_dpll *pll = old_state->shared_dpll;
12789 I915_STATE_WARN(pll->active_mask & crtc_mask,
12790 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12791 pipe_name(drm_crtc_index(crtc)));
12792 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12793 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12794 pipe_name(drm_crtc_index(crtc)));
12799 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12800 struct drm_atomic_state *state,
12801 struct drm_crtc_state *old_state,
12802 struct drm_crtc_state *new_state)
12804 if (!needs_modeset(new_state) &&
12805 !to_intel_crtc_state(new_state)->update_pipe)
12808 verify_wm_state(crtc, new_state);
12809 verify_connector_state(crtc->dev, state, crtc);
12810 verify_crtc_state(crtc, old_state, new_state);
12811 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12815 verify_disabled_dpll_state(struct drm_device *dev)
12817 struct drm_i915_private *dev_priv = to_i915(dev);
12820 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12821 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12825 intel_modeset_verify_disabled(struct drm_device *dev,
12826 struct drm_atomic_state *state)
12828 verify_encoder_state(dev, state);
12829 verify_connector_state(dev, state, NULL);
12830 verify_disabled_dpll_state(dev);
12833 static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
12835 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
12836 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12839 * The scanline counter increments at the leading edge of hsync.
12841 * On most platforms it starts counting from vtotal-1 on the
12842 * first active line. That means the scanline counter value is
12843 * always one less than what we would expect. Ie. just after
12844 * start of vblank, which also occurs at start of hsync (on the
12845 * last active line), the scanline counter will read vblank_start-1.
12847 * On gen2 the scanline counter starts counting from 1 instead
12848 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12849 * to keep the value positive), instead of adding one.
12851 * On HSW+ the behaviour of the scanline counter depends on the output
12852 * type. For DP ports it behaves like most other platforms, but on HDMI
12853 * there's an extra 1 line difference. So we need to add two instead of
12854 * one to the value.
12856 * On VLV/CHV DSI the scanline counter would appear to increment
12857 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12858 * that means we can't tell whether we're in vblank or not while
12859 * we're on that particular line. We must still set scanline_offset
12860 * to 1 so that the vblank timestamps come out correct when we query
12861 * the scanline counter from within the vblank interrupt handler.
12862 * However if queried just before the start of vblank we'll get an
12863 * answer that's slightly in the future.
12865 if (IS_GEN(dev_priv, 2)) {
12866 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
12869 vtotal = adjusted_mode->crtc_vtotal;
12870 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12873 crtc->scanline_offset = vtotal - 1;
12874 } else if (HAS_DDI(dev_priv) &&
12875 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
12876 crtc->scanline_offset = 2;
12878 crtc->scanline_offset = 1;
12881 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12883 struct drm_device *dev = state->dev;
12884 struct drm_i915_private *dev_priv = to_i915(dev);
12885 struct drm_crtc *crtc;
12886 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12889 if (!dev_priv->display.crtc_compute_clock)
12892 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12894 struct intel_shared_dpll *old_dpll =
12895 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12897 if (!needs_modeset(new_crtc_state))
12900 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12905 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12910 * This implements the workaround described in the "notes" section of the mode
12911 * set sequence documentation. When going from no pipes or single pipe to
12912 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12913 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12915 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12917 struct drm_crtc_state *crtc_state;
12918 struct intel_crtc *intel_crtc;
12919 struct drm_crtc *crtc;
12920 struct intel_crtc_state *first_crtc_state = NULL;
12921 struct intel_crtc_state *other_crtc_state = NULL;
12922 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12925 /* look at all crtc's that are going to be enabled in during modeset */
12926 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12927 intel_crtc = to_intel_crtc(crtc);
12929 if (!crtc_state->active || !needs_modeset(crtc_state))
12932 if (first_crtc_state) {
12933 other_crtc_state = to_intel_crtc_state(crtc_state);
12936 first_crtc_state = to_intel_crtc_state(crtc_state);
12937 first_pipe = intel_crtc->pipe;
12941 /* No workaround needed? */
12942 if (!first_crtc_state)
12945 /* w/a possibly needed, check how many crtc's are already enabled. */
12946 for_each_intel_crtc(state->dev, intel_crtc) {
12947 struct intel_crtc_state *pipe_config;
12949 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12950 if (IS_ERR(pipe_config))
12951 return PTR_ERR(pipe_config);
12953 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12955 if (!pipe_config->base.active ||
12956 needs_modeset(&pipe_config->base))
12959 /* 2 or more enabled crtcs means no need for w/a */
12960 if (enabled_pipe != INVALID_PIPE)
12963 enabled_pipe = intel_crtc->pipe;
12966 if (enabled_pipe != INVALID_PIPE)
12967 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12968 else if (other_crtc_state)
12969 other_crtc_state->hsw_workaround_pipe = first_pipe;
12974 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12976 struct drm_crtc *crtc;
12978 /* Add all pipes to the state */
12979 for_each_crtc(state->dev, crtc) {
12980 struct drm_crtc_state *crtc_state;
12982 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12983 if (IS_ERR(crtc_state))
12984 return PTR_ERR(crtc_state);
12990 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12992 struct drm_crtc *crtc;
12995 * Add all pipes to the state, and force
12996 * a modeset on all the active ones.
12998 for_each_crtc(state->dev, crtc) {
12999 struct drm_crtc_state *crtc_state;
13002 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13003 if (IS_ERR(crtc_state))
13004 return PTR_ERR(crtc_state);
13006 if (!crtc_state->active || needs_modeset(crtc_state))
13009 crtc_state->mode_changed = true;
13011 ret = drm_atomic_add_affected_connectors(state, crtc);
13015 ret = drm_atomic_add_affected_planes(state, crtc);
13023 static int intel_modeset_checks(struct drm_atomic_state *state)
13025 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13026 struct drm_i915_private *dev_priv = to_i915(state->dev);
13027 struct drm_crtc *crtc;
13028 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13031 if (!check_digital_port_conflicts(state)) {
13032 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13036 /* keep the current setting */
13037 if (!intel_state->cdclk.force_min_cdclk_changed)
13038 intel_state->cdclk.force_min_cdclk =
13039 dev_priv->cdclk.force_min_cdclk;
13041 intel_state->modeset = true;
13042 intel_state->active_crtcs = dev_priv->active_crtcs;
13043 intel_state->cdclk.logical = dev_priv->cdclk.logical;
13044 intel_state->cdclk.actual = dev_priv->cdclk.actual;
13045 intel_state->cdclk.pipe = INVALID_PIPE;
13047 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13048 if (new_crtc_state->active)
13049 intel_state->active_crtcs |= 1 << i;
13051 intel_state->active_crtcs &= ~(1 << i);
13053 if (old_crtc_state->active != new_crtc_state->active)
13054 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13058 * See if the config requires any additional preparation, e.g.
13059 * to adjust global state with pipes off. We need to do this
13060 * here so we can get the modeset_pipe updated config for the new
13061 * mode set on this crtc. For other crtcs we need to use the
13062 * adjusted_mode bits in the crtc directly.
13064 if (dev_priv->display.modeset_calc_cdclk) {
13067 ret = dev_priv->display.modeset_calc_cdclk(state);
13072 * Writes to dev_priv->cdclk.logical must protected by
13073 * holding all the crtc locks, even if we don't end up
13074 * touching the hardware
13076 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
13077 &intel_state->cdclk.logical)) {
13078 ret = intel_lock_all_pipes(state);
13083 if (is_power_of_2(intel_state->active_crtcs)) {
13084 struct drm_crtc *crtc;
13085 struct drm_crtc_state *crtc_state;
13087 pipe = ilog2(intel_state->active_crtcs);
13088 crtc = &intel_get_crtc_for_pipe(dev_priv, pipe)->base;
13089 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
13090 if (crtc_state && needs_modeset(crtc_state))
13091 pipe = INVALID_PIPE;
13093 pipe = INVALID_PIPE;
13096 /* All pipes must be switched off while we change the cdclk. */
13097 if (pipe != INVALID_PIPE &&
13098 intel_cdclk_needs_cd2x_update(dev_priv,
13099 &dev_priv->cdclk.actual,
13100 &intel_state->cdclk.actual)) {
13101 ret = intel_lock_all_pipes(state);
13105 intel_state->cdclk.pipe = pipe;
13106 } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
13107 &intel_state->cdclk.actual)) {
13108 ret = intel_modeset_all_pipes(state);
13112 intel_state->cdclk.pipe = INVALID_PIPE;
13115 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
13116 intel_state->cdclk.logical.cdclk,
13117 intel_state->cdclk.actual.cdclk);
13118 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
13119 intel_state->cdclk.logical.voltage_level,
13120 intel_state->cdclk.actual.voltage_level);
13123 intel_modeset_clear_plls(state);
13125 if (IS_HASWELL(dev_priv))
13126 return haswell_mode_set_planes_workaround(state);
13132 * Handle calculation of various watermark data at the end of the atomic check
13133 * phase. The code here should be run after the per-crtc and per-plane 'check'
13134 * handlers to ensure that all derived state has been updated.
13136 static int calc_watermark_data(struct intel_atomic_state *state)
13138 struct drm_device *dev = state->base.dev;
13139 struct drm_i915_private *dev_priv = to_i915(dev);
13141 /* Is there platform-specific watermark information to calculate? */
13142 if (dev_priv->display.compute_global_watermarks)
13143 return dev_priv->display.compute_global_watermarks(state);
13149 * intel_atomic_check - validate state object
13151 * @state: state to validate
13153 static int intel_atomic_check(struct drm_device *dev,
13154 struct drm_atomic_state *state)
13156 struct drm_i915_private *dev_priv = to_i915(dev);
13157 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13158 struct drm_crtc *crtc;
13159 struct drm_crtc_state *old_crtc_state, *crtc_state;
13161 bool any_ms = intel_state->cdclk.force_min_cdclk_changed;
13163 /* Catch I915_MODE_FLAG_INHERITED */
13164 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
13166 if (crtc_state->mode.private_flags !=
13167 old_crtc_state->mode.private_flags)
13168 crtc_state->mode_changed = true;
13171 ret = drm_atomic_helper_check_modeset(dev, state);
13175 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
13176 struct intel_crtc_state *pipe_config =
13177 to_intel_crtc_state(crtc_state);
13179 if (!needs_modeset(crtc_state))
13182 if (!crtc_state->enable) {
13187 ret = intel_modeset_pipe_config(crtc, pipe_config);
13188 if (ret == -EDEADLK)
13191 intel_dump_pipe_config(to_intel_crtc(crtc),
13192 pipe_config, "[failed]");
13196 if (intel_pipe_config_compare(dev_priv,
13197 to_intel_crtc_state(old_crtc_state),
13198 pipe_config, true)) {
13199 crtc_state->mode_changed = false;
13200 pipe_config->update_pipe = true;
13203 if (needs_modeset(crtc_state))
13206 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13207 needs_modeset(crtc_state) ?
13208 "[modeset]" : "[fastset]");
13211 ret = drm_dp_mst_atomic_check(state);
13216 ret = intel_modeset_checks(state);
13221 intel_state->cdclk.logical = dev_priv->cdclk.logical;
13224 ret = icl_add_linked_planes(intel_state);
13228 ret = drm_atomic_helper_check_planes(dev, state);
13232 intel_fbc_choose_crtc(dev_priv, intel_state);
13233 return calc_watermark_data(intel_state);
13236 static int intel_atomic_prepare_commit(struct drm_device *dev,
13237 struct drm_atomic_state *state)
13239 return drm_atomic_helper_prepare_planes(dev, state);
13242 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13244 struct drm_device *dev = crtc->base.dev;
13245 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
13247 if (!vblank->max_vblank_count)
13248 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
13250 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13253 static void intel_update_crtc(struct drm_crtc *crtc,
13254 struct drm_atomic_state *state,
13255 struct drm_crtc_state *old_crtc_state,
13256 struct drm_crtc_state *new_crtc_state)
13258 struct drm_device *dev = crtc->dev;
13259 struct drm_i915_private *dev_priv = to_i915(dev);
13260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13261 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
13262 bool modeset = needs_modeset(new_crtc_state);
13263 struct intel_plane_state *new_plane_state =
13264 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
13265 to_intel_plane(crtc->primary));
13268 update_scanline_offset(pipe_config);
13269 dev_priv->display.crtc_enable(pipe_config, state);
13271 /* vblanks work again, re-enable pipe CRC. */
13272 intel_crtc_enable_pipe_crc(intel_crtc);
13274 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
13277 if (pipe_config->update_pipe)
13278 intel_encoders_update_pipe(crtc, pipe_config, state);
13281 if (pipe_config->update_pipe && !pipe_config->enable_fbc)
13282 intel_fbc_disable(intel_crtc);
13283 else if (new_plane_state)
13284 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
13286 intel_begin_crtc_commit(to_intel_atomic_state(state), intel_crtc);
13288 if (INTEL_GEN(dev_priv) >= 9)
13289 skl_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
13291 i9xx_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
13293 intel_finish_crtc_commit(to_intel_atomic_state(state), intel_crtc);
13296 static void intel_update_crtcs(struct drm_atomic_state *state)
13298 struct drm_crtc *crtc;
13299 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13302 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13303 if (!new_crtc_state->active)
13306 intel_update_crtc(crtc, state, old_crtc_state,
13311 static void skl_update_crtcs(struct drm_atomic_state *state)
13313 struct drm_i915_private *dev_priv = to_i915(state->dev);
13314 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13315 struct drm_crtc *crtc;
13316 struct intel_crtc *intel_crtc;
13317 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13318 struct intel_crtc_state *cstate;
13319 unsigned int updated = 0;
13323 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
13324 u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
13325 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
13327 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
13328 /* ignore allocations for crtc's that have been turned off. */
13329 if (new_crtc_state->active)
13330 entries[i] = to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
13332 /* If 2nd DBuf slice required, enable it here */
13333 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
13334 icl_dbuf_slices_update(dev_priv, required_slices);
13337 * Whenever the number of active pipes changes, we need to make sure we
13338 * update the pipes in the right order so that their ddb allocations
13339 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
13340 * cause pipe underruns and other bad stuff.
13345 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13346 bool vbl_wait = false;
13347 unsigned int cmask = drm_crtc_mask(crtc);
13349 intel_crtc = to_intel_crtc(crtc);
13350 cstate = to_intel_crtc_state(new_crtc_state);
13351 pipe = intel_crtc->pipe;
13353 if (updated & cmask || !cstate->base.active)
13356 if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb,
13358 INTEL_INFO(dev_priv)->num_pipes, i))
13362 entries[i] = cstate->wm.skl.ddb;
13365 * If this is an already active pipe, it's DDB changed,
13366 * and this isn't the last pipe that needs updating
13367 * then we need to wait for a vblank to pass for the
13368 * new ddb allocation to take effect.
13370 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
13371 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
13372 !new_crtc_state->active_changed &&
13373 intel_state->wm_results.dirty_pipes != updated)
13376 intel_update_crtc(crtc, state, old_crtc_state,
13380 intel_wait_for_vblank(dev_priv, pipe);
13384 } while (progress);
13386 /* If 2nd DBuf slice is no more required disable it */
13387 if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
13388 icl_dbuf_slices_update(dev_priv, required_slices);
13391 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
13393 struct intel_atomic_state *state, *next;
13394 struct llist_node *freed;
13396 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
13397 llist_for_each_entry_safe(state, next, freed, freed)
13398 drm_atomic_state_put(&state->base);
13401 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
13403 struct drm_i915_private *dev_priv =
13404 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
13406 intel_atomic_helper_free_state(dev_priv);
13409 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
13411 struct wait_queue_entry wait_fence, wait_reset;
13412 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
13414 init_wait_entry(&wait_fence, 0);
13415 init_wait_entry(&wait_reset, 0);
13417 prepare_to_wait(&intel_state->commit_ready.wait,
13418 &wait_fence, TASK_UNINTERRUPTIBLE);
13419 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
13420 &wait_reset, TASK_UNINTERRUPTIBLE);
13423 if (i915_sw_fence_done(&intel_state->commit_ready)
13424 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
13429 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
13430 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
13433 static void intel_atomic_cleanup_work(struct work_struct *work)
13435 struct drm_atomic_state *state =
13436 container_of(work, struct drm_atomic_state, commit_work);
13437 struct drm_i915_private *i915 = to_i915(state->dev);
13439 drm_atomic_helper_cleanup_planes(&i915->drm, state);
13440 drm_atomic_helper_commit_cleanup_done(state);
13441 drm_atomic_state_put(state);
13443 intel_atomic_helper_free_state(i915);
13446 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13448 struct drm_device *dev = state->dev;
13449 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13450 struct drm_i915_private *dev_priv = to_i915(dev);
13451 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13452 struct intel_crtc_state *new_intel_crtc_state, *old_intel_crtc_state;
13453 struct drm_crtc *crtc;
13454 struct intel_crtc *intel_crtc;
13455 u64 put_domains[I915_MAX_PIPES] = {};
13456 intel_wakeref_t wakeref = 0;
13459 intel_atomic_commit_fence_wait(intel_state);
13461 drm_atomic_helper_wait_for_dependencies(state);
13463 if (intel_state->modeset)
13464 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13466 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13467 old_intel_crtc_state = to_intel_crtc_state(old_crtc_state);
13468 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13469 intel_crtc = to_intel_crtc(crtc);
13471 if (needs_modeset(new_crtc_state) ||
13472 to_intel_crtc_state(new_crtc_state)->update_pipe) {
13474 put_domains[intel_crtc->pipe] =
13475 modeset_get_crtc_power_domains(crtc,
13476 new_intel_crtc_state);
13479 if (!needs_modeset(new_crtc_state))
13482 intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);
13484 if (old_crtc_state->active) {
13485 intel_crtc_disable_planes(intel_state, intel_crtc);
13488 * We need to disable pipe CRC before disabling the pipe,
13489 * or we race against vblank off.
13491 intel_crtc_disable_pipe_crc(intel_crtc);
13493 dev_priv->display.crtc_disable(old_intel_crtc_state, state);
13494 intel_crtc->active = false;
13495 intel_fbc_disable(intel_crtc);
13496 intel_disable_shared_dpll(old_intel_crtc_state);
13499 * Underruns don't always raise
13500 * interrupts, so check manually.
13502 intel_check_cpu_fifo_underruns(dev_priv);
13503 intel_check_pch_fifo_underruns(dev_priv);
13505 /* FIXME unify this for all platforms */
13506 if (!new_crtc_state->active &&
13507 !HAS_GMCH(dev_priv) &&
13508 dev_priv->display.initial_watermarks)
13509 dev_priv->display.initial_watermarks(intel_state,
13510 new_intel_crtc_state);
13514 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
13515 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
13516 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
13518 if (intel_state->modeset) {
13519 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13521 intel_set_cdclk_pre_plane_update(dev_priv,
13522 &intel_state->cdclk.actual,
13523 &dev_priv->cdclk.actual,
13524 intel_state->cdclk.pipe);
13527 * SKL workaround: bspec recommends we disable the SAGV when we
13528 * have more then one pipe enabled
13530 if (!intel_can_enable_sagv(state))
13531 intel_disable_sagv(dev_priv);
13533 intel_modeset_verify_disabled(dev, state);
13536 /* Complete the events for pipes that have now been disabled */
13537 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13538 bool modeset = needs_modeset(new_crtc_state);
13540 /* Complete events for now disable pipes here. */
13541 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
13542 spin_lock_irq(&dev->event_lock);
13543 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
13544 spin_unlock_irq(&dev->event_lock);
13546 new_crtc_state->event = NULL;
13550 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13551 dev_priv->display.update_crtcs(state);
13553 if (intel_state->modeset)
13554 intel_set_cdclk_post_plane_update(dev_priv,
13555 &intel_state->cdclk.actual,
13556 &dev_priv->cdclk.actual,
13557 intel_state->cdclk.pipe);
13559 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13560 * already, but still need the state for the delayed optimization. To
13562 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13563 * - schedule that vblank worker _before_ calling hw_done
13564 * - at the start of commit_tail, cancel it _synchrously
13565 * - switch over to the vblank wait helper in the core after that since
13566 * we don't need out special handling any more.
13568 drm_atomic_helper_wait_for_flip_done(dev, state);
13570 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13571 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13573 if (new_crtc_state->active &&
13574 !needs_modeset(new_crtc_state) &&
13575 (new_intel_crtc_state->base.color_mgmt_changed ||
13576 new_intel_crtc_state->update_pipe))
13577 intel_color_load_luts(new_intel_crtc_state);
13581 * Now that the vblank has passed, we can go ahead and program the
13582 * optimal watermarks on platforms that need two-step watermark
13585 * TODO: Move this (and other cleanup) to an async worker eventually.
13587 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13588 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13590 if (dev_priv->display.optimize_watermarks)
13591 dev_priv->display.optimize_watermarks(intel_state,
13592 new_intel_crtc_state);
13595 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13596 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13598 if (put_domains[i])
13599 modeset_put_power_domains(dev_priv, put_domains[i]);
13601 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13604 if (intel_state->modeset)
13605 intel_verify_planes(intel_state);
13607 if (intel_state->modeset && intel_can_enable_sagv(state))
13608 intel_enable_sagv(dev_priv);
13610 drm_atomic_helper_commit_hw_done(state);
13612 if (intel_state->modeset) {
13613 /* As one of the primary mmio accessors, KMS has a high
13614 * likelihood of triggering bugs in unclaimed access. After we
13615 * finish modesetting, see if an error has been flagged, and if
13616 * so enable debugging for the next modeset - and hope we catch
13619 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
13620 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
13624 * Defer the cleanup of the old state to a separate worker to not
13625 * impede the current task (userspace for blocking modesets) that
13626 * are executed inline. For out-of-line asynchronous modesets/flips,
13627 * deferring to a new worker seems overkill, but we would place a
13628 * schedule point (cond_resched()) here anyway to keep latencies
13631 INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
13632 queue_work(system_highpri_wq, &state->commit_work);
13635 static void intel_atomic_commit_work(struct work_struct *work)
13637 struct drm_atomic_state *state =
13638 container_of(work, struct drm_atomic_state, commit_work);
13640 intel_atomic_commit_tail(state);
13643 static int __i915_sw_fence_call
13644 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13645 enum i915_sw_fence_notify notify)
13647 struct intel_atomic_state *state =
13648 container_of(fence, struct intel_atomic_state, commit_ready);
13651 case FENCE_COMPLETE:
13652 /* we do blocking waits in the worker, nothing to do here */
13656 struct intel_atomic_helper *helper =
13657 &to_i915(state->base.dev)->atomic_helper;
13659 if (llist_add(&state->freed, &helper->free_list))
13660 schedule_work(&helper->free_work);
13665 return NOTIFY_DONE;
13668 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13670 struct drm_plane_state *old_plane_state, *new_plane_state;
13671 struct drm_plane *plane;
13674 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13675 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13676 intel_fb_obj(new_plane_state->fb),
13677 to_intel_plane(plane)->frontbuffer_bit);
13681 * intel_atomic_commit - commit validated state object
13683 * @state: the top-level driver state object
13684 * @nonblock: nonblocking commit
13686 * This function commits a top-level state object that has been validated
13687 * with drm_atomic_helper_check().
13690 * Zero for success or -errno.
13692 static int intel_atomic_commit(struct drm_device *dev,
13693 struct drm_atomic_state *state,
13696 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13697 struct drm_i915_private *dev_priv = to_i915(dev);
13700 drm_atomic_state_get(state);
13701 i915_sw_fence_init(&intel_state->commit_ready,
13702 intel_atomic_commit_ready);
13705 * The intel_legacy_cursor_update() fast path takes care
13706 * of avoiding the vblank waits for simple cursor
13707 * movement and flips. For cursor on/off and size changes,
13708 * we want to perform the vblank waits so that watermark
13709 * updates happen during the correct frames. Gen9+ have
13710 * double buffered watermarks and so shouldn't need this.
13712 * Unset state->legacy_cursor_update before the call to
13713 * drm_atomic_helper_setup_commit() because otherwise
13714 * drm_atomic_helper_wait_for_flip_done() is a noop and
13715 * we get FIFO underruns because we didn't wait
13718 * FIXME doing watermarks and fb cleanup from a vblank worker
13719 * (assuming we had any) would solve these problems.
13721 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
13722 struct intel_crtc_state *new_crtc_state;
13723 struct intel_crtc *crtc;
13726 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
13727 if (new_crtc_state->wm.need_postvbl_update ||
13728 new_crtc_state->update_wm_post)
13729 state->legacy_cursor_update = false;
13732 ret = intel_atomic_prepare_commit(dev, state);
13734 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13735 i915_sw_fence_commit(&intel_state->commit_ready);
13739 ret = drm_atomic_helper_setup_commit(state, nonblock);
13741 ret = drm_atomic_helper_swap_state(state, true);
13744 i915_sw_fence_commit(&intel_state->commit_ready);
13746 drm_atomic_helper_cleanup_planes(dev, state);
13749 dev_priv->wm.distrust_bios_wm = false;
13750 intel_shared_dpll_swap_state(state);
13751 intel_atomic_track_fbs(state);
13753 if (intel_state->modeset) {
13754 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
13755 sizeof(intel_state->min_cdclk));
13756 memcpy(dev_priv->min_voltage_level,
13757 intel_state->min_voltage_level,
13758 sizeof(intel_state->min_voltage_level));
13759 dev_priv->active_crtcs = intel_state->active_crtcs;
13760 dev_priv->cdclk.force_min_cdclk =
13761 intel_state->cdclk.force_min_cdclk;
13763 intel_cdclk_swap_state(intel_state);
13766 drm_atomic_state_get(state);
13767 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13769 i915_sw_fence_commit(&intel_state->commit_ready);
13770 if (nonblock && intel_state->modeset) {
13771 queue_work(dev_priv->modeset_wq, &state->commit_work);
13772 } else if (nonblock) {
13773 queue_work(system_unbound_wq, &state->commit_work);
13775 if (intel_state->modeset)
13776 flush_workqueue(dev_priv->modeset_wq);
13777 intel_atomic_commit_tail(state);
13783 static const struct drm_crtc_funcs intel_crtc_funcs = {
13784 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13785 .set_config = drm_atomic_helper_set_config,
13786 .destroy = intel_crtc_destroy,
13787 .page_flip = drm_atomic_helper_page_flip,
13788 .atomic_duplicate_state = intel_crtc_duplicate_state,
13789 .atomic_destroy_state = intel_crtc_destroy_state,
13790 .set_crc_source = intel_crtc_set_crc_source,
13791 .verify_crc_source = intel_crtc_verify_crc_source,
13792 .get_crc_sources = intel_crtc_get_crc_sources,
13795 struct wait_rps_boost {
13796 struct wait_queue_entry wait;
13798 struct drm_crtc *crtc;
13799 struct i915_request *request;
13802 static int do_rps_boost(struct wait_queue_entry *_wait,
13803 unsigned mode, int sync, void *key)
13805 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
13806 struct i915_request *rq = wait->request;
13809 * If we missed the vblank, but the request is already running it
13810 * is reasonable to assume that it will complete before the next
13811 * vblank without our intervention, so leave RPS alone.
13813 if (!i915_request_started(rq))
13814 gen6_rps_boost(rq);
13815 i915_request_put(rq);
13817 drm_crtc_vblank_put(wait->crtc);
13819 list_del(&wait->wait.entry);
13824 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
13825 struct dma_fence *fence)
13827 struct wait_rps_boost *wait;
13829 if (!dma_fence_is_i915(fence))
13832 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
13835 if (drm_crtc_vblank_get(crtc))
13838 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
13840 drm_crtc_vblank_put(crtc);
13844 wait->request = to_request(dma_fence_get(fence));
13847 wait->wait.func = do_rps_boost;
13848 wait->wait.flags = 0;
13850 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
13853 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
13855 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
13856 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13857 struct drm_framebuffer *fb = plane_state->base.fb;
13858 struct i915_vma *vma;
13860 if (plane->id == PLANE_CURSOR &&
13861 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
13862 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13863 const int align = intel_cursor_alignment(dev_priv);
13866 err = i915_gem_object_attach_phys(obj, align);
13871 vma = intel_pin_and_fence_fb_obj(fb,
13872 &plane_state->view,
13873 intel_plane_uses_fence(plane_state),
13874 &plane_state->flags);
13876 return PTR_ERR(vma);
13878 plane_state->vma = vma;
13883 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
13885 struct i915_vma *vma;
13887 vma = fetch_and_zero(&old_plane_state->vma);
13889 intel_unpin_fb_vma(vma, old_plane_state->flags);
13892 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
13894 struct i915_sched_attr attr = {
13895 .priority = I915_PRIORITY_DISPLAY,
13898 i915_gem_object_wait_priority(obj, 0, &attr);
13902 * intel_prepare_plane_fb - Prepare fb for usage on plane
13903 * @plane: drm plane to prepare for
13904 * @new_state: the plane state being prepared
13906 * Prepares a framebuffer for usage on a display plane. Generally this
13907 * involves pinning the underlying object and updating the frontbuffer tracking
13908 * bits. Some older platforms need special physical address handling for
13911 * Must be called with struct_mutex held.
13913 * Returns 0 on success, negative error code on failure.
13916 intel_prepare_plane_fb(struct drm_plane *plane,
13917 struct drm_plane_state *new_state)
13919 struct intel_atomic_state *intel_state =
13920 to_intel_atomic_state(new_state->state);
13921 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13922 struct drm_framebuffer *fb = new_state->fb;
13923 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13924 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13928 struct drm_crtc_state *crtc_state =
13929 drm_atomic_get_new_crtc_state(new_state->state,
13930 plane->state->crtc);
13932 /* Big Hammer, we also need to ensure that any pending
13933 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13934 * current scanout is retired before unpinning the old
13935 * framebuffer. Note that we rely on userspace rendering
13936 * into the buffer attached to the pipe they are waiting
13937 * on. If not, userspace generates a GPU hang with IPEHR
13938 * point to the MI_WAIT_FOR_EVENT.
13940 * This should only fail upon a hung GPU, in which case we
13941 * can safely continue.
13943 if (needs_modeset(crtc_state)) {
13944 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13945 old_obj->resv, NULL,
13953 if (new_state->fence) { /* explicit fencing */
13954 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13956 I915_FENCE_TIMEOUT,
13965 ret = i915_gem_object_pin_pages(obj);
13969 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13971 i915_gem_object_unpin_pages(obj);
13975 ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
13977 mutex_unlock(&dev_priv->drm.struct_mutex);
13978 i915_gem_object_unpin_pages(obj);
13982 fb_obj_bump_render_priority(obj);
13983 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13985 if (!new_state->fence) { /* implicit fencing */
13986 struct dma_fence *fence;
13988 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13990 false, I915_FENCE_TIMEOUT,
13995 fence = reservation_object_get_excl_rcu(obj->resv);
13997 add_rps_boost_after_vblank(new_state->crtc, fence);
13998 dma_fence_put(fence);
14001 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
14005 * We declare pageflips to be interactive and so merit a small bias
14006 * towards upclocking to deliver the frame on time. By only changing
14007 * the RPS thresholds to sample more regularly and aim for higher
14008 * clocks we can hopefully deliver low power workloads (like kodi)
14009 * that are not quite steady state without resorting to forcing
14010 * maximum clocks following a vblank miss (see do_rps_boost()).
14012 if (!intel_state->rps_interactive) {
14013 intel_rps_mark_interactive(dev_priv, true);
14014 intel_state->rps_interactive = true;
14021 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14022 * @plane: drm plane to clean up for
14023 * @old_state: the state from the previous modeset
14025 * Cleans up a framebuffer that has just been removed from a plane.
14027 * Must be called with struct_mutex held.
14030 intel_cleanup_plane_fb(struct drm_plane *plane,
14031 struct drm_plane_state *old_state)
14033 struct intel_atomic_state *intel_state =
14034 to_intel_atomic_state(old_state->state);
14035 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14037 if (intel_state->rps_interactive) {
14038 intel_rps_mark_interactive(dev_priv, false);
14039 intel_state->rps_interactive = false;
14042 /* Should only be called after a successful intel_prepare_plane_fb()! */
14043 mutex_lock(&dev_priv->drm.struct_mutex);
14044 intel_plane_unpin_fb(to_intel_plane_state(old_state));
14045 mutex_unlock(&dev_priv->drm.struct_mutex);
14049 skl_max_scale(const struct intel_crtc_state *crtc_state,
14052 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
14053 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14054 int max_scale, mult;
14055 int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
14057 if (!crtc_state->base.enable)
14058 return DRM_PLANE_HELPER_NO_SCALING;
14060 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14061 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
14063 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
14066 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
14067 return DRM_PLANE_HELPER_NO_SCALING;
14070 * skl max scale is lower of:
14071 * close to 3 but not 3, -1 is for that purpose
14075 mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
14076 tmpclk1 = (1 << 16) * mult - 1;
14077 tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
14078 max_scale = min(tmpclk1, tmpclk2);
14083 static void intel_begin_crtc_commit(struct intel_atomic_state *state,
14084 struct intel_crtc *crtc)
14086 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14087 struct intel_crtc_state *old_crtc_state =
14088 intel_atomic_get_old_crtc_state(state, crtc);
14089 struct intel_crtc_state *new_crtc_state =
14090 intel_atomic_get_new_crtc_state(state, crtc);
14091 bool modeset = needs_modeset(&new_crtc_state->base);
14093 /* Perform vblank evasion around commit operation */
14094 intel_pipe_update_start(new_crtc_state);
14099 if (new_crtc_state->base.color_mgmt_changed ||
14100 new_crtc_state->update_pipe)
14101 intel_color_commit(new_crtc_state);
14103 if (new_crtc_state->update_pipe)
14104 intel_update_pipe_config(old_crtc_state, new_crtc_state);
14105 else if (INTEL_GEN(dev_priv) >= 9)
14106 skl_detach_scalers(new_crtc_state);
14109 if (dev_priv->display.atomic_update_watermarks)
14110 dev_priv->display.atomic_update_watermarks(state,
14114 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14115 struct intel_crtc_state *crtc_state)
14117 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14119 if (!IS_GEN(dev_priv, 2))
14120 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14122 if (crtc_state->has_pch_encoder) {
14123 enum pipe pch_transcoder =
14124 intel_crtc_pch_transcoder(crtc);
14126 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14130 static void intel_finish_crtc_commit(struct intel_atomic_state *state,
14131 struct intel_crtc *crtc)
14133 struct intel_crtc_state *old_crtc_state =
14134 intel_atomic_get_old_crtc_state(state, crtc);
14135 struct intel_crtc_state *new_crtc_state =
14136 intel_atomic_get_new_crtc_state(state, crtc);
14138 intel_pipe_update_end(new_crtc_state);
14140 if (new_crtc_state->update_pipe &&
14141 !needs_modeset(&new_crtc_state->base) &&
14142 old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
14143 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14147 * intel_plane_destroy - destroy a plane
14148 * @plane: plane to destroy
14150 * Common destruction function for all types of planes (primary, cursor,
14153 void intel_plane_destroy(struct drm_plane *plane)
14155 drm_plane_cleanup(plane);
14156 kfree(to_intel_plane(plane));
14159 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
14160 u32 format, u64 modifier)
14162 switch (modifier) {
14163 case DRM_FORMAT_MOD_LINEAR:
14164 case I915_FORMAT_MOD_X_TILED:
14171 case DRM_FORMAT_C8:
14172 case DRM_FORMAT_RGB565:
14173 case DRM_FORMAT_XRGB1555:
14174 case DRM_FORMAT_XRGB8888:
14175 return modifier == DRM_FORMAT_MOD_LINEAR ||
14176 modifier == I915_FORMAT_MOD_X_TILED;
14182 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
14183 u32 format, u64 modifier)
14185 switch (modifier) {
14186 case DRM_FORMAT_MOD_LINEAR:
14187 case I915_FORMAT_MOD_X_TILED:
14194 case DRM_FORMAT_C8:
14195 case DRM_FORMAT_RGB565:
14196 case DRM_FORMAT_XRGB8888:
14197 case DRM_FORMAT_XBGR8888:
14198 case DRM_FORMAT_XRGB2101010:
14199 case DRM_FORMAT_XBGR2101010:
14200 return modifier == DRM_FORMAT_MOD_LINEAR ||
14201 modifier == I915_FORMAT_MOD_X_TILED;
14207 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
14208 u32 format, u64 modifier)
14210 return modifier == DRM_FORMAT_MOD_LINEAR &&
14211 format == DRM_FORMAT_ARGB8888;
14214 static const struct drm_plane_funcs i965_plane_funcs = {
14215 .update_plane = drm_atomic_helper_update_plane,
14216 .disable_plane = drm_atomic_helper_disable_plane,
14217 .destroy = intel_plane_destroy,
14218 .atomic_get_property = intel_plane_atomic_get_property,
14219 .atomic_set_property = intel_plane_atomic_set_property,
14220 .atomic_duplicate_state = intel_plane_duplicate_state,
14221 .atomic_destroy_state = intel_plane_destroy_state,
14222 .format_mod_supported = i965_plane_format_mod_supported,
14225 static const struct drm_plane_funcs i8xx_plane_funcs = {
14226 .update_plane = drm_atomic_helper_update_plane,
14227 .disable_plane = drm_atomic_helper_disable_plane,
14228 .destroy = intel_plane_destroy,
14229 .atomic_get_property = intel_plane_atomic_get_property,
14230 .atomic_set_property = intel_plane_atomic_set_property,
14231 .atomic_duplicate_state = intel_plane_duplicate_state,
14232 .atomic_destroy_state = intel_plane_destroy_state,
14233 .format_mod_supported = i8xx_plane_format_mod_supported,
14237 intel_legacy_cursor_update(struct drm_plane *plane,
14238 struct drm_crtc *crtc,
14239 struct drm_framebuffer *fb,
14240 int crtc_x, int crtc_y,
14241 unsigned int crtc_w, unsigned int crtc_h,
14242 u32 src_x, u32 src_y,
14243 u32 src_w, u32 src_h,
14244 struct drm_modeset_acquire_ctx *ctx)
14246 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
14248 struct drm_plane_state *old_plane_state, *new_plane_state;
14249 struct intel_plane *intel_plane = to_intel_plane(plane);
14250 struct drm_framebuffer *old_fb;
14251 struct intel_crtc_state *crtc_state =
14252 to_intel_crtc_state(crtc->state);
14253 struct intel_crtc_state *new_crtc_state;
14256 * When crtc is inactive or there is a modeset pending,
14257 * wait for it to complete in the slowpath
14259 if (!crtc_state->base.active || needs_modeset(&crtc_state->base) ||
14260 crtc_state->update_pipe)
14263 old_plane_state = plane->state;
14265 * Don't do an async update if there is an outstanding commit modifying
14266 * the plane. This prevents our async update's changes from getting
14267 * overridden by a previous synchronous update's state.
14269 if (old_plane_state->commit &&
14270 !try_wait_for_completion(&old_plane_state->commit->hw_done))
14274 * If any parameters change that may affect watermarks,
14275 * take the slowpath. Only changing fb or position should be
14278 if (old_plane_state->crtc != crtc ||
14279 old_plane_state->src_w != src_w ||
14280 old_plane_state->src_h != src_h ||
14281 old_plane_state->crtc_w != crtc_w ||
14282 old_plane_state->crtc_h != crtc_h ||
14283 !old_plane_state->fb != !fb)
14286 new_plane_state = intel_plane_duplicate_state(plane);
14287 if (!new_plane_state)
14290 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(crtc));
14291 if (!new_crtc_state) {
14296 drm_atomic_set_fb_for_plane(new_plane_state, fb);
14298 new_plane_state->src_x = src_x;
14299 new_plane_state->src_y = src_y;
14300 new_plane_state->src_w = src_w;
14301 new_plane_state->src_h = src_h;
14302 new_plane_state->crtc_x = crtc_x;
14303 new_plane_state->crtc_y = crtc_y;
14304 new_plane_state->crtc_w = crtc_w;
14305 new_plane_state->crtc_h = crtc_h;
14307 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
14308 to_intel_plane_state(old_plane_state),
14309 to_intel_plane_state(new_plane_state));
14313 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
14317 ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
14321 intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
14323 old_fb = old_plane_state->fb;
14324 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
14325 intel_plane->frontbuffer_bit);
14327 /* Swap plane state */
14328 plane->state = new_plane_state;
14331 * We cannot swap crtc_state as it may be in use by an atomic commit or
14332 * page flip that's running simultaneously. If we swap crtc_state and
14333 * destroy the old state, we will cause a use-after-free there.
14335 * Only update active_planes, which is needed for our internal
14336 * bookkeeping. Either value will do the right thing when updating
14337 * planes atomically. If the cursor was part of the atomic update then
14338 * we would have taken the slowpath.
14340 crtc_state->active_planes = new_crtc_state->active_planes;
14342 if (plane->state->visible)
14343 intel_update_plane(intel_plane, crtc_state,
14344 to_intel_plane_state(plane->state));
14346 intel_disable_plane(intel_plane, crtc_state);
14348 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
14351 mutex_unlock(&dev_priv->drm.struct_mutex);
14353 if (new_crtc_state)
14354 intel_crtc_destroy_state(crtc, &new_crtc_state->base);
14356 intel_plane_destroy_state(plane, new_plane_state);
14358 intel_plane_destroy_state(plane, old_plane_state);
14362 return drm_atomic_helper_update_plane(plane, crtc, fb,
14363 crtc_x, crtc_y, crtc_w, crtc_h,
14364 src_x, src_y, src_w, src_h, ctx);
14367 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
14368 .update_plane = intel_legacy_cursor_update,
14369 .disable_plane = drm_atomic_helper_disable_plane,
14370 .destroy = intel_plane_destroy,
14371 .atomic_get_property = intel_plane_atomic_get_property,
14372 .atomic_set_property = intel_plane_atomic_set_property,
14373 .atomic_duplicate_state = intel_plane_duplicate_state,
14374 .atomic_destroy_state = intel_plane_destroy_state,
14375 .format_mod_supported = intel_cursor_format_mod_supported,
14378 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
14379 enum i9xx_plane_id i9xx_plane)
14381 if (!HAS_FBC(dev_priv))
14384 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
14385 return i9xx_plane == PLANE_A; /* tied to pipe A */
14386 else if (IS_IVYBRIDGE(dev_priv))
14387 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
14388 i9xx_plane == PLANE_C;
14389 else if (INTEL_GEN(dev_priv) >= 4)
14390 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
14392 return i9xx_plane == PLANE_A;
14395 static struct intel_plane *
14396 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
14398 struct intel_plane *plane;
14399 const struct drm_plane_funcs *plane_funcs;
14400 unsigned int supported_rotations;
14401 unsigned int possible_crtcs;
14402 const u64 *modifiers;
14403 const u32 *formats;
14407 if (INTEL_GEN(dev_priv) >= 9)
14408 return skl_universal_plane_create(dev_priv, pipe,
14411 plane = intel_plane_alloc();
14415 plane->pipe = pipe;
14417 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14418 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14420 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
14421 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
14423 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
14424 plane->id = PLANE_PRIMARY;
14425 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
14427 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
14428 if (plane->has_fbc) {
14429 struct intel_fbc *fbc = &dev_priv->fbc;
14431 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
14434 if (INTEL_GEN(dev_priv) >= 4) {
14435 formats = i965_primary_formats;
14436 num_formats = ARRAY_SIZE(i965_primary_formats);
14437 modifiers = i9xx_format_modifiers;
14439 plane->max_stride = i9xx_plane_max_stride;
14440 plane->update_plane = i9xx_update_plane;
14441 plane->disable_plane = i9xx_disable_plane;
14442 plane->get_hw_state = i9xx_plane_get_hw_state;
14443 plane->check_plane = i9xx_plane_check;
14445 plane_funcs = &i965_plane_funcs;
14447 formats = i8xx_primary_formats;
14448 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14449 modifiers = i9xx_format_modifiers;
14451 plane->max_stride = i9xx_plane_max_stride;
14452 plane->update_plane = i9xx_update_plane;
14453 plane->disable_plane = i9xx_disable_plane;
14454 plane->get_hw_state = i9xx_plane_get_hw_state;
14455 plane->check_plane = i9xx_plane_check;
14457 plane_funcs = &i8xx_plane_funcs;
14460 possible_crtcs = BIT(pipe);
14462 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
14463 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
14464 possible_crtcs, plane_funcs,
14465 formats, num_formats, modifiers,
14466 DRM_PLANE_TYPE_PRIMARY,
14467 "primary %c", pipe_name(pipe));
14469 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
14470 possible_crtcs, plane_funcs,
14471 formats, num_formats, modifiers,
14472 DRM_PLANE_TYPE_PRIMARY,
14474 plane_name(plane->i9xx_plane));
14478 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
14479 supported_rotations =
14480 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
14481 DRM_MODE_REFLECT_X;
14482 } else if (INTEL_GEN(dev_priv) >= 4) {
14483 supported_rotations =
14484 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
14486 supported_rotations = DRM_MODE_ROTATE_0;
14489 if (INTEL_GEN(dev_priv) >= 4)
14490 drm_plane_create_rotation_property(&plane->base,
14492 supported_rotations);
14494 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
14499 intel_plane_free(plane);
14501 return ERR_PTR(ret);
14504 static struct intel_plane *
14505 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
14508 unsigned int possible_crtcs;
14509 struct intel_plane *cursor;
14512 cursor = intel_plane_alloc();
14513 if (IS_ERR(cursor))
14516 cursor->pipe = pipe;
14517 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
14518 cursor->id = PLANE_CURSOR;
14519 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
14521 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14522 cursor->max_stride = i845_cursor_max_stride;
14523 cursor->update_plane = i845_update_cursor;
14524 cursor->disable_plane = i845_disable_cursor;
14525 cursor->get_hw_state = i845_cursor_get_hw_state;
14526 cursor->check_plane = i845_check_cursor;
14528 cursor->max_stride = i9xx_cursor_max_stride;
14529 cursor->update_plane = i9xx_update_cursor;
14530 cursor->disable_plane = i9xx_disable_cursor;
14531 cursor->get_hw_state = i9xx_cursor_get_hw_state;
14532 cursor->check_plane = i9xx_check_cursor;
14535 cursor->cursor.base = ~0;
14536 cursor->cursor.cntl = ~0;
14538 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
14539 cursor->cursor.size = ~0;
14541 possible_crtcs = BIT(pipe);
14543 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
14544 possible_crtcs, &intel_cursor_plane_funcs,
14545 intel_cursor_formats,
14546 ARRAY_SIZE(intel_cursor_formats),
14547 cursor_format_modifiers,
14548 DRM_PLANE_TYPE_CURSOR,
14549 "cursor %c", pipe_name(pipe));
14553 if (INTEL_GEN(dev_priv) >= 4)
14554 drm_plane_create_rotation_property(&cursor->base,
14556 DRM_MODE_ROTATE_0 |
14557 DRM_MODE_ROTATE_180);
14559 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14564 intel_plane_free(cursor);
14566 return ERR_PTR(ret);
14569 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
14570 struct intel_crtc_state *crtc_state)
14572 struct intel_crtc_scaler_state *scaler_state =
14573 &crtc_state->scaler_state;
14574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14577 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
14578 if (!crtc->num_scalers)
14581 for (i = 0; i < crtc->num_scalers; i++) {
14582 struct intel_scaler *scaler = &scaler_state->scalers[i];
14584 scaler->in_use = 0;
14588 scaler_state->scaler_id = -1;
14591 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
14593 struct intel_crtc *intel_crtc;
14594 struct intel_crtc_state *crtc_state = NULL;
14595 struct intel_plane *primary = NULL;
14596 struct intel_plane *cursor = NULL;
14599 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14603 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14608 __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base);
14609 intel_crtc->config = crtc_state;
14611 primary = intel_primary_plane_create(dev_priv, pipe);
14612 if (IS_ERR(primary)) {
14613 ret = PTR_ERR(primary);
14616 intel_crtc->plane_ids_mask |= BIT(primary->id);
14618 for_each_sprite(dev_priv, pipe, sprite) {
14619 struct intel_plane *plane;
14621 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
14622 if (IS_ERR(plane)) {
14623 ret = PTR_ERR(plane);
14626 intel_crtc->plane_ids_mask |= BIT(plane->id);
14629 cursor = intel_cursor_plane_create(dev_priv, pipe);
14630 if (IS_ERR(cursor)) {
14631 ret = PTR_ERR(cursor);
14634 intel_crtc->plane_ids_mask |= BIT(cursor->id);
14636 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
14637 &primary->base, &cursor->base,
14639 "pipe %c", pipe_name(pipe));
14643 intel_crtc->pipe = pipe;
14645 /* initialize shared scalers */
14646 intel_crtc_init_scalers(intel_crtc, crtc_state);
14648 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
14649 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
14650 dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
14652 if (INTEL_GEN(dev_priv) < 9) {
14653 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
14655 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14656 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
14657 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
14660 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14662 intel_color_init(intel_crtc);
14664 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14670 * drm_mode_config_cleanup() will free up any
14671 * crtcs/planes already initialized.
14679 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
14680 struct drm_file *file)
14682 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14683 struct drm_crtc *drmmode_crtc;
14684 struct intel_crtc *crtc;
14686 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
14690 crtc = to_intel_crtc(drmmode_crtc);
14691 pipe_from_crtc_id->pipe = crtc->pipe;
14696 static int intel_encoder_clones(struct intel_encoder *encoder)
14698 struct drm_device *dev = encoder->base.dev;
14699 struct intel_encoder *source_encoder;
14700 int index_mask = 0;
14703 for_each_intel_encoder(dev, source_encoder) {
14704 if (encoders_cloneable(encoder, source_encoder))
14705 index_mask |= (1 << entry);
14713 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
14715 if (!IS_MOBILE(dev_priv))
14718 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14721 if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14727 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
14729 if (INTEL_GEN(dev_priv) >= 9)
14732 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14735 if (HAS_PCH_LPT_H(dev_priv) &&
14736 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14739 /* DDI E can't be used if DDI A requires 4 lanes */
14740 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14743 if (!dev_priv->vbt.int_crt_support)
14749 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14754 if (HAS_DDI(dev_priv))
14757 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14758 * everywhere where registers can be write protected.
14760 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14765 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14766 u32 val = I915_READ(PP_CONTROL(pps_idx));
14768 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14769 I915_WRITE(PP_CONTROL(pps_idx), val);
14773 static void intel_pps_init(struct drm_i915_private *dev_priv)
14775 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14776 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14777 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14778 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14780 dev_priv->pps_mmio_base = PPS_BASE;
14782 intel_pps_unlock_regs_wa(dev_priv);
14785 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14787 struct intel_encoder *encoder;
14788 bool dpd_is_edp = false;
14790 intel_pps_init(dev_priv);
14792 if (!HAS_DISPLAY(dev_priv))
14795 if (IS_ELKHARTLAKE(dev_priv)) {
14796 intel_ddi_init(dev_priv, PORT_A);
14797 intel_ddi_init(dev_priv, PORT_B);
14798 intel_ddi_init(dev_priv, PORT_C);
14799 icl_dsi_init(dev_priv);
14800 } else if (INTEL_GEN(dev_priv) >= 11) {
14801 intel_ddi_init(dev_priv, PORT_A);
14802 intel_ddi_init(dev_priv, PORT_B);
14803 intel_ddi_init(dev_priv, PORT_C);
14804 intel_ddi_init(dev_priv, PORT_D);
14805 intel_ddi_init(dev_priv, PORT_E);
14807 * On some ICL SKUs port F is not present. No strap bits for
14808 * this, so rely on VBT.
14809 * Work around broken VBTs on SKUs known to have no port F.
14811 if (IS_ICL_WITH_PORT_F(dev_priv) &&
14812 intel_bios_is_port_present(dev_priv, PORT_F))
14813 intel_ddi_init(dev_priv, PORT_F);
14815 icl_dsi_init(dev_priv);
14816 } else if (IS_GEN9_LP(dev_priv)) {
14818 * FIXME: Broxton doesn't support port detection via the
14819 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14820 * detect the ports.
14822 intel_ddi_init(dev_priv, PORT_A);
14823 intel_ddi_init(dev_priv, PORT_B);
14824 intel_ddi_init(dev_priv, PORT_C);
14826 vlv_dsi_init(dev_priv);
14827 } else if (HAS_DDI(dev_priv)) {
14830 if (intel_ddi_crt_present(dev_priv))
14831 intel_crt_init(dev_priv);
14834 * Haswell uses DDI functions to detect digital outputs.
14835 * On SKL pre-D0 the strap isn't connected, so we assume
14838 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14839 /* WaIgnoreDDIAStrap: skl */
14840 if (found || IS_GEN9_BC(dev_priv))
14841 intel_ddi_init(dev_priv, PORT_A);
14843 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14845 found = I915_READ(SFUSE_STRAP);
14847 if (found & SFUSE_STRAP_DDIB_DETECTED)
14848 intel_ddi_init(dev_priv, PORT_B);
14849 if (found & SFUSE_STRAP_DDIC_DETECTED)
14850 intel_ddi_init(dev_priv, PORT_C);
14851 if (found & SFUSE_STRAP_DDID_DETECTED)
14852 intel_ddi_init(dev_priv, PORT_D);
14853 if (found & SFUSE_STRAP_DDIF_DETECTED)
14854 intel_ddi_init(dev_priv, PORT_F);
14856 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14858 if (IS_GEN9_BC(dev_priv) &&
14859 intel_bios_is_port_present(dev_priv, PORT_E))
14860 intel_ddi_init(dev_priv, PORT_E);
14862 } else if (HAS_PCH_SPLIT(dev_priv)) {
14866 * intel_edp_init_connector() depends on this completing first,
14867 * to prevent the registration of both eDP and LVDS and the
14868 * incorrect sharing of the PPS.
14870 intel_lvds_init(dev_priv);
14871 intel_crt_init(dev_priv);
14873 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14875 if (ilk_has_edp_a(dev_priv))
14876 intel_dp_init(dev_priv, DP_A, PORT_A);
14878 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14879 /* PCH SDVOB multiplex with HDMIB */
14880 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14882 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14883 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14884 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14887 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14888 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14890 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14891 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14893 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14894 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14896 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14897 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14898 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14899 bool has_edp, has_port;
14901 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
14902 intel_crt_init(dev_priv);
14905 * The DP_DETECTED bit is the latched state of the DDC
14906 * SDA pin at boot. However since eDP doesn't require DDC
14907 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14908 * eDP ports may have been muxed to an alternate function.
14909 * Thus we can't rely on the DP_DETECTED bit alone to detect
14910 * eDP ports. Consult the VBT as well as DP_DETECTED to
14911 * detect eDP ports.
14913 * Sadly the straps seem to be missing sometimes even for HDMI
14914 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14915 * and VBT for the presence of the port. Additionally we can't
14916 * trust the port type the VBT declares as we've seen at least
14917 * HDMI ports that the VBT claim are DP or eDP.
14919 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14920 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14921 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14922 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14923 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14924 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14926 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14927 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14928 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14929 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14930 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14931 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14933 if (IS_CHERRYVIEW(dev_priv)) {
14935 * eDP not supported on port D,
14936 * so no need to worry about it
14938 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14939 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14940 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14941 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14942 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14945 vlv_dsi_init(dev_priv);
14946 } else if (IS_PINEVIEW(dev_priv)) {
14947 intel_lvds_init(dev_priv);
14948 intel_crt_init(dev_priv);
14949 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
14950 bool found = false;
14952 if (IS_MOBILE(dev_priv))
14953 intel_lvds_init(dev_priv);
14955 intel_crt_init(dev_priv);
14957 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14958 DRM_DEBUG_KMS("probing SDVOB\n");
14959 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14960 if (!found && IS_G4X(dev_priv)) {
14961 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14962 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14965 if (!found && IS_G4X(dev_priv))
14966 intel_dp_init(dev_priv, DP_B, PORT_B);
14969 /* Before G4X SDVOC doesn't have its own detect register */
14971 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14972 DRM_DEBUG_KMS("probing SDVOC\n");
14973 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14976 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14978 if (IS_G4X(dev_priv)) {
14979 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14980 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14982 if (IS_G4X(dev_priv))
14983 intel_dp_init(dev_priv, DP_C, PORT_C);
14986 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14987 intel_dp_init(dev_priv, DP_D, PORT_D);
14989 if (SUPPORTS_TV(dev_priv))
14990 intel_tv_init(dev_priv);
14991 } else if (IS_GEN(dev_priv, 2)) {
14992 if (IS_I85X(dev_priv))
14993 intel_lvds_init(dev_priv);
14995 intel_crt_init(dev_priv);
14996 intel_dvo_init(dev_priv);
14999 intel_psr_init(dev_priv);
15001 for_each_intel_encoder(&dev_priv->drm, encoder) {
15002 encoder->base.possible_crtcs = encoder->crtc_mask;
15003 encoder->base.possible_clones =
15004 intel_encoder_clones(encoder);
15007 intel_init_pch_refclk(dev_priv);
15009 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
15012 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15014 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15015 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15017 drm_framebuffer_cleanup(fb);
15019 i915_gem_object_lock(obj);
15020 WARN_ON(!obj->framebuffer_references--);
15021 i915_gem_object_unlock(obj);
15023 i915_gem_object_put(obj);
15028 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15029 struct drm_file *file,
15030 unsigned int *handle)
15032 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15034 if (obj->userptr.mm) {
15035 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15039 return drm_gem_handle_create(file, &obj->base, handle);
15042 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15043 struct drm_file *file,
15044 unsigned flags, unsigned color,
15045 struct drm_clip_rect *clips,
15046 unsigned num_clips)
15048 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15050 i915_gem_object_flush_if_display(obj);
15051 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
15056 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15057 .destroy = intel_user_framebuffer_destroy,
15058 .create_handle = intel_user_framebuffer_create_handle,
15059 .dirty = intel_user_framebuffer_dirty,
15063 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15064 u32 pixel_format, u64 fb_modifier)
15066 struct intel_crtc *crtc;
15067 struct intel_plane *plane;
15070 * We assume the primary plane for pipe A has
15071 * the highest stride limits of them all.
15073 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
15074 plane = to_intel_plane(crtc->base.primary);
15076 return plane->max_stride(plane, pixel_format, fb_modifier,
15077 DRM_MODE_ROTATE_0);
15080 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
15081 struct drm_i915_gem_object *obj,
15082 struct drm_mode_fb_cmd2 *mode_cmd)
15084 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
15085 struct drm_framebuffer *fb = &intel_fb->base;
15087 unsigned int tiling, stride;
15091 i915_gem_object_lock(obj);
15092 obj->framebuffer_references++;
15093 tiling = i915_gem_object_get_tiling(obj);
15094 stride = i915_gem_object_get_stride(obj);
15095 i915_gem_object_unlock(obj);
15097 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15099 * If there's a fence, enforce that
15100 * the fb modifier and tiling mode match.
15102 if (tiling != I915_TILING_NONE &&
15103 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15104 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
15108 if (tiling == I915_TILING_X) {
15109 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15110 } else if (tiling == I915_TILING_Y) {
15111 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
15116 if (!drm_any_plane_has_format(&dev_priv->drm,
15117 mode_cmd->pixel_format,
15118 mode_cmd->modifier[0])) {
15119 struct drm_format_name_buf format_name;
15121 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
15122 drm_get_format_name(mode_cmd->pixel_format,
15124 mode_cmd->modifier[0]);
15129 * gen2/3 display engine uses the fence if present,
15130 * so the tiling mode must match the fb modifier exactly.
15132 if (INTEL_GEN(dev_priv) < 4 &&
15133 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15134 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
15138 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
15139 mode_cmd->modifier[0]);
15140 if (mode_cmd->pitches[0] > pitch_limit) {
15141 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
15142 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
15143 "tiled" : "linear",
15144 mode_cmd->pitches[0], pitch_limit);
15149 * If there's a fence, enforce that
15150 * the fb pitch and fence stride match.
15152 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
15153 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
15154 mode_cmd->pitches[0], stride);
15158 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15159 if (mode_cmd->offsets[0] != 0)
15162 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
15164 for (i = 0; i < fb->format->num_planes; i++) {
15165 u32 stride_alignment;
15167 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
15168 DRM_DEBUG_KMS("bad plane %d handle\n", i);
15172 stride_alignment = intel_fb_stride_alignment(fb, i);
15175 * Display WA #0531: skl,bxt,kbl,glk
15177 * Render decompression and plane width > 3840
15178 * combined with horizontal panning requires the
15179 * plane stride to be a multiple of 4. We'll just
15180 * require the entire fb to accommodate that to avoid
15181 * potential runtime errors at plane configuration time.
15183 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
15184 is_ccs_modifier(fb->modifier))
15185 stride_alignment *= 4;
15187 if (fb->pitches[i] & (stride_alignment - 1)) {
15188 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
15189 i, fb->pitches[i], stride_alignment);
15193 fb->obj[i] = &obj->base;
15196 ret = intel_fill_fb_info(dev_priv, fb);
15200 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
15202 DRM_ERROR("framebuffer init failed %d\n", ret);
15209 i915_gem_object_lock(obj);
15210 obj->framebuffer_references--;
15211 i915_gem_object_unlock(obj);
15215 static struct drm_framebuffer *
15216 intel_user_framebuffer_create(struct drm_device *dev,
15217 struct drm_file *filp,
15218 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15220 struct drm_framebuffer *fb;
15221 struct drm_i915_gem_object *obj;
15222 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15224 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15226 return ERR_PTR(-ENOENT);
15228 fb = intel_framebuffer_create(obj, &mode_cmd);
15230 i915_gem_object_put(obj);
15235 static void intel_atomic_state_free(struct drm_atomic_state *state)
15237 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
15239 drm_atomic_state_default_release(state);
15241 i915_sw_fence_fini(&intel_state->commit_ready);
15246 static enum drm_mode_status
15247 intel_mode_valid(struct drm_device *dev,
15248 const struct drm_display_mode *mode)
15250 struct drm_i915_private *dev_priv = to_i915(dev);
15251 int hdisplay_max, htotal_max;
15252 int vdisplay_max, vtotal_max;
15255 * Can't reject DBLSCAN here because Xorg ddxen can add piles
15256 * of DBLSCAN modes to the output's mode list when they detect
15257 * the scaling mode property on the connector. And they don't
15258 * ask the kernel to validate those modes in any way until
15259 * modeset time at which point the client gets a protocol error.
15260 * So in order to not upset those clients we silently ignore the
15261 * DBLSCAN flag on such connectors. For other connectors we will
15262 * reject modes with the DBLSCAN flag in encoder->compute_config().
15263 * And we always reject DBLSCAN modes in connector->mode_valid()
15264 * as we never want such modes on the connector's mode list.
15267 if (mode->vscan > 1)
15268 return MODE_NO_VSCAN;
15270 if (mode->flags & DRM_MODE_FLAG_HSKEW)
15271 return MODE_H_ILLEGAL;
15273 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
15274 DRM_MODE_FLAG_NCSYNC |
15275 DRM_MODE_FLAG_PCSYNC))
15278 if (mode->flags & (DRM_MODE_FLAG_BCAST |
15279 DRM_MODE_FLAG_PIXMUX |
15280 DRM_MODE_FLAG_CLKDIV2))
15283 if (INTEL_GEN(dev_priv) >= 9 ||
15284 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
15285 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
15286 vdisplay_max = 4096;
15289 } else if (INTEL_GEN(dev_priv) >= 3) {
15290 hdisplay_max = 4096;
15291 vdisplay_max = 4096;
15295 hdisplay_max = 2048;
15296 vdisplay_max = 2048;
15301 if (mode->hdisplay > hdisplay_max ||
15302 mode->hsync_start > htotal_max ||
15303 mode->hsync_end > htotal_max ||
15304 mode->htotal > htotal_max)
15305 return MODE_H_ILLEGAL;
15307 if (mode->vdisplay > vdisplay_max ||
15308 mode->vsync_start > vtotal_max ||
15309 mode->vsync_end > vtotal_max ||
15310 mode->vtotal > vtotal_max)
15311 return MODE_V_ILLEGAL;
15316 static const struct drm_mode_config_funcs intel_mode_funcs = {
15317 .fb_create = intel_user_framebuffer_create,
15318 .get_format_info = intel_get_format_info,
15319 .output_poll_changed = intel_fbdev_output_poll_changed,
15320 .mode_valid = intel_mode_valid,
15321 .atomic_check = intel_atomic_check,
15322 .atomic_commit = intel_atomic_commit,
15323 .atomic_state_alloc = intel_atomic_state_alloc,
15324 .atomic_state_clear = intel_atomic_state_clear,
15325 .atomic_state_free = intel_atomic_state_free,
15329 * intel_init_display_hooks - initialize the display modesetting hooks
15330 * @dev_priv: device private
15332 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15334 intel_init_cdclk_hooks(dev_priv);
15336 if (INTEL_GEN(dev_priv) >= 9) {
15337 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15338 dev_priv->display.get_initial_plane_config =
15339 skylake_get_initial_plane_config;
15340 dev_priv->display.crtc_compute_clock =
15341 haswell_crtc_compute_clock;
15342 dev_priv->display.crtc_enable = haswell_crtc_enable;
15343 dev_priv->display.crtc_disable = haswell_crtc_disable;
15344 } else if (HAS_DDI(dev_priv)) {
15345 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15346 dev_priv->display.get_initial_plane_config =
15347 i9xx_get_initial_plane_config;
15348 dev_priv->display.crtc_compute_clock =
15349 haswell_crtc_compute_clock;
15350 dev_priv->display.crtc_enable = haswell_crtc_enable;
15351 dev_priv->display.crtc_disable = haswell_crtc_disable;
15352 } else if (HAS_PCH_SPLIT(dev_priv)) {
15353 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15354 dev_priv->display.get_initial_plane_config =
15355 i9xx_get_initial_plane_config;
15356 dev_priv->display.crtc_compute_clock =
15357 ironlake_crtc_compute_clock;
15358 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15359 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15360 } else if (IS_CHERRYVIEW(dev_priv)) {
15361 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15362 dev_priv->display.get_initial_plane_config =
15363 i9xx_get_initial_plane_config;
15364 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15365 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15366 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15367 } else if (IS_VALLEYVIEW(dev_priv)) {
15368 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15369 dev_priv->display.get_initial_plane_config =
15370 i9xx_get_initial_plane_config;
15371 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15372 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15373 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15374 } else if (IS_G4X(dev_priv)) {
15375 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15376 dev_priv->display.get_initial_plane_config =
15377 i9xx_get_initial_plane_config;
15378 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15379 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15380 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15381 } else if (IS_PINEVIEW(dev_priv)) {
15382 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15383 dev_priv->display.get_initial_plane_config =
15384 i9xx_get_initial_plane_config;
15385 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15386 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15387 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15388 } else if (!IS_GEN(dev_priv, 2)) {
15389 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15390 dev_priv->display.get_initial_plane_config =
15391 i9xx_get_initial_plane_config;
15392 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15393 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15394 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15396 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15397 dev_priv->display.get_initial_plane_config =
15398 i9xx_get_initial_plane_config;
15399 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15400 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15401 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15404 if (IS_GEN(dev_priv, 5)) {
15405 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15406 } else if (IS_GEN(dev_priv, 6)) {
15407 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15408 } else if (IS_IVYBRIDGE(dev_priv)) {
15409 /* FIXME: detect B0+ stepping and use auto training */
15410 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15411 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15412 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15415 if (INTEL_GEN(dev_priv) >= 9)
15416 dev_priv->display.update_crtcs = skl_update_crtcs;
15418 dev_priv->display.update_crtcs = intel_update_crtcs;
15421 /* Disable the VGA plane that we never use */
15422 static void i915_disable_vga(struct drm_i915_private *dev_priv)
15424 struct pci_dev *pdev = dev_priv->drm.pdev;
15426 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15428 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15429 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
15430 outb(SR01, VGA_SR_INDEX);
15431 sr1 = inb(VGA_SR_DATA);
15432 outb(sr1 | 1<<5, VGA_SR_DATA);
15433 vga_put(pdev, VGA_RSRC_LEGACY_IO);
15436 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15437 POSTING_READ(vga_reg);
15440 void intel_modeset_init_hw(struct drm_device *dev)
15442 struct drm_i915_private *dev_priv = to_i915(dev);
15444 intel_update_cdclk(dev_priv);
15445 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
15446 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
15450 * Calculate what we think the watermarks should be for the state we've read
15451 * out of the hardware and then immediately program those watermarks so that
15452 * we ensure the hardware settings match our internal state.
15454 * We can calculate what we think WM's should be by creating a duplicate of the
15455 * current state (which was constructed during hardware readout) and running it
15456 * through the atomic check code to calculate new watermark values in the
15459 static void sanitize_watermarks(struct drm_device *dev)
15461 struct drm_i915_private *dev_priv = to_i915(dev);
15462 struct drm_atomic_state *state;
15463 struct intel_atomic_state *intel_state;
15464 struct drm_crtc *crtc;
15465 struct drm_crtc_state *cstate;
15466 struct drm_modeset_acquire_ctx ctx;
15470 /* Only supported on platforms that use atomic watermark design */
15471 if (!dev_priv->display.optimize_watermarks)
15475 * We need to hold connection_mutex before calling duplicate_state so
15476 * that the connector loop is protected.
15478 drm_modeset_acquire_init(&ctx, 0);
15480 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15481 if (ret == -EDEADLK) {
15482 drm_modeset_backoff(&ctx);
15484 } else if (WARN_ON(ret)) {
15488 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15489 if (WARN_ON(IS_ERR(state)))
15492 intel_state = to_intel_atomic_state(state);
15495 * Hardware readout is the only time we don't want to calculate
15496 * intermediate watermarks (since we don't trust the current
15499 if (!HAS_GMCH(dev_priv))
15500 intel_state->skip_intermediate_wm = true;
15502 ret = intel_atomic_check(dev, state);
15505 * If we fail here, it means that the hardware appears to be
15506 * programmed in a way that shouldn't be possible, given our
15507 * understanding of watermark requirements. This might mean a
15508 * mistake in the hardware readout code or a mistake in the
15509 * watermark calculations for a given platform. Raise a WARN
15510 * so that this is noticeable.
15512 * If this actually happens, we'll have to just leave the
15513 * BIOS-programmed watermarks untouched and hope for the best.
15515 WARN(true, "Could not determine valid watermarks for inherited state\n");
15519 /* Write calculated watermark values back */
15520 for_each_new_crtc_in_state(state, crtc, cstate, i) {
15521 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15523 cs->wm.need_postvbl_update = true;
15524 dev_priv->display.optimize_watermarks(intel_state, cs);
15526 to_intel_crtc_state(crtc->state)->wm = cs->wm;
15530 drm_atomic_state_put(state);
15532 drm_modeset_drop_locks(&ctx);
15533 drm_modeset_acquire_fini(&ctx);
15536 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
15538 if (IS_GEN(dev_priv, 5)) {
15540 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
15542 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
15543 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
15544 dev_priv->fdi_pll_freq = 270000;
15549 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
15552 static int intel_initial_commit(struct drm_device *dev)
15554 struct drm_atomic_state *state = NULL;
15555 struct drm_modeset_acquire_ctx ctx;
15556 struct drm_crtc *crtc;
15557 struct drm_crtc_state *crtc_state;
15560 state = drm_atomic_state_alloc(dev);
15564 drm_modeset_acquire_init(&ctx, 0);
15567 state->acquire_ctx = &ctx;
15569 drm_for_each_crtc(crtc, dev) {
15570 crtc_state = drm_atomic_get_crtc_state(state, crtc);
15571 if (IS_ERR(crtc_state)) {
15572 ret = PTR_ERR(crtc_state);
15576 if (crtc_state->active) {
15577 ret = drm_atomic_add_affected_planes(state, crtc);
15582 * FIXME hack to force a LUT update to avoid the
15583 * plane update forcing the pipe gamma on without
15584 * having a proper LUT loaded. Remove once we
15585 * have readout for pipe gamma enable.
15587 crtc_state->color_mgmt_changed = true;
15591 ret = drm_atomic_commit(state);
15594 if (ret == -EDEADLK) {
15595 drm_atomic_state_clear(state);
15596 drm_modeset_backoff(&ctx);
15600 drm_atomic_state_put(state);
15602 drm_modeset_drop_locks(&ctx);
15603 drm_modeset_acquire_fini(&ctx);
15608 int intel_modeset_init(struct drm_device *dev)
15610 struct drm_i915_private *dev_priv = to_i915(dev);
15611 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15613 struct intel_crtc *crtc;
15616 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
15618 drm_mode_config_init(dev);
15620 dev->mode_config.min_width = 0;
15621 dev->mode_config.min_height = 0;
15623 dev->mode_config.preferred_depth = 24;
15624 dev->mode_config.prefer_shadow = 1;
15626 dev->mode_config.allow_fb_modifiers = true;
15628 dev->mode_config.funcs = &intel_mode_funcs;
15630 init_llist_head(&dev_priv->atomic_helper.free_list);
15631 INIT_WORK(&dev_priv->atomic_helper.free_work,
15632 intel_atomic_helper_free_state_worker);
15634 intel_init_quirks(dev_priv);
15636 intel_fbc_init(dev_priv);
15638 intel_init_pm(dev_priv);
15641 * There may be no VBT; and if the BIOS enabled SSC we can
15642 * just keep using it to avoid unnecessary flicker. Whereas if the
15643 * BIOS isn't using it, don't assume it will work even if the VBT
15644 * indicates as much.
15646 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15647 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15650 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15651 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15652 bios_lvds_use_ssc ? "en" : "dis",
15653 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15654 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15658 /* maximum framebuffer dimensions */
15659 if (IS_GEN(dev_priv, 2)) {
15660 dev->mode_config.max_width = 2048;
15661 dev->mode_config.max_height = 2048;
15662 } else if (IS_GEN(dev_priv, 3)) {
15663 dev->mode_config.max_width = 4096;
15664 dev->mode_config.max_height = 4096;
15666 dev->mode_config.max_width = 8192;
15667 dev->mode_config.max_height = 8192;
15670 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15671 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15672 dev->mode_config.cursor_height = 1023;
15673 } else if (IS_GEN(dev_priv, 2)) {
15674 dev->mode_config.cursor_width = 64;
15675 dev->mode_config.cursor_height = 64;
15677 dev->mode_config.cursor_width = 256;
15678 dev->mode_config.cursor_height = 256;
15681 dev->mode_config.fb_base = ggtt->gmadr.start;
15683 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15684 INTEL_INFO(dev_priv)->num_pipes,
15685 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15687 for_each_pipe(dev_priv, pipe) {
15688 ret = intel_crtc_init(dev_priv, pipe);
15690 drm_mode_config_cleanup(dev);
15695 intel_shared_dpll_init(dev);
15696 intel_update_fdi_pll_freq(dev_priv);
15698 intel_update_czclk(dev_priv);
15699 intel_modeset_init_hw(dev);
15701 intel_hdcp_component_init(dev_priv);
15703 if (dev_priv->max_cdclk_freq == 0)
15704 intel_update_max_cdclk(dev_priv);
15706 /* Just disable it once at startup */
15707 i915_disable_vga(dev_priv);
15708 intel_setup_outputs(dev_priv);
15710 drm_modeset_lock_all(dev);
15711 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15712 drm_modeset_unlock_all(dev);
15714 for_each_intel_crtc(dev, crtc) {
15715 struct intel_initial_plane_config plane_config = {};
15721 * Note that reserving the BIOS fb up front prevents us
15722 * from stuffing other stolen allocations like the ring
15723 * on top. This prevents some ugliness at boot time, and
15724 * can even allow for smooth boot transitions if the BIOS
15725 * fb is large enough for the active pipe configuration.
15727 dev_priv->display.get_initial_plane_config(crtc,
15731 * If the fb is shared between multiple heads, we'll
15732 * just get the first one.
15734 intel_find_initial_plane_obj(crtc, &plane_config);
15738 * Make sure hardware watermarks really match the state we read out.
15739 * Note that we need to do this after reconstructing the BIOS fb's
15740 * since the watermark calculation done here will use pstate->fb.
15742 if (!HAS_GMCH(dev_priv))
15743 sanitize_watermarks(dev);
15746 * Force all active planes to recompute their states. So that on
15747 * mode_setcrtc after probe, all the intel_plane_state variables
15748 * are already calculated and there is no assert_plane warnings
15751 ret = intel_initial_commit(dev);
15753 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
15758 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15760 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15761 /* 640x480@60Hz, ~25175 kHz */
15762 struct dpll clock = {
15772 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15774 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15775 pipe_name(pipe), clock.vco, clock.dot);
15777 fp = i9xx_dpll_compute_fp(&clock);
15778 dpll = DPLL_DVO_2X_MODE |
15779 DPLL_VGA_MODE_DIS |
15780 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15781 PLL_P2_DIVIDE_BY_4 |
15782 PLL_REF_INPUT_DREFCLK |
15785 I915_WRITE(FP0(pipe), fp);
15786 I915_WRITE(FP1(pipe), fp);
15788 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15789 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15790 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15791 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15792 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15793 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15794 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15797 * Apparently we need to have VGA mode enabled prior to changing
15798 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15799 * dividers, even though the register value does change.
15801 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15802 I915_WRITE(DPLL(pipe), dpll);
15804 /* Wait for the clocks to stabilize. */
15805 POSTING_READ(DPLL(pipe));
15808 /* The pixel multiplier can only be updated once the
15809 * DPLL is enabled and the clocks are stable.
15811 * So write it again.
15813 I915_WRITE(DPLL(pipe), dpll);
15815 /* We do this three times for luck */
15816 for (i = 0; i < 3 ; i++) {
15817 I915_WRITE(DPLL(pipe), dpll);
15818 POSTING_READ(DPLL(pipe));
15819 udelay(150); /* wait for warmup */
15822 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15823 POSTING_READ(PIPECONF(pipe));
15825 intel_wait_for_pipe_scanline_moving(crtc);
15828 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15830 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15832 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15835 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
15836 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
15837 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
15838 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
15839 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
15841 I915_WRITE(PIPECONF(pipe), 0);
15842 POSTING_READ(PIPECONF(pipe));
15844 intel_wait_for_pipe_scanline_stopped(crtc);
15846 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15847 POSTING_READ(DPLL(pipe));
15851 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15853 struct intel_crtc *crtc;
15855 if (INTEL_GEN(dev_priv) >= 4)
15858 for_each_intel_crtc(&dev_priv->drm, crtc) {
15859 struct intel_plane *plane =
15860 to_intel_plane(crtc->base.primary);
15861 struct intel_crtc *plane_crtc;
15864 if (!plane->get_hw_state(plane, &pipe))
15867 if (pipe == crtc->pipe)
15870 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
15871 plane->base.base.id, plane->base.name);
15873 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15874 intel_plane_disable_noatomic(plane_crtc, plane);
15878 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15880 struct drm_device *dev = crtc->base.dev;
15881 struct intel_encoder *encoder;
15883 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15889 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15891 struct drm_device *dev = encoder->base.dev;
15892 struct intel_connector *connector;
15894 for_each_connector_on_encoder(dev, &encoder->base, connector)
15900 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15901 enum pipe pch_transcoder)
15903 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15904 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15907 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15908 struct drm_modeset_acquire_ctx *ctx)
15910 struct drm_device *dev = crtc->base.dev;
15911 struct drm_i915_private *dev_priv = to_i915(dev);
15912 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
15913 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
15915 /* Clear any frame start delays used for debugging left by the BIOS */
15916 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15917 i915_reg_t reg = PIPECONF(cpu_transcoder);
15920 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15923 if (crtc_state->base.active) {
15924 struct intel_plane *plane;
15926 /* Disable everything but the primary plane */
15927 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15928 const struct intel_plane_state *plane_state =
15929 to_intel_plane_state(plane->base.state);
15931 if (plane_state->base.visible &&
15932 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15933 intel_plane_disable_noatomic(crtc, plane);
15937 * Disable any background color set by the BIOS, but enable the
15938 * gamma and CSC to match how we program our planes.
15940 if (INTEL_GEN(dev_priv) >= 9)
15941 I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
15942 SKL_BOTTOM_COLOR_GAMMA_ENABLE |
15943 SKL_BOTTOM_COLOR_CSC_ENABLE);
15946 /* Adjust the state of the output pipe according to whether we
15947 * have active connectors/encoders. */
15948 if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
15949 intel_crtc_disable_noatomic(&crtc->base, ctx);
15951 if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
15953 * We start out with underrun reporting disabled to avoid races.
15954 * For correct bookkeeping mark this on active crtcs.
15956 * Also on gmch platforms we dont have any hardware bits to
15957 * disable the underrun reporting. Which means we need to start
15958 * out with underrun reporting disabled also on inactive pipes,
15959 * since otherwise we'll complain about the garbage we read when
15960 * e.g. coming up after runtime pm.
15962 * No protection against concurrent access is required - at
15963 * worst a fifo underrun happens which also sets this to false.
15965 crtc->cpu_fifo_underrun_disabled = true;
15967 * We track the PCH trancoder underrun reporting state
15968 * within the crtc. With crtc for pipe A housing the underrun
15969 * reporting state for PCH transcoder A, crtc for pipe B housing
15970 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15971 * and marking underrun reporting as disabled for the non-existing
15972 * PCH transcoders B and C would prevent enabling the south
15973 * error interrupt (see cpt_can_enable_serr_int()).
15975 if (has_pch_trancoder(dev_priv, crtc->pipe))
15976 crtc->pch_fifo_underrun_disabled = true;
15980 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
15982 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
15985 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
15986 * the hardware when a high res displays plugged in. DPLL P
15987 * divider is zero, and the pipe timings are bonkers. We'll
15988 * try to disable everything in that case.
15990 * FIXME would be nice to be able to sanitize this state
15991 * without several WARNs, but for now let's take the easy
15994 return IS_GEN(dev_priv, 6) &&
15995 crtc_state->base.active &&
15996 crtc_state->shared_dpll &&
15997 crtc_state->port_clock == 0;
16000 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
16003 struct intel_connector *connector;
16004 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
16005 struct intel_crtc_state *crtc_state = crtc ?
16006 to_intel_crtc_state(crtc->base.state) : NULL;
16008 /* We need to check both for a crtc link (meaning that the
16009 * encoder is active and trying to read from a pipe) and the
16010 * pipe itself being active. */
16011 bool has_active_crtc = crtc_state &&
16012 crtc_state->base.active;
16014 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
16015 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
16016 pipe_name(crtc->pipe));
16017 has_active_crtc = false;
16020 connector = intel_encoder_find_connector(encoder);
16021 if (connector && !has_active_crtc) {
16022 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16023 encoder->base.base.id,
16024 encoder->base.name);
16026 /* Connector is active, but has no active pipe. This is
16027 * fallout from our resume register restoring. Disable
16028 * the encoder manually again. */
16030 struct drm_encoder *best_encoder;
16032 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16033 encoder->base.base.id,
16034 encoder->base.name);
16036 /* avoid oopsing in case the hooks consult best_encoder */
16037 best_encoder = connector->base.state->best_encoder;
16038 connector->base.state->best_encoder = &encoder->base;
16040 if (encoder->disable)
16041 encoder->disable(encoder, crtc_state,
16042 connector->base.state);
16043 if (encoder->post_disable)
16044 encoder->post_disable(encoder, crtc_state,
16045 connector->base.state);
16047 connector->base.state->best_encoder = best_encoder;
16049 encoder->base.crtc = NULL;
16051 /* Inconsistent output/port/pipe state happens presumably due to
16052 * a bug in one of the get_hw_state functions. Or someplace else
16053 * in our code, like the register restore mess on resume. Clamp
16054 * things to off as a safer default. */
16056 connector->base.dpms = DRM_MODE_DPMS_OFF;
16057 connector->base.encoder = NULL;
16060 /* notify opregion of the sanitized encoder state */
16061 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
16063 if (INTEL_GEN(dev_priv) >= 11)
16064 icl_sanitize_encoder_pll_mapping(encoder);
16067 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16069 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16071 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16072 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16073 i915_disable_vga(dev_priv);
16077 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16079 intel_wakeref_t wakeref;
16082 * This function can be called both from intel_modeset_setup_hw_state or
16083 * at a very early point in our resume sequence, where the power well
16084 * structures are not yet restored. Since this function is at a very
16085 * paranoid "someone might have enabled VGA while we were not looking"
16086 * level, just check if the power well is enabled instead of trying to
16087 * follow the "don't touch the power well if we don't need it" policy
16088 * the rest of the driver uses.
16090 wakeref = intel_display_power_get_if_enabled(dev_priv,
16095 i915_redisable_vga_power_on(dev_priv);
16097 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA, wakeref);
16100 /* FIXME read out full plane state for all planes */
16101 static void readout_plane_state(struct drm_i915_private *dev_priv)
16103 struct intel_plane *plane;
16104 struct intel_crtc *crtc;
16106 for_each_intel_plane(&dev_priv->drm, plane) {
16107 struct intel_plane_state *plane_state =
16108 to_intel_plane_state(plane->base.state);
16109 struct intel_crtc_state *crtc_state;
16110 enum pipe pipe = PIPE_A;
16113 visible = plane->get_hw_state(plane, &pipe);
16115 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16116 crtc_state = to_intel_crtc_state(crtc->base.state);
16118 intel_set_plane_visible(crtc_state, plane_state, visible);
16120 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
16121 plane->base.base.id, plane->base.name,
16122 enableddisabled(visible), pipe_name(pipe));
16125 for_each_intel_crtc(&dev_priv->drm, crtc) {
16126 struct intel_crtc_state *crtc_state =
16127 to_intel_crtc_state(crtc->base.state);
16129 fixup_active_planes(crtc_state);
16133 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16135 struct drm_i915_private *dev_priv = to_i915(dev);
16137 struct intel_crtc *crtc;
16138 struct intel_encoder *encoder;
16139 struct intel_connector *connector;
16140 struct drm_connector_list_iter conn_iter;
16143 dev_priv->active_crtcs = 0;
16145 for_each_intel_crtc(dev, crtc) {
16146 struct intel_crtc_state *crtc_state =
16147 to_intel_crtc_state(crtc->base.state);
16149 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16150 memset(crtc_state, 0, sizeof(*crtc_state));
16151 __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
16153 crtc_state->base.active = crtc_state->base.enable =
16154 dev_priv->display.get_pipe_config(crtc, crtc_state);
16156 crtc->base.enabled = crtc_state->base.enable;
16157 crtc->active = crtc_state->base.active;
16159 if (crtc_state->base.active)
16160 dev_priv->active_crtcs |= 1 << crtc->pipe;
16162 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16163 crtc->base.base.id, crtc->base.name,
16164 enableddisabled(crtc_state->base.active));
16167 readout_plane_state(dev_priv);
16169 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16170 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16172 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
16173 &pll->state.hw_state);
16174 pll->state.crtc_mask = 0;
16175 for_each_intel_crtc(dev, crtc) {
16176 struct intel_crtc_state *crtc_state =
16177 to_intel_crtc_state(crtc->base.state);
16179 if (crtc_state->base.active &&
16180 crtc_state->shared_dpll == pll)
16181 pll->state.crtc_mask |= 1 << crtc->pipe;
16183 pll->active_mask = pll->state.crtc_mask;
16185 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16186 pll->info->name, pll->state.crtc_mask, pll->on);
16189 for_each_intel_encoder(dev, encoder) {
16192 if (encoder->get_hw_state(encoder, &pipe)) {
16193 struct intel_crtc_state *crtc_state;
16195 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16196 crtc_state = to_intel_crtc_state(crtc->base.state);
16198 encoder->base.crtc = &crtc->base;
16199 encoder->get_config(encoder, crtc_state);
16201 encoder->base.crtc = NULL;
16204 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16205 encoder->base.base.id, encoder->base.name,
16206 enableddisabled(encoder->base.crtc),
16210 drm_connector_list_iter_begin(dev, &conn_iter);
16211 for_each_intel_connector_iter(connector, &conn_iter) {
16212 if (connector->get_hw_state(connector)) {
16213 connector->base.dpms = DRM_MODE_DPMS_ON;
16215 encoder = connector->encoder;
16216 connector->base.encoder = &encoder->base;
16218 if (encoder->base.crtc &&
16219 encoder->base.crtc->state->active) {
16221 * This has to be done during hardware readout
16222 * because anything calling .crtc_disable may
16223 * rely on the connector_mask being accurate.
16225 encoder->base.crtc->state->connector_mask |=
16226 drm_connector_mask(&connector->base);
16227 encoder->base.crtc->state->encoder_mask |=
16228 drm_encoder_mask(&encoder->base);
16232 connector->base.dpms = DRM_MODE_DPMS_OFF;
16233 connector->base.encoder = NULL;
16235 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16236 connector->base.base.id, connector->base.name,
16237 enableddisabled(connector->base.encoder));
16239 drm_connector_list_iter_end(&conn_iter);
16241 for_each_intel_crtc(dev, crtc) {
16242 struct intel_crtc_state *crtc_state =
16243 to_intel_crtc_state(crtc->base.state);
16246 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16247 if (crtc_state->base.active) {
16248 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
16249 crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
16250 crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
16251 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
16252 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16255 * The initial mode needs to be set in order to keep
16256 * the atomic core happy. It wants a valid mode if the
16257 * crtc's enabled, so we do the above call.
16259 * But we don't set all the derived state fully, hence
16260 * set a flag to indicate that a full recalculation is
16261 * needed on the next commit.
16263 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
16265 intel_crtc_compute_pixel_rate(crtc_state);
16267 if (dev_priv->display.modeset_calc_cdclk) {
16268 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
16269 if (WARN_ON(min_cdclk < 0))
16273 drm_calc_timestamping_constants(&crtc->base,
16274 &crtc_state->base.adjusted_mode);
16275 update_scanline_offset(crtc_state);
16278 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
16279 dev_priv->min_voltage_level[crtc->pipe] =
16280 crtc_state->min_voltage_level;
16282 intel_pipe_config_sanity_check(dev_priv, crtc_state);
16287 get_encoder_power_domains(struct drm_i915_private *dev_priv)
16289 struct intel_encoder *encoder;
16291 for_each_intel_encoder(&dev_priv->drm, encoder) {
16292 struct intel_crtc_state *crtc_state;
16294 if (!encoder->get_power_domains)
16298 * MST-primary and inactive encoders don't have a crtc state
16299 * and neither of these require any power domain references.
16301 if (!encoder->base.crtc)
16304 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
16305 encoder->get_power_domains(encoder, crtc_state);
16309 static void intel_early_display_was(struct drm_i915_private *dev_priv)
16311 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
16312 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
16313 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
16316 if (IS_HASWELL(dev_priv)) {
16318 * WaRsPkgCStateDisplayPMReq:hsw
16319 * System hang if this isn't done before disabling all planes!
16321 I915_WRITE(CHICKEN_PAR1_1,
16322 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
16326 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
16327 enum port port, i915_reg_t hdmi_reg)
16329 u32 val = I915_READ(hdmi_reg);
16331 if (val & SDVO_ENABLE ||
16332 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
16335 DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
16338 val &= ~SDVO_PIPE_SEL_MASK;
16339 val |= SDVO_PIPE_SEL(PIPE_A);
16341 I915_WRITE(hdmi_reg, val);
16344 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
16345 enum port port, i915_reg_t dp_reg)
16347 u32 val = I915_READ(dp_reg);
16349 if (val & DP_PORT_EN ||
16350 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
16353 DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
16356 val &= ~DP_PIPE_SEL_MASK;
16357 val |= DP_PIPE_SEL(PIPE_A);
16359 I915_WRITE(dp_reg, val);
16362 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
16365 * The BIOS may select transcoder B on some of the PCH
16366 * ports even it doesn't enable the port. This would trip
16367 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
16368 * Sanitize the transcoder select bits to prevent that. We
16369 * assume that the BIOS never actually enabled the port,
16370 * because if it did we'd actually have to toggle the port
16371 * on and back off to make the transcoder A select stick
16372 * (see. intel_dp_link_down(), intel_disable_hdmi(),
16373 * intel_disable_sdvo()).
16375 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
16376 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
16377 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
16379 /* PCH SDVOB multiplex with HDMIB */
16380 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
16381 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
16382 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
16385 /* Scan out the current hw modeset state,
16386 * and sanitizes it to the current state
16389 intel_modeset_setup_hw_state(struct drm_device *dev,
16390 struct drm_modeset_acquire_ctx *ctx)
16392 struct drm_i915_private *dev_priv = to_i915(dev);
16393 struct intel_crtc_state *crtc_state;
16394 struct intel_encoder *encoder;
16395 struct intel_crtc *crtc;
16396 intel_wakeref_t wakeref;
16399 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
16401 intel_early_display_was(dev_priv);
16402 intel_modeset_readout_hw_state(dev);
16404 /* HW state is read out, now we need to sanitize this mess. */
16405 get_encoder_power_domains(dev_priv);
16407 if (HAS_PCH_IBX(dev_priv))
16408 ibx_sanitize_pch_ports(dev_priv);
16411 * intel_sanitize_plane_mapping() may need to do vblank
16412 * waits, so we need vblank interrupts restored beforehand.
16414 for_each_intel_crtc(&dev_priv->drm, crtc) {
16415 crtc_state = to_intel_crtc_state(crtc->base.state);
16417 drm_crtc_vblank_reset(&crtc->base);
16419 if (crtc_state->base.active)
16420 intel_crtc_vblank_on(crtc_state);
16423 intel_sanitize_plane_mapping(dev_priv);
16425 for_each_intel_encoder(dev, encoder)
16426 intel_sanitize_encoder(encoder);
16428 for_each_intel_crtc(&dev_priv->drm, crtc) {
16429 crtc_state = to_intel_crtc_state(crtc->base.state);
16430 intel_sanitize_crtc(crtc, ctx);
16431 intel_dump_pipe_config(crtc, crtc_state,
16432 "[setup_hw_state]");
16435 intel_modeset_update_connector_atomic_state(dev);
16437 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16438 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16440 if (!pll->on || pll->active_mask)
16443 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
16446 pll->info->funcs->disable(dev_priv, pll);
16450 if (IS_G4X(dev_priv)) {
16451 g4x_wm_get_hw_state(dev_priv);
16452 g4x_wm_sanitize(dev_priv);
16453 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16454 vlv_wm_get_hw_state(dev_priv);
16455 vlv_wm_sanitize(dev_priv);
16456 } else if (INTEL_GEN(dev_priv) >= 9) {
16457 skl_wm_get_hw_state(dev_priv);
16458 } else if (HAS_PCH_SPLIT(dev_priv)) {
16459 ilk_wm_get_hw_state(dev_priv);
16462 for_each_intel_crtc(dev, crtc) {
16465 crtc_state = to_intel_crtc_state(crtc->base.state);
16466 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc_state);
16467 if (WARN_ON(put_domains))
16468 modeset_put_power_domains(dev_priv, put_domains);
16471 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
16473 intel_fbc_init_pipe_state(dev_priv);
16476 void intel_display_resume(struct drm_device *dev)
16478 struct drm_i915_private *dev_priv = to_i915(dev);
16479 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16480 struct drm_modeset_acquire_ctx ctx;
16483 dev_priv->modeset_restore_state = NULL;
16485 state->acquire_ctx = &ctx;
16487 drm_modeset_acquire_init(&ctx, 0);
16490 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16491 if (ret != -EDEADLK)
16494 drm_modeset_backoff(&ctx);
16498 ret = __intel_display_resume(dev, state, &ctx);
16500 intel_enable_ipc(dev_priv);
16501 drm_modeset_drop_locks(&ctx);
16502 drm_modeset_acquire_fini(&ctx);
16505 DRM_ERROR("Restoring old state failed with %i\n", ret);
16507 drm_atomic_state_put(state);
16510 static void intel_hpd_poll_fini(struct drm_device *dev)
16512 struct intel_connector *connector;
16513 struct drm_connector_list_iter conn_iter;
16515 /* Kill all the work that may have been queued by hpd. */
16516 drm_connector_list_iter_begin(dev, &conn_iter);
16517 for_each_intel_connector_iter(connector, &conn_iter) {
16518 if (connector->modeset_retry_work.func)
16519 cancel_work_sync(&connector->modeset_retry_work);
16520 if (connector->hdcp.shim) {
16521 cancel_delayed_work_sync(&connector->hdcp.check_work);
16522 cancel_work_sync(&connector->hdcp.prop_work);
16525 drm_connector_list_iter_end(&conn_iter);
16528 void intel_modeset_cleanup(struct drm_device *dev)
16530 struct drm_i915_private *dev_priv = to_i915(dev);
16532 flush_workqueue(dev_priv->modeset_wq);
16534 flush_work(&dev_priv->atomic_helper.free_work);
16535 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
16538 * Interrupts and polling as the first thing to avoid creating havoc.
16539 * Too much stuff here (turning of connectors, ...) would
16540 * experience fancy races otherwise.
16542 intel_irq_uninstall(dev_priv);
16545 * Due to the hpd irq storm handling the hotplug work can re-arm the
16546 * poll handlers. Hence disable polling after hpd handling is shut down.
16548 intel_hpd_poll_fini(dev);
16550 /* poll work can call into fbdev, hence clean that up afterwards */
16551 intel_fbdev_fini(dev_priv);
16553 intel_unregister_dsm_handler();
16555 intel_fbc_global_disable(dev_priv);
16557 /* flush any delayed tasks or pending work */
16558 flush_scheduled_work();
16560 intel_hdcp_component_fini(dev_priv);
16562 drm_mode_config_cleanup(dev);
16564 intel_overlay_cleanup(dev_priv);
16566 intel_teardown_gmbus(dev_priv);
16568 destroy_workqueue(dev_priv->modeset_wq);
16570 intel_fbc_cleanup_cfb(dev_priv);
16574 * set vga decode state - true == enable VGA decode
16576 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
16578 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16581 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16582 DRM_ERROR("failed to read control word\n");
16586 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16590 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16592 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16594 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16595 DRM_ERROR("failed to write control word\n");
16602 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16604 struct intel_display_error_state {
16606 u32 power_well_driver;
16608 struct intel_cursor_error_state {
16613 } cursor[I915_MAX_PIPES];
16615 struct intel_pipe_error_state {
16616 bool power_domain_on;
16619 } pipe[I915_MAX_PIPES];
16621 struct intel_plane_error_state {
16629 } plane[I915_MAX_PIPES];
16631 struct intel_transcoder_error_state {
16633 bool power_domain_on;
16634 enum transcoder cpu_transcoder;
16647 struct intel_display_error_state *
16648 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16650 struct intel_display_error_state *error;
16651 int transcoders[] = {
16659 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
16661 if (!HAS_DISPLAY(dev_priv))
16664 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16668 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16669 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
16671 for_each_pipe(dev_priv, i) {
16672 error->pipe[i].power_domain_on =
16673 __intel_display_power_is_enabled(dev_priv,
16674 POWER_DOMAIN_PIPE(i));
16675 if (!error->pipe[i].power_domain_on)
16678 error->cursor[i].control = I915_READ(CURCNTR(i));
16679 error->cursor[i].position = I915_READ(CURPOS(i));
16680 error->cursor[i].base = I915_READ(CURBASE(i));
16682 error->plane[i].control = I915_READ(DSPCNTR(i));
16683 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16684 if (INTEL_GEN(dev_priv) <= 3) {
16685 error->plane[i].size = I915_READ(DSPSIZE(i));
16686 error->plane[i].pos = I915_READ(DSPPOS(i));
16688 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16689 error->plane[i].addr = I915_READ(DSPADDR(i));
16690 if (INTEL_GEN(dev_priv) >= 4) {
16691 error->plane[i].surface = I915_READ(DSPSURF(i));
16692 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16695 error->pipe[i].source = I915_READ(PIPESRC(i));
16697 if (HAS_GMCH(dev_priv))
16698 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16701 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
16702 enum transcoder cpu_transcoder = transcoders[i];
16704 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
16707 error->transcoder[i].available = true;
16708 error->transcoder[i].power_domain_on =
16709 __intel_display_power_is_enabled(dev_priv,
16710 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16711 if (!error->transcoder[i].power_domain_on)
16714 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16716 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16717 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16718 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16719 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16720 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16721 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16722 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16728 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16731 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16732 struct intel_display_error_state *error)
16734 struct drm_i915_private *dev_priv = m->i915;
16740 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
16741 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16742 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16743 error->power_well_driver);
16744 for_each_pipe(dev_priv, i) {
16745 err_printf(m, "Pipe [%d]:\n", i);
16746 err_printf(m, " Power: %s\n",
16747 onoff(error->pipe[i].power_domain_on));
16748 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16749 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16751 err_printf(m, "Plane [%d]:\n", i);
16752 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16753 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16754 if (INTEL_GEN(dev_priv) <= 3) {
16755 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16756 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16758 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16759 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16760 if (INTEL_GEN(dev_priv) >= 4) {
16761 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16762 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16765 err_printf(m, "Cursor [%d]:\n", i);
16766 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16767 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16768 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16771 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
16772 if (!error->transcoder[i].available)
16775 err_printf(m, "CPU transcoder: %s\n",
16776 transcoder_name(error->transcoder[i].cpu_transcoder));
16777 err_printf(m, " Power: %s\n",
16778 onoff(error->transcoder[i].power_domain_on));
16779 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16780 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16781 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16782 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16783 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16784 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16785 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);