drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 /* Primary plane formats for gen <= 3 */
  53 static const uint32_t i8xx_primary_formats[] = {
  54         DRM_FORMAT_C8,
  55         DRM_FORMAT_RGB565,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_XRGB8888,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t i965_primary_formats[] = {
  62         DRM_FORMAT_C8,
  63         DRM_FORMAT_RGB565,
  64         DRM_FORMAT_XRGB8888,
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68 };
  69
  70 static const uint64_t i9xx_format_modifiers[] = {
  71         I915_FORMAT_MOD_X_TILED,
  72         DRM_FORMAT_MOD_LINEAR,
  73         DRM_FORMAT_MOD_INVALID
  74 };
  75
  76 static const uint32_t skl_primary_formats[] = {
  77         DRM_FORMAT_C8,
  78         DRM_FORMAT_RGB565,
  79         DRM_FORMAT_XRGB8888,
  80         DRM_FORMAT_XBGR8888,
  81         DRM_FORMAT_ARGB8888,
  82         DRM_FORMAT_ABGR8888,
  83         DRM_FORMAT_XRGB2101010,
  84         DRM_FORMAT_XBGR2101010,
  85         DRM_FORMAT_YUYV,
  86         DRM_FORMAT_YVYU,
  87         DRM_FORMAT_UYVY,
  88         DRM_FORMAT_VYUY,
  89 };
  90
  91 static const uint64_t skl_format_modifiers_noccs[] = {
  92         I915_FORMAT_MOD_Yf_TILED,
  93         I915_FORMAT_MOD_Y_TILED,
  94         I915_FORMAT_MOD_X_TILED,
  95         DRM_FORMAT_MOD_LINEAR,
  96         DRM_FORMAT_MOD_INVALID
  97 };
  98
  99 static const uint64_t skl_format_modifiers_ccs[] = {
 100         I915_FORMAT_MOD_Yf_TILED_CCS,
 101         I915_FORMAT_MOD_Y_TILED_CCS,
 102         I915_FORMAT_MOD_Yf_TILED,
 103         I915_FORMAT_MOD_Y_TILED,
 104         I915_FORMAT_MOD_X_TILED,
 105         DRM_FORMAT_MOD_LINEAR,
 106         DRM_FORMAT_MOD_INVALID
 107 };
 108
 109 /* Cursor formats */
 110 static const uint32_t intel_cursor_formats[] = {
 111         DRM_FORMAT_ARGB8888,
 112 };
 113
 114 static const uint64_t cursor_format_modifiers[] = {
 115         DRM_FORMAT_MOD_LINEAR,
 116         DRM_FORMAT_MOD_INVALID
 117 };
 118
 119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 120                                 struct intel_crtc_state *pipe_config);
 121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 122                                    struct intel_crtc_state *pipe_config);
 123
 124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 125                                   struct drm_i915_gem_object *obj,
 126                                   struct drm_mode_fb_cmd2 *mode_cmd);
 127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 131                                          struct intel_link_m_n *m_n,
 132                                          struct intel_link_m_n *m2_n2);
 133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 136 static void vlv_prepare_pll(struct intel_crtc *crtc,
 137                             const struct intel_crtc_state *pipe_config);
 138 static void chv_prepare_pll(struct intel_crtc *crtc,
 139                             const struct intel_crtc_state *pipe_config);
 140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 143                                     struct intel_crtc_state *crtc_state);
 144 static void skylake_pfit_enable(struct intel_crtc *crtc);
 145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 148                                          struct drm_modeset_acquire_ctx *ctx);
 149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 150
 151 struct intel_limit {
 152         struct {
 153                 int min, max;
 154         } dot, vco, n, m, m1, m2, p, p1;
 155
 156         struct {
 157                 int dot_limit;
 158                 int p2_slow, p2_fast;
 159         } p2;
 160 };
 161
 162 /* returns HPLL frequency in kHz */
 163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 164 {
 165         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 166
 167         /* Obtain SKU information */
 168         mutex_lock(&dev_priv->sb_lock);
 169         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 170                 CCK_FUSE_HPLL_FREQ_MASK;
 171         mutex_unlock(&dev_priv->sb_lock);
 172
 173         return vco_freq[hpll_freq] * 1000;
 174 }
 175
 176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 177                       const char *name, u32 reg, int ref_freq)
 178 {
 179         u32 val;
 180         int divider;
 181
 182         mutex_lock(&dev_priv->sb_lock);
 183         val = vlv_cck_read(dev_priv, reg);
 184         mutex_unlock(&dev_priv->sb_lock);
 185
 186         divider = val & CCK_FREQUENCY_VALUES;
 187
 188         WARN((val & CCK_FREQUENCY_STATUS) !=
 189              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 190              "%s change in progress\n", name);
 191
 192         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 193 }
 194
 195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 196                            const char *name, u32 reg)
 197 {
 198         if (dev_priv->hpll_freq == 0)
 199                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 200
 201         return vlv_get_cck_clock(dev_priv, name, reg,
 202                                  dev_priv->hpll_freq);
 203 }
 204
 205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 206 {
 207         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 208                 return;
 209
 210         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 211                                                       CCK_CZ_CLOCK_CONTROL);
 212
 213         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 214 }
 215
 216 static inline u32 /* units of 100MHz */
 217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 218                     const struct intel_crtc_state *pipe_config)
 219 {
 220         if (HAS_DDI(dev_priv))
 221                 return pipe_config->port_clock; /* SPLL */
 222         else
 223                 return dev_priv->fdi_pll_freq;
 224 }
 225
 226 static const struct intel_limit intel_limits_i8xx_dac = {
 227         .dot = { .min = 25000, .max = 350000 },
 228         .vco = { .min = 908000, .max = 1512000 },
 229         .n = { .min = 2, .max = 16 },
 230         .m = { .min = 96, .max = 140 },
 231         .m1 = { .min = 18, .max = 26 },
 232         .m2 = { .min = 6, .max = 16 },
 233         .p = { .min = 4, .max = 128 },
 234         .p1 = { .min = 2, .max = 33 },
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 4, .p2_fast = 2 },
 237 };
 238
 239 static const struct intel_limit intel_limits_i8xx_dvo = {
 240         .dot = { .min = 25000, .max = 350000 },
 241         .vco = { .min = 908000, .max = 1512000 },
 242         .n = { .min = 2, .max = 16 },
 243         .m = { .min = 96, .max = 140 },
 244         .m1 = { .min = 18, .max = 26 },
 245         .m2 = { .min = 6, .max = 16 },
 246         .p = { .min = 4, .max = 128 },
 247         .p1 = { .min = 2, .max = 33 },
 248         .p2 = { .dot_limit = 165000,
 249                 .p2_slow = 4, .p2_fast = 4 },
 250 };
 251
 252 static const struct intel_limit intel_limits_i8xx_lvds = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 908000, .max = 1512000 },
 255         .n = { .min = 2, .max = 16 },
 256         .m = { .min = 96, .max = 140 },
 257         .m1 = { .min = 18, .max = 26 },
 258         .m2 = { .min = 6, .max = 16 },
 259         .p = { .min = 4, .max = 128 },
 260         .p1 = { .min = 1, .max = 6 },
 261         .p2 = { .dot_limit = 165000,
 262                 .p2_slow = 14, .p2_fast = 7 },
 263 };
 264
 265 static const struct intel_limit intel_limits_i9xx_sdvo = {
 266         .dot = { .min = 20000, .max = 400000 },
 267         .vco = { .min = 1400000, .max = 2800000 },
 268         .n = { .min = 1, .max = 6 },
 269         .m = { .min = 70, .max = 120 },
 270         .m1 = { .min = 8, .max = 18 },
 271         .m2 = { .min = 3, .max = 7 },
 272         .p = { .min = 5, .max = 80 },
 273         .p1 = { .min = 1, .max = 8 },
 274         .p2 = { .dot_limit = 200000,
 275                 .p2_slow = 10, .p2_fast = 5 },
 276 };
 277
 278 static const struct intel_limit intel_limits_i9xx_lvds = {
 279         .dot = { .min = 20000, .max = 400000 },
 280         .vco = { .min = 1400000, .max = 2800000 },
 281         .n = { .min = 1, .max = 6 },
 282         .m = { .min = 70, .max = 120 },
 283         .m1 = { .min = 8, .max = 18 },
 284         .m2 = { .min = 3, .max = 7 },
 285         .p = { .min = 7, .max = 98 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 112000,
 288                 .p2_slow = 14, .p2_fast = 7 },
 289 };
 290
 291
 292 static const struct intel_limit intel_limits_g4x_sdvo = {
 293         .dot = { .min = 25000, .max = 270000 },
 294         .vco = { .min = 1750000, .max = 3500000},
 295         .n = { .min = 1, .max = 4 },
 296         .m = { .min = 104, .max = 138 },
 297         .m1 = { .min = 17, .max = 23 },
 298         .m2 = { .min = 5, .max = 11 },
 299         .p = { .min = 10, .max = 30 },
 300         .p1 = { .min = 1, .max = 3},
 301         .p2 = { .dot_limit = 270000,
 302                 .p2_slow = 10,
 303                 .p2_fast = 10
 304         },
 305 };
 306
 307 static const struct intel_limit intel_limits_g4x_hdmi = {
 308         .dot = { .min = 22000, .max = 400000 },
 309         .vco = { .min = 1750000, .max = 3500000},
 310         .n = { .min = 1, .max = 4 },
 311         .m = { .min = 104, .max = 138 },
 312         .m1 = { .min = 16, .max = 23 },
 313         .m2 = { .min = 5, .max = 11 },
 314         .p = { .min = 5, .max = 80 },
 315         .p1 = { .min = 1, .max = 8},
 316         .p2 = { .dot_limit = 165000,
 317                 .p2_slow = 10, .p2_fast = 5 },
 318 };
 319
 320 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 321         .dot = { .min = 20000, .max = 115000 },
 322         .vco = { .min = 1750000, .max = 3500000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 104, .max = 138 },
 325         .m1 = { .min = 17, .max = 23 },
 326         .m2 = { .min = 5, .max = 11 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 0,
 330                 .p2_slow = 14, .p2_fast = 14
 331         },
 332 };
 333
 334 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 335         .dot = { .min = 80000, .max = 224000 },
 336         .vco = { .min = 1750000, .max = 3500000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 104, .max = 138 },
 339         .m1 = { .min = 17, .max = 23 },
 340         .m2 = { .min = 5, .max = 11 },
 341         .p = { .min = 14, .max = 42 },
 342         .p1 = { .min = 2, .max = 6 },
 343         .p2 = { .dot_limit = 0,
 344                 .p2_slow = 7, .p2_fast = 7
 345         },
 346 };
 347
 348 static const struct intel_limit intel_limits_pineview_sdvo = {
 349         .dot = { .min = 20000, .max = 400000},
 350         .vco = { .min = 1700000, .max = 3500000 },
 351         /* Pineview's Ncounter is a ring counter */
 352         .n = { .min = 3, .max = 6 },
 353         .m = { .min = 2, .max = 256 },
 354         /* Pineview only has one combined m divider, which we treat as m2. */
 355         .m1 = { .min = 0, .max = 0 },
 356         .m2 = { .min = 0, .max = 254 },
 357         .p = { .min = 5, .max = 80 },
 358         .p1 = { .min = 1, .max = 8 },
 359         .p2 = { .dot_limit = 200000,
 360                 .p2_slow = 10, .p2_fast = 5 },
 361 };
 362
 363 static const struct intel_limit intel_limits_pineview_lvds = {
 364         .dot = { .min = 20000, .max = 400000 },
 365         .vco = { .min = 1700000, .max = 3500000 },
 366         .n = { .min = 3, .max = 6 },
 367         .m = { .min = 2, .max = 256 },
 368         .m1 = { .min = 0, .max = 0 },
 369         .m2 = { .min = 0, .max = 254 },
 370         .p = { .min = 7, .max = 112 },
 371         .p1 = { .min = 1, .max = 8 },
 372         .p2 = { .dot_limit = 112000,
 373                 .p2_slow = 14, .p2_fast = 14 },
 374 };
 375
 376 /* Ironlake / Sandybridge
 377  *
 378  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 379  * the range value for them is (actual_value - 2).
 380  */
 381 static const struct intel_limit intel_limits_ironlake_dac = {
 382         .dot = { .min = 25000, .max = 350000 },
 383         .vco = { .min = 1760000, .max = 3510000 },
 384         .n = { .min = 1, .max = 5 },
 385         .m = { .min = 79, .max = 127 },
 386         .m1 = { .min = 12, .max = 22 },
 387         .m2 = { .min = 5, .max = 9 },
 388         .p = { .min = 5, .max = 80 },
 389         .p1 = { .min = 1, .max = 8 },
 390         .p2 = { .dot_limit = 225000,
 391                 .p2_slow = 10, .p2_fast = 5 },
 392 };
 393
 394 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 395         .dot = { .min = 25000, .max = 350000 },
 396         .vco = { .min = 1760000, .max = 3510000 },
 397         .n = { .min = 1, .max = 3 },
 398         .m = { .min = 79, .max = 118 },
 399         .m1 = { .min = 12, .max = 22 },
 400         .m2 = { .min = 5, .max = 9 },
 401         .p = { .min = 28, .max = 112 },
 402         .p1 = { .min = 2, .max = 8 },
 403         .p2 = { .dot_limit = 225000,
 404                 .p2_slow = 14, .p2_fast = 14 },
 405 };
 406
 407 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 408         .dot = { .min = 25000, .max = 350000 },
 409         .vco = { .min = 1760000, .max = 3510000 },
 410         .n = { .min = 1, .max = 3 },
 411         .m = { .min = 79, .max = 127 },
 412         .m1 = { .min = 12, .max = 22 },
 413         .m2 = { .min = 5, .max = 9 },
 414         .p = { .min = 14, .max = 56 },
 415         .p1 = { .min = 2, .max = 8 },
 416         .p2 = { .dot_limit = 225000,
 417                 .p2_slow = 7, .p2_fast = 7 },
 418 };
 419
 420 /* LVDS 100mhz refclk limits. */
 421 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 422         .dot = { .min = 25000, .max = 350000 },
 423         .vco = { .min = 1760000, .max = 3510000 },
 424         .n = { .min = 1, .max = 2 },
 425         .m = { .min = 79, .max = 126 },
 426         .m1 = { .min = 12, .max = 22 },
 427         .m2 = { .min = 5, .max = 9 },
 428         .p = { .min = 28, .max = 112 },
 429         .p1 = { .min = 2, .max = 8 },
 430         .p2 = { .dot_limit = 225000,
 431                 .p2_slow = 14, .p2_fast = 14 },
 432 };
 433
 434 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 435         .dot = { .min = 25000, .max = 350000 },
 436         .vco = { .min = 1760000, .max = 3510000 },
 437         .n = { .min = 1, .max = 3 },
 438         .m = { .min = 79, .max = 126 },
 439         .m1 = { .min = 12, .max = 22 },
 440         .m2 = { .min = 5, .max = 9 },
 441         .p = { .min = 14, .max = 42 },
 442         .p1 = { .min = 2, .max = 6 },
 443         .p2 = { .dot_limit = 225000,
 444                 .p2_slow = 7, .p2_fast = 7 },
 445 };
 446
 447 static const struct intel_limit intel_limits_vlv = {
 448          /*
 449           * These are the data rate limits (measured in fast clocks)
 450           * since those are the strictest limits we have. The fast
 451           * clock and actual rate limits are more relaxed, so checking
 452           * them would make no difference.
 453           */
 454         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 455         .vco = { .min = 4000000, .max = 6000000 },
 456         .n = { .min = 1, .max = 7 },
 457         .m1 = { .min = 2, .max = 3 },
 458         .m2 = { .min = 11, .max = 156 },
 459         .p1 = { .min = 2, .max = 3 },
 460         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 461 };
 462
 463 static const struct intel_limit intel_limits_chv = {
 464         /*
 465          * These are the data rate limits (measured in fast clocks)
 466          * since those are the strictest limits we have.  The fast
 467          * clock and actual rate limits are more relaxed, so checking
 468          * them would make no difference.
 469          */
 470         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 471         .vco = { .min = 4800000, .max = 6480000 },
 472         .n = { .min = 1, .max = 1 },
 473         .m1 = { .min = 2, .max = 2 },
 474         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 475         .p1 = { .min = 2, .max = 4 },
 476         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 477 };
 478
 479 static const struct intel_limit intel_limits_bxt = {
 480         /* FIXME: find real dot limits */
 481         .dot = { .min = 0, .max = INT_MAX },
 482         .vco = { .min = 4800000, .max = 6700000 },
 483         .n = { .min = 1, .max = 1 },
 484         .m1 = { .min = 2, .max = 2 },
 485         /* FIXME: find real m2 limits */
 486         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 487         .p1 = { .min = 2, .max = 4 },
 488         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 489 };
 490
 491 static bool
 492 needs_modeset(struct drm_crtc_state *state)
 493 {
 494         return drm_atomic_crtc_needs_modeset(state);
 495 }
 496
 497 /*
 498  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 499  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 500  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 501  * The helpers' return value is the rate of the clock that is fed to the
 502  * display engine's pipe which can be the above fast dot clock rate or a
 503  * divided-down version of it.
 504  */
 505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 506 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 507 {
 508         clock->m = clock->m2 + 2;
 509         clock->p = clock->p1 * clock->p2;
 510         if (WARN_ON(clock->n == 0 || clock->p == 0))
 511                 return 0;
 512         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 513         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 514
 515         return clock->dot;
 516 }
 517
 518 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 519 {
 520         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 521 }
 522
 523 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 524 {
 525         clock->m = i9xx_dpll_compute_m(clock);
 526         clock->p = clock->p1 * clock->p2;
 527         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 528                 return 0;
 529         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 530         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 531
 532         return clock->dot;
 533 }
 534
 535 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 536 {
 537         clock->m = clock->m1 * clock->m2;
 538         clock->p = clock->p1 * clock->p2;
 539         if (WARN_ON(clock->n == 0 || clock->p == 0))
 540                 return 0;
 541         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 542         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 543
 544         return clock->dot / 5;
 545 }
 546
 547 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 548 {
 549         clock->m = clock->m1 * clock->m2;
 550         clock->p = clock->p1 * clock->p2;
 551         if (WARN_ON(clock->n == 0 || clock->p == 0))
 552                 return 0;
 553         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 554                         clock->n << 22);
 555         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 556
 557         return clock->dot / 5;
 558 }
 559
 560 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 561 /**
 562  * Returns whether the given set of divisors are valid for a given refclk with
 563  * the given connectors.
 564  */
 565
 566 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 567                                const struct intel_limit *limit,
 568                                const struct dpll *clock)
 569 {
 570         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 571                 INTELPllInvalid("n out of range\n");
 572         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 573                 INTELPllInvalid("p1 out of range\n");
 574         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 575                 INTELPllInvalid("m2 out of range\n");
 576         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 577                 INTELPllInvalid("m1 out of range\n");
 578
 579         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 580             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 581                 if (clock->m1 <= clock->m2)
 582                         INTELPllInvalid("m1 <= m2\n");
 583
 584         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 585             !IS_GEN9_LP(dev_priv)) {
 586                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 587                         INTELPllInvalid("p out of range\n");
 588                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 589                         INTELPllInvalid("m out of range\n");
 590         }
 591
 592         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 593                 INTELPllInvalid("vco out of range\n");
 594         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 595          * connector, etc., rather than just a single range.
 596          */
 597         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 598                 INTELPllInvalid("dot out of range\n");
 599
 600         return true;
 601 }
 602
 603 static int
 604 i9xx_select_p2_div(const struct intel_limit *limit,
 605                    const struct intel_crtc_state *crtc_state,
 606                    int target)
 607 {
 608         struct drm_device *dev = crtc_state->base.crtc->dev;
 609
 610         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 611                 /*
 612                  * For LVDS just rely on its current settings for dual-channel.
 613                  * We haven't figured out how to reliably set up different
 614                  * single/dual channel state, if we even can.
 615                  */
 616                 if (intel_is_dual_link_lvds(dev))
 617                         return limit->p2.p2_fast;
 618                 else
 619                         return limit->p2.p2_slow;
 620         } else {
 621                 if (target < limit->p2.dot_limit)
 622                         return limit->p2.p2_slow;
 623                 else
 624                         return limit->p2.p2_fast;
 625         }
 626 }
 627
 628 /*
 629  * Returns a set of divisors for the desired target clock with the given
 630  * refclk, or FALSE.  The returned values represent the clock equation:
 631  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 632  *
 633  * Target and reference clocks are specified in kHz.
 634  *
 635  * If match_clock is provided, then best_clock P divider must match the P
 636  * divider from @match_clock used for LVDS downclocking.
 637  */
 638 static bool
 639 i9xx_find_best_dpll(const struct intel_limit *limit,
 640                     struct intel_crtc_state *crtc_state,
 641                     int target, int refclk, struct dpll *match_clock,
 642                     struct dpll *best_clock)
 643 {
 644         struct drm_device *dev = crtc_state->base.crtc->dev;
 645         struct dpll clock;
 646         int err = target;
 647
 648         memset(best_clock, 0, sizeof(*best_clock));
 649
 650         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 651
 652         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 653              clock.m1++) {
 654                 for (clock.m2 = limit->m2.min;
 655                      clock.m2 <= limit->m2.max; clock.m2++) {
 656                         if (clock.m2 >= clock.m1)
 657                                 break;
 658                         for (clock.n = limit->n.min;
 659                              clock.n <= limit->n.max; clock.n++) {
 660                                 for (clock.p1 = limit->p1.min;
 661                                         clock.p1 <= limit->p1.max; clock.p1++) {
 662                                         int this_err;
 663
 664                                         i9xx_calc_dpll_params(refclk, &clock);
 665                                         if (!intel_PLL_is_valid(to_i915(dev),
 666                                                                 limit,
 667                                                                 &clock))
 668                                                 continue;
 669                                         if (match_clock &&
 670                                             clock.p != match_clock->p)
 671                                                 continue;
 672
 673                                         this_err = abs(clock.dot - target);
 674                                         if (this_err < err) {
 675                                                 *best_clock = clock;
 676                                                 err = this_err;
 677                                         }
 678                                 }
 679                         }
 680                 }
 681         }
 682
 683         return (err != target);
 684 }
 685
 686 /*
 687  * Returns a set of divisors for the desired target clock with the given
 688  * refclk, or FALSE.  The returned values represent the clock equation:
 689  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 690  *
 691  * Target and reference clocks are specified in kHz.
 692  *
 693  * If match_clock is provided, then best_clock P divider must match the P
 694  * divider from @match_clock used for LVDS downclocking.
 695  */
 696 static bool
 697 pnv_find_best_dpll(const struct intel_limit *limit,
 698                    struct intel_crtc_state *crtc_state,
 699                    int target, int refclk, struct dpll *match_clock,
 700                    struct dpll *best_clock)
 701 {
 702         struct drm_device *dev = crtc_state->base.crtc->dev;
 703         struct dpll clock;
 704         int err = target;
 705
 706         memset(best_clock, 0, sizeof(*best_clock));
 707
 708         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 709
 710         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711              clock.m1++) {
 712                 for (clock.m2 = limit->m2.min;
 713                      clock.m2 <= limit->m2.max; clock.m2++) {
 714                         for (clock.n = limit->n.min;
 715                              clock.n <= limit->n.max; clock.n++) {
 716                                 for (clock.p1 = limit->p1.min;
 717                                         clock.p1 <= limit->p1.max; clock.p1++) {
 718                                         int this_err;
 719
 720                                         pnv_calc_dpll_params(refclk, &clock);
 721                                         if (!intel_PLL_is_valid(to_i915(dev),
 722                                                                 limit,
 723                                                                 &clock))
 724                                                 continue;
 725                                         if (match_clock &&
 726                                             clock.p != match_clock->p)
 727                                                 continue;
 728
 729                                         this_err = abs(clock.dot - target);
 730                                         if (this_err < err) {
 731                                                 *best_clock = clock;
 732                                                 err = this_err;
 733                                         }
 734                                 }
 735                         }
 736                 }
 737         }
 738
 739         return (err != target);
 740 }
 741
 742 /*
 743  * Returns a set of divisors for the desired target clock with the given
 744  * refclk, or FALSE.  The returned values represent the clock equation:
 745  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 746  *
 747  * Target and reference clocks are specified in kHz.
 748  *
 749  * If match_clock is provided, then best_clock P divider must match the P
 750  * divider from @match_clock used for LVDS downclocking.
 751  */
 752 static bool
 753 g4x_find_best_dpll(const struct intel_limit *limit,
 754                    struct intel_crtc_state *crtc_state,
 755                    int target, int refclk, struct dpll *match_clock,
 756                    struct dpll *best_clock)
 757 {
 758         struct drm_device *dev = crtc_state->base.crtc->dev;
 759         struct dpll clock;
 760         int max_n;
 761         bool found = false;
 762         /* approximately equals target * 0.00585 */
 763         int err_most = (target >> 8) + (target >> 9);
 764
 765         memset(best_clock, 0, sizeof(*best_clock));
 766
 767         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 768
 769         max_n = limit->n.max;
 770         /* based on hardware requirement, prefer smaller n to precision */
 771         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 772                 /* based on hardware requirement, prefere larger m1,m2 */
 773                 for (clock.m1 = limit->m1.max;
 774                      clock.m1 >= limit->m1.min; clock.m1--) {
 775                         for (clock.m2 = limit->m2.max;
 776                              clock.m2 >= limit->m2.min; clock.m2--) {
 777                                 for (clock.p1 = limit->p1.max;
 778                                      clock.p1 >= limit->p1.min; clock.p1--) {
 779                                         int this_err;
 780
 781                                         i9xx_calc_dpll_params(refclk, &clock);
 782                                         if (!intel_PLL_is_valid(to_i915(dev),
 783                                                                 limit,
 784                                                                 &clock))
 785                                                 continue;
 786
 787                                         this_err = abs(clock.dot - target);
 788                                         if (this_err < err_most) {
 789                                                 *best_clock = clock;
 790                                                 err_most = this_err;
 791                                                 max_n = clock.n;
 792                                                 found = true;
 793                                         }
 794                                 }
 795                         }
 796                 }
 797         }
 798         return found;
 799 }
 800
 801 /*
 802  * Check if the calculated PLL configuration is more optimal compared to the
 803  * best configuration and error found so far. Return the calculated error.
 804  */
 805 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 806                                const struct dpll *calculated_clock,
 807                                const struct dpll *best_clock,
 808                                unsigned int best_error_ppm,
 809                                unsigned int *error_ppm)
 810 {
 811         /*
 812          * For CHV ignore the error and consider only the P value.
 813          * Prefer a bigger P value based on HW requirements.
 814          */
 815         if (IS_CHERRYVIEW(to_i915(dev))) {
 816                 *error_ppm = 0;
 817
 818                 return calculated_clock->p > best_clock->p;
 819         }
 820
 821         if (WARN_ON_ONCE(!target_freq))
 822                 return false;
 823
 824         *error_ppm = div_u64(1000000ULL *
 825                                 abs(target_freq - calculated_clock->dot),
 826                              target_freq);
 827         /*
 828          * Prefer a better P value over a better (smaller) error if the error
 829          * is small. Ensure this preference for future configurations too by
 830          * setting the error to 0.
 831          */
 832         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 833                 *error_ppm = 0;
 834
 835                 return true;
 836         }
 837
 838         return *error_ppm + 10 < best_error_ppm;
 839 }
 840
 841 /*
 842  * Returns a set of divisors for the desired target clock with the given
 843  * refclk, or FALSE.  The returned values represent the clock equation:
 844  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 845  */
 846 static bool
 847 vlv_find_best_dpll(const struct intel_limit *limit,
 848                    struct intel_crtc_state *crtc_state,
 849                    int target, int refclk, struct dpll *match_clock,
 850                    struct dpll *best_clock)
 851 {
 852         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 853         struct drm_device *dev = crtc->base.dev;
 854         struct dpll clock;
 855         unsigned int bestppm = 1000000;
 856         /* min update 19.2 MHz */
 857         int max_n = min(limit->n.max, refclk / 19200);
 858         bool found = false;
 859
 860         target *= 5; /* fast clock */
 861
 862         memset(best_clock, 0, sizeof(*best_clock));
 863
 864         /* based on hardware requirement, prefer smaller n to precision */
 865         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 866                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 867                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 868                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 869                                 clock.p = clock.p1 * clock.p2;
 870                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 871                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 872                                         unsigned int ppm;
 873
 874                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 875                                                                      refclk * clock.m1);
 876
 877                                         vlv_calc_dpll_params(refclk, &clock);
 878
 879                                         if (!intel_PLL_is_valid(to_i915(dev),
 880                                                                 limit,
 881                                                                 &clock))
 882                                                 continue;
 883
 884                                         if (!vlv_PLL_is_optimal(dev, target,
 885                                                                 &clock,
 886                                                                 best_clock,
 887                                                                 bestppm, &ppm))
 888                                                 continue;
 889
 890                                         *best_clock = clock;
 891                                         bestppm = ppm;
 892                                         found = true;
 893                                 }
 894                         }
 895                 }
 896         }
 897
 898         return found;
 899 }
 900
 901 /*
 902  * Returns a set of divisors for the desired target clock with the given
 903  * refclk, or FALSE.  The returned values represent the clock equation:
 904  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 905  */
 906 static bool
 907 chv_find_best_dpll(const struct intel_limit *limit,
 908                    struct intel_crtc_state *crtc_state,
 909                    int target, int refclk, struct dpll *match_clock,
 910                    struct dpll *best_clock)
 911 {
 912         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 913         struct drm_device *dev = crtc->base.dev;
 914         unsigned int best_error_ppm;
 915         struct dpll clock;
 916         uint64_t m2;
 917         int found = false;
 918
 919         memset(best_clock, 0, sizeof(*best_clock));
 920         best_error_ppm = 1000000;
 921
 922         /*
 923          * Based on hardware doc, the n always set to 1, and m1 always
 924          * set to 2.  If requires to support 200Mhz refclk, we need to
 925          * revisit this because n may not 1 anymore.
 926          */
 927         clock.n = 1, clock.m1 = 2;
 928         target *= 5;    /* fast clock */
 929
 930         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 931                 for (clock.p2 = limit->p2.p2_fast;
 932                                 clock.p2 >= limit->p2.p2_slow;
 933                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 934                         unsigned int error_ppm;
 935
 936                         clock.p = clock.p1 * clock.p2;
 937
 938                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 939                                         clock.n) << 22, refclk * clock.m1);
 940
 941                         if (m2 > INT_MAX/clock.m1)
 942                                 continue;
 943
 944                         clock.m2 = m2;
 945
 946                         chv_calc_dpll_params(refclk, &clock);
 947
 948                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 949                                 continue;
 950
 951                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 952                                                 best_error_ppm, &error_ppm))
 953                                 continue;
 954
 955                         *best_clock = clock;
 956                         best_error_ppm = error_ppm;
 957                         found = true;
 958                 }
 959         }
 960
 961         return found;
 962 }
 963
 964 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 965                         struct dpll *best_clock)
 966 {
 967         int refclk = 100000;
 968         const struct intel_limit *limit = &intel_limits_bxt;
 969
 970         return chv_find_best_dpll(limit, crtc_state,
 971                                   target_clock, refclk, NULL, best_clock);
 972 }
 973
 974 bool intel_crtc_active(struct intel_crtc *crtc)
 975 {
 976         /* Be paranoid as we can arrive here with only partial
 977          * state retrieved from the hardware during setup.
 978          *
 979          * We can ditch the adjusted_mode.crtc_clock check as soon
 980          * as Haswell has gained clock readout/fastboot support.
 981          *
 982          * We can ditch the crtc->primary->fb check as soon as we can
 983          * properly reconstruct framebuffers.
 984          *
 985          * FIXME: The intel_crtc->active here should be switched to
 986          * crtc->state->active once we have proper CRTC states wired up
 987          * for atomic.
 988          */
 989         return crtc->active && crtc->base.primary->state->fb &&
 990                 crtc->config->base.adjusted_mode.crtc_clock;
 991 }
 992
 993 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 994                                              enum pipe pipe)
 995 {
 996         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 997
 998         return crtc->config->cpu_transcoder;
 999 }
1000
1001 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1002 {
1003         i915_reg_t reg = PIPEDSL(pipe);
1004         u32 line1, line2;
1005         u32 line_mask;
1006
1007         if (IS_GEN2(dev_priv))
1008                 line_mask = DSL_LINEMASK_GEN2;
1009         else
1010                 line_mask = DSL_LINEMASK_GEN3;
1011
1012         line1 = I915_READ(reg) & line_mask;
1013         msleep(5);
1014         line2 = I915_READ(reg) & line_mask;
1015
1016         return line1 == line2;
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @crtc: crtc whose pipe to wait for
1022  *
1023  * After disabling a pipe, we can't wait for vblank in the usual way,
1024  * spinning on the vblank interrupt status bit, since we won't actually
1025  * see an interrupt when the pipe is disabled.
1026  *
1027  * On Gen4 and above:
1028  *   wait for the pipe register state bit to turn off
1029  *
1030  * Otherwise:
1031  *   wait for the display line value to settle (it usually
1032  *   ends up stopping at the start of the next frame).
1033  *
1034  */
1035 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1038         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1039         enum pipe pipe = crtc->pipe;
1040
1041         if (INTEL_GEN(dev_priv) >= 4) {
1042                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1043
1044                 /* Wait for the Pipe State to go off */
1045                 if (intel_wait_for_register(dev_priv,
1046                                             reg, I965_PIPECONF_ACTIVE, 0,
1047                                             100))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         } else {
1050                 /* Wait for the display line to settle */
1051                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1052                         WARN(1, "pipe_off wait timed out\n");
1053         }
1054 }
1055
1056 /* Only for pre-ILK configs */
1057 void assert_pll(struct drm_i915_private *dev_priv,
1058                 enum pipe pipe, bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         val = I915_READ(DPLL(pipe));
1064         cur_state = !!(val & DPLL_VCO_ENABLE);
1065         I915_STATE_WARN(cur_state != state,
1066              "PLL state assertion failure (expected %s, current %s)\n",
1067                         onoff(state), onoff(cur_state));
1068 }
1069
1070 /* XXX: the dsi pll is shared between MIPI DSI ports */
1071 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1072 {
1073         u32 val;
1074         bool cur_state;
1075
1076         mutex_lock(&dev_priv->sb_lock);
1077         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1078         mutex_unlock(&dev_priv->sb_lock);
1079
1080         cur_state = val & DSI_PLL_VCO_EN;
1081         I915_STATE_WARN(cur_state != state,
1082              "DSI PLL state assertion failure (expected %s, current %s)\n",
1083                         onoff(state), onoff(cur_state));
1084 }
1085
1086 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1087                           enum pipe pipe, bool state)
1088 {
1089         bool cur_state;
1090         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1091                                                                       pipe);
1092
1093         if (HAS_DDI(dev_priv)) {
1094                 /* DDI does not have a specific FDI_TX register */
1095                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1096                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1097         } else {
1098                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1099                 cur_state = !!(val & FDI_TX_ENABLE);
1100         }
1101         I915_STATE_WARN(cur_state != state,
1102              "FDI TX state assertion failure (expected %s, current %s)\n",
1103                         onoff(state), onoff(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109                           enum pipe pipe, bool state)
1110 {
1111         u32 val;
1112         bool cur_state;
1113
1114         val = I915_READ(FDI_RX_CTL(pipe));
1115         cur_state = !!(val & FDI_RX_ENABLE);
1116         I915_STATE_WARN(cur_state != state,
1117              "FDI RX state assertion failure (expected %s, current %s)\n",
1118                         onoff(state), onoff(cur_state));
1119 }
1120 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1121 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122
1123 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1124                                       enum pipe pipe)
1125 {
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (IS_GEN5(dev_priv))
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv))
1134                 return;
1135
1136         val = I915_READ(FDI_TX_CTL(pipe));
1137         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1138 }
1139
1140 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1141                        enum pipe pipe, bool state)
1142 {
1143         u32 val;
1144         bool cur_state;
1145
1146         val = I915_READ(FDI_RX_CTL(pipe));
1147         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1148         I915_STATE_WARN(cur_state != state,
1149              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1150                         onoff(state), onoff(cur_state));
1151 }
1152
1153 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1154 {
1155         i915_reg_t pp_reg;
1156         u32 val;
1157         enum pipe panel_pipe = PIPE_A;
1158         bool locked = true;
1159
1160         if (WARN_ON(HAS_DDI(dev_priv)))
1161                 return;
1162
1163         if (HAS_PCH_SPLIT(dev_priv)) {
1164                 u32 port_sel;
1165
1166                 pp_reg = PP_CONTROL(0);
1167                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1168
1169                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1170                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1171                         panel_pipe = PIPE_B;
1172                 /* XXX: else fix for eDP */
1173         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1174                 /* presumably write lock depends on pipe, not port select */
1175                 pp_reg = PP_CONTROL(pipe);
1176                 panel_pipe = pipe;
1177         } else {
1178                 pp_reg = PP_CONTROL(0);
1179                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1180                         panel_pipe = PIPE_B;
1181         }
1182
1183         val = I915_READ(pp_reg);
1184         if (!(val & PANEL_POWER_ON) ||
1185             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1186                 locked = false;
1187
1188         I915_STATE_WARN(panel_pipe == pipe && locked,
1189              "panel assertion failure, pipe %c regs locked\n",
1190              pipe_name(pipe));
1191 }
1192
1193 static void assert_cursor(struct drm_i915_private *dev_priv,
1194                           enum pipe pipe, bool state)
1195 {
1196         bool cur_state;
1197
1198         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1199                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1200         else
1201                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1202
1203         I915_STATE_WARN(cur_state != state,
1204              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1205                         pipe_name(pipe), onoff(state), onoff(cur_state));
1206 }
1207 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1208 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1209
1210 void assert_pipe(struct drm_i915_private *dev_priv,
1211                  enum pipe pipe, bool state)
1212 {
1213         bool cur_state;
1214         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1215                                                                       pipe);
1216         enum intel_display_power_domain power_domain;
1217
1218         /* we keep both pipes enabled on 830 */
1219         if (IS_I830(dev_priv))
1220                 state = true;
1221
1222         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1223         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1224                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1225                 cur_state = !!(val & PIPECONF_ENABLE);
1226
1227                 intel_display_power_put(dev_priv, power_domain);
1228         } else {
1229                 cur_state = false;
1230         }
1231
1232         I915_STATE_WARN(cur_state != state,
1233              "pipe %c assertion failure (expected %s, current %s)\n",
1234                         pipe_name(pipe), onoff(state), onoff(cur_state));
1235 }
1236
1237 static void assert_plane(struct drm_i915_private *dev_priv,
1238                          enum plane plane, bool state)
1239 {
1240         u32 val;
1241         bool cur_state;
1242
1243         val = I915_READ(DSPCNTR(plane));
1244         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1245         I915_STATE_WARN(cur_state != state,
1246              "plane %c assertion failure (expected %s, current %s)\n",
1247                         plane_name(plane), onoff(state), onoff(cur_state));
1248 }
1249
1250 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1251 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1252
1253 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1254                                    enum pipe pipe)
1255 {
1256         int i;
1257
1258         /* Primary planes are fixed to pipes on gen4+ */
1259         if (INTEL_GEN(dev_priv) >= 4) {
1260                 u32 val = I915_READ(DSPCNTR(pipe));
1261                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1262                      "plane %c assertion failure, should be disabled but not\n",
1263                      plane_name(pipe));
1264                 return;
1265         }
1266
1267         /* Need to check both planes against the pipe */
1268         for_each_pipe(dev_priv, i) {
1269                 u32 val = I915_READ(DSPCNTR(i));
1270                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279                                     enum pipe pipe)
1280 {
1281         int sprite;
1282
1283         if (INTEL_GEN(dev_priv) >= 9) {
1284                 for_each_sprite(dev_priv, pipe, sprite) {
1285                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1286                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1287                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1288                              sprite, pipe_name(pipe));
1289                 }
1290         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1291                 for_each_sprite(dev_priv, pipe, sprite) {
1292                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1293                         I915_STATE_WARN(val & SP_ENABLE,
1294                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1295                              sprite_name(pipe, sprite), pipe_name(pipe));
1296                 }
1297         } else if (INTEL_GEN(dev_priv) >= 7) {
1298                 u32 val = I915_READ(SPRCTL(pipe));
1299                 I915_STATE_WARN(val & SPRITE_ENABLE,
1300                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1301                      plane_name(pipe), pipe_name(pipe));
1302         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1303                 u32 val = I915_READ(DVSCNTR(pipe));
1304                 I915_STATE_WARN(val & DVS_ENABLE,
1305                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1306                      plane_name(pipe), pipe_name(pipe));
1307         }
1308 }
1309
1310 static void assert_vblank_disabled(struct drm_crtc *crtc)
1311 {
1312         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1313                 drm_crtc_vblank_put(crtc);
1314 }
1315
1316 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         u32 val;
1320         bool enabled;
1321
1322         val = I915_READ(PCH_TRANSCONF(pipe));
1323         enabled = !!(val & TRANS_ENABLE);
1324         I915_STATE_WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330                             enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332         if ((val & DP_PORT_EN) == 0)
1333                 return false;
1334
1335         if (HAS_PCH_CPT(dev_priv)) {
1336                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1337                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1338                         return false;
1339         } else if (IS_CHERRYVIEW(dev_priv)) {
1340                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & SDVO_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv)) {
1356                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1357                         return false;
1358         } else if (IS_CHERRYVIEW(dev_priv)) {
1359                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1360                         return false;
1361         } else {
1362                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1363                         return false;
1364         }
1365         return true;
1366 }
1367
1368 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1369                               enum pipe pipe, u32 val)
1370 {
1371         if ((val & LVDS_PORT_EN) == 0)
1372                 return false;
1373
1374         if (HAS_PCH_CPT(dev_priv)) {
1375                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & ADPA_DAC_ENABLE) == 0)
1388                 return false;
1389         if (HAS_PCH_CPT(dev_priv)) {
1390                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1391                         return false;
1392         } else {
1393                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1394                         return false;
1395         }
1396         return true;
1397 }
1398
1399 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1400                                    enum pipe pipe, i915_reg_t reg,
1401                                    u32 port_sel)
1402 {
1403         u32 val = I915_READ(reg);
1404         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406              i915_mmio_reg_offset(reg), pipe_name(pipe));
1407
1408         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1409              && (val & DP_PIPEB_SELECT),
1410              "IBX PCH dp port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414                                      enum pipe pipe, i915_reg_t reg)
1415 {
1416         u32 val = I915_READ(reg);
1417         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419              i915_mmio_reg_offset(reg), pipe_name(pipe));
1420
1421         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1422              && (val & SDVO_PIPE_B_SELECT),
1423              "IBX PCH hdmi port still using transcoder B\n");
1424 }
1425
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1427                                       enum pipe pipe)
1428 {
1429         u32 val;
1430
1431         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1432         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1434
1435         val = I915_READ(PCH_ADPA);
1436         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1437              "PCH VGA enabled on transcoder %c, should be disabled\n",
1438              pipe_name(pipe));
1439
1440         val = I915_READ(PCH_LVDS);
1441         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1442              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1443              pipe_name(pipe));
1444
1445         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1447         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1448 }
1449
1450 static void _vlv_enable_pll(struct intel_crtc *crtc,
1451                             const struct intel_crtc_state *pipe_config)
1452 {
1453         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1454         enum pipe pipe = crtc->pipe;
1455
1456         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457         POSTING_READ(DPLL(pipe));
1458         udelay(150);
1459
1460         if (intel_wait_for_register(dev_priv,
1461                                     DPLL(pipe),
1462                                     DPLL_LOCK_VLV,
1463                                     DPLL_LOCK_VLV,
1464                                     1))
1465                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1466 }
1467
1468 static void vlv_enable_pll(struct intel_crtc *crtc,
1469                            const struct intel_crtc_state *pipe_config)
1470 {
1471         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1472         enum pipe pipe = crtc->pipe;
1473
1474         assert_pipe_disabled(dev_priv, pipe);
1475
1476         /* PLL is protected by panel, make sure we can write it */
1477         assert_panel_unlocked(dev_priv, pipe);
1478
1479         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1480                 _vlv_enable_pll(crtc, pipe_config);
1481
1482         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1483         POSTING_READ(DPLL_MD(pipe));
1484 }
1485
1486
1487 static void _chv_enable_pll(struct intel_crtc *crtc,
1488                             const struct intel_crtc_state *pipe_config)
1489 {
1490         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1491         enum pipe pipe = crtc->pipe;
1492         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1493         u32 tmp;
1494
1495         mutex_lock(&dev_priv->sb_lock);
1496
1497         /* Enable back the 10bit clock to display controller */
1498         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1499         tmp |= DPIO_DCLKP_EN;
1500         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1501
1502         mutex_unlock(&dev_priv->sb_lock);
1503
1504         /*
1505          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1506          */
1507         udelay(1);
1508
1509         /* Enable PLL */
1510         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1511
1512         /* Check PLL is locked */
1513         if (intel_wait_for_register(dev_priv,
1514                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1515                                     1))
1516                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1517 }
1518
1519 static void chv_enable_pll(struct intel_crtc *crtc,
1520                            const struct intel_crtc_state *pipe_config)
1521 {
1522         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1523         enum pipe pipe = crtc->pipe;
1524
1525         assert_pipe_disabled(dev_priv, pipe);
1526
1527         /* PLL is protected by panel, make sure we can write it */
1528         assert_panel_unlocked(dev_priv, pipe);
1529
1530         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1531                 _chv_enable_pll(crtc, pipe_config);
1532
1533         if (pipe != PIPE_A) {
1534                 /*
1535                  * WaPixelRepeatModeFixForC0:chv
1536                  *
1537                  * DPLLCMD is AWOL. Use chicken bits to propagate
1538                  * the value from DPLLBMD to either pipe B or C.
1539                  */
1540                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1541                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1542                 I915_WRITE(CBR4_VLV, 0);
1543                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1544
1545                 /*
1546                  * DPLLB VGA mode also seems to cause problems.
1547                  * We should always have it disabled.
1548                  */
1549                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1550         } else {
1551                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1552                 POSTING_READ(DPLL_MD(pipe));
1553         }
1554 }
1555
1556 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1557 {
1558         struct intel_crtc *crtc;
1559         int count = 0;
1560
1561         for_each_intel_crtc(&dev_priv->drm, crtc) {
1562                 count += crtc->base.state->active &&
1563                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1564         }
1565
1566         return count;
1567 }
1568
1569 static void i9xx_enable_pll(struct intel_crtc *crtc,
1570                             const struct intel_crtc_state *crtc_state)
1571 {
1572         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1573         i915_reg_t reg = DPLL(crtc->pipe);
1574         u32 dpll = crtc_state->dpll_hw_state.dpll;
1575         int i;
1576
1577         assert_pipe_disabled(dev_priv, crtc->pipe);
1578
1579         /* PLL is protected by panel, make sure we can write it */
1580         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1581                 assert_panel_unlocked(dev_priv, crtc->pipe);
1582
1583         /* Enable DVO 2x clock on both PLLs if necessary */
1584         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1585                 /*
1586                  * It appears to be important that we don't enable this
1587                  * for the current pipe before otherwise configuring the
1588                  * PLL. No idea how this should be handled if multiple
1589                  * DVO outputs are enabled simultaneosly.
1590                  */
1591                 dpll |= DPLL_DVO_2X_MODE;
1592                 I915_WRITE(DPLL(!crtc->pipe),
1593                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1594         }
1595
1596         /*
1597          * Apparently we need to have VGA mode enabled prior to changing
1598          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1599          * dividers, even though the register value does change.
1600          */
1601         I915_WRITE(reg, 0);
1602
1603         I915_WRITE(reg, dpll);
1604
1605         /* Wait for the clocks to stabilize. */
1606         POSTING_READ(reg);
1607         udelay(150);
1608
1609         if (INTEL_GEN(dev_priv) >= 4) {
1610                 I915_WRITE(DPLL_MD(crtc->pipe),
1611                            crtc_state->dpll_hw_state.dpll_md);
1612         } else {
1613                 /* The pixel multiplier can only be updated once the
1614                  * DPLL is enabled and the clocks are stable.
1615                  *
1616                  * So write it again.
1617                  */
1618                 I915_WRITE(reg, dpll);
1619         }
1620
1621         /* We do this three times for luck */
1622         for (i = 0; i < 3; i++) {
1623                 I915_WRITE(reg, dpll);
1624                 POSTING_READ(reg);
1625                 udelay(150); /* wait for warmup */
1626         }
1627 }
1628
1629 static void i9xx_disable_pll(struct intel_crtc *crtc)
1630 {
1631         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1632         enum pipe pipe = crtc->pipe;
1633
1634         /* Disable DVO 2x clock on both PLLs if necessary */
1635         if (IS_I830(dev_priv) &&
1636             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1637             !intel_num_dvo_pipes(dev_priv)) {
1638                 I915_WRITE(DPLL(PIPE_B),
1639                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1640                 I915_WRITE(DPLL(PIPE_A),
1641                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1642         }
1643
1644         /* Don't disable pipe or pipe PLLs if needed */
1645         if (IS_I830(dev_priv))
1646                 return;
1647
1648         /* Make sure the pipe isn't still relying on us */
1649         assert_pipe_disabled(dev_priv, pipe);
1650
1651         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1652         POSTING_READ(DPLL(pipe));
1653 }
1654
1655 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1656 {
1657         u32 val;
1658
1659         /* Make sure the pipe isn't still relying on us */
1660         assert_pipe_disabled(dev_priv, pipe);
1661
1662         val = DPLL_INTEGRATED_REF_CLK_VLV |
1663                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1664         if (pipe != PIPE_A)
1665                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1666
1667         I915_WRITE(DPLL(pipe), val);
1668         POSTING_READ(DPLL(pipe));
1669 }
1670
1671 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1672 {
1673         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1674         u32 val;
1675
1676         /* Make sure the pipe isn't still relying on us */
1677         assert_pipe_disabled(dev_priv, pipe);
1678
1679         val = DPLL_SSC_REF_CLK_CHV |
1680                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1681         if (pipe != PIPE_A)
1682                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1683
1684         I915_WRITE(DPLL(pipe), val);
1685         POSTING_READ(DPLL(pipe));
1686
1687         mutex_lock(&dev_priv->sb_lock);
1688
1689         /* Disable 10bit clock to display controller */
1690         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1691         val &= ~DPIO_DCLKP_EN;
1692         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1693
1694         mutex_unlock(&dev_priv->sb_lock);
1695 }
1696
1697 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1698                          struct intel_digital_port *dport,
1699                          unsigned int expected_mask)
1700 {
1701         u32 port_mask;
1702         i915_reg_t dpll_reg;
1703
1704         switch (dport->base.port) {
1705         case PORT_B:
1706                 port_mask = DPLL_PORTB_READY_MASK;
1707                 dpll_reg = DPLL(0);
1708                 break;
1709         case PORT_C:
1710                 port_mask = DPLL_PORTC_READY_MASK;
1711                 dpll_reg = DPLL(0);
1712                 expected_mask <<= 4;
1713                 break;
1714         case PORT_D:
1715                 port_mask = DPLL_PORTD_READY_MASK;
1716                 dpll_reg = DPIO_PHY_STATUS;
1717                 break;
1718         default:
1719                 BUG();
1720         }
1721
1722         if (intel_wait_for_register(dev_priv,
1723                                     dpll_reg, port_mask, expected_mask,
1724                                     1000))
1725                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1726                      port_name(dport->base.port),
1727                      I915_READ(dpll_reg) & port_mask, expected_mask);
1728 }
1729
1730 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1731                                            enum pipe pipe)
1732 {
1733         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1734                                                                 pipe);
1735         i915_reg_t reg;
1736         uint32_t val, pipeconf_val;
1737
1738         /* Make sure PCH DPLL is enabled */
1739         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1740
1741         /* FDI must be feeding us bits for PCH ports */
1742         assert_fdi_tx_enabled(dev_priv, pipe);
1743         assert_fdi_rx_enabled(dev_priv, pipe);
1744
1745         if (HAS_PCH_CPT(dev_priv)) {
1746                 /* Workaround: Set the timing override bit before enabling the
1747                  * pch transcoder. */
1748                 reg = TRANS_CHICKEN2(pipe);
1749                 val = I915_READ(reg);
1750                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1751                 I915_WRITE(reg, val);
1752         }
1753
1754         reg = PCH_TRANSCONF(pipe);
1755         val = I915_READ(reg);
1756         pipeconf_val = I915_READ(PIPECONF(pipe));
1757
1758         if (HAS_PCH_IBX(dev_priv)) {
1759                 /*
1760                  * Make the BPC in transcoder be consistent with
1761                  * that in pipeconf reg. For HDMI we must use 8bpc
1762                  * here for both 8bpc and 12bpc.
1763                  */
1764                 val &= ~PIPECONF_BPC_MASK;
1765                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1766                         val |= PIPECONF_8BPC;
1767                 else
1768                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1769         }
1770
1771         val &= ~TRANS_INTERLACE_MASK;
1772         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1773                 if (HAS_PCH_IBX(dev_priv) &&
1774                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1775                         val |= TRANS_LEGACY_INTERLACED_ILK;
1776                 else
1777                         val |= TRANS_INTERLACED;
1778         else
1779                 val |= TRANS_PROGRESSIVE;
1780
1781         I915_WRITE(reg, val | TRANS_ENABLE);
1782         if (intel_wait_for_register(dev_priv,
1783                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1784                                     100))
1785                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1786 }
1787
1788 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1789                                       enum transcoder cpu_transcoder)
1790 {
1791         u32 val, pipeconf_val;
1792
1793         /* FDI must be feeding us bits for PCH ports */
1794         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1795         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1796
1797         /* Workaround: set timing override bit. */
1798         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1799         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1801
1802         val = TRANS_ENABLE;
1803         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1804
1805         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1806             PIPECONF_INTERLACED_ILK)
1807                 val |= TRANS_INTERLACED;
1808         else
1809                 val |= TRANS_PROGRESSIVE;
1810
1811         I915_WRITE(LPT_TRANSCONF, val);
1812         if (intel_wait_for_register(dev_priv,
1813                                     LPT_TRANSCONF,
1814                                     TRANS_STATE_ENABLE,
1815                                     TRANS_STATE_ENABLE,
1816                                     100))
1817                 DRM_ERROR("Failed to enable PCH transcoder\n");
1818 }
1819
1820 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1821                                             enum pipe pipe)
1822 {
1823         i915_reg_t reg;
1824         uint32_t val;
1825
1826         /* FDI relies on the transcoder */
1827         assert_fdi_tx_disabled(dev_priv, pipe);
1828         assert_fdi_rx_disabled(dev_priv, pipe);
1829
1830         /* Ports must be off as well */
1831         assert_pch_ports_disabled(dev_priv, pipe);
1832
1833         reg = PCH_TRANSCONF(pipe);
1834         val = I915_READ(reg);
1835         val &= ~TRANS_ENABLE;
1836         I915_WRITE(reg, val);
1837         /* wait for PCH transcoder off, transcoder state */
1838         if (intel_wait_for_register(dev_priv,
1839                                     reg, TRANS_STATE_ENABLE, 0,
1840                                     50))
1841                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1842
1843         if (HAS_PCH_CPT(dev_priv)) {
1844                 /* Workaround: Clear the timing override chicken bit again. */
1845                 reg = TRANS_CHICKEN2(pipe);
1846                 val = I915_READ(reg);
1847                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1848                 I915_WRITE(reg, val);
1849         }
1850 }
1851
1852 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1853 {
1854         u32 val;
1855
1856         val = I915_READ(LPT_TRANSCONF);
1857         val &= ~TRANS_ENABLE;
1858         I915_WRITE(LPT_TRANSCONF, val);
1859         /* wait for PCH transcoder off, transcoder state */
1860         if (intel_wait_for_register(dev_priv,
1861                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1862                                     50))
1863                 DRM_ERROR("Failed to disable PCH transcoder\n");
1864
1865         /* Workaround: clear timing override bit. */
1866         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1867         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1868         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1869 }
1870
1871 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1872 {
1873         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1874
1875         WARN_ON(!crtc->config->has_pch_encoder);
1876
1877         if (HAS_PCH_LPT(dev_priv))
1878                 return PIPE_A;
1879         else
1880                 return crtc->pipe;
1881 }
1882
1883 /**
1884  * intel_enable_pipe - enable a pipe, asserting requirements
1885  * @crtc: crtc responsible for the pipe
1886  *
1887  * Enable @crtc's pipe, making sure that various hardware specific requirements
1888  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1889  */
1890 static void intel_enable_pipe(struct intel_crtc *crtc)
1891 {
1892         struct drm_device *dev = crtc->base.dev;
1893         struct drm_i915_private *dev_priv = to_i915(dev);
1894         enum pipe pipe = crtc->pipe;
1895         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1896         i915_reg_t reg;
1897         u32 val;
1898
1899         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1900
1901         assert_planes_disabled(dev_priv, pipe);
1902         assert_cursor_disabled(dev_priv, pipe);
1903         assert_sprites_disabled(dev_priv, pipe);
1904
1905         /*
1906          * A pipe without a PLL won't actually be able to drive bits from
1907          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1908          * need the check.
1909          */
1910         if (HAS_GMCH_DISPLAY(dev_priv)) {
1911                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1912                         assert_dsi_pll_enabled(dev_priv);
1913                 else
1914                         assert_pll_enabled(dev_priv, pipe);
1915         } else {
1916                 if (crtc->config->has_pch_encoder) {
1917                         /* if driving the PCH, we need FDI enabled */
1918                         assert_fdi_rx_pll_enabled(dev_priv,
1919                                                   intel_crtc_pch_transcoder(crtc));
1920                         assert_fdi_tx_pll_enabled(dev_priv,
1921                                                   (enum pipe) cpu_transcoder);
1922                 }
1923                 /* FIXME: assert CPU port conditions for SNB+ */
1924         }
1925
1926         reg = PIPECONF(cpu_transcoder);
1927         val = I915_READ(reg);
1928         if (val & PIPECONF_ENABLE) {
1929                 /* we keep both pipes enabled on 830 */
1930                 WARN_ON(!IS_I830(dev_priv));
1931                 return;
1932         }
1933
1934         I915_WRITE(reg, val | PIPECONF_ENABLE);
1935         POSTING_READ(reg);
1936
1937         /*
1938          * Until the pipe starts DSL will read as 0, which would cause
1939          * an apparent vblank timestamp jump, which messes up also the
1940          * frame count when it's derived from the timestamps. So let's
1941          * wait for the pipe to start properly before we call
1942          * drm_crtc_vblank_on()
1943          */
1944         if (dev->max_vblank_count == 0 &&
1945             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1946                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1947 }
1948
1949 /**
1950  * intel_disable_pipe - disable a pipe, asserting requirements
1951  * @crtc: crtc whose pipes is to be disabled
1952  *
1953  * Disable the pipe of @crtc, making sure that various hardware
1954  * specific requirements are met, if applicable, e.g. plane
1955  * disabled, panel fitter off, etc.
1956  *
1957  * Will wait until the pipe has shut down before returning.
1958  */
1959 static void intel_disable_pipe(struct intel_crtc *crtc)
1960 {
1961         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1962         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1963         enum pipe pipe = crtc->pipe;
1964         i915_reg_t reg;
1965         u32 val;
1966
1967         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1968
1969         /*
1970          * Make sure planes won't keep trying to pump pixels to us,
1971          * or we might hang the display.
1972          */
1973         assert_planes_disabled(dev_priv, pipe);
1974         assert_cursor_disabled(dev_priv, pipe);
1975         assert_sprites_disabled(dev_priv, pipe);
1976
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if ((val & PIPECONF_ENABLE) == 0)
1980                 return;
1981
1982         /*
1983          * Double wide has implications for planes
1984          * so best keep it disabled when not needed.
1985          */
1986         if (crtc->config->double_wide)
1987                 val &= ~PIPECONF_DOUBLE_WIDE;
1988
1989         /* Don't disable pipe or pipe PLLs if needed */
1990         if (!IS_I830(dev_priv))
1991                 val &= ~PIPECONF_ENABLE;
1992
1993         I915_WRITE(reg, val);
1994         if ((val & PIPECONF_ENABLE) == 0)
1995                 intel_wait_for_pipe_off(crtc);
1996 }
1997
1998 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1999 {
2000         return IS_GEN2(dev_priv) ? 2048 : 4096;
2001 }
2002
2003 static unsigned int
2004 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2005 {
2006         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2007         unsigned int cpp = fb->format->cpp[plane];
2008
2009         switch (fb->modifier) {
2010         case DRM_FORMAT_MOD_LINEAR:
2011                 return cpp;
2012         case I915_FORMAT_MOD_X_TILED:
2013                 if (IS_GEN2(dev_priv))
2014                         return 128;
2015                 else
2016                         return 512;
2017         case I915_FORMAT_MOD_Y_TILED_CCS:
2018                 if (plane == 1)
2019                         return 128;
2020                 /* fall through */
2021         case I915_FORMAT_MOD_Y_TILED:
2022                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2023                         return 128;
2024                 else
2025                         return 512;
2026         case I915_FORMAT_MOD_Yf_TILED_CCS:
2027                 if (plane == 1)
2028                         return 128;
2029                 /* fall through */
2030         case I915_FORMAT_MOD_Yf_TILED:
2031                 switch (cpp) {
2032                 case 1:
2033                         return 64;
2034                 case 2:
2035                 case 4:
2036                         return 128;
2037                 case 8:
2038                 case 16:
2039                         return 256;
2040                 default:
2041                         MISSING_CASE(cpp);
2042                         return cpp;
2043                 }
2044                 break;
2045         default:
2046                 MISSING_CASE(fb->modifier);
2047                 return cpp;
2048         }
2049 }
2050
2051 static unsigned int
2052 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2053 {
2054         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2055                 return 1;
2056         else
2057                 return intel_tile_size(to_i915(fb->dev)) /
2058                         intel_tile_width_bytes(fb, plane);
2059 }
2060
2061 /* Return the tile dimensions in pixel units */
2062 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2063                             unsigned int *tile_width,
2064                             unsigned int *tile_height)
2065 {
2066         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2067         unsigned int cpp = fb->format->cpp[plane];
2068
2069         *tile_width = tile_width_bytes / cpp;
2070         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2071 }
2072
2073 unsigned int
2074 intel_fb_align_height(const struct drm_framebuffer *fb,
2075                       int plane, unsigned int height)
2076 {
2077         unsigned int tile_height = intel_tile_height(fb, plane);
2078
2079         return ALIGN(height, tile_height);
2080 }
2081
2082 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2083 {
2084         unsigned int size = 0;
2085         int i;
2086
2087         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2088                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2089
2090         return size;
2091 }
2092
2093 static void
2094 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2095                         const struct drm_framebuffer *fb,
2096                         unsigned int rotation)
2097 {
2098         view->type = I915_GGTT_VIEW_NORMAL;
2099         if (drm_rotation_90_or_270(rotation)) {
2100                 view->type = I915_GGTT_VIEW_ROTATED;
2101                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2102         }
2103 }
2104
2105 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2106 {
2107         if (IS_I830(dev_priv))
2108                 return 16 * 1024;
2109         else if (IS_I85X(dev_priv))
2110                 return 256;
2111         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2112                 return 32;
2113         else
2114                 return 4 * 1024;
2115 }
2116
2117 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2118 {
2119         if (INTEL_INFO(dev_priv)->gen >= 9)
2120                 return 256 * 1024;
2121         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2122                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2123                 return 128 * 1024;
2124         else if (INTEL_INFO(dev_priv)->gen >= 4)
2125                 return 4 * 1024;
2126         else
2127                 return 0;
2128 }
2129
2130 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2131                                          int plane)
2132 {
2133         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2134
2135         /* AUX_DIST needs only 4K alignment */
2136         if (plane == 1)
2137                 return 4096;
2138
2139         switch (fb->modifier) {
2140         case DRM_FORMAT_MOD_LINEAR:
2141                 return intel_linear_alignment(dev_priv);
2142         case I915_FORMAT_MOD_X_TILED:
2143                 if (INTEL_GEN(dev_priv) >= 9)
2144                         return 256 * 1024;
2145                 return 0;
2146         case I915_FORMAT_MOD_Y_TILED_CCS:
2147         case I915_FORMAT_MOD_Yf_TILED_CCS:
2148         case I915_FORMAT_MOD_Y_TILED:
2149         case I915_FORMAT_MOD_Yf_TILED:
2150                 return 1 * 1024 * 1024;
2151         default:
2152                 MISSING_CASE(fb->modifier);
2153                 return 0;
2154         }
2155 }
2156
2157 struct i915_vma *
2158 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2159 {
2160         struct drm_device *dev = fb->dev;
2161         struct drm_i915_private *dev_priv = to_i915(dev);
2162         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2163         struct i915_ggtt_view view;
2164         struct i915_vma *vma;
2165         u32 alignment;
2166
2167         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2168
2169         alignment = intel_surf_alignment(fb, 0);
2170
2171         intel_fill_fb_ggtt_view(&view, fb, rotation);
2172
2173         /* Note that the w/a also requires 64 PTE of padding following the
2174          * bo. We currently fill all unused PTE with the shadow page and so
2175          * we should always have valid PTE following the scanout preventing
2176          * the VT-d warning.
2177          */
2178         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2179                 alignment = 256 * 1024;
2180
2181         /*
2182          * Global gtt pte registers are special registers which actually forward
2183          * writes to a chunk of system memory. Which means that there is no risk
2184          * that the register values disappear as soon as we call
2185          * intel_runtime_pm_put(), so it is correct to wrap only the
2186          * pin/unpin/fence and not more.
2187          */
2188         intel_runtime_pm_get(dev_priv);
2189
2190         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2191
2192         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2193         if (IS_ERR(vma))
2194                 goto err;
2195
2196         if (i915_vma_is_map_and_fenceable(vma)) {
2197                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2198                  * fence, whereas 965+ only requires a fence if using
2199                  * framebuffer compression.  For simplicity, we always, when
2200                  * possible, install a fence as the cost is not that onerous.
2201                  *
2202                  * If we fail to fence the tiled scanout, then either the
2203                  * modeset will reject the change (which is highly unlikely as
2204                  * the affected systems, all but one, do not have unmappable
2205                  * space) or we will not be able to enable full powersaving
2206                  * techniques (also likely not to apply due to various limits
2207                  * FBC and the like impose on the size of the buffer, which
2208                  * presumably we violated anyway with this unmappable buffer).
2209                  * Anyway, it is presumably better to stumble onwards with
2210                  * something and try to run the system in a "less than optimal"
2211                  * mode that matches the user configuration.
2212                  */
2213                 i915_vma_pin_fence(vma);
2214         }
2215
2216         i915_vma_get(vma);
2217 err:
2218         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2219
2220         intel_runtime_pm_put(dev_priv);
2221         return vma;
2222 }
2223
2224 void intel_unpin_fb_vma(struct i915_vma *vma)
2225 {
2226         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2227
2228         i915_vma_unpin_fence(vma);
2229         i915_gem_object_unpin_from_display_plane(vma);
2230         i915_vma_put(vma);
2231 }
2232
2233 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2234                           unsigned int rotation)
2235 {
2236         if (drm_rotation_90_or_270(rotation))
2237                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2238         else
2239                 return fb->pitches[plane];
2240 }
2241
2242 /*
2243  * Convert the x/y offsets into a linear offset.
2244  * Only valid with 0/180 degree rotation, which is fine since linear
2245  * offset is only used with linear buffers on pre-hsw and tiled buffers
2246  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2247  */
2248 u32 intel_fb_xy_to_linear(int x, int y,
2249                           const struct intel_plane_state *state,
2250                           int plane)
2251 {
2252         const struct drm_framebuffer *fb = state->base.fb;
2253         unsigned int cpp = fb->format->cpp[plane];
2254         unsigned int pitch = fb->pitches[plane];
2255
2256         return y * pitch + x * cpp;
2257 }
2258
2259 /*
2260  * Add the x/y offsets derived from fb->offsets[] to the user
2261  * specified plane src x/y offsets. The resulting x/y offsets
2262  * specify the start of scanout from the beginning of the gtt mapping.
2263  */
2264 void intel_add_fb_offsets(int *x, int *y,
2265                           const struct intel_plane_state *state,
2266                           int plane)
2267
2268 {
2269         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2270         unsigned int rotation = state->base.rotation;
2271
2272         if (drm_rotation_90_or_270(rotation)) {
2273                 *x += intel_fb->rotated[plane].x;
2274                 *y += intel_fb->rotated[plane].y;
2275         } else {
2276                 *x += intel_fb->normal[plane].x;
2277                 *y += intel_fb->normal[plane].y;
2278         }
2279 }
2280
2281 static u32 __intel_adjust_tile_offset(int *x, int *y,
2282                                       unsigned int tile_width,
2283                                       unsigned int tile_height,
2284                                       unsigned int tile_size,
2285                                       unsigned int pitch_tiles,
2286                                       u32 old_offset,
2287                                       u32 new_offset)
2288 {
2289         unsigned int pitch_pixels = pitch_tiles * tile_width;
2290         unsigned int tiles;
2291
2292         WARN_ON(old_offset & (tile_size - 1));
2293         WARN_ON(new_offset & (tile_size - 1));
2294         WARN_ON(new_offset > old_offset);
2295
2296         tiles = (old_offset - new_offset) / tile_size;
2297
2298         *y += tiles / pitch_tiles * tile_height;
2299         *x += tiles % pitch_tiles * tile_width;
2300
2301         /* minimize x in case it got needlessly big */
2302         *y += *x / pitch_pixels * tile_height;
2303         *x %= pitch_pixels;
2304
2305         return new_offset;
2306 }
2307
2308 static u32 _intel_adjust_tile_offset(int *x, int *y,
2309                                      const struct drm_framebuffer *fb, int plane,
2310                                      unsigned int rotation,
2311                                      u32 old_offset, u32 new_offset)
2312 {
2313         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2314         unsigned int cpp = fb->format->cpp[plane];
2315         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2316
2317         WARN_ON(new_offset > old_offset);
2318
2319         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2320                 unsigned int tile_size, tile_width, tile_height;
2321                 unsigned int pitch_tiles;
2322
2323                 tile_size = intel_tile_size(dev_priv);
2324                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2325
2326                 if (drm_rotation_90_or_270(rotation)) {
2327                         pitch_tiles = pitch / tile_height;
2328                         swap(tile_width, tile_height);
2329                 } else {
2330                         pitch_tiles = pitch / (tile_width * cpp);
2331                 }
2332
2333                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2334                                            tile_size, pitch_tiles,
2335                                            old_offset, new_offset);
2336         } else {
2337                 old_offset += *y * pitch + *x * cpp;
2338
2339                 *y = (old_offset - new_offset) / pitch;
2340                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2341         }
2342
2343         return new_offset;
2344 }
2345
2346 /*
2347  * Adjust the tile offset by moving the difference into
2348  * the x/y offsets.
2349  */
2350 static u32 intel_adjust_tile_offset(int *x, int *y,
2351                                     const struct intel_plane_state *state, int plane,
2352                                     u32 old_offset, u32 new_offset)
2353 {
2354         return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2355                                          state->base.rotation,
2356                                          old_offset, new_offset);
2357 }
2358
2359 /*
2360  * Computes the linear offset to the base tile and adjusts
2361  * x, y. bytes per pixel is assumed to be a power-of-two.
2362  *
2363  * In the 90/270 rotated case, x and y are assumed
2364  * to be already rotated to match the rotated GTT view, and
2365  * pitch is the tile_height aligned framebuffer height.
2366  *
2367  * This function is used when computing the derived information
2368  * under intel_framebuffer, so using any of that information
2369  * here is not allowed. Anything under drm_framebuffer can be
2370  * used. This is why the user has to pass in the pitch since it
2371  * is specified in the rotated orientation.
2372  */
2373 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2374                                       int *x, int *y,
2375                                       const struct drm_framebuffer *fb, int plane,
2376                                       unsigned int pitch,
2377                                       unsigned int rotation,
2378                                       u32 alignment)
2379 {
2380         uint64_t fb_modifier = fb->modifier;
2381         unsigned int cpp = fb->format->cpp[plane];
2382         u32 offset, offset_aligned;
2383
2384         if (alignment)
2385                 alignment--;
2386
2387         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2388                 unsigned int tile_size, tile_width, tile_height;
2389                 unsigned int tile_rows, tiles, pitch_tiles;
2390
2391                 tile_size = intel_tile_size(dev_priv);
2392                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2393
2394                 if (drm_rotation_90_or_270(rotation)) {
2395                         pitch_tiles = pitch / tile_height;
2396                         swap(tile_width, tile_height);
2397                 } else {
2398                         pitch_tiles = pitch / (tile_width * cpp);
2399                 }
2400
2401                 tile_rows = *y / tile_height;
2402                 *y %= tile_height;
2403
2404                 tiles = *x / tile_width;
2405                 *x %= tile_width;
2406
2407                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2408                 offset_aligned = offset & ~alignment;
2409
2410                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2411                                            tile_size, pitch_tiles,
2412                                            offset, offset_aligned);
2413         } else {
2414                 offset = *y * pitch + *x * cpp;
2415                 offset_aligned = offset & ~alignment;
2416
2417                 *y = (offset & alignment) / pitch;
2418                 *x = ((offset & alignment) - *y * pitch) / cpp;
2419         }
2420
2421         return offset_aligned;
2422 }
2423
2424 u32 intel_compute_tile_offset(int *x, int *y,
2425                               const struct intel_plane_state *state,
2426                               int plane)
2427 {
2428         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2429         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2430         const struct drm_framebuffer *fb = state->base.fb;
2431         unsigned int rotation = state->base.rotation;
2432         int pitch = intel_fb_pitch(fb, plane, rotation);
2433         u32 alignment;
2434
2435         if (intel_plane->id == PLANE_CURSOR)
2436                 alignment = intel_cursor_alignment(dev_priv);
2437         else
2438                 alignment = intel_surf_alignment(fb, plane);
2439
2440         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2441                                           rotation, alignment);
2442 }
2443
2444 /* Convert the fb->offset[] into x/y offsets */
2445 static int intel_fb_offset_to_xy(int *x, int *y,
2446                                  const struct drm_framebuffer *fb, int plane)
2447 {
2448         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2449
2450         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2451             fb->offsets[plane] % intel_tile_size(dev_priv))
2452                 return -EINVAL;
2453
2454         *x = 0;
2455         *y = 0;
2456
2457         _intel_adjust_tile_offset(x, y,
2458                                   fb, plane, DRM_MODE_ROTATE_0,
2459                                   fb->offsets[plane], 0);
2460
2461         return 0;
2462 }
2463
2464 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2465 {
2466         switch (fb_modifier) {
2467         case I915_FORMAT_MOD_X_TILED:
2468                 return I915_TILING_X;
2469         case I915_FORMAT_MOD_Y_TILED:
2470         case I915_FORMAT_MOD_Y_TILED_CCS:
2471                 return I915_TILING_Y;
2472         default:
2473                 return I915_TILING_NONE;
2474         }
2475 }
2476
2477 static const struct drm_format_info ccs_formats[] = {
2478         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2479         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2480         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2481         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2482 };
2483
2484 static const struct drm_format_info *
2485 lookup_format_info(const struct drm_format_info formats[],
2486                    int num_formats, u32 format)
2487 {
2488         int i;
2489
2490         for (i = 0; i < num_formats; i++) {
2491                 if (formats[i].format == format)
2492                         return &formats[i];
2493         }
2494
2495         return NULL;
2496 }
2497
2498 static const struct drm_format_info *
2499 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2500 {
2501         switch (cmd->modifier[0]) {
2502         case I915_FORMAT_MOD_Y_TILED_CCS:
2503         case I915_FORMAT_MOD_Yf_TILED_CCS:
2504                 return lookup_format_info(ccs_formats,
2505                                           ARRAY_SIZE(ccs_formats),
2506                                           cmd->pixel_format);
2507         default:
2508                 return NULL;
2509         }
2510 }
2511
2512 static int
2513 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2514                    struct drm_framebuffer *fb)
2515 {
2516         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2517         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2518         u32 gtt_offset_rotated = 0;
2519         unsigned int max_size = 0;
2520         int i, num_planes = fb->format->num_planes;
2521         unsigned int tile_size = intel_tile_size(dev_priv);
2522
2523         for (i = 0; i < num_planes; i++) {
2524                 unsigned int width, height;
2525                 unsigned int cpp, size;
2526                 u32 offset;
2527                 int x, y;
2528                 int ret;
2529
2530                 cpp = fb->format->cpp[i];
2531                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2532                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2533
2534                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2535                 if (ret) {
2536                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2537                                       i, fb->offsets[i]);
2538                         return ret;
2539                 }
2540
2541                 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2542                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2543                         int hsub = fb->format->hsub;
2544                         int vsub = fb->format->vsub;
2545                         int tile_width, tile_height;
2546                         int main_x, main_y;
2547                         int ccs_x, ccs_y;
2548
2549                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2550                         tile_width *= hsub;
2551                         tile_height *= vsub;
2552
2553                         ccs_x = (x * hsub) % tile_width;
2554                         ccs_y = (y * vsub) % tile_height;
2555                         main_x = intel_fb->normal[0].x % tile_width;
2556                         main_y = intel_fb->normal[0].y % tile_height;
2557
2558                         /*
2559                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2560                          * x/y offsets must match between CCS and the main surface.
2561                          */
2562                         if (main_x != ccs_x || main_y != ccs_y) {
2563                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2564                                               main_x, main_y,
2565                                               ccs_x, ccs_y,
2566                                               intel_fb->normal[0].x,
2567                                               intel_fb->normal[0].y,
2568                                               x, y);
2569                                 return -EINVAL;
2570                         }
2571                 }
2572
2573                 /*
2574                  * The fence (if used) is aligned to the start of the object
2575                  * so having the framebuffer wrap around across the edge of the
2576                  * fenced region doesn't really work. We have no API to configure
2577                  * the fence start offset within the object (nor could we probably
2578                  * on gen2/3). So it's just easier if we just require that the
2579                  * fb layout agrees with the fence layout. We already check that the
2580                  * fb stride matches the fence stride elsewhere.
2581                  */
2582                 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2583                     (x + width) * cpp > fb->pitches[i]) {
2584                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2585                                       i, fb->offsets[i]);
2586                         return -EINVAL;
2587                 }
2588
2589                 /*
2590                  * First pixel of the framebuffer from
2591                  * the start of the normal gtt mapping.
2592                  */
2593                 intel_fb->normal[i].x = x;
2594                 intel_fb->normal[i].y = y;
2595
2596                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2597                                                     fb, i, fb->pitches[i],
2598                                                     DRM_MODE_ROTATE_0, tile_size);
2599                 offset /= tile_size;
2600
2601                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2602                         unsigned int tile_width, tile_height;
2603                         unsigned int pitch_tiles;
2604                         struct drm_rect r;
2605
2606                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2607
2608                         rot_info->plane[i].offset = offset;
2609                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2610                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2611                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2612
2613                         intel_fb->rotated[i].pitch =
2614                                 rot_info->plane[i].height * tile_height;
2615
2616                         /* how many tiles does this plane need */
2617                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2618                         /*
2619                          * If the plane isn't horizontally tile aligned,
2620                          * we need one more tile.
2621                          */
2622                         if (x != 0)
2623                                 size++;
2624
2625                         /* rotate the x/y offsets to match the GTT view */
2626                         r.x1 = x;
2627                         r.y1 = y;
2628                         r.x2 = x + width;
2629                         r.y2 = y + height;
2630                         drm_rect_rotate(&r,
2631                                         rot_info->plane[i].width * tile_width,
2632                                         rot_info->plane[i].height * tile_height,
2633                                         DRM_MODE_ROTATE_270);
2634                         x = r.x1;
2635                         y = r.y1;
2636
2637                         /* rotate the tile dimensions to match the GTT view */
2638                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2639                         swap(tile_width, tile_height);
2640
2641                         /*
2642                          * We only keep the x/y offsets, so push all of the
2643                          * gtt offset into the x/y offsets.
2644                          */
2645                         __intel_adjust_tile_offset(&x, &y,
2646                                                    tile_width, tile_height,
2647                                                    tile_size, pitch_tiles,
2648                                                    gtt_offset_rotated * tile_size, 0);
2649
2650                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2651
2652                         /*
2653                          * First pixel of the framebuffer from
2654                          * the start of the rotated gtt mapping.
2655                          */
2656                         intel_fb->rotated[i].x = x;
2657                         intel_fb->rotated[i].y = y;
2658                 } else {
2659                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2660                                             x * cpp, tile_size);
2661                 }
2662
2663                 /* how many tiles in total needed in the bo */
2664                 max_size = max(max_size, offset + size);
2665         }
2666
2667         if (max_size * tile_size > intel_fb->obj->base.size) {
2668                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2669                               max_size * tile_size, intel_fb->obj->base.size);
2670                 return -EINVAL;
2671         }
2672
2673         return 0;
2674 }
2675
2676 static int i9xx_format_to_fourcc(int format)
2677 {
2678         switch (format) {
2679         case DISPPLANE_8BPP:
2680                 return DRM_FORMAT_C8;
2681         case DISPPLANE_BGRX555:
2682                 return DRM_FORMAT_XRGB1555;
2683         case DISPPLANE_BGRX565:
2684                 return DRM_FORMAT_RGB565;
2685         default:
2686         case DISPPLANE_BGRX888:
2687                 return DRM_FORMAT_XRGB8888;
2688         case DISPPLANE_RGBX888:
2689                 return DRM_FORMAT_XBGR8888;
2690         case DISPPLANE_BGRX101010:
2691                 return DRM_FORMAT_XRGB2101010;
2692         case DISPPLANE_RGBX101010:
2693                 return DRM_FORMAT_XBGR2101010;
2694         }
2695 }
2696
2697 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2698 {
2699         switch (format) {
2700         case PLANE_CTL_FORMAT_RGB_565:
2701                 return DRM_FORMAT_RGB565;
2702         default:
2703         case PLANE_CTL_FORMAT_XRGB_8888:
2704                 if (rgb_order) {
2705                         if (alpha)
2706                                 return DRM_FORMAT_ABGR8888;
2707                         else
2708                                 return DRM_FORMAT_XBGR8888;
2709                 } else {
2710                         if (alpha)
2711                                 return DRM_FORMAT_ARGB8888;
2712                         else
2713                                 return DRM_FORMAT_XRGB8888;
2714                 }
2715         case PLANE_CTL_FORMAT_XRGB_2101010:
2716                 if (rgb_order)
2717                         return DRM_FORMAT_XBGR2101010;
2718                 else
2719                         return DRM_FORMAT_XRGB2101010;
2720         }
2721 }
2722
2723 static bool
2724 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2725                               struct intel_initial_plane_config *plane_config)
2726 {
2727         struct drm_device *dev = crtc->base.dev;
2728         struct drm_i915_private *dev_priv = to_i915(dev);
2729         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2730         struct drm_i915_gem_object *obj = NULL;
2731         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2732         struct drm_framebuffer *fb = &plane_config->fb->base;
2733         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2734         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2735                                     PAGE_SIZE);
2736
2737         size_aligned -= base_aligned;
2738
2739         if (plane_config->size == 0)
2740                 return false;
2741
2742         /* If the FB is too big, just don't use it since fbdev is not very
2743          * important and we should probably use that space with FBC or other
2744          * features. */
2745         if (size_aligned * 2 > ggtt->stolen_usable_size)
2746                 return false;
2747
2748         mutex_lock(&dev->struct_mutex);
2749         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2750                                                              base_aligned,
2751                                                              base_aligned,
2752                                                              size_aligned);
2753         mutex_unlock(&dev->struct_mutex);
2754         if (!obj)
2755                 return false;
2756
2757         if (plane_config->tiling == I915_TILING_X)
2758                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2759
2760         mode_cmd.pixel_format = fb->format->format;
2761         mode_cmd.width = fb->width;
2762         mode_cmd.height = fb->height;
2763         mode_cmd.pitches[0] = fb->pitches[0];
2764         mode_cmd.modifier[0] = fb->modifier;
2765         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2766
2767         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2768                 DRM_DEBUG_KMS("intel fb init failed\n");
2769                 goto out_unref_obj;
2770         }
2771
2772
2773         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2774         return true;
2775
2776 out_unref_obj:
2777         i915_gem_object_put(obj);
2778         return false;
2779 }
2780
2781 static void
2782 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2783                         struct intel_plane_state *plane_state,
2784                         bool visible)
2785 {
2786         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2787
2788         plane_state->base.visible = visible;
2789
2790         /* FIXME pre-g4x don't work like this */
2791         if (visible) {
2792                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2793                 crtc_state->active_planes |= BIT(plane->id);
2794         } else {
2795                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2796                 crtc_state->active_planes &= ~BIT(plane->id);
2797         }
2798
2799         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2800                       crtc_state->base.crtc->name,
2801                       crtc_state->active_planes);
2802 }
2803
2804 static void
2805 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2806                              struct intel_initial_plane_config *plane_config)
2807 {
2808         struct drm_device *dev = intel_crtc->base.dev;
2809         struct drm_i915_private *dev_priv = to_i915(dev);
2810         struct drm_crtc *c;
2811         struct drm_i915_gem_object *obj;
2812         struct drm_plane *primary = intel_crtc->base.primary;
2813         struct drm_plane_state *plane_state = primary->state;
2814         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2815         struct intel_plane *intel_plane = to_intel_plane(primary);
2816         struct intel_plane_state *intel_state =
2817                 to_intel_plane_state(plane_state);
2818         struct drm_framebuffer *fb;
2819
2820         if (!plane_config->fb)
2821                 return;
2822
2823         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2824                 fb = &plane_config->fb->base;
2825                 goto valid_fb;
2826         }
2827
2828         kfree(plane_config->fb);
2829
2830         /*
2831          * Failed to alloc the obj, check to see if we should share
2832          * an fb with another CRTC instead
2833          */
2834         for_each_crtc(dev, c) {
2835                 struct intel_plane_state *state;
2836
2837                 if (c == &intel_crtc->base)
2838                         continue;
2839
2840                 if (!to_intel_crtc(c)->active)
2841                         continue;
2842
2843                 state = to_intel_plane_state(c->primary->state);
2844                 if (!state->vma)
2845                         continue;
2846
2847                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2848                         fb = c->primary->fb;
2849                         drm_framebuffer_get(fb);
2850                         goto valid_fb;
2851                 }
2852         }
2853
2854         /*
2855          * We've failed to reconstruct the BIOS FB.  Current display state
2856          * indicates that the primary plane is visible, but has a NULL FB,
2857          * which will lead to problems later if we don't fix it up.  The
2858          * simplest solution is to just disable the primary plane now and
2859          * pretend the BIOS never had it enabled.
2860          */
2861         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2862                                 to_intel_plane_state(plane_state),
2863                                 false);
2864         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2865         trace_intel_disable_plane(primary, intel_crtc);
2866         intel_plane->disable_plane(intel_plane, intel_crtc);
2867
2868         return;
2869
2870 valid_fb:
2871         mutex_lock(&dev->struct_mutex);
2872         intel_state->vma =
2873                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2874         mutex_unlock(&dev->struct_mutex);
2875         if (IS_ERR(intel_state->vma)) {
2876                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2877                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2878
2879                 intel_state->vma = NULL;
2880                 drm_framebuffer_put(fb);
2881                 return;
2882         }
2883
2884         plane_state->src_x = 0;
2885         plane_state->src_y = 0;
2886         plane_state->src_w = fb->width << 16;
2887         plane_state->src_h = fb->height << 16;
2888
2889         plane_state->crtc_x = 0;
2890         plane_state->crtc_y = 0;
2891         plane_state->crtc_w = fb->width;
2892         plane_state->crtc_h = fb->height;
2893
2894         intel_state->base.src = drm_plane_state_src(plane_state);
2895         intel_state->base.dst = drm_plane_state_dest(plane_state);
2896
2897         obj = intel_fb_obj(fb);
2898         if (i915_gem_object_is_tiled(obj))
2899                 dev_priv->preserve_bios_swizzle = true;
2900
2901         drm_framebuffer_get(fb);
2902         primary->fb = primary->state->fb = fb;
2903         primary->crtc = primary->state->crtc = &intel_crtc->base;
2904
2905         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2906                                 to_intel_plane_state(plane_state),
2907                                 true);
2908
2909         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2910                   &obj->frontbuffer_bits);
2911 }
2912
2913 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2914                                unsigned int rotation)
2915 {
2916         int cpp = fb->format->cpp[plane];
2917
2918         switch (fb->modifier) {
2919         case DRM_FORMAT_MOD_LINEAR:
2920         case I915_FORMAT_MOD_X_TILED:
2921                 switch (cpp) {
2922                 case 8:
2923                         return 4096;
2924                 case 4:
2925                 case 2:
2926                 case 1:
2927                         return 8192;
2928                 default:
2929                         MISSING_CASE(cpp);
2930                         break;
2931                 }
2932                 break;
2933         case I915_FORMAT_MOD_Y_TILED_CCS:
2934         case I915_FORMAT_MOD_Yf_TILED_CCS:
2935                 /* FIXME AUX plane? */
2936         case I915_FORMAT_MOD_Y_TILED:
2937         case I915_FORMAT_MOD_Yf_TILED:
2938                 switch (cpp) {
2939                 case 8:
2940                         return 2048;
2941                 case 4:
2942                         return 4096;
2943                 case 2:
2944                 case 1:
2945                         return 8192;
2946                 default:
2947                         MISSING_CASE(cpp);
2948                         break;
2949                 }
2950                 break;
2951         default:
2952                 MISSING_CASE(fb->modifier);
2953         }
2954
2955         return 2048;
2956 }
2957
2958 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2959                                            int main_x, int main_y, u32 main_offset)
2960 {
2961         const struct drm_framebuffer *fb = plane_state->base.fb;
2962         int hsub = fb->format->hsub;
2963         int vsub = fb->format->vsub;
2964         int aux_x = plane_state->aux.x;
2965         int aux_y = plane_state->aux.y;
2966         u32 aux_offset = plane_state->aux.offset;
2967         u32 alignment = intel_surf_alignment(fb, 1);
2968
2969         while (aux_offset >= main_offset && aux_y <= main_y) {
2970                 int x, y;
2971
2972                 if (aux_x == main_x && aux_y == main_y)
2973                         break;
2974
2975                 if (aux_offset == 0)
2976                         break;
2977
2978                 x = aux_x / hsub;
2979                 y = aux_y / vsub;
2980                 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2981                                                       aux_offset, aux_offset - alignment);
2982                 aux_x = x * hsub + aux_x % hsub;
2983                 aux_y = y * vsub + aux_y % vsub;
2984         }
2985
2986         if (aux_x != main_x || aux_y != main_y)
2987                 return false;
2988
2989         plane_state->aux.offset = aux_offset;
2990         plane_state->aux.x = aux_x;
2991         plane_state->aux.y = aux_y;
2992
2993         return true;
2994 }
2995
2996 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2997 {
2998         const struct drm_framebuffer *fb = plane_state->base.fb;
2999         unsigned int rotation = plane_state->base.rotation;
3000         int x = plane_state->base.src.x1 >> 16;
3001         int y = plane_state->base.src.y1 >> 16;
3002         int w = drm_rect_width(&plane_state->base.src) >> 16;
3003         int h = drm_rect_height(&plane_state->base.src) >> 16;
3004         int max_width = skl_max_plane_width(fb, 0, rotation);
3005         int max_height = 4096;
3006         u32 alignment, offset, aux_offset = plane_state->aux.offset;
3007
3008         if (w > max_width || h > max_height) {
3009                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3010                               w, h, max_width, max_height);
3011                 return -EINVAL;
3012         }
3013
3014         intel_add_fb_offsets(&x, &y, plane_state, 0);
3015         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3016         alignment = intel_surf_alignment(fb, 0);
3017
3018         /*
3019          * AUX surface offset is specified as the distance from the
3020          * main surface offset, and it must be non-negative. Make
3021          * sure that is what we will get.
3022          */
3023         if (offset > aux_offset)
3024                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3025                                                   offset, aux_offset & ~(alignment - 1));
3026
3027         /*
3028          * When using an X-tiled surface, the plane blows up
3029          * if the x offset + width exceed the stride.
3030          *
3031          * TODO: linear and Y-tiled seem fine, Yf untested,
3032          */
3033         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3034                 int cpp = fb->format->cpp[0];
3035
3036                 while ((x + w) * cpp > fb->pitches[0]) {
3037                         if (offset == 0) {
3038                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3039                                 return -EINVAL;
3040                         }
3041
3042                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3043                                                           offset, offset - alignment);
3044                 }
3045         }
3046
3047         /*
3048          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3049          * they match with the main surface x/y offsets.
3050          */
3051         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3052             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3053                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3054                         if (offset == 0)
3055                                 break;
3056
3057                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3058                                                           offset, offset - alignment);
3059                 }
3060
3061                 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3062                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3063                         return -EINVAL;
3064                 }
3065         }
3066
3067         plane_state->main.offset = offset;
3068         plane_state->main.x = x;
3069         plane_state->main.y = y;
3070
3071         return 0;
3072 }
3073
3074 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3075 {
3076         const struct drm_framebuffer *fb = plane_state->base.fb;
3077         unsigned int rotation = plane_state->base.rotation;
3078         int max_width = skl_max_plane_width(fb, 1, rotation);
3079         int max_height = 4096;
3080         int x = plane_state->base.src.x1 >> 17;
3081         int y = plane_state->base.src.y1 >> 17;
3082         int w = drm_rect_width(&plane_state->base.src) >> 17;
3083         int h = drm_rect_height(&plane_state->base.src) >> 17;
3084         u32 offset;
3085
3086         intel_add_fb_offsets(&x, &y, plane_state, 1);
3087         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3088
3089         /* FIXME not quite sure how/if these apply to the chroma plane */
3090         if (w > max_width || h > max_height) {
3091                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3092                               w, h, max_width, max_height);
3093                 return -EINVAL;
3094         }
3095
3096         plane_state->aux.offset = offset;
3097         plane_state->aux.x = x;
3098         plane_state->aux.y = y;
3099
3100         return 0;
3101 }
3102
3103 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3104 {
3105         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3106         struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3107         const struct drm_framebuffer *fb = plane_state->base.fb;
3108         int src_x = plane_state->base.src.x1 >> 16;
3109         int src_y = plane_state->base.src.y1 >> 16;
3110         int hsub = fb->format->hsub;
3111         int vsub = fb->format->vsub;
3112         int x = src_x / hsub;
3113         int y = src_y / vsub;
3114         u32 offset;
3115
3116         switch (plane->id) {
3117         case PLANE_PRIMARY:
3118         case PLANE_SPRITE0:
3119                 break;
3120         default:
3121                 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3122                 return -EINVAL;
3123         }
3124
3125         if (crtc->pipe == PIPE_C) {
3126                 DRM_DEBUG_KMS("No RC support on pipe C\n");
3127                 return -EINVAL;
3128         }
3129
3130         if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3131                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3132                               plane_state->base.rotation);
3133                 return -EINVAL;
3134         }
3135
3136         intel_add_fb_offsets(&x, &y, plane_state, 1);
3137         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3138
3139         plane_state->aux.offset = offset;
3140         plane_state->aux.x = x * hsub + src_x % hsub;
3141         plane_state->aux.y = y * vsub + src_y % vsub;
3142
3143         return 0;
3144 }
3145
3146 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3147 {
3148         const struct drm_framebuffer *fb = plane_state->base.fb;
3149         unsigned int rotation = plane_state->base.rotation;
3150         int ret;
3151
3152         if (!plane_state->base.visible)
3153                 return 0;
3154
3155         /* Rotate src coordinates to match rotated GTT view */
3156         if (drm_rotation_90_or_270(rotation))
3157                 drm_rect_rotate(&plane_state->base.src,
3158                                 fb->width << 16, fb->height << 16,
3159                                 DRM_MODE_ROTATE_270);
3160
3161         /*
3162          * Handle the AUX surface first since
3163          * the main surface setup depends on it.
3164          */
3165         if (fb->format->format == DRM_FORMAT_NV12) {
3166                 ret = skl_check_nv12_aux_surface(plane_state);
3167                 if (ret)
3168                         return ret;
3169         } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3170                    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3171                 ret = skl_check_ccs_aux_surface(plane_state);
3172                 if (ret)
3173                         return ret;
3174         } else {
3175                 plane_state->aux.offset = ~0xfff;
3176                 plane_state->aux.x = 0;
3177                 plane_state->aux.y = 0;
3178         }
3179
3180         ret = skl_check_main_surface(plane_state);
3181         if (ret)
3182                 return ret;
3183
3184         return 0;
3185 }
3186
3187 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3188                           const struct intel_plane_state *plane_state)
3189 {
3190         struct drm_i915_private *dev_priv =
3191                 to_i915(plane_state->base.plane->dev);
3192         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3193         const struct drm_framebuffer *fb = plane_state->base.fb;
3194         unsigned int rotation = plane_state->base.rotation;
3195         u32 dspcntr;
3196
3197         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3198
3199         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3200             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3201                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3202
3203         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3204                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3205
3206         if (INTEL_GEN(dev_priv) < 4)
3207                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3208
3209         switch (fb->format->format) {
3210         case DRM_FORMAT_C8:
3211                 dspcntr |= DISPPLANE_8BPP;
3212                 break;
3213         case DRM_FORMAT_XRGB1555:
3214                 dspcntr |= DISPPLANE_BGRX555;
3215                 break;
3216         case DRM_FORMAT_RGB565:
3217                 dspcntr |= DISPPLANE_BGRX565;
3218                 break;
3219         case DRM_FORMAT_XRGB8888:
3220                 dspcntr |= DISPPLANE_BGRX888;
3221                 break;
3222         case DRM_FORMAT_XBGR8888:
3223                 dspcntr |= DISPPLANE_RGBX888;
3224                 break;
3225         case DRM_FORMAT_XRGB2101010:
3226                 dspcntr |= DISPPLANE_BGRX101010;
3227                 break;
3228         case DRM_FORMAT_XBGR2101010:
3229                 dspcntr |= DISPPLANE_RGBX101010;
3230                 break;
3231         default:
3232                 MISSING_CASE(fb->format->format);
3233                 return 0;
3234         }
3235
3236         if (INTEL_GEN(dev_priv) >= 4 &&
3237             fb->modifier == I915_FORMAT_MOD_X_TILED)
3238                 dspcntr |= DISPPLANE_TILED;
3239
3240         if (rotation & DRM_MODE_ROTATE_180)
3241                 dspcntr |= DISPPLANE_ROTATE_180;
3242
3243         if (rotation & DRM_MODE_REFLECT_X)
3244                 dspcntr |= DISPPLANE_MIRROR;
3245
3246         return dspcntr;
3247 }
3248
3249 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3250 {
3251         struct drm_i915_private *dev_priv =
3252                 to_i915(plane_state->base.plane->dev);
3253         int src_x = plane_state->base.src.x1 >> 16;
3254         int src_y = plane_state->base.src.y1 >> 16;
3255         u32 offset;
3256
3257         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3258
3259         if (INTEL_GEN(dev_priv) >= 4)
3260                 offset = intel_compute_tile_offset(&src_x, &src_y,
3261                                                    plane_state, 0);
3262         else
3263                 offset = 0;
3264
3265         /* HSW/BDW do this automagically in hardware */
3266         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3267                 unsigned int rotation = plane_state->base.rotation;
3268                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3269                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3270
3271                 if (rotation & DRM_MODE_ROTATE_180) {
3272                         src_x += src_w - 1;
3273                         src_y += src_h - 1;
3274                 } else if (rotation & DRM_MODE_REFLECT_X) {
3275                         src_x += src_w - 1;
3276                 }
3277         }
3278
3279         plane_state->main.offset = offset;
3280         plane_state->main.x = src_x;
3281         plane_state->main.y = src_y;
3282
3283         return 0;
3284 }
3285
3286 static void i9xx_update_primary_plane(struct intel_plane *primary,
3287                                       const struct intel_crtc_state *crtc_state,
3288                                       const struct intel_plane_state *plane_state)
3289 {
3290         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3291         const struct drm_framebuffer *fb = plane_state->base.fb;
3292         enum plane plane = primary->plane;
3293         u32 linear_offset;
3294         u32 dspcntr = plane_state->ctl;
3295         i915_reg_t reg = DSPCNTR(plane);
3296         int x = plane_state->main.x;
3297         int y = plane_state->main.y;
3298         unsigned long irqflags;
3299         u32 dspaddr_offset;
3300
3301         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3302
3303         if (INTEL_GEN(dev_priv) >= 4)
3304                 dspaddr_offset = plane_state->main.offset;
3305         else
3306                 dspaddr_offset = linear_offset;
3307
3308         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3309
3310         if (INTEL_GEN(dev_priv) < 4) {
3311                 /* pipesrc and dspsize control the size that is scaled from,
3312                  * which should always be the user's requested size.
3313                  */
3314                 I915_WRITE_FW(DSPSIZE(plane),
3315                               ((crtc_state->pipe_src_h - 1) << 16) |
3316                               (crtc_state->pipe_src_w - 1));
3317                 I915_WRITE_FW(DSPPOS(plane), 0);
3318         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3319                 I915_WRITE_FW(PRIMSIZE(plane),
3320                               ((crtc_state->pipe_src_h - 1) << 16) |
3321                               (crtc_state->pipe_src_w - 1));
3322                 I915_WRITE_FW(PRIMPOS(plane), 0);
3323                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3324         }
3325
3326         I915_WRITE_FW(reg, dspcntr);
3327
3328         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3329         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3330                 I915_WRITE_FW(DSPSURF(plane),
3331                               intel_plane_ggtt_offset(plane_state) +
3332                               dspaddr_offset);
3333                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3334         } else if (INTEL_GEN(dev_priv) >= 4) {
3335                 I915_WRITE_FW(DSPSURF(plane),
3336                               intel_plane_ggtt_offset(plane_state) +
3337                               dspaddr_offset);
3338                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3339                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3340         } else {
3341                 I915_WRITE_FW(DSPADDR(plane),
3342                               intel_plane_ggtt_offset(plane_state) +
3343                               dspaddr_offset);
3344         }
3345         POSTING_READ_FW(reg);
3346
3347         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3348 }
3349
3350 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3351                                        struct intel_crtc *crtc)
3352 {
3353         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3354         enum plane plane = primary->plane;
3355         unsigned long irqflags;
3356
3357         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3358
3359         I915_WRITE_FW(DSPCNTR(plane), 0);
3360         if (INTEL_INFO(dev_priv)->gen >= 4)
3361                 I915_WRITE_FW(DSPSURF(plane), 0);
3362         else
3363                 I915_WRITE_FW(DSPADDR(plane), 0);
3364         POSTING_READ_FW(DSPCNTR(plane));
3365
3366         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3367 }
3368
3369 static u32
3370 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3371 {
3372         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3373                 return 64;
3374         else
3375                 return intel_tile_width_bytes(fb, plane);
3376 }
3377
3378 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3379 {
3380         struct drm_device *dev = intel_crtc->base.dev;
3381         struct drm_i915_private *dev_priv = to_i915(dev);
3382
3383         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3384         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3385         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3386 }
3387
3388 /*
3389  * This function detaches (aka. unbinds) unused scalers in hardware
3390  */
3391 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3392 {
3393         struct intel_crtc_scaler_state *scaler_state;
3394         int i;
3395
3396         scaler_state = &intel_crtc->config->scaler_state;
3397
3398         /* loop through and disable scalers that aren't in use */
3399         for (i = 0; i < intel_crtc->num_scalers; i++) {
3400                 if (!scaler_state->scalers[i].in_use)
3401                         skl_detach_scaler(intel_crtc, i);
3402         }
3403 }
3404
3405 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3406                      unsigned int rotation)
3407 {
3408         u32 stride;
3409
3410         if (plane >= fb->format->num_planes)
3411                 return 0;
3412
3413         stride = intel_fb_pitch(fb, plane, rotation);
3414
3415         /*
3416          * The stride is either expressed as a multiple of 64 bytes chunks for
3417          * linear buffers or in number of tiles for tiled buffers.
3418          */
3419         if (drm_rotation_90_or_270(rotation))
3420                 stride /= intel_tile_height(fb, plane);
3421         else
3422                 stride /= intel_fb_stride_alignment(fb, plane);
3423
3424         return stride;
3425 }
3426
3427 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3428 {
3429         switch (pixel_format) {
3430         case DRM_FORMAT_C8:
3431                 return PLANE_CTL_FORMAT_INDEXED;
3432         case DRM_FORMAT_RGB565:
3433                 return PLANE_CTL_FORMAT_RGB_565;
3434         case DRM_FORMAT_XBGR8888:
3435         case DRM_FORMAT_ABGR8888:
3436                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3437         case DRM_FORMAT_XRGB8888:
3438         case DRM_FORMAT_ARGB8888:
3439                 return PLANE_CTL_FORMAT_XRGB_8888;
3440         case DRM_FORMAT_XRGB2101010:
3441                 return PLANE_CTL_FORMAT_XRGB_2101010;
3442         case DRM_FORMAT_XBGR2101010:
3443                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3444         case DRM_FORMAT_YUYV:
3445                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3446         case DRM_FORMAT_YVYU:
3447                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3448         case DRM_FORMAT_UYVY:
3449                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3450         case DRM_FORMAT_VYUY:
3451                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3452         default:
3453                 MISSING_CASE(pixel_format);
3454         }
3455
3456         return 0;
3457 }
3458
3459 /*
3460  * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3461  * to be already pre-multiplied. We need to add a knob (or a different
3462  * DRM_FORMAT) for user-space to configure that.
3463  */
3464 static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3465 {
3466         switch (pixel_format) {
3467         case DRM_FORMAT_ABGR8888:
3468         case DRM_FORMAT_ARGB8888:
3469                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3470         default:
3471                 return PLANE_CTL_ALPHA_DISABLE;
3472         }
3473 }
3474
3475 static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
3476 {
3477         switch (pixel_format) {
3478         case DRM_FORMAT_ABGR8888:
3479         case DRM_FORMAT_ARGB8888:
3480                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3481         default:
3482                 return PLANE_COLOR_ALPHA_DISABLE;
3483         }
3484 }
3485
3486 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3487 {
3488         switch (fb_modifier) {
3489         case DRM_FORMAT_MOD_LINEAR:
3490                 break;
3491         case I915_FORMAT_MOD_X_TILED:
3492                 return PLANE_CTL_TILED_X;
3493         case I915_FORMAT_MOD_Y_TILED:
3494                 return PLANE_CTL_TILED_Y;
3495         case I915_FORMAT_MOD_Y_TILED_CCS:
3496                 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3497         case I915_FORMAT_MOD_Yf_TILED:
3498                 return PLANE_CTL_TILED_YF;
3499         case I915_FORMAT_MOD_Yf_TILED_CCS:
3500                 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3501         default:
3502                 MISSING_CASE(fb_modifier);
3503         }
3504
3505         return 0;
3506 }
3507
3508 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3509 {
3510         switch (rotation) {
3511         case DRM_MODE_ROTATE_0:
3512                 break;
3513         /*
3514          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3515          * while i915 HW rotation is clockwise, thats why this swapping.
3516          */
3517         case DRM_MODE_ROTATE_90:
3518                 return PLANE_CTL_ROTATE_270;
3519         case DRM_MODE_ROTATE_180:
3520                 return PLANE_CTL_ROTATE_180;
3521         case DRM_MODE_ROTATE_270:
3522                 return PLANE_CTL_ROTATE_90;
3523         default:
3524                 MISSING_CASE(rotation);
3525         }
3526
3527         return 0;
3528 }
3529
3530 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3531                   const struct intel_plane_state *plane_state)
3532 {
3533         struct drm_i915_private *dev_priv =
3534                 to_i915(plane_state->base.plane->dev);
3535         const struct drm_framebuffer *fb = plane_state->base.fb;
3536         unsigned int rotation = plane_state->base.rotation;
3537         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3538         u32 plane_ctl;
3539
3540         plane_ctl = PLANE_CTL_ENABLE;
3541
3542         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3543                 plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
3544                 plane_ctl |=
3545                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3546                         PLANE_CTL_PIPE_CSC_ENABLE |
3547                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3548         }
3549
3550         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3551         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3552         plane_ctl |= skl_plane_ctl_rotation(rotation);
3553
3554         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3555                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3556         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3557                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3558
3559         return plane_ctl;
3560 }
3561
3562 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3563                         const struct intel_plane_state *plane_state)
3564 {
3565         const struct drm_framebuffer *fb = plane_state->base.fb;
3566         u32 plane_color_ctl = 0;
3567
3568         plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3569         plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3570         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3571         plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3572
3573         return plane_color_ctl;
3574 }
3575
3576 static int
3577 __intel_display_resume(struct drm_device *dev,
3578                        struct drm_atomic_state *state,
3579                        struct drm_modeset_acquire_ctx *ctx)
3580 {
3581         struct drm_crtc_state *crtc_state;
3582         struct drm_crtc *crtc;
3583         int i, ret;
3584
3585         intel_modeset_setup_hw_state(dev, ctx);
3586         i915_redisable_vga(to_i915(dev));
3587
3588         if (!state)
3589                 return 0;
3590
3591         /*
3592          * We've duplicated the state, pointers to the old state are invalid.
3593          *
3594          * Don't attempt to use the old state until we commit the duplicated state.
3595          */
3596         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3597                 /*
3598                  * Force recalculation even if we restore
3599                  * current state. With fast modeset this may not result
3600                  * in a modeset when the state is compatible.
3601                  */
3602                 crtc_state->mode_changed = true;
3603         }
3604
3605         /* ignore any reset values/BIOS leftovers in the WM registers */
3606         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3607                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3608
3609         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3610
3611         WARN_ON(ret == -EDEADLK);
3612         return ret;
3613 }
3614
3615 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3616 {
3617         return intel_has_gpu_reset(dev_priv) &&
3618                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3619 }
3620
3621 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3622 {
3623         struct drm_device *dev = &dev_priv->drm;
3624         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3625         struct drm_atomic_state *state;
3626         int ret;
3627
3628
3629         /* reset doesn't touch the display */
3630         if (!i915_modparams.force_reset_modeset_test &&
3631             !gpu_reset_clobbers_display(dev_priv))
3632                 return;
3633
3634         /* We have a modeset vs reset deadlock, defensively unbreak it. */
3635         set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3636         wake_up_all(&dev_priv->gpu_error.wait_queue);
3637
3638         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3639                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3640                 i915_gem_set_wedged(dev_priv);
3641         }
3642
3643         /*
3644          * Need mode_config.mutex so that we don't
3645          * trample ongoing ->detect() and whatnot.
3646          */
3647         mutex_lock(&dev->mode_config.mutex);
3648         drm_modeset_acquire_init(ctx, 0);
3649         while (1) {
3650                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3651                 if (ret != -EDEADLK)
3652                         break;
3653
3654                 drm_modeset_backoff(ctx);
3655         }
3656         /*
3657          * Disabling the crtcs gracefully seems nicer. Also the
3658          * g33 docs say we should at least disable all the planes.
3659          */
3660         state = drm_atomic_helper_duplicate_state(dev, ctx);
3661         if (IS_ERR(state)) {
3662                 ret = PTR_ERR(state);
3663                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3664                 return;
3665         }
3666
3667         ret = drm_atomic_helper_disable_all(dev, ctx);
3668         if (ret) {
3669                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3670                 drm_atomic_state_put(state);
3671                 return;
3672         }
3673
3674         dev_priv->modeset_restore_state = state;
3675         state->acquire_ctx = ctx;
3676 }
3677
3678 void intel_finish_reset(struct drm_i915_private *dev_priv)
3679 {
3680         struct drm_device *dev = &dev_priv->drm;
3681         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3682         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3683         int ret;
3684
3685         /* reset doesn't touch the display */
3686         if (!i915_modparams.force_reset_modeset_test &&
3687             !gpu_reset_clobbers_display(dev_priv))
3688                 return;
3689
3690         if (!state)
3691                 goto unlock;
3692
3693         dev_priv->modeset_restore_state = NULL;
3694
3695         /* reset doesn't touch the display */
3696         if (!gpu_reset_clobbers_display(dev_priv)) {
3697                 /* for testing only restore the display */
3698                 ret = __intel_display_resume(dev, state, ctx);
3699                 if (ret)
3700                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3701         } else {
3702                 /*
3703                  * The display has been reset as well,
3704                  * so need a full re-initialization.
3705                  */
3706                 intel_runtime_pm_disable_interrupts(dev_priv);
3707                 intel_runtime_pm_enable_interrupts(dev_priv);
3708
3709                 intel_pps_unlock_regs_wa(dev_priv);
3710                 intel_modeset_init_hw(dev);
3711                 intel_init_clock_gating(dev_priv);
3712
3713                 spin_lock_irq(&dev_priv->irq_lock);
3714                 if (dev_priv->display.hpd_irq_setup)
3715                         dev_priv->display.hpd_irq_setup(dev_priv);
3716                 spin_unlock_irq(&dev_priv->irq_lock);
3717
3718                 ret = __intel_display_resume(dev, state, ctx);
3719                 if (ret)
3720                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3721
3722                 intel_hpd_init(dev_priv);
3723         }
3724
3725         drm_atomic_state_put(state);
3726 unlock:
3727         drm_modeset_drop_locks(ctx);
3728         drm_modeset_acquire_fini(ctx);
3729         mutex_unlock(&dev->mode_config.mutex);
3730
3731         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3732 }
3733
3734 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3735                                      const struct intel_crtc_state *new_crtc_state)
3736 {
3737         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3738         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3739
3740         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3741         crtc->base.mode = new_crtc_state->base.mode;
3742
3743         /*
3744          * Update pipe size and adjust fitter if needed: the reason for this is
3745          * that in compute_mode_changes we check the native mode (not the pfit
3746          * mode) to see if we can flip rather than do a full mode set. In the
3747          * fastboot case, we'll flip, but if we don't update the pipesrc and
3748          * pfit state, we'll end up with a big fb scanned out into the wrong
3749          * sized surface.
3750          */
3751
3752         I915_WRITE(PIPESRC(crtc->pipe),
3753                    ((new_crtc_state->pipe_src_w - 1) << 16) |
3754                    (new_crtc_state->pipe_src_h - 1));
3755
3756         /* on skylake this is done by detaching scalers */
3757         if (INTEL_GEN(dev_priv) >= 9) {
3758                 skl_detach_scalers(crtc);
3759
3760                 if (new_crtc_state->pch_pfit.enabled)
3761                         skylake_pfit_enable(crtc);
3762         } else if (HAS_PCH_SPLIT(dev_priv)) {
3763                 if (new_crtc_state->pch_pfit.enabled)
3764                         ironlake_pfit_enable(crtc);
3765                 else if (old_crtc_state->pch_pfit.enabled)
3766                         ironlake_pfit_disable(crtc, true);
3767         }
3768 }
3769
3770 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3771 {
3772         struct drm_device *dev = crtc->base.dev;
3773         struct drm_i915_private *dev_priv = to_i915(dev);
3774         int pipe = crtc->pipe;
3775         i915_reg_t reg;
3776         u32 temp;
3777
3778         /* enable normal train */
3779         reg = FDI_TX_CTL(pipe);
3780         temp = I915_READ(reg);
3781         if (IS_IVYBRIDGE(dev_priv)) {
3782                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3783                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3784         } else {
3785                 temp &= ~FDI_LINK_TRAIN_NONE;
3786                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3787         }
3788         I915_WRITE(reg, temp);
3789
3790         reg = FDI_RX_CTL(pipe);
3791         temp = I915_READ(reg);
3792         if (HAS_PCH_CPT(dev_priv)) {
3793                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3794                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3795         } else {
3796                 temp &= ~FDI_LINK_TRAIN_NONE;
3797                 temp |= FDI_LINK_TRAIN_NONE;
3798         }
3799         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3800
3801         /* wait one idle pattern time */
3802         POSTING_READ(reg);
3803         udelay(1000);
3804
3805         /* IVB wants error correction enabled */
3806         if (IS_IVYBRIDGE(dev_priv))
3807                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3808                            FDI_FE_ERRC_ENABLE);
3809 }
3810
3811 /* The FDI link training functions for ILK/Ibexpeak. */
3812 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3813                                     const struct intel_crtc_state *crtc_state)
3814 {
3815         struct drm_device *dev = crtc->base.dev;
3816         struct drm_i915_private *dev_priv = to_i915(dev);
3817         int pipe = crtc->pipe;
3818         i915_reg_t reg;
3819         u32 temp, tries;
3820
3821         /* FDI needs bits from pipe first */
3822         assert_pipe_enabled(dev_priv, pipe);
3823
3824         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3825            for train result */
3826         reg = FDI_RX_IMR(pipe);
3827         temp = I915_READ(reg);
3828         temp &= ~FDI_RX_SYMBOL_LOCK;
3829         temp &= ~FDI_RX_BIT_LOCK;
3830         I915_WRITE(reg, temp);
3831         I915_READ(reg);
3832         udelay(150);
3833
3834         /* enable CPU FDI TX and PCH FDI RX */
3835         reg = FDI_TX_CTL(pipe);
3836         temp = I915_READ(reg);
3837         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3838         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3839         temp &= ~FDI_LINK_TRAIN_NONE;
3840         temp |= FDI_LINK_TRAIN_PATTERN_1;
3841         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3842
3843         reg = FDI_RX_CTL(pipe);
3844         temp = I915_READ(reg);
3845         temp &= ~FDI_LINK_TRAIN_NONE;
3846         temp |= FDI_LINK_TRAIN_PATTERN_1;
3847         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3848
3849         POSTING_READ(reg);
3850         udelay(150);
3851
3852         /* Ironlake workaround, enable clock pointer after FDI enable*/
3853         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3854         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3855                    FDI_RX_PHASE_SYNC_POINTER_EN);
3856
3857         reg = FDI_RX_IIR(pipe);
3858         for (tries = 0; tries < 5; tries++) {
3859                 temp = I915_READ(reg);
3860                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3861
3862                 if ((temp & FDI_RX_BIT_LOCK)) {
3863                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3864                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3865                         break;
3866                 }
3867         }
3868         if (tries == 5)
3869                 DRM_ERROR("FDI train 1 fail!\n");
3870
3871         /* Train 2 */
3872         reg = FDI_TX_CTL(pipe);
3873         temp = I915_READ(reg);
3874         temp &= ~FDI_LINK_TRAIN_NONE;
3875         temp |= FDI_LINK_TRAIN_PATTERN_2;
3876         I915_WRITE(reg, temp);
3877
3878         reg = FDI_RX_CTL(pipe);
3879         temp = I915_READ(reg);
3880         temp &= ~FDI_LINK_TRAIN_NONE;
3881         temp |= FDI_LINK_TRAIN_PATTERN_2;
3882         I915_WRITE(reg, temp);
3883
3884         POSTING_READ(reg);
3885         udelay(150);
3886
3887         reg = FDI_RX_IIR(pipe);
3888         for (tries = 0; tries < 5; tries++) {
3889                 temp = I915_READ(reg);
3890                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3891
3892                 if (temp & FDI_RX_SYMBOL_LOCK) {
3893                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3894                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3895                         break;
3896                 }
3897         }
3898         if (tries == 5)
3899                 DRM_ERROR("FDI train 2 fail!\n");
3900
3901         DRM_DEBUG_KMS("FDI train done\n");
3902
3903 }
3904
3905 static const int snb_b_fdi_train_param[] = {
3906         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3907         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3908         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3909         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3910 };
3911
3912 /* The FDI link training functions for SNB/Cougarpoint. */
3913 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3914                                 const struct intel_crtc_state *crtc_state)
3915 {
3916         struct drm_device *dev = crtc->base.dev;
3917         struct drm_i915_private *dev_priv = to_i915(dev);
3918         int pipe = crtc->pipe;
3919         i915_reg_t reg;
3920         u32 temp, i, retry;
3921
3922         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3923            for train result */
3924         reg = FDI_RX_IMR(pipe);
3925         temp = I915_READ(reg);
3926         temp &= ~FDI_RX_SYMBOL_LOCK;
3927         temp &= ~FDI_RX_BIT_LOCK;
3928         I915_WRITE(reg, temp);
3929
3930         POSTING_READ(reg);
3931         udelay(150);
3932
3933         /* enable CPU FDI TX and PCH FDI RX */
3934         reg = FDI_TX_CTL(pipe);
3935         temp = I915_READ(reg);
3936         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3937         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3938         temp &= ~FDI_LINK_TRAIN_NONE;
3939         temp |= FDI_LINK_TRAIN_PATTERN_1;
3940         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3941         /* SNB-B */
3942         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3943         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3944
3945         I915_WRITE(FDI_RX_MISC(pipe),
3946                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3947
3948         reg = FDI_RX_CTL(pipe);
3949         temp = I915_READ(reg);
3950         if (HAS_PCH_CPT(dev_priv)) {
3951                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3952                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3953         } else {
3954                 temp &= ~FDI_LINK_TRAIN_NONE;
3955                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3956         }
3957         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3958
3959         POSTING_READ(reg);
3960         udelay(150);
3961
3962         for (i = 0; i < 4; i++) {
3963                 reg = FDI_TX_CTL(pipe);
3964                 temp = I915_READ(reg);
3965                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3966                 temp |= snb_b_fdi_train_param[i];
3967                 I915_WRITE(reg, temp);
3968
3969                 POSTING_READ(reg);
3970                 udelay(500);
3971
3972                 for (retry = 0; retry < 5; retry++) {
3973                         reg = FDI_RX_IIR(pipe);
3974                         temp = I915_READ(reg);
3975                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3976                         if (temp & FDI_RX_BIT_LOCK) {
3977                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3978                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3979                                 break;
3980                         }
3981                         udelay(50);
3982                 }
3983                 if (retry < 5)
3984                         break;
3985         }
3986         if (i == 4)
3987                 DRM_ERROR("FDI train 1 fail!\n");
3988
3989         /* Train 2 */
3990         reg = FDI_TX_CTL(pipe);
3991         temp = I915_READ(reg);
3992         temp &= ~FDI_LINK_TRAIN_NONE;
3993         temp |= FDI_LINK_TRAIN_PATTERN_2;
3994         if (IS_GEN6(dev_priv)) {
3995                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3996                 /* SNB-B */
3997                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3998         }
3999         I915_WRITE(reg, temp);
4000
4001         reg = FDI_RX_CTL(pipe);
4002         temp = I915_READ(reg);
4003         if (HAS_PCH_CPT(dev_priv)) {
4004                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4005                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4006         } else {
4007                 temp &= ~FDI_LINK_TRAIN_NONE;
4008                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4009         }
4010         I915_WRITE(reg, temp);
4011
4012         POSTING_READ(reg);
4013         udelay(150);
4014
4015         for (i = 0; i < 4; i++) {
4016                 reg = FDI_TX_CTL(pipe);
4017                 temp = I915_READ(reg);
4018                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4019                 temp |= snb_b_fdi_train_param[i];
4020                 I915_WRITE(reg, temp);
4021
4022                 POSTING_READ(reg);
4023                 udelay(500);
4024
4025                 for (retry = 0; retry < 5; retry++) {
4026                         reg = FDI_RX_IIR(pipe);
4027                         temp = I915_READ(reg);
4028                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4029                         if (temp & FDI_RX_SYMBOL_LOCK) {
4030                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4031                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4032                                 break;
4033                         }
4034                         udelay(50);
4035                 }
4036                 if (retry < 5)
4037                         break;
4038         }
4039         if (i == 4)
4040                 DRM_ERROR("FDI train 2 fail!\n");
4041
4042         DRM_DEBUG_KMS("FDI train done.\n");
4043 }
4044
4045 /* Manual link training for Ivy Bridge A0 parts */
4046 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4047                                       const struct intel_crtc_state *crtc_state)
4048 {
4049         struct drm_device *dev = crtc->base.dev;
4050         struct drm_i915_private *dev_priv = to_i915(dev);
4051         int pipe = crtc->pipe;
4052         i915_reg_t reg;
4053         u32 temp, i, j;
4054
4055         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4056            for train result */
4057         reg = FDI_RX_IMR(pipe);
4058         temp = I915_READ(reg);
4059         temp &= ~FDI_RX_SYMBOL_LOCK;
4060         temp &= ~FDI_RX_BIT_LOCK;
4061         I915_WRITE(reg, temp);
4062
4063         POSTING_READ(reg);
4064         udelay(150);
4065
4066         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4067                       I915_READ(FDI_RX_IIR(pipe)));
4068
4069         /* Try each vswing and preemphasis setting twice before moving on */
4070         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4071                 /* disable first in case we need to retry */
4072                 reg = FDI_TX_CTL(pipe);
4073                 temp = I915_READ(reg);
4074                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4075                 temp &= ~FDI_TX_ENABLE;
4076                 I915_WRITE(reg, temp);
4077
4078                 reg = FDI_RX_CTL(pipe);
4079                 temp = I915_READ(reg);
4080                 temp &= ~FDI_LINK_TRAIN_AUTO;
4081                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4082                 temp &= ~FDI_RX_ENABLE;
4083                 I915_WRITE(reg, temp);
4084
4085                 /* enable CPU FDI TX and PCH FDI RX */
4086                 reg = FDI_TX_CTL(pipe);
4087                 temp = I915_READ(reg);
4088                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4089                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4090                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4091                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4092                 temp |= snb_b_fdi_train_param[j/2];
4093                 temp |= FDI_COMPOSITE_SYNC;
4094                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4095
4096                 I915_WRITE(FDI_RX_MISC(pipe),
4097                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4098
4099                 reg = FDI_RX_CTL(pipe);
4100                 temp = I915_READ(reg);
4101                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4102                 temp |= FDI_COMPOSITE_SYNC;
4103                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4104
4105                 POSTING_READ(reg);
4106                 udelay(1); /* should be 0.5us */
4107
4108                 for (i = 0; i < 4; i++) {
4109                         reg = FDI_RX_IIR(pipe);
4110                         temp = I915_READ(reg);
4111                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4112
4113                         if (temp & FDI_RX_BIT_LOCK ||
4114                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4115                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4116                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4117                                               i);
4118                                 break;
4119                         }
4120                         udelay(1); /* should be 0.5us */
4121                 }
4122                 if (i == 4) {
4123                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4124                         continue;
4125                 }
4126
4127                 /* Train 2 */
4128                 reg = FDI_TX_CTL(pipe);
4129                 temp = I915_READ(reg);
4130                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4131                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4132                 I915_WRITE(reg, temp);
4133
4134                 reg = FDI_RX_CTL(pipe);
4135                 temp = I915_READ(reg);
4136                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4137                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4138                 I915_WRITE(reg, temp);
4139
4140                 POSTING_READ(reg);
4141                 udelay(2); /* should be 1.5us */
4142
4143                 for (i = 0; i < 4; i++) {
4144                         reg = FDI_RX_IIR(pipe);
4145                         temp = I915_READ(reg);
4146                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4147
4148                         if (temp & FDI_RX_SYMBOL_LOCK ||
4149                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4150                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4151                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4152                                               i);
4153                                 goto train_done;
4154                         }
4155                         udelay(2); /* should be 1.5us */
4156                 }
4157                 if (i == 4)
4158                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4159         }
4160
4161 train_done:
4162         DRM_DEBUG_KMS("FDI train done.\n");
4163 }
4164
4165 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4166 {
4167         struct drm_device *dev = intel_crtc->base.dev;
4168         struct drm_i915_private *dev_priv = to_i915(dev);
4169         int pipe = intel_crtc->pipe;
4170         i915_reg_t reg;
4171         u32 temp;
4172
4173         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4174         reg = FDI_RX_CTL(pipe);
4175         temp = I915_READ(reg);
4176         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4177         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4178         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4179         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4180
4181         POSTING_READ(reg);
4182         udelay(200);
4183
4184         /* Switch from Rawclk to PCDclk */
4185         temp = I915_READ(reg);
4186         I915_WRITE(reg, temp | FDI_PCDCLK);
4187
4188         POSTING_READ(reg);
4189         udelay(200);
4190
4191         /* Enable CPU FDI TX PLL, always on for Ironlake */
4192         reg = FDI_TX_CTL(pipe);
4193         temp = I915_READ(reg);
4194         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4195                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4196
4197                 POSTING_READ(reg);
4198                 udelay(100);
4199         }
4200 }
4201
4202 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4203 {
4204         struct drm_device *dev = intel_crtc->base.dev;
4205         struct drm_i915_private *dev_priv = to_i915(dev);
4206         int pipe = intel_crtc->pipe;
4207         i915_reg_t reg;
4208         u32 temp;
4209
4210         /* Switch from PCDclk to Rawclk */
4211         reg = FDI_RX_CTL(pipe);
4212         temp = I915_READ(reg);
4213         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4214
4215         /* Disable CPU FDI TX PLL */
4216         reg = FDI_TX_CTL(pipe);
4217         temp = I915_READ(reg);
4218         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4219
4220         POSTING_READ(reg);
4221         udelay(100);
4222
4223         reg = FDI_RX_CTL(pipe);
4224         temp = I915_READ(reg);
4225         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4226
4227         /* Wait for the clocks to turn off. */
4228         POSTING_READ(reg);
4229         udelay(100);
4230 }
4231
4232 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4233 {
4234         struct drm_device *dev = crtc->dev;
4235         struct drm_i915_private *dev_priv = to_i915(dev);
4236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4237         int pipe = intel_crtc->pipe;
4238         i915_reg_t reg;
4239         u32 temp;
4240
4241         /* disable CPU FDI tx and PCH FDI rx */
4242         reg = FDI_TX_CTL(pipe);
4243         temp = I915_READ(reg);
4244         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4245         POSTING_READ(reg);
4246
4247         reg = FDI_RX_CTL(pipe);
4248         temp = I915_READ(reg);
4249         temp &= ~(0x7 << 16);
4250         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4251         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4252
4253         POSTING_READ(reg);
4254         udelay(100);
4255
4256         /* Ironlake workaround, disable clock pointer after downing FDI */
4257         if (HAS_PCH_IBX(dev_priv))
4258                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4259
4260         /* still set train pattern 1 */
4261         reg = FDI_TX_CTL(pipe);
4262         temp = I915_READ(reg);
4263         temp &= ~FDI_LINK_TRAIN_NONE;
4264         temp |= FDI_LINK_TRAIN_PATTERN_1;
4265         I915_WRITE(reg, temp);
4266
4267         reg = FDI_RX_CTL(pipe);
4268         temp = I915_READ(reg);
4269         if (HAS_PCH_CPT(dev_priv)) {
4270                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4271                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4272         } else {
4273                 temp &= ~FDI_LINK_TRAIN_NONE;
4274                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4275         }
4276         /* BPC in FDI rx is consistent with that in PIPECONF */
4277         temp &= ~(0x07 << 16);
4278         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4279         I915_WRITE(reg, temp);
4280
4281         POSTING_READ(reg);
4282         udelay(100);
4283 }
4284
4285 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4286 {
4287         struct drm_crtc *crtc;
4288         bool cleanup_done;
4289
4290         drm_for_each_crtc(crtc, &dev_priv->drm) {
4291                 struct drm_crtc_commit *commit;
4292                 spin_lock(&crtc->commit_lock);
4293                 commit = list_first_entry_or_null(&crtc->commit_list,
4294                                                   struct drm_crtc_commit, commit_entry);
4295                 cleanup_done = commit ?
4296                         try_wait_for_completion(&commit->cleanup_done) : true;
4297                 spin_unlock(&crtc->commit_lock);
4298
4299                 if (cleanup_done)
4300                         continue;
4301
4302                 drm_crtc_wait_one_vblank(crtc);
4303
4304                 return true;
4305         }
4306
4307         return false;
4308 }
4309
4310 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4311 {
4312         u32 temp;
4313
4314         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4315
4316         mutex_lock(&dev_priv->sb_lock);
4317
4318         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4319         temp |= SBI_SSCCTL_DISABLE;
4320         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4321
4322         mutex_unlock(&dev_priv->sb_lock);
4323 }
4324
4325 /* Program iCLKIP clock to the desired frequency */
4326 static void lpt_program_iclkip(struct intel_crtc *crtc)
4327 {
4328         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4329         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4330         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4331         u32 temp;
4332
4333         lpt_disable_iclkip(dev_priv);
4334
4335         /* The iCLK virtual clock root frequency is in MHz,
4336          * but the adjusted_mode->crtc_clock in in KHz. To get the
4337          * divisors, it is necessary to divide one by another, so we
4338          * convert the virtual clock precision to KHz here for higher
4339          * precision.
4340          */
4341         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4342                 u32 iclk_virtual_root_freq = 172800 * 1000;
4343                 u32 iclk_pi_range = 64;
4344                 u32 desired_divisor;
4345
4346                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4347                                                     clock << auxdiv);
4348                 divsel = (desired_divisor / iclk_pi_range) - 2;
4349                 phaseinc = desired_divisor % iclk_pi_range;
4350
4351                 /*
4352                  * Near 20MHz is a corner case which is
4353                  * out of range for the 7-bit divisor
4354                  */
4355                 if (divsel <= 0x7f)
4356                         break;
4357         }
4358
4359         /* This should not happen with any sane values */
4360         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4361                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4362         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4363                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4364
4365         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4366                         clock,
4367                         auxdiv,
4368                         divsel,
4369                         phasedir,
4370                         phaseinc);
4371
4372         mutex_lock(&dev_priv->sb_lock);
4373
4374         /* Program SSCDIVINTPHASE6 */
4375         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4376         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4377         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4378         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4379         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4380         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4381         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4382         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4383
4384         /* Program SSCAUXDIV */
4385         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4386         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4387         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4388         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4389
4390         /* Enable modulator and associated divider */
4391         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4392         temp &= ~SBI_SSCCTL_DISABLE;
4393         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4394
4395         mutex_unlock(&dev_priv->sb_lock);
4396
4397         /* Wait for initialization time */
4398         udelay(24);
4399
4400         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4401 }
4402
4403 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4404 {
4405         u32 divsel, phaseinc, auxdiv;
4406         u32 iclk_virtual_root_freq = 172800 * 1000;
4407         u32 iclk_pi_range = 64;
4408         u32 desired_divisor;
4409         u32 temp;
4410
4411         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4412                 return 0;
4413
4414         mutex_lock(&dev_priv->sb_lock);
4415
4416         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4417         if (temp & SBI_SSCCTL_DISABLE) {
4418                 mutex_unlock(&dev_priv->sb_lock);
4419                 return 0;
4420         }
4421
4422         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4423         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4424                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4425         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4426                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4427
4428         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4429         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4430                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4431
4432         mutex_unlock(&dev_priv->sb_lock);
4433
4434         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4435
4436         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4437                                  desired_divisor << auxdiv);
4438 }
4439
4440 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4441                                                 enum pipe pch_transcoder)
4442 {
4443         struct drm_device *dev = crtc->base.dev;
4444         struct drm_i915_private *dev_priv = to_i915(dev);
4445         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4446
4447         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4448                    I915_READ(HTOTAL(cpu_transcoder)));
4449         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4450                    I915_READ(HBLANK(cpu_transcoder)));
4451         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4452                    I915_READ(HSYNC(cpu_transcoder)));
4453
4454         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4455                    I915_READ(VTOTAL(cpu_transcoder)));
4456         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4457                    I915_READ(VBLANK(cpu_transcoder)));
4458         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4459                    I915_READ(VSYNC(cpu_transcoder)));
4460         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4461                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4462 }
4463
4464 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4465 {
4466         struct drm_i915_private *dev_priv = to_i915(dev);
4467         uint32_t temp;
4468
4469         temp = I915_READ(SOUTH_CHICKEN1);
4470         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4471                 return;
4472
4473         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4474         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4475
4476         temp &= ~FDI_BC_BIFURCATION_SELECT;
4477         if (enable)
4478                 temp |= FDI_BC_BIFURCATION_SELECT;
4479
4480         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4481         I915_WRITE(SOUTH_CHICKEN1, temp);
4482         POSTING_READ(SOUTH_CHICKEN1);
4483 }
4484
4485 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4486 {
4487         struct drm_device *dev = intel_crtc->base.dev;
4488
4489         switch (intel_crtc->pipe) {
4490         case PIPE_A:
4491                 break;
4492         case PIPE_B:
4493                 if (intel_crtc->config->fdi_lanes > 2)
4494                         cpt_set_fdi_bc_bifurcation(dev, false);
4495                 else
4496                         cpt_set_fdi_bc_bifurcation(dev, true);
4497
4498                 break;
4499         case PIPE_C:
4500                 cpt_set_fdi_bc_bifurcation(dev, true);
4501
4502                 break;
4503         default:
4504                 BUG();
4505         }
4506 }
4507
4508 /* Return which DP Port should be selected for Transcoder DP control */
4509 static enum port
4510 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4511 {
4512         struct drm_device *dev = crtc->base.dev;
4513         struct intel_encoder *encoder;
4514
4515         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4516                 if (encoder->type == INTEL_OUTPUT_DP ||
4517                     encoder->type == INTEL_OUTPUT_EDP)
4518                         return encoder->port;
4519         }
4520
4521         return -1;
4522 }
4523
4524 /*
4525  * Enable PCH resources required for PCH ports:
4526  *   - PCH PLLs
4527  *   - FDI training & RX/TX
4528  *   - update transcoder timings
4529  *   - DP transcoding bits
4530  *   - transcoder
4531  */
4532 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4533 {
4534         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4535         struct drm_device *dev = crtc->base.dev;
4536         struct drm_i915_private *dev_priv = to_i915(dev);
4537         int pipe = crtc->pipe;
4538         u32 temp;
4539
4540         assert_pch_transcoder_disabled(dev_priv, pipe);
4541
4542         if (IS_IVYBRIDGE(dev_priv))
4543                 ivybridge_update_fdi_bc_bifurcation(crtc);
4544
4545         /* Write the TU size bits before fdi link training, so that error
4546          * detection works. */
4547         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4548                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4549
4550         /* For PCH output, training FDI link */
4551         dev_priv->display.fdi_link_train(crtc, crtc_state);
4552
4553         /* We need to program the right clock selection before writing the pixel
4554          * mutliplier into the DPLL. */
4555         if (HAS_PCH_CPT(dev_priv)) {
4556                 u32 sel;
4557
4558                 temp = I915_READ(PCH_DPLL_SEL);
4559                 temp |= TRANS_DPLL_ENABLE(pipe);
4560                 sel = TRANS_DPLLB_SEL(pipe);
4561                 if (crtc_state->shared_dpll ==
4562                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4563                         temp |= sel;
4564                 else
4565                         temp &= ~sel;
4566                 I915_WRITE(PCH_DPLL_SEL, temp);
4567         }
4568
4569         /* XXX: pch pll's can be enabled any time before we enable the PCH
4570          * transcoder, and we actually should do this to not upset any PCH
4571          * transcoder that already use the clock when we share it.
4572          *
4573          * Note that enable_shared_dpll tries to do the right thing, but
4574          * get_shared_dpll unconditionally resets the pll - we need that to have
4575          * the right LVDS enable sequence. */
4576         intel_enable_shared_dpll(crtc);
4577
4578         /* set transcoder timing, panel must allow it */
4579         assert_panel_unlocked(dev_priv, pipe);
4580         ironlake_pch_transcoder_set_timings(crtc, pipe);
4581
4582         intel_fdi_normal_train(crtc);
4583
4584         /* For PCH DP, enable TRANS_DP_CTL */
4585         if (HAS_PCH_CPT(dev_priv) &&
4586             intel_crtc_has_dp_encoder(crtc_state)) {
4587                 const struct drm_display_mode *adjusted_mode =
4588                         &crtc_state->base.adjusted_mode;
4589                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4590                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4591                 temp = I915_READ(reg);
4592                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4593                           TRANS_DP_SYNC_MASK |
4594                           TRANS_DP_BPC_MASK);
4595                 temp |= TRANS_DP_OUTPUT_ENABLE;
4596                 temp |= bpc << 9; /* same format but at 11:9 */
4597
4598                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4599                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4600                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4601                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4602
4603                 switch (intel_trans_dp_port_sel(crtc)) {
4604                 case PORT_B:
4605                         temp |= TRANS_DP_PORT_SEL_B;
4606                         break;
4607                 case PORT_C:
4608                         temp |= TRANS_DP_PORT_SEL_C;
4609                         break;
4610                 case PORT_D:
4611                         temp |= TRANS_DP_PORT_SEL_D;
4612                         break;
4613                 default:
4614                         BUG();
4615                 }
4616
4617                 I915_WRITE(reg, temp);
4618         }
4619
4620         ironlake_enable_pch_transcoder(dev_priv, pipe);
4621 }
4622
4623 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4624 {
4625         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4626         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4627         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4628
4629         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4630
4631         lpt_program_iclkip(crtc);
4632
4633         /* Set transcoder timing. */
4634         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4635
4636         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4637 }
4638
4639 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4640 {
4641         struct drm_i915_private *dev_priv = to_i915(dev);
4642         i915_reg_t dslreg = PIPEDSL(pipe);
4643         u32 temp;
4644
4645         temp = I915_READ(dslreg);
4646         udelay(500);
4647         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4648                 if (wait_for(I915_READ(dslreg) != temp, 5))
4649                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4650         }
4651 }
4652
4653 static int
4654 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4655                   unsigned int scaler_user, int *scaler_id,
4656                   int src_w, int src_h, int dst_w, int dst_h)
4657 {
4658         struct intel_crtc_scaler_state *scaler_state =
4659                 &crtc_state->scaler_state;
4660         struct intel_crtc *intel_crtc =
4661                 to_intel_crtc(crtc_state->base.crtc);
4662         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4663         const struct drm_display_mode *adjusted_mode =
4664                 &crtc_state->base.adjusted_mode;
4665         int need_scaling;
4666
4667         /*
4668          * Src coordinates are already rotated by 270 degrees for
4669          * the 90/270 degree plane rotation cases (to match the
4670          * GTT mapping), hence no need to account for rotation here.
4671          */
4672         need_scaling = src_w != dst_w || src_h != dst_h;
4673
4674         if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4675                 need_scaling = true;
4676
4677         /*
4678          * Scaling/fitting not supported in IF-ID mode in GEN9+
4679          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4680          * Once NV12 is enabled, handle it here while allocating scaler
4681          * for NV12.
4682          */
4683         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4684             need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4685                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4686                 return -EINVAL;
4687         }
4688
4689         /*
4690          * if plane is being disabled or scaler is no more required or force detach
4691          *  - free scaler binded to this plane/crtc
4692          *  - in order to do this, update crtc->scaler_usage
4693          *
4694          * Here scaler state in crtc_state is set free so that
4695          * scaler can be assigned to other user. Actual register
4696          * update to free the scaler is done in plane/panel-fit programming.
4697          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4698          */
4699         if (force_detach || !need_scaling) {
4700                 if (*scaler_id >= 0) {
4701                         scaler_state->scaler_users &= ~(1 << scaler_user);
4702                         scaler_state->scalers[*scaler_id].in_use = 0;
4703
4704                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4705                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4706                                 intel_crtc->pipe, scaler_user, *scaler_id,
4707                                 scaler_state->scaler_users);
4708                         *scaler_id = -1;
4709                 }
4710                 return 0;
4711         }
4712
4713         /* range checks */
4714         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4715                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4716
4717                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4718                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4719                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4720                         "size is out of scaler range\n",
4721                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4722                 return -EINVAL;
4723         }
4724
4725         /* mark this plane as a scaler user in crtc_state */
4726         scaler_state->scaler_users |= (1 << scaler_user);
4727         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4728                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4729                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4730                 scaler_state->scaler_users);
4731
4732         return 0;
4733 }
4734
4735 /**
4736  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4737  *
4738  * @state: crtc's scaler state
4739  *
4740  * Return
4741  *     0 - scaler_usage updated successfully
4742  *    error - requested scaling cannot be supported or other error condition
4743  */
4744 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4745 {
4746         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4747
4748         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4749                 &state->scaler_state.scaler_id,
4750                 state->pipe_src_w, state->pipe_src_h,
4751                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4752 }
4753
4754 /**
4755  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4756  *
4757  * @state: crtc's scaler state
4758  * @plane_state: atomic plane state to update
4759  *
4760  * Return
4761  *     0 - scaler_usage updated successfully
4762  *    error - requested scaling cannot be supported or other error condition
4763  */
4764 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4765                                    struct intel_plane_state *plane_state)
4766 {
4767
4768         struct intel_plane *intel_plane =
4769                 to_intel_plane(plane_state->base.plane);
4770         struct drm_framebuffer *fb = plane_state->base.fb;
4771         int ret;
4772
4773         bool force_detach = !fb || !plane_state->base.visible;
4774
4775         ret = skl_update_scaler(crtc_state, force_detach,
4776                                 drm_plane_index(&intel_plane->base),
4777                                 &plane_state->scaler_id,
4778                                 drm_rect_width(&plane_state->base.src) >> 16,
4779                                 drm_rect_height(&plane_state->base.src) >> 16,
4780                                 drm_rect_width(&plane_state->base.dst),
4781                                 drm_rect_height(&plane_state->base.dst));
4782
4783         if (ret || plane_state->scaler_id < 0)
4784                 return ret;
4785
4786         /* check colorkey */
4787         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4788                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4789                               intel_plane->base.base.id,
4790                               intel_plane->base.name);
4791                 return -EINVAL;
4792         }
4793
4794         /* Check src format */
4795         switch (fb->format->format) {
4796         case DRM_FORMAT_RGB565:
4797         case DRM_FORMAT_XBGR8888:
4798         case DRM_FORMAT_XRGB8888:
4799         case DRM_FORMAT_ABGR8888:
4800         case DRM_FORMAT_ARGB8888:
4801         case DRM_FORMAT_XRGB2101010:
4802         case DRM_FORMAT_XBGR2101010:
4803         case DRM_FORMAT_YUYV:
4804         case DRM_FORMAT_YVYU:
4805         case DRM_FORMAT_UYVY:
4806         case DRM_FORMAT_VYUY:
4807                 break;
4808         default:
4809                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4810                               intel_plane->base.base.id, intel_plane->base.name,
4811                               fb->base.id, fb->format->format);
4812                 return -EINVAL;
4813         }
4814
4815         return 0;
4816 }
4817
4818 static void skylake_scaler_disable(struct intel_crtc *crtc)
4819 {
4820         int i;
4821
4822         for (i = 0; i < crtc->num_scalers; i++)
4823                 skl_detach_scaler(crtc, i);
4824 }
4825
4826 static void skylake_pfit_enable(struct intel_crtc *crtc)
4827 {
4828         struct drm_device *dev = crtc->base.dev;
4829         struct drm_i915_private *dev_priv = to_i915(dev);
4830         int pipe = crtc->pipe;
4831         struct intel_crtc_scaler_state *scaler_state =
4832                 &crtc->config->scaler_state;
4833
4834         if (crtc->config->pch_pfit.enabled) {
4835                 int id;
4836
4837                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4838                         return;
4839
4840                 id = scaler_state->scaler_id;
4841                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4842                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4843                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4844                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4845         }
4846 }
4847
4848 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4849 {
4850         struct drm_device *dev = crtc->base.dev;
4851         struct drm_i915_private *dev_priv = to_i915(dev);
4852         int pipe = crtc->pipe;
4853
4854         if (crtc->config->pch_pfit.enabled) {
4855                 /* Force use of hard-coded filter coefficients
4856                  * as some pre-programmed values are broken,
4857                  * e.g. x201.
4858                  */
4859                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4860                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4861                                                  PF_PIPE_SEL_IVB(pipe));
4862                 else
4863                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4864                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4865                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4866         }
4867 }
4868
4869 void hsw_enable_ips(struct intel_crtc *crtc)
4870 {
4871         struct drm_device *dev = crtc->base.dev;
4872         struct drm_i915_private *dev_priv = to_i915(dev);
4873
4874         if (!crtc->config->ips_enabled)
4875                 return;
4876
4877         /*
4878          * We can only enable IPS after we enable a plane and wait for a vblank
4879          * This function is called from post_plane_update, which is run after
4880          * a vblank wait.
4881          */
4882
4883         assert_plane_enabled(dev_priv, crtc->plane);
4884         if (IS_BROADWELL(dev_priv)) {
4885                 mutex_lock(&dev_priv->pcu_lock);
4886                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4887                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
4888                 mutex_unlock(&dev_priv->pcu_lock);
4889                 /* Quoting Art Runyan: "its not safe to expect any particular
4890                  * value in IPS_CTL bit 31 after enabling IPS through the
4891                  * mailbox." Moreover, the mailbox may return a bogus state,
4892                  * so we need to just enable it and continue on.
4893                  */
4894         } else {
4895                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4896                 /* The bit only becomes 1 in the next vblank, so this wait here
4897                  * is essentially intel_wait_for_vblank. If we don't have this
4898                  * and don't wait for vblanks until the end of crtc_enable, then
4899                  * the HW state readout code will complain that the expected
4900                  * IPS_CTL value is not the one we read. */
4901                 if (intel_wait_for_register(dev_priv,
4902                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4903                                             50))
4904                         DRM_ERROR("Timed out waiting for IPS enable\n");
4905         }
4906 }
4907
4908 void hsw_disable_ips(struct intel_crtc *crtc)
4909 {
4910         struct drm_device *dev = crtc->base.dev;
4911         struct drm_i915_private *dev_priv = to_i915(dev);
4912
4913         if (!crtc->config->ips_enabled)
4914                 return;
4915
4916         assert_plane_enabled(dev_priv, crtc->plane);
4917         if (IS_BROADWELL(dev_priv)) {
4918                 mutex_lock(&dev_priv->pcu_lock);
4919                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4920                 mutex_unlock(&dev_priv->pcu_lock);
4921                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4922                 if (intel_wait_for_register(dev_priv,
4923                                             IPS_CTL, IPS_ENABLE, 0,
4924                                             42))
4925                         DRM_ERROR("Timed out waiting for IPS disable\n");
4926         } else {
4927                 I915_WRITE(IPS_CTL, 0);
4928                 POSTING_READ(IPS_CTL);
4929         }
4930
4931         /* We need to wait for a vblank before we can disable the plane. */
4932         intel_wait_for_vblank(dev_priv, crtc->pipe);
4933 }
4934
4935 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4936 {
4937         if (intel_crtc->overlay) {
4938                 struct drm_device *dev = intel_crtc->base.dev;
4939
4940                 mutex_lock(&dev->struct_mutex);
4941                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4942                 mutex_unlock(&dev->struct_mutex);
4943         }
4944
4945         /* Let userspace switch the overlay on again. In most cases userspace
4946          * has to recompute where to put it anyway.
4947          */
4948 }
4949
4950 /**
4951  * intel_post_enable_primary - Perform operations after enabling primary plane
4952  * @crtc: the CRTC whose primary plane was just enabled
4953  *
4954  * Performs potentially sleeping operations that must be done after the primary
4955  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4956  * called due to an explicit primary plane update, or due to an implicit
4957  * re-enable that is caused when a sprite plane is updated to no longer
4958  * completely hide the primary plane.
4959  */
4960 static void
4961 intel_post_enable_primary(struct drm_crtc *crtc)
4962 {
4963         struct drm_device *dev = crtc->dev;
4964         struct drm_i915_private *dev_priv = to_i915(dev);
4965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4966         int pipe = intel_crtc->pipe;
4967
4968         /*
4969          * FIXME IPS should be fine as long as one plane is
4970          * enabled, but in practice it seems to have problems
4971          * when going from primary only to sprite only and vice
4972          * versa.
4973          */
4974         hsw_enable_ips(intel_crtc);
4975
4976         /*
4977          * Gen2 reports pipe underruns whenever all planes are disabled.
4978          * So don't enable underrun reporting before at least some planes
4979          * are enabled.
4980          * FIXME: Need to fix the logic to work when we turn off all planes
4981          * but leave the pipe running.
4982          */
4983         if (IS_GEN2(dev_priv))
4984                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4985
4986         /* Underruns don't always raise interrupts, so check manually. */
4987         intel_check_cpu_fifo_underruns(dev_priv);
4988         intel_check_pch_fifo_underruns(dev_priv);
4989 }
4990
4991 /* FIXME move all this to pre_plane_update() with proper state tracking */
4992 static void
4993 intel_pre_disable_primary(struct drm_crtc *crtc)
4994 {
4995         struct drm_device *dev = crtc->dev;
4996         struct drm_i915_private *dev_priv = to_i915(dev);
4997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4998         int pipe = intel_crtc->pipe;
4999
5000         /*
5001          * Gen2 reports pipe underruns whenever all planes are disabled.
5002          * So diasble underrun reporting before all the planes get disabled.
5003          * FIXME: Need to fix the logic to work when we turn off all planes
5004          * but leave the pipe running.
5005          */
5006         if (IS_GEN2(dev_priv))
5007                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5008
5009         /*
5010          * FIXME IPS should be fine as long as one plane is
5011          * enabled, but in practice it seems to have problems
5012          * when going from primary only to sprite only and vice
5013          * versa.
5014          */
5015         hsw_disable_ips(intel_crtc);
5016 }
5017
5018 /* FIXME get rid of this and use pre_plane_update */
5019 static void
5020 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5021 {
5022         struct drm_device *dev = crtc->dev;
5023         struct drm_i915_private *dev_priv = to_i915(dev);
5024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5025         int pipe = intel_crtc->pipe;
5026
5027         intel_pre_disable_primary(crtc);
5028
5029         /*
5030          * Vblank time updates from the shadow to live plane control register
5031          * are blocked if the memory self-refresh mode is active at that
5032          * moment. So to make sure the plane gets truly disabled, disable
5033          * first the self-refresh mode. The self-refresh enable bit in turn
5034          * will be checked/applied by the HW only at the next frame start
5035          * event which is after the vblank start event, so we need to have a
5036          * wait-for-vblank between disabling the plane and the pipe.
5037          */
5038         if (HAS_GMCH_DISPLAY(dev_priv) &&
5039             intel_set_memory_cxsr(dev_priv, false))
5040                 intel_wait_for_vblank(dev_priv, pipe);
5041 }
5042
5043 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5044 {
5045         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5046         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5047         struct intel_crtc_state *pipe_config =
5048                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5049                                                 crtc);
5050         struct drm_plane *primary = crtc->base.primary;
5051         struct drm_plane_state *old_pri_state =
5052                 drm_atomic_get_existing_plane_state(old_state, primary);
5053
5054         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5055
5056         if (pipe_config->update_wm_post && pipe_config->base.active)
5057                 intel_update_watermarks(crtc);
5058
5059         if (old_pri_state) {
5060                 struct intel_plane_state *primary_state =
5061                         intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5062                                                          to_intel_plane(primary));
5063                 struct intel_plane_state *old_primary_state =
5064                         to_intel_plane_state(old_pri_state);
5065
5066                 intel_fbc_post_update(crtc);
5067
5068                 if (primary_state->base.visible &&
5069                     (needs_modeset(&pipe_config->base) ||
5070                      !old_primary_state->base.visible))
5071                         intel_post_enable_primary(&crtc->base);
5072         }
5073 }
5074
5075 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5076                                    struct intel_crtc_state *pipe_config)
5077 {
5078         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5079         struct drm_device *dev = crtc->base.dev;
5080         struct drm_i915_private *dev_priv = to_i915(dev);
5081         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5082         struct drm_plane *primary = crtc->base.primary;
5083         struct drm_plane_state *old_pri_state =
5084                 drm_atomic_get_existing_plane_state(old_state, primary);
5085         bool modeset = needs_modeset(&pipe_config->base);
5086         struct intel_atomic_state *old_intel_state =
5087                 to_intel_atomic_state(old_state);
5088
5089         if (old_pri_state) {
5090                 struct intel_plane_state *primary_state =
5091                         intel_atomic_get_new_plane_state(old_intel_state,
5092                                                          to_intel_plane(primary));
5093                 struct intel_plane_state *old_primary_state =
5094                         to_intel_plane_state(old_pri_state);
5095
5096                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5097
5098                 if (old_primary_state->base.visible &&
5099                     (modeset || !primary_state->base.visible))
5100                         intel_pre_disable_primary(&crtc->base);
5101         }
5102
5103         /*
5104          * Vblank time updates from the shadow to live plane control register
5105          * are blocked if the memory self-refresh mode is active at that
5106          * moment. So to make sure the plane gets truly disabled, disable
5107          * first the self-refresh mode. The self-refresh enable bit in turn
5108          * will be checked/applied by the HW only at the next frame start
5109          * event which is after the vblank start event, so we need to have a
5110          * wait-for-vblank between disabling the plane and the pipe.
5111          */
5112         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5113             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5114                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5115
5116         /*
5117          * IVB workaround: must disable low power watermarks for at least
5118          * one frame before enabling scaling.  LP watermarks can be re-enabled
5119          * when scaling is disabled.
5120          *
5121          * WaCxSRDisabledForSpriteScaling:ivb
5122          */
5123         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5124                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5125
5126         /*
5127          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5128          * watermark programming here.
5129          */
5130         if (needs_modeset(&pipe_config->base))
5131                 return;
5132
5133         /*
5134          * For platforms that support atomic watermarks, program the
5135          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5136          * will be the intermediate values that are safe for both pre- and
5137          * post- vblank; when vblank happens, the 'active' values will be set
5138          * to the final 'target' values and we'll do this again to get the
5139          * optimal watermarks.  For gen9+ platforms, the values we program here
5140          * will be the final target values which will get automatically latched
5141          * at vblank time; no further programming will be necessary.
5142          *
5143          * If a platform hasn't been transitioned to atomic watermarks yet,
5144          * we'll continue to update watermarks the old way, if flags tell
5145          * us to.
5146          */
5147         if (dev_priv->display.initial_watermarks != NULL)
5148                 dev_priv->display.initial_watermarks(old_intel_state,
5149                                                      pipe_config);
5150         else if (pipe_config->update_wm_pre)
5151                 intel_update_watermarks(crtc);
5152 }
5153
5154 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5155 {
5156         struct drm_device *dev = crtc->dev;
5157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5158         struct drm_plane *p;
5159         int pipe = intel_crtc->pipe;
5160
5161         intel_crtc_dpms_overlay_disable(intel_crtc);
5162
5163         drm_for_each_plane_mask(p, dev, plane_mask)
5164                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5165
5166         /*
5167          * FIXME: Once we grow proper nuclear flip support out of this we need
5168          * to compute the mask of flip planes precisely. For the time being
5169          * consider this a flip to a NULL plane.
5170          */
5171         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5172 }
5173
5174 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5175                                           struct intel_crtc_state *crtc_state,
5176                                           struct drm_atomic_state *old_state)
5177 {
5178         struct drm_connector_state *conn_state;
5179         struct drm_connector *conn;
5180         int i;
5181
5182         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5183                 struct intel_encoder *encoder =
5184                         to_intel_encoder(conn_state->best_encoder);
5185
5186                 if (conn_state->crtc != crtc)
5187                         continue;
5188
5189                 if (encoder->pre_pll_enable)
5190                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5191         }
5192 }
5193
5194 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5195                                       struct intel_crtc_state *crtc_state,
5196                                       struct drm_atomic_state *old_state)
5197 {
5198         struct drm_connector_state *conn_state;
5199         struct drm_connector *conn;
5200         int i;
5201
5202         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5203                 struct intel_encoder *encoder =
5204                         to_intel_encoder(conn_state->best_encoder);
5205
5206                 if (conn_state->crtc != crtc)
5207                         continue;
5208
5209                 if (encoder->pre_enable)
5210                         encoder->pre_enable(encoder, crtc_state, conn_state);
5211         }
5212 }
5213
5214 static void intel_encoders_enable(struct drm_crtc *crtc,
5215                                   struct intel_crtc_state *crtc_state,
5216                                   struct drm_atomic_state *old_state)
5217 {
5218         struct drm_connector_state *conn_state;
5219         struct drm_connector *conn;
5220         int i;
5221
5222         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5223                 struct intel_encoder *encoder =
5224                         to_intel_encoder(conn_state->best_encoder);
5225
5226                 if (conn_state->crtc != crtc)
5227                         continue;
5228
5229                 encoder->enable(encoder, crtc_state, conn_state);
5230                 intel_opregion_notify_encoder(encoder, true);
5231         }
5232 }
5233
5234 static void intel_encoders_disable(struct drm_crtc *crtc,
5235                                    struct intel_crtc_state *old_crtc_state,
5236                                    struct drm_atomic_state *old_state)
5237 {
5238         struct drm_connector_state *old_conn_state;
5239         struct drm_connector *conn;
5240         int i;
5241
5242         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5243                 struct intel_encoder *encoder =
5244                         to_intel_encoder(old_conn_state->best_encoder);
5245
5246                 if (old_conn_state->crtc != crtc)
5247                         continue;
5248
5249                 intel_opregion_notify_encoder(encoder, false);
5250                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5251         }
5252 }
5253
5254 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5255                                         struct intel_crtc_state *old_crtc_state,
5256                                         struct drm_atomic_state *old_state)
5257 {
5258         struct drm_connector_state *old_conn_state;
5259         struct drm_connector *conn;
5260         int i;
5261
5262         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5263                 struct intel_encoder *encoder =
5264                         to_intel_encoder(old_conn_state->best_encoder);
5265
5266                 if (old_conn_state->crtc != crtc)
5267                         continue;
5268
5269                 if (encoder->post_disable)
5270                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5271         }
5272 }
5273
5274 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5275                                             struct intel_crtc_state *old_crtc_state,
5276                                             struct drm_atomic_state *old_state)
5277 {
5278         struct drm_connector_state *old_conn_state;
5279         struct drm_connector *conn;
5280         int i;
5281
5282         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5283                 struct intel_encoder *encoder =
5284                         to_intel_encoder(old_conn_state->best_encoder);
5285
5286                 if (old_conn_state->crtc != crtc)
5287                         continue;
5288
5289                 if (encoder->post_pll_disable)
5290                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5291         }
5292 }
5293
5294 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5295                                  struct drm_atomic_state *old_state)
5296 {
5297         struct drm_crtc *crtc = pipe_config->base.crtc;
5298         struct drm_device *dev = crtc->dev;
5299         struct drm_i915_private *dev_priv = to_i915(dev);
5300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5301         int pipe = intel_crtc->pipe;
5302         struct intel_atomic_state *old_intel_state =
5303                 to_intel_atomic_state(old_state);
5304
5305         if (WARN_ON(intel_crtc->active))
5306                 return;
5307
5308         /*
5309          * Sometimes spurious CPU pipe underruns happen during FDI
5310          * training, at least with VGA+HDMI cloning. Suppress them.
5311          *
5312          * On ILK we get an occasional spurious CPU pipe underruns
5313          * between eDP port A enable and vdd enable. Also PCH port
5314          * enable seems to result in the occasional CPU pipe underrun.
5315          *
5316          * Spurious PCH underruns also occur during PCH enabling.
5317          */
5318         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5319                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5320         if (intel_crtc->config->has_pch_encoder)
5321                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5322
5323         if (intel_crtc->config->has_pch_encoder)
5324                 intel_prepare_shared_dpll(intel_crtc);
5325
5326         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5327                 intel_dp_set_m_n(intel_crtc, M1_N1);
5328
5329         intel_set_pipe_timings(intel_crtc);
5330         intel_set_pipe_src_size(intel_crtc);
5331
5332         if (intel_crtc->config->has_pch_encoder) {
5333                 intel_cpu_transcoder_set_m_n(intel_crtc,
5334                                      &intel_crtc->config->fdi_m_n, NULL);
5335         }
5336
5337         ironlake_set_pipeconf(crtc);
5338
5339         intel_crtc->active = true;
5340
5341         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5342
5343         if (intel_crtc->config->has_pch_encoder) {
5344                 /* Note: FDI PLL enabling _must_ be done before we enable the
5345                  * cpu pipes, hence this is separate from all the other fdi/pch
5346                  * enabling. */
5347                 ironlake_fdi_pll_enable(intel_crtc);
5348         } else {
5349                 assert_fdi_tx_disabled(dev_priv, pipe);
5350                 assert_fdi_rx_disabled(dev_priv, pipe);
5351         }
5352
5353         ironlake_pfit_enable(intel_crtc);
5354
5355         /*
5356          * On ILK+ LUT must be loaded before the pipe is running but with
5357          * clocks enabled
5358          */
5359         intel_color_load_luts(&pipe_config->base);
5360
5361         if (dev_priv->display.initial_watermarks != NULL)
5362                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5363         intel_enable_pipe(intel_crtc);
5364
5365         if (intel_crtc->config->has_pch_encoder)
5366                 ironlake_pch_enable(pipe_config);
5367
5368         assert_vblank_disabled(crtc);
5369         drm_crtc_vblank_on(crtc);
5370
5371         intel_encoders_enable(crtc, pipe_config, old_state);
5372
5373         if (HAS_PCH_CPT(dev_priv))
5374                 cpt_verify_modeset(dev, intel_crtc->pipe);
5375
5376         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5377         if (intel_crtc->config->has_pch_encoder)
5378                 intel_wait_for_vblank(dev_priv, pipe);
5379         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5380         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5381 }
5382
5383 /* IPS only exists on ULT machines and is tied to pipe A. */
5384 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5385 {
5386         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5387 }
5388
5389 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5390                                             enum pipe pipe, bool apply)
5391 {
5392         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5393         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5394
5395         if (apply)
5396                 val |= mask;
5397         else
5398                 val &= ~mask;
5399
5400         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5401 }
5402
5403 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5404                                 struct drm_atomic_state *old_state)
5405 {
5406         struct drm_crtc *crtc = pipe_config->base.crtc;
5407         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5409         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5410         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5411         struct intel_atomic_state *old_intel_state =
5412                 to_intel_atomic_state(old_state);
5413         bool psl_clkgate_wa;
5414
5415         if (WARN_ON(intel_crtc->active))
5416                 return;
5417
5418         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5419
5420         if (intel_crtc->config->shared_dpll)
5421                 intel_enable_shared_dpll(intel_crtc);
5422
5423         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5424                 intel_dp_set_m_n(intel_crtc, M1_N1);
5425
5426         if (!transcoder_is_dsi(cpu_transcoder))
5427                 intel_set_pipe_timings(intel_crtc);
5428
5429         intel_set_pipe_src_size(intel_crtc);
5430
5431         if (cpu_transcoder != TRANSCODER_EDP &&
5432             !transcoder_is_dsi(cpu_transcoder)) {
5433                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5434                            intel_crtc->config->pixel_multiplier - 1);
5435         }
5436
5437         if (intel_crtc->config->has_pch_encoder) {
5438                 intel_cpu_transcoder_set_m_n(intel_crtc,
5439                                      &intel_crtc->config->fdi_m_n, NULL);
5440         }
5441
5442         if (!transcoder_is_dsi(cpu_transcoder))
5443                 haswell_set_pipeconf(crtc);
5444
5445         haswell_set_pipemisc(crtc);
5446
5447         intel_color_set_csc(&pipe_config->base);
5448
5449         intel_crtc->active = true;
5450
5451         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5452
5453         if (!transcoder_is_dsi(cpu_transcoder))
5454                 intel_ddi_enable_pipe_clock(pipe_config);
5455
5456         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5457         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5458                          intel_crtc->config->pch_pfit.enabled;
5459         if (psl_clkgate_wa)
5460                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5461
5462         if (INTEL_GEN(dev_priv) >= 9)
5463                 skylake_pfit_enable(intel_crtc);
5464         else
5465                 ironlake_pfit_enable(intel_crtc);
5466
5467         /*
5468          * On ILK+ LUT must be loaded before the pipe is running but with
5469          * clocks enabled
5470          */
5471         intel_color_load_luts(&pipe_config->base);
5472
5473         intel_ddi_set_pipe_settings(pipe_config);
5474         if (!transcoder_is_dsi(cpu_transcoder))
5475                 intel_ddi_enable_transcoder_func(pipe_config);
5476
5477         if (dev_priv->display.initial_watermarks != NULL)
5478                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5479
5480         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5481         if (!transcoder_is_dsi(cpu_transcoder))
5482                 intel_enable_pipe(intel_crtc);
5483
5484         if (intel_crtc->config->has_pch_encoder)
5485                 lpt_pch_enable(pipe_config);
5486
5487         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5488                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5489
5490         assert_vblank_disabled(crtc);
5491         drm_crtc_vblank_on(crtc);
5492
5493         intel_encoders_enable(crtc, pipe_config, old_state);
5494
5495         if (psl_clkgate_wa) {
5496                 intel_wait_for_vblank(dev_priv, pipe);
5497                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5498         }
5499
5500         /* If we change the relative order between pipe/planes enabling, we need
5501          * to change the workaround. */
5502         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5503         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5504                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5505                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5506         }
5507 }
5508
5509 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5510 {
5511         struct drm_device *dev = crtc->base.dev;
5512         struct drm_i915_private *dev_priv = to_i915(dev);
5513         int pipe = crtc->pipe;
5514
5515         /* To avoid upsetting the power well on haswell only disable the pfit if
5516          * it's in use. The hw state code will make sure we get this right. */
5517         if (force || crtc->config->pch_pfit.enabled) {
5518                 I915_WRITE(PF_CTL(pipe), 0);
5519                 I915_WRITE(PF_WIN_POS(pipe), 0);
5520                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5521         }
5522 }
5523
5524 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5525                                   struct drm_atomic_state *old_state)
5526 {
5527         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5528         struct drm_device *dev = crtc->dev;
5529         struct drm_i915_private *dev_priv = to_i915(dev);
5530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5531         int pipe = intel_crtc->pipe;
5532
5533         /*
5534          * Sometimes spurious CPU pipe underruns happen when the
5535          * pipe is already disabled, but FDI RX/TX is still enabled.
5536          * Happens at least with VGA+HDMI cloning. Suppress them.
5537          */
5538         if (intel_crtc->config->has_pch_encoder) {
5539                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5540                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5541         }
5542
5543         intel_encoders_disable(crtc, old_crtc_state, old_state);
5544
5545         drm_crtc_vblank_off(crtc);
5546         assert_vblank_disabled(crtc);
5547
5548         intel_disable_pipe(intel_crtc);
5549
5550         ironlake_pfit_disable(intel_crtc, false);
5551
5552         if (intel_crtc->config->has_pch_encoder)
5553                 ironlake_fdi_disable(crtc);
5554
5555         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5556
5557         if (intel_crtc->config->has_pch_encoder) {
5558                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5559
5560                 if (HAS_PCH_CPT(dev_priv)) {
5561                         i915_reg_t reg;
5562                         u32 temp;
5563
5564                         /* disable TRANS_DP_CTL */
5565                         reg = TRANS_DP_CTL(pipe);
5566                         temp = I915_READ(reg);
5567                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5568                                   TRANS_DP_PORT_SEL_MASK);
5569                         temp |= TRANS_DP_PORT_SEL_NONE;
5570                         I915_WRITE(reg, temp);
5571
5572                         /* disable DPLL_SEL */
5573                         temp = I915_READ(PCH_DPLL_SEL);
5574                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5575                         I915_WRITE(PCH_DPLL_SEL, temp);
5576                 }
5577
5578                 ironlake_fdi_pll_disable(intel_crtc);
5579         }
5580
5581         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5582         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5583 }
5584
5585 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5586                                  struct drm_atomic_state *old_state)
5587 {
5588         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5589         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5591         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5592
5593         intel_encoders_disable(crtc, old_crtc_state, old_state);
5594
5595         drm_crtc_vblank_off(crtc);
5596         assert_vblank_disabled(crtc);
5597
5598         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5599         if (!transcoder_is_dsi(cpu_transcoder))
5600                 intel_disable_pipe(intel_crtc);
5601
5602         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5603                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5604
5605         if (!transcoder_is_dsi(cpu_transcoder))
5606                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5607
5608         if (INTEL_GEN(dev_priv) >= 9)
5609                 skylake_scaler_disable(intel_crtc);
5610         else
5611                 ironlake_pfit_disable(intel_crtc, false);
5612
5613         if (!transcoder_is_dsi(cpu_transcoder))
5614                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5615
5616         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5617 }
5618
5619 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5620 {
5621         struct drm_device *dev = crtc->base.dev;
5622         struct drm_i915_private *dev_priv = to_i915(dev);
5623         struct intel_crtc_state *pipe_config = crtc->config;
5624
5625         if (!pipe_config->gmch_pfit.control)
5626                 return;
5627
5628         /*
5629          * The panel fitter should only be adjusted whilst the pipe is disabled,
5630          * according to register description and PRM.
5631          */
5632         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5633         assert_pipe_disabled(dev_priv, crtc->pipe);
5634
5635         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5636         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5637
5638         /* Border color in case we don't scale up to the full screen. Black by
5639          * default, change to something else for debugging. */
5640         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5641 }
5642
5643 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5644 {
5645         switch (port) {
5646         case PORT_A:
5647                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5648         case PORT_B:
5649                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5650         case PORT_C:
5651                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5652         case PORT_D:
5653                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5654         case PORT_E:
5655                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5656         default:
5657                 MISSING_CASE(port);
5658                 return POWER_DOMAIN_PORT_OTHER;
5659         }
5660 }
5661
5662 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5663                                   struct intel_crtc_state *crtc_state)
5664 {
5665         struct drm_device *dev = crtc->dev;
5666         struct drm_i915_private *dev_priv = to_i915(dev);
5667         struct drm_encoder *encoder;
5668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5669         enum pipe pipe = intel_crtc->pipe;
5670         u64 mask;
5671         enum transcoder transcoder = crtc_state->cpu_transcoder;
5672
5673         if (!crtc_state->base.active)
5674                 return 0;
5675
5676         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5677         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5678         if (crtc_state->pch_pfit.enabled ||
5679             crtc_state->pch_pfit.force_thru)
5680                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5681
5682         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5683                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5684
5685                 mask |= BIT_ULL(intel_encoder->power_domain);
5686         }
5687
5688         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5689                 mask |= BIT(POWER_DOMAIN_AUDIO);
5690
5691         if (crtc_state->shared_dpll)
5692                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5693
5694         return mask;
5695 }
5696
5697 static u64
5698 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5699                                struct intel_crtc_state *crtc_state)
5700 {
5701         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5703         enum intel_display_power_domain domain;
5704         u64 domains, new_domains, old_domains;
5705
5706         old_domains = intel_crtc->enabled_power_domains;
5707         intel_crtc->enabled_power_domains = new_domains =
5708                 get_crtc_power_domains(crtc, crtc_state);
5709
5710         domains = new_domains & ~old_domains;
5711
5712         for_each_power_domain(domain, domains)
5713                 intel_display_power_get(dev_priv, domain);
5714
5715         return old_domains & ~new_domains;
5716 }
5717
5718 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5719                                       u64 domains)
5720 {
5721         enum intel_display_power_domain domain;
5722
5723         for_each_power_domain(domain, domains)
5724                 intel_display_power_put(dev_priv, domain);
5725 }
5726
5727 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5728                                    struct drm_atomic_state *old_state)
5729 {
5730         struct intel_atomic_state *old_intel_state =
5731                 to_intel_atomic_state(old_state);
5732         struct drm_crtc *crtc = pipe_config->base.crtc;
5733         struct drm_device *dev = crtc->dev;
5734         struct drm_i915_private *dev_priv = to_i915(dev);
5735         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5736         int pipe = intel_crtc->pipe;
5737
5738         if (WARN_ON(intel_crtc->active))
5739                 return;
5740
5741         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5742                 intel_dp_set_m_n(intel_crtc, M1_N1);
5743
5744         intel_set_pipe_timings(intel_crtc);
5745         intel_set_pipe_src_size(intel_crtc);
5746
5747         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5748                 struct drm_i915_private *dev_priv = to_i915(dev);
5749
5750                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5751                 I915_WRITE(CHV_CANVAS(pipe), 0);
5752         }
5753
5754         i9xx_set_pipeconf(intel_crtc);
5755
5756         intel_crtc->active = true;
5757
5758         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5759
5760         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5761
5762         if (IS_CHERRYVIEW(dev_priv)) {
5763                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5764                 chv_enable_pll(intel_crtc, intel_crtc->config);
5765         } else {
5766                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5767                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5768         }
5769
5770         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5771
5772         i9xx_pfit_enable(intel_crtc);
5773
5774         intel_color_load_luts(&pipe_config->base);
5775
5776         dev_priv->display.initial_watermarks(old_intel_state,
5777                                              pipe_config);
5778         intel_enable_pipe(intel_crtc);
5779
5780         assert_vblank_disabled(crtc);
5781         drm_crtc_vblank_on(crtc);
5782
5783         intel_encoders_enable(crtc, pipe_config, old_state);
5784 }
5785
5786 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5787 {
5788         struct drm_device *dev = crtc->base.dev;
5789         struct drm_i915_private *dev_priv = to_i915(dev);
5790
5791         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5792         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5793 }
5794
5795 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5796                              struct drm_atomic_state *old_state)
5797 {
5798         struct intel_atomic_state *old_intel_state =
5799                 to_intel_atomic_state(old_state);
5800         struct drm_crtc *crtc = pipe_config->base.crtc;
5801         struct drm_device *dev = crtc->dev;
5802         struct drm_i915_private *dev_priv = to_i915(dev);
5803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5804         enum pipe pipe = intel_crtc->pipe;
5805
5806         if (WARN_ON(intel_crtc->active))
5807                 return;
5808
5809         i9xx_set_pll_dividers(intel_crtc);
5810
5811         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5812                 intel_dp_set_m_n(intel_crtc, M1_N1);
5813
5814         intel_set_pipe_timings(intel_crtc);
5815         intel_set_pipe_src_size(intel_crtc);
5816
5817         i9xx_set_pipeconf(intel_crtc);
5818
5819         intel_crtc->active = true;
5820
5821         if (!IS_GEN2(dev_priv))
5822                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5823
5824         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5825
5826         i9xx_enable_pll(intel_crtc, pipe_config);
5827
5828         i9xx_pfit_enable(intel_crtc);
5829
5830         intel_color_load_luts(&pipe_config->base);
5831
5832         if (dev_priv->display.initial_watermarks != NULL)
5833                 dev_priv->display.initial_watermarks(old_intel_state,
5834                                                      intel_crtc->config);
5835         else
5836                 intel_update_watermarks(intel_crtc);
5837         intel_enable_pipe(intel_crtc);
5838
5839         assert_vblank_disabled(crtc);
5840         drm_crtc_vblank_on(crtc);
5841
5842         intel_encoders_enable(crtc, pipe_config, old_state);
5843 }
5844
5845 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5846 {
5847         struct drm_device *dev = crtc->base.dev;
5848         struct drm_i915_private *dev_priv = to_i915(dev);
5849
5850         if (!crtc->config->gmch_pfit.control)
5851                 return;
5852
5853         assert_pipe_disabled(dev_priv, crtc->pipe);
5854
5855         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5856                          I915_READ(PFIT_CONTROL));
5857         I915_WRITE(PFIT_CONTROL, 0);
5858 }
5859
5860 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5861                               struct drm_atomic_state *old_state)
5862 {
5863         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5864         struct drm_device *dev = crtc->dev;
5865         struct drm_i915_private *dev_priv = to_i915(dev);
5866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5867         int pipe = intel_crtc->pipe;
5868
5869         /*
5870          * On gen2 planes are double buffered but the pipe isn't, so we must
5871          * wait for planes to fully turn off before disabling the pipe.
5872          */
5873         if (IS_GEN2(dev_priv))
5874                 intel_wait_for_vblank(dev_priv, pipe);
5875
5876         intel_encoders_disable(crtc, old_crtc_state, old_state);
5877
5878         drm_crtc_vblank_off(crtc);
5879         assert_vblank_disabled(crtc);
5880
5881         intel_disable_pipe(intel_crtc);
5882
5883         i9xx_pfit_disable(intel_crtc);
5884
5885         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5886
5887         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5888                 if (IS_CHERRYVIEW(dev_priv))
5889                         chv_disable_pll(dev_priv, pipe);
5890                 else if (IS_VALLEYVIEW(dev_priv))
5891                         vlv_disable_pll(dev_priv, pipe);
5892                 else
5893                         i9xx_disable_pll(intel_crtc);
5894         }
5895
5896         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5897
5898         if (!IS_GEN2(dev_priv))
5899                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5900
5901         if (!dev_priv->display.initial_watermarks)
5902                 intel_update_watermarks(intel_crtc);
5903
5904         /* clock the pipe down to 640x480@60 to potentially save power */
5905         if (IS_I830(dev_priv))
5906                 i830_enable_pipe(dev_priv, pipe);
5907 }
5908
5909 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5910                                         struct drm_modeset_acquire_ctx *ctx)
5911 {
5912         struct intel_encoder *encoder;
5913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5914         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5915         enum intel_display_power_domain domain;
5916         u64 domains;
5917         struct drm_atomic_state *state;
5918         struct intel_crtc_state *crtc_state;
5919         int ret;
5920
5921         if (!intel_crtc->active)
5922                 return;
5923
5924         if (crtc->primary->state->visible) {
5925                 intel_pre_disable_primary_noatomic(crtc);
5926
5927                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5928                 crtc->primary->state->visible = false;
5929         }
5930
5931         state = drm_atomic_state_alloc(crtc->dev);
5932         if (!state) {
5933                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5934                               crtc->base.id, crtc->name);
5935                 return;
5936         }
5937
5938         state->acquire_ctx = ctx;
5939
5940         /* Everything's already locked, -EDEADLK can't happen. */
5941         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5942         ret = drm_atomic_add_affected_connectors(state, crtc);
5943
5944         WARN_ON(IS_ERR(crtc_state) || ret);
5945
5946         dev_priv->display.crtc_disable(crtc_state, state);
5947
5948         drm_atomic_state_put(state);
5949
5950         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5951                       crtc->base.id, crtc->name);
5952
5953         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5954         crtc->state->active = false;
5955         intel_crtc->active = false;
5956         crtc->enabled = false;
5957         crtc->state->connector_mask = 0;
5958         crtc->state->encoder_mask = 0;
5959
5960         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5961                 encoder->base.crtc = NULL;
5962
5963         intel_fbc_disable(intel_crtc);
5964         intel_update_watermarks(intel_crtc);
5965         intel_disable_shared_dpll(intel_crtc);
5966
5967         domains = intel_crtc->enabled_power_domains;
5968         for_each_power_domain(domain, domains)
5969                 intel_display_power_put(dev_priv, domain);
5970         intel_crtc->enabled_power_domains = 0;
5971
5972         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5973         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
5974         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
5975 }
5976
5977 /*
5978  * turn all crtc's off, but do not adjust state
5979  * This has to be paired with a call to intel_modeset_setup_hw_state.
5980  */
5981 int intel_display_suspend(struct drm_device *dev)
5982 {
5983         struct drm_i915_private *dev_priv = to_i915(dev);
5984         struct drm_atomic_state *state;
5985         int ret;
5986
5987         state = drm_atomic_helper_suspend(dev);
5988         ret = PTR_ERR_OR_ZERO(state);
5989         if (ret)
5990                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5991         else
5992                 dev_priv->modeset_restore_state = state;
5993         return ret;
5994 }
5995
5996 void intel_encoder_destroy(struct drm_encoder *encoder)
5997 {
5998         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5999
6000         drm_encoder_cleanup(encoder);
6001         kfree(intel_encoder);
6002 }
6003
6004 /* Cross check the actual hw state with our own modeset state tracking (and it's
6005  * internal consistency). */
6006 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6007                                          struct drm_connector_state *conn_state)
6008 {
6009         struct intel_connector *connector = to_intel_connector(conn_state->connector);
6010
6011         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6012                       connector->base.base.id,
6013                       connector->base.name);
6014
6015         if (connector->get_hw_state(connector)) {
6016                 struct intel_encoder *encoder = connector->encoder;
6017
6018                 I915_STATE_WARN(!crtc_state,
6019                          "connector enabled without attached crtc\n");
6020
6021                 if (!crtc_state)
6022                         return;
6023
6024                 I915_STATE_WARN(!crtc_state->active,
6025                       "connector is active, but attached crtc isn't\n");
6026
6027                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6028                         return;
6029
6030                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6031                         "atomic encoder doesn't match attached encoder\n");
6032
6033                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6034                         "attached encoder crtc differs from connector crtc\n");
6035         } else {
6036                 I915_STATE_WARN(crtc_state && crtc_state->active,
6037                         "attached crtc is active, but connector isn't\n");
6038                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6039                         "best encoder set without crtc!\n");
6040         }
6041 }
6042
6043 int intel_connector_init(struct intel_connector *connector)
6044 {
6045         struct intel_digital_connector_state *conn_state;
6046
6047         /*
6048          * Allocate enough memory to hold intel_digital_connector_state,
6049          * This might be a few bytes too many, but for connectors that don't
6050          * need it we'll free the state and allocate a smaller one on the first
6051          * succesful commit anyway.
6052          */
6053         conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6054         if (!conn_state)
6055                 return -ENOMEM;
6056
6057         __drm_atomic_helper_connector_reset(&connector->base,
6058                                             &conn_state->base);
6059
6060         return 0;
6061 }
6062
6063 struct intel_connector *intel_connector_alloc(void)
6064 {
6065         struct intel_connector *connector;
6066
6067         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6068         if (!connector)
6069                 return NULL;
6070
6071         if (intel_connector_init(connector) < 0) {
6072                 kfree(connector);
6073                 return NULL;
6074         }
6075
6076         return connector;
6077 }
6078
6079 /*
6080  * Free the bits allocated by intel_connector_alloc.
6081  * This should only be used after intel_connector_alloc has returned
6082  * successfully, and before drm_connector_init returns successfully.
6083  * Otherwise the destroy callbacks for the connector and the state should
6084  * take care of proper cleanup/free
6085  */
6086 void intel_connector_free(struct intel_connector *connector)
6087 {
6088         kfree(to_intel_digital_connector_state(connector->base.state));
6089         kfree(connector);
6090 }
6091
6092 /* Simple connector->get_hw_state implementation for encoders that support only
6093  * one connector and no cloning and hence the encoder state determines the state
6094  * of the connector. */
6095 bool intel_connector_get_hw_state(struct intel_connector *connector)
6096 {
6097         enum pipe pipe = 0;
6098         struct intel_encoder *encoder = connector->encoder;
6099
6100         return encoder->get_hw_state(encoder, &pipe);
6101 }
6102
6103 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6104 {
6105         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6106                 return crtc_state->fdi_lanes;
6107
6108         return 0;
6109 }
6110
6111 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6112                                      struct intel_crtc_state *pipe_config)
6113 {
6114         struct drm_i915_private *dev_priv = to_i915(dev);
6115         struct drm_atomic_state *state = pipe_config->base.state;
6116         struct intel_crtc *other_crtc;
6117         struct intel_crtc_state *other_crtc_state;
6118
6119         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6120                       pipe_name(pipe), pipe_config->fdi_lanes);
6121         if (pipe_config->fdi_lanes > 4) {
6122                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6123                               pipe_name(pipe), pipe_config->fdi_lanes);
6124                 return -EINVAL;
6125         }
6126
6127         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6128                 if (pipe_config->fdi_lanes > 2) {
6129                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6130                                       pipe_config->fdi_lanes);
6131                         return -EINVAL;
6132                 } else {
6133                         return 0;
6134                 }
6135         }
6136
6137         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6138                 return 0;
6139
6140         /* Ivybridge 3 pipe is really complicated */
6141         switch (pipe) {
6142         case PIPE_A:
6143                 return 0;
6144         case PIPE_B:
6145                 if (pipe_config->fdi_lanes <= 2)
6146                         return 0;
6147
6148                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6149                 other_crtc_state =
6150                         intel_atomic_get_crtc_state(state, other_crtc);
6151                 if (IS_ERR(other_crtc_state))
6152                         return PTR_ERR(other_crtc_state);
6153
6154                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6155                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6156                                       pipe_name(pipe), pipe_config->fdi_lanes);
6157                         return -EINVAL;
6158                 }
6159                 return 0;
6160         case PIPE_C:
6161                 if (pipe_config->fdi_lanes > 2) {
6162                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6163                                       pipe_name(pipe), pipe_config->fdi_lanes);
6164                         return -EINVAL;
6165                 }
6166
6167                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6168                 other_crtc_state =
6169                         intel_atomic_get_crtc_state(state, other_crtc);
6170                 if (IS_ERR(other_crtc_state))
6171                         return PTR_ERR(other_crtc_state);
6172
6173                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6174                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6175                         return -EINVAL;
6176                 }
6177                 return 0;
6178         default:
6179                 BUG();
6180         }
6181 }
6182
6183 #define RETRY 1
6184 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6185                                        struct intel_crtc_state *pipe_config)
6186 {
6187         struct drm_device *dev = intel_crtc->base.dev;
6188         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6189         int lane, link_bw, fdi_dotclock, ret;
6190         bool needs_recompute = false;
6191
6192 retry:
6193         /* FDI is a binary signal running at ~2.7GHz, encoding
6194          * each output octet as 10 bits. The actual frequency
6195          * is stored as a divider into a 100MHz clock, and the
6196          * mode pixel clock is stored in units of 1KHz.
6197          * Hence the bw of each lane in terms of the mode signal
6198          * is:
6199          */
6200         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6201
6202         fdi_dotclock = adjusted_mode->crtc_clock;
6203
6204         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6205                                            pipe_config->pipe_bpp);
6206
6207         pipe_config->fdi_lanes = lane;
6208
6209         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6210                                link_bw, &pipe_config->fdi_m_n, false);
6211
6212         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6213         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6214                 pipe_config->pipe_bpp -= 2*3;
6215                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6216                               pipe_config->pipe_bpp);
6217                 needs_recompute = true;
6218                 pipe_config->bw_constrained = true;
6219
6220                 goto retry;
6221         }
6222
6223         if (needs_recompute)
6224                 return RETRY;
6225
6226         return ret;
6227 }
6228
6229 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6230                                      struct intel_crtc_state *pipe_config)
6231 {
6232         if (pipe_config->ips_force_disable)
6233                 return false;
6234
6235         if (pipe_config->pipe_bpp > 24)
6236                 return false;
6237
6238         /* HSW can handle pixel rate up to cdclk? */
6239         if (IS_HASWELL(dev_priv))
6240                 return true;
6241
6242         /*
6243          * We compare against max which means we must take
6244          * the increased cdclk requirement into account when
6245          * calculating the new cdclk.
6246          *
6247          * Should measure whether using a lower cdclk w/o IPS
6248          */
6249         return pipe_config->pixel_rate <=
6250                 dev_priv->max_cdclk_freq * 95 / 100;
6251 }
6252
6253 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6254                                    struct intel_crtc_state *pipe_config)
6255 {
6256         struct drm_device *dev = crtc->base.dev;
6257         struct drm_i915_private *dev_priv = to_i915(dev);
6258
6259         pipe_config->ips_enabled = i915_modparams.enable_ips &&
6260                 hsw_crtc_supports_ips(crtc) &&
6261                 pipe_config_supports_ips(dev_priv, pipe_config);
6262 }
6263
6264 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6265 {
6266         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6267
6268         /* GDG double wide on either pipe, otherwise pipe A only */
6269         return INTEL_INFO(dev_priv)->gen < 4 &&
6270                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6271 }
6272
6273 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6274 {
6275         uint32_t pixel_rate;
6276
6277         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6278
6279         /*
6280          * We only use IF-ID interlacing. If we ever use
6281          * PF-ID we'll need to adjust the pixel_rate here.
6282          */
6283
6284         if (pipe_config->pch_pfit.enabled) {
6285                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6286                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6287
6288                 pipe_w = pipe_config->pipe_src_w;
6289                 pipe_h = pipe_config->pipe_src_h;
6290
6291                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6292                 pfit_h = pfit_size & 0xFFFF;
6293                 if (pipe_w < pfit_w)
6294                         pipe_w = pfit_w;
6295                 if (pipe_h < pfit_h)
6296                         pipe_h = pfit_h;
6297
6298                 if (WARN_ON(!pfit_w || !pfit_h))
6299                         return pixel_rate;
6300
6301                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6302                                      pfit_w * pfit_h);
6303         }
6304
6305         return pixel_rate;
6306 }
6307
6308 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6309 {
6310         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6311
6312         if (HAS_GMCH_DISPLAY(dev_priv))
6313                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6314                 crtc_state->pixel_rate =
6315                         crtc_state->base.adjusted_mode.crtc_clock;
6316         else
6317                 crtc_state->pixel_rate =
6318                         ilk_pipe_pixel_rate(crtc_state);
6319 }
6320
6321 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6322                                      struct intel_crtc_state *pipe_config)
6323 {
6324         struct drm_device *dev = crtc->base.dev;
6325         struct drm_i915_private *dev_priv = to_i915(dev);
6326         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6327         int clock_limit = dev_priv->max_dotclk_freq;
6328
6329         if (INTEL_GEN(dev_priv) < 4) {
6330                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6331
6332                 /*
6333                  * Enable double wide mode when the dot clock
6334                  * is > 90% of the (display) core speed.
6335                  */
6336                 if (intel_crtc_supports_double_wide(crtc) &&
6337                     adjusted_mode->crtc_clock > clock_limit) {
6338                         clock_limit = dev_priv->max_dotclk_freq;
6339                         pipe_config->double_wide = true;
6340                 }
6341         }
6342
6343         if (adjusted_mode->crtc_clock > clock_limit) {
6344                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6345                               adjusted_mode->crtc_clock, clock_limit,
6346                               yesno(pipe_config->double_wide));
6347                 return -EINVAL;
6348         }
6349
6350         if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6351                 /*
6352                  * There is only one pipe CSC unit per pipe, and we need that
6353                  * for output conversion from RGB->YCBCR. So if CTM is already
6354                  * applied we can't support YCBCR420 output.
6355                  */
6356                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6357                 return -EINVAL;
6358         }
6359
6360         /*
6361          * Pipe horizontal size must be even in:
6362          * - DVO ganged mode
6363          * - LVDS dual channel mode
6364          * - Double wide pipe
6365          */
6366         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6367              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6368                 pipe_config->pipe_src_w &= ~1;
6369
6370         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6371          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6372          */
6373         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6374                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6375                 return -EINVAL;
6376
6377         intel_crtc_compute_pixel_rate(pipe_config);
6378
6379         if (HAS_IPS(dev_priv))
6380                 hsw_compute_ips_config(crtc, pipe_config);
6381
6382         if (pipe_config->has_pch_encoder)
6383                 return ironlake_fdi_compute_config(crtc, pipe_config);
6384
6385         return 0;
6386 }
6387
6388 static void
6389 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6390 {
6391         while (*num > DATA_LINK_M_N_MASK ||
6392                *den > DATA_LINK_M_N_MASK) {
6393                 *num >>= 1;
6394                 *den >>= 1;
6395         }
6396 }
6397
6398 static void compute_m_n(unsigned int m, unsigned int n,
6399                         uint32_t *ret_m, uint32_t *ret_n,
6400                         bool reduce_m_n)
6401 {
6402         /*
6403          * Reduce M/N as much as possible without loss in precision. Several DP
6404          * dongles in particular seem to be fussy about too large *link* M/N
6405          * values. The passed in values are more likely to have the least
6406          * significant bits zero than M after rounding below, so do this first.
6407          */
6408         if (reduce_m_n) {
6409                 while ((m & 1) == 0 && (n & 1) == 0) {
6410                         m >>= 1;
6411                         n >>= 1;
6412                 }
6413         }
6414
6415         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6416         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6417         intel_reduce_m_n_ratio(ret_m, ret_n);
6418 }
6419
6420 void
6421 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6422                        int pixel_clock, int link_clock,
6423                        struct intel_link_m_n *m_n,
6424                        bool reduce_m_n)
6425 {
6426         m_n->tu = 64;
6427
6428         compute_m_n(bits_per_pixel * pixel_clock,
6429                     link_clock * nlanes * 8,
6430                     &m_n->gmch_m, &m_n->gmch_n,
6431                     reduce_m_n);
6432
6433         compute_m_n(pixel_clock, link_clock,
6434                     &m_n->link_m, &m_n->link_n,
6435                     reduce_m_n);
6436 }
6437
6438 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6439 {
6440         if (i915_modparams.panel_use_ssc >= 0)
6441                 return i915_modparams.panel_use_ssc != 0;
6442         return dev_priv->vbt.lvds_use_ssc
6443                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6444 }
6445
6446 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6447 {
6448         return (1 << dpll->n) << 16 | dpll->m2;
6449 }
6450
6451 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6452 {
6453         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6454 }
6455
6456 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6457                                      struct intel_crtc_state *crtc_state,
6458                                      struct dpll *reduced_clock)
6459 {
6460         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6461         u32 fp, fp2 = 0;
6462
6463         if (IS_PINEVIEW(dev_priv)) {
6464                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6465                 if (reduced_clock)
6466                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6467         } else {
6468                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6469                 if (reduced_clock)
6470                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6471         }
6472
6473         crtc_state->dpll_hw_state.fp0 = fp;
6474
6475         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6476             reduced_clock) {
6477                 crtc_state->dpll_hw_state.fp1 = fp2;
6478         } else {
6479                 crtc_state->dpll_hw_state.fp1 = fp;
6480         }
6481 }
6482
6483 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6484                 pipe)
6485 {
6486         u32 reg_val;
6487
6488         /*
6489          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6490          * and set it to a reasonable value instead.
6491          */
6492         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6493         reg_val &= 0xffffff00;
6494         reg_val |= 0x00000030;
6495         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6496
6497         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6498         reg_val &= 0x00ffffff;
6499         reg_val |= 0x8c000000;
6500         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6501
6502         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6503         reg_val &= 0xffffff00;
6504         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6505
6506         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6507         reg_val &= 0x00ffffff;
6508         reg_val |= 0xb0000000;
6509         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6510 }
6511
6512 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6513                                          struct intel_link_m_n *m_n)
6514 {
6515         struct drm_device *dev = crtc->base.dev;
6516         struct drm_i915_private *dev_priv = to_i915(dev);
6517         int pipe = crtc->pipe;
6518
6519         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6520         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6521         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6522         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6523 }
6524
6525 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6526                                          struct intel_link_m_n *m_n,
6527                                          struct intel_link_m_n *m2_n2)
6528 {
6529         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6530         int pipe = crtc->pipe;
6531         enum transcoder transcoder = crtc->config->cpu_transcoder;
6532
6533         if (INTEL_GEN(dev_priv) >= 5) {
6534                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6535                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6536                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6537                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6538                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6539                  * for gen < 8) and if DRRS is supported (to make sure the
6540                  * registers are not unnecessarily accessed).
6541                  */
6542                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6543                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6544                         I915_WRITE(PIPE_DATA_M2(transcoder),
6545                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6546                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6547                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6548                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6549                 }
6550         } else {
6551                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6552                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6553                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6554                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6555         }
6556 }
6557
6558 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6559 {
6560         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6561
6562         if (m_n == M1_N1) {
6563                 dp_m_n = &crtc->config->dp_m_n;
6564                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6565         } else if (m_n == M2_N2) {
6566
6567                 /*
6568                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6569                  * needs to be programmed into M1_N1.
6570                  */
6571                 dp_m_n = &crtc->config->dp_m2_n2;
6572         } else {
6573                 DRM_ERROR("Unsupported divider value\n");
6574                 return;
6575         }
6576
6577         if (crtc->config->has_pch_encoder)
6578                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6579         else
6580                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6581 }
6582
6583 static void vlv_compute_dpll(struct intel_crtc *crtc,
6584                              struct intel_crtc_state *pipe_config)
6585 {
6586         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6587                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6588         if (crtc->pipe != PIPE_A)
6589                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6590
6591         /* DPLL not used with DSI, but still need the rest set up */
6592         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6593                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6594                         DPLL_EXT_BUFFER_ENABLE_VLV;
6595
6596         pipe_config->dpll_hw_state.dpll_md =
6597                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6598 }
6599
6600 static void chv_compute_dpll(struct intel_crtc *crtc,
6601                              struct intel_crtc_state *pipe_config)
6602 {
6603         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6604                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6605         if (crtc->pipe != PIPE_A)
6606                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6607
6608         /* DPLL not used with DSI, but still need the rest set up */
6609         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6610                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6611
6612         pipe_config->dpll_hw_state.dpll_md =
6613                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6614 }
6615
6616 static void vlv_prepare_pll(struct intel_crtc *crtc,
6617                             const struct intel_crtc_state *pipe_config)
6618 {
6619         struct drm_device *dev = crtc->base.dev;
6620         struct drm_i915_private *dev_priv = to_i915(dev);
6621         enum pipe pipe = crtc->pipe;
6622         u32 mdiv;
6623         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6624         u32 coreclk, reg_val;
6625
6626         /* Enable Refclk */
6627         I915_WRITE(DPLL(pipe),
6628                    pipe_config->dpll_hw_state.dpll &
6629                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6630
6631         /* No need to actually set up the DPLL with DSI */
6632         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6633                 return;
6634
6635         mutex_lock(&dev_priv->sb_lock);
6636
6637         bestn = pipe_config->dpll.n;
6638         bestm1 = pipe_config->dpll.m1;
6639         bestm2 = pipe_config->dpll.m2;
6640         bestp1 = pipe_config->dpll.p1;
6641         bestp2 = pipe_config->dpll.p2;
6642
6643         /* See eDP HDMI DPIO driver vbios notes doc */
6644
6645         /* PLL B needs special handling */
6646         if (pipe == PIPE_B)
6647                 vlv_pllb_recal_opamp(dev_priv, pipe);
6648
6649         /* Set up Tx target for periodic Rcomp update */
6650         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6651
6652         /* Disable target IRef on PLL */
6653         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6654         reg_val &= 0x00ffffff;
6655         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6656
6657         /* Disable fast lock */
6658         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6659
6660         /* Set idtafcrecal before PLL is enabled */
6661         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6662         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6663         mdiv |= ((bestn << DPIO_N_SHIFT));
6664         mdiv |= (1 << DPIO_K_SHIFT);
6665
6666         /*
6667          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6668          * but we don't support that).
6669          * Note: don't use the DAC post divider as it seems unstable.
6670          */
6671         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6672         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6673
6674         mdiv |= DPIO_ENABLE_CALIBRATION;
6675         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6676
6677         /* Set HBR and RBR LPF coefficients */
6678         if (pipe_config->port_clock == 162000 ||
6679             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6680             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6681                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6682                                  0x009f0003);
6683         else
6684                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6685                                  0x00d0000f);
6686
6687         if (intel_crtc_has_dp_encoder(pipe_config)) {
6688                 /* Use SSC source */
6689                 if (pipe == PIPE_A)
6690                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6691                                          0x0df40000);
6692                 else
6693                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6694                                          0x0df70000);
6695         } else { /* HDMI or VGA */
6696                 /* Use bend source */
6697                 if (pipe == PIPE_A)
6698                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6699                                          0x0df70000);
6700                 else
6701                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6702                                          0x0df40000);
6703         }
6704
6705         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6706         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6707         if (intel_crtc_has_dp_encoder(crtc->config))
6708                 coreclk |= 0x01000000;
6709         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6710
6711         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6712         mutex_unlock(&dev_priv->sb_lock);
6713 }
6714
6715 static void chv_prepare_pll(struct intel_crtc *crtc,
6716                             const struct intel_crtc_state *pipe_config)
6717 {
6718         struct drm_device *dev = crtc->base.dev;
6719         struct drm_i915_private *dev_priv = to_i915(dev);
6720         enum pipe pipe = crtc->pipe;
6721         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6722         u32 loopfilter, tribuf_calcntr;
6723         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6724         u32 dpio_val;
6725         int vco;
6726
6727         /* Enable Refclk and SSC */
6728         I915_WRITE(DPLL(pipe),
6729                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6730
6731         /* No need to actually set up the DPLL with DSI */
6732         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6733                 return;
6734
6735         bestn = pipe_config->dpll.n;
6736         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6737         bestm1 = pipe_config->dpll.m1;
6738         bestm2 = pipe_config->dpll.m2 >> 22;
6739         bestp1 = pipe_config->dpll.p1;
6740         bestp2 = pipe_config->dpll.p2;
6741         vco = pipe_config->dpll.vco;
6742         dpio_val = 0;
6743         loopfilter = 0;
6744
6745         mutex_lock(&dev_priv->sb_lock);
6746
6747         /* p1 and p2 divider */
6748         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6749                         5 << DPIO_CHV_S1_DIV_SHIFT |
6750                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6751                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6752                         1 << DPIO_CHV_K_DIV_SHIFT);
6753
6754         /* Feedback post-divider - m2 */
6755         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6756
6757         /* Feedback refclk divider - n and m1 */
6758         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6759                         DPIO_CHV_M1_DIV_BY_2 |
6760                         1 << DPIO_CHV_N_DIV_SHIFT);
6761
6762         /* M2 fraction division */
6763         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6764
6765         /* M2 fraction division enable */
6766         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6767         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6768         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6769         if (bestm2_frac)
6770                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6771         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6772
6773         /* Program digital lock detect threshold */
6774         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6775         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6776                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6777         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6778         if (!bestm2_frac)
6779                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6780         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6781
6782         /* Loop filter */
6783         if (vco == 5400000) {
6784                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6785                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6786                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6787                 tribuf_calcntr = 0x9;
6788         } else if (vco <= 6200000) {
6789                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6790                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6791                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6792                 tribuf_calcntr = 0x9;
6793         } else if (vco <= 6480000) {
6794                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6795                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6796                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6797                 tribuf_calcntr = 0x8;
6798         } else {
6799                 /* Not supported. Apply the same limits as in the max case */
6800                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6801                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6802                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6803                 tribuf_calcntr = 0;
6804         }
6805         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6806
6807         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6808         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6809         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6810         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6811
6812         /* AFC Recal */
6813         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6814                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6815                         DPIO_AFC_RECAL);
6816
6817         mutex_unlock(&dev_priv->sb_lock);
6818 }
6819
6820 /**
6821  * vlv_force_pll_on - forcibly enable just the PLL
6822  * @dev_priv: i915 private structure
6823  * @pipe: pipe PLL to enable
6824  * @dpll: PLL configuration
6825  *
6826  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6827  * in cases where we need the PLL enabled even when @pipe is not going to
6828  * be enabled.
6829  */
6830 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6831                      const struct dpll *dpll)
6832 {
6833         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6834         struct intel_crtc_state *pipe_config;
6835
6836         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6837         if (!pipe_config)
6838                 return -ENOMEM;
6839
6840         pipe_config->base.crtc = &crtc->base;
6841         pipe_config->pixel_multiplier = 1;
6842         pipe_config->dpll = *dpll;
6843
6844         if (IS_CHERRYVIEW(dev_priv)) {
6845                 chv_compute_dpll(crtc, pipe_config);
6846                 chv_prepare_pll(crtc, pipe_config);
6847                 chv_enable_pll(crtc, pipe_config);
6848         } else {
6849                 vlv_compute_dpll(crtc, pipe_config);
6850                 vlv_prepare_pll(crtc, pipe_config);
6851                 vlv_enable_pll(crtc, pipe_config);
6852         }
6853
6854         kfree(pipe_config);
6855
6856         return 0;
6857 }
6858
6859 /**
6860  * vlv_force_pll_off - forcibly disable just the PLL
6861  * @dev_priv: i915 private structure
6862  * @pipe: pipe PLL to disable
6863  *
6864  * Disable the PLL for @pipe. To be used in cases where we need
6865  * the PLL enabled even when @pipe is not going to be enabled.
6866  */
6867 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6868 {
6869         if (IS_CHERRYVIEW(dev_priv))
6870                 chv_disable_pll(dev_priv, pipe);
6871         else
6872                 vlv_disable_pll(dev_priv, pipe);
6873 }
6874
6875 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6876                               struct intel_crtc_state *crtc_state,
6877                               struct dpll *reduced_clock)
6878 {
6879         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6880         u32 dpll;
6881         struct dpll *clock = &crtc_state->dpll;
6882
6883         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6884
6885         dpll = DPLL_VGA_MODE_DIS;
6886
6887         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6888                 dpll |= DPLLB_MODE_LVDS;
6889         else
6890                 dpll |= DPLLB_MODE_DAC_SERIAL;
6891
6892         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6893             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6894                 dpll |= (crtc_state->pixel_multiplier - 1)
6895                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6896         }
6897
6898         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6899             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6900                 dpll |= DPLL_SDVO_HIGH_SPEED;
6901
6902         if (intel_crtc_has_dp_encoder(crtc_state))
6903                 dpll |= DPLL_SDVO_HIGH_SPEED;
6904
6905         /* compute bitmask from p1 value */
6906         if (IS_PINEVIEW(dev_priv))
6907                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6908         else {
6909                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6910                 if (IS_G4X(dev_priv) && reduced_clock)
6911                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6912         }
6913         switch (clock->p2) {
6914         case 5:
6915                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6916                 break;
6917         case 7:
6918                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6919                 break;
6920         case 10:
6921                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6922                 break;
6923         case 14:
6924                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6925                 break;
6926         }
6927         if (INTEL_GEN(dev_priv) >= 4)
6928                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6929
6930         if (crtc_state->sdvo_tv_clock)
6931                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6932         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6933                  intel_panel_use_ssc(dev_priv))
6934                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6935         else
6936                 dpll |= PLL_REF_INPUT_DREFCLK;
6937
6938         dpll |= DPLL_VCO_ENABLE;
6939         crtc_state->dpll_hw_state.dpll = dpll;
6940
6941         if (INTEL_GEN(dev_priv) >= 4) {
6942                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6943                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6944                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6945         }
6946 }
6947
6948 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6949                               struct intel_crtc_state *crtc_state,
6950                               struct dpll *reduced_clock)
6951 {
6952         struct drm_device *dev = crtc->base.dev;
6953         struct drm_i915_private *dev_priv = to_i915(dev);
6954         u32 dpll;
6955         struct dpll *clock = &crtc_state->dpll;
6956
6957         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6958
6959         dpll = DPLL_VGA_MODE_DIS;
6960
6961         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6962                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6963         } else {
6964                 if (clock->p1 == 2)
6965                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6966                 else
6967                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6968                 if (clock->p2 == 4)
6969                         dpll |= PLL_P2_DIVIDE_BY_4;
6970         }
6971
6972         if (!IS_I830(dev_priv) &&
6973             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6974                 dpll |= DPLL_DVO_2X_MODE;
6975
6976         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6977             intel_panel_use_ssc(dev_priv))
6978                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6979         else
6980                 dpll |= PLL_REF_INPUT_DREFCLK;
6981
6982         dpll |= DPLL_VCO_ENABLE;
6983         crtc_state->dpll_hw_state.dpll = dpll;
6984 }
6985
6986 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6987 {
6988         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6989         enum pipe pipe = intel_crtc->pipe;
6990         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6991         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6992         uint32_t crtc_vtotal, crtc_vblank_end;
6993         int vsyncshift = 0;
6994
6995         /* We need to be careful not to changed the adjusted mode, for otherwise
6996          * the hw state checker will get angry at the mismatch. */
6997         crtc_vtotal = adjusted_mode->crtc_vtotal;
6998         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6999
7000         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7001                 /* the chip adds 2 halflines automatically */
7002                 crtc_vtotal -= 1;
7003                 crtc_vblank_end -= 1;
7004
7005                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7006                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7007                 else
7008                         vsyncshift = adjusted_mode->crtc_hsync_start -
7009                                 adjusted_mode->crtc_htotal / 2;
7010                 if (vsyncshift < 0)
7011                         vsyncshift += adjusted_mode->crtc_htotal;
7012         }
7013
7014         if (INTEL_GEN(dev_priv) > 3)
7015                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7016
7017         I915_WRITE(HTOTAL(cpu_transcoder),
7018                    (adjusted_mode->crtc_hdisplay - 1) |
7019                    ((adjusted_mode->crtc_htotal - 1) << 16));
7020         I915_WRITE(HBLANK(cpu_transcoder),
7021                    (adjusted_mode->crtc_hblank_start - 1) |
7022                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7023         I915_WRITE(HSYNC(cpu_transcoder),
7024                    (adjusted_mode->crtc_hsync_start - 1) |
7025                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7026
7027         I915_WRITE(VTOTAL(cpu_transcoder),
7028                    (adjusted_mode->crtc_vdisplay - 1) |
7029                    ((crtc_vtotal - 1) << 16));
7030         I915_WRITE(VBLANK(cpu_transcoder),
7031                    (adjusted_mode->crtc_vblank_start - 1) |
7032                    ((crtc_vblank_end - 1) << 16));
7033         I915_WRITE(VSYNC(cpu_transcoder),
7034                    (adjusted_mode->crtc_vsync_start - 1) |
7035                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7036
7037         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7038          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7039          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7040          * bits. */
7041         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7042             (pipe == PIPE_B || pipe == PIPE_C))
7043                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7044
7045 }
7046
7047 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7048 {
7049         struct drm_device *dev = intel_crtc->base.dev;
7050         struct drm_i915_private *dev_priv = to_i915(dev);
7051         enum pipe pipe = intel_crtc->pipe;
7052
7053         /* pipesrc controls the size that is scaled from, which should
7054          * always be the user's requested size.
7055          */
7056         I915_WRITE(PIPESRC(pipe),
7057                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7058                    (intel_crtc->config->pipe_src_h - 1));
7059 }
7060
7061 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7062                                    struct intel_crtc_state *pipe_config)
7063 {
7064         struct drm_device *dev = crtc->base.dev;
7065         struct drm_i915_private *dev_priv = to_i915(dev);
7066         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7067         uint32_t tmp;
7068
7069         tmp = I915_READ(HTOTAL(cpu_transcoder));
7070         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7071         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7072         tmp = I915_READ(HBLANK(cpu_transcoder));
7073         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7074         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7075         tmp = I915_READ(HSYNC(cpu_transcoder));
7076         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7077         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7078
7079         tmp = I915_READ(VTOTAL(cpu_transcoder));
7080         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7081         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7082         tmp = I915_READ(VBLANK(cpu_transcoder));
7083         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7084         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7085         tmp = I915_READ(VSYNC(cpu_transcoder));
7086         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7087         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7088
7089         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7090                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7091                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7092                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7093         }
7094 }
7095
7096 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7097                                     struct intel_crtc_state *pipe_config)
7098 {
7099         struct drm_device *dev = crtc->base.dev;
7100         struct drm_i915_private *dev_priv = to_i915(dev);
7101         u32 tmp;
7102
7103         tmp = I915_READ(PIPESRC(crtc->pipe));
7104         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7105         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7106
7107         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7108         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7109 }
7110
7111 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7112                                  struct intel_crtc_state *pipe_config)
7113 {
7114         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7115         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7116         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7117         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7118
7119         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7120         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7121         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7122         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7123
7124         mode->flags = pipe_config->base.adjusted_mode.flags;
7125         mode->type = DRM_MODE_TYPE_DRIVER;
7126
7127         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7128
7129         mode->hsync = drm_mode_hsync(mode);
7130         mode->vrefresh = drm_mode_vrefresh(mode);
7131         drm_mode_set_name(mode);
7132 }
7133
7134 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7135 {
7136         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7137         uint32_t pipeconf;
7138
7139         pipeconf = 0;
7140
7141         /* we keep both pipes enabled on 830 */
7142         if (IS_I830(dev_priv))
7143                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7144
7145         if (intel_crtc->config->double_wide)
7146                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7147
7148         /* only g4x and later have fancy bpc/dither controls */
7149         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7150             IS_CHERRYVIEW(dev_priv)) {
7151                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7152                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7153                         pipeconf |= PIPECONF_DITHER_EN |
7154                                     PIPECONF_DITHER_TYPE_SP;
7155
7156                 switch (intel_crtc->config->pipe_bpp) {
7157                 case 18:
7158                         pipeconf |= PIPECONF_6BPC;
7159                         break;
7160                 case 24:
7161                         pipeconf |= PIPECONF_8BPC;
7162                         break;
7163                 case 30:
7164                         pipeconf |= PIPECONF_10BPC;
7165                         break;
7166                 default:
7167                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7168                         BUG();
7169                 }
7170         }
7171
7172         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7173                 if (INTEL_GEN(dev_priv) < 4 ||
7174                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7175                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7176                 else
7177                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7178         } else
7179                 pipeconf |= PIPECONF_PROGRESSIVE;
7180
7181         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7182              intel_crtc->config->limited_color_range)
7183                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7184
7185         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7186         POSTING_READ(PIPECONF(intel_crtc->pipe));
7187 }
7188
7189 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7190                                    struct intel_crtc_state *crtc_state)
7191 {
7192         struct drm_device *dev = crtc->base.dev;
7193         struct drm_i915_private *dev_priv = to_i915(dev);
7194         const struct intel_limit *limit;
7195         int refclk = 48000;
7196
7197         memset(&crtc_state->dpll_hw_state, 0,
7198                sizeof(crtc_state->dpll_hw_state));
7199
7200         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7201                 if (intel_panel_use_ssc(dev_priv)) {
7202                         refclk = dev_priv->vbt.lvds_ssc_freq;
7203                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7204                 }
7205
7206                 limit = &intel_limits_i8xx_lvds;
7207         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7208                 limit = &intel_limits_i8xx_dvo;
7209         } else {
7210                 limit = &intel_limits_i8xx_dac;
7211         }
7212
7213         if (!crtc_state->clock_set &&
7214             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7215                                  refclk, NULL, &crtc_state->dpll)) {
7216                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7217                 return -EINVAL;
7218         }
7219
7220         i8xx_compute_dpll(crtc, crtc_state, NULL);
7221
7222         return 0;
7223 }
7224
7225 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7226                                   struct intel_crtc_state *crtc_state)
7227 {
7228         struct drm_device *dev = crtc->base.dev;
7229         struct drm_i915_private *dev_priv = to_i915(dev);
7230         const struct intel_limit *limit;
7231         int refclk = 96000;
7232
7233         memset(&crtc_state->dpll_hw_state, 0,
7234                sizeof(crtc_state->dpll_hw_state));
7235
7236         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7237                 if (intel_panel_use_ssc(dev_priv)) {
7238                         refclk = dev_priv->vbt.lvds_ssc_freq;
7239                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7240                 }
7241
7242                 if (intel_is_dual_link_lvds(dev))
7243                         limit = &intel_limits_g4x_dual_channel_lvds;
7244                 else
7245                         limit = &intel_limits_g4x_single_channel_lvds;
7246         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7247                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7248                 limit = &intel_limits_g4x_hdmi;
7249         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7250                 limit = &intel_limits_g4x_sdvo;
7251         } else {
7252                 /* The option is for other outputs */
7253                 limit = &intel_limits_i9xx_sdvo;
7254         }
7255
7256         if (!crtc_state->clock_set &&
7257             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7258                                 refclk, NULL, &crtc_state->dpll)) {
7259                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7260                 return -EINVAL;
7261         }
7262
7263         i9xx_compute_dpll(crtc, crtc_state, NULL);
7264
7265         return 0;
7266 }
7267
7268 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7269                                   struct intel_crtc_state *crtc_state)
7270 {
7271         struct drm_device *dev = crtc->base.dev;
7272         struct drm_i915_private *dev_priv = to_i915(dev);
7273         const struct intel_limit *limit;
7274         int refclk = 96000;
7275
7276         memset(&crtc_state->dpll_hw_state, 0,
7277                sizeof(crtc_state->dpll_hw_state));
7278
7279         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7280                 if (intel_panel_use_ssc(dev_priv)) {
7281                         refclk = dev_priv->vbt.lvds_ssc_freq;
7282                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7283                 }
7284
7285                 limit = &intel_limits_pineview_lvds;
7286         } else {
7287                 limit = &intel_limits_pineview_sdvo;
7288         }
7289
7290         if (!crtc_state->clock_set &&
7291             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7292                                 refclk, NULL, &crtc_state->dpll)) {
7293                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7294                 return -EINVAL;
7295         }
7296
7297         i9xx_compute_dpll(crtc, crtc_state, NULL);
7298
7299         return 0;
7300 }
7301
7302 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7303                                    struct intel_crtc_state *crtc_state)
7304 {
7305         struct drm_device *dev = crtc->base.dev;
7306         struct drm_i915_private *dev_priv = to_i915(dev);
7307         const struct intel_limit *limit;
7308         int refclk = 96000;
7309
7310         memset(&crtc_state->dpll_hw_state, 0,
7311                sizeof(crtc_state->dpll_hw_state));
7312
7313         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7314                 if (intel_panel_use_ssc(dev_priv)) {
7315                         refclk = dev_priv->vbt.lvds_ssc_freq;
7316                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7317                 }
7318
7319                 limit = &intel_limits_i9xx_lvds;
7320         } else {
7321                 limit = &intel_limits_i9xx_sdvo;
7322         }
7323
7324         if (!crtc_state->clock_set &&
7325             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7326                                  refclk, NULL, &crtc_state->dpll)) {
7327                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7328                 return -EINVAL;
7329         }
7330
7331         i9xx_compute_dpll(crtc, crtc_state, NULL);
7332
7333         return 0;
7334 }
7335
7336 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7337                                   struct intel_crtc_state *crtc_state)
7338 {
7339         int refclk = 100000;
7340         const struct intel_limit *limit = &intel_limits_chv;
7341
7342         memset(&crtc_state->dpll_hw_state, 0,
7343                sizeof(crtc_state->dpll_hw_state));
7344
7345         if (!crtc_state->clock_set &&
7346             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7347                                 refclk, NULL, &crtc_state->dpll)) {
7348                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7349                 return -EINVAL;
7350         }
7351
7352         chv_compute_dpll(crtc, crtc_state);
7353
7354         return 0;
7355 }
7356
7357 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7358                                   struct intel_crtc_state *crtc_state)
7359 {
7360         int refclk = 100000;
7361         const struct intel_limit *limit = &intel_limits_vlv;
7362
7363         memset(&crtc_state->dpll_hw_state, 0,
7364                sizeof(crtc_state->dpll_hw_state));
7365
7366         if (!crtc_state->clock_set &&
7367             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7368                                 refclk, NULL, &crtc_state->dpll)) {
7369                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7370                 return -EINVAL;
7371         }
7372
7373         vlv_compute_dpll(crtc, crtc_state);
7374
7375         return 0;
7376 }
7377
7378 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7379                                  struct intel_crtc_state *pipe_config)
7380 {
7381         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7382         uint32_t tmp;
7383
7384         if (INTEL_GEN(dev_priv) <= 3 &&
7385             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7386                 return;
7387
7388         tmp = I915_READ(PFIT_CONTROL);
7389         if (!(tmp & PFIT_ENABLE))
7390                 return;
7391
7392         /* Check whether the pfit is attached to our pipe. */
7393         if (INTEL_GEN(dev_priv) < 4) {
7394                 if (crtc->pipe != PIPE_B)
7395                         return;
7396         } else {
7397                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7398                         return;
7399         }
7400
7401         pipe_config->gmch_pfit.control = tmp;
7402         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7403 }
7404
7405 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7406                                struct intel_crtc_state *pipe_config)
7407 {
7408         struct drm_device *dev = crtc->base.dev;
7409         struct drm_i915_private *dev_priv = to_i915(dev);
7410         int pipe = pipe_config->cpu_transcoder;
7411         struct dpll clock;
7412         u32 mdiv;
7413         int refclk = 100000;
7414
7415         /* In case of DSI, DPLL will not be used */
7416         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7417                 return;
7418
7419         mutex_lock(&dev_priv->sb_lock);
7420         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7421         mutex_unlock(&dev_priv->sb_lock);
7422
7423         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7424         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7425         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7426         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7427         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7428
7429         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7430 }
7431
7432 static void
7433 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7434                               struct intel_initial_plane_config *plane_config)
7435 {
7436         struct drm_device *dev = crtc->base.dev;
7437         struct drm_i915_private *dev_priv = to_i915(dev);
7438         u32 val, base, offset;
7439         int pipe = crtc->pipe, plane = crtc->plane;
7440         int fourcc, pixel_format;
7441         unsigned int aligned_height;
7442         struct drm_framebuffer *fb;
7443         struct intel_framebuffer *intel_fb;
7444
7445         val = I915_READ(DSPCNTR(plane));
7446         if (!(val & DISPLAY_PLANE_ENABLE))
7447                 return;
7448
7449         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7450         if (!intel_fb) {
7451                 DRM_DEBUG_KMS("failed to alloc fb\n");
7452                 return;
7453         }
7454
7455         fb = &intel_fb->base;
7456
7457         fb->dev = dev;
7458
7459         if (INTEL_GEN(dev_priv) >= 4) {
7460                 if (val & DISPPLANE_TILED) {
7461                         plane_config->tiling = I915_TILING_X;
7462                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7463                 }
7464         }
7465
7466         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7467         fourcc = i9xx_format_to_fourcc(pixel_format);
7468         fb->format = drm_format_info(fourcc);
7469
7470         if (INTEL_GEN(dev_priv) >= 4) {
7471                 if (plane_config->tiling)
7472                         offset = I915_READ(DSPTILEOFF(plane));
7473                 else
7474                         offset = I915_READ(DSPLINOFF(plane));
7475                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7476         } else {
7477                 base = I915_READ(DSPADDR(plane));
7478         }
7479         plane_config->base = base;
7480
7481         val = I915_READ(PIPESRC(pipe));
7482         fb->width = ((val >> 16) & 0xfff) + 1;
7483         fb->height = ((val >> 0) & 0xfff) + 1;
7484
7485         val = I915_READ(DSPSTRIDE(pipe));
7486         fb->pitches[0] = val & 0xffffffc0;
7487
7488         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7489
7490         plane_config->size = fb->pitches[0] * aligned_height;
7491
7492         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7493                       pipe_name(pipe), plane, fb->width, fb->height,
7494                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7495                       plane_config->size);
7496
7497         plane_config->fb = intel_fb;
7498 }
7499
7500 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7501                                struct intel_crtc_state *pipe_config)
7502 {
7503         struct drm_device *dev = crtc->base.dev;
7504         struct drm_i915_private *dev_priv = to_i915(dev);
7505         int pipe = pipe_config->cpu_transcoder;
7506         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7507         struct dpll clock;
7508         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7509         int refclk = 100000;
7510
7511         /* In case of DSI, DPLL will not be used */
7512         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7513                 return;
7514
7515         mutex_lock(&dev_priv->sb_lock);
7516         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7517         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7518         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7519         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7520         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7521         mutex_unlock(&dev_priv->sb_lock);
7522
7523         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7524         clock.m2 = (pll_dw0 & 0xff) << 22;
7525         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7526                 clock.m2 |= pll_dw2 & 0x3fffff;
7527         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7528         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7529         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7530
7531         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7532 }
7533
7534 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7535                                  struct intel_crtc_state *pipe_config)
7536 {
7537         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7538         enum intel_display_power_domain power_domain;
7539         uint32_t tmp;
7540         bool ret;
7541
7542         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7543         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7544                 return false;
7545
7546         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7547         pipe_config->shared_dpll = NULL;
7548
7549         ret = false;
7550
7551         tmp = I915_READ(PIPECONF(crtc->pipe));
7552         if (!(tmp & PIPECONF_ENABLE))
7553                 goto out;
7554
7555         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7556             IS_CHERRYVIEW(dev_priv)) {
7557                 switch (tmp & PIPECONF_BPC_MASK) {
7558                 case PIPECONF_6BPC:
7559                         pipe_config->pipe_bpp = 18;
7560                         break;
7561                 case PIPECONF_8BPC:
7562                         pipe_config->pipe_bpp = 24;
7563                         break;
7564                 case PIPECONF_10BPC:
7565                         pipe_config->pipe_bpp = 30;
7566                         break;
7567                 default:
7568                         break;
7569                 }
7570         }
7571
7572         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7573             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7574                 pipe_config->limited_color_range = true;
7575
7576         if (INTEL_GEN(dev_priv) < 4)
7577                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7578
7579         intel_get_pipe_timings(crtc, pipe_config);
7580         intel_get_pipe_src_size(crtc, pipe_config);
7581
7582         i9xx_get_pfit_config(crtc, pipe_config);
7583
7584         if (INTEL_GEN(dev_priv) >= 4) {
7585                 /* No way to read it out on pipes B and C */
7586                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7587                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7588                 else
7589                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7590                 pipe_config->pixel_multiplier =
7591                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7592                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7593                 pipe_config->dpll_hw_state.dpll_md = tmp;
7594         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7595                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7596                 tmp = I915_READ(DPLL(crtc->pipe));
7597                 pipe_config->pixel_multiplier =
7598                         ((tmp & SDVO_MULTIPLIER_MASK)
7599                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7600         } else {
7601                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7602                  * port and will be fixed up in the encoder->get_config
7603                  * function. */
7604                 pipe_config->pixel_multiplier = 1;
7605         }
7606         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7607         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7608                 /*
7609                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7610                  * on 830. Filter it out here so that we don't
7611                  * report errors due to that.
7612                  */
7613                 if (IS_I830(dev_priv))
7614                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7615
7616                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7617                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7618         } else {
7619                 /* Mask out read-only status bits. */
7620                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7621                                                      DPLL_PORTC_READY_MASK |
7622                                                      DPLL_PORTB_READY_MASK);
7623         }
7624
7625         if (IS_CHERRYVIEW(dev_priv))
7626                 chv_crtc_clock_get(crtc, pipe_config);
7627         else if (IS_VALLEYVIEW(dev_priv))
7628                 vlv_crtc_clock_get(crtc, pipe_config);
7629         else
7630                 i9xx_crtc_clock_get(crtc, pipe_config);
7631
7632         /*
7633          * Normally the dotclock is filled in by the encoder .get_config()
7634          * but in case the pipe is enabled w/o any ports we need a sane
7635          * default.
7636          */
7637         pipe_config->base.adjusted_mode.crtc_clock =
7638                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7639
7640         ret = true;
7641
7642 out:
7643         intel_display_power_put(dev_priv, power_domain);
7644
7645         return ret;
7646 }
7647
7648 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7649 {
7650         struct intel_encoder *encoder;
7651         int i;
7652         u32 val, final;
7653         bool has_lvds = false;
7654         bool has_cpu_edp = false;
7655         bool has_panel = false;
7656         bool has_ck505 = false;
7657         bool can_ssc = false;
7658         bool using_ssc_source = false;
7659
7660         /* We need to take the global config into account */
7661         for_each_intel_encoder(&dev_priv->drm, encoder) {
7662                 switch (encoder->type) {
7663                 case INTEL_OUTPUT_LVDS:
7664                         has_panel = true;
7665                         has_lvds = true;
7666                         break;
7667                 case INTEL_OUTPUT_EDP:
7668                         has_panel = true;
7669                         if (encoder->port == PORT_A)
7670                                 has_cpu_edp = true;
7671                         break;
7672                 default:
7673                         break;
7674                 }
7675         }
7676
7677         if (HAS_PCH_IBX(dev_priv)) {
7678                 has_ck505 = dev_priv->vbt.display_clock_mode;
7679                 can_ssc = has_ck505;
7680         } else {
7681                 has_ck505 = false;
7682                 can_ssc = true;
7683         }
7684
7685         /* Check if any DPLLs are using the SSC source */
7686         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7687                 u32 temp = I915_READ(PCH_DPLL(i));
7688
7689                 if (!(temp & DPLL_VCO_ENABLE))
7690                         continue;
7691
7692                 if ((temp & PLL_REF_INPUT_MASK) ==
7693                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7694                         using_ssc_source = true;
7695                         break;
7696                 }
7697         }
7698
7699         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7700                       has_panel, has_lvds, has_ck505, using_ssc_source);
7701
7702         /* Ironlake: try to setup display ref clock before DPLL
7703          * enabling. This is only under driver's control after
7704          * PCH B stepping, previous chipset stepping should be
7705          * ignoring this setting.
7706          */
7707         val = I915_READ(PCH_DREF_CONTROL);
7708
7709         /* As we must carefully and slowly disable/enable each source in turn,
7710          * compute the final state we want first and check if we need to
7711          * make any changes at all.
7712          */
7713         final = val;
7714         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7715         if (has_ck505)
7716                 final |= DREF_NONSPREAD_CK505_ENABLE;
7717         else
7718                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7719
7720         final &= ~DREF_SSC_SOURCE_MASK;
7721         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7722         final &= ~DREF_SSC1_ENABLE;
7723
7724         if (has_panel) {
7725                 final |= DREF_SSC_SOURCE_ENABLE;
7726
7727                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7728                         final |= DREF_SSC1_ENABLE;
7729
7730                 if (has_cpu_edp) {
7731                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7732                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7733                         else
7734                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7735                 } else
7736                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7737         } else if (using_ssc_source) {
7738                 final |= DREF_SSC_SOURCE_ENABLE;
7739                 final |= DREF_SSC1_ENABLE;
7740         }
7741
7742         if (final == val)
7743                 return;
7744
7745         /* Always enable nonspread source */
7746         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7747
7748         if (has_ck505)
7749                 val |= DREF_NONSPREAD_CK505_ENABLE;
7750         else
7751                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7752
7753         if (has_panel) {
7754                 val &= ~DREF_SSC_SOURCE_MASK;
7755                 val |= DREF_SSC_SOURCE_ENABLE;
7756
7757                 /* SSC must be turned on before enabling the CPU output  */
7758                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7759                         DRM_DEBUG_KMS("Using SSC on panel\n");
7760                         val |= DREF_SSC1_ENABLE;
7761                 } else
7762                         val &= ~DREF_SSC1_ENABLE;
7763
7764                 /* Get SSC going before enabling the outputs */
7765                 I915_WRITE(PCH_DREF_CONTROL, val);
7766                 POSTING_READ(PCH_DREF_CONTROL);
7767                 udelay(200);
7768
7769                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7770
7771                 /* Enable CPU source on CPU attached eDP */
7772                 if (has_cpu_edp) {
7773                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7774                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7775                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7776                         } else
7777                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7778                 } else
7779                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7780
7781                 I915_WRITE(PCH_DREF_CONTROL, val);
7782                 POSTING_READ(PCH_DREF_CONTROL);
7783                 udelay(200);
7784         } else {
7785                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7786
7787                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7788
7789                 /* Turn off CPU output */
7790                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7791
7792                 I915_WRITE(PCH_DREF_CONTROL, val);
7793                 POSTING_READ(PCH_DREF_CONTROL);
7794                 udelay(200);
7795
7796                 if (!using_ssc_source) {
7797                         DRM_DEBUG_KMS("Disabling SSC source\n");
7798
7799                         /* Turn off the SSC source */
7800                         val &= ~DREF_SSC_SOURCE_MASK;
7801                         val |= DREF_SSC_SOURCE_DISABLE;
7802
7803                         /* Turn off SSC1 */
7804                         val &= ~DREF_SSC1_ENABLE;
7805
7806                         I915_WRITE(PCH_DREF_CONTROL, val);
7807                         POSTING_READ(PCH_DREF_CONTROL);
7808                         udelay(200);
7809                 }
7810         }
7811
7812         BUG_ON(val != final);
7813 }
7814
7815 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7816 {
7817         uint32_t tmp;
7818
7819         tmp = I915_READ(SOUTH_CHICKEN2);
7820         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7821         I915_WRITE(SOUTH_CHICKEN2, tmp);
7822
7823         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7824                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7825                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7826
7827         tmp = I915_READ(SOUTH_CHICKEN2);
7828         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7829         I915_WRITE(SOUTH_CHICKEN2, tmp);
7830
7831         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7832                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7833                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7834 }
7835
7836 /* WaMPhyProgramming:hsw */
7837 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7838 {
7839         uint32_t tmp;
7840
7841         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7842         tmp &= ~(0xFF << 24);
7843         tmp |= (0x12 << 24);
7844         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7845
7846         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7847         tmp |= (1 << 11);
7848         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7849
7850         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7851         tmp |= (1 << 11);
7852         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7853
7854         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7855         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7856         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7857
7858         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7859         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7860         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7861
7862         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7863         tmp &= ~(7 << 13);
7864         tmp |= (5 << 13);
7865         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7866
7867         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7868         tmp &= ~(7 << 13);
7869         tmp |= (5 << 13);
7870         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7871
7872         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7873         tmp &= ~0xFF;
7874         tmp |= 0x1C;
7875         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7876
7877         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7878         tmp &= ~0xFF;
7879         tmp |= 0x1C;
7880         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7881
7882         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7883         tmp &= ~(0xFF << 16);
7884         tmp |= (0x1C << 16);
7885         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7886
7887         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7888         tmp &= ~(0xFF << 16);
7889         tmp |= (0x1C << 16);
7890         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7891
7892         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7893         tmp |= (1 << 27);
7894         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7895
7896         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7897         tmp |= (1 << 27);
7898         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7899
7900         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7901         tmp &= ~(0xF << 28);
7902         tmp |= (4 << 28);
7903         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7904
7905         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7906         tmp &= ~(0xF << 28);
7907         tmp |= (4 << 28);
7908         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7909 }
7910
7911 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7912  * Programming" based on the parameters passed:
7913  * - Sequence to enable CLKOUT_DP
7914  * - Sequence to enable CLKOUT_DP without spread
7915  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7916  */
7917 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7918                                  bool with_spread, bool with_fdi)
7919 {
7920         uint32_t reg, tmp;
7921
7922         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7923                 with_spread = true;
7924         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7925             with_fdi, "LP PCH doesn't have FDI\n"))
7926                 with_fdi = false;
7927
7928         mutex_lock(&dev_priv->sb_lock);
7929
7930         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7931         tmp &= ~SBI_SSCCTL_DISABLE;
7932         tmp |= SBI_SSCCTL_PATHALT;
7933         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7934
7935         udelay(24);
7936
7937         if (with_spread) {
7938                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7939                 tmp &= ~SBI_SSCCTL_PATHALT;
7940                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7941
7942                 if (with_fdi) {
7943                         lpt_reset_fdi_mphy(dev_priv);
7944                         lpt_program_fdi_mphy(dev_priv);
7945                 }
7946         }
7947
7948         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7949         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7950         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7951         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7952
7953         mutex_unlock(&dev_priv->sb_lock);
7954 }
7955
7956 /* Sequence to disable CLKOUT_DP */
7957 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7958 {
7959         uint32_t reg, tmp;
7960
7961         mutex_lock(&dev_priv->sb_lock);
7962
7963         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7964         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7965         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7966         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7967
7968         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7969         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7970                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7971                         tmp |= SBI_SSCCTL_PATHALT;
7972                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7973                         udelay(32);
7974                 }
7975                 tmp |= SBI_SSCCTL_DISABLE;
7976                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7977         }
7978
7979         mutex_unlock(&dev_priv->sb_lock);
7980 }
7981
7982 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7983
7984 static const uint16_t sscdivintphase[] = {
7985         [BEND_IDX( 50)] = 0x3B23,
7986         [BEND_IDX( 45)] = 0x3B23,
7987         [BEND_IDX( 40)] = 0x3C23,
7988         [BEND_IDX( 35)] = 0x3C23,
7989         [BEND_IDX( 30)] = 0x3D23,
7990         [BEND_IDX( 25)] = 0x3D23,
7991         [BEND_IDX( 20)] = 0x3E23,
7992         [BEND_IDX( 15)] = 0x3E23,
7993         [BEND_IDX( 10)] = 0x3F23,
7994         [BEND_IDX(  5)] = 0x3F23,
7995         [BEND_IDX(  0)] = 0x0025,
7996         [BEND_IDX( -5)] = 0x0025,
7997         [BEND_IDX(-10)] = 0x0125,
7998         [BEND_IDX(-15)] = 0x0125,
7999         [BEND_IDX(-20)] = 0x0225,
8000         [BEND_IDX(-25)] = 0x0225,
8001         [BEND_IDX(-30)] = 0x0325,
8002         [BEND_IDX(-35)] = 0x0325,
8003         [BEND_IDX(-40)] = 0x0425,
8004         [BEND_IDX(-45)] = 0x0425,
8005         [BEND_IDX(-50)] = 0x0525,
8006 };
8007
8008 /*
8009  * Bend CLKOUT_DP
8010  * steps -50 to 50 inclusive, in steps of 5
8011  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8012  * change in clock period = -(steps / 10) * 5.787 ps
8013  */
8014 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8015 {
8016         uint32_t tmp;
8017         int idx = BEND_IDX(steps);
8018
8019         if (WARN_ON(steps % 5 != 0))
8020                 return;
8021
8022         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8023                 return;
8024
8025         mutex_lock(&dev_priv->sb_lock);
8026
8027         if (steps % 10 != 0)
8028                 tmp = 0xAAAAAAAB;
8029         else
8030                 tmp = 0x00000000;
8031         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8032
8033         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8034         tmp &= 0xffff0000;
8035         tmp |= sscdivintphase[idx];
8036         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8037
8038         mutex_unlock(&dev_priv->sb_lock);
8039 }
8040
8041 #undef BEND_IDX
8042
8043 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8044 {
8045         struct intel_encoder *encoder;
8046         bool has_vga = false;
8047
8048         for_each_intel_encoder(&dev_priv->drm, encoder) {
8049                 switch (encoder->type) {
8050                 case INTEL_OUTPUT_ANALOG:
8051                         has_vga = true;
8052                         break;
8053                 default:
8054                         break;
8055                 }
8056         }
8057
8058         if (has_vga) {
8059                 lpt_bend_clkout_dp(dev_priv, 0);
8060                 lpt_enable_clkout_dp(dev_priv, true, true);
8061         } else {
8062                 lpt_disable_clkout_dp(dev_priv);
8063         }
8064 }
8065
8066 /*
8067  * Initialize reference clocks when the driver loads
8068  */
8069 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8070 {
8071         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8072                 ironlake_init_pch_refclk(dev_priv);
8073         else if (HAS_PCH_LPT(dev_priv))
8074                 lpt_init_pch_refclk(dev_priv);
8075 }
8076
8077 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8078 {
8079         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8081         int pipe = intel_crtc->pipe;
8082         uint32_t val;
8083
8084         val = 0;
8085
8086         switch (intel_crtc->config->pipe_bpp) {
8087         case 18:
8088                 val |= PIPECONF_6BPC;
8089                 break;
8090         case 24:
8091                 val |= PIPECONF_8BPC;
8092                 break;
8093         case 30:
8094                 val |= PIPECONF_10BPC;
8095                 break;
8096         case 36:
8097                 val |= PIPECONF_12BPC;
8098                 break;
8099         default:
8100                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8101                 BUG();
8102         }
8103
8104         if (intel_crtc->config->dither)
8105                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8106
8107         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8108                 val |= PIPECONF_INTERLACED_ILK;
8109         else
8110                 val |= PIPECONF_PROGRESSIVE;
8111
8112         if (intel_crtc->config->limited_color_range)
8113                 val |= PIPECONF_COLOR_RANGE_SELECT;
8114
8115         I915_WRITE(PIPECONF(pipe), val);
8116         POSTING_READ(PIPECONF(pipe));
8117 }
8118
8119 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8120 {
8121         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8123         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8124         u32 val = 0;
8125
8126         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8127                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8128
8129         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8130                 val |= PIPECONF_INTERLACED_ILK;
8131         else
8132                 val |= PIPECONF_PROGRESSIVE;
8133
8134         I915_WRITE(PIPECONF(cpu_transcoder), val);
8135         POSTING_READ(PIPECONF(cpu_transcoder));
8136 }
8137
8138 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8139 {
8140         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8141         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8142         struct intel_crtc_state *config = intel_crtc->config;
8143
8144         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8145                 u32 val = 0;
8146
8147                 switch (intel_crtc->config->pipe_bpp) {
8148                 case 18:
8149                         val |= PIPEMISC_DITHER_6_BPC;
8150                         break;
8151                 case 24:
8152                         val |= PIPEMISC_DITHER_8_BPC;
8153                         break;
8154                 case 30:
8155                         val |= PIPEMISC_DITHER_10_BPC;
8156                         break;
8157                 case 36:
8158                         val |= PIPEMISC_DITHER_12_BPC;
8159                         break;
8160                 default:
8161                         /* Case prevented by pipe_config_set_bpp. */
8162                         BUG();
8163                 }
8164
8165                 if (intel_crtc->config->dither)
8166                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8167
8168                 if (config->ycbcr420) {
8169                         val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8170                                 PIPEMISC_YUV420_ENABLE |
8171                                 PIPEMISC_YUV420_MODE_FULL_BLEND;
8172                 }
8173
8174                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8175         }
8176 }
8177
8178 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8179 {
8180         /*
8181          * Account for spread spectrum to avoid
8182          * oversubscribing the link. Max center spread
8183          * is 2.5%; use 5% for safety's sake.
8184          */
8185         u32 bps = target_clock * bpp * 21 / 20;
8186         return DIV_ROUND_UP(bps, link_bw * 8);
8187 }
8188
8189 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8190 {
8191         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8192 }
8193
8194 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8195                                   struct intel_crtc_state *crtc_state,
8196                                   struct dpll *reduced_clock)
8197 {
8198         struct drm_crtc *crtc = &intel_crtc->base;
8199         struct drm_device *dev = crtc->dev;
8200         struct drm_i915_private *dev_priv = to_i915(dev);
8201         u32 dpll, fp, fp2;
8202         int factor;
8203
8204         /* Enable autotuning of the PLL clock (if permissible) */
8205         factor = 21;
8206         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8207                 if ((intel_panel_use_ssc(dev_priv) &&
8208                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8209                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8210                         factor = 25;
8211         } else if (crtc_state->sdvo_tv_clock)
8212                 factor = 20;
8213
8214         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8215
8216         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8217                 fp |= FP_CB_TUNE;
8218
8219         if (reduced_clock) {
8220                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8221
8222                 if (reduced_clock->m < factor * reduced_clock->n)
8223                         fp2 |= FP_CB_TUNE;
8224         } else {
8225                 fp2 = fp;
8226         }
8227
8228         dpll = 0;
8229
8230         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8231                 dpll |= DPLLB_MODE_LVDS;
8232         else
8233                 dpll |= DPLLB_MODE_DAC_SERIAL;
8234
8235         dpll |= (crtc_state->pixel_multiplier - 1)
8236                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8237
8238         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8239             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8240                 dpll |= DPLL_SDVO_HIGH_SPEED;
8241
8242         if (intel_crtc_has_dp_encoder(crtc_state))
8243                 dpll |= DPLL_SDVO_HIGH_SPEED;
8244
8245         /*
8246          * The high speed IO clock is only really required for
8247          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8248          * possible to share the DPLL between CRT and HDMI. Enabling
8249          * the clock needlessly does no real harm, except use up a
8250          * bit of power potentially.
8251          *
8252          * We'll limit this to IVB with 3 pipes, since it has only two
8253          * DPLLs and so DPLL sharing is the only way to get three pipes
8254          * driving PCH ports at the same time. On SNB we could do this,
8255          * and potentially avoid enabling the second DPLL, but it's not
8256          * clear if it''s a win or loss power wise. No point in doing
8257          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8258          */
8259         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8260             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8261                 dpll |= DPLL_SDVO_HIGH_SPEED;
8262
8263         /* compute bitmask from p1 value */
8264         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8265         /* also FPA1 */
8266         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8267
8268         switch (crtc_state->dpll.p2) {
8269         case 5:
8270                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8271                 break;
8272         case 7:
8273                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8274                 break;
8275         case 10:
8276                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8277                 break;
8278         case 14:
8279                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8280                 break;
8281         }
8282
8283         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8284             intel_panel_use_ssc(dev_priv))
8285                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8286         else
8287                 dpll |= PLL_REF_INPUT_DREFCLK;
8288
8289         dpll |= DPLL_VCO_ENABLE;
8290
8291         crtc_state->dpll_hw_state.dpll = dpll;
8292         crtc_state->dpll_hw_state.fp0 = fp;
8293         crtc_state->dpll_hw_state.fp1 = fp2;
8294 }
8295
8296 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8297                                        struct intel_crtc_state *crtc_state)
8298 {
8299         struct drm_device *dev = crtc->base.dev;
8300         struct drm_i915_private *dev_priv = to_i915(dev);
8301         const struct intel_limit *limit;
8302         int refclk = 120000;
8303
8304         memset(&crtc_state->dpll_hw_state, 0,
8305                sizeof(crtc_state->dpll_hw_state));
8306
8307         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8308         if (!crtc_state->has_pch_encoder)
8309                 return 0;
8310
8311         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8312                 if (intel_panel_use_ssc(dev_priv)) {
8313                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8314                                       dev_priv->vbt.lvds_ssc_freq);
8315                         refclk = dev_priv->vbt.lvds_ssc_freq;
8316                 }
8317
8318                 if (intel_is_dual_link_lvds(dev)) {
8319                         if (refclk == 100000)
8320                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8321                         else
8322                                 limit = &intel_limits_ironlake_dual_lvds;
8323                 } else {
8324                         if (refclk == 100000)
8325                                 limit = &intel_limits_ironlake_single_lvds_100m;
8326                         else
8327                                 limit = &intel_limits_ironlake_single_lvds;
8328                 }
8329         } else {
8330                 limit = &intel_limits_ironlake_dac;
8331         }
8332
8333         if (!crtc_state->clock_set &&
8334             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8335                                 refclk, NULL, &crtc_state->dpll)) {
8336                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8337                 return -EINVAL;
8338         }
8339
8340         ironlake_compute_dpll(crtc, crtc_state, NULL);
8341
8342         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8343                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8344                                  pipe_name(crtc->pipe));
8345                 return -EINVAL;
8346         }
8347
8348         return 0;
8349 }
8350
8351 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8352                                          struct intel_link_m_n *m_n)
8353 {
8354         struct drm_device *dev = crtc->base.dev;
8355         struct drm_i915_private *dev_priv = to_i915(dev);
8356         enum pipe pipe = crtc->pipe;
8357
8358         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8359         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8360         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8361                 & ~TU_SIZE_MASK;
8362         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8363         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8364                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8365 }
8366
8367 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8368                                          enum transcoder transcoder,
8369                                          struct intel_link_m_n *m_n,
8370                                          struct intel_link_m_n *m2_n2)
8371 {
8372         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8373         enum pipe pipe = crtc->pipe;
8374
8375         if (INTEL_GEN(dev_priv) >= 5) {
8376                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8377                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8378                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8379                         & ~TU_SIZE_MASK;
8380                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8381                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8382                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8383                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8384                  * gen < 8) and if DRRS is supported (to make sure the
8385                  * registers are not unnecessarily read).
8386                  */
8387                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8388                         crtc->config->has_drrs) {
8389                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8390                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8391                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8392                                         & ~TU_SIZE_MASK;
8393                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8394                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8395                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8396                 }
8397         } else {
8398                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8399                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8400                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8401                         & ~TU_SIZE_MASK;
8402                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8403                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8404                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8405         }
8406 }
8407
8408 void intel_dp_get_m_n(struct intel_crtc *crtc,
8409                       struct intel_crtc_state *pipe_config)
8410 {
8411         if (pipe_config->has_pch_encoder)
8412                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8413         else
8414                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8415                                              &pipe_config->dp_m_n,
8416                                              &pipe_config->dp_m2_n2);
8417 }
8418
8419 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8420                                         struct intel_crtc_state *pipe_config)
8421 {
8422         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8423                                      &pipe_config->fdi_m_n, NULL);
8424 }
8425
8426 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8427                                     struct intel_crtc_state *pipe_config)
8428 {
8429         struct drm_device *dev = crtc->base.dev;
8430         struct drm_i915_private *dev_priv = to_i915(dev);
8431         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8432         uint32_t ps_ctrl = 0;
8433         int id = -1;
8434         int i;
8435
8436         /* find scaler attached to this pipe */
8437         for (i = 0; i < crtc->num_scalers; i++) {
8438                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8439                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8440                         id = i;
8441                         pipe_config->pch_pfit.enabled = true;
8442                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8443                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8444                         break;
8445                 }
8446         }
8447
8448         scaler_state->scaler_id = id;
8449         if (id >= 0) {
8450                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8451         } else {
8452                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8453         }
8454 }
8455
8456 static void
8457 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8458                                  struct intel_initial_plane_config *plane_config)
8459 {
8460         struct drm_device *dev = crtc->base.dev;
8461         struct drm_i915_private *dev_priv = to_i915(dev);
8462         u32 val, base, offset, stride_mult, tiling, alpha;
8463         int pipe = crtc->pipe;
8464         int fourcc, pixel_format;
8465         unsigned int aligned_height;
8466         struct drm_framebuffer *fb;
8467         struct intel_framebuffer *intel_fb;
8468
8469         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8470         if (!intel_fb) {
8471                 DRM_DEBUG_KMS("failed to alloc fb\n");
8472                 return;
8473         }
8474
8475         fb = &intel_fb->base;
8476
8477         fb->dev = dev;
8478
8479         val = I915_READ(PLANE_CTL(pipe, 0));
8480         if (!(val & PLANE_CTL_ENABLE))
8481                 goto error;
8482
8483         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8484
8485         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8486                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, 0));
8487                 alpha &= PLANE_COLOR_ALPHA_MASK;
8488         } else {
8489                 alpha = val & PLANE_CTL_ALPHA_MASK;
8490         }
8491
8492         fourcc = skl_format_to_fourcc(pixel_format,
8493                                       val & PLANE_CTL_ORDER_RGBX, alpha);
8494         fb->format = drm_format_info(fourcc);
8495
8496         tiling = val & PLANE_CTL_TILED_MASK;
8497         switch (tiling) {
8498         case PLANE_CTL_TILED_LINEAR:
8499                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8500                 break;
8501         case PLANE_CTL_TILED_X:
8502                 plane_config->tiling = I915_TILING_X;
8503                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8504                 break;
8505         case PLANE_CTL_TILED_Y:
8506                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8507                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8508                 else
8509                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
8510                 break;
8511         case PLANE_CTL_TILED_YF:
8512                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8513                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8514                 else
8515                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8516                 break;
8517         default:
8518                 MISSING_CASE(tiling);
8519                 goto error;
8520         }
8521
8522         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8523         plane_config->base = base;
8524
8525         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8526
8527         val = I915_READ(PLANE_SIZE(pipe, 0));
8528         fb->height = ((val >> 16) & 0xfff) + 1;
8529         fb->width = ((val >> 0) & 0x1fff) + 1;
8530
8531         val = I915_READ(PLANE_STRIDE(pipe, 0));
8532         stride_mult = intel_fb_stride_alignment(fb, 0);
8533         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8534
8535         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8536
8537         plane_config->size = fb->pitches[0] * aligned_height;
8538
8539         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8540                       pipe_name(pipe), fb->width, fb->height,
8541                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8542                       plane_config->size);
8543
8544         plane_config->fb = intel_fb;
8545         return;
8546
8547 error:
8548         kfree(intel_fb);
8549 }
8550
8551 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8552                                      struct intel_crtc_state *pipe_config)
8553 {
8554         struct drm_device *dev = crtc->base.dev;
8555         struct drm_i915_private *dev_priv = to_i915(dev);
8556         uint32_t tmp;
8557
8558         tmp = I915_READ(PF_CTL(crtc->pipe));
8559
8560         if (tmp & PF_ENABLE) {
8561                 pipe_config->pch_pfit.enabled = true;
8562                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8563                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8564
8565                 /* We currently do not free assignements of panel fitters on
8566                  * ivb/hsw (since we don't use the higher upscaling modes which
8567                  * differentiates them) so just WARN about this case for now. */
8568                 if (IS_GEN7(dev_priv)) {
8569                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8570                                 PF_PIPE_SEL_IVB(crtc->pipe));
8571                 }
8572         }
8573 }
8574
8575 static void
8576 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8577                                   struct intel_initial_plane_config *plane_config)
8578 {
8579         struct drm_device *dev = crtc->base.dev;
8580         struct drm_i915_private *dev_priv = to_i915(dev);
8581         u32 val, base, offset;
8582         int pipe = crtc->pipe;
8583         int fourcc, pixel_format;
8584         unsigned int aligned_height;
8585         struct drm_framebuffer *fb;
8586         struct intel_framebuffer *intel_fb;
8587
8588         val = I915_READ(DSPCNTR(pipe));
8589         if (!(val & DISPLAY_PLANE_ENABLE))
8590                 return;
8591
8592         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8593         if (!intel_fb) {
8594                 DRM_DEBUG_KMS("failed to alloc fb\n");
8595                 return;
8596         }
8597
8598         fb = &intel_fb->base;
8599
8600         fb->dev = dev;
8601
8602         if (INTEL_GEN(dev_priv) >= 4) {
8603                 if (val & DISPPLANE_TILED) {
8604                         plane_config->tiling = I915_TILING_X;
8605                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8606                 }
8607         }
8608
8609         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8610         fourcc = i9xx_format_to_fourcc(pixel_format);
8611         fb->format = drm_format_info(fourcc);
8612
8613         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8614         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8615                 offset = I915_READ(DSPOFFSET(pipe));
8616         } else {
8617                 if (plane_config->tiling)
8618                         offset = I915_READ(DSPTILEOFF(pipe));
8619                 else
8620                         offset = I915_READ(DSPLINOFF(pipe));
8621         }
8622         plane_config->base = base;
8623
8624         val = I915_READ(PIPESRC(pipe));
8625         fb->width = ((val >> 16) & 0xfff) + 1;
8626         fb->height = ((val >> 0) & 0xfff) + 1;
8627
8628         val = I915_READ(DSPSTRIDE(pipe));
8629         fb->pitches[0] = val & 0xffffffc0;
8630
8631         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8632
8633         plane_config->size = fb->pitches[0] * aligned_height;
8634
8635         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8636                       pipe_name(pipe), fb->width, fb->height,
8637                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8638                       plane_config->size);
8639
8640         plane_config->fb = intel_fb;
8641 }
8642
8643 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8644                                      struct intel_crtc_state *pipe_config)
8645 {
8646         struct drm_device *dev = crtc->base.dev;
8647         struct drm_i915_private *dev_priv = to_i915(dev);
8648         enum intel_display_power_domain power_domain;
8649         uint32_t tmp;
8650         bool ret;
8651
8652         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8653         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8654                 return false;
8655
8656         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8657         pipe_config->shared_dpll = NULL;
8658
8659         ret = false;
8660         tmp = I915_READ(PIPECONF(crtc->pipe));
8661         if (!(tmp & PIPECONF_ENABLE))
8662                 goto out;
8663
8664         switch (tmp & PIPECONF_BPC_MASK) {
8665         case PIPECONF_6BPC:
8666                 pipe_config->pipe_bpp = 18;
8667                 break;
8668         case PIPECONF_8BPC:
8669                 pipe_config->pipe_bpp = 24;
8670                 break;
8671         case PIPECONF_10BPC:
8672                 pipe_config->pipe_bpp = 30;
8673                 break;
8674         case PIPECONF_12BPC:
8675                 pipe_config->pipe_bpp = 36;
8676                 break;
8677         default:
8678                 break;
8679         }
8680
8681         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8682                 pipe_config->limited_color_range = true;
8683
8684         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8685                 struct intel_shared_dpll *pll;
8686                 enum intel_dpll_id pll_id;
8687
8688                 pipe_config->has_pch_encoder = true;
8689
8690                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8691                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8692                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8693
8694                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8695
8696                 if (HAS_PCH_IBX(dev_priv)) {
8697                         /*
8698                          * The pipe->pch transcoder and pch transcoder->pll
8699                          * mapping is fixed.
8700                          */
8701                         pll_id = (enum intel_dpll_id) crtc->pipe;
8702                 } else {
8703                         tmp = I915_READ(PCH_DPLL_SEL);
8704                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8705                                 pll_id = DPLL_ID_PCH_PLL_B;
8706                         else
8707                                 pll_id= DPLL_ID_PCH_PLL_A;
8708                 }
8709
8710                 pipe_config->shared_dpll =
8711                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8712                 pll = pipe_config->shared_dpll;
8713
8714                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8715                                                  &pipe_config->dpll_hw_state));
8716
8717                 tmp = pipe_config->dpll_hw_state.dpll;
8718                 pipe_config->pixel_multiplier =
8719                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8720                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8721
8722                 ironlake_pch_clock_get(crtc, pipe_config);
8723         } else {
8724                 pipe_config->pixel_multiplier = 1;
8725         }
8726
8727         intel_get_pipe_timings(crtc, pipe_config);
8728         intel_get_pipe_src_size(crtc, pipe_config);
8729
8730         ironlake_get_pfit_config(crtc, pipe_config);
8731
8732         ret = true;
8733
8734 out:
8735         intel_display_power_put(dev_priv, power_domain);
8736
8737         return ret;
8738 }
8739
8740 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8741 {
8742         struct drm_device *dev = &dev_priv->drm;
8743         struct intel_crtc *crtc;
8744
8745         for_each_intel_crtc(dev, crtc)
8746                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8747                      pipe_name(crtc->pipe));
8748
8749         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8750                         "Display power well on\n");
8751         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8752         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8753         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8754         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8755         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8756              "CPU PWM1 enabled\n");
8757         if (IS_HASWELL(dev_priv))
8758                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8759                      "CPU PWM2 enabled\n");
8760         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8761              "PCH PWM1 enabled\n");
8762         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8763              "Utility pin enabled\n");
8764         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8765
8766         /*
8767          * In theory we can still leave IRQs enabled, as long as only the HPD
8768          * interrupts remain enabled. We used to check for that, but since it's
8769          * gen-specific and since we only disable LCPLL after we fully disable
8770          * the interrupts, the check below should be enough.
8771          */
8772         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8773 }
8774
8775 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8776 {
8777         if (IS_HASWELL(dev_priv))
8778                 return I915_READ(D_COMP_HSW);
8779         else
8780                 return I915_READ(D_COMP_BDW);
8781 }
8782
8783 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8784 {
8785         if (IS_HASWELL(dev_priv)) {
8786                 mutex_lock(&dev_priv->pcu_lock);
8787                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8788                                             val))
8789                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8790                 mutex_unlock(&dev_priv->pcu_lock);
8791         } else {
8792                 I915_WRITE(D_COMP_BDW, val);
8793                 POSTING_READ(D_COMP_BDW);
8794         }
8795 }
8796
8797 /*
8798  * This function implements pieces of two sequences from BSpec:
8799  * - Sequence for display software to disable LCPLL
8800  * - Sequence for display software to allow package C8+
8801  * The steps implemented here are just the steps that actually touch the LCPLL
8802  * register. Callers should take care of disabling all the display engine
8803  * functions, doing the mode unset, fixing interrupts, etc.
8804  */
8805 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8806                               bool switch_to_fclk, bool allow_power_down)
8807 {
8808         uint32_t val;
8809
8810         assert_can_disable_lcpll(dev_priv);
8811
8812         val = I915_READ(LCPLL_CTL);
8813
8814         if (switch_to_fclk) {
8815                 val |= LCPLL_CD_SOURCE_FCLK;
8816                 I915_WRITE(LCPLL_CTL, val);
8817
8818                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8819                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8820                         DRM_ERROR("Switching to FCLK failed\n");
8821
8822                 val = I915_READ(LCPLL_CTL);
8823         }
8824
8825         val |= LCPLL_PLL_DISABLE;
8826         I915_WRITE(LCPLL_CTL, val);
8827         POSTING_READ(LCPLL_CTL);
8828
8829         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8830                 DRM_ERROR("LCPLL still locked\n");
8831
8832         val = hsw_read_dcomp(dev_priv);
8833         val |= D_COMP_COMP_DISABLE;
8834         hsw_write_dcomp(dev_priv, val);
8835         ndelay(100);
8836
8837         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8838                      1))
8839                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8840
8841         if (allow_power_down) {
8842                 val = I915_READ(LCPLL_CTL);
8843                 val |= LCPLL_POWER_DOWN_ALLOW;
8844                 I915_WRITE(LCPLL_CTL, val);
8845                 POSTING_READ(LCPLL_CTL);
8846         }
8847 }
8848
8849 /*
8850  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8851  * source.
8852  */
8853 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8854 {
8855         uint32_t val;
8856
8857         val = I915_READ(LCPLL_CTL);
8858
8859         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8860                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8861                 return;
8862
8863         /*
8864          * Make sure we're not on PC8 state before disabling PC8, otherwise
8865          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8866          */
8867         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8868
8869         if (val & LCPLL_POWER_DOWN_ALLOW) {
8870                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8871                 I915_WRITE(LCPLL_CTL, val);
8872                 POSTING_READ(LCPLL_CTL);
8873         }
8874
8875         val = hsw_read_dcomp(dev_priv);
8876         val |= D_COMP_COMP_FORCE;
8877         val &= ~D_COMP_COMP_DISABLE;
8878         hsw_write_dcomp(dev_priv, val);
8879
8880         val = I915_READ(LCPLL_CTL);
8881         val &= ~LCPLL_PLL_DISABLE;
8882         I915_WRITE(LCPLL_CTL, val);
8883
8884         if (intel_wait_for_register(dev_priv,
8885                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8886                                     5))
8887                 DRM_ERROR("LCPLL not locked yet\n");
8888
8889         if (val & LCPLL_CD_SOURCE_FCLK) {
8890                 val = I915_READ(LCPLL_CTL);
8891                 val &= ~LCPLL_CD_SOURCE_FCLK;
8892                 I915_WRITE(LCPLL_CTL, val);
8893
8894                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8895                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8896                         DRM_ERROR("Switching back to LCPLL failed\n");
8897         }
8898
8899         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8900
8901         intel_update_cdclk(dev_priv);
8902         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
8903 }
8904
8905 /*
8906  * Package states C8 and deeper are really deep PC states that can only be
8907  * reached when all the devices on the system allow it, so even if the graphics
8908  * device allows PC8+, it doesn't mean the system will actually get to these
8909  * states. Our driver only allows PC8+ when going into runtime PM.
8910  *
8911  * The requirements for PC8+ are that all the outputs are disabled, the power
8912  * well is disabled and most interrupts are disabled, and these are also
8913  * requirements for runtime PM. When these conditions are met, we manually do
8914  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8915  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8916  * hang the machine.
8917  *
8918  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8919  * the state of some registers, so when we come back from PC8+ we need to
8920  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8921  * need to take care of the registers kept by RC6. Notice that this happens even
8922  * if we don't put the device in PCI D3 state (which is what currently happens
8923  * because of the runtime PM support).
8924  *
8925  * For more, read "Display Sequences for Package C8" on the hardware
8926  * documentation.
8927  */
8928 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8929 {
8930         uint32_t val;
8931
8932         DRM_DEBUG_KMS("Enabling package C8+\n");
8933
8934         if (HAS_PCH_LPT_LP(dev_priv)) {
8935                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8936                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8937                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8938         }
8939
8940         lpt_disable_clkout_dp(dev_priv);
8941         hsw_disable_lcpll(dev_priv, true, true);
8942 }
8943
8944 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8945 {
8946         uint32_t val;
8947
8948         DRM_DEBUG_KMS("Disabling package C8+\n");
8949
8950         hsw_restore_lcpll(dev_priv);
8951         lpt_init_pch_refclk(dev_priv);
8952
8953         if (HAS_PCH_LPT_LP(dev_priv)) {
8954                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8955                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8956                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8957         }
8958 }
8959
8960 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8961                                       struct intel_crtc_state *crtc_state)
8962 {
8963         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8964                 struct intel_encoder *encoder =
8965                         intel_ddi_get_crtc_new_encoder(crtc_state);
8966
8967                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8968                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8969                                          pipe_name(crtc->pipe));
8970                         return -EINVAL;
8971                 }
8972         }
8973
8974         return 0;
8975 }
8976
8977 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8978                                    enum port port,
8979                                    struct intel_crtc_state *pipe_config)
8980 {
8981         enum intel_dpll_id id;
8982         u32 temp;
8983
8984         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8985         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
8986
8987         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8988                 return;
8989
8990         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8991 }
8992
8993 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8994                                 enum port port,
8995                                 struct intel_crtc_state *pipe_config)
8996 {
8997         enum intel_dpll_id id;
8998
8999         switch (port) {
9000         case PORT_A:
9001                 id = DPLL_ID_SKL_DPLL0;
9002                 break;
9003         case PORT_B:
9004                 id = DPLL_ID_SKL_DPLL1;
9005                 break;
9006         case PORT_C:
9007                 id = DPLL_ID_SKL_DPLL2;
9008                 break;
9009         default:
9010                 DRM_ERROR("Incorrect port type\n");
9011                 return;
9012         }
9013
9014         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9015 }
9016
9017 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9018                                 enum port port,
9019                                 struct intel_crtc_state *pipe_config)
9020 {
9021         enum intel_dpll_id id;
9022         u32 temp;
9023
9024         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9025         id = temp >> (port * 3 + 1);
9026
9027         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9028                 return;
9029
9030         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9031 }
9032
9033 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9034                                 enum port port,
9035                                 struct intel_crtc_state *pipe_config)
9036 {
9037         enum intel_dpll_id id;
9038         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9039
9040         switch (ddi_pll_sel) {
9041         case PORT_CLK_SEL_WRPLL1:
9042                 id = DPLL_ID_WRPLL1;
9043                 break;
9044         case PORT_CLK_SEL_WRPLL2:
9045                 id = DPLL_ID_WRPLL2;
9046                 break;
9047         case PORT_CLK_SEL_SPLL:
9048                 id = DPLL_ID_SPLL;
9049                 break;
9050         case PORT_CLK_SEL_LCPLL_810:
9051                 id = DPLL_ID_LCPLL_810;
9052                 break;
9053         case PORT_CLK_SEL_LCPLL_1350:
9054                 id = DPLL_ID_LCPLL_1350;
9055                 break;
9056         case PORT_CLK_SEL_LCPLL_2700:
9057                 id = DPLL_ID_LCPLL_2700;
9058                 break;
9059         default:
9060                 MISSING_CASE(ddi_pll_sel);
9061                 /* fall through */
9062         case PORT_CLK_SEL_NONE:
9063                 return;
9064         }
9065
9066         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9067 }
9068
9069 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9070                                      struct intel_crtc_state *pipe_config,
9071                                      u64 *power_domain_mask)
9072 {
9073         struct drm_device *dev = crtc->base.dev;
9074         struct drm_i915_private *dev_priv = to_i915(dev);
9075         enum intel_display_power_domain power_domain;
9076         u32 tmp;
9077
9078         /*
9079          * The pipe->transcoder mapping is fixed with the exception of the eDP
9080          * transcoder handled below.
9081          */
9082         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9083
9084         /*
9085          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9086          * consistency and less surprising code; it's in always on power).
9087          */
9088         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9089         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9090                 enum pipe trans_edp_pipe;
9091                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9092                 default:
9093                         WARN(1, "unknown pipe linked to edp transcoder\n");
9094                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9095                 case TRANS_DDI_EDP_INPUT_A_ON:
9096                         trans_edp_pipe = PIPE_A;
9097                         break;
9098                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9099                         trans_edp_pipe = PIPE_B;
9100                         break;
9101                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9102                         trans_edp_pipe = PIPE_C;
9103                         break;
9104                 }
9105
9106                 if (trans_edp_pipe == crtc->pipe)
9107                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9108         }
9109
9110         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9111         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9112                 return false;
9113         *power_domain_mask |= BIT_ULL(power_domain);
9114
9115         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9116
9117         return tmp & PIPECONF_ENABLE;
9118 }
9119
9120 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9121                                          struct intel_crtc_state *pipe_config,
9122                                          u64 *power_domain_mask)
9123 {
9124         struct drm_device *dev = crtc->base.dev;
9125         struct drm_i915_private *dev_priv = to_i915(dev);
9126         enum intel_display_power_domain power_domain;
9127         enum port port;
9128         enum transcoder cpu_transcoder;
9129         u32 tmp;
9130
9131         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9132                 if (port == PORT_A)
9133                         cpu_transcoder = TRANSCODER_DSI_A;
9134                 else
9135                         cpu_transcoder = TRANSCODER_DSI_C;
9136
9137                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9138                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9139                         continue;
9140                 *power_domain_mask |= BIT_ULL(power_domain);
9141
9142                 /*
9143                  * The PLL needs to be enabled with a valid divider
9144                  * configuration, otherwise accessing DSI registers will hang
9145                  * the machine. See BSpec North Display Engine
9146                  * registers/MIPI[BXT]. We can break out here early, since we
9147                  * need the same DSI PLL to be enabled for both DSI ports.
9148                  */
9149                 if (!intel_dsi_pll_is_enabled(dev_priv))
9150                         break;
9151
9152                 /* XXX: this works for video mode only */
9153                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9154                 if (!(tmp & DPI_ENABLE))
9155                         continue;
9156
9157                 tmp = I915_READ(MIPI_CTRL(port));
9158                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9159                         continue;
9160
9161                 pipe_config->cpu_transcoder = cpu_transcoder;
9162                 break;
9163         }
9164
9165         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9166 }
9167
9168 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9169                                        struct intel_crtc_state *pipe_config)
9170 {
9171         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9172         struct intel_shared_dpll *pll;
9173         enum port port;
9174         uint32_t tmp;
9175
9176         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9177
9178         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9179
9180         if (IS_CANNONLAKE(dev_priv))
9181                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9182         else if (IS_GEN9_BC(dev_priv))
9183                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9184         else if (IS_GEN9_LP(dev_priv))
9185                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9186         else
9187                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9188
9189         pll = pipe_config->shared_dpll;
9190         if (pll) {
9191                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9192                                                  &pipe_config->dpll_hw_state));
9193         }
9194
9195         /*
9196          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9197          * DDI E. So just check whether this pipe is wired to DDI E and whether
9198          * the PCH transcoder is on.
9199          */
9200         if (INTEL_GEN(dev_priv) < 9 &&
9201             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9202                 pipe_config->has_pch_encoder = true;
9203
9204                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9205                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9206                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9207
9208                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9209         }
9210 }
9211
9212 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9213                                     struct intel_crtc_state *pipe_config)
9214 {
9215         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9216         enum intel_display_power_domain power_domain;
9217         u64 power_domain_mask;
9218         bool active;
9219
9220         intel_crtc_init_scalers(crtc, pipe_config);
9221
9222         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9223         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9224                 return false;
9225         power_domain_mask = BIT_ULL(power_domain);
9226
9227         pipe_config->shared_dpll = NULL;
9228
9229         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9230
9231         if (IS_GEN9_LP(dev_priv) &&
9232             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9233                 WARN_ON(active);
9234                 active = true;
9235         }
9236
9237         if (!active)
9238                 goto out;
9239
9240         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9241                 haswell_get_ddi_port_state(crtc, pipe_config);
9242                 intel_get_pipe_timings(crtc, pipe_config);
9243         }
9244
9245         intel_get_pipe_src_size(crtc, pipe_config);
9246
9247         pipe_config->gamma_mode =
9248                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9249
9250         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9251                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9252                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9253
9254                 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9255                         bool blend_mode_420 = tmp &
9256                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
9257
9258                         pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9259                         if (pipe_config->ycbcr420 != clrspace_yuv ||
9260                             pipe_config->ycbcr420 != blend_mode_420)
9261                                 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9262                 } else if (clrspace_yuv) {
9263                         DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9264                 }
9265         }
9266
9267         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9268         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9269                 power_domain_mask |= BIT_ULL(power_domain);
9270                 if (INTEL_GEN(dev_priv) >= 9)
9271                         skylake_get_pfit_config(crtc, pipe_config);
9272                 else
9273                         ironlake_get_pfit_config(crtc, pipe_config);
9274         }
9275
9276         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9277             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9278                 pipe_config->pixel_multiplier =
9279                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9280         } else {
9281                 pipe_config->pixel_multiplier = 1;
9282         }
9283
9284 out:
9285         for_each_power_domain(power_domain, power_domain_mask)
9286                 intel_display_power_put(dev_priv, power_domain);
9287
9288         return active;
9289 }
9290
9291 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9292 {
9293         struct drm_i915_private *dev_priv =
9294                 to_i915(plane_state->base.plane->dev);
9295         const struct drm_framebuffer *fb = plane_state->base.fb;
9296         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9297         u32 base;
9298
9299         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9300                 base = obj->phys_handle->busaddr;
9301         else
9302                 base = intel_plane_ggtt_offset(plane_state);
9303
9304         base += plane_state->main.offset;
9305
9306         /* ILK+ do this automagically */
9307         if (HAS_GMCH_DISPLAY(dev_priv) &&
9308             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9309                 base += (plane_state->base.crtc_h *
9310                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9311
9312         return base;
9313 }
9314
9315 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9316 {
9317         int x = plane_state->base.crtc_x;
9318         int y = plane_state->base.crtc_y;
9319         u32 pos = 0;
9320
9321         if (x < 0) {
9322                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9323                 x = -x;
9324         }
9325         pos |= x << CURSOR_X_SHIFT;
9326
9327         if (y < 0) {
9328                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9329                 y = -y;
9330         }
9331         pos |= y << CURSOR_Y_SHIFT;
9332
9333         return pos;
9334 }
9335
9336 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9337 {
9338         const struct drm_mode_config *config =
9339                 &plane_state->base.plane->dev->mode_config;
9340         int width = plane_state->base.crtc_w;
9341         int height = plane_state->base.crtc_h;
9342
9343         return width > 0 && width <= config->cursor_width &&
9344                 height > 0 && height <= config->cursor_height;
9345 }
9346
9347 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9348                               struct intel_plane_state *plane_state)
9349 {
9350         const struct drm_framebuffer *fb = plane_state->base.fb;
9351         int src_x, src_y;
9352         u32 offset;
9353         int ret;
9354
9355         ret = drm_plane_helper_check_state(&plane_state->base,
9356                                            &plane_state->clip,
9357                                            DRM_PLANE_HELPER_NO_SCALING,
9358                                            DRM_PLANE_HELPER_NO_SCALING,
9359                                            true, true);
9360         if (ret)
9361                 return ret;
9362
9363         if (!fb)
9364                 return 0;
9365
9366         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9367                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9368                 return -EINVAL;
9369         }
9370
9371         src_x = plane_state->base.src_x >> 16;
9372         src_y = plane_state->base.src_y >> 16;
9373
9374         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9375         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9376
9377         if (src_x != 0 || src_y != 0) {
9378                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9379                 return -EINVAL;
9380         }
9381
9382         plane_state->main.offset = offset;
9383
9384         return 0;
9385 }
9386
9387 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9388                            const struct intel_plane_state *plane_state)
9389 {
9390         const struct drm_framebuffer *fb = plane_state->base.fb;
9391
9392         return CURSOR_ENABLE |
9393                 CURSOR_GAMMA_ENABLE |
9394                 CURSOR_FORMAT_ARGB |
9395                 CURSOR_STRIDE(fb->pitches[0]);
9396 }
9397
9398 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9399 {
9400         int width = plane_state->base.crtc_w;
9401
9402         /*
9403          * 845g/865g are only limited by the width of their cursors,
9404          * the height is arbitrary up to the precision of the register.
9405          */
9406         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9407 }
9408
9409 static int i845_check_cursor(struct intel_plane *plane,
9410                              struct intel_crtc_state *crtc_state,
9411                              struct intel_plane_state *plane_state)
9412 {
9413         const struct drm_framebuffer *fb = plane_state->base.fb;
9414         int ret;
9415
9416         ret = intel_check_cursor(crtc_state, plane_state);
9417         if (ret)
9418                 return ret;
9419
9420         /* if we want to turn off the cursor ignore width and height */
9421         if (!fb)
9422                 return 0;
9423
9424         /* Check for which cursor types we support */
9425         if (!i845_cursor_size_ok(plane_state)) {
9426                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9427                           plane_state->base.crtc_w,
9428                           plane_state->base.crtc_h);
9429                 return -EINVAL;
9430         }
9431
9432         switch (fb->pitches[0]) {
9433         case 256:
9434         case 512:
9435         case 1024:
9436         case 2048:
9437                 break;
9438         default:
9439                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9440                               fb->pitches[0]);
9441                 return -EINVAL;
9442         }
9443
9444         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9445
9446         return 0;
9447 }
9448
9449 static void i845_update_cursor(struct intel_plane *plane,
9450                                const struct intel_crtc_state *crtc_state,
9451                                const struct intel_plane_state *plane_state)
9452 {
9453         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9454         u32 cntl = 0, base = 0, pos = 0, size = 0;
9455         unsigned long irqflags;
9456
9457         if (plane_state && plane_state->base.visible) {
9458                 unsigned int width = plane_state->base.crtc_w;
9459                 unsigned int height = plane_state->base.crtc_h;
9460
9461                 cntl = plane_state->ctl;
9462                 size = (height << 12) | width;
9463
9464                 base = intel_cursor_base(plane_state);
9465                 pos = intel_cursor_position(plane_state);
9466         }
9467
9468         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9469
9470         /* On these chipsets we can only modify the base/size/stride
9471          * whilst the cursor is disabled.
9472          */
9473         if (plane->cursor.base != base ||
9474             plane->cursor.size != size ||
9475             plane->cursor.cntl != cntl) {
9476                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9477                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9478                 I915_WRITE_FW(CURSIZE, size);
9479                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9480                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9481
9482                 plane->cursor.base = base;
9483                 plane->cursor.size = size;
9484                 plane->cursor.cntl = cntl;
9485         } else {
9486                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9487         }
9488
9489         POSTING_READ_FW(CURCNTR(PIPE_A));
9490
9491         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9492 }
9493
9494 static void i845_disable_cursor(struct intel_plane *plane,
9495                                 struct intel_crtc *crtc)
9496 {
9497         i845_update_cursor(plane, NULL, NULL);
9498 }
9499
9500 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9501                            const struct intel_plane_state *plane_state)
9502 {
9503         struct drm_i915_private *dev_priv =
9504                 to_i915(plane_state->base.plane->dev);
9505         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9506         u32 cntl;
9507
9508         cntl = MCURSOR_GAMMA_ENABLE;
9509
9510         if (HAS_DDI(dev_priv))
9511                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9512
9513         cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9514
9515         switch (plane_state->base.crtc_w) {
9516         case 64:
9517                 cntl |= CURSOR_MODE_64_ARGB_AX;
9518                 break;
9519         case 128:
9520                 cntl |= CURSOR_MODE_128_ARGB_AX;
9521                 break;
9522         case 256:
9523                 cntl |= CURSOR_MODE_256_ARGB_AX;
9524                 break;
9525         default:
9526                 MISSING_CASE(plane_state->base.crtc_w);
9527                 return 0;
9528         }
9529
9530         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9531                 cntl |= CURSOR_ROTATE_180;
9532
9533         return cntl;
9534 }
9535
9536 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9537 {
9538         struct drm_i915_private *dev_priv =
9539                 to_i915(plane_state->base.plane->dev);
9540         int width = plane_state->base.crtc_w;
9541         int height = plane_state->base.crtc_h;
9542
9543         if (!intel_cursor_size_ok(plane_state))
9544                 return false;
9545
9546         /* Cursor width is limited to a few power-of-two sizes */
9547         switch (width) {
9548         case 256:
9549         case 128:
9550         case 64:
9551                 break;
9552         default:
9553                 return false;
9554         }
9555
9556         /*
9557          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9558          * height from 8 lines up to the cursor width, when the
9559          * cursor is not rotated. Everything else requires square
9560          * cursors.
9561          */
9562         if (HAS_CUR_FBC(dev_priv) &&
9563             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9564                 if (height < 8 || height > width)
9565                         return false;
9566         } else {
9567                 if (height != width)
9568                         return false;
9569         }
9570
9571         return true;
9572 }
9573
9574 static int i9xx_check_cursor(struct intel_plane *plane,
9575                              struct intel_crtc_state *crtc_state,
9576                              struct intel_plane_state *plane_state)
9577 {
9578         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9579         const struct drm_framebuffer *fb = plane_state->base.fb;
9580         enum pipe pipe = plane->pipe;
9581         int ret;
9582
9583         ret = intel_check_cursor(crtc_state, plane_state);
9584         if (ret)
9585                 return ret;
9586
9587         /* if we want to turn off the cursor ignore width and height */
9588         if (!fb)
9589                 return 0;
9590
9591         /* Check for which cursor types we support */
9592         if (!i9xx_cursor_size_ok(plane_state)) {
9593                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9594                           plane_state->base.crtc_w,
9595                           plane_state->base.crtc_h);
9596                 return -EINVAL;
9597         }
9598
9599         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9600                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9601                               fb->pitches[0], plane_state->base.crtc_w);
9602                 return -EINVAL;
9603         }
9604
9605         /*
9606          * There's something wrong with the cursor on CHV pipe C.
9607          * If it straddles the left edge of the screen then
9608          * moving it away from the edge or disabling it often
9609          * results in a pipe underrun, and often that can lead to
9610          * dead pipe (constant underrun reported, and it scans
9611          * out just a solid color). To recover from that, the
9612          * display power well must be turned off and on again.
9613          * Refuse the put the cursor into that compromised position.
9614          */
9615         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9616             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9617                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9618                 return -EINVAL;
9619         }
9620
9621         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9622
9623         return 0;
9624 }
9625
9626 static void i9xx_update_cursor(struct intel_plane *plane,
9627                                const struct intel_crtc_state *crtc_state,
9628                                const struct intel_plane_state *plane_state)
9629 {
9630         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9631         enum pipe pipe = plane->pipe;
9632         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9633         unsigned long irqflags;
9634
9635         if (plane_state && plane_state->base.visible) {
9636                 cntl = plane_state->ctl;
9637
9638                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9639                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9640
9641                 base = intel_cursor_base(plane_state);
9642                 pos = intel_cursor_position(plane_state);
9643         }
9644
9645         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9646
9647         /*
9648          * On some platforms writing CURCNTR first will also
9649          * cause CURPOS to be armed by the CURBASE write.
9650          * Without the CURCNTR write the CURPOS write would
9651          * arm itself. Thus we always start the full update
9652          * with a CURCNTR write.
9653          *
9654          * On other platforms CURPOS always requires the
9655          * CURBASE write to arm the update. Additonally
9656          * a write to any of the cursor register will cancel
9657          * an already armed cursor update. Thus leaving out
9658          * the CURBASE write after CURPOS could lead to a
9659          * cursor that doesn't appear to move, or even change
9660          * shape. Thus we always write CURBASE.
9661          *
9662          * CURCNTR and CUR_FBC_CTL are always
9663          * armed by the CURBASE write only.
9664          */
9665         if (plane->cursor.base != base ||
9666             plane->cursor.size != fbc_ctl ||
9667             plane->cursor.cntl != cntl) {
9668                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9669                 if (HAS_CUR_FBC(dev_priv))
9670                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9671                 I915_WRITE_FW(CURPOS(pipe), pos);
9672                 I915_WRITE_FW(CURBASE(pipe), base);
9673
9674                 plane->cursor.base = base;
9675                 plane->cursor.size = fbc_ctl;
9676                 plane->cursor.cntl = cntl;
9677         } else {
9678                 I915_WRITE_FW(CURPOS(pipe), pos);
9679                 I915_WRITE_FW(CURBASE(pipe), base);
9680         }
9681
9682         POSTING_READ_FW(CURBASE(pipe));
9683
9684         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9685 }
9686
9687 static void i9xx_disable_cursor(struct intel_plane *plane,
9688                                 struct intel_crtc *crtc)
9689 {
9690         i9xx_update_cursor(plane, NULL, NULL);
9691 }
9692
9693
9694 /* VESA 640x480x72Hz mode to set on the pipe */
9695 static const struct drm_display_mode load_detect_mode = {
9696         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9697                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9698 };
9699
9700 struct drm_framebuffer *
9701 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9702                          struct drm_mode_fb_cmd2 *mode_cmd)
9703 {
9704         struct intel_framebuffer *intel_fb;
9705         int ret;
9706
9707         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9708         if (!intel_fb)
9709                 return ERR_PTR(-ENOMEM);
9710
9711         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9712         if (ret)
9713                 goto err;
9714
9715         return &intel_fb->base;
9716
9717 err:
9718         kfree(intel_fb);
9719         return ERR_PTR(ret);
9720 }
9721
9722 static u32
9723 intel_framebuffer_pitch_for_width(int width, int bpp)
9724 {
9725         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9726         return ALIGN(pitch, 64);
9727 }
9728
9729 static u32
9730 intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9731 {
9732         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9733         return PAGE_ALIGN(pitch * mode->vdisplay);
9734 }
9735
9736 static struct drm_framebuffer *
9737 intel_framebuffer_create_for_mode(struct drm_device *dev,
9738                                   const struct drm_display_mode *mode,
9739                                   int depth, int bpp)
9740 {
9741         struct drm_framebuffer *fb;
9742         struct drm_i915_gem_object *obj;
9743         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9744
9745         obj = i915_gem_object_create(to_i915(dev),
9746                                     intel_framebuffer_size_for_mode(mode, bpp));
9747         if (IS_ERR(obj))
9748                 return ERR_CAST(obj);
9749
9750         mode_cmd.width = mode->hdisplay;
9751         mode_cmd.height = mode->vdisplay;
9752         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9753                                                                 bpp);
9754         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9755
9756         fb = intel_framebuffer_create(obj, &mode_cmd);
9757         if (IS_ERR(fb))
9758                 i915_gem_object_put(obj);
9759
9760         return fb;
9761 }
9762
9763 static struct drm_framebuffer *
9764 mode_fits_in_fbdev(struct drm_device *dev,
9765                    const struct drm_display_mode *mode)
9766 {
9767 #ifdef CONFIG_DRM_FBDEV_EMULATION
9768         struct drm_i915_private *dev_priv = to_i915(dev);
9769         struct drm_i915_gem_object *obj;
9770         struct drm_framebuffer *fb;
9771
9772         if (!dev_priv->fbdev)
9773                 return NULL;
9774
9775         if (!dev_priv->fbdev->fb)
9776                 return NULL;
9777
9778         obj = dev_priv->fbdev->fb->obj;
9779         BUG_ON(!obj);
9780
9781         fb = &dev_priv->fbdev->fb->base;
9782         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9783                                                                fb->format->cpp[0] * 8))
9784                 return NULL;
9785
9786         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9787                 return NULL;
9788
9789         drm_framebuffer_get(fb);
9790         return fb;
9791 #else
9792         return NULL;
9793 #endif
9794 }
9795
9796 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9797                                            struct drm_crtc *crtc,
9798                                            const struct drm_display_mode *mode,
9799                                            struct drm_framebuffer *fb,
9800                                            int x, int y)
9801 {
9802         struct drm_plane_state *plane_state;
9803         int hdisplay, vdisplay;
9804         int ret;
9805
9806         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9807         if (IS_ERR(plane_state))
9808                 return PTR_ERR(plane_state);
9809
9810         if (mode)
9811                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9812         else
9813                 hdisplay = vdisplay = 0;
9814
9815         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9816         if (ret)
9817                 return ret;
9818         drm_atomic_set_fb_for_plane(plane_state, fb);
9819         plane_state->crtc_x = 0;
9820         plane_state->crtc_y = 0;
9821         plane_state->crtc_w = hdisplay;
9822         plane_state->crtc_h = vdisplay;
9823         plane_state->src_x = x << 16;
9824         plane_state->src_y = y << 16;
9825         plane_state->src_w = hdisplay << 16;
9826         plane_state->src_h = vdisplay << 16;
9827
9828         return 0;
9829 }
9830
9831 int intel_get_load_detect_pipe(struct drm_connector *connector,
9832                                const struct drm_display_mode *mode,
9833                                struct intel_load_detect_pipe *old,
9834                                struct drm_modeset_acquire_ctx *ctx)
9835 {
9836         struct intel_crtc *intel_crtc;
9837         struct intel_encoder *intel_encoder =
9838                 intel_attached_encoder(connector);
9839         struct drm_crtc *possible_crtc;
9840         struct drm_encoder *encoder = &intel_encoder->base;
9841         struct drm_crtc *crtc = NULL;
9842         struct drm_device *dev = encoder->dev;
9843         struct drm_i915_private *dev_priv = to_i915(dev);
9844         struct drm_framebuffer *fb;
9845         struct drm_mode_config *config = &dev->mode_config;
9846         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9847         struct drm_connector_state *connector_state;
9848         struct intel_crtc_state *crtc_state;
9849         int ret, i = -1;
9850
9851         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9852                       connector->base.id, connector->name,
9853                       encoder->base.id, encoder->name);
9854
9855         old->restore_state = NULL;
9856
9857         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9858
9859         /*
9860          * Algorithm gets a little messy:
9861          *
9862          *   - if the connector already has an assigned crtc, use it (but make
9863          *     sure it's on first)
9864          *
9865          *   - try to find the first unused crtc that can drive this connector,
9866          *     and use that if we find one
9867          */
9868
9869         /* See if we already have a CRTC for this connector */
9870         if (connector->state->crtc) {
9871                 crtc = connector->state->crtc;
9872
9873                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9874                 if (ret)
9875                         goto fail;
9876
9877                 /* Make sure the crtc and connector are running */
9878                 goto found;
9879         }
9880
9881         /* Find an unused one (if possible) */
9882         for_each_crtc(dev, possible_crtc) {
9883                 i++;
9884                 if (!(encoder->possible_crtcs & (1 << i)))
9885                         continue;
9886
9887                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9888                 if (ret)
9889                         goto fail;
9890
9891                 if (possible_crtc->state->enable) {
9892                         drm_modeset_unlock(&possible_crtc->mutex);
9893                         continue;
9894                 }
9895
9896                 crtc = possible_crtc;
9897                 break;
9898         }
9899
9900         /*
9901          * If we didn't find an unused CRTC, don't use any.
9902          */
9903         if (!crtc) {
9904                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9905                 ret = -ENODEV;
9906                 goto fail;
9907         }
9908
9909 found:
9910         intel_crtc = to_intel_crtc(crtc);
9911
9912         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9913         if (ret)
9914                 goto fail;
9915
9916         state = drm_atomic_state_alloc(dev);
9917         restore_state = drm_atomic_state_alloc(dev);
9918         if (!state || !restore_state) {
9919                 ret = -ENOMEM;
9920                 goto fail;
9921         }
9922
9923         state->acquire_ctx = ctx;
9924         restore_state->acquire_ctx = ctx;
9925
9926         connector_state = drm_atomic_get_connector_state(state, connector);
9927         if (IS_ERR(connector_state)) {
9928                 ret = PTR_ERR(connector_state);
9929                 goto fail;
9930         }
9931
9932         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9933         if (ret)
9934                 goto fail;
9935
9936         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9937         if (IS_ERR(crtc_state)) {
9938                 ret = PTR_ERR(crtc_state);
9939                 goto fail;
9940         }
9941
9942         crtc_state->base.active = crtc_state->base.enable = true;
9943
9944         if (!mode)
9945                 mode = &load_detect_mode;
9946
9947         /* We need a framebuffer large enough to accommodate all accesses
9948          * that the plane may generate whilst we perform load detection.
9949          * We can not rely on the fbcon either being present (we get called
9950          * during its initialisation to detect all boot displays, or it may
9951          * not even exist) or that it is large enough to satisfy the
9952          * requested mode.
9953          */
9954         fb = mode_fits_in_fbdev(dev, mode);
9955         if (fb == NULL) {
9956                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9957                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9958         } else
9959                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9960         if (IS_ERR(fb)) {
9961                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9962                 ret = PTR_ERR(fb);
9963                 goto fail;
9964         }
9965
9966         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9967         if (ret)
9968                 goto fail;
9969
9970         drm_framebuffer_put(fb);
9971
9972         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9973         if (ret)
9974                 goto fail;
9975
9976         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9977         if (!ret)
9978                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9979         if (!ret)
9980                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9981         if (ret) {
9982                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9983                 goto fail;
9984         }
9985
9986         ret = drm_atomic_commit(state);
9987         if (ret) {
9988                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9989                 goto fail;
9990         }
9991
9992         old->restore_state = restore_state;
9993         drm_atomic_state_put(state);
9994
9995         /* let the connector get through one full cycle before testing */
9996         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9997         return true;
9998
9999 fail:
10000         if (state) {
10001                 drm_atomic_state_put(state);
10002                 state = NULL;
10003         }
10004         if (restore_state) {
10005                 drm_atomic_state_put(restore_state);
10006                 restore_state = NULL;
10007         }
10008
10009         if (ret == -EDEADLK)
10010                 return ret;
10011
10012         return false;
10013 }
10014
10015 void intel_release_load_detect_pipe(struct drm_connector *connector,
10016                                     struct intel_load_detect_pipe *old,
10017                                     struct drm_modeset_acquire_ctx *ctx)
10018 {
10019         struct intel_encoder *intel_encoder =
10020                 intel_attached_encoder(connector);
10021         struct drm_encoder *encoder = &intel_encoder->base;
10022         struct drm_atomic_state *state = old->restore_state;
10023         int ret;
10024
10025         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10026                       connector->base.id, connector->name,
10027                       encoder->base.id, encoder->name);
10028
10029         if (!state)
10030                 return;
10031
10032         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10033         if (ret)
10034                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10035         drm_atomic_state_put(state);
10036 }
10037
10038 static int i9xx_pll_refclk(struct drm_device *dev,
10039                            const struct intel_crtc_state *pipe_config)
10040 {
10041         struct drm_i915_private *dev_priv = to_i915(dev);
10042         u32 dpll = pipe_config->dpll_hw_state.dpll;
10043
10044         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10045                 return dev_priv->vbt.lvds_ssc_freq;
10046         else if (HAS_PCH_SPLIT(dev_priv))
10047                 return 120000;
10048         else if (!IS_GEN2(dev_priv))
10049                 return 96000;
10050         else
10051                 return 48000;
10052 }
10053
10054 /* Returns the clock of the currently programmed mode of the given pipe. */
10055 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10056                                 struct intel_crtc_state *pipe_config)
10057 {
10058         struct drm_device *dev = crtc->base.dev;
10059         struct drm_i915_private *dev_priv = to_i915(dev);
10060         int pipe = pipe_config->cpu_transcoder;
10061         u32 dpll = pipe_config->dpll_hw_state.dpll;
10062         u32 fp;
10063         struct dpll clock;
10064         int port_clock;
10065         int refclk = i9xx_pll_refclk(dev, pipe_config);
10066
10067         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10068                 fp = pipe_config->dpll_hw_state.fp0;
10069         else
10070                 fp = pipe_config->dpll_hw_state.fp1;
10071
10072         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10073         if (IS_PINEVIEW(dev_priv)) {
10074                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10075                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10076         } else {
10077                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10078                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10079         }
10080
10081         if (!IS_GEN2(dev_priv)) {
10082                 if (IS_PINEVIEW(dev_priv))
10083                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10084                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10085                 else
10086                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10087                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10088
10089                 switch (dpll & DPLL_MODE_MASK) {
10090                 case DPLLB_MODE_DAC_SERIAL:
10091                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10092                                 5 : 10;
10093                         break;
10094                 case DPLLB_MODE_LVDS:
10095                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10096                                 7 : 14;
10097                         break;
10098                 default:
10099                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10100                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10101                         return;
10102                 }
10103
10104                 if (IS_PINEVIEW(dev_priv))
10105                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10106                 else
10107                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10108         } else {
10109                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10110                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10111
10112                 if (is_lvds) {
10113                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10114                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10115
10116                         if (lvds & LVDS_CLKB_POWER_UP)
10117                                 clock.p2 = 7;
10118                         else
10119                                 clock.p2 = 14;
10120                 } else {
10121                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10122                                 clock.p1 = 2;
10123                         else {
10124                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10125                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10126                         }
10127                         if (dpll & PLL_P2_DIVIDE_BY_4)
10128                                 clock.p2 = 4;
10129                         else
10130                                 clock.p2 = 2;
10131                 }
10132
10133                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10134         }
10135
10136         /*
10137          * This value includes pixel_multiplier. We will use
10138          * port_clock to compute adjusted_mode.crtc_clock in the
10139          * encoder's get_config() function.
10140          */
10141         pipe_config->port_clock = port_clock;
10142 }
10143
10144 int intel_dotclock_calculate(int link_freq,
10145                              const struct intel_link_m_n *m_n)
10146 {
10147         /*
10148          * The calculation for the data clock is:
10149          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10150          * But we want to avoid losing precison if possible, so:
10151          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10152          *
10153          * and the link clock is simpler:
10154          * link_clock = (m * link_clock) / n
10155          */
10156
10157         if (!m_n->link_n)
10158                 return 0;
10159
10160         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10161 }
10162
10163 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10164                                    struct intel_crtc_state *pipe_config)
10165 {
10166         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10167
10168         /* read out port_clock from the DPLL */
10169         i9xx_crtc_clock_get(crtc, pipe_config);
10170
10171         /*
10172          * In case there is an active pipe without active ports,
10173          * we may need some idea for the dotclock anyway.
10174          * Calculate one based on the FDI configuration.
10175          */
10176         pipe_config->base.adjusted_mode.crtc_clock =
10177                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10178                                          &pipe_config->fdi_m_n);
10179 }
10180
10181 /* Returns the currently programmed mode of the given encoder. */
10182 struct drm_display_mode *
10183 intel_encoder_current_mode(struct intel_encoder *encoder)
10184 {
10185         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10186         struct intel_crtc_state *crtc_state;
10187         struct drm_display_mode *mode;
10188         struct intel_crtc *crtc;
10189         enum pipe pipe;
10190
10191         if (!encoder->get_hw_state(encoder, &pipe))
10192                 return NULL;
10193
10194         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10195
10196         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10197         if (!mode)
10198                 return NULL;
10199
10200         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10201         if (!crtc_state) {
10202                 kfree(mode);
10203                 return NULL;
10204         }
10205
10206         crtc_state->base.crtc = &crtc->base;
10207
10208         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10209                 kfree(crtc_state);
10210                 kfree(mode);
10211                 return NULL;
10212         }
10213
10214         encoder->get_config(encoder, crtc_state);
10215
10216         intel_mode_from_pipe_config(mode, crtc_state);
10217
10218         kfree(crtc_state);
10219
10220         return mode;
10221 }
10222
10223 static void intel_crtc_destroy(struct drm_crtc *crtc)
10224 {
10225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10226
10227         drm_crtc_cleanup(crtc);
10228         kfree(intel_crtc);
10229 }
10230
10231 /**
10232  * intel_wm_need_update - Check whether watermarks need updating
10233  * @plane: drm plane
10234  * @state: new plane state
10235  *
10236  * Check current plane state versus the new one to determine whether
10237  * watermarks need to be recalculated.
10238  *
10239  * Returns true or false.
10240  */
10241 static bool intel_wm_need_update(struct drm_plane *plane,
10242                                  struct drm_plane_state *state)
10243 {
10244         struct intel_plane_state *new = to_intel_plane_state(state);
10245         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10246
10247         /* Update watermarks on tiling or size changes. */
10248         if (new->base.visible != cur->base.visible)
10249                 return true;
10250
10251         if (!cur->base.fb || !new->base.fb)
10252                 return false;
10253
10254         if (cur->base.fb->modifier != new->base.fb->modifier ||
10255             cur->base.rotation != new->base.rotation ||
10256             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10257             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10258             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10259             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10260                 return true;
10261
10262         return false;
10263 }
10264
10265 static bool needs_scaling(const struct intel_plane_state *state)
10266 {
10267         int src_w = drm_rect_width(&state->base.src) >> 16;
10268         int src_h = drm_rect_height(&state->base.src) >> 16;
10269         int dst_w = drm_rect_width(&state->base.dst);
10270         int dst_h = drm_rect_height(&state->base.dst);
10271
10272         return (src_w != dst_w || src_h != dst_h);
10273 }
10274
10275 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10276                                     struct drm_crtc_state *crtc_state,
10277                                     const struct intel_plane_state *old_plane_state,
10278                                     struct drm_plane_state *plane_state)
10279 {
10280         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10281         struct drm_crtc *crtc = crtc_state->crtc;
10282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10283         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10284         struct drm_device *dev = crtc->dev;
10285         struct drm_i915_private *dev_priv = to_i915(dev);
10286         bool mode_changed = needs_modeset(crtc_state);
10287         bool was_crtc_enabled = old_crtc_state->base.active;
10288         bool is_crtc_enabled = crtc_state->active;
10289         bool turn_off, turn_on, visible, was_visible;
10290         struct drm_framebuffer *fb = plane_state->fb;
10291         int ret;
10292
10293         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10294                 ret = skl_update_scaler_plane(
10295                         to_intel_crtc_state(crtc_state),
10296                         to_intel_plane_state(plane_state));
10297                 if (ret)
10298                         return ret;
10299         }
10300
10301         was_visible = old_plane_state->base.visible;
10302         visible = plane_state->visible;
10303
10304         if (!was_crtc_enabled && WARN_ON(was_visible))
10305                 was_visible = false;
10306
10307         /*
10308          * Visibility is calculated as if the crtc was on, but
10309          * after scaler setup everything depends on it being off
10310          * when the crtc isn't active.
10311          *
10312          * FIXME this is wrong for watermarks. Watermarks should also
10313          * be computed as if the pipe would be active. Perhaps move
10314          * per-plane wm computation to the .check_plane() hook, and
10315          * only combine the results from all planes in the current place?
10316          */
10317         if (!is_crtc_enabled) {
10318                 plane_state->visible = visible = false;
10319                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10320         }
10321
10322         if (!was_visible && !visible)
10323                 return 0;
10324
10325         if (fb != old_plane_state->base.fb)
10326                 pipe_config->fb_changed = true;
10327
10328         turn_off = was_visible && (!visible || mode_changed);
10329         turn_on = visible && (!was_visible || mode_changed);
10330
10331         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10332                          intel_crtc->base.base.id, intel_crtc->base.name,
10333                          plane->base.base.id, plane->base.name,
10334                          fb ? fb->base.id : -1);
10335
10336         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10337                          plane->base.base.id, plane->base.name,
10338                          was_visible, visible,
10339                          turn_off, turn_on, mode_changed);
10340
10341         if (turn_on) {
10342                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10343                         pipe_config->update_wm_pre = true;
10344
10345                 /* must disable cxsr around plane enable/disable */
10346                 if (plane->id != PLANE_CURSOR)
10347                         pipe_config->disable_cxsr = true;
10348         } else if (turn_off) {
10349                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10350                         pipe_config->update_wm_post = true;
10351
10352                 /* must disable cxsr around plane enable/disable */
10353                 if (plane->id != PLANE_CURSOR)
10354                         pipe_config->disable_cxsr = true;
10355         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10356                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10357                         /* FIXME bollocks */
10358                         pipe_config->update_wm_pre = true;
10359                         pipe_config->update_wm_post = true;
10360                 }
10361         }
10362
10363         if (visible || was_visible)
10364                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10365
10366         /*
10367          * WaCxSRDisabledForSpriteScaling:ivb
10368          *
10369          * cstate->update_wm was already set above, so this flag will
10370          * take effect when we commit and program watermarks.
10371          */
10372         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10373             needs_scaling(to_intel_plane_state(plane_state)) &&
10374             !needs_scaling(old_plane_state))
10375                 pipe_config->disable_lp_wm = true;
10376
10377         return 0;
10378 }
10379
10380 static bool encoders_cloneable(const struct intel_encoder *a,
10381                                const struct intel_encoder *b)
10382 {
10383         /* masks could be asymmetric, so check both ways */
10384         return a == b || (a->cloneable & (1 << b->type) &&
10385                           b->cloneable & (1 << a->type));
10386 }
10387
10388 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10389                                          struct intel_crtc *crtc,
10390                                          struct intel_encoder *encoder)
10391 {
10392         struct intel_encoder *source_encoder;
10393         struct drm_connector *connector;
10394         struct drm_connector_state *connector_state;
10395         int i;
10396
10397         for_each_new_connector_in_state(state, connector, connector_state, i) {
10398                 if (connector_state->crtc != &crtc->base)
10399                         continue;
10400
10401                 source_encoder =
10402                         to_intel_encoder(connector_state->best_encoder);
10403                 if (!encoders_cloneable(encoder, source_encoder))
10404                         return false;
10405         }
10406
10407         return true;
10408 }
10409
10410 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10411                                    struct drm_crtc_state *crtc_state)
10412 {
10413         struct drm_device *dev = crtc->dev;
10414         struct drm_i915_private *dev_priv = to_i915(dev);
10415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10416         struct intel_crtc_state *pipe_config =
10417                 to_intel_crtc_state(crtc_state);
10418         struct drm_atomic_state *state = crtc_state->state;
10419         int ret;
10420         bool mode_changed = needs_modeset(crtc_state);
10421
10422         if (mode_changed && !crtc_state->active)
10423                 pipe_config->update_wm_post = true;
10424
10425         if (mode_changed && crtc_state->enable &&
10426             dev_priv->display.crtc_compute_clock &&
10427             !WARN_ON(pipe_config->shared_dpll)) {
10428                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10429                                                            pipe_config);
10430                 if (ret)
10431                         return ret;
10432         }
10433
10434         if (crtc_state->color_mgmt_changed) {
10435                 ret = intel_color_check(crtc, crtc_state);
10436                 if (ret)
10437                         return ret;
10438
10439                 /*
10440                  * Changing color management on Intel hardware is
10441                  * handled as part of planes update.
10442                  */
10443                 crtc_state->planes_changed = true;
10444         }
10445
10446         ret = 0;
10447         if (dev_priv->display.compute_pipe_wm) {
10448                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10449                 if (ret) {
10450                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10451                         return ret;
10452                 }
10453         }
10454
10455         if (dev_priv->display.compute_intermediate_wm &&
10456             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10457                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10458                         return 0;
10459
10460                 /*
10461                  * Calculate 'intermediate' watermarks that satisfy both the
10462                  * old state and the new state.  We can program these
10463                  * immediately.
10464                  */
10465                 ret = dev_priv->display.compute_intermediate_wm(dev,
10466                                                                 intel_crtc,
10467                                                                 pipe_config);
10468                 if (ret) {
10469                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10470                         return ret;
10471                 }
10472         } else if (dev_priv->display.compute_intermediate_wm) {
10473                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10474                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10475         }
10476
10477         if (INTEL_GEN(dev_priv) >= 9) {
10478                 if (mode_changed)
10479                         ret = skl_update_scaler_crtc(pipe_config);
10480
10481                 if (!ret)
10482                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10483                                                             pipe_config);
10484                 if (!ret)
10485                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10486                                                          pipe_config);
10487         }
10488
10489         return ret;
10490 }
10491
10492 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10493         .atomic_begin = intel_begin_crtc_commit,
10494         .atomic_flush = intel_finish_crtc_commit,
10495         .atomic_check = intel_crtc_atomic_check,
10496 };
10497
10498 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10499 {
10500         struct intel_connector *connector;
10501         struct drm_connector_list_iter conn_iter;
10502
10503         drm_connector_list_iter_begin(dev, &conn_iter);
10504         for_each_intel_connector_iter(connector, &conn_iter) {
10505                 if (connector->base.state->crtc)
10506                         drm_connector_unreference(&connector->base);
10507
10508                 if (connector->base.encoder) {
10509                         connector->base.state->best_encoder =
10510                                 connector->base.encoder;
10511                         connector->base.state->crtc =
10512                                 connector->base.encoder->crtc;
10513
10514                         drm_connector_reference(&connector->base);
10515                 } else {
10516                         connector->base.state->best_encoder = NULL;
10517                         connector->base.state->crtc = NULL;
10518                 }
10519         }
10520         drm_connector_list_iter_end(&conn_iter);
10521 }
10522
10523 static void
10524 connected_sink_compute_bpp(struct intel_connector *connector,
10525                            struct intel_crtc_state *pipe_config)
10526 {
10527         const struct drm_display_info *info = &connector->base.display_info;
10528         int bpp = pipe_config->pipe_bpp;
10529
10530         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10531                       connector->base.base.id,
10532                       connector->base.name);
10533
10534         /* Don't use an invalid EDID bpc value */
10535         if (info->bpc != 0 && info->bpc * 3 < bpp) {
10536                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10537                               bpp, info->bpc * 3);
10538                 pipe_config->pipe_bpp = info->bpc * 3;
10539         }
10540
10541         /* Clamp bpp to 8 on screens without EDID 1.4 */
10542         if (info->bpc == 0 && bpp > 24) {
10543                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10544                               bpp);
10545                 pipe_config->pipe_bpp = 24;
10546         }
10547 }
10548
10549 static int
10550 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10551                           struct intel_crtc_state *pipe_config)
10552 {
10553         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10554         struct drm_atomic_state *state;
10555         struct drm_connector *connector;
10556         struct drm_connector_state *connector_state;
10557         int bpp, i;
10558
10559         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10560             IS_CHERRYVIEW(dev_priv)))
10561                 bpp = 10*3;
10562         else if (INTEL_GEN(dev_priv) >= 5)
10563                 bpp = 12*3;
10564         else
10565                 bpp = 8*3;
10566
10567
10568         pipe_config->pipe_bpp = bpp;
10569
10570         state = pipe_config->base.state;
10571
10572         /* Clamp display bpp to EDID value */
10573         for_each_new_connector_in_state(state, connector, connector_state, i) {
10574                 if (connector_state->crtc != &crtc->base)
10575                         continue;
10576
10577                 connected_sink_compute_bpp(to_intel_connector(connector),
10578                                            pipe_config);
10579         }
10580
10581         return bpp;
10582 }
10583
10584 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10585 {
10586         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10587                         "type: 0x%x flags: 0x%x\n",
10588                 mode->crtc_clock,
10589                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10590                 mode->crtc_hsync_end, mode->crtc_htotal,
10591                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10592                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10593 }
10594
10595 static inline void
10596 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10597                       unsigned int lane_count, struct intel_link_m_n *m_n)
10598 {
10599         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10600                       id, lane_count,
10601                       m_n->gmch_m, m_n->gmch_n,
10602                       m_n->link_m, m_n->link_n, m_n->tu);
10603 }
10604
10605 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10606
10607 static const char * const output_type_str[] = {
10608         OUTPUT_TYPE(UNUSED),
10609         OUTPUT_TYPE(ANALOG),
10610         OUTPUT_TYPE(DVO),
10611         OUTPUT_TYPE(SDVO),
10612         OUTPUT_TYPE(LVDS),
10613         OUTPUT_TYPE(TVOUT),
10614         OUTPUT_TYPE(HDMI),
10615         OUTPUT_TYPE(DP),
10616         OUTPUT_TYPE(EDP),
10617         OUTPUT_TYPE(DSI),
10618         OUTPUT_TYPE(DDI),
10619         OUTPUT_TYPE(DP_MST),
10620 };
10621
10622 #undef OUTPUT_TYPE
10623
10624 static void snprintf_output_types(char *buf, size_t len,
10625                                   unsigned int output_types)
10626 {
10627         char *str = buf;
10628         int i;
10629
10630         str[0] = '\0';
10631
10632         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10633                 int r;
10634
10635                 if ((output_types & BIT(i)) == 0)
10636                         continue;
10637
10638                 r = snprintf(str, len, "%s%s",
10639                              str != buf ? "," : "", output_type_str[i]);
10640                 if (r >= len)
10641                         break;
10642                 str += r;
10643                 len -= r;
10644
10645                 output_types &= ~BIT(i);
10646         }
10647
10648         WARN_ON_ONCE(output_types != 0);
10649 }
10650
10651 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10652                                    struct intel_crtc_state *pipe_config,
10653                                    const char *context)
10654 {
10655         struct drm_device *dev = crtc->base.dev;
10656         struct drm_i915_private *dev_priv = to_i915(dev);
10657         struct drm_plane *plane;
10658         struct intel_plane *intel_plane;
10659         struct intel_plane_state *state;
10660         struct drm_framebuffer *fb;
10661         char buf[64];
10662
10663         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10664                       crtc->base.base.id, crtc->base.name, context);
10665
10666         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10667         DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10668                       buf, pipe_config->output_types);
10669
10670         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10671                       transcoder_name(pipe_config->cpu_transcoder),
10672                       pipe_config->pipe_bpp, pipe_config->dither);
10673
10674         if (pipe_config->has_pch_encoder)
10675                 intel_dump_m_n_config(pipe_config, "fdi",
10676                                       pipe_config->fdi_lanes,
10677                                       &pipe_config->fdi_m_n);
10678
10679         if (pipe_config->ycbcr420)
10680                 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10681
10682         if (intel_crtc_has_dp_encoder(pipe_config)) {
10683                 intel_dump_m_n_config(pipe_config, "dp m_n",
10684                                 pipe_config->lane_count, &pipe_config->dp_m_n);
10685                 if (pipe_config->has_drrs)
10686                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
10687                                               pipe_config->lane_count,
10688                                               &pipe_config->dp_m2_n2);
10689         }
10690
10691         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10692                       pipe_config->has_audio, pipe_config->has_infoframe);
10693
10694         DRM_DEBUG_KMS("requested mode:\n");
10695         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10696         DRM_DEBUG_KMS("adjusted mode:\n");
10697         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10698         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10699         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10700                       pipe_config->port_clock,
10701                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10702                       pipe_config->pixel_rate);
10703
10704         if (INTEL_GEN(dev_priv) >= 9)
10705                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10706                               crtc->num_scalers,
10707                               pipe_config->scaler_state.scaler_users,
10708                               pipe_config->scaler_state.scaler_id);
10709
10710         if (HAS_GMCH_DISPLAY(dev_priv))
10711                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10712                               pipe_config->gmch_pfit.control,
10713                               pipe_config->gmch_pfit.pgm_ratios,
10714                               pipe_config->gmch_pfit.lvds_border_bits);
10715         else
10716                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10717                               pipe_config->pch_pfit.pos,
10718                               pipe_config->pch_pfit.size,
10719                               enableddisabled(pipe_config->pch_pfit.enabled));
10720
10721         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10722                       pipe_config->ips_enabled, pipe_config->double_wide);
10723
10724         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10725
10726         DRM_DEBUG_KMS("planes on this crtc\n");
10727         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10728                 struct drm_format_name_buf format_name;
10729                 intel_plane = to_intel_plane(plane);
10730                 if (intel_plane->pipe != crtc->pipe)
10731                         continue;
10732
10733                 state = to_intel_plane_state(plane->state);
10734                 fb = state->base.fb;
10735                 if (!fb) {
10736                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10737                                       plane->base.id, plane->name, state->scaler_id);
10738                         continue;
10739                 }
10740
10741                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10742                               plane->base.id, plane->name,
10743                               fb->base.id, fb->width, fb->height,
10744                               drm_get_format_name(fb->format->format, &format_name));
10745                 if (INTEL_GEN(dev_priv) >= 9)
10746                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10747                                       state->scaler_id,
10748                                       state->base.src.x1 >> 16,
10749                                       state->base.src.y1 >> 16,
10750                                       drm_rect_width(&state->base.src) >> 16,
10751                                       drm_rect_height(&state->base.src) >> 16,
10752                                       state->base.dst.x1, state->base.dst.y1,
10753                                       drm_rect_width(&state->base.dst),
10754                                       drm_rect_height(&state->base.dst));
10755         }
10756 }
10757
10758 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10759 {
10760         struct drm_device *dev = state->dev;
10761         struct drm_connector *connector;
10762         struct drm_connector_list_iter conn_iter;
10763         unsigned int used_ports = 0;
10764         unsigned int used_mst_ports = 0;
10765
10766         /*
10767          * Walk the connector list instead of the encoder
10768          * list to detect the problem on ddi platforms
10769          * where there's just one encoder per digital port.
10770          */
10771         drm_connector_list_iter_begin(dev, &conn_iter);
10772         drm_for_each_connector_iter(connector, &conn_iter) {
10773                 struct drm_connector_state *connector_state;
10774                 struct intel_encoder *encoder;
10775
10776                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10777                 if (!connector_state)
10778                         connector_state = connector->state;
10779
10780                 if (!connector_state->best_encoder)
10781                         continue;
10782
10783                 encoder = to_intel_encoder(connector_state->best_encoder);
10784
10785                 WARN_ON(!connector_state->crtc);
10786
10787                 switch (encoder->type) {
10788                         unsigned int port_mask;
10789                 case INTEL_OUTPUT_DDI:
10790                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
10791                                 break;
10792                 case INTEL_OUTPUT_DP:
10793                 case INTEL_OUTPUT_HDMI:
10794                 case INTEL_OUTPUT_EDP:
10795                         port_mask = 1 << encoder->port;
10796
10797                         /* the same port mustn't appear more than once */
10798                         if (used_ports & port_mask)
10799                                 return false;
10800
10801                         used_ports |= port_mask;
10802                         break;
10803                 case INTEL_OUTPUT_DP_MST:
10804                         used_mst_ports |=
10805                                 1 << encoder->port;
10806                         break;
10807                 default:
10808                         break;
10809                 }
10810         }
10811         drm_connector_list_iter_end(&conn_iter);
10812
10813         /* can't mix MST and SST/HDMI on the same port */
10814         if (used_ports & used_mst_ports)
10815                 return false;
10816
10817         return true;
10818 }
10819
10820 static void
10821 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10822 {
10823         struct drm_i915_private *dev_priv =
10824                 to_i915(crtc_state->base.crtc->dev);
10825         struct intel_crtc_scaler_state scaler_state;
10826         struct intel_dpll_hw_state dpll_hw_state;
10827         struct intel_shared_dpll *shared_dpll;
10828         struct intel_crtc_wm_state wm_state;
10829         bool force_thru, ips_force_disable;
10830
10831         /* FIXME: before the switch to atomic started, a new pipe_config was
10832          * kzalloc'd. Code that depends on any field being zero should be
10833          * fixed, so that the crtc_state can be safely duplicated. For now,
10834          * only fields that are know to not cause problems are preserved. */
10835
10836         scaler_state = crtc_state->scaler_state;
10837         shared_dpll = crtc_state->shared_dpll;
10838         dpll_hw_state = crtc_state->dpll_hw_state;
10839         force_thru = crtc_state->pch_pfit.force_thru;
10840         ips_force_disable = crtc_state->ips_force_disable;
10841         if (IS_G4X(dev_priv) ||
10842             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10843                 wm_state = crtc_state->wm;
10844
10845         /* Keep base drm_crtc_state intact, only clear our extended struct */
10846         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10847         memset(&crtc_state->base + 1, 0,
10848                sizeof(*crtc_state) - sizeof(crtc_state->base));
10849
10850         crtc_state->scaler_state = scaler_state;
10851         crtc_state->shared_dpll = shared_dpll;
10852         crtc_state->dpll_hw_state = dpll_hw_state;
10853         crtc_state->pch_pfit.force_thru = force_thru;
10854         crtc_state->ips_force_disable = ips_force_disable;
10855         if (IS_G4X(dev_priv) ||
10856             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10857                 crtc_state->wm = wm_state;
10858 }
10859
10860 static int
10861 intel_modeset_pipe_config(struct drm_crtc *crtc,
10862                           struct intel_crtc_state *pipe_config)
10863 {
10864         struct drm_atomic_state *state = pipe_config->base.state;
10865         struct intel_encoder *encoder;
10866         struct drm_connector *connector;
10867         struct drm_connector_state *connector_state;
10868         int base_bpp, ret = -EINVAL;
10869         int i;
10870         bool retry = true;
10871
10872         clear_intel_crtc_state(pipe_config);
10873
10874         pipe_config->cpu_transcoder =
10875                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10876
10877         /*
10878          * Sanitize sync polarity flags based on requested ones. If neither
10879          * positive or negative polarity is requested, treat this as meaning
10880          * negative polarity.
10881          */
10882         if (!(pipe_config->base.adjusted_mode.flags &
10883               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10884                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10885
10886         if (!(pipe_config->base.adjusted_mode.flags &
10887               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10888                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10889
10890         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10891                                              pipe_config);
10892         if (base_bpp < 0)
10893                 goto fail;
10894
10895         /*
10896          * Determine the real pipe dimensions. Note that stereo modes can
10897          * increase the actual pipe size due to the frame doubling and
10898          * insertion of additional space for blanks between the frame. This
10899          * is stored in the crtc timings. We use the requested mode to do this
10900          * computation to clearly distinguish it from the adjusted mode, which
10901          * can be changed by the connectors in the below retry loop.
10902          */
10903         drm_mode_get_hv_timing(&pipe_config->base.mode,
10904                                &pipe_config->pipe_src_w,
10905                                &pipe_config->pipe_src_h);
10906
10907         for_each_new_connector_in_state(state, connector, connector_state, i) {
10908                 if (connector_state->crtc != crtc)
10909                         continue;
10910
10911                 encoder = to_intel_encoder(connector_state->best_encoder);
10912
10913                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10914                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10915                         goto fail;
10916                 }
10917
10918                 /*
10919                  * Determine output_types before calling the .compute_config()
10920                  * hooks so that the hooks can use this information safely.
10921                  */
10922                 if (encoder->compute_output_type)
10923                         pipe_config->output_types |=
10924                                 BIT(encoder->compute_output_type(encoder, pipe_config,
10925                                                                  connector_state));
10926                 else
10927                         pipe_config->output_types |= BIT(encoder->type);
10928         }
10929
10930 encoder_retry:
10931         /* Ensure the port clock defaults are reset when retrying. */
10932         pipe_config->port_clock = 0;
10933         pipe_config->pixel_multiplier = 1;
10934
10935         /* Fill in default crtc timings, allow encoders to overwrite them. */
10936         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10937                               CRTC_STEREO_DOUBLE);
10938
10939         /* Pass our mode to the connectors and the CRTC to give them a chance to
10940          * adjust it according to limitations or connector properties, and also
10941          * a chance to reject the mode entirely.
10942          */
10943         for_each_new_connector_in_state(state, connector, connector_state, i) {
10944                 if (connector_state->crtc != crtc)
10945                         continue;
10946
10947                 encoder = to_intel_encoder(connector_state->best_encoder);
10948
10949                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10950                         DRM_DEBUG_KMS("Encoder config failure\n");
10951                         goto fail;
10952                 }
10953         }
10954
10955         /* Set default port clock if not overwritten by the encoder. Needs to be
10956          * done afterwards in case the encoder adjusts the mode. */
10957         if (!pipe_config->port_clock)
10958                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10959                         * pipe_config->pixel_multiplier;
10960
10961         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10962         if (ret < 0) {
10963                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10964                 goto fail;
10965         }
10966
10967         if (ret == RETRY) {
10968                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10969                         ret = -EINVAL;
10970                         goto fail;
10971                 }
10972
10973                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10974                 retry = false;
10975                 goto encoder_retry;
10976         }
10977
10978         /* Dithering seems to not pass-through bits correctly when it should, so
10979          * only enable it on 6bpc panels and when its not a compliance
10980          * test requesting 6bpc video pattern.
10981          */
10982         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10983                 !pipe_config->dither_force_disable;
10984         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10985                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10986
10987 fail:
10988         return ret;
10989 }
10990
10991 static void
10992 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10993 {
10994         struct drm_crtc *crtc;
10995         struct drm_crtc_state *new_crtc_state;
10996         int i;
10997
10998         /* Double check state. */
10999         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11000                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11001
11002                 /*
11003                  * Update legacy state to satisfy fbc code. This can
11004                  * be removed when fbc uses the atomic state.
11005                  */
11006                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11007                         struct drm_plane_state *plane_state = crtc->primary->state;
11008
11009                         crtc->primary->fb = plane_state->fb;
11010                         crtc->x = plane_state->src_x >> 16;
11011                         crtc->y = plane_state->src_y >> 16;
11012                 }
11013         }
11014 }
11015
11016 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11017 {
11018         int diff;
11019
11020         if (clock1 == clock2)
11021                 return true;
11022
11023         if (!clock1 || !clock2)
11024                 return false;
11025
11026         diff = abs(clock1 - clock2);
11027
11028         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11029                 return true;
11030
11031         return false;
11032 }
11033
11034 static bool
11035 intel_compare_m_n(unsigned int m, unsigned int n,
11036                   unsigned int m2, unsigned int n2,
11037                   bool exact)
11038 {
11039         if (m == m2 && n == n2)
11040                 return true;
11041
11042         if (exact || !m || !n || !m2 || !n2)
11043                 return false;
11044
11045         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11046
11047         if (n > n2) {
11048                 while (n > n2) {
11049                         m2 <<= 1;
11050                         n2 <<= 1;
11051                 }
11052         } else if (n < n2) {
11053                 while (n < n2) {
11054                         m <<= 1;
11055                         n <<= 1;
11056                 }
11057         }
11058
11059         if (n != n2)
11060                 return false;
11061
11062         return intel_fuzzy_clock_check(m, m2);
11063 }
11064
11065 static bool
11066 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11067                        struct intel_link_m_n *m2_n2,
11068                        bool adjust)
11069 {
11070         if (m_n->tu == m2_n2->tu &&
11071             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11072                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11073             intel_compare_m_n(m_n->link_m, m_n->link_n,
11074                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11075                 if (adjust)
11076                         *m2_n2 = *m_n;
11077
11078                 return true;
11079         }
11080
11081         return false;
11082 }
11083
11084 static void __printf(3, 4)
11085 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11086 {
11087         char *level;
11088         unsigned int category;
11089         struct va_format vaf;
11090         va_list args;
11091
11092         if (adjust) {
11093                 level = KERN_DEBUG;
11094                 category = DRM_UT_KMS;
11095         } else {
11096                 level = KERN_ERR;
11097                 category = DRM_UT_NONE;
11098         }
11099
11100         va_start(args, format);
11101         vaf.fmt = format;
11102         vaf.va = &args;
11103
11104         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11105
11106         va_end(args);
11107 }
11108
11109 static bool
11110 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11111                           struct intel_crtc_state *current_config,
11112                           struct intel_crtc_state *pipe_config,
11113                           bool adjust)
11114 {
11115         bool ret = true;
11116         bool fixup_inherited = adjust &&
11117                 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11118                 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11119
11120 #define PIPE_CONF_CHECK_X(name) \
11121         if (current_config->name != pipe_config->name) { \
11122                 pipe_config_err(adjust, __stringify(name), \
11123                           "(expected 0x%08x, found 0x%08x)\n", \
11124                           current_config->name, \
11125                           pipe_config->name); \
11126                 ret = false; \
11127         }
11128
11129 #define PIPE_CONF_CHECK_I(name) \
11130         if (current_config->name != pipe_config->name) { \
11131                 pipe_config_err(adjust, __stringify(name), \
11132                           "(expected %i, found %i)\n", \
11133                           current_config->name, \
11134                           pipe_config->name); \
11135                 ret = false; \
11136         }
11137
11138 #define PIPE_CONF_CHECK_BOOL(name)      \
11139         if (current_config->name != pipe_config->name) { \
11140                 pipe_config_err(adjust, __stringify(name), \
11141                           "(expected %s, found %s)\n", \
11142                           yesno(current_config->name), \
11143                           yesno(pipe_config->name)); \
11144                 ret = false; \
11145         }
11146
11147 /*
11148  * Checks state where we only read out the enabling, but not the entire
11149  * state itself (like full infoframes or ELD for audio). These states
11150  * require a full modeset on bootup to fix up.
11151  */
11152 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) \
11153         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11154                 PIPE_CONF_CHECK_BOOL(name); \
11155         } else { \
11156                 pipe_config_err(adjust, __stringify(name), \
11157                           "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
11158                           yesno(current_config->name), \
11159                           yesno(pipe_config->name)); \
11160                 ret = false; \
11161         }
11162
11163 #define PIPE_CONF_CHECK_P(name) \
11164         if (current_config->name != pipe_config->name) { \
11165                 pipe_config_err(adjust, __stringify(name), \
11166                           "(expected %p, found %p)\n", \
11167                           current_config->name, \
11168                           pipe_config->name); \
11169                 ret = false; \
11170         }
11171
11172 #define PIPE_CONF_CHECK_M_N(name) \
11173         if (!intel_compare_link_m_n(&current_config->name, \
11174                                     &pipe_config->name,\
11175                                     adjust)) { \
11176                 pipe_config_err(adjust, __stringify(name), \
11177                           "(expected tu %i gmch %i/%i link %i/%i, " \
11178                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11179                           current_config->name.tu, \
11180                           current_config->name.gmch_m, \
11181                           current_config->name.gmch_n, \
11182                           current_config->name.link_m, \
11183                           current_config->name.link_n, \
11184                           pipe_config->name.tu, \
11185                           pipe_config->name.gmch_m, \
11186                           pipe_config->name.gmch_n, \
11187                           pipe_config->name.link_m, \
11188                           pipe_config->name.link_n); \
11189                 ret = false; \
11190         }
11191
11192 /* This is required for BDW+ where there is only one set of registers for
11193  * switching between high and low RR.
11194  * This macro can be used whenever a comparison has to be made between one
11195  * hw state and multiple sw state variables.
11196  */
11197 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11198         if (!intel_compare_link_m_n(&current_config->name, \
11199                                     &pipe_config->name, adjust) && \
11200             !intel_compare_link_m_n(&current_config->alt_name, \
11201                                     &pipe_config->name, adjust)) { \
11202                 pipe_config_err(adjust, __stringify(name), \
11203                           "(expected tu %i gmch %i/%i link %i/%i, " \
11204                           "or tu %i gmch %i/%i link %i/%i, " \
11205                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11206                           current_config->name.tu, \
11207                           current_config->name.gmch_m, \
11208                           current_config->name.gmch_n, \
11209                           current_config->name.link_m, \
11210                           current_config->name.link_n, \
11211                           current_config->alt_name.tu, \
11212                           current_config->alt_name.gmch_m, \
11213                           current_config->alt_name.gmch_n, \
11214                           current_config->alt_name.link_m, \
11215                           current_config->alt_name.link_n, \
11216                           pipe_config->name.tu, \
11217                           pipe_config->name.gmch_m, \
11218                           pipe_config->name.gmch_n, \
11219                           pipe_config->name.link_m, \
11220                           pipe_config->name.link_n); \
11221                 ret = false; \
11222         }
11223
11224 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11225         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11226                 pipe_config_err(adjust, __stringify(name), \
11227                           "(%x) (expected %i, found %i)\n", \
11228                           (mask), \
11229                           current_config->name & (mask), \
11230                           pipe_config->name & (mask)); \
11231                 ret = false; \
11232         }
11233
11234 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11235         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11236                 pipe_config_err(adjust, __stringify(name), \
11237                           "(expected %i, found %i)\n", \
11238                           current_config->name, \
11239                           pipe_config->name); \
11240                 ret = false; \
11241         }
11242
11243 #define PIPE_CONF_QUIRK(quirk)  \
11244         ((current_config->quirks | pipe_config->quirks) & (quirk))
11245
11246         PIPE_CONF_CHECK_I(cpu_transcoder);
11247
11248         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11249         PIPE_CONF_CHECK_I(fdi_lanes);
11250         PIPE_CONF_CHECK_M_N(fdi_m_n);
11251
11252         PIPE_CONF_CHECK_I(lane_count);
11253         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11254
11255         if (INTEL_GEN(dev_priv) < 8) {
11256                 PIPE_CONF_CHECK_M_N(dp_m_n);
11257
11258                 if (current_config->has_drrs)
11259                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11260         } else
11261                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11262
11263         PIPE_CONF_CHECK_X(output_types);
11264
11265         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11266         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11267         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11268         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11269         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11270         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11271
11272         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11273         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11274         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11275         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11276         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11277         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11278
11279         PIPE_CONF_CHECK_I(pixel_multiplier);
11280         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11281         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11282             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11283                 PIPE_CONF_CHECK_BOOL(limited_color_range);
11284
11285         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11286         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11287         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11288         PIPE_CONF_CHECK_BOOL(ycbcr420);
11289
11290         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11291
11292         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11293                               DRM_MODE_FLAG_INTERLACE);
11294
11295         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11296                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11297                                       DRM_MODE_FLAG_PHSYNC);
11298                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11299                                       DRM_MODE_FLAG_NHSYNC);
11300                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11301                                       DRM_MODE_FLAG_PVSYNC);
11302                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11303                                       DRM_MODE_FLAG_NVSYNC);
11304         }
11305
11306         PIPE_CONF_CHECK_X(gmch_pfit.control);
11307         /* pfit ratios are autocomputed by the hw on gen4+ */
11308         if (INTEL_GEN(dev_priv) < 4)
11309                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11310         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11311
11312         if (!adjust) {
11313                 PIPE_CONF_CHECK_I(pipe_src_w);
11314                 PIPE_CONF_CHECK_I(pipe_src_h);
11315
11316                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11317                 if (current_config->pch_pfit.enabled) {
11318                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11319                         PIPE_CONF_CHECK_X(pch_pfit.size);
11320                 }
11321
11322                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11323                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11324         }
11325
11326         PIPE_CONF_CHECK_BOOL(double_wide);
11327
11328         PIPE_CONF_CHECK_P(shared_dpll);
11329         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11330         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11331         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11332         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11333         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11334         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11335         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11336         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11337         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11338         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11339         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11340         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11341         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11342         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11343         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11344         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11345         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11346         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11347         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11348         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11349         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11350
11351         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11352         PIPE_CONF_CHECK_X(dsi_pll.div);
11353
11354         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11355                 PIPE_CONF_CHECK_I(pipe_bpp);
11356
11357         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11358         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11359
11360         PIPE_CONF_CHECK_I(min_voltage_level);
11361
11362 #undef PIPE_CONF_CHECK_X
11363 #undef PIPE_CONF_CHECK_I
11364 #undef PIPE_CONF_CHECK_BOOL
11365 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11366 #undef PIPE_CONF_CHECK_P
11367 #undef PIPE_CONF_CHECK_FLAGS
11368 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11369 #undef PIPE_CONF_QUIRK
11370
11371         return ret;
11372 }
11373
11374 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11375                                            const struct intel_crtc_state *pipe_config)
11376 {
11377         if (pipe_config->has_pch_encoder) {
11378                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11379                                                             &pipe_config->fdi_m_n);
11380                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11381
11382                 /*
11383                  * FDI already provided one idea for the dotclock.
11384                  * Yell if the encoder disagrees.
11385                  */
11386                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11387                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11388                      fdi_dotclock, dotclock);
11389         }
11390 }
11391
11392 static void verify_wm_state(struct drm_crtc *crtc,
11393                             struct drm_crtc_state *new_state)
11394 {
11395         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11396         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11397         struct skl_pipe_wm hw_wm, *sw_wm;
11398         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11399         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11401         const enum pipe pipe = intel_crtc->pipe;
11402         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11403
11404         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11405                 return;
11406
11407         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11408         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11409
11410         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11411         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11412
11413         /* planes */
11414         for_each_universal_plane(dev_priv, pipe, plane) {
11415                 hw_plane_wm = &hw_wm.planes[plane];
11416                 sw_plane_wm = &sw_wm->planes[plane];
11417
11418                 /* Watermarks */
11419                 for (level = 0; level <= max_level; level++) {
11420                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11421                                                 &sw_plane_wm->wm[level]))
11422                                 continue;
11423
11424                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11425                                   pipe_name(pipe), plane + 1, level,
11426                                   sw_plane_wm->wm[level].plane_en,
11427                                   sw_plane_wm->wm[level].plane_res_b,
11428                                   sw_plane_wm->wm[level].plane_res_l,
11429                                   hw_plane_wm->wm[level].plane_en,
11430                                   hw_plane_wm->wm[level].plane_res_b,
11431                                   hw_plane_wm->wm[level].plane_res_l);
11432                 }
11433
11434                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11435                                          &sw_plane_wm->trans_wm)) {
11436                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11437                                   pipe_name(pipe), plane + 1,
11438                                   sw_plane_wm->trans_wm.plane_en,
11439                                   sw_plane_wm->trans_wm.plane_res_b,
11440                                   sw_plane_wm->trans_wm.plane_res_l,
11441                                   hw_plane_wm->trans_wm.plane_en,
11442                                   hw_plane_wm->trans_wm.plane_res_b,
11443                                   hw_plane_wm->trans_wm.plane_res_l);
11444                 }
11445
11446                 /* DDB */
11447                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11448                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11449
11450                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11451                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11452                                   pipe_name(pipe), plane + 1,
11453                                   sw_ddb_entry->start, sw_ddb_entry->end,
11454                                   hw_ddb_entry->start, hw_ddb_entry->end);
11455                 }
11456         }
11457
11458         /*
11459          * cursor
11460          * If the cursor plane isn't active, we may not have updated it's ddb
11461          * allocation. In that case since the ddb allocation will be updated
11462          * once the plane becomes visible, we can skip this check
11463          */
11464         if (1) {
11465                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11466                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11467
11468                 /* Watermarks */
11469                 for (level = 0; level <= max_level; level++) {
11470                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11471                                                 &sw_plane_wm->wm[level]))
11472                                 continue;
11473
11474                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11475                                   pipe_name(pipe), level,
11476                                   sw_plane_wm->wm[level].plane_en,
11477                                   sw_plane_wm->wm[level].plane_res_b,
11478                                   sw_plane_wm->wm[level].plane_res_l,
11479                                   hw_plane_wm->wm[level].plane_en,
11480                                   hw_plane_wm->wm[level].plane_res_b,
11481                                   hw_plane_wm->wm[level].plane_res_l);
11482                 }
11483
11484                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11485                                          &sw_plane_wm->trans_wm)) {
11486                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11487                                   pipe_name(pipe),
11488                                   sw_plane_wm->trans_wm.plane_en,
11489                                   sw_plane_wm->trans_wm.plane_res_b,
11490                                   sw_plane_wm->trans_wm.plane_res_l,
11491                                   hw_plane_wm->trans_wm.plane_en,
11492                                   hw_plane_wm->trans_wm.plane_res_b,
11493                                   hw_plane_wm->trans_wm.plane_res_l);
11494                 }
11495
11496                 /* DDB */
11497                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11498                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11499
11500                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11501                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11502                                   pipe_name(pipe),
11503                                   sw_ddb_entry->start, sw_ddb_entry->end,
11504                                   hw_ddb_entry->start, hw_ddb_entry->end);
11505                 }
11506         }
11507 }
11508
11509 static void
11510 verify_connector_state(struct drm_device *dev,
11511                        struct drm_atomic_state *state,
11512                        struct drm_crtc *crtc)
11513 {
11514         struct drm_connector *connector;
11515         struct drm_connector_state *new_conn_state;
11516         int i;
11517
11518         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11519                 struct drm_encoder *encoder = connector->encoder;
11520                 struct drm_crtc_state *crtc_state = NULL;
11521
11522                 if (new_conn_state->crtc != crtc)
11523                         continue;
11524
11525                 if (crtc)
11526                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11527
11528                 intel_connector_verify_state(crtc_state, new_conn_state);
11529
11530                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11531                      "connector's atomic encoder doesn't match legacy encoder\n");
11532         }
11533 }
11534
11535 static void
11536 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11537 {
11538         struct intel_encoder *encoder;
11539         struct drm_connector *connector;
11540         struct drm_connector_state *old_conn_state, *new_conn_state;
11541         int i;
11542
11543         for_each_intel_encoder(dev, encoder) {
11544                 bool enabled = false, found = false;
11545                 enum pipe pipe;
11546
11547                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11548                               encoder->base.base.id,
11549                               encoder->base.name);
11550
11551                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11552                                                    new_conn_state, i) {
11553                         if (old_conn_state->best_encoder == &encoder->base)
11554                                 found = true;
11555
11556                         if (new_conn_state->best_encoder != &encoder->base)
11557                                 continue;
11558                         found = enabled = true;
11559
11560                         I915_STATE_WARN(new_conn_state->crtc !=
11561                                         encoder->base.crtc,
11562                              "connector's crtc doesn't match encoder crtc\n");
11563                 }
11564
11565                 if (!found)
11566                         continue;
11567
11568                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11569                      "encoder's enabled state mismatch "
11570                      "(expected %i, found %i)\n",
11571                      !!encoder->base.crtc, enabled);
11572
11573                 if (!encoder->base.crtc) {
11574                         bool active;
11575
11576                         active = encoder->get_hw_state(encoder, &pipe);
11577                         I915_STATE_WARN(active,
11578                              "encoder detached but still enabled on pipe %c.\n",
11579                              pipe_name(pipe));
11580                 }
11581         }
11582 }
11583
11584 static void
11585 verify_crtc_state(struct drm_crtc *crtc,
11586                   struct drm_crtc_state *old_crtc_state,
11587                   struct drm_crtc_state *new_crtc_state)
11588 {
11589         struct drm_device *dev = crtc->dev;
11590         struct drm_i915_private *dev_priv = to_i915(dev);
11591         struct intel_encoder *encoder;
11592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11593         struct intel_crtc_state *pipe_config, *sw_config;
11594         struct drm_atomic_state *old_state;
11595         bool active;
11596
11597         old_state = old_crtc_state->state;
11598         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11599         pipe_config = to_intel_crtc_state(old_crtc_state);
11600         memset(pipe_config, 0, sizeof(*pipe_config));
11601         pipe_config->base.crtc = crtc;
11602         pipe_config->base.state = old_state;
11603
11604         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11605
11606         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11607
11608         /* we keep both pipes enabled on 830 */
11609         if (IS_I830(dev_priv))
11610                 active = new_crtc_state->active;
11611
11612         I915_STATE_WARN(new_crtc_state->active != active,
11613              "crtc active state doesn't match with hw state "
11614              "(expected %i, found %i)\n", new_crtc_state->active, active);
11615
11616         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11617              "transitional active state does not match atomic hw state "
11618              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11619
11620         for_each_encoder_on_crtc(dev, crtc, encoder) {
11621                 enum pipe pipe;
11622
11623                 active = encoder->get_hw_state(encoder, &pipe);
11624                 I915_STATE_WARN(active != new_crtc_state->active,
11625                         "[ENCODER:%i] active %i with crtc active %i\n",
11626                         encoder->base.base.id, active, new_crtc_state->active);
11627
11628                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11629                                 "Encoder connected to wrong pipe %c\n",
11630                                 pipe_name(pipe));
11631
11632                 if (active)
11633                         encoder->get_config(encoder, pipe_config);
11634         }
11635
11636         intel_crtc_compute_pixel_rate(pipe_config);
11637
11638         if (!new_crtc_state->active)
11639                 return;
11640
11641         intel_pipe_config_sanity_check(dev_priv, pipe_config);
11642
11643         sw_config = to_intel_crtc_state(new_crtc_state);
11644         if (!intel_pipe_config_compare(dev_priv, sw_config,
11645                                        pipe_config, false)) {
11646                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11647                 intel_dump_pipe_config(intel_crtc, pipe_config,
11648                                        "[hw state]");
11649                 intel_dump_pipe_config(intel_crtc, sw_config,
11650                                        "[sw state]");
11651         }
11652 }
11653
11654 static void
11655 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11656                          struct intel_shared_dpll *pll,
11657                          struct drm_crtc *crtc,
11658                          struct drm_crtc_state *new_state)
11659 {
11660         struct intel_dpll_hw_state dpll_hw_state;
11661         unsigned crtc_mask;
11662         bool active;
11663
11664         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11665
11666         DRM_DEBUG_KMS("%s\n", pll->name);
11667
11668         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11669
11670         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11671                 I915_STATE_WARN(!pll->on && pll->active_mask,
11672                      "pll in active use but not on in sw tracking\n");
11673                 I915_STATE_WARN(pll->on && !pll->active_mask,
11674                      "pll is on but not used by any active crtc\n");
11675                 I915_STATE_WARN(pll->on != active,
11676                      "pll on state mismatch (expected %i, found %i)\n",
11677                      pll->on, active);
11678         }
11679
11680         if (!crtc) {
11681                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11682                                 "more active pll users than references: %x vs %x\n",
11683                                 pll->active_mask, pll->state.crtc_mask);
11684
11685                 return;
11686         }
11687
11688         crtc_mask = 1 << drm_crtc_index(crtc);
11689
11690         if (new_state->active)
11691                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11692                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11693                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11694         else
11695                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11696                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11697                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11698
11699         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11700                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11701                         crtc_mask, pll->state.crtc_mask);
11702
11703         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11704                                           &dpll_hw_state,
11705                                           sizeof(dpll_hw_state)),
11706                         "pll hw state mismatch\n");
11707 }
11708
11709 static void
11710 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11711                          struct drm_crtc_state *old_crtc_state,
11712                          struct drm_crtc_state *new_crtc_state)
11713 {
11714         struct drm_i915_private *dev_priv = to_i915(dev);
11715         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11716         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11717
11718         if (new_state->shared_dpll)
11719                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11720
11721         if (old_state->shared_dpll &&
11722             old_state->shared_dpll != new_state->shared_dpll) {
11723                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11724                 struct intel_shared_dpll *pll = old_state->shared_dpll;
11725
11726                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11727                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11728                                 pipe_name(drm_crtc_index(crtc)));
11729                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11730                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11731                                 pipe_name(drm_crtc_index(crtc)));
11732         }
11733 }
11734
11735 static void
11736 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11737                           struct drm_atomic_state *state,
11738                           struct drm_crtc_state *old_state,
11739                           struct drm_crtc_state *new_state)
11740 {
11741         if (!needs_modeset(new_state) &&
11742             !to_intel_crtc_state(new_state)->update_pipe)
11743                 return;
11744
11745         verify_wm_state(crtc, new_state);
11746         verify_connector_state(crtc->dev, state, crtc);
11747         verify_crtc_state(crtc, old_state, new_state);
11748         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11749 }
11750
11751 static void
11752 verify_disabled_dpll_state(struct drm_device *dev)
11753 {
11754         struct drm_i915_private *dev_priv = to_i915(dev);
11755         int i;
11756
11757         for (i = 0; i < dev_priv->num_shared_dpll; i++)
11758                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11759 }
11760
11761 static void
11762 intel_modeset_verify_disabled(struct drm_device *dev,
11763                               struct drm_atomic_state *state)
11764 {
11765         verify_encoder_state(dev, state);
11766         verify_connector_state(dev, state, NULL);
11767         verify_disabled_dpll_state(dev);
11768 }
11769
11770 static void update_scanline_offset(struct intel_crtc *crtc)
11771 {
11772         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11773
11774         /*
11775          * The scanline counter increments at the leading edge of hsync.
11776          *
11777          * On most platforms it starts counting from vtotal-1 on the
11778          * first active line. That means the scanline counter value is
11779          * always one less than what we would expect. Ie. just after
11780          * start of vblank, which also occurs at start of hsync (on the
11781          * last active line), the scanline counter will read vblank_start-1.
11782          *
11783          * On gen2 the scanline counter starts counting from 1 instead
11784          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11785          * to keep the value positive), instead of adding one.
11786          *
11787          * On HSW+ the behaviour of the scanline counter depends on the output
11788          * type. For DP ports it behaves like most other platforms, but on HDMI
11789          * there's an extra 1 line difference. So we need to add two instead of
11790          * one to the value.
11791          *
11792          * On VLV/CHV DSI the scanline counter would appear to increment
11793          * approx. 1/3 of a scanline before start of vblank. Unfortunately
11794          * that means we can't tell whether we're in vblank or not while
11795          * we're on that particular line. We must still set scanline_offset
11796          * to 1 so that the vblank timestamps come out correct when we query
11797          * the scanline counter from within the vblank interrupt handler.
11798          * However if queried just before the start of vblank we'll get an
11799          * answer that's slightly in the future.
11800          */
11801         if (IS_GEN2(dev_priv)) {
11802                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11803                 int vtotal;
11804
11805                 vtotal = adjusted_mode->crtc_vtotal;
11806                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11807                         vtotal /= 2;
11808
11809                 crtc->scanline_offset = vtotal - 1;
11810         } else if (HAS_DDI(dev_priv) &&
11811                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11812                 crtc->scanline_offset = 2;
11813         } else
11814                 crtc->scanline_offset = 1;
11815 }
11816
11817 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11818 {
11819         struct drm_device *dev = state->dev;
11820         struct drm_i915_private *dev_priv = to_i915(dev);
11821         struct drm_crtc *crtc;
11822         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11823         int i;
11824
11825         if (!dev_priv->display.crtc_compute_clock)
11826                 return;
11827
11828         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11829                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11830                 struct intel_shared_dpll *old_dpll =
11831                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
11832
11833                 if (!needs_modeset(new_crtc_state))
11834                         continue;
11835
11836                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11837
11838                 if (!old_dpll)
11839                         continue;
11840
11841                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11842         }
11843 }
11844
11845 /*
11846  * This implements the workaround described in the "notes" section of the mode
11847  * set sequence documentation. When going from no pipes or single pipe to
11848  * multiple pipes, and planes are enabled after the pipe, we need to wait at
11849  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11850  */
11851 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11852 {
11853         struct drm_crtc_state *crtc_state;
11854         struct intel_crtc *intel_crtc;
11855         struct drm_crtc *crtc;
11856         struct intel_crtc_state *first_crtc_state = NULL;
11857         struct intel_crtc_state *other_crtc_state = NULL;
11858         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11859         int i;
11860
11861         /* look at all crtc's that are going to be enabled in during modeset */
11862         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11863                 intel_crtc = to_intel_crtc(crtc);
11864
11865                 if (!crtc_state->active || !needs_modeset(crtc_state))
11866                         continue;
11867
11868                 if (first_crtc_state) {
11869                         other_crtc_state = to_intel_crtc_state(crtc_state);
11870                         break;
11871                 } else {
11872                         first_crtc_state = to_intel_crtc_state(crtc_state);
11873                         first_pipe = intel_crtc->pipe;
11874                 }
11875         }
11876
11877         /* No workaround needed? */
11878         if (!first_crtc_state)
11879                 return 0;
11880
11881         /* w/a possibly needed, check how many crtc's are already enabled. */
11882         for_each_intel_crtc(state->dev, intel_crtc) {
11883                 struct intel_crtc_state *pipe_config;
11884
11885                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11886                 if (IS_ERR(pipe_config))
11887                         return PTR_ERR(pipe_config);
11888
11889                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11890
11891                 if (!pipe_config->base.active ||
11892                     needs_modeset(&pipe_config->base))
11893                         continue;
11894
11895                 /* 2 or more enabled crtcs means no need for w/a */
11896                 if (enabled_pipe != INVALID_PIPE)
11897                         return 0;
11898
11899                 enabled_pipe = intel_crtc->pipe;
11900         }
11901
11902         if (enabled_pipe != INVALID_PIPE)
11903                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11904         else if (other_crtc_state)
11905                 other_crtc_state->hsw_workaround_pipe = first_pipe;
11906
11907         return 0;
11908 }
11909
11910 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11911 {
11912         struct drm_crtc *crtc;
11913
11914         /* Add all pipes to the state */
11915         for_each_crtc(state->dev, crtc) {
11916                 struct drm_crtc_state *crtc_state;
11917
11918                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11919                 if (IS_ERR(crtc_state))
11920                         return PTR_ERR(crtc_state);
11921         }
11922
11923         return 0;
11924 }
11925
11926 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11927 {
11928         struct drm_crtc *crtc;
11929
11930         /*
11931          * Add all pipes to the state, and force
11932          * a modeset on all the active ones.
11933          */
11934         for_each_crtc(state->dev, crtc) {
11935                 struct drm_crtc_state *crtc_state;
11936                 int ret;
11937
11938                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11939                 if (IS_ERR(crtc_state))
11940                         return PTR_ERR(crtc_state);
11941
11942                 if (!crtc_state->active || needs_modeset(crtc_state))
11943                         continue;
11944
11945                 crtc_state->mode_changed = true;
11946
11947                 ret = drm_atomic_add_affected_connectors(state, crtc);
11948                 if (ret)
11949                         return ret;
11950
11951                 ret = drm_atomic_add_affected_planes(state, crtc);
11952                 if (ret)
11953                         return ret;
11954         }
11955
11956         return 0;
11957 }
11958
11959 static int intel_modeset_checks(struct drm_atomic_state *state)
11960 {
11961         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11962         struct drm_i915_private *dev_priv = to_i915(state->dev);
11963         struct drm_crtc *crtc;
11964         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11965         int ret = 0, i;
11966
11967         if (!check_digital_port_conflicts(state)) {
11968                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11969                 return -EINVAL;
11970         }
11971
11972         intel_state->modeset = true;
11973         intel_state->active_crtcs = dev_priv->active_crtcs;
11974         intel_state->cdclk.logical = dev_priv->cdclk.logical;
11975         intel_state->cdclk.actual = dev_priv->cdclk.actual;
11976
11977         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11978                 if (new_crtc_state->active)
11979                         intel_state->active_crtcs |= 1 << i;
11980                 else
11981                         intel_state->active_crtcs &= ~(1 << i);
11982
11983                 if (old_crtc_state->active != new_crtc_state->active)
11984                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11985         }
11986
11987         /*
11988          * See if the config requires any additional preparation, e.g.
11989          * to adjust global state with pipes off.  We need to do this
11990          * here so we can get the modeset_pipe updated config for the new
11991          * mode set on this crtc.  For other crtcs we need to use the
11992          * adjusted_mode bits in the crtc directly.
11993          */
11994         if (dev_priv->display.modeset_calc_cdclk) {
11995                 ret = dev_priv->display.modeset_calc_cdclk(state);
11996                 if (ret < 0)
11997                         return ret;
11998
11999                 /*
12000                  * Writes to dev_priv->cdclk.logical must protected by
12001                  * holding all the crtc locks, even if we don't end up
12002                  * touching the hardware
12003                  */
12004                 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
12005                                         &intel_state->cdclk.logical)) {
12006                         ret = intel_lock_all_pipes(state);
12007                         if (ret < 0)
12008                                 return ret;
12009                 }
12010
12011                 /* All pipes must be switched off while we change the cdclk. */
12012                 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
12013                                               &intel_state->cdclk.actual)) {
12014                         ret = intel_modeset_all_pipes(state);
12015                         if (ret < 0)
12016                                 return ret;
12017                 }
12018
12019                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12020                               intel_state->cdclk.logical.cdclk,
12021                               intel_state->cdclk.actual.cdclk);
12022                 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
12023                               intel_state->cdclk.logical.voltage_level,
12024                               intel_state->cdclk.actual.voltage_level);
12025         } else {
12026                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12027         }
12028
12029         intel_modeset_clear_plls(state);
12030
12031         if (IS_HASWELL(dev_priv))
12032                 return haswell_mode_set_planes_workaround(state);
12033
12034         return 0;
12035 }
12036
12037 /*
12038  * Handle calculation of various watermark data at the end of the atomic check
12039  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12040  * handlers to ensure that all derived state has been updated.
12041  */
12042 static int calc_watermark_data(struct drm_atomic_state *state)
12043 {
12044         struct drm_device *dev = state->dev;
12045         struct drm_i915_private *dev_priv = to_i915(dev);
12046
12047         /* Is there platform-specific watermark information to calculate? */
12048         if (dev_priv->display.compute_global_watermarks)
12049                 return dev_priv->display.compute_global_watermarks(state);
12050
12051         return 0;
12052 }
12053
12054 /**
12055  * intel_atomic_check - validate state object
12056  * @dev: drm device
12057  * @state: state to validate
12058  */
12059 static int intel_atomic_check(struct drm_device *dev,
12060                               struct drm_atomic_state *state)
12061 {
12062         struct drm_i915_private *dev_priv = to_i915(dev);
12063         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12064         struct drm_crtc *crtc;
12065         struct drm_crtc_state *old_crtc_state, *crtc_state;
12066         int ret, i;
12067         bool any_ms = false;
12068
12069         ret = drm_atomic_helper_check_modeset(dev, state);
12070         if (ret)
12071                 return ret;
12072
12073         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12074                 struct intel_crtc_state *pipe_config =
12075                         to_intel_crtc_state(crtc_state);
12076
12077                 /* Catch I915_MODE_FLAG_INHERITED */
12078                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12079                         crtc_state->mode_changed = true;
12080
12081                 if (!needs_modeset(crtc_state))
12082                         continue;
12083
12084                 if (!crtc_state->enable) {
12085                         any_ms = true;
12086                         continue;
12087                 }
12088
12089                 /* FIXME: For only active_changed we shouldn't need to do any
12090                  * state recomputation at all. */
12091
12092                 ret = drm_atomic_add_affected_connectors(state, crtc);
12093                 if (ret)
12094                         return ret;
12095
12096                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12097                 if (ret) {
12098                         intel_dump_pipe_config(to_intel_crtc(crtc),
12099                                                pipe_config, "[failed]");
12100                         return ret;
12101                 }
12102
12103                 if (i915_modparams.fastboot &&
12104                     intel_pipe_config_compare(dev_priv,
12105                                         to_intel_crtc_state(old_crtc_state),
12106                                         pipe_config, true)) {
12107                         crtc_state->mode_changed = false;
12108                         pipe_config->update_pipe = true;
12109                 }
12110
12111                 if (needs_modeset(crtc_state))
12112                         any_ms = true;
12113
12114                 ret = drm_atomic_add_affected_planes(state, crtc);
12115                 if (ret)
12116                         return ret;
12117
12118                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12119                                        needs_modeset(crtc_state) ?
12120                                        "[modeset]" : "[fastset]");
12121         }
12122
12123         if (any_ms) {
12124                 ret = intel_modeset_checks(state);
12125
12126                 if (ret)
12127                         return ret;
12128         } else {
12129                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12130         }
12131
12132         ret = drm_atomic_helper_check_planes(dev, state);
12133         if (ret)
12134                 return ret;
12135
12136         intel_fbc_choose_crtc(dev_priv, state);
12137         return calc_watermark_data(state);
12138 }
12139
12140 static int intel_atomic_prepare_commit(struct drm_device *dev,
12141                                        struct drm_atomic_state *state)
12142 {
12143         return drm_atomic_helper_prepare_planes(dev, state);
12144 }
12145
12146 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12147 {
12148         struct drm_device *dev = crtc->base.dev;
12149
12150         if (!dev->max_vblank_count)
12151                 return drm_crtc_accurate_vblank_count(&crtc->base);
12152
12153         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12154 }
12155
12156 static void intel_update_crtc(struct drm_crtc *crtc,
12157                               struct drm_atomic_state *state,
12158                               struct drm_crtc_state *old_crtc_state,
12159                               struct drm_crtc_state *new_crtc_state)
12160 {
12161         struct drm_device *dev = crtc->dev;
12162         struct drm_i915_private *dev_priv = to_i915(dev);
12163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12164         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12165         bool modeset = needs_modeset(new_crtc_state);
12166
12167         if (modeset) {
12168                 update_scanline_offset(intel_crtc);
12169                 dev_priv->display.crtc_enable(pipe_config, state);
12170         } else {
12171                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12172                                        pipe_config);
12173         }
12174
12175         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12176                 intel_fbc_enable(
12177                     intel_crtc, pipe_config,
12178                     to_intel_plane_state(crtc->primary->state));
12179         }
12180
12181         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12182 }
12183
12184 static void intel_update_crtcs(struct drm_atomic_state *state)
12185 {
12186         struct drm_crtc *crtc;
12187         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12188         int i;
12189
12190         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12191                 if (!new_crtc_state->active)
12192                         continue;
12193
12194                 intel_update_crtc(crtc, state, old_crtc_state,
12195                                   new_crtc_state);
12196         }
12197 }
12198
12199 static void skl_update_crtcs(struct drm_atomic_state *state)
12200 {
12201         struct drm_i915_private *dev_priv = to_i915(state->dev);
12202         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12203         struct drm_crtc *crtc;
12204         struct intel_crtc *intel_crtc;
12205         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12206         struct intel_crtc_state *cstate;
12207         unsigned int updated = 0;
12208         bool progress;
12209         enum pipe pipe;
12210         int i;
12211
12212         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12213
12214         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12215                 /* ignore allocations for crtc's that have been turned off. */
12216                 if (new_crtc_state->active)
12217                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12218
12219         /*
12220          * Whenever the number of active pipes changes, we need to make sure we
12221          * update the pipes in the right order so that their ddb allocations
12222          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12223          * cause pipe underruns and other bad stuff.
12224          */
12225         do {
12226                 progress = false;
12227
12228                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12229                         bool vbl_wait = false;
12230                         unsigned int cmask = drm_crtc_mask(crtc);
12231
12232                         intel_crtc = to_intel_crtc(crtc);
12233                         cstate = to_intel_crtc_state(new_crtc_state);
12234                         pipe = intel_crtc->pipe;
12235
12236                         if (updated & cmask || !cstate->base.active)
12237                                 continue;
12238
12239                         if (skl_ddb_allocation_overlaps(dev_priv,
12240                                                         entries,
12241                                                         &cstate->wm.skl.ddb,
12242                                                         i))
12243                                 continue;
12244
12245                         updated |= cmask;
12246                         entries[i] = &cstate->wm.skl.ddb;
12247
12248                         /*
12249                          * If this is an already active pipe, it's DDB changed,
12250                          * and this isn't the last pipe that needs updating
12251                          * then we need to wait for a vblank to pass for the
12252                          * new ddb allocation to take effect.
12253                          */
12254                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12255                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12256                             !new_crtc_state->active_changed &&
12257                             intel_state->wm_results.dirty_pipes != updated)
12258                                 vbl_wait = true;
12259
12260                         intel_update_crtc(crtc, state, old_crtc_state,
12261                                           new_crtc_state);
12262
12263                         if (vbl_wait)
12264                                 intel_wait_for_vblank(dev_priv, pipe);
12265
12266                         progress = true;
12267                 }
12268         } while (progress);
12269 }
12270
12271 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12272 {
12273         struct intel_atomic_state *state, *next;
12274         struct llist_node *freed;
12275
12276         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12277         llist_for_each_entry_safe(state, next, freed, freed)
12278                 drm_atomic_state_put(&state->base);
12279 }
12280
12281 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12282 {
12283         struct drm_i915_private *dev_priv =
12284                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12285
12286         intel_atomic_helper_free_state(dev_priv);
12287 }
12288
12289 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12290 {
12291         struct wait_queue_entry wait_fence, wait_reset;
12292         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12293
12294         init_wait_entry(&wait_fence, 0);
12295         init_wait_entry(&wait_reset, 0);
12296         for (;;) {
12297                 prepare_to_wait(&intel_state->commit_ready.wait,
12298                                 &wait_fence, TASK_UNINTERRUPTIBLE);
12299                 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12300                                 &wait_reset, TASK_UNINTERRUPTIBLE);
12301
12302
12303                 if (i915_sw_fence_done(&intel_state->commit_ready)
12304                     || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12305                         break;
12306
12307                 schedule();
12308         }
12309         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12310         finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12311 }
12312
12313 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12314 {
12315         struct drm_device *dev = state->dev;
12316         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12317         struct drm_i915_private *dev_priv = to_i915(dev);
12318         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12319         struct drm_crtc *crtc;
12320         struct intel_crtc_state *intel_cstate;
12321         u64 put_domains[I915_MAX_PIPES] = {};
12322         int i;
12323
12324         intel_atomic_commit_fence_wait(intel_state);
12325
12326         drm_atomic_helper_wait_for_dependencies(state);
12327
12328         if (intel_state->modeset)
12329                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12330
12331         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12332                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12333
12334                 if (needs_modeset(new_crtc_state) ||
12335                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12336
12337                         put_domains[to_intel_crtc(crtc)->pipe] =
12338                                 modeset_get_crtc_power_domains(crtc,
12339                                         to_intel_crtc_state(new_crtc_state));
12340                 }
12341
12342                 if (!needs_modeset(new_crtc_state))
12343                         continue;
12344
12345                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12346                                        to_intel_crtc_state(new_crtc_state));
12347
12348                 if (old_crtc_state->active) {
12349                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12350                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12351                         intel_crtc->active = false;
12352                         intel_fbc_disable(intel_crtc);
12353                         intel_disable_shared_dpll(intel_crtc);
12354
12355                         /*
12356                          * Underruns don't always raise
12357                          * interrupts, so check manually.
12358                          */
12359                         intel_check_cpu_fifo_underruns(dev_priv);
12360                         intel_check_pch_fifo_underruns(dev_priv);
12361
12362                         if (!new_crtc_state->active) {
12363                                 /*
12364                                  * Make sure we don't call initial_watermarks
12365                                  * for ILK-style watermark updates.
12366                                  *
12367                                  * No clue what this is supposed to achieve.
12368                                  */
12369                                 if (INTEL_GEN(dev_priv) >= 9)
12370                                         dev_priv->display.initial_watermarks(intel_state,
12371                                                                              to_intel_crtc_state(new_crtc_state));
12372                         }
12373                 }
12374         }
12375
12376         /* Only after disabling all output pipelines that will be changed can we
12377          * update the the output configuration. */
12378         intel_modeset_update_crtc_state(state);
12379
12380         if (intel_state->modeset) {
12381                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12382
12383                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12384
12385                 /*
12386                  * SKL workaround: bspec recommends we disable the SAGV when we
12387                  * have more then one pipe enabled
12388                  */
12389                 if (!intel_can_enable_sagv(state))
12390                         intel_disable_sagv(dev_priv);
12391
12392                 intel_modeset_verify_disabled(dev, state);
12393         }
12394
12395         /* Complete the events for pipes that have now been disabled */
12396         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12397                 bool modeset = needs_modeset(new_crtc_state);
12398
12399                 /* Complete events for now disable pipes here. */
12400                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12401                         spin_lock_irq(&dev->event_lock);
12402                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12403                         spin_unlock_irq(&dev->event_lock);
12404
12405                         new_crtc_state->event = NULL;
12406                 }
12407         }
12408
12409         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12410         dev_priv->display.update_crtcs(state);
12411
12412         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12413          * already, but still need the state for the delayed optimization. To
12414          * fix this:
12415          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12416          * - schedule that vblank worker _before_ calling hw_done
12417          * - at the start of commit_tail, cancel it _synchrously
12418          * - switch over to the vblank wait helper in the core after that since
12419          *   we don't need out special handling any more.
12420          */
12421         drm_atomic_helper_wait_for_flip_done(dev, state);
12422
12423         /*
12424          * Now that the vblank has passed, we can go ahead and program the
12425          * optimal watermarks on platforms that need two-step watermark
12426          * programming.
12427          *
12428          * TODO: Move this (and other cleanup) to an async worker eventually.
12429          */
12430         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12431                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12432
12433                 if (dev_priv->display.optimize_watermarks)
12434                         dev_priv->display.optimize_watermarks(intel_state,
12435                                                               intel_cstate);
12436         }
12437
12438         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12439                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12440
12441                 if (put_domains[i])
12442                         modeset_put_power_domains(dev_priv, put_domains[i]);
12443
12444                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12445         }
12446
12447         if (intel_state->modeset && intel_can_enable_sagv(state))
12448                 intel_enable_sagv(dev_priv);
12449
12450         drm_atomic_helper_commit_hw_done(state);
12451
12452         if (intel_state->modeset) {
12453                 /* As one of the primary mmio accessors, KMS has a high
12454                  * likelihood of triggering bugs in unclaimed access. After we
12455                  * finish modesetting, see if an error has been flagged, and if
12456                  * so enable debugging for the next modeset - and hope we catch
12457                  * the culprit.
12458                  */
12459                 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12460                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12461         }
12462
12463         drm_atomic_helper_cleanup_planes(dev, state);
12464
12465         drm_atomic_helper_commit_cleanup_done(state);
12466
12467         drm_atomic_state_put(state);
12468
12469         intel_atomic_helper_free_state(dev_priv);
12470 }
12471
12472 static void intel_atomic_commit_work(struct work_struct *work)
12473 {
12474         struct drm_atomic_state *state =
12475                 container_of(work, struct drm_atomic_state, commit_work);
12476
12477         intel_atomic_commit_tail(state);
12478 }
12479
12480 static int __i915_sw_fence_call
12481 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12482                           enum i915_sw_fence_notify notify)
12483 {
12484         struct intel_atomic_state *state =
12485                 container_of(fence, struct intel_atomic_state, commit_ready);
12486
12487         switch (notify) {
12488         case FENCE_COMPLETE:
12489                 /* we do blocking waits in the worker, nothing to do here */
12490                 break;
12491         case FENCE_FREE:
12492                 {
12493                         struct intel_atomic_helper *helper =
12494                                 &to_i915(state->base.dev)->atomic_helper;
12495
12496                         if (llist_add(&state->freed, &helper->free_list))
12497                                 schedule_work(&helper->free_work);
12498                         break;
12499                 }
12500         }
12501
12502         return NOTIFY_DONE;
12503 }
12504
12505 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12506 {
12507         struct drm_plane_state *old_plane_state, *new_plane_state;
12508         struct drm_plane *plane;
12509         int i;
12510
12511         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12512                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12513                                   intel_fb_obj(new_plane_state->fb),
12514                                   to_intel_plane(plane)->frontbuffer_bit);
12515 }
12516
12517 /**
12518  * intel_atomic_commit - commit validated state object
12519  * @dev: DRM device
12520  * @state: the top-level driver state object
12521  * @nonblock: nonblocking commit
12522  *
12523  * This function commits a top-level state object that has been validated
12524  * with drm_atomic_helper_check().
12525  *
12526  * RETURNS
12527  * Zero for success or -errno.
12528  */
12529 static int intel_atomic_commit(struct drm_device *dev,
12530                                struct drm_atomic_state *state,
12531                                bool nonblock)
12532 {
12533         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12534         struct drm_i915_private *dev_priv = to_i915(dev);
12535         int ret = 0;
12536
12537         drm_atomic_state_get(state);
12538         i915_sw_fence_init(&intel_state->commit_ready,
12539                            intel_atomic_commit_ready);
12540
12541         /*
12542          * The intel_legacy_cursor_update() fast path takes care
12543          * of avoiding the vblank waits for simple cursor
12544          * movement and flips. For cursor on/off and size changes,
12545          * we want to perform the vblank waits so that watermark
12546          * updates happen during the correct frames. Gen9+ have
12547          * double buffered watermarks and so shouldn't need this.
12548          *
12549          * Unset state->legacy_cursor_update before the call to
12550          * drm_atomic_helper_setup_commit() because otherwise
12551          * drm_atomic_helper_wait_for_flip_done() is a noop and
12552          * we get FIFO underruns because we didn't wait
12553          * for vblank.
12554          *
12555          * FIXME doing watermarks and fb cleanup from a vblank worker
12556          * (assuming we had any) would solve these problems.
12557          */
12558         if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12559                 struct intel_crtc_state *new_crtc_state;
12560                 struct intel_crtc *crtc;
12561                 int i;
12562
12563                 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12564                         if (new_crtc_state->wm.need_postvbl_update ||
12565                             new_crtc_state->update_wm_post)
12566                                 state->legacy_cursor_update = false;
12567         }
12568
12569         ret = intel_atomic_prepare_commit(dev, state);
12570         if (ret) {
12571                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12572                 i915_sw_fence_commit(&intel_state->commit_ready);
12573                 return ret;
12574         }
12575
12576         ret = drm_atomic_helper_setup_commit(state, nonblock);
12577         if (!ret)
12578                 ret = drm_atomic_helper_swap_state(state, true);
12579
12580         if (ret) {
12581                 i915_sw_fence_commit(&intel_state->commit_ready);
12582
12583                 drm_atomic_helper_cleanup_planes(dev, state);
12584                 return ret;
12585         }
12586         dev_priv->wm.distrust_bios_wm = false;
12587         intel_shared_dpll_swap_state(state);
12588         intel_atomic_track_fbs(state);
12589
12590         if (intel_state->modeset) {
12591                 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12592                        sizeof(intel_state->min_cdclk));
12593                 memcpy(dev_priv->min_voltage_level,
12594                        intel_state->min_voltage_level,
12595                        sizeof(intel_state->min_voltage_level));
12596                 dev_priv->active_crtcs = intel_state->active_crtcs;
12597                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12598                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12599         }
12600
12601         drm_atomic_state_get(state);
12602         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12603
12604         i915_sw_fence_commit(&intel_state->commit_ready);
12605         if (nonblock)
12606                 queue_work(system_unbound_wq, &state->commit_work);
12607         else
12608                 intel_atomic_commit_tail(state);
12609
12610
12611         return 0;
12612 }
12613
12614 static const struct drm_crtc_funcs intel_crtc_funcs = {
12615         .gamma_set = drm_atomic_helper_legacy_gamma_set,
12616         .set_config = drm_atomic_helper_set_config,
12617         .destroy = intel_crtc_destroy,
12618         .page_flip = drm_atomic_helper_page_flip,
12619         .atomic_duplicate_state = intel_crtc_duplicate_state,
12620         .atomic_destroy_state = intel_crtc_destroy_state,
12621         .set_crc_source = intel_crtc_set_crc_source,
12622 };
12623
12624 struct wait_rps_boost {
12625         struct wait_queue_entry wait;
12626
12627         struct drm_crtc *crtc;
12628         struct drm_i915_gem_request *request;
12629 };
12630
12631 static int do_rps_boost(struct wait_queue_entry *_wait,
12632                         unsigned mode, int sync, void *key)
12633 {
12634         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12635         struct drm_i915_gem_request *rq = wait->request;
12636
12637         gen6_rps_boost(rq, NULL);
12638         i915_gem_request_put(rq);
12639
12640         drm_crtc_vblank_put(wait->crtc);
12641
12642         list_del(&wait->wait.entry);
12643         kfree(wait);
12644         return 1;
12645 }
12646
12647 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12648                                        struct dma_fence *fence)
12649 {
12650         struct wait_rps_boost *wait;
12651
12652         if (!dma_fence_is_i915(fence))
12653                 return;
12654
12655         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12656                 return;
12657
12658         if (drm_crtc_vblank_get(crtc))
12659                 return;
12660
12661         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12662         if (!wait) {
12663                 drm_crtc_vblank_put(crtc);
12664                 return;
12665         }
12666
12667         wait->request = to_request(dma_fence_get(fence));
12668         wait->crtc = crtc;
12669
12670         wait->wait.func = do_rps_boost;
12671         wait->wait.flags = 0;
12672
12673         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12674 }
12675
12676 /**
12677  * intel_prepare_plane_fb - Prepare fb for usage on plane
12678  * @plane: drm plane to prepare for
12679  * @fb: framebuffer to prepare for presentation
12680  *
12681  * Prepares a framebuffer for usage on a display plane.  Generally this
12682  * involves pinning the underlying object and updating the frontbuffer tracking
12683  * bits.  Some older platforms need special physical address handling for
12684  * cursor planes.
12685  *
12686  * Must be called with struct_mutex held.
12687  *
12688  * Returns 0 on success, negative error code on failure.
12689  */
12690 int
12691 intel_prepare_plane_fb(struct drm_plane *plane,
12692                        struct drm_plane_state *new_state)
12693 {
12694         struct intel_atomic_state *intel_state =
12695                 to_intel_atomic_state(new_state->state);
12696         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12697         struct drm_framebuffer *fb = new_state->fb;
12698         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12699         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12700         int ret;
12701
12702         if (old_obj) {
12703                 struct drm_crtc_state *crtc_state =
12704                         drm_atomic_get_existing_crtc_state(new_state->state,
12705                                                            plane->state->crtc);
12706
12707                 /* Big Hammer, we also need to ensure that any pending
12708                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12709                  * current scanout is retired before unpinning the old
12710                  * framebuffer. Note that we rely on userspace rendering
12711                  * into the buffer attached to the pipe they are waiting
12712                  * on. If not, userspace generates a GPU hang with IPEHR
12713                  * point to the MI_WAIT_FOR_EVENT.
12714                  *
12715                  * This should only fail upon a hung GPU, in which case we
12716                  * can safely continue.
12717                  */
12718                 if (needs_modeset(crtc_state)) {
12719                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12720                                                               old_obj->resv, NULL,
12721                                                               false, 0,
12722                                                               GFP_KERNEL);
12723                         if (ret < 0)
12724                                 return ret;
12725                 }
12726         }
12727
12728         if (new_state->fence) { /* explicit fencing */
12729                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12730                                                     new_state->fence,
12731                                                     I915_FENCE_TIMEOUT,
12732                                                     GFP_KERNEL);
12733                 if (ret < 0)
12734                         return ret;
12735         }
12736
12737         if (!obj)
12738                 return 0;
12739
12740         ret = i915_gem_object_pin_pages(obj);
12741         if (ret)
12742                 return ret;
12743
12744         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12745         if (ret) {
12746                 i915_gem_object_unpin_pages(obj);
12747                 return ret;
12748         }
12749
12750         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12751             INTEL_INFO(dev_priv)->cursor_needs_physical) {
12752                 const int align = intel_cursor_alignment(dev_priv);
12753
12754                 ret = i915_gem_object_attach_phys(obj, align);
12755         } else {
12756                 struct i915_vma *vma;
12757
12758                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12759                 if (!IS_ERR(vma))
12760                         to_intel_plane_state(new_state)->vma = vma;
12761                 else
12762                         ret =  PTR_ERR(vma);
12763         }
12764
12765         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12766
12767         mutex_unlock(&dev_priv->drm.struct_mutex);
12768         i915_gem_object_unpin_pages(obj);
12769         if (ret)
12770                 return ret;
12771
12772         if (!new_state->fence) { /* implicit fencing */
12773                 struct dma_fence *fence;
12774
12775                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12776                                                       obj->resv, NULL,
12777                                                       false, I915_FENCE_TIMEOUT,
12778                                                       GFP_KERNEL);
12779                 if (ret < 0)
12780                         return ret;
12781
12782                 fence = reservation_object_get_excl_rcu(obj->resv);
12783                 if (fence) {
12784                         add_rps_boost_after_vblank(new_state->crtc, fence);
12785                         dma_fence_put(fence);
12786                 }
12787         } else {
12788                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12789         }
12790
12791         return 0;
12792 }
12793
12794 /**
12795  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12796  * @plane: drm plane to clean up for
12797  * @fb: old framebuffer that was on plane
12798  *
12799  * Cleans up a framebuffer that has just been removed from a plane.
12800  *
12801  * Must be called with struct_mutex held.
12802  */
12803 void
12804 intel_cleanup_plane_fb(struct drm_plane *plane,
12805                        struct drm_plane_state *old_state)
12806 {
12807         struct i915_vma *vma;
12808
12809         /* Should only be called after a successful intel_prepare_plane_fb()! */
12810         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12811         if (vma) {
12812                 mutex_lock(&plane->dev->struct_mutex);
12813                 intel_unpin_fb_vma(vma);
12814                 mutex_unlock(&plane->dev->struct_mutex);
12815         }
12816 }
12817
12818 int
12819 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12820 {
12821         struct drm_i915_private *dev_priv;
12822         int max_scale;
12823         int crtc_clock, max_dotclk;
12824
12825         if (!intel_crtc || !crtc_state->base.enable)
12826                 return DRM_PLANE_HELPER_NO_SCALING;
12827
12828         dev_priv = to_i915(intel_crtc->base.dev);
12829
12830         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12831         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12832
12833         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
12834                 max_dotclk *= 2;
12835
12836         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12837                 return DRM_PLANE_HELPER_NO_SCALING;
12838
12839         /*
12840          * skl max scale is lower of:
12841          *    close to 3 but not 3, -1 is for that purpose
12842          *            or
12843          *    cdclk/crtc_clock
12844          */
12845         max_scale = min((1 << 16) * 3 - 1,
12846                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12847
12848         return max_scale;
12849 }
12850
12851 static int
12852 intel_check_primary_plane(struct intel_plane *plane,
12853                           struct intel_crtc_state *crtc_state,
12854                           struct intel_plane_state *state)
12855 {
12856         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12857         struct drm_crtc *crtc = state->base.crtc;
12858         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12859         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12860         bool can_position = false;
12861         int ret;
12862
12863         if (INTEL_GEN(dev_priv) >= 9) {
12864                 /* use scaler when colorkey is not required */
12865                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12866                         min_scale = 1;
12867                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12868                 }
12869                 can_position = true;
12870         }
12871
12872         ret = drm_plane_helper_check_state(&state->base,
12873                                            &state->clip,
12874                                            min_scale, max_scale,
12875                                            can_position, true);
12876         if (ret)
12877                 return ret;
12878
12879         if (!state->base.fb)
12880                 return 0;
12881
12882         if (INTEL_GEN(dev_priv) >= 9) {
12883                 ret = skl_check_plane_surface(state);
12884                 if (ret)
12885                         return ret;
12886
12887                 state->ctl = skl_plane_ctl(crtc_state, state);
12888         } else {
12889                 ret = i9xx_check_plane_surface(state);
12890                 if (ret)
12891                         return ret;
12892
12893                 state->ctl = i9xx_plane_ctl(crtc_state, state);
12894         }
12895
12896         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
12897                 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
12898
12899         return 0;
12900 }
12901
12902 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12903                                     struct drm_crtc_state *old_crtc_state)
12904 {
12905         struct drm_device *dev = crtc->dev;
12906         struct drm_i915_private *dev_priv = to_i915(dev);
12907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12908         struct intel_crtc_state *old_intel_cstate =
12909                 to_intel_crtc_state(old_crtc_state);
12910         struct intel_atomic_state *old_intel_state =
12911                 to_intel_atomic_state(old_crtc_state->state);
12912         struct intel_crtc_state *intel_cstate =
12913                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12914         bool modeset = needs_modeset(&intel_cstate->base);
12915
12916         if (!modeset &&
12917             (intel_cstate->base.color_mgmt_changed ||
12918              intel_cstate->update_pipe)) {
12919                 intel_color_set_csc(&intel_cstate->base);
12920                 intel_color_load_luts(&intel_cstate->base);
12921         }
12922
12923         /* Perform vblank evasion around commit operation */
12924         intel_pipe_update_start(intel_cstate);
12925
12926         if (modeset)
12927                 goto out;
12928
12929         if (intel_cstate->update_pipe)
12930                 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12931         else if (INTEL_GEN(dev_priv) >= 9)
12932                 skl_detach_scalers(intel_crtc);
12933
12934 out:
12935         if (dev_priv->display.atomic_update_watermarks)
12936                 dev_priv->display.atomic_update_watermarks(old_intel_state,
12937                                                            intel_cstate);
12938 }
12939
12940 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12941                                      struct drm_crtc_state *old_crtc_state)
12942 {
12943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12944         struct intel_atomic_state *old_intel_state =
12945                 to_intel_atomic_state(old_crtc_state->state);
12946         struct intel_crtc_state *new_crtc_state =
12947                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12948
12949         intel_pipe_update_end(new_crtc_state);
12950 }
12951
12952 /**
12953  * intel_plane_destroy - destroy a plane
12954  * @plane: plane to destroy
12955  *
12956  * Common destruction function for all types of planes (primary, cursor,
12957  * sprite).
12958  */
12959 void intel_plane_destroy(struct drm_plane *plane)
12960 {
12961         drm_plane_cleanup(plane);
12962         kfree(to_intel_plane(plane));
12963 }
12964
12965 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12966 {
12967         switch (format) {
12968         case DRM_FORMAT_C8:
12969         case DRM_FORMAT_RGB565:
12970         case DRM_FORMAT_XRGB1555:
12971         case DRM_FORMAT_XRGB8888:
12972                 return modifier == DRM_FORMAT_MOD_LINEAR ||
12973                         modifier == I915_FORMAT_MOD_X_TILED;
12974         default:
12975                 return false;
12976         }
12977 }
12978
12979 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
12980 {
12981         switch (format) {
12982         case DRM_FORMAT_C8:
12983         case DRM_FORMAT_RGB565:
12984         case DRM_FORMAT_XRGB8888:
12985         case DRM_FORMAT_XBGR8888:
12986         case DRM_FORMAT_XRGB2101010:
12987         case DRM_FORMAT_XBGR2101010:
12988                 return modifier == DRM_FORMAT_MOD_LINEAR ||
12989                         modifier == I915_FORMAT_MOD_X_TILED;
12990         default:
12991                 return false;
12992         }
12993 }
12994
12995 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
12996 {
12997         switch (format) {
12998         case DRM_FORMAT_XRGB8888:
12999         case DRM_FORMAT_XBGR8888:
13000         case DRM_FORMAT_ARGB8888:
13001         case DRM_FORMAT_ABGR8888:
13002                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13003                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13004                         return true;
13005                 /* fall through */
13006         case DRM_FORMAT_RGB565:
13007         case DRM_FORMAT_XRGB2101010:
13008         case DRM_FORMAT_XBGR2101010:
13009         case DRM_FORMAT_YUYV:
13010         case DRM_FORMAT_YVYU:
13011         case DRM_FORMAT_UYVY:
13012         case DRM_FORMAT_VYUY:
13013                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13014                         return true;
13015                 /* fall through */
13016         case DRM_FORMAT_C8:
13017                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13018                     modifier == I915_FORMAT_MOD_X_TILED ||
13019                     modifier == I915_FORMAT_MOD_Y_TILED)
13020                         return true;
13021                 /* fall through */
13022         default:
13023                 return false;
13024         }
13025 }
13026
13027 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
13028                                                      uint32_t format,
13029                                                      uint64_t modifier)
13030 {
13031         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13032
13033         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13034                 return false;
13035
13036         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13037             modifier != DRM_FORMAT_MOD_LINEAR)
13038                 return false;
13039
13040         if (INTEL_GEN(dev_priv) >= 9)
13041                 return skl_mod_supported(format, modifier);
13042         else if (INTEL_GEN(dev_priv) >= 4)
13043                 return i965_mod_supported(format, modifier);
13044         else
13045                 return i8xx_mod_supported(format, modifier);
13046
13047         unreachable();
13048 }
13049
13050 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
13051                                                     uint32_t format,
13052                                                     uint64_t modifier)
13053 {
13054         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13055                 return false;
13056
13057         return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
13058 }
13059
13060 static struct drm_plane_funcs intel_plane_funcs = {
13061         .update_plane = drm_atomic_helper_update_plane,
13062         .disable_plane = drm_atomic_helper_disable_plane,
13063         .destroy = intel_plane_destroy,
13064         .atomic_get_property = intel_plane_atomic_get_property,
13065         .atomic_set_property = intel_plane_atomic_set_property,
13066         .atomic_duplicate_state = intel_plane_duplicate_state,
13067         .atomic_destroy_state = intel_plane_destroy_state,
13068         .format_mod_supported = intel_primary_plane_format_mod_supported,
13069 };
13070
13071 static int
13072 intel_legacy_cursor_update(struct drm_plane *plane,
13073                            struct drm_crtc *crtc,
13074                            struct drm_framebuffer *fb,
13075                            int crtc_x, int crtc_y,
13076                            unsigned int crtc_w, unsigned int crtc_h,
13077                            uint32_t src_x, uint32_t src_y,
13078                            uint32_t src_w, uint32_t src_h,
13079                            struct drm_modeset_acquire_ctx *ctx)
13080 {
13081         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13082         int ret;
13083         struct drm_plane_state *old_plane_state, *new_plane_state;
13084         struct intel_plane *intel_plane = to_intel_plane(plane);
13085         struct drm_framebuffer *old_fb;
13086         struct drm_crtc_state *crtc_state = crtc->state;
13087         struct i915_vma *old_vma, *vma;
13088
13089         /*
13090          * When crtc is inactive or there is a modeset pending,
13091          * wait for it to complete in the slowpath
13092          */
13093         if (!crtc_state->active || needs_modeset(crtc_state) ||
13094             to_intel_crtc_state(crtc_state)->update_pipe)
13095                 goto slow;
13096
13097         old_plane_state = plane->state;
13098         /*
13099          * Don't do an async update if there is an outstanding commit modifying
13100          * the plane.  This prevents our async update's changes from getting
13101          * overridden by a previous synchronous update's state.
13102          */
13103         if (old_plane_state->commit &&
13104             !try_wait_for_completion(&old_plane_state->commit->hw_done))
13105                 goto slow;
13106
13107         /*
13108          * If any parameters change that may affect watermarks,
13109          * take the slowpath. Only changing fb or position should be
13110          * in the fastpath.
13111          */
13112         if (old_plane_state->crtc != crtc ||
13113             old_plane_state->src_w != src_w ||
13114             old_plane_state->src_h != src_h ||
13115             old_plane_state->crtc_w != crtc_w ||
13116             old_plane_state->crtc_h != crtc_h ||
13117             !old_plane_state->fb != !fb)
13118                 goto slow;
13119
13120         new_plane_state = intel_plane_duplicate_state(plane);
13121         if (!new_plane_state)
13122                 return -ENOMEM;
13123
13124         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13125
13126         new_plane_state->src_x = src_x;
13127         new_plane_state->src_y = src_y;
13128         new_plane_state->src_w = src_w;
13129         new_plane_state->src_h = src_h;
13130         new_plane_state->crtc_x = crtc_x;
13131         new_plane_state->crtc_y = crtc_y;
13132         new_plane_state->crtc_w = crtc_w;
13133         new_plane_state->crtc_h = crtc_h;
13134
13135         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13136                                                   to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13137                                                   to_intel_plane_state(plane->state),
13138                                                   to_intel_plane_state(new_plane_state));
13139         if (ret)
13140                 goto out_free;
13141
13142         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13143         if (ret)
13144                 goto out_free;
13145
13146         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13147                 int align = intel_cursor_alignment(dev_priv);
13148
13149                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13150                 if (ret) {
13151                         DRM_DEBUG_KMS("failed to attach phys object\n");
13152                         goto out_unlock;
13153                 }
13154         } else {
13155                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13156                 if (IS_ERR(vma)) {
13157                         DRM_DEBUG_KMS("failed to pin object\n");
13158
13159                         ret = PTR_ERR(vma);
13160                         goto out_unlock;
13161                 }
13162
13163                 to_intel_plane_state(new_plane_state)->vma = vma;
13164         }
13165
13166         old_fb = old_plane_state->fb;
13167
13168         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13169                           intel_plane->frontbuffer_bit);
13170
13171         /* Swap plane state */
13172         plane->state = new_plane_state;
13173
13174         if (plane->state->visible) {
13175                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13176                 intel_plane->update_plane(intel_plane,
13177                                           to_intel_crtc_state(crtc->state),
13178                                           to_intel_plane_state(plane->state));
13179         } else {
13180                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13181                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13182         }
13183
13184         old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13185         if (old_vma)
13186                 intel_unpin_fb_vma(old_vma);
13187
13188 out_unlock:
13189         mutex_unlock(&dev_priv->drm.struct_mutex);
13190 out_free:
13191         if (ret)
13192                 intel_plane_destroy_state(plane, new_plane_state);
13193         else
13194                 intel_plane_destroy_state(plane, old_plane_state);
13195         return ret;
13196
13197 slow:
13198         return drm_atomic_helper_update_plane(plane, crtc, fb,
13199                                               crtc_x, crtc_y, crtc_w, crtc_h,
13200                                               src_x, src_y, src_w, src_h, ctx);
13201 }
13202
13203 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13204         .update_plane = intel_legacy_cursor_update,
13205         .disable_plane = drm_atomic_helper_disable_plane,
13206         .destroy = intel_plane_destroy,
13207         .atomic_get_property = intel_plane_atomic_get_property,
13208         .atomic_set_property = intel_plane_atomic_set_property,
13209         .atomic_duplicate_state = intel_plane_duplicate_state,
13210         .atomic_destroy_state = intel_plane_destroy_state,
13211         .format_mod_supported = intel_cursor_plane_format_mod_supported,
13212 };
13213
13214 static struct intel_plane *
13215 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13216 {
13217         struct intel_plane *primary = NULL;
13218         struct intel_plane_state *state = NULL;
13219         const uint32_t *intel_primary_formats;
13220         unsigned int supported_rotations;
13221         unsigned int num_formats;
13222         const uint64_t *modifiers;
13223         int ret;
13224
13225         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13226         if (!primary) {
13227                 ret = -ENOMEM;
13228                 goto fail;
13229         }
13230
13231         state = intel_create_plane_state(&primary->base);
13232         if (!state) {
13233                 ret = -ENOMEM;
13234                 goto fail;
13235         }
13236
13237         primary->base.state = &state->base;
13238
13239         primary->can_scale = false;
13240         primary->max_downscale = 1;
13241         if (INTEL_GEN(dev_priv) >= 9) {
13242                 primary->can_scale = true;
13243                 state->scaler_id = -1;
13244         }
13245         primary->pipe = pipe;
13246         /*
13247          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13248          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13249          */
13250         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13251                 primary->plane = (enum plane) !pipe;
13252         else
13253                 primary->plane = (enum plane) pipe;
13254         primary->id = PLANE_PRIMARY;
13255         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13256         primary->check_plane = intel_check_primary_plane;
13257
13258         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13259                 intel_primary_formats = skl_primary_formats;
13260                 num_formats = ARRAY_SIZE(skl_primary_formats);
13261                 modifiers = skl_format_modifiers_ccs;
13262
13263                 primary->update_plane = skl_update_plane;
13264                 primary->disable_plane = skl_disable_plane;
13265         } else if (INTEL_GEN(dev_priv) >= 9) {
13266                 intel_primary_formats = skl_primary_formats;
13267                 num_formats = ARRAY_SIZE(skl_primary_formats);
13268                 if (pipe < PIPE_C)
13269                         modifiers = skl_format_modifiers_ccs;
13270                 else
13271                         modifiers = skl_format_modifiers_noccs;
13272
13273                 primary->update_plane = skl_update_plane;
13274                 primary->disable_plane = skl_disable_plane;
13275         } else if (INTEL_GEN(dev_priv) >= 4) {
13276                 intel_primary_formats = i965_primary_formats;
13277                 num_formats = ARRAY_SIZE(i965_primary_formats);
13278                 modifiers = i9xx_format_modifiers;
13279
13280                 primary->update_plane = i9xx_update_primary_plane;
13281                 primary->disable_plane = i9xx_disable_primary_plane;
13282         } else {
13283                 intel_primary_formats = i8xx_primary_formats;
13284                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13285                 modifiers = i9xx_format_modifiers;
13286
13287                 primary->update_plane = i9xx_update_primary_plane;
13288                 primary->disable_plane = i9xx_disable_primary_plane;
13289         }
13290
13291         if (INTEL_GEN(dev_priv) >= 9)
13292                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13293                                                0, &intel_plane_funcs,
13294                                                intel_primary_formats, num_formats,
13295                                                modifiers,
13296                                                DRM_PLANE_TYPE_PRIMARY,
13297                                                "plane 1%c", pipe_name(pipe));
13298         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13299                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13300                                                0, &intel_plane_funcs,
13301                                                intel_primary_formats, num_formats,
13302                                                modifiers,
13303                                                DRM_PLANE_TYPE_PRIMARY,
13304                                                "primary %c", pipe_name(pipe));
13305         else
13306                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13307                                                0, &intel_plane_funcs,
13308                                                intel_primary_formats, num_formats,
13309                                                modifiers,
13310                                                DRM_PLANE_TYPE_PRIMARY,
13311                                                "plane %c", plane_name(primary->plane));
13312         if (ret)
13313                 goto fail;
13314
13315         if (INTEL_GEN(dev_priv) >= 9) {
13316                 supported_rotations =
13317                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13318                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13319         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13320                 supported_rotations =
13321                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13322                         DRM_MODE_REFLECT_X;
13323         } else if (INTEL_GEN(dev_priv) >= 4) {
13324                 supported_rotations =
13325                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13326         } else {
13327                 supported_rotations = DRM_MODE_ROTATE_0;
13328         }
13329
13330         if (INTEL_GEN(dev_priv) >= 4)
13331                 drm_plane_create_rotation_property(&primary->base,
13332                                                    DRM_MODE_ROTATE_0,
13333                                                    supported_rotations);
13334
13335         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13336
13337         return primary;
13338
13339 fail:
13340         kfree(state);
13341         kfree(primary);
13342
13343         return ERR_PTR(ret);
13344 }
13345
13346 static struct intel_plane *
13347 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13348                           enum pipe pipe)
13349 {
13350         struct intel_plane *cursor = NULL;
13351         struct intel_plane_state *state = NULL;
13352         int ret;
13353
13354         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13355         if (!cursor) {
13356                 ret = -ENOMEM;
13357                 goto fail;
13358         }
13359
13360         state = intel_create_plane_state(&cursor->base);
13361         if (!state) {
13362                 ret = -ENOMEM;
13363                 goto fail;
13364         }
13365
13366         cursor->base.state = &state->base;
13367
13368         cursor->can_scale = false;
13369         cursor->max_downscale = 1;
13370         cursor->pipe = pipe;
13371         cursor->plane = pipe;
13372         cursor->id = PLANE_CURSOR;
13373         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13374
13375         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13376                 cursor->update_plane = i845_update_cursor;
13377                 cursor->disable_plane = i845_disable_cursor;
13378                 cursor->check_plane = i845_check_cursor;
13379         } else {
13380                 cursor->update_plane = i9xx_update_cursor;
13381                 cursor->disable_plane = i9xx_disable_cursor;
13382                 cursor->check_plane = i9xx_check_cursor;
13383         }
13384
13385         cursor->cursor.base = ~0;
13386         cursor->cursor.cntl = ~0;
13387
13388         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13389                 cursor->cursor.size = ~0;
13390
13391         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13392                                        0, &intel_cursor_plane_funcs,
13393                                        intel_cursor_formats,
13394                                        ARRAY_SIZE(intel_cursor_formats),
13395                                        cursor_format_modifiers,
13396                                        DRM_PLANE_TYPE_CURSOR,
13397                                        "cursor %c", pipe_name(pipe));
13398         if (ret)
13399                 goto fail;
13400
13401         if (INTEL_GEN(dev_priv) >= 4)
13402                 drm_plane_create_rotation_property(&cursor->base,
13403                                                    DRM_MODE_ROTATE_0,
13404                                                    DRM_MODE_ROTATE_0 |
13405                                                    DRM_MODE_ROTATE_180);
13406
13407         if (INTEL_GEN(dev_priv) >= 9)
13408                 state->scaler_id = -1;
13409
13410         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13411
13412         return cursor;
13413
13414 fail:
13415         kfree(state);
13416         kfree(cursor);
13417
13418         return ERR_PTR(ret);
13419 }
13420
13421 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13422                                     struct intel_crtc_state *crtc_state)
13423 {
13424         struct intel_crtc_scaler_state *scaler_state =
13425                 &crtc_state->scaler_state;
13426         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13427         int i;
13428
13429         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13430         if (!crtc->num_scalers)
13431                 return;
13432
13433         for (i = 0; i < crtc->num_scalers; i++) {
13434                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13435
13436                 scaler->in_use = 0;
13437                 scaler->mode = PS_SCALER_MODE_DYN;
13438         }
13439
13440         scaler_state->scaler_id = -1;
13441 }
13442
13443 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13444 {
13445         struct intel_crtc *intel_crtc;
13446         struct intel_crtc_state *crtc_state = NULL;
13447         struct intel_plane *primary = NULL;
13448         struct intel_plane *cursor = NULL;
13449         int sprite, ret;
13450
13451         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13452         if (!intel_crtc)
13453                 return -ENOMEM;
13454
13455         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13456         if (!crtc_state) {
13457                 ret = -ENOMEM;
13458                 goto fail;
13459         }
13460         intel_crtc->config = crtc_state;
13461         intel_crtc->base.state = &crtc_state->base;
13462         crtc_state->base.crtc = &intel_crtc->base;
13463
13464         primary = intel_primary_plane_create(dev_priv, pipe);
13465         if (IS_ERR(primary)) {
13466                 ret = PTR_ERR(primary);
13467                 goto fail;
13468         }
13469         intel_crtc->plane_ids_mask |= BIT(primary->id);
13470
13471         for_each_sprite(dev_priv, pipe, sprite) {
13472                 struct intel_plane *plane;
13473
13474                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13475                 if (IS_ERR(plane)) {
13476                         ret = PTR_ERR(plane);
13477                         goto fail;
13478                 }
13479                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13480         }
13481
13482         cursor = intel_cursor_plane_create(dev_priv, pipe);
13483         if (IS_ERR(cursor)) {
13484                 ret = PTR_ERR(cursor);
13485                 goto fail;
13486         }
13487         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13488
13489         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13490                                         &primary->base, &cursor->base,
13491                                         &intel_crtc_funcs,
13492                                         "pipe %c", pipe_name(pipe));
13493         if (ret)
13494                 goto fail;
13495
13496         intel_crtc->pipe = pipe;
13497         intel_crtc->plane = primary->plane;
13498
13499         /* initialize shared scalers */
13500         intel_crtc_init_scalers(intel_crtc, crtc_state);
13501
13502         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13503                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13504         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13505         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13506
13507         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13508
13509         intel_color_init(&intel_crtc->base);
13510
13511         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13512
13513         return 0;
13514
13515 fail:
13516         /*
13517          * drm_mode_config_cleanup() will free up any
13518          * crtcs/planes already initialized.
13519          */
13520         kfree(crtc_state);
13521         kfree(intel_crtc);
13522
13523         return ret;
13524 }
13525
13526 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13527 {
13528         struct drm_device *dev = connector->base.dev;
13529
13530         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13531
13532         if (!connector->base.state->crtc)
13533                 return INVALID_PIPE;
13534
13535         return to_intel_crtc(connector->base.state->crtc)->pipe;
13536 }
13537
13538 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13539                                 struct drm_file *file)
13540 {
13541         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13542         struct drm_crtc *drmmode_crtc;
13543         struct intel_crtc *crtc;
13544
13545         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13546         if (!drmmode_crtc)
13547                 return -ENOENT;
13548
13549         crtc = to_intel_crtc(drmmode_crtc);
13550         pipe_from_crtc_id->pipe = crtc->pipe;
13551
13552         return 0;
13553 }
13554
13555 static int intel_encoder_clones(struct intel_encoder *encoder)
13556 {
13557         struct drm_device *dev = encoder->base.dev;
13558         struct intel_encoder *source_encoder;
13559         int index_mask = 0;
13560         int entry = 0;
13561
13562         for_each_intel_encoder(dev, source_encoder) {
13563                 if (encoders_cloneable(encoder, source_encoder))
13564                         index_mask |= (1 << entry);
13565
13566                 entry++;
13567         }
13568
13569         return index_mask;
13570 }
13571
13572 static bool has_edp_a(struct drm_i915_private *dev_priv)
13573 {
13574         if (!IS_MOBILE(dev_priv))
13575                 return false;
13576
13577         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13578                 return false;
13579
13580         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13581                 return false;
13582
13583         return true;
13584 }
13585
13586 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13587 {
13588         if (INTEL_GEN(dev_priv) >= 9)
13589                 return false;
13590
13591         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13592                 return false;
13593
13594         if (IS_CHERRYVIEW(dev_priv))
13595                 return false;
13596
13597         if (HAS_PCH_LPT_H(dev_priv) &&
13598             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13599                 return false;
13600
13601         /* DDI E can't be used if DDI A requires 4 lanes */
13602         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13603                 return false;
13604
13605         if (!dev_priv->vbt.int_crt_support)
13606                 return false;
13607
13608         return true;
13609 }
13610
13611 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13612 {
13613         int pps_num;
13614         int pps_idx;
13615
13616         if (HAS_DDI(dev_priv))
13617                 return;
13618         /*
13619          * This w/a is needed at least on CPT/PPT, but to be sure apply it
13620          * everywhere where registers can be write protected.
13621          */
13622         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13623                 pps_num = 2;
13624         else
13625                 pps_num = 1;
13626
13627         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13628                 u32 val = I915_READ(PP_CONTROL(pps_idx));
13629
13630                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13631                 I915_WRITE(PP_CONTROL(pps_idx), val);
13632         }
13633 }
13634
13635 static void intel_pps_init(struct drm_i915_private *dev_priv)
13636 {
13637         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13638                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13639         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13640                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13641         else
13642                 dev_priv->pps_mmio_base = PPS_BASE;
13643
13644         intel_pps_unlock_regs_wa(dev_priv);
13645 }
13646
13647 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13648 {
13649         struct intel_encoder *encoder;
13650         bool dpd_is_edp = false;
13651
13652         intel_pps_init(dev_priv);
13653
13654         /*
13655          * intel_edp_init_connector() depends on this completing first, to
13656          * prevent the registeration of both eDP and LVDS and the incorrect
13657          * sharing of the PPS.
13658          */
13659         intel_lvds_init(dev_priv);
13660
13661         if (intel_crt_present(dev_priv))
13662                 intel_crt_init(dev_priv);
13663
13664         if (IS_GEN9_LP(dev_priv)) {
13665                 /*
13666                  * FIXME: Broxton doesn't support port detection via the
13667                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13668                  * detect the ports.
13669                  */
13670                 intel_ddi_init(dev_priv, PORT_A);
13671                 intel_ddi_init(dev_priv, PORT_B);
13672                 intel_ddi_init(dev_priv, PORT_C);
13673
13674                 intel_dsi_init(dev_priv);
13675         } else if (HAS_DDI(dev_priv)) {
13676                 int found;
13677
13678                 /*
13679                  * Haswell uses DDI functions to detect digital outputs.
13680                  * On SKL pre-D0 the strap isn't connected, so we assume
13681                  * it's there.
13682                  */
13683                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13684                 /* WaIgnoreDDIAStrap: skl */
13685                 if (found || IS_GEN9_BC(dev_priv))
13686                         intel_ddi_init(dev_priv, PORT_A);
13687
13688                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13689                  * register */
13690                 found = I915_READ(SFUSE_STRAP);
13691
13692                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13693                         intel_ddi_init(dev_priv, PORT_B);
13694                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13695                         intel_ddi_init(dev_priv, PORT_C);
13696                 if (found & SFUSE_STRAP_DDID_DETECTED)
13697                         intel_ddi_init(dev_priv, PORT_D);
13698                 /*
13699                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13700                  */
13701                 if (IS_GEN9_BC(dev_priv) &&
13702                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13703                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13704                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13705                         intel_ddi_init(dev_priv, PORT_E);
13706
13707         } else if (HAS_PCH_SPLIT(dev_priv)) {
13708                 int found;
13709                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13710
13711                 if (has_edp_a(dev_priv))
13712                         intel_dp_init(dev_priv, DP_A, PORT_A);
13713
13714                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13715                         /* PCH SDVOB multiplex with HDMIB */
13716                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13717                         if (!found)
13718                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13719                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13720                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13721                 }
13722
13723                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13724                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13725
13726                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13727                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13728
13729                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13730                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13731
13732                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13733                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13734         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13735                 bool has_edp, has_port;
13736
13737                 /*
13738                  * The DP_DETECTED bit is the latched state of the DDC
13739                  * SDA pin at boot. However since eDP doesn't require DDC
13740                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13741                  * eDP ports may have been muxed to an alternate function.
13742                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13743                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13744                  * detect eDP ports.
13745                  *
13746                  * Sadly the straps seem to be missing sometimes even for HDMI
13747                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13748                  * and VBT for the presence of the port. Additionally we can't
13749                  * trust the port type the VBT declares as we've seen at least
13750                  * HDMI ports that the VBT claim are DP or eDP.
13751                  */
13752                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13753                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13754                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13755                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13756                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13757                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13758
13759                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13760                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13761                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13762                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13763                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13764                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13765
13766                 if (IS_CHERRYVIEW(dev_priv)) {
13767                         /*
13768                          * eDP not supported on port D,
13769                          * so no need to worry about it
13770                          */
13771                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13772                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13773                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13774                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13775                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13776                 }
13777
13778                 intel_dsi_init(dev_priv);
13779         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13780                 bool found = false;
13781
13782                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13783                         DRM_DEBUG_KMS("probing SDVOB\n");
13784                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13785                         if (!found && IS_G4X(dev_priv)) {
13786                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13787                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13788                         }
13789
13790                         if (!found && IS_G4X(dev_priv))
13791                                 intel_dp_init(dev_priv, DP_B, PORT_B);
13792                 }
13793
13794                 /* Before G4X SDVOC doesn't have its own detect register */
13795
13796                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13797                         DRM_DEBUG_KMS("probing SDVOC\n");
13798                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13799                 }
13800
13801                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13802
13803                         if (IS_G4X(dev_priv)) {
13804                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13805                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13806                         }
13807                         if (IS_G4X(dev_priv))
13808                                 intel_dp_init(dev_priv, DP_C, PORT_C);
13809                 }
13810
13811                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13812                         intel_dp_init(dev_priv, DP_D, PORT_D);
13813         } else if (IS_GEN2(dev_priv))
13814                 intel_dvo_init(dev_priv);
13815
13816         if (SUPPORTS_TV(dev_priv))
13817                 intel_tv_init(dev_priv);
13818
13819         intel_psr_init(dev_priv);
13820
13821         for_each_intel_encoder(&dev_priv->drm, encoder) {
13822                 encoder->base.possible_crtcs = encoder->crtc_mask;
13823                 encoder->base.possible_clones =
13824                         intel_encoder_clones(encoder);
13825         }
13826
13827         intel_init_pch_refclk(dev_priv);
13828
13829         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13830 }
13831
13832 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13833 {
13834         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13835
13836         drm_framebuffer_cleanup(fb);
13837
13838         i915_gem_object_lock(intel_fb->obj);
13839         WARN_ON(!intel_fb->obj->framebuffer_references--);
13840         i915_gem_object_unlock(intel_fb->obj);
13841
13842         i915_gem_object_put(intel_fb->obj);
13843
13844         kfree(intel_fb);
13845 }
13846
13847 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13848                                                 struct drm_file *file,
13849                                                 unsigned int *handle)
13850 {
13851         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13852         struct drm_i915_gem_object *obj = intel_fb->obj;
13853
13854         if (obj->userptr.mm) {
13855                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13856                 return -EINVAL;
13857         }
13858
13859         return drm_gem_handle_create(file, &obj->base, handle);
13860 }
13861
13862 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13863                                         struct drm_file *file,
13864                                         unsigned flags, unsigned color,
13865                                         struct drm_clip_rect *clips,
13866                                         unsigned num_clips)
13867 {
13868         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13869
13870         i915_gem_object_flush_if_display(obj);
13871         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13872
13873         return 0;
13874 }
13875
13876 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13877         .destroy = intel_user_framebuffer_destroy,
13878         .create_handle = intel_user_framebuffer_create_handle,
13879         .dirty = intel_user_framebuffer_dirty,
13880 };
13881
13882 static
13883 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13884                          uint64_t fb_modifier, uint32_t pixel_format)
13885 {
13886         u32 gen = INTEL_GEN(dev_priv);
13887
13888         if (gen >= 9) {
13889                 int cpp = drm_format_plane_cpp(pixel_format, 0);
13890
13891                 /* "The stride in bytes must not exceed the of the size of 8K
13892                  *  pixels and 32K bytes."
13893                  */
13894                 return min(8192 * cpp, 32768);
13895         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13896                 return 32*1024;
13897         } else if (gen >= 4) {
13898                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13899                         return 16*1024;
13900                 else
13901                         return 32*1024;
13902         } else if (gen >= 3) {
13903                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13904                         return 8*1024;
13905                 else
13906                         return 16*1024;
13907         } else {
13908                 /* XXX DSPC is limited to 4k tiled */
13909                 return 8*1024;
13910         }
13911 }
13912
13913 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13914                                   struct drm_i915_gem_object *obj,
13915                                   struct drm_mode_fb_cmd2 *mode_cmd)
13916 {
13917         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13918         struct drm_framebuffer *fb = &intel_fb->base;
13919         struct drm_format_name_buf format_name;
13920         u32 pitch_limit;
13921         unsigned int tiling, stride;
13922         int ret = -EINVAL;
13923         int i;
13924
13925         i915_gem_object_lock(obj);
13926         obj->framebuffer_references++;
13927         tiling = i915_gem_object_get_tiling(obj);
13928         stride = i915_gem_object_get_stride(obj);
13929         i915_gem_object_unlock(obj);
13930
13931         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13932                 /*
13933                  * If there's a fence, enforce that
13934                  * the fb modifier and tiling mode match.
13935                  */
13936                 if (tiling != I915_TILING_NONE &&
13937                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13938                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13939                         goto err;
13940                 }
13941         } else {
13942                 if (tiling == I915_TILING_X) {
13943                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13944                 } else if (tiling == I915_TILING_Y) {
13945                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13946                         goto err;
13947                 }
13948         }
13949
13950         /* Passed in modifier sanity checking. */
13951         switch (mode_cmd->modifier[0]) {
13952         case I915_FORMAT_MOD_Y_TILED_CCS:
13953         case I915_FORMAT_MOD_Yf_TILED_CCS:
13954                 switch (mode_cmd->pixel_format) {
13955                 case DRM_FORMAT_XBGR8888:
13956                 case DRM_FORMAT_ABGR8888:
13957                 case DRM_FORMAT_XRGB8888:
13958                 case DRM_FORMAT_ARGB8888:
13959                         break;
13960                 default:
13961                         DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13962                         goto err;
13963                 }
13964                 /* fall through */
13965         case I915_FORMAT_MOD_Y_TILED:
13966         case I915_FORMAT_MOD_Yf_TILED:
13967                 if (INTEL_GEN(dev_priv) < 9) {
13968                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13969                                       mode_cmd->modifier[0]);
13970                         goto err;
13971                 }
13972         case DRM_FORMAT_MOD_LINEAR:
13973         case I915_FORMAT_MOD_X_TILED:
13974                 break;
13975         default:
13976                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13977                               mode_cmd->modifier[0]);
13978                 goto err;
13979         }
13980
13981         /*
13982          * gen2/3 display engine uses the fence if present,
13983          * so the tiling mode must match the fb modifier exactly.
13984          */
13985         if (INTEL_INFO(dev_priv)->gen < 4 &&
13986             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13987                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13988                 goto err;
13989         }
13990
13991         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13992                                            mode_cmd->pixel_format);
13993         if (mode_cmd->pitches[0] > pitch_limit) {
13994                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13995                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13996                               "tiled" : "linear",
13997                               mode_cmd->pitches[0], pitch_limit);
13998                 goto err;
13999         }
14000
14001         /*
14002          * If there's a fence, enforce that
14003          * the fb pitch and fence stride match.
14004          */
14005         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14006                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14007                               mode_cmd->pitches[0], stride);
14008                 goto err;
14009         }
14010
14011         /* Reject formats not supported by any plane early. */
14012         switch (mode_cmd->pixel_format) {
14013         case DRM_FORMAT_C8:
14014         case DRM_FORMAT_RGB565:
14015         case DRM_FORMAT_XRGB8888:
14016         case DRM_FORMAT_ARGB8888:
14017                 break;
14018         case DRM_FORMAT_XRGB1555:
14019                 if (INTEL_GEN(dev_priv) > 3) {
14020                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14021                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14022                         goto err;
14023                 }
14024                 break;
14025         case DRM_FORMAT_ABGR8888:
14026                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14027                     INTEL_GEN(dev_priv) < 9) {
14028                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14029                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14030                         goto err;
14031                 }
14032                 break;
14033         case DRM_FORMAT_XBGR8888:
14034         case DRM_FORMAT_XRGB2101010:
14035         case DRM_FORMAT_XBGR2101010:
14036                 if (INTEL_GEN(dev_priv) < 4) {
14037                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14038                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14039                         goto err;
14040                 }
14041                 break;
14042         case DRM_FORMAT_ABGR2101010:
14043                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14044                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14045                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14046                         goto err;
14047                 }
14048                 break;
14049         case DRM_FORMAT_YUYV:
14050         case DRM_FORMAT_UYVY:
14051         case DRM_FORMAT_YVYU:
14052         case DRM_FORMAT_VYUY:
14053                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14054                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14055                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14056                         goto err;
14057                 }
14058                 break;
14059         default:
14060                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14061                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14062                 goto err;
14063         }
14064
14065         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14066         if (mode_cmd->offsets[0] != 0)
14067                 goto err;
14068
14069         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14070
14071         for (i = 0; i < fb->format->num_planes; i++) {
14072                 u32 stride_alignment;
14073
14074                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14075                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
14076                         goto err;
14077                 }
14078
14079                 stride_alignment = intel_fb_stride_alignment(fb, i);
14080
14081                 /*
14082                  * Display WA #0531: skl,bxt,kbl,glk
14083                  *
14084                  * Render decompression and plane width > 3840
14085                  * combined with horizontal panning requires the
14086                  * plane stride to be a multiple of 4. We'll just
14087                  * require the entire fb to accommodate that to avoid
14088                  * potential runtime errors at plane configuration time.
14089                  */
14090                 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14091                     (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14092                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14093                         stride_alignment *= 4;
14094
14095                 if (fb->pitches[i] & (stride_alignment - 1)) {
14096                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14097                                       i, fb->pitches[i], stride_alignment);
14098                         goto err;
14099                 }
14100         }
14101
14102         intel_fb->obj = obj;
14103
14104         ret = intel_fill_fb_info(dev_priv, fb);
14105         if (ret)
14106                 goto err;
14107
14108         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14109         if (ret) {
14110                 DRM_ERROR("framebuffer init failed %d\n", ret);
14111                 goto err;
14112         }
14113
14114         return 0;
14115
14116 err:
14117         i915_gem_object_lock(obj);
14118         obj->framebuffer_references--;
14119         i915_gem_object_unlock(obj);
14120         return ret;
14121 }
14122
14123 static struct drm_framebuffer *
14124 intel_user_framebuffer_create(struct drm_device *dev,
14125                               struct drm_file *filp,
14126                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14127 {
14128         struct drm_framebuffer *fb;
14129         struct drm_i915_gem_object *obj;
14130         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14131
14132         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14133         if (!obj)
14134                 return ERR_PTR(-ENOENT);
14135
14136         fb = intel_framebuffer_create(obj, &mode_cmd);
14137         if (IS_ERR(fb))
14138                 i915_gem_object_put(obj);
14139
14140         return fb;
14141 }
14142
14143 static void intel_atomic_state_free(struct drm_atomic_state *state)
14144 {
14145         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14146
14147         drm_atomic_state_default_release(state);
14148
14149         i915_sw_fence_fini(&intel_state->commit_ready);
14150
14151         kfree(state);
14152 }
14153
14154 static const struct drm_mode_config_funcs intel_mode_funcs = {
14155         .fb_create = intel_user_framebuffer_create,
14156         .get_format_info = intel_get_format_info,
14157         .output_poll_changed = intel_fbdev_output_poll_changed,
14158         .atomic_check = intel_atomic_check,
14159         .atomic_commit = intel_atomic_commit,
14160         .atomic_state_alloc = intel_atomic_state_alloc,
14161         .atomic_state_clear = intel_atomic_state_clear,
14162         .atomic_state_free = intel_atomic_state_free,
14163 };
14164
14165 /**
14166  * intel_init_display_hooks - initialize the display modesetting hooks
14167  * @dev_priv: device private
14168  */
14169 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14170 {
14171         intel_init_cdclk_hooks(dev_priv);
14172
14173         if (INTEL_INFO(dev_priv)->gen >= 9) {
14174                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14175                 dev_priv->display.get_initial_plane_config =
14176                         skylake_get_initial_plane_config;
14177                 dev_priv->display.crtc_compute_clock =
14178                         haswell_crtc_compute_clock;
14179                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14180                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14181         } else if (HAS_DDI(dev_priv)) {
14182                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14183                 dev_priv->display.get_initial_plane_config =
14184                         ironlake_get_initial_plane_config;
14185                 dev_priv->display.crtc_compute_clock =
14186                         haswell_crtc_compute_clock;
14187                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14188                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14189         } else if (HAS_PCH_SPLIT(dev_priv)) {
14190                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14191                 dev_priv->display.get_initial_plane_config =
14192                         ironlake_get_initial_plane_config;
14193                 dev_priv->display.crtc_compute_clock =
14194                         ironlake_crtc_compute_clock;
14195                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14196                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14197         } else if (IS_CHERRYVIEW(dev_priv)) {
14198                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14199                 dev_priv->display.get_initial_plane_config =
14200                         i9xx_get_initial_plane_config;
14201                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14202                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14203                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14204         } else if (IS_VALLEYVIEW(dev_priv)) {
14205                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14206                 dev_priv->display.get_initial_plane_config =
14207                         i9xx_get_initial_plane_config;
14208                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14209                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14210                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14211         } else if (IS_G4X(dev_priv)) {
14212                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14213                 dev_priv->display.get_initial_plane_config =
14214                         i9xx_get_initial_plane_config;
14215                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14216                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14217                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14218         } else if (IS_PINEVIEW(dev_priv)) {
14219                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14220                 dev_priv->display.get_initial_plane_config =
14221                         i9xx_get_initial_plane_config;
14222                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14223                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14224                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14225         } else if (!IS_GEN2(dev_priv)) {
14226                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14227                 dev_priv->display.get_initial_plane_config =
14228                         i9xx_get_initial_plane_config;
14229                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14230                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14231                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14232         } else {
14233                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14234                 dev_priv->display.get_initial_plane_config =
14235                         i9xx_get_initial_plane_config;
14236                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14237                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14238                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14239         }
14240
14241         if (IS_GEN5(dev_priv)) {
14242                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14243         } else if (IS_GEN6(dev_priv)) {
14244                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14245         } else if (IS_IVYBRIDGE(dev_priv)) {
14246                 /* FIXME: detect B0+ stepping and use auto training */
14247                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14248         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14249                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14250         }
14251
14252         if (INTEL_GEN(dev_priv) >= 9)
14253                 dev_priv->display.update_crtcs = skl_update_crtcs;
14254         else
14255                 dev_priv->display.update_crtcs = intel_update_crtcs;
14256 }
14257
14258 /*
14259  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14260  */
14261 static void quirk_ssc_force_disable(struct drm_device *dev)
14262 {
14263         struct drm_i915_private *dev_priv = to_i915(dev);
14264         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14265         DRM_INFO("applying lvds SSC disable quirk\n");
14266 }
14267
14268 /*
14269  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14270  * brightness value
14271  */
14272 static void quirk_invert_brightness(struct drm_device *dev)
14273 {
14274         struct drm_i915_private *dev_priv = to_i915(dev);
14275         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14276         DRM_INFO("applying inverted panel brightness quirk\n");
14277 }
14278
14279 /* Some VBT's incorrectly indicate no backlight is present */
14280 static void quirk_backlight_present(struct drm_device *dev)
14281 {
14282         struct drm_i915_private *dev_priv = to_i915(dev);
14283         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14284         DRM_INFO("applying backlight present quirk\n");
14285 }
14286
14287 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14288  * which is 300 ms greater than eDP spec T12 min.
14289  */
14290 static void quirk_increase_t12_delay(struct drm_device *dev)
14291 {
14292         struct drm_i915_private *dev_priv = to_i915(dev);
14293
14294         dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14295         DRM_INFO("Applying T12 delay quirk\n");
14296 }
14297
14298 struct intel_quirk {
14299         int device;
14300         int subsystem_vendor;
14301         int subsystem_device;
14302         void (*hook)(struct drm_device *dev);
14303 };
14304
14305 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14306 struct intel_dmi_quirk {
14307         void (*hook)(struct drm_device *dev);
14308         const struct dmi_system_id (*dmi_id_list)[];
14309 };
14310
14311 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14312 {
14313         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14314         return 1;
14315 }
14316
14317 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14318         {
14319                 .dmi_id_list = &(const struct dmi_system_id[]) {
14320                         {
14321                                 .callback = intel_dmi_reverse_brightness,
14322                                 .ident = "NCR Corporation",
14323                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14324                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14325                                 },
14326                         },
14327                         { }  /* terminating entry */
14328                 },
14329                 .hook = quirk_invert_brightness,
14330         },
14331 };
14332
14333 static struct intel_quirk intel_quirks[] = {
14334         /* Lenovo U160 cannot use SSC on LVDS */
14335         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14336
14337         /* Sony Vaio Y cannot use SSC on LVDS */
14338         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14339
14340         /* Acer Aspire 5734Z must invert backlight brightness */
14341         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14342
14343         /* Acer/eMachines G725 */
14344         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14345
14346         /* Acer/eMachines e725 */
14347         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14348
14349         /* Acer/Packard Bell NCL20 */
14350         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14351
14352         /* Acer Aspire 4736Z */
14353         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14354
14355         /* Acer Aspire 5336 */
14356         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14357
14358         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14359         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14360
14361         /* Acer C720 Chromebook (Core i3 4005U) */
14362         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14363
14364         /* Apple Macbook 2,1 (Core 2 T7400) */
14365         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14366
14367         /* Apple Macbook 4,1 */
14368         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14369
14370         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14371         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14372
14373         /* HP Chromebook 14 (Celeron 2955U) */
14374         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14375
14376         /* Dell Chromebook 11 */
14377         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14378
14379         /* Dell Chromebook 11 (2015 version) */
14380         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14381
14382         /* Toshiba Satellite P50-C-18C */
14383         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14384 };
14385
14386 static void intel_init_quirks(struct drm_device *dev)
14387 {
14388         struct pci_dev *d = dev->pdev;
14389         int i;
14390
14391         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14392                 struct intel_quirk *q = &intel_quirks[i];
14393
14394                 if (d->device == q->device &&
14395                     (d->subsystem_vendor == q->subsystem_vendor ||
14396                      q->subsystem_vendor == PCI_ANY_ID) &&
14397                     (d->subsystem_device == q->subsystem_device ||
14398                      q->subsystem_device == PCI_ANY_ID))
14399                         q->hook(dev);
14400         }
14401         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14402                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14403                         intel_dmi_quirks[i].hook(dev);
14404         }
14405 }
14406
14407 /* Disable the VGA plane that we never use */
14408 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14409 {
14410         struct pci_dev *pdev = dev_priv->drm.pdev;
14411         u8 sr1;
14412         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14413
14414         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14415         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14416         outb(SR01, VGA_SR_INDEX);
14417         sr1 = inb(VGA_SR_DATA);
14418         outb(sr1 | 1<<5, VGA_SR_DATA);
14419         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14420         udelay(300);
14421
14422         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14423         POSTING_READ(vga_reg);
14424 }
14425
14426 void intel_modeset_init_hw(struct drm_device *dev)
14427 {
14428         struct drm_i915_private *dev_priv = to_i915(dev);
14429
14430         intel_update_cdclk(dev_priv);
14431         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
14432         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14433 }
14434
14435 /*
14436  * Calculate what we think the watermarks should be for the state we've read
14437  * out of the hardware and then immediately program those watermarks so that
14438  * we ensure the hardware settings match our internal state.
14439  *
14440  * We can calculate what we think WM's should be by creating a duplicate of the
14441  * current state (which was constructed during hardware readout) and running it
14442  * through the atomic check code to calculate new watermark values in the
14443  * state object.
14444  */
14445 static void sanitize_watermarks(struct drm_device *dev)
14446 {
14447         struct drm_i915_private *dev_priv = to_i915(dev);
14448         struct drm_atomic_state *state;
14449         struct intel_atomic_state *intel_state;
14450         struct drm_crtc *crtc;
14451         struct drm_crtc_state *cstate;
14452         struct drm_modeset_acquire_ctx ctx;
14453         int ret;
14454         int i;
14455
14456         /* Only supported on platforms that use atomic watermark design */
14457         if (!dev_priv->display.optimize_watermarks)
14458                 return;
14459
14460         /*
14461          * We need to hold connection_mutex before calling duplicate_state so
14462          * that the connector loop is protected.
14463          */
14464         drm_modeset_acquire_init(&ctx, 0);
14465 retry:
14466         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14467         if (ret == -EDEADLK) {
14468                 drm_modeset_backoff(&ctx);
14469                 goto retry;
14470         } else if (WARN_ON(ret)) {
14471                 goto fail;
14472         }
14473
14474         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14475         if (WARN_ON(IS_ERR(state)))
14476                 goto fail;
14477
14478         intel_state = to_intel_atomic_state(state);
14479
14480         /*
14481          * Hardware readout is the only time we don't want to calculate
14482          * intermediate watermarks (since we don't trust the current
14483          * watermarks).
14484          */
14485         if (!HAS_GMCH_DISPLAY(dev_priv))
14486                 intel_state->skip_intermediate_wm = true;
14487
14488         ret = intel_atomic_check(dev, state);
14489         if (ret) {
14490                 /*
14491                  * If we fail here, it means that the hardware appears to be
14492                  * programmed in a way that shouldn't be possible, given our
14493                  * understanding of watermark requirements.  This might mean a
14494                  * mistake in the hardware readout code or a mistake in the
14495                  * watermark calculations for a given platform.  Raise a WARN
14496                  * so that this is noticeable.
14497                  *
14498                  * If this actually happens, we'll have to just leave the
14499                  * BIOS-programmed watermarks untouched and hope for the best.
14500                  */
14501                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14502                 goto put_state;
14503         }
14504
14505         /* Write calculated watermark values back */
14506         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14507                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14508
14509                 cs->wm.need_postvbl_update = true;
14510                 dev_priv->display.optimize_watermarks(intel_state, cs);
14511
14512                 to_intel_crtc_state(crtc->state)->wm = cs->wm;
14513         }
14514
14515 put_state:
14516         drm_atomic_state_put(state);
14517 fail:
14518         drm_modeset_drop_locks(&ctx);
14519         drm_modeset_acquire_fini(&ctx);
14520 }
14521
14522 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
14523 {
14524         if (IS_GEN5(dev_priv)) {
14525                 u32 fdi_pll_clk =
14526                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
14527
14528                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
14529         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
14530                 dev_priv->fdi_pll_freq = 270000;
14531         } else {
14532                 return;
14533         }
14534
14535         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
14536 }
14537
14538 int intel_modeset_init(struct drm_device *dev)
14539 {
14540         struct drm_i915_private *dev_priv = to_i915(dev);
14541         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14542         enum pipe pipe;
14543         struct intel_crtc *crtc;
14544
14545         drm_mode_config_init(dev);
14546
14547         dev->mode_config.min_width = 0;
14548         dev->mode_config.min_height = 0;
14549
14550         dev->mode_config.preferred_depth = 24;
14551         dev->mode_config.prefer_shadow = 1;
14552
14553         dev->mode_config.allow_fb_modifiers = true;
14554
14555         dev->mode_config.funcs = &intel_mode_funcs;
14556
14557         init_llist_head(&dev_priv->atomic_helper.free_list);
14558         INIT_WORK(&dev_priv->atomic_helper.free_work,
14559                   intel_atomic_helper_free_state_worker);
14560
14561         intel_init_quirks(dev);
14562
14563         intel_init_pm(dev_priv);
14564
14565         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14566                 return 0;
14567
14568         /*
14569          * There may be no VBT; and if the BIOS enabled SSC we can
14570          * just keep using it to avoid unnecessary flicker.  Whereas if the
14571          * BIOS isn't using it, don't assume it will work even if the VBT
14572          * indicates as much.
14573          */
14574         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14575                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14576                                             DREF_SSC1_ENABLE);
14577
14578                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14579                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14580                                      bios_lvds_use_ssc ? "en" : "dis",
14581                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14582                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14583                 }
14584         }
14585
14586         if (IS_GEN2(dev_priv)) {
14587                 dev->mode_config.max_width = 2048;
14588                 dev->mode_config.max_height = 2048;
14589         } else if (IS_GEN3(dev_priv)) {
14590                 dev->mode_config.max_width = 4096;
14591                 dev->mode_config.max_height = 4096;
14592         } else {
14593                 dev->mode_config.max_width = 8192;
14594                 dev->mode_config.max_height = 8192;
14595         }
14596
14597         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14598                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14599                 dev->mode_config.cursor_height = 1023;
14600         } else if (IS_GEN2(dev_priv)) {
14601                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14602                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14603         } else {
14604                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14605                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14606         }
14607
14608         dev->mode_config.fb_base = ggtt->mappable_base;
14609
14610         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14611                       INTEL_INFO(dev_priv)->num_pipes,
14612                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14613
14614         for_each_pipe(dev_priv, pipe) {
14615                 int ret;
14616
14617                 ret = intel_crtc_init(dev_priv, pipe);
14618                 if (ret) {
14619                         drm_mode_config_cleanup(dev);
14620                         return ret;
14621                 }
14622         }
14623
14624         intel_shared_dpll_init(dev);
14625         intel_update_fdi_pll_freq(dev_priv);
14626
14627         intel_update_czclk(dev_priv);
14628         intel_modeset_init_hw(dev);
14629
14630         if (dev_priv->max_cdclk_freq == 0)
14631                 intel_update_max_cdclk(dev_priv);
14632
14633         /* Just disable it once at startup */
14634         i915_disable_vga(dev_priv);
14635         intel_setup_outputs(dev_priv);
14636
14637         drm_modeset_lock_all(dev);
14638         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14639         drm_modeset_unlock_all(dev);
14640
14641         for_each_intel_crtc(dev, crtc) {
14642                 struct intel_initial_plane_config plane_config = {};
14643
14644                 if (!crtc->active)
14645                         continue;
14646
14647                 /*
14648                  * Note that reserving the BIOS fb up front prevents us
14649                  * from stuffing other stolen allocations like the ring
14650                  * on top.  This prevents some ugliness at boot time, and
14651                  * can even allow for smooth boot transitions if the BIOS
14652                  * fb is large enough for the active pipe configuration.
14653                  */
14654                 dev_priv->display.get_initial_plane_config(crtc,
14655                                                            &plane_config);
14656
14657                 /*
14658                  * If the fb is shared between multiple heads, we'll
14659                  * just get the first one.
14660                  */
14661                 intel_find_initial_plane_obj(crtc, &plane_config);
14662         }
14663
14664         /*
14665          * Make sure hardware watermarks really match the state we read out.
14666          * Note that we need to do this after reconstructing the BIOS fb's
14667          * since the watermark calculation done here will use pstate->fb.
14668          */
14669         if (!HAS_GMCH_DISPLAY(dev_priv))
14670                 sanitize_watermarks(dev);
14671
14672         return 0;
14673 }
14674
14675 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14676 {
14677         /* 640x480@60Hz, ~25175 kHz */
14678         struct dpll clock = {
14679                 .m1 = 18,
14680                 .m2 = 7,
14681                 .p1 = 13,
14682                 .p2 = 4,
14683                 .n = 2,
14684         };
14685         u32 dpll, fp;
14686         int i;
14687
14688         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14689
14690         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14691                       pipe_name(pipe), clock.vco, clock.dot);
14692
14693         fp = i9xx_dpll_compute_fp(&clock);
14694         dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14695                 DPLL_VGA_MODE_DIS |
14696                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14697                 PLL_P2_DIVIDE_BY_4 |
14698                 PLL_REF_INPUT_DREFCLK |
14699                 DPLL_VCO_ENABLE;
14700
14701         I915_WRITE(FP0(pipe), fp);
14702         I915_WRITE(FP1(pipe), fp);
14703
14704         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14705         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14706         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14707         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14708         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14709         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14710         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14711
14712         /*
14713          * Apparently we need to have VGA mode enabled prior to changing
14714          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14715          * dividers, even though the register value does change.
14716          */
14717         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14718         I915_WRITE(DPLL(pipe), dpll);
14719
14720         /* Wait for the clocks to stabilize. */
14721         POSTING_READ(DPLL(pipe));
14722         udelay(150);
14723
14724         /* The pixel multiplier can only be updated once the
14725          * DPLL is enabled and the clocks are stable.
14726          *
14727          * So write it again.
14728          */
14729         I915_WRITE(DPLL(pipe), dpll);
14730
14731         /* We do this three times for luck */
14732         for (i = 0; i < 3 ; i++) {
14733                 I915_WRITE(DPLL(pipe), dpll);
14734                 POSTING_READ(DPLL(pipe));
14735                 udelay(150); /* wait for warmup */
14736         }
14737
14738         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14739         POSTING_READ(PIPECONF(pipe));
14740 }
14741
14742 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14743 {
14744         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14745                       pipe_name(pipe));
14746
14747         assert_plane_disabled(dev_priv, PLANE_A);
14748         assert_plane_disabled(dev_priv, PLANE_B);
14749
14750         I915_WRITE(PIPECONF(pipe), 0);
14751         POSTING_READ(PIPECONF(pipe));
14752
14753         if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14754                 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14755
14756         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14757         POSTING_READ(DPLL(pipe));
14758 }
14759
14760 static bool
14761 intel_check_plane_mapping(struct intel_crtc *crtc)
14762 {
14763         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14764         u32 val;
14765
14766         if (INTEL_INFO(dev_priv)->num_pipes == 1)
14767                 return true;
14768
14769         val = I915_READ(DSPCNTR(!crtc->plane));
14770
14771         if ((val & DISPLAY_PLANE_ENABLE) &&
14772             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14773                 return false;
14774
14775         return true;
14776 }
14777
14778 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14779 {
14780         struct drm_device *dev = crtc->base.dev;
14781         struct intel_encoder *encoder;
14782
14783         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14784                 return true;
14785
14786         return false;
14787 }
14788
14789 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14790 {
14791         struct drm_device *dev = encoder->base.dev;
14792         struct intel_connector *connector;
14793
14794         for_each_connector_on_encoder(dev, &encoder->base, connector)
14795                 return connector;
14796
14797         return NULL;
14798 }
14799
14800 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14801                               enum pipe pch_transcoder)
14802 {
14803         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14804                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
14805 }
14806
14807 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14808                                 struct drm_modeset_acquire_ctx *ctx)
14809 {
14810         struct drm_device *dev = crtc->base.dev;
14811         struct drm_i915_private *dev_priv = to_i915(dev);
14812         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14813
14814         /* Clear any frame start delays used for debugging left by the BIOS */
14815         if (!transcoder_is_dsi(cpu_transcoder)) {
14816                 i915_reg_t reg = PIPECONF(cpu_transcoder);
14817
14818                 I915_WRITE(reg,
14819                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14820         }
14821
14822         /* restore vblank interrupts to correct state */
14823         drm_crtc_vblank_reset(&crtc->base);
14824         if (crtc->active) {
14825                 struct intel_plane *plane;
14826
14827                 drm_crtc_vblank_on(&crtc->base);
14828
14829                 /* Disable everything but the primary plane */
14830                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14831                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14832                                 continue;
14833
14834                         trace_intel_disable_plane(&plane->base, crtc);
14835                         plane->disable_plane(plane, crtc);
14836                 }
14837         }
14838
14839         /* We need to sanitize the plane -> pipe mapping first because this will
14840          * disable the crtc (and hence change the state) if it is wrong. Note
14841          * that gen4+ has a fixed plane -> pipe mapping.  */
14842         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14843                 bool plane;
14844
14845                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14846                               crtc->base.base.id, crtc->base.name);
14847
14848                 /* Pipe has the wrong plane attached and the plane is active.
14849                  * Temporarily change the plane mapping and disable everything
14850                  * ...  */
14851                 plane = crtc->plane;
14852                 crtc->base.primary->state->visible = true;
14853                 crtc->plane = !plane;
14854                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14855                 crtc->plane = plane;
14856         }
14857
14858         /* Adjust the state of the output pipe according to whether we
14859          * have active connectors/encoders. */
14860         if (crtc->active && !intel_crtc_has_encoders(crtc))
14861                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14862
14863         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14864                 /*
14865                  * We start out with underrun reporting disabled to avoid races.
14866                  * For correct bookkeeping mark this on active crtcs.
14867                  *
14868                  * Also on gmch platforms we dont have any hardware bits to
14869                  * disable the underrun reporting. Which means we need to start
14870                  * out with underrun reporting disabled also on inactive pipes,
14871                  * since otherwise we'll complain about the garbage we read when
14872                  * e.g. coming up after runtime pm.
14873                  *
14874                  * No protection against concurrent access is required - at
14875                  * worst a fifo underrun happens which also sets this to false.
14876                  */
14877                 crtc->cpu_fifo_underrun_disabled = true;
14878                 /*
14879                  * We track the PCH trancoder underrun reporting state
14880                  * within the crtc. With crtc for pipe A housing the underrun
14881                  * reporting state for PCH transcoder A, crtc for pipe B housing
14882                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14883                  * and marking underrun reporting as disabled for the non-existing
14884                  * PCH transcoders B and C would prevent enabling the south
14885                  * error interrupt (see cpt_can_enable_serr_int()).
14886                  */
14887                 if (has_pch_trancoder(dev_priv, crtc->pipe))
14888                         crtc->pch_fifo_underrun_disabled = true;
14889         }
14890 }
14891
14892 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14893 {
14894         struct intel_connector *connector;
14895
14896         /* We need to check both for a crtc link (meaning that the
14897          * encoder is active and trying to read from a pipe) and the
14898          * pipe itself being active. */
14899         bool has_active_crtc = encoder->base.crtc &&
14900                 to_intel_crtc(encoder->base.crtc)->active;
14901
14902         connector = intel_encoder_find_connector(encoder);
14903         if (connector && !has_active_crtc) {
14904                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14905                               encoder->base.base.id,
14906                               encoder->base.name);
14907
14908                 /* Connector is active, but has no active pipe. This is
14909                  * fallout from our resume register restoring. Disable
14910                  * the encoder manually again. */
14911                 if (encoder->base.crtc) {
14912                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14913
14914                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14915                                       encoder->base.base.id,
14916                                       encoder->base.name);
14917                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14918                         if (encoder->post_disable)
14919                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14920                 }
14921                 encoder->base.crtc = NULL;
14922
14923                 /* Inconsistent output/port/pipe state happens presumably due to
14924                  * a bug in one of the get_hw_state functions. Or someplace else
14925                  * in our code, like the register restore mess on resume. Clamp
14926                  * things to off as a safer default. */
14927
14928                 connector->base.dpms = DRM_MODE_DPMS_OFF;
14929                 connector->base.encoder = NULL;
14930         }
14931         /* Enabled encoders without active connectors will be fixed in
14932          * the crtc fixup. */
14933 }
14934
14935 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14936 {
14937         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14938
14939         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14940                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14941                 i915_disable_vga(dev_priv);
14942         }
14943 }
14944
14945 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14946 {
14947         /* This function can be called both from intel_modeset_setup_hw_state or
14948          * at a very early point in our resume sequence, where the power well
14949          * structures are not yet restored. Since this function is at a very
14950          * paranoid "someone might have enabled VGA while we were not looking"
14951          * level, just check if the power well is enabled instead of trying to
14952          * follow the "don't touch the power well if we don't need it" policy
14953          * the rest of the driver uses. */
14954         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14955                 return;
14956
14957         i915_redisable_vga_power_on(dev_priv);
14958
14959         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14960 }
14961
14962 static bool primary_get_hw_state(struct intel_plane *plane)
14963 {
14964         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14965
14966         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14967 }
14968
14969 /* FIXME read out full plane state for all planes */
14970 static void readout_plane_state(struct intel_crtc *crtc)
14971 {
14972         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14973         bool visible;
14974
14975         visible = crtc->active && primary_get_hw_state(primary);
14976
14977         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14978                                 to_intel_plane_state(primary->base.state),
14979                                 visible);
14980 }
14981
14982 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14983 {
14984         struct drm_i915_private *dev_priv = to_i915(dev);
14985         enum pipe pipe;
14986         struct intel_crtc *crtc;
14987         struct intel_encoder *encoder;
14988         struct intel_connector *connector;
14989         struct drm_connector_list_iter conn_iter;
14990         int i;
14991
14992         dev_priv->active_crtcs = 0;
14993
14994         for_each_intel_crtc(dev, crtc) {
14995                 struct intel_crtc_state *crtc_state =
14996                         to_intel_crtc_state(crtc->base.state);
14997
14998                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14999                 memset(crtc_state, 0, sizeof(*crtc_state));
15000                 crtc_state->base.crtc = &crtc->base;
15001
15002                 crtc_state->base.active = crtc_state->base.enable =
15003                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15004
15005                 crtc->base.enabled = crtc_state->base.enable;
15006                 crtc->active = crtc_state->base.active;
15007
15008                 if (crtc_state->base.active)
15009                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15010
15011                 readout_plane_state(crtc);
15012
15013                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15014                               crtc->base.base.id, crtc->base.name,
15015                               enableddisabled(crtc_state->base.active));
15016         }
15017
15018         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15019                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15020
15021                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15022                                                   &pll->state.hw_state);
15023                 pll->state.crtc_mask = 0;
15024                 for_each_intel_crtc(dev, crtc) {
15025                         struct intel_crtc_state *crtc_state =
15026                                 to_intel_crtc_state(crtc->base.state);
15027
15028                         if (crtc_state->base.active &&
15029                             crtc_state->shared_dpll == pll)
15030                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15031                 }
15032                 pll->active_mask = pll->state.crtc_mask;
15033
15034                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15035                               pll->name, pll->state.crtc_mask, pll->on);
15036         }
15037
15038         for_each_intel_encoder(dev, encoder) {
15039                 pipe = 0;
15040
15041                 if (encoder->get_hw_state(encoder, &pipe)) {
15042                         struct intel_crtc_state *crtc_state;
15043
15044                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15045                         crtc_state = to_intel_crtc_state(crtc->base.state);
15046
15047                         encoder->base.crtc = &crtc->base;
15048                         encoder->get_config(encoder, crtc_state);
15049                 } else {
15050                         encoder->base.crtc = NULL;
15051                 }
15052
15053                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15054                               encoder->base.base.id, encoder->base.name,
15055                               enableddisabled(encoder->base.crtc),
15056                               pipe_name(pipe));
15057         }
15058
15059         drm_connector_list_iter_begin(dev, &conn_iter);
15060         for_each_intel_connector_iter(connector, &conn_iter) {
15061                 if (connector->get_hw_state(connector)) {
15062                         connector->base.dpms = DRM_MODE_DPMS_ON;
15063
15064                         encoder = connector->encoder;
15065                         connector->base.encoder = &encoder->base;
15066
15067                         if (encoder->base.crtc &&
15068                             encoder->base.crtc->state->active) {
15069                                 /*
15070                                  * This has to be done during hardware readout
15071                                  * because anything calling .crtc_disable may
15072                                  * rely on the connector_mask being accurate.
15073                                  */
15074                                 encoder->base.crtc->state->connector_mask |=
15075                                         1 << drm_connector_index(&connector->base);
15076                                 encoder->base.crtc->state->encoder_mask |=
15077                                         1 << drm_encoder_index(&encoder->base);
15078                         }
15079
15080                 } else {
15081                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15082                         connector->base.encoder = NULL;
15083                 }
15084                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15085                               connector->base.base.id, connector->base.name,
15086                               enableddisabled(connector->base.encoder));
15087         }
15088         drm_connector_list_iter_end(&conn_iter);
15089
15090         for_each_intel_crtc(dev, crtc) {
15091                 struct intel_crtc_state *crtc_state =
15092                         to_intel_crtc_state(crtc->base.state);
15093                 int min_cdclk = 0;
15094
15095                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15096                 if (crtc_state->base.active) {
15097                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15098                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15099                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15100
15101                         /*
15102                          * The initial mode needs to be set in order to keep
15103                          * the atomic core happy. It wants a valid mode if the
15104                          * crtc's enabled, so we do the above call.
15105                          *
15106                          * But we don't set all the derived state fully, hence
15107                          * set a flag to indicate that a full recalculation is
15108                          * needed on the next commit.
15109                          */
15110                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15111
15112                         intel_crtc_compute_pixel_rate(crtc_state);
15113
15114                         if (dev_priv->display.modeset_calc_cdclk) {
15115                                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15116                                 if (WARN_ON(min_cdclk < 0))
15117                                         min_cdclk = 0;
15118                         }
15119
15120                         drm_calc_timestamping_constants(&crtc->base,
15121                                                         &crtc_state->base.adjusted_mode);
15122                         update_scanline_offset(crtc);
15123                 }
15124
15125                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15126                 dev_priv->min_voltage_level[crtc->pipe] =
15127                         crtc_state->min_voltage_level;
15128
15129                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15130         }
15131 }
15132
15133 static void
15134 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15135 {
15136         struct intel_encoder *encoder;
15137
15138         for_each_intel_encoder(&dev_priv->drm, encoder) {
15139                 u64 get_domains;
15140                 enum intel_display_power_domain domain;
15141
15142                 if (!encoder->get_power_domains)
15143                         continue;
15144
15145                 get_domains = encoder->get_power_domains(encoder);
15146                 for_each_power_domain(domain, get_domains)
15147                         intel_display_power_get(dev_priv, domain);
15148         }
15149 }
15150
15151 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15152 {
15153         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
15154         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
15155                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
15156                            DARBF_GATING_DIS);
15157
15158         if (IS_HASWELL(dev_priv)) {
15159                 /*
15160                  * WaRsPkgCStateDisplayPMReq:hsw
15161                  * System hang if this isn't done before disabling all planes!
15162                  */
15163                 I915_WRITE(CHICKEN_PAR1_1,
15164                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15165         }
15166 }
15167
15168 /* Scan out the current hw modeset state,
15169  * and sanitizes it to the current state
15170  */
15171 static void
15172 intel_modeset_setup_hw_state(struct drm_device *dev,
15173                              struct drm_modeset_acquire_ctx *ctx)
15174 {
15175         struct drm_i915_private *dev_priv = to_i915(dev);
15176         enum pipe pipe;
15177         struct intel_crtc *crtc;
15178         struct intel_encoder *encoder;
15179         int i;
15180
15181         intel_early_display_was(dev_priv);
15182         intel_modeset_readout_hw_state(dev);
15183
15184         /* HW state is read out, now we need to sanitize this mess. */
15185         get_encoder_power_domains(dev_priv);
15186
15187         for_each_intel_encoder(dev, encoder) {
15188                 intel_sanitize_encoder(encoder);
15189         }
15190
15191         for_each_pipe(dev_priv, pipe) {
15192                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15193
15194                 intel_sanitize_crtc(crtc, ctx);
15195                 intel_dump_pipe_config(crtc, crtc->config,
15196                                        "[setup_hw_state]");
15197         }
15198
15199         intel_modeset_update_connector_atomic_state(dev);
15200
15201         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15202                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15203
15204                 if (!pll->on || pll->active_mask)
15205                         continue;
15206
15207                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15208
15209                 pll->funcs.disable(dev_priv, pll);
15210                 pll->on = false;
15211         }
15212
15213         if (IS_G4X(dev_priv)) {
15214                 g4x_wm_get_hw_state(dev);
15215                 g4x_wm_sanitize(dev_priv);
15216         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15217                 vlv_wm_get_hw_state(dev);
15218                 vlv_wm_sanitize(dev_priv);
15219         } else if (INTEL_GEN(dev_priv) >= 9) {
15220                 skl_wm_get_hw_state(dev);
15221         } else if (HAS_PCH_SPLIT(dev_priv)) {
15222                 ilk_wm_get_hw_state(dev);
15223         }
15224
15225         for_each_intel_crtc(dev, crtc) {
15226                 u64 put_domains;
15227
15228                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15229                 if (WARN_ON(put_domains))
15230                         modeset_put_power_domains(dev_priv, put_domains);
15231         }
15232         intel_display_set_init_power(dev_priv, false);
15233
15234         intel_power_domains_verify_state(dev_priv);
15235
15236         intel_fbc_init_pipe_state(dev_priv);
15237 }
15238
15239 void intel_display_resume(struct drm_device *dev)
15240 {
15241         struct drm_i915_private *dev_priv = to_i915(dev);
15242         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15243         struct drm_modeset_acquire_ctx ctx;
15244         int ret;
15245
15246         dev_priv->modeset_restore_state = NULL;
15247         if (state)
15248                 state->acquire_ctx = &ctx;
15249
15250         drm_modeset_acquire_init(&ctx, 0);
15251
15252         while (1) {
15253                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15254                 if (ret != -EDEADLK)
15255                         break;
15256
15257                 drm_modeset_backoff(&ctx);
15258         }
15259
15260         if (!ret)
15261                 ret = __intel_display_resume(dev, state, &ctx);
15262
15263         intel_enable_ipc(dev_priv);
15264         drm_modeset_drop_locks(&ctx);
15265         drm_modeset_acquire_fini(&ctx);
15266
15267         if (ret)
15268                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15269         if (state)
15270                 drm_atomic_state_put(state);
15271 }
15272
15273 int intel_connector_register(struct drm_connector *connector)
15274 {
15275         struct intel_connector *intel_connector = to_intel_connector(connector);
15276         int ret;
15277
15278         ret = intel_backlight_device_register(intel_connector);
15279         if (ret)
15280                 goto err;
15281
15282         return 0;
15283
15284 err:
15285         return ret;
15286 }
15287
15288 void intel_connector_unregister(struct drm_connector *connector)
15289 {
15290         struct intel_connector *intel_connector = to_intel_connector(connector);
15291
15292         intel_backlight_device_unregister(intel_connector);
15293         intel_panel_destroy_backlight(connector);
15294 }
15295
15296 static void intel_hpd_poll_fini(struct drm_device *dev)
15297 {
15298         struct intel_connector *connector;
15299         struct drm_connector_list_iter conn_iter;
15300
15301         /* First disable polling... */
15302         drm_kms_helper_poll_fini(dev);
15303
15304         /* Then kill the work that may have been queued by hpd. */
15305         drm_connector_list_iter_begin(dev, &conn_iter);
15306         for_each_intel_connector_iter(connector, &conn_iter) {
15307                 if (connector->modeset_retry_work.func)
15308                         cancel_work_sync(&connector->modeset_retry_work);
15309         }
15310         drm_connector_list_iter_end(&conn_iter);
15311 }
15312
15313 void intel_modeset_cleanup(struct drm_device *dev)
15314 {
15315         struct drm_i915_private *dev_priv = to_i915(dev);
15316
15317         flush_work(&dev_priv->atomic_helper.free_work);
15318         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15319
15320         intel_disable_gt_powersave(dev_priv);
15321
15322         /*
15323          * Interrupts and polling as the first thing to avoid creating havoc.
15324          * Too much stuff here (turning of connectors, ...) would
15325          * experience fancy races otherwise.
15326          */
15327         intel_irq_uninstall(dev_priv);
15328
15329         /*
15330          * Due to the hpd irq storm handling the hotplug work can re-arm the
15331          * poll handlers. Hence disable polling after hpd handling is shut down.
15332          */
15333         intel_hpd_poll_fini(dev);
15334
15335         /* poll work can call into fbdev, hence clean that up afterwards */
15336         intel_fbdev_fini(dev_priv);
15337
15338         intel_unregister_dsm_handler();
15339
15340         intel_fbc_global_disable(dev_priv);
15341
15342         /* flush any delayed tasks or pending work */
15343         flush_scheduled_work();
15344
15345         drm_mode_config_cleanup(dev);
15346
15347         intel_cleanup_overlay(dev_priv);
15348
15349         intel_cleanup_gt_powersave(dev_priv);
15350
15351         intel_teardown_gmbus(dev_priv);
15352 }
15353
15354 void intel_connector_attach_encoder(struct intel_connector *connector,
15355                                     struct intel_encoder *encoder)
15356 {
15357         connector->encoder = encoder;
15358         drm_mode_connector_attach_encoder(&connector->base,
15359                                           &encoder->base);
15360 }
15361
15362 /*
15363  * set vga decode state - true == enable VGA decode
15364  */
15365 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15366 {
15367         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15368         u16 gmch_ctrl;
15369
15370         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15371                 DRM_ERROR("failed to read control word\n");
15372                 return -EIO;
15373         }
15374
15375         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15376                 return 0;
15377
15378         if (state)
15379                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15380         else
15381                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15382
15383         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15384                 DRM_ERROR("failed to write control word\n");
15385                 return -EIO;
15386         }
15387
15388         return 0;
15389 }
15390
15391 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15392
15393 struct intel_display_error_state {
15394
15395         u32 power_well_driver;
15396
15397         int num_transcoders;
15398
15399         struct intel_cursor_error_state {
15400                 u32 control;
15401                 u32 position;
15402                 u32 base;
15403                 u32 size;
15404         } cursor[I915_MAX_PIPES];
15405
15406         struct intel_pipe_error_state {
15407                 bool power_domain_on;
15408                 u32 source;
15409                 u32 stat;
15410         } pipe[I915_MAX_PIPES];
15411
15412         struct intel_plane_error_state {
15413                 u32 control;
15414                 u32 stride;
15415                 u32 size;
15416                 u32 pos;
15417                 u32 addr;
15418                 u32 surface;
15419                 u32 tile_offset;
15420         } plane[I915_MAX_PIPES];
15421
15422         struct intel_transcoder_error_state {
15423                 bool power_domain_on;
15424                 enum transcoder cpu_transcoder;
15425
15426                 u32 conf;
15427
15428                 u32 htotal;
15429                 u32 hblank;
15430                 u32 hsync;
15431                 u32 vtotal;
15432                 u32 vblank;
15433                 u32 vsync;
15434         } transcoder[4];
15435 };
15436
15437 struct intel_display_error_state *
15438 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15439 {
15440         struct intel_display_error_state *error;
15441         int transcoders[] = {
15442                 TRANSCODER_A,
15443                 TRANSCODER_B,
15444                 TRANSCODER_C,
15445                 TRANSCODER_EDP,
15446         };
15447         int i;
15448
15449         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15450                 return NULL;
15451
15452         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15453         if (error == NULL)
15454                 return NULL;
15455
15456         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15457                 error->power_well_driver =
15458                         I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15459
15460         for_each_pipe(dev_priv, i) {
15461                 error->pipe[i].power_domain_on =
15462                         __intel_display_power_is_enabled(dev_priv,
15463                                                          POWER_DOMAIN_PIPE(i));
15464                 if (!error->pipe[i].power_domain_on)
15465                         continue;
15466
15467                 error->cursor[i].control = I915_READ(CURCNTR(i));
15468                 error->cursor[i].position = I915_READ(CURPOS(i));
15469                 error->cursor[i].base = I915_READ(CURBASE(i));
15470
15471                 error->plane[i].control = I915_READ(DSPCNTR(i));
15472                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15473                 if (INTEL_GEN(dev_priv) <= 3) {
15474                         error->plane[i].size = I915_READ(DSPSIZE(i));
15475                         error->plane[i].pos = I915_READ(DSPPOS(i));
15476                 }
15477                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15478                         error->plane[i].addr = I915_READ(DSPADDR(i));
15479                 if (INTEL_GEN(dev_priv) >= 4) {
15480                         error->plane[i].surface = I915_READ(DSPSURF(i));
15481                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15482                 }
15483
15484                 error->pipe[i].source = I915_READ(PIPESRC(i));
15485
15486                 if (HAS_GMCH_DISPLAY(dev_priv))
15487                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15488         }
15489
15490         /* Note: this does not include DSI transcoders. */
15491         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15492         if (HAS_DDI(dev_priv))
15493                 error->num_transcoders++; /* Account for eDP. */
15494
15495         for (i = 0; i < error->num_transcoders; i++) {
15496                 enum transcoder cpu_transcoder = transcoders[i];
15497
15498                 error->transcoder[i].power_domain_on =
15499                         __intel_display_power_is_enabled(dev_priv,
15500                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15501                 if (!error->transcoder[i].power_domain_on)
15502                         continue;
15503
15504                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15505
15506                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15507                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15508                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15509                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15510                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15511                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15512                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15513         }
15514
15515         return error;
15516 }
15517
15518 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15519
15520 void
15521 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15522                                 struct intel_display_error_state *error)
15523 {
15524         struct drm_i915_private *dev_priv = m->i915;
15525         int i;
15526
15527         if (!error)
15528                 return;
15529
15530         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15531         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15532                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15533                            error->power_well_driver);
15534         for_each_pipe(dev_priv, i) {
15535                 err_printf(m, "Pipe [%d]:\n", i);
15536                 err_printf(m, "  Power: %s\n",
15537                            onoff(error->pipe[i].power_domain_on));
15538                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15539                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15540
15541                 err_printf(m, "Plane [%d]:\n", i);
15542                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15543                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15544                 if (INTEL_GEN(dev_priv) <= 3) {
15545                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15546                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15547                 }
15548                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15549                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15550                 if (INTEL_GEN(dev_priv) >= 4) {
15551                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15552                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15553                 }
15554
15555                 err_printf(m, "Cursor [%d]:\n", i);
15556                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15557                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15558                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15559         }
15560
15561         for (i = 0; i < error->num_transcoders; i++) {
15562                 err_printf(m, "CPU transcoder: %s\n",
15563                            transcoder_name(error->transcoder[i].cpu_transcoder));
15564                 err_printf(m, "  Power: %s\n",
15565                            onoff(error->transcoder[i].power_domain_on));
15566                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15567                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15568                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15569                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15570                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15571                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15572                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15573         }
15574 }
15575
15576 #endif