drivers/gpu/drm/i915/intel_device_info.h

   1 /*
   2  * Copyright © 2014-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DEVICE_INFO_H_
  26 #define _INTEL_DEVICE_INFO_H_
  27
  28 #include <uapi/drm/i915_drm.h>
  29
  30 #include "intel_step.h"
  31
  32 #include "display/intel_display.h"
  33
  34 #include "gt/intel_engine_types.h"
  35 #include "gt/intel_context_types.h"
  36 #include "gt/intel_sseu.h"
  37
  38 struct drm_printer;
  39 struct drm_i915_private;
  40
  41 /* Keep in gen based order, and chronological order within a gen */
  42 enum intel_platform {
  43         INTEL_PLATFORM_UNINITIALIZED = 0,
  44         /* gen2 */
  45         INTEL_I830,
  46         INTEL_I845G,
  47         INTEL_I85X,
  48         INTEL_I865G,
  49         /* gen3 */
  50         INTEL_I915G,
  51         INTEL_I915GM,
  52         INTEL_I945G,
  53         INTEL_I945GM,
  54         INTEL_G33,
  55         INTEL_PINEVIEW,
  56         /* gen4 */
  57         INTEL_I965G,
  58         INTEL_I965GM,
  59         INTEL_G45,
  60         INTEL_GM45,
  61         /* gen5 */
  62         INTEL_IRONLAKE,
  63         /* gen6 */
  64         INTEL_SANDYBRIDGE,
  65         /* gen7 */
  66         INTEL_IVYBRIDGE,
  67         INTEL_VALLEYVIEW,
  68         INTEL_HASWELL,
  69         /* gen8 */
  70         INTEL_BROADWELL,
  71         INTEL_CHERRYVIEW,
  72         /* gen9 */
  73         INTEL_SKYLAKE,
  74         INTEL_BROXTON,
  75         INTEL_KABYLAKE,
  76         INTEL_GEMINILAKE,
  77         INTEL_COFFEELAKE,
  78         INTEL_COMETLAKE,
  79         /* gen11 */
  80         INTEL_ICELAKE,
  81         INTEL_ELKHARTLAKE,
  82         INTEL_JASPERLAKE,
  83         /* gen12 */
  84         INTEL_TIGERLAKE,
  85         INTEL_ROCKETLAKE,
  86         INTEL_DG1,
  87         INTEL_ALDERLAKE_S,
  88         INTEL_ALDERLAKE_P,
  89         INTEL_XEHPSDV,
  90         INTEL_DG2,
  91         INTEL_PONTEVECCHIO,
  92         INTEL_METEORLAKE,
  93         INTEL_MAX_PLATFORMS
  94 };
  95
  96 /*
  97  * Subplatform bits share the same namespace per parent platform. In other words
  98  * it is fine for the same bit to be used on multiple parent platforms.
  99  */
 100
 101 #define INTEL_SUBPLATFORM_BITS (3)
 102 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
 103
 104 /* HSW/BDW/SKL/KBL/CFL */
 105 #define INTEL_SUBPLATFORM_ULT   (0)
 106 #define INTEL_SUBPLATFORM_ULX   (1)
 107
 108 /* ICL */
 109 #define INTEL_SUBPLATFORM_PORTF (0)
 110
 111 /* TGL */
 112 #define INTEL_SUBPLATFORM_UY    (0)
 113
 114 /* DG2 */
 115 #define INTEL_SUBPLATFORM_G10   0
 116 #define INTEL_SUBPLATFORM_G11   1
 117 #define INTEL_SUBPLATFORM_G12   2
 118
 119 /* ADL */
 120 #define INTEL_SUBPLATFORM_RPL   0
 121
 122 /* ADL-P */
 123 /*
 124  * As #define INTEL_SUBPLATFORM_RPL 0 will apply
 125  * here too, SUBPLATFORM_N will have different
 126  * bit set
 127  */
 128 #define INTEL_SUBPLATFORM_N    1
 129
 130 /* MTL */
 131 #define INTEL_SUBPLATFORM_M     0
 132 #define INTEL_SUBPLATFORM_P     1
 133
 134 enum intel_ppgtt_type {
 135         INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 136         INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 137         INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
 138 };
 139
 140 #define DEV_INFO_FOR_EACH_FLAG(func) \
 141         func(is_mobile); \
 142         func(is_lp); \
 143         func(require_force_probe); \
 144         func(is_dgfx); \
 145         /* Keep has_* in alphabetical order */ \
 146         func(has_64bit_reloc); \
 147         func(has_64k_pages); \
 148         func(needs_compact_pt); \
 149         func(gpu_reset_clobbers_display); \
 150         func(has_reset_engine); \
 151         func(has_3d_pipeline); \
 152         func(has_4tile); \
 153         func(has_flat_ccs); \
 154         func(has_global_mocs); \
 155         func(has_gt_uc); \
 156         func(has_heci_pxp); \
 157         func(has_heci_gscfi); \
 158         func(has_guc_deprivilege); \
 159         func(has_l3_ccs_read); \
 160         func(has_l3_dpf); \
 161         func(has_llc); \
 162         func(has_logical_ring_contexts); \
 163         func(has_logical_ring_elsq); \
 164         func(has_media_ratio_mode); \
 165         func(has_mslice_steering); \
 166         func(has_one_eu_per_fuse_bit); \
 167         func(has_pooled_eu); \
 168         func(has_pxp); \
 169         func(has_rc6); \
 170         func(has_rc6p); \
 171         func(has_rps); \
 172         func(has_runtime_pm); \
 173         func(has_snoop); \
 174         func(has_coherent_ggtt); \
 175         func(unfenced_needs_alignment); \
 176         func(hws_needs_physical);
 177
 178 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
 179         /* Keep in alphabetical order */ \
 180         func(cursor_needs_physical); \
 181         func(has_cdclk_crawl); \
 182         func(has_dmc); \
 183         func(has_ddi); \
 184         func(has_dp_mst); \
 185         func(has_dsb); \
 186         func(has_dsc); \
 187         func(has_fpga_dbg); \
 188         func(has_gmch); \
 189         func(has_hdcp); \
 190         func(has_hotplug); \
 191         func(has_hti); \
 192         func(has_ipc); \
 193         func(has_modular_fia); \
 194         func(has_overlay); \
 195         func(has_psr); \
 196         func(has_psr_hw_tracking); \
 197         func(overlay_needs_physical); \
 198         func(supports_tv);
 199
 200 struct ip_version {
 201         u8 ver;
 202         u8 rel;
 203 };
 204
 205 struct intel_device_info {
 206         struct ip_version graphics;
 207         struct ip_version media;
 208
 209         intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
 210
 211         enum intel_platform platform;
 212
 213         unsigned int dma_mask_size; /* available DMA address bits */
 214
 215         enum intel_ppgtt_type ppgtt_type;
 216         unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
 217
 218         unsigned int page_sizes; /* page sizes supported by the HW */
 219
 220         u32 memory_regions; /* regions supported by the HW */
 221
 222         u8 gt; /* GT number, 0 if undefined */
 223
 224 #define DEFINE_FLAG(name) u8 name:1
 225         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 226 #undef DEFINE_FLAG
 227
 228         struct {
 229                 u8 ver;
 230                 u8 rel;
 231
 232                 u8 pipe_mask;
 233                 u8 cpu_transcoder_mask;
 234                 u8 fbc_mask;
 235                 u8 abox_mask;
 236
 237                 struct {
 238                         u16 size; /* in blocks */
 239                         u8 slice_mask;
 240                 } dbuf;
 241
 242 #define DEFINE_FLAG(name) u8 name:1
 243                 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 244 #undef DEFINE_FLAG
 245
 246                 /* Global register offset for the display engine */
 247                 u32 mmio_offset;
 248
 249                 /* Register offsets for the various display pipes and transcoders */
 250                 u32 pipe_offsets[I915_MAX_TRANSCODERS];
 251                 u32 trans_offsets[I915_MAX_TRANSCODERS];
 252                 u32 cursor_offsets[I915_MAX_PIPES];
 253
 254                 struct {
 255                         u32 degamma_lut_size;
 256                         u32 gamma_lut_size;
 257                         u32 degamma_lut_tests;
 258                         u32 gamma_lut_tests;
 259                 } color;
 260         } display;
 261 };
 262
 263 struct intel_runtime_info {
 264         /*
 265          * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
 266          * into single runtime conditionals, and also to provide groundwork
 267          * for future per platform, or per SKU build optimizations.
 268          *
 269          * Array can be extended when necessary if the corresponding
 270          * BUILD_BUG_ON is hit.
 271          */
 272         u32 platform_mask[2];
 273
 274         u16 device_id;
 275
 276         u8 num_sprites[I915_MAX_PIPES];
 277         u8 num_scalers[I915_MAX_PIPES];
 278
 279         u32 rawclk_freq;
 280
 281         struct intel_step_info step;
 282 };
 283
 284 struct intel_driver_caps {
 285         unsigned int scheduler;
 286         bool has_logical_contexts:1;
 287 };
 288
 289 const char *intel_platform_name(enum intel_platform platform);
 290
 291 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
 292 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
 293
 294 void intel_device_info_print_static(const struct intel_device_info *info,
 295                                     struct drm_printer *p);
 296 void intel_device_info_print_runtime(const struct intel_runtime_info *info,
 297                                      struct drm_printer *p);
 298
 299 void intel_driver_caps_print(const struct intel_driver_caps *caps,
 300                              struct drm_printer *p);
 301
 302 #endif