2 * Copyright © 2014-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef _INTEL_DEVICE_INFO_H_
26 #define _INTEL_DEVICE_INFO_H_
28 #include <uapi/drm/i915_drm.h>
30 #include "intel_step.h"
32 #include "display/intel_display.h"
34 #include "gt/intel_engine_types.h"
35 #include "gt/intel_context_types.h"
36 #include "gt/intel_sseu.h"
39 struct drm_i915_private;
40 struct intel_gt_definition;
42 /* Keep in gen based order, and chronological order within a gen */
44 INTEL_PLATFORM_UNINITIALIZED = 0,
98 * Subplatform bits share the same namespace per parent platform. In other words
99 * it is fine for the same bit to be used on multiple parent platforms.
102 #define INTEL_SUBPLATFORM_BITS (3)
103 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
105 /* HSW/BDW/SKL/KBL/CFL */
106 #define INTEL_SUBPLATFORM_ULT (0)
107 #define INTEL_SUBPLATFORM_ULX (1)
110 #define INTEL_SUBPLATFORM_PORTF (0)
113 #define INTEL_SUBPLATFORM_UY (0)
116 #define INTEL_SUBPLATFORM_G10 0
117 #define INTEL_SUBPLATFORM_G11 1
118 #define INTEL_SUBPLATFORM_G12 2
121 #define INTEL_SUBPLATFORM_RPL 0
125 * As #define INTEL_SUBPLATFORM_RPL 0 will apply
126 * here too, SUBPLATFORM_N will have different
129 #define INTEL_SUBPLATFORM_N 1
132 #define INTEL_SUBPLATFORM_M 0
133 #define INTEL_SUBPLATFORM_P 1
135 enum intel_ppgtt_type {
136 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
137 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
138 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
141 #define DEV_INFO_FOR_EACH_FLAG(func) \
144 func(require_force_probe); \
146 /* Keep has_* in alphabetical order */ \
147 func(has_64bit_reloc); \
148 func(has_64k_pages); \
149 func(needs_compact_pt); \
150 func(gpu_reset_clobbers_display); \
151 func(has_reset_engine); \
152 func(has_3d_pipeline); \
154 func(has_flat_ccs); \
155 func(has_global_mocs); \
157 func(has_heci_pxp); \
158 func(has_heci_gscfi); \
159 func(has_guc_deprivilege); \
160 func(has_l3_ccs_read); \
163 func(has_logical_ring_contexts); \
164 func(has_logical_ring_elsq); \
165 func(has_media_ratio_mode); \
166 func(has_mslice_steering); \
167 func(has_one_eu_per_fuse_bit); \
172 func(has_runtime_pm); \
174 func(has_coherent_ggtt); \
175 func(tuning_thread_rr_after_dep); \
176 func(unfenced_needs_alignment); \
177 func(hws_needs_physical);
179 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
180 /* Keep in alphabetical order */ \
181 func(cursor_needs_physical); \
182 func(has_cdclk_crawl); \
186 func(has_fpga_dbg); \
191 func(has_modular_fia); \
194 func(has_psr_hw_tracking); \
195 func(overlay_needs_physical); \
203 struct intel_runtime_info {
205 struct ip_version ip;
208 struct ip_version ip;
211 struct ip_version ip;
215 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
216 * single runtime conditionals, and also to provide groundwork for
217 * future per platform, or per SKU build optimizations.
219 * Array can be extended when necessary if the corresponding
220 * BUILD_BUG_ON is hit.
222 u32 platform_mask[2];
226 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
230 struct intel_step_info step;
232 unsigned int page_sizes; /* page sizes supported by the HW */
234 enum intel_ppgtt_type ppgtt_type;
235 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
237 u32 memory_regions; /* regions supported by the HW */
244 u8 cpu_transcoder_mask;
246 u8 num_sprites[I915_MAX_PIPES];
247 u8 num_scalers[I915_MAX_PIPES];
257 struct intel_device_info {
258 enum intel_platform platform;
260 unsigned int dma_mask_size; /* available DMA address bits */
262 const struct intel_gt_definition *extra_gt_list;
264 u8 gt; /* GT number, 0 if undefined */
266 #define DEFINE_FLAG(name) u8 name:1
267 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
274 u16 size; /* in blocks */
278 #define DEFINE_FLAG(name) u8 name:1
279 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
282 /* Global register offset for the display engine */
285 /* Register offsets for the various display pipes and transcoders */
286 u32 pipe_offsets[I915_MAX_TRANSCODERS];
287 u32 trans_offsets[I915_MAX_TRANSCODERS];
288 u32 cursor_offsets[I915_MAX_PIPES];
291 u32 degamma_lut_size;
293 u32 degamma_lut_tests;
299 * Initial runtime info. Do not access outside of i915_driver_create().
301 const struct intel_runtime_info __runtime;
304 struct intel_driver_caps {
305 unsigned int scheduler;
306 bool has_logical_contexts:1;
309 const char *intel_platform_name(enum intel_platform platform);
311 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
312 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
314 void intel_device_info_print(const struct intel_device_info *info,
315 const struct intel_runtime_info *runtime,
316 struct drm_printer *p);
318 void intel_driver_caps_print(const struct intel_driver_caps *caps,
319 struct drm_printer *p);