drivers/gpu/drm/i915/intel_device_info.h

   1 /*
   2  * Copyright © 2014-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DEVICE_INFO_H_
  26 #define _INTEL_DEVICE_INFO_H_
  27
  28 #include <uapi/drm/i915_drm.h>
  29
  30 #include "intel_step.h"
  31
  32 #include "display/intel_display.h"
  33
  34 #include "gt/intel_engine_types.h"
  35 #include "gt/intel_context_types.h"
  36 #include "gt/intel_sseu.h"
  37
  38 struct drm_printer;
  39 struct drm_i915_private;
  40 struct intel_gt_definition;
  41
  42 /* Keep in gen based order, and chronological order within a gen */
  43 enum intel_platform {
  44         INTEL_PLATFORM_UNINITIALIZED = 0,
  45         /* gen2 */
  46         INTEL_I830,
  47         INTEL_I845G,
  48         INTEL_I85X,
  49         INTEL_I865G,
  50         /* gen3 */
  51         INTEL_I915G,
  52         INTEL_I915GM,
  53         INTEL_I945G,
  54         INTEL_I945GM,
  55         INTEL_G33,
  56         INTEL_PINEVIEW,
  57         /* gen4 */
  58         INTEL_I965G,
  59         INTEL_I965GM,
  60         INTEL_G45,
  61         INTEL_GM45,
  62         /* gen5 */
  63         INTEL_IRONLAKE,
  64         /* gen6 */
  65         INTEL_SANDYBRIDGE,
  66         /* gen7 */
  67         INTEL_IVYBRIDGE,
  68         INTEL_VALLEYVIEW,
  69         INTEL_HASWELL,
  70         /* gen8 */
  71         INTEL_BROADWELL,
  72         INTEL_CHERRYVIEW,
  73         /* gen9 */
  74         INTEL_SKYLAKE,
  75         INTEL_BROXTON,
  76         INTEL_KABYLAKE,
  77         INTEL_GEMINILAKE,
  78         INTEL_COFFEELAKE,
  79         INTEL_COMETLAKE,
  80         /* gen11 */
  81         INTEL_ICELAKE,
  82         INTEL_ELKHARTLAKE,
  83         INTEL_JASPERLAKE,
  84         /* gen12 */
  85         INTEL_TIGERLAKE,
  86         INTEL_ROCKETLAKE,
  87         INTEL_DG1,
  88         INTEL_ALDERLAKE_S,
  89         INTEL_ALDERLAKE_P,
  90         INTEL_XEHPSDV,
  91         INTEL_DG2,
  92         INTEL_PONTEVECCHIO,
  93         INTEL_METEORLAKE,
  94         INTEL_MAX_PLATFORMS
  95 };
  96
  97 /*
  98  * Subplatform bits share the same namespace per parent platform. In other words
  99  * it is fine for the same bit to be used on multiple parent platforms.
 100  */
 101
 102 #define INTEL_SUBPLATFORM_BITS (3)
 103 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
 104
 105 /* HSW/BDW/SKL/KBL/CFL */
 106 #define INTEL_SUBPLATFORM_ULT   (0)
 107 #define INTEL_SUBPLATFORM_ULX   (1)
 108
 109 /* ICL */
 110 #define INTEL_SUBPLATFORM_PORTF (0)
 111
 112 /* TGL */
 113 #define INTEL_SUBPLATFORM_UY    (0)
 114
 115 /* DG2 */
 116 #define INTEL_SUBPLATFORM_G10   0
 117 #define INTEL_SUBPLATFORM_G11   1
 118 #define INTEL_SUBPLATFORM_G12   2
 119
 120 /* ADL */
 121 #define INTEL_SUBPLATFORM_RPL   0
 122
 123 /* ADL-P */
 124 /*
 125  * As #define INTEL_SUBPLATFORM_RPL 0 will apply
 126  * here too, SUBPLATFORM_N will have different
 127  * bit set
 128  */
 129 #define INTEL_SUBPLATFORM_N    1
 130
 131 /* MTL */
 132 #define INTEL_SUBPLATFORM_M     0
 133 #define INTEL_SUBPLATFORM_P     1
 134
 135 enum intel_ppgtt_type {
 136         INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 137         INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 138         INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
 139 };
 140
 141 #define DEV_INFO_FOR_EACH_FLAG(func) \
 142         func(is_mobile); \
 143         func(is_lp); \
 144         func(require_force_probe); \
 145         func(is_dgfx); \
 146         /* Keep has_* in alphabetical order */ \
 147         func(has_64bit_reloc); \
 148         func(has_64k_pages); \
 149         func(gpu_reset_clobbers_display); \
 150         func(has_reset_engine); \
 151         func(has_3d_pipeline); \
 152         func(has_4tile); \
 153         func(has_flat_ccs); \
 154         func(has_global_mocs); \
 155         func(has_gmd_id); \
 156         func(has_gt_uc); \
 157         func(has_heci_pxp); \
 158         func(has_heci_gscfi); \
 159         func(has_guc_deprivilege); \
 160         func(has_l3_ccs_read); \
 161         func(has_l3_dpf); \
 162         func(has_llc); \
 163         func(has_logical_ring_contexts); \
 164         func(has_logical_ring_elsq); \
 165         func(has_media_ratio_mode); \
 166         func(has_mslice_steering); \
 167         func(has_oa_bpc_reporting); \
 168         func(has_oa_slice_contrib_limits); \
 169         func(has_one_eu_per_fuse_bit); \
 170         func(has_pxp); \
 171         func(has_rc6); \
 172         func(has_rc6p); \
 173         func(has_rps); \
 174         func(has_runtime_pm); \
 175         func(has_snoop); \
 176         func(has_coherent_ggtt); \
 177         func(tuning_thread_rr_after_dep); \
 178         func(unfenced_needs_alignment); \
 179         func(hws_needs_physical);
 180
 181 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
 182         /* Keep in alphabetical order */ \
 183         func(cursor_needs_physical); \
 184         func(has_cdclk_crawl); \
 185         func(has_cdclk_squash); \
 186         func(has_ddi); \
 187         func(has_dp_mst); \
 188         func(has_dsb); \
 189         func(has_fpga_dbg); \
 190         func(has_gmch); \
 191         func(has_hotplug); \
 192         func(has_hti); \
 193         func(has_ipc); \
 194         func(has_modular_fia); \
 195         func(has_overlay); \
 196         func(has_psr); \
 197         func(has_psr_hw_tracking); \
 198         func(overlay_needs_physical); \
 199         func(supports_tv);
 200
 201 struct intel_ip_version {
 202         u8 ver;
 203         u8 rel;
 204         u8 step;
 205 };
 206
 207 struct intel_runtime_info {
 208         /*
 209          * Single "graphics" IP version that represents
 210          * render, compute and copy behavior.
 211          */
 212         struct {
 213                 struct intel_ip_version ip;
 214         } graphics;
 215         struct {
 216                 struct intel_ip_version ip;
 217         } media;
 218         struct {
 219                 struct intel_ip_version ip;
 220         } display;
 221
 222         /*
 223          * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
 224          * single runtime conditionals, and also to provide groundwork for
 225          * future per platform, or per SKU build optimizations.
 226          *
 227          * Array can be extended when necessary if the corresponding
 228          * BUILD_BUG_ON is hit.
 229          */
 230         u32 platform_mask[2];
 231
 232         u16 device_id;
 233
 234         intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
 235
 236         u32 rawclk_freq;
 237
 238         struct intel_step_info step;
 239
 240         unsigned int page_sizes; /* page sizes supported by the HW */
 241
 242         enum intel_ppgtt_type ppgtt_type;
 243         unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
 244
 245         u32 memory_regions; /* regions supported by the HW */
 246
 247         bool has_pooled_eu;
 248
 249         /* display */
 250         struct {
 251                 u8 pipe_mask;
 252                 u8 cpu_transcoder_mask;
 253
 254                 u8 num_sprites[I915_MAX_PIPES];
 255                 u8 num_scalers[I915_MAX_PIPES];
 256
 257                 u8 fbc_mask;
 258
 259                 bool has_hdcp;
 260                 bool has_dmc;
 261                 bool has_dsc;
 262         };
 263 };
 264
 265 struct intel_device_info {
 266         enum intel_platform platform;
 267
 268         unsigned int dma_mask_size; /* available DMA address bits */
 269
 270         const struct intel_gt_definition *extra_gt_list;
 271
 272         u8 gt; /* GT number, 0 if undefined */
 273
 274 #define DEFINE_FLAG(name) u8 name:1
 275         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 276 #undef DEFINE_FLAG
 277
 278         struct {
 279                 u8 abox_mask;
 280
 281                 struct {
 282                         u16 size; /* in blocks */
 283                         u8 slice_mask;
 284                 } dbuf;
 285
 286 #define DEFINE_FLAG(name) u8 name:1
 287                 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 288 #undef DEFINE_FLAG
 289
 290                 /* Global register offset for the display engine */
 291                 u32 mmio_offset;
 292
 293                 /* Register offsets for the various display pipes and transcoders */
 294                 u32 pipe_offsets[I915_MAX_TRANSCODERS];
 295                 u32 trans_offsets[I915_MAX_TRANSCODERS];
 296                 u32 cursor_offsets[I915_MAX_PIPES];
 297
 298                 struct {
 299                         u32 degamma_lut_size;
 300                         u32 gamma_lut_size;
 301                         u32 degamma_lut_tests;
 302                         u32 gamma_lut_tests;
 303                 } color;
 304         } display;
 305
 306         /*
 307          * Initial runtime info. Do not access outside of i915_driver_create().
 308          */
 309         const struct intel_runtime_info __runtime;
 310 };
 311
 312 struct intel_driver_caps {
 313         unsigned int scheduler;
 314         bool has_logical_contexts:1;
 315 };
 316
 317 const char *intel_platform_name(enum intel_platform platform);
 318
 319 void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
 320 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
 321
 322 void intel_device_info_print(const struct intel_device_info *info,
 323                              const struct intel_runtime_info *runtime,
 324                              struct drm_printer *p);
 325
 326 void intel_driver_caps_print(const struct intel_driver_caps *caps,
 327                              struct drm_printer *p);
 328
 329 #endif