2 * Copyright © 2014-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef _INTEL_DEVICE_INFO_H_
26 #define _INTEL_DEVICE_INFO_H_
28 #include <uapi/drm/i915_drm.h>
30 #include "intel_step.h"
32 #include "display/intel_display.h"
34 #include "gt/intel_engine_types.h"
35 #include "gt/intel_context_types.h"
36 #include "gt/intel_sseu.h"
39 struct drm_i915_private;
41 /* Keep in gen based order, and chronological order within a gen */
43 INTEL_PLATFORM_UNINITIALIZED = 0,
95 * Subplatform bits share the same namespace per parent platform. In other words
96 * it is fine for the same bit to be used on multiple parent platforms.
99 #define INTEL_SUBPLATFORM_BITS (2)
100 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
102 /* HSW/BDW/SKL/KBL/CFL */
103 #define INTEL_SUBPLATFORM_ULT (0)
104 #define INTEL_SUBPLATFORM_ULX (1)
107 #define INTEL_SUBPLATFORM_PORTF (0)
110 #define INTEL_SUBPLATFORM_G10 0
111 #define INTEL_SUBPLATFORM_G11 1
114 #define INTEL_SUBPLATFORM_RPL_S 0
116 enum intel_ppgtt_type {
117 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
118 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
119 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
122 #define DEV_INFO_FOR_EACH_FLAG(func) \
125 func(require_force_probe); \
127 /* Keep has_* in alphabetical order */ \
128 func(has_64bit_reloc); \
129 func(gpu_reset_clobbers_display); \
130 func(has_reset_engine); \
131 func(has_global_mocs); \
135 func(has_logical_ring_contexts); \
136 func(has_logical_ring_elsq); \
138 func(has_pooled_eu); \
143 func(has_runtime_pm); \
145 func(has_coherent_ggtt); \
146 func(unfenced_needs_alignment); \
147 func(hws_needs_physical);
149 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
150 /* Keep in alphabetical order */ \
151 func(cursor_needs_physical); \
152 func(has_cdclk_crawl); \
159 func(has_fpga_dbg); \
165 func(has_modular_fia); \
168 func(has_psr_hw_tracking); \
169 func(overlay_needs_physical); \
172 struct intel_device_info {
178 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
180 enum intel_platform platform;
182 unsigned int dma_mask_size; /* available DMA address bits */
184 enum intel_ppgtt_type ppgtt_type;
185 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
187 unsigned int page_sizes; /* page sizes supported by the HW */
189 u32 memory_regions; /* regions supported by the HW */
191 u32 display_mmio_offset;
193 u8 gt; /* GT number, 0 if undefined */
196 u8 cpu_transcoder_mask;
200 #define DEFINE_FLAG(name) u8 name:1
201 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
207 #define DEFINE_FLAG(name) u8 name:1
208 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
213 u16 size; /* in blocks */
217 /* Register offsets for the various display pipes and transcoders */
218 int pipe_offsets[I915_MAX_TRANSCODERS];
219 int trans_offsets[I915_MAX_TRANSCODERS];
220 int cursor_offsets[I915_MAX_PIPES];
223 u32 degamma_lut_size;
225 u32 degamma_lut_tests;
230 struct intel_runtime_info {
232 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
233 * into single runtime conditionals, and also to provide groundwork
234 * for future per platform, or per SKU build optimizations.
236 * Array can be extended when necessary if the corresponding
237 * BUILD_BUG_ON is hit.
239 u32 platform_mask[2];
243 u8 num_sprites[I915_MAX_PIPES];
244 u8 num_scalers[I915_MAX_PIPES];
248 struct intel_step_info step;
251 struct intel_driver_caps {
252 unsigned int scheduler;
253 bool has_logical_contexts:1;
256 const char *intel_platform_name(enum intel_platform platform);
258 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
259 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
261 void intel_device_info_print_static(const struct intel_device_info *info,
262 struct drm_printer *p);
263 void intel_device_info_print_runtime(const struct intel_runtime_info *info,
264 struct drm_printer *p);
266 void intel_driver_caps_print(const struct intel_driver_caps *caps,
267 struct drm_printer *p);