drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  35 };
  36
  37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  38  * them for both DP and FDI transports, allowing those ports to
  39  * automatically adapt to HDMI connections as well
  40  */
  41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  42         { 0x00FFFFFF, 0x0006000E, 0x0 },
  43         { 0x00D75FFF, 0x0005000A, 0x0 },
  44         { 0x00C30FFF, 0x00040006, 0x0 },
  45         { 0x80AAAFFF, 0x000B0000, 0x0 },
  46         { 0x00FFFFFF, 0x0005000A, 0x0 },
  47         { 0x00D75FFF, 0x000C0004, 0x0 },
  48         { 0x80C30FFF, 0x000B0000, 0x0 },
  49         { 0x00FFFFFF, 0x00040006, 0x0 },
  50         { 0x80D75FFF, 0x000B0000, 0x0 },
  51 };
  52
  53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  54         { 0x00FFFFFF, 0x0007000E, 0x0 },
  55         { 0x00D75FFF, 0x000F000A, 0x0 },
  56         { 0x00C30FFF, 0x00060006, 0x0 },
  57         { 0x00AAAFFF, 0x001E0000, 0x0 },
  58         { 0x00FFFFFF, 0x000F000A, 0x0 },
  59         { 0x00D75FFF, 0x00160004, 0x0 },
  60         { 0x00C30FFF, 0x001E0000, 0x0 },
  61         { 0x00FFFFFF, 0x00060006, 0x0 },
  62         { 0x00D75FFF, 0x001E0000, 0x0 },
  63 };
  64
  65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  66                                         /* Idx  NT mV d T mV d  db      */
  67         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  68         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  69         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  70         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  71         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  72         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  73         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  74         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  75         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  76         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  77         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  78         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  79 };
  80
  81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  82         { 0x00FFFFFF, 0x00000012, 0x0 },
  83         { 0x00EBAFFF, 0x00020011, 0x0 },
  84         { 0x00C71FFF, 0x0006000F, 0x0 },
  85         { 0x00AAAFFF, 0x000E000A, 0x0 },
  86         { 0x00FFFFFF, 0x00020011, 0x0 },
  87         { 0x00DB6FFF, 0x0005000F, 0x0 },
  88         { 0x00BEEFFF, 0x000A000C, 0x0 },
  89         { 0x00FFFFFF, 0x0005000F, 0x0 },
  90         { 0x00DB6FFF, 0x000A000C, 0x0 },
  91 };
  92
  93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  94         { 0x00FFFFFF, 0x0007000E, 0x0 },
  95         { 0x00D75FFF, 0x000E000A, 0x0 },
  96         { 0x00BEFFFF, 0x00140006, 0x0 },
  97         { 0x80B2CFFF, 0x001B0002, 0x0 },
  98         { 0x00FFFFFF, 0x000E000A, 0x0 },
  99         { 0x00DB6FFF, 0x00160005, 0x0 },
 100         { 0x80C71FFF, 0x001A0002, 0x0 },
 101         { 0x00F7DFFF, 0x00180004, 0x0 },
 102         { 0x80D75FFF, 0x001B0002, 0x0 },
 103 };
 104
 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 106         { 0x00FFFFFF, 0x0001000E, 0x0 },
 107         { 0x00D75FFF, 0x0004000A, 0x0 },
 108         { 0x00C30FFF, 0x00070006, 0x0 },
 109         { 0x00AAAFFF, 0x000C0000, 0x0 },
 110         { 0x00FFFFFF, 0x0004000A, 0x0 },
 111         { 0x00D75FFF, 0x00090004, 0x0 },
 112         { 0x00C30FFF, 0x000C0000, 0x0 },
 113         { 0x00FFFFFF, 0x00070006, 0x0 },
 114         { 0x00D75FFF, 0x000C0000, 0x0 },
 115 };
 116
 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 118                                         /* Idx  NT mV d T mV df db      */
 119         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 120         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 121         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 122         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 123         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 124         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 125         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 126         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 127         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 128         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 129 };
 130
 131 /* Skylake H and S */
 132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 133         { 0x00002016, 0x000000A0, 0x0 },
 134         { 0x00005012, 0x0000009B, 0x0 },
 135         { 0x00007011, 0x00000088, 0x0 },
 136         { 0x80009010, 0x000000C0, 0x1 },
 137         { 0x00002016, 0x0000009B, 0x0 },
 138         { 0x00005012, 0x00000088, 0x0 },
 139         { 0x80007011, 0x000000C0, 0x1 },
 140         { 0x00002016, 0x000000DF, 0x0 },
 141         { 0x80005012, 0x000000C0, 0x1 },
 142 };
 143
 144 /* Skylake U */
 145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 146         { 0x0000201B, 0x000000A2, 0x0 },
 147         { 0x00005012, 0x00000088, 0x0 },
 148         { 0x80007011, 0x000000CD, 0x1 },
 149         { 0x80009010, 0x000000C0, 0x1 },
 150         { 0x0000201B, 0x0000009D, 0x0 },
 151         { 0x80005012, 0x000000C0, 0x1 },
 152         { 0x80007011, 0x000000C0, 0x1 },
 153         { 0x00002016, 0x00000088, 0x0 },
 154         { 0x80005012, 0x000000C0, 0x1 },
 155 };
 156
 157 /* Skylake Y */
 158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 159         { 0x00000018, 0x000000A2, 0x0 },
 160         { 0x00005012, 0x00000088, 0x0 },
 161         { 0x80007011, 0x000000CD, 0x3 },
 162         { 0x80009010, 0x000000C0, 0x3 },
 163         { 0x00000018, 0x0000009D, 0x0 },
 164         { 0x80005012, 0x000000C0, 0x3 },
 165         { 0x80007011, 0x000000C0, 0x3 },
 166         { 0x00000018, 0x00000088, 0x0 },
 167         { 0x80005012, 0x000000C0, 0x3 },
 168 };
 169
 170 /* Kabylake H and S */
 171 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 172         { 0x00002016, 0x000000A0, 0x0 },
 173         { 0x00005012, 0x0000009B, 0x0 },
 174         { 0x00007011, 0x00000088, 0x0 },
 175         { 0x80009010, 0x000000C0, 0x1 },
 176         { 0x00002016, 0x0000009B, 0x0 },
 177         { 0x00005012, 0x00000088, 0x0 },
 178         { 0x80007011, 0x000000C0, 0x1 },
 179         { 0x00002016, 0x00000097, 0x0 },
 180         { 0x80005012, 0x000000C0, 0x1 },
 181 };
 182
 183 /* Kabylake U */
 184 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 185         { 0x0000201B, 0x000000A1, 0x0 },
 186         { 0x00005012, 0x00000088, 0x0 },
 187         { 0x80007011, 0x000000CD, 0x3 },
 188         { 0x80009010, 0x000000C0, 0x3 },
 189         { 0x0000201B, 0x0000009D, 0x0 },
 190         { 0x80005012, 0x000000C0, 0x3 },
 191         { 0x80007011, 0x000000C0, 0x3 },
 192         { 0x00002016, 0x0000004F, 0x0 },
 193         { 0x80005012, 0x000000C0, 0x3 },
 194 };
 195
 196 /* Kabylake Y */
 197 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 198         { 0x00001017, 0x000000A1, 0x0 },
 199         { 0x00005012, 0x00000088, 0x0 },
 200         { 0x80007011, 0x000000CD, 0x3 },
 201         { 0x8000800F, 0x000000C0, 0x3 },
 202         { 0x00001017, 0x0000009D, 0x0 },
 203         { 0x80005012, 0x000000C0, 0x3 },
 204         { 0x80007011, 0x000000C0, 0x3 },
 205         { 0x00001017, 0x0000004C, 0x0 },
 206         { 0x80005012, 0x000000C0, 0x3 },
 207 };
 208
 209 /*
 210  * Skylake/Kabylake H and S
 211  * eDP 1.4 low vswing translation parameters
 212  */
 213 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 214         { 0x00000018, 0x000000A8, 0x0 },
 215         { 0x00004013, 0x000000A9, 0x0 },
 216         { 0x00007011, 0x000000A2, 0x0 },
 217         { 0x00009010, 0x0000009C, 0x0 },
 218         { 0x00000018, 0x000000A9, 0x0 },
 219         { 0x00006013, 0x000000A2, 0x0 },
 220         { 0x00007011, 0x000000A6, 0x0 },
 221         { 0x00000018, 0x000000AB, 0x0 },
 222         { 0x00007013, 0x0000009F, 0x0 },
 223         { 0x00000018, 0x000000DF, 0x0 },
 224 };
 225
 226 /*
 227  * Skylake/Kabylake U
 228  * eDP 1.4 low vswing translation parameters
 229  */
 230 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 231         { 0x00000018, 0x000000A8, 0x0 },
 232         { 0x00004013, 0x000000A9, 0x0 },
 233         { 0x00007011, 0x000000A2, 0x0 },
 234         { 0x00009010, 0x0000009C, 0x0 },
 235         { 0x00000018, 0x000000A9, 0x0 },
 236         { 0x00006013, 0x000000A2, 0x0 },
 237         { 0x00007011, 0x000000A6, 0x0 },
 238         { 0x00002016, 0x000000AB, 0x0 },
 239         { 0x00005013, 0x0000009F, 0x0 },
 240         { 0x00000018, 0x000000DF, 0x0 },
 241 };
 242
 243 /*
 244  * Skylake/Kabylake Y
 245  * eDP 1.4 low vswing translation parameters
 246  */
 247 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 248         { 0x00000018, 0x000000A8, 0x0 },
 249         { 0x00004013, 0x000000AB, 0x0 },
 250         { 0x00007011, 0x000000A4, 0x0 },
 251         { 0x00009010, 0x000000DF, 0x0 },
 252         { 0x00000018, 0x000000AA, 0x0 },
 253         { 0x00006013, 0x000000A4, 0x0 },
 254         { 0x00007011, 0x0000009D, 0x0 },
 255         { 0x00000018, 0x000000A0, 0x0 },
 256         { 0x00006012, 0x000000DF, 0x0 },
 257         { 0x00000018, 0x0000008A, 0x0 },
 258 };
 259
 260 /* Skylake/Kabylake U, H and S */
 261 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 262         { 0x00000018, 0x000000AC, 0x0 },
 263         { 0x00005012, 0x0000009D, 0x0 },
 264         { 0x00007011, 0x00000088, 0x0 },
 265         { 0x00000018, 0x000000A1, 0x0 },
 266         { 0x00000018, 0x00000098, 0x0 },
 267         { 0x00004013, 0x00000088, 0x0 },
 268         { 0x80006012, 0x000000CD, 0x1 },
 269         { 0x00000018, 0x000000DF, 0x0 },
 270         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 271         { 0x80003015, 0x000000C0, 0x1 },
 272         { 0x80000018, 0x000000C0, 0x1 },
 273 };
 274
 275 /* Skylake/Kabylake Y */
 276 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 277         { 0x00000018, 0x000000A1, 0x0 },
 278         { 0x00005012, 0x000000DF, 0x0 },
 279         { 0x80007011, 0x000000CB, 0x3 },
 280         { 0x00000018, 0x000000A4, 0x0 },
 281         { 0x00000018, 0x0000009D, 0x0 },
 282         { 0x00004013, 0x00000080, 0x0 },
 283         { 0x80006013, 0x000000C0, 0x3 },
 284         { 0x00000018, 0x0000008A, 0x0 },
 285         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 286         { 0x80003015, 0x000000C0, 0x3 },
 287         { 0x80000018, 0x000000C0, 0x3 },
 288 };
 289
 290 struct bxt_ddi_buf_trans {
 291         u32 margin;     /* swing value */
 292         u32 scale;      /* scale value */
 293         u32 enable;     /* scale enable */
 294         u32 deemphasis;
 295         bool default_index; /* true if the entry represents default value */
 296 };
 297
 298 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 299                                         /* Idx  NT mV diff      db  */
 300         { 52,  0x9A, 0, 128, true  },   /* 0:   400             0   */
 301         { 78,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 302         { 104, 0x9A, 0, 64,  false },   /* 2:   400             6   */
 303         { 154, 0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 304         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 305         { 116, 0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 306         { 154, 0x9A, 0, 64,  false },   /* 6:   600             6   */
 307         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 308         { 154, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 309         { 154, 0x9A, 1, 128, false },   /* 9:   1200            0   */
 310 };
 311
 312 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 313                                         /* Idx  NT mV diff      db  */
 314         { 26, 0, 0, 128, false },       /* 0:   200             0   */
 315         { 38, 0, 0, 112, false },       /* 1:   200             1.5 */
 316         { 48, 0, 0, 96,  false },       /* 2:   200             4   */
 317         { 54, 0, 0, 69,  false },       /* 3:   200             6   */
 318         { 32, 0, 0, 128, false },       /* 4:   250             0   */
 319         { 48, 0, 0, 104, false },       /* 5:   250             1.5 */
 320         { 54, 0, 0, 85,  false },       /* 6:   250             4   */
 321         { 43, 0, 0, 128, false },       /* 7:   300             0   */
 322         { 54, 0, 0, 101, false },       /* 8:   300             1.5 */
 323         { 48, 0, 0, 128, false },       /* 9:   300             0   */
 324 };
 325
 326 /* BSpec has 2 recommended values - entries 0 and 8.
 327  * Using the entry with higher vswing.
 328  */
 329 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 330                                         /* Idx  NT mV diff      db  */
 331         { 52,  0x9A, 0, 128, false },   /* 0:   400             0   */
 332         { 52,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 333         { 52,  0x9A, 0, 64,  false },   /* 2:   400             6   */
 334         { 42,  0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 335         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 336         { 77,  0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 337         { 77,  0x9A, 0, 64,  false },   /* 6:   600             6   */
 338         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 339         { 102, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 340         { 154, 0x9A, 1, 128, true },    /* 9:   1200            0   */
 341 };
 342
 343 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
 344 {
 345         switch (encoder->type) {
 346         case INTEL_OUTPUT_DP_MST:
 347                 return enc_to_mst(&encoder->base)->primary->port;
 348         case INTEL_OUTPUT_DP:
 349         case INTEL_OUTPUT_EDP:
 350         case INTEL_OUTPUT_HDMI:
 351         case INTEL_OUTPUT_UNKNOWN:
 352                 return enc_to_dig_port(&encoder->base)->port;
 353         case INTEL_OUTPUT_ANALOG:
 354                 return PORT_E;
 355         default:
 356                 MISSING_CASE(encoder->type);
 357                 return PORT_A;
 358         }
 359 }
 360
 361 static const struct ddi_buf_trans *
 362 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 363 {
 364         if (dev_priv->vbt.edp.low_vswing) {
 365                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 366                 return bdw_ddi_translations_edp;
 367         } else {
 368                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 369                 return bdw_ddi_translations_dp;
 370         }
 371 }
 372
 373 static const struct ddi_buf_trans *
 374 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 375 {
 376         if (IS_SKL_ULX(dev_priv)) {
 377                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 378                 return skl_y_ddi_translations_dp;
 379         } else if (IS_SKL_ULT(dev_priv)) {
 380                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 381                 return skl_u_ddi_translations_dp;
 382         } else {
 383                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 384                 return skl_ddi_translations_dp;
 385         }
 386 }
 387
 388 static const struct ddi_buf_trans *
 389 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 390 {
 391         if (IS_KBL_ULX(dev_priv)) {
 392                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 393                 return kbl_y_ddi_translations_dp;
 394         } else if (IS_KBL_ULT(dev_priv)) {
 395                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 396                 return kbl_u_ddi_translations_dp;
 397         } else {
 398                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 399                 return kbl_ddi_translations_dp;
 400         }
 401 }
 402
 403 static const struct ddi_buf_trans *
 404 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 405 {
 406         if (dev_priv->vbt.edp.low_vswing) {
 407                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 408                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 409                         return skl_y_ddi_translations_edp;
 410                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
 411                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 412                         return skl_u_ddi_translations_edp;
 413                 } else {
 414                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 415                         return skl_ddi_translations_edp;
 416                 }
 417         }
 418
 419         if (IS_KABYLAKE(dev_priv))
 420                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 421         else
 422                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 423 }
 424
 425 static const struct ddi_buf_trans *
 426 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 427 {
 428         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 429                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 430                 return skl_y_ddi_translations_hdmi;
 431         } else {
 432                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 433                 return skl_ddi_translations_hdmi;
 434         }
 435 }
 436
 437 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 438 {
 439         int n_hdmi_entries;
 440         int hdmi_level;
 441         int hdmi_default_entry;
 442
 443         hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 444
 445         if (IS_BROXTON(dev_priv))
 446                 return hdmi_level;
 447
 448         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 449                 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 450                 hdmi_default_entry = 8;
 451         } else if (IS_BROADWELL(dev_priv)) {
 452                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 453                 hdmi_default_entry = 7;
 454         } else if (IS_HASWELL(dev_priv)) {
 455                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 456                 hdmi_default_entry = 6;
 457         } else {
 458                 WARN(1, "ddi translation table missing\n");
 459                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 460                 hdmi_default_entry = 7;
 461         }
 462
 463         /* Choose a good default if VBT is badly populated */
 464         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 465             hdmi_level >= n_hdmi_entries)
 466                 hdmi_level = hdmi_default_entry;
 467
 468         return hdmi_level;
 469 }
 470
 471 /*
 472  * Starting with Haswell, DDI port buffers must be programmed with correct
 473  * values in advance. This function programs the correct values for
 474  * DP/eDP/FDI use cases.
 475  */
 476 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
 477 {
 478         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 479         u32 iboost_bit = 0;
 480         int i, n_dp_entries, n_edp_entries, size;
 481         enum port port = intel_ddi_get_encoder_port(encoder);
 482         const struct ddi_buf_trans *ddi_translations_fdi;
 483         const struct ddi_buf_trans *ddi_translations_dp;
 484         const struct ddi_buf_trans *ddi_translations_edp;
 485         const struct ddi_buf_trans *ddi_translations;
 486
 487         if (IS_BROXTON(dev_priv))
 488                 return;
 489
 490         if (IS_KABYLAKE(dev_priv)) {
 491                 ddi_translations_fdi = NULL;
 492                 ddi_translations_dp =
 493                                 kbl_get_buf_trans_dp(dev_priv, &n_dp_entries);
 494                 ddi_translations_edp =
 495                                 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
 496         } else if (IS_SKYLAKE(dev_priv)) {
 497                 ddi_translations_fdi = NULL;
 498                 ddi_translations_dp =
 499                                 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
 500                 ddi_translations_edp =
 501                                 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
 502         } else if (IS_BROADWELL(dev_priv)) {
 503                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 504                 ddi_translations_dp = bdw_ddi_translations_dp;
 505                 ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries);
 506                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 507         } else if (IS_HASWELL(dev_priv)) {
 508                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 509                 ddi_translations_dp = hsw_ddi_translations_dp;
 510                 ddi_translations_edp = hsw_ddi_translations_dp;
 511                 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 512         } else {
 513                 WARN(1, "ddi translation table missing\n");
 514                 ddi_translations_edp = bdw_ddi_translations_dp;
 515                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 516                 ddi_translations_dp = bdw_ddi_translations_dp;
 517                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 518                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 519         }
 520
 521         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 522                 /* If we're boosting the current, set bit 31 of trans1 */
 523                 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 524                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 525
 526                 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
 527                             port != PORT_A && port != PORT_E &&
 528                             n_edp_entries > 9))
 529                         n_edp_entries = 9;
 530         }
 531
 532         switch (encoder->type) {
 533         case INTEL_OUTPUT_EDP:
 534                 ddi_translations = ddi_translations_edp;
 535                 size = n_edp_entries;
 536                 break;
 537         case INTEL_OUTPUT_DP:
 538                 ddi_translations = ddi_translations_dp;
 539                 size = n_dp_entries;
 540                 break;
 541         case INTEL_OUTPUT_ANALOG:
 542                 ddi_translations = ddi_translations_fdi;
 543                 size = n_dp_entries;
 544                 break;
 545         default:
 546                 BUG();
 547         }
 548
 549         for (i = 0; i < size; i++) {
 550                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 551                            ddi_translations[i].trans1 | iboost_bit);
 552                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 553                            ddi_translations[i].trans2);
 554         }
 555 }
 556
 557 /*
 558  * Starting with Haswell, DDI port buffers must be programmed with correct
 559  * values in advance. This function programs the correct values for
 560  * HDMI/DVI use cases.
 561  */
 562 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
 563 {
 564         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 565         u32 iboost_bit = 0;
 566         int n_hdmi_entries, hdmi_level;
 567         enum port port = intel_ddi_get_encoder_port(encoder);
 568         const struct ddi_buf_trans *ddi_translations_hdmi;
 569
 570         if (IS_BROXTON(dev_priv))
 571                 return;
 572
 573         hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
 574
 575         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 576                 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 577
 578                 /* If we're boosting the current, set bit 31 of trans1 */
 579                 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 580                         iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 581         } else if (IS_BROADWELL(dev_priv)) {
 582                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 583                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 584         } else if (IS_HASWELL(dev_priv)) {
 585                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 586                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 587         } else {
 588                 WARN(1, "ddi translation table missing\n");
 589                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 590                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 591         }
 592
 593         /* Entry 9 is for HDMI: */
 594         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 595                    ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
 596         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 597                    ddi_translations_hdmi[hdmi_level].trans2);
 598 }
 599
 600 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 601                                     enum port port)
 602 {
 603         i915_reg_t reg = DDI_BUF_CTL(port);
 604         int i;
 605
 606         for (i = 0; i < 16; i++) {
 607                 udelay(1);
 608                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 609                         return;
 610         }
 611         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 612 }
 613
 614 static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
 615 {
 616         switch (pll->id) {
 617         case DPLL_ID_WRPLL1:
 618                 return PORT_CLK_SEL_WRPLL1;
 619         case DPLL_ID_WRPLL2:
 620                 return PORT_CLK_SEL_WRPLL2;
 621         case DPLL_ID_SPLL:
 622                 return PORT_CLK_SEL_SPLL;
 623         case DPLL_ID_LCPLL_810:
 624                 return PORT_CLK_SEL_LCPLL_810;
 625         case DPLL_ID_LCPLL_1350:
 626                 return PORT_CLK_SEL_LCPLL_1350;
 627         case DPLL_ID_LCPLL_2700:
 628                 return PORT_CLK_SEL_LCPLL_2700;
 629         default:
 630                 MISSING_CASE(pll->id);
 631                 return PORT_CLK_SEL_NONE;
 632         }
 633 }
 634
 635 /* Starting with Haswell, different DDI ports can work in FDI mode for
 636  * connection to the PCH-located connectors. For this, it is necessary to train
 637  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 638  *
 639  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 640  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 641  * DDI A (which is used for eDP)
 642  */
 643
 644 void hsw_fdi_link_train(struct drm_crtc *crtc)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         struct drm_i915_private *dev_priv = to_i915(dev);
 648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 649         struct intel_encoder *encoder;
 650         u32 temp, i, rx_ctl_val, ddi_pll_sel;
 651
 652         for_each_encoder_on_crtc(dev, crtc, encoder) {
 653                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
 654                 intel_prepare_dp_ddi_buffers(encoder);
 655         }
 656
 657         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 658          * mode set "sequence for CRT port" document:
 659          * - TP1 to TP2 time with the default value
 660          * - FDI delay to 90h
 661          *
 662          * WaFDIAutoLinkSetTimingOverrride:hsw
 663          */
 664         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 665                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 666                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 667
 668         /* Enable the PCH Receiver FDI PLL */
 669         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 670                      FDI_RX_PLL_ENABLE |
 671                      FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
 672         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 673         POSTING_READ(FDI_RX_CTL(PIPE_A));
 674         udelay(220);
 675
 676         /* Switch from Rawclk to PCDclk */
 677         rx_ctl_val |= FDI_PCDCLK;
 678         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 679
 680         /* Configure Port Clock Select */
 681         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(intel_crtc->config->shared_dpll);
 682         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
 683         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
 684
 685         /* Start the training iterating through available voltages and emphasis,
 686          * testing each value twice. */
 687         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 688                 /* Configure DP_TP_CTL with auto-training */
 689                 I915_WRITE(DP_TP_CTL(PORT_E),
 690                                         DP_TP_CTL_FDI_AUTOTRAIN |
 691                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 692                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 693                                         DP_TP_CTL_ENABLE);
 694
 695                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 696                  * DDI E does not support port reversal, the functionality is
 697                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 698                  * port reversal bit */
 699                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 700                            DDI_BUF_CTL_ENABLE |
 701                            ((intel_crtc->config->fdi_lanes - 1) << 1) |
 702                            DDI_BUF_TRANS_SELECT(i / 2));
 703                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 704
 705                 udelay(600);
 706
 707                 /* Program PCH FDI Receiver TU */
 708                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 709
 710                 /* Enable PCH FDI Receiver with auto-training */
 711                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 712                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 713                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 714
 715                 /* Wait for FDI receiver lane calibration */
 716                 udelay(30);
 717
 718                 /* Unset FDI_RX_MISC pwrdn lanes */
 719                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 720                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 721                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 722                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 723
 724                 /* Wait for FDI auto training time */
 725                 udelay(5);
 726
 727                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 728                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 729                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 730                         break;
 731                 }
 732
 733                 /*
 734                  * Leave things enabled even if we failed to train FDI.
 735                  * Results in less fireworks from the state checker.
 736                  */
 737                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
 738                         DRM_ERROR("FDI link training failed!\n");
 739                         break;
 740                 }
 741
 742                 rx_ctl_val &= ~FDI_RX_ENABLE;
 743                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 744                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 745
 746                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 747                 temp &= ~DDI_BUF_CTL_ENABLE;
 748                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 749                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 750
 751                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 752                 temp = I915_READ(DP_TP_CTL(PORT_E));
 753                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 754                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 755                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 756                 POSTING_READ(DP_TP_CTL(PORT_E));
 757
 758                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 759
 760                 /* Reset FDI_RX_MISC pwrdn lanes */
 761                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 762                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 763                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 764                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 765                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 766         }
 767
 768         /* Enable normal pixel sending for FDI */
 769         I915_WRITE(DP_TP_CTL(PORT_E),
 770                    DP_TP_CTL_FDI_AUTOTRAIN |
 771                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 772                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 773                    DP_TP_CTL_ENABLE);
 774 }
 775
 776 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 777 {
 778         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 779         struct intel_digital_port *intel_dig_port =
 780                 enc_to_dig_port(&encoder->base);
 781
 782         intel_dp->DP = intel_dig_port->saved_port_bits |
 783                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 784         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 785 }
 786
 787 static struct intel_encoder *
 788 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 789 {
 790         struct drm_device *dev = crtc->dev;
 791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 792         struct intel_encoder *intel_encoder, *ret = NULL;
 793         int num_encoders = 0;
 794
 795         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 796                 ret = intel_encoder;
 797                 num_encoders++;
 798         }
 799
 800         if (num_encoders != 1)
 801                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 802                      pipe_name(intel_crtc->pipe));
 803
 804         BUG_ON(ret == NULL);
 805         return ret;
 806 }
 807
 808 struct intel_encoder *
 809 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 810 {
 811         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 812         struct intel_encoder *ret = NULL;
 813         struct drm_atomic_state *state;
 814         struct drm_connector *connector;
 815         struct drm_connector_state *connector_state;
 816         int num_encoders = 0;
 817         int i;
 818
 819         state = crtc_state->base.state;
 820
 821         for_each_connector_in_state(state, connector, connector_state, i) {
 822                 if (connector_state->crtc != crtc_state->base.crtc)
 823                         continue;
 824
 825                 ret = to_intel_encoder(connector_state->best_encoder);
 826                 num_encoders++;
 827         }
 828
 829         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
 830              pipe_name(crtc->pipe));
 831
 832         BUG_ON(ret == NULL);
 833         return ret;
 834 }
 835
 836 #define LC_FREQ 2700
 837
 838 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 839                                    i915_reg_t reg)
 840 {
 841         int refclk = LC_FREQ;
 842         int n, p, r;
 843         u32 wrpll;
 844
 845         wrpll = I915_READ(reg);
 846         switch (wrpll & WRPLL_PLL_REF_MASK) {
 847         case WRPLL_PLL_SSC:
 848         case WRPLL_PLL_NON_SSC:
 849                 /*
 850                  * We could calculate spread here, but our checking
 851                  * code only cares about 5% accuracy, and spread is a max of
 852                  * 0.5% downspread.
 853                  */
 854                 refclk = 135;
 855                 break;
 856         case WRPLL_PLL_LCPLL:
 857                 refclk = LC_FREQ;
 858                 break;
 859         default:
 860                 WARN(1, "bad wrpll refclk\n");
 861                 return 0;
 862         }
 863
 864         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 865         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 866         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 867
 868         /* Convert to KHz, p & r have a fixed point portion */
 869         return (refclk * n * 100) / (p * r);
 870 }
 871
 872 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 873                                uint32_t dpll)
 874 {
 875         i915_reg_t cfgcr1_reg, cfgcr2_reg;
 876         uint32_t cfgcr1_val, cfgcr2_val;
 877         uint32_t p0, p1, p2, dco_freq;
 878
 879         cfgcr1_reg = DPLL_CFGCR1(dpll);
 880         cfgcr2_reg = DPLL_CFGCR2(dpll);
 881
 882         cfgcr1_val = I915_READ(cfgcr1_reg);
 883         cfgcr2_val = I915_READ(cfgcr2_reg);
 884
 885         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
 886         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
 887
 888         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
 889                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
 890         else
 891                 p1 = 1;
 892
 893
 894         switch (p0) {
 895         case DPLL_CFGCR2_PDIV_1:
 896                 p0 = 1;
 897                 break;
 898         case DPLL_CFGCR2_PDIV_2:
 899                 p0 = 2;
 900                 break;
 901         case DPLL_CFGCR2_PDIV_3:
 902                 p0 = 3;
 903                 break;
 904         case DPLL_CFGCR2_PDIV_7:
 905                 p0 = 7;
 906                 break;
 907         }
 908
 909         switch (p2) {
 910         case DPLL_CFGCR2_KDIV_5:
 911                 p2 = 5;
 912                 break;
 913         case DPLL_CFGCR2_KDIV_2:
 914                 p2 = 2;
 915                 break;
 916         case DPLL_CFGCR2_KDIV_3:
 917                 p2 = 3;
 918                 break;
 919         case DPLL_CFGCR2_KDIV_1:
 920                 p2 = 1;
 921                 break;
 922         }
 923
 924         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
 925
 926         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
 927                 1000) / 0x8000;
 928
 929         return dco_freq / (p0 * p1 * p2 * 5);
 930 }
 931
 932 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 933 {
 934         int dotclock;
 935
 936         if (pipe_config->has_pch_encoder)
 937                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 938                                                     &pipe_config->fdi_m_n);
 939         else if (intel_crtc_has_dp_encoder(pipe_config))
 940                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 941                                                     &pipe_config->dp_m_n);
 942         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
 943                 dotclock = pipe_config->port_clock * 2 / 3;
 944         else
 945                 dotclock = pipe_config->port_clock;
 946
 947         if (pipe_config->pixel_multiplier)
 948                 dotclock /= pipe_config->pixel_multiplier;
 949
 950         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 951 }
 952
 953 static void skl_ddi_clock_get(struct intel_encoder *encoder,
 954                                 struct intel_crtc_state *pipe_config)
 955 {
 956         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 957         int link_clock = 0;
 958         uint32_t dpll_ctl1, dpll;
 959
 960         dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
 961
 962         dpll_ctl1 = I915_READ(DPLL_CTRL1);
 963
 964         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
 965                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
 966         } else {
 967                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
 968                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
 969
 970                 switch (link_clock) {
 971                 case DPLL_CTRL1_LINK_RATE_810:
 972                         link_clock = 81000;
 973                         break;
 974                 case DPLL_CTRL1_LINK_RATE_1080:
 975                         link_clock = 108000;
 976                         break;
 977                 case DPLL_CTRL1_LINK_RATE_1350:
 978                         link_clock = 135000;
 979                         break;
 980                 case DPLL_CTRL1_LINK_RATE_1620:
 981                         link_clock = 162000;
 982                         break;
 983                 case DPLL_CTRL1_LINK_RATE_2160:
 984                         link_clock = 216000;
 985                         break;
 986                 case DPLL_CTRL1_LINK_RATE_2700:
 987                         link_clock = 270000;
 988                         break;
 989                 default:
 990                         WARN(1, "Unsupported link rate\n");
 991                         break;
 992                 }
 993                 link_clock *= 2;
 994         }
 995
 996         pipe_config->port_clock = link_clock;
 997
 998         ddi_dotclock_get(pipe_config);
 999 }
1000
1001 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1002                               struct intel_crtc_state *pipe_config)
1003 {
1004         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1005         int link_clock = 0;
1006         u32 val, pll;
1007
1008         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1009         switch (val & PORT_CLK_SEL_MASK) {
1010         case PORT_CLK_SEL_LCPLL_810:
1011                 link_clock = 81000;
1012                 break;
1013         case PORT_CLK_SEL_LCPLL_1350:
1014                 link_clock = 135000;
1015                 break;
1016         case PORT_CLK_SEL_LCPLL_2700:
1017                 link_clock = 270000;
1018                 break;
1019         case PORT_CLK_SEL_WRPLL1:
1020                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1021                 break;
1022         case PORT_CLK_SEL_WRPLL2:
1023                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1024                 break;
1025         case PORT_CLK_SEL_SPLL:
1026                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1027                 if (pll == SPLL_PLL_FREQ_810MHz)
1028                         link_clock = 81000;
1029                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1030                         link_clock = 135000;
1031                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1032                         link_clock = 270000;
1033                 else {
1034                         WARN(1, "bad spll freq\n");
1035                         return;
1036                 }
1037                 break;
1038         default:
1039                 WARN(1, "bad port clock sel\n");
1040                 return;
1041         }
1042
1043         pipe_config->port_clock = link_clock * 2;
1044
1045         ddi_dotclock_get(pipe_config);
1046 }
1047
1048 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1049                                 enum intel_dpll_id dpll)
1050 {
1051         struct intel_shared_dpll *pll;
1052         struct intel_dpll_hw_state *state;
1053         struct dpll clock;
1054
1055         /* For DDI ports we always use a shared PLL. */
1056         if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1057                 return 0;
1058
1059         pll = &dev_priv->shared_dplls[dpll];
1060         state = &pll->config.hw_state;
1061
1062         clock.m1 = 2;
1063         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1064         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1065                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1066         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1067         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1068         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1069
1070         return chv_calc_dpll_params(100000, &clock);
1071 }
1072
1073 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1074                                 struct intel_crtc_state *pipe_config)
1075 {
1076         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1077         enum port port = intel_ddi_get_encoder_port(encoder);
1078         uint32_t dpll = port;
1079
1080         pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1081
1082         ddi_dotclock_get(pipe_config);
1083 }
1084
1085 void intel_ddi_clock_get(struct intel_encoder *encoder,
1086                          struct intel_crtc_state *pipe_config)
1087 {
1088         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1089
1090         if (INTEL_GEN(dev_priv) <= 8)
1091                 hsw_ddi_clock_get(encoder, pipe_config);
1092         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1093                 skl_ddi_clock_get(encoder, pipe_config);
1094         else if (IS_BROXTON(dev_priv))
1095                 bxt_ddi_clock_get(encoder, pipe_config);
1096 }
1097
1098 static bool
1099 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1100                    struct intel_crtc_state *crtc_state,
1101                    struct intel_encoder *intel_encoder)
1102 {
1103         struct intel_shared_dpll *pll;
1104
1105         pll = intel_get_shared_dpll(intel_crtc, crtc_state,
1106                                     intel_encoder);
1107         if (!pll)
1108                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1109                                  pipe_name(intel_crtc->pipe));
1110
1111         return pll;
1112 }
1113
1114 static bool
1115 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1116                    struct intel_crtc_state *crtc_state,
1117                    struct intel_encoder *intel_encoder)
1118 {
1119         struct intel_shared_dpll *pll;
1120
1121         pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1122         if (pll == NULL) {
1123                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1124                                  pipe_name(intel_crtc->pipe));
1125                 return false;
1126         }
1127
1128         return true;
1129 }
1130
1131 static bool
1132 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1133                    struct intel_crtc_state *crtc_state,
1134                    struct intel_encoder *intel_encoder)
1135 {
1136         return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1137 }
1138
1139 /*
1140  * Tries to find a *shared* PLL for the CRTC and store it in
1141  * intel_crtc->ddi_pll_sel.
1142  *
1143  * For private DPLLs, compute_config() should do the selection for us. This
1144  * function should be folded into compute_config() eventually.
1145  */
1146 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1147                           struct intel_crtc_state *crtc_state)
1148 {
1149         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
1150         struct intel_encoder *intel_encoder =
1151                 intel_ddi_get_crtc_new_encoder(crtc_state);
1152
1153         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1154                 return skl_ddi_pll_select(intel_crtc, crtc_state,
1155                                           intel_encoder);
1156         else if (IS_BROXTON(dev_priv))
1157                 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1158                                           intel_encoder);
1159         else
1160                 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1161                                           intel_encoder);
1162 }
1163
1164 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1165 {
1166         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1168         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1169         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1170         int type = intel_encoder->type;
1171         uint32_t temp;
1172
1173         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1174                 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1175
1176                 temp = TRANS_MSA_SYNC_CLK;
1177                 switch (intel_crtc->config->pipe_bpp) {
1178                 case 18:
1179                         temp |= TRANS_MSA_6_BPC;
1180                         break;
1181                 case 24:
1182                         temp |= TRANS_MSA_8_BPC;
1183                         break;
1184                 case 30:
1185                         temp |= TRANS_MSA_10_BPC;
1186                         break;
1187                 case 36:
1188                         temp |= TRANS_MSA_12_BPC;
1189                         break;
1190                 default:
1191                         BUG();
1192                 }
1193                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1194         }
1195 }
1196
1197 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1198 {
1199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1200         struct drm_device *dev = crtc->dev;
1201         struct drm_i915_private *dev_priv = to_i915(dev);
1202         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1203         uint32_t temp;
1204         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1205         if (state == true)
1206                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1207         else
1208                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1209         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1210 }
1211
1212 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1213 {
1214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1215         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1216         struct drm_device *dev = crtc->dev;
1217         struct drm_i915_private *dev_priv = to_i915(dev);
1218         enum pipe pipe = intel_crtc->pipe;
1219         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1220         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1221         int type = intel_encoder->type;
1222         uint32_t temp;
1223
1224         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1225         temp = TRANS_DDI_FUNC_ENABLE;
1226         temp |= TRANS_DDI_SELECT_PORT(port);
1227
1228         switch (intel_crtc->config->pipe_bpp) {
1229         case 18:
1230                 temp |= TRANS_DDI_BPC_6;
1231                 break;
1232         case 24:
1233                 temp |= TRANS_DDI_BPC_8;
1234                 break;
1235         case 30:
1236                 temp |= TRANS_DDI_BPC_10;
1237                 break;
1238         case 36:
1239                 temp |= TRANS_DDI_BPC_12;
1240                 break;
1241         default:
1242                 BUG();
1243         }
1244
1245         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1246                 temp |= TRANS_DDI_PVSYNC;
1247         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1248                 temp |= TRANS_DDI_PHSYNC;
1249
1250         if (cpu_transcoder == TRANSCODER_EDP) {
1251                 switch (pipe) {
1252                 case PIPE_A:
1253                         /* On Haswell, can only use the always-on power well for
1254                          * eDP when not using the panel fitter, and when not
1255                          * using motion blur mitigation (which we don't
1256                          * support). */
1257                         if (IS_HASWELL(dev_priv) &&
1258                             (intel_crtc->config->pch_pfit.enabled ||
1259                              intel_crtc->config->pch_pfit.force_thru))
1260                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1261                         else
1262                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1263                         break;
1264                 case PIPE_B:
1265                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1266                         break;
1267                 case PIPE_C:
1268                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1269                         break;
1270                 default:
1271                         BUG();
1272                         break;
1273                 }
1274         }
1275
1276         if (type == INTEL_OUTPUT_HDMI) {
1277                 if (intel_crtc->config->has_hdmi_sink)
1278                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1279                 else
1280                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1281         } else if (type == INTEL_OUTPUT_ANALOG) {
1282                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1283                 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1284         } else if (type == INTEL_OUTPUT_DP ||
1285                    type == INTEL_OUTPUT_EDP) {
1286                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1287                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1288         } else if (type == INTEL_OUTPUT_DP_MST) {
1289                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1290                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1291         } else {
1292                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1293                      intel_encoder->type, pipe_name(pipe));
1294         }
1295
1296         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1297 }
1298
1299 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1300                                        enum transcoder cpu_transcoder)
1301 {
1302         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1303         uint32_t val = I915_READ(reg);
1304
1305         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1306         val |= TRANS_DDI_PORT_NONE;
1307         I915_WRITE(reg, val);
1308 }
1309
1310 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1311 {
1312         struct drm_device *dev = intel_connector->base.dev;
1313         struct drm_i915_private *dev_priv = to_i915(dev);
1314         struct intel_encoder *intel_encoder = intel_connector->encoder;
1315         int type = intel_connector->base.connector_type;
1316         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1317         enum pipe pipe = 0;
1318         enum transcoder cpu_transcoder;
1319         enum intel_display_power_domain power_domain;
1320         uint32_t tmp;
1321         bool ret;
1322
1323         power_domain = intel_display_port_power_domain(intel_encoder);
1324         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1325                 return false;
1326
1327         if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1328                 ret = false;
1329                 goto out;
1330         }
1331
1332         if (port == PORT_A)
1333                 cpu_transcoder = TRANSCODER_EDP;
1334         else
1335                 cpu_transcoder = (enum transcoder) pipe;
1336
1337         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1338
1339         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1340         case TRANS_DDI_MODE_SELECT_HDMI:
1341         case TRANS_DDI_MODE_SELECT_DVI:
1342                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1343                 break;
1344
1345         case TRANS_DDI_MODE_SELECT_DP_SST:
1346                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1347                       type == DRM_MODE_CONNECTOR_DisplayPort;
1348                 break;
1349
1350         case TRANS_DDI_MODE_SELECT_DP_MST:
1351                 /* if the transcoder is in MST state then
1352                  * connector isn't connected */
1353                 ret = false;
1354                 break;
1355
1356         case TRANS_DDI_MODE_SELECT_FDI:
1357                 ret = type == DRM_MODE_CONNECTOR_VGA;
1358                 break;
1359
1360         default:
1361                 ret = false;
1362                 break;
1363         }
1364
1365 out:
1366         intel_display_power_put(dev_priv, power_domain);
1367
1368         return ret;
1369 }
1370
1371 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1372                             enum pipe *pipe)
1373 {
1374         struct drm_device *dev = encoder->base.dev;
1375         struct drm_i915_private *dev_priv = to_i915(dev);
1376         enum port port = intel_ddi_get_encoder_port(encoder);
1377         enum intel_display_power_domain power_domain;
1378         u32 tmp;
1379         int i;
1380         bool ret;
1381
1382         power_domain = intel_display_port_power_domain(encoder);
1383         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1384                 return false;
1385
1386         ret = false;
1387
1388         tmp = I915_READ(DDI_BUF_CTL(port));
1389
1390         if (!(tmp & DDI_BUF_CTL_ENABLE))
1391                 goto out;
1392
1393         if (port == PORT_A) {
1394                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1395
1396                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1397                 case TRANS_DDI_EDP_INPUT_A_ON:
1398                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1399                         *pipe = PIPE_A;
1400                         break;
1401                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1402                         *pipe = PIPE_B;
1403                         break;
1404                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1405                         *pipe = PIPE_C;
1406                         break;
1407                 }
1408
1409                 ret = true;
1410
1411                 goto out;
1412         }
1413
1414         for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1415                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1416
1417                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1418                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1419                             TRANS_DDI_MODE_SELECT_DP_MST)
1420                                 goto out;
1421
1422                         *pipe = i;
1423                         ret = true;
1424
1425                         goto out;
1426                 }
1427         }
1428
1429         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1430
1431 out:
1432         if (ret && IS_BROXTON(dev_priv)) {
1433                 tmp = I915_READ(BXT_PHY_CTL(port));
1434                 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1435                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1436                         DRM_ERROR("Port %c enabled but PHY powered down? "
1437                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
1438         }
1439
1440         intel_display_power_put(dev_priv, power_domain);
1441
1442         return ret;
1443 }
1444
1445 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1446 {
1447         struct drm_crtc *crtc = &intel_crtc->base;
1448         struct drm_device *dev = crtc->dev;
1449         struct drm_i915_private *dev_priv = to_i915(dev);
1450         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1451         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1452         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1453
1454         if (cpu_transcoder != TRANSCODER_EDP)
1455                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1456                            TRANS_CLK_SEL_PORT(port));
1457 }
1458
1459 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1460 {
1461         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
1462         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1463
1464         if (cpu_transcoder != TRANSCODER_EDP)
1465                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1466                            TRANS_CLK_SEL_DISABLED);
1467 }
1468
1469 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1470                                 enum port port, uint8_t iboost)
1471 {
1472         u32 tmp;
1473
1474         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1475         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1476         if (iboost)
1477                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1478         else
1479                 tmp |= BALANCE_LEG_DISABLE(port);
1480         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1481 }
1482
1483 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1484 {
1485         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1486         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1487         enum port port = intel_dig_port->port;
1488         int type = encoder->type;
1489         const struct ddi_buf_trans *ddi_translations;
1490         uint8_t iboost;
1491         uint8_t dp_iboost, hdmi_iboost;
1492         int n_entries;
1493
1494         /* VBT may override standard boost values */
1495         dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1496         hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1497
1498         if (type == INTEL_OUTPUT_DP) {
1499                 if (dp_iboost) {
1500                         iboost = dp_iboost;
1501                 } else {
1502                         if (IS_KABYLAKE(dev_priv))
1503                                 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1504                                                                         &n_entries);
1505                         else
1506                                 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1507                                                                         &n_entries);
1508                         iboost = ddi_translations[level].i_boost;
1509                 }
1510         } else if (type == INTEL_OUTPUT_EDP) {
1511                 if (dp_iboost) {
1512                         iboost = dp_iboost;
1513                 } else {
1514                         ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1515
1516                         if (WARN_ON(port != PORT_A &&
1517                                     port != PORT_E && n_entries > 9))
1518                                 n_entries = 9;
1519
1520                         iboost = ddi_translations[level].i_boost;
1521                 }
1522         } else if (type == INTEL_OUTPUT_HDMI) {
1523                 if (hdmi_iboost) {
1524                         iboost = hdmi_iboost;
1525                 } else {
1526                         ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1527                         iboost = ddi_translations[level].i_boost;
1528                 }
1529         } else {
1530                 return;
1531         }
1532
1533         /* Make sure that the requested I_boost is valid */
1534         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1535                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1536                 return;
1537         }
1538
1539         _skl_ddi_set_iboost(dev_priv, port, iboost);
1540
1541         if (port == PORT_A && intel_dig_port->max_lanes == 4)
1542                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1543 }
1544
1545 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1546                                     u32 level, enum port port, int type)
1547 {
1548         const struct bxt_ddi_buf_trans *ddi_translations;
1549         u32 n_entries, i;
1550         uint32_t val;
1551
1552         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1553                 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1554                 ddi_translations = bxt_ddi_translations_edp;
1555         } else if (type == INTEL_OUTPUT_DP
1556                         || type == INTEL_OUTPUT_EDP) {
1557                 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1558                 ddi_translations = bxt_ddi_translations_dp;
1559         } else if (type == INTEL_OUTPUT_HDMI) {
1560                 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1561                 ddi_translations = bxt_ddi_translations_hdmi;
1562         } else {
1563                 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1564                                 type);
1565                 return;
1566         }
1567
1568         /* Check if default value has to be used */
1569         if (level >= n_entries ||
1570             (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1571                 for (i = 0; i < n_entries; i++) {
1572                         if (ddi_translations[i].default_index) {
1573                                 level = i;
1574                                 break;
1575                         }
1576                 }
1577         }
1578
1579         /*
1580          * While we write to the group register to program all lanes at once we
1581          * can read only lane registers and we pick lanes 0/1 for that.
1582          */
1583         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1584         val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1585         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1586
1587         val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1588         val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1589         val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1590                ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1591         I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1592
1593         val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1594         val &= ~SCALE_DCOMP_METHOD;
1595         if (ddi_translations[level].enable)
1596                 val |= SCALE_DCOMP_METHOD;
1597
1598         if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1599                 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1600
1601         I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1602
1603         val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1604         val &= ~DE_EMPHASIS;
1605         val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1606         I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1607
1608         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1609         val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1610         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1611 }
1612
1613 static uint32_t translate_signal_level(int signal_levels)
1614 {
1615         uint32_t level;
1616
1617         switch (signal_levels) {
1618         default:
1619                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1620                               signal_levels);
1621         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1622                 level = 0;
1623                 break;
1624         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1625                 level = 1;
1626                 break;
1627         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1628                 level = 2;
1629                 break;
1630         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1631                 level = 3;
1632                 break;
1633
1634         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1635                 level = 4;
1636                 break;
1637         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1638                 level = 5;
1639                 break;
1640         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1641                 level = 6;
1642                 break;
1643
1644         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1645                 level = 7;
1646                 break;
1647         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1648                 level = 8;
1649                 break;
1650
1651         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1652                 level = 9;
1653                 break;
1654         }
1655
1656         return level;
1657 }
1658
1659 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1660 {
1661         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1662         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
1663         struct intel_encoder *encoder = &dport->base;
1664         uint8_t train_set = intel_dp->train_set[0];
1665         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1666                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1667         enum port port = dport->port;
1668         uint32_t level;
1669
1670         level = translate_signal_level(signal_levels);
1671
1672         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1673                 skl_ddi_set_iboost(encoder, level);
1674         else if (IS_BROXTON(dev_priv))
1675                 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
1676
1677         return DDI_BUF_TRANS_SELECT(level);
1678 }
1679
1680 void intel_ddi_clk_select(struct intel_encoder *encoder,
1681                           struct intel_shared_dpll *pll)
1682 {
1683         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1684         enum port port = intel_ddi_get_encoder_port(encoder);
1685
1686         if (WARN_ON(!pll))
1687                 return;
1688
1689         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1690                 uint32_t val;
1691
1692                 /* DDI -> PLL mapping  */
1693                 val = I915_READ(DPLL_CTRL2);
1694
1695                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1696                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1697                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
1698                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1699
1700                 I915_WRITE(DPLL_CTRL2, val);
1701
1702         } else if (INTEL_INFO(dev_priv)->gen < 9) {
1703                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1704         }
1705 }
1706
1707 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
1708                                     int link_rate, uint32_t lane_count,
1709                                     struct intel_shared_dpll *pll,
1710                                     bool link_mst)
1711 {
1712         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1713         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1714         enum port port = intel_ddi_get_encoder_port(encoder);
1715
1716         intel_dp_set_link_params(intel_dp, link_rate, lane_count,
1717                                  link_mst);
1718         if (encoder->type == INTEL_OUTPUT_EDP)
1719                 intel_edp_panel_on(intel_dp);
1720
1721         intel_ddi_clk_select(encoder, pll);
1722         intel_prepare_dp_ddi_buffers(encoder);
1723         intel_ddi_init_dp_buf_reg(encoder);
1724         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1725         intel_dp_start_link_train(intel_dp);
1726         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
1727                 intel_dp_stop_link_train(intel_dp);
1728 }
1729
1730 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
1731                                       bool has_hdmi_sink,
1732                                       struct drm_display_mode *adjusted_mode,
1733                                       struct intel_shared_dpll *pll)
1734 {
1735         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1736         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1737         struct drm_encoder *drm_encoder = &encoder->base;
1738         enum port port = intel_ddi_get_encoder_port(encoder);
1739         int level = intel_ddi_hdmi_level(dev_priv, port);
1740
1741         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1742         intel_ddi_clk_select(encoder, pll);
1743         intel_prepare_hdmi_ddi_buffers(encoder);
1744         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1745                 skl_ddi_set_iboost(encoder, level);
1746         else if (IS_BROXTON(dev_priv))
1747                 bxt_ddi_vswing_sequence(dev_priv, level, port,
1748                                         INTEL_OUTPUT_HDMI);
1749
1750         intel_hdmi->set_infoframes(drm_encoder,
1751                                    has_hdmi_sink,
1752                                    adjusted_mode);
1753 }
1754
1755 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder,
1756                                  struct intel_crtc_state *pipe_config,
1757                                  struct drm_connector_state *conn_state)
1758 {
1759         struct drm_encoder *encoder = &intel_encoder->base;
1760         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1761         int type = intel_encoder->type;
1762
1763         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1764                 intel_ddi_pre_enable_dp(intel_encoder,
1765                                         crtc->config->port_clock,
1766                                         crtc->config->lane_count,
1767                                         crtc->config->shared_dpll,
1768                                         intel_crtc_has_type(crtc->config,
1769                                                             INTEL_OUTPUT_DP_MST));
1770         }
1771         if (type == INTEL_OUTPUT_HDMI) {
1772                 intel_ddi_pre_enable_hdmi(intel_encoder,
1773                                           crtc->config->has_hdmi_sink,
1774                                           &crtc->config->base.adjusted_mode,
1775                                           crtc->config->shared_dpll);
1776         }
1777 }
1778
1779 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
1780                                    struct intel_crtc_state *old_crtc_state,
1781                                    struct drm_connector_state *old_conn_state)
1782 {
1783         struct drm_encoder *encoder = &intel_encoder->base;
1784         struct drm_device *dev = encoder->dev;
1785         struct drm_i915_private *dev_priv = to_i915(dev);
1786         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1787         int type = intel_encoder->type;
1788         uint32_t val;
1789         bool wait = false;
1790
1791         /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
1792
1793         val = I915_READ(DDI_BUF_CTL(port));
1794         if (val & DDI_BUF_CTL_ENABLE) {
1795                 val &= ~DDI_BUF_CTL_ENABLE;
1796                 I915_WRITE(DDI_BUF_CTL(port), val);
1797                 wait = true;
1798         }
1799
1800         val = I915_READ(DP_TP_CTL(port));
1801         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1802         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1803         I915_WRITE(DP_TP_CTL(port), val);
1804
1805         if (wait)
1806                 intel_wait_ddi_buf_idle(dev_priv, port);
1807
1808         if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1809                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1810                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1811                 intel_edp_panel_vdd_on(intel_dp);
1812                 intel_edp_panel_off(intel_dp);
1813         }
1814
1815         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1816                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1817                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
1818         else if (INTEL_INFO(dev)->gen < 9)
1819                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1820
1821         if (type == INTEL_OUTPUT_HDMI) {
1822                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1823
1824                 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1825         }
1826 }
1827
1828 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1829                                 struct intel_crtc_state *old_crtc_state,
1830                                 struct drm_connector_state *old_conn_state)
1831 {
1832         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1833         uint32_t val;
1834
1835         /*
1836          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
1837          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
1838          * step 13 is the correct place for it. Step 18 is where it was
1839          * originally before the BUN.
1840          */
1841         val = I915_READ(FDI_RX_CTL(PIPE_A));
1842         val &= ~FDI_RX_ENABLE;
1843         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1844
1845         intel_ddi_post_disable(intel_encoder, old_crtc_state, old_conn_state);
1846
1847         val = I915_READ(FDI_RX_MISC(PIPE_A));
1848         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1849         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1850         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1851
1852         val = I915_READ(FDI_RX_CTL(PIPE_A));
1853         val &= ~FDI_PCDCLK;
1854         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1855
1856         val = I915_READ(FDI_RX_CTL(PIPE_A));
1857         val &= ~FDI_RX_PLL_ENABLE;
1858         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1859 }
1860
1861 static void intel_enable_ddi(struct intel_encoder *intel_encoder,
1862                              struct intel_crtc_state *pipe_config,
1863                              struct drm_connector_state *conn_state)
1864 {
1865         struct drm_encoder *encoder = &intel_encoder->base;
1866         struct drm_crtc *crtc = encoder->crtc;
1867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1868         struct drm_device *dev = encoder->dev;
1869         struct drm_i915_private *dev_priv = to_i915(dev);
1870         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1871         int type = intel_encoder->type;
1872
1873         if (type == INTEL_OUTPUT_HDMI) {
1874                 struct intel_digital_port *intel_dig_port =
1875                         enc_to_dig_port(encoder);
1876
1877                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1878                  * are ignored so nothing special needs to be done besides
1879                  * enabling the port.
1880                  */
1881                 I915_WRITE(DDI_BUF_CTL(port),
1882                            intel_dig_port->saved_port_bits |
1883                            DDI_BUF_CTL_ENABLE);
1884         } else if (type == INTEL_OUTPUT_EDP) {
1885                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1886
1887                 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1888                         intel_dp_stop_link_train(intel_dp);
1889
1890                 intel_edp_backlight_on(intel_dp);
1891                 intel_psr_enable(intel_dp);
1892                 intel_edp_drrs_enable(intel_dp, pipe_config);
1893         }
1894
1895         if (intel_crtc->config->has_audio) {
1896                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1897                 intel_audio_codec_enable(intel_encoder);
1898         }
1899 }
1900
1901 static void intel_disable_ddi(struct intel_encoder *intel_encoder,
1902                               struct intel_crtc_state *old_crtc_state,
1903                               struct drm_connector_state *old_conn_state)
1904 {
1905         struct drm_encoder *encoder = &intel_encoder->base;
1906         struct drm_crtc *crtc = encoder->crtc;
1907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1908         int type = intel_encoder->type;
1909         struct drm_device *dev = encoder->dev;
1910         struct drm_i915_private *dev_priv = to_i915(dev);
1911
1912         if (intel_crtc->config->has_audio) {
1913                 intel_audio_codec_disable(intel_encoder);
1914                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1915         }
1916
1917         if (type == INTEL_OUTPUT_EDP) {
1918                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1919
1920                 intel_edp_drrs_disable(intel_dp, old_crtc_state);
1921                 intel_psr_disable(intel_dp);
1922                 intel_edp_backlight_off(intel_dp);
1923         }
1924 }
1925
1926 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1927                             enum dpio_phy phy)
1928 {
1929         enum port port;
1930
1931         if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
1932                 return false;
1933
1934         if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1935              (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
1936                 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
1937                                  phy);
1938
1939                 return false;
1940         }
1941
1942         if (phy == DPIO_PHY1 &&
1943             !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
1944                 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
1945
1946                 return false;
1947         }
1948
1949         if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
1950                 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
1951                                  phy);
1952
1953                 return false;
1954         }
1955
1956         for_each_port_masked(port,
1957                              phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
1958                                                 BIT(PORT_A)) {
1959                 u32 tmp = I915_READ(BXT_PHY_CTL(port));
1960
1961                 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
1962                         DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
1963                                          "for port %c powered down "
1964                                          "(PHY_CTL %08x)\n",
1965                                          phy, port_name(port), tmp);
1966
1967                         return false;
1968                 }
1969         }
1970
1971         return true;
1972 }
1973
1974 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1975 {
1976         u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
1977
1978         return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1979 }
1980
1981 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
1982                                   enum dpio_phy phy)
1983 {
1984         if (intel_wait_for_register(dev_priv,
1985                                     BXT_PORT_REF_DW3(phy),
1986                                     GRC_DONE, GRC_DONE,
1987                                     10))
1988                 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
1989 }
1990
1991 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1992 {
1993         u32 val;
1994
1995         if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
1996                 /* Still read out the GRC value for state verification */
1997                 if (phy == DPIO_PHY0)
1998                         dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
1999
2000                 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
2001                         DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
2002                                          "won't reprogram it\n", phy);
2003
2004                         return;
2005                 }
2006
2007                 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
2008                                  "force reprogramming it\n", phy);
2009         }
2010
2011         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2012         val |= GT_DISPLAY_POWER_ON(phy);
2013         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2014
2015         /*
2016          * The PHY registers start out inaccessible and respond to reads with
2017          * all 1s.  Eventually they become accessible as they power up, then
2018          * the reserved bit will give the default 0.  Poll on the reserved bit
2019          * becoming 0 to find when the PHY is accessible.
2020          * HW team confirmed that the time to reach phypowergood status is
2021          * anywhere between 50 us and 100us.
2022          */
2023         if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
2024                 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
2025                 DRM_ERROR("timeout during PHY%d power on\n", phy);
2026         }
2027
2028         /* Program PLL Rcomp code offset */
2029         val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2030         val &= ~IREF0RC_OFFSET_MASK;
2031         val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2032         I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2033
2034         val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2035         val &= ~IREF1RC_OFFSET_MASK;
2036         val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2037         I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2038
2039         /* Program power gating */
2040         val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2041         val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2042                 SUS_CLK_CONFIG;
2043         I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2044
2045         if (phy == DPIO_PHY0) {
2046                 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2047                 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2048                 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2049         }
2050
2051         val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2052         val &= ~OCL2_LDOFUSE_PWR_DIS;
2053         /*
2054          * On PHY1 disable power on the second channel, since no port is
2055          * connected there. On PHY0 both channels have a port, so leave it
2056          * enabled.
2057          * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2058          * power down the second channel on PHY0 as well.
2059          *
2060          * FIXME: Clarify programming of the following, the register is
2061          * read-only with bit 6 fixed at 0 at least in stepping A.
2062          */
2063         if (phy == DPIO_PHY1)
2064                 val |= OCL2_LDOFUSE_PWR_DIS;
2065         I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2066
2067         if (phy == DPIO_PHY0) {
2068                 uint32_t grc_code;
2069                 /*
2070                  * PHY0 isn't connected to an RCOMP resistor so copy over
2071                  * the corresponding calibrated value from PHY1, and disable
2072                  * the automatic calibration on PHY0.
2073                  */
2074                 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
2075                 grc_code = val << GRC_CODE_FAST_SHIFT |
2076                            val << GRC_CODE_SLOW_SHIFT |
2077                            val;
2078                 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2079
2080                 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2081                 val |= GRC_DIS | GRC_RDY_OVRD;
2082                 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2083         }
2084
2085         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2086         val |= COMMON_RESET_DIS;
2087         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2088
2089         if (phy == DPIO_PHY1)
2090                 bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
2091 }
2092
2093 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
2094 {
2095         uint32_t val;
2096
2097         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2098         val &= ~COMMON_RESET_DIS;
2099         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2100
2101         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2102         val &= ~GT_DISPLAY_POWER_ON(phy);
2103         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2104 }
2105
2106 static bool __printf(6, 7)
2107 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2108                        i915_reg_t reg, u32 mask, u32 expected,
2109                        const char *reg_fmt, ...)
2110 {
2111         struct va_format vaf;
2112         va_list args;
2113         u32 val;
2114
2115         val = I915_READ(reg);
2116         if ((val & mask) == expected)
2117                 return true;
2118
2119         va_start(args, reg_fmt);
2120         vaf.fmt = reg_fmt;
2121         vaf.va = &args;
2122
2123         DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
2124                          "current %08x, expected %08x (mask %08x)\n",
2125                          phy, &vaf, reg.reg, val, (val & ~mask) | expected,
2126                          mask);
2127
2128         va_end(args);
2129
2130         return false;
2131 }
2132
2133 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
2134                               enum dpio_phy phy)
2135 {
2136         uint32_t mask;
2137         bool ok;
2138
2139 #define _CHK(reg, mask, exp, fmt, ...)                                  \
2140         __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,      \
2141                                ## __VA_ARGS__)
2142
2143         if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
2144                 return false;
2145
2146         ok = true;
2147
2148         /* PLL Rcomp code offset */
2149         ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
2150                     IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
2151                     "BXT_PORT_CL1CM_DW9(%d)", phy);
2152         ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
2153                     IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
2154                     "BXT_PORT_CL1CM_DW10(%d)", phy);
2155
2156         /* Power gating */
2157         mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
2158         ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
2159                     "BXT_PORT_CL1CM_DW28(%d)", phy);
2160
2161         if (phy == DPIO_PHY0)
2162                 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
2163                            DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
2164                            "BXT_PORT_CL2CM_DW6_BC");
2165
2166         /*
2167          * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
2168          * at least on stepping A this bit is read-only and fixed at 0.
2169          */
2170
2171         if (phy == DPIO_PHY0) {
2172                 u32 grc_code = dev_priv->bxt_phy_grc;
2173
2174                 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
2175                            grc_code << GRC_CODE_SLOW_SHIFT |
2176                            grc_code;
2177                 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
2178                        GRC_CODE_NOM_MASK;
2179                 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
2180                             "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
2181
2182                 mask = GRC_DIS | GRC_RDY_OVRD;
2183                 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
2184                             "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
2185         }
2186
2187         return ok;
2188 #undef _CHK
2189 }
2190
2191 static uint8_t
2192 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
2193                                      struct intel_crtc_state *pipe_config)
2194 {
2195         switch (pipe_config->lane_count) {
2196         case 1:
2197                 return 0;
2198         case 2:
2199                 return BIT(2) | BIT(0);
2200         case 4:
2201                 return BIT(3) | BIT(2) | BIT(0);
2202         default:
2203                 MISSING_CASE(pipe_config->lane_count);
2204
2205                 return 0;
2206         }
2207 }
2208
2209 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2210                                    struct intel_crtc_state *pipe_config,
2211                                    struct drm_connector_state *conn_state)
2212 {
2213         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2214         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2215         enum port port = dport->port;
2216         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2217         int lane;
2218
2219         for (lane = 0; lane < 4; lane++) {
2220                 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2221
2222                 /*
2223                  * Note that on CHV this flag is called UPAR, but has
2224                  * the same function.
2225                  */
2226                 val &= ~LATENCY_OPTIM;
2227                 if (intel_crtc->config->lane_lat_optim_mask & BIT(lane))
2228                         val |= LATENCY_OPTIM;
2229
2230                 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2231         }
2232 }
2233
2234 static uint8_t
2235 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
2236 {
2237         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2238         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2239         enum port port = dport->port;
2240         int lane;
2241         uint8_t mask;
2242
2243         mask = 0;
2244         for (lane = 0; lane < 4; lane++) {
2245                 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2246
2247                 if (val & LATENCY_OPTIM)
2248                         mask |= BIT(lane);
2249         }
2250
2251         return mask;
2252 }
2253
2254 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2255 {
2256         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2257         struct drm_i915_private *dev_priv =
2258                 to_i915(intel_dig_port->base.base.dev);
2259         enum port port = intel_dig_port->port;
2260         uint32_t val;
2261         bool wait = false;
2262
2263         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2264                 val = I915_READ(DDI_BUF_CTL(port));
2265                 if (val & DDI_BUF_CTL_ENABLE) {
2266                         val &= ~DDI_BUF_CTL_ENABLE;
2267                         I915_WRITE(DDI_BUF_CTL(port), val);
2268                         wait = true;
2269                 }
2270
2271                 val = I915_READ(DP_TP_CTL(port));
2272                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2273                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2274                 I915_WRITE(DP_TP_CTL(port), val);
2275                 POSTING_READ(DP_TP_CTL(port));
2276
2277                 if (wait)
2278                         intel_wait_ddi_buf_idle(dev_priv, port);
2279         }
2280
2281         val = DP_TP_CTL_ENABLE |
2282               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2283         if (intel_dp->link_mst)
2284                 val |= DP_TP_CTL_MODE_MST;
2285         else {
2286                 val |= DP_TP_CTL_MODE_SST;
2287                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2288                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2289         }
2290         I915_WRITE(DP_TP_CTL(port), val);
2291         POSTING_READ(DP_TP_CTL(port));
2292
2293         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2294         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2295         POSTING_READ(DDI_BUF_CTL(port));
2296
2297         udelay(600);
2298 }
2299
2300 void intel_ddi_get_config(struct intel_encoder *encoder,
2301                           struct intel_crtc_state *pipe_config)
2302 {
2303         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2304         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2305         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2306         struct intel_hdmi *intel_hdmi;
2307         u32 temp, flags = 0;
2308
2309         /* XXX: DSI transcoder paranoia */
2310         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2311                 return;
2312
2313         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2314         if (temp & TRANS_DDI_PHSYNC)
2315                 flags |= DRM_MODE_FLAG_PHSYNC;
2316         else
2317                 flags |= DRM_MODE_FLAG_NHSYNC;
2318         if (temp & TRANS_DDI_PVSYNC)
2319                 flags |= DRM_MODE_FLAG_PVSYNC;
2320         else
2321                 flags |= DRM_MODE_FLAG_NVSYNC;
2322
2323         pipe_config->base.adjusted_mode.flags |= flags;
2324
2325         switch (temp & TRANS_DDI_BPC_MASK) {
2326         case TRANS_DDI_BPC_6:
2327                 pipe_config->pipe_bpp = 18;
2328                 break;
2329         case TRANS_DDI_BPC_8:
2330                 pipe_config->pipe_bpp = 24;
2331                 break;
2332         case TRANS_DDI_BPC_10:
2333                 pipe_config->pipe_bpp = 30;
2334                 break;
2335         case TRANS_DDI_BPC_12:
2336                 pipe_config->pipe_bpp = 36;
2337                 break;
2338         default:
2339                 break;
2340         }
2341
2342         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2343         case TRANS_DDI_MODE_SELECT_HDMI:
2344                 pipe_config->has_hdmi_sink = true;
2345                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2346
2347                 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2348                         pipe_config->has_infoframe = true;
2349                 /* fall through */
2350         case TRANS_DDI_MODE_SELECT_DVI:
2351                 pipe_config->lane_count = 4;
2352                 break;
2353         case TRANS_DDI_MODE_SELECT_FDI:
2354                 break;
2355         case TRANS_DDI_MODE_SELECT_DP_SST:
2356         case TRANS_DDI_MODE_SELECT_DP_MST:
2357                 pipe_config->lane_count =
2358                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2359                 intel_dp_get_m_n(intel_crtc, pipe_config);
2360                 break;
2361         default:
2362                 break;
2363         }
2364
2365         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2366                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2367                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2368                         pipe_config->has_audio = true;
2369         }
2370
2371         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2372             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2373                 /*
2374                  * This is a big fat ugly hack.
2375                  *
2376                  * Some machines in UEFI boot mode provide us a VBT that has 18
2377                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2378                  * unknown we fail to light up. Yet the same BIOS boots up with
2379                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2380                  * max, not what it tells us to use.
2381                  *
2382                  * Note: This will still be broken if the eDP panel is not lit
2383                  * up by the BIOS, and thus we can't get the mode at module
2384                  * load.
2385                  */
2386                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2387                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2388                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2389         }
2390
2391         intel_ddi_clock_get(encoder, pipe_config);
2392
2393         if (IS_BROXTON(dev_priv))
2394                 pipe_config->lane_lat_optim_mask =
2395                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2396 }
2397
2398 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2399                                      struct intel_crtc_state *pipe_config,
2400                                      struct drm_connector_state *conn_state)
2401 {
2402         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2403         int type = encoder->type;
2404         int port = intel_ddi_get_encoder_port(encoder);
2405         int ret;
2406
2407         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2408
2409         if (port == PORT_A)
2410                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2411
2412         if (type == INTEL_OUTPUT_HDMI)
2413                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2414         else
2415                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2416
2417         if (IS_BROXTON(dev_priv) && ret)
2418                 pipe_config->lane_lat_optim_mask =
2419                         bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2420                                                              pipe_config);
2421
2422         return ret;
2423
2424 }
2425
2426 static const struct drm_encoder_funcs intel_ddi_funcs = {
2427         .reset = intel_dp_encoder_reset,
2428         .destroy = intel_dp_encoder_destroy,
2429 };
2430
2431 static struct intel_connector *
2432 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2433 {
2434         struct intel_connector *connector;
2435         enum port port = intel_dig_port->port;
2436
2437         connector = intel_connector_alloc();
2438         if (!connector)
2439                 return NULL;
2440
2441         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2442         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2443                 kfree(connector);
2444                 return NULL;
2445         }
2446
2447         return connector;
2448 }
2449
2450 static struct intel_connector *
2451 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2452 {
2453         struct intel_connector *connector;
2454         enum port port = intel_dig_port->port;
2455
2456         connector = intel_connector_alloc();
2457         if (!connector)
2458                 return NULL;
2459
2460         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2461         intel_hdmi_init_connector(intel_dig_port, connector);
2462
2463         return connector;
2464 }
2465
2466 struct intel_shared_dpll *
2467 intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
2468 {
2469         struct intel_connector *connector = intel_dp->attached_connector;
2470         struct intel_encoder *encoder = connector->encoder;
2471         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2472         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2473         struct intel_shared_dpll *pll = NULL;
2474         struct intel_shared_dpll_config tmp_pll_config;
2475         enum intel_dpll_id dpll_id;
2476
2477         if (IS_BROXTON(dev_priv)) {
2478                 dpll_id =  (enum intel_dpll_id)dig_port->port;
2479                 /*
2480                  * Select the required PLL. This works for platforms where
2481                  * there is no shared DPLL.
2482                  */
2483                 pll = &dev_priv->shared_dplls[dpll_id];
2484                 if (WARN_ON(pll->active_mask)) {
2485
2486                         DRM_ERROR("Shared DPLL in use. active_mask:%x\n",
2487                                   pll->active_mask);
2488                         return NULL;
2489                 }
2490                 tmp_pll_config = pll->config;
2491                 if (!bxt_ddi_dp_set_dpll_hw_state(clock,
2492                                                   &pll->config.hw_state)) {
2493                         DRM_ERROR("Could not setup DPLL\n");
2494                         pll->config = tmp_pll_config;
2495                         return NULL;
2496                 }
2497         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2498                 pll = skl_find_link_pll(dev_priv, clock);
2499         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2500                 pll = hsw_ddi_dp_get_dpll(encoder, clock);
2501         }
2502         return pll;
2503 }
2504
2505 void intel_ddi_init(struct drm_device *dev, enum port port)
2506 {
2507         struct drm_i915_private *dev_priv = to_i915(dev);
2508         struct intel_digital_port *intel_dig_port;
2509         struct intel_encoder *intel_encoder;
2510         struct drm_encoder *encoder;
2511         bool init_hdmi, init_dp, init_lspcon = false;
2512         int max_lanes;
2513
2514         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2515                 switch (port) {
2516                 case PORT_A:
2517                         max_lanes = 4;
2518                         break;
2519                 case PORT_E:
2520                         max_lanes = 0;
2521                         break;
2522                 default:
2523                         max_lanes = 4;
2524                         break;
2525                 }
2526         } else {
2527                 switch (port) {
2528                 case PORT_A:
2529                         max_lanes = 2;
2530                         break;
2531                 case PORT_E:
2532                         max_lanes = 2;
2533                         break;
2534                 default:
2535                         max_lanes = 4;
2536                         break;
2537                 }
2538         }
2539
2540         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2541                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2542         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2543
2544         if (intel_bios_is_lspcon_present(dev_priv, port)) {
2545                 /*
2546                  * Lspcon device needs to be driven with DP connector
2547                  * with special detection sequence. So make sure DP
2548                  * is initialized before lspcon.
2549                  */
2550                 init_dp = true;
2551                 init_lspcon = true;
2552                 init_hdmi = false;
2553                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2554         }
2555
2556         if (!init_dp && !init_hdmi) {
2557                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2558                               port_name(port));
2559                 return;
2560         }
2561
2562         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2563         if (!intel_dig_port)
2564                 return;
2565
2566         intel_encoder = &intel_dig_port->base;
2567         encoder = &intel_encoder->base;
2568
2569         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2570                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2571
2572         intel_encoder->compute_config = intel_ddi_compute_config;
2573         intel_encoder->enable = intel_enable_ddi;
2574         if (IS_BROXTON(dev_priv))
2575                 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2576         intel_encoder->pre_enable = intel_ddi_pre_enable;
2577         intel_encoder->disable = intel_disable_ddi;
2578         intel_encoder->post_disable = intel_ddi_post_disable;
2579         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2580         intel_encoder->get_config = intel_ddi_get_config;
2581         intel_encoder->suspend = intel_dp_encoder_suspend;
2582
2583         intel_dig_port->port = port;
2584         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2585                                           (DDI_BUF_PORT_REVERSAL |
2586                                            DDI_A_4_LANES);
2587
2588         /*
2589          * Bspec says that DDI_A_4_LANES is the only supported configuration
2590          * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
2591          * wasn't lit up at boot.  Force this bit on in our internal
2592          * configuration so that we use the proper lane count for our
2593          * calculations.
2594          */
2595         if (IS_BROXTON(dev_priv) && port == PORT_A) {
2596                 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2597                         DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2598                         intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2599                         max_lanes = 4;
2600                 }
2601         }
2602
2603         intel_dig_port->max_lanes = max_lanes;
2604
2605         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2606         intel_encoder->port = port;
2607         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2608         intel_encoder->cloneable = 0;
2609
2610         if (init_dp) {
2611                 if (!intel_ddi_init_dp_connector(intel_dig_port))
2612                         goto err;
2613
2614                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2615                 /*
2616                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2617                  * interrupts to check the external panel connection.
2618                  */
2619                 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && port == PORT_B)
2620                         dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2621                 else
2622                         dev_priv->hotplug.irq_port[port] = intel_dig_port;
2623         }
2624
2625         /* In theory we don't need the encoder->type check, but leave it just in
2626          * case we have some really bad VBTs... */
2627         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2628                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2629                         goto err;
2630         }
2631
2632         if (init_lspcon) {
2633                 if (lspcon_init(intel_dig_port))
2634                         /* TODO: handle hdmi info frame part */
2635                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2636                                 port_name(port));
2637                 else
2638                         /*
2639                          * LSPCON init faied, but DP init was success, so
2640                          * lets try to drive as DP++ port.
2641                          */
2642                         DRM_ERROR("LSPCON init failed on port %c\n",
2643                                 port_name(port));
2644         }
2645
2646         return;
2647
2648 err:
2649         drm_encoder_cleanup(encoder);
2650         kfree(intel_dig_port);
2651 }