drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: CDCLK / RAWCLK
  28  *
  29  * The display engine uses several different clocks to do its work. There
  30  * are two main clocks involved that aren't directly related to the actual
  31  * pixel clock or any symbol/bit clock of the actual output port. These
  32  * are the core display clock (CDCLK) and RAWCLK.
  33  *
  34  * CDCLK clocks most of the display pipe logic, and thus its frequency
  35  * must be high enough to support the rate at which pixels are flowing
  36  * through the pipes. Downscaling must also be accounted as that increases
  37  * the effective pixel rate.
  38  *
  39  * On several platforms the CDCLK frequency can be changed dynamically
  40  * to minimize power consumption for a given display configuration.
  41  * Typically changes to the CDCLK frequency require all the display pipes
  42  * to be shut down while the frequency is being changed.
  43  *
  44  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  45  * DMC will not change the active CDCLK frequency however, so that part
  46  * will still be performed by the driver directly.
  47  *
  48  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  49  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  50  * really need to know about RAWCLK is its frequency so that various
  51  * dividers can be programmed correctly.
  52  */
  53
  54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  55                                    struct intel_cdclk_state *cdclk_state)
  56 {
  57         cdclk_state->cdclk = 133333;
  58 }
  59
  60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  61                                    struct intel_cdclk_state *cdclk_state)
  62 {
  63         cdclk_state->cdclk = 200000;
  64 }
  65
  66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  67                                    struct intel_cdclk_state *cdclk_state)
  68 {
  69         cdclk_state->cdclk = 266667;
  70 }
  71
  72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  73                                    struct intel_cdclk_state *cdclk_state)
  74 {
  75         cdclk_state->cdclk = 333333;
  76 }
  77
  78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  79                                    struct intel_cdclk_state *cdclk_state)
  80 {
  81         cdclk_state->cdclk = 400000;
  82 }
  83
  84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  85                                    struct intel_cdclk_state *cdclk_state)
  86 {
  87         cdclk_state->cdclk = 450000;
  88 }
  89
  90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  91                            struct intel_cdclk_state *cdclk_state)
  92 {
  93         struct pci_dev *pdev = dev_priv->drm.pdev;
  94         u16 hpllcc = 0;
  95
  96         /*
  97          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  98          * encoding is different :(
  99          * FIXME is this the right way to detect 852GM/852GMV?
 100          */
 101         if (pdev->revision == 0x1) {
 102                 cdclk_state->cdclk = 133333;
 103                 return;
 104         }
 105
 106         pci_bus_read_config_word(pdev->bus,
 107                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 108
 109         /* Assume that the hardware is in the high speed state.  This
 110          * should be the default.
 111          */
 112         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 113         case GC_CLOCK_133_200:
 114         case GC_CLOCK_133_200_2:
 115         case GC_CLOCK_100_200:
 116                 cdclk_state->cdclk = 200000;
 117                 break;
 118         case GC_CLOCK_166_250:
 119                 cdclk_state->cdclk = 250000;
 120                 break;
 121         case GC_CLOCK_100_133:
 122                 cdclk_state->cdclk = 133333;
 123                 break;
 124         case GC_CLOCK_133_266:
 125         case GC_CLOCK_133_266_2:
 126         case GC_CLOCK_166_266:
 127                 cdclk_state->cdclk = 266667;
 128                 break;
 129         }
 130 }
 131
 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 133                              struct intel_cdclk_state *cdclk_state)
 134 {
 135         struct pci_dev *pdev = dev_priv->drm.pdev;
 136         u16 gcfgc = 0;
 137
 138         pci_read_config_word(pdev, GCFGC, &gcfgc);
 139
 140         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 141                 cdclk_state->cdclk = 133333;
 142                 return;
 143         }
 144
 145         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 146         case GC_DISPLAY_CLOCK_333_320_MHZ:
 147                 cdclk_state->cdclk = 333333;
 148                 break;
 149         default:
 150         case GC_DISPLAY_CLOCK_190_200_MHZ:
 151                 cdclk_state->cdclk = 190000;
 152                 break;
 153         }
 154 }
 155
 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 157                              struct intel_cdclk_state *cdclk_state)
 158 {
 159         struct pci_dev *pdev = dev_priv->drm.pdev;
 160         u16 gcfgc = 0;
 161
 162         pci_read_config_word(pdev, GCFGC, &gcfgc);
 163
 164         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 165                 cdclk_state->cdclk = 133333;
 166                 return;
 167         }
 168
 169         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 170         case GC_DISPLAY_CLOCK_333_320_MHZ:
 171                 cdclk_state->cdclk = 320000;
 172                 break;
 173         default:
 174         case GC_DISPLAY_CLOCK_190_200_MHZ:
 175                 cdclk_state->cdclk = 200000;
 176                 break;
 177         }
 178 }
 179
 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         static const unsigned int blb_vco[8] = {
 183                 [0] = 3200000,
 184                 [1] = 4000000,
 185                 [2] = 5333333,
 186                 [3] = 4800000,
 187                 [4] = 6400000,
 188         };
 189         static const unsigned int pnv_vco[8] = {
 190                 [0] = 3200000,
 191                 [1] = 4000000,
 192                 [2] = 5333333,
 193                 [3] = 4800000,
 194                 [4] = 2666667,
 195         };
 196         static const unsigned int cl_vco[8] = {
 197                 [0] = 3200000,
 198                 [1] = 4000000,
 199                 [2] = 5333333,
 200                 [3] = 6400000,
 201                 [4] = 3333333,
 202                 [5] = 3566667,
 203                 [6] = 4266667,
 204         };
 205         static const unsigned int elk_vco[8] = {
 206                 [0] = 3200000,
 207                 [1] = 4000000,
 208                 [2] = 5333333,
 209                 [3] = 4800000,
 210         };
 211         static const unsigned int ctg_vco[8] = {
 212                 [0] = 3200000,
 213                 [1] = 4000000,
 214                 [2] = 5333333,
 215                 [3] = 6400000,
 216                 [4] = 2666667,
 217                 [5] = 4266667,
 218         };
 219         const unsigned int *vco_table;
 220         unsigned int vco;
 221         uint8_t tmp = 0;
 222
 223         /* FIXME other chipsets? */
 224         if (IS_GM45(dev_priv))
 225                 vco_table = ctg_vco;
 226         else if (IS_G45(dev_priv))
 227                 vco_table = elk_vco;
 228         else if (IS_I965GM(dev_priv))
 229                 vco_table = cl_vco;
 230         else if (IS_PINEVIEW(dev_priv))
 231                 vco_table = pnv_vco;
 232         else if (IS_G33(dev_priv))
 233                 vco_table = blb_vco;
 234         else
 235                 return 0;
 236
 237         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 238
 239         vco = vco_table[tmp & 0x7];
 240         if (vco == 0)
 241                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 242         else
 243                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 244
 245         return vco;
 246 }
 247
 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 249                           struct intel_cdclk_state *cdclk_state)
 250 {
 251         struct pci_dev *pdev = dev_priv->drm.pdev;
 252         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
 253         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
 254         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
 255         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
 256         const uint8_t *div_table;
 257         unsigned int cdclk_sel;
 258         uint16_t tmp = 0;
 259
 260         cdclk_state->vco = intel_hpll_vco(dev_priv);
 261
 262         pci_read_config_word(pdev, GCFGC, &tmp);
 263
 264         cdclk_sel = (tmp >> 4) & 0x7;
 265
 266         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 267                 goto fail;
 268
 269         switch (cdclk_state->vco) {
 270         case 3200000:
 271                 div_table = div_3200;
 272                 break;
 273         case 4000000:
 274                 div_table = div_4000;
 275                 break;
 276         case 4800000:
 277                 div_table = div_4800;
 278                 break;
 279         case 5333333:
 280                 div_table = div_5333;
 281                 break;
 282         default:
 283                 goto fail;
 284         }
 285
 286         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 287                                                div_table[cdclk_sel]);
 288         return;
 289
 290 fail:
 291         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 292                   cdclk_state->vco, tmp);
 293         cdclk_state->cdclk = 190476;
 294 }
 295
 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 297                           struct intel_cdclk_state *cdclk_state)
 298 {
 299         struct pci_dev *pdev = dev_priv->drm.pdev;
 300         u16 gcfgc = 0;
 301
 302         pci_read_config_word(pdev, GCFGC, &gcfgc);
 303
 304         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 305         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 306                 cdclk_state->cdclk = 266667;
 307                 break;
 308         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 309                 cdclk_state->cdclk = 333333;
 310                 break;
 311         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 312                 cdclk_state->cdclk = 444444;
 313                 break;
 314         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 315                 cdclk_state->cdclk = 200000;
 316                 break;
 317         default:
 318                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 319         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 320                 cdclk_state->cdclk = 133333;
 321                 break;
 322         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 323                 cdclk_state->cdclk = 166667;
 324                 break;
 325         }
 326 }
 327
 328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 329                              struct intel_cdclk_state *cdclk_state)
 330 {
 331         struct pci_dev *pdev = dev_priv->drm.pdev;
 332         static const uint8_t div_3200[] = { 16, 10,  8 };
 333         static const uint8_t div_4000[] = { 20, 12, 10 };
 334         static const uint8_t div_5333[] = { 24, 16, 14 };
 335         const uint8_t *div_table;
 336         unsigned int cdclk_sel;
 337         uint16_t tmp = 0;
 338
 339         cdclk_state->vco = intel_hpll_vco(dev_priv);
 340
 341         pci_read_config_word(pdev, GCFGC, &tmp);
 342
 343         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 344
 345         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 346                 goto fail;
 347
 348         switch (cdclk_state->vco) {
 349         case 3200000:
 350                 div_table = div_3200;
 351                 break;
 352         case 4000000:
 353                 div_table = div_4000;
 354                 break;
 355         case 5333333:
 356                 div_table = div_5333;
 357                 break;
 358         default:
 359                 goto fail;
 360         }
 361
 362         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 363                                                div_table[cdclk_sel]);
 364         return;
 365
 366 fail:
 367         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 368                   cdclk_state->vco, tmp);
 369         cdclk_state->cdclk = 200000;
 370 }
 371
 372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 373                            struct intel_cdclk_state *cdclk_state)
 374 {
 375         struct pci_dev *pdev = dev_priv->drm.pdev;
 376         unsigned int cdclk_sel;
 377         uint16_t tmp = 0;
 378
 379         cdclk_state->vco = intel_hpll_vco(dev_priv);
 380
 381         pci_read_config_word(pdev, GCFGC, &tmp);
 382
 383         cdclk_sel = (tmp >> 12) & 0x1;
 384
 385         switch (cdclk_state->vco) {
 386         case 2666667:
 387         case 4000000:
 388         case 5333333:
 389                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 390                 break;
 391         case 3200000:
 392                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 393                 break;
 394         default:
 395                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 396                           cdclk_state->vco, tmp);
 397                 cdclk_state->cdclk = 222222;
 398                 break;
 399         }
 400 }
 401
 402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 403                           struct intel_cdclk_state *cdclk_state)
 404 {
 405         uint32_t lcpll = I915_READ(LCPLL_CTL);
 406         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 407
 408         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 409                 cdclk_state->cdclk = 800000;
 410         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 411                 cdclk_state->cdclk = 450000;
 412         else if (freq == LCPLL_CLK_FREQ_450)
 413                 cdclk_state->cdclk = 450000;
 414         else if (IS_HSW_ULT(dev_priv))
 415                 cdclk_state->cdclk = 337500;
 416         else
 417                 cdclk_state->cdclk = 540000;
 418 }
 419
 420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 421 {
 422         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 423                 333333 : 320000;
 424
 425         /*
 426          * We seem to get an unstable or solid color picture at 200MHz.
 427          * Not sure what's wrong. For now use 200MHz only when all pipes
 428          * are off.
 429          */
 430         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 431                 return 400000;
 432         else if (min_cdclk > 266667)
 433                 return freq_320;
 434         else if (min_cdclk > 0)
 435                 return 266667;
 436         else
 437                 return 200000;
 438 }
 439
 440 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
 441 {
 442         if (IS_VALLEYVIEW(dev_priv)) {
 443                 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 444                         return 2;
 445                 else if (cdclk >= 266667)
 446                         return 1;
 447                 else
 448                         return 0;
 449         } else {
 450                 /*
 451                  * Specs are full of misinformation, but testing on actual
 452                  * hardware has shown that we just need to write the desired
 453                  * CCK divider into the Punit register.
 454                  */
 455                 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 456         }
 457 }
 458
 459 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 460                           struct intel_cdclk_state *cdclk_state)
 461 {
 462         u32 val;
 463
 464         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 465         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 466                                                CCK_DISPLAY_CLOCK_CONTROL,
 467                                                cdclk_state->vco);
 468
 469         mutex_lock(&dev_priv->pcu_lock);
 470         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 471         mutex_unlock(&dev_priv->pcu_lock);
 472
 473         if (IS_VALLEYVIEW(dev_priv))
 474                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
 475                         DSPFREQGUAR_SHIFT;
 476         else
 477                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
 478                         DSPFREQGUAR_SHIFT_CHV;
 479 }
 480
 481 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 482 {
 483         unsigned int credits, default_credits;
 484
 485         if (IS_CHERRYVIEW(dev_priv))
 486                 default_credits = PFI_CREDIT(12);
 487         else
 488                 default_credits = PFI_CREDIT(8);
 489
 490         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 491                 /* CHV suggested value is 31 or 63 */
 492                 if (IS_CHERRYVIEW(dev_priv))
 493                         credits = PFI_CREDIT_63;
 494                 else
 495                         credits = PFI_CREDIT(15);
 496         } else {
 497                 credits = default_credits;
 498         }
 499
 500         /*
 501          * WA - write default credits before re-programming
 502          * FIXME: should we also set the resend bit here?
 503          */
 504         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 505                    default_credits);
 506
 507         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 508                    credits | PFI_CREDIT_RESEND);
 509
 510         /*
 511          * FIXME is this guaranteed to clear
 512          * immediately or should we poll for it?
 513          */
 514         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 515 }
 516
 517 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 518                           const struct intel_cdclk_state *cdclk_state)
 519 {
 520         int cdclk = cdclk_state->cdclk;
 521         u32 val, cmd = cdclk_state->voltage_level;
 522
 523         /* There are cases where we can end up here with power domains
 524          * off and a CDCLK frequency other than the minimum, like when
 525          * issuing a modeset without actually changing any display after
 526          * a system suspend.  So grab the PIPE-A domain, which covers
 527          * the HW blocks needed for the following programming.
 528          */
 529         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 530
 531         mutex_lock(&dev_priv->pcu_lock);
 532         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 533         val &= ~DSPFREQGUAR_MASK;
 534         val |= (cmd << DSPFREQGUAR_SHIFT);
 535         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 536         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 537                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 538                      50)) {
 539                 DRM_ERROR("timed out waiting for CDclk change\n");
 540         }
 541         mutex_unlock(&dev_priv->pcu_lock);
 542
 543         mutex_lock(&dev_priv->sb_lock);
 544
 545         if (cdclk == 400000) {
 546                 u32 divider;
 547
 548                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 549                                             cdclk) - 1;
 550
 551                 /* adjust cdclk divider */
 552                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 553                 val &= ~CCK_FREQUENCY_VALUES;
 554                 val |= divider;
 555                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 556
 557                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 558                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 559                              50))
 560                         DRM_ERROR("timed out waiting for CDclk change\n");
 561         }
 562
 563         /* adjust self-refresh exit latency value */
 564         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 565         val &= ~0x7f;
 566
 567         /*
 568          * For high bandwidth configs, we set a higher latency in the bunit
 569          * so that the core display fetch happens in time to avoid underruns.
 570          */
 571         if (cdclk == 400000)
 572                 val |= 4500 / 250; /* 4.5 usec */
 573         else
 574                 val |= 3000 / 250; /* 3.0 usec */
 575         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 576
 577         mutex_unlock(&dev_priv->sb_lock);
 578
 579         intel_update_cdclk(dev_priv);
 580
 581         vlv_program_pfi_credits(dev_priv);
 582
 583         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 584 }
 585
 586 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 587                           const struct intel_cdclk_state *cdclk_state)
 588 {
 589         int cdclk = cdclk_state->cdclk;
 590         u32 val, cmd = cdclk_state->voltage_level;
 591
 592         switch (cdclk) {
 593         case 333333:
 594         case 320000:
 595         case 266667:
 596         case 200000:
 597                 break;
 598         default:
 599                 MISSING_CASE(cdclk);
 600                 return;
 601         }
 602
 603         /* There are cases where we can end up here with power domains
 604          * off and a CDCLK frequency other than the minimum, like when
 605          * issuing a modeset without actually changing any display after
 606          * a system suspend.  So grab the PIPE-A domain, which covers
 607          * the HW blocks needed for the following programming.
 608          */
 609         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 610
 611         mutex_lock(&dev_priv->pcu_lock);
 612         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 613         val &= ~DSPFREQGUAR_MASK_CHV;
 614         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 615         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 616         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 617                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 618                      50)) {
 619                 DRM_ERROR("timed out waiting for CDclk change\n");
 620         }
 621         mutex_unlock(&dev_priv->pcu_lock);
 622
 623         intel_update_cdclk(dev_priv);
 624
 625         vlv_program_pfi_credits(dev_priv);
 626
 627         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 628 }
 629
 630 static int bdw_calc_cdclk(int min_cdclk)
 631 {
 632         if (min_cdclk > 540000)
 633                 return 675000;
 634         else if (min_cdclk > 450000)
 635                 return 540000;
 636         else if (min_cdclk > 337500)
 637                 return 450000;
 638         else
 639                 return 337500;
 640 }
 641
 642 static u8 bdw_calc_voltage_level(int cdclk)
 643 {
 644         switch (cdclk) {
 645         default:
 646         case 337500:
 647                 return 2;
 648         case 450000:
 649                 return 0;
 650         case 540000:
 651                 return 1;
 652         case 675000:
 653                 return 3;
 654         }
 655 }
 656
 657 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 658                           struct intel_cdclk_state *cdclk_state)
 659 {
 660         uint32_t lcpll = I915_READ(LCPLL_CTL);
 661         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 662
 663         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 664                 cdclk_state->cdclk = 800000;
 665         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 666                 cdclk_state->cdclk = 450000;
 667         else if (freq == LCPLL_CLK_FREQ_450)
 668                 cdclk_state->cdclk = 450000;
 669         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 670                 cdclk_state->cdclk = 540000;
 671         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 672                 cdclk_state->cdclk = 337500;
 673         else
 674                 cdclk_state->cdclk = 675000;
 675
 676         /*
 677          * Can't read this out :( Let's assume it's
 678          * at least what the CDCLK frequency requires.
 679          */
 680         cdclk_state->voltage_level =
 681                 bdw_calc_voltage_level(cdclk_state->cdclk);
 682 }
 683
 684 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 685                           const struct intel_cdclk_state *cdclk_state)
 686 {
 687         int cdclk = cdclk_state->cdclk;
 688         uint32_t val;
 689         int ret;
 690
 691         if (WARN((I915_READ(LCPLL_CTL) &
 692                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 693                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 694                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 695                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 696                  "trying to change cdclk frequency with cdclk not enabled\n"))
 697                 return;
 698
 699         mutex_lock(&dev_priv->pcu_lock);
 700         ret = sandybridge_pcode_write(dev_priv,
 701                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 702         mutex_unlock(&dev_priv->pcu_lock);
 703         if (ret) {
 704                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 705                 return;
 706         }
 707
 708         val = I915_READ(LCPLL_CTL);
 709         val |= LCPLL_CD_SOURCE_FCLK;
 710         I915_WRITE(LCPLL_CTL, val);
 711
 712         /*
 713          * According to the spec, it should be enough to poll for this 1 us.
 714          * However, extensive testing shows that this can take longer.
 715          */
 716         if (wait_for_us(I915_READ(LCPLL_CTL) &
 717                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 718                 DRM_ERROR("Switching to FCLK failed\n");
 719
 720         val = I915_READ(LCPLL_CTL);
 721         val &= ~LCPLL_CLK_FREQ_MASK;
 722
 723         switch (cdclk) {
 724         default:
 725                 MISSING_CASE(cdclk);
 726                 /* fall through */
 727         case 337500:
 728                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 729                 break;
 730         case 450000:
 731                 val |= LCPLL_CLK_FREQ_450;
 732                 break;
 733         case 540000:
 734                 val |= LCPLL_CLK_FREQ_54O_BDW;
 735                 break;
 736         case 675000:
 737                 val |= LCPLL_CLK_FREQ_675_BDW;
 738                 break;
 739         }
 740
 741         I915_WRITE(LCPLL_CTL, val);
 742
 743         val = I915_READ(LCPLL_CTL);
 744         val &= ~LCPLL_CD_SOURCE_FCLK;
 745         I915_WRITE(LCPLL_CTL, val);
 746
 747         if (wait_for_us((I915_READ(LCPLL_CTL) &
 748                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 749                 DRM_ERROR("Switching back to LCPLL failed\n");
 750
 751         mutex_lock(&dev_priv->pcu_lock);
 752         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
 753                                 cdclk_state->voltage_level);
 754         mutex_unlock(&dev_priv->pcu_lock);
 755
 756         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 757
 758         intel_update_cdclk(dev_priv);
 759
 760         WARN(cdclk != dev_priv->cdclk.hw.cdclk,
 761              "cdclk requested %d kHz but got %d kHz\n",
 762              cdclk, dev_priv->cdclk.hw.cdclk);
 763 }
 764
 765 static int skl_calc_cdclk(int min_cdclk, int vco)
 766 {
 767         if (vco == 8640000) {
 768                 if (min_cdclk > 540000)
 769                         return 617143;
 770                 else if (min_cdclk > 432000)
 771                         return 540000;
 772                 else if (min_cdclk > 308571)
 773                         return 432000;
 774                 else
 775                         return 308571;
 776         } else {
 777                 if (min_cdclk > 540000)
 778                         return 675000;
 779                 else if (min_cdclk > 450000)
 780                         return 540000;
 781                 else if (min_cdclk > 337500)
 782                         return 450000;
 783                 else
 784                         return 337500;
 785         }
 786 }
 787
 788 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 789                              struct intel_cdclk_state *cdclk_state)
 790 {
 791         u32 val;
 792
 793         cdclk_state->ref = 24000;
 794         cdclk_state->vco = 0;
 795
 796         val = I915_READ(LCPLL1_CTL);
 797         if ((val & LCPLL_PLL_ENABLE) == 0)
 798                 return;
 799
 800         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 801                 return;
 802
 803         val = I915_READ(DPLL_CTRL1);
 804
 805         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 806                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 807                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 808                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 809                 return;
 810
 811         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 812         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 813         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 814         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 815         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 816                 cdclk_state->vco = 8100000;
 817                 break;
 818         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 819         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 820                 cdclk_state->vco = 8640000;
 821                 break;
 822         default:
 823                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 824                 break;
 825         }
 826 }
 827
 828 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 829                           struct intel_cdclk_state *cdclk_state)
 830 {
 831         u32 cdctl;
 832
 833         skl_dpll0_update(dev_priv, cdclk_state);
 834
 835         cdclk_state->cdclk = cdclk_state->ref;
 836
 837         if (cdclk_state->vco == 0)
 838                 return;
 839
 840         cdctl = I915_READ(CDCLK_CTL);
 841
 842         if (cdclk_state->vco == 8640000) {
 843                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 844                 case CDCLK_FREQ_450_432:
 845                         cdclk_state->cdclk = 432000;
 846                         break;
 847                 case CDCLK_FREQ_337_308:
 848                         cdclk_state->cdclk = 308571;
 849                         break;
 850                 case CDCLK_FREQ_540:
 851                         cdclk_state->cdclk = 540000;
 852                         break;
 853                 case CDCLK_FREQ_675_617:
 854                         cdclk_state->cdclk = 617143;
 855                         break;
 856                 default:
 857                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 858                         break;
 859                 }
 860         } else {
 861                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 862                 case CDCLK_FREQ_450_432:
 863                         cdclk_state->cdclk = 450000;
 864                         break;
 865                 case CDCLK_FREQ_337_308:
 866                         cdclk_state->cdclk = 337500;
 867                         break;
 868                 case CDCLK_FREQ_540:
 869                         cdclk_state->cdclk = 540000;
 870                         break;
 871                 case CDCLK_FREQ_675_617:
 872                         cdclk_state->cdclk = 675000;
 873                         break;
 874                 default:
 875                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 876                         break;
 877                 }
 878         }
 879 }
 880
 881 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 882 static int skl_cdclk_decimal(int cdclk)
 883 {
 884         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 885 }
 886
 887 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 888                                         int vco)
 889 {
 890         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 891
 892         dev_priv->skl_preferred_vco_freq = vco;
 893
 894         if (changed)
 895                 intel_update_max_cdclk(dev_priv);
 896 }
 897
 898 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 899 {
 900         int min_cdclk = skl_calc_cdclk(0, vco);
 901         u32 val;
 902
 903         WARN_ON(vco != 8100000 && vco != 8640000);
 904
 905         /* select the minimum CDCLK before enabling DPLL 0 */
 906         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
 907         I915_WRITE(CDCLK_CTL, val);
 908         POSTING_READ(CDCLK_CTL);
 909
 910         /*
 911          * We always enable DPLL0 with the lowest link rate possible, but still
 912          * taking into account the VCO required to operate the eDP panel at the
 913          * desired frequency. The usual DP link rates operate with a VCO of
 914          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 915          * The modeset code is responsible for the selection of the exact link
 916          * rate later on, with the constraint of choosing a frequency that
 917          * works with vco.
 918          */
 919         val = I915_READ(DPLL_CTRL1);
 920
 921         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 922                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 923         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 924         if (vco == 8640000)
 925                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 926                                             SKL_DPLL0);
 927         else
 928                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 929                                             SKL_DPLL0);
 930
 931         I915_WRITE(DPLL_CTRL1, val);
 932         POSTING_READ(DPLL_CTRL1);
 933
 934         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 935
 936         if (intel_wait_for_register(dev_priv,
 937                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 938                                     5))
 939                 DRM_ERROR("DPLL0 not locked\n");
 940
 941         dev_priv->cdclk.hw.vco = vco;
 942
 943         /* We'll want to keep using the current vco from now on. */
 944         skl_set_preferred_cdclk_vco(dev_priv, vco);
 945 }
 946
 947 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 948 {
 949         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 950         if (intel_wait_for_register(dev_priv,
 951                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 952                                    1))
 953                 DRM_ERROR("Couldn't disable DPLL0\n");
 954
 955         dev_priv->cdclk.hw.vco = 0;
 956 }
 957
 958 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 959                           const struct intel_cdclk_state *cdclk_state)
 960 {
 961         int cdclk = cdclk_state->cdclk;
 962         int vco = cdclk_state->vco;
 963         u32 freq_select, pcu_ack;
 964         int ret;
 965
 966         mutex_lock(&dev_priv->pcu_lock);
 967         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 968                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
 969                                 SKL_CDCLK_READY_FOR_CHANGE,
 970                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
 971         mutex_unlock(&dev_priv->pcu_lock);
 972         if (ret) {
 973                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
 974                           ret);
 975                 return;
 976         }
 977
 978         /* set CDCLK_CTL */
 979         switch (cdclk) {
 980         default:
 981                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
 982                 WARN_ON(vco != 0);
 983                 /* fall through */
 984         case 308571:
 985         case 337500:
 986                 freq_select = CDCLK_FREQ_337_308;
 987                 pcu_ack = 0;
 988                 break;
 989         case 450000:
 990         case 432000:
 991                 freq_select = CDCLK_FREQ_450_432;
 992                 pcu_ack = 1;
 993                 break;
 994         case 540000:
 995                 freq_select = CDCLK_FREQ_540;
 996                 pcu_ack = 2;
 997                 break;
 998         case 617143:
 999         case 675000:
1000                 freq_select = CDCLK_FREQ_675_617;
1001                 pcu_ack = 3;
1002                 break;
1003         }
1004
1005         if (dev_priv->cdclk.hw.vco != 0 &&
1006             dev_priv->cdclk.hw.vco != vco)
1007                 skl_dpll0_disable(dev_priv);
1008
1009         if (dev_priv->cdclk.hw.vco != vco)
1010                 skl_dpll0_enable(dev_priv, vco);
1011
1012         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
1013         POSTING_READ(CDCLK_CTL);
1014
1015         /* inform PCU of the change */
1016         mutex_lock(&dev_priv->pcu_lock);
1017         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
1018         mutex_unlock(&dev_priv->pcu_lock);
1019
1020         intel_update_cdclk(dev_priv);
1021 }
1022
1023 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1024 {
1025         uint32_t cdctl, expected;
1026
1027         /*
1028          * check if the pre-os initialized the display
1029          * There is SWF18 scratchpad register defined which is set by the
1030          * pre-os which can be used by the OS drivers to check the status
1031          */
1032         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1033                 goto sanitize;
1034
1035         intel_update_cdclk(dev_priv);
1036         /* Is PLL enabled and locked ? */
1037         if (dev_priv->cdclk.hw.vco == 0 ||
1038             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1039                 goto sanitize;
1040
1041         /* DPLL okay; verify the cdclock
1042          *
1043          * Noticed in some instances that the freq selection is correct but
1044          * decimal part is programmed wrong from BIOS where pre-os does not
1045          * enable display. Verify the same as well.
1046          */
1047         cdctl = I915_READ(CDCLK_CTL);
1048         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1049                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1050         if (cdctl == expected)
1051                 /* All well; nothing to sanitize */
1052                 return;
1053
1054 sanitize:
1055         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1056
1057         /* force cdclk programming */
1058         dev_priv->cdclk.hw.cdclk = 0;
1059         /* force full PLL disable + enable */
1060         dev_priv->cdclk.hw.vco = -1;
1061 }
1062
1063 /**
1064  * skl_init_cdclk - Initialize CDCLK on SKL
1065  * @dev_priv: i915 device
1066  *
1067  * Initialize CDCLK for SKL and derivatives. This is generally
1068  * done only during the display core initialization sequence,
1069  * after which the DMC will take care of turning CDCLK off/on
1070  * as needed.
1071  */
1072 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1073 {
1074         struct intel_cdclk_state cdclk_state;
1075
1076         skl_sanitize_cdclk(dev_priv);
1077
1078         if (dev_priv->cdclk.hw.cdclk != 0 &&
1079             dev_priv->cdclk.hw.vco != 0) {
1080                 /*
1081                  * Use the current vco as our initial
1082                  * guess as to what the preferred vco is.
1083                  */
1084                 if (dev_priv->skl_preferred_vco_freq == 0)
1085                         skl_set_preferred_cdclk_vco(dev_priv,
1086                                                     dev_priv->cdclk.hw.vco);
1087                 return;
1088         }
1089
1090         cdclk_state = dev_priv->cdclk.hw;
1091
1092         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1093         if (cdclk_state.vco == 0)
1094                 cdclk_state.vco = 8100000;
1095         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1096
1097         skl_set_cdclk(dev_priv, &cdclk_state);
1098 }
1099
1100 /**
1101  * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1102  * @dev_priv: i915 device
1103  *
1104  * Uninitialize CDCLK for SKL and derivatives. This is done only
1105  * during the display core uninitialization sequence.
1106  */
1107 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1108 {
1109         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1110
1111         cdclk_state.cdclk = cdclk_state.ref;
1112         cdclk_state.vco = 0;
1113
1114         skl_set_cdclk(dev_priv, &cdclk_state);
1115 }
1116
1117 static int bxt_calc_cdclk(int min_cdclk)
1118 {
1119         if (min_cdclk > 576000)
1120                 return 624000;
1121         else if (min_cdclk > 384000)
1122                 return 576000;
1123         else if (min_cdclk > 288000)
1124                 return 384000;
1125         else if (min_cdclk > 144000)
1126                 return 288000;
1127         else
1128                 return 144000;
1129 }
1130
1131 static int glk_calc_cdclk(int min_cdclk)
1132 {
1133         if (min_cdclk > 158400)
1134                 return 316800;
1135         else if (min_cdclk > 79200)
1136                 return 158400;
1137         else
1138                 return 79200;
1139 }
1140
1141 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1142 {
1143         int ratio;
1144
1145         if (cdclk == dev_priv->cdclk.hw.ref)
1146                 return 0;
1147
1148         switch (cdclk) {
1149         default:
1150                 MISSING_CASE(cdclk);
1151                 /* fall through */
1152         case 144000:
1153         case 288000:
1154         case 384000:
1155         case 576000:
1156                 ratio = 60;
1157                 break;
1158         case 624000:
1159                 ratio = 65;
1160                 break;
1161         }
1162
1163         return dev_priv->cdclk.hw.ref * ratio;
1164 }
1165
1166 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1167 {
1168         int ratio;
1169
1170         if (cdclk == dev_priv->cdclk.hw.ref)
1171                 return 0;
1172
1173         switch (cdclk) {
1174         default:
1175                 MISSING_CASE(cdclk);
1176                 /* fall through */
1177         case  79200:
1178         case 158400:
1179         case 316800:
1180                 ratio = 33;
1181                 break;
1182         }
1183
1184         return dev_priv->cdclk.hw.ref * ratio;
1185 }
1186
1187 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1188                               struct intel_cdclk_state *cdclk_state)
1189 {
1190         u32 val;
1191
1192         cdclk_state->ref = 19200;
1193         cdclk_state->vco = 0;
1194
1195         val = I915_READ(BXT_DE_PLL_ENABLE);
1196         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1197                 return;
1198
1199         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1200                 return;
1201
1202         val = I915_READ(BXT_DE_PLL_CTL);
1203         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1204 }
1205
1206 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1207                           struct intel_cdclk_state *cdclk_state)
1208 {
1209         u32 divider;
1210         int div;
1211
1212         bxt_de_pll_update(dev_priv, cdclk_state);
1213
1214         cdclk_state->cdclk = cdclk_state->ref;
1215
1216         if (cdclk_state->vco == 0)
1217                 return;
1218
1219         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1220
1221         switch (divider) {
1222         case BXT_CDCLK_CD2X_DIV_SEL_1:
1223                 div = 2;
1224                 break;
1225         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1226                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1227                 div = 3;
1228                 break;
1229         case BXT_CDCLK_CD2X_DIV_SEL_2:
1230                 div = 4;
1231                 break;
1232         case BXT_CDCLK_CD2X_DIV_SEL_4:
1233                 div = 8;
1234                 break;
1235         default:
1236                 MISSING_CASE(divider);
1237                 return;
1238         }
1239
1240         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1241 }
1242
1243 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1244 {
1245         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1246
1247         /* Timeout 200us */
1248         if (intel_wait_for_register(dev_priv,
1249                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1250                                     1))
1251                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1252
1253         dev_priv->cdclk.hw.vco = 0;
1254 }
1255
1256 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1257 {
1258         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1259         u32 val;
1260
1261         val = I915_READ(BXT_DE_PLL_CTL);
1262         val &= ~BXT_DE_PLL_RATIO_MASK;
1263         val |= BXT_DE_PLL_RATIO(ratio);
1264         I915_WRITE(BXT_DE_PLL_CTL, val);
1265
1266         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1267
1268         /* Timeout 200us */
1269         if (intel_wait_for_register(dev_priv,
1270                                     BXT_DE_PLL_ENABLE,
1271                                     BXT_DE_PLL_LOCK,
1272                                     BXT_DE_PLL_LOCK,
1273                                     1))
1274                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1275
1276         dev_priv->cdclk.hw.vco = vco;
1277 }
1278
1279 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1280                           const struct intel_cdclk_state *cdclk_state)
1281 {
1282         int cdclk = cdclk_state->cdclk;
1283         int vco = cdclk_state->vco;
1284         u32 val, divider;
1285         int ret;
1286
1287         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1288         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1289         default:
1290                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1291                 WARN_ON(vco != 0);
1292                 /* fall through */
1293         case 2:
1294                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1295                 break;
1296         case 3:
1297                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1298                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1299                 break;
1300         case 4:
1301                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1302                 break;
1303         case 8:
1304                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1305                 break;
1306         }
1307
1308         /* Inform power controller of upcoming frequency change */
1309         mutex_lock(&dev_priv->pcu_lock);
1310         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1311                                       0x80000000);
1312         mutex_unlock(&dev_priv->pcu_lock);
1313
1314         if (ret) {
1315                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1316                           ret, cdclk);
1317                 return;
1318         }
1319
1320         if (dev_priv->cdclk.hw.vco != 0 &&
1321             dev_priv->cdclk.hw.vco != vco)
1322                 bxt_de_pll_disable(dev_priv);
1323
1324         if (dev_priv->cdclk.hw.vco != vco)
1325                 bxt_de_pll_enable(dev_priv, vco);
1326
1327         val = divider | skl_cdclk_decimal(cdclk);
1328         /*
1329          * FIXME if only the cd2x divider needs changing, it could be done
1330          * without shutting off the pipe (if only one pipe is active).
1331          */
1332         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1333         /*
1334          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1335          * enable otherwise.
1336          */
1337         if (cdclk >= 500000)
1338                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1339         I915_WRITE(CDCLK_CTL, val);
1340
1341         mutex_lock(&dev_priv->pcu_lock);
1342         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1343                                       DIV_ROUND_UP(cdclk, 25000));
1344         mutex_unlock(&dev_priv->pcu_lock);
1345
1346         if (ret) {
1347                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1348                           ret, cdclk);
1349                 return;
1350         }
1351
1352         intel_update_cdclk(dev_priv);
1353 }
1354
1355 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1356 {
1357         u32 cdctl, expected;
1358
1359         intel_update_cdclk(dev_priv);
1360
1361         if (dev_priv->cdclk.hw.vco == 0 ||
1362             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1363                 goto sanitize;
1364
1365         /* DPLL okay; verify the cdclock
1366          *
1367          * Some BIOS versions leave an incorrect decimal frequency value and
1368          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1369          * so sanitize this register.
1370          */
1371         cdctl = I915_READ(CDCLK_CTL);
1372         /*
1373          * Let's ignore the pipe field, since BIOS could have configured the
1374          * dividers both synching to an active pipe, or asynchronously
1375          * (PIPE_NONE).
1376          */
1377         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1378
1379         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1380                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1381         /*
1382          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1383          * enable otherwise.
1384          */
1385         if (dev_priv->cdclk.hw.cdclk >= 500000)
1386                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1387
1388         if (cdctl == expected)
1389                 /* All well; nothing to sanitize */
1390                 return;
1391
1392 sanitize:
1393         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1394
1395         /* force cdclk programming */
1396         dev_priv->cdclk.hw.cdclk = 0;
1397
1398         /* force full PLL disable + enable */
1399         dev_priv->cdclk.hw.vco = -1;
1400 }
1401
1402 /**
1403  * bxt_init_cdclk - Initialize CDCLK on BXT
1404  * @dev_priv: i915 device
1405  *
1406  * Initialize CDCLK for BXT and derivatives. This is generally
1407  * done only during the display core initialization sequence,
1408  * after which the DMC will take care of turning CDCLK off/on
1409  * as needed.
1410  */
1411 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1412 {
1413         struct intel_cdclk_state cdclk_state;
1414
1415         bxt_sanitize_cdclk(dev_priv);
1416
1417         if (dev_priv->cdclk.hw.cdclk != 0 &&
1418             dev_priv->cdclk.hw.vco != 0)
1419                 return;
1420
1421         cdclk_state = dev_priv->cdclk.hw;
1422
1423         /*
1424          * FIXME:
1425          * - The initial CDCLK needs to be read from VBT.
1426          *   Need to make this change after VBT has changes for BXT.
1427          */
1428         if (IS_GEMINILAKE(dev_priv)) {
1429                 cdclk_state.cdclk = glk_calc_cdclk(0);
1430                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1431         } else {
1432                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1433                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1434         }
1435
1436         bxt_set_cdclk(dev_priv, &cdclk_state);
1437 }
1438
1439 /**
1440  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1441  * @dev_priv: i915 device
1442  *
1443  * Uninitialize CDCLK for BXT and derivatives. This is done only
1444  * during the display core uninitialization sequence.
1445  */
1446 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1447 {
1448         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1449
1450         cdclk_state.cdclk = cdclk_state.ref;
1451         cdclk_state.vco = 0;
1452
1453         bxt_set_cdclk(dev_priv, &cdclk_state);
1454 }
1455
1456 static int cnl_calc_cdclk(int min_cdclk)
1457 {
1458         if (min_cdclk > 336000)
1459                 return 528000;
1460         else if (min_cdclk > 168000)
1461                 return 336000;
1462         else
1463                 return 168000;
1464 }
1465
1466 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1467                                  struct intel_cdclk_state *cdclk_state)
1468 {
1469         u32 val;
1470
1471         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1472                 cdclk_state->ref = 24000;
1473         else
1474                 cdclk_state->ref = 19200;
1475
1476         cdclk_state->vco = 0;
1477
1478         val = I915_READ(BXT_DE_PLL_ENABLE);
1479         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1480                 return;
1481
1482         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1483                 return;
1484
1485         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1486 }
1487
1488 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1489                          struct intel_cdclk_state *cdclk_state)
1490 {
1491         u32 divider;
1492         int div;
1493
1494         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1495
1496         cdclk_state->cdclk = cdclk_state->ref;
1497
1498         if (cdclk_state->vco == 0)
1499                 return;
1500
1501         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1502
1503         switch (divider) {
1504         case BXT_CDCLK_CD2X_DIV_SEL_1:
1505                 div = 2;
1506                 break;
1507         case BXT_CDCLK_CD2X_DIV_SEL_2:
1508                 div = 4;
1509                 break;
1510         default:
1511                 MISSING_CASE(divider);
1512                 return;
1513         }
1514
1515         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1516 }
1517
1518 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1519 {
1520         u32 val;
1521
1522         val = I915_READ(BXT_DE_PLL_ENABLE);
1523         val &= ~BXT_DE_PLL_PLL_ENABLE;
1524         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1525
1526         /* Timeout 200us */
1527         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1528                 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1529
1530         dev_priv->cdclk.hw.vco = 0;
1531 }
1532
1533 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1534 {
1535         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1536         u32 val;
1537
1538         val = CNL_CDCLK_PLL_RATIO(ratio);
1539         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1540
1541         val |= BXT_DE_PLL_PLL_ENABLE;
1542         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1543
1544         /* Timeout 200us */
1545         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1546                 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1547
1548         dev_priv->cdclk.hw.vco = vco;
1549 }
1550
1551 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1552                           const struct intel_cdclk_state *cdclk_state)
1553 {
1554         int cdclk = cdclk_state->cdclk;
1555         int vco = cdclk_state->vco;
1556         u32 val, divider, pcu_ack;
1557         int ret;
1558
1559         mutex_lock(&dev_priv->pcu_lock);
1560         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1561                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1562                                 SKL_CDCLK_READY_FOR_CHANGE,
1563                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1564         mutex_unlock(&dev_priv->pcu_lock);
1565         if (ret) {
1566                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1567                           ret);
1568                 return;
1569         }
1570
1571         /* cdclk = vco / 2 / div{1,2} */
1572         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1573         default:
1574                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1575                 WARN_ON(vco != 0);
1576                 /* fall through */
1577         case 2:
1578                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1579                 break;
1580         case 4:
1581                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1582                 break;
1583         }
1584
1585         switch (cdclk) {
1586         case 528000:
1587                 pcu_ack = 2;
1588                 break;
1589         case 336000:
1590                 pcu_ack = 1;
1591                 break;
1592         case 168000:
1593         default:
1594                 pcu_ack = 0;
1595                 break;
1596         }
1597
1598         if (dev_priv->cdclk.hw.vco != 0 &&
1599             dev_priv->cdclk.hw.vco != vco)
1600                 cnl_cdclk_pll_disable(dev_priv);
1601
1602         if (dev_priv->cdclk.hw.vco != vco)
1603                 cnl_cdclk_pll_enable(dev_priv, vco);
1604
1605         val = divider | skl_cdclk_decimal(cdclk);
1606         /*
1607          * FIXME if only the cd2x divider needs changing, it could be done
1608          * without shutting off the pipe (if only one pipe is active).
1609          */
1610         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1611         I915_WRITE(CDCLK_CTL, val);
1612
1613         /* inform PCU of the change */
1614         mutex_lock(&dev_priv->pcu_lock);
1615         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
1616         mutex_unlock(&dev_priv->pcu_lock);
1617
1618         intel_update_cdclk(dev_priv);
1619 }
1620
1621 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1622 {
1623         int ratio;
1624
1625         if (cdclk == dev_priv->cdclk.hw.ref)
1626                 return 0;
1627
1628         switch (cdclk) {
1629         default:
1630                 MISSING_CASE(cdclk);
1631                 /* fall through */
1632         case 168000:
1633         case 336000:
1634                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1635                 break;
1636         case 528000:
1637                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1638                 break;
1639         }
1640
1641         return dev_priv->cdclk.hw.ref * ratio;
1642 }
1643
1644 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1645 {
1646         u32 cdctl, expected;
1647
1648         intel_update_cdclk(dev_priv);
1649
1650         if (dev_priv->cdclk.hw.vco == 0 ||
1651             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1652                 goto sanitize;
1653
1654         /* DPLL okay; verify the cdclock
1655          *
1656          * Some BIOS versions leave an incorrect decimal frequency value and
1657          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1658          * so sanitize this register.
1659          */
1660         cdctl = I915_READ(CDCLK_CTL);
1661         /*
1662          * Let's ignore the pipe field, since BIOS could have configured the
1663          * dividers both synching to an active pipe, or asynchronously
1664          * (PIPE_NONE).
1665          */
1666         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1667
1668         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1669                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1670
1671         if (cdctl == expected)
1672                 /* All well; nothing to sanitize */
1673                 return;
1674
1675 sanitize:
1676         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1677
1678         /* force cdclk programming */
1679         dev_priv->cdclk.hw.cdclk = 0;
1680
1681         /* force full PLL disable + enable */
1682         dev_priv->cdclk.hw.vco = -1;
1683 }
1684
1685 /**
1686  * cnl_init_cdclk - Initialize CDCLK on CNL
1687  * @dev_priv: i915 device
1688  *
1689  * Initialize CDCLK for CNL. This is generally
1690  * done only during the display core initialization sequence,
1691  * after which the DMC will take care of turning CDCLK off/on
1692  * as needed.
1693  */
1694 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1695 {
1696         struct intel_cdclk_state cdclk_state;
1697
1698         cnl_sanitize_cdclk(dev_priv);
1699
1700         if (dev_priv->cdclk.hw.cdclk != 0 &&
1701             dev_priv->cdclk.hw.vco != 0)
1702                 return;
1703
1704         cdclk_state = dev_priv->cdclk.hw;
1705
1706         cdclk_state.cdclk = cnl_calc_cdclk(0);
1707         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1708
1709         cnl_set_cdclk(dev_priv, &cdclk_state);
1710 }
1711
1712 /**
1713  * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1714  * @dev_priv: i915 device
1715  *
1716  * Uninitialize CDCLK for CNL. This is done only
1717  * during the display core uninitialization sequence.
1718  */
1719 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1720 {
1721         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1722
1723         cdclk_state.cdclk = cdclk_state.ref;
1724         cdclk_state.vco = 0;
1725
1726         cnl_set_cdclk(dev_priv, &cdclk_state);
1727 }
1728
1729 /**
1730  * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
1731  * @a: first CDCLK state
1732  * @b: second CDCLK state
1733  *
1734  * Returns:
1735  * True if the CDCLK states require pipes to be off during reprogramming, false if not.
1736  */
1737 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1738                                const struct intel_cdclk_state *b)
1739 {
1740         return a->cdclk != b->cdclk ||
1741                 a->vco != b->vco ||
1742                 a->ref != b->ref;
1743 }
1744
1745 /**
1746  * intel_cdclk_changed - Determine if two CDCLK states are different
1747  * @a: first CDCLK state
1748  * @b: second CDCLK state
1749  *
1750  * Returns:
1751  * True if the CDCLK states don't match, false if they do.
1752  */
1753 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1754                          const struct intel_cdclk_state *b)
1755 {
1756         return intel_cdclk_needs_modeset(a, b) ||
1757                 a->voltage_level != b->voltage_level;
1758 }
1759
1760 /**
1761  * intel_set_cdclk - Push the CDCLK state to the hardware
1762  * @dev_priv: i915 device
1763  * @cdclk_state: new CDCLK state
1764  *
1765  * Program the hardware based on the passed in CDCLK state,
1766  * if necessary.
1767  */
1768 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1769                      const struct intel_cdclk_state *cdclk_state)
1770 {
1771         if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
1772                 return;
1773
1774         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1775                 return;
1776
1777         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz, voltage_level %d\n",
1778                          cdclk_state->cdclk, cdclk_state->vco,
1779                          cdclk_state->ref, cdclk_state->voltage_level);
1780
1781         dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1782 }
1783
1784 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
1785                                      int pixel_rate)
1786 {
1787         if (INTEL_GEN(dev_priv) >= 10)
1788                 /*
1789                  * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
1790                  * once DDI clock voltage requirements are
1791                  * handled correctly.
1792                  */
1793                 return pixel_rate;
1794         else if (IS_GEMINILAKE(dev_priv))
1795                 /*
1796                  * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1797                  * as a temporary workaround. Use a higher cdclk instead. (Note that
1798                  * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1799                  * cdclk.)
1800                  */
1801                 return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
1802         else if (IS_GEN9(dev_priv) ||
1803                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1804                 return pixel_rate;
1805         else if (IS_CHERRYVIEW(dev_priv))
1806                 return DIV_ROUND_UP(pixel_rate * 100, 95);
1807         else
1808                 return DIV_ROUND_UP(pixel_rate * 100, 90);
1809 }
1810
1811 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
1812 {
1813         struct drm_i915_private *dev_priv =
1814                 to_i915(crtc_state->base.crtc->dev);
1815         int min_cdclk;
1816
1817         if (!crtc_state->base.enable)
1818                 return 0;
1819
1820         min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
1821
1822         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1823         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1824                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
1825
1826         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1827          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1828          * there may be audio corruption or screen corruption." This cdclk
1829          * restriction for GLK is 316.8 MHz.
1830          */
1831         if (intel_crtc_has_dp_encoder(crtc_state) &&
1832             crtc_state->has_audio &&
1833             crtc_state->port_clock >= 540000 &&
1834             crtc_state->lane_count == 4) {
1835                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1836                         /* Display WA #1145: glk,cnl */
1837                         min_cdclk = max(316800, min_cdclk);
1838                 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
1839                         /* Display WA #1144: skl,bxt */
1840                         min_cdclk = max(432000, min_cdclk);
1841                 }
1842         }
1843
1844         /* According to BSpec, "The CD clock frequency must be at least twice
1845          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1846          */
1847         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
1848                 min_cdclk = max(2 * 96000, min_cdclk);
1849
1850         if (min_cdclk > dev_priv->max_cdclk_freq) {
1851                 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
1852                               min_cdclk, dev_priv->max_cdclk_freq);
1853                 return -EINVAL;
1854         }
1855
1856         return min_cdclk;
1857 }
1858
1859 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
1860 {
1861         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1862         struct drm_i915_private *dev_priv = to_i915(state->dev);
1863         struct intel_crtc *crtc;
1864         struct intel_crtc_state *crtc_state;
1865         int min_cdclk, i;
1866         enum pipe pipe;
1867
1868         memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
1869                sizeof(intel_state->min_cdclk));
1870
1871         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
1872                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
1873                 if (min_cdclk < 0)
1874                         return min_cdclk;
1875
1876                 intel_state->min_cdclk[i] = min_cdclk;
1877         }
1878
1879         min_cdclk = 0;
1880         for_each_pipe(dev_priv, pipe)
1881                 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
1882
1883         return min_cdclk;
1884 }
1885
1886 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1887 {
1888         struct drm_i915_private *dev_priv = to_i915(state->dev);
1889         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1890         int min_cdclk, cdclk;
1891
1892         min_cdclk = intel_compute_min_cdclk(state);
1893         if (min_cdclk < 0)
1894                 return min_cdclk;
1895
1896         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
1897
1898         intel_state->cdclk.logical.cdclk = cdclk;
1899         intel_state->cdclk.logical.voltage_level =
1900                 vlv_calc_voltage_level(dev_priv, cdclk);
1901
1902         if (!intel_state->active_crtcs) {
1903                 cdclk = vlv_calc_cdclk(dev_priv, 0);
1904
1905                 intel_state->cdclk.actual.cdclk = cdclk;
1906                 intel_state->cdclk.actual.voltage_level =
1907                         vlv_calc_voltage_level(dev_priv, cdclk);
1908         } else {
1909                 intel_state->cdclk.actual =
1910                         intel_state->cdclk.logical;
1911         }
1912
1913         return 0;
1914 }
1915
1916 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1917 {
1918         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1919         int min_cdclk, cdclk;
1920
1921         min_cdclk = intel_compute_min_cdclk(state);
1922         if (min_cdclk < 0)
1923                 return min_cdclk;
1924
1925         /*
1926          * FIXME should also account for plane ratio
1927          * once 64bpp pixel formats are supported.
1928          */
1929         cdclk = bdw_calc_cdclk(min_cdclk);
1930
1931         intel_state->cdclk.logical.cdclk = cdclk;
1932         intel_state->cdclk.logical.voltage_level =
1933                 bdw_calc_voltage_level(cdclk);
1934
1935         if (!intel_state->active_crtcs) {
1936                 cdclk = bdw_calc_cdclk(0);
1937
1938                 intel_state->cdclk.actual.cdclk = cdclk;
1939                 intel_state->cdclk.actual.voltage_level =
1940                         bdw_calc_voltage_level(cdclk);
1941         } else {
1942                 intel_state->cdclk.actual =
1943                         intel_state->cdclk.logical;
1944         }
1945
1946         return 0;
1947 }
1948
1949 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1950 {
1951         struct drm_i915_private *dev_priv = to_i915(state->dev);
1952         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1953         int min_cdclk, cdclk, vco;
1954
1955         min_cdclk = intel_compute_min_cdclk(state);
1956         if (min_cdclk < 0)
1957                 return min_cdclk;
1958
1959         vco = intel_state->cdclk.logical.vco;
1960         if (!vco)
1961                 vco = dev_priv->skl_preferred_vco_freq;
1962
1963         /*
1964          * FIXME should also account for plane ratio
1965          * once 64bpp pixel formats are supported.
1966          */
1967         cdclk = skl_calc_cdclk(min_cdclk, vco);
1968
1969         intel_state->cdclk.logical.vco = vco;
1970         intel_state->cdclk.logical.cdclk = cdclk;
1971
1972         if (!intel_state->active_crtcs) {
1973                 cdclk = skl_calc_cdclk(0, vco);
1974
1975                 intel_state->cdclk.actual.vco = vco;
1976                 intel_state->cdclk.actual.cdclk = cdclk;
1977         } else {
1978                 intel_state->cdclk.actual =
1979                         intel_state->cdclk.logical;
1980         }
1981
1982         return 0;
1983 }
1984
1985 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1986 {
1987         struct drm_i915_private *dev_priv = to_i915(state->dev);
1988         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1989         int min_cdclk, cdclk, vco;
1990
1991         min_cdclk = intel_compute_min_cdclk(state);
1992         if (min_cdclk < 0)
1993                 return min_cdclk;
1994
1995         if (IS_GEMINILAKE(dev_priv)) {
1996                 cdclk = glk_calc_cdclk(min_cdclk);
1997                 vco = glk_de_pll_vco(dev_priv, cdclk);
1998         } else {
1999                 cdclk = bxt_calc_cdclk(min_cdclk);
2000                 vco = bxt_de_pll_vco(dev_priv, cdclk);
2001         }
2002
2003         intel_state->cdclk.logical.vco = vco;
2004         intel_state->cdclk.logical.cdclk = cdclk;
2005
2006         if (!intel_state->active_crtcs) {
2007                 if (IS_GEMINILAKE(dev_priv)) {
2008                         cdclk = glk_calc_cdclk(0);
2009                         vco = glk_de_pll_vco(dev_priv, cdclk);
2010                 } else {
2011                         cdclk = bxt_calc_cdclk(0);
2012                         vco = bxt_de_pll_vco(dev_priv, cdclk);
2013                 }
2014
2015                 intel_state->cdclk.actual.vco = vco;
2016                 intel_state->cdclk.actual.cdclk = cdclk;
2017         } else {
2018                 intel_state->cdclk.actual =
2019                         intel_state->cdclk.logical;
2020         }
2021
2022         return 0;
2023 }
2024
2025 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
2026 {
2027         struct drm_i915_private *dev_priv = to_i915(state->dev);
2028         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2029         int min_cdclk, cdclk, vco;
2030
2031         min_cdclk = intel_compute_min_cdclk(state);
2032         if (min_cdclk < 0)
2033                 return min_cdclk;
2034
2035         cdclk = cnl_calc_cdclk(min_cdclk);
2036         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2037
2038         intel_state->cdclk.logical.vco = vco;
2039         intel_state->cdclk.logical.cdclk = cdclk;
2040
2041         if (!intel_state->active_crtcs) {
2042                 cdclk = cnl_calc_cdclk(0);
2043                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2044
2045                 intel_state->cdclk.actual.vco = vco;
2046                 intel_state->cdclk.actual.cdclk = cdclk;
2047         } else {
2048                 intel_state->cdclk.actual =
2049                         intel_state->cdclk.logical;
2050         }
2051
2052         return 0;
2053 }
2054
2055 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2056 {
2057         int max_cdclk_freq = dev_priv->max_cdclk_freq;
2058
2059         if (INTEL_GEN(dev_priv) >= 10)
2060                 /*
2061                  * FIXME: Allow '2 * max_cdclk_freq'
2062                  * once DDI clock voltage requirements are
2063                  * handled correctly.
2064                  */
2065                 return max_cdclk_freq;
2066         else if (IS_GEMINILAKE(dev_priv))
2067                 /*
2068                  * FIXME: Limiting to 99% as a temporary workaround. See
2069                  * intel_min_cdclk() for details.
2070                  */
2071                 return 2 * max_cdclk_freq * 99 / 100;
2072         else if (IS_GEN9(dev_priv) ||
2073                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2074                 return max_cdclk_freq;
2075         else if (IS_CHERRYVIEW(dev_priv))
2076                 return max_cdclk_freq*95/100;
2077         else if (INTEL_INFO(dev_priv)->gen < 4)
2078                 return 2*max_cdclk_freq*90/100;
2079         else
2080                 return max_cdclk_freq*90/100;
2081 }
2082
2083 /**
2084  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2085  * @dev_priv: i915 device
2086  *
2087  * Determine the maximum CDCLK frequency the platform supports, and also
2088  * derive the maximum dot clock frequency the maximum CDCLK frequency
2089  * allows.
2090  */
2091 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2092 {
2093         if (IS_CANNONLAKE(dev_priv)) {
2094                 dev_priv->max_cdclk_freq = 528000;
2095         } else if (IS_GEN9_BC(dev_priv)) {
2096                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2097                 int max_cdclk, vco;
2098
2099                 vco = dev_priv->skl_preferred_vco_freq;
2100                 WARN_ON(vco != 8100000 && vco != 8640000);
2101
2102                 /*
2103                  * Use the lower (vco 8640) cdclk values as a
2104                  * first guess. skl_calc_cdclk() will correct it
2105                  * if the preferred vco is 8100 instead.
2106                  */
2107                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2108                         max_cdclk = 617143;
2109                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2110                         max_cdclk = 540000;
2111                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2112                         max_cdclk = 432000;
2113                 else
2114                         max_cdclk = 308571;
2115
2116                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2117         } else if (IS_GEMINILAKE(dev_priv)) {
2118                 dev_priv->max_cdclk_freq = 316800;
2119         } else if (IS_BROXTON(dev_priv)) {
2120                 dev_priv->max_cdclk_freq = 624000;
2121         } else if (IS_BROADWELL(dev_priv))  {
2122                 /*
2123                  * FIXME with extra cooling we can allow
2124                  * 540 MHz for ULX and 675 Mhz for ULT.
2125                  * How can we know if extra cooling is
2126                  * available? PCI ID, VTB, something else?
2127                  */
2128                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2129                         dev_priv->max_cdclk_freq = 450000;
2130                 else if (IS_BDW_ULX(dev_priv))
2131                         dev_priv->max_cdclk_freq = 450000;
2132                 else if (IS_BDW_ULT(dev_priv))
2133                         dev_priv->max_cdclk_freq = 540000;
2134                 else
2135                         dev_priv->max_cdclk_freq = 675000;
2136         } else if (IS_CHERRYVIEW(dev_priv)) {
2137                 dev_priv->max_cdclk_freq = 320000;
2138         } else if (IS_VALLEYVIEW(dev_priv)) {
2139                 dev_priv->max_cdclk_freq = 400000;
2140         } else {
2141                 /* otherwise assume cdclk is fixed */
2142                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2143         }
2144
2145         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2146
2147         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2148                          dev_priv->max_cdclk_freq);
2149
2150         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2151                          dev_priv->max_dotclk_freq);
2152 }
2153
2154 /**
2155  * intel_update_cdclk - Determine the current CDCLK frequency
2156  * @dev_priv: i915 device
2157  *
2158  * Determine the current CDCLK frequency.
2159  */
2160 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2161 {
2162         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2163
2164         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
2165                          dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
2166                          dev_priv->cdclk.hw.ref);
2167
2168         /*
2169          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2170          * Programmng [sic] note: bit[9:2] should be programmed to the number
2171          * of cdclk that generates 4MHz reference clock freq which is used to
2172          * generate GMBus clock. This will vary with the cdclk freq.
2173          */
2174         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2175                 I915_WRITE(GMBUSFREQ_VLV,
2176                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2177 }
2178
2179 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2180 {
2181         u32 rawclk;
2182         int divider, fraction;
2183
2184         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2185                 /* 24 MHz */
2186                 divider = 24000;
2187                 fraction = 0;
2188         } else {
2189                 /* 19.2 MHz */
2190                 divider = 19000;
2191                 fraction = 200;
2192         }
2193
2194         rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2195         if (fraction)
2196                 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2197                                                             fraction) - 1);
2198
2199         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2200         return divider + fraction;
2201 }
2202
2203 static int pch_rawclk(struct drm_i915_private *dev_priv)
2204 {
2205         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2206 }
2207
2208 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2209 {
2210         /* RAWCLK_FREQ_VLV register updated from power well code */
2211         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2212                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2213 }
2214
2215 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2216 {
2217         uint32_t clkcfg;
2218
2219         /* hrawclock is 1/4 the FSB frequency */
2220         clkcfg = I915_READ(CLKCFG);
2221         switch (clkcfg & CLKCFG_FSB_MASK) {
2222         case CLKCFG_FSB_400:
2223                 return 100000;
2224         case CLKCFG_FSB_533:
2225                 return 133333;
2226         case CLKCFG_FSB_667:
2227                 return 166667;
2228         case CLKCFG_FSB_800:
2229                 return 200000;
2230         case CLKCFG_FSB_1067:
2231         case CLKCFG_FSB_1067_ALT:
2232                 return 266667;
2233         case CLKCFG_FSB_1333:
2234         case CLKCFG_FSB_1333_ALT:
2235                 return 333333;
2236         default:
2237                 return 133333;
2238         }
2239 }
2240
2241 /**
2242  * intel_update_rawclk - Determine the current RAWCLK frequency
2243  * @dev_priv: i915 device
2244  *
2245  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2246  * frequency clock so this needs to done only once.
2247  */
2248 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2249 {
2250
2251         if (HAS_PCH_CNP(dev_priv))
2252                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2253         else if (HAS_PCH_SPLIT(dev_priv))
2254                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2255         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2256                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2257         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2258                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2259         else
2260                 /* no rawclk on other platforms, or no need to know it */
2261                 return;
2262
2263         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2264 }
2265
2266 /**
2267  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2268  * @dev_priv: i915 device
2269  */
2270 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2271 {
2272         if (IS_CHERRYVIEW(dev_priv)) {
2273                 dev_priv->display.set_cdclk = chv_set_cdclk;
2274                 dev_priv->display.modeset_calc_cdclk =
2275                         vlv_modeset_calc_cdclk;
2276         } else if (IS_VALLEYVIEW(dev_priv)) {
2277                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2278                 dev_priv->display.modeset_calc_cdclk =
2279                         vlv_modeset_calc_cdclk;
2280         } else if (IS_BROADWELL(dev_priv)) {
2281                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2282                 dev_priv->display.modeset_calc_cdclk =
2283                         bdw_modeset_calc_cdclk;
2284         } else if (IS_GEN9_LP(dev_priv)) {
2285                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2286                 dev_priv->display.modeset_calc_cdclk =
2287                         bxt_modeset_calc_cdclk;
2288         } else if (IS_GEN9_BC(dev_priv)) {
2289                 dev_priv->display.set_cdclk = skl_set_cdclk;
2290                 dev_priv->display.modeset_calc_cdclk =
2291                         skl_modeset_calc_cdclk;
2292         } else if (IS_CANNONLAKE(dev_priv)) {
2293                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2294                 dev_priv->display.modeset_calc_cdclk =
2295                         cnl_modeset_calc_cdclk;
2296         }
2297
2298         if (IS_CANNONLAKE(dev_priv))
2299                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2300         else if (IS_GEN9_BC(dev_priv))
2301                 dev_priv->display.get_cdclk = skl_get_cdclk;
2302         else if (IS_GEN9_LP(dev_priv))
2303                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2304         else if (IS_BROADWELL(dev_priv))
2305                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2306         else if (IS_HASWELL(dev_priv))
2307                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2308         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2309                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2310         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2311                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2312         else if (IS_GEN5(dev_priv))
2313                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2314         else if (IS_GM45(dev_priv))
2315                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2316         else if (IS_G45(dev_priv))
2317                 dev_priv->display.get_cdclk = g33_get_cdclk;
2318         else if (IS_I965GM(dev_priv))
2319                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2320         else if (IS_I965G(dev_priv))
2321                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2322         else if (IS_PINEVIEW(dev_priv))
2323                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2324         else if (IS_G33(dev_priv))
2325                 dev_priv->display.get_cdclk = g33_get_cdclk;
2326         else if (IS_I945GM(dev_priv))
2327                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2328         else if (IS_I945G(dev_priv))
2329                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2330         else if (IS_I915GM(dev_priv))
2331                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2332         else if (IS_I915G(dev_priv))
2333                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2334         else if (IS_I865G(dev_priv))
2335                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2336         else if (IS_I85X(dev_priv))
2337                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2338         else if (IS_I845G(dev_priv))
2339                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2340         else { /* 830 */
2341                 WARN(!IS_I830(dev_priv),
2342                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2343                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2344         }
2345 }