2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include "intel_drv.h"
30 #include <drm/drm_edid.h>
34 * DOC: High Definition Audio over HDMI and Display Port
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
44 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
58 } hdmi_audio_clock[] = {
59 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
60 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
61 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
62 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
63 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
64 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
65 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
66 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
67 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
68 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
71 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
72 static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
76 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
77 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
81 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
82 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
83 adjusted_mode->crtc_clock);
87 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
88 hdmi_audio_clock[i].clock,
89 hdmi_audio_clock[i].config);
91 return hdmi_audio_clock[i].config;
94 static bool intel_eld_uptodate(struct drm_connector *connector,
95 int reg_eldv, uint32_t bits_eldv,
96 int reg_elda, uint32_t bits_elda,
99 struct drm_i915_private *dev_priv = connector->dev->dev_private;
100 uint8_t *eld = connector->eld;
104 tmp = I915_READ(reg_eldv);
110 tmp = I915_READ(reg_elda);
112 I915_WRITE(reg_elda, tmp);
114 for (i = 0; i < drm_eld_size(eld) / 4; i++)
115 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
121 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
123 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
126 DRM_DEBUG_KMS("Disable audio codec\n");
128 tmp = I915_READ(G4X_AUD_VID_DID);
129 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
130 eldv = G4X_ELDV_DEVCL_DEVBLC;
132 eldv = G4X_ELDV_DEVCTG;
135 tmp = I915_READ(G4X_AUD_CNTL_ST);
137 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
140 static void g4x_audio_codec_enable(struct drm_connector *connector,
141 struct intel_encoder *encoder,
142 const struct drm_display_mode *adjusted_mode)
144 struct drm_i915_private *dev_priv = connector->dev->dev_private;
145 uint8_t *eld = connector->eld;
150 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
152 tmp = I915_READ(G4X_AUD_VID_DID);
153 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
154 eldv = G4X_ELDV_DEVCL_DEVBLC;
156 eldv = G4X_ELDV_DEVCTG;
158 if (intel_eld_uptodate(connector,
159 G4X_AUD_CNTL_ST, eldv,
160 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
164 tmp = I915_READ(G4X_AUD_CNTL_ST);
165 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
166 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
167 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
169 len = min(drm_eld_size(eld) / 4, len);
170 DRM_DEBUG_DRIVER("ELD size %d\n", len);
171 for (i = 0; i < len; i++)
172 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
174 tmp = I915_READ(G4X_AUD_CNTL_ST);
176 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
179 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
181 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
182 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
183 enum pipe pipe = intel_crtc->pipe;
186 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
188 /* Disable timestamps */
189 tmp = I915_READ(HSW_AUD_CFG(pipe));
190 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
191 tmp |= AUD_CONFIG_N_PROG_ENABLE;
192 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
193 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
194 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
195 tmp |= AUD_CONFIG_N_VALUE_INDEX;
196 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
199 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
200 tmp &= ~AUDIO_ELD_VALID(pipe);
201 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
202 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
205 static void hsw_audio_codec_enable(struct drm_connector *connector,
206 struct intel_encoder *encoder,
207 const struct drm_display_mode *adjusted_mode)
209 struct drm_i915_private *dev_priv = connector->dev->dev_private;
210 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
211 enum pipe pipe = intel_crtc->pipe;
212 const uint8_t *eld = connector->eld;
216 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
217 pipe_name(pipe), drm_eld_size(eld));
219 /* Enable audio presence detect, invalidate ELD */
220 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
221 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
222 tmp &= ~AUDIO_ELD_VALID(pipe);
223 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
226 * FIXME: We're supposed to wait for vblank here, but we have vblanks
227 * disabled during the mode set. The proper fix would be to push the
228 * rest of the setup into a vblank work item, queued here, but the
229 * infrastructure is not there yet.
232 /* Reset ELD write address */
233 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
234 tmp &= ~IBX_ELD_ADDRESS_MASK;
235 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
237 /* Up to 84 bytes of hw ELD buffer */
238 len = min(drm_eld_size(eld), 84);
239 for (i = 0; i < len / 4; i++)
240 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
243 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
244 tmp |= AUDIO_ELD_VALID(pipe);
245 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
247 /* Enable timestamps */
248 tmp = I915_READ(HSW_AUD_CFG(pipe));
249 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
250 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
251 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
252 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
253 tmp |= AUD_CONFIG_N_VALUE_INDEX;
255 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
256 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
259 static void ilk_audio_codec_disable(struct intel_encoder *encoder)
261 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
262 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
263 struct intel_digital_port *intel_dig_port =
264 enc_to_dig_port(&encoder->base);
265 enum port port = intel_dig_port->port;
266 enum pipe pipe = intel_crtc->pipe;
271 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
272 port_name(port), pipe_name(pipe));
274 if (WARN_ON(port == PORT_A))
277 if (HAS_PCH_IBX(dev_priv->dev)) {
278 aud_config = IBX_AUD_CFG(pipe);
279 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
280 } else if (IS_VALLEYVIEW(dev_priv)) {
281 aud_config = VLV_AUD_CFG(pipe);
282 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
284 aud_config = CPT_AUD_CFG(pipe);
285 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
288 /* Disable timestamps */
289 tmp = I915_READ(aud_config);
290 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
291 tmp |= AUD_CONFIG_N_PROG_ENABLE;
292 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
293 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
294 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
295 tmp |= AUD_CONFIG_N_VALUE_INDEX;
296 I915_WRITE(aud_config, tmp);
298 eldv = IBX_ELD_VALID(port);
301 tmp = I915_READ(aud_cntrl_st2);
303 I915_WRITE(aud_cntrl_st2, tmp);
306 static void ilk_audio_codec_enable(struct drm_connector *connector,
307 struct intel_encoder *encoder,
308 const struct drm_display_mode *adjusted_mode)
310 struct drm_i915_private *dev_priv = connector->dev->dev_private;
311 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
312 struct intel_digital_port *intel_dig_port =
313 enc_to_dig_port(&encoder->base);
314 enum port port = intel_dig_port->port;
315 enum pipe pipe = intel_crtc->pipe;
316 uint8_t *eld = connector->eld;
325 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
326 port_name(port), pipe_name(pipe), drm_eld_size(eld));
328 if (WARN_ON(port == PORT_A))
332 * FIXME: We're supposed to wait for vblank here, but we have vblanks
333 * disabled during the mode set. The proper fix would be to push the
334 * rest of the setup into a vblank work item, queued here, but the
335 * infrastructure is not there yet.
338 if (HAS_PCH_IBX(connector->dev)) {
339 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
340 aud_config = IBX_AUD_CFG(pipe);
341 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
342 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
343 } else if (IS_VALLEYVIEW(connector->dev)) {
344 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
345 aud_config = VLV_AUD_CFG(pipe);
346 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
347 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
349 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
350 aud_config = CPT_AUD_CFG(pipe);
351 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
352 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
355 eldv = IBX_ELD_VALID(port);
358 tmp = I915_READ(aud_cntrl_st2);
360 I915_WRITE(aud_cntrl_st2, tmp);
362 /* Reset ELD write address */
363 tmp = I915_READ(aud_cntl_st);
364 tmp &= ~IBX_ELD_ADDRESS_MASK;
365 I915_WRITE(aud_cntl_st, tmp);
367 /* Up to 84 bytes of hw ELD buffer */
368 len = min(drm_eld_size(eld), 84);
369 for (i = 0; i < len / 4; i++)
370 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
373 tmp = I915_READ(aud_cntrl_st2);
375 I915_WRITE(aud_cntrl_st2, tmp);
377 /* Enable timestamps */
378 tmp = I915_READ(aud_config);
379 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
380 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
381 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
382 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
383 tmp |= AUD_CONFIG_N_VALUE_INDEX;
385 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
386 I915_WRITE(aud_config, tmp);
390 * intel_audio_codec_enable - Enable the audio codec for HD audio
391 * @intel_encoder: encoder on which to enable audio
393 * The enable sequences may only be performed after enabling the transcoder and
394 * port, and after completed link training.
396 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
398 struct drm_encoder *encoder = &intel_encoder->base;
399 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
400 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
401 struct drm_connector *connector;
402 struct drm_device *dev = encoder->dev;
403 struct drm_i915_private *dev_priv = dev->dev_private;
404 struct i915_audio_component *acomp = dev_priv->audio_component;
405 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
406 enum port port = intel_dig_port->port;
408 connector = drm_select_eld(encoder);
412 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
415 connector->encoder->base.id,
416 connector->encoder->name);
419 connector->eld[5] &= ~(3 << 2);
420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
421 connector->eld[5] |= (1 << 2);
423 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
425 if (dev_priv->display.audio_codec_enable)
426 dev_priv->display.audio_codec_enable(connector, intel_encoder,
429 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
430 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
434 * intel_audio_codec_disable - Disable the audio codec for HD audio
435 * @intel_encoder: encoder on which to disable audio
437 * The disable sequences must be performed before disabling the transcoder or
440 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
442 struct drm_encoder *encoder = &intel_encoder->base;
443 struct drm_device *dev = encoder->dev;
444 struct drm_i915_private *dev_priv = dev->dev_private;
445 struct i915_audio_component *acomp = dev_priv->audio_component;
446 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
447 enum port port = intel_dig_port->port;
449 if (dev_priv->display.audio_codec_disable)
450 dev_priv->display.audio_codec_disable(intel_encoder);
452 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
453 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
457 * intel_init_audio - Set up chip specific audio functions
460 void intel_init_audio(struct drm_device *dev)
462 struct drm_i915_private *dev_priv = dev->dev_private;
465 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
466 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
467 } else if (IS_VALLEYVIEW(dev)) {
468 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
469 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
470 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
471 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
472 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
473 } else if (HAS_PCH_SPLIT(dev)) {
474 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
475 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
479 static void i915_audio_component_get_power(struct device *dev)
481 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
484 static void i915_audio_component_put_power(struct device *dev)
486 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
489 static void i915_audio_component_codec_wake_override(struct device *dev,
492 struct drm_i915_private *dev_priv = dev_to_i915(dev);
495 if (!IS_SKYLAKE(dev_priv))
499 * Enable/disable generating the codec wake signal, overriding the
500 * internal logic to generate the codec wake to controller.
502 tmp = I915_READ(HSW_AUD_CHICKENBIT);
503 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
504 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
505 usleep_range(1000, 1500);
508 tmp = I915_READ(HSW_AUD_CHICKENBIT);
509 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
510 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
511 usleep_range(1000, 1500);
515 /* Get CDCLK in kHz */
516 static int i915_audio_component_get_cdclk_freq(struct device *dev)
518 struct drm_i915_private *dev_priv = dev_to_i915(dev);
521 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
524 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
525 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
527 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
532 static const struct i915_audio_component_ops i915_audio_component_ops = {
533 .owner = THIS_MODULE,
534 .get_power = i915_audio_component_get_power,
535 .put_power = i915_audio_component_put_power,
536 .codec_wake_override = i915_audio_component_codec_wake_override,
537 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
540 static int i915_audio_component_bind(struct device *i915_dev,
541 struct device *hda_dev, void *data)
543 struct i915_audio_component *acomp = data;
544 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
546 if (WARN_ON(acomp->ops || acomp->dev))
549 drm_modeset_lock_all(dev_priv->dev);
550 acomp->ops = &i915_audio_component_ops;
551 acomp->dev = i915_dev;
552 dev_priv->audio_component = acomp;
553 drm_modeset_unlock_all(dev_priv->dev);
558 static void i915_audio_component_unbind(struct device *i915_dev,
559 struct device *hda_dev, void *data)
561 struct i915_audio_component *acomp = data;
562 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
564 drm_modeset_lock_all(dev_priv->dev);
567 dev_priv->audio_component = NULL;
568 drm_modeset_unlock_all(dev_priv->dev);
571 static const struct component_ops i915_audio_component_bind_ops = {
572 .bind = i915_audio_component_bind,
573 .unbind = i915_audio_component_unbind,
577 * i915_audio_component_init - initialize and register the audio component
578 * @dev_priv: i915 device instance
580 * This will register with the component framework a child component which
581 * will bind dynamically to the snd_hda_intel driver's corresponding master
582 * component when the latter is registered. During binding the child
583 * initializes an instance of struct i915_audio_component which it receives
584 * from the master. The master can then start to use the interface defined by
585 * this struct. Each side can break the binding at any point by deregistering
586 * its own component after which each side's component unbind callback is
589 * We ignore any error during registration and continue with reduced
590 * functionality (i.e. without HDMI audio).
592 void i915_audio_component_init(struct drm_i915_private *dev_priv)
596 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
598 DRM_ERROR("failed to add audio component (%d)\n", ret);
599 /* continue with reduced functionality */
603 dev_priv->audio_component_registered = true;
607 * i915_audio_component_cleanup - deregister the audio component
608 * @dev_priv: i915 device instance
610 * Deregisters the audio component, breaking any existing binding to the
611 * corresponding snd_hda_intel driver's master component.
613 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
615 if (!dev_priv->audio_component_registered)
618 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
619 dev_priv->audio_component_registered = false;