2 * Copyright © 2008-2015 Intel Corporation
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25 #include <linux/dma-fence-array.h>
26 #include <linux/dma-fence-chain.h>
27 #include <linux/irq_work.h>
28 #include <linux/prefetch.h>
29 #include <linux/sched.h>
30 #include <linux/sched/clock.h>
31 #include <linux/sched/signal.h>
33 #include "gem/i915_gem_context.h"
34 #include "gt/intel_context.h"
35 #include "gt/intel_ring.h"
36 #include "gt/intel_rps.h"
38 #include "i915_active.h"
40 #include "i915_globals.h"
41 #include "i915_trace.h"
45 struct list_head link;
47 struct i915_sw_fence *fence;
48 void (*hook)(struct i915_request *rq, struct dma_fence *signal);
49 struct i915_request *signal;
52 static struct i915_global_request {
53 struct i915_global base;
54 struct kmem_cache *slab_requests;
55 struct kmem_cache *slab_execute_cbs;
58 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
60 return dev_name(to_request(fence)->i915->drm.dev);
63 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
65 const struct i915_gem_context *ctx;
68 * The timeline struct (as part of the ppgtt underneath a context)
69 * may be freed when the request is no longer in use by the GPU.
70 * We could extend the life of a context to beyond that of all
71 * fences, possibly keeping the hw resource around indefinitely,
72 * or we just give them a false name. Since
73 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
74 * lie seems justifiable.
76 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
79 ctx = i915_request_gem_context(to_request(fence));
81 return "[" DRIVER_NAME "]";
86 static bool i915_fence_signaled(struct dma_fence *fence)
88 return i915_request_completed(to_request(fence));
91 static bool i915_fence_enable_signaling(struct dma_fence *fence)
93 return i915_request_enable_breadcrumb(to_request(fence));
96 static signed long i915_fence_wait(struct dma_fence *fence,
100 return i915_request_wait(to_request(fence),
101 interruptible | I915_WAIT_PRIORITY,
105 struct kmem_cache *i915_request_slab_cache(void)
107 return global.slab_requests;
110 static void i915_fence_release(struct dma_fence *fence)
112 struct i915_request *rq = to_request(fence);
115 * The request is put onto a RCU freelist (i.e. the address
116 * is immediately reused), mark the fences as being freed now.
117 * Otherwise the debugobjects for the fences are only marked as
118 * freed when the slab cache itself is freed, and so we would get
119 * caught trying to reuse dead objects.
121 i915_sw_fence_fini(&rq->submit);
122 i915_sw_fence_fini(&rq->semaphore);
124 /* Keep one request on each engine for reserved use under mempressure */
125 if (!cmpxchg(&rq->engine->request_pool, NULL, rq))
128 kmem_cache_free(global.slab_requests, rq);
131 const struct dma_fence_ops i915_fence_ops = {
132 .get_driver_name = i915_fence_get_driver_name,
133 .get_timeline_name = i915_fence_get_timeline_name,
134 .enable_signaling = i915_fence_enable_signaling,
135 .signaled = i915_fence_signaled,
136 .wait = i915_fence_wait,
137 .release = i915_fence_release,
140 static void irq_execute_cb(struct irq_work *wrk)
142 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
144 i915_sw_fence_complete(cb->fence);
145 kmem_cache_free(global.slab_execute_cbs, cb);
148 static void irq_execute_cb_hook(struct irq_work *wrk)
150 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
152 cb->hook(container_of(cb->fence, struct i915_request, submit),
154 i915_request_put(cb->signal);
159 static void __notify_execute_cb(struct i915_request *rq)
161 struct execute_cb *cb;
163 lockdep_assert_held(&rq->lock);
165 if (list_empty(&rq->execute_cb))
168 list_for_each_entry(cb, &rq->execute_cb, link)
169 irq_work_queue(&cb->work);
172 * XXX Rollback on __i915_request_unsubmit()
174 * In the future, perhaps when we have an active time-slicing scheduler,
175 * it will be interesting to unsubmit parallel execution and remove
176 * busywaits from the GPU until their master is restarted. This is
177 * quite hairy, we have to carefully rollback the fence and do a
178 * preempt-to-idle cycle on the target engine, all the while the
179 * master execute_cb may refire.
181 INIT_LIST_HEAD(&rq->execute_cb);
185 remove_from_client(struct i915_request *request)
187 struct drm_i915_file_private *file_priv;
189 if (!READ_ONCE(request->file_priv))
193 file_priv = xchg(&request->file_priv, NULL);
195 spin_lock(&file_priv->mm.lock);
196 list_del(&request->client_link);
197 spin_unlock(&file_priv->mm.lock);
202 static void free_capture_list(struct i915_request *request)
204 struct i915_capture_list *capture;
206 capture = fetch_and_zero(&request->capture_list);
208 struct i915_capture_list *next = capture->next;
215 static void __i915_request_fill(struct i915_request *rq, u8 val)
217 void *vaddr = rq->ring->vaddr;
221 if (rq->postfix < head) {
222 memset(vaddr + head, val, rq->ring->size - head);
225 memset(vaddr + head, val, rq->postfix - head);
228 static void remove_from_engine(struct i915_request *rq)
230 struct intel_engine_cs *engine, *locked;
233 * Virtual engines complicate acquiring the engine timeline lock,
234 * as their rq->engine pointer is not stable until under that
235 * engine lock. The simple ploy we use is to take the lock then
236 * check that the rq still belongs to the newly locked engine.
238 locked = READ_ONCE(rq->engine);
239 spin_lock_irq(&locked->active.lock);
240 while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
241 spin_unlock(&locked->active.lock);
242 spin_lock(&engine->active.lock);
245 list_del_init(&rq->sched.link);
246 clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
247 clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
248 spin_unlock_irq(&locked->active.lock);
251 bool i915_request_retire(struct i915_request *rq)
253 if (!i915_request_completed(rq))
258 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
259 trace_i915_request_retire(rq);
262 * We know the GPU must have read the request to have
263 * sent us the seqno + interrupt, so use the position
264 * of tail of the request to update the last known position
267 * Note this requires that we are always called in request
270 GEM_BUG_ON(!list_is_first(&rq->link,
271 &i915_request_timeline(rq)->requests));
272 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
273 /* Poison before we release our space in the ring */
274 __i915_request_fill(rq, POISON_FREE);
275 rq->ring->head = rq->postfix;
278 * We only loosely track inflight requests across preemption,
279 * and so we may find ourselves attempting to retire a _completed_
280 * request that we have removed from the HW and put back on a run
283 remove_from_engine(rq);
285 spin_lock_irq(&rq->lock);
286 i915_request_mark_complete(rq);
287 if (!i915_request_signaled(rq))
288 dma_fence_signal_locked(&rq->fence);
289 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
290 i915_request_cancel_breadcrumb(rq);
291 if (i915_request_has_waitboost(rq)) {
292 GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters));
293 atomic_dec(&rq->engine->gt->rps.num_waiters);
295 if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) {
296 set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
297 __notify_execute_cb(rq);
299 GEM_BUG_ON(!list_empty(&rq->execute_cb));
300 spin_unlock_irq(&rq->lock);
302 remove_from_client(rq);
303 __list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */
305 intel_context_exit(rq->context);
306 intel_context_unpin(rq->context);
308 free_capture_list(rq);
309 i915_sched_node_fini(&rq->sched);
310 i915_request_put(rq);
315 void i915_request_retire_upto(struct i915_request *rq)
317 struct intel_timeline * const tl = i915_request_timeline(rq);
318 struct i915_request *tmp;
322 GEM_BUG_ON(!i915_request_completed(rq));
325 tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
326 } while (i915_request_retire(tmp) && tmp != rq);
330 __await_execution(struct i915_request *rq,
331 struct i915_request *signal,
332 void (*hook)(struct i915_request *rq,
333 struct dma_fence *signal),
336 struct execute_cb *cb;
338 if (i915_request_is_active(signal)) {
340 hook(rq, &signal->fence);
344 cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
348 cb->fence = &rq->submit;
349 i915_sw_fence_await(cb->fence);
350 init_irq_work(&cb->work, irq_execute_cb);
354 cb->signal = i915_request_get(signal);
355 cb->work.func = irq_execute_cb_hook;
358 spin_lock_irq(&signal->lock);
359 if (i915_request_is_active(signal)) {
361 hook(rq, &signal->fence);
362 i915_request_put(signal);
364 i915_sw_fence_complete(cb->fence);
365 kmem_cache_free(global.slab_execute_cbs, cb);
367 list_add_tail(&cb->link, &signal->execute_cb);
369 spin_unlock_irq(&signal->lock);
374 static bool fatal_error(int error)
377 case 0: /* not an error! */
378 case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */
379 case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */
386 void __i915_request_skip(struct i915_request *rq)
388 GEM_BUG_ON(!fatal_error(rq->fence.error));
390 if (rq->infix == rq->postfix)
394 * As this request likely depends on state from the lost
395 * context, clear out all the user operations leaving the
396 * breadcrumb at the end (so we get the fence notifications).
398 __i915_request_fill(rq, 0);
399 rq->infix = rq->postfix;
402 void i915_request_set_error_once(struct i915_request *rq, int error)
406 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
408 if (i915_request_signaled(rq))
411 old = READ_ONCE(rq->fence.error);
413 if (fatal_error(old))
415 } while (!try_cmpxchg(&rq->fence.error, &old, error));
418 bool __i915_request_submit(struct i915_request *request)
420 struct intel_engine_cs *engine = request->engine;
423 RQ_TRACE(request, "\n");
425 GEM_BUG_ON(!irqs_disabled());
426 lockdep_assert_held(&engine->active.lock);
429 * With the advent of preempt-to-busy, we frequently encounter
430 * requests that we have unsubmitted from HW, but left running
431 * until the next ack and so have completed in the meantime. On
432 * resubmission of that completed request, we can skip
433 * updating the payload, and execlists can even skip submitting
436 * We must remove the request from the caller's priority queue,
437 * and the caller must only call us when the request is in their
438 * priority queue, under the active.lock. This ensures that the
439 * request has *not* yet been retired and we can safely move
440 * the request into the engine->active.list where it will be
441 * dropped upon retiring. (Otherwise if resubmit a *retired*
442 * request, this would be a horrible use-after-free.)
444 if (i915_request_completed(request))
447 if (unlikely(intel_context_is_banned(request->context)))
448 i915_request_set_error_once(request, -EIO);
449 if (unlikely(fatal_error(request->fence.error)))
450 __i915_request_skip(request);
453 * Are we using semaphores when the gpu is already saturated?
455 * Using semaphores incurs a cost in having the GPU poll a
456 * memory location, busywaiting for it to change. The continual
457 * memory reads can have a noticeable impact on the rest of the
458 * system with the extra bus traffic, stalling the cpu as it too
459 * tries to access memory across the bus (perf stat -e bus-cycles).
461 * If we installed a semaphore on this request and we only submit
462 * the request after the signaler completed, that indicates the
463 * system is overloaded and using semaphores at this time only
464 * increases the amount of work we are doing. If so, we disable
465 * further use of semaphores until we are idle again, whence we
466 * optimistically try again.
468 if (request->sched.semaphores &&
469 i915_sw_fence_signaled(&request->semaphore))
470 engine->saturated |= request->sched.semaphores;
472 engine->emit_fini_breadcrumb(request,
473 request->ring->vaddr + request->postfix);
475 trace_i915_request_execute(request);
479 xfer: /* We may be recursing from the signal callback of another i915 fence */
480 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
482 if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) {
483 list_move_tail(&request->sched.link, &engine->active.requests);
484 clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
487 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) &&
488 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) &&
489 !i915_request_enable_breadcrumb(request))
490 intel_engine_signal_breadcrumbs(engine);
492 __notify_execute_cb(request);
494 spin_unlock(&request->lock);
499 void i915_request_submit(struct i915_request *request)
501 struct intel_engine_cs *engine = request->engine;
504 /* Will be called from irq-context when using foreign fences. */
505 spin_lock_irqsave(&engine->active.lock, flags);
507 __i915_request_submit(request);
509 spin_unlock_irqrestore(&engine->active.lock, flags);
512 void __i915_request_unsubmit(struct i915_request *request)
514 struct intel_engine_cs *engine = request->engine;
516 RQ_TRACE(request, "\n");
518 GEM_BUG_ON(!irqs_disabled());
519 lockdep_assert_held(&engine->active.lock);
522 * Only unwind in reverse order, required so that the per-context list
523 * is kept in seqno/ring order.
526 /* We may be recursing from the signal callback of another i915 fence */
527 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
529 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
530 i915_request_cancel_breadcrumb(request);
532 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
533 clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
535 spin_unlock(&request->lock);
537 /* We've already spun, don't charge on resubmitting. */
538 if (request->sched.semaphores && i915_request_started(request))
539 request->sched.semaphores = 0;
542 * We don't need to wake_up any waiters on request->execute, they
543 * will get woken by any other event or us re-adding this request
544 * to the engine timeline (__i915_request_submit()). The waiters
545 * should be quite adapt at finding that the request now has a new
546 * global_seqno to the one they went to sleep on.
550 void i915_request_unsubmit(struct i915_request *request)
552 struct intel_engine_cs *engine = request->engine;
555 /* Will be called from irq-context when using foreign fences. */
556 spin_lock_irqsave(&engine->active.lock, flags);
558 __i915_request_unsubmit(request);
560 spin_unlock_irqrestore(&engine->active.lock, flags);
563 static int __i915_sw_fence_call
564 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
566 struct i915_request *request =
567 container_of(fence, typeof(*request), submit);
571 trace_i915_request_submit(request);
573 if (unlikely(fence->error))
574 i915_request_set_error_once(request, fence->error);
577 * We need to serialize use of the submit_request() callback
578 * with its hotplugging performed during an emergency
579 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
580 * critical section in order to force i915_gem_set_wedged() to
581 * wait until the submit_request() is completed before
585 request->engine->submit_request(request);
590 i915_request_put(request);
597 static int __i915_sw_fence_call
598 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
600 struct i915_request *rq = container_of(fence, typeof(*rq), semaphore);
607 i915_request_put(rq);
614 static void retire_requests(struct intel_timeline *tl)
616 struct i915_request *rq, *rn;
618 list_for_each_entry_safe(rq, rn, &tl->requests, link)
619 if (!i915_request_retire(rq))
623 static noinline struct i915_request *
624 request_alloc_slow(struct intel_timeline *tl,
625 struct i915_request **rsvd,
628 struct i915_request *rq;
630 /* If we cannot wait, dip into our reserves */
631 if (!gfpflags_allow_blocking(gfp)) {
632 rq = xchg(rsvd, NULL);
633 if (!rq) /* Use the normal failure path for one final WARN */
639 if (list_empty(&tl->requests))
642 /* Move our oldest request to the slab-cache (if not in use!) */
643 rq = list_first_entry(&tl->requests, typeof(*rq), link);
644 i915_request_retire(rq);
646 rq = kmem_cache_alloc(global.slab_requests,
647 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
651 /* Ratelimit ourselves to prevent oom from malicious clients */
652 rq = list_last_entry(&tl->requests, typeof(*rq), link);
653 cond_synchronize_rcu(rq->rcustate);
655 /* Retire our old requests in the hope that we free some */
659 return kmem_cache_alloc(global.slab_requests, gfp);
662 static void __i915_request_ctor(void *arg)
664 struct i915_request *rq = arg;
666 spin_lock_init(&rq->lock);
667 i915_sched_node_init(&rq->sched);
668 i915_sw_fence_init(&rq->submit, submit_notify);
669 i915_sw_fence_init(&rq->semaphore, semaphore_notify);
671 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0);
673 rq->file_priv = NULL;
674 rq->capture_list = NULL;
676 INIT_LIST_HEAD(&rq->execute_cb);
679 struct i915_request *
680 __i915_request_create(struct intel_context *ce, gfp_t gfp)
682 struct intel_timeline *tl = ce->timeline;
683 struct i915_request *rq;
687 might_sleep_if(gfpflags_allow_blocking(gfp));
689 /* Check that the caller provided an already pinned context */
690 __intel_context_pin(ce);
693 * Beware: Dragons be flying overhead.
695 * We use RCU to look up requests in flight. The lookups may
696 * race with the request being allocated from the slab freelist.
697 * That is the request we are writing to here, may be in the process
698 * of being read by __i915_active_request_get_rcu(). As such,
699 * we have to be very careful when overwriting the contents. During
700 * the RCU lookup, we change chase the request->engine pointer,
701 * read the request->global_seqno and increment the reference count.
703 * The reference count is incremented atomically. If it is zero,
704 * the lookup knows the request is unallocated and complete. Otherwise,
705 * it is either still in use, or has been reallocated and reset
706 * with dma_fence_init(). This increment is safe for release as we
707 * check that the request we have a reference to and matches the active
710 * Before we increment the refcount, we chase the request->engine
711 * pointer. We must not call kmem_cache_zalloc() or else we set
712 * that pointer to NULL and cause a crash during the lookup. If
713 * we see the request is completed (based on the value of the
714 * old engine and seqno), the lookup is complete and reports NULL.
715 * If we decide the request is not completed (new engine or seqno),
716 * then we grab a reference and double check that it is still the
717 * active request - which it won't be and restart the lookup.
719 * Do not use kmem_cache_zalloc() here!
721 rq = kmem_cache_alloc(global.slab_requests,
722 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
724 rq = request_alloc_slow(tl, &ce->engine->request_pool, gfp);
731 rq->i915 = ce->engine->i915;
733 rq->engine = ce->engine;
735 rq->execution_mask = ce->engine->mask;
737 kref_init(&rq->fence.refcount);
740 INIT_LIST_HEAD(&rq->fence.cb_list);
742 ret = intel_timeline_get_seqno(tl, rq, &seqno);
746 rq->fence.context = tl->fence_context;
747 rq->fence.seqno = seqno;
749 RCU_INIT_POINTER(rq->timeline, tl);
750 RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline);
751 rq->hwsp_seqno = tl->hwsp_seqno;
752 GEM_BUG_ON(i915_request_completed(rq));
754 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
756 /* We bump the ref for the fence chain */
757 i915_sw_fence_reinit(&i915_request_get(rq)->submit);
758 i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
760 i915_sched_node_reinit(&rq->sched);
762 /* No zalloc, everything must be cleared after use */
764 GEM_BUG_ON(rq->file_priv);
765 GEM_BUG_ON(rq->capture_list);
766 GEM_BUG_ON(!list_empty(&rq->execute_cb));
769 * Reserve space in the ring buffer for all the commands required to
770 * eventually emit this request. This is to guarantee that the
771 * i915_request_add() call can't fail. Note that the reserve may need
772 * to be redone if the request is not actually submitted straight
773 * away, e.g. because a GPU scheduler has deferred it.
775 * Note that due to how we add reserved_space to intel_ring_begin()
776 * we need to double our request to ensure that if we need to wrap
777 * around inside i915_request_add() there is sufficient space at
778 * the beginning of the ring as well.
781 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
784 * Record the position of the start of the request so that
785 * should we detect the updated seqno part-way through the
786 * GPU processing the request, we never over-estimate the
787 * position of the head.
789 rq->head = rq->ring->emit;
791 ret = rq->engine->request_alloc(rq);
795 rq->infix = rq->ring->emit; /* end of header; start of user payload */
797 intel_context_mark_active(ce);
798 list_add_tail_rcu(&rq->link, &tl->requests);
803 ce->ring->emit = rq->head;
805 /* Make sure we didn't add ourselves to external state before freeing */
806 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
807 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
810 kmem_cache_free(global.slab_requests, rq);
812 intel_context_unpin(ce);
816 struct i915_request *
817 i915_request_create(struct intel_context *ce)
819 struct i915_request *rq;
820 struct intel_timeline *tl;
822 tl = intel_context_timeline_lock(ce);
826 /* Move our oldest request to the slab-cache (if not in use!) */
827 rq = list_first_entry(&tl->requests, typeof(*rq), link);
828 if (!list_is_last(&rq->link, &tl->requests))
829 i915_request_retire(rq);
831 intel_context_enter(ce);
832 rq = __i915_request_create(ce, GFP_KERNEL);
833 intel_context_exit(ce); /* active reference transferred to request */
837 /* Check that we do not interrupt ourselves with a new request */
838 rq->cookie = lockdep_pin_lock(&tl->mutex);
843 intel_context_timeline_unlock(tl);
848 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
850 struct dma_fence *fence;
853 if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline))
856 if (i915_request_started(signal))
861 spin_lock_irq(&signal->lock);
863 struct list_head *pos = READ_ONCE(signal->link.prev);
864 struct i915_request *prev;
866 /* Confirm signal has not been retired, the link is valid */
867 if (unlikely(i915_request_started(signal)))
870 /* Is signal the earliest request on its timeline? */
871 if (pos == &rcu_dereference(signal->timeline)->requests)
875 * Peek at the request before us in the timeline. That
876 * request will only be valid before it is retired, so
877 * after acquiring a reference to it, confirm that it is
878 * still part of the signaler's timeline.
880 prev = list_entry(pos, typeof(*prev), link);
881 if (!i915_request_get_rcu(prev))
884 /* After the strong barrier, confirm prev is still attached */
885 if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
886 i915_request_put(prev);
890 fence = &prev->fence;
892 spin_unlock_irq(&signal->lock);
898 if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
899 err = i915_sw_fence_await_dma_fence(&rq->submit,
902 dma_fence_put(fence);
907 static intel_engine_mask_t
908 already_busywaiting(struct i915_request *rq)
911 * Polling a semaphore causes bus traffic, delaying other users of
912 * both the GPU and CPU. We want to limit the impact on others,
913 * while taking advantage of early submission to reduce GPU
914 * latency. Therefore we restrict ourselves to not using more
915 * than one semaphore from each source, and not using a semaphore
916 * if we have detected the engine is saturated (i.e. would not be
917 * submitted early and cause bus traffic reading an already passed
920 * See the are-we-too-late? check in __i915_request_submit().
922 return rq->sched.semaphores | READ_ONCE(rq->engine->saturated);
926 __emit_semaphore_wait(struct i915_request *to,
927 struct i915_request *from,
930 const int has_token = INTEL_GEN(to->i915) >= 12;
935 GEM_BUG_ON(INTEL_GEN(to->i915) < 8);
936 GEM_BUG_ON(i915_request_has_initial_breadcrumb(to));
938 /* We need to pin the signaler's HWSP until we are finished reading. */
939 err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
947 cs = intel_ring_begin(to, len);
952 * Using greater-than-or-equal here means we have to worry
953 * about seqno wraparound. To side step that issue, we swap
954 * the timeline HWSP upon wrapping, so that everyone listening
955 * for the old (pre-wrap) values do not see the much smaller
956 * (post-wrap) values than they were expecting (and so wait
959 *cs++ = (MI_SEMAPHORE_WAIT |
960 MI_SEMAPHORE_GLOBAL_GTT |
962 MI_SEMAPHORE_SAD_GTE_SDD) +
972 intel_ring_advance(to, cs);
977 emit_semaphore_wait(struct i915_request *to,
978 struct i915_request *from,
981 const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask;
982 struct i915_sw_fence *wait = &to->submit;
984 if (!intel_context_use_semaphores(to->context))
987 if (i915_request_has_initial_breadcrumb(to))
990 if (!rcu_access_pointer(from->hwsp_cacheline))
994 * If this or its dependents are waiting on an external fence
995 * that may fail catastrophically, then we want to avoid using
996 * sempahores as they bypass the fence signaling metadata, and we
997 * lose the fence->error propagation.
999 if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN)
1002 /* Just emit the first semaphore we see as request space is limited. */
1003 if (already_busywaiting(to) & mask)
1006 if (i915_request_await_start(to, from) < 0)
1009 /* Only submit our spinner after the signaler is running! */
1010 if (__await_execution(to, from, NULL, gfp))
1013 if (__emit_semaphore_wait(to, from, from->fence.seqno))
1016 to->sched.semaphores |= mask;
1017 wait = &to->semaphore;
1020 return i915_sw_fence_await_dma_fence(wait,
1026 i915_request_await_request(struct i915_request *to, struct i915_request *from)
1030 GEM_BUG_ON(to == from);
1031 GEM_BUG_ON(to->timeline == from->timeline);
1033 if (i915_request_completed(from)) {
1034 i915_sw_fence_set_error_once(&to->submit, from->fence.error);
1038 if (to->engine->schedule) {
1039 ret = i915_sched_node_add_dependency(&to->sched,
1041 I915_DEPENDENCY_EXTERNAL);
1046 if (to->engine == from->engine)
1047 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
1051 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
1058 static void mark_external(struct i915_request *rq)
1061 * The downside of using semaphores is that we lose metadata passing
1062 * along the signaling chain. This is particularly nasty when we
1063 * need to pass along a fatal error such as EFAULT or EDEADLK. For
1064 * fatal errors we want to scrub the request before it is executed,
1065 * which means that we cannot preload the request onto HW and have
1066 * it wait upon a semaphore.
1068 rq->sched.flags |= I915_SCHED_HAS_EXTERNAL_CHAIN;
1072 __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1075 return i915_sw_fence_await_dma_fence(&rq->submit, fence,
1076 i915_fence_context_timeout(rq->i915,
1082 i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1084 struct dma_fence *iter;
1087 if (!to_dma_fence_chain(fence))
1088 return __i915_request_await_external(rq, fence);
1090 dma_fence_chain_for_each(iter, fence) {
1091 struct dma_fence_chain *chain = to_dma_fence_chain(iter);
1093 if (!dma_fence_is_i915(chain->fence)) {
1094 err = __i915_request_await_external(rq, iter);
1098 err = i915_request_await_dma_fence(rq, chain->fence);
1103 dma_fence_put(iter);
1108 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
1110 struct dma_fence **child = &fence;
1111 unsigned int nchild = 1;
1115 * Note that if the fence-array was created in signal-on-any mode,
1116 * we should *not* decompose it into its individual fences. However,
1117 * we don't currently store which mode the fence-array is operating
1118 * in. Fortunately, the only user of signal-on-any is private to
1119 * amdgpu and we should not see any incoming fence-array from
1120 * sync-file being in signal-on-any mode.
1122 if (dma_fence_is_array(fence)) {
1123 struct dma_fence_array *array = to_dma_fence_array(fence);
1125 child = array->fences;
1126 nchild = array->num_fences;
1127 GEM_BUG_ON(!nchild);
1132 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1133 i915_sw_fence_set_error_once(&rq->submit, fence->error);
1138 * Requests on the same timeline are explicitly ordered, along
1139 * with their dependencies, by i915_request_add() which ensures
1140 * that requests are submitted in-order through each ring.
1142 if (fence->context == rq->fence.context)
1145 /* Squash repeated waits to the same timelines */
1146 if (fence->context &&
1147 intel_timeline_sync_is_later(i915_request_timeline(rq),
1151 if (dma_fence_is_i915(fence))
1152 ret = i915_request_await_request(rq, to_request(fence));
1154 ret = i915_request_await_external(rq, fence);
1158 /* Record the latest fence used against each timeline */
1160 intel_timeline_sync_set(i915_request_timeline(rq),
1167 static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
1168 struct dma_fence *fence)
1170 return __intel_timeline_sync_is_later(tl,
1175 static int intel_timeline_sync_set_start(struct intel_timeline *tl,
1176 const struct dma_fence *fence)
1178 return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);
1182 __i915_request_await_execution(struct i915_request *to,
1183 struct i915_request *from,
1184 void (*hook)(struct i915_request *rq,
1185 struct dma_fence *signal))
1189 GEM_BUG_ON(intel_context_is_barrier(from->context));
1191 /* Submit both requests at the same time */
1192 err = __await_execution(to, from, hook, I915_FENCE_GFP);
1196 /* Squash repeated depenendices to the same timelines */
1197 if (intel_timeline_sync_has_start(i915_request_timeline(to),
1202 * Wait until the start of this request.
1204 * The execution cb fires when we submit the request to HW. But in
1205 * many cases this may be long before the request itself is ready to
1206 * run (consider that we submit 2 requests for the same context, where
1207 * the request of interest is behind an indefinite spinner). So we hook
1208 * up to both to reduce our queues and keep the execution lag minimised
1209 * in the worst case, though we hope that the await_start is elided.
1211 err = i915_request_await_start(to, from);
1216 * Ensure both start together [after all semaphores in signal]
1218 * Now that we are queued to the HW at roughly the same time (thanks
1219 * to the execute cb) and are ready to run at roughly the same time
1220 * (thanks to the await start), our signaler may still be indefinitely
1221 * delayed by waiting on a semaphore from a remote engine. If our
1222 * signaler depends on a semaphore, so indirectly do we, and we do not
1223 * want to start our payload until our signaler also starts theirs.
1226 * However, there is also a second condition for which we need to wait
1227 * for the precise start of the signaler. Consider that the signaler
1228 * was submitted in a chain of requests following another context
1229 * (with just an ordinary intra-engine fence dependency between the
1230 * two). In this case the signaler is queued to HW, but not for
1231 * immediate execution, and so we must wait until it reaches the
1234 if (intel_engine_has_semaphores(to->engine) &&
1235 !i915_request_has_initial_breadcrumb(to)) {
1236 err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
1241 /* Couple the dependency tree for PI on this exposed to->fence */
1242 if (to->engine->schedule) {
1243 err = i915_sched_node_add_dependency(&to->sched,
1245 I915_DEPENDENCY_WEAK);
1250 return intel_timeline_sync_set_start(i915_request_timeline(to),
1255 i915_request_await_execution(struct i915_request *rq,
1256 struct dma_fence *fence,
1257 void (*hook)(struct i915_request *rq,
1258 struct dma_fence *signal))
1260 struct dma_fence **child = &fence;
1261 unsigned int nchild = 1;
1264 if (dma_fence_is_array(fence)) {
1265 struct dma_fence_array *array = to_dma_fence_array(fence);
1267 /* XXX Error for signal-on-any fence arrays */
1269 child = array->fences;
1270 nchild = array->num_fences;
1271 GEM_BUG_ON(!nchild);
1276 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1277 i915_sw_fence_set_error_once(&rq->submit, fence->error);
1281 if (fence->context == rq->fence.context)
1285 * We don't squash repeated fence dependencies here as we
1286 * want to run our callback in all cases.
1289 if (dma_fence_is_i915(fence))
1290 ret = __i915_request_await_execution(rq,
1294 ret = i915_request_await_external(rq, fence);
1303 * i915_request_await_object - set this request to (async) wait upon a bo
1304 * @to: request we are wishing to use
1305 * @obj: object which may be in use on another ring.
1306 * @write: whether the wait is on behalf of a writer
1308 * This code is meant to abstract object synchronization with the GPU.
1309 * Conceptually we serialise writes between engines inside the GPU.
1310 * We only allow one engine to write into a buffer at any time, but
1311 * multiple readers. To ensure each has a coherent view of memory, we must:
1313 * - If there is an outstanding write request to the object, the new
1314 * request must wait for it to complete (either CPU or in hw, requests
1315 * on the same ring will be naturally ordered).
1317 * - If we are a write request (pending_write_domain is set), the new
1318 * request must wait for outstanding read requests to complete.
1320 * Returns 0 if successful, else propagates up the lower layer error.
1323 i915_request_await_object(struct i915_request *to,
1324 struct drm_i915_gem_object *obj,
1327 struct dma_fence *excl;
1331 struct dma_fence **shared;
1332 unsigned int count, i;
1334 ret = dma_resv_get_fences_rcu(obj->base.resv,
1335 &excl, &count, &shared);
1339 for (i = 0; i < count; i++) {
1340 ret = i915_request_await_dma_fence(to, shared[i]);
1344 dma_fence_put(shared[i]);
1347 for (; i < count; i++)
1348 dma_fence_put(shared[i]);
1351 excl = dma_resv_get_excl_rcu(obj->base.resv);
1356 ret = i915_request_await_dma_fence(to, excl);
1358 dma_fence_put(excl);
1364 static struct i915_request *
1365 __i915_request_add_to_timeline(struct i915_request *rq)
1367 struct intel_timeline *timeline = i915_request_timeline(rq);
1368 struct i915_request *prev;
1371 * Dependency tracking and request ordering along the timeline
1372 * is special cased so that we can eliminate redundant ordering
1373 * operations while building the request (we know that the timeline
1374 * itself is ordered, and here we guarantee it).
1376 * As we know we will need to emit tracking along the timeline,
1377 * we embed the hooks into our request struct -- at the cost of
1378 * having to have specialised no-allocation interfaces (which will
1379 * be beneficial elsewhere).
1381 * A second benefit to open-coding i915_request_await_request is
1382 * that we can apply a slight variant of the rules specialised
1383 * for timelines that jump between engines (such as virtual engines).
1384 * If we consider the case of virtual engine, we must emit a dma-fence
1385 * to prevent scheduling of the second request until the first is
1386 * complete (to maximise our greedy late load balancing) and this
1387 * precludes optimising to use semaphores serialisation of a single
1388 * timeline across engines.
1390 prev = to_request(__i915_active_fence_set(&timeline->last_request,
1392 if (prev && !i915_request_completed(prev)) {
1394 * The requests are supposed to be kept in order. However,
1395 * we need to be wary in case the timeline->last_request
1396 * is used as a barrier for external modification to this
1399 GEM_BUG_ON(prev->context == rq->context &&
1400 i915_seqno_passed(prev->fence.seqno,
1403 if (is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask))
1404 i915_sw_fence_await_sw_fence(&rq->submit,
1408 __i915_sw_fence_await_dma_fence(&rq->submit,
1411 if (rq->engine->schedule)
1412 __i915_sched_node_add_dependency(&rq->sched,
1419 * Make sure that no request gazumped us - if it was allocated after
1420 * our i915_request_alloc() and called __i915_request_add() before
1421 * us, the timeline will hold its seqno which is later than ours.
1423 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1429 * NB: This function is not allowed to fail. Doing so would mean the the
1430 * request is not being tracked for completion but the work itself is
1431 * going to happen on the hardware. This would be a Bad Thing(tm).
1433 struct i915_request *__i915_request_commit(struct i915_request *rq)
1435 struct intel_engine_cs *engine = rq->engine;
1436 struct intel_ring *ring = rq->ring;
1442 * To ensure that this call will not fail, space for its emissions
1443 * should already have been reserved in the ring buffer. Let the ring
1444 * know that it is time to use that space up.
1446 GEM_BUG_ON(rq->reserved_space > ring->space);
1447 rq->reserved_space = 0;
1448 rq->emitted_jiffies = jiffies;
1451 * Record the position of the start of the breadcrumb so that
1452 * should we detect the updated seqno part-way through the
1453 * GPU processing the request, we never over-estimate the
1454 * position of the ring's HEAD.
1456 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1457 GEM_BUG_ON(IS_ERR(cs));
1458 rq->postfix = intel_ring_offset(rq, cs);
1460 return __i915_request_add_to_timeline(rq);
1463 void __i915_request_queue(struct i915_request *rq,
1464 const struct i915_sched_attr *attr)
1467 * Let the backend know a new request has arrived that may need
1468 * to adjust the existing execution schedule due to a high priority
1469 * request - i.e. we may want to preempt the current request in order
1470 * to run a high priority dependency chain *before* we can execute this
1473 * This is called before the request is ready to run so that we can
1474 * decide whether to preempt the entire chain so that it is ready to
1475 * run at the earliest possible convenience.
1477 if (attr && rq->engine->schedule)
1478 rq->engine->schedule(rq, attr);
1479 i915_sw_fence_commit(&rq->semaphore);
1480 i915_sw_fence_commit(&rq->submit);
1483 void i915_request_add(struct i915_request *rq)
1485 struct intel_timeline * const tl = i915_request_timeline(rq);
1486 struct i915_sched_attr attr = {};
1487 struct i915_gem_context *ctx;
1489 lockdep_assert_held(&tl->mutex);
1490 lockdep_unpin_lock(&tl->mutex, rq->cookie);
1492 trace_i915_request_add(rq);
1493 __i915_request_commit(rq);
1495 /* XXX placeholder for selftests */
1497 ctx = rcu_dereference(rq->context->gem_context);
1502 __i915_request_queue(rq, &attr);
1504 mutex_unlock(&tl->mutex);
1507 static unsigned long local_clock_ns(unsigned int *cpu)
1512 * Cheaply and approximately convert from nanoseconds to microseconds.
1513 * The result and subsequent calculations are also defined in the same
1514 * approximate microseconds units. The principal source of timing
1515 * error here is from the simple truncation.
1517 * Note that local_clock() is only defined wrt to the current CPU;
1518 * the comparisons are no longer valid if we switch CPUs. Instead of
1519 * blocking preemption for the entire busywait, we can detect the CPU
1520 * switch and use that as indicator of system load and a reason to
1521 * stop busywaiting, see busywait_stop().
1530 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1532 unsigned int this_cpu;
1534 if (time_after(local_clock_ns(&this_cpu), timeout))
1537 return this_cpu != cpu;
1540 static bool __i915_spin_request(const struct i915_request * const rq, int state)
1542 unsigned long timeout_ns;
1546 * Only wait for the request if we know it is likely to complete.
1548 * We don't track the timestamps around requests, nor the average
1549 * request length, so we do not have a good indicator that this
1550 * request will complete within the timeout. What we do know is the
1551 * order in which requests are executed by the context and so we can
1552 * tell if the request has been started. If the request is not even
1553 * running yet, it is a fair assumption that it will not complete
1554 * within our relatively short timeout.
1556 if (!i915_request_is_running(rq))
1560 * When waiting for high frequency requests, e.g. during synchronous
1561 * rendering split between the CPU and GPU, the finite amount of time
1562 * required to set up the irq and wait upon it limits the response
1563 * rate. By busywaiting on the request completion for a short while we
1564 * can service the high frequency waits as quick as possible. However,
1565 * if it is a slow request, we want to sleep as quickly as possible.
1566 * The tradeoff between waiting and sleeping is roughly the time it
1567 * takes to sleep on a request, on the order of a microsecond.
1570 timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns);
1571 timeout_ns += local_clock_ns(&cpu);
1573 if (i915_request_completed(rq))
1576 if (signal_pending_state(state, current))
1579 if (busywait_stop(timeout_ns, cpu))
1583 } while (!need_resched());
1588 struct request_wait {
1589 struct dma_fence_cb cb;
1590 struct task_struct *tsk;
1593 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1595 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1597 wake_up_process(wait->tsk);
1601 * i915_request_wait - wait until execution of request has finished
1602 * @rq: the request to wait upon
1603 * @flags: how to wait
1604 * @timeout: how long to wait in jiffies
1606 * i915_request_wait() waits for the request to be completed, for a
1607 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1610 * Returns the remaining time (in jiffies) if the request completed, which may
1611 * be zero or -ETIME if the request is unfinished after the timeout expires.
1612 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1613 * pending before the request completes.
1615 long i915_request_wait(struct i915_request *rq,
1619 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1620 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1621 struct request_wait wait;
1624 GEM_BUG_ON(timeout < 0);
1626 if (dma_fence_is_signaled(&rq->fence))
1632 trace_i915_request_wait_begin(rq, flags);
1635 * We must never wait on the GPU while holding a lock as we
1636 * may need to perform a GPU reset. So while we don't need to
1637 * serialise wait/reset with an explicit lock, we do want
1638 * lockdep to detect potential dependency cycles.
1640 mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
1643 * Optimistic spin before touching IRQs.
1645 * We may use a rather large value here to offset the penalty of
1646 * switching away from the active task. Frequently, the client will
1647 * wait upon an old swapbuffer to throttle itself to remain within a
1648 * frame of the gpu. If the client is running in lockstep with the gpu,
1649 * then it should not be waiting long at all, and a sleep now will incur
1650 * extra scheduler latency in producing the next frame. To try to
1651 * avoid adding the cost of enabling/disabling the interrupt to the
1652 * short wait, we first spin to see if the request would have completed
1653 * in the time taken to setup the interrupt.
1655 * We need upto 5us to enable the irq, and upto 20us to hide the
1656 * scheduler latency of a context switch, ignoring the secondary
1657 * impacts from a context switch such as cache eviction.
1659 * The scheme used for low-latency IO is called "hybrid interrupt
1660 * polling". The suggestion there is to sleep until just before you
1661 * expect to be woken by the device interrupt and then poll for its
1662 * completion. That requires having a good predictor for the request
1663 * duration, which we currently lack.
1665 if (IS_ACTIVE(CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT) &&
1666 __i915_spin_request(rq, state)) {
1667 dma_fence_signal(&rq->fence);
1672 * This client is about to stall waiting for the GPU. In many cases
1673 * this is undesirable and limits the throughput of the system, as
1674 * many clients cannot continue processing user input/output whilst
1675 * blocked. RPS autotuning may take tens of milliseconds to respond
1676 * to the GPU load and thus incurs additional latency for the client.
1677 * We can circumvent that by promoting the GPU frequency to maximum
1678 * before we sleep. This makes the GPU throttle up much more quickly
1679 * (good for benchmarks and user experience, e.g. window animations),
1680 * but at a cost of spending more power processing the workload
1681 * (bad for battery).
1683 if (flags & I915_WAIT_PRIORITY) {
1684 if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
1685 intel_rps_boost(rq);
1689 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1693 set_current_state(state);
1695 if (i915_request_completed(rq)) {
1696 dma_fence_signal(&rq->fence);
1700 intel_engine_flush_submission(rq->engine);
1702 if (signal_pending_state(state, current)) {
1703 timeout = -ERESTARTSYS;
1712 timeout = io_schedule_timeout(timeout);
1714 __set_current_state(TASK_RUNNING);
1716 dma_fence_remove_callback(&rq->fence, &wait.cb);
1719 mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
1720 trace_i915_request_wait_end(rq);
1724 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1725 #include "selftests/mock_request.c"
1726 #include "selftests/i915_request.c"
1729 static void i915_global_request_shrink(void)
1731 kmem_cache_shrink(global.slab_execute_cbs);
1732 kmem_cache_shrink(global.slab_requests);
1735 static void i915_global_request_exit(void)
1737 kmem_cache_destroy(global.slab_execute_cbs);
1738 kmem_cache_destroy(global.slab_requests);
1741 static struct i915_global_request global = { {
1742 .shrink = i915_global_request_shrink,
1743 .exit = i915_global_request_exit,
1746 int __init i915_global_request_init(void)
1748 global.slab_requests =
1749 kmem_cache_create("i915_request",
1750 sizeof(struct i915_request),
1751 __alignof__(struct i915_request),
1752 SLAB_HWCACHE_ALIGN |
1753 SLAB_RECLAIM_ACCOUNT |
1754 SLAB_TYPESAFE_BY_RCU,
1755 __i915_request_ctor);
1756 if (!global.slab_requests)
1759 global.slab_execute_cbs = KMEM_CACHE(execute_cb,
1760 SLAB_HWCACHE_ALIGN |
1761 SLAB_RECLAIM_ACCOUNT |
1762 SLAB_TYPESAFE_BY_RCU);
1763 if (!global.slab_execute_cbs)
1766 i915_global_register(&global.base);
1770 kmem_cache_destroy(global.slab_requests);