1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * DOC: The i915 register macro definition style guide
31 * Follow the style described here for new macros, and while changing existing
32 * macros. Do **not** mass change existing definitions just to update the style.
37 * Keep helper macros near the top. For example, _PIPE() and friends.
39 * Prefix macros that generally should not be used outside of this file with
40 * underscore '_'. For example, _PIPE() and friends, single instances of
41 * registers that are defined solely for the use by function-like macros.
43 * Avoid using the underscore prefixed macros outside of this file. There are
44 * exceptions, but keep them to a minimum.
46 * There are two basic types of register definitions: Single registers and
47 * register groups. Register groups are registers which have two or more
48 * instances, for example one per pipe, port, transcoder, etc. Register groups
49 * should be defined using function-like macros.
51 * For single registers, define the register offset first, followed by register
54 * For register groups, define the register instance offsets first, prefixed
55 * with underscore, followed by a function-like macro choosing the right
56 * instance based on the parameter, followed by register contents.
58 * Define the register contents (i.e. bit and bit field macros) from most
59 * significant to least significant bit. Indent the register content macros
60 * using two extra spaces between ``#define`` and the macro name.
62 * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
63 * contents so that they are already shifted in place, and can be directly
64 * OR'd. For convenience, function-like macros may be used to define bit fields,
65 * but do note that the macros may be needed to read as well as write the
68 * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
69 * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
72 * Group the register and its contents together without blank lines, separate
73 * from other registers and their contents with one blank line.
75 * Indent macro values from macro names using TABs. Align values vertically. Use
76 * braces in macro values as needed to avoid unintended precedence after macro
77 * substitution. Use spaces in macro values according to kernel coding
78 * style. Use lower case in hexadecimal values.
83 * Try to name registers according to the specs. If the register name changes in
84 * the specs from platform to another, stick to the original name.
86 * Try to re-use existing register macro definitions. Only add new macros for
87 * new register offsets, or when the register contents have changed enough to
88 * warrant a full redefinition.
90 * When a register macro changes for a new platform, prefix the new macro using
91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
92 * prefix signifies the start platform/generation using the register.
94 * When a bit (field) macro changes or gets added for a new platform, while
95 * retaining the existing register macro, add a platform acronym or generation
96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
101 * (Note that the values in the example are indented using spaces instead of
102 * TABs to avoid misalignment in generated documentation. Use TABs in the
105 * #define _FOO_A 0xf000
106 * #define _FOO_B 0xf001
107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
108 * #define FOO_ENABLE (1 << 31)
109 * #define FOO_MODE_MASK (0xf << 16)
110 * #define FOO_MODE_SHIFT 16
111 * #define FOO_MODE_BAR (0 << 16)
112 * #define FOO_MODE_BAZ (1 << 16)
113 * #define FOO_MODE_QUX_SNB (2 << 16)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
123 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
125 #define INVALID_MMIO_REG _MMIO(0)
127 static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
132 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
134 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
137 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
139 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
143 * Given the first two numbers __a and __b of arbitrarily many evenly spaced
144 * numbers, pick the 0-based __index'th value.
146 * Always prefer this over _PICK() if the numbers are evenly spaced.
148 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
151 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
153 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
155 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
158 * Named helper wrappers around _PICK_EVEN() and _PICK().
160 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
161 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
162 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
163 #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
164 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
165 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
166 #define _PORT(port, a, b) _PICK_EVEN(port, a, b)
167 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
168 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
169 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
170 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
171 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
172 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
173 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
175 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
176 #define _MASKED_FIELD(mask, value) ({ \
177 if (__builtin_constant_p(mask)) \
178 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
179 if (__builtin_constant_p(value)) \
180 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
181 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
182 BUILD_BUG_ON_MSG((value) & ~(mask), \
183 "Incorrect value for mask"); \
184 __MASKED_FIELD(mask, value); })
185 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
186 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
201 #define RENDER_CLASS 0
202 #define VIDEO_DECODE_CLASS 1
203 #define VIDEO_ENHANCEMENT_CLASS 2
204 #define COPY_ENGINE_CLASS 3
205 #define OTHER_CLASS 4
206 #define MAX_ENGINE_CLASS 4
208 #define OTHER_GTPM_INSTANCE 1
209 #define MAX_ENGINE_INSTANCE 3
211 /* PCI config space */
213 #define MCHBAR_I915 0x44
214 #define MCHBAR_I965 0x48
215 #define MCHBAR_SIZE (4 * 4096)
218 #define DEVEN_MCHBAR_EN (1 << 28)
220 /* BSM in include/drm/i915_drm.h */
222 #define HPLLCC 0xc0 /* 85x only */
223 #define GC_CLOCK_CONTROL_MASK (0x7 << 0)
224 #define GC_CLOCK_133_200 (0 << 0)
225 #define GC_CLOCK_100_200 (1 << 0)
226 #define GC_CLOCK_100_133 (2 << 0)
227 #define GC_CLOCK_133_266 (3 << 0)
228 #define GC_CLOCK_133_200_2 (4 << 0)
229 #define GC_CLOCK_133_266_2 (5 << 0)
230 #define GC_CLOCK_166_266 (6 << 0)
231 #define GC_CLOCK_166_250 (7 << 0)
233 #define I915_GDRST 0xc0 /* PCI config register */
234 #define GRDOM_FULL (0 << 2)
235 #define GRDOM_RENDER (1 << 2)
236 #define GRDOM_MEDIA (3 << 2)
237 #define GRDOM_MASK (3 << 2)
238 #define GRDOM_RESET_STATUS (1 << 1)
239 #define GRDOM_RESET_ENABLE (1 << 0)
241 /* BSpec only has register offset, PCI device and bit found empirically */
242 #define I830_CLOCK_GATE 0xc8 /* device 0 */
243 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
245 #define GCDGMBUS 0xcc
248 #define GCFGC 0xf0 /* 915+ only */
249 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
250 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
251 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
252 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
253 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
254 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
255 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
256 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
257 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
258 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
259 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
260 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
261 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
262 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
263 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
264 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
265 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
266 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
267 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
268 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
269 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
270 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
271 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
272 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
273 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
274 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
275 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
276 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
277 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
283 #define SWSCI_SCISEL (1 << 15)
284 #define SWSCI_GSSCIE (1 << 0)
286 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
289 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
290 #define ILK_GRDOM_FULL (0 << 1)
291 #define ILK_GRDOM_RENDER (1 << 1)
292 #define ILK_GRDOM_MEDIA (3 << 1)
293 #define ILK_GRDOM_MASK (3 << 1)
294 #define ILK_GRDOM_RESET_ENABLE (1 << 0)
296 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
297 #define GEN6_MBC_SNPCR_SHIFT 21
298 #define GEN6_MBC_SNPCR_MASK (3 << 21)
299 #define GEN6_MBC_SNPCR_MAX (0 << 21)
300 #define GEN6_MBC_SNPCR_MED (1 << 21)
301 #define GEN6_MBC_SNPCR_LOW (2 << 21)
302 #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */
304 #define VLV_G3DCTL _MMIO(0x9024)
305 #define VLV_GSCKGCTL _MMIO(0x9028)
307 #define GEN6_MBCTL _MMIO(0x0907c)
308 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
309 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
310 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
311 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
312 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
314 #define GEN6_GDRST _MMIO(0x941c)
315 #define GEN6_GRDOM_FULL (1 << 0)
316 #define GEN6_GRDOM_RENDER (1 << 1)
317 #define GEN6_GRDOM_MEDIA (1 << 2)
318 #define GEN6_GRDOM_BLT (1 << 3)
319 #define GEN6_GRDOM_VECS (1 << 4)
320 #define GEN9_GRDOM_GUC (1 << 5)
321 #define GEN8_GRDOM_MEDIA2 (1 << 7)
322 /* GEN11 changed all bit defs except for FULL & RENDER */
323 #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
324 #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
325 #define GEN11_GRDOM_BLT (1 << 2)
326 #define GEN11_GRDOM_GUC (1 << 3)
327 #define GEN11_GRDOM_MEDIA (1 << 5)
328 #define GEN11_GRDOM_MEDIA2 (1 << 6)
329 #define GEN11_GRDOM_MEDIA3 (1 << 7)
330 #define GEN11_GRDOM_MEDIA4 (1 << 8)
331 #define GEN11_GRDOM_VECS (1 << 13)
332 #define GEN11_GRDOM_VECS2 (1 << 14)
334 #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228)
335 #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base + 0x518)
336 #define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base + 0x220)
337 #define PP_DIR_DCLV_2G 0xffffffff
339 #define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
340 #define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8)
342 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
343 #define GEN8_RPCS_ENABLE (1 << 31)
344 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
345 #define GEN8_RPCS_S_CNT_SHIFT 15
346 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
347 #define GEN11_RPCS_S_CNT_SHIFT 12
348 #define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
349 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
350 #define GEN8_RPCS_SS_CNT_SHIFT 8
351 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
352 #define GEN8_RPCS_EU_MAX_SHIFT 4
353 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
354 #define GEN8_RPCS_EU_MIN_SHIFT 0
355 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
357 #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
359 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
360 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
361 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
362 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
364 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
365 #define HSW_RCS_CONTEXT_ENABLE (1 << 7)
366 #define HSW_RCS_INHIBIT (1 << 8)
368 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
369 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
370 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
371 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
372 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
373 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
374 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
375 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
376 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
377 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
379 #define GAM_ECOCHK _MMIO(0x4090)
380 #define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
381 #define ECOCHK_SNB_BIT (1 << 10)
382 #define ECOCHK_DIS_TLB (1 << 8)
383 #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
384 #define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
385 #define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
386 #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
387 #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
388 #define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
389 #define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
390 #define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
392 #define GAC_ECO_BITS _MMIO(0x14090)
393 #define ECOBITS_SNB_BIT (1 << 13)
394 #define ECOBITS_PPGTT_CACHE64B (3 << 8)
395 #define ECOBITS_PPGTT_CACHE4B (0 << 8)
397 #define GAB_CTL _MMIO(0x24000)
398 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
400 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
401 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
402 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
403 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
404 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
405 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
406 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
407 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
408 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
409 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
410 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
411 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
412 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
413 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
414 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
415 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
416 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
417 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
421 #define VGA_ST01_MDA 0x3ba
422 #define VGA_ST01_CGA 0x3da
424 #define _VGA_MSR_WRITE _MMIO(0x3c2)
425 #define VGA_MSR_WRITE 0x3c2
426 #define VGA_MSR_READ 0x3cc
427 #define VGA_MSR_MEM_EN (1 << 1)
428 #define VGA_MSR_CGA_MODE (1 << 0)
430 #define VGA_SR_INDEX 0x3c4
432 #define VGA_SR_DATA 0x3c5
434 #define VGA_AR_INDEX 0x3c0
435 #define VGA_AR_VID_EN (1 << 5)
436 #define VGA_AR_DATA_WRITE 0x3c0
437 #define VGA_AR_DATA_READ 0x3c1
439 #define VGA_GR_INDEX 0x3ce
440 #define VGA_GR_DATA 0x3cf
442 #define VGA_GR_MEM_READ_MODE_SHIFT 3
443 #define VGA_GR_MEM_READ_MODE_PLANE 1
445 #define VGA_GR_MEM_MODE_MASK 0xc
446 #define VGA_GR_MEM_MODE_SHIFT 2
447 #define VGA_GR_MEM_A0000_AFFFF 0
448 #define VGA_GR_MEM_A0000_BFFFF 1
449 #define VGA_GR_MEM_B0000_B7FFF 2
450 #define VGA_GR_MEM_B0000_BFFFF 3
452 #define VGA_DACMASK 0x3c6
453 #define VGA_DACRX 0x3c7
454 #define VGA_DACWX 0x3c8
455 #define VGA_DACDATA 0x3c9
457 #define VGA_CR_INDEX_MDA 0x3b4
458 #define VGA_CR_DATA_MDA 0x3b5
459 #define VGA_CR_INDEX_CGA 0x3d4
460 #define VGA_CR_DATA_CGA 0x3d5
462 #define MI_PREDICATE_SRC0 _MMIO(0x2400)
463 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
464 #define MI_PREDICATE_SRC1 _MMIO(0x2408)
465 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
467 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
468 #define LOWER_SLICE_ENABLED (1 << 0)
469 #define LOWER_SLICE_DISABLED (0 << 0)
472 * Registers used only by the command parser
474 #define BCS_SWCTRL _MMIO(0x22200)
476 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
477 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
478 #define HS_INVOCATION_COUNT _MMIO(0x2300)
479 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
480 #define DS_INVOCATION_COUNT _MMIO(0x2308)
481 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
482 #define IA_VERTICES_COUNT _MMIO(0x2310)
483 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
484 #define IA_PRIMITIVES_COUNT _MMIO(0x2318)
485 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
486 #define VS_INVOCATION_COUNT _MMIO(0x2320)
487 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
488 #define GS_INVOCATION_COUNT _MMIO(0x2328)
489 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
490 #define GS_PRIMITIVES_COUNT _MMIO(0x2330)
491 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
492 #define CL_INVOCATION_COUNT _MMIO(0x2338)
493 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
494 #define CL_PRIMITIVES_COUNT _MMIO(0x2340)
495 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
496 #define PS_INVOCATION_COUNT _MMIO(0x2348)
497 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
498 #define PS_DEPTH_COUNT _MMIO(0x2350)
499 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
501 /* There are the 4 64-bit counter registers, one for each stream output */
502 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
503 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
505 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
506 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
508 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
509 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
510 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
511 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
512 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
513 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
515 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
516 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
517 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
519 /* There are the 16 64-bit CS General Purpose Registers */
520 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
521 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
523 #define GEN7_OACONTROL _MMIO(0x2360)
524 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
525 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
526 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
527 #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
528 #define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
529 #define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
530 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
531 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
532 #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
533 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
534 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
535 #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
536 #define GEN7_OACONTROL_FORMAT_SHIFT 2
537 #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
538 #define GEN7_OACONTROL_ENABLE (1 << 0)
540 #define GEN8_OACTXID _MMIO(0x2364)
542 #define GEN8_OA_DEBUG _MMIO(0x2B04)
543 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
544 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
545 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
546 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
548 #define GEN8_OACONTROL _MMIO(0x2B00)
549 #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
550 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
551 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
552 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
553 #define GEN8_OA_REPORT_FORMAT_SHIFT 2
554 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
555 #define GEN8_OA_COUNTER_ENABLE (1 << 0)
557 #define GEN8_OACTXCONTROL _MMIO(0x2360)
558 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F
559 #define GEN8_OA_TIMER_PERIOD_SHIFT 2
560 #define GEN8_OA_TIMER_ENABLE (1 << 1)
561 #define GEN8_OA_COUNTER_RESUME (1 << 0)
563 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
564 #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
565 #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
566 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
567 #define GEN7_OABUFFER_RESUME (1 << 0)
569 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
570 #define GEN8_OABUFFER _MMIO(0x2b14)
571 #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
573 #define GEN7_OASTATUS1 _MMIO(0x2364)
574 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
575 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
576 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
577 #define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
579 #define GEN7_OASTATUS2 _MMIO(0x2368)
580 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
581 #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
583 #define GEN8_OASTATUS _MMIO(0x2b08)
584 #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
585 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
586 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
587 #define GEN8_OASTATUS_REPORT_LOST (1 << 0)
589 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
590 #define GEN8_OAHEADPTR_MASK 0xffffffc0
591 #define GEN8_OATAILPTR _MMIO(0x2B10)
592 #define GEN8_OATAILPTR_MASK 0xffffffc0
594 #define OABUFFER_SIZE_128K (0 << 3)
595 #define OABUFFER_SIZE_256K (1 << 3)
596 #define OABUFFER_SIZE_512K (2 << 3)
597 #define OABUFFER_SIZE_1M (3 << 3)
598 #define OABUFFER_SIZE_2M (4 << 3)
599 #define OABUFFER_SIZE_4M (5 << 3)
600 #define OABUFFER_SIZE_8M (6 << 3)
601 #define OABUFFER_SIZE_16M (7 << 3)
604 * Flexible, Aggregate EU Counter Registers.
605 * Note: these aren't contiguous
607 #define EU_PERF_CNTL0 _MMIO(0xe458)
608 #define EU_PERF_CNTL1 _MMIO(0xe558)
609 #define EU_PERF_CNTL2 _MMIO(0xe658)
610 #define EU_PERF_CNTL3 _MMIO(0xe758)
611 #define EU_PERF_CNTL4 _MMIO(0xe45c)
612 #define EU_PERF_CNTL5 _MMIO(0xe55c)
613 #define EU_PERF_CNTL6 _MMIO(0xe65c)
619 #define OASTARTTRIG1 _MMIO(0x2710)
620 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
621 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff
623 #define OASTARTTRIG2 _MMIO(0x2714)
624 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
625 #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
626 #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
627 #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
628 #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
629 #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
630 #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
631 #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
632 #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
633 #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
634 #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
635 #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
636 #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
637 #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
638 #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
639 #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
640 #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
641 #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
642 #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
643 #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
644 #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
645 #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
646 #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
647 #define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
648 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
649 #define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
650 #define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
651 #define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
652 #define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
654 #define OASTARTTRIG3 _MMIO(0x2718)
655 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf
656 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
657 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
658 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
659 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
660 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
661 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
662 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
663 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
665 #define OASTARTTRIG4 _MMIO(0x271c)
666 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf
667 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
668 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
669 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
670 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
671 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
672 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
673 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
674 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
676 #define OASTARTTRIG5 _MMIO(0x2720)
677 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
678 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff
680 #define OASTARTTRIG6 _MMIO(0x2724)
681 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
682 #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
683 #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
684 #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
685 #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
686 #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
687 #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
688 #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
689 #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
690 #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
691 #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
692 #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
693 #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
694 #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
695 #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
696 #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
697 #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
698 #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
699 #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
700 #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
701 #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
702 #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
703 #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
704 #define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
705 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
706 #define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
707 #define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
708 #define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
709 #define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
711 #define OASTARTTRIG7 _MMIO(0x2728)
712 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf
713 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
714 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
715 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
716 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
717 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
718 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
719 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
720 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
722 #define OASTARTTRIG8 _MMIO(0x272c)
723 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf
724 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
725 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
726 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
727 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
728 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
729 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
730 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
731 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
733 #define OAREPORTTRIG1 _MMIO(0x2740)
734 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
735 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
737 #define OAREPORTTRIG2 _MMIO(0x2744)
738 #define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
739 #define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
740 #define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
741 #define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
742 #define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
743 #define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
744 #define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
745 #define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
746 #define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
747 #define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
748 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
749 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
750 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
751 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
752 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
753 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
754 #define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
755 #define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
756 #define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
757 #define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
758 #define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
759 #define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
760 #define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
761 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
762 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
764 #define OAREPORTTRIG3 _MMIO(0x2748)
765 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
766 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
767 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
768 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
769 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
770 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
771 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
772 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
773 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
775 #define OAREPORTTRIG4 _MMIO(0x274c)
776 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
777 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
778 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
779 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
780 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
781 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
782 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
783 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
784 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
786 #define OAREPORTTRIG5 _MMIO(0x2750)
787 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
788 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
790 #define OAREPORTTRIG6 _MMIO(0x2754)
791 #define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
792 #define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
793 #define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
794 #define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
795 #define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
796 #define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
797 #define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
798 #define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
799 #define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
800 #define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
801 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
802 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
803 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
804 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
805 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
806 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
807 #define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
808 #define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
809 #define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
810 #define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
811 #define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
812 #define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
813 #define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
814 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
815 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
817 #define OAREPORTTRIG7 _MMIO(0x2758)
818 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
819 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
820 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
821 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
822 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
823 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
824 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
825 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
826 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
828 #define OAREPORTTRIG8 _MMIO(0x275c)
829 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
830 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
831 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
832 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
833 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
834 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
835 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
836 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
837 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
840 #define OACEC_COMPARE_LESS_OR_EQUAL 6
841 #define OACEC_COMPARE_NOT_EQUAL 5
842 #define OACEC_COMPARE_LESS_THAN 4
843 #define OACEC_COMPARE_GREATER_OR_EQUAL 3
844 #define OACEC_COMPARE_EQUAL 2
845 #define OACEC_COMPARE_GREATER_THAN 1
846 #define OACEC_COMPARE_ANY_EQUAL 0
848 #define OACEC_COMPARE_VALUE_MASK 0xffff
849 #define OACEC_COMPARE_VALUE_SHIFT 3
851 #define OACEC_SELECT_NOA (0 << 19)
852 #define OACEC_SELECT_PREV (1 << 19)
853 #define OACEC_SELECT_BOOLEAN (2 << 19)
856 #define OACEC_MASK_MASK 0xffff
857 #define OACEC_CONSIDERATIONS_MASK 0xffff
858 #define OACEC_CONSIDERATIONS_SHIFT 16
860 #define OACEC0_0 _MMIO(0x2770)
861 #define OACEC0_1 _MMIO(0x2774)
862 #define OACEC1_0 _MMIO(0x2778)
863 #define OACEC1_1 _MMIO(0x277c)
864 #define OACEC2_0 _MMIO(0x2780)
865 #define OACEC2_1 _MMIO(0x2784)
866 #define OACEC3_0 _MMIO(0x2788)
867 #define OACEC3_1 _MMIO(0x278c)
868 #define OACEC4_0 _MMIO(0x2790)
869 #define OACEC4_1 _MMIO(0x2794)
870 #define OACEC5_0 _MMIO(0x2798)
871 #define OACEC5_1 _MMIO(0x279c)
872 #define OACEC6_0 _MMIO(0x27a0)
873 #define OACEC6_1 _MMIO(0x27a4)
874 #define OACEC7_0 _MMIO(0x27a8)
875 #define OACEC7_1 _MMIO(0x27ac)
877 /* OA perf counters */
878 #define OA_PERFCNT1_LO _MMIO(0x91B8)
879 #define OA_PERFCNT1_HI _MMIO(0x91BC)
880 #define OA_PERFCNT2_LO _MMIO(0x91C0)
881 #define OA_PERFCNT2_HI _MMIO(0x91C4)
882 #define OA_PERFCNT3_LO _MMIO(0x91C8)
883 #define OA_PERFCNT3_HI _MMIO(0x91CC)
884 #define OA_PERFCNT4_LO _MMIO(0x91D8)
885 #define OA_PERFCNT4_HI _MMIO(0x91DC)
887 #define OA_PERFMATRIX_LO _MMIO(0x91C8)
888 #define OA_PERFMATRIX_HI _MMIO(0x91CC)
890 /* RPM unit config (Gen8+) */
891 #define RPM_CONFIG0 _MMIO(0x0D00)
892 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
893 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
894 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
895 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
896 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
897 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
898 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
899 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
900 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
901 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
902 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
903 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
905 #define RPM_CONFIG1 _MMIO(0x0D04)
906 #define GEN10_GT_NOA_ENABLE (1 << 9)
908 /* GPM unit config (Gen9+) */
909 #define CTC_MODE _MMIO(0xA26C)
910 #define CTC_SOURCE_PARAMETER_MASK 1
911 #define CTC_SOURCE_CRYSTAL_CLOCK 0
912 #define CTC_SOURCE_DIVIDE_LOGIC 1
913 #define CTC_SHIFT_PARAMETER_SHIFT 1
914 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
916 /* RCP unit config (Gen8+) */
917 #define RCP_CONFIG _MMIO(0x0D08)
920 #define HSW_MBVID2_NOA0 _MMIO(0x9E80)
921 #define HSW_MBVID2_NOA1 _MMIO(0x9E84)
922 #define HSW_MBVID2_NOA2 _MMIO(0x9E88)
923 #define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
924 #define HSW_MBVID2_NOA4 _MMIO(0x9E90)
925 #define HSW_MBVID2_NOA5 _MMIO(0x9E94)
926 #define HSW_MBVID2_NOA6 _MMIO(0x9E98)
927 #define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
928 #define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
929 #define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
931 #define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
934 #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
936 #define MICRO_BP0_0 _MMIO(0x9800)
937 #define MICRO_BP0_2 _MMIO(0x9804)
938 #define MICRO_BP0_1 _MMIO(0x9808)
940 #define MICRO_BP1_0 _MMIO(0x980C)
941 #define MICRO_BP1_2 _MMIO(0x9810)
942 #define MICRO_BP1_1 _MMIO(0x9814)
944 #define MICRO_BP2_0 _MMIO(0x9818)
945 #define MICRO_BP2_2 _MMIO(0x981C)
946 #define MICRO_BP2_1 _MMIO(0x9820)
948 #define MICRO_BP3_0 _MMIO(0x9824)
949 #define MICRO_BP3_2 _MMIO(0x9828)
950 #define MICRO_BP3_1 _MMIO(0x982C)
952 #define MICRO_BP_TRIGGER _MMIO(0x9830)
953 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
954 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
955 #define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
957 #define GDT_CHICKEN_BITS _MMIO(0x9840)
958 #define GT_NOA_ENABLE 0x00000080
960 #define NOA_DATA _MMIO(0x986C)
961 #define NOA_WRITE _MMIO(0x9888)
963 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
964 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
965 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
970 #define DEBUG_RESET_I830 _MMIO(0x6070)
971 #define DEBUG_RESET_FULL (1 << 7)
972 #define DEBUG_RESET_RENDER (1 << 8)
973 #define DEBUG_RESET_DISPLAY (1 << 9)
978 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
979 #define IOSF_DEVFN_SHIFT 24
980 #define IOSF_OPCODE_SHIFT 16
981 #define IOSF_PORT_SHIFT 8
982 #define IOSF_BYTE_ENABLES_SHIFT 4
983 #define IOSF_BAR_SHIFT 1
984 #define IOSF_SB_BUSY (1 << 0)
985 #define IOSF_PORT_BUNIT 0x03
986 #define IOSF_PORT_PUNIT 0x04
987 #define IOSF_PORT_NC 0x11
988 #define IOSF_PORT_DPIO 0x12
989 #define IOSF_PORT_GPIO_NC 0x13
990 #define IOSF_PORT_CCK 0x14
991 #define IOSF_PORT_DPIO_2 0x1a
992 #define IOSF_PORT_FLISDSI 0x1b
993 #define IOSF_PORT_GPIO_SC 0x48
994 #define IOSF_PORT_GPIO_SUS 0xa8
995 #define IOSF_PORT_CCU 0xa9
996 #define CHV_IOSF_PORT_GPIO_N 0x13
997 #define CHV_IOSF_PORT_GPIO_SE 0x48
998 #define CHV_IOSF_PORT_GPIO_E 0xa8
999 #define CHV_IOSF_PORT_GPIO_SW 0xb2
1000 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1001 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1003 /* See configdb bunit SB addr map */
1004 #define BUNIT_REG_BISOC 0x11
1006 #define PUNIT_REG_DSPFREQ 0x36
1007 #define DSPFREQSTAT_SHIFT_CHV 24
1008 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1009 #define DSPFREQGUAR_SHIFT_CHV 8
1010 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1011 #define DSPFREQSTAT_SHIFT 30
1012 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1013 #define DSPFREQGUAR_SHIFT 14
1014 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1015 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1016 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1017 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
1018 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1019 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1020 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1021 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1022 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1023 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1024 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1025 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1026 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1027 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1028 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1029 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1032 * i915_power_well_id:
1034 * IDs used to look up power wells. Power wells accessed directly bypassing
1035 * the power domains framework must be assigned a unique ID. The rest of power
1036 * wells must be assigned DISP_PW_ID_NONE.
1038 enum i915_power_well_id {
1042 BXT_DISP_PW_DPIO_CMN_A,
1043 VLV_DISP_PW_DPIO_CMN_BC,
1044 GLK_DISP_PW_DPIO_CMN_C,
1045 CHV_DISP_PW_DPIO_CMN_D,
1047 SKL_DISP_PW_MISC_IO,
1052 #define PUNIT_REG_PWRGT_CTRL 0x60
1053 #define PUNIT_REG_PWRGT_STATUS 0x61
1054 #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
1055 #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
1056 #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
1057 #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
1058 #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
1060 #define PUNIT_PWGT_IDX_RENDER 0
1061 #define PUNIT_PWGT_IDX_MEDIA 1
1062 #define PUNIT_PWGT_IDX_DISP2D 3
1063 #define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
1064 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
1065 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
1066 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
1067 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
1068 #define PUNIT_PWGT_IDX_DPIO_RX0 10
1069 #define PUNIT_PWGT_IDX_DPIO_RX1 11
1070 #define PUNIT_PWGT_IDX_DPIO_CMN_D 12
1072 #define PUNIT_REG_GPU_LFM 0xd3
1073 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
1074 #define PUNIT_REG_GPU_FREQ_STS 0xd8
1075 #define GPLLENABLE (1 << 4)
1076 #define GENFREQSTATUS (1 << 0)
1077 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1078 #define PUNIT_REG_CZ_TIMESTAMP 0xce
1080 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1081 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1083 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1084 #define FB_GFX_FREQ_FUSE_MASK 0xff
1085 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1086 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1087 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1089 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1090 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1092 #define PUNIT_REG_DDR_SETUP2 0x139
1093 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1094 #define FORCE_DDR_LOW_FREQ (1 << 1)
1095 #define FORCE_DDR_HIGH_FREQ (1 << 0)
1097 #define PUNIT_GPU_STATUS_REG 0xdb
1098 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1099 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1100 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1101 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1103 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1104 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1105 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1107 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1108 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1109 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1110 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1111 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1112 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1113 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1114 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1115 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1116 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1118 #define VLV_TURBO_SOC_OVERRIDE 0x04
1119 #define VLV_OVERRIDE_EN 1
1120 #define VLV_SOC_TDP_EN (1 << 1)
1121 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1122 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1124 /* vlv2 north clock has */
1125 #define CCK_FUSE_REG 0x8
1126 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
1127 #define CCK_REG_DSI_PLL_FUSE 0x44
1128 #define CCK_REG_DSI_PLL_CONTROL 0x48
1129 #define DSI_PLL_VCO_EN (1 << 31)
1130 #define DSI_PLL_LDO_GATE (1 << 30)
1131 #define DSI_PLL_P1_POST_DIV_SHIFT 17
1132 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1133 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1134 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1135 #define DSI_PLL_MUX_MASK (3 << 9)
1136 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1137 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1138 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1139 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1140 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1141 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1142 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1143 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1144 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1145 #define DSI_PLL_LOCK (1 << 0)
1146 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
1147 #define DSI_PLL_LFSR (1 << 31)
1148 #define DSI_PLL_FRACTION_EN (1 << 30)
1149 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
1150 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1151 #define DSI_PLL_USYNC_CNT_SHIFT 18
1152 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1153 #define DSI_PLL_N1_DIV_SHIFT 16
1154 #define DSI_PLL_N1_DIV_MASK (3 << 16)
1155 #define DSI_PLL_M1_DIV_SHIFT 0
1156 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1157 #define CCK_CZ_CLOCK_CONTROL 0x62
1158 #define CCK_GPLL_CLOCK_CONTROL 0x67
1159 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1160 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1161 #define CCK_TRUNK_FORCE_ON (1 << 17)
1162 #define CCK_TRUNK_FORCE_OFF (1 << 16)
1163 #define CCK_FREQUENCY_STATUS (0x1f << 8)
1164 #define CCK_FREQUENCY_STATUS_SHIFT 8
1165 #define CCK_FREQUENCY_VALUES (0x1f << 0)
1167 /* DPIO registers */
1168 #define DPIO_DEVFN 0
1170 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1171 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
1172 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
1173 #define DPIO_SFR_BYPASS (1 << 1)
1174 #define DPIO_CMNRST (1 << 0)
1176 #define DPIO_PHY(pipe) ((pipe) >> 1)
1177 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1180 * Per pipe/PLL DPIO regs
1182 #define _VLV_PLL_DW3_CH0 0x800c
1183 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
1184 #define DPIO_POST_DIV_DAC 0
1185 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1186 #define DPIO_POST_DIV_LVDS1 2
1187 #define DPIO_POST_DIV_LVDS2 3
1188 #define DPIO_K_SHIFT (24) /* 4 bits */
1189 #define DPIO_P1_SHIFT (21) /* 3 bits */
1190 #define DPIO_P2_SHIFT (16) /* 5 bits */
1191 #define DPIO_N_SHIFT (12) /* 4 bits */
1192 #define DPIO_ENABLE_CALIBRATION (1 << 11)
1193 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
1194 #define DPIO_M2DIV_MASK 0xff
1195 #define _VLV_PLL_DW3_CH1 0x802c
1196 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1198 #define _VLV_PLL_DW5_CH0 0x8014
1199 #define DPIO_REFSEL_OVERRIDE 27
1200 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
1201 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
1202 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
1203 #define DPIO_PLL_REFCLK_SEL_MASK 3
1204 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1205 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
1206 #define _VLV_PLL_DW5_CH1 0x8034
1207 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1209 #define _VLV_PLL_DW7_CH0 0x801c
1210 #define _VLV_PLL_DW7_CH1 0x803c
1211 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1213 #define _VLV_PLL_DW8_CH0 0x8040
1214 #define _VLV_PLL_DW8_CH1 0x8060
1215 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1217 #define VLV_PLL_DW9_BCAST 0xc044
1218 #define _VLV_PLL_DW9_CH0 0x8044
1219 #define _VLV_PLL_DW9_CH1 0x8064
1220 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1222 #define _VLV_PLL_DW10_CH0 0x8048
1223 #define _VLV_PLL_DW10_CH1 0x8068
1224 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1226 #define _VLV_PLL_DW11_CH0 0x804c
1227 #define _VLV_PLL_DW11_CH1 0x806c
1228 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1230 /* Spec for ref block start counts at DW10 */
1231 #define VLV_REF_DW13 0x80ac
1233 #define VLV_CMN_DW0 0x8100
1236 * Per DDI channel DPIO regs
1239 #define _VLV_PCS_DW0_CH0 0x8200
1240 #define _VLV_PCS_DW0_CH1 0x8400
1241 #define DPIO_PCS_TX_LANE2_RESET (1 << 16)
1242 #define DPIO_PCS_TX_LANE1_RESET (1 << 7)
1243 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
1244 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
1245 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1247 #define _VLV_PCS01_DW0_CH0 0x200
1248 #define _VLV_PCS23_DW0_CH0 0x400
1249 #define _VLV_PCS01_DW0_CH1 0x2600
1250 #define _VLV_PCS23_DW0_CH1 0x2800
1251 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1252 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1254 #define _VLV_PCS_DW1_CH0 0x8204
1255 #define _VLV_PCS_DW1_CH1 0x8404
1256 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
1257 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
1258 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1259 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1260 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
1261 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1263 #define _VLV_PCS01_DW1_CH0 0x204
1264 #define _VLV_PCS23_DW1_CH0 0x404
1265 #define _VLV_PCS01_DW1_CH1 0x2604
1266 #define _VLV_PCS23_DW1_CH1 0x2804
1267 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1268 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1270 #define _VLV_PCS_DW8_CH0 0x8220
1271 #define _VLV_PCS_DW8_CH1 0x8420
1272 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1273 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1274 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1276 #define _VLV_PCS01_DW8_CH0 0x0220
1277 #define _VLV_PCS23_DW8_CH0 0x0420
1278 #define _VLV_PCS01_DW8_CH1 0x2620
1279 #define _VLV_PCS23_DW8_CH1 0x2820
1280 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1281 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1283 #define _VLV_PCS_DW9_CH0 0x8224
1284 #define _VLV_PCS_DW9_CH1 0x8424
1285 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
1286 #define DPIO_PCS_TX2MARGIN_000 (0 << 13)
1287 #define DPIO_PCS_TX2MARGIN_101 (1 << 13)
1288 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
1289 #define DPIO_PCS_TX1MARGIN_000 (0 << 10)
1290 #define DPIO_PCS_TX1MARGIN_101 (1 << 10)
1291 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1293 #define _VLV_PCS01_DW9_CH0 0x224
1294 #define _VLV_PCS23_DW9_CH0 0x424
1295 #define _VLV_PCS01_DW9_CH1 0x2624
1296 #define _VLV_PCS23_DW9_CH1 0x2824
1297 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1298 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1300 #define _CHV_PCS_DW10_CH0 0x8228
1301 #define _CHV_PCS_DW10_CH1 0x8428
1302 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
1303 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
1304 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
1305 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
1306 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
1307 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
1308 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
1309 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
1310 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1312 #define _VLV_PCS01_DW10_CH0 0x0228
1313 #define _VLV_PCS23_DW10_CH0 0x0428
1314 #define _VLV_PCS01_DW10_CH1 0x2628
1315 #define _VLV_PCS23_DW10_CH1 0x2828
1316 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1317 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1319 #define _VLV_PCS_DW11_CH0 0x822c
1320 #define _VLV_PCS_DW11_CH1 0x842c
1321 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
1322 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
1323 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
1324 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
1325 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1327 #define _VLV_PCS01_DW11_CH0 0x022c
1328 #define _VLV_PCS23_DW11_CH0 0x042c
1329 #define _VLV_PCS01_DW11_CH1 0x262c
1330 #define _VLV_PCS23_DW11_CH1 0x282c
1331 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1332 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1334 #define _VLV_PCS01_DW12_CH0 0x0230
1335 #define _VLV_PCS23_DW12_CH0 0x0430
1336 #define _VLV_PCS01_DW12_CH1 0x2630
1337 #define _VLV_PCS23_DW12_CH1 0x2830
1338 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1339 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1341 #define _VLV_PCS_DW12_CH0 0x8230
1342 #define _VLV_PCS_DW12_CH1 0x8430
1343 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
1344 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
1345 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
1346 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
1347 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
1348 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1350 #define _VLV_PCS_DW14_CH0 0x8238
1351 #define _VLV_PCS_DW14_CH1 0x8438
1352 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1354 #define _VLV_PCS_DW23_CH0 0x825c
1355 #define _VLV_PCS_DW23_CH1 0x845c
1356 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1358 #define _VLV_TX_DW2_CH0 0x8288
1359 #define _VLV_TX_DW2_CH1 0x8488
1360 #define DPIO_SWING_MARGIN000_SHIFT 16
1361 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1362 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1363 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1365 #define _VLV_TX_DW3_CH0 0x828c
1366 #define _VLV_TX_DW3_CH1 0x848c
1367 /* The following bit for CHV phy */
1368 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
1369 #define DPIO_SWING_MARGIN101_SHIFT 16
1370 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1371 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1373 #define _VLV_TX_DW4_CH0 0x8290
1374 #define _VLV_TX_DW4_CH1 0x8490
1375 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
1376 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1377 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
1378 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1379 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1381 #define _VLV_TX3_DW4_CH0 0x690
1382 #define _VLV_TX3_DW4_CH1 0x2a90
1383 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1385 #define _VLV_TX_DW5_CH0 0x8294
1386 #define _VLV_TX_DW5_CH1 0x8494
1387 #define DPIO_TX_OCALINIT_EN (1 << 31)
1388 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1390 #define _VLV_TX_DW11_CH0 0x82ac
1391 #define _VLV_TX_DW11_CH1 0x84ac
1392 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1394 #define _VLV_TX_DW14_CH0 0x82b8
1395 #define _VLV_TX_DW14_CH1 0x84b8
1396 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1398 /* CHV dpPhy registers */
1399 #define _CHV_PLL_DW0_CH0 0x8000
1400 #define _CHV_PLL_DW0_CH1 0x8180
1401 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1403 #define _CHV_PLL_DW1_CH0 0x8004
1404 #define _CHV_PLL_DW1_CH1 0x8184
1405 #define DPIO_CHV_N_DIV_SHIFT 8
1406 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1407 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1409 #define _CHV_PLL_DW2_CH0 0x8008
1410 #define _CHV_PLL_DW2_CH1 0x8188
1411 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1413 #define _CHV_PLL_DW3_CH0 0x800c
1414 #define _CHV_PLL_DW3_CH1 0x818c
1415 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1416 #define DPIO_CHV_FIRST_MOD (0 << 8)
1417 #define DPIO_CHV_SECOND_MOD (1 << 8)
1418 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1419 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1420 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1422 #define _CHV_PLL_DW6_CH0 0x8018
1423 #define _CHV_PLL_DW6_CH1 0x8198
1424 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
1425 #define DPIO_CHV_INT_COEFF_SHIFT 8
1426 #define DPIO_CHV_PROP_COEFF_SHIFT 0
1427 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1429 #define _CHV_PLL_DW8_CH0 0x8020
1430 #define _CHV_PLL_DW8_CH1 0x81A0
1431 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1432 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1433 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1435 #define _CHV_PLL_DW9_CH0 0x8024
1436 #define _CHV_PLL_DW9_CH1 0x81A4
1437 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1438 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1439 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1440 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1442 #define _CHV_CMN_DW0_CH0 0x8100
1443 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1444 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1445 #define DPIO_ALLDL_POWERDOWN (1 << 1)
1446 #define DPIO_ANYDL_POWERDOWN (1 << 0)
1448 #define _CHV_CMN_DW5_CH0 0x8114
1449 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1450 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1451 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1452 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
1453 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1454 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1455 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
1456 #define CHV_BUFLEFTENA1_MASK (3 << 22)
1458 #define _CHV_CMN_DW13_CH0 0x8134
1459 #define _CHV_CMN_DW0_CH1 0x8080
1460 #define DPIO_CHV_S1_DIV_SHIFT 21
1461 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1462 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1463 #define DPIO_CHV_K_DIV_SHIFT 4
1464 #define DPIO_PLL_FREQLOCK (1 << 1)
1465 #define DPIO_PLL_LOCK (1 << 0)
1466 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1468 #define _CHV_CMN_DW14_CH0 0x8138
1469 #define _CHV_CMN_DW1_CH1 0x8084
1470 #define DPIO_AFC_RECAL (1 << 14)
1471 #define DPIO_DCLKP_EN (1 << 13)
1472 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1473 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1474 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1475 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1476 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1477 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1478 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1479 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1480 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1482 #define _CHV_CMN_DW19_CH0 0x814c
1483 #define _CHV_CMN_DW6_CH1 0x8098
1484 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1485 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1486 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1487 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1489 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1491 #define CHV_CMN_DW28 0x8170
1492 #define DPIO_CL1POWERDOWNEN (1 << 23)
1493 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1494 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1495 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1496 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1497 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1499 #define CHV_CMN_DW30 0x8178
1500 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1501 #define DPIO_LRC_BYPASS (1 << 3)
1503 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1504 (lane) * 0x200 + (offset))
1506 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1507 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1508 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1509 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1510 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1511 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1512 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1513 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1514 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1515 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1516 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1517 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1518 #define DPIO_FRC_LATENCY_SHFIT 8
1519 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1520 #define DPIO_UPAR_SHIFT 30
1522 /* BXT PHY registers */
1523 #define _BXT_PHY0_BASE 0x6C000
1524 #define _BXT_PHY1_BASE 0x162000
1525 #define _BXT_PHY2_BASE 0x163000
1526 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1530 #define _BXT_PHY(phy, reg) \
1531 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1533 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1534 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1535 (reg_ch1) - _BXT_PHY0_BASE))
1536 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1537 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1539 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1540 #define MIPIO_RST_CTRL (1 << 2)
1542 #define _BXT_PHY_CTL_DDI_A 0x64C00
1543 #define _BXT_PHY_CTL_DDI_B 0x64C10
1544 #define _BXT_PHY_CTL_DDI_C 0x64C20
1545 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1546 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1547 #define BXT_PHY_LANE_ENABLED (1 << 8)
1548 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1551 #define _PHY_CTL_FAMILY_EDP 0x64C80
1552 #define _PHY_CTL_FAMILY_DDI 0x64C90
1553 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
1554 #define COMMON_RESET_DIS (1 << 31)
1555 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1556 _PHY_CTL_FAMILY_EDP, \
1557 _PHY_CTL_FAMILY_DDI_C)
1559 /* BXT PHY PLL registers */
1560 #define _PORT_PLL_A 0x46074
1561 #define _PORT_PLL_B 0x46078
1562 #define _PORT_PLL_C 0x4607c
1563 #define PORT_PLL_ENABLE (1 << 31)
1564 #define PORT_PLL_LOCK (1 << 30)
1565 #define PORT_PLL_REF_SEL (1 << 27)
1566 #define PORT_PLL_POWER_ENABLE (1 << 26)
1567 #define PORT_PLL_POWER_STATE (1 << 25)
1568 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1570 #define _PORT_PLL_EBB_0_A 0x162034
1571 #define _PORT_PLL_EBB_0_B 0x6C034
1572 #define _PORT_PLL_EBB_0_C 0x6C340
1573 #define PORT_PLL_P1_SHIFT 13
1574 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1575 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1576 #define PORT_PLL_P2_SHIFT 8
1577 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1578 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1579 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1580 _PORT_PLL_EBB_0_B, \
1583 #define _PORT_PLL_EBB_4_A 0x162038
1584 #define _PORT_PLL_EBB_4_B 0x6C038
1585 #define _PORT_PLL_EBB_4_C 0x6C344
1586 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1587 #define PORT_PLL_RECALIBRATE (1 << 14)
1588 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1589 _PORT_PLL_EBB_4_B, \
1592 #define _PORT_PLL_0_A 0x162100
1593 #define _PORT_PLL_0_B 0x6C100
1594 #define _PORT_PLL_0_C 0x6C380
1596 #define PORT_PLL_M2_MASK 0xFF
1598 #define PORT_PLL_N_SHIFT 8
1599 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1600 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1602 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1604 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1606 #define PORT_PLL_PROP_COEFF_MASK 0xF
1607 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1608 #define PORT_PLL_INT_COEFF(x) ((x) << 8)
1609 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1610 #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1612 #define PORT_PLL_TARGET_CNT_MASK 0x3FF
1614 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1615 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1617 #define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27)
1618 #define PORT_PLL_DCO_AMP_DEFAULT 15
1619 #define PORT_PLL_DCO_AMP_MASK 0x3c00
1620 #define PORT_PLL_DCO_AMP(x) ((x) << 10)
1621 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1624 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1627 /* BXT PHY common lane registers */
1628 #define _PORT_CL1CM_DW0_A 0x162000
1629 #define _PORT_CL1CM_DW0_BC 0x6C000
1630 #define PHY_POWER_GOOD (1 << 16)
1631 #define PHY_RESERVED (1 << 7)
1632 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1634 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1635 #define CL_POWER_DOWN_ENABLE (1 << 4)
1636 #define SUS_CLOCK_CONFIG (3 << 0)
1638 #define _ICL_PORT_CL_DW5_A 0x162014
1639 #define _ICL_PORT_CL_DW5_B 0x6C014
1640 #define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
1643 #define _CNL_PORT_CL_DW10_A 0x162028
1644 #define _ICL_PORT_CL_DW10_B 0x6c028
1645 #define ICL_PORT_CL_DW10(port) _MMIO_PORT(port, \
1646 _CNL_PORT_CL_DW10_A, \
1647 _ICL_PORT_CL_DW10_B)
1648 #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1649 #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1650 #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1651 #define PWR_UP_ALL_LANES (0x0 << 4)
1652 #define PWR_DOWN_LN_3_2_1 (0xe << 4)
1653 #define PWR_DOWN_LN_3_2 (0xc << 4)
1654 #define PWR_DOWN_LN_3 (0x8 << 4)
1655 #define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1656 #define PWR_DOWN_LN_1_0 (0x3 << 4)
1657 #define PWR_DOWN_LN_1 (0x2 << 4)
1658 #define PWR_DOWN_LN_3_1 (0xa << 4)
1659 #define PWR_DOWN_LN_3_1_0 (0xb << 4)
1660 #define PWR_DOWN_LN_MASK (0xf << 4)
1661 #define PWR_DOWN_LN_SHIFT 4
1663 #define _PORT_CL1CM_DW9_A 0x162024
1664 #define _PORT_CL1CM_DW9_BC 0x6C024
1665 #define IREF0RC_OFFSET_SHIFT 8
1666 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1667 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1669 #define _PORT_CL1CM_DW10_A 0x162028
1670 #define _PORT_CL1CM_DW10_BC 0x6C028
1671 #define IREF1RC_OFFSET_SHIFT 8
1672 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1673 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1675 #define _ICL_PORT_CL_DW12_A 0x162030
1676 #define _ICL_PORT_CL_DW12_B 0x6C030
1677 #define ICL_LANE_ENABLE_AUX (1 << 0)
1678 #define ICL_PORT_CL_DW12(port) _MMIO_PORT((port), \
1679 _ICL_PORT_CL_DW12_A, \
1680 _ICL_PORT_CL_DW12_B)
1682 #define _PORT_CL1CM_DW28_A 0x162070
1683 #define _PORT_CL1CM_DW28_BC 0x6C070
1684 #define OCL1_POWER_DOWN_EN (1 << 23)
1685 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1686 #define SUS_CLK_CONFIG 0x3
1687 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1689 #define _PORT_CL1CM_DW30_A 0x162078
1690 #define _PORT_CL1CM_DW30_BC 0x6C078
1691 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1692 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1694 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1695 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1696 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1697 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1698 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1699 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1700 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1701 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1702 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1703 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1704 #define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \
1705 _CNL_PORT_PCS_DW1_GRP_AE, \
1706 _CNL_PORT_PCS_DW1_GRP_B, \
1707 _CNL_PORT_PCS_DW1_GRP_C, \
1708 _CNL_PORT_PCS_DW1_GRP_D, \
1709 _CNL_PORT_PCS_DW1_GRP_AE, \
1710 _CNL_PORT_PCS_DW1_GRP_F))
1712 #define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
1713 _CNL_PORT_PCS_DW1_LN0_AE, \
1714 _CNL_PORT_PCS_DW1_LN0_B, \
1715 _CNL_PORT_PCS_DW1_LN0_C, \
1716 _CNL_PORT_PCS_DW1_LN0_D, \
1717 _CNL_PORT_PCS_DW1_LN0_AE, \
1718 _CNL_PORT_PCS_DW1_LN0_F))
1720 #define _ICL_PORT_PCS_DW1_GRP_A 0x162604
1721 #define _ICL_PORT_PCS_DW1_GRP_B 0x6C604
1722 #define _ICL_PORT_PCS_DW1_LN0_A 0x162804
1723 #define _ICL_PORT_PCS_DW1_LN0_B 0x6C804
1724 #define _ICL_PORT_PCS_DW1_AUX_A 0x162304
1725 #define _ICL_PORT_PCS_DW1_AUX_B 0x6c304
1726 #define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\
1727 _ICL_PORT_PCS_DW1_GRP_A, \
1728 _ICL_PORT_PCS_DW1_GRP_B)
1729 #define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \
1730 _ICL_PORT_PCS_DW1_LN0_A, \
1731 _ICL_PORT_PCS_DW1_LN0_B)
1732 #define ICL_PORT_PCS_DW1_AUX(port) _MMIO_PORT(port, \
1733 _ICL_PORT_PCS_DW1_AUX_A, \
1734 _ICL_PORT_PCS_DW1_AUX_B)
1735 #define COMMON_KEEPER_EN (1 << 26)
1737 /* CNL Port TX registers */
1738 #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
1739 #define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
1740 #define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
1741 #define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
1742 #define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
1743 #define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
1744 #define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
1745 #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
1746 #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
1747 #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
1748 #define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \
1749 _CNL_PORT_TX_AE_GRP_OFFSET, \
1750 _CNL_PORT_TX_B_GRP_OFFSET, \
1751 _CNL_PORT_TX_B_GRP_OFFSET, \
1752 _CNL_PORT_TX_D_GRP_OFFSET, \
1753 _CNL_PORT_TX_AE_GRP_OFFSET, \
1754 _CNL_PORT_TX_F_GRP_OFFSET) + \
1756 #define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \
1757 _CNL_PORT_TX_AE_LN0_OFFSET, \
1758 _CNL_PORT_TX_B_LN0_OFFSET, \
1759 _CNL_PORT_TX_B_LN0_OFFSET, \
1760 _CNL_PORT_TX_D_LN0_OFFSET, \
1761 _CNL_PORT_TX_AE_LN0_OFFSET, \
1762 _CNL_PORT_TX_F_LN0_OFFSET) + \
1765 #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
1766 #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
1767 #define _ICL_PORT_TX_DW2_GRP_A 0x162688
1768 #define _ICL_PORT_TX_DW2_GRP_B 0x6C688
1769 #define _ICL_PORT_TX_DW2_LN0_A 0x162888
1770 #define _ICL_PORT_TX_DW2_LN0_B 0x6C888
1771 #define _ICL_PORT_TX_DW2_AUX_A 0x162388
1772 #define _ICL_PORT_TX_DW2_AUX_B 0x6c388
1773 #define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \
1774 _ICL_PORT_TX_DW2_GRP_A, \
1775 _ICL_PORT_TX_DW2_GRP_B)
1776 #define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \
1777 _ICL_PORT_TX_DW2_LN0_A, \
1778 _ICL_PORT_TX_DW2_LN0_B)
1779 #define ICL_PORT_TX_DW2_AUX(port) _MMIO_PORT(port, \
1780 _ICL_PORT_TX_DW2_AUX_A, \
1781 _ICL_PORT_TX_DW2_AUX_B)
1782 #define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
1783 #define SWING_SEL_UPPER_MASK (1 << 15)
1784 #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
1785 #define SWING_SEL_LOWER_MASK (0x7 << 11)
1786 #define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
1787 #define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
1788 #define RCOMP_SCALAR(x) ((x) << 0)
1789 #define RCOMP_SCALAR_MASK (0xFF << 0)
1791 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450
1792 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
1793 #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
1794 #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
1795 #define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
1796 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
1797 _CNL_PORT_TX_DW4_LN0_AE)))
1798 #define _ICL_PORT_TX_DW4_GRP_A 0x162690
1799 #define _ICL_PORT_TX_DW4_GRP_B 0x6C690
1800 #define _ICL_PORT_TX_DW4_LN0_A 0x162890
1801 #define _ICL_PORT_TX_DW4_LN1_A 0x162990
1802 #define _ICL_PORT_TX_DW4_LN0_B 0x6C890
1803 #define _ICL_PORT_TX_DW4_AUX_A 0x162390
1804 #define _ICL_PORT_TX_DW4_AUX_B 0x6c390
1805 #define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \
1806 _ICL_PORT_TX_DW4_GRP_A, \
1807 _ICL_PORT_TX_DW4_GRP_B)
1808 #define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \
1809 _ICL_PORT_TX_DW4_LN0_A, \
1810 _ICL_PORT_TX_DW4_LN0_B) + \
1811 ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
1812 _ICL_PORT_TX_DW4_LN0_A)))
1813 #define ICL_PORT_TX_DW4_AUX(port) _MMIO_PORT(port, \
1814 _ICL_PORT_TX_DW4_AUX_A, \
1815 _ICL_PORT_TX_DW4_AUX_B)
1816 #define LOADGEN_SELECT (1 << 31)
1817 #define POST_CURSOR_1(x) ((x) << 12)
1818 #define POST_CURSOR_1_MASK (0x3F << 12)
1819 #define POST_CURSOR_2(x) ((x) << 6)
1820 #define POST_CURSOR_2_MASK (0x3F << 6)
1821 #define CURSOR_COEFF(x) ((x) << 0)
1822 #define CURSOR_COEFF_MASK (0x3F << 0)
1824 #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
1825 #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
1826 #define _ICL_PORT_TX_DW5_GRP_A 0x162694
1827 #define _ICL_PORT_TX_DW5_GRP_B 0x6C694
1828 #define _ICL_PORT_TX_DW5_LN0_A 0x162894
1829 #define _ICL_PORT_TX_DW5_LN0_B 0x6C894
1830 #define _ICL_PORT_TX_DW5_AUX_A 0x162394
1831 #define _ICL_PORT_TX_DW5_AUX_B 0x6c394
1832 #define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \
1833 _ICL_PORT_TX_DW5_GRP_A, \
1834 _ICL_PORT_TX_DW5_GRP_B)
1835 #define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \
1836 _ICL_PORT_TX_DW5_LN0_A, \
1837 _ICL_PORT_TX_DW5_LN0_B)
1838 #define ICL_PORT_TX_DW5_AUX(port) _MMIO_PORT(port, \
1839 _ICL_PORT_TX_DW5_AUX_A, \
1840 _ICL_PORT_TX_DW5_AUX_B)
1841 #define TX_TRAINING_EN (1 << 31)
1842 #define TAP2_DISABLE (1 << 30)
1843 #define TAP3_DISABLE (1 << 29)
1844 #define SCALING_MODE_SEL(x) ((x) << 18)
1845 #define SCALING_MODE_SEL_MASK (0x7 << 18)
1846 #define RTERM_SELECT(x) ((x) << 3)
1847 #define RTERM_SELECT_MASK (0x7 << 3)
1849 #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
1850 #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
1851 #define N_SCALAR(x) ((x) << 24)
1852 #define N_SCALAR_MASK (0x7F << 24)
1854 #define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
1855 _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
1857 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
1858 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
1859 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
1860 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
1861 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
1862 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
1863 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
1864 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
1865 #define MG_TX1_LINK_PARAMS(port, ln) \
1866 MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
1867 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
1868 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
1870 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
1871 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
1872 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
1873 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
1874 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
1875 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
1876 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
1877 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
1878 #define MG_TX2_LINK_PARAMS(port, ln) \
1879 MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
1880 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
1881 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
1882 #define CRI_USE_FS32 (1 << 5)
1884 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
1885 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
1886 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
1887 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
1888 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
1889 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
1890 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
1891 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
1892 #define MG_TX1_PISO_READLOAD(port, ln) \
1893 MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
1894 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
1895 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
1897 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
1898 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
1899 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
1900 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
1901 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
1902 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
1903 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
1904 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
1905 #define MG_TX2_PISO_READLOAD(port, ln) \
1906 MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
1907 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
1908 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
1909 #define CRI_CALCINIT (1 << 1)
1911 #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
1912 #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
1913 #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
1914 #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
1915 #define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
1916 #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
1917 #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
1918 #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
1919 #define MG_TX1_SWINGCTRL(port, ln) \
1920 MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
1921 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
1922 MG_TX_SWINGCTRL_TX1LN1_PORT1)
1924 #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
1925 #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
1926 #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
1927 #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
1928 #define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
1929 #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
1930 #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
1931 #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
1932 #define MG_TX2_SWINGCTRL(port, ln) \
1933 MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
1934 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
1935 MG_TX_SWINGCTRL_TX2LN1_PORT1)
1936 #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
1937 #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
1939 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
1940 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
1941 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
1942 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
1943 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
1944 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
1945 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
1946 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
1947 #define MG_TX1_DRVCTRL(port, ln) \
1948 MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
1949 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
1950 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
1952 #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
1953 #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
1954 #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
1955 #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
1956 #define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
1957 #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
1958 #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
1959 #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
1960 #define MG_TX2_DRVCTRL(port, ln) \
1961 MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
1962 MG_TX_DRVCTRL_TX2LN0_PORT2, \
1963 MG_TX_DRVCTRL_TX2LN1_PORT1)
1964 #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
1965 #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
1966 #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
1967 #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
1968 #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
1969 #define CRI_LOADGEN_SEL(x) ((x) << 12)
1970 #define CRI_LOADGEN_SEL_MASK (0x3 << 12)
1972 #define MG_CLKHUB_LN0_PORT1 0x16839C
1973 #define MG_CLKHUB_LN1_PORT1 0x16879C
1974 #define MG_CLKHUB_LN0_PORT2 0x16939C
1975 #define MG_CLKHUB_LN1_PORT2 0x16979C
1976 #define MG_CLKHUB_LN0_PORT3 0x16A39C
1977 #define MG_CLKHUB_LN1_PORT3 0x16A79C
1978 #define MG_CLKHUB_LN0_PORT4 0x16B39C
1979 #define MG_CLKHUB_LN1_PORT4 0x16B79C
1980 #define MG_CLKHUB(port, ln) \
1981 MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
1982 MG_CLKHUB_LN0_PORT2, \
1983 MG_CLKHUB_LN1_PORT1)
1984 #define CFG_LOW_RATE_LKREN_EN (1 << 11)
1986 #define MG_TX_DCC_TX1LN0_PORT1 0x168110
1987 #define MG_TX_DCC_TX1LN1_PORT1 0x168510
1988 #define MG_TX_DCC_TX1LN0_PORT2 0x169110
1989 #define MG_TX_DCC_TX1LN1_PORT2 0x169510
1990 #define MG_TX_DCC_TX1LN0_PORT3 0x16A110
1991 #define MG_TX_DCC_TX1LN1_PORT3 0x16A510
1992 #define MG_TX_DCC_TX1LN0_PORT4 0x16B110
1993 #define MG_TX_DCC_TX1LN1_PORT4 0x16B510
1994 #define MG_TX1_DCC(port, ln) \
1995 MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
1996 MG_TX_DCC_TX1LN0_PORT2, \
1997 MG_TX_DCC_TX1LN1_PORT1)
1998 #define MG_TX_DCC_TX2LN0_PORT1 0x168090
1999 #define MG_TX_DCC_TX2LN1_PORT1 0x168490
2000 #define MG_TX_DCC_TX2LN0_PORT2 0x169090
2001 #define MG_TX_DCC_TX2LN1_PORT2 0x169490
2002 #define MG_TX_DCC_TX2LN0_PORT3 0x16A090
2003 #define MG_TX_DCC_TX2LN1_PORT3 0x16A490
2004 #define MG_TX_DCC_TX2LN0_PORT4 0x16B090
2005 #define MG_TX_DCC_TX2LN1_PORT4 0x16B490
2006 #define MG_TX2_DCC(port, ln) \
2007 MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
2008 MG_TX_DCC_TX2LN0_PORT2, \
2009 MG_TX_DCC_TX2LN1_PORT1)
2010 #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
2011 #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
2012 #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
2014 #define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
2015 #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
2016 #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
2017 #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
2018 #define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
2019 #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
2020 #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
2021 #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
2022 #define MG_DP_MODE(port, ln) \
2023 MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \
2024 MG_DP_MODE_LN0_ACU_PORT2, \
2025 MG_DP_MODE_LN1_ACU_PORT1)
2026 #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
2027 #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2028 #define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
2029 #define MG_DP_MODE_CFG_TRPWR_GATING (1 << 4)
2030 #define MG_DP_MODE_CFG_CLNPWR_GATING (1 << 3)
2031 #define MG_DP_MODE_CFG_DIGPWR_GATING (1 << 2)
2032 #define MG_DP_MODE_CFG_GAONPWR_GATING (1 << 1)
2034 #define MG_MISC_SUS0_PORT1 0x168814
2035 #define MG_MISC_SUS0_PORT2 0x169814
2036 #define MG_MISC_SUS0_PORT3 0x16A814
2037 #define MG_MISC_SUS0_PORT4 0x16B814
2038 #define MG_MISC_SUS0(tc_port) \
2039 _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))
2040 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK (3 << 14)
2041 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14)
2042 #define MG_MISC_SUS0_CFG_TR2PWR_GATING (1 << 12)
2043 #define MG_MISC_SUS0_CFG_CL2PWR_GATING (1 << 11)
2044 #define MG_MISC_SUS0_CFG_GAONPWR_GATING (1 << 10)
2045 #define MG_MISC_SUS0_CFG_TRPWR_GATING (1 << 7)
2046 #define MG_MISC_SUS0_CFG_CL1PWR_GATING (1 << 6)
2047 #define MG_MISC_SUS0_CFG_DGPWR_GATING (1 << 5)
2049 /* The spec defines this only for BXT PHY0, but lets assume that this
2050 * would exist for PHY1 too if it had a second channel.
2052 #define _PORT_CL2CM_DW6_A 0x162358
2053 #define _PORT_CL2CM_DW6_BC 0x6C358
2054 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2055 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2057 #define CNL_PORT_COMP_DW0 _MMIO(0x162100)
2058 #define COMP_INIT (1 << 31)
2059 #define CNL_PORT_COMP_DW1 _MMIO(0x162104)
2060 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
2061 #define PROCESS_INFO_DOT_0 (0 << 26)
2062 #define PROCESS_INFO_DOT_1 (1 << 26)
2063 #define PROCESS_INFO_DOT_4 (2 << 26)
2064 #define PROCESS_INFO_MASK (7 << 26)
2065 #define PROCESS_INFO_SHIFT 26
2066 #define VOLTAGE_INFO_0_85V (0 << 24)
2067 #define VOLTAGE_INFO_0_95V (1 << 24)
2068 #define VOLTAGE_INFO_1_05V (2 << 24)
2069 #define VOLTAGE_INFO_MASK (3 << 24)
2070 #define VOLTAGE_INFO_SHIFT 24
2071 #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
2072 #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
2074 #define _ICL_PORT_COMP_DW0_A 0x162100
2075 #define _ICL_PORT_COMP_DW0_B 0x6C100
2076 #define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
2077 _ICL_PORT_COMP_DW0_B)
2078 #define _ICL_PORT_COMP_DW1_A 0x162104
2079 #define _ICL_PORT_COMP_DW1_B 0x6C104
2080 #define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
2081 _ICL_PORT_COMP_DW1_B)
2082 #define _ICL_PORT_COMP_DW3_A 0x16210C
2083 #define _ICL_PORT_COMP_DW3_B 0x6C10C
2084 #define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
2085 _ICL_PORT_COMP_DW3_B)
2086 #define _ICL_PORT_COMP_DW9_A 0x162124
2087 #define _ICL_PORT_COMP_DW9_B 0x6C124
2088 #define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
2089 _ICL_PORT_COMP_DW9_B)
2090 #define _ICL_PORT_COMP_DW10_A 0x162128
2091 #define _ICL_PORT_COMP_DW10_B 0x6C128
2092 #define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
2093 _ICL_PORT_COMP_DW10_A, \
2094 _ICL_PORT_COMP_DW10_B)
2096 /* ICL PHY DFLEX registers */
2097 #define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
2098 #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
2099 #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
2101 /* BXT PHY Ref registers */
2102 #define _PORT_REF_DW3_A 0x16218C
2103 #define _PORT_REF_DW3_BC 0x6C18C
2104 #define GRC_DONE (1 << 22)
2105 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
2107 #define _PORT_REF_DW6_A 0x162198
2108 #define _PORT_REF_DW6_BC 0x6C198
2109 #define GRC_CODE_SHIFT 24
2110 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
2111 #define GRC_CODE_FAST_SHIFT 16
2112 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
2113 #define GRC_CODE_SLOW_SHIFT 8
2114 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2115 #define GRC_CODE_NOM_MASK 0xFF
2116 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
2118 #define _PORT_REF_DW8_A 0x1621A0
2119 #define _PORT_REF_DW8_BC 0x6C1A0
2120 #define GRC_DIS (1 << 15)
2121 #define GRC_RDY_OVRD (1 << 1)
2122 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
2124 /* BXT PHY PCS registers */
2125 #define _PORT_PCS_DW10_LN01_A 0x162428
2126 #define _PORT_PCS_DW10_LN01_B 0x6C428
2127 #define _PORT_PCS_DW10_LN01_C 0x6C828
2128 #define _PORT_PCS_DW10_GRP_A 0x162C28
2129 #define _PORT_PCS_DW10_GRP_B 0x6CC28
2130 #define _PORT_PCS_DW10_GRP_C 0x6CE28
2131 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2132 _PORT_PCS_DW10_LN01_B, \
2133 _PORT_PCS_DW10_LN01_C)
2134 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2135 _PORT_PCS_DW10_GRP_B, \
2136 _PORT_PCS_DW10_GRP_C)
2138 #define TX2_SWING_CALC_INIT (1 << 31)
2139 #define TX1_SWING_CALC_INIT (1 << 30)
2141 #define _PORT_PCS_DW12_LN01_A 0x162430
2142 #define _PORT_PCS_DW12_LN01_B 0x6C430
2143 #define _PORT_PCS_DW12_LN01_C 0x6C830
2144 #define _PORT_PCS_DW12_LN23_A 0x162630
2145 #define _PORT_PCS_DW12_LN23_B 0x6C630
2146 #define _PORT_PCS_DW12_LN23_C 0x6CA30
2147 #define _PORT_PCS_DW12_GRP_A 0x162c30
2148 #define _PORT_PCS_DW12_GRP_B 0x6CC30
2149 #define _PORT_PCS_DW12_GRP_C 0x6CE30
2150 #define LANESTAGGER_STRAP_OVRD (1 << 6)
2151 #define LANE_STAGGER_MASK 0x1F
2152 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2153 _PORT_PCS_DW12_LN01_B, \
2154 _PORT_PCS_DW12_LN01_C)
2155 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2156 _PORT_PCS_DW12_LN23_B, \
2157 _PORT_PCS_DW12_LN23_C)
2158 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2159 _PORT_PCS_DW12_GRP_B, \
2160 _PORT_PCS_DW12_GRP_C)
2162 /* BXT PHY TX registers */
2163 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2164 ((lane) & 1) * 0x80)
2166 #define _PORT_TX_DW2_LN0_A 0x162508
2167 #define _PORT_TX_DW2_LN0_B 0x6C508
2168 #define _PORT_TX_DW2_LN0_C 0x6C908
2169 #define _PORT_TX_DW2_GRP_A 0x162D08
2170 #define _PORT_TX_DW2_GRP_B 0x6CD08
2171 #define _PORT_TX_DW2_GRP_C 0x6CF08
2172 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2173 _PORT_TX_DW2_LN0_B, \
2175 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2176 _PORT_TX_DW2_GRP_B, \
2178 #define MARGIN_000_SHIFT 16
2179 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2180 #define UNIQ_TRANS_SCALE_SHIFT 8
2181 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2183 #define _PORT_TX_DW3_LN0_A 0x16250C
2184 #define _PORT_TX_DW3_LN0_B 0x6C50C
2185 #define _PORT_TX_DW3_LN0_C 0x6C90C
2186 #define _PORT_TX_DW3_GRP_A 0x162D0C
2187 #define _PORT_TX_DW3_GRP_B 0x6CD0C
2188 #define _PORT_TX_DW3_GRP_C 0x6CF0C
2189 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2190 _PORT_TX_DW3_LN0_B, \
2192 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2193 _PORT_TX_DW3_GRP_B, \
2195 #define SCALE_DCOMP_METHOD (1 << 26)
2196 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
2198 #define _PORT_TX_DW4_LN0_A 0x162510
2199 #define _PORT_TX_DW4_LN0_B 0x6C510
2200 #define _PORT_TX_DW4_LN0_C 0x6C910
2201 #define _PORT_TX_DW4_GRP_A 0x162D10
2202 #define _PORT_TX_DW4_GRP_B 0x6CD10
2203 #define _PORT_TX_DW4_GRP_C 0x6CF10
2204 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2205 _PORT_TX_DW4_LN0_B, \
2207 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2208 _PORT_TX_DW4_GRP_B, \
2210 #define DEEMPH_SHIFT 24
2211 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2213 #define _PORT_TX_DW5_LN0_A 0x162514
2214 #define _PORT_TX_DW5_LN0_B 0x6C514
2215 #define _PORT_TX_DW5_LN0_C 0x6C914
2216 #define _PORT_TX_DW5_GRP_A 0x162D14
2217 #define _PORT_TX_DW5_GRP_B 0x6CD14
2218 #define _PORT_TX_DW5_GRP_C 0x6CF14
2219 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2220 _PORT_TX_DW5_LN0_B, \
2222 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2223 _PORT_TX_DW5_GRP_B, \
2225 #define DCC_DELAY_RANGE_1 (1 << 9)
2226 #define DCC_DELAY_RANGE_2 (1 << 8)
2228 #define _PORT_TX_DW14_LN0_A 0x162538
2229 #define _PORT_TX_DW14_LN0_B 0x6C538
2230 #define _PORT_TX_DW14_LN0_C 0x6C938
2231 #define LATENCY_OPTIM_SHIFT 30
2232 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
2233 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2234 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2235 _PORT_TX_DW14_LN0_C) + \
2236 _BXT_LANE_OFFSET(lane))
2238 /* UAIMI scratch pad register 1 */
2239 #define UAIMI_SPR1 _MMIO(0x4F074)
2240 /* SKL VccIO mask */
2241 #define SKL_VCCIO_MASK 0x1
2242 /* SKL balance leg register */
2243 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
2244 /* I_boost values */
2245 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
2246 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
2247 /* Balance leg disable bits */
2248 #define BALANCE_LEG_DISABLE_SHIFT 23
2249 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
2253 * [0-7] @ 0x2000 gen2,gen3
2254 * [8-15] @ 0x3000 945,g33,pnv
2256 * [0-15] @ 0x3000 gen4,gen5
2258 * [0-15] @ 0x100000 gen6,vlv,chv
2259 * [0-31] @ 0x100000 gen7+
2261 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2262 #define I830_FENCE_START_MASK 0x07f80000
2263 #define I830_FENCE_TILING_Y_SHIFT 12
2264 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2265 #define I830_FENCE_PITCH_SHIFT 4
2266 #define I830_FENCE_REG_VALID (1 << 0)
2267 #define I915_FENCE_MAX_PITCH_VAL 4
2268 #define I830_FENCE_MAX_PITCH_VAL 6
2269 #define I830_FENCE_MAX_SIZE_VAL (1 << 8)
2271 #define I915_FENCE_START_MASK 0x0ff00000
2272 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2274 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2275 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
2276 #define I965_FENCE_PITCH_SHIFT 2
2277 #define I965_FENCE_TILING_Y_SHIFT 1
2278 #define I965_FENCE_REG_VALID (1 << 0)
2279 #define I965_FENCE_MAX_PITCH_VAL 0x0400
2281 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2282 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
2283 #define GEN6_FENCE_PITCH_SHIFT 32
2284 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
2287 /* control register for cpu gtt access */
2288 #define TILECTL _MMIO(0x101000)
2289 #define TILECTL_SWZCTL (1 << 0)
2290 #define TILECTL_TLBPF (1 << 1)
2291 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2292 #define TILECTL_BACKSNOOP_DIS (1 << 3)
2295 * Instruction and interrupt control regs
2297 #define PGTBL_CTL _MMIO(0x02020)
2298 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2299 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
2300 #define PGTBL_ER _MMIO(0x02024)
2301 #define PRB0_BASE (0x2030 - 0x30)
2302 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
2303 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
2304 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
2305 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
2306 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
2307 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
2308 #define RENDER_RING_BASE 0x02000
2309 #define BSD_RING_BASE 0x04000
2310 #define GEN6_BSD_RING_BASE 0x12000
2311 #define GEN8_BSD2_RING_BASE 0x1c000
2312 #define GEN11_BSD_RING_BASE 0x1c0000
2313 #define GEN11_BSD2_RING_BASE 0x1c4000
2314 #define GEN11_BSD3_RING_BASE 0x1d0000
2315 #define GEN11_BSD4_RING_BASE 0x1d4000
2316 #define VEBOX_RING_BASE 0x1a000
2317 #define GEN11_VEBOX_RING_BASE 0x1c8000
2318 #define GEN11_VEBOX2_RING_BASE 0x1d8000
2319 #define BLT_RING_BASE 0x22000
2320 #define RING_TAIL(base) _MMIO((base) + 0x30)
2321 #define RING_HEAD(base) _MMIO((base) + 0x34)
2322 #define RING_START(base) _MMIO((base) + 0x38)
2323 #define RING_CTL(base) _MMIO((base) + 0x3c)
2324 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2325 #define RING_SYNC_0(base) _MMIO((base) + 0x40)
2326 #define RING_SYNC_1(base) _MMIO((base) + 0x44)
2327 #define RING_SYNC_2(base) _MMIO((base) + 0x48)
2328 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2329 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2330 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2331 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2332 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2333 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2334 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2335 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2336 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2337 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2338 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2339 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2340 #define GEN6_NOSYNC INVALID_MMIO_REG
2341 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
2342 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
2343 #define RING_HWS_PGA(base) _MMIO((base) + 0x80)
2344 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2345 #define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
2346 #define RESET_CTL_REQUEST_RESET (1 << 0)
2347 #define RESET_CTL_READY_TO_RESET (1 << 1)
2348 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2350 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
2351 #define GTT_CACHE_EN_ALL 0xF0007FFF
2352 #define GEN7_WR_WATERMARK _MMIO(0x4028)
2353 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2354 #define ARB_MODE _MMIO(0x4030)
2355 #define ARB_MODE_SWIZZLE_SNB (1 << 4)
2356 #define ARB_MODE_SWIZZLE_IVB (1 << 5)
2357 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2358 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
2359 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2360 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
2361 #define GEN7_LRA_LIMITS_REG_NUM 13
2362 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2363 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2365 #define GAMTARBMODE _MMIO(0x04a08)
2366 #define ARB_MODE_BWGTLB_DISABLE (1 << 9)
2367 #define ARB_MODE_SWIZZLE_BDW (1 << 1)
2368 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2369 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
2370 #define GEN8_RING_FAULT_REG _MMIO(0x4094)
2371 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2372 #define RING_FAULT_GTTSEL_MASK (1 << 11)
2373 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2374 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2375 #define RING_FAULT_VALID (1 << 0)
2376 #define DONE_REG _MMIO(0x40b0)
2377 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2378 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2379 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
2380 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2381 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2382 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2383 #define RING_ACTHD(base) _MMIO((base) + 0x74)
2384 #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
2385 #define RING_NOPID(base) _MMIO((base) + 0x94)
2386 #define RING_IMR(base) _MMIO((base) + 0xa8)
2387 #define RING_HWSTAM(base) _MMIO((base) + 0x98)
2388 #define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
2389 #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
2390 #define TAIL_ADDR 0x001FFFF8
2391 #define HEAD_WRAP_COUNT 0xFFE00000
2392 #define HEAD_WRAP_ONE 0x00200000
2393 #define HEAD_ADDR 0x001FFFFC
2394 #define RING_NR_PAGES 0x001FF000
2395 #define RING_REPORT_MASK 0x00000006
2396 #define RING_REPORT_64K 0x00000002
2397 #define RING_REPORT_128K 0x00000004
2398 #define RING_NO_REPORT 0x00000000
2399 #define RING_VALID_MASK 0x00000001
2400 #define RING_VALID 0x00000001
2401 #define RING_INVALID 0x00000000
2402 #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
2403 #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
2404 #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
2406 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2407 #define RING_MAX_NONPRIV_SLOTS 12
2409 #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2411 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2412 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
2414 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2415 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2417 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2418 #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
2419 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
2420 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
2423 #define PRB0_TAIL _MMIO(0x2030)
2424 #define PRB0_HEAD _MMIO(0x2034)
2425 #define PRB0_START _MMIO(0x2038)
2426 #define PRB0_CTL _MMIO(0x203c)
2427 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2428 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2429 #define PRB1_START _MMIO(0x2048) /* 915+ only */
2430 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */
2432 #define IPEIR_I965 _MMIO(0x2064)
2433 #define IPEHR_I965 _MMIO(0x2068)
2434 #define GEN7_SC_INSTDONE _MMIO(0x7100)
2435 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2436 #define GEN7_ROW_INSTDONE _MMIO(0xe164)
2437 #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2438 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2439 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2440 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2441 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2442 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
2443 #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
2444 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
2445 #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
2446 #define RING_IPEIR(base) _MMIO((base) + 0x64)
2447 #define RING_IPEHR(base) _MMIO((base) + 0x68)
2449 * On GEN4, only the render ring INSTDONE exists and has a different
2450 * layout than the GEN7+ version.
2451 * The GEN2 counterpart of this register is GEN2_INSTDONE.
2453 #define RING_INSTDONE(base) _MMIO((base) + 0x6c)
2454 #define RING_INSTPS(base) _MMIO((base) + 0x70)
2455 #define RING_DMA_FADD(base) _MMIO((base) + 0x78)
2456 #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
2457 #define RING_INSTPM(base) _MMIO((base) + 0xc0)
2458 #define RING_MI_MODE(base) _MMIO((base) + 0x9c)
2459 #define INSTPS _MMIO(0x2070) /* 965+ only */
2460 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2461 #define ACTHD_I965 _MMIO(0x2074)
2462 #define HWS_PGA _MMIO(0x2080)
2463 #define HWS_ADDRESS_MASK 0xfffff000
2464 #define HWS_START_ADDRESS_SHIFT 4
2465 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
2466 #define PWRCTX_EN (1 << 0)
2467 #define IPEIR _MMIO(0x2088)
2468 #define IPEHR _MMIO(0x208c)
2469 #define GEN2_INSTDONE _MMIO(0x2090)
2470 #define NOPID _MMIO(0x2094)
2471 #define HWSTAM _MMIO(0x2098)
2472 #define DMA_FADD_I8XX _MMIO(0x20d0)
2473 #define RING_BBSTATE(base) _MMIO((base) + 0x110)
2474 #define RING_BB_PPGTT (1 << 5)
2475 #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
2476 #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
2477 #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
2478 #define RING_BBADDR(base) _MMIO((base) + 0x140)
2479 #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
2480 #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
2481 #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
2482 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
2483 #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
2485 #define ERROR_GEN6 _MMIO(0x40a0)
2486 #define GEN7_ERR_INT _MMIO(0x44040)
2487 #define ERR_INT_POISON (1 << 31)
2488 #define ERR_INT_MMIO_UNCLAIMED (1 << 13)
2489 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
2490 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
2491 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
2492 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
2493 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
2494 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
2495 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
2496 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
2498 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2499 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2500 #define FAULT_VA_HIGH_BITS (0xf << 0)
2501 #define FAULT_GTT_SEL (1 << 4)
2503 #define FPGA_DBG _MMIO(0x42300)
2504 #define FPGA_DBG_RM_NOCLAIM (1 << 31)
2506 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2507 #define CLAIM_ER_CLR (1 << 31)
2508 #define CLAIM_ER_OVERFLOW (1 << 16)
2509 #define CLAIM_ER_CTR_MASK 0xffff
2511 #define DERRMR _MMIO(0x44050)
2512 /* Note that HBLANK events are reserved on bdw+ */
2513 #define DERRMR_PIPEA_SCANLINE (1 << 0)
2514 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
2515 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
2516 #define DERRMR_PIPEA_VBLANK (1 << 3)
2517 #define DERRMR_PIPEA_HBLANK (1 << 5)
2518 #define DERRMR_PIPEB_SCANLINE (1 << 8)
2519 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
2520 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
2521 #define DERRMR_PIPEB_VBLANK (1 << 11)
2522 #define DERRMR_PIPEB_HBLANK (1 << 13)
2523 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2524 #define DERRMR_PIPEC_SCANLINE (1 << 14)
2525 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
2526 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
2527 #define DERRMR_PIPEC_VBLANK (1 << 21)
2528 #define DERRMR_PIPEC_HBLANK (1 << 22)
2531 /* GM45+ chicken bits -- debug workaround bits that may be required
2532 * for various sorts of correct behavior. The top 16 bits of each are
2533 * the enables for writing to the corresponding low bit.
2535 #define _3D_CHICKEN _MMIO(0x2084)
2536 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2537 #define _3D_CHICKEN2 _MMIO(0x208c)
2539 #define FF_SLICE_CHICKEN _MMIO(0x2088)
2540 #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
2542 /* Disables pipelining of read flushes past the SF-WIZ interface.
2543 * Required on all Ironlake steppings according to the B-Spec, but the
2544 * particular danger of not doing so is not specified.
2546 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2547 #define _3D_CHICKEN3 _MMIO(0x2090)
2548 #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
2549 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2550 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2551 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2552 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */
2553 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
2555 #define MI_MODE _MMIO(0x209c)
2556 # define VS_TIMER_DISPATCH (1 << 6)
2557 # define MI_FLUSH_ENABLE (1 << 12)
2558 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2559 # define MODE_IDLE (1 << 9)
2560 # define STOP_RING (1 << 8)
2562 #define GEN6_GT_MODE _MMIO(0x20d0)
2563 #define GEN7_GT_MODE _MMIO(0x7008)
2564 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2565 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2566 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2567 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2568 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2569 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2570 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2571 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2573 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2574 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2575 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2577 /* WaClearTdlStateAckDirtyBits */
2578 #define GEN8_STATE_ACK _MMIO(0x20F0)
2579 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2580 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2581 #define GEN9_STATE_ACK_TDL0 (1 << 12)
2582 #define GEN9_STATE_ACK_TDL1 (1 << 13)
2583 #define GEN9_STATE_ACK_TDL2 (1 << 14)
2584 #define GEN9_STATE_ACK_TDL3 (1 << 15)
2585 #define GEN9_SUBSLICE_TDL_ACK_BITS \
2586 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2587 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2589 #define GFX_MODE _MMIO(0x2520)
2590 #define GFX_MODE_GEN7 _MMIO(0x229c)
2591 #define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)
2592 #define GFX_RUN_LIST_ENABLE (1 << 15)
2593 #define GFX_INTERRUPT_STEERING (1 << 14)
2594 #define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
2595 #define GFX_SURFACE_FAULT_ENABLE (1 << 12)
2596 #define GFX_REPLAY_MODE (1 << 11)
2597 #define GFX_PSMI_GRANULARITY (1 << 10)
2598 #define GFX_PPGTT_ENABLE (1 << 9)
2599 #define GEN8_GFX_PPGTT_48B (1 << 7)
2601 #define GFX_FORWARD_VBLANK_MASK (3 << 5)
2602 #define GFX_FORWARD_VBLANK_NEVER (0 << 5)
2603 #define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
2604 #define GFX_FORWARD_VBLANK_COND (2 << 5)
2606 #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2608 #define VLV_DISPLAY_BASE 0x180000
2609 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
2610 #define BXT_MIPI_BASE 0x60000
2612 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2613 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2614 #define SCPD0 _MMIO(0x209c) /* 915+ only */
2615 #define IER _MMIO(0x20a0)
2616 #define IIR _MMIO(0x20a4)
2617 #define IMR _MMIO(0x20a8)
2618 #define ISR _MMIO(0x20ac)
2619 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2620 #define GINT_DIS (1 << 22)
2621 #define GCFG_DIS (1 << 8)
2622 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2623 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2624 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2625 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2626 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2627 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2628 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2629 #define VLV_PCBR_ADDR_SHIFT 12
2631 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2632 #define EIR _MMIO(0x20b0)
2633 #define EMR _MMIO(0x20b4)
2634 #define ESR _MMIO(0x20b8)
2635 #define GM45_ERROR_PAGE_TABLE (1 << 5)
2636 #define GM45_ERROR_MEM_PRIV (1 << 4)
2637 #define I915_ERROR_PAGE_TABLE (1 << 4)
2638 #define GM45_ERROR_CP_PRIV (1 << 3)
2639 #define I915_ERROR_MEMORY_REFRESH (1 << 1)
2640 #define I915_ERROR_INSTRUCTION (1 << 0)
2641 #define INSTPM _MMIO(0x20c0)
2642 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */
2643 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
2644 will not assert AGPBUSY# and will only
2645 be delivered when out of C3. */
2646 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
2647 #define INSTPM_TLB_INVALIDATE (1 << 9)
2648 #define INSTPM_SYNC_FLUSH (1 << 5)
2649 #define ACTHD _MMIO(0x20c8)
2650 #define MEM_MODE _MMIO(0x20cc)
2651 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2652 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2653 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
2654 #define FW_BLC _MMIO(0x20d8)
2655 #define FW_BLC2 _MMIO(0x20dc)
2656 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
2657 #define FW_BLC_SELF_EN_MASK (1 << 31)
2658 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
2659 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */
2660 #define MM_BURST_LENGTH 0x00700000
2661 #define MM_FIFO_WATERMARK 0x0001F000
2662 #define LM_BURST_LENGTH 0x00000700
2663 #define LM_FIFO_WATERMARK 0x0000001F
2664 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
2666 #define MBUS_ABOX_CTL _MMIO(0x45038)
2667 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
2668 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
2669 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
2670 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
2671 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
2672 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
2673 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
2674 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
2676 #define _PIPEA_MBUS_DBOX_CTL 0x7003C
2677 #define _PIPEB_MBUS_DBOX_CTL 0x7103C
2678 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2679 _PIPEB_MBUS_DBOX_CTL)
2680 #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
2681 #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
2682 #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
2683 #define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
2684 #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
2685 #define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
2687 #define MBUS_UBOX_CTL _MMIO(0x4503C)
2688 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
2689 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
2691 /* Make render/texture TLB fetches lower priorty than associated data
2692 * fetches. This is not turned on by default
2694 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
2696 /* Isoch request wait on GTT enable (Display A/B/C streams).
2697 * Make isoch requests stall on the TLB update. May cause
2698 * display underruns (test mode only)
2700 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
2702 /* Block grant count for isoch requests when block count is
2703 * set to a finite value.
2705 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
2706 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
2707 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
2708 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
2709 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
2711 /* Enable render writes to complete in C2/C3/C4 power states.
2712 * If this isn't enabled, render writes are prevented in low
2713 * power states. That seems bad to me.
2715 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
2717 /* This acknowledges an async flip immediately instead
2718 * of waiting for 2TLB fetches.
2720 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
2722 /* Enables non-sequential data reads through arbiter
2724 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
2726 /* Disable FSB snooping of cacheable write cycles from binner/render
2729 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
2731 /* Arbiter time slice for non-isoch streams */
2732 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
2733 #define MI_ARB_TIME_SLICE_1 (0 << 5)
2734 #define MI_ARB_TIME_SLICE_2 (1 << 5)
2735 #define MI_ARB_TIME_SLICE_4 (2 << 5)
2736 #define MI_ARB_TIME_SLICE_6 (3 << 5)
2737 #define MI_ARB_TIME_SLICE_8 (4 << 5)
2738 #define MI_ARB_TIME_SLICE_10 (5 << 5)
2739 #define MI_ARB_TIME_SLICE_14 (6 << 5)
2740 #define MI_ARB_TIME_SLICE_16 (7 << 5)
2742 /* Low priority grace period page size */
2743 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
2744 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
2746 /* Disable display A/B trickle feed */
2747 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2749 /* Set display plane priority */
2750 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
2751 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
2753 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
2754 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
2755 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
2757 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
2758 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
2759 #define CM0_IZ_OPT_DISABLE (1 << 6)
2760 #define CM0_ZR_OPT_DISABLE (1 << 5)
2761 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
2762 #define CM0_DEPTH_EVICT_DISABLE (1 << 4)
2763 #define CM0_COLOR_EVICT_DISABLE (1 << 3)
2764 #define CM0_DEPTH_WRITE_DISABLE (1 << 1)
2765 #define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
2766 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
2767 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
2768 #define GFX_FLSH_CNTL_EN (1 << 0)
2769 #define ECOSKPD _MMIO(0x21d0)
2770 #define ECO_GATING_CX_ONLY (1 << 3)
2771 #define ECO_FLIP_DONE (1 << 0)
2773 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
2774 #define RC_OP_FLUSH_ENABLE (1 << 0)
2775 #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
2776 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
2777 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)
2778 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
2779 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
2781 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
2782 #define GEN6_BLITTER_LOCK_SHIFT 16
2783 #define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
2785 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
2786 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
2787 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2788 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
2790 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2791 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2793 /* Fuse readout registers for GT */
2794 #define HSW_PAVP_FUSE1 _MMIO(0x911C)
2795 #define HSW_F1_EU_DIS_SHIFT 16
2796 #define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT)
2797 #define HSW_F1_EU_DIS_10EUS 0
2798 #define HSW_F1_EU_DIS_8EUS 1
2799 #define HSW_F1_EU_DIS_6EUS 2
2801 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
2802 #define CHV_FGT_DISABLE_SS0 (1 << 10)
2803 #define CHV_FGT_DISABLE_SS1 (1 << 11)
2804 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2805 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2806 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2807 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2808 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2809 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2810 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2811 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2813 #define GEN8_FUSE2 _MMIO(0x9120)
2814 #define GEN8_F2_SS_DIS_SHIFT 21
2815 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
2816 #define GEN8_F2_S_ENA_SHIFT 25
2817 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2819 #define GEN9_F2_SS_DIS_SHIFT 20
2820 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2822 #define GEN10_F2_S_ENA_SHIFT 22
2823 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
2824 #define GEN10_F2_SS_DIS_SHIFT 18
2825 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
2827 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
2828 #define GEN10_L3BANK_PAIR_COUNT 4
2829 #define GEN10_L3BANK_MASK 0x0F
2831 #define GEN8_EU_DISABLE0 _MMIO(0x9134)
2832 #define GEN8_EU_DIS0_S0_MASK 0xffffff
2833 #define GEN8_EU_DIS0_S1_SHIFT 24
2834 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2836 #define GEN8_EU_DISABLE1 _MMIO(0x9138)
2837 #define GEN8_EU_DIS1_S1_MASK 0xffff
2838 #define GEN8_EU_DIS1_S2_SHIFT 16
2839 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2841 #define GEN8_EU_DISABLE2 _MMIO(0x913c)
2842 #define GEN8_EU_DIS2_S2_MASK 0xff
2844 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
2846 #define GEN10_EU_DISABLE3 _MMIO(0x9140)
2847 #define GEN10_EU_DIS_SS_MASK 0xff
2849 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
2850 #define GEN11_GT_VDBOX_DISABLE_MASK 0xff
2851 #define GEN11_GT_VEBOX_DISABLE_SHIFT 16
2852 #define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
2854 #define GEN11_EU_DISABLE _MMIO(0x9134)
2855 #define GEN11_EU_DIS_MASK 0xFF
2857 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
2858 #define GEN11_GT_S_ENA_MASK 0xFF
2860 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
2862 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
2863 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
2864 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
2865 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
2866 #define GEN6_BSD_GO_INDICATOR (1 << 4)
2868 /* On modern GEN architectures interrupt control consists of two sets
2869 * of registers. The first set pertains to the ring generating the
2870 * interrupt. The second control is for the functional block generating the
2871 * interrupt. These are PM, GT, DE, etc.
2873 * Luckily *knocks on wood* all the ring interrupt bits match up with the
2874 * GT interrupt bits, so we don't need to duplicate the defines.
2876 * These defines should cover us well from SNB->HSW with minor exceptions
2877 * it can also work on ILK.
2879 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2880 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2881 #define GT_BLT_USER_INTERRUPT (1 << 22)
2882 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2883 #define GT_BSD_USER_INTERRUPT (1 << 12)
2884 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2885 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
2886 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2887 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2888 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2889 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2890 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2891 #define GT_RENDER_USER_INTERRUPT (1 << 0)
2893 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
2894 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
2896 #define GT_PARITY_ERROR(dev_priv) \
2897 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
2898 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
2900 /* These are all the "old" interrupts */
2901 #define ILK_BSD_USER_INTERRUPT (1 << 5)
2903 #define I915_PM_INTERRUPT (1 << 31)
2904 #define I915_ISP_INTERRUPT (1 << 22)
2905 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
2906 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
2907 #define I915_MIPIC_INTERRUPT (1 << 19)
2908 #define I915_MIPIA_INTERRUPT (1 << 18)
2909 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
2910 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
2911 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
2912 #define I915_MASTER_ERROR_INTERRUPT (1 << 15)
2913 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
2914 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
2915 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
2916 #define I915_HWB_OOM_INTERRUPT (1 << 13)
2917 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
2918 #define I915_SYNC_STATUS_INTERRUPT (1 << 12)
2919 #define I915_MISC_INTERRUPT (1 << 11)
2920 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
2921 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
2922 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
2923 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
2924 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
2925 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
2926 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
2927 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
2928 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
2929 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
2930 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
2931 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
2932 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
2933 #define I915_DEBUG_INTERRUPT (1 << 2)
2934 #define I915_WINVALID_INTERRUPT (1 << 1)
2935 #define I915_USER_INTERRUPT (1 << 1)
2936 #define I915_ASLE_INTERRUPT (1 << 0)
2937 #define I915_BSD_USER_INTERRUPT (1 << 25)
2939 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
2940 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000
2942 /* DisplayPort Audio w/ LPE */
2943 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
2944 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
2946 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
2947 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
2948 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
2949 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
2950 _VLV_AUD_PORT_EN_B_DBG, \
2951 _VLV_AUD_PORT_EN_C_DBG, \
2952 _VLV_AUD_PORT_EN_D_DBG)
2953 #define VLV_AMP_MUTE (1 << 1)
2955 #define GEN6_BSD_RNCID _MMIO(0x12198)
2957 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
2958 #define GEN7_FF_SCHED_MASK 0x0077070
2959 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
2960 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
2961 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
2962 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
2963 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
2964 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
2965 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
2966 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
2967 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
2968 #define GEN7_FF_VS_SCHED_HW (0x0 << 12)
2969 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
2970 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
2971 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
2972 #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
2975 * Framebuffer compression (915+ only)
2978 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2979 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2980 #define FBC_CONTROL _MMIO(0x3208)
2981 #define FBC_CTL_EN (1 << 31)
2982 #define FBC_CTL_PERIODIC (1 << 30)
2983 #define FBC_CTL_INTERVAL_SHIFT (16)
2984 #define FBC_CTL_UNCOMPRESSIBLE (1 << 14)
2985 #define FBC_CTL_C3_IDLE (1 << 13)
2986 #define FBC_CTL_STRIDE_SHIFT (5)
2987 #define FBC_CTL_FENCENO_SHIFT (0)
2988 #define FBC_COMMAND _MMIO(0x320c)
2989 #define FBC_CMD_COMPRESS (1 << 0)
2990 #define FBC_STATUS _MMIO(0x3210)
2991 #define FBC_STAT_COMPRESSING (1 << 31)
2992 #define FBC_STAT_COMPRESSED (1 << 30)
2993 #define FBC_STAT_MODIFIED (1 << 29)
2994 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
2995 #define FBC_CONTROL2 _MMIO(0x3214)
2996 #define FBC_CTL_FENCE_DBL (0 << 4)
2997 #define FBC_CTL_IDLE_IMM (0 << 2)
2998 #define FBC_CTL_IDLE_FULL (1 << 2)
2999 #define FBC_CTL_IDLE_LINE (2 << 2)
3000 #define FBC_CTL_IDLE_DEBUG (3 << 2)
3001 #define FBC_CTL_CPU_FENCE (1 << 1)
3002 #define FBC_CTL_PLANE(plane) ((plane) << 0)
3003 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
3004 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
3006 #define FBC_LL_SIZE (1536)
3008 #define FBC_LLC_READ_CTRL _MMIO(0x9044)
3009 #define FBC_LLC_FULLY_OPEN (1 << 30)
3011 /* Framebuffer compression for GM45+ */
3012 #define DPFC_CB_BASE _MMIO(0x3200)
3013 #define DPFC_CONTROL _MMIO(0x3208)
3014 #define DPFC_CTL_EN (1 << 31)
3015 #define DPFC_CTL_PLANE(plane) ((plane) << 30)
3016 #define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29)
3017 #define DPFC_CTL_FENCE_EN (1 << 29)
3018 #define IVB_DPFC_CTL_FENCE_EN (1 << 28)
3019 #define DPFC_CTL_PERSISTENT_MODE (1 << 25)
3020 #define DPFC_SR_EN (1 << 10)
3021 #define DPFC_CTL_LIMIT_1X (0 << 6)
3022 #define DPFC_CTL_LIMIT_2X (1 << 6)
3023 #define DPFC_CTL_LIMIT_4X (2 << 6)
3024 #define DPFC_RECOMP_CTL _MMIO(0x320c)
3025 #define DPFC_RECOMP_STALL_EN (1 << 27)
3026 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
3027 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3028 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3029 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3030 #define DPFC_STATUS _MMIO(0x3210)
3031 #define DPFC_INVAL_SEG_SHIFT (16)
3032 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
3033 #define DPFC_COMP_SEG_SHIFT (0)
3034 #define DPFC_COMP_SEG_MASK (0x000007ff)
3035 #define DPFC_STATUS2 _MMIO(0x3214)
3036 #define DPFC_FENCE_YOFF _MMIO(0x3218)
3037 #define DPFC_CHICKEN _MMIO(0x3224)
3038 #define DPFC_HT_MODIFY (1 << 31)
3040 /* Framebuffer compression for Ironlake */
3041 #define ILK_DPFC_CB_BASE _MMIO(0x43200)
3042 #define ILK_DPFC_CONTROL _MMIO(0x43208)
3043 #define FBC_CTL_FALSE_COLOR (1 << 10)
3044 /* The bit 28-8 is reserved */
3045 #define DPFC_RESERVED (0x1FFFFF00)
3046 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
3047 #define ILK_DPFC_STATUS _MMIO(0x43210)
3048 #define ILK_DPFC_COMP_SEG_MASK 0x7ff
3049 #define IVB_FBC_STATUS2 _MMIO(0x43214)
3050 #define IVB_FBC_COMP_SEG_MASK 0x7ff
3051 #define BDW_FBC_COMP_SEG_MASK 0xfff
3052 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3053 #define ILK_DPFC_CHICKEN _MMIO(0x43224)
3054 #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3055 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
3056 #define ILK_FBC_RT_BASE _MMIO(0x2128)
3057 #define ILK_FBC_RT_VALID (1 << 0)
3058 #define SNB_FBC_FRONT_BUFFER (1 << 1)
3060 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
3061 #define ILK_FBCQ_DIS (1 << 22)
3062 #define ILK_PABSTRETCH_DIS (1 << 21)
3066 * Framebuffer compression for Sandybridge
3068 * The following two registers are of type GTTMMADR
3070 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
3071 #define SNB_CPU_FENCE_ENABLE (1 << 29)
3072 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
3074 /* Framebuffer compression for Ivybridge */
3075 #define IVB_FBC_RT_BASE _MMIO(0x7020)
3077 #define IPS_CTL _MMIO(0x43408)
3078 #define IPS_ENABLE (1 << 31)
3080 #define MSG_FBC_REND_STATE _MMIO(0x50380)
3081 #define FBC_REND_NUKE (1 << 2)
3082 #define FBC_REND_CACHE_CLEAN (1 << 1)
3087 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3090 # define GPIO_CLOCK_DIR_MASK (1 << 0)
3091 # define GPIO_CLOCK_DIR_IN (0 << 1)
3092 # define GPIO_CLOCK_DIR_OUT (1 << 1)
3093 # define GPIO_CLOCK_VAL_MASK (1 << 2)
3094 # define GPIO_CLOCK_VAL_OUT (1 << 3)
3095 # define GPIO_CLOCK_VAL_IN (1 << 4)
3096 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3097 # define GPIO_DATA_DIR_MASK (1 << 8)
3098 # define GPIO_DATA_DIR_IN (0 << 9)
3099 # define GPIO_DATA_DIR_OUT (1 << 9)
3100 # define GPIO_DATA_VAL_MASK (1 << 10)
3101 # define GPIO_DATA_VAL_OUT (1 << 11)
3102 # define GPIO_DATA_VAL_IN (1 << 12)
3103 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3105 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3106 #define GMBUS_AKSV_SELECT (1 << 11)
3107 #define GMBUS_RATE_100KHZ (0 << 8)
3108 #define GMBUS_RATE_50KHZ (1 << 8)
3109 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */
3110 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
3111 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
3112 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3113 #define GMBUS_PIN_DISABLED 0
3114 #define GMBUS_PIN_SSC 1
3115 #define GMBUS_PIN_VGADDC 2
3116 #define GMBUS_PIN_PANEL 3
3117 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
3118 #define GMBUS_PIN_DPC 4 /* HDMIC */
3119 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
3120 #define GMBUS_PIN_DPD 6 /* HDMID */
3121 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */
3122 #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
3123 #define GMBUS_PIN_2_BXT 2
3124 #define GMBUS_PIN_3_BXT 3
3125 #define GMBUS_PIN_4_CNP 4
3126 #define GMBUS_PIN_9_TC1_ICP 9
3127 #define GMBUS_PIN_10_TC2_ICP 10
3128 #define GMBUS_PIN_11_TC3_ICP 11
3129 #define GMBUS_PIN_12_TC4_ICP 12
3131 #define GMBUS_NUM_PINS 13 /* including 0 */
3132 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3133 #define GMBUS_SW_CLR_INT (1 << 31)
3134 #define GMBUS_SW_RDY (1 << 30)
3135 #define GMBUS_ENT (1 << 29) /* enable timeout */
3136 #define GMBUS_CYCLE_NONE (0 << 25)
3137 #define GMBUS_CYCLE_WAIT (1 << 25)
3138 #define GMBUS_CYCLE_INDEX (2 << 25)
3139 #define GMBUS_CYCLE_STOP (4 << 25)
3140 #define GMBUS_BYTE_COUNT_SHIFT 16
3141 #define GMBUS_BYTE_COUNT_MAX 256U
3142 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U
3143 #define GMBUS_SLAVE_INDEX_SHIFT 8
3144 #define GMBUS_SLAVE_ADDR_SHIFT 1
3145 #define GMBUS_SLAVE_READ (1 << 0)
3146 #define GMBUS_SLAVE_WRITE (0 << 0)
3147 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3148 #define GMBUS_INUSE (1 << 15)
3149 #define GMBUS_HW_WAIT_PHASE (1 << 14)
3150 #define GMBUS_STALL_TIMEOUT (1 << 13)
3151 #define GMBUS_INT (1 << 12)
3152 #define GMBUS_HW_RDY (1 << 11)
3153 #define GMBUS_SATOER (1 << 10)
3154 #define GMBUS_ACTIVE (1 << 9)
3155 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3156 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3157 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3158 #define GMBUS_NAK_EN (1 << 3)
3159 #define GMBUS_IDLE_EN (1 << 2)
3160 #define GMBUS_HW_WAIT_EN (1 << 1)
3161 #define GMBUS_HW_RDY_EN (1 << 0)
3162 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3163 #define GMBUS_2BYTE_INDEX_EN (1 << 31)
3166 * Clock control & power management
3168 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
3169 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
3170 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
3171 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3173 #define VGA0 _MMIO(0x6000)
3174 #define VGA1 _MMIO(0x6004)
3175 #define VGA_PD _MMIO(0x6010)
3176 #define VGA0_PD_P2_DIV_4 (1 << 7)
3177 #define VGA0_PD_P1_DIV_2 (1 << 5)
3178 #define VGA0_PD_P1_SHIFT 0
3179 #define VGA0_PD_P1_MASK (0x1f << 0)
3180 #define VGA1_PD_P2_DIV_4 (1 << 15)
3181 #define VGA1_PD_P1_DIV_2 (1 << 13)
3182 #define VGA1_PD_P1_SHIFT 8
3183 #define VGA1_PD_P1_MASK (0x1f << 8)
3184 #define DPLL_VCO_ENABLE (1 << 31)
3185 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
3186 #define DPLL_DVO_2X_MODE (1 << 30)
3187 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
3188 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
3189 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
3190 #define DPLL_VGA_MODE_DIS (1 << 28)
3191 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
3192 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
3193 #define DPLL_MODE_MASK (3 << 26)
3194 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3195 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3196 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
3197 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
3198 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
3199 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
3200 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
3201 #define DPLL_LOCK_VLV (1 << 15)
3202 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
3203 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
3204 #define DPLL_SSC_REF_CLK_CHV (1 << 13)
3205 #define DPLL_PORTC_READY_MASK (0xf << 4)
3206 #define DPLL_PORTB_READY_MASK (0xf)
3208 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
3210 /* Additional CHV pll/phy registers */
3211 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3212 #define DPLL_PORTD_READY_MASK (0xf)
3213 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3214 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
3215 #define PHY_LDO_DELAY_0NS 0x0
3216 #define PHY_LDO_DELAY_200NS 0x1
3217 #define PHY_LDO_DELAY_600NS 0x2
3218 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
3219 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
3220 #define PHY_CH_SU_PSR 0x1
3221 #define PHY_CH_DEEP_PSR 0x7
3222 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
3223 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
3224 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3225 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3226 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
3227 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3230 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3231 * this field (only one bit may be set).
3233 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3234 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
3235 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3236 /* i830, required in DVO non-gang */
3237 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
3238 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
3239 #define PLL_REF_INPUT_DREFCLK (0 << 13)
3240 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
3241 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
3242 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3243 #define PLL_REF_INPUT_MASK (3 << 13)
3244 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
3246 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3247 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3248 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
3249 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3250 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3253 * Parallel to Serial Load Pulse phase selection.
3254 * Selects the phase for the 10X DPLL clock for the PCIe
3255 * digital display port. The range is 4 to 13; 10 or more
3256 * is just a flip delay. The default is 6
3258 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3259 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3261 * SDVO multiplier for 945G/GM. Not used on 965.
3263 #define SDVO_MULTIPLIER_MASK 0x000000ff
3264 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
3265 #define SDVO_MULTIPLIER_SHIFT_VGA 0
3267 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
3268 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
3269 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
3270 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3273 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3275 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3277 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3278 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
3279 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3280 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3281 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3283 * SDVO/UDI pixel multiplier.
3285 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3286 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3287 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3288 * dummy bytes in the datastream at an increased clock rate, with both sides of
3289 * the link knowing how many bytes are fill.
3291 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3292 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3293 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3294 * through an SDVO command.
3296 * This register field has values of multiplication factor minus 1, with
3297 * a maximum multiplier of 5 for SDVO.
3299 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3300 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3302 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3303 * This best be set to the default value (3) or the CRT won't work. No,
3304 * I don't entirely understand what this does...
3306 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3307 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
3309 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3311 #define _FPA0 0x6040
3312 #define _FPA1 0x6044
3313 #define _FPB0 0x6048
3314 #define _FPB1 0x604c
3315 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3316 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3317 #define FP_N_DIV_MASK 0x003f0000
3318 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
3319 #define FP_N_DIV_SHIFT 16
3320 #define FP_M1_DIV_MASK 0x00003f00
3321 #define FP_M1_DIV_SHIFT 8
3322 #define FP_M2_DIV_MASK 0x0000003f
3323 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
3324 #define FP_M2_DIV_SHIFT 0
3325 #define DPLL_TEST _MMIO(0x606c)
3326 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3327 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3328 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3329 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3330 #define DPLLB_TEST_N_BYPASS (1 << 19)
3331 #define DPLLB_TEST_M_BYPASS (1 << 18)
3332 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3333 #define DPLLA_TEST_N_BYPASS (1 << 3)
3334 #define DPLLA_TEST_M_BYPASS (1 << 2)
3335 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
3336 #define D_STATE _MMIO(0x6104)
3337 #define DSTATE_GFX_RESET_I830 (1 << 6)
3338 #define DSTATE_PLL_D3_OFF (1 << 3)
3339 #define DSTATE_GFX_CLOCK_GATING (1 << 1)
3340 #define DSTATE_DOT_CLOCK_GATING (1 << 0)
3341 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
3342 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3343 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3344 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
3345 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
3346 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
3347 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
3348 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
3349 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
3350 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3351 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3352 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3353 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3354 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3355 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3356 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3357 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3358 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3359 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3360 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3361 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3362 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3363 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3364 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3365 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3366 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
3367 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3368 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3369 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3370 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
3372 * This bit must be set on the 830 to prevent hangs when turning off the
3375 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3376 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3377 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3378 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
3379 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
3381 #define RENCLK_GATE_D1 _MMIO(0x6204)
3382 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
3383 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
3384 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3385 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3386 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3387 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3388 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3389 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3390 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
3391 /* This bit must be unset on 855,865 */
3392 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
3393 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3394 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
3395 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
3396 /* This bit must be set on 855,865. */
3397 # define SV_CLOCK_GATE_DISABLE (1 << 0)
3398 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3399 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3400 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3401 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3402 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3403 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3404 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3405 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3406 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3407 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3408 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3409 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3410 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3411 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3412 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3413 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3414 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3416 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
3417 /* This bit must always be set on 965G/965GM */
3418 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3419 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3420 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3421 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3422 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3423 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
3424 /* This bit must always be set on 965G */
3425 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3426 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3427 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3428 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3429 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3430 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3431 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3432 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3433 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3434 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3435 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3436 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3437 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3438 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3439 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3440 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3441 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3442 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3443 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3445 #define RENCLK_GATE_D2 _MMIO(0x6208)
3446 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3447 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3448 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
3450 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
3451 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3453 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
3454 #define DEUC _MMIO(0x6214) /* CRL only */
3456 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3457 #define FW_CSPWRDWNEN (1 << 15)
3459 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3461 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3462 #define CDCLK_FREQ_SHIFT 4
3463 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3464 #define CZCLK_FREQ_MASK 0xf
3466 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3467 #define PFI_CREDIT_63 (9 << 28) /* chv only */
3468 #define PFI_CREDIT_31 (8 << 28) /* chv only */
3469 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3470 #define PFI_CREDIT_RESEND (1 << 27)
3471 #define VGA_FAST_MODE_DISABLE (1 << 14)
3473 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
3478 #define PALETTE_A_OFFSET 0xa000
3479 #define PALETTE_B_OFFSET 0xa800
3480 #define CHV_PALETTE_C_OFFSET 0xc000
3481 #define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
3482 dev_priv->info.display_mmio_offset + (i) * 4)
3484 /* MCH MMIO space */
3489 * This mirrors the MCHBAR MMIO space whose location is determined by
3490 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3491 * every way. It is not accessible from the CP register read instructions.
3493 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3496 #define MCHBAR_MIRROR_BASE 0x10000
3498 #define MCHBAR_MIRROR_BASE_SNB 0x140000
3500 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3501 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3502 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3503 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
3504 #define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
3506 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3507 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3509 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3510 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3511 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3512 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3513 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3514 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
3515 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
3516 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
3517 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3518 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
3520 /* Pineview MCH register contains DDR3 setting */
3521 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3522 #define CSHRDDR3CTL_DDR3 (1 << 2)
3524 /* 965 MCH register controlling DRAM channel configuration */
3525 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3526 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3528 /* snb MCH registers for reading the DRAM channel configuration */
3529 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3530 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3531 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3532 #define MAD_DIMM_ECC_MASK (0x3 << 24)
3533 #define MAD_DIMM_ECC_OFF (0x0 << 24)
3534 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3535 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3536 #define MAD_DIMM_ECC_ON (0x3 << 24)
3537 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3538 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3539 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
3540 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
3541 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3542 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3543 #define MAD_DIMM_A_SELECT (0x1 << 16)
3544 /* DIMM sizes are in multiples of 256mb. */
3545 #define MAD_DIMM_B_SIZE_SHIFT 8
3546 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3547 #define MAD_DIMM_A_SIZE_SHIFT 0
3548 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3550 /* snb MCH registers for priority tuning */
3551 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3552 #define MCH_SSKPD_WM0_MASK 0x3f
3553 #define MCH_SSKPD_WM0_VAL 0xc
3555 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3557 /* Clocking configuration register */
3558 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3559 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
3560 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3561 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3562 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3563 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
3564 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
3565 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
3567 * Note that on at least on ELK the below value is reported for both
3568 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3569 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3571 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
3572 #define CLKCFG_FSB_MASK (7 << 0)
3573 #define CLKCFG_MEM_533 (1 << 4)
3574 #define CLKCFG_MEM_667 (2 << 4)
3575 #define CLKCFG_MEM_800 (3 << 4)
3576 #define CLKCFG_MEM_MASK (7 << 4)
3578 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3579 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3581 #define TSC1 _MMIO(0x11001)
3582 #define TSE (1 << 0)
3583 #define TR1 _MMIO(0x11006)
3584 #define TSFS _MMIO(0x11020)
3585 #define TSFS_SLOPE_MASK 0x0000ff00
3586 #define TSFS_SLOPE_SHIFT 8
3587 #define TSFS_INTR_MASK 0x000000ff
3589 #define CRSTANDVID _MMIO(0x11100)
3590 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3591 #define PXVFREQ_PX_MASK 0x7f000000
3592 #define PXVFREQ_PX_SHIFT 24
3593 #define VIDFREQ_BASE _MMIO(0x11110)
3594 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3595 #define VIDFREQ2 _MMIO(0x11114)
3596 #define VIDFREQ3 _MMIO(0x11118)
3597 #define VIDFREQ4 _MMIO(0x1111c)
3598 #define VIDFREQ_P0_MASK 0x1f000000
3599 #define VIDFREQ_P0_SHIFT 24
3600 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3601 #define VIDFREQ_P0_CSCLK_SHIFT 20
3602 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3603 #define VIDFREQ_P0_CRCLK_SHIFT 16
3604 #define VIDFREQ_P1_MASK 0x00001f00
3605 #define VIDFREQ_P1_SHIFT 8
3606 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3607 #define VIDFREQ_P1_CSCLK_SHIFT 4
3608 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3609 #define INTTOEXT_BASE_ILK _MMIO(0x11300)
3610 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3611 #define INTTOEXT_MAP3_SHIFT 24
3612 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
3613 #define INTTOEXT_MAP2_SHIFT 16
3614 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
3615 #define INTTOEXT_MAP1_SHIFT 8
3616 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
3617 #define INTTOEXT_MAP0_SHIFT 0
3618 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
3619 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
3620 #define MEMCTL_CMD_MASK 0xe000
3621 #define MEMCTL_CMD_SHIFT 13
3622 #define MEMCTL_CMD_RCLK_OFF 0
3623 #define MEMCTL_CMD_RCLK_ON 1
3624 #define MEMCTL_CMD_CHFREQ 2
3625 #define MEMCTL_CMD_CHVID 3
3626 #define MEMCTL_CMD_VMMOFF 4
3627 #define MEMCTL_CMD_VMMON 5
3628 #define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
3629 when command complete */
3630 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3631 #define MEMCTL_FREQ_SHIFT 8
3632 #define MEMCTL_SFCAVM (1 << 7)
3633 #define MEMCTL_TGT_VID_MASK 0x007f
3634 #define MEMIHYST _MMIO(0x1117c)
3635 #define MEMINTREN _MMIO(0x11180) /* 16 bits */
3636 #define MEMINT_RSEXIT_EN (1 << 8)
3637 #define MEMINT_CX_SUPR_EN (1 << 7)
3638 #define MEMINT_CONT_BUSY_EN (1 << 6)
3639 #define MEMINT_AVG_BUSY_EN (1 << 5)
3640 #define MEMINT_EVAL_CHG_EN (1 << 4)
3641 #define MEMINT_MON_IDLE_EN (1 << 3)
3642 #define MEMINT_UP_EVAL_EN (1 << 2)
3643 #define MEMINT_DOWN_EVAL_EN (1 << 1)
3644 #define MEMINT_SW_CMD_EN (1 << 0)
3645 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
3646 #define MEM_RSEXIT_MASK 0xc000
3647 #define MEM_RSEXIT_SHIFT 14
3648 #define MEM_CONT_BUSY_MASK 0x3000
3649 #define MEM_CONT_BUSY_SHIFT 12
3650 #define MEM_AVG_BUSY_MASK 0x0c00
3651 #define MEM_AVG_BUSY_SHIFT 10
3652 #define MEM_EVAL_CHG_MASK 0x0300
3653 #define MEM_EVAL_BUSY_SHIFT 8
3654 #define MEM_MON_IDLE_MASK 0x00c0
3655 #define MEM_MON_IDLE_SHIFT 6
3656 #define MEM_UP_EVAL_MASK 0x0030
3657 #define MEM_UP_EVAL_SHIFT 4
3658 #define MEM_DOWN_EVAL_MASK 0x000c
3659 #define MEM_DOWN_EVAL_SHIFT 2
3660 #define MEM_SW_CMD_MASK 0x0003
3661 #define MEM_INT_STEER_GFX 0
3662 #define MEM_INT_STEER_CMR 1
3663 #define MEM_INT_STEER_SMI 2
3664 #define MEM_INT_STEER_SCI 3
3665 #define MEMINTRSTS _MMIO(0x11184)
3666 #define MEMINT_RSEXIT (1 << 7)
3667 #define MEMINT_CONT_BUSY (1 << 6)
3668 #define MEMINT_AVG_BUSY (1 << 5)
3669 #define MEMINT_EVAL_CHG (1 << 4)
3670 #define MEMINT_MON_IDLE (1 << 3)
3671 #define MEMINT_UP_EVAL (1 << 2)
3672 #define MEMINT_DOWN_EVAL (1 << 1)
3673 #define MEMINT_SW_CMD (1 << 0)
3674 #define MEMMODECTL _MMIO(0x11190)
3675 #define MEMMODE_BOOST_EN (1 << 31)
3676 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3677 #define MEMMODE_BOOST_FREQ_SHIFT 24
3678 #define MEMMODE_IDLE_MODE_MASK 0x00030000
3679 #define MEMMODE_IDLE_MODE_SHIFT 16
3680 #define MEMMODE_IDLE_MODE_EVAL 0
3681 #define MEMMODE_IDLE_MODE_CONT 1
3682 #define MEMMODE_HWIDLE_EN (1 << 15)
3683 #define MEMMODE_SWMODE_EN (1 << 14)
3684 #define MEMMODE_RCLK_GATE (1 << 13)
3685 #define MEMMODE_HW_UPDATE (1 << 12)
3686 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3687 #define MEMMODE_FSTART_SHIFT 8
3688 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3689 #define MEMMODE_FMAX_SHIFT 4
3690 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
3691 #define RCBMAXAVG _MMIO(0x1119c)
3692 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
3693 #define SWMEMCMD_RENDER_OFF (0 << 13)
3694 #define SWMEMCMD_RENDER_ON (1 << 13)
3695 #define SWMEMCMD_SWFREQ (2 << 13)
3696 #define SWMEMCMD_TARVID (3 << 13)
3697 #define SWMEMCMD_VRM_OFF (4 << 13)
3698 #define SWMEMCMD_VRM_ON (5 << 13)
3699 #define CMDSTS (1 << 12)
3700 #define SFCAVM (1 << 11)
3701 #define SWFREQ_MASK 0x0380 /* P0-7 */
3702 #define SWFREQ_SHIFT 7
3703 #define TARVID_MASK 0x001f
3704 #define MEMSTAT_CTG _MMIO(0x111a0)
3705 #define RCBMINAVG _MMIO(0x111a0)
3706 #define RCUPEI _MMIO(0x111b0)
3707 #define RCDNEI _MMIO(0x111b4)
3708 #define RSTDBYCTL _MMIO(0x111b8)
3709 #define RS1EN (1 << 31)
3710 #define RS2EN (1 << 30)
3711 #define RS3EN (1 << 29)
3712 #define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */
3713 #define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */
3714 #define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */
3715 #define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */
3716 #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */
3717 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
3718 #define RSX_STATUS_MASK (7 << 20)
3719 #define RSX_STATUS_ON (0 << 20)
3720 #define RSX_STATUS_RC1 (1 << 20)
3721 #define RSX_STATUS_RC1E (2 << 20)
3722 #define RSX_STATUS_RS1 (3 << 20)
3723 #define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */
3724 #define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */
3725 #define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */
3726 #define RSX_STATUS_RSVD2 (7 << 20)
3727 #define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */
3728 #define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */
3729 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */
3730 #define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */
3731 #define RS1CONTSAV_MASK (3 << 14)
3732 #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */
3733 #define RS1CONTSAV_RSVD (1 << 14)
3734 #define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */
3735 #define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */
3736 #define NORMSLEXLAT_MASK (3 << 12)
3737 #define SLOW_RS123 (0 << 12)
3738 #define SLOW_RS23 (1 << 12)
3739 #define SLOW_RS3 (2 << 12)
3740 #define NORMAL_RS123 (3 << 12)
3741 #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */
3742 #define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3743 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3744 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
3745 #define RS_CSTATE_MASK (3 << 4)
3746 #define RS_CSTATE_C367_RS1 (0 << 4)
3747 #define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
3748 #define RS_CSTATE_RSVD (2 << 4)
3749 #define RS_CSTATE_C367_RS2 (3 << 4)
3750 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
3751 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
3752 #define VIDCTL _MMIO(0x111c0)
3753 #define VIDSTS _MMIO(0x111c8)
3754 #define VIDSTART _MMIO(0x111cc) /* 8 bits */
3755 #define MEMSTAT_ILK _MMIO(0x111f8)
3756 #define MEMSTAT_VID_MASK 0x7f00
3757 #define MEMSTAT_VID_SHIFT 8
3758 #define MEMSTAT_PSTATE_MASK 0x00f8
3759 #define MEMSTAT_PSTATE_SHIFT 3
3760 #define MEMSTAT_MON_ACTV (1 << 2)
3761 #define MEMSTAT_SRC_CTL_MASK 0x0003
3762 #define MEMSTAT_SRC_CTL_CORE 0
3763 #define MEMSTAT_SRC_CTL_TRB 1
3764 #define MEMSTAT_SRC_CTL_THM 2
3765 #define MEMSTAT_SRC_CTL_STDBY 3
3766 #define RCPREVBSYTUPAVG _MMIO(0x113b8)
3767 #define RCPREVBSYTDNAVG _MMIO(0x113bc)
3768 #define PMMISC _MMIO(0x11214)
3769 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
3770 #define SDEW _MMIO(0x1124c)
3771 #define CSIEW0 _MMIO(0x11250)
3772 #define CSIEW1 _MMIO(0x11254)
3773 #define CSIEW2 _MMIO(0x11258)
3774 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
3775 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
3776 #define MCHAFE _MMIO(0x112c0)
3777 #define CSIEC _MMIO(0x112e0)
3778 #define DMIEC _MMIO(0x112e4)
3779 #define DDREC _MMIO(0x112e8)
3780 #define PEG0EC _MMIO(0x112ec)
3781 #define PEG1EC _MMIO(0x112f0)
3782 #define GFXEC _MMIO(0x112f4)
3783 #define RPPREVBSYTUPAVG _MMIO(0x113b8)
3784 #define RPPREVBSYTDNAVG _MMIO(0x113bc)
3785 #define ECR _MMIO(0x11600)
3786 #define ECR_GPFE (1 << 31)
3787 #define ECR_IMONE (1 << 30)
3788 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
3789 #define OGW0 _MMIO(0x11608)
3790 #define OGW1 _MMIO(0x1160c)
3791 #define EG0 _MMIO(0x11610)
3792 #define EG1 _MMIO(0x11614)
3793 #define EG2 _MMIO(0x11618)
3794 #define EG3 _MMIO(0x1161c)
3795 #define EG4 _MMIO(0x11620)
3796 #define EG5 _MMIO(0x11624)
3797 #define EG6 _MMIO(0x11628)
3798 #define EG7 _MMIO(0x1162c)
3799 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
3800 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
3801 #define LCFUSE02 _MMIO(0x116c0)
3802 #define LCFUSE_HIV_MASK 0x000000ff
3803 #define CSIPLL0 _MMIO(0x12c10)
3804 #define DDRMPLL1 _MMIO(0X12c20)
3805 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
3807 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3808 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
3810 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3811 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3812 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3813 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3814 #define BXT_RP_STATE_CAP _MMIO(0x138170)
3817 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3818 * 8300) freezing up around GPU hangs. Looks as if even
3819 * scheduling/timer interrupts start misbehaving if the RPS
3820 * EI/thresholds are "bad", leading to a very sluggish or even
3823 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
3824 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
3825 #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
3826 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3827 (IS_GEN9_LP(dev_priv) ? \
3828 INTERVAL_0_833_US(us) : \
3829 INTERVAL_1_33_US(us)) : \
3830 INTERVAL_1_28_US(us))
3832 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3833 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3834 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
3835 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3836 (IS_GEN9_LP(dev_priv) ? \
3837 INTERVAL_0_833_TO_US(interval) : \
3838 INTERVAL_1_33_TO_US(interval)) : \
3839 INTERVAL_1_28_TO_US(interval))
3842 * Logical Context regs
3844 #define CCID _MMIO(0x2180)
3845 #define CCID_EN BIT(0)
3846 #define CCID_EXTENDED_STATE_RESTORE BIT(2)
3847 #define CCID_EXTENDED_STATE_SAVE BIT(3)
3849 * Notes on SNB/IVB/VLV context size:
3850 * - Power context is saved elsewhere (LLC or stolen)
3851 * - Ring/execlist context is saved on SNB, not on IVB
3852 * - Extended context size already includes render context size
3853 * - We always need to follow the extended context size.
3854 * SNB BSpec has comments indicating that we should use the
3855 * render context size instead if execlists are disabled, but
3856 * based on empirical testing that's just nonsense.
3857 * - Pipelined/VF state is saved on SNB/IVB respectively
3858 * - GT1 size just indicates how much of render context
3859 * doesn't need saving on GT1
3861 #define CXT_SIZE _MMIO(0x21a0)
3862 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
3863 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
3864 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
3865 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3866 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
3867 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
3868 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3869 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
3870 #define GEN7_CXT_SIZE _MMIO(0x21a8)
3871 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
3872 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
3873 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
3874 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3875 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
3876 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
3877 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3878 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
3881 INTEL_ADVANCED_CONTEXT = 0,
3882 INTEL_LEGACY_32B_CONTEXT,
3883 INTEL_ADVANCED_AD_CONTEXT,
3884 INTEL_LEGACY_64B_CONTEXT
3889 FAULT_AND_HALT, /* Debug only */
3891 FAULT_AND_CONTINUE /* Unsupported */
3894 #define GEN8_CTX_VALID (1 << 0)
3895 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
3896 #define GEN8_CTX_FORCE_RESTORE (1 << 2)
3897 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
3898 #define GEN8_CTX_PRIVILEGE (1 << 8)
3899 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
3901 #define GEN8_CTX_ID_SHIFT 32
3902 #define GEN8_CTX_ID_WIDTH 21
3903 #define GEN11_SW_CTX_ID_SHIFT 37
3904 #define GEN11_SW_CTX_ID_WIDTH 11
3905 #define GEN11_ENGINE_CLASS_SHIFT 61
3906 #define GEN11_ENGINE_CLASS_WIDTH 3
3907 #define GEN11_ENGINE_INSTANCE_SHIFT 48
3908 #define GEN11_ENGINE_INSTANCE_WIDTH 6
3910 #define CHV_CLK_CTL1 _MMIO(0x101100)
3911 #define VLV_CLK_CTL2 _MMIO(0x101104)
3912 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
3918 #define OVADD _MMIO(0x30000)
3919 #define DOVSTA _MMIO(0x30008)
3920 #define OC_BUF (0x3 << 20)
3921 #define OGAMC5 _MMIO(0x30010)
3922 #define OGAMC4 _MMIO(0x30014)
3923 #define OGAMC3 _MMIO(0x30018)
3924 #define OGAMC2 _MMIO(0x3001c)
3925 #define OGAMC1 _MMIO(0x30020)
3926 #define OGAMC0 _MMIO(0x30024)
3929 * GEN9 clock gating regs
3931 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
3932 #define DARBF_GATING_DIS (1 << 27)
3933 #define PWM2_GATING_DIS (1 << 14)
3934 #define PWM1_GATING_DIS (1 << 13)
3936 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
3937 #define BXT_GMBUS_GATING_DIS (1 << 14)
3939 #define _CLKGATE_DIS_PSL_A 0x46520
3940 #define _CLKGATE_DIS_PSL_B 0x46524
3941 #define _CLKGATE_DIS_PSL_C 0x46528
3942 #define DUPS1_GATING_DIS (1 << 15)
3943 #define DUPS2_GATING_DIS (1 << 19)
3944 #define DUPS3_GATING_DIS (1 << 23)
3945 #define DPF_GATING_DIS (1 << 10)
3946 #define DPF_RAM_GATING_DIS (1 << 9)
3947 #define DPFR_GATING_DIS (1 << 8)
3949 #define CLKGATE_DIS_PSL(pipe) \
3950 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
3953 * GEN10 clock gating regs
3955 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
3956 #define SARBUNIT_CLKGATE_DIS (1 << 5)
3957 #define RCCUNIT_CLKGATE_DIS (1 << 7)
3958 #define MSCUNIT_CLKGATE_DIS (1 << 10)
3960 #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
3961 #define GWUNIT_CLKGATE_DIS (1 << 16)
3963 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
3964 #define VFUNIT_CLKGATE_DIS (1 << 20)
3966 #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
3967 #define CGPSF_CLKGATE_DIS (1 << 3)
3970 * Display engine regs
3973 /* Pipe A CRC regs */
3974 #define _PIPE_CRC_CTL_A 0x60050
3975 #define PIPE_CRC_ENABLE (1 << 31)
3976 /* ivb+ source selection */
3977 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
3978 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
3979 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
3980 /* ilk+ source selection */
3981 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
3982 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
3983 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
3984 /* embedded DP port on the north display block, reserved on ivb */
3985 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
3986 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
3987 /* vlv source selection */
3988 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
3989 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
3990 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
3991 /* with DP port the pipe source is invalid */
3992 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
3993 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
3994 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
3995 /* gen3+ source selection */
3996 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
3997 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
3998 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
3999 /* with DP/TV port the pipe source is invalid */
4000 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
4001 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
4002 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
4003 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
4004 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
4005 /* gen2 doesn't have source selection bits */
4006 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
4008 #define _PIPE_CRC_RES_1_A_IVB 0x60064
4009 #define _PIPE_CRC_RES_2_A_IVB 0x60068
4010 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
4011 #define _PIPE_CRC_RES_4_A_IVB 0x60070
4012 #define _PIPE_CRC_RES_5_A_IVB 0x60074
4014 #define _PIPE_CRC_RES_RED_A 0x60060
4015 #define _PIPE_CRC_RES_GREEN_A 0x60064
4016 #define _PIPE_CRC_RES_BLUE_A 0x60068
4017 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
4018 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
4020 /* Pipe B CRC regs */
4021 #define _PIPE_CRC_RES_1_B_IVB 0x61064
4022 #define _PIPE_CRC_RES_2_B_IVB 0x61068
4023 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
4024 #define _PIPE_CRC_RES_4_B_IVB 0x61070
4025 #define _PIPE_CRC_RES_5_B_IVB 0x61074
4027 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4028 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4029 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4030 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4031 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4032 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4034 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4035 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4036 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4037 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4038 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4040 /* Pipe A timing regs */
4041 #define _HTOTAL_A 0x60000
4042 #define _HBLANK_A 0x60004
4043 #define _HSYNC_A 0x60008
4044 #define _VTOTAL_A 0x6000c
4045 #define _VBLANK_A 0x60010
4046 #define _VSYNC_A 0x60014
4047 #define _PIPEASRC 0x6001c
4048 #define _BCLRPAT_A 0x60020
4049 #define _VSYNCSHIFT_A 0x60028
4050 #define _PIPE_MULT_A 0x6002c
4052 /* Pipe B timing regs */
4053 #define _HTOTAL_B 0x61000
4054 #define _HBLANK_B 0x61004
4055 #define _HSYNC_B 0x61008
4056 #define _VTOTAL_B 0x6100c
4057 #define _VBLANK_B 0x61010
4058 #define _VSYNC_B 0x61014
4059 #define _PIPEBSRC 0x6101c
4060 #define _BCLRPAT_B 0x61020
4061 #define _VSYNCSHIFT_B 0x61028
4062 #define _PIPE_MULT_B 0x6102c
4064 #define TRANSCODER_A_OFFSET 0x60000
4065 #define TRANSCODER_B_OFFSET 0x61000
4066 #define TRANSCODER_C_OFFSET 0x62000
4067 #define CHV_TRANSCODER_C_OFFSET 0x63000
4068 #define TRANSCODER_EDP_OFFSET 0x6f000
4070 #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
4071 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
4072 dev_priv->info.display_mmio_offset)
4074 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4075 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4076 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4077 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4078 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4079 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4080 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4081 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4082 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4083 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4085 /* VLV eDP PSR registers */
4086 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
4087 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
4088 #define VLV_EDP_PSR_ENABLE (1 << 0)
4089 #define VLV_EDP_PSR_RESET (1 << 1)
4090 #define VLV_EDP_PSR_MODE_MASK (7 << 2)
4091 #define VLV_EDP_PSR_MODE_HW_TIMER (1 << 3)
4092 #define VLV_EDP_PSR_MODE_SW_TIMER (1 << 2)
4093 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1 << 7)
4094 #define VLV_EDP_PSR_ACTIVE_ENTRY (1 << 8)
4095 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1 << 9)
4096 #define VLV_EDP_PSR_DBL_FRAME (1 << 10)
4097 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff << 16)
4098 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
4099 #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
4101 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
4102 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
4103 #define VLV_EDP_PSR_SDP_FREQ_MASK (3 << 30)
4104 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1 << 31)
4105 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1 << 30)
4106 #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
4108 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
4109 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
4110 #define VLV_EDP_PSR_LAST_STATE_MASK (7 << 3)
4111 #define VLV_EDP_PSR_CURR_STATE_MASK 7
4112 #define VLV_EDP_PSR_DISABLED (0 << 0)
4113 #define VLV_EDP_PSR_INACTIVE (1 << 0)
4114 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2 << 0)
4115 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3 << 0)
4116 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4 << 0)
4117 #define VLV_EDP_PSR_EXIT (5 << 0)
4118 #define VLV_EDP_PSR_IN_TRANS (1 << 7)
4119 #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
4121 /* HSW+ eDP PSR registers */
4122 #define HSW_EDP_PSR_BASE 0x64800
4123 #define BDW_EDP_PSR_BASE 0x6f800
4124 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
4125 #define EDP_PSR_ENABLE (1 << 31)
4126 #define BDW_PSR_SINGLE_FRAME (1 << 30)
4127 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
4128 #define EDP_PSR_LINK_STANDBY (1 << 27)
4129 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
4130 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
4131 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
4132 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
4133 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
4134 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4135 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
4136 #define EDP_PSR_TP1_TP2_SEL (0 << 11)
4137 #define EDP_PSR_TP1_TP3_SEL (1 << 11)
4138 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */
4139 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
4140 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
4141 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
4142 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
4143 #define EDP_PSR_TP1_TIME_500us (0 << 4)
4144 #define EDP_PSR_TP1_TIME_100us (1 << 4)
4145 #define EDP_PSR_TP1_TIME_2500us (2 << 4)
4146 #define EDP_PSR_TP1_TIME_0us (3 << 4)
4147 #define EDP_PSR_IDLE_FRAME_SHIFT 0
4149 /* Bspec claims those aren't shifted but stay at 0x64800 */
4150 #define EDP_PSR_IMR _MMIO(0x64834)
4151 #define EDP_PSR_IIR _MMIO(0x64838)
4152 #define EDP_PSR_ERROR(trans) (1 << (((trans) * 8 + 10) & 31))
4153 #define EDP_PSR_POST_EXIT(trans) (1 << (((trans) * 8 + 9) & 31))
4154 #define EDP_PSR_PRE_ENTRY(trans) (1 << (((trans) * 8 + 8) & 31))
4156 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4157 #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
4158 #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4159 #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
4160 #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
4161 #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4163 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
4165 #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
4166 #define EDP_PSR_STATUS_STATE_MASK (7 << 29)
4167 #define EDP_PSR_STATUS_STATE_SHIFT 29
4168 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
4169 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
4170 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
4171 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
4172 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
4173 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
4174 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
4175 #define EDP_PSR_STATUS_LINK_MASK (3 << 26)
4176 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
4177 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
4178 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
4179 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4180 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4181 #define EDP_PSR_STATUS_COUNT_SHIFT 16
4182 #define EDP_PSR_STATUS_COUNT_MASK 0xf
4183 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
4184 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
4185 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
4186 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
4187 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
4188 #define EDP_PSR_STATUS_IDLE_MASK 0xf
4190 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
4191 #define EDP_PSR_PERF_CNT_MASK 0xffffff
4193 #define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
4194 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
4195 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
4196 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
4197 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
4198 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
4199 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4201 #define EDP_PSR2_CTL _MMIO(0x6f900)
4202 #define EDP_PSR2_ENABLE (1 << 31)
4203 #define EDP_SU_TRACK_ENABLE (1 << 30)
4204 #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
4205 #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */
4206 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
4207 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
4208 #define EDP_PSR2_TP2_TIME_500us (0 << 8)
4209 #define EDP_PSR2_TP2_TIME_100us (1 << 8)
4210 #define EDP_PSR2_TP2_TIME_2500us (2 << 8)
4211 #define EDP_PSR2_TP2_TIME_50us (3 << 8)
4212 #define EDP_PSR2_TP2_TIME_MASK (3 << 8)
4213 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4214 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4215 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
4216 #define EDP_PSR2_IDLE_FRAME_MASK 0xf
4217 #define EDP_PSR2_IDLE_FRAME_SHIFT 0
4219 #define _PSR_EVENT_TRANS_A 0x60848
4220 #define _PSR_EVENT_TRANS_B 0x61848
4221 #define _PSR_EVENT_TRANS_C 0x62848
4222 #define _PSR_EVENT_TRANS_D 0x63848
4223 #define _PSR_EVENT_TRANS_EDP 0x6F848
4224 #define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
4225 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
4226 #define PSR_EVENT_PSR2_DISABLED (1 << 16)
4227 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
4228 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
4229 #define PSR_EVENT_GRAPHICS_RESET (1 << 12)
4230 #define PSR_EVENT_PCH_INTERRUPT (1 << 11)
4231 #define PSR_EVENT_MEMORY_UP (1 << 10)
4232 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
4233 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
4234 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
4235 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
4236 #define PSR_EVENT_HDCP_ENABLE (1 << 4)
4237 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
4238 #define PSR_EVENT_VBI_ENABLE (1 << 2)
4239 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
4240 #define PSR_EVENT_PSR_DISABLE (1 << 0)
4242 #define EDP_PSR2_STATUS _MMIO(0x6f940)
4243 #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
4244 #define EDP_PSR2_STATUS_STATE_SHIFT 28
4246 /* VGA port control */
4247 #define ADPA _MMIO(0x61100)
4248 #define PCH_ADPA _MMIO(0xe1100)
4249 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4251 #define ADPA_DAC_ENABLE (1 << 31)
4252 #define ADPA_DAC_DISABLE 0
4253 #define ADPA_PIPE_SEL_SHIFT 30
4254 #define ADPA_PIPE_SEL_MASK (1 << 30)
4255 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
4256 #define ADPA_PIPE_SEL_SHIFT_CPT 29
4257 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
4258 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4259 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4260 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
4261 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
4262 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4263 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
4264 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
4265 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
4266 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
4267 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
4268 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
4269 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
4270 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
4271 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
4272 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
4273 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
4274 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
4275 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
4276 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
4277 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4278 #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
4279 #define ADPA_SETS_HVPOLARITY 0
4280 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4281 #define ADPA_VSYNC_CNTL_ENABLE 0
4282 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4283 #define ADPA_HSYNC_CNTL_ENABLE 0
4284 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4285 #define ADPA_VSYNC_ACTIVE_LOW 0
4286 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4287 #define ADPA_HSYNC_ACTIVE_LOW 0
4288 #define ADPA_DPMS_MASK (~(3 << 10))
4289 #define ADPA_DPMS_ON (0 << 10)
4290 #define ADPA_DPMS_SUSPEND (1 << 10)
4291 #define ADPA_DPMS_STANDBY (2 << 10)
4292 #define ADPA_DPMS_OFF (3 << 10)
4295 /* Hotplug control (945+ only) */
4296 #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
4297 #define PORTB_HOTPLUG_INT_EN (1 << 29)
4298 #define PORTC_HOTPLUG_INT_EN (1 << 28)
4299 #define PORTD_HOTPLUG_INT_EN (1 << 27)
4300 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
4301 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
4302 #define TV_HOTPLUG_INT_EN (1 << 18)
4303 #define CRT_HOTPLUG_INT_EN (1 << 9)
4304 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4305 PORTC_HOTPLUG_INT_EN | \
4306 PORTD_HOTPLUG_INT_EN | \
4307 SDVOC_HOTPLUG_INT_EN | \
4308 SDVOB_HOTPLUG_INT_EN | \
4310 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
4311 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
4312 /* must use period 64 on GM45 according to docs */
4313 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
4314 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
4315 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
4316 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
4317 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
4318 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
4319 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
4320 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
4321 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
4322 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
4323 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4324 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
4326 #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
4328 * HDMI/DP bits are g4x+
4330 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4331 * Please check the detailed lore in the commit message for for experimental
4334 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4335 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
4336 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
4337 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
4338 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4339 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
4340 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
4341 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
4342 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
4343 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
4344 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
4345 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
4346 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
4347 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
4348 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
4349 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
4350 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
4351 /* CRT/TV common between gen3+ */
4352 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
4353 #define TV_HOTPLUG_INT_STATUS (1 << 10)
4354 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
4355 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
4356 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
4357 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
4358 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
4359 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
4360 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
4361 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
4363 /* SDVO is different across gen3/4 */
4364 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
4365 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
4367 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4368 * since reality corrobates that they're the same as on gen3. But keep these
4369 * bits here (and the comment!) to help any other lost wanderers back onto the
4372 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
4373 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
4374 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
4375 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
4376 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
4377 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4378 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4379 PORTB_HOTPLUG_INT_STATUS | \
4380 PORTC_HOTPLUG_INT_STATUS | \
4381 PORTD_HOTPLUG_INT_STATUS)
4383 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
4384 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4385 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4386 PORTB_HOTPLUG_INT_STATUS | \
4387 PORTC_HOTPLUG_INT_STATUS | \
4388 PORTD_HOTPLUG_INT_STATUS)
4390 /* SDVO and HDMI port control.
4391 * The same register may be used for SDVO or HDMI */
4392 #define _GEN3_SDVOB 0x61140
4393 #define _GEN3_SDVOC 0x61160
4394 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
4395 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
4396 #define GEN4_HDMIB GEN3_SDVOB
4397 #define GEN4_HDMIC GEN3_SDVOC
4398 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4399 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4400 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4401 #define PCH_SDVOB _MMIO(0xe1140)
4402 #define PCH_HDMIB PCH_SDVOB
4403 #define PCH_HDMIC _MMIO(0xe1150)
4404 #define PCH_HDMID _MMIO(0xe1160)
4406 #define PORT_DFT_I9XX _MMIO(0x61150)
4407 #define DC_BALANCE_RESET (1 << 25)
4408 #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
4409 #define DC_BALANCE_RESET_VLV (1 << 31)
4410 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
4411 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
4412 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
4413 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
4415 /* Gen 3 SDVO bits: */
4416 #define SDVO_ENABLE (1 << 31)
4417 #define SDVO_PIPE_SEL_SHIFT 30
4418 #define SDVO_PIPE_SEL_MASK (1 << 30)
4419 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
4420 #define SDVO_STALL_SELECT (1 << 29)
4421 #define SDVO_INTERRUPT_ENABLE (1 << 26)
4423 * 915G/GM SDVO pixel multiplier.
4424 * Programmed value is multiplier - 1, up to 5x.
4425 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4427 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
4428 #define SDVO_PORT_MULTIPLY_SHIFT 23
4429 #define SDVO_PHASE_SELECT_MASK (15 << 19)
4430 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
4431 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
4432 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
4433 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
4434 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
4435 #define SDVO_DETECTED (1 << 2)
4436 /* Bits to be preserved when writing */
4437 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4438 SDVO_INTERRUPT_ENABLE)
4439 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4441 /* Gen 4 SDVO/HDMI bits: */
4442 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
4443 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
4444 #define SDVO_ENCODING_SDVO (0 << 10)
4445 #define SDVO_ENCODING_HDMI (2 << 10)
4446 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
4447 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
4448 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
4449 #define SDVO_AUDIO_ENABLE (1 << 6)
4450 /* VSYNC/HSYNC bits new with 965, default is to be set */
4451 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4452 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
4454 /* Gen 5 (IBX) SDVO/HDMI bits: */
4455 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
4456 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
4458 /* Gen 6 (CPT) SDVO/HDMI bits: */
4459 #define SDVO_PIPE_SEL_SHIFT_CPT 29
4460 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
4461 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4463 /* CHV SDVO/HDMI bits: */
4464 #define SDVO_PIPE_SEL_SHIFT_CHV 24
4465 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
4466 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
4469 /* DVO port control */
4470 #define _DVOA 0x61120
4471 #define DVOA _MMIO(_DVOA)
4472 #define _DVOB 0x61140
4473 #define DVOB _MMIO(_DVOB)
4474 #define _DVOC 0x61160
4475 #define DVOC _MMIO(_DVOC)
4476 #define DVO_ENABLE (1 << 31)
4477 #define DVO_PIPE_SEL_SHIFT 30
4478 #define DVO_PIPE_SEL_MASK (1 << 30)
4479 #define DVO_PIPE_SEL(pipe) ((pipe) << 30)
4480 #define DVO_PIPE_STALL_UNUSED (0 << 28)
4481 #define DVO_PIPE_STALL (1 << 28)
4482 #define DVO_PIPE_STALL_TV (2 << 28)
4483 #define DVO_PIPE_STALL_MASK (3 << 28)
4484 #define DVO_USE_VGA_SYNC (1 << 15)
4485 #define DVO_DATA_ORDER_I740 (0 << 14)
4486 #define DVO_DATA_ORDER_FP (1 << 14)
4487 #define DVO_VSYNC_DISABLE (1 << 11)
4488 #define DVO_HSYNC_DISABLE (1 << 10)
4489 #define DVO_VSYNC_TRISTATE (1 << 9)
4490 #define DVO_HSYNC_TRISTATE (1 << 8)
4491 #define DVO_BORDER_ENABLE (1 << 7)
4492 #define DVO_DATA_ORDER_GBRG (1 << 6)
4493 #define DVO_DATA_ORDER_RGGB (0 << 6)
4494 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
4495 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
4496 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
4497 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
4498 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
4499 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
4500 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
4501 #define DVO_PRESERVE_MASK (0x7 << 24)
4502 #define DVOA_SRCDIM _MMIO(0x61124)
4503 #define DVOB_SRCDIM _MMIO(0x61144)
4504 #define DVOC_SRCDIM _MMIO(0x61164)
4505 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
4506 #define DVO_SRCDIM_VERTICAL_SHIFT 0
4508 /* LVDS port control */
4509 #define LVDS _MMIO(0x61180)
4511 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4512 * the DPLL semantics change when the LVDS is assigned to that pipe.
4514 #define LVDS_PORT_EN (1 << 31)
4515 /* Selects pipe B for LVDS data. Must be set on pre-965. */
4516 #define LVDS_PIPE_SEL_SHIFT 30
4517 #define LVDS_PIPE_SEL_MASK (1 << 30)
4518 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
4519 #define LVDS_PIPE_SEL_SHIFT_CPT 29
4520 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
4521 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4522 /* LVDS dithering flag on 965/g4x platform */
4523 #define LVDS_ENABLE_DITHER (1 << 25)
4524 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4525 #define LVDS_VSYNC_POLARITY (1 << 21)
4526 #define LVDS_HSYNC_POLARITY (1 << 20)
4528 /* Enable border for unscaled (or aspect-scaled) display */
4529 #define LVDS_BORDER_ENABLE (1 << 15)
4531 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4534 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
4535 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
4536 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
4538 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4539 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4542 #define LVDS_A3_POWER_MASK (3 << 6)
4543 #define LVDS_A3_POWER_DOWN (0 << 6)
4544 #define LVDS_A3_POWER_UP (3 << 6)
4546 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
4549 #define LVDS_CLKB_POWER_MASK (3 << 4)
4550 #define LVDS_CLKB_POWER_DOWN (0 << 4)
4551 #define LVDS_CLKB_POWER_UP (3 << 4)
4553 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
4554 * setting for whether we are in dual-channel mode. The B3 pair will
4555 * additionally only be powered up when LVDS_A3_POWER_UP is set.
4557 #define LVDS_B0B3_POWER_MASK (3 << 2)
4558 #define LVDS_B0B3_POWER_DOWN (0 << 2)
4559 #define LVDS_B0B3_POWER_UP (3 << 2)
4561 /* Video Data Island Packet control */
4562 #define VIDEO_DIP_DATA _MMIO(0x61178)
4563 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4564 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4565 * of the infoframe structure specified by CEA-861. */
4566 #define VIDEO_DIP_DATA_SIZE 32
4567 #define VIDEO_DIP_VSC_DATA_SIZE 36
4568 #define VIDEO_DIP_CTL _MMIO(0x61170)
4570 #define VIDEO_DIP_ENABLE (1 << 31)
4571 #define VIDEO_DIP_PORT(port) ((port) << 29)
4572 #define VIDEO_DIP_PORT_MASK (3 << 29)
4573 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
4574 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
4575 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
4576 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
4577 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
4578 #define VIDEO_DIP_SELECT_AVI (0 << 19)
4579 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
4580 #define VIDEO_DIP_SELECT_SPD (3 << 19)
4581 #define VIDEO_DIP_SELECT_MASK (3 << 19)
4582 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
4583 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
4584 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
4585 #define VIDEO_DIP_FREQ_MASK (3 << 16)
4586 /* HSW and later: */
4587 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4588 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
4589 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
4590 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
4591 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
4592 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
4594 #define DRM_DIP_ENABLE (1 << 28)
4595 #define PSR_VSC_BIT_7_SET (1 << 27)
4596 #define VSC_SELECT_MASK (0x3 << 26)
4597 #define VSC_SELECT_SHIFT 26
4598 #define VSC_DIP_HW_HEA_DATA (0 << 26)
4599 #define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
4600 #define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
4601 #define VSC_DIP_SW_HEA_DATA (3 << 26)
4602 #define VDIP_ENABLE_PPS (1 << 24)
4604 /* Panel power sequencing */
4605 #define PPS_BASE 0x61200
4606 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
4607 #define PCH_PPS_BASE 0xC7200
4609 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
4610 PPS_BASE + (reg) + \
4613 #define _PP_STATUS 0x61200
4614 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
4615 #define PP_ON (1 << 31)
4617 * Indicates that all dependencies of the panel are on:
4621 * - LVDS/DVOB/DVOC on
4623 #define PP_READY (1 << 30)
4624 #define PP_SEQUENCE_NONE (0 << 28)
4625 #define PP_SEQUENCE_POWER_UP (1 << 28)
4626 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
4627 #define PP_SEQUENCE_MASK (3 << 28)
4628 #define PP_SEQUENCE_SHIFT 28
4629 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
4630 #define PP_SEQUENCE_STATE_MASK 0x0000000f
4631 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
4632 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
4633 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
4634 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
4635 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
4636 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
4637 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
4638 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
4639 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
4641 #define _PP_CONTROL 0x61204
4642 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
4643 #define PANEL_UNLOCK_REGS (0xabcd << 16)
4644 #define PANEL_UNLOCK_MASK (0xffff << 16)
4645 #define BXT_POWER_CYCLE_DELAY_MASK 0x1f0
4646 #define BXT_POWER_CYCLE_DELAY_SHIFT 4
4647 #define EDP_FORCE_VDD (1 << 3)
4648 #define EDP_BLC_ENABLE (1 << 2)
4649 #define PANEL_POWER_RESET (1 << 1)
4650 #define PANEL_POWER_OFF (0 << 0)
4651 #define PANEL_POWER_ON (1 << 0)
4653 #define _PP_ON_DELAYS 0x61208
4654 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4655 #define PANEL_PORT_SELECT_SHIFT 30
4656 #define PANEL_PORT_SELECT_MASK (3 << 30)
4657 #define PANEL_PORT_SELECT_LVDS (0 << 30)
4658 #define PANEL_PORT_SELECT_DPA (1 << 30)
4659 #define PANEL_PORT_SELECT_DPC (2 << 30)
4660 #define PANEL_PORT_SELECT_DPD (3 << 30)
4661 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
4662 #define PANEL_POWER_UP_DELAY_MASK 0x1fff0000
4663 #define PANEL_POWER_UP_DELAY_SHIFT 16
4664 #define PANEL_LIGHT_ON_DELAY_MASK 0x1fff
4665 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
4667 #define _PP_OFF_DELAYS 0x6120C
4668 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4669 #define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000
4670 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
4671 #define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff
4672 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4674 #define _PP_DIVISOR 0x61210
4675 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
4676 #define PP_REFERENCE_DIVIDER_MASK 0xffffff00
4677 #define PP_REFERENCE_DIVIDER_SHIFT 8
4678 #define PANEL_POWER_CYCLE_DELAY_MASK 0x1f
4679 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4682 #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
4683 #define PFIT_ENABLE (1 << 31)
4684 #define PFIT_PIPE_MASK (3 << 29)
4685 #define PFIT_PIPE_SHIFT 29
4686 #define VERT_INTERP_DISABLE (0 << 10)
4687 #define VERT_INTERP_BILINEAR (1 << 10)
4688 #define VERT_INTERP_MASK (3 << 10)
4689 #define VERT_AUTO_SCALE (1 << 9)
4690 #define HORIZ_INTERP_DISABLE (0 << 6)
4691 #define HORIZ_INTERP_BILINEAR (1 << 6)
4692 #define HORIZ_INTERP_MASK (3 << 6)
4693 #define HORIZ_AUTO_SCALE (1 << 5)
4694 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
4695 #define PFIT_FILTER_FUZZY (0 << 24)
4696 #define PFIT_SCALING_AUTO (0 << 26)
4697 #define PFIT_SCALING_PROGRAMMED (1 << 26)
4698 #define PFIT_SCALING_PILLAR (2 << 26)
4699 #define PFIT_SCALING_LETTER (3 << 26)
4700 #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
4702 #define PFIT_VERT_SCALE_SHIFT 20
4703 #define PFIT_VERT_SCALE_MASK 0xfff00000
4704 #define PFIT_HORIZ_SCALE_SHIFT 4
4705 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
4707 #define PFIT_VERT_SCALE_SHIFT_965 16
4708 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
4709 #define PFIT_HORIZ_SCALE_SHIFT_965 0
4710 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
4712 #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
4714 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
4715 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
4716 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4717 _VLV_BLC_PWM_CTL2_B)
4719 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
4720 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
4721 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4724 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
4725 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
4726 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4727 _VLV_BLC_HIST_CTL_B)
4729 /* Backlight control */
4730 #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
4731 #define BLM_PWM_ENABLE (1 << 31)
4732 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
4733 #define BLM_PIPE_SELECT (1 << 29)
4734 #define BLM_PIPE_SELECT_IVB (3 << 29)
4735 #define BLM_PIPE_A (0 << 29)
4736 #define BLM_PIPE_B (1 << 29)
4737 #define BLM_PIPE_C (2 << 29) /* ivb + */
4738 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
4739 #define BLM_TRANSCODER_B BLM_PIPE_B
4740 #define BLM_TRANSCODER_C BLM_PIPE_C
4741 #define BLM_TRANSCODER_EDP (3 << 29)
4742 #define BLM_PIPE(pipe) ((pipe) << 29)
4743 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
4744 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
4745 #define BLM_PHASE_IN_ENABLE (1 << 25)
4746 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
4747 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
4748 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
4749 #define BLM_PHASE_IN_COUNT_SHIFT (8)
4750 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
4751 #define BLM_PHASE_IN_INCR_SHIFT (0)
4752 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
4753 #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
4755 * This is the most significant 15 bits of the number of backlight cycles in a
4756 * complete cycle of the modulated backlight control.
4758 * The actual value is this field multiplied by two.
4760 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
4761 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
4762 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
4764 * This is the number of cycles out of the backlight modulation cycle for which
4765 * the backlight is on.
4767 * This field must be no greater than the number of cycles in the complete
4768 * backlight modulation cycle.
4770 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
4771 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
4772 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
4773 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
4775 #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
4776 #define BLM_HISTOGRAM_ENABLE (1 << 31)
4778 /* New registers for PCH-split platforms. Safe where new bits show up, the
4779 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
4780 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
4781 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
4783 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
4785 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
4786 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
4787 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
4788 #define BLM_PCH_PWM_ENABLE (1 << 31)
4789 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
4790 #define BLM_PCH_POLARITY (1 << 29)
4791 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
4793 #define UTIL_PIN_CTL _MMIO(0x48400)
4794 #define UTIL_PIN_ENABLE (1 << 31)
4796 #define UTIL_PIN_PIPE(x) ((x) << 29)
4797 #define UTIL_PIN_PIPE_MASK (3 << 29)
4798 #define UTIL_PIN_MODE_PWM (1 << 24)
4799 #define UTIL_PIN_MODE_MASK (0xf << 24)
4800 #define UTIL_PIN_POLARITY (1 << 22)
4802 /* BXT backlight register definition. */
4803 #define _BXT_BLC_PWM_CTL1 0xC8250
4804 #define BXT_BLC_PWM_ENABLE (1 << 31)
4805 #define BXT_BLC_PWM_POLARITY (1 << 29)
4806 #define _BXT_BLC_PWM_FREQ1 0xC8254
4807 #define _BXT_BLC_PWM_DUTY1 0xC8258
4809 #define _BXT_BLC_PWM_CTL2 0xC8350
4810 #define _BXT_BLC_PWM_FREQ2 0xC8354
4811 #define _BXT_BLC_PWM_DUTY2 0xC8358
4813 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
4814 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
4815 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
4816 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
4817 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
4818 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
4820 #define PCH_GTC_CTL _MMIO(0xe7000)
4821 #define PCH_GTC_ENABLE (1 << 31)
4823 /* TV port control */
4824 #define TV_CTL _MMIO(0x68000)
4825 /* Enables the TV encoder */
4826 # define TV_ENC_ENABLE (1 << 31)
4827 /* Sources the TV encoder input from pipe B instead of A. */
4828 # define TV_ENC_PIPE_SEL_SHIFT 30
4829 # define TV_ENC_PIPE_SEL_MASK (1 << 30)
4830 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
4831 /* Outputs composite video (DAC A only) */
4832 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
4833 /* Outputs SVideo video (DAC B/C) */
4834 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
4835 /* Outputs Component video (DAC A/B/C) */
4836 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
4837 /* Outputs Composite and SVideo (DAC A/B/C) */
4838 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
4839 # define TV_TRILEVEL_SYNC (1 << 21)
4840 /* Enables slow sync generation (945GM only) */
4841 # define TV_SLOW_SYNC (1 << 20)
4842 /* Selects 4x oversampling for 480i and 576p */
4843 # define TV_OVERSAMPLE_4X (0 << 18)
4844 /* Selects 2x oversampling for 720p and 1080i */
4845 # define TV_OVERSAMPLE_2X (1 << 18)
4846 /* Selects no oversampling for 1080p */
4847 # define TV_OVERSAMPLE_NONE (2 << 18)
4848 /* Selects 8x oversampling */
4849 # define TV_OVERSAMPLE_8X (3 << 18)
4850 /* Selects progressive mode rather than interlaced */
4851 # define TV_PROGRESSIVE (1 << 17)
4852 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
4853 # define TV_PAL_BURST (1 << 16)
4854 /* Field for setting delay of Y compared to C */
4855 # define TV_YC_SKEW_MASK (7 << 12)
4856 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
4857 # define TV_ENC_SDP_FIX (1 << 11)
4859 * Enables a fix for the 915GM only.
4861 * Not sure what it does.
4863 # define TV_ENC_C0_FIX (1 << 10)
4864 /* Bits that must be preserved by software */
4865 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
4866 # define TV_FUSE_STATE_MASK (3 << 4)
4867 /* Read-only state that reports all features enabled */
4868 # define TV_FUSE_STATE_ENABLED (0 << 4)
4869 /* Read-only state that reports that Macrovision is disabled in hardware*/
4870 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
4871 /* Read-only state that reports that TV-out is disabled in hardware. */
4872 # define TV_FUSE_STATE_DISABLED (2 << 4)
4873 /* Normal operation */
4874 # define TV_TEST_MODE_NORMAL (0 << 0)
4875 /* Encoder test pattern 1 - combo pattern */
4876 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
4877 /* Encoder test pattern 2 - full screen vertical 75% color bars */
4878 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
4879 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
4880 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
4881 /* Encoder test pattern 4 - random noise */
4882 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
4883 /* Encoder test pattern 5 - linear color ramps */
4884 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
4886 * This test mode forces the DACs to 50% of full output.
4888 * This is used for load detection in combination with TVDAC_SENSE_MASK
4890 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
4891 # define TV_TEST_MODE_MASK (7 << 0)
4893 #define TV_DAC _MMIO(0x68004)
4894 # define TV_DAC_SAVE 0x00ffff00
4896 * Reports that DAC state change logic has reported change (RO).
4898 * This gets cleared when TV_DAC_STATE_EN is cleared
4900 # define TVDAC_STATE_CHG (1 << 31)
4901 # define TVDAC_SENSE_MASK (7 << 28)
4902 /* Reports that DAC A voltage is above the detect threshold */
4903 # define TVDAC_A_SENSE (1 << 30)
4904 /* Reports that DAC B voltage is above the detect threshold */
4905 # define TVDAC_B_SENSE (1 << 29)
4906 /* Reports that DAC C voltage is above the detect threshold */
4907 # define TVDAC_C_SENSE (1 << 28)
4909 * Enables DAC state detection logic, for load-based TV detection.
4911 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
4912 * to off, for load detection to work.
4914 # define TVDAC_STATE_CHG_EN (1 << 27)
4915 /* Sets the DAC A sense value to high */
4916 # define TVDAC_A_SENSE_CTL (1 << 26)
4917 /* Sets the DAC B sense value to high */
4918 # define TVDAC_B_SENSE_CTL (1 << 25)
4919 /* Sets the DAC C sense value to high */
4920 # define TVDAC_C_SENSE_CTL (1 << 24)
4921 /* Overrides the ENC_ENABLE and DAC voltage levels */
4922 # define DAC_CTL_OVERRIDE (1 << 7)
4923 /* Sets the slew rate. Must be preserved in software */
4924 # define ENC_TVDAC_SLEW_FAST (1 << 6)
4925 # define DAC_A_1_3_V (0 << 4)
4926 # define DAC_A_1_1_V (1 << 4)
4927 # define DAC_A_0_7_V (2 << 4)
4928 # define DAC_A_MASK (3 << 4)
4929 # define DAC_B_1_3_V (0 << 2)
4930 # define DAC_B_1_1_V (1 << 2)
4931 # define DAC_B_0_7_V (2 << 2)
4932 # define DAC_B_MASK (3 << 2)
4933 # define DAC_C_1_3_V (0 << 0)
4934 # define DAC_C_1_1_V (1 << 0)
4935 # define DAC_C_0_7_V (2 << 0)
4936 # define DAC_C_MASK (3 << 0)
4939 * CSC coefficients are stored in a floating point format with 9 bits of
4940 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
4941 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
4942 * -1 (0x3) being the only legal negative value.
4944 #define TV_CSC_Y _MMIO(0x68010)
4945 # define TV_RY_MASK 0x07ff0000
4946 # define TV_RY_SHIFT 16
4947 # define TV_GY_MASK 0x00000fff
4948 # define TV_GY_SHIFT 0
4950 #define TV_CSC_Y2 _MMIO(0x68014)
4951 # define TV_BY_MASK 0x07ff0000
4952 # define TV_BY_SHIFT 16
4954 * Y attenuation for component video.
4956 * Stored in 1.9 fixed point.
4958 # define TV_AY_MASK 0x000003ff
4959 # define TV_AY_SHIFT 0
4961 #define TV_CSC_U _MMIO(0x68018)
4962 # define TV_RU_MASK 0x07ff0000
4963 # define TV_RU_SHIFT 16
4964 # define TV_GU_MASK 0x000007ff
4965 # define TV_GU_SHIFT 0
4967 #define TV_CSC_U2 _MMIO(0x6801c)
4968 # define TV_BU_MASK 0x07ff0000
4969 # define TV_BU_SHIFT 16
4971 * U attenuation for component video.
4973 * Stored in 1.9 fixed point.
4975 # define TV_AU_MASK 0x000003ff
4976 # define TV_AU_SHIFT 0
4978 #define TV_CSC_V _MMIO(0x68020)
4979 # define TV_RV_MASK 0x0fff0000
4980 # define TV_RV_SHIFT 16
4981 # define TV_GV_MASK 0x000007ff
4982 # define TV_GV_SHIFT 0
4984 #define TV_CSC_V2 _MMIO(0x68024)
4985 # define TV_BV_MASK 0x07ff0000
4986 # define TV_BV_SHIFT 16
4988 * V attenuation for component video.
4990 * Stored in 1.9 fixed point.
4992 # define TV_AV_MASK 0x000007ff
4993 # define TV_AV_SHIFT 0
4995 #define TV_CLR_KNOBS _MMIO(0x68028)
4996 /* 2s-complement brightness adjustment */
4997 # define TV_BRIGHTNESS_MASK 0xff000000
4998 # define TV_BRIGHTNESS_SHIFT 24
4999 /* Contrast adjustment, as a 2.6 unsigned floating point number */
5000 # define TV_CONTRAST_MASK 0x00ff0000
5001 # define TV_CONTRAST_SHIFT 16
5002 /* Saturation adjustment, as a 2.6 unsigned floating point number */
5003 # define TV_SATURATION_MASK 0x0000ff00
5004 # define TV_SATURATION_SHIFT 8
5005 /* Hue adjustment, as an integer phase angle in degrees */
5006 # define TV_HUE_MASK 0x000000ff
5007 # define TV_HUE_SHIFT 0
5009 #define TV_CLR_LEVEL _MMIO(0x6802c)
5010 /* Controls the DAC level for black */
5011 # define TV_BLACK_LEVEL_MASK 0x01ff0000
5012 # define TV_BLACK_LEVEL_SHIFT 16
5013 /* Controls the DAC level for blanking */
5014 # define TV_BLANK_LEVEL_MASK 0x000001ff
5015 # define TV_BLANK_LEVEL_SHIFT 0
5017 #define TV_H_CTL_1 _MMIO(0x68030)
5018 /* Number of pixels in the hsync. */
5019 # define TV_HSYNC_END_MASK 0x1fff0000
5020 # define TV_HSYNC_END_SHIFT 16
5021 /* Total number of pixels minus one in the line (display and blanking). */
5022 # define TV_HTOTAL_MASK 0x00001fff
5023 # define TV_HTOTAL_SHIFT 0
5025 #define TV_H_CTL_2 _MMIO(0x68034)
5026 /* Enables the colorburst (needed for non-component color) */
5027 # define TV_BURST_ENA (1 << 31)
5028 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
5029 # define TV_HBURST_START_SHIFT 16
5030 # define TV_HBURST_START_MASK 0x1fff0000
5031 /* Length of the colorburst */
5032 # define TV_HBURST_LEN_SHIFT 0
5033 # define TV_HBURST_LEN_MASK 0x0001fff
5035 #define TV_H_CTL_3 _MMIO(0x68038)
5036 /* End of hblank, measured in pixels minus one from start of hsync */
5037 # define TV_HBLANK_END_SHIFT 16
5038 # define TV_HBLANK_END_MASK 0x1fff0000
5039 /* Start of hblank, measured in pixels minus one from start of hsync */
5040 # define TV_HBLANK_START_SHIFT 0
5041 # define TV_HBLANK_START_MASK 0x0001fff
5043 #define TV_V_CTL_1 _MMIO(0x6803c)
5045 # define TV_NBR_END_SHIFT 16
5046 # define TV_NBR_END_MASK 0x07ff0000
5048 # define TV_VI_END_F1_SHIFT 8
5049 # define TV_VI_END_F1_MASK 0x00003f00
5051 # define TV_VI_END_F2_SHIFT 0
5052 # define TV_VI_END_F2_MASK 0x0000003f
5054 #define TV_V_CTL_2 _MMIO(0x68040)
5055 /* Length of vsync, in half lines */
5056 # define TV_VSYNC_LEN_MASK 0x07ff0000
5057 # define TV_VSYNC_LEN_SHIFT 16
5058 /* Offset of the start of vsync in field 1, measured in one less than the
5059 * number of half lines.
5061 # define TV_VSYNC_START_F1_MASK 0x00007f00
5062 # define TV_VSYNC_START_F1_SHIFT 8
5064 * Offset of the start of vsync in field 2, measured in one less than the
5065 * number of half lines.
5067 # define TV_VSYNC_START_F2_MASK 0x0000007f
5068 # define TV_VSYNC_START_F2_SHIFT 0
5070 #define TV_V_CTL_3 _MMIO(0x68044)
5071 /* Enables generation of the equalization signal */
5072 # define TV_EQUAL_ENA (1 << 31)
5073 /* Length of vsync, in half lines */
5074 # define TV_VEQ_LEN_MASK 0x007f0000
5075 # define TV_VEQ_LEN_SHIFT 16
5076 /* Offset of the start of equalization in field 1, measured in one less than
5077 * the number of half lines.
5079 # define TV_VEQ_START_F1_MASK 0x0007f00
5080 # define TV_VEQ_START_F1_SHIFT 8
5082 * Offset of the start of equalization in field 2, measured in one less than
5083 * the number of half lines.
5085 # define TV_VEQ_START_F2_MASK 0x000007f
5086 # define TV_VEQ_START_F2_SHIFT 0
5088 #define TV_V_CTL_4 _MMIO(0x68048)
5090 * Offset to start of vertical colorburst, measured in one less than the
5091 * number of lines from vertical start.
5093 # define TV_VBURST_START_F1_MASK 0x003f0000
5094 # define TV_VBURST_START_F1_SHIFT 16
5096 * Offset to the end of vertical colorburst, measured in one less than the
5097 * number of lines from the start of NBR.
5099 # define TV_VBURST_END_F1_MASK 0x000000ff
5100 # define TV_VBURST_END_F1_SHIFT 0
5102 #define TV_V_CTL_5 _MMIO(0x6804c)
5104 * Offset to start of vertical colorburst, measured in one less than the
5105 * number of lines from vertical start.
5107 # define TV_VBURST_START_F2_MASK 0x003f0000
5108 # define TV_VBURST_START_F2_SHIFT 16
5110 * Offset to the end of vertical colorburst, measured in one less than the
5111 * number of lines from the start of NBR.
5113 # define TV_VBURST_END_F2_MASK 0x000000ff
5114 # define TV_VBURST_END_F2_SHIFT 0
5116 #define TV_V_CTL_6 _MMIO(0x68050)
5118 * Offset to start of vertical colorburst, measured in one less than the
5119 * number of lines from vertical start.
5121 # define TV_VBURST_START_F3_MASK 0x003f0000
5122 # define TV_VBURST_START_F3_SHIFT 16
5124 * Offset to the end of vertical colorburst, measured in one less than the
5125 * number of lines from the start of NBR.
5127 # define TV_VBURST_END_F3_MASK 0x000000ff
5128 # define TV_VBURST_END_F3_SHIFT 0
5130 #define TV_V_CTL_7 _MMIO(0x68054)
5132 * Offset to start of vertical colorburst, measured in one less than the
5133 * number of lines from vertical start.
5135 # define TV_VBURST_START_F4_MASK 0x003f0000
5136 # define TV_VBURST_START_F4_SHIFT 16
5138 * Offset to the end of vertical colorburst, measured in one less than the
5139 * number of lines from the start of NBR.
5141 # define TV_VBURST_END_F4_MASK 0x000000ff
5142 # define TV_VBURST_END_F4_SHIFT 0
5144 #define TV_SC_CTL_1 _MMIO(0x68060)
5145 /* Turns on the first subcarrier phase generation DDA */
5146 # define TV_SC_DDA1_EN (1 << 31)
5147 /* Turns on the first subcarrier phase generation DDA */
5148 # define TV_SC_DDA2_EN (1 << 30)
5149 /* Turns on the first subcarrier phase generation DDA */
5150 # define TV_SC_DDA3_EN (1 << 29)
5151 /* Sets the subcarrier DDA to reset frequency every other field */
5152 # define TV_SC_RESET_EVERY_2 (0 << 24)
5153 /* Sets the subcarrier DDA to reset frequency every fourth field */
5154 # define TV_SC_RESET_EVERY_4 (1 << 24)
5155 /* Sets the subcarrier DDA to reset frequency every eighth field */
5156 # define TV_SC_RESET_EVERY_8 (2 << 24)
5157 /* Sets the subcarrier DDA to never reset the frequency */
5158 # define TV_SC_RESET_NEVER (3 << 24)
5159 /* Sets the peak amplitude of the colorburst.*/
5160 # define TV_BURST_LEVEL_MASK 0x00ff0000
5161 # define TV_BURST_LEVEL_SHIFT 16
5162 /* Sets the increment of the first subcarrier phase generation DDA */
5163 # define TV_SCDDA1_INC_MASK 0x00000fff
5164 # define TV_SCDDA1_INC_SHIFT 0
5166 #define TV_SC_CTL_2 _MMIO(0x68064)
5167 /* Sets the rollover for the second subcarrier phase generation DDA */
5168 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
5169 # define TV_SCDDA2_SIZE_SHIFT 16
5170 /* Sets the increent of the second subcarrier phase generation DDA */
5171 # define TV_SCDDA2_INC_MASK 0x00007fff
5172 # define TV_SCDDA2_INC_SHIFT 0
5174 #define TV_SC_CTL_3 _MMIO(0x68068)
5175 /* Sets the rollover for the third subcarrier phase generation DDA */
5176 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
5177 # define TV_SCDDA3_SIZE_SHIFT 16
5178 /* Sets the increent of the third subcarrier phase generation DDA */
5179 # define TV_SCDDA3_INC_MASK 0x00007fff
5180 # define TV_SCDDA3_INC_SHIFT 0
5182 #define TV_WIN_POS _MMIO(0x68070)
5183 /* X coordinate of the display from the start of horizontal active */
5184 # define TV_XPOS_MASK 0x1fff0000
5185 # define TV_XPOS_SHIFT 16
5186 /* Y coordinate of the display from the start of vertical active (NBR) */
5187 # define TV_YPOS_MASK 0x00000fff
5188 # define TV_YPOS_SHIFT 0
5190 #define TV_WIN_SIZE _MMIO(0x68074)
5191 /* Horizontal size of the display window, measured in pixels*/
5192 # define TV_XSIZE_MASK 0x1fff0000
5193 # define TV_XSIZE_SHIFT 16
5195 * Vertical size of the display window, measured in pixels.
5197 * Must be even for interlaced modes.
5199 # define TV_YSIZE_MASK 0x00000fff
5200 # define TV_YSIZE_SHIFT 0
5202 #define TV_FILTER_CTL_1 _MMIO(0x68080)
5204 * Enables automatic scaling calculation.
5206 * If set, the rest of the registers are ignored, and the calculated values can
5207 * be read back from the register.
5209 # define TV_AUTO_SCALE (1 << 31)
5211 * Disables the vertical filter.
5213 * This is required on modes more than 1024 pixels wide */
5214 # define TV_V_FILTER_BYPASS (1 << 29)
5215 /* Enables adaptive vertical filtering */
5216 # define TV_VADAPT (1 << 28)
5217 # define TV_VADAPT_MODE_MASK (3 << 26)
5218 /* Selects the least adaptive vertical filtering mode */
5219 # define TV_VADAPT_MODE_LEAST (0 << 26)
5220 /* Selects the moderately adaptive vertical filtering mode */
5221 # define TV_VADAPT_MODE_MODERATE (1 << 26)
5222 /* Selects the most adaptive vertical filtering mode */
5223 # define TV_VADAPT_MODE_MOST (3 << 26)
5225 * Sets the horizontal scaling factor.
5227 * This should be the fractional part of the horizontal scaling factor divided
5228 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5230 * (src width - 1) / ((oversample * dest width) - 1)
5232 # define TV_HSCALE_FRAC_MASK 0x00003fff
5233 # define TV_HSCALE_FRAC_SHIFT 0
5235 #define TV_FILTER_CTL_2 _MMIO(0x68084)
5237 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5239 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5241 # define TV_VSCALE_INT_MASK 0x00038000
5242 # define TV_VSCALE_INT_SHIFT 15
5244 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5246 * \sa TV_VSCALE_INT_MASK
5248 # define TV_VSCALE_FRAC_MASK 0x00007fff
5249 # define TV_VSCALE_FRAC_SHIFT 0
5251 #define TV_FILTER_CTL_3 _MMIO(0x68088)
5253 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5255 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5257 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5259 # define TV_VSCALE_IP_INT_MASK 0x00038000
5260 # define TV_VSCALE_IP_INT_SHIFT 15
5262 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5264 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5266 * \sa TV_VSCALE_IP_INT_MASK
5268 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5269 # define TV_VSCALE_IP_FRAC_SHIFT 0
5271 #define TV_CC_CONTROL _MMIO(0x68090)
5272 # define TV_CC_ENABLE (1 << 31)
5274 * Specifies which field to send the CC data in.
5276 * CC data is usually sent in field 0.
5278 # define TV_CC_FID_MASK (1 << 27)
5279 # define TV_CC_FID_SHIFT 27
5280 /* Sets the horizontal position of the CC data. Usually 135. */
5281 # define TV_CC_HOFF_MASK 0x03ff0000
5282 # define TV_CC_HOFF_SHIFT 16
5283 /* Sets the vertical position of the CC data. Usually 21 */
5284 # define TV_CC_LINE_MASK 0x0000003f
5285 # define TV_CC_LINE_SHIFT 0
5287 #define TV_CC_DATA _MMIO(0x68094)
5288 # define TV_CC_RDY (1 << 31)
5289 /* Second word of CC data to be transmitted. */
5290 # define TV_CC_DATA_2_MASK 0x007f0000
5291 # define TV_CC_DATA_2_SHIFT 16
5292 /* First word of CC data to be transmitted. */
5293 # define TV_CC_DATA_1_MASK 0x0000007f
5294 # define TV_CC_DATA_1_SHIFT 0
5296 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
5297 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
5298 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
5299 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
5302 #define DP_A _MMIO(0x64000) /* eDP */
5303 #define DP_B _MMIO(0x64100)
5304 #define DP_C _MMIO(0x64200)
5305 #define DP_D _MMIO(0x64300)
5307 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5308 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5309 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5311 #define DP_PORT_EN (1 << 31)
5312 #define DP_PIPE_SEL_SHIFT 30
5313 #define DP_PIPE_SEL_MASK (1 << 30)
5314 #define DP_PIPE_SEL(pipe) ((pipe) << 30)
5315 #define DP_PIPE_SEL_SHIFT_IVB 29
5316 #define DP_PIPE_SEL_MASK_IVB (3 << 29)
5317 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
5318 #define DP_PIPE_SEL_SHIFT_CHV 16
5319 #define DP_PIPE_SEL_MASK_CHV (3 << 16)
5320 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
5322 /* Link training mode - select a suitable mode for each stage */
5323 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
5324 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
5325 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
5326 #define DP_LINK_TRAIN_OFF (3 << 28)
5327 #define DP_LINK_TRAIN_MASK (3 << 28)
5328 #define DP_LINK_TRAIN_SHIFT 28
5330 /* CPT Link training mode */
5331 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
5332 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
5333 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
5334 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
5335 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
5336 #define DP_LINK_TRAIN_SHIFT_CPT 8
5338 /* Signal voltages. These are mostly controlled by the other end */
5339 #define DP_VOLTAGE_0_4 (0 << 25)
5340 #define DP_VOLTAGE_0_6 (1 << 25)
5341 #define DP_VOLTAGE_0_8 (2 << 25)
5342 #define DP_VOLTAGE_1_2 (3 << 25)
5343 #define DP_VOLTAGE_MASK (7 << 25)
5344 #define DP_VOLTAGE_SHIFT 25
5346 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5349 #define DP_PRE_EMPHASIS_0 (0 << 22)
5350 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
5351 #define DP_PRE_EMPHASIS_6 (2 << 22)
5352 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
5353 #define DP_PRE_EMPHASIS_MASK (7 << 22)
5354 #define DP_PRE_EMPHASIS_SHIFT 22
5356 /* How many wires to use. I guess 3 was too hard */
5357 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5358 #define DP_PORT_WIDTH_MASK (7 << 19)
5359 #define DP_PORT_WIDTH_SHIFT 19
5361 /* Mystic DPCD version 1.1 special mode */
5362 #define DP_ENHANCED_FRAMING (1 << 18)
5365 #define DP_PLL_FREQ_270MHZ (0 << 16)
5366 #define DP_PLL_FREQ_162MHZ (1 << 16)
5367 #define DP_PLL_FREQ_MASK (3 << 16)
5369 /* locked once port is enabled */
5370 #define DP_PORT_REVERSAL (1 << 15)
5373 #define DP_PLL_ENABLE (1 << 14)
5375 /* sends the clock on lane 15 of the PEG for debug */
5376 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
5378 #define DP_SCRAMBLING_DISABLE (1 << 12)
5379 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
5381 /* limit RGB values to avoid confusing TVs */
5382 #define DP_COLOR_RANGE_16_235 (1 << 8)
5384 /* Turn on the audio link */
5385 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
5387 /* vs and hs sync polarity */
5388 #define DP_SYNC_VS_HIGH (1 << 4)
5389 #define DP_SYNC_HS_HIGH (1 << 3)
5392 #define DP_DETECTED (1 << 2)
5394 /* The aux channel provides a way to talk to the
5395 * signal sink for DDC etc. Max packet size supported
5396 * is 20 bytes in each direction, hence the 5 fixed
5399 #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
5400 #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
5401 #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
5402 #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
5403 #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
5404 #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
5406 #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
5407 #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
5408 #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
5409 #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
5410 #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
5411 #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
5413 #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
5414 #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
5415 #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
5416 #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
5417 #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
5418 #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
5420 #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
5421 #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
5422 #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
5423 #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
5424 #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
5425 #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
5427 #define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410)
5428 #define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414)
5429 #define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418)
5430 #define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c)
5431 #define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420)
5432 #define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424)
5434 #define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
5435 #define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
5436 #define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
5437 #define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
5438 #define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
5439 #define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
5441 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5442 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5444 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
5445 #define DP_AUX_CH_CTL_DONE (1 << 30)
5446 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
5447 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
5448 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
5449 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
5450 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
5451 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
5452 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
5453 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
5454 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
5455 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
5456 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
5457 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
5458 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
5459 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
5460 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
5461 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
5462 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
5463 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
5464 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
5465 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5466 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5467 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
5468 #define DP_AUX_CH_CTL_TBT_IO (1 << 11)
5469 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5470 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5471 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
5474 * Computing GMCH M and N values for the Display Port link
5476 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5478 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5480 * The GMCH value is used internally
5482 * bytes_per_pixel is the number of bytes coming out of the plane,
5483 * which is after the LUTs, so we want the bytes for our color format.
5484 * For our current usage, this is always 3, one byte for R, G and B.
5486 #define _PIPEA_DATA_M_G4X 0x70050
5487 #define _PIPEB_DATA_M_G4X 0x71050
5489 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5490 #define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */
5491 #define TU_SIZE_SHIFT 25
5492 #define TU_SIZE_MASK (0x3f << 25)
5494 #define DATA_LINK_M_N_MASK (0xffffff)
5495 #define DATA_LINK_N_MAX (0x800000)
5497 #define _PIPEA_DATA_N_G4X 0x70054
5498 #define _PIPEB_DATA_N_G4X 0x71054
5499 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
5502 * Computing Link M and N values for the Display Port link
5504 * Link M / N = pixel_clock / ls_clk
5506 * (the DP spec calls pixel_clock the 'strm_clk')
5508 * The Link value is transmitted in the Main Stream
5509 * Attributes and VB-ID.
5512 #define _PIPEA_LINK_M_G4X 0x70060
5513 #define _PIPEB_LINK_M_G4X 0x71060
5514 #define PIPEA_DP_LINK_M_MASK (0xffffff)
5516 #define _PIPEA_LINK_N_G4X 0x70064
5517 #define _PIPEB_LINK_N_G4X 0x71064
5518 #define PIPEA_DP_LINK_N_MASK (0xffffff)
5520 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5521 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5522 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5523 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5525 /* Display & cursor control */
5528 #define _PIPEADSL 0x70000
5529 #define DSL_LINEMASK_GEN2 0x00000fff
5530 #define DSL_LINEMASK_GEN3 0x00001fff
5531 #define _PIPEACONF 0x70008
5532 #define PIPECONF_ENABLE (1 << 31)
5533 #define PIPECONF_DISABLE 0
5534 #define PIPECONF_DOUBLE_WIDE (1 << 30)
5535 #define I965_PIPECONF_ACTIVE (1 << 30)
5536 #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
5537 #define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
5538 #define PIPECONF_SINGLE_WIDE 0
5539 #define PIPECONF_PIPE_UNLOCKED 0
5540 #define PIPECONF_PIPE_LOCKED (1 << 25)
5541 #define PIPECONF_PALETTE 0
5542 #define PIPECONF_GAMMA (1 << 24)
5543 #define PIPECONF_FORCE_BORDER (1 << 25)
5544 #define PIPECONF_INTERLACE_MASK (7 << 21)
5545 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
5546 /* Note that pre-gen3 does not support interlaced display directly. Panel
5547 * fitting must be disabled on pre-ilk for interlaced. */
5548 #define PIPECONF_PROGRESSIVE (0 << 21)
5549 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
5550 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
5551 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5552 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
5553 /* Ironlake and later have a complete new set of values for interlaced. PFIT
5554 * means panel fitter required, PF means progressive fetch, DBL means power
5555 * saving pixel doubling. */
5556 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
5557 #define PIPECONF_INTERLACED_ILK (3 << 21)
5558 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
5559 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
5560 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
5561 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
5562 #define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
5563 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
5564 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
5565 #define PIPECONF_BPC_MASK (0x7 << 5)
5566 #define PIPECONF_8BPC (0 << 5)
5567 #define PIPECONF_10BPC (1 << 5)
5568 #define PIPECONF_6BPC (2 << 5)
5569 #define PIPECONF_12BPC (3 << 5)
5570 #define PIPECONF_DITHER_EN (1 << 4)
5571 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5572 #define PIPECONF_DITHER_TYPE_SP (0 << 2)
5573 #define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
5574 #define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
5575 #define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
5576 #define _PIPEASTAT 0x70024
5577 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
5578 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
5579 #define PIPE_CRC_ERROR_ENABLE (1UL << 29)
5580 #define PIPE_CRC_DONE_ENABLE (1UL << 28)
5581 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
5582 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
5583 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
5584 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
5585 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
5586 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
5587 #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
5588 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
5589 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
5590 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
5591 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
5592 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
5593 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
5594 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
5595 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
5596 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
5597 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
5598 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
5599 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
5600 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
5601 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
5602 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
5603 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
5604 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
5605 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
5606 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
5607 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
5608 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
5609 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
5610 #define PIPE_DPST_EVENT_STATUS (1UL << 7)
5611 #define PIPE_A_PSR_STATUS_VLV (1UL << 6)
5612 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
5613 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
5614 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
5615 #define PIPE_B_PSR_STATUS_VLV (1UL << 3)
5616 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
5617 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
5618 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
5619 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
5620 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
5621 #define PIPE_HBLANK_INT_STATUS (1UL << 0)
5622 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
5624 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
5625 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
5627 #define PIPE_A_OFFSET 0x70000
5628 #define PIPE_B_OFFSET 0x71000
5629 #define PIPE_C_OFFSET 0x72000
5630 #define CHV_PIPE_C_OFFSET 0x74000
5632 * There's actually no pipe EDP. Some pipe registers have
5633 * simply shifted from the pipe to the transcoder, while
5634 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5635 * to access such registers in transcoder EDP.
5637 #define PIPE_EDP_OFFSET 0x7f000
5639 #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
5640 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
5641 dev_priv->info.display_mmio_offset)
5643 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5644 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
5645 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5646 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5647 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
5649 #define _PIPE_MISC_A 0x70030
5650 #define _PIPE_MISC_B 0x71030
5651 #define PIPEMISC_YUV420_ENABLE (1 << 27)
5652 #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
5653 #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
5654 #define PIPEMISC_DITHER_BPC_MASK (7 << 5)
5655 #define PIPEMISC_DITHER_8_BPC (0 << 5)
5656 #define PIPEMISC_DITHER_10_BPC (1 << 5)
5657 #define PIPEMISC_DITHER_6_BPC (2 << 5)
5658 #define PIPEMISC_DITHER_12_BPC (3 << 5)
5659 #define PIPEMISC_DITHER_ENABLE (1 << 4)
5660 #define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
5661 #define PIPEMISC_DITHER_TYPE_SP (0 << 2)
5662 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
5664 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5665 #define PIPEB_LINE_COMPARE_INT_EN (1 << 29)
5666 #define PIPEB_HLINE_INT_EN (1 << 28)
5667 #define PIPEB_VBLANK_INT_EN (1 << 27)
5668 #define SPRITED_FLIP_DONE_INT_EN (1 << 26)
5669 #define SPRITEC_FLIP_DONE_INT_EN (1 << 25)
5670 #define PLANEB_FLIP_DONE_INT_EN (1 << 24)
5671 #define PIPE_PSR_INT_EN (1 << 22)
5672 #define PIPEA_LINE_COMPARE_INT_EN (1 << 21)
5673 #define PIPEA_HLINE_INT_EN (1 << 20)
5674 #define PIPEA_VBLANK_INT_EN (1 << 19)
5675 #define SPRITEB_FLIP_DONE_INT_EN (1 << 18)
5676 #define SPRITEA_FLIP_DONE_INT_EN (1 << 17)
5677 #define PLANEA_FLIPDONE_INT_EN (1 << 16)
5678 #define PIPEC_LINE_COMPARE_INT_EN (1 << 13)
5679 #define PIPEC_HLINE_INT_EN (1 << 12)
5680 #define PIPEC_VBLANK_INT_EN (1 << 11)
5681 #define SPRITEF_FLIPDONE_INT_EN (1 << 10)
5682 #define SPRITEE_FLIPDONE_INT_EN (1 << 9)
5683 #define PLANEC_FLIPDONE_INT_EN (1 << 8)
5685 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5686 #define SPRITEF_INVALID_GTT_INT_EN (1 << 27)
5687 #define SPRITEE_INVALID_GTT_INT_EN (1 << 26)
5688 #define PLANEC_INVALID_GTT_INT_EN (1 << 25)
5689 #define CURSORC_INVALID_GTT_INT_EN (1 << 24)
5690 #define CURSORB_INVALID_GTT_INT_EN (1 << 23)
5691 #define CURSORA_INVALID_GTT_INT_EN (1 << 22)
5692 #define SPRITED_INVALID_GTT_INT_EN (1 << 21)
5693 #define SPRITEC_INVALID_GTT_INT_EN (1 << 20)
5694 #define PLANEB_INVALID_GTT_INT_EN (1 << 19)
5695 #define SPRITEB_INVALID_GTT_INT_EN (1 << 18)
5696 #define SPRITEA_INVALID_GTT_INT_EN (1 << 17)
5697 #define PLANEA_INVALID_GTT_INT_EN (1 << 16)
5698 #define DPINVGTT_EN_MASK 0xff0000
5699 #define DPINVGTT_EN_MASK_CHV 0xfff0000
5700 #define SPRITEF_INVALID_GTT_STATUS (1 << 11)
5701 #define SPRITEE_INVALID_GTT_STATUS (1 << 10)
5702 #define PLANEC_INVALID_GTT_STATUS (1 << 9)
5703 #define CURSORC_INVALID_GTT_STATUS (1 << 8)
5704 #define CURSORB_INVALID_GTT_STATUS (1 << 7)
5705 #define CURSORA_INVALID_GTT_STATUS (1 << 6)
5706 #define SPRITED_INVALID_GTT_STATUS (1 << 5)
5707 #define SPRITEC_INVALID_GTT_STATUS (1 << 4)
5708 #define PLANEB_INVALID_GTT_STATUS (1 << 3)
5709 #define SPRITEB_INVALID_GTT_STATUS (1 << 2)
5710 #define SPRITEA_INVALID_GTT_STATUS (1 << 1)
5711 #define PLANEA_INVALID_GTT_STATUS (1 << 0)
5712 #define DPINVGTT_STATUS_MASK 0xff
5713 #define DPINVGTT_STATUS_MASK_CHV 0xfff
5715 #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
5716 #define DSPARB_CSTART_MASK (0x7f << 7)
5717 #define DSPARB_CSTART_SHIFT 7
5718 #define DSPARB_BSTART_MASK (0x7f)
5719 #define DSPARB_BSTART_SHIFT 0
5720 #define DSPARB_BEND_SHIFT 9 /* on 855 */
5721 #define DSPARB_AEND_SHIFT 0
5722 #define DSPARB_SPRITEA_SHIFT_VLV 0
5723 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
5724 #define DSPARB_SPRITEB_SHIFT_VLV 8
5725 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
5726 #define DSPARB_SPRITEC_SHIFT_VLV 16
5727 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
5728 #define DSPARB_SPRITED_SHIFT_VLV 24
5729 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
5730 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5731 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
5732 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
5733 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
5734 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
5735 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
5736 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
5737 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
5738 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
5739 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
5740 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
5741 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
5742 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
5743 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5744 #define DSPARB_SPRITEE_SHIFT_VLV 0
5745 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
5746 #define DSPARB_SPRITEF_SHIFT_VLV 8
5747 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
5749 /* pnv/gen4/g4x/vlv/chv */
5750 #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
5751 #define DSPFW_SR_SHIFT 23
5752 #define DSPFW_SR_MASK (0x1ff << 23)
5753 #define DSPFW_CURSORB_SHIFT 16
5754 #define DSPFW_CURSORB_MASK (0x3f << 16)
5755 #define DSPFW_PLANEB_SHIFT 8
5756 #define DSPFW_PLANEB_MASK (0x7f << 8)
5757 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
5758 #define DSPFW_PLANEA_SHIFT 0
5759 #define DSPFW_PLANEA_MASK (0x7f << 0)
5760 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
5761 #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
5762 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
5763 #define DSPFW_FBC_SR_SHIFT 28
5764 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
5765 #define DSPFW_FBC_HPLL_SR_SHIFT 24
5766 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
5767 #define DSPFW_SPRITEB_SHIFT (16)
5768 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
5769 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
5770 #define DSPFW_CURSORA_SHIFT 8
5771 #define DSPFW_CURSORA_MASK (0x3f << 8)
5772 #define DSPFW_PLANEC_OLD_SHIFT 0
5773 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
5774 #define DSPFW_SPRITEA_SHIFT 0
5775 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
5776 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
5777 #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
5778 #define DSPFW_HPLL_SR_EN (1 << 31)
5779 #define PINEVIEW_SELF_REFRESH_EN (1 << 30)
5780 #define DSPFW_CURSOR_SR_SHIFT 24
5781 #define DSPFW_CURSOR_SR_MASK (0x3f << 24)
5782 #define DSPFW_HPLL_CURSOR_SHIFT 16
5783 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
5784 #define DSPFW_HPLL_SR_SHIFT 0
5785 #define DSPFW_HPLL_SR_MASK (0x1ff << 0)
5788 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
5789 #define DSPFW_SPRITEB_WM1_SHIFT 16
5790 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
5791 #define DSPFW_CURSORA_WM1_SHIFT 8
5792 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
5793 #define DSPFW_SPRITEA_WM1_SHIFT 0
5794 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
5795 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
5796 #define DSPFW_PLANEB_WM1_SHIFT 24
5797 #define DSPFW_PLANEB_WM1_MASK (0xff << 24)
5798 #define DSPFW_PLANEA_WM1_SHIFT 16
5799 #define DSPFW_PLANEA_WM1_MASK (0xff << 16)
5800 #define DSPFW_CURSORB_WM1_SHIFT 8
5801 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
5802 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
5803 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
5804 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
5805 #define DSPFW_SR_WM1_SHIFT 0
5806 #define DSPFW_SR_WM1_MASK (0x1ff << 0)
5807 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5808 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5809 #define DSPFW_SPRITED_WM1_SHIFT 24
5810 #define DSPFW_SPRITED_WM1_MASK (0xff << 24)
5811 #define DSPFW_SPRITED_SHIFT 16
5812 #define DSPFW_SPRITED_MASK_VLV (0xff << 16)
5813 #define DSPFW_SPRITEC_WM1_SHIFT 8
5814 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
5815 #define DSPFW_SPRITEC_SHIFT 0
5816 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
5817 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5818 #define DSPFW_SPRITEF_WM1_SHIFT 24
5819 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
5820 #define DSPFW_SPRITEF_SHIFT 16
5821 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
5822 #define DSPFW_SPRITEE_WM1_SHIFT 8
5823 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
5824 #define DSPFW_SPRITEE_SHIFT 0
5825 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
5826 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5827 #define DSPFW_PLANEC_WM1_SHIFT 24
5828 #define DSPFW_PLANEC_WM1_MASK (0xff << 24)
5829 #define DSPFW_PLANEC_SHIFT 16
5830 #define DSPFW_PLANEC_MASK_VLV (0xff << 16)
5831 #define DSPFW_CURSORC_WM1_SHIFT 8
5832 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
5833 #define DSPFW_CURSORC_SHIFT 0
5834 #define DSPFW_CURSORC_MASK (0x3f << 0)
5836 /* vlv/chv high order bits */
5837 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
5838 #define DSPFW_SR_HI_SHIFT 24
5839 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
5840 #define DSPFW_SPRITEF_HI_SHIFT 23
5841 #define DSPFW_SPRITEF_HI_MASK (1 << 23)
5842 #define DSPFW_SPRITEE_HI_SHIFT 22
5843 #define DSPFW_SPRITEE_HI_MASK (1 << 22)
5844 #define DSPFW_PLANEC_HI_SHIFT 21
5845 #define DSPFW_PLANEC_HI_MASK (1 << 21)
5846 #define DSPFW_SPRITED_HI_SHIFT 20
5847 #define DSPFW_SPRITED_HI_MASK (1 << 20)
5848 #define DSPFW_SPRITEC_HI_SHIFT 16
5849 #define DSPFW_SPRITEC_HI_MASK (1 << 16)
5850 #define DSPFW_PLANEB_HI_SHIFT 12
5851 #define DSPFW_PLANEB_HI_MASK (1 << 12)
5852 #define DSPFW_SPRITEB_HI_SHIFT 8
5853 #define DSPFW_SPRITEB_HI_MASK (1 << 8)
5854 #define DSPFW_SPRITEA_HI_SHIFT 4
5855 #define DSPFW_SPRITEA_HI_MASK (1 << 4)
5856 #define DSPFW_PLANEA_HI_SHIFT 0
5857 #define DSPFW_PLANEA_HI_MASK (1 << 0)
5858 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
5859 #define DSPFW_SR_WM1_HI_SHIFT 24
5860 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
5861 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
5862 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
5863 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
5864 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
5865 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
5866 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
5867 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
5868 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
5869 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
5870 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
5871 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
5872 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
5873 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
5874 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
5875 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
5876 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
5877 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
5878 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
5880 /* drain latency register values*/
5881 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5882 #define DDL_CURSOR_SHIFT 24
5883 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
5884 #define DDL_PLANE_SHIFT 0
5885 #define DDL_PRECISION_HIGH (1 << 7)
5886 #define DDL_PRECISION_LOW (0 << 7)
5887 #define DRAIN_LATENCY_MASK 0x7f
5889 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
5890 #define CBR_PND_DEADLINE_DISABLE (1 << 31)
5891 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
5893 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
5894 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
5896 /* FIFO watermark sizes etc */
5897 #define G4X_FIFO_LINE_SIZE 64
5898 #define I915_FIFO_LINE_SIZE 64
5899 #define I830_FIFO_LINE_SIZE 32
5901 #define VALLEYVIEW_FIFO_SIZE 255
5902 #define G4X_FIFO_SIZE 127
5903 #define I965_FIFO_SIZE 512
5904 #define I945_FIFO_SIZE 127
5905 #define I915_FIFO_SIZE 95
5906 #define I855GM_FIFO_SIZE 127 /* In cachelines */
5907 #define I830_FIFO_SIZE 95
5909 #define VALLEYVIEW_MAX_WM 0xff
5910 #define G4X_MAX_WM 0x3f
5911 #define I915_MAX_WM 0x3f
5913 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
5914 #define PINEVIEW_FIFO_LINE_SIZE 64
5915 #define PINEVIEW_MAX_WM 0x1ff
5916 #define PINEVIEW_DFT_WM 0x3f
5917 #define PINEVIEW_DFT_HPLLOFF_WM 0
5918 #define PINEVIEW_GUARD_WM 10
5919 #define PINEVIEW_CURSOR_FIFO 64
5920 #define PINEVIEW_CURSOR_MAX_WM 0x3f
5921 #define PINEVIEW_CURSOR_DFT_WM 0
5922 #define PINEVIEW_CURSOR_GUARD_WM 5
5924 #define VALLEYVIEW_CURSOR_MAX_WM 64
5925 #define I965_CURSOR_FIFO 64
5926 #define I965_CURSOR_MAX_WM 32
5927 #define I965_CURSOR_DFT_WM 8
5929 /* Watermark register definitions for SKL */
5930 #define _CUR_WM_A_0 0x70140
5931 #define _CUR_WM_B_0 0x71140
5932 #define _PLANE_WM_1_A_0 0x70240
5933 #define _PLANE_WM_1_B_0 0x71240
5934 #define _PLANE_WM_2_A_0 0x70340
5935 #define _PLANE_WM_2_B_0 0x71340
5936 #define _PLANE_WM_TRANS_1_A_0 0x70268
5937 #define _PLANE_WM_TRANS_1_B_0 0x71268
5938 #define _PLANE_WM_TRANS_2_A_0 0x70368
5939 #define _PLANE_WM_TRANS_2_B_0 0x71368
5940 #define _CUR_WM_TRANS_A_0 0x70168
5941 #define _CUR_WM_TRANS_B_0 0x71168
5942 #define PLANE_WM_EN (1 << 31)
5943 #define PLANE_WM_LINES_SHIFT 14
5944 #define PLANE_WM_LINES_MASK 0x1f
5945 #define PLANE_WM_BLOCKS_MASK 0x3ff
5947 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
5948 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
5949 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
5951 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
5952 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
5953 #define _PLANE_WM_BASE(pipe, plane) \
5954 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
5955 #define PLANE_WM(pipe, plane, level) \
5956 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
5957 #define _PLANE_WM_TRANS_1(pipe) \
5958 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
5959 #define _PLANE_WM_TRANS_2(pipe) \
5960 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
5961 #define PLANE_WM_TRANS(pipe, plane) \
5962 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
5964 /* define the Watermark register on Ironlake */
5965 #define WM0_PIPEA_ILK _MMIO(0x45100)
5966 #define WM0_PIPE_PLANE_MASK (0xffff << 16)
5967 #define WM0_PIPE_PLANE_SHIFT 16
5968 #define WM0_PIPE_SPRITE_MASK (0xff << 8)
5969 #define WM0_PIPE_SPRITE_SHIFT 8
5970 #define WM0_PIPE_CURSOR_MASK (0xff)
5972 #define WM0_PIPEB_ILK _MMIO(0x45104)
5973 #define WM0_PIPEC_IVB _MMIO(0x45200)
5974 #define WM1_LP_ILK _MMIO(0x45108)
5975 #define WM1_LP_SR_EN (1 << 31)
5976 #define WM1_LP_LATENCY_SHIFT 24
5977 #define WM1_LP_LATENCY_MASK (0x7f << 24)
5978 #define WM1_LP_FBC_MASK (0xf << 20)
5979 #define WM1_LP_FBC_SHIFT 20
5980 #define WM1_LP_FBC_SHIFT_BDW 19
5981 #define WM1_LP_SR_MASK (0x7ff << 8)
5982 #define WM1_LP_SR_SHIFT 8
5983 #define WM1_LP_CURSOR_MASK (0xff)
5984 #define WM2_LP_ILK _MMIO(0x4510c)
5985 #define WM2_LP_EN (1 << 31)
5986 #define WM3_LP_ILK _MMIO(0x45110)
5987 #define WM3_LP_EN (1 << 31)
5988 #define WM1S_LP_ILK _MMIO(0x45120)
5989 #define WM2S_LP_IVB _MMIO(0x45124)
5990 #define WM3S_LP_IVB _MMIO(0x45128)
5991 #define WM1S_LP_EN (1 << 31)
5993 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
5994 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
5995 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
5997 /* Memory latency timer register */
5998 #define MLTR_ILK _MMIO(0x11222)
5999 #define MLTR_WM1_SHIFT 0
6000 #define MLTR_WM2_SHIFT 8
6001 /* the unit of memory self-refresh latency time is 0.5us */
6002 #define ILK_SRLT_MASK 0x3f
6005 /* the address where we get all kinds of latency value */
6006 #define SSKPD _MMIO(0x5d10)
6007 #define SSKPD_WM_MASK 0x3f
6008 #define SSKPD_WM0_SHIFT 0
6009 #define SSKPD_WM1_SHIFT 8
6010 #define SSKPD_WM2_SHIFT 16
6011 #define SSKPD_WM3_SHIFT 24
6014 * The two pipe frame counter registers are not synchronized, so
6015 * reading a stable value is somewhat tricky. The following code
6019 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6020 * PIPE_FRAME_HIGH_SHIFT;
6021 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6022 * PIPE_FRAME_LOW_SHIFT);
6023 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6024 * PIPE_FRAME_HIGH_SHIFT);
6025 * } while (high1 != high2);
6026 * frame = (high1 << 8) | low1;
6028 #define _PIPEAFRAMEHIGH 0x70040
6029 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
6030 #define PIPE_FRAME_HIGH_SHIFT 0
6031 #define _PIPEAFRAMEPIXEL 0x70044
6032 #define PIPE_FRAME_LOW_MASK 0xff000000
6033 #define PIPE_FRAME_LOW_SHIFT 24
6034 #define PIPE_PIXEL_MASK 0x00ffffff
6035 #define PIPE_PIXEL_SHIFT 0
6036 /* GM45+ just has to be different */
6037 #define _PIPEA_FRMCOUNT_G4X 0x70040
6038 #define _PIPEA_FLIPCOUNT_G4X 0x70044
6039 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6040 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6042 /* Cursor A & B regs */
6043 #define _CURACNTR 0x70080
6044 /* Old style CUR*CNTR flags (desktop 8xx) */
6045 #define CURSOR_ENABLE 0x80000000
6046 #define CURSOR_GAMMA_ENABLE 0x40000000
6047 #define CURSOR_STRIDE_SHIFT 28
6048 #define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6049 #define CURSOR_FORMAT_SHIFT 24
6050 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
6051 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
6052 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
6053 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
6054 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
6055 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
6056 /* New style CUR*CNTR flags */
6057 #define MCURSOR_MODE 0x27
6058 #define MCURSOR_MODE_DISABLE 0x00
6059 #define MCURSOR_MODE_128_32B_AX 0x02
6060 #define MCURSOR_MODE_256_32B_AX 0x03
6061 #define MCURSOR_MODE_64_32B_AX 0x07
6062 #define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6063 #define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6064 #define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6065 #define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
6066 #define MCURSOR_PIPE_SELECT_SHIFT 28
6067 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
6068 #define MCURSOR_GAMMA_ENABLE (1 << 26)
6069 #define MCURSOR_PIPE_CSC_ENABLE (1 << 24)
6070 #define MCURSOR_ROTATE_180 (1 << 15)
6071 #define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
6072 #define _CURABASE 0x70084
6073 #define _CURAPOS 0x70088
6074 #define CURSOR_POS_MASK 0x007FF
6075 #define CURSOR_POS_SIGN 0x8000
6076 #define CURSOR_X_SHIFT 0
6077 #define CURSOR_Y_SHIFT 16
6078 #define CURSIZE _MMIO(0x700a0) /* 845/865 */
6079 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
6080 #define CUR_FBC_CTL_EN (1 << 31)
6081 #define _CURASURFLIVE 0x700ac /* g4x+ */
6082 #define _CURBCNTR 0x700c0
6083 #define _CURBBASE 0x700c4
6084 #define _CURBPOS 0x700c8
6086 #define _CURBCNTR_IVB 0x71080
6087 #define _CURBBASE_IVB 0x71084
6088 #define _CURBPOS_IVB 0x71088
6090 #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
6091 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
6092 dev_priv->info.display_mmio_offset)
6094 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6095 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6096 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6097 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6098 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6100 #define CURSOR_A_OFFSET 0x70080
6101 #define CURSOR_B_OFFSET 0x700c0
6102 #define CHV_CURSOR_C_OFFSET 0x700e0
6103 #define IVB_CURSOR_B_OFFSET 0x71080
6104 #define IVB_CURSOR_C_OFFSET 0x72080
6106 /* Display A control */
6107 #define _DSPACNTR 0x70180
6108 #define DISPLAY_PLANE_ENABLE (1 << 31)
6109 #define DISPLAY_PLANE_DISABLE 0
6110 #define DISPPLANE_GAMMA_ENABLE (1 << 30)
6111 #define DISPPLANE_GAMMA_DISABLE 0
6112 #define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
6113 #define DISPPLANE_YUV422 (0x0 << 26)
6114 #define DISPPLANE_8BPP (0x2 << 26)
6115 #define DISPPLANE_BGRA555 (0x3 << 26)
6116 #define DISPPLANE_BGRX555 (0x4 << 26)
6117 #define DISPPLANE_BGRX565 (0x5 << 26)
6118 #define DISPPLANE_BGRX888 (0x6 << 26)
6119 #define DISPPLANE_BGRA888 (0x7 << 26)
6120 #define DISPPLANE_RGBX101010 (0x8 << 26)
6121 #define DISPPLANE_RGBA101010 (0x9 << 26)
6122 #define DISPPLANE_BGRX101010 (0xa << 26)
6123 #define DISPPLANE_RGBX161616 (0xc << 26)
6124 #define DISPPLANE_RGBX888 (0xe << 26)
6125 #define DISPPLANE_RGBA888 (0xf << 26)
6126 #define DISPPLANE_STEREO_ENABLE (1 << 25)
6127 #define DISPPLANE_STEREO_DISABLE 0
6128 #define DISPPLANE_PIPE_CSC_ENABLE (1 << 24)
6129 #define DISPPLANE_SEL_PIPE_SHIFT 24
6130 #define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
6131 #define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6132 #define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
6133 #define DISPPLANE_SRC_KEY_DISABLE 0
6134 #define DISPPLANE_LINE_DOUBLE (1 << 20)
6135 #define DISPPLANE_NO_LINE_DOUBLE 0
6136 #define DISPPLANE_STEREO_POLARITY_FIRST 0
6137 #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
6138 #define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
6139 #define DISPPLANE_ROTATE_180 (1 << 15)
6140 #define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
6141 #define DISPPLANE_TILED (1 << 10)
6142 #define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
6143 #define _DSPAADDR 0x70184
6144 #define _DSPASTRIDE 0x70188
6145 #define _DSPAPOS 0x7018C /* reserved */
6146 #define _DSPASIZE 0x70190
6147 #define _DSPASURF 0x7019C /* 965+ only */
6148 #define _DSPATILEOFF 0x701A4 /* 965+ only */
6149 #define _DSPAOFFSET 0x701A4 /* HSW */
6150 #define _DSPASURFLIVE 0x701AC
6152 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6153 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6154 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6155 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6156 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6157 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6158 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6159 #define DSPLINOFF(plane) DSPADDR(plane)
6160 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6161 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
6163 /* CHV pipe B blender and primary plane */
6164 #define _CHV_BLEND_A 0x60a00
6165 #define CHV_BLEND_LEGACY (0 << 30)
6166 #define CHV_BLEND_ANDROID (1 << 30)
6167 #define CHV_BLEND_MPO (2 << 30)
6168 #define CHV_BLEND_MASK (3 << 30)
6169 #define _CHV_CANVAS_A 0x60a04
6170 #define _PRIMPOS_A 0x60a08
6171 #define _PRIMSIZE_A 0x60a0c
6172 #define _PRIMCNSTALPHA_A 0x60a10
6173 #define PRIM_CONST_ALPHA_ENABLE (1 << 31)
6175 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6176 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6177 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6178 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6179 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6181 /* Display/Sprite base address macros */
6182 #define DISP_BASEADDR_MASK (0xfffff000)
6183 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
6184 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
6197 #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
6198 #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
6199 #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
6200 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6203 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
6204 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
6205 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
6206 #define _PIPEBFRAMEHIGH 0x71040
6207 #define _PIPEBFRAMEPIXEL 0x71044
6208 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
6209 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
6212 /* Display B control */
6213 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
6214 #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
6215 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
6216 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6217 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6218 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
6219 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
6220 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
6221 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
6222 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
6223 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
6224 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
6225 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
6227 /* Sprite A control */
6228 #define _DVSACNTR 0x72180
6229 #define DVS_ENABLE (1 << 31)
6230 #define DVS_GAMMA_ENABLE (1 << 30)
6231 #define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
6232 #define DVS_PIXFORMAT_MASK (3 << 25)
6233 #define DVS_FORMAT_YUV422 (0 << 25)
6234 #define DVS_FORMAT_RGBX101010 (1 << 25)
6235 #define DVS_FORMAT_RGBX888 (2 << 25)
6236 #define DVS_FORMAT_RGBX161616 (3 << 25)
6237 #define DVS_PIPE_CSC_ENABLE (1 << 24)
6238 #define DVS_SOURCE_KEY (1 << 22)
6239 #define DVS_RGB_ORDER_XBGR (1 << 20)
6240 #define DVS_YUV_FORMAT_BT709 (1 << 18)
6241 #define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6242 #define DVS_YUV_ORDER_YUYV (0 << 16)
6243 #define DVS_YUV_ORDER_UYVY (1 << 16)
6244 #define DVS_YUV_ORDER_YVYU (2 << 16)
6245 #define DVS_YUV_ORDER_VYUY (3 << 16)
6246 #define DVS_ROTATE_180 (1 << 15)
6247 #define DVS_DEST_KEY (1 << 2)
6248 #define DVS_TRICKLE_FEED_DISABLE (1 << 14)
6249 #define DVS_TILED (1 << 10)
6250 #define _DVSALINOFF 0x72184
6251 #define _DVSASTRIDE 0x72188
6252 #define _DVSAPOS 0x7218c
6253 #define _DVSASIZE 0x72190
6254 #define _DVSAKEYVAL 0x72194
6255 #define _DVSAKEYMSK 0x72198
6256 #define _DVSASURF 0x7219c
6257 #define _DVSAKEYMAXVAL 0x721a0
6258 #define _DVSATILEOFF 0x721a4
6259 #define _DVSASURFLIVE 0x721ac
6260 #define _DVSASCALE 0x72204
6261 #define DVS_SCALE_ENABLE (1 << 31)
6262 #define DVS_FILTER_MASK (3 << 29)
6263 #define DVS_FILTER_MEDIUM (0 << 29)
6264 #define DVS_FILTER_ENHANCING (1 << 29)
6265 #define DVS_FILTER_SOFTENING (2 << 29)
6266 #define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6267 #define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6268 #define _DVSAGAMC 0x72300
6270 #define _DVSBCNTR 0x73180
6271 #define _DVSBLINOFF 0x73184
6272 #define _DVSBSTRIDE 0x73188
6273 #define _DVSBPOS 0x7318c
6274 #define _DVSBSIZE 0x73190
6275 #define _DVSBKEYVAL 0x73194
6276 #define _DVSBKEYMSK 0x73198
6277 #define _DVSBSURF 0x7319c
6278 #define _DVSBKEYMAXVAL 0x731a0
6279 #define _DVSBTILEOFF 0x731a4
6280 #define _DVSBSURFLIVE 0x731ac
6281 #define _DVSBSCALE 0x73204
6282 #define _DVSBGAMC 0x73300
6284 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6285 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6286 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6287 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6288 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6289 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6290 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6291 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6292 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6293 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6294 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6295 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6297 #define _SPRA_CTL 0x70280
6298 #define SPRITE_ENABLE (1 << 31)
6299 #define SPRITE_GAMMA_ENABLE (1 << 30)
6300 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6301 #define SPRITE_PIXFORMAT_MASK (7 << 25)
6302 #define SPRITE_FORMAT_YUV422 (0 << 25)
6303 #define SPRITE_FORMAT_RGBX101010 (1 << 25)
6304 #define SPRITE_FORMAT_RGBX888 (2 << 25)
6305 #define SPRITE_FORMAT_RGBX161616 (3 << 25)
6306 #define SPRITE_FORMAT_YUV444 (4 << 25)
6307 #define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
6308 #define SPRITE_PIPE_CSC_ENABLE (1 << 24)
6309 #define SPRITE_SOURCE_KEY (1 << 22)
6310 #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
6311 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
6312 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
6313 #define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
6314 #define SPRITE_YUV_ORDER_YUYV (0 << 16)
6315 #define SPRITE_YUV_ORDER_UYVY (1 << 16)
6316 #define SPRITE_YUV_ORDER_YVYU (2 << 16)
6317 #define SPRITE_YUV_ORDER_VYUY (3 << 16)
6318 #define SPRITE_ROTATE_180 (1 << 15)
6319 #define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
6320 #define SPRITE_INT_GAMMA_ENABLE (1 << 13)
6321 #define SPRITE_TILED (1 << 10)
6322 #define SPRITE_DEST_KEY (1 << 2)
6323 #define _SPRA_LINOFF 0x70284
6324 #define _SPRA_STRIDE 0x70288
6325 #define _SPRA_POS 0x7028c
6326 #define _SPRA_SIZE 0x70290
6327 #define _SPRA_KEYVAL 0x70294
6328 #define _SPRA_KEYMSK 0x70298
6329 #define _SPRA_SURF 0x7029c
6330 #define _SPRA_KEYMAX 0x702a0
6331 #define _SPRA_TILEOFF 0x702a4
6332 #define _SPRA_OFFSET 0x702a4
6333 #define _SPRA_SURFLIVE 0x702ac
6334 #define _SPRA_SCALE 0x70304
6335 #define SPRITE_SCALE_ENABLE (1 << 31)
6336 #define SPRITE_FILTER_MASK (3 << 29)
6337 #define SPRITE_FILTER_MEDIUM (0 << 29)
6338 #define SPRITE_FILTER_ENHANCING (1 << 29)
6339 #define SPRITE_FILTER_SOFTENING (2 << 29)
6340 #define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6341 #define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
6342 #define _SPRA_GAMC 0x70400
6344 #define _SPRB_CTL 0x71280
6345 #define _SPRB_LINOFF 0x71284
6346 #define _SPRB_STRIDE 0x71288
6347 #define _SPRB_POS 0x7128c
6348 #define _SPRB_SIZE 0x71290
6349 #define _SPRB_KEYVAL 0x71294
6350 #define _SPRB_KEYMSK 0x71298
6351 #define _SPRB_SURF 0x7129c
6352 #define _SPRB_KEYMAX 0x712a0
6353 #define _SPRB_TILEOFF 0x712a4
6354 #define _SPRB_OFFSET 0x712a4
6355 #define _SPRB_SURFLIVE 0x712ac
6356 #define _SPRB_SCALE 0x71304
6357 #define _SPRB_GAMC 0x71400
6359 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6360 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6361 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6362 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6363 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6364 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6365 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6366 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6367 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6368 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6369 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6370 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6371 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
6372 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6374 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6375 #define SP_ENABLE (1 << 31)
6376 #define SP_GAMMA_ENABLE (1 << 30)
6377 #define SP_PIXFORMAT_MASK (0xf << 26)
6378 #define SP_FORMAT_YUV422 (0 << 26)
6379 #define SP_FORMAT_BGR565 (5 << 26)
6380 #define SP_FORMAT_BGRX8888 (6 << 26)
6381 #define SP_FORMAT_BGRA8888 (7 << 26)
6382 #define SP_FORMAT_RGBX1010102 (8 << 26)
6383 #define SP_FORMAT_RGBA1010102 (9 << 26)
6384 #define SP_FORMAT_RGBX8888 (0xe << 26)
6385 #define SP_FORMAT_RGBA8888 (0xf << 26)
6386 #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
6387 #define SP_SOURCE_KEY (1 << 22)
6388 #define SP_YUV_FORMAT_BT709 (1 << 18)
6389 #define SP_YUV_BYTE_ORDER_MASK (3 << 16)
6390 #define SP_YUV_ORDER_YUYV (0 << 16)
6391 #define SP_YUV_ORDER_UYVY (1 << 16)
6392 #define SP_YUV_ORDER_YVYU (2 << 16)
6393 #define SP_YUV_ORDER_VYUY (3 << 16)
6394 #define SP_ROTATE_180 (1 << 15)
6395 #define SP_TILED (1 << 10)
6396 #define SP_MIRROR (1 << 8) /* CHV pipe B */
6397 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6398 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6399 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6400 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6401 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6402 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6403 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6404 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6405 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6406 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6407 #define SP_CONST_ALPHA_ENABLE (1 << 31)
6408 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
6409 #define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
6410 #define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
6411 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
6412 #define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
6413 #define SP_SH_COS(x) (x) /* u3.7 */
6414 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
6416 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6417 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6418 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6419 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6420 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6421 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6422 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6423 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6424 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6425 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6426 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6427 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
6428 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
6429 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
6431 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6432 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6434 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6435 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6436 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6437 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6438 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6439 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6440 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6441 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6442 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6443 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6444 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6445 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6446 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6447 #define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
6450 * CHV pipe B sprite CSC
6452 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
6453 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6454 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
6456 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6457 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6459 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6460 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6461 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6462 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
6463 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
6465 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6466 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6467 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6468 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6469 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6470 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
6471 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
6473 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6474 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6475 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6476 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
6477 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
6479 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6480 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6481 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6482 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
6483 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
6485 /* Skylake plane registers */
6487 #define _PLANE_CTL_1_A 0x70180
6488 #define _PLANE_CTL_2_A 0x70280
6489 #define _PLANE_CTL_3_A 0x70380
6490 #define PLANE_CTL_ENABLE (1 << 31)
6491 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
6492 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6494 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6495 * expanded to include bit 23 as well. However, the shift-24 based values
6496 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6498 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
6499 #define PLANE_CTL_FORMAT_YUV422 (0 << 24)
6500 #define PLANE_CTL_FORMAT_NV12 (1 << 24)
6501 #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
6502 #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
6503 #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
6504 #define PLANE_CTL_FORMAT_AYUV (8 << 24)
6505 #define PLANE_CTL_FORMAT_INDEXED (12 << 24)
6506 #define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
6507 #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
6508 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
6509 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
6510 #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
6511 #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
6512 #define PLANE_CTL_ORDER_BGRX (0 << 20)
6513 #define PLANE_CTL_ORDER_RGBX (1 << 20)
6514 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6515 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6516 #define PLANE_CTL_YUV422_YUYV (0 << 16)
6517 #define PLANE_CTL_YUV422_UYVY (1 << 16)
6518 #define PLANE_CTL_YUV422_YVYU (2 << 16)
6519 #define PLANE_CTL_YUV422_VYUY (3 << 16)
6520 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
6521 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
6522 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
6523 #define PLANE_CTL_TILED_MASK (0x7 << 10)
6524 #define PLANE_CTL_TILED_LINEAR (0 << 10)
6525 #define PLANE_CTL_TILED_X (1 << 10)
6526 #define PLANE_CTL_TILED_Y (4 << 10)
6527 #define PLANE_CTL_TILED_YF (5 << 10)
6528 #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
6529 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
6530 #define PLANE_CTL_ALPHA_DISABLE (0 << 4)
6531 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
6532 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
6533 #define PLANE_CTL_ROTATE_MASK 0x3
6534 #define PLANE_CTL_ROTATE_0 0x0
6535 #define PLANE_CTL_ROTATE_90 0x1
6536 #define PLANE_CTL_ROTATE_180 0x2
6537 #define PLANE_CTL_ROTATE_270 0x3
6538 #define _PLANE_STRIDE_1_A 0x70188
6539 #define _PLANE_STRIDE_2_A 0x70288
6540 #define _PLANE_STRIDE_3_A 0x70388
6541 #define _PLANE_POS_1_A 0x7018c
6542 #define _PLANE_POS_2_A 0x7028c
6543 #define _PLANE_POS_3_A 0x7038c
6544 #define _PLANE_SIZE_1_A 0x70190
6545 #define _PLANE_SIZE_2_A 0x70290
6546 #define _PLANE_SIZE_3_A 0x70390
6547 #define _PLANE_SURF_1_A 0x7019c
6548 #define _PLANE_SURF_2_A 0x7029c
6549 #define _PLANE_SURF_3_A 0x7039c
6550 #define _PLANE_OFFSET_1_A 0x701a4
6551 #define _PLANE_OFFSET_2_A 0x702a4
6552 #define _PLANE_OFFSET_3_A 0x703a4
6553 #define _PLANE_KEYVAL_1_A 0x70194
6554 #define _PLANE_KEYVAL_2_A 0x70294
6555 #define _PLANE_KEYMSK_1_A 0x70198
6556 #define _PLANE_KEYMSK_2_A 0x70298
6557 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
6558 #define _PLANE_KEYMAX_1_A 0x701a0
6559 #define _PLANE_KEYMAX_2_A 0x702a0
6560 #define PLANE_KEYMAX_ALPHA_SHIFT 24
6561 #define _PLANE_AUX_DIST_1_A 0x701c0
6562 #define _PLANE_AUX_DIST_2_A 0x702c0
6563 #define _PLANE_AUX_OFFSET_1_A 0x701c4
6564 #define _PLANE_AUX_OFFSET_2_A 0x702c4
6565 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
6566 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
6567 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
6568 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
6569 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6570 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
6571 #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
6572 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
6573 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
6574 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
6575 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
6576 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
6577 #define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
6578 #define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
6579 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
6580 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
6581 #define _PLANE_BUF_CFG_1_A 0x7027c
6582 #define _PLANE_BUF_CFG_2_A 0x7037c
6583 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
6584 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
6587 #define _PLANE_CTL_1_B 0x71180
6588 #define _PLANE_CTL_2_B 0x71280
6589 #define _PLANE_CTL_3_B 0x71380
6590 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6591 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6592 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6593 #define PLANE_CTL(pipe, plane) \
6594 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6596 #define _PLANE_STRIDE_1_B 0x71188
6597 #define _PLANE_STRIDE_2_B 0x71288
6598 #define _PLANE_STRIDE_3_B 0x71388
6599 #define _PLANE_STRIDE_1(pipe) \
6600 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6601 #define _PLANE_STRIDE_2(pipe) \
6602 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6603 #define _PLANE_STRIDE_3(pipe) \
6604 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6605 #define PLANE_STRIDE(pipe, plane) \
6606 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6608 #define _PLANE_POS_1_B 0x7118c
6609 #define _PLANE_POS_2_B 0x7128c
6610 #define _PLANE_POS_3_B 0x7138c
6611 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6612 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6613 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6614 #define PLANE_POS(pipe, plane) \
6615 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6617 #define _PLANE_SIZE_1_B 0x71190
6618 #define _PLANE_SIZE_2_B 0x71290
6619 #define _PLANE_SIZE_3_B 0x71390
6620 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6621 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6622 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6623 #define PLANE_SIZE(pipe, plane) \
6624 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6626 #define _PLANE_SURF_1_B 0x7119c
6627 #define _PLANE_SURF_2_B 0x7129c
6628 #define _PLANE_SURF_3_B 0x7139c
6629 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6630 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6631 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6632 #define PLANE_SURF(pipe, plane) \
6633 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6635 #define _PLANE_OFFSET_1_B 0x711a4
6636 #define _PLANE_OFFSET_2_B 0x712a4
6637 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6638 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6639 #define PLANE_OFFSET(pipe, plane) \
6640 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6642 #define _PLANE_KEYVAL_1_B 0x71194
6643 #define _PLANE_KEYVAL_2_B 0x71294
6644 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6645 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6646 #define PLANE_KEYVAL(pipe, plane) \
6647 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6649 #define _PLANE_KEYMSK_1_B 0x71198
6650 #define _PLANE_KEYMSK_2_B 0x71298
6651 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6652 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6653 #define PLANE_KEYMSK(pipe, plane) \
6654 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6656 #define _PLANE_KEYMAX_1_B 0x711a0
6657 #define _PLANE_KEYMAX_2_B 0x712a0
6658 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6659 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6660 #define PLANE_KEYMAX(pipe, plane) \
6661 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6663 #define _PLANE_BUF_CFG_1_B 0x7127c
6664 #define _PLANE_BUF_CFG_2_B 0x7137c
6665 #define SKL_DDB_ENTRY_MASK 0x3FF
6666 #define ICL_DDB_ENTRY_MASK 0x7FF
6667 #define DDB_ENTRY_END_SHIFT 16
6668 #define _PLANE_BUF_CFG_1(pipe) \
6669 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6670 #define _PLANE_BUF_CFG_2(pipe) \
6671 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6672 #define PLANE_BUF_CFG(pipe, plane) \
6673 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
6675 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
6676 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
6677 #define _PLANE_NV12_BUF_CFG_1(pipe) \
6678 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6679 #define _PLANE_NV12_BUF_CFG_2(pipe) \
6680 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6681 #define PLANE_NV12_BUF_CFG(pipe, plane) \
6682 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6684 #define _PLANE_AUX_DIST_1_B 0x711c0
6685 #define _PLANE_AUX_DIST_2_B 0x712c0
6686 #define _PLANE_AUX_DIST_1(pipe) \
6687 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6688 #define _PLANE_AUX_DIST_2(pipe) \
6689 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6690 #define PLANE_AUX_DIST(pipe, plane) \
6691 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6693 #define _PLANE_AUX_OFFSET_1_B 0x711c4
6694 #define _PLANE_AUX_OFFSET_2_B 0x712c4
6695 #define _PLANE_AUX_OFFSET_1(pipe) \
6696 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6697 #define _PLANE_AUX_OFFSET_2(pipe) \
6698 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6699 #define PLANE_AUX_OFFSET(pipe, plane) \
6700 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6702 #define _PLANE_COLOR_CTL_1_B 0x711CC
6703 #define _PLANE_COLOR_CTL_2_B 0x712CC
6704 #define _PLANE_COLOR_CTL_3_B 0x713CC
6705 #define _PLANE_COLOR_CTL_1(pipe) \
6706 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6707 #define _PLANE_COLOR_CTL_2(pipe) \
6708 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6709 #define PLANE_COLOR_CTL(pipe, plane) \
6710 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6712 #/* SKL new cursor registers */
6713 #define _CUR_BUF_CFG_A 0x7017c
6714 #define _CUR_BUF_CFG_B 0x7117c
6715 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
6718 #define VGACNTRL _MMIO(0x71400)
6719 # define VGA_DISP_DISABLE (1 << 31)
6720 # define VGA_2X_MODE (1 << 30)
6721 # define VGA_PIPE_B_SELECT (1 << 29)
6723 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
6727 #define CPU_VGACNTRL _MMIO(0x41000)
6729 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
6730 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
6731 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
6732 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
6733 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
6734 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
6735 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
6736 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
6737 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
6738 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
6739 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
6741 /* refresh rate hardware control */
6742 #define RR_HW_CTL _MMIO(0x45300)
6743 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
6744 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
6746 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
6747 #define FDI_PLL_FB_CLOCK_MASK 0xff
6748 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
6749 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
6750 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
6751 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
6752 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
6754 #define PCH_3DCGDIS0 _MMIO(0x46020)
6755 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
6756 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
6758 #define PCH_3DCGDIS1 _MMIO(0x46024)
6759 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
6761 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
6762 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
6763 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
6764 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
6767 #define _PIPEA_DATA_M1 0x60030
6768 #define PIPE_DATA_M1_OFFSET 0
6769 #define _PIPEA_DATA_N1 0x60034
6770 #define PIPE_DATA_N1_OFFSET 0
6772 #define _PIPEA_DATA_M2 0x60038
6773 #define PIPE_DATA_M2_OFFSET 0
6774 #define _PIPEA_DATA_N2 0x6003c
6775 #define PIPE_DATA_N2_OFFSET 0
6777 #define _PIPEA_LINK_M1 0x60040
6778 #define PIPE_LINK_M1_OFFSET 0
6779 #define _PIPEA_LINK_N1 0x60044
6780 #define PIPE_LINK_N1_OFFSET 0
6782 #define _PIPEA_LINK_M2 0x60048
6783 #define PIPE_LINK_M2_OFFSET 0
6784 #define _PIPEA_LINK_N2 0x6004c
6785 #define PIPE_LINK_N2_OFFSET 0
6787 /* PIPEB timing regs are same start from 0x61000 */
6789 #define _PIPEB_DATA_M1 0x61030
6790 #define _PIPEB_DATA_N1 0x61034
6791 #define _PIPEB_DATA_M2 0x61038
6792 #define _PIPEB_DATA_N2 0x6103c
6793 #define _PIPEB_LINK_M1 0x61040
6794 #define _PIPEB_LINK_N1 0x61044
6795 #define _PIPEB_LINK_M2 0x61048
6796 #define _PIPEB_LINK_N2 0x6104c
6798 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
6799 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
6800 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
6801 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
6802 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
6803 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
6804 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
6805 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
6807 /* CPU panel fitter */
6808 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
6809 #define _PFA_CTL_1 0x68080
6810 #define _PFB_CTL_1 0x68880
6811 #define PF_ENABLE (1 << 31)
6812 #define PF_PIPE_SEL_MASK_IVB (3 << 29)
6813 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
6814 #define PF_FILTER_MASK (3 << 23)
6815 #define PF_FILTER_PROGRAMMED (0 << 23)
6816 #define PF_FILTER_MED_3x3 (1 << 23)
6817 #define PF_FILTER_EDGE_ENHANCE (2 << 23)
6818 #define PF_FILTER_EDGE_SOFTEN (3 << 23)
6819 #define _PFA_WIN_SZ 0x68074
6820 #define _PFB_WIN_SZ 0x68874
6821 #define _PFA_WIN_POS 0x68070
6822 #define _PFB_WIN_POS 0x68870
6823 #define _PFA_VSCALE 0x68084
6824 #define _PFB_VSCALE 0x68884
6825 #define _PFA_HSCALE 0x68090
6826 #define _PFB_HSCALE 0x68890
6828 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
6829 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
6830 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
6831 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
6832 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
6834 #define _PSA_CTL 0x68180
6835 #define _PSB_CTL 0x68980
6836 #define PS_ENABLE (1 << 31)
6837 #define _PSA_WIN_SZ 0x68174
6838 #define _PSB_WIN_SZ 0x68974
6839 #define _PSA_WIN_POS 0x68170
6840 #define _PSB_WIN_POS 0x68970
6842 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
6843 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
6844 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
6849 #define _PS_1A_CTRL 0x68180
6850 #define _PS_2A_CTRL 0x68280
6851 #define _PS_1B_CTRL 0x68980
6852 #define _PS_2B_CTRL 0x68A80
6853 #define _PS_1C_CTRL 0x69180
6854 #define PS_SCALER_EN (1 << 31)
6855 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
6856 #define SKL_PS_SCALER_MODE_DYN (0 << 28)
6857 #define SKL_PS_SCALER_MODE_HQ (1 << 28)
6858 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
6859 #define PS_SCALER_MODE_PLANAR (1 << 29)
6860 #define PS_SCALER_MODE_PACKED (0 << 29)
6861 #define PS_PLANE_SEL_MASK (7 << 25)
6862 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
6863 #define PS_FILTER_MASK (3 << 23)
6864 #define PS_FILTER_MEDIUM (0 << 23)
6865 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
6866 #define PS_FILTER_BILINEAR (3 << 23)
6867 #define PS_VERT3TAP (1 << 21)
6868 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
6869 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
6870 #define PS_PWRUP_PROGRESS (1 << 17)
6871 #define PS_V_FILTER_BYPASS (1 << 8)
6872 #define PS_VADAPT_EN (1 << 7)
6873 #define PS_VADAPT_MODE_MASK (3 << 5)
6874 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
6875 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
6876 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
6878 #define _PS_PWR_GATE_1A 0x68160
6879 #define _PS_PWR_GATE_2A 0x68260
6880 #define _PS_PWR_GATE_1B 0x68960
6881 #define _PS_PWR_GATE_2B 0x68A60
6882 #define _PS_PWR_GATE_1C 0x69160
6883 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
6884 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
6885 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
6886 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
6887 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
6888 #define PS_PWR_GATE_SLPEN_8 0
6889 #define PS_PWR_GATE_SLPEN_16 1
6890 #define PS_PWR_GATE_SLPEN_24 2
6891 #define PS_PWR_GATE_SLPEN_32 3
6893 #define _PS_WIN_POS_1A 0x68170
6894 #define _PS_WIN_POS_2A 0x68270
6895 #define _PS_WIN_POS_1B 0x68970
6896 #define _PS_WIN_POS_2B 0x68A70
6897 #define _PS_WIN_POS_1C 0x69170
6899 #define _PS_WIN_SZ_1A 0x68174
6900 #define _PS_WIN_SZ_2A 0x68274
6901 #define _PS_WIN_SZ_1B 0x68974
6902 #define _PS_WIN_SZ_2B 0x68A74
6903 #define _PS_WIN_SZ_1C 0x69174
6905 #define _PS_VSCALE_1A 0x68184
6906 #define _PS_VSCALE_2A 0x68284
6907 #define _PS_VSCALE_1B 0x68984
6908 #define _PS_VSCALE_2B 0x68A84
6909 #define _PS_VSCALE_1C 0x69184
6911 #define _PS_HSCALE_1A 0x68190
6912 #define _PS_HSCALE_2A 0x68290
6913 #define _PS_HSCALE_1B 0x68990
6914 #define _PS_HSCALE_2B 0x68A90
6915 #define _PS_HSCALE_1C 0x69190
6917 #define _PS_VPHASE_1A 0x68188
6918 #define _PS_VPHASE_2A 0x68288
6919 #define _PS_VPHASE_1B 0x68988
6920 #define _PS_VPHASE_2B 0x68A88
6921 #define _PS_VPHASE_1C 0x69188
6922 #define PS_Y_PHASE(x) ((x) << 16)
6923 #define PS_UV_RGB_PHASE(x) ((x) << 0)
6924 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
6925 #define PS_PHASE_TRIP (1 << 0)
6927 #define _PS_HPHASE_1A 0x68194
6928 #define _PS_HPHASE_2A 0x68294
6929 #define _PS_HPHASE_1B 0x68994
6930 #define _PS_HPHASE_2B 0x68A94
6931 #define _PS_HPHASE_1C 0x69194
6933 #define _PS_ECC_STAT_1A 0x681D0
6934 #define _PS_ECC_STAT_2A 0x682D0
6935 #define _PS_ECC_STAT_1B 0x689D0
6936 #define _PS_ECC_STAT_2B 0x68AD0
6937 #define _PS_ECC_STAT_1C 0x691D0
6939 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
6940 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
6941 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
6942 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
6943 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
6944 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
6945 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
6946 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
6947 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
6948 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
6949 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
6950 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
6951 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
6952 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
6953 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
6954 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
6955 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
6956 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
6957 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
6958 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
6959 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
6960 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
6961 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
6962 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
6963 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
6964 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
6965 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
6966 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
6968 /* legacy palette */
6969 #define _LGC_PALETTE_A 0x4a000
6970 #define _LGC_PALETTE_B 0x4a800
6971 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
6973 #define _GAMMA_MODE_A 0x4a480
6974 #define _GAMMA_MODE_B 0x4ac80
6975 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
6976 #define GAMMA_MODE_MODE_MASK (3 << 0)
6977 #define GAMMA_MODE_MODE_8BIT (0 << 0)
6978 #define GAMMA_MODE_MODE_10BIT (1 << 0)
6979 #define GAMMA_MODE_MODE_12BIT (2 << 0)
6980 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
6983 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
6984 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
6985 #define CSR_HTP_ADDR_SKL 0x00500034
6986 #define CSR_SSP_BASE _MMIO(0x8F074)
6987 #define CSR_HTP_SKL _MMIO(0x8F004)
6988 #define CSR_LAST_WRITE _MMIO(0x8F034)
6989 #define CSR_LAST_WRITE_VALUE 0xc003b400
6990 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
6991 #define CSR_MMIO_START_RANGE 0x80000
6992 #define CSR_MMIO_END_RANGE 0x8FFFF
6993 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
6994 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
6995 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
6998 #define DE_MASTER_IRQ_CONTROL (1 << 31)
6999 #define DE_SPRITEB_FLIP_DONE (1 << 29)
7000 #define DE_SPRITEA_FLIP_DONE (1 << 28)
7001 #define DE_PLANEB_FLIP_DONE (1 << 27)
7002 #define DE_PLANEA_FLIP_DONE (1 << 26)
7003 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7004 #define DE_PCU_EVENT (1 << 25)
7005 #define DE_GTT_FAULT (1 << 24)
7006 #define DE_POISON (1 << 23)
7007 #define DE_PERFORM_COUNTER (1 << 22)
7008 #define DE_PCH_EVENT (1 << 21)
7009 #define DE_AUX_CHANNEL_A (1 << 20)
7010 #define DE_DP_A_HOTPLUG (1 << 19)
7011 #define DE_GSE (1 << 18)
7012 #define DE_PIPEB_VBLANK (1 << 15)
7013 #define DE_PIPEB_EVEN_FIELD (1 << 14)
7014 #define DE_PIPEB_ODD_FIELD (1 << 13)
7015 #define DE_PIPEB_LINE_COMPARE (1 << 12)
7016 #define DE_PIPEB_VSYNC (1 << 11)
7017 #define DE_PIPEB_CRC_DONE (1 << 10)
7018 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
7019 #define DE_PIPEA_VBLANK (1 << 7)
7020 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
7021 #define DE_PIPEA_EVEN_FIELD (1 << 6)
7022 #define DE_PIPEA_ODD_FIELD (1 << 5)
7023 #define DE_PIPEA_LINE_COMPARE (1 << 4)
7024 #define DE_PIPEA_VSYNC (1 << 3)
7025 #define DE_PIPEA_CRC_DONE (1 << 2)
7026 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
7027 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
7028 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
7030 /* More Ivybridge lolz */
7031 #define DE_ERR_INT_IVB (1 << 30)
7032 #define DE_GSE_IVB (1 << 29)
7033 #define DE_PCH_EVENT_IVB (1 << 28)
7034 #define DE_DP_A_HOTPLUG_IVB (1 << 27)
7035 #define DE_AUX_CHANNEL_A_IVB (1 << 26)
7036 #define DE_EDP_PSR_INT_HSW (1 << 19)
7037 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
7038 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
7039 #define DE_PIPEC_VBLANK_IVB (1 << 10)
7040 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
7041 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
7042 #define DE_PIPEB_VBLANK_IVB (1 << 5)
7043 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
7044 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
7045 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
7046 #define DE_PIPEA_VBLANK_IVB (1 << 0)
7047 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
7049 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
7050 #define MASTER_INTERRUPT_ENABLE (1 << 31)
7052 #define DEISR _MMIO(0x44000)
7053 #define DEIMR _MMIO(0x44004)
7054 #define DEIIR _MMIO(0x44008)
7055 #define DEIER _MMIO(0x4400c)
7057 #define GTISR _MMIO(0x44010)
7058 #define GTIMR _MMIO(0x44014)
7059 #define GTIIR _MMIO(0x44018)
7060 #define GTIER _MMIO(0x4401c)
7062 #define GEN8_MASTER_IRQ _MMIO(0x44200)
7063 #define GEN8_MASTER_IRQ_CONTROL (1 << 31)
7064 #define GEN8_PCU_IRQ (1 << 30)
7065 #define GEN8_DE_PCH_IRQ (1 << 23)
7066 #define GEN8_DE_MISC_IRQ (1 << 22)
7067 #define GEN8_DE_PORT_IRQ (1 << 20)
7068 #define GEN8_DE_PIPE_C_IRQ (1 << 18)
7069 #define GEN8_DE_PIPE_B_IRQ (1 << 17)
7070 #define GEN8_DE_PIPE_A_IRQ (1 << 16)
7071 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
7072 #define GEN8_GT_VECS_IRQ (1 << 6)
7073 #define GEN8_GT_GUC_IRQ (1 << 5)
7074 #define GEN8_GT_PM_IRQ (1 << 4)
7075 #define GEN8_GT_VCS2_IRQ (1 << 3)
7076 #define GEN8_GT_VCS1_IRQ (1 << 2)
7077 #define GEN8_GT_BCS_IRQ (1 << 1)
7078 #define GEN8_GT_RCS_IRQ (1 << 0)
7080 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7081 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7082 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7083 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7085 #define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31)
7086 #define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30)
7087 #define GEN9_GUC_DISPLAY_EVENT (1 << 29)
7088 #define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28)
7089 #define GEN9_GUC_IOMMU_MSG_EVENT (1 << 27)
7090 #define GEN9_GUC_DB_RING_EVENT (1 << 26)
7091 #define GEN9_GUC_DMA_DONE_EVENT (1 << 25)
7092 #define GEN9_GUC_FATAL_ERROR_EVENT (1 << 24)
7093 #define GEN9_GUC_NOTIFICATION_EVENT (1 << 23)
7095 #define GEN8_RCS_IRQ_SHIFT 0
7096 #define GEN8_BCS_IRQ_SHIFT 16
7097 #define GEN8_VCS1_IRQ_SHIFT 0
7098 #define GEN8_VCS2_IRQ_SHIFT 16
7099 #define GEN8_VECS_IRQ_SHIFT 0
7100 #define GEN8_WD_IRQ_SHIFT 16
7102 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7103 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7104 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7105 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7106 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
7107 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
7108 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
7109 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
7110 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
7111 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
7112 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
7113 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
7114 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
7115 #define GEN8_PIPE_VSYNC (1 << 1)
7116 #define GEN8_PIPE_VBLANK (1 << 0)
7117 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
7118 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
7119 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
7120 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
7121 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
7122 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
7123 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
7124 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
7125 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
7126 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
7127 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7128 (GEN8_PIPE_CURSOR_FAULT | \
7129 GEN8_PIPE_SPRITE_FAULT | \
7130 GEN8_PIPE_PRIMARY_FAULT)
7131 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7132 (GEN9_PIPE_CURSOR_FAULT | \
7133 GEN9_PIPE_PLANE4_FAULT | \
7134 GEN9_PIPE_PLANE3_FAULT | \
7135 GEN9_PIPE_PLANE2_FAULT | \
7136 GEN9_PIPE_PLANE1_FAULT)
7138 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7139 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7140 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7141 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7142 #define ICL_AUX_CHANNEL_E (1 << 29)
7143 #define CNL_AUX_CHANNEL_F (1 << 28)
7144 #define GEN9_AUX_CHANNEL_D (1 << 27)
7145 #define GEN9_AUX_CHANNEL_C (1 << 26)
7146 #define GEN9_AUX_CHANNEL_B (1 << 25)
7147 #define BXT_DE_PORT_HP_DDIC (1 << 5)
7148 #define BXT_DE_PORT_HP_DDIB (1 << 4)
7149 #define BXT_DE_PORT_HP_DDIA (1 << 3)
7150 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
7151 BXT_DE_PORT_HP_DDIB | \
7152 BXT_DE_PORT_HP_DDIC)
7153 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
7154 #define BXT_DE_PORT_GMBUS (1 << 1)
7155 #define GEN8_AUX_CHANNEL_A (1 << 0)
7157 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
7158 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
7159 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7160 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7161 #define GEN8_DE_MISC_GSE (1 << 27)
7162 #define GEN8_DE_EDP_PSR (1 << 19)
7164 #define GEN8_PCU_ISR _MMIO(0x444e0)
7165 #define GEN8_PCU_IMR _MMIO(0x444e4)
7166 #define GEN8_PCU_IIR _MMIO(0x444e8)
7167 #define GEN8_PCU_IER _MMIO(0x444ec)
7169 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
7170 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
7171 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
7172 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
7173 #define GEN11_GU_MISC_GSE (1 << 27)
7175 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
7176 #define GEN11_MASTER_IRQ (1 << 31)
7177 #define GEN11_PCU_IRQ (1 << 30)
7178 #define GEN11_GU_MISC_IRQ (1 << 29)
7179 #define GEN11_DISPLAY_IRQ (1 << 16)
7180 #define GEN11_GT_DW_IRQ(x) (1 << (x))
7181 #define GEN11_GT_DW1_IRQ (1 << 1)
7182 #define GEN11_GT_DW0_IRQ (1 << 0)
7184 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
7185 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
7186 #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
7187 #define GEN11_DE_PCH_IRQ (1 << 23)
7188 #define GEN11_DE_MISC_IRQ (1 << 22)
7189 #define GEN11_DE_HPD_IRQ (1 << 21)
7190 #define GEN11_DE_PORT_IRQ (1 << 20)
7191 #define GEN11_DE_PIPE_C (1 << 18)
7192 #define GEN11_DE_PIPE_B (1 << 17)
7193 #define GEN11_DE_PIPE_A (1 << 16)
7195 #define GEN11_DE_HPD_ISR _MMIO(0x44470)
7196 #define GEN11_DE_HPD_IMR _MMIO(0x44474)
7197 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
7198 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
7199 #define GEN11_TC4_HOTPLUG (1 << 19)
7200 #define GEN11_TC3_HOTPLUG (1 << 18)
7201 #define GEN11_TC2_HOTPLUG (1 << 17)
7202 #define GEN11_TC1_HOTPLUG (1 << 16)
7203 #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
7204 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \
7205 GEN11_TC3_HOTPLUG | \
7206 GEN11_TC2_HOTPLUG | \
7208 #define GEN11_TBT4_HOTPLUG (1 << 3)
7209 #define GEN11_TBT3_HOTPLUG (1 << 2)
7210 #define GEN11_TBT2_HOTPLUG (1 << 1)
7211 #define GEN11_TBT1_HOTPLUG (1 << 0)
7212 #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
7213 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \
7214 GEN11_TBT3_HOTPLUG | \
7215 GEN11_TBT2_HOTPLUG | \
7218 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
7219 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
7220 #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)
7221 #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
7222 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
7223 #define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4)
7225 #define GEN11_GT_INTR_DW0 _MMIO(0x190018)
7226 #define GEN11_CSME (31)
7227 #define GEN11_GUNIT (28)
7228 #define GEN11_GUC (25)
7229 #define GEN11_WDPERF (20)
7230 #define GEN11_KCR (19)
7231 #define GEN11_GTPM (16)
7232 #define GEN11_BCS (15)
7233 #define GEN11_RCS0 (0)
7235 #define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
7236 #define GEN11_VECS(x) (31 - (x))
7237 #define GEN11_VCS(x) (x)
7239 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
7241 #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
7242 #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
7243 #define GEN11_INTR_DATA_VALID (1 << 31)
7244 #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
7245 #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
7246 #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
7248 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
7250 #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
7251 #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
7253 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
7255 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
7256 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
7257 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
7258 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7259 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
7260 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
7262 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
7263 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
7264 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
7265 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
7266 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
7267 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
7268 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
7269 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7270 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7272 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
7273 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7274 #define ILK_ELPIN_409_SELECT (1 << 25)
7275 #define ILK_DPARB_GATE (1 << 22)
7276 #define ILK_VSDPFD_FULL (1 << 21)
7277 #define FUSE_STRAP _MMIO(0x42014)
7278 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
7279 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
7280 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
7281 #define IVB_PIPE_C_DISABLE (1 << 28)
7282 #define ILK_HDCP_DISABLE (1 << 25)
7283 #define ILK_eDP_A_DISABLE (1 << 24)
7284 #define HSW_CDCLK_LIMIT (1 << 24)
7285 #define ILK_DESKTOP (1 << 23)
7287 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
7288 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
7289 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
7290 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
7291 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
7292 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
7294 #define IVB_CHICKEN3 _MMIO(0x4200c)
7295 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
7296 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
7298 #define CHICKEN_PAR1_1 _MMIO(0x42080)
7299 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
7300 #define DPA_MASK_VBLANK_SRD (1 << 15)
7301 #define FORCE_ARB_IDLE_PLANES (1 << 14)
7302 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
7304 #define CHICKEN_PAR2_1 _MMIO(0x42090)
7305 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
7307 #define CHICKEN_MISC_2 _MMIO(0x42084)
7308 #define CNL_COMP_PWR_DOWN (1 << 23)
7309 #define GLK_CL2_PWR_DOWN (1 << 12)
7310 #define GLK_CL1_PWR_DOWN (1 << 11)
7311 #define GLK_CL0_PWR_DOWN (1 << 10)
7313 #define CHICKEN_MISC_4 _MMIO(0x4208c)
7314 #define FBC_STRIDE_OVERRIDE (1 << 13)
7315 #define FBC_STRIDE_MASK 0x1FFF
7317 #define _CHICKEN_PIPESL_1_A 0x420b0
7318 #define _CHICKEN_PIPESL_1_B 0x420b4
7319 #define HSW_FBCQ_DIS (1 << 22)
7320 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
7321 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7323 #define CHICKEN_TRANS_A 0x420c0
7324 #define CHICKEN_TRANS_B 0x420c4
7325 #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
7326 #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
7327 #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
7328 #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
7329 #define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */
7330 #define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */
7331 #define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15)
7332 #define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12)
7334 #define DISP_ARB_CTL _MMIO(0x45000)
7335 #define DISP_FBC_MEMORY_WAKE (1 << 31)
7336 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13)
7337 #define DISP_FBC_WM_DIS (1 << 15)
7338 #define DISP_ARB_CTL2 _MMIO(0x45004)
7339 #define DISP_DATA_PARTITION_5_6 (1 << 6)
7340 #define DISP_IPC_ENABLE (1 << 3)
7341 #define DBUF_CTL _MMIO(0x45008)
7342 #define DBUF_CTL_S1 _MMIO(0x45008)
7343 #define DBUF_CTL_S2 _MMIO(0x44FE8)
7344 #define DBUF_POWER_REQUEST (1 << 31)
7345 #define DBUF_POWER_STATE (1 << 30)
7346 #define GEN7_MSG_CTL _MMIO(0x45010)
7347 #define WAIT_FOR_PCH_RESET_ACK (1 << 1)
7348 #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
7349 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
7350 #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
7352 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
7353 #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
7354 #define MASK_WAKEMEM (1 << 13)
7355 #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
7357 #define SKL_DFSM _MMIO(0x51000)
7358 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
7359 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
7360 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
7361 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
7362 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
7363 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
7364 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
7365 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
7367 #define SKL_DSSM _MMIO(0x51004)
7368 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
7369 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
7370 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
7371 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
7372 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
7374 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
7375 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
7377 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
7378 #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
7379 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
7381 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
7382 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
7383 #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
7384 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
7385 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
7386 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7387 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7388 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7389 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7392 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
7393 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
7394 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
7396 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
7397 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
7398 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
7399 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
7400 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
7402 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
7403 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
7405 #define HIZ_CHICKEN _MMIO(0x7018)
7406 # define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
7407 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3)
7409 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
7410 #define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
7412 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7413 #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
7415 #define GEN7_SARCHKMD _MMIO(0xB000)
7416 #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
7417 #define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
7419 #define GEN7_L3SQCREG1 _MMIO(0xB010)
7420 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
7422 #define GEN8_L3SQCREG1 _MMIO(0xB100)
7424 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7425 * Using the formula in BSpec leads to a hang, while the formula here works
7426 * fine and matches the formulas for all other platforms. A BSpec change
7427 * request has been filed to clarify this.
7429 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
7430 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
7431 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
7433 #define GEN7_L3CNTLREG1 _MMIO(0xB01C)
7434 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
7435 #define GEN7_L3AGDIS (1 << 19)
7436 #define GEN7_L3CNTLREG2 _MMIO(0xB020)
7437 #define GEN7_L3CNTLREG3 _MMIO(0xB024)
7439 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
7440 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
7441 #define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
7442 #define GEN11_I2M_WRITE_DISABLE (1 << 28)
7444 #define GEN7_L3SQCREG4 _MMIO(0xb034)
7445 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
7447 #define GEN8_L3SQCREG4 _MMIO(0xb118)
7448 #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
7449 #define GEN8_LQSC_RO_PERF_DIS (1 << 27)
7450 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
7453 #define HDC_CHICKEN0 _MMIO(0x7300)
7454 #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
7455 #define ICL_HDC_MODE _MMIO(0xE5F4)
7456 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
7457 #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
7458 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
7459 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
7460 #define HDC_FORCE_NON_COHERENT (1 << 4)
7461 #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
7463 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
7466 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
7467 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
7469 #define GEN9_WM_CHICKEN3 _MMIO(0x5588)
7470 #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
7472 /* WaCatErrorRejectionIssue */
7473 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
7474 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
7476 #define HSW_SCRATCH1 _MMIO(0xb038)
7477 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
7479 #define BDW_SCRATCH1 _MMIO(0xb11c)
7480 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
7483 #define _PIPEA_CHICKEN 0x70038
7484 #define _PIPEB_CHICKEN 0x71038
7485 #define _PIPEC_CHICKEN 0x72038
7486 #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
7487 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
7492 #define PCH_DISPLAY_BASE 0xc0000u
7494 /* south display engine interrupt: IBX */
7495 #define SDE_AUDIO_POWER_D (1 << 27)
7496 #define SDE_AUDIO_POWER_C (1 << 26)
7497 #define SDE_AUDIO_POWER_B (1 << 25)
7498 #define SDE_AUDIO_POWER_SHIFT (25)
7499 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
7500 #define SDE_GMBUS (1 << 24)
7501 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
7502 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
7503 #define SDE_AUDIO_HDCP_MASK (3 << 22)
7504 #define SDE_AUDIO_TRANSB (1 << 21)
7505 #define SDE_AUDIO_TRANSA (1 << 20)
7506 #define SDE_AUDIO_TRANS_MASK (3 << 20)
7507 #define SDE_POISON (1 << 19)
7509 #define SDE_FDI_RXB (1 << 17)
7510 #define SDE_FDI_RXA (1 << 16)
7511 #define SDE_FDI_MASK (3 << 16)
7512 #define SDE_AUXD (1 << 15)
7513 #define SDE_AUXC (1 << 14)
7514 #define SDE_AUXB (1 << 13)
7515 #define SDE_AUX_MASK (7 << 13)
7517 #define SDE_CRT_HOTPLUG (1 << 11)
7518 #define SDE_PORTD_HOTPLUG (1 << 10)
7519 #define SDE_PORTC_HOTPLUG (1 << 9)
7520 #define SDE_PORTB_HOTPLUG (1 << 8)
7521 #define SDE_SDVOB_HOTPLUG (1 << 6)
7522 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
7523 SDE_SDVOB_HOTPLUG | \
7524 SDE_PORTB_HOTPLUG | \
7525 SDE_PORTC_HOTPLUG | \
7527 #define SDE_TRANSB_CRC_DONE (1 << 5)
7528 #define SDE_TRANSB_CRC_ERR (1 << 4)
7529 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
7530 #define SDE_TRANSA_CRC_DONE (1 << 2)
7531 #define SDE_TRANSA_CRC_ERR (1 << 1)
7532 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
7533 #define SDE_TRANS_MASK (0x3f)
7535 /* south display engine interrupt: CPT - CNP */
7536 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
7537 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
7538 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
7539 #define SDE_AUDIO_POWER_SHIFT_CPT 29
7540 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
7541 #define SDE_AUXD_CPT (1 << 27)
7542 #define SDE_AUXC_CPT (1 << 26)
7543 #define SDE_AUXB_CPT (1 << 25)
7544 #define SDE_AUX_MASK_CPT (7 << 25)
7545 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
7546 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
7547 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
7548 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
7549 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
7550 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
7551 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
7552 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
7553 SDE_SDVOB_HOTPLUG_CPT | \
7554 SDE_PORTD_HOTPLUG_CPT | \
7555 SDE_PORTC_HOTPLUG_CPT | \
7556 SDE_PORTB_HOTPLUG_CPT)
7557 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
7558 SDE_PORTD_HOTPLUG_CPT | \
7559 SDE_PORTC_HOTPLUG_CPT | \
7560 SDE_PORTB_HOTPLUG_CPT | \
7561 SDE_PORTA_HOTPLUG_SPT)
7562 #define SDE_GMBUS_CPT (1 << 17)
7563 #define SDE_ERROR_CPT (1 << 16)
7564 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
7565 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
7566 #define SDE_FDI_RXC_CPT (1 << 8)
7567 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
7568 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
7569 #define SDE_FDI_RXB_CPT (1 << 4)
7570 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
7571 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
7572 #define SDE_FDI_RXA_CPT (1 << 0)
7573 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
7574 SDE_AUDIO_CP_REQ_B_CPT | \
7575 SDE_AUDIO_CP_REQ_A_CPT)
7576 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
7577 SDE_AUDIO_CP_CHG_B_CPT | \
7578 SDE_AUDIO_CP_CHG_A_CPT)
7579 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
7583 /* south display engine interrupt: ICP */
7584 #define SDE_TC4_HOTPLUG_ICP (1 << 27)
7585 #define SDE_TC3_HOTPLUG_ICP (1 << 26)
7586 #define SDE_TC2_HOTPLUG_ICP (1 << 25)
7587 #define SDE_TC1_HOTPLUG_ICP (1 << 24)
7588 #define SDE_GMBUS_ICP (1 << 23)
7589 #define SDE_DDIB_HOTPLUG_ICP (1 << 17)
7590 #define SDE_DDIA_HOTPLUG_ICP (1 << 16)
7591 #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
7592 #define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
7593 #define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \
7594 SDE_DDIA_HOTPLUG_ICP)
7595 #define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \
7596 SDE_TC3_HOTPLUG_ICP | \
7597 SDE_TC2_HOTPLUG_ICP | \
7598 SDE_TC1_HOTPLUG_ICP)
7600 #define SDEISR _MMIO(0xc4000)
7601 #define SDEIMR _MMIO(0xc4004)
7602 #define SDEIIR _MMIO(0xc4008)
7603 #define SDEIER _MMIO(0xc400c)
7605 #define SERR_INT _MMIO(0xc4040)
7606 #define SERR_INT_POISON (1 << 31)
7607 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
7609 /* digital port hotplug */
7610 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
7611 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
7612 #define BXT_DDIA_HPD_INVERT (1 << 27)
7613 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
7614 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
7615 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
7616 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
7617 #define PORTD_HOTPLUG_ENABLE (1 << 20)
7618 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
7619 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
7620 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
7621 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
7622 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
7623 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
7624 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
7625 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
7626 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
7627 #define PORTC_HOTPLUG_ENABLE (1 << 12)
7628 #define BXT_DDIC_HPD_INVERT (1 << 11)
7629 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
7630 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
7631 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
7632 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
7633 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
7634 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
7635 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
7636 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
7637 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
7638 #define PORTB_HOTPLUG_ENABLE (1 << 4)
7639 #define BXT_DDIB_HPD_INVERT (1 << 3)
7640 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
7641 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
7642 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
7643 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
7644 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
7645 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
7646 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
7647 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
7648 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
7649 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
7650 BXT_DDIB_HPD_INVERT | \
7651 BXT_DDIC_HPD_INVERT)
7653 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
7654 #define PORTE_HOTPLUG_ENABLE (1 << 4)
7655 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
7656 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
7657 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
7658 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
7660 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
7661 * functionality covered in PCH_PORT_HOTPLUG is split into
7662 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
7665 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
7666 #define ICP_DDIB_HPD_ENABLE (1 << 7)
7667 #define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
7668 #define ICP_DDIB_HPD_NO_DETECT (0 << 4)
7669 #define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
7670 #define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
7671 #define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
7672 #define ICP_DDIA_HPD_ENABLE (1 << 3)
7673 #define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
7674 #define ICP_DDIA_HPD_NO_DETECT (0 << 0)
7675 #define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
7676 #define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
7677 #define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
7679 #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
7680 #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
7681 /* Icelake DSC Rate Control Range Parameter Registers */
7682 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
7683 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
7684 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
7685 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
7686 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
7687 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
7688 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
7689 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
7690 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
7691 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
7692 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
7693 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
7694 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7695 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
7696 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
7697 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7698 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
7699 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
7700 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7701 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
7702 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
7703 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7704 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
7705 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
7706 #define RC_BPG_OFFSET_SHIFT 10
7707 #define RC_MAX_QP_SHIFT 5
7708 #define RC_MIN_QP_SHIFT 0
7710 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
7711 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
7712 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
7713 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
7714 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
7715 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
7716 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
7717 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
7718 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
7719 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
7720 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
7721 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
7722 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7723 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
7724 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
7725 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7726 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
7727 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
7728 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7729 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
7730 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
7731 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7732 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
7733 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
7735 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
7736 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
7737 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
7738 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
7739 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
7740 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
7741 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
7742 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
7743 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
7744 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
7745 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
7746 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
7747 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7748 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
7749 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
7750 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7751 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
7752 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
7753 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7754 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
7755 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
7756 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7757 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
7758 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
7760 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
7761 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
7762 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
7763 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
7764 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
7765 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
7766 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
7767 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
7768 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
7769 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
7770 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
7771 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
7772 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7773 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
7774 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
7775 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7776 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
7777 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
7778 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7779 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
7780 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
7781 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7782 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
7783 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
7785 #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
7786 #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
7788 #define _PCH_DPLL_A 0xc6014
7789 #define _PCH_DPLL_B 0xc6018
7790 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
7792 #define _PCH_FPA0 0xc6040
7793 #define FP_CB_TUNE (0x3 << 22)
7794 #define _PCH_FPA1 0xc6044
7795 #define _PCH_FPB0 0xc6048
7796 #define _PCH_FPB1 0xc604c
7797 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
7798 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
7800 #define PCH_DPLL_TEST _MMIO(0xc606c)
7802 #define PCH_DREF_CONTROL _MMIO(0xC6200)
7803 #define DREF_CONTROL_MASK 0x7fc3
7804 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
7805 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
7806 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
7807 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
7808 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
7809 #define DREF_SSC_SOURCE_ENABLE (2 << 11)
7810 #define DREF_SSC_SOURCE_MASK (3 << 11)
7811 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
7812 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
7813 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
7814 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
7815 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
7816 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
7817 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
7818 #define DREF_SSC4_DOWNSPREAD (0 << 6)
7819 #define DREF_SSC4_CENTERSPREAD (1 << 6)
7820 #define DREF_SSC1_DISABLE (0 << 1)
7821 #define DREF_SSC1_ENABLE (1 << 1)
7822 #define DREF_SSC4_DISABLE (0)
7823 #define DREF_SSC4_ENABLE (1)
7825 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
7826 #define FDL_TP1_TIMER_SHIFT 12
7827 #define FDL_TP1_TIMER_MASK (3 << 12)
7828 #define FDL_TP2_TIMER_SHIFT 10
7829 #define FDL_TP2_TIMER_MASK (3 << 10)
7830 #define RAWCLK_FREQ_MASK 0x3ff
7831 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
7832 #define CNP_RAWCLK_DIV(div) ((div) << 16)
7833 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
7834 #define CNP_RAWCLK_FRAC(frac) ((frac) << 26)
7835 #define ICP_RAWCLK_DEN(den) ((den) << 26)
7836 #define ICP_RAWCLK_NUM(num) ((num) << 11)
7838 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
7840 #define PCH_SSC4_PARMS _MMIO(0xc6210)
7841 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
7843 #define PCH_DPLL_SEL _MMIO(0xc7000)
7844 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
7845 #define TRANS_DPLLA_SEL(pipe) 0
7846 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
7850 #define _PCH_TRANS_HTOTAL_A 0xe0000
7851 #define TRANS_HTOTAL_SHIFT 16
7852 #define TRANS_HACTIVE_SHIFT 0
7853 #define _PCH_TRANS_HBLANK_A 0xe0004
7854 #define TRANS_HBLANK_END_SHIFT 16
7855 #define TRANS_HBLANK_START_SHIFT 0
7856 #define _PCH_TRANS_HSYNC_A 0xe0008
7857 #define TRANS_HSYNC_END_SHIFT 16
7858 #define TRANS_HSYNC_START_SHIFT 0
7859 #define _PCH_TRANS_VTOTAL_A 0xe000c
7860 #define TRANS_VTOTAL_SHIFT 16
7861 #define TRANS_VACTIVE_SHIFT 0
7862 #define _PCH_TRANS_VBLANK_A 0xe0010
7863 #define TRANS_VBLANK_END_SHIFT 16
7864 #define TRANS_VBLANK_START_SHIFT 0
7865 #define _PCH_TRANS_VSYNC_A 0xe0014
7866 #define TRANS_VSYNC_END_SHIFT 16
7867 #define TRANS_VSYNC_START_SHIFT 0
7868 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
7870 #define _PCH_TRANSA_DATA_M1 0xe0030
7871 #define _PCH_TRANSA_DATA_N1 0xe0034
7872 #define _PCH_TRANSA_DATA_M2 0xe0038
7873 #define _PCH_TRANSA_DATA_N2 0xe003c
7874 #define _PCH_TRANSA_LINK_M1 0xe0040
7875 #define _PCH_TRANSA_LINK_N1 0xe0044
7876 #define _PCH_TRANSA_LINK_M2 0xe0048
7877 #define _PCH_TRANSA_LINK_N2 0xe004c
7879 /* Per-transcoder DIP controls (PCH) */
7880 #define _VIDEO_DIP_CTL_A 0xe0200
7881 #define _VIDEO_DIP_DATA_A 0xe0208
7882 #define _VIDEO_DIP_GCP_A 0xe0210
7883 #define GCP_COLOR_INDICATION (1 << 2)
7884 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
7885 #define GCP_AV_MUTE (1 << 0)
7887 #define _VIDEO_DIP_CTL_B 0xe1200
7888 #define _VIDEO_DIP_DATA_B 0xe1208
7889 #define _VIDEO_DIP_GCP_B 0xe1210
7891 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
7892 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
7893 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
7895 /* Per-transcoder DIP controls (VLV) */
7896 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
7897 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
7898 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
7900 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
7901 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
7902 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
7904 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
7905 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
7906 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
7908 #define VLV_TVIDEO_DIP_CTL(pipe) \
7909 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
7910 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
7911 #define VLV_TVIDEO_DIP_DATA(pipe) \
7912 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
7913 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
7914 #define VLV_TVIDEO_DIP_GCP(pipe) \
7915 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
7916 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
7918 /* Haswell DIP controls */
7920 #define _HSW_VIDEO_DIP_CTL_A 0x60200
7921 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
7922 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
7923 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
7924 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
7925 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
7926 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
7927 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
7928 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
7929 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
7930 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
7931 #define _HSW_VIDEO_DIP_GCP_A 0x60210
7933 #define _HSW_VIDEO_DIP_CTL_B 0x61200
7934 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
7935 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
7936 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
7937 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
7938 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
7939 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
7940 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
7941 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
7942 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
7943 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
7944 #define _HSW_VIDEO_DIP_GCP_B 0x61210
7946 /* Icelake PPS_DATA and _ECC DIP Registers.
7947 * These are available for transcoders B,C and eDP.
7948 * Adding the _A so as to reuse the _MMIO_TRANS2
7949 * definition, with which it offsets to the right location.
7952 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
7953 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
7954 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
7955 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
7957 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
7958 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
7959 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
7960 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
7961 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
7962 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
7963 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
7964 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
7966 #define _HSW_STEREO_3D_CTL_A 0x70020
7967 #define S3D_ENABLE (1 << 31)
7968 #define _HSW_STEREO_3D_CTL_B 0x71020
7970 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
7972 #define _PCH_TRANS_HTOTAL_B 0xe1000
7973 #define _PCH_TRANS_HBLANK_B 0xe1004
7974 #define _PCH_TRANS_HSYNC_B 0xe1008
7975 #define _PCH_TRANS_VTOTAL_B 0xe100c
7976 #define _PCH_TRANS_VBLANK_B 0xe1010
7977 #define _PCH_TRANS_VSYNC_B 0xe1014
7978 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
7980 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
7981 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
7982 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
7983 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
7984 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
7985 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
7986 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
7988 #define _PCH_TRANSB_DATA_M1 0xe1030
7989 #define _PCH_TRANSB_DATA_N1 0xe1034
7990 #define _PCH_TRANSB_DATA_M2 0xe1038
7991 #define _PCH_TRANSB_DATA_N2 0xe103c
7992 #define _PCH_TRANSB_LINK_M1 0xe1040
7993 #define _PCH_TRANSB_LINK_N1 0xe1044
7994 #define _PCH_TRANSB_LINK_M2 0xe1048
7995 #define _PCH_TRANSB_LINK_N2 0xe104c
7997 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
7998 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
7999 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
8000 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
8001 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
8002 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8003 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8004 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8006 #define _PCH_TRANSACONF 0xf0008
8007 #define _PCH_TRANSBCONF 0xf1008
8008 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8009 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
8010 #define TRANS_DISABLE (0 << 31)
8011 #define TRANS_ENABLE (1 << 31)
8012 #define TRANS_STATE_MASK (1 << 30)
8013 #define TRANS_STATE_DISABLE (0 << 30)
8014 #define TRANS_STATE_ENABLE (1 << 30)
8015 #define TRANS_FSYNC_DELAY_HB1 (0 << 27)
8016 #define TRANS_FSYNC_DELAY_HB2 (1 << 27)
8017 #define TRANS_FSYNC_DELAY_HB3 (2 << 27)
8018 #define TRANS_FSYNC_DELAY_HB4 (3 << 27)
8019 #define TRANS_INTERLACE_MASK (7 << 21)
8020 #define TRANS_PROGRESSIVE (0 << 21)
8021 #define TRANS_INTERLACED (3 << 21)
8022 #define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8023 #define TRANS_8BPC (0 << 5)
8024 #define TRANS_10BPC (1 << 5)
8025 #define TRANS_6BPC (2 << 5)
8026 #define TRANS_12BPC (3 << 5)
8028 #define _TRANSA_CHICKEN1 0xf0060
8029 #define _TRANSB_CHICKEN1 0xf1060
8030 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8031 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10)
8032 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)
8033 #define _TRANSA_CHICKEN2 0xf0064
8034 #define _TRANSB_CHICKEN2 0xf1064
8035 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8036 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
8037 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
8038 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
8039 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
8040 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
8042 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
8043 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
8044 #define FDIA_PHASE_SYNC_SHIFT_EN 18
8045 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8046 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8047 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
8048 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
8049 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
8050 #define SPT_PWM_GRANULARITY (1 << 0)
8051 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
8052 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
8053 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
8054 #define LPT_PWM_GRANULARITY (1 << 5)
8055 #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
8057 #define _FDI_RXA_CHICKEN 0xc200c
8058 #define _FDI_RXB_CHICKEN 0xc2010
8059 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
8060 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
8061 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8063 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
8064 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8065 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8066 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8067 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8068 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8069 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
8072 #define _FDI_TXA_CTL 0x60100
8073 #define _FDI_TXB_CTL 0x61100
8074 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8075 #define FDI_TX_DISABLE (0 << 31)
8076 #define FDI_TX_ENABLE (1 << 31)
8077 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
8078 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
8079 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
8080 #define FDI_LINK_TRAIN_NONE (3 << 28)
8081 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
8082 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
8083 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
8084 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
8085 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8086 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8087 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
8088 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
8089 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8090 SNB has different settings. */
8091 /* SNB A-stepping */
8092 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8093 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8094 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8095 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8096 /* SNB B-stepping */
8097 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
8098 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
8099 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
8100 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
8101 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
8102 #define FDI_DP_PORT_WIDTH_SHIFT 19
8103 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
8104 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8105 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
8106 /* Ironlake: hardwired to 1 */
8107 #define FDI_TX_PLL_ENABLE (1 << 14)
8109 /* Ivybridge has different bits for lolz */
8110 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
8111 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
8112 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
8113 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
8115 /* both Tx and Rx */
8116 #define FDI_COMPOSITE_SYNC (1 << 11)
8117 #define FDI_LINK_TRAIN_AUTO (1 << 10)
8118 #define FDI_SCRAMBLING_ENABLE (0 << 7)
8119 #define FDI_SCRAMBLING_DISABLE (1 << 7)
8121 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8122 #define _FDI_RXA_CTL 0xf000c
8123 #define _FDI_RXB_CTL 0xf100c
8124 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8125 #define FDI_RX_ENABLE (1 << 31)
8126 /* train, dp width same as FDI_TX */
8127 #define FDI_FS_ERRC_ENABLE (1 << 27)
8128 #define FDI_FE_ERRC_ENABLE (1 << 26)
8129 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
8130 #define FDI_8BPC (0 << 16)
8131 #define FDI_10BPC (1 << 16)
8132 #define FDI_6BPC (2 << 16)
8133 #define FDI_12BPC (3 << 16)
8134 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
8135 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
8136 #define FDI_RX_PLL_ENABLE (1 << 13)
8137 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
8138 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
8139 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
8140 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
8141 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
8142 #define FDI_PCDCLK (1 << 4)
8144 #define FDI_AUTO_TRAINING (1 << 10)
8145 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
8146 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
8147 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
8148 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
8149 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
8151 #define _FDI_RXA_MISC 0xf0010
8152 #define _FDI_RXB_MISC 0xf1010
8153 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
8154 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
8155 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
8156 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
8157 #define FDI_RX_TP1_TO_TP2_48 (2 << 20)
8158 #define FDI_RX_TP1_TO_TP2_64 (3 << 20)
8159 #define FDI_RX_FDI_DELAY_90 (0x90 << 0)
8160 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
8162 #define _FDI_RXA_TUSIZE1 0xf0030
8163 #define _FDI_RXA_TUSIZE2 0xf0038
8164 #define _FDI_RXB_TUSIZE1 0xf1030
8165 #define _FDI_RXB_TUSIZE2 0xf1038
8166 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
8167 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
8169 /* FDI_RX interrupt register format */
8170 #define FDI_RX_INTER_LANE_ALIGN (1 << 10)
8171 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */
8172 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */
8173 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
8174 #define FDI_RX_FS_CODE_ERR (1 << 6)
8175 #define FDI_RX_FE_CODE_ERR (1 << 5)
8176 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
8177 #define FDI_RX_HDCP_LINK_FAIL (1 << 3)
8178 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
8179 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
8180 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
8182 #define _FDI_RXA_IIR 0xf0014
8183 #define _FDI_RXA_IMR 0xf0018
8184 #define _FDI_RXB_IIR 0xf1014
8185 #define _FDI_RXB_IMR 0xf1018
8186 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
8187 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
8189 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
8190 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
8192 #define PCH_LVDS _MMIO(0xe1180)
8193 #define LVDS_DETECTED (1 << 1)
8195 #define _PCH_DP_B 0xe4100
8196 #define PCH_DP_B _MMIO(_PCH_DP_B)
8197 #define _PCH_DPB_AUX_CH_CTL 0xe4110
8198 #define _PCH_DPB_AUX_CH_DATA1 0xe4114
8199 #define _PCH_DPB_AUX_CH_DATA2 0xe4118
8200 #define _PCH_DPB_AUX_CH_DATA3 0xe411c
8201 #define _PCH_DPB_AUX_CH_DATA4 0xe4120
8202 #define _PCH_DPB_AUX_CH_DATA5 0xe4124
8204 #define _PCH_DP_C 0xe4200
8205 #define PCH_DP_C _MMIO(_PCH_DP_C)
8206 #define _PCH_DPC_AUX_CH_CTL 0xe4210
8207 #define _PCH_DPC_AUX_CH_DATA1 0xe4214
8208 #define _PCH_DPC_AUX_CH_DATA2 0xe4218
8209 #define _PCH_DPC_AUX_CH_DATA3 0xe421c
8210 #define _PCH_DPC_AUX_CH_DATA4 0xe4220
8211 #define _PCH_DPC_AUX_CH_DATA5 0xe4224
8213 #define _PCH_DP_D 0xe4300
8214 #define PCH_DP_D _MMIO(_PCH_DP_D)
8215 #define _PCH_DPD_AUX_CH_CTL 0xe4310
8216 #define _PCH_DPD_AUX_CH_DATA1 0xe4314
8217 #define _PCH_DPD_AUX_CH_DATA2 0xe4318
8218 #define _PCH_DPD_AUX_CH_DATA3 0xe431c
8219 #define _PCH_DPD_AUX_CH_DATA4 0xe4320
8220 #define _PCH_DPD_AUX_CH_DATA5 0xe4324
8222 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
8223 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
8226 #define _TRANS_DP_CTL_A 0xe0300
8227 #define _TRANS_DP_CTL_B 0xe1300
8228 #define _TRANS_DP_CTL_C 0xe2300
8229 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8230 #define TRANS_DP_OUTPUT_ENABLE (1 << 31)
8231 #define TRANS_DP_PORT_SEL_MASK (3 << 29)
8232 #define TRANS_DP_PORT_SEL_NONE (3 << 29)
8233 #define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
8234 #define TRANS_DP_AUDIO_ONLY (1 << 26)
8235 #define TRANS_DP_ENH_FRAMING (1 << 18)
8236 #define TRANS_DP_8BPC (0 << 9)
8237 #define TRANS_DP_10BPC (1 << 9)
8238 #define TRANS_DP_6BPC (2 << 9)
8239 #define TRANS_DP_12BPC (3 << 9)
8240 #define TRANS_DP_BPC_MASK (3 << 9)
8241 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
8242 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
8243 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
8244 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
8245 #define TRANS_DP_SYNC_MASK (3 << 3)
8247 /* SNB eDP training params */
8248 /* SNB A-stepping */
8249 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8250 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8251 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8252 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8253 /* SNB B-stepping */
8254 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
8255 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
8256 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
8257 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
8258 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
8259 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
8262 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
8263 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
8264 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
8265 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
8266 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
8267 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
8268 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
8271 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
8272 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
8273 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
8274 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
8275 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
8277 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
8279 #define VLV_PMWGICZ _MMIO(0x1300a4)
8281 #define RC6_LOCATION _MMIO(0xD40)
8282 #define RC6_CTX_IN_DRAM (1 << 0)
8283 #define RC6_CTX_BASE _MMIO(0xD48)
8284 #define RC6_CTX_BASE_MASK 0xFFFFFFF0
8285 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
8286 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
8287 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
8288 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
8289 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
8290 #define IDLE_TIME_MASK 0xFFFFF
8291 #define FORCEWAKE _MMIO(0xA18C)
8292 #define FORCEWAKE_VLV _MMIO(0x1300b0)
8293 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
8294 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
8295 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
8296 #define FORCEWAKE_ACK_HSW _MMIO(0x130044)
8297 #define FORCEWAKE_ACK _MMIO(0x130090)
8298 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
8299 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
8300 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
8301 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
8303 #define VLV_GTLC_PW_STATUS _MMIO(0x130094)
8304 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
8305 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
8306 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
8307 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
8308 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
8309 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
8310 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
8311 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
8312 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
8313 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
8314 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
8315 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
8316 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
8317 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
8318 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
8319 #define FORCEWAKE_KERNEL BIT(0)
8320 #define FORCEWAKE_USER BIT(1)
8321 #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
8322 #define FORCEWAKE_MT_ACK _MMIO(0x130040)
8323 #define ECOBUS _MMIO(0xa180)
8324 #define FORCEWAKE_MT_ENABLE (1 << 5)
8325 #define VLV_SPAREG2H _MMIO(0xA194)
8326 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
8327 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
8328 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
8330 #define GTFIFODBG _MMIO(0x120000)
8331 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
8332 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
8333 #define GT_FIFO_SBDROPERR (1 << 6)
8334 #define GT_FIFO_BLOBDROPERR (1 << 5)
8335 #define GT_FIFO_SB_READ_ABORTERR (1 << 4)
8336 #define GT_FIFO_DROPERR (1 << 3)
8337 #define GT_FIFO_OVFERR (1 << 2)
8338 #define GT_FIFO_IAWRERR (1 << 1)
8339 #define GT_FIFO_IARDERR (1 << 0)
8341 #define GTFIFOCTL _MMIO(0x120008)
8342 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
8343 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
8344 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
8345 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
8347 #define HSW_IDICR _MMIO(0x9008)
8348 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
8349 #define HSW_EDRAM_CAP _MMIO(0x120010)
8350 #define EDRAM_ENABLED 0x1
8351 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
8352 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
8353 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
8355 #define GEN6_UCGCTL1 _MMIO(0x9400)
8356 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
8357 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
8358 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
8359 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
8361 #define GEN6_UCGCTL2 _MMIO(0x9404)
8362 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
8363 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
8364 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
8365 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
8366 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
8367 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
8369 #define GEN6_UCGCTL3 _MMIO(0x9408)
8370 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
8372 #define GEN7_UCGCTL4 _MMIO(0x940c)
8373 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
8374 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
8376 #define GEN6_RCGCTL1 _MMIO(0x9410)
8377 #define GEN6_RCGCTL2 _MMIO(0x9414)
8378 #define GEN6_RSTCTL _MMIO(0x9420)
8380 #define GEN8_UCGCTL6 _MMIO(0x9430)
8381 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
8382 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
8383 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
8385 #define GEN6_GFXPAUSE _MMIO(0xA000)
8386 #define GEN6_RPNSWREQ _MMIO(0xA008)
8387 #define GEN6_TURBO_DISABLE (1 << 31)
8388 #define GEN6_FREQUENCY(x) ((x) << 25)
8389 #define HSW_FREQUENCY(x) ((x) << 24)
8390 #define GEN9_FREQUENCY(x) ((x) << 23)
8391 #define GEN6_OFFSET(x) ((x) << 19)
8392 #define GEN6_AGGRESSIVE_TURBO (0 << 15)
8393 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
8394 #define GEN6_RC_CONTROL _MMIO(0xA090)
8395 #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
8396 #define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
8397 #define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
8398 #define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
8399 #define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
8400 #define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
8401 #define GEN7_RC_CTL_TO_MODE (1 << 28)
8402 #define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
8403 #define GEN6_RC_CTL_HW_ENABLE (1 << 31)
8404 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
8405 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
8406 #define GEN6_RPSTAT1 _MMIO(0xA01C)
8407 #define GEN6_CAGF_SHIFT 8
8408 #define HSW_CAGF_SHIFT 7
8409 #define GEN9_CAGF_SHIFT 23
8410 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
8411 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
8412 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
8413 #define GEN6_RP_CONTROL _MMIO(0xA024)
8414 #define GEN6_RP_MEDIA_TURBO (1 << 11)
8415 #define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
8416 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
8417 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
8418 #define GEN6_RP_MEDIA_HW_MODE (1 << 9)
8419 #define GEN6_RP_MEDIA_SW_MODE (0 << 9)
8420 #define GEN6_RP_MEDIA_IS_GFX (1 << 8)
8421 #define GEN6_RP_ENABLE (1 << 7)
8422 #define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
8423 #define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
8424 #define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
8425 #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
8426 #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
8427 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
8428 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
8429 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
8430 #define GEN6_RP_EI_MASK 0xffffff
8431 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
8432 #define GEN6_RP_CUR_UP _MMIO(0xA054)
8433 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
8434 #define GEN6_RP_PREV_UP _MMIO(0xA058)
8435 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
8436 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
8437 #define GEN6_RP_CUR_DOWN _MMIO(0xA060)
8438 #define GEN6_RP_PREV_DOWN _MMIO(0xA064)
8439 #define GEN6_RP_UP_EI _MMIO(0xA068)
8440 #define GEN6_RP_DOWN_EI _MMIO(0xA06C)
8441 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
8442 #define GEN6_RPDEUHWTC _MMIO(0xA080)
8443 #define GEN6_RPDEUC _MMIO(0xA084)
8444 #define GEN6_RPDEUCSW _MMIO(0xA088)
8445 #define GEN6_RC_STATE _MMIO(0xA094)
8446 #define RC_SW_TARGET_STATE_SHIFT 16
8447 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
8448 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
8449 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
8450 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8451 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8452 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
8453 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
8454 #define GEN6_RC_SLEEP _MMIO(0xA0B0)
8455 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
8456 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
8457 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
8458 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
8459 #define VLV_RCEDATA _MMIO(0xA0BC)
8460 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
8461 #define GEN6_PMINTRMSK _MMIO(0xA168)
8462 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
8463 #define ARAT_EXPIRED_INTRMSK (1 << 9)
8464 #define GEN8_MISC_CTRL0 _MMIO(0xA180)
8465 #define VLV_PWRDWNUPCTL _MMIO(0xA294)
8466 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
8467 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
8468 #define GEN9_PG_ENABLE _MMIO(0xA210)
8469 #define GEN9_RENDER_PG_ENABLE (1 << 0)
8470 #define GEN9_MEDIA_PG_ENABLE (1 << 1)
8471 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
8472 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
8473 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
8475 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8476 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
8477 #define PIXEL_OVERLAP_CNT_SHIFT 30
8479 #define GEN6_PMISR _MMIO(0x44020)
8480 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
8481 #define GEN6_PMIIR _MMIO(0x44028)
8482 #define GEN6_PMIER _MMIO(0x4402C)
8483 #define GEN6_PM_MBOX_EVENT (1 << 25)
8484 #define GEN6_PM_THERMAL_EVENT (1 << 24)
8485 #define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
8486 #define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
8487 #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
8488 #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
8489 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
8490 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
8491 GEN6_PM_RP_UP_THRESHOLD | \
8492 GEN6_PM_RP_DOWN_EI_EXPIRED | \
8493 GEN6_PM_RP_DOWN_THRESHOLD | \
8494 GEN6_PM_RP_DOWN_TIMEOUT)
8496 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
8497 #define GEN7_GT_SCRATCH_REG_NUM 8
8499 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
8500 #define VLV_GFX_CLK_STATUS_BIT (1 << 3)
8501 #define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
8503 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
8504 #define VLV_COUNTER_CONTROL _MMIO(0x138104)
8505 #define VLV_COUNT_RANGE_HIGH (1 << 15)
8506 #define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
8507 #define VLV_RENDER_RC0_COUNT_EN (1 << 4)
8508 #define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
8509 #define VLV_RENDER_RC6_COUNT_EN (1 << 0)
8510 #define GEN6_GT_GFX_RC6 _MMIO(0x138108)
8511 #define VLV_GT_RENDER_RC6 _MMIO(0x138108)
8512 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
8514 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
8515 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
8516 #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
8517 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
8519 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
8520 #define GEN6_PCODE_READY (1 << 31)
8521 #define GEN6_PCODE_ERROR_MASK 0xFF
8522 #define GEN6_PCODE_SUCCESS 0x0
8523 #define GEN6_PCODE_ILLEGAL_CMD 0x1
8524 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8525 #define GEN6_PCODE_TIMEOUT 0x3
8526 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
8527 #define GEN7_PCODE_TIMEOUT 0x2
8528 #define GEN7_PCODE_ILLEGAL_DATA 0x3
8529 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8530 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
8531 #define GEN6_PCODE_READ_RC6VIDS 0x5
8532 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
8533 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
8534 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
8535 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
8536 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
8537 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
8538 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
8539 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
8540 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
8541 #define SKL_PCODE_CDCLK_CONTROL 0x7
8542 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
8543 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
8544 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
8545 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
8546 #define GEN6_READ_OC_PARAMS 0xc
8547 #define GEN6_PCODE_READ_D_COMP 0x10
8548 #define GEN6_PCODE_WRITE_D_COMP 0x11
8549 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
8550 #define DISPLAY_IPS_CONTROL 0x19
8551 /* See also IPS_CTL */
8552 #define IPS_PCODE_CONTROL (1 << 30)
8553 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
8554 #define GEN9_PCODE_SAGV_CONTROL 0x21
8555 #define GEN9_SAGV_DISABLE 0x0
8556 #define GEN9_SAGV_IS_DISABLED 0x1
8557 #define GEN9_SAGV_ENABLE 0x3
8558 #define GEN6_PCODE_DATA _MMIO(0x138128)
8559 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
8560 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
8561 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
8563 #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
8564 #define GEN6_CORE_CPD_STATE_MASK (7 << 4)
8565 #define GEN6_RCn_MASK 7
8571 #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
8572 #define GEN8_LSLICESTAT_MASK 0x7
8574 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
8575 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
8576 #define CHV_SS_PG_ENABLE (1 << 1)
8577 #define CHV_EU08_PG_ENABLE (1 << 9)
8578 #define CHV_EU19_PG_ENABLE (1 << 17)
8579 #define CHV_EU210_PG_ENABLE (1 << 25)
8581 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
8582 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
8583 #define CHV_EU311_PG_ENABLE (1 << 1)
8585 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
8586 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
8587 ((slice) % 3) * 0x4)
8588 #define GEN9_PGCTL_SLICE_ACK (1 << 0)
8589 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
8590 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
8592 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
8593 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
8594 ((slice) % 3) * 0x8)
8595 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
8596 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8597 ((slice) % 3) * 0x8)
8598 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
8599 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
8600 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
8601 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
8602 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
8603 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
8604 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
8605 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
8607 #define GEN7_MISCCPCTL _MMIO(0x9424)
8608 #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
8609 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
8610 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
8611 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
8613 #define GEN8_GARBCNTL _MMIO(0xB004)
8614 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
8615 #define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
8616 #define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
8617 #define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
8619 #define GEN11_GLBLINVL _MMIO(0xB404)
8620 #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
8621 #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
8623 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
8624 #define DFR_DISABLE (1 << 9)
8626 #define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
8627 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
8628 #define GEN11_HASH_CTRL_BIT0 (1 << 0)
8629 #define GEN11_HASH_CTRL_BIT4 (1 << 12)
8631 #define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
8632 #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
8633 #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
8635 #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
8636 #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
8639 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
8640 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
8641 #define GEN7_PARITY_ERROR_VALID (1 << 13)
8642 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
8643 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
8644 #define GEN7_PARITY_ERROR_ROW(reg) \
8645 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8646 #define GEN7_PARITY_ERROR_BANK(reg) \
8647 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8648 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
8649 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8650 #define GEN7_L3CDERRST1_ENABLE (1 << 7)
8652 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
8653 #define GEN7_L3LOG_SIZE 0x80
8655 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
8656 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
8657 #define GEN7_MAX_PS_THREAD_DEP (8 << 12)
8658 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
8659 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
8660 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
8662 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
8663 #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
8664 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
8666 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
8667 #define FLOW_CONTROL_ENABLE (1 << 15)
8668 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
8669 #define STALL_DOP_GATING_DISABLE (1 << 5)
8670 #define THROTTLE_12_5 (7 << 2)
8671 #define DISABLE_EARLY_EOT (1 << 1)
8673 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
8674 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
8675 #define DOP_CLOCK_GATING_DISABLE (1 << 0)
8676 #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
8677 #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
8679 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
8680 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
8682 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
8683 #define GEN8_ST_PO_DISABLE (1 << 13)
8685 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
8686 #define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
8687 #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
8688 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
8689 #define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
8690 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
8692 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
8693 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8)
8694 #define GEN9_ENABLE_YV12_BUGFIX (1 << 4)
8695 #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2)
8698 #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
8699 #define INTEL_AUDIO_DEVCL 0x808629FB
8700 #define INTEL_AUDIO_DEVBLC 0x80862801
8701 #define INTEL_AUDIO_DEVCTG 0x80862802
8703 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
8704 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
8705 #define G4X_ELDV_DEVCTG (1 << 14)
8706 #define G4X_ELD_ADDR_MASK (0xf << 5)
8707 #define G4X_ELD_ACK (1 << 4)
8708 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
8710 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
8711 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
8712 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
8713 _IBX_HDMIW_HDMIEDID_B)
8714 #define _IBX_AUD_CNTL_ST_A 0xE20B4
8715 #define _IBX_AUD_CNTL_ST_B 0xE21B4
8716 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
8718 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
8719 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
8720 #define IBX_ELD_ACK (1 << 4)
8721 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
8722 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
8723 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
8725 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
8726 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
8727 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
8728 #define _CPT_AUD_CNTL_ST_A 0xE50B4
8729 #define _CPT_AUD_CNTL_ST_B 0xE51B4
8730 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
8731 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
8733 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
8734 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
8735 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
8736 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
8737 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
8738 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
8739 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
8741 /* These are the 4 32-bit write offset registers for each stream
8742 * output buffer. It determines the offset from the
8743 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
8745 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
8747 #define _IBX_AUD_CONFIG_A 0xe2000
8748 #define _IBX_AUD_CONFIG_B 0xe2100
8749 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
8750 #define _CPT_AUD_CONFIG_A 0xe5000
8751 #define _CPT_AUD_CONFIG_B 0xe5100
8752 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
8753 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
8754 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
8755 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
8757 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
8758 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
8759 #define AUD_CONFIG_UPPER_N_SHIFT 20
8760 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
8761 #define AUD_CONFIG_LOWER_N_SHIFT 4
8762 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
8763 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
8764 #define AUD_CONFIG_N(n) \
8765 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
8766 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
8767 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
8768 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
8769 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
8770 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
8771 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
8772 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
8773 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
8774 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
8775 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
8776 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
8777 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
8778 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
8779 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
8782 #define _HSW_AUD_CONFIG_A 0x65000
8783 #define _HSW_AUD_CONFIG_B 0x65100
8784 #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
8786 #define _HSW_AUD_MISC_CTRL_A 0x65010
8787 #define _HSW_AUD_MISC_CTRL_B 0x65110
8788 #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
8790 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028
8791 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128
8792 #define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
8793 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
8794 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
8795 #define AUD_CONFIG_M_MASK 0xfffff
8797 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
8798 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
8799 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
8801 /* Audio Digital Converter */
8802 #define _HSW_AUD_DIG_CNVT_1 0x65080
8803 #define _HSW_AUD_DIG_CNVT_2 0x65180
8804 #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
8805 #define DIP_PORT_SEL_MASK 0x3
8807 #define _HSW_AUD_EDID_DATA_A 0x65050
8808 #define _HSW_AUD_EDID_DATA_B 0x65150
8809 #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
8811 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
8812 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
8813 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
8814 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
8815 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
8816 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
8818 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
8819 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
8822 * HSW - ICL power wells
8824 * Platforms have up to 3 power well control register sets, each set
8825 * controlling up to 16 power wells via a request/status HW flag tuple:
8826 * - main (HSW_PWR_WELL_CTL[1-4])
8827 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
8828 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
8829 * Each control register set consists of up to 4 registers used by different
8830 * sources that can request a power well to be enabled:
8831 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
8832 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
8833 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
8834 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
8836 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
8837 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
8838 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
8839 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
8840 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
8841 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
8843 /* HSW/BDW power well */
8844 #define HSW_PW_CTL_IDX_GLOBAL 15
8846 /* SKL/BXT/GLK/CNL power wells */
8847 #define SKL_PW_CTL_IDX_PW_2 15
8848 #define SKL_PW_CTL_IDX_PW_1 14
8849 #define CNL_PW_CTL_IDX_AUX_F 12
8850 #define CNL_PW_CTL_IDX_AUX_D 11
8851 #define GLK_PW_CTL_IDX_AUX_C 10
8852 #define GLK_PW_CTL_IDX_AUX_B 9
8853 #define GLK_PW_CTL_IDX_AUX_A 8
8854 #define CNL_PW_CTL_IDX_DDI_F 6
8855 #define SKL_PW_CTL_IDX_DDI_D 4
8856 #define SKL_PW_CTL_IDX_DDI_C 3
8857 #define SKL_PW_CTL_IDX_DDI_B 2
8858 #define SKL_PW_CTL_IDX_DDI_A_E 1
8859 #define GLK_PW_CTL_IDX_DDI_A 1
8860 #define SKL_PW_CTL_IDX_MISC_IO 0
8862 /* ICL - power wells */
8863 #define ICL_PW_CTL_IDX_PW_4 3
8864 #define ICL_PW_CTL_IDX_PW_3 2
8865 #define ICL_PW_CTL_IDX_PW_2 1
8866 #define ICL_PW_CTL_IDX_PW_1 0
8868 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
8869 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
8870 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
8871 #define ICL_PW_CTL_IDX_AUX_TBT4 11
8872 #define ICL_PW_CTL_IDX_AUX_TBT3 10
8873 #define ICL_PW_CTL_IDX_AUX_TBT2 9
8874 #define ICL_PW_CTL_IDX_AUX_TBT1 8
8875 #define ICL_PW_CTL_IDX_AUX_F 5
8876 #define ICL_PW_CTL_IDX_AUX_E 4
8877 #define ICL_PW_CTL_IDX_AUX_D 3
8878 #define ICL_PW_CTL_IDX_AUX_C 2
8879 #define ICL_PW_CTL_IDX_AUX_B 1
8880 #define ICL_PW_CTL_IDX_AUX_A 0
8882 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
8883 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
8884 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
8885 #define ICL_PW_CTL_IDX_DDI_F 5
8886 #define ICL_PW_CTL_IDX_DDI_E 4
8887 #define ICL_PW_CTL_IDX_DDI_D 3
8888 #define ICL_PW_CTL_IDX_DDI_C 2
8889 #define ICL_PW_CTL_IDX_DDI_B 1
8890 #define ICL_PW_CTL_IDX_DDI_A 0
8892 /* HSW - power well misc debug registers */
8893 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
8894 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
8895 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
8896 #define HSW_PWR_WELL_FORCE_ON (1 << 19)
8897 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
8899 /* SKL Fuse Status */
8900 enum skl_power_gate {
8908 #define SKL_FUSE_STATUS _MMIO(0x42000)
8909 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
8911 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
8912 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
8914 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
8915 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
8917 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
8918 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
8920 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
8921 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
8922 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
8924 #define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
8925 #define _CNL_AUX_ANAOVRD1_B 0x162250
8926 #define _CNL_AUX_ANAOVRD1_C 0x162210
8927 #define _CNL_AUX_ANAOVRD1_D 0x1622D0
8928 #define _CNL_AUX_ANAOVRD1_F 0x162A90
8929 #define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
8930 _CNL_AUX_ANAOVRD1_B, \
8931 _CNL_AUX_ANAOVRD1_C, \
8932 _CNL_AUX_ANAOVRD1_D, \
8933 _CNL_AUX_ANAOVRD1_F))
8934 #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
8935 #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
8937 /* HDCP Key Registers */
8938 #define HDCP_KEY_CONF _MMIO(0x66c00)
8939 #define HDCP_AKSV_SEND_TRIGGER BIT(31)
8940 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
8941 #define HDCP_KEY_LOAD_TRIGGER BIT(8)
8942 #define HDCP_KEY_STATUS _MMIO(0x66c04)
8943 #define HDCP_FUSE_IN_PROGRESS BIT(7)
8944 #define HDCP_FUSE_ERROR BIT(6)
8945 #define HDCP_FUSE_DONE BIT(5)
8946 #define HDCP_KEY_LOAD_STATUS BIT(1)
8947 #define HDCP_KEY_LOAD_DONE BIT(0)
8948 #define HDCP_AKSV_LO _MMIO(0x66c10)
8949 #define HDCP_AKSV_HI _MMIO(0x66c14)
8951 /* HDCP Repeater Registers */
8952 #define HDCP_REP_CTL _MMIO(0x66d00)
8953 #define HDCP_DDIB_REP_PRESENT BIT(30)
8954 #define HDCP_DDIA_REP_PRESENT BIT(29)
8955 #define HDCP_DDIC_REP_PRESENT BIT(28)
8956 #define HDCP_DDID_REP_PRESENT BIT(27)
8957 #define HDCP_DDIF_REP_PRESENT BIT(26)
8958 #define HDCP_DDIE_REP_PRESENT BIT(25)
8959 #define HDCP_DDIB_SHA1_M0 (1 << 20)
8960 #define HDCP_DDIA_SHA1_M0 (2 << 20)
8961 #define HDCP_DDIC_SHA1_M0 (3 << 20)
8962 #define HDCP_DDID_SHA1_M0 (4 << 20)
8963 #define HDCP_DDIF_SHA1_M0 (5 << 20)
8964 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
8965 #define HDCP_SHA1_BUSY BIT(16)
8966 #define HDCP_SHA1_READY BIT(17)
8967 #define HDCP_SHA1_COMPLETE BIT(18)
8968 #define HDCP_SHA1_V_MATCH BIT(19)
8969 #define HDCP_SHA1_TEXT_32 (1 << 1)
8970 #define HDCP_SHA1_COMPLETE_HASH (2 << 1)
8971 #define HDCP_SHA1_TEXT_24 (4 << 1)
8972 #define HDCP_SHA1_TEXT_16 (5 << 1)
8973 #define HDCP_SHA1_TEXT_8 (6 << 1)
8974 #define HDCP_SHA1_TEXT_0 (7 << 1)
8975 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
8976 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
8977 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
8978 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
8979 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
8980 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
8981 #define HDCP_SHA_TEXT _MMIO(0x66d18)
8983 /* HDCP Auth Registers */
8984 #define _PORTA_HDCP_AUTHENC 0x66800
8985 #define _PORTB_HDCP_AUTHENC 0x66500
8986 #define _PORTC_HDCP_AUTHENC 0x66600
8987 #define _PORTD_HDCP_AUTHENC 0x66700
8988 #define _PORTE_HDCP_AUTHENC 0x66A00
8989 #define _PORTF_HDCP_AUTHENC 0x66900
8990 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
8991 _PORTA_HDCP_AUTHENC, \
8992 _PORTB_HDCP_AUTHENC, \
8993 _PORTC_HDCP_AUTHENC, \
8994 _PORTD_HDCP_AUTHENC, \
8995 _PORTE_HDCP_AUTHENC, \
8996 _PORTF_HDCP_AUTHENC) + (x))
8997 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
8998 #define HDCP_CONF_CAPTURE_AN BIT(0)
8999 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
9000 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
9001 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
9002 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
9003 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
9004 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
9005 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
9006 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
9007 #define HDCP_STATUS_STREAM_A_ENC BIT(31)
9008 #define HDCP_STATUS_STREAM_B_ENC BIT(30)
9009 #define HDCP_STATUS_STREAM_C_ENC BIT(29)
9010 #define HDCP_STATUS_STREAM_D_ENC BIT(28)
9011 #define HDCP_STATUS_AUTH BIT(21)
9012 #define HDCP_STATUS_ENC BIT(20)
9013 #define HDCP_STATUS_RI_MATCH BIT(19)
9014 #define HDCP_STATUS_R0_READY BIT(18)
9015 #define HDCP_STATUS_AN_READY BIT(17)
9016 #define HDCP_STATUS_CIPHER BIT(16)
9017 #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
9019 /* Per-pipe DDI Function Control */
9020 #define _TRANS_DDI_FUNC_CTL_A 0x60400
9021 #define _TRANS_DDI_FUNC_CTL_B 0x61400
9022 #define _TRANS_DDI_FUNC_CTL_C 0x62400
9023 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
9024 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9026 #define TRANS_DDI_FUNC_ENABLE (1 << 31)
9027 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9028 #define TRANS_DDI_PORT_MASK (7 << 28)
9029 #define TRANS_DDI_PORT_SHIFT 28
9030 #define TRANS_DDI_SELECT_PORT(x) ((x) << 28)
9031 #define TRANS_DDI_PORT_NONE (0 << 28)
9032 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
9033 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
9034 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
9035 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
9036 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
9037 #define TRANS_DDI_MODE_SELECT_FDI (4 << 24)
9038 #define TRANS_DDI_BPC_MASK (7 << 20)
9039 #define TRANS_DDI_BPC_8 (0 << 20)
9040 #define TRANS_DDI_BPC_10 (1 << 20)
9041 #define TRANS_DDI_BPC_6 (2 << 20)
9042 #define TRANS_DDI_BPC_12 (3 << 20)
9043 #define TRANS_DDI_PVSYNC (1 << 17)
9044 #define TRANS_DDI_PHSYNC (1 << 16)
9045 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
9046 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
9047 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
9048 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
9049 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
9050 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
9051 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
9052 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
9053 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
9054 #define TRANS_DDI_BFI_ENABLE (1 << 4)
9055 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
9056 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
9057 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
9058 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9059 | TRANS_DDI_HDMI_SCRAMBLING)
9061 /* DisplayPort Transport Control */
9062 #define _DP_TP_CTL_A 0x64040
9063 #define _DP_TP_CTL_B 0x64140
9064 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
9065 #define DP_TP_CTL_ENABLE (1 << 31)
9066 #define DP_TP_CTL_MODE_SST (0 << 27)
9067 #define DP_TP_CTL_MODE_MST (1 << 27)
9068 #define DP_TP_CTL_FORCE_ACT (1 << 25)
9069 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
9070 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
9071 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
9072 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
9073 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
9074 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
9075 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
9076 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
9077 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
9078 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
9080 /* DisplayPort Transport Status */
9081 #define _DP_TP_STATUS_A 0x64044
9082 #define _DP_TP_STATUS_B 0x64144
9083 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
9084 #define DP_TP_STATUS_IDLE_DONE (1 << 25)
9085 #define DP_TP_STATUS_ACT_SENT (1 << 24)
9086 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
9087 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
9088 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
9089 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
9090 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
9092 /* DDI Buffer Control */
9093 #define _DDI_BUF_CTL_A 0x64000
9094 #define _DDI_BUF_CTL_B 0x64100
9095 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
9096 #define DDI_BUF_CTL_ENABLE (1 << 31)
9097 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
9098 #define DDI_BUF_EMP_MASK (0xf << 24)
9099 #define DDI_BUF_PORT_REVERSAL (1 << 16)
9100 #define DDI_BUF_IS_IDLE (1 << 7)
9101 #define DDI_A_4_LANES (1 << 4)
9102 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
9103 #define DDI_PORT_WIDTH_MASK (7 << 1)
9104 #define DDI_PORT_WIDTH_SHIFT 1
9105 #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
9107 /* DDI Buffer Translations */
9108 #define _DDI_BUF_TRANS_A 0x64E00
9109 #define _DDI_BUF_TRANS_B 0x64E60
9110 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
9111 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
9112 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
9114 /* Sideband Interface (SBI) is programmed indirectly, via
9115 * SBI_ADDR, which contains the register offset; and SBI_DATA,
9116 * which contains the payload */
9117 #define SBI_ADDR _MMIO(0xC6000)
9118 #define SBI_DATA _MMIO(0xC6004)
9119 #define SBI_CTL_STAT _MMIO(0xC6008)
9120 #define SBI_CTL_DEST_ICLK (0x0 << 16)
9121 #define SBI_CTL_DEST_MPHY (0x1 << 16)
9122 #define SBI_CTL_OP_IORD (0x2 << 8)
9123 #define SBI_CTL_OP_IOWR (0x3 << 8)
9124 #define SBI_CTL_OP_CRRD (0x6 << 8)
9125 #define SBI_CTL_OP_CRWR (0x7 << 8)
9126 #define SBI_RESPONSE_FAIL (0x1 << 1)
9127 #define SBI_RESPONSE_SUCCESS (0x0 << 1)
9128 #define SBI_BUSY (0x1 << 0)
9129 #define SBI_READY (0x0 << 0)
9132 #define SBI_SSCDIVINTPHASE 0x0200
9133 #define SBI_SSCDIVINTPHASE6 0x0600
9134 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
9135 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
9136 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
9137 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
9138 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
9139 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
9140 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
9141 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
9142 #define SBI_SSCDITHPHASE 0x0204
9143 #define SBI_SSCCTL 0x020c
9144 #define SBI_SSCCTL6 0x060C
9145 #define SBI_SSCCTL_PATHALT (1 << 3)
9146 #define SBI_SSCCTL_DISABLE (1 << 0)
9147 #define SBI_SSCAUXDIV6 0x0610
9148 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
9149 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
9150 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
9151 #define SBI_DBUFF0 0x2a00
9152 #define SBI_GEN0 0x1f00
9153 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
9155 /* LPT PIXCLK_GATE */
9156 #define PIXCLK_GATE _MMIO(0xC6020)
9157 #define PIXCLK_GATE_UNGATE (1 << 0)
9158 #define PIXCLK_GATE_GATE (0 << 0)
9161 #define SPLL_CTL _MMIO(0x46020)
9162 #define SPLL_PLL_ENABLE (1 << 31)
9163 #define SPLL_PLL_SSC (1 << 28)
9164 #define SPLL_PLL_NON_SSC (2 << 28)
9165 #define SPLL_PLL_LCPLL (3 << 28)
9166 #define SPLL_PLL_REF_MASK (3 << 28)
9167 #define SPLL_PLL_FREQ_810MHz (0 << 26)
9168 #define SPLL_PLL_FREQ_1350MHz (1 << 26)
9169 #define SPLL_PLL_FREQ_2700MHz (2 << 26)
9170 #define SPLL_PLL_FREQ_MASK (3 << 26)
9173 #define _WRPLL_CTL1 0x46040
9174 #define _WRPLL_CTL2 0x46060
9175 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
9176 #define WRPLL_PLL_ENABLE (1 << 31)
9177 #define WRPLL_PLL_SSC (1 << 28)
9178 #define WRPLL_PLL_NON_SSC (2 << 28)
9179 #define WRPLL_PLL_LCPLL (3 << 28)
9180 #define WRPLL_PLL_REF_MASK (3 << 28)
9181 /* WRPLL divider programming */
9182 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
9183 #define WRPLL_DIVIDER_REF_MASK (0xff)
9184 #define WRPLL_DIVIDER_POST(x) ((x) << 8)
9185 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
9186 #define WRPLL_DIVIDER_POST_SHIFT 8
9187 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
9188 #define WRPLL_DIVIDER_FB_SHIFT 16
9189 #define WRPLL_DIVIDER_FB_MASK (0xff << 16)
9191 /* Port clock selection */
9192 #define _PORT_CLK_SEL_A 0x46100
9193 #define _PORT_CLK_SEL_B 0x46104
9194 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
9195 #define PORT_CLK_SEL_LCPLL_2700 (0 << 29)
9196 #define PORT_CLK_SEL_LCPLL_1350 (1 << 29)
9197 #define PORT_CLK_SEL_LCPLL_810 (2 << 29)
9198 #define PORT_CLK_SEL_SPLL (3 << 29)
9199 #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29)
9200 #define PORT_CLK_SEL_WRPLL1 (4 << 29)
9201 #define PORT_CLK_SEL_WRPLL2 (5 << 29)
9202 #define PORT_CLK_SEL_NONE (7 << 29)
9203 #define PORT_CLK_SEL_MASK (7 << 29)
9205 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
9206 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
9207 #define DDI_CLK_SEL_NONE (0x0 << 28)
9208 #define DDI_CLK_SEL_MG (0x8 << 28)
9209 #define DDI_CLK_SEL_TBT_162 (0xC << 28)
9210 #define DDI_CLK_SEL_TBT_270 (0xD << 28)
9211 #define DDI_CLK_SEL_TBT_540 (0xE << 28)
9212 #define DDI_CLK_SEL_TBT_810 (0xF << 28)
9213 #define DDI_CLK_SEL_MASK (0xF << 28)
9215 /* Transcoder clock selection */
9216 #define _TRANS_CLK_SEL_A 0x46140
9217 #define _TRANS_CLK_SEL_B 0x46144
9218 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
9219 /* For each transcoder, we need to select the corresponding port clock */
9220 #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
9221 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
9223 #define CDCLK_FREQ _MMIO(0x46200)
9225 #define _TRANSA_MSA_MISC 0x60410
9226 #define _TRANSB_MSA_MISC 0x61410
9227 #define _TRANSC_MSA_MISC 0x62410
9228 #define _TRANS_EDP_MSA_MISC 0x6f410
9229 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9231 #define TRANS_MSA_SYNC_CLK (1 << 0)
9232 #define TRANS_MSA_SAMPLING_444 (2 << 1)
9233 #define TRANS_MSA_CLRSP_YCBCR (2 << 3)
9234 #define TRANS_MSA_6_BPC (0 << 5)
9235 #define TRANS_MSA_8_BPC (1 << 5)
9236 #define TRANS_MSA_10_BPC (2 << 5)
9237 #define TRANS_MSA_12_BPC (3 << 5)
9238 #define TRANS_MSA_16_BPC (4 << 5)
9239 #define TRANS_MSA_CEA_RANGE (1 << 3)
9242 #define LCPLL_CTL _MMIO(0x130040)
9243 #define LCPLL_PLL_DISABLE (1 << 31)
9244 #define LCPLL_PLL_LOCK (1 << 30)
9245 #define LCPLL_CLK_FREQ_MASK (3 << 26)
9246 #define LCPLL_CLK_FREQ_450 (0 << 26)
9247 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
9248 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
9249 #define LCPLL_CLK_FREQ_675_BDW (3 << 26)
9250 #define LCPLL_CD_CLOCK_DISABLE (1 << 25)
9251 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
9252 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
9253 #define LCPLL_POWER_DOWN_ALLOW (1 << 22)
9254 #define LCPLL_CD_SOURCE_FCLK (1 << 21)
9255 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
9262 #define CDCLK_CTL _MMIO(0x46000)
9263 #define CDCLK_FREQ_SEL_MASK (3 << 26)
9264 #define CDCLK_FREQ_450_432 (0 << 26)
9265 #define CDCLK_FREQ_540 (1 << 26)
9266 #define CDCLK_FREQ_337_308 (2 << 26)
9267 #define CDCLK_FREQ_675_617 (3 << 26)
9268 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
9269 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
9270 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
9271 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
9272 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
9273 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
9274 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
9275 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
9276 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
9277 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
9278 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
9281 #define LCPLL1_CTL _MMIO(0x46010)
9282 #define LCPLL2_CTL _MMIO(0x46014)
9283 #define LCPLL_PLL_ENABLE (1 << 31)
9286 #define DPLL_CTRL1 _MMIO(0x6C058)
9287 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
9288 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
9289 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
9290 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
9291 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
9292 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
9293 #define DPLL_CTRL1_LINK_RATE_2700 0
9294 #define DPLL_CTRL1_LINK_RATE_1350 1
9295 #define DPLL_CTRL1_LINK_RATE_810 2
9296 #define DPLL_CTRL1_LINK_RATE_1620 3
9297 #define DPLL_CTRL1_LINK_RATE_1080 4
9298 #define DPLL_CTRL1_LINK_RATE_2160 5
9301 #define DPLL_CTRL2 _MMIO(0x6C05C)
9302 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
9303 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
9304 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
9305 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
9306 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
9309 #define DPLL_STATUS _MMIO(0x6C060)
9310 #define DPLL_LOCK(id) (1 << ((id) * 8))
9313 #define _DPLL1_CFGCR1 0x6C040
9314 #define _DPLL2_CFGCR1 0x6C048
9315 #define _DPLL3_CFGCR1 0x6C050
9316 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
9317 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
9318 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
9319 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
9321 #define _DPLL1_CFGCR2 0x6C044
9322 #define _DPLL2_CFGCR2 0x6C04C
9323 #define _DPLL3_CFGCR2 0x6C054
9324 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
9325 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
9326 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
9327 #define DPLL_CFGCR2_KDIV_MASK (3 << 5)
9328 #define DPLL_CFGCR2_KDIV(x) ((x) << 5)
9329 #define DPLL_CFGCR2_KDIV_5 (0 << 5)
9330 #define DPLL_CFGCR2_KDIV_2 (1 << 5)
9331 #define DPLL_CFGCR2_KDIV_3 (2 << 5)
9332 #define DPLL_CFGCR2_KDIV_1 (3 << 5)
9333 #define DPLL_CFGCR2_PDIV_MASK (7 << 2)
9334 #define DPLL_CFGCR2_PDIV(x) ((x) << 2)
9335 #define DPLL_CFGCR2_PDIV_1 (0 << 2)
9336 #define DPLL_CFGCR2_PDIV_2 (1 << 2)
9337 #define DPLL_CFGCR2_PDIV_3 (2 << 2)
9338 #define DPLL_CFGCR2_PDIV_7 (4 << 2)
9339 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
9341 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
9342 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
9347 #define DPCLKA_CFGCR0 _MMIO(0x6C200)
9348 #define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
9349 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
9351 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
9353 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9354 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9357 #define DPLL0_ENABLE 0x46010
9358 #define DPLL1_ENABLE 0x46014
9359 #define PLL_ENABLE (1 << 31)
9360 #define PLL_LOCK (1 << 30)
9361 #define PLL_POWER_ENABLE (1 << 27)
9362 #define PLL_POWER_STATE (1 << 26)
9363 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
9365 #define TBT_PLL_ENABLE _MMIO(0x46020)
9367 #define _MG_PLL1_ENABLE 0x46030
9368 #define _MG_PLL2_ENABLE 0x46034
9369 #define _MG_PLL3_ENABLE 0x46038
9370 #define _MG_PLL4_ENABLE 0x4603C
9371 /* Bits are the same as DPLL0_ENABLE */
9372 #define MG_PLL_ENABLE(port) _MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \
9375 #define _MG_REFCLKIN_CTL_PORT1 0x16892C
9376 #define _MG_REFCLKIN_CTL_PORT2 0x16992C
9377 #define _MG_REFCLKIN_CTL_PORT3 0x16A92C
9378 #define _MG_REFCLKIN_CTL_PORT4 0x16B92C
9379 #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
9380 #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
9381 #define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
9382 _MG_REFCLKIN_CTL_PORT1, \
9383 _MG_REFCLKIN_CTL_PORT2)
9385 #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
9386 #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
9387 #define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
9388 #define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
9389 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
9390 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
9391 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
9392 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
9393 #define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
9394 _MG_CLKTOP2_CORECLKCTL1_PORT1, \
9395 _MG_CLKTOP2_CORECLKCTL1_PORT2)
9397 #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
9398 #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
9399 #define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
9400 #define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
9401 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
9402 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
9403 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
9404 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
9405 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
9406 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
9407 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
9408 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
9409 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
9410 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
9411 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
9412 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
9413 #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
9414 _MG_CLKTOP2_HSCLKCTL_PORT1, \
9415 _MG_CLKTOP2_HSCLKCTL_PORT2)
9417 #define _MG_PLL_DIV0_PORT1 0x168A00
9418 #define _MG_PLL_DIV0_PORT2 0x169A00
9419 #define _MG_PLL_DIV0_PORT3 0x16AA00
9420 #define _MG_PLL_DIV0_PORT4 0x16BA00
9421 #define MG_PLL_DIV0_FRACNEN_H (1 << 30)
9422 #define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
9423 #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
9424 #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
9425 #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
9426 #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
9427 #define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \
9430 #define _MG_PLL_DIV1_PORT1 0x168A04
9431 #define _MG_PLL_DIV1_PORT2 0x169A04
9432 #define _MG_PLL_DIV1_PORT3 0x16AA04
9433 #define _MG_PLL_DIV1_PORT4 0x16BA04
9434 #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
9435 #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
9436 #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
9437 #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
9438 #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
9439 #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
9440 #define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
9441 #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
9442 #define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV1_PORT1, \
9445 #define _MG_PLL_LF_PORT1 0x168A08
9446 #define _MG_PLL_LF_PORT2 0x169A08
9447 #define _MG_PLL_LF_PORT3 0x16AA08
9448 #define _MG_PLL_LF_PORT4 0x16BA08
9449 #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
9450 #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
9451 #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
9452 #define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
9453 #define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
9454 #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
9455 #define MG_PLL_LF(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_LF_PORT1, \
9458 #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
9459 #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
9460 #define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
9461 #define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
9462 #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
9463 #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
9464 #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
9465 #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
9466 #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
9467 #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
9468 #define MG_PLL_FRAC_LOCK(port) _MMIO_PORT((port) - PORT_C, \
9469 _MG_PLL_FRAC_LOCK_PORT1, \
9470 _MG_PLL_FRAC_LOCK_PORT2)
9472 #define _MG_PLL_SSC_PORT1 0x168A10
9473 #define _MG_PLL_SSC_PORT2 0x169A10
9474 #define _MG_PLL_SSC_PORT3 0x16AA10
9475 #define _MG_PLL_SSC_PORT4 0x16BA10
9476 #define MG_PLL_SSC_EN (1 << 28)
9477 #define MG_PLL_SSC_TYPE(x) ((x) << 26)
9478 #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
9479 #define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
9480 #define MG_PLL_SSC_FLLEN (1 << 9)
9481 #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
9482 #define MG_PLL_SSC(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_SSC_PORT1, \
9485 #define _MG_PLL_BIAS_PORT1 0x168A14
9486 #define _MG_PLL_BIAS_PORT2 0x169A14
9487 #define _MG_PLL_BIAS_PORT3 0x16AA14
9488 #define _MG_PLL_BIAS_PORT4 0x16BA14
9489 #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
9490 #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
9491 #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
9492 #define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
9493 #define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
9494 #define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
9495 #define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
9496 #define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
9497 #define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
9498 #define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
9499 #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
9500 #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
9501 #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
9502 #define MG_PLL_BIAS(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_BIAS_PORT1, \
9505 #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
9506 #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
9507 #define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
9508 #define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
9509 #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
9510 #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
9511 #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
9512 #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
9513 #define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
9514 #define MG_PLL_TDC_COLDST_BIAS(port) _MMIO_PORT((port) - PORT_C, \
9515 _MG_PLL_TDC_COLDST_BIAS_PORT1, \
9516 _MG_PLL_TDC_COLDST_BIAS_PORT2)
9518 #define _CNL_DPLL0_CFGCR0 0x6C000
9519 #define _CNL_DPLL1_CFGCR0 0x6C080
9520 #define DPLL_CFGCR0_HDMI_MODE (1 << 30)
9521 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
9522 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
9523 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
9524 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
9525 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
9526 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
9527 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
9528 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
9529 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
9530 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
9531 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
9532 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
9533 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
9534 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
9535 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
9536 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
9538 #define _CNL_DPLL0_CFGCR1 0x6C004
9539 #define _CNL_DPLL1_CFGCR1 0x6C084
9540 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
9541 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
9542 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
9543 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
9544 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
9545 #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
9546 #define DPLL_CFGCR1_KDIV_SHIFT (6)
9547 #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
9548 #define DPLL_CFGCR1_KDIV_1 (1 << 6)
9549 #define DPLL_CFGCR1_KDIV_2 (2 << 6)
9550 #define DPLL_CFGCR1_KDIV_4 (4 << 6)
9551 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
9552 #define DPLL_CFGCR1_PDIV_SHIFT (2)
9553 #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
9554 #define DPLL_CFGCR1_PDIV_2 (1 << 2)
9555 #define DPLL_CFGCR1_PDIV_3 (2 << 2)
9556 #define DPLL_CFGCR1_PDIV_5 (4 << 2)
9557 #define DPLL_CFGCR1_PDIV_7 (8 << 2)
9558 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
9559 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
9560 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
9562 #define _ICL_DPLL0_CFGCR0 0x164000
9563 #define _ICL_DPLL1_CFGCR0 0x164080
9564 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
9567 #define _ICL_DPLL0_CFGCR1 0x164004
9568 #define _ICL_DPLL1_CFGCR1 0x164084
9569 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
9572 /* BXT display engine PLL */
9573 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
9574 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
9575 #define BXT_DE_PLL_RATIO_MASK 0xff
9577 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
9578 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
9579 #define BXT_DE_PLL_LOCK (1 << 30)
9580 #define CNL_CDCLK_PLL_RATIO(x) (x)
9581 #define CNL_CDCLK_PLL_RATIO_MASK 0xff
9584 #define DC_STATE_EN _MMIO(0x45504)
9585 #define DC_STATE_DISABLE 0
9586 #define DC_STATE_EN_UPTO_DC5 (1 << 0)
9587 #define DC_STATE_EN_DC9 (1 << 3)
9588 #define DC_STATE_EN_UPTO_DC6 (2 << 0)
9589 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
9591 #define DC_STATE_DEBUG _MMIO(0x45520)
9592 #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
9593 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
9595 #define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
9596 #define BXT_REQ_DATA_MASK 0x3F
9597 #define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12
9598 #define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12)
9599 #define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333
9601 #define BXT_D_CR_DRP0_DUNIT8 0x1000
9602 #define BXT_D_CR_DRP0_DUNIT9 0x1200
9603 #define BXT_D_CR_DRP0_DUNIT_START 8
9604 #define BXT_D_CR_DRP0_DUNIT_END 11
9605 #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
9606 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
9607 BXT_D_CR_DRP0_DUNIT9))
9608 #define BXT_DRAM_RANK_MASK 0x3
9609 #define BXT_DRAM_RANK_SINGLE 0x1
9610 #define BXT_DRAM_RANK_DUAL 0x3
9611 #define BXT_DRAM_WIDTH_MASK (0x3 << 4)
9612 #define BXT_DRAM_WIDTH_SHIFT 4
9613 #define BXT_DRAM_WIDTH_X8 (0x0 << 4)
9614 #define BXT_DRAM_WIDTH_X16 (0x1 << 4)
9615 #define BXT_DRAM_WIDTH_X32 (0x2 << 4)
9616 #define BXT_DRAM_WIDTH_X64 (0x3 << 4)
9617 #define BXT_DRAM_SIZE_MASK (0x7 << 6)
9618 #define BXT_DRAM_SIZE_SHIFT 6
9619 #define BXT_DRAM_SIZE_4GB (0x0 << 6)
9620 #define BXT_DRAM_SIZE_6GB (0x1 << 6)
9621 #define BXT_DRAM_SIZE_8GB (0x2 << 6)
9622 #define BXT_DRAM_SIZE_12GB (0x3 << 6)
9623 #define BXT_DRAM_SIZE_16GB (0x4 << 6)
9625 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
9626 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
9627 #define SKL_REQ_DATA_MASK (0xF << 0)
9629 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
9630 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
9631 #define SKL_DRAM_S_SHIFT 16
9632 #define SKL_DRAM_SIZE_MASK 0x3F
9633 #define SKL_DRAM_WIDTH_MASK (0x3 << 8)
9634 #define SKL_DRAM_WIDTH_SHIFT 8
9635 #define SKL_DRAM_WIDTH_X8 (0x0 << 8)
9636 #define SKL_DRAM_WIDTH_X16 (0x1 << 8)
9637 #define SKL_DRAM_WIDTH_X32 (0x2 << 8)
9638 #define SKL_DRAM_RANK_MASK (0x1 << 10)
9639 #define SKL_DRAM_RANK_SHIFT 10
9640 #define SKL_DRAM_RANK_SINGLE (0x0 << 10)
9641 #define SKL_DRAM_RANK_DUAL (0x1 << 10)
9643 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
9644 * since on HSW we can't write to it using I915_WRITE. */
9645 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
9646 #define D_COMP_BDW _MMIO(0x138144)
9647 #define D_COMP_RCOMP_IN_PROGRESS (1 << 9)
9648 #define D_COMP_COMP_FORCE (1 << 8)
9649 #define D_COMP_COMP_DISABLE (1 << 0)
9651 /* Pipe WM_LINETIME - watermark line time */
9652 #define _PIPE_WM_LINETIME_A 0x45270
9653 #define _PIPE_WM_LINETIME_B 0x45274
9654 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
9655 #define PIPE_WM_LINETIME_MASK (0x1ff)
9656 #define PIPE_WM_LINETIME_TIME(x) ((x))
9657 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16)
9658 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16)
9661 #define SFUSE_STRAP _MMIO(0xc2014)
9662 #define SFUSE_STRAP_FUSE_LOCK (1 << 13)
9663 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
9664 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
9665 #define SFUSE_STRAP_CRT_DISABLED (1 << 6)
9666 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
9667 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
9668 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
9669 #define SFUSE_STRAP_DDID_DETECTED (1 << 0)
9671 #define WM_MISC _MMIO(0x45260)
9672 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
9674 #define WM_DBG _MMIO(0x45280)
9675 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
9676 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
9677 #define WM_DBG_DISALLOW_SPRITE (1 << 2)
9680 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
9681 #define _PIPE_A_CSC_COEFF_BY 0x49014
9682 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
9683 #define _PIPE_A_CSC_COEFF_BU 0x4901c
9684 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
9685 #define _PIPE_A_CSC_COEFF_BV 0x49024
9686 #define _PIPE_A_CSC_MODE 0x49028
9687 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
9688 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
9689 #define CSC_MODE_YUV_TO_RGB (1 << 0)
9690 #define _PIPE_A_CSC_PREOFF_HI 0x49030
9691 #define _PIPE_A_CSC_PREOFF_ME 0x49034
9692 #define _PIPE_A_CSC_PREOFF_LO 0x49038
9693 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
9694 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
9695 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
9697 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
9698 #define _PIPE_B_CSC_COEFF_BY 0x49114
9699 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
9700 #define _PIPE_B_CSC_COEFF_BU 0x4911c
9701 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
9702 #define _PIPE_B_CSC_COEFF_BV 0x49124
9703 #define _PIPE_B_CSC_MODE 0x49128
9704 #define _PIPE_B_CSC_PREOFF_HI 0x49130
9705 #define _PIPE_B_CSC_PREOFF_ME 0x49134
9706 #define _PIPE_B_CSC_PREOFF_LO 0x49138
9707 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
9708 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
9709 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
9711 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
9712 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
9713 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
9714 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
9715 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
9716 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
9717 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
9718 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
9719 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
9720 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
9721 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
9722 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
9723 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
9725 /* pipe degamma/gamma LUTs on IVB+ */
9726 #define _PAL_PREC_INDEX_A 0x4A400
9727 #define _PAL_PREC_INDEX_B 0x4AC00
9728 #define _PAL_PREC_INDEX_C 0x4B400
9729 #define PAL_PREC_10_12_BIT (0 << 31)
9730 #define PAL_PREC_SPLIT_MODE (1 << 31)
9731 #define PAL_PREC_AUTO_INCREMENT (1 << 15)
9732 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
9733 #define _PAL_PREC_DATA_A 0x4A404
9734 #define _PAL_PREC_DATA_B 0x4AC04
9735 #define _PAL_PREC_DATA_C 0x4B404
9736 #define _PAL_PREC_GC_MAX_A 0x4A410
9737 #define _PAL_PREC_GC_MAX_B 0x4AC10
9738 #define _PAL_PREC_GC_MAX_C 0x4B410
9739 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
9740 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
9741 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
9742 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
9743 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
9744 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
9746 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
9747 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
9748 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
9749 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
9751 #define _PRE_CSC_GAMC_INDEX_A 0x4A484
9752 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
9753 #define _PRE_CSC_GAMC_INDEX_C 0x4B484
9754 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
9755 #define _PRE_CSC_GAMC_DATA_A 0x4A488
9756 #define _PRE_CSC_GAMC_DATA_B 0x4AC88
9757 #define _PRE_CSC_GAMC_DATA_C 0x4B488
9759 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
9760 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
9762 /* pipe CSC & degamma/gamma LUTs on CHV */
9763 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
9764 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
9765 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
9766 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
9767 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
9768 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
9769 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
9770 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
9771 #define CGM_PIPE_MODE_GAMMA (1 << 2)
9772 #define CGM_PIPE_MODE_CSC (1 << 1)
9773 #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
9775 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
9776 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
9777 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
9778 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
9779 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
9780 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
9781 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
9782 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
9784 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
9785 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
9786 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
9787 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
9788 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
9789 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
9790 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
9791 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
9793 /* MIPI DSI registers */
9795 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
9796 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
9798 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
9799 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
9800 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
9801 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
9803 #define _ICL_DSI_ESC_CLK_DIV0 0x6b090
9804 #define _ICL_DSI_ESC_CLK_DIV1 0x6b890
9805 #define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \
9806 _ICL_DSI_ESC_CLK_DIV0, \
9807 _ICL_DSI_ESC_CLK_DIV1)
9808 #define _ICL_DPHY_ESC_CLK_DIV0 0x162190
9809 #define _ICL_DPHY_ESC_CLK_DIV1 0x6C190
9810 #define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \
9811 _ICL_DPHY_ESC_CLK_DIV0, \
9812 _ICL_DPHY_ESC_CLK_DIV1)
9813 #define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16)
9814 #define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
9815 #define ICL_ESC_CLK_DIV_MASK 0x1ff
9816 #define ICL_ESC_CLK_DIV_SHIFT 0
9817 #define DSI_MAX_ESC_CLK 20000 /* in KHz */
9819 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
9820 #define GEN4_TIMESTAMP _MMIO(0x2358)
9821 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
9822 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
9824 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
9825 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
9826 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
9827 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
9828 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
9830 #define _PIPE_FRMTMSTMP_A 0x70048
9831 #define PIPE_FRMTMSTMP(pipe) \
9832 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
9834 /* BXT MIPI clock controls */
9835 #define BXT_MAX_VAR_OUTPUT_KHZ 39500
9837 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
9838 #define BXT_MIPI1_DIV_SHIFT 26
9839 #define BXT_MIPI2_DIV_SHIFT 10
9840 #define BXT_MIPI_DIV_SHIFT(port) \
9841 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
9842 BXT_MIPI2_DIV_SHIFT)
9844 /* TX control divider to select actual TX clock output from (8x/var) */
9845 #define BXT_MIPI1_TX_ESCLK_SHIFT 26
9846 #define BXT_MIPI2_TX_ESCLK_SHIFT 10
9847 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
9848 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
9849 BXT_MIPI2_TX_ESCLK_SHIFT)
9850 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
9851 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
9852 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
9853 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
9854 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
9855 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
9856 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
9857 /* RX upper control divider to select actual RX clock output from 8x */
9858 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
9859 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
9860 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
9861 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
9862 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
9863 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
9864 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
9865 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
9866 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
9867 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
9868 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
9869 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
9870 /* 8/3X divider to select the actual 8/3X clock output from 8x */
9871 #define BXT_MIPI1_8X_BY3_SHIFT 19
9872 #define BXT_MIPI2_8X_BY3_SHIFT 3
9873 #define BXT_MIPI_8X_BY3_SHIFT(port) \
9874 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
9875 BXT_MIPI2_8X_BY3_SHIFT)
9876 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
9877 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
9878 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
9879 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
9880 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
9881 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
9882 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
9883 /* RX lower control divider to select actual RX clock output from 8x */
9884 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
9885 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
9886 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
9887 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
9888 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
9889 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
9890 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
9891 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
9892 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
9893 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
9894 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
9895 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
9897 #define RX_DIVIDER_BIT_1_2 0x3
9898 #define RX_DIVIDER_BIT_3_4 0xC
9900 /* BXT MIPI mode configure */
9901 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
9902 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
9903 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
9904 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
9906 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
9907 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
9908 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
9909 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
9911 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
9912 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
9913 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
9914 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
9916 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
9917 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
9918 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9919 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9920 #define BXT_DSIC_16X_BY1 (0 << 10)
9921 #define BXT_DSIC_16X_BY2 (1 << 10)
9922 #define BXT_DSIC_16X_BY3 (2 << 10)
9923 #define BXT_DSIC_16X_BY4 (3 << 10)
9924 #define BXT_DSIC_16X_MASK (3 << 10)
9925 #define BXT_DSIA_16X_BY1 (0 << 8)
9926 #define BXT_DSIA_16X_BY2 (1 << 8)
9927 #define BXT_DSIA_16X_BY3 (2 << 8)
9928 #define BXT_DSIA_16X_BY4 (3 << 8)
9929 #define BXT_DSIA_16X_MASK (3 << 8)
9930 #define BXT_DSI_FREQ_SEL_SHIFT 8
9931 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
9933 #define BXT_DSI_PLL_RATIO_MAX 0x7D
9934 #define BXT_DSI_PLL_RATIO_MIN 0x22
9935 #define GLK_DSI_PLL_RATIO_MAX 0x6F
9936 #define GLK_DSI_PLL_RATIO_MIN 0x22
9937 #define BXT_DSI_PLL_RATIO_MASK 0xFF
9938 #define BXT_REF_CLOCK_KHZ 19200
9940 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
9941 #define BXT_DSI_PLL_DO_ENABLE (1 << 31)
9942 #define BXT_DSI_PLL_LOCKED (1 << 30)
9944 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
9945 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
9946 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
9948 /* BXT port control */
9949 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0
9950 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
9951 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
9953 /* ICL DSI MODE control */
9954 #define _ICL_DSI_IO_MODECTL_0 0x6B094
9955 #define _ICL_DSI_IO_MODECTL_1 0x6B894
9956 #define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \
9957 _ICL_DSI_IO_MODECTL_0, \
9958 _ICL_DSI_IO_MODECTL_1)
9959 #define COMBO_PHY_MODE_DSI (1 << 0)
9961 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
9962 #define STAP_SELECT (1 << 0)
9964 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
9965 #define HS_IO_CTRL_SELECT (1 << 0)
9967 #define DPI_ENABLE (1 << 31) /* A + C */
9968 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
9969 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
9970 #define DUAL_LINK_MODE_SHIFT 26
9971 #define DUAL_LINK_MODE_MASK (1 << 26)
9972 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
9973 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
9974 #define DITHERING_ENABLE (1 << 25) /* A + C */
9975 #define FLOPPED_HSTX (1 << 23)
9976 #define DE_INVERT (1 << 19) /* XXX */
9977 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
9978 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
9979 #define AFE_LATCHOUT (1 << 17)
9980 #define LP_OUTPUT_HOLD (1 << 16)
9981 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
9982 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
9983 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
9984 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
9986 #define CSB_MASK (3 << 9)
9987 #define CSB_20MHZ (0 << 9)
9988 #define CSB_10MHZ (1 << 9)
9989 #define CSB_40MHZ (2 << 9)
9990 #define BANDGAP_MASK (1 << 8)
9991 #define BANDGAP_PNW_CIRCUIT (0 << 8)
9992 #define BANDGAP_LNC_CIRCUIT (1 << 8)
9993 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
9994 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
9995 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
9996 #define TEARING_EFFECT_SHIFT 2 /* A + C */
9997 #define TEARING_EFFECT_MASK (3 << 2)
9998 #define TEARING_EFFECT_OFF (0 << 2)
9999 #define TEARING_EFFECT_DSI (1 << 2)
10000 #define TEARING_EFFECT_GPIO (2 << 2)
10001 #define LANE_CONFIGURATION_SHIFT 0
10002 #define LANE_CONFIGURATION_MASK (3 << 0)
10003 #define LANE_CONFIGURATION_4LANE (0 << 0)
10004 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
10005 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
10007 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
10008 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
10009 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
10010 #define TEARING_EFFECT_DELAY_SHIFT 0
10011 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
10013 /* XXX: all bits reserved */
10014 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
10016 /* MIPI DSI Controller and D-PHY registers */
10018 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
10019 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
10020 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
10021 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
10022 #define ULPS_STATE_MASK (3 << 1)
10023 #define ULPS_STATE_ENTER (2 << 1)
10024 #define ULPS_STATE_EXIT (1 << 1)
10025 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
10026 #define DEVICE_READY (1 << 0)
10028 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
10029 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
10030 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
10031 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
10032 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
10033 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
10034 #define TEARING_EFFECT (1 << 31)
10035 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
10036 #define GEN_READ_DATA_AVAIL (1 << 29)
10037 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
10038 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
10039 #define RX_PROT_VIOLATION (1 << 26)
10040 #define RX_INVALID_TX_LENGTH (1 << 25)
10041 #define ACK_WITH_NO_ERROR (1 << 24)
10042 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
10043 #define LP_RX_TIMEOUT (1 << 22)
10044 #define HS_TX_TIMEOUT (1 << 21)
10045 #define DPI_FIFO_UNDERRUN (1 << 20)
10046 #define LOW_CONTENTION (1 << 19)
10047 #define HIGH_CONTENTION (1 << 18)
10048 #define TXDSI_VC_ID_INVALID (1 << 17)
10049 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
10050 #define TXCHECKSUM_ERROR (1 << 15)
10051 #define TXECC_MULTIBIT_ERROR (1 << 14)
10052 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
10053 #define TXFALSE_CONTROL_ERROR (1 << 12)
10054 #define RXDSI_VC_ID_INVALID (1 << 11)
10055 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
10056 #define RXCHECKSUM_ERROR (1 << 9)
10057 #define RXECC_MULTIBIT_ERROR (1 << 8)
10058 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
10059 #define RXFALSE_CONTROL_ERROR (1 << 6)
10060 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
10061 #define RX_LP_TX_SYNC_ERROR (1 << 4)
10062 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
10063 #define RXEOT_SYNC_ERROR (1 << 2)
10064 #define RXSOT_SYNC_ERROR (1 << 1)
10065 #define RXSOT_ERROR (1 << 0)
10067 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
10068 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
10069 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
10070 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
10071 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
10072 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
10073 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
10074 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
10075 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
10076 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
10077 #define VID_MODE_FORMAT_MASK (0xf << 7)
10078 #define VID_MODE_NOT_SUPPORTED (0 << 7)
10079 #define VID_MODE_FORMAT_RGB565 (1 << 7)
10080 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
10081 #define VID_MODE_FORMAT_RGB666 (3 << 7)
10082 #define VID_MODE_FORMAT_RGB888 (4 << 7)
10083 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
10084 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
10085 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
10086 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
10087 #define DATA_LANES_PRG_REG_SHIFT 0
10088 #define DATA_LANES_PRG_REG_MASK (7 << 0)
10090 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
10091 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
10092 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
10093 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
10095 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
10096 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
10097 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
10098 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
10100 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
10101 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
10102 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
10103 #define TURN_AROUND_TIMEOUT_MASK 0x3f
10105 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
10106 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
10107 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
10108 #define DEVICE_RESET_TIMER_MASK 0xffff
10110 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
10111 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
10112 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
10113 #define VERTICAL_ADDRESS_SHIFT 16
10114 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
10115 #define HORIZONTAL_ADDRESS_SHIFT 0
10116 #define HORIZONTAL_ADDRESS_MASK 0xffff
10118 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
10119 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
10120 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
10121 #define DBI_FIFO_EMPTY_HALF (0 << 0)
10122 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
10123 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
10125 /* regs below are bits 15:0 */
10126 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
10127 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
10128 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
10130 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
10131 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
10132 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
10134 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
10135 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
10136 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
10138 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
10139 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
10140 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
10142 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
10143 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
10144 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
10146 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
10147 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
10148 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
10150 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
10151 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
10152 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
10154 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
10155 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
10156 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
10158 /* regs above are bits 15:0 */
10160 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
10161 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
10162 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
10163 #define DPI_LP_MODE (1 << 6)
10164 #define BACKLIGHT_OFF (1 << 5)
10165 #define BACKLIGHT_ON (1 << 4)
10166 #define COLOR_MODE_OFF (1 << 3)
10167 #define COLOR_MODE_ON (1 << 2)
10168 #define TURN_ON (1 << 1)
10169 #define SHUTDOWN (1 << 0)
10171 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
10172 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
10173 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
10174 #define COMMAND_BYTE_SHIFT 0
10175 #define COMMAND_BYTE_MASK (0x3f << 0)
10177 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
10178 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
10179 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
10180 #define MASTER_INIT_TIMER_SHIFT 0
10181 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
10183 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
10184 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
10185 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
10186 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
10187 #define MAX_RETURN_PKT_SIZE_SHIFT 0
10188 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
10190 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
10191 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
10192 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
10193 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
10194 #define DISABLE_VIDEO_BTA (1 << 3)
10195 #define IP_TG_CONFIG (1 << 2)
10196 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
10197 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
10198 #define VIDEO_MODE_BURST (3 << 0)
10200 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
10201 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
10202 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
10203 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
10204 #define BXT_DPHY_DEFEATURE_EN (1 << 8)
10205 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
10206 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
10207 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
10208 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
10209 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
10210 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
10211 #define CLOCKSTOP (1 << 1)
10212 #define EOT_DISABLE (1 << 0)
10214 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
10215 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
10216 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
10217 #define LP_BYTECLK_SHIFT 0
10218 #define LP_BYTECLK_MASK (0xffff << 0)
10220 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
10221 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
10222 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
10224 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
10225 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
10226 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
10229 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
10230 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
10231 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
10234 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
10235 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
10236 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
10238 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
10239 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
10240 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
10241 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
10242 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
10243 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
10244 #define LONG_PACKET_WORD_COUNT_SHIFT 8
10245 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
10246 #define SHORT_PACKET_PARAM_SHIFT 8
10247 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
10248 #define VIRTUAL_CHANNEL_SHIFT 6
10249 #define VIRTUAL_CHANNEL_MASK (3 << 6)
10250 #define DATA_TYPE_SHIFT 0
10251 #define DATA_TYPE_MASK (0x3f << 0)
10252 /* data type values, see include/video/mipi_display.h */
10254 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
10255 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
10256 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
10257 #define DPI_FIFO_EMPTY (1 << 28)
10258 #define DBI_FIFO_EMPTY (1 << 27)
10259 #define LP_CTRL_FIFO_EMPTY (1 << 26)
10260 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
10261 #define LP_CTRL_FIFO_FULL (1 << 24)
10262 #define HS_CTRL_FIFO_EMPTY (1 << 18)
10263 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
10264 #define HS_CTRL_FIFO_FULL (1 << 16)
10265 #define LP_DATA_FIFO_EMPTY (1 << 10)
10266 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
10267 #define LP_DATA_FIFO_FULL (1 << 8)
10268 #define HS_DATA_FIFO_EMPTY (1 << 2)
10269 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
10270 #define HS_DATA_FIFO_FULL (1 << 0)
10272 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
10273 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
10274 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
10275 #define DBI_HS_LP_MODE_MASK (1 << 0)
10276 #define DBI_LP_MODE (1 << 0)
10277 #define DBI_HS_MODE (0 << 0)
10279 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
10280 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
10281 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
10282 #define EXIT_ZERO_COUNT_SHIFT 24
10283 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
10284 #define TRAIL_COUNT_SHIFT 16
10285 #define TRAIL_COUNT_MASK (0x1f << 16)
10286 #define CLK_ZERO_COUNT_SHIFT 8
10287 #define CLK_ZERO_COUNT_MASK (0xff << 8)
10288 #define PREPARE_COUNT_SHIFT 0
10289 #define PREPARE_COUNT_MASK (0x3f << 0)
10291 #define _ICL_DSI_T_INIT_MASTER_0 0x6b088
10292 #define _ICL_DSI_T_INIT_MASTER_1 0x6b888
10293 #define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \
10294 _ICL_DSI_T_INIT_MASTER_0,\
10295 _ICL_DSI_T_INIT_MASTER_1)
10297 #define _DPHY_CLK_TIMING_PARAM_0 0x162180
10298 #define _DPHY_CLK_TIMING_PARAM_1 0x6c180
10299 #define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
10300 _DPHY_CLK_TIMING_PARAM_0,\
10301 _DPHY_CLK_TIMING_PARAM_1)
10302 #define _DSI_CLK_TIMING_PARAM_0 0x6b080
10303 #define _DSI_CLK_TIMING_PARAM_1 0x6b880
10304 #define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
10305 _DSI_CLK_TIMING_PARAM_0,\
10306 _DSI_CLK_TIMING_PARAM_1)
10307 #define CLK_PREPARE_OVERRIDE (1 << 31)
10308 #define CLK_PREPARE(x) ((x) << 28)
10309 #define CLK_PREPARE_MASK (0x7 << 28)
10310 #define CLK_PREPARE_SHIFT 28
10311 #define CLK_ZERO_OVERRIDE (1 << 27)
10312 #define CLK_ZERO(x) ((x) << 20)
10313 #define CLK_ZERO_MASK (0xf << 20)
10314 #define CLK_ZERO_SHIFT 20
10315 #define CLK_PRE_OVERRIDE (1 << 19)
10316 #define CLK_PRE(x) ((x) << 16)
10317 #define CLK_PRE_MASK (0x3 << 16)
10318 #define CLK_PRE_SHIFT 16
10319 #define CLK_POST_OVERRIDE (1 << 15)
10320 #define CLK_POST(x) ((x) << 8)
10321 #define CLK_POST_MASK (0x7 << 8)
10322 #define CLK_POST_SHIFT 8
10323 #define CLK_TRAIL_OVERRIDE (1 << 7)
10324 #define CLK_TRAIL(x) ((x) << 0)
10325 #define CLK_TRAIL_MASK (0xf << 0)
10326 #define CLK_TRAIL_SHIFT 0
10328 #define _DPHY_DATA_TIMING_PARAM_0 0x162184
10329 #define _DPHY_DATA_TIMING_PARAM_1 0x6c184
10330 #define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
10331 _DPHY_DATA_TIMING_PARAM_0,\
10332 _DPHY_DATA_TIMING_PARAM_1)
10333 #define _DSI_DATA_TIMING_PARAM_0 0x6B084
10334 #define _DSI_DATA_TIMING_PARAM_1 0x6B884
10335 #define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
10336 _DSI_DATA_TIMING_PARAM_0,\
10337 _DSI_DATA_TIMING_PARAM_1)
10338 #define HS_PREPARE_OVERRIDE (1 << 31)
10339 #define HS_PREPARE(x) ((x) << 24)
10340 #define HS_PREPARE_MASK (0x7 << 24)
10341 #define HS_PREPARE_SHIFT 24
10342 #define HS_ZERO_OVERRIDE (1 << 23)
10343 #define HS_ZERO(x) ((x) << 16)
10344 #define HS_ZERO_MASK (0xf << 16)
10345 #define HS_ZERO_SHIFT 16
10346 #define HS_TRAIL_OVERRIDE (1 << 15)
10347 #define HS_TRAIL(x) ((x) << 8)
10348 #define HS_TRAIL_MASK (0x7 << 8)
10349 #define HS_TRAIL_SHIFT 8
10350 #define HS_EXIT_OVERRIDE (1 << 7)
10351 #define HS_EXIT(x) ((x) << 0)
10352 #define HS_EXIT_MASK (0x7 << 0)
10353 #define HS_EXIT_SHIFT 0
10355 #define _DPHY_TA_TIMING_PARAM_0 0x162188
10356 #define _DPHY_TA_TIMING_PARAM_1 0x6c188
10357 #define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
10358 _DPHY_TA_TIMING_PARAM_0,\
10359 _DPHY_TA_TIMING_PARAM_1)
10360 #define _DSI_TA_TIMING_PARAM_0 0x6b098
10361 #define _DSI_TA_TIMING_PARAM_1 0x6b898
10362 #define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
10363 _DSI_TA_TIMING_PARAM_0,\
10364 _DSI_TA_TIMING_PARAM_1)
10365 #define TA_SURE_OVERRIDE (1 << 31)
10366 #define TA_SURE(x) ((x) << 16)
10367 #define TA_SURE_MASK (0x1f << 16)
10368 #define TA_SURE_SHIFT 16
10369 #define TA_GO_OVERRIDE (1 << 15)
10370 #define TA_GO(x) ((x) << 8)
10371 #define TA_GO_MASK (0xf << 8)
10372 #define TA_GO_SHIFT 8
10373 #define TA_GET_OVERRIDE (1 << 7)
10374 #define TA_GET(x) ((x) << 0)
10375 #define TA_GET_MASK (0xf << 0)
10376 #define TA_GET_SHIFT 0
10379 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
10380 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
10381 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
10383 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
10384 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
10385 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
10386 #define LP_HS_SSW_CNT_SHIFT 16
10387 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
10388 #define HS_LP_PWR_SW_CNT_SHIFT 0
10389 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
10391 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
10392 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
10393 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
10394 #define STOP_STATE_STALL_COUNTER_SHIFT 0
10395 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
10397 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
10398 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
10399 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
10400 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
10401 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
10402 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
10403 #define RX_CONTENTION_DETECTED (1 << 0)
10405 /* XXX: only pipe A ?!? */
10406 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
10407 #define DBI_TYPEC_ENABLE (1 << 31)
10408 #define DBI_TYPEC_WIP (1 << 30)
10409 #define DBI_TYPEC_OPTION_SHIFT 28
10410 #define DBI_TYPEC_OPTION_MASK (3 << 28)
10411 #define DBI_TYPEC_FREQ_SHIFT 24
10412 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
10413 #define DBI_TYPEC_OVERRIDE (1 << 8)
10414 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
10415 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
10418 /* MIPI adapter registers */
10420 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
10421 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
10422 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
10423 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
10424 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
10425 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
10426 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
10427 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
10428 #define READ_REQUEST_PRIORITY_SHIFT 3
10429 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
10430 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
10431 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
10432 #define RGB_FLIP_TO_BGR (1 << 2)
10434 #define BXT_PIPE_SELECT_SHIFT 7
10435 #define BXT_PIPE_SELECT_MASK (7 << 7)
10436 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
10437 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
10438 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
10439 #define GLK_MIPIIO_RESET_RELEASED (1 << 28)
10440 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
10441 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
10442 #define GLK_LP_WAKE (1 << 22)
10443 #define GLK_LP11_LOW_PWR_MODE (1 << 21)
10444 #define GLK_LP00_LOW_PWR_MODE (1 << 20)
10445 #define GLK_FIREWALL_ENABLE (1 << 16)
10446 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
10447 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
10448 #define BXT_DSC_ENABLE (1 << 3)
10449 #define BXT_RGB_FLIP (1 << 2)
10450 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
10451 #define GLK_MIPIIO_ENABLE (1 << 0)
10453 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
10454 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
10455 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
10456 #define DATA_MEM_ADDRESS_SHIFT 5
10457 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
10458 #define DATA_VALID (1 << 0)
10460 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
10461 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
10462 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
10463 #define DATA_LENGTH_SHIFT 0
10464 #define DATA_LENGTH_MASK (0xfffff << 0)
10466 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
10467 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
10468 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
10469 #define COMMAND_MEM_ADDRESS_SHIFT 5
10470 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
10471 #define AUTO_PWG_ENABLE (1 << 2)
10472 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
10473 #define COMMAND_VALID (1 << 0)
10475 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
10476 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
10477 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
10478 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
10479 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
10481 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
10482 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
10483 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
10485 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
10486 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
10487 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
10488 #define READ_DATA_VALID(n) (1 << (n))
10490 /* For UMS only (deprecated): */
10491 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
10492 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
10494 /* MOCS (Memory Object Control State) registers */
10495 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
10497 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
10498 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
10499 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
10500 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
10501 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
10502 /* Media decoder 2 MOCS registers */
10503 #define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)
10505 #define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
10506 #define PMFLUSHDONE_LNICRSDROP (1 << 20)
10507 #define PMFLUSH_GAPL3UNBLOCK (1 << 21)
10508 #define PMFLUSHDONE_LNEBLK (1 << 22)
10511 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
10512 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
10513 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
10514 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
10515 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
10517 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
10518 #define MMCD_PCLA (1 << 31)
10519 #define MMCD_HOTSPOT_EN (1 << 27)
10521 #define _ICL_PHY_MISC_A 0x64C00
10522 #define _ICL_PHY_MISC_B 0x64C04
10523 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
10525 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
10527 /* Icelake Display Stream Compression Registers */
10528 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
10529 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
10530 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
10531 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
10532 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
10533 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
10534 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10535 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
10536 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
10537 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10538 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
10539 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
10540 #define DSC_VBR_ENABLE (1 << 19)
10541 #define DSC_422_ENABLE (1 << 18)
10542 #define DSC_COLOR_SPACE_CONVERSION (1 << 17)
10543 #define DSC_BLOCK_PREDICTION (1 << 16)
10544 #define DSC_LINE_BUF_DEPTH_SHIFT 12
10545 #define DSC_BPC_SHIFT 8
10546 #define DSC_VER_MIN_SHIFT 4
10547 #define DSC_VER_MAJ (0x1 << 0)
10549 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
10550 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
10551 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
10552 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
10553 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
10554 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
10555 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10556 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
10557 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
10558 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10559 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
10560 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
10561 #define DSC_BPP(bpp) ((bpp) << 0)
10563 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
10564 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
10565 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
10566 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
10567 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
10568 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
10569 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10570 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
10571 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
10572 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10573 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
10574 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
10575 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
10576 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
10578 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
10579 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
10580 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
10581 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
10582 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
10583 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
10584 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10585 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
10586 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
10587 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10588 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
10589 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
10590 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
10591 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
10593 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
10594 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
10595 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
10596 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
10597 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
10598 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
10599 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10600 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
10601 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
10602 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10603 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
10604 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
10605 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
10606 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
10608 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
10609 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
10610 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
10611 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
10612 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
10613 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
10614 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10615 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
10616 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
10617 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10618 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
10619 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
10620 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
10621 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
10623 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
10624 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
10625 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
10626 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
10627 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
10628 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
10629 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10630 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
10631 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
10632 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10633 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
10634 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
10635 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
10636 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
10637 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
10638 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
10640 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
10641 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
10642 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
10643 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
10644 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
10645 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
10646 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10647 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
10648 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
10649 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10650 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
10651 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
10652 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
10653 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
10655 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
10656 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
10657 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
10658 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
10659 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
10660 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
10661 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10662 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
10663 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
10664 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10665 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
10666 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
10667 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
10668 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
10670 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
10671 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
10672 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
10673 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
10674 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
10675 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
10676 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10677 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
10678 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
10679 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10680 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
10681 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
10682 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
10683 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
10685 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
10686 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
10687 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
10688 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
10689 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
10690 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
10691 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10692 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
10693 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
10694 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10695 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
10696 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
10697 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
10698 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
10699 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
10700 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
10702 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
10703 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
10704 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
10705 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
10706 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
10707 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
10708 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10709 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
10710 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
10711 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10712 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
10713 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
10715 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
10716 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
10717 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
10718 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
10719 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
10720 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
10721 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10722 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
10723 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
10724 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10725 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
10726 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
10728 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
10729 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
10730 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
10731 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
10732 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
10733 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
10734 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10735 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
10736 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
10737 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10738 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
10739 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
10741 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
10742 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
10743 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
10744 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
10745 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
10746 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
10747 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10748 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
10749 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
10750 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10751 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
10752 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
10754 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
10755 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
10756 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
10757 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
10758 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
10759 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
10760 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10761 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
10762 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
10763 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10764 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
10765 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
10767 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
10768 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
10769 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
10770 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
10771 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
10772 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
10773 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10774 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
10775 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
10776 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10777 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
10778 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
10779 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
10780 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
10782 /* Icelake Rate Control Buffer Threshold Registers */
10783 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
10784 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
10785 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
10786 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
10787 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
10788 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
10789 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
10790 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
10791 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
10792 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
10793 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
10794 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
10795 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10796 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
10797 _ICL_DSC0_RC_BUF_THRESH_0_PC)
10798 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10799 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
10800 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
10801 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10802 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
10803 _ICL_DSC1_RC_BUF_THRESH_0_PC)
10804 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10805 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
10806 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
10808 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
10809 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
10810 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
10811 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
10812 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
10813 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
10814 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
10815 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
10816 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
10817 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
10818 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
10819 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
10820 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10821 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
10822 _ICL_DSC0_RC_BUF_THRESH_1_PC)
10823 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10824 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
10825 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
10826 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10827 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
10828 _ICL_DSC1_RC_BUF_THRESH_1_PC)
10829 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10830 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
10831 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
10833 #define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
10834 #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
10835 #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
10836 #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
10837 #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
10838 #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
10840 #define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
10841 #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
10843 #define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
10844 #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
10846 #endif /* _I915_REG_H_ */