1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory.
32 #define INTEL_GMCH_CTRL 0x52
33 #define INTEL_GMCH_ENABLED 0x4
34 #define INTEL_GMCH_MEM_MASK 0x1
35 #define INTEL_GMCH_MEM_64M 0x1
36 #define INTEL_GMCH_MEM_128M 0
38 #define INTEL_GMCH_GMS_MASK (0xf << 4)
39 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
40 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
41 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
42 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
46 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
47 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
48 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
49 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
50 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
51 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
52 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
53 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
55 /* PCI config space */
57 #define HPLLCC 0xc0 /* 855 only */
58 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
59 #define GC_CLOCK_133_200 (0 << 0)
60 #define GC_CLOCK_100_200 (1 << 0)
61 #define GC_CLOCK_100_133 (2 << 0)
62 #define GC_CLOCK_166_250 (3 << 0)
63 #define GCFGC 0xf0 /* 915+ only */
64 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
65 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
66 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
67 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
68 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
69 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
70 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
71 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
72 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
73 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
74 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
75 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
76 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
77 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
78 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
79 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
80 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
81 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
82 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
83 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
84 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
85 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
86 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
89 #define GDRST_FULL (0<<2)
90 #define GDRST_RENDER (1<<2)
91 #define GDRST_MEDIA (3<<2)
95 #define VGA_ST01_MDA 0x3ba
96 #define VGA_ST01_CGA 0x3da
98 #define VGA_MSR_WRITE 0x3c2
99 #define VGA_MSR_READ 0x3cc
100 #define VGA_MSR_MEM_EN (1<<1)
101 #define VGA_MSR_CGA_MODE (1<<0)
103 #define VGA_SR_INDEX 0x3c4
104 #define VGA_SR_DATA 0x3c5
106 #define VGA_AR_INDEX 0x3c0
107 #define VGA_AR_VID_EN (1<<5)
108 #define VGA_AR_DATA_WRITE 0x3c0
109 #define VGA_AR_DATA_READ 0x3c1
111 #define VGA_GR_INDEX 0x3ce
112 #define VGA_GR_DATA 0x3cf
114 #define VGA_GR_MEM_READ_MODE_SHIFT 3
115 #define VGA_GR_MEM_READ_MODE_PLANE 1
117 #define VGA_GR_MEM_MODE_MASK 0xc
118 #define VGA_GR_MEM_MODE_SHIFT 2
119 #define VGA_GR_MEM_A0000_AFFFF 0
120 #define VGA_GR_MEM_A0000_BFFFF 1
121 #define VGA_GR_MEM_B0000_B7FFF 2
122 #define VGA_GR_MEM_B0000_BFFFF 3
124 #define VGA_DACMASK 0x3c6
125 #define VGA_DACRX 0x3c7
126 #define VGA_DACWX 0x3c8
127 #define VGA_DACDATA 0x3c9
129 #define VGA_CR_INDEX_MDA 0x3b4
130 #define VGA_CR_DATA_MDA 0x3b5
131 #define VGA_CR_INDEX_CGA 0x3d4
132 #define VGA_CR_DATA_CGA 0x3d5
135 * Memory interface instructions used by the kernel
137 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
139 #define MI_NOOP MI_INSTR(0, 0)
140 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
141 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
142 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
143 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
144 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
145 #define MI_FLUSH MI_INSTR(0x04, 0)
146 #define MI_READ_FLUSH (1 << 0)
147 #define MI_EXE_FLUSH (1 << 1)
148 #define MI_NO_WRITE_FLUSH (1 << 2)
149 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
150 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
151 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
152 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
153 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
154 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
155 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
156 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
157 #define MI_STORE_DWORD_INDEX_SHIFT 2
158 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
159 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
160 #define MI_BATCH_NON_SECURE (1)
161 #define MI_BATCH_NON_SECURE_I965 (1<<8)
162 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
165 * 3D instructions used by the kernel
167 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
169 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
170 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
171 #define SC_UPDATE_SCISSOR (0x1<<1)
172 #define SC_ENABLE_MASK (0x1<<0)
173 #define SC_ENABLE (0x1<<0)
174 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
175 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
176 #define SCI_YMIN_MASK (0xffff<<16)
177 #define SCI_XMIN_MASK (0xffff<<0)
178 #define SCI_YMAX_MASK (0xffff<<16)
179 #define SCI_XMAX_MASK (0xffff<<0)
180 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
181 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
182 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
183 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
184 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
185 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
186 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
187 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
188 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
189 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
190 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
191 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
192 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
193 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
194 #define BLT_DEPTH_8 (0<<24)
195 #define BLT_DEPTH_16_565 (1<<24)
196 #define BLT_DEPTH_16_1555 (2<<24)
197 #define BLT_DEPTH_32 (3<<24)
198 #define BLT_ROP_GXCOPY (0xcc<<16)
199 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
200 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
201 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
202 #define ASYNC_FLIP (1<<22)
203 #define DISPLAY_PLANE_A (0<<20)
204 #define DISPLAY_PLANE_B (1<<20)
209 #define FENCE_REG_830_0 0x2000
210 #define FENCE_REG_945_8 0x3000
211 #define I830_FENCE_START_MASK 0x07f80000
212 #define I830_FENCE_TILING_Y_SHIFT 12
213 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
214 #define I830_FENCE_PITCH_SHIFT 4
215 #define I830_FENCE_REG_VALID (1<<0)
216 #define I915_FENCE_MAX_PITCH_VAL 0x10
217 #define I830_FENCE_MAX_PITCH_VAL 6
218 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
220 #define I915_FENCE_START_MASK 0x0ff00000
221 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
223 #define FENCE_REG_965_0 0x03000
224 #define I965_FENCE_PITCH_SHIFT 2
225 #define I965_FENCE_TILING_Y_SHIFT 1
226 #define I965_FENCE_REG_VALID (1<<0)
227 #define I965_FENCE_MAX_PITCH_VAL 0x0400
230 * Instruction and interrupt control regs
232 #define PGTBL_ER 0x02024
233 #define PRB0_TAIL 0x02030
234 #define PRB0_HEAD 0x02034
235 #define PRB0_START 0x02038
236 #define PRB0_CTL 0x0203c
237 #define TAIL_ADDR 0x001FFFF8
238 #define HEAD_WRAP_COUNT 0xFFE00000
239 #define HEAD_WRAP_ONE 0x00200000
240 #define HEAD_ADDR 0x001FFFFC
241 #define RING_NR_PAGES 0x001FF000
242 #define RING_REPORT_MASK 0x00000006
243 #define RING_REPORT_64K 0x00000002
244 #define RING_REPORT_128K 0x00000004
245 #define RING_NO_REPORT 0x00000000
246 #define RING_VALID_MASK 0x00000001
247 #define RING_VALID 0x00000001
248 #define RING_INVALID 0x00000000
249 #define PRB1_TAIL 0x02040 /* 915+ only */
250 #define PRB1_HEAD 0x02044 /* 915+ only */
251 #define PRB1_START 0x02048 /* 915+ only */
252 #define PRB1_CTL 0x0204c /* 915+ only */
253 #define IPEIR_I965 0x02064
254 #define IPEHR_I965 0x02068
255 #define INSTDONE_I965 0x0206c
256 #define INSTPS 0x02070 /* 965+ only */
257 #define INSTDONE1 0x0207c /* 965+ only */
258 #define ACTHD_I965 0x02074
259 #define HWS_PGA 0x02080
260 #define HWS_ADDRESS_MASK 0xfffff000
261 #define HWS_START_ADDRESS_SHIFT 4
262 #define IPEIR 0x02088
263 #define IPEHR 0x0208c
264 #define INSTDONE 0x02090
265 #define NOPID 0x02094
266 #define HWSTAM 0x02098
267 #define SCPD0 0x0209c /* 915+ only */
272 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
273 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
274 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
275 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
276 #define I915_HWB_OOM_INTERRUPT (1<<13)
277 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
278 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
279 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
280 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
281 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
282 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
283 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
284 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
285 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
286 #define I915_DEBUG_INTERRUPT (1<<2)
287 #define I915_USER_INTERRUPT (1<<1)
288 #define I915_ASLE_INTERRUPT (1<<0)
292 #define GM45_ERROR_PAGE_TABLE (1<<5)
293 #define GM45_ERROR_MEM_PRIV (1<<4)
294 #define I915_ERROR_PAGE_TABLE (1<<4)
295 #define GM45_ERROR_CP_PRIV (1<<3)
296 #define I915_ERROR_MEMORY_REFRESH (1<<1)
297 #define I915_ERROR_INSTRUCTION (1<<0)
298 #define INSTPM 0x020c0
299 #define ACTHD 0x020c8
300 #define FW_BLC 0x020d8
301 #define FW_BLC2 0x020dc
302 #define FW_BLC_SELF 0x020e0 /* 915+ only */
303 #define FW_BLC_SELF_EN (1<<15)
304 #define MM_BURST_LENGTH 0x00700000
305 #define MM_FIFO_WATERMARK 0x0001F000
306 #define LM_BURST_LENGTH 0x00000700
307 #define LM_FIFO_WATERMARK 0x0000001F
308 #define MI_ARB_STATE 0x020e4 /* 915+ only */
309 #define CACHE_MODE_0 0x02120 /* 915+ only */
310 #define CM0_MASK_SHIFT 16
311 #define CM0_IZ_OPT_DISABLE (1<<6)
312 #define CM0_ZR_OPT_DISABLE (1<<5)
313 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
314 #define CM0_COLOR_EVICT_DISABLE (1<<3)
315 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
316 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
317 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
321 * Framebuffer compression (915+ only)
324 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
325 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
326 #define FBC_CONTROL 0x03208
327 #define FBC_CTL_EN (1<<31)
328 #define FBC_CTL_PERIODIC (1<<30)
329 #define FBC_CTL_INTERVAL_SHIFT (16)
330 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
331 #define FBC_CTL_STRIDE_SHIFT (5)
332 #define FBC_CTL_FENCENO (1<<0)
333 #define FBC_COMMAND 0x0320c
334 #define FBC_CMD_COMPRESS (1<<0)
335 #define FBC_STATUS 0x03210
336 #define FBC_STAT_COMPRESSING (1<<31)
337 #define FBC_STAT_COMPRESSED (1<<30)
338 #define FBC_STAT_MODIFIED (1<<29)
339 #define FBC_STAT_CURRENT_LINE (1<<0)
340 #define FBC_CONTROL2 0x03214
341 #define FBC_CTL_FENCE_DBL (0<<4)
342 #define FBC_CTL_IDLE_IMM (0<<2)
343 #define FBC_CTL_IDLE_FULL (1<<2)
344 #define FBC_CTL_IDLE_LINE (2<<2)
345 #define FBC_CTL_IDLE_DEBUG (3<<2)
346 #define FBC_CTL_CPU_FENCE (1<<1)
347 #define FBC_CTL_PLANEA (0<<0)
348 #define FBC_CTL_PLANEB (1<<0)
349 #define FBC_FENCE_OFF 0x0321b
350 #define FBC_TAG 0x03300
352 #define FBC_LL_SIZE (1536)
365 # define GPIO_CLOCK_DIR_MASK (1 << 0)
366 # define GPIO_CLOCK_DIR_IN (0 << 1)
367 # define GPIO_CLOCK_DIR_OUT (1 << 1)
368 # define GPIO_CLOCK_VAL_MASK (1 << 2)
369 # define GPIO_CLOCK_VAL_OUT (1 << 3)
370 # define GPIO_CLOCK_VAL_IN (1 << 4)
371 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
372 # define GPIO_DATA_DIR_MASK (1 << 8)
373 # define GPIO_DATA_DIR_IN (0 << 9)
374 # define GPIO_DATA_DIR_OUT (1 << 9)
375 # define GPIO_DATA_VAL_MASK (1 << 10)
376 # define GPIO_DATA_VAL_OUT (1 << 11)
377 # define GPIO_DATA_VAL_IN (1 << 12)
378 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
381 * Clock control & power management
386 #define VGA_PD 0x6010
387 #define VGA0_PD_P2_DIV_4 (1 << 7)
388 #define VGA0_PD_P1_DIV_2 (1 << 5)
389 #define VGA0_PD_P1_SHIFT 0
390 #define VGA0_PD_P1_MASK (0x1f << 0)
391 #define VGA1_PD_P2_DIV_4 (1 << 15)
392 #define VGA1_PD_P1_DIV_2 (1 << 13)
393 #define VGA1_PD_P1_SHIFT 8
394 #define VGA1_PD_P1_MASK (0x1f << 8)
395 #define DPLL_A 0x06014
396 #define DPLL_B 0x06018
397 #define DPLL_VCO_ENABLE (1 << 31)
398 #define DPLL_DVO_HIGH_SPEED (1 << 30)
399 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
400 #define DPLL_VGA_MODE_DIS (1 << 28)
401 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
402 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
403 #define DPLL_MODE_MASK (3 << 26)
404 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
405 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
406 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
407 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
408 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
409 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
410 #define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
412 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
413 #define I915_CRC_ERROR_ENABLE (1UL<<29)
414 #define I915_CRC_DONE_ENABLE (1UL<<28)
415 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
416 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
417 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
418 #define I915_DPST_EVENT_ENABLE (1UL<<23)
419 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
420 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
421 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
422 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
423 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
424 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
425 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
426 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
427 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
428 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
429 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
430 #define I915_DPST_EVENT_STATUS (1UL<<7)
431 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
432 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
433 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
434 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
435 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
436 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
438 #define SRX_INDEX 0x3c4
439 #define SRX_DATA 0x3c5
441 #define SR01_SCREEN_OFF (1<<5)
444 #define PPCR_ON (1<<0)
447 #define DVOB_ON (1<<31)
449 #define DVOC_ON (1<<31)
451 #define LVDS_ON (1<<31)
454 #define ADPA_DPMS_MASK (~(3<<10))
455 #define ADPA_DPMS_ON (0<<10)
456 #define ADPA_DPMS_SUSPEND (1<<10)
457 #define ADPA_DPMS_STANDBY (2<<10)
458 #define ADPA_DPMS_OFF (3<<10)
460 #define RING_TAIL 0x00
461 #define TAIL_ADDR 0x001FFFF8
462 #define RING_HEAD 0x04
463 #define HEAD_WRAP_COUNT 0xFFE00000
464 #define HEAD_WRAP_ONE 0x00200000
465 #define HEAD_ADDR 0x001FFFFC
466 #define RING_START 0x08
467 #define START_ADDR 0xFFFFF000
468 #define RING_LEN 0x0C
469 #define RING_NR_PAGES 0x001FF000
470 #define RING_REPORT_MASK 0x00000006
471 #define RING_REPORT_64K 0x00000002
472 #define RING_REPORT_128K 0x00000004
473 #define RING_NO_REPORT 0x00000000
474 #define RING_VALID_MASK 0x00000001
475 #define RING_VALID 0x00000001
476 #define RING_INVALID 0x00000000
478 /* Scratch pad debug 0 reg:
480 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
482 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
483 * this field (only one bit may be set).
485 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
486 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
487 #define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
488 /* i830, required in DVO non-gang */
489 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
490 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
491 #define PLL_REF_INPUT_DREFCLK (0 << 13)
492 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
493 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
494 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
495 #define PLL_REF_INPUT_MASK (3 << 13)
496 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
498 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
499 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
500 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
501 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
502 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
505 * Parallel to Serial Load Pulse phase selection.
506 * Selects the phase for the 10X DPLL clock for the PCIe
507 * digital display port. The range is 4 to 13; 10 or more
508 * is just a flip delay. The default is 6
510 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
511 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
513 * SDVO multiplier for 945G/GM. Not used on 965.
515 #define SDVO_MULTIPLIER_MASK 0x000000ff
516 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
517 #define SDVO_MULTIPLIER_SHIFT_VGA 0
518 #define DPLL_A_MD 0x0601c /* 965+ only */
520 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
522 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
524 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
525 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
526 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
527 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
528 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
530 * SDVO/UDI pixel multiplier.
532 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
533 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
534 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
535 * dummy bytes in the datastream at an increased clock rate, with both sides of
536 * the link knowing how many bytes are fill.
538 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
539 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
540 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
541 * through an SDVO command.
543 * This register field has values of multiplication factor minus 1, with
544 * a maximum multiplier of 5 for SDVO.
546 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
547 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
549 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
550 * This best be set to the default value (3) or the CRT won't work. No,
551 * I don't entirely understand what this does...
553 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
554 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
555 #define DPLL_B_MD 0x06020 /* 965+ only */
560 #define FP_N_DIV_MASK 0x003f0000
561 #define FP_N_IGD_DIV_MASK 0x00ff0000
562 #define FP_N_DIV_SHIFT 16
563 #define FP_M1_DIV_MASK 0x00003f00
564 #define FP_M1_DIV_SHIFT 8
565 #define FP_M2_DIV_MASK 0x0000003f
566 #define FP_M2_IGD_DIV_MASK 0x000000ff
567 #define FP_M2_DIV_SHIFT 0
568 #define DPLL_TEST 0x606c
569 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
570 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
571 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
572 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
573 #define DPLLB_TEST_N_BYPASS (1 << 19)
574 #define DPLLB_TEST_M_BYPASS (1 << 18)
575 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
576 #define DPLLA_TEST_N_BYPASS (1 << 3)
577 #define DPLLA_TEST_M_BYPASS (1 << 2)
578 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
579 #define D_STATE 0x6104
580 #define DSTATE_PLL_D3_OFF (1<<3)
581 #define DSTATE_GFX_CLOCK_GATING (1<<1)
582 #define DSTATE_DOT_CLOCK_GATING (1<<0)
583 #define DSPCLK_GATE_D 0x6200
584 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
585 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
586 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
587 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
588 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
589 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
590 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
591 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
592 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
593 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
594 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
595 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
596 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
597 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
598 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
599 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
600 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
601 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
602 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
603 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
604 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
605 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
606 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
607 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
608 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
609 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
610 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
611 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
613 * This bit must be set on the 830 to prevent hangs when turning off the
616 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
617 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
618 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
619 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
620 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
622 #define RENCLK_GATE_D1 0x6204
623 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
624 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
625 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
626 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
627 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
628 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
629 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
630 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
631 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
632 /** This bit must be unset on 855,865 */
633 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
634 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
635 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
636 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
637 /** This bit must be set on 855,865. */
638 # define SV_CLOCK_GATE_DISABLE (1 << 0)
639 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
640 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
641 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
642 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
643 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
644 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
645 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
646 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
647 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
648 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
649 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
650 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
651 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
652 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
653 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
654 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
655 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
657 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
658 /** This bit must always be set on 965G/965GM */
659 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
660 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
661 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
662 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
663 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
664 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
665 /** This bit must always be set on 965G */
666 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
667 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
668 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
669 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
670 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
671 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
672 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
673 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
674 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
675 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
676 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
677 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
678 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
679 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
680 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
681 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
682 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
683 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
684 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
686 #define RENCLK_GATE_D2 0x6208
687 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
688 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
689 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
690 #define RAMCLK_GATE_D 0x6210 /* CRL only */
691 #define DEUC 0x6214 /* CRL only */
697 #define PALETTE_A 0x0a000
698 #define PALETTE_B 0x0a800
705 * This mirrors the MCHBAR MMIO space whose location is determined by
706 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
707 * every way. It is not accessible from the CP register read instructions.
710 #define MCHBAR_MIRROR_BASE 0x10000
712 /** 915-945 and GM965 MCH register controlling DRAM channel access */
714 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
715 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
716 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
717 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
718 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
719 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
721 /** 965 MCH register controlling DRAM channel configuration */
722 #define C0DRB3 0x10206
723 #define C1DRB3 0x10606
725 /* Clocking configuration register */
726 #define CLKCFG 0x10c00
727 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
728 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
729 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
730 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
731 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
732 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
733 /* Note, below two are guess */
734 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
735 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
736 #define CLKCFG_FSB_MASK (7 << 0)
737 #define CLKCFG_MEM_533 (1 << 4)
738 #define CLKCFG_MEM_667 (2 << 4)
739 #define CLKCFG_MEM_800 (3 << 4)
740 #define CLKCFG_MEM_MASK (7 << 4)
742 /** GM965 GM45 render standby register */
743 #define MCHBAR_RENDER_STANDBY 0x111B8
745 #define PEG_BAND_GAP_DATA 0x14d68
751 #define OVADD 0x30000
752 #define DOVSTA 0x30008
753 #define OC_BUF (0x3<<20)
754 #define OGAMC5 0x30010
755 #define OGAMC4 0x30014
756 #define OGAMC3 0x30018
757 #define OGAMC2 0x3001c
758 #define OGAMC1 0x30020
759 #define OGAMC0 0x30024
762 * Display engine regs
765 /* Pipe A timing regs */
766 #define HTOTAL_A 0x60000
767 #define HBLANK_A 0x60004
768 #define HSYNC_A 0x60008
769 #define VTOTAL_A 0x6000c
770 #define VBLANK_A 0x60010
771 #define VSYNC_A 0x60014
772 #define PIPEASRC 0x6001c
773 #define BCLRPAT_A 0x60020
775 /* Pipe B timing regs */
776 #define HTOTAL_B 0x61000
777 #define HBLANK_B 0x61004
778 #define HSYNC_B 0x61008
779 #define VTOTAL_B 0x6100c
780 #define VBLANK_B 0x61010
781 #define VSYNC_B 0x61014
782 #define PIPEBSRC 0x6101c
783 #define BCLRPAT_B 0x61020
785 /* VGA port control */
787 #define ADPA_DAC_ENABLE (1<<31)
788 #define ADPA_DAC_DISABLE 0
789 #define ADPA_PIPE_SELECT_MASK (1<<30)
790 #define ADPA_PIPE_A_SELECT 0
791 #define ADPA_PIPE_B_SELECT (1<<30)
792 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
793 #define ADPA_SETS_HVPOLARITY 0
794 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
795 #define ADPA_VSYNC_CNTL_ENABLE 0
796 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
797 #define ADPA_HSYNC_CNTL_ENABLE 0
798 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
799 #define ADPA_VSYNC_ACTIVE_LOW 0
800 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
801 #define ADPA_HSYNC_ACTIVE_LOW 0
802 #define ADPA_DPMS_MASK (~(3<<10))
803 #define ADPA_DPMS_ON (0<<10)
804 #define ADPA_DPMS_SUSPEND (1<<10)
805 #define ADPA_DPMS_STANDBY (2<<10)
806 #define ADPA_DPMS_OFF (3<<10)
808 /* Hotplug control (945+ only) */
809 #define PORT_HOTPLUG_EN 0x61110
810 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
811 #define DPB_HOTPLUG_INT_EN (1 << 29)
812 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
813 #define DPC_HOTPLUG_INT_EN (1 << 28)
814 #define HDMID_HOTPLUG_INT_EN (1 << 27)
815 #define DPD_HOTPLUG_INT_EN (1 << 27)
816 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
817 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
818 #define TV_HOTPLUG_INT_EN (1 << 18)
819 #define CRT_EOS_INT_EN (1 << 10)
820 #define CRT_HOTPLUG_INT_EN (1 << 9)
821 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
822 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
823 /* must use period 64 on GM45 according to docs */
824 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
825 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
826 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
827 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
828 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
829 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
830 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
831 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
832 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
833 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
834 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
835 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
836 #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
837 #define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f
838 #define HOTPLUG_EN_MASK (HDMIB_HOTPLUG_INT_EN | \
839 HDMIC_HOTPLUG_INT_EN | \
840 HDMID_HOTPLUG_INT_EN | \
841 SDVOB_HOTPLUG_INT_EN | \
842 SDVOC_HOTPLUG_INT_EN | \
843 TV_HOTPLUG_INT_EN | \
847 #define PORT_HOTPLUG_STAT 0x61114
848 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
849 #define DPB_HOTPLUG_INT_STATUS (1 << 29)
850 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
851 #define DPC_HOTPLUG_INT_STATUS (1 << 28)
852 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
853 #define DPD_HOTPLUG_INT_STATUS (1 << 27)
854 #define CRT_EOS_INT_STATUS (1 << 12)
855 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
856 #define TV_HOTPLUG_INT_STATUS (1 << 10)
857 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
858 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
859 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
860 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
861 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
862 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
864 /* SDVO port control */
865 #define SDVOB 0x61140
866 #define SDVOC 0x61160
867 #define SDVO_ENABLE (1 << 31)
868 #define SDVO_PIPE_B_SELECT (1 << 30)
869 #define SDVO_STALL_SELECT (1 << 29)
870 #define SDVO_INTERRUPT_ENABLE (1 << 26)
872 * 915G/GM SDVO pixel multiplier.
874 * Programmed value is multiplier - 1, up to 5x.
876 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
878 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
879 #define SDVO_PORT_MULTIPLY_SHIFT 23
880 #define SDVO_PHASE_SELECT_MASK (15 << 19)
881 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
882 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
883 #define SDVOC_GANG_MODE (1 << 16)
884 #define SDVO_ENCODING_SDVO (0x0 << 10)
885 #define SDVO_ENCODING_HDMI (0x2 << 10)
886 /** Requird for HDMI operation */
887 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
888 #define SDVO_BORDER_ENABLE (1 << 7)
889 #define SDVO_AUDIO_ENABLE (1 << 6)
890 /** New with 965, default is to be set */
891 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
892 /** New with 965, default is to be set */
893 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
894 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
895 #define SDVO_DETECTED (1 << 2)
896 /* Bits to be preserved when writing */
897 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
898 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
900 /* DVO port control */
904 #define DVO_ENABLE (1 << 31)
905 #define DVO_PIPE_B_SELECT (1 << 30)
906 #define DVO_PIPE_STALL_UNUSED (0 << 28)
907 #define DVO_PIPE_STALL (1 << 28)
908 #define DVO_PIPE_STALL_TV (2 << 28)
909 #define DVO_PIPE_STALL_MASK (3 << 28)
910 #define DVO_USE_VGA_SYNC (1 << 15)
911 #define DVO_DATA_ORDER_I740 (0 << 14)
912 #define DVO_DATA_ORDER_FP (1 << 14)
913 #define DVO_VSYNC_DISABLE (1 << 11)
914 #define DVO_HSYNC_DISABLE (1 << 10)
915 #define DVO_VSYNC_TRISTATE (1 << 9)
916 #define DVO_HSYNC_TRISTATE (1 << 8)
917 #define DVO_BORDER_ENABLE (1 << 7)
918 #define DVO_DATA_ORDER_GBRG (1 << 6)
919 #define DVO_DATA_ORDER_RGGB (0 << 6)
920 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
921 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
922 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
923 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
924 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
925 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
926 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
927 #define DVO_PRESERVE_MASK (0x7<<24)
928 #define DVOA_SRCDIM 0x61124
929 #define DVOB_SRCDIM 0x61144
930 #define DVOC_SRCDIM 0x61164
931 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
932 #define DVO_SRCDIM_VERTICAL_SHIFT 0
934 /* LVDS port control */
937 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
938 * the DPLL semantics change when the LVDS is assigned to that pipe.
940 #define LVDS_PORT_EN (1 << 31)
941 /* Selects pipe B for LVDS data. Must be set on pre-965. */
942 #define LVDS_PIPEB_SELECT (1 << 30)
944 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
947 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
948 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
949 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
951 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
952 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
955 #define LVDS_A3_POWER_MASK (3 << 6)
956 #define LVDS_A3_POWER_DOWN (0 << 6)
957 #define LVDS_A3_POWER_UP (3 << 6)
959 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
962 #define LVDS_CLKB_POWER_MASK (3 << 4)
963 #define LVDS_CLKB_POWER_DOWN (0 << 4)
964 #define LVDS_CLKB_POWER_UP (3 << 4)
966 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
967 * setting for whether we are in dual-channel mode. The B3 pair will
968 * additionally only be powered up when LVDS_A3_POWER_UP is set.
970 #define LVDS_B0B3_POWER_MASK (3 << 2)
971 #define LVDS_B0B3_POWER_DOWN (0 << 2)
972 #define LVDS_B0B3_POWER_UP (3 << 2)
974 /* Panel power sequencing */
975 #define PP_STATUS 0x61200
976 #define PP_ON (1 << 31)
978 * Indicates that all dependencies of the panel are on:
982 * - LVDS/DVOB/DVOC on
984 #define PP_READY (1 << 30)
985 #define PP_SEQUENCE_NONE (0 << 28)
986 #define PP_SEQUENCE_ON (1 << 28)
987 #define PP_SEQUENCE_OFF (2 << 28)
988 #define PP_SEQUENCE_MASK 0x30000000
989 #define PP_CONTROL 0x61204
990 #define POWER_TARGET_ON (1 << 0)
991 #define PP_ON_DELAYS 0x61208
992 #define PP_OFF_DELAYS 0x6120c
993 #define PP_DIVISOR 0x61210
996 #define PFIT_CONTROL 0x61230
997 #define PFIT_ENABLE (1 << 31)
998 #define PFIT_PIPE_MASK (3 << 29)
999 #define PFIT_PIPE_SHIFT 29
1000 #define VERT_INTERP_DISABLE (0 << 10)
1001 #define VERT_INTERP_BILINEAR (1 << 10)
1002 #define VERT_INTERP_MASK (3 << 10)
1003 #define VERT_AUTO_SCALE (1 << 9)
1004 #define HORIZ_INTERP_DISABLE (0 << 6)
1005 #define HORIZ_INTERP_BILINEAR (1 << 6)
1006 #define HORIZ_INTERP_MASK (3 << 6)
1007 #define HORIZ_AUTO_SCALE (1 << 5)
1008 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1009 #define PFIT_FILTER_FUZZY (0 << 24)
1010 #define PFIT_SCALING_AUTO (0 << 26)
1011 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1012 #define PFIT_SCALING_PILLAR (2 << 26)
1013 #define PFIT_SCALING_LETTER (3 << 26)
1014 #define PFIT_PGM_RATIOS 0x61234
1015 #define PFIT_VERT_SCALE_MASK 0xfff00000
1016 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1018 #define PFIT_VERT_SCALE_SHIFT 20
1019 #define PFIT_VERT_SCALE_MASK 0xfff00000
1020 #define PFIT_HORIZ_SCALE_SHIFT 4
1021 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1023 #define PFIT_VERT_SCALE_SHIFT_965 16
1024 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1025 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1026 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1028 #define PFIT_AUTO_RATIOS 0x61238
1030 /* Backlight control */
1031 #define BLC_PWM_CTL 0x61254
1032 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1033 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1034 #define BLM_COMBINATION_MODE (1 << 30)
1036 * This is the most significant 15 bits of the number of backlight cycles in a
1037 * complete cycle of the modulated backlight control.
1039 * The actual value is this field multiplied by two.
1041 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1042 #define BLM_LEGACY_MODE (1 << 16)
1044 * This is the number of cycles out of the backlight modulation cycle for which
1045 * the backlight is on.
1047 * This field must be no greater than the number of cycles in the complete
1048 * backlight modulation cycle.
1050 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1051 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1053 /* TV port control */
1054 #define TV_CTL 0x68000
1055 /** Enables the TV encoder */
1056 # define TV_ENC_ENABLE (1 << 31)
1057 /** Sources the TV encoder input from pipe B instead of A. */
1058 # define TV_ENC_PIPEB_SELECT (1 << 30)
1059 /** Outputs composite video (DAC A only) */
1060 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1061 /** Outputs SVideo video (DAC B/C) */
1062 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1063 /** Outputs Component video (DAC A/B/C) */
1064 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1065 /** Outputs Composite and SVideo (DAC A/B/C) */
1066 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1067 # define TV_TRILEVEL_SYNC (1 << 21)
1068 /** Enables slow sync generation (945GM only) */
1069 # define TV_SLOW_SYNC (1 << 20)
1070 /** Selects 4x oversampling for 480i and 576p */
1071 # define TV_OVERSAMPLE_4X (0 << 18)
1072 /** Selects 2x oversampling for 720p and 1080i */
1073 # define TV_OVERSAMPLE_2X (1 << 18)
1074 /** Selects no oversampling for 1080p */
1075 # define TV_OVERSAMPLE_NONE (2 << 18)
1076 /** Selects 8x oversampling */
1077 # define TV_OVERSAMPLE_8X (3 << 18)
1078 /** Selects progressive mode rather than interlaced */
1079 # define TV_PROGRESSIVE (1 << 17)
1080 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1081 # define TV_PAL_BURST (1 << 16)
1082 /** Field for setting delay of Y compared to C */
1083 # define TV_YC_SKEW_MASK (7 << 12)
1084 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1085 # define TV_ENC_SDP_FIX (1 << 11)
1087 * Enables a fix for the 915GM only.
1089 * Not sure what it does.
1091 # define TV_ENC_C0_FIX (1 << 10)
1092 /** Bits that must be preserved by software */
1093 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1094 # define TV_FUSE_STATE_MASK (3 << 4)
1095 /** Read-only state that reports all features enabled */
1096 # define TV_FUSE_STATE_ENABLED (0 << 4)
1097 /** Read-only state that reports that Macrovision is disabled in hardware*/
1098 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1099 /** Read-only state that reports that TV-out is disabled in hardware. */
1100 # define TV_FUSE_STATE_DISABLED (2 << 4)
1101 /** Normal operation */
1102 # define TV_TEST_MODE_NORMAL (0 << 0)
1103 /** Encoder test pattern 1 - combo pattern */
1104 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
1105 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1106 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
1107 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1108 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
1109 /** Encoder test pattern 4 - random noise */
1110 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
1111 /** Encoder test pattern 5 - linear color ramps */
1112 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
1114 * This test mode forces the DACs to 50% of full output.
1116 * This is used for load detection in combination with TVDAC_SENSE_MASK
1118 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1119 # define TV_TEST_MODE_MASK (7 << 0)
1121 #define TV_DAC 0x68004
1123 * Reports that DAC state change logic has reported change (RO).
1125 * This gets cleared when TV_DAC_STATE_EN is cleared
1127 # define TVDAC_STATE_CHG (1 << 31)
1128 # define TVDAC_SENSE_MASK (7 << 28)
1129 /** Reports that DAC A voltage is above the detect threshold */
1130 # define TVDAC_A_SENSE (1 << 30)
1131 /** Reports that DAC B voltage is above the detect threshold */
1132 # define TVDAC_B_SENSE (1 << 29)
1133 /** Reports that DAC C voltage is above the detect threshold */
1134 # define TVDAC_C_SENSE (1 << 28)
1136 * Enables DAC state detection logic, for load-based TV detection.
1138 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1139 * to off, for load detection to work.
1141 # define TVDAC_STATE_CHG_EN (1 << 27)
1142 /** Sets the DAC A sense value to high */
1143 # define TVDAC_A_SENSE_CTL (1 << 26)
1144 /** Sets the DAC B sense value to high */
1145 # define TVDAC_B_SENSE_CTL (1 << 25)
1146 /** Sets the DAC C sense value to high */
1147 # define TVDAC_C_SENSE_CTL (1 << 24)
1148 /** Overrides the ENC_ENABLE and DAC voltage levels */
1149 # define DAC_CTL_OVERRIDE (1 << 7)
1150 /** Sets the slew rate. Must be preserved in software */
1151 # define ENC_TVDAC_SLEW_FAST (1 << 6)
1152 # define DAC_A_1_3_V (0 << 4)
1153 # define DAC_A_1_1_V (1 << 4)
1154 # define DAC_A_0_7_V (2 << 4)
1155 # define DAC_A_MASK (3 << 4)
1156 # define DAC_B_1_3_V (0 << 2)
1157 # define DAC_B_1_1_V (1 << 2)
1158 # define DAC_B_0_7_V (2 << 2)
1159 # define DAC_B_MASK (3 << 2)
1160 # define DAC_C_1_3_V (0 << 0)
1161 # define DAC_C_1_1_V (1 << 0)
1162 # define DAC_C_0_7_V (2 << 0)
1163 # define DAC_C_MASK (3 << 0)
1166 * CSC coefficients are stored in a floating point format with 9 bits of
1167 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1168 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1169 * -1 (0x3) being the only legal negative value.
1171 #define TV_CSC_Y 0x68010
1172 # define TV_RY_MASK 0x07ff0000
1173 # define TV_RY_SHIFT 16
1174 # define TV_GY_MASK 0x00000fff
1175 # define TV_GY_SHIFT 0
1177 #define TV_CSC_Y2 0x68014
1178 # define TV_BY_MASK 0x07ff0000
1179 # define TV_BY_SHIFT 16
1181 * Y attenuation for component video.
1183 * Stored in 1.9 fixed point.
1185 # define TV_AY_MASK 0x000003ff
1186 # define TV_AY_SHIFT 0
1188 #define TV_CSC_U 0x68018
1189 # define TV_RU_MASK 0x07ff0000
1190 # define TV_RU_SHIFT 16
1191 # define TV_GU_MASK 0x000007ff
1192 # define TV_GU_SHIFT 0
1194 #define TV_CSC_U2 0x6801c
1195 # define TV_BU_MASK 0x07ff0000
1196 # define TV_BU_SHIFT 16
1198 * U attenuation for component video.
1200 * Stored in 1.9 fixed point.
1202 # define TV_AU_MASK 0x000003ff
1203 # define TV_AU_SHIFT 0
1205 #define TV_CSC_V 0x68020
1206 # define TV_RV_MASK 0x0fff0000
1207 # define TV_RV_SHIFT 16
1208 # define TV_GV_MASK 0x000007ff
1209 # define TV_GV_SHIFT 0
1211 #define TV_CSC_V2 0x68024
1212 # define TV_BV_MASK 0x07ff0000
1213 # define TV_BV_SHIFT 16
1215 * V attenuation for component video.
1217 * Stored in 1.9 fixed point.
1219 # define TV_AV_MASK 0x000007ff
1220 # define TV_AV_SHIFT 0
1222 #define TV_CLR_KNOBS 0x68028
1223 /** 2s-complement brightness adjustment */
1224 # define TV_BRIGHTNESS_MASK 0xff000000
1225 # define TV_BRIGHTNESS_SHIFT 24
1226 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1227 # define TV_CONTRAST_MASK 0x00ff0000
1228 # define TV_CONTRAST_SHIFT 16
1229 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1230 # define TV_SATURATION_MASK 0x0000ff00
1231 # define TV_SATURATION_SHIFT 8
1232 /** Hue adjustment, as an integer phase angle in degrees */
1233 # define TV_HUE_MASK 0x000000ff
1234 # define TV_HUE_SHIFT 0
1236 #define TV_CLR_LEVEL 0x6802c
1237 /** Controls the DAC level for black */
1238 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1239 # define TV_BLACK_LEVEL_SHIFT 16
1240 /** Controls the DAC level for blanking */
1241 # define TV_BLANK_LEVEL_MASK 0x000001ff
1242 # define TV_BLANK_LEVEL_SHIFT 0
1244 #define TV_H_CTL_1 0x68030
1245 /** Number of pixels in the hsync. */
1246 # define TV_HSYNC_END_MASK 0x1fff0000
1247 # define TV_HSYNC_END_SHIFT 16
1248 /** Total number of pixels minus one in the line (display and blanking). */
1249 # define TV_HTOTAL_MASK 0x00001fff
1250 # define TV_HTOTAL_SHIFT 0
1252 #define TV_H_CTL_2 0x68034
1253 /** Enables the colorburst (needed for non-component color) */
1254 # define TV_BURST_ENA (1 << 31)
1255 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1256 # define TV_HBURST_START_SHIFT 16
1257 # define TV_HBURST_START_MASK 0x1fff0000
1258 /** Length of the colorburst */
1259 # define TV_HBURST_LEN_SHIFT 0
1260 # define TV_HBURST_LEN_MASK 0x0001fff
1262 #define TV_H_CTL_3 0x68038
1263 /** End of hblank, measured in pixels minus one from start of hsync */
1264 # define TV_HBLANK_END_SHIFT 16
1265 # define TV_HBLANK_END_MASK 0x1fff0000
1266 /** Start of hblank, measured in pixels minus one from start of hsync */
1267 # define TV_HBLANK_START_SHIFT 0
1268 # define TV_HBLANK_START_MASK 0x0001fff
1270 #define TV_V_CTL_1 0x6803c
1272 # define TV_NBR_END_SHIFT 16
1273 # define TV_NBR_END_MASK 0x07ff0000
1275 # define TV_VI_END_F1_SHIFT 8
1276 # define TV_VI_END_F1_MASK 0x00003f00
1278 # define TV_VI_END_F2_SHIFT 0
1279 # define TV_VI_END_F2_MASK 0x0000003f
1281 #define TV_V_CTL_2 0x68040
1282 /** Length of vsync, in half lines */
1283 # define TV_VSYNC_LEN_MASK 0x07ff0000
1284 # define TV_VSYNC_LEN_SHIFT 16
1285 /** Offset of the start of vsync in field 1, measured in one less than the
1286 * number of half lines.
1288 # define TV_VSYNC_START_F1_MASK 0x00007f00
1289 # define TV_VSYNC_START_F1_SHIFT 8
1291 * Offset of the start of vsync in field 2, measured in one less than the
1292 * number of half lines.
1294 # define TV_VSYNC_START_F2_MASK 0x0000007f
1295 # define TV_VSYNC_START_F2_SHIFT 0
1297 #define TV_V_CTL_3 0x68044
1298 /** Enables generation of the equalization signal */
1299 # define TV_EQUAL_ENA (1 << 31)
1300 /** Length of vsync, in half lines */
1301 # define TV_VEQ_LEN_MASK 0x007f0000
1302 # define TV_VEQ_LEN_SHIFT 16
1303 /** Offset of the start of equalization in field 1, measured in one less than
1304 * the number of half lines.
1306 # define TV_VEQ_START_F1_MASK 0x0007f00
1307 # define TV_VEQ_START_F1_SHIFT 8
1309 * Offset of the start of equalization in field 2, measured in one less than
1310 * the number of half lines.
1312 # define TV_VEQ_START_F2_MASK 0x000007f
1313 # define TV_VEQ_START_F2_SHIFT 0
1315 #define TV_V_CTL_4 0x68048
1317 * Offset to start of vertical colorburst, measured in one less than the
1318 * number of lines from vertical start.
1320 # define TV_VBURST_START_F1_MASK 0x003f0000
1321 # define TV_VBURST_START_F1_SHIFT 16
1323 * Offset to the end of vertical colorburst, measured in one less than the
1324 * number of lines from the start of NBR.
1326 # define TV_VBURST_END_F1_MASK 0x000000ff
1327 # define TV_VBURST_END_F1_SHIFT 0
1329 #define TV_V_CTL_5 0x6804c
1331 * Offset to start of vertical colorburst, measured in one less than the
1332 * number of lines from vertical start.
1334 # define TV_VBURST_START_F2_MASK 0x003f0000
1335 # define TV_VBURST_START_F2_SHIFT 16
1337 * Offset to the end of vertical colorburst, measured in one less than the
1338 * number of lines from the start of NBR.
1340 # define TV_VBURST_END_F2_MASK 0x000000ff
1341 # define TV_VBURST_END_F2_SHIFT 0
1343 #define TV_V_CTL_6 0x68050
1345 * Offset to start of vertical colorburst, measured in one less than the
1346 * number of lines from vertical start.
1348 # define TV_VBURST_START_F3_MASK 0x003f0000
1349 # define TV_VBURST_START_F3_SHIFT 16
1351 * Offset to the end of vertical colorburst, measured in one less than the
1352 * number of lines from the start of NBR.
1354 # define TV_VBURST_END_F3_MASK 0x000000ff
1355 # define TV_VBURST_END_F3_SHIFT 0
1357 #define TV_V_CTL_7 0x68054
1359 * Offset to start of vertical colorburst, measured in one less than the
1360 * number of lines from vertical start.
1362 # define TV_VBURST_START_F4_MASK 0x003f0000
1363 # define TV_VBURST_START_F4_SHIFT 16
1365 * Offset to the end of vertical colorburst, measured in one less than the
1366 * number of lines from the start of NBR.
1368 # define TV_VBURST_END_F4_MASK 0x000000ff
1369 # define TV_VBURST_END_F4_SHIFT 0
1371 #define TV_SC_CTL_1 0x68060
1372 /** Turns on the first subcarrier phase generation DDA */
1373 # define TV_SC_DDA1_EN (1 << 31)
1374 /** Turns on the first subcarrier phase generation DDA */
1375 # define TV_SC_DDA2_EN (1 << 30)
1376 /** Turns on the first subcarrier phase generation DDA */
1377 # define TV_SC_DDA3_EN (1 << 29)
1378 /** Sets the subcarrier DDA to reset frequency every other field */
1379 # define TV_SC_RESET_EVERY_2 (0 << 24)
1380 /** Sets the subcarrier DDA to reset frequency every fourth field */
1381 # define TV_SC_RESET_EVERY_4 (1 << 24)
1382 /** Sets the subcarrier DDA to reset frequency every eighth field */
1383 # define TV_SC_RESET_EVERY_8 (2 << 24)
1384 /** Sets the subcarrier DDA to never reset the frequency */
1385 # define TV_SC_RESET_NEVER (3 << 24)
1386 /** Sets the peak amplitude of the colorburst.*/
1387 # define TV_BURST_LEVEL_MASK 0x00ff0000
1388 # define TV_BURST_LEVEL_SHIFT 16
1389 /** Sets the increment of the first subcarrier phase generation DDA */
1390 # define TV_SCDDA1_INC_MASK 0x00000fff
1391 # define TV_SCDDA1_INC_SHIFT 0
1393 #define TV_SC_CTL_2 0x68064
1394 /** Sets the rollover for the second subcarrier phase generation DDA */
1395 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1396 # define TV_SCDDA2_SIZE_SHIFT 16
1397 /** Sets the increent of the second subcarrier phase generation DDA */
1398 # define TV_SCDDA2_INC_MASK 0x00007fff
1399 # define TV_SCDDA2_INC_SHIFT 0
1401 #define TV_SC_CTL_3 0x68068
1402 /** Sets the rollover for the third subcarrier phase generation DDA */
1403 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1404 # define TV_SCDDA3_SIZE_SHIFT 16
1405 /** Sets the increent of the third subcarrier phase generation DDA */
1406 # define TV_SCDDA3_INC_MASK 0x00007fff
1407 # define TV_SCDDA3_INC_SHIFT 0
1409 #define TV_WIN_POS 0x68070
1410 /** X coordinate of the display from the start of horizontal active */
1411 # define TV_XPOS_MASK 0x1fff0000
1412 # define TV_XPOS_SHIFT 16
1413 /** Y coordinate of the display from the start of vertical active (NBR) */
1414 # define TV_YPOS_MASK 0x00000fff
1415 # define TV_YPOS_SHIFT 0
1417 #define TV_WIN_SIZE 0x68074
1418 /** Horizontal size of the display window, measured in pixels*/
1419 # define TV_XSIZE_MASK 0x1fff0000
1420 # define TV_XSIZE_SHIFT 16
1422 * Vertical size of the display window, measured in pixels.
1424 * Must be even for interlaced modes.
1426 # define TV_YSIZE_MASK 0x00000fff
1427 # define TV_YSIZE_SHIFT 0
1429 #define TV_FILTER_CTL_1 0x68080
1431 * Enables automatic scaling calculation.
1433 * If set, the rest of the registers are ignored, and the calculated values can
1434 * be read back from the register.
1436 # define TV_AUTO_SCALE (1 << 31)
1438 * Disables the vertical filter.
1440 * This is required on modes more than 1024 pixels wide */
1441 # define TV_V_FILTER_BYPASS (1 << 29)
1442 /** Enables adaptive vertical filtering */
1443 # define TV_VADAPT (1 << 28)
1444 # define TV_VADAPT_MODE_MASK (3 << 26)
1445 /** Selects the least adaptive vertical filtering mode */
1446 # define TV_VADAPT_MODE_LEAST (0 << 26)
1447 /** Selects the moderately adaptive vertical filtering mode */
1448 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1449 /** Selects the most adaptive vertical filtering mode */
1450 # define TV_VADAPT_MODE_MOST (3 << 26)
1452 * Sets the horizontal scaling factor.
1454 * This should be the fractional part of the horizontal scaling factor divided
1455 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1457 * (src width - 1) / ((oversample * dest width) - 1)
1459 # define TV_HSCALE_FRAC_MASK 0x00003fff
1460 # define TV_HSCALE_FRAC_SHIFT 0
1462 #define TV_FILTER_CTL_2 0x68084
1464 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1466 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1468 # define TV_VSCALE_INT_MASK 0x00038000
1469 # define TV_VSCALE_INT_SHIFT 15
1471 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1473 * \sa TV_VSCALE_INT_MASK
1475 # define TV_VSCALE_FRAC_MASK 0x00007fff
1476 # define TV_VSCALE_FRAC_SHIFT 0
1478 #define TV_FILTER_CTL_3 0x68088
1480 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1482 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1484 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1486 # define TV_VSCALE_IP_INT_MASK 0x00038000
1487 # define TV_VSCALE_IP_INT_SHIFT 15
1489 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1491 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1493 * \sa TV_VSCALE_IP_INT_MASK
1495 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1496 # define TV_VSCALE_IP_FRAC_SHIFT 0
1498 #define TV_CC_CONTROL 0x68090
1499 # define TV_CC_ENABLE (1 << 31)
1501 * Specifies which field to send the CC data in.
1503 * CC data is usually sent in field 0.
1505 # define TV_CC_FID_MASK (1 << 27)
1506 # define TV_CC_FID_SHIFT 27
1507 /** Sets the horizontal position of the CC data. Usually 135. */
1508 # define TV_CC_HOFF_MASK 0x03ff0000
1509 # define TV_CC_HOFF_SHIFT 16
1510 /** Sets the vertical position of the CC data. Usually 21 */
1511 # define TV_CC_LINE_MASK 0x0000003f
1512 # define TV_CC_LINE_SHIFT 0
1514 #define TV_CC_DATA 0x68094
1515 # define TV_CC_RDY (1 << 31)
1516 /** Second word of CC data to be transmitted. */
1517 # define TV_CC_DATA_2_MASK 0x007f0000
1518 # define TV_CC_DATA_2_SHIFT 16
1519 /** First word of CC data to be transmitted. */
1520 # define TV_CC_DATA_1_MASK 0x0000007f
1521 # define TV_CC_DATA_1_SHIFT 0
1523 #define TV_H_LUMA_0 0x68100
1524 #define TV_H_LUMA_59 0x681ec
1525 #define TV_H_CHROMA_0 0x68200
1526 #define TV_H_CHROMA_59 0x682ec
1527 #define TV_V_LUMA_0 0x68300
1528 #define TV_V_LUMA_42 0x683a8
1529 #define TV_V_CHROMA_0 0x68400
1530 #define TV_V_CHROMA_42 0x684a8
1533 #define DP_A 0x64000 /* eDP */
1534 #define DP_B 0x64100
1535 #define DP_C 0x64200
1536 #define DP_D 0x64300
1538 #define DP_PORT_EN (1 << 31)
1539 #define DP_PIPEB_SELECT (1 << 30)
1541 /* Link training mode - select a suitable mode for each stage */
1542 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
1543 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
1544 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1545 #define DP_LINK_TRAIN_OFF (3 << 28)
1546 #define DP_LINK_TRAIN_MASK (3 << 28)
1547 #define DP_LINK_TRAIN_SHIFT 28
1549 /* Signal voltages. These are mostly controlled by the other end */
1550 #define DP_VOLTAGE_0_4 (0 << 25)
1551 #define DP_VOLTAGE_0_6 (1 << 25)
1552 #define DP_VOLTAGE_0_8 (2 << 25)
1553 #define DP_VOLTAGE_1_2 (3 << 25)
1554 #define DP_VOLTAGE_MASK (7 << 25)
1555 #define DP_VOLTAGE_SHIFT 25
1557 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1560 #define DP_PRE_EMPHASIS_0 (0 << 22)
1561 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
1562 #define DP_PRE_EMPHASIS_6 (2 << 22)
1563 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
1564 #define DP_PRE_EMPHASIS_MASK (7 << 22)
1565 #define DP_PRE_EMPHASIS_SHIFT 22
1567 /* How many wires to use. I guess 3 was too hard */
1568 #define DP_PORT_WIDTH_1 (0 << 19)
1569 #define DP_PORT_WIDTH_2 (1 << 19)
1570 #define DP_PORT_WIDTH_4 (3 << 19)
1571 #define DP_PORT_WIDTH_MASK (7 << 19)
1573 /* Mystic DPCD version 1.1 special mode */
1574 #define DP_ENHANCED_FRAMING (1 << 18)
1577 #define DP_PLL_FREQ_270MHZ (0 << 16)
1578 #define DP_PLL_FREQ_160MHZ (1 << 16)
1579 #define DP_PLL_FREQ_MASK (3 << 16)
1581 /** locked once port is enabled */
1582 #define DP_PORT_REVERSAL (1 << 15)
1585 #define DP_PLL_ENABLE (1 << 14)
1587 /** sends the clock on lane 15 of the PEG for debug */
1588 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1590 #define DP_SCRAMBLING_DISABLE (1 << 12)
1591 #define DP_SCRAMBLING_DISABLE_IGDNG (1 << 7)
1593 /** limit RGB values to avoid confusing TVs */
1594 #define DP_COLOR_RANGE_16_235 (1 << 8)
1596 /** Turn on the audio link */
1597 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1599 /** vs and hs sync polarity */
1600 #define DP_SYNC_VS_HIGH (1 << 4)
1601 #define DP_SYNC_HS_HIGH (1 << 3)
1604 #define DP_DETECTED (1 << 2)
1606 /** The aux channel provides a way to talk to the
1607 * signal sink for DDC etc. Max packet size supported
1608 * is 20 bytes in each direction, hence the 5 fixed
1611 #define DPA_AUX_CH_CTL 0x64010
1612 #define DPA_AUX_CH_DATA1 0x64014
1613 #define DPA_AUX_CH_DATA2 0x64018
1614 #define DPA_AUX_CH_DATA3 0x6401c
1615 #define DPA_AUX_CH_DATA4 0x64020
1616 #define DPA_AUX_CH_DATA5 0x64024
1618 #define DPB_AUX_CH_CTL 0x64110
1619 #define DPB_AUX_CH_DATA1 0x64114
1620 #define DPB_AUX_CH_DATA2 0x64118
1621 #define DPB_AUX_CH_DATA3 0x6411c
1622 #define DPB_AUX_CH_DATA4 0x64120
1623 #define DPB_AUX_CH_DATA5 0x64124
1625 #define DPC_AUX_CH_CTL 0x64210
1626 #define DPC_AUX_CH_DATA1 0x64214
1627 #define DPC_AUX_CH_DATA2 0x64218
1628 #define DPC_AUX_CH_DATA3 0x6421c
1629 #define DPC_AUX_CH_DATA4 0x64220
1630 #define DPC_AUX_CH_DATA5 0x64224
1632 #define DPD_AUX_CH_CTL 0x64310
1633 #define DPD_AUX_CH_DATA1 0x64314
1634 #define DPD_AUX_CH_DATA2 0x64318
1635 #define DPD_AUX_CH_DATA3 0x6431c
1636 #define DPD_AUX_CH_DATA4 0x64320
1637 #define DPD_AUX_CH_DATA5 0x64324
1639 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
1640 #define DP_AUX_CH_CTL_DONE (1 << 30)
1641 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
1642 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
1643 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
1644 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
1645 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
1646 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
1647 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
1648 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
1649 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
1650 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
1651 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
1652 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
1653 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
1654 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
1655 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
1656 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
1657 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
1658 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1659 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
1662 * Computing GMCH M and N values for the Display Port link
1664 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1666 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1668 * The GMCH value is used internally
1670 * bytes_per_pixel is the number of bytes coming out of the plane,
1671 * which is after the LUTs, so we want the bytes for our color format.
1672 * For our current usage, this is always 3, one byte for R, G and B.
1674 #define PIPEA_GMCH_DATA_M 0x70050
1675 #define PIPEB_GMCH_DATA_M 0x71050
1677 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1678 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
1679 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
1681 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
1683 #define PIPEA_GMCH_DATA_N 0x70054
1684 #define PIPEB_GMCH_DATA_N 0x71054
1685 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
1688 * Computing Link M and N values for the Display Port link
1690 * Link M / N = pixel_clock / ls_clk
1692 * (the DP spec calls pixel_clock the 'strm_clk')
1694 * The Link value is transmitted in the Main Stream
1695 * Attributes and VB-ID.
1698 #define PIPEA_DP_LINK_M 0x70060
1699 #define PIPEB_DP_LINK_M 0x71060
1700 #define PIPEA_DP_LINK_M_MASK (0xffffff)
1702 #define PIPEA_DP_LINK_N 0x70064
1703 #define PIPEB_DP_LINK_N 0x71064
1704 #define PIPEA_DP_LINK_N_MASK (0xffffff)
1706 /* Display & cursor control */
1709 #define PIPEADSL 0x70000
1710 #define PIPEACONF 0x70008
1711 #define PIPEACONF_ENABLE (1<<31)
1712 #define PIPEACONF_DISABLE 0
1713 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1714 #define I965_PIPECONF_ACTIVE (1<<30)
1715 #define PIPEACONF_SINGLE_WIDE 0
1716 #define PIPEACONF_PIPE_UNLOCKED 0
1717 #define PIPEACONF_PIPE_LOCKED (1<<25)
1718 #define PIPEACONF_PALETTE 0
1719 #define PIPEACONF_GAMMA (1<<24)
1720 #define PIPECONF_FORCE_BORDER (1<<25)
1721 #define PIPECONF_PROGRESSIVE (0 << 21)
1722 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1723 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1724 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
1725 #define PIPEASTAT 0x70024
1726 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1727 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1728 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
1729 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1730 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1731 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1732 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1733 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1734 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1735 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1736 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1737 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1738 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1739 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1740 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1741 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1742 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1743 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1744 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1745 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1746 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1747 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
1748 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1749 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1750 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1751 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1752 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1753 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1754 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1756 #define DSPARB 0x70030
1757 #define DSPARB_CSTART_MASK (0x7f << 7)
1758 #define DSPARB_CSTART_SHIFT 7
1759 #define DSPARB_BSTART_MASK (0x7f)
1760 #define DSPARB_BSTART_SHIFT 0
1761 #define DSPARB_BEND_SHIFT 9 /* on 855 */
1762 #define DSPARB_AEND_SHIFT 0
1764 #define DSPFW1 0x70034
1765 #define DSPFW2 0x70038
1766 #define DSPFW3 0x7003c
1767 #define IGD_SELF_REFRESH_EN (1<<30)
1769 /* FIFO watermark sizes etc */
1770 #define I915_FIFO_LINE_SIZE 64
1771 #define I830_FIFO_LINE_SIZE 32
1772 #define I945_FIFO_SIZE 127 /* 945 & 965 */
1773 #define I915_FIFO_SIZE 95
1774 #define I855GM_FIFO_SIZE 127 /* In cachelines */
1775 #define I830_FIFO_SIZE 95
1776 #define I915_MAX_WM 0x3f
1778 #define IGD_DISPLAY_FIFO 512 /* in 64byte unit */
1779 #define IGD_FIFO_LINE_SIZE 64
1780 #define IGD_MAX_WM 0x1ff
1781 #define IGD_DFT_WM 0x3f
1782 #define IGD_DFT_HPLLOFF_WM 0
1783 #define IGD_GUARD_WM 10
1784 #define IGD_CURSOR_FIFO 64
1785 #define IGD_CURSOR_MAX_WM 0x3f
1786 #define IGD_CURSOR_DFT_WM 0
1787 #define IGD_CURSOR_GUARD_WM 5
1790 * The two pipe frame counter registers are not synchronized, so
1791 * reading a stable value is somewhat tricky. The following code
1795 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1796 * PIPE_FRAME_HIGH_SHIFT;
1797 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
1798 * PIPE_FRAME_LOW_SHIFT);
1799 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1800 * PIPE_FRAME_HIGH_SHIFT);
1801 * } while (high1 != high2);
1802 * frame = (high1 << 8) | low1;
1804 #define PIPEAFRAMEHIGH 0x70040
1805 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
1806 #define PIPE_FRAME_HIGH_SHIFT 0
1807 #define PIPEAFRAMEPIXEL 0x70044
1808 #define PIPE_FRAME_LOW_MASK 0xff000000
1809 #define PIPE_FRAME_LOW_SHIFT 24
1810 #define PIPE_PIXEL_MASK 0x00ffffff
1811 #define PIPE_PIXEL_SHIFT 0
1812 /* GM45+ just has to be different */
1813 #define PIPEA_FRMCOUNT_GM45 0x70040
1814 #define PIPEA_FLIPCOUNT_GM45 0x70044
1816 /* Cursor A & B regs */
1817 #define CURACNTR 0x70080
1818 /* Old style CUR*CNTR flags (desktop 8xx) */
1819 #define CURSOR_ENABLE 0x80000000
1820 #define CURSOR_GAMMA_ENABLE 0x40000000
1821 #define CURSOR_STRIDE_MASK 0x30000000
1822 #define CURSOR_FORMAT_SHIFT 24
1823 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
1824 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
1825 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
1826 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
1827 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
1828 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
1829 /* New style CUR*CNTR flags */
1830 #define CURSOR_MODE 0x27
1831 #define CURSOR_MODE_DISABLE 0x00
1832 #define CURSOR_MODE_64_32B_AX 0x07
1833 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
1834 #define MCURSOR_PIPE_SELECT (1 << 28)
1835 #define MCURSOR_PIPE_A 0x00
1836 #define MCURSOR_PIPE_B (1 << 28)
1837 #define MCURSOR_GAMMA_ENABLE (1 << 26)
1838 #define CURABASE 0x70084
1839 #define CURAPOS 0x70088
1840 #define CURSOR_POS_MASK 0x007FF
1841 #define CURSOR_POS_SIGN 0x8000
1842 #define CURSOR_X_SHIFT 0
1843 #define CURSOR_Y_SHIFT 16
1844 #define CURSIZE 0x700a0
1845 #define CURBCNTR 0x700c0
1846 #define CURBBASE 0x700c4
1847 #define CURBPOS 0x700c8
1849 /* Display A control */
1850 #define DSPACNTR 0x70180
1851 #define DISPLAY_PLANE_ENABLE (1<<31)
1852 #define DISPLAY_PLANE_DISABLE 0
1853 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1854 #define DISPPLANE_GAMMA_DISABLE 0
1855 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1856 #define DISPPLANE_8BPP (0x2<<26)
1857 #define DISPPLANE_15_16BPP (0x4<<26)
1858 #define DISPPLANE_16BPP (0x5<<26)
1859 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1860 #define DISPPLANE_32BPP (0x7<<26)
1861 #define DISPPLANE_STEREO_ENABLE (1<<25)
1862 #define DISPPLANE_STEREO_DISABLE 0
1863 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1864 #define DISPPLANE_SEL_PIPE_A 0
1865 #define DISPPLANE_SEL_PIPE_B (1<<24)
1866 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1867 #define DISPPLANE_SRC_KEY_DISABLE 0
1868 #define DISPPLANE_LINE_DOUBLE (1<<20)
1869 #define DISPPLANE_NO_LINE_DOUBLE 0
1870 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1871 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1872 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* IGDNG */
1873 #define DISPPLANE_TILED (1<<10)
1874 #define DSPAADDR 0x70184
1875 #define DSPASTRIDE 0x70188
1876 #define DSPAPOS 0x7018C /* reserved */
1877 #define DSPASIZE 0x70190
1878 #define DSPASURF 0x7019C /* 965+ only */
1879 #define DSPATILEOFF 0x701A4 /* 965+ only */
1882 #define SWF00 0x71410
1883 #define SWF01 0x71414
1884 #define SWF02 0x71418
1885 #define SWF03 0x7141c
1886 #define SWF04 0x71420
1887 #define SWF05 0x71424
1888 #define SWF06 0x71428
1889 #define SWF10 0x70410
1890 #define SWF11 0x70414
1891 #define SWF14 0x71420
1892 #define SWF30 0x72414
1893 #define SWF31 0x72418
1894 #define SWF32 0x7241c
1897 #define PIPEBDSL 0x71000
1898 #define PIPEBCONF 0x71008
1899 #define PIPEBSTAT 0x71024
1900 #define PIPEBFRAMEHIGH 0x71040
1901 #define PIPEBFRAMEPIXEL 0x71044
1902 #define PIPEB_FRMCOUNT_GM45 0x71040
1903 #define PIPEB_FLIPCOUNT_GM45 0x71044
1906 /* Display B control */
1907 #define DSPBCNTR 0x71180
1908 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1909 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1910 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
1911 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1912 #define DSPBADDR 0x71184
1913 #define DSPBSTRIDE 0x71188
1914 #define DSPBPOS 0x7118C
1915 #define DSPBSIZE 0x71190
1916 #define DSPBSURF 0x7119C
1917 #define DSPBTILEOFF 0x711A4
1920 #define VGACNTRL 0x71400
1921 # define VGA_DISP_DISABLE (1 << 31)
1922 # define VGA_2X_MODE (1 << 30)
1923 # define VGA_PIPE_B_SELECT (1 << 29)
1927 #define CPU_VGACNTRL 0x41000
1929 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
1930 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
1931 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
1932 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
1933 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
1934 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
1935 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
1936 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
1937 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
1939 /* refresh rate hardware control */
1940 #define RR_HW_CTL 0x45300
1941 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
1942 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
1944 #define FDI_PLL_BIOS_0 0x46000
1945 #define FDI_PLL_BIOS_1 0x46004
1946 #define FDI_PLL_BIOS_2 0x46008
1947 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
1948 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
1949 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
1951 #define FDI_PLL_FREQ_CTL 0x46030
1952 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
1953 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
1954 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
1957 #define PIPEA_DATA_M1 0x60030
1958 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
1959 #define TU_SIZE_MASK 0x7e000000
1960 #define PIPEA_DATA_M1_OFFSET 0
1961 #define PIPEA_DATA_N1 0x60034
1962 #define PIPEA_DATA_N1_OFFSET 0
1964 #define PIPEA_DATA_M2 0x60038
1965 #define PIPEA_DATA_M2_OFFSET 0
1966 #define PIPEA_DATA_N2 0x6003c
1967 #define PIPEA_DATA_N2_OFFSET 0
1969 #define PIPEA_LINK_M1 0x60040
1970 #define PIPEA_LINK_M1_OFFSET 0
1971 #define PIPEA_LINK_N1 0x60044
1972 #define PIPEA_LINK_N1_OFFSET 0
1974 #define PIPEA_LINK_M2 0x60048
1975 #define PIPEA_LINK_M2_OFFSET 0
1976 #define PIPEA_LINK_N2 0x6004c
1977 #define PIPEA_LINK_N2_OFFSET 0
1979 /* PIPEB timing regs are same start from 0x61000 */
1981 #define PIPEB_DATA_M1 0x61030
1982 #define PIPEB_DATA_M1_OFFSET 0
1983 #define PIPEB_DATA_N1 0x61034
1984 #define PIPEB_DATA_N1_OFFSET 0
1986 #define PIPEB_DATA_M2 0x61038
1987 #define PIPEB_DATA_M2_OFFSET 0
1988 #define PIPEB_DATA_N2 0x6103c
1989 #define PIPEB_DATA_N2_OFFSET 0
1991 #define PIPEB_LINK_M1 0x61040
1992 #define PIPEB_LINK_M1_OFFSET 0
1993 #define PIPEB_LINK_N1 0x61044
1994 #define PIPEB_LINK_N1_OFFSET 0
1996 #define PIPEB_LINK_M2 0x61048
1997 #define PIPEB_LINK_M2_OFFSET 0
1998 #define PIPEB_LINK_N2 0x6104c
1999 #define PIPEB_LINK_N2_OFFSET 0
2001 /* CPU panel fitter */
2002 #define PFA_CTL_1 0x68080
2003 #define PFB_CTL_1 0x68880
2004 #define PF_ENABLE (1<<31)
2005 #define PFA_WIN_SZ 0x68074
2006 #define PFB_WIN_SZ 0x68874
2007 #define PFA_WIN_POS 0x68070
2008 #define PFB_WIN_POS 0x68870
2010 /* legacy palette */
2011 #define LGC_PALETTE_A 0x4a000
2012 #define LGC_PALETTE_B 0x4a800
2015 #define DE_MASTER_IRQ_CONTROL (1 << 31)
2016 #define DE_SPRITEB_FLIP_DONE (1 << 29)
2017 #define DE_SPRITEA_FLIP_DONE (1 << 28)
2018 #define DE_PLANEB_FLIP_DONE (1 << 27)
2019 #define DE_PLANEA_FLIP_DONE (1 << 26)
2020 #define DE_PCU_EVENT (1 << 25)
2021 #define DE_GTT_FAULT (1 << 24)
2022 #define DE_POISON (1 << 23)
2023 #define DE_PERFORM_COUNTER (1 << 22)
2024 #define DE_PCH_EVENT (1 << 21)
2025 #define DE_AUX_CHANNEL_A (1 << 20)
2026 #define DE_DP_A_HOTPLUG (1 << 19)
2027 #define DE_GSE (1 << 18)
2028 #define DE_PIPEB_VBLANK (1 << 15)
2029 #define DE_PIPEB_EVEN_FIELD (1 << 14)
2030 #define DE_PIPEB_ODD_FIELD (1 << 13)
2031 #define DE_PIPEB_LINE_COMPARE (1 << 12)
2032 #define DE_PIPEB_VSYNC (1 << 11)
2033 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2034 #define DE_PIPEA_VBLANK (1 << 7)
2035 #define DE_PIPEA_EVEN_FIELD (1 << 6)
2036 #define DE_PIPEA_ODD_FIELD (1 << 5)
2037 #define DE_PIPEA_LINE_COMPARE (1 << 4)
2038 #define DE_PIPEA_VSYNC (1 << 3)
2039 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2041 #define DEISR 0x44000
2042 #define DEIMR 0x44004
2043 #define DEIIR 0x44008
2044 #define DEIER 0x4400c
2047 #define GT_SYNC_STATUS (1 << 2)
2048 #define GT_USER_INTERRUPT (1 << 0)
2050 #define GTISR 0x44010
2051 #define GTIMR 0x44014
2052 #define GTIIR 0x44018
2053 #define GTIER 0x4401c
2055 #define DISP_ARB_CTL 0x45000
2056 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2060 /* south display engine interrupt */
2061 #define SDE_CRT_HOTPLUG (1 << 11)
2062 #define SDE_PORTD_HOTPLUG (1 << 10)
2063 #define SDE_PORTC_HOTPLUG (1 << 9)
2064 #define SDE_PORTB_HOTPLUG (1 << 8)
2065 #define SDE_SDVOB_HOTPLUG (1 << 6)
2067 #define SDEISR 0xc4000
2068 #define SDEIMR 0xc4004
2069 #define SDEIIR 0xc4008
2070 #define SDEIER 0xc400c
2072 /* digital port hotplug */
2073 #define PCH_PORT_HOTPLUG 0xc4030
2074 #define PORTD_HOTPLUG_ENABLE (1 << 20)
2075 #define PORTD_PULSE_DURATION_2ms (0)
2076 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2077 #define PORTD_PULSE_DURATION_6ms (2 << 18)
2078 #define PORTD_PULSE_DURATION_100ms (3 << 18)
2079 #define PORTD_HOTPLUG_NO_DETECT (0)
2080 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2081 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2082 #define PORTC_HOTPLUG_ENABLE (1 << 12)
2083 #define PORTC_PULSE_DURATION_2ms (0)
2084 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2085 #define PORTC_PULSE_DURATION_6ms (2 << 10)
2086 #define PORTC_PULSE_DURATION_100ms (3 << 10)
2087 #define PORTC_HOTPLUG_NO_DETECT (0)
2088 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2089 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2090 #define PORTB_HOTPLUG_ENABLE (1 << 4)
2091 #define PORTB_PULSE_DURATION_2ms (0)
2092 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2093 #define PORTB_PULSE_DURATION_6ms (2 << 2)
2094 #define PORTB_PULSE_DURATION_100ms (3 << 2)
2095 #define PORTB_HOTPLUG_NO_DETECT (0)
2096 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2097 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2099 #define PCH_GPIOA 0xc5010
2100 #define PCH_GPIOB 0xc5014
2101 #define PCH_GPIOC 0xc5018
2102 #define PCH_GPIOD 0xc501c
2103 #define PCH_GPIOE 0xc5020
2104 #define PCH_GPIOF 0xc5024
2106 #define PCH_DPLL_A 0xc6014
2107 #define PCH_DPLL_B 0xc6018
2109 #define PCH_FPA0 0xc6040
2110 #define PCH_FPA1 0xc6044
2111 #define PCH_FPB0 0xc6048
2112 #define PCH_FPB1 0xc604c
2114 #define PCH_DPLL_TEST 0xc606c
2116 #define PCH_DREF_CONTROL 0xC6200
2117 #define DREF_CONTROL_MASK 0x7fc3
2118 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2119 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2120 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2121 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2122 #define DREF_SSC_SOURCE_DISABLE (0<<11)
2123 #define DREF_SSC_SOURCE_ENABLE (2<<11)
2124 #define DREF_SSC_SOURCE_MASK (2<<11)
2125 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2126 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2127 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2128 #define DREF_NONSPREAD_SOURCE_MASK (2<<9)
2129 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2130 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2131 #define DREF_SSC4_DOWNSPREAD (0<<6)
2132 #define DREF_SSC4_CENTERSPREAD (1<<6)
2133 #define DREF_SSC1_DISABLE (0<<1)
2134 #define DREF_SSC1_ENABLE (1<<1)
2135 #define DREF_SSC4_DISABLE (0)
2136 #define DREF_SSC4_ENABLE (1)
2138 #define PCH_RAWCLK_FREQ 0xc6204
2139 #define FDL_TP1_TIMER_SHIFT 12
2140 #define FDL_TP1_TIMER_MASK (3<<12)
2141 #define FDL_TP2_TIMER_SHIFT 10
2142 #define FDL_TP2_TIMER_MASK (3<<10)
2143 #define RAWCLK_FREQ_MASK 0x3ff
2145 #define PCH_DPLL_TMR_CFG 0xc6208
2147 #define PCH_SSC4_PARMS 0xc6210
2148 #define PCH_SSC4_AUX_PARMS 0xc6214
2152 #define TRANS_HTOTAL_A 0xe0000
2153 #define TRANS_HTOTAL_SHIFT 16
2154 #define TRANS_HACTIVE_SHIFT 0
2155 #define TRANS_HBLANK_A 0xe0004
2156 #define TRANS_HBLANK_END_SHIFT 16
2157 #define TRANS_HBLANK_START_SHIFT 0
2158 #define TRANS_HSYNC_A 0xe0008
2159 #define TRANS_HSYNC_END_SHIFT 16
2160 #define TRANS_HSYNC_START_SHIFT 0
2161 #define TRANS_VTOTAL_A 0xe000c
2162 #define TRANS_VTOTAL_SHIFT 16
2163 #define TRANS_VACTIVE_SHIFT 0
2164 #define TRANS_VBLANK_A 0xe0010
2165 #define TRANS_VBLANK_END_SHIFT 16
2166 #define TRANS_VBLANK_START_SHIFT 0
2167 #define TRANS_VSYNC_A 0xe0014
2168 #define TRANS_VSYNC_END_SHIFT 16
2169 #define TRANS_VSYNC_START_SHIFT 0
2171 #define TRANSA_DATA_M1 0xe0030
2172 #define TRANSA_DATA_N1 0xe0034
2173 #define TRANSA_DATA_M2 0xe0038
2174 #define TRANSA_DATA_N2 0xe003c
2175 #define TRANSA_DP_LINK_M1 0xe0040
2176 #define TRANSA_DP_LINK_N1 0xe0044
2177 #define TRANSA_DP_LINK_M2 0xe0048
2178 #define TRANSA_DP_LINK_N2 0xe004c
2180 #define TRANS_HTOTAL_B 0xe1000
2181 #define TRANS_HBLANK_B 0xe1004
2182 #define TRANS_HSYNC_B 0xe1008
2183 #define TRANS_VTOTAL_B 0xe100c
2184 #define TRANS_VBLANK_B 0xe1010
2185 #define TRANS_VSYNC_B 0xe1014
2187 #define TRANSB_DATA_M1 0xe1030
2188 #define TRANSB_DATA_N1 0xe1034
2189 #define TRANSB_DATA_M2 0xe1038
2190 #define TRANSB_DATA_N2 0xe103c
2191 #define TRANSB_DP_LINK_M1 0xe1040
2192 #define TRANSB_DP_LINK_N1 0xe1044
2193 #define TRANSB_DP_LINK_M2 0xe1048
2194 #define TRANSB_DP_LINK_N2 0xe104c
2196 #define TRANSACONF 0xf0008
2197 #define TRANSBCONF 0xf1008
2198 #define TRANS_DISABLE (0<<31)
2199 #define TRANS_ENABLE (1<<31)
2200 #define TRANS_STATE_MASK (1<<30)
2201 #define TRANS_STATE_DISABLE (0<<30)
2202 #define TRANS_STATE_ENABLE (1<<30)
2203 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
2204 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
2205 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
2206 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
2207 #define TRANS_DP_AUDIO_ONLY (1<<26)
2208 #define TRANS_DP_VIDEO_AUDIO (0<<26)
2209 #define TRANS_PROGRESSIVE (0<<21)
2210 #define TRANS_8BPC (0<<5)
2211 #define TRANS_10BPC (1<<5)
2212 #define TRANS_6BPC (2<<5)
2213 #define TRANS_12BPC (3<<5)
2215 #define FDI_RXA_CHICKEN 0xc200c
2216 #define FDI_RXB_CHICKEN 0xc2010
2217 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
2220 #define FDI_TXA_CTL 0x60100
2221 #define FDI_TXB_CTL 0x61100
2222 #define FDI_TX_DISABLE (0<<31)
2223 #define FDI_TX_ENABLE (1<<31)
2224 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
2225 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
2226 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
2227 #define FDI_LINK_TRAIN_NONE (3<<28)
2228 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
2229 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
2230 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
2231 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
2232 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
2233 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
2234 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
2235 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
2236 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
2237 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
2238 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
2239 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
2240 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
2241 /* IGDNG: hardwired to 1 */
2242 #define FDI_TX_PLL_ENABLE (1<<14)
2243 /* both Tx and Rx */
2244 #define FDI_SCRAMBLING_ENABLE (0<<7)
2245 #define FDI_SCRAMBLING_DISABLE (1<<7)
2247 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
2248 #define FDI_RXA_CTL 0xf000c
2249 #define FDI_RXB_CTL 0xf100c
2250 #define FDI_RX_ENABLE (1<<31)
2251 #define FDI_RX_DISABLE (0<<31)
2252 /* train, dp width same as FDI_TX */
2253 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
2254 #define FDI_8BPC (0<<16)
2255 #define FDI_10BPC (1<<16)
2256 #define FDI_6BPC (2<<16)
2257 #define FDI_12BPC (3<<16)
2258 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
2259 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
2260 #define FDI_RX_PLL_ENABLE (1<<13)
2261 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
2262 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
2263 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
2264 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
2265 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2266 #define FDI_SEL_RAWCLK (0<<4)
2267 #define FDI_SEL_PCDCLK (1<<4)
2269 #define FDI_RXA_MISC 0xf0010
2270 #define FDI_RXB_MISC 0xf1010
2271 #define FDI_RXA_TUSIZE1 0xf0030
2272 #define FDI_RXA_TUSIZE2 0xf0038
2273 #define FDI_RXB_TUSIZE1 0xf1030
2274 #define FDI_RXB_TUSIZE2 0xf1038
2276 /* FDI_RX interrupt register format */
2277 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
2278 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
2279 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
2280 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
2281 #define FDI_RX_FS_CODE_ERR (1<<6)
2282 #define FDI_RX_FE_CODE_ERR (1<<5)
2283 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
2284 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
2285 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
2286 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
2287 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
2289 #define FDI_RXA_IIR 0xf0014
2290 #define FDI_RXA_IMR 0xf0018
2291 #define FDI_RXB_IIR 0xf1014
2292 #define FDI_RXB_IMR 0xf1018
2294 #define FDI_PLL_CTL_1 0xfe000
2295 #define FDI_PLL_CTL_2 0xfe004
2298 #define PCH_ADPA 0xe1100
2299 #define ADPA_TRANS_SELECT_MASK (1<<30)
2300 #define ADPA_TRANS_A_SELECT 0
2301 #define ADPA_TRANS_B_SELECT (1<<30)
2302 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2303 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2304 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2305 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2306 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2307 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2308 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2309 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2310 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2311 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2312 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2313 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2314 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2315 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2316 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2317 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2318 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2319 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2320 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2323 #define HDMIB 0xe1140
2324 #define PORT_ENABLE (1 << 31)
2325 #define TRANSCODER_A (0)
2326 #define TRANSCODER_B (1 << 30)
2327 #define COLOR_FORMAT_8bpc (0)
2328 #define COLOR_FORMAT_12bpc (3 << 26)
2329 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
2330 #define SDVO_ENCODING (0)
2331 #define TMDS_ENCODING (2 << 10)
2332 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
2333 #define SDVOB_BORDER_ENABLE (1 << 7)
2334 #define AUDIO_ENABLE (1 << 6)
2335 #define VSYNC_ACTIVE_HIGH (1 << 4)
2336 #define HSYNC_ACTIVE_HIGH (1 << 3)
2337 #define PORT_DETECTED (1 << 2)
2339 #define HDMIC 0xe1150
2340 #define HDMID 0xe1160
2342 #define PCH_LVDS 0xe1180
2343 #define LVDS_DETECTED (1 << 1)
2345 #define BLC_PWM_CPU_CTL2 0x48250
2346 #define PWM_ENABLE (1 << 31)
2347 #define PWM_PIPE_A (0 << 29)
2348 #define PWM_PIPE_B (1 << 29)
2349 #define BLC_PWM_CPU_CTL 0x48254
2351 #define BLC_PWM_PCH_CTL1 0xc8250
2352 #define PWM_PCH_ENABLE (1 << 31)
2353 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
2354 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
2355 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
2356 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
2358 #define BLC_PWM_PCH_CTL2 0xc8254
2360 #define PCH_PP_STATUS 0xc7200
2361 #define PCH_PP_CONTROL 0xc7204
2362 #define EDP_FORCE_VDD (1 << 3)
2363 #define EDP_BLC_ENABLE (1 << 2)
2364 #define PANEL_POWER_RESET (1 << 1)
2365 #define PANEL_POWER_OFF (0 << 0)
2366 #define PANEL_POWER_ON (1 << 0)
2367 #define PCH_PP_ON_DELAYS 0xc7208
2368 #define EDP_PANEL (1 << 30)
2369 #define PCH_PP_OFF_DELAYS 0xc720c
2370 #define PCH_PP_DIVISOR 0xc7210
2372 #define PCH_DP_B 0xe4100
2373 #define PCH_DPB_AUX_CH_CTL 0xe4110
2374 #define PCH_DPB_AUX_CH_DATA1 0xe4114
2375 #define PCH_DPB_AUX_CH_DATA2 0xe4118
2376 #define PCH_DPB_AUX_CH_DATA3 0xe411c
2377 #define PCH_DPB_AUX_CH_DATA4 0xe4120
2378 #define PCH_DPB_AUX_CH_DATA5 0xe4124
2380 #define PCH_DP_C 0xe4200
2381 #define PCH_DPC_AUX_CH_CTL 0xe4210
2382 #define PCH_DPC_AUX_CH_DATA1 0xe4214
2383 #define PCH_DPC_AUX_CH_DATA2 0xe4218
2384 #define PCH_DPC_AUX_CH_DATA3 0xe421c
2385 #define PCH_DPC_AUX_CH_DATA4 0xe4220
2386 #define PCH_DPC_AUX_CH_DATA5 0xe4224
2388 #define PCH_DP_D 0xe4300
2389 #define PCH_DPD_AUX_CH_CTL 0xe4310
2390 #define PCH_DPD_AUX_CH_DATA1 0xe4314
2391 #define PCH_DPD_AUX_CH_DATA2 0xe4318
2392 #define PCH_DPD_AUX_CH_DATA3 0xe431c
2393 #define PCH_DPD_AUX_CH_DATA4 0xe4320
2394 #define PCH_DPD_AUX_CH_DATA5 0xe4324
2396 #endif /* _I915_REG_H_ */