1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "i915_reg_defs.h"
29 #include "display/intel_display_reg_defs.h"
32 * DOC: The i915 register macro definition style guide
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
40 * Keep helper macros near the top. For example, _PIPE() and friends.
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
54 * For single registers, define the register offset first, followed by register
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
119 #define GU_CNTL _MMIO(0x101010)
120 #define LMEM_INIT REG_BIT(7)
122 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
123 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
124 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
125 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
126 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
127 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
128 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
129 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
130 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
131 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
132 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
133 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
134 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
135 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
136 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
137 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
138 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
139 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
141 #define _VGA_MSR_WRITE _MMIO(0x3c2)
143 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
144 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
145 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
150 #define DEBUG_RESET_I830 _MMIO(0x6070)
151 #define DEBUG_RESET_FULL (1 << 7)
152 #define DEBUG_RESET_RENDER (1 << 8)
153 #define DEBUG_RESET_DISPLAY (1 << 9)
158 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
159 #define IOSF_DEVFN_SHIFT 24
160 #define IOSF_OPCODE_SHIFT 16
161 #define IOSF_PORT_SHIFT 8
162 #define IOSF_BYTE_ENABLES_SHIFT 4
163 #define IOSF_BAR_SHIFT 1
164 #define IOSF_SB_BUSY (1 << 0)
165 #define IOSF_PORT_BUNIT 0x03
166 #define IOSF_PORT_PUNIT 0x04
167 #define IOSF_PORT_NC 0x11
168 #define IOSF_PORT_DPIO 0x12
169 #define IOSF_PORT_GPIO_NC 0x13
170 #define IOSF_PORT_CCK 0x14
171 #define IOSF_PORT_DPIO_2 0x1a
172 #define IOSF_PORT_FLISDSI 0x1b
173 #define IOSF_PORT_GPIO_SC 0x48
174 #define IOSF_PORT_GPIO_SUS 0xa8
175 #define IOSF_PORT_CCU 0xa9
176 #define CHV_IOSF_PORT_GPIO_N 0x13
177 #define CHV_IOSF_PORT_GPIO_SE 0x48
178 #define CHV_IOSF_PORT_GPIO_E 0xa8
179 #define CHV_IOSF_PORT_GPIO_SW 0xb2
180 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
181 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
186 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
187 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
188 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
189 #define DPIO_SFR_BYPASS (1 << 1)
190 #define DPIO_CMNRST (1 << 0)
192 #define DPIO_PHY(pipe) ((pipe) >> 1)
195 * Per pipe/PLL DPIO regs
197 #define _VLV_PLL_DW3_CH0 0x800c
198 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
199 #define DPIO_POST_DIV_DAC 0
200 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
201 #define DPIO_POST_DIV_LVDS1 2
202 #define DPIO_POST_DIV_LVDS2 3
203 #define DPIO_K_SHIFT (24) /* 4 bits */
204 #define DPIO_P1_SHIFT (21) /* 3 bits */
205 #define DPIO_P2_SHIFT (16) /* 5 bits */
206 #define DPIO_N_SHIFT (12) /* 4 bits */
207 #define DPIO_ENABLE_CALIBRATION (1 << 11)
208 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
209 #define DPIO_M2DIV_MASK 0xff
210 #define _VLV_PLL_DW3_CH1 0x802c
211 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
213 #define _VLV_PLL_DW5_CH0 0x8014
214 #define DPIO_REFSEL_OVERRIDE 27
215 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
216 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
217 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
218 #define DPIO_PLL_REFCLK_SEL_MASK 3
219 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
220 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
221 #define _VLV_PLL_DW5_CH1 0x8034
222 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
224 #define _VLV_PLL_DW7_CH0 0x801c
225 #define _VLV_PLL_DW7_CH1 0x803c
226 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
228 #define _VLV_PLL_DW8_CH0 0x8040
229 #define _VLV_PLL_DW8_CH1 0x8060
230 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
232 #define VLV_PLL_DW9_BCAST 0xc044
233 #define _VLV_PLL_DW9_CH0 0x8044
234 #define _VLV_PLL_DW9_CH1 0x8064
235 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
237 #define _VLV_PLL_DW10_CH0 0x8048
238 #define _VLV_PLL_DW10_CH1 0x8068
239 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
241 #define _VLV_PLL_DW11_CH0 0x804c
242 #define _VLV_PLL_DW11_CH1 0x806c
243 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
245 /* Spec for ref block start counts at DW10 */
246 #define VLV_REF_DW13 0x80ac
248 #define VLV_CMN_DW0 0x8100
251 * Per DDI channel DPIO regs
254 #define _VLV_PCS_DW0_CH0 0x8200
255 #define _VLV_PCS_DW0_CH1 0x8400
256 #define DPIO_PCS_TX_LANE2_RESET (1 << 16)
257 #define DPIO_PCS_TX_LANE1_RESET (1 << 7)
258 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
259 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
260 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
262 #define _VLV_PCS01_DW0_CH0 0x200
263 #define _VLV_PCS23_DW0_CH0 0x400
264 #define _VLV_PCS01_DW0_CH1 0x2600
265 #define _VLV_PCS23_DW0_CH1 0x2800
266 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
267 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
269 #define _VLV_PCS_DW1_CH0 0x8204
270 #define _VLV_PCS_DW1_CH1 0x8404
271 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
272 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
273 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
274 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
275 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
276 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
278 #define _VLV_PCS01_DW1_CH0 0x204
279 #define _VLV_PCS23_DW1_CH0 0x404
280 #define _VLV_PCS01_DW1_CH1 0x2604
281 #define _VLV_PCS23_DW1_CH1 0x2804
282 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
283 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
285 #define _VLV_PCS_DW8_CH0 0x8220
286 #define _VLV_PCS_DW8_CH1 0x8420
287 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
288 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
289 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
291 #define _VLV_PCS01_DW8_CH0 0x0220
292 #define _VLV_PCS23_DW8_CH0 0x0420
293 #define _VLV_PCS01_DW8_CH1 0x2620
294 #define _VLV_PCS23_DW8_CH1 0x2820
295 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
296 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
298 #define _VLV_PCS_DW9_CH0 0x8224
299 #define _VLV_PCS_DW9_CH1 0x8424
300 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
301 #define DPIO_PCS_TX2MARGIN_000 (0 << 13)
302 #define DPIO_PCS_TX2MARGIN_101 (1 << 13)
303 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
304 #define DPIO_PCS_TX1MARGIN_000 (0 << 10)
305 #define DPIO_PCS_TX1MARGIN_101 (1 << 10)
306 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
308 #define _VLV_PCS01_DW9_CH0 0x224
309 #define _VLV_PCS23_DW9_CH0 0x424
310 #define _VLV_PCS01_DW9_CH1 0x2624
311 #define _VLV_PCS23_DW9_CH1 0x2824
312 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
313 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
315 #define _CHV_PCS_DW10_CH0 0x8228
316 #define _CHV_PCS_DW10_CH1 0x8428
317 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
318 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
319 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
320 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
321 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
322 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
323 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
324 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
325 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
327 #define _VLV_PCS01_DW10_CH0 0x0228
328 #define _VLV_PCS23_DW10_CH0 0x0428
329 #define _VLV_PCS01_DW10_CH1 0x2628
330 #define _VLV_PCS23_DW10_CH1 0x2828
331 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
332 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
334 #define _VLV_PCS_DW11_CH0 0x822c
335 #define _VLV_PCS_DW11_CH1 0x842c
336 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
337 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
338 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
339 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
340 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
342 #define _VLV_PCS01_DW11_CH0 0x022c
343 #define _VLV_PCS23_DW11_CH0 0x042c
344 #define _VLV_PCS01_DW11_CH1 0x262c
345 #define _VLV_PCS23_DW11_CH1 0x282c
346 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
347 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
349 #define _VLV_PCS01_DW12_CH0 0x0230
350 #define _VLV_PCS23_DW12_CH0 0x0430
351 #define _VLV_PCS01_DW12_CH1 0x2630
352 #define _VLV_PCS23_DW12_CH1 0x2830
353 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
354 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
356 #define _VLV_PCS_DW12_CH0 0x8230
357 #define _VLV_PCS_DW12_CH1 0x8430
358 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
359 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
360 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
361 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
362 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
363 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
365 #define _VLV_PCS_DW14_CH0 0x8238
366 #define _VLV_PCS_DW14_CH1 0x8438
367 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
369 #define _VLV_PCS_DW23_CH0 0x825c
370 #define _VLV_PCS_DW23_CH1 0x845c
371 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
373 #define _VLV_TX_DW2_CH0 0x8288
374 #define _VLV_TX_DW2_CH1 0x8488
375 #define DPIO_SWING_MARGIN000_SHIFT 16
376 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
377 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
378 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
380 #define _VLV_TX_DW3_CH0 0x828c
381 #define _VLV_TX_DW3_CH1 0x848c
382 /* The following bit for CHV phy */
383 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
384 #define DPIO_SWING_MARGIN101_SHIFT 16
385 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
386 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
388 #define _VLV_TX_DW4_CH0 0x8290
389 #define _VLV_TX_DW4_CH1 0x8490
390 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
391 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
392 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
393 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
394 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
396 #define _VLV_TX3_DW4_CH0 0x690
397 #define _VLV_TX3_DW4_CH1 0x2a90
398 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
400 #define _VLV_TX_DW5_CH0 0x8294
401 #define _VLV_TX_DW5_CH1 0x8494
402 #define DPIO_TX_OCALINIT_EN (1 << 31)
403 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
405 #define _VLV_TX_DW11_CH0 0x82ac
406 #define _VLV_TX_DW11_CH1 0x84ac
407 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
409 #define _VLV_TX_DW14_CH0 0x82b8
410 #define _VLV_TX_DW14_CH1 0x84b8
411 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
413 /* CHV dpPhy registers */
414 #define _CHV_PLL_DW0_CH0 0x8000
415 #define _CHV_PLL_DW0_CH1 0x8180
416 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
418 #define _CHV_PLL_DW1_CH0 0x8004
419 #define _CHV_PLL_DW1_CH1 0x8184
420 #define DPIO_CHV_N_DIV_SHIFT 8
421 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
422 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
424 #define _CHV_PLL_DW2_CH0 0x8008
425 #define _CHV_PLL_DW2_CH1 0x8188
426 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
428 #define _CHV_PLL_DW3_CH0 0x800c
429 #define _CHV_PLL_DW3_CH1 0x818c
430 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
431 #define DPIO_CHV_FIRST_MOD (0 << 8)
432 #define DPIO_CHV_SECOND_MOD (1 << 8)
433 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
434 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
435 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
437 #define _CHV_PLL_DW6_CH0 0x8018
438 #define _CHV_PLL_DW6_CH1 0x8198
439 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
440 #define DPIO_CHV_INT_COEFF_SHIFT 8
441 #define DPIO_CHV_PROP_COEFF_SHIFT 0
442 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
444 #define _CHV_PLL_DW8_CH0 0x8020
445 #define _CHV_PLL_DW8_CH1 0x81A0
446 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
447 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
448 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
450 #define _CHV_PLL_DW9_CH0 0x8024
451 #define _CHV_PLL_DW9_CH1 0x81A4
452 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
453 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
454 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
455 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
457 #define _CHV_CMN_DW0_CH0 0x8100
458 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
459 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
460 #define DPIO_ALLDL_POWERDOWN (1 << 1)
461 #define DPIO_ANYDL_POWERDOWN (1 << 0)
463 #define _CHV_CMN_DW5_CH0 0x8114
464 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
465 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
466 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
467 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
468 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
469 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
470 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
471 #define CHV_BUFLEFTENA1_MASK (3 << 22)
473 #define _CHV_CMN_DW13_CH0 0x8134
474 #define _CHV_CMN_DW0_CH1 0x8080
475 #define DPIO_CHV_S1_DIV_SHIFT 21
476 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
477 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
478 #define DPIO_CHV_K_DIV_SHIFT 4
479 #define DPIO_PLL_FREQLOCK (1 << 1)
480 #define DPIO_PLL_LOCK (1 << 0)
481 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
483 #define _CHV_CMN_DW14_CH0 0x8138
484 #define _CHV_CMN_DW1_CH1 0x8084
485 #define DPIO_AFC_RECAL (1 << 14)
486 #define DPIO_DCLKP_EN (1 << 13)
487 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
488 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
489 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
490 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
491 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
492 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
493 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
494 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
495 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
497 #define _CHV_CMN_DW19_CH0 0x814c
498 #define _CHV_CMN_DW6_CH1 0x8098
499 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
500 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
501 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
502 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
504 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
506 #define CHV_CMN_DW28 0x8170
507 #define DPIO_CL1POWERDOWNEN (1 << 23)
508 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
509 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
510 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
511 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
512 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
514 #define CHV_CMN_DW30 0x8178
515 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
516 #define DPIO_LRC_BYPASS (1 << 3)
518 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
519 (lane) * 0x200 + (offset))
521 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
522 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
523 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
524 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
525 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
526 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
527 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
528 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
529 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
530 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
531 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
532 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
533 #define DPIO_FRC_LATENCY_SHFIT 8
534 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
535 #define DPIO_UPAR_SHIFT 30
537 /* BXT PHY registers */
538 #define _BXT_PHY0_BASE 0x6C000
539 #define _BXT_PHY1_BASE 0x162000
540 #define _BXT_PHY2_BASE 0x163000
541 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
545 #define _BXT_PHY(phy, reg) \
546 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
548 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
549 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
550 (reg_ch1) - _BXT_PHY0_BASE))
551 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
552 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
554 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
555 #define MIPIO_RST_CTRL (1 << 2)
557 #define _BXT_PHY_CTL_DDI_A 0x64C00
558 #define _BXT_PHY_CTL_DDI_B 0x64C10
559 #define _BXT_PHY_CTL_DDI_C 0x64C20
560 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
561 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
562 #define BXT_PHY_LANE_ENABLED (1 << 8)
563 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
566 #define _PHY_CTL_FAMILY_EDP 0x64C80
567 #define _PHY_CTL_FAMILY_DDI 0x64C90
568 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
569 #define COMMON_RESET_DIS (1 << 31)
570 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
571 _PHY_CTL_FAMILY_EDP, \
572 _PHY_CTL_FAMILY_DDI_C)
574 /* BXT PHY PLL registers */
575 #define _PORT_PLL_A 0x46074
576 #define _PORT_PLL_B 0x46078
577 #define _PORT_PLL_C 0x4607c
578 #define PORT_PLL_ENABLE REG_BIT(31)
579 #define PORT_PLL_LOCK REG_BIT(30)
580 #define PORT_PLL_REF_SEL REG_BIT(27)
581 #define PORT_PLL_POWER_ENABLE REG_BIT(26)
582 #define PORT_PLL_POWER_STATE REG_BIT(25)
583 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
585 #define _PORT_PLL_EBB_0_A 0x162034
586 #define _PORT_PLL_EBB_0_B 0x6C034
587 #define _PORT_PLL_EBB_0_C 0x6C340
588 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
589 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
590 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
591 #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
592 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
596 #define _PORT_PLL_EBB_4_A 0x162038
597 #define _PORT_PLL_EBB_4_B 0x6C038
598 #define _PORT_PLL_EBB_4_C 0x6C344
599 #define PORT_PLL_RECALIBRATE REG_BIT(14)
600 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
601 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
605 #define _PORT_PLL_0_A 0x162100
606 #define _PORT_PLL_0_B 0x6C100
607 #define _PORT_PLL_0_C 0x6C380
609 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
610 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
612 #define PORT_PLL_N_MASK REG_GENMASK(11, 8)
613 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
615 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
616 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
618 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
620 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
621 #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
622 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
623 #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
624 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
625 #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
627 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
628 #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
630 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
631 #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
633 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
634 #define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10)
635 #define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
636 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
639 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
642 /* BXT PHY common lane registers */
643 #define _PORT_CL1CM_DW0_A 0x162000
644 #define _PORT_CL1CM_DW0_BC 0x6C000
645 #define PHY_POWER_GOOD (1 << 16)
646 #define PHY_RESERVED (1 << 7)
647 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
649 #define _PORT_CL1CM_DW9_A 0x162024
650 #define _PORT_CL1CM_DW9_BC 0x6C024
651 #define IREF0RC_OFFSET_SHIFT 8
652 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
653 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
655 #define _PORT_CL1CM_DW10_A 0x162028
656 #define _PORT_CL1CM_DW10_BC 0x6C028
657 #define IREF1RC_OFFSET_SHIFT 8
658 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
659 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
661 #define _PORT_CL1CM_DW28_A 0x162070
662 #define _PORT_CL1CM_DW28_BC 0x6C070
663 #define OCL1_POWER_DOWN_EN (1 << 23)
664 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
665 #define SUS_CLK_CONFIG 0x3
666 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
668 #define _PORT_CL1CM_DW30_A 0x162078
669 #define _PORT_CL1CM_DW30_BC 0x6C078
670 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
671 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
673 /* The spec defines this only for BXT PHY0, but lets assume that this
674 * would exist for PHY1 too if it had a second channel.
676 #define _PORT_CL2CM_DW6_A 0x162358
677 #define _PORT_CL2CM_DW6_BC 0x6C358
678 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
679 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
681 /* BXT PHY Ref registers */
682 #define _PORT_REF_DW3_A 0x16218C
683 #define _PORT_REF_DW3_BC 0x6C18C
684 #define GRC_DONE (1 << 22)
685 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
687 #define _PORT_REF_DW6_A 0x162198
688 #define _PORT_REF_DW6_BC 0x6C198
689 #define GRC_CODE_SHIFT 24
690 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
691 #define GRC_CODE_FAST_SHIFT 16
692 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
693 #define GRC_CODE_SLOW_SHIFT 8
694 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
695 #define GRC_CODE_NOM_MASK 0xFF
696 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
698 #define _PORT_REF_DW8_A 0x1621A0
699 #define _PORT_REF_DW8_BC 0x6C1A0
700 #define GRC_DIS (1 << 15)
701 #define GRC_RDY_OVRD (1 << 1)
702 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
704 /* BXT PHY PCS registers */
705 #define _PORT_PCS_DW10_LN01_A 0x162428
706 #define _PORT_PCS_DW10_LN01_B 0x6C428
707 #define _PORT_PCS_DW10_LN01_C 0x6C828
708 #define _PORT_PCS_DW10_GRP_A 0x162C28
709 #define _PORT_PCS_DW10_GRP_B 0x6CC28
710 #define _PORT_PCS_DW10_GRP_C 0x6CE28
711 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
712 _PORT_PCS_DW10_LN01_B, \
713 _PORT_PCS_DW10_LN01_C)
714 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
715 _PORT_PCS_DW10_GRP_B, \
716 _PORT_PCS_DW10_GRP_C)
718 #define TX2_SWING_CALC_INIT (1 << 31)
719 #define TX1_SWING_CALC_INIT (1 << 30)
721 #define _PORT_PCS_DW12_LN01_A 0x162430
722 #define _PORT_PCS_DW12_LN01_B 0x6C430
723 #define _PORT_PCS_DW12_LN01_C 0x6C830
724 #define _PORT_PCS_DW12_LN23_A 0x162630
725 #define _PORT_PCS_DW12_LN23_B 0x6C630
726 #define _PORT_PCS_DW12_LN23_C 0x6CA30
727 #define _PORT_PCS_DW12_GRP_A 0x162c30
728 #define _PORT_PCS_DW12_GRP_B 0x6CC30
729 #define _PORT_PCS_DW12_GRP_C 0x6CE30
730 #define LANESTAGGER_STRAP_OVRD (1 << 6)
731 #define LANE_STAGGER_MASK 0x1F
732 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
733 _PORT_PCS_DW12_LN01_B, \
734 _PORT_PCS_DW12_LN01_C)
735 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
736 _PORT_PCS_DW12_LN23_B, \
737 _PORT_PCS_DW12_LN23_C)
738 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
739 _PORT_PCS_DW12_GRP_B, \
740 _PORT_PCS_DW12_GRP_C)
742 /* BXT PHY TX registers */
743 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
746 #define _PORT_TX_DW2_LN0_A 0x162508
747 #define _PORT_TX_DW2_LN0_B 0x6C508
748 #define _PORT_TX_DW2_LN0_C 0x6C908
749 #define _PORT_TX_DW2_GRP_A 0x162D08
750 #define _PORT_TX_DW2_GRP_B 0x6CD08
751 #define _PORT_TX_DW2_GRP_C 0x6CF08
752 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
753 _PORT_TX_DW2_LN0_B, \
755 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
756 _PORT_TX_DW2_GRP_B, \
758 #define MARGIN_000_SHIFT 16
759 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
760 #define UNIQ_TRANS_SCALE_SHIFT 8
761 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
763 #define _PORT_TX_DW3_LN0_A 0x16250C
764 #define _PORT_TX_DW3_LN0_B 0x6C50C
765 #define _PORT_TX_DW3_LN0_C 0x6C90C
766 #define _PORT_TX_DW3_GRP_A 0x162D0C
767 #define _PORT_TX_DW3_GRP_B 0x6CD0C
768 #define _PORT_TX_DW3_GRP_C 0x6CF0C
769 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
770 _PORT_TX_DW3_LN0_B, \
772 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
773 _PORT_TX_DW3_GRP_B, \
775 #define SCALE_DCOMP_METHOD (1 << 26)
776 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
778 #define _PORT_TX_DW4_LN0_A 0x162510
779 #define _PORT_TX_DW4_LN0_B 0x6C510
780 #define _PORT_TX_DW4_LN0_C 0x6C910
781 #define _PORT_TX_DW4_GRP_A 0x162D10
782 #define _PORT_TX_DW4_GRP_B 0x6CD10
783 #define _PORT_TX_DW4_GRP_C 0x6CF10
784 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
785 _PORT_TX_DW4_LN0_B, \
787 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
788 _PORT_TX_DW4_GRP_B, \
790 #define DEEMPH_SHIFT 24
791 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
793 #define _PORT_TX_DW5_LN0_A 0x162514
794 #define _PORT_TX_DW5_LN0_B 0x6C514
795 #define _PORT_TX_DW5_LN0_C 0x6C914
796 #define _PORT_TX_DW5_GRP_A 0x162D14
797 #define _PORT_TX_DW5_GRP_B 0x6CD14
798 #define _PORT_TX_DW5_GRP_C 0x6CF14
799 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
800 _PORT_TX_DW5_LN0_B, \
802 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
803 _PORT_TX_DW5_GRP_B, \
805 #define DCC_DELAY_RANGE_1 (1 << 9)
806 #define DCC_DELAY_RANGE_2 (1 << 8)
808 #define _PORT_TX_DW14_LN0_A 0x162538
809 #define _PORT_TX_DW14_LN0_B 0x6C538
810 #define _PORT_TX_DW14_LN0_C 0x6C938
811 #define LATENCY_OPTIM_SHIFT 30
812 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
813 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
814 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
815 _PORT_TX_DW14_LN0_C) + \
816 _BXT_LANE_OFFSET(lane))
818 /* UAIMI scratch pad register 1 */
819 #define UAIMI_SPR1 _MMIO(0x4F074)
821 #define SKL_VCCIO_MASK 0x1
822 /* SKL balance leg register */
823 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
825 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
826 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
827 /* Balance leg disable bits */
828 #define BALANCE_LEG_DISABLE_SHIFT 23
829 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
833 * [0-7] @ 0x2000 gen2,gen3
834 * [8-15] @ 0x3000 945,g33,pnv
836 * [0-15] @ 0x3000 gen4,gen5
838 * [0-15] @ 0x100000 gen6,vlv,chv
839 * [0-31] @ 0x100000 gen7+
841 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
842 #define I830_FENCE_START_MASK 0x07f80000
843 #define I830_FENCE_TILING_Y_SHIFT 12
844 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
845 #define I830_FENCE_PITCH_SHIFT 4
846 #define I830_FENCE_REG_VALID (1 << 0)
847 #define I915_FENCE_MAX_PITCH_VAL 4
848 #define I830_FENCE_MAX_PITCH_VAL 6
849 #define I830_FENCE_MAX_SIZE_VAL (1 << 8)
851 #define I915_FENCE_START_MASK 0x0ff00000
852 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
854 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
855 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
856 #define I965_FENCE_PITCH_SHIFT 2
857 #define I965_FENCE_TILING_Y_SHIFT 1
858 #define I965_FENCE_REG_VALID (1 << 0)
859 #define I965_FENCE_MAX_PITCH_VAL 0x0400
861 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
862 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
863 #define GEN6_FENCE_PITCH_SHIFT 32
864 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
867 /* control register for cpu gtt access */
868 #define TILECTL _MMIO(0x101000)
869 #define TILECTL_SWZCTL (1 << 0)
870 #define TILECTL_TLBPF (1 << 1)
871 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
872 #define TILECTL_BACKSNOOP_DIS (1 << 3)
875 * Instruction and interrupt control regs
877 #define PGTBL_CTL _MMIO(0x02020)
878 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
879 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
880 #define PGTBL_ER _MMIO(0x02024)
881 #define PRB0_BASE (0x2030 - 0x30)
882 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
883 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
884 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
885 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
886 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
887 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
888 #define RENDER_RING_BASE 0x02000
889 #define BSD_RING_BASE 0x04000
890 #define GEN6_BSD_RING_BASE 0x12000
891 #define GEN8_BSD2_RING_BASE 0x1c000
892 #define GEN11_BSD_RING_BASE 0x1c0000
893 #define GEN11_BSD2_RING_BASE 0x1c4000
894 #define GEN11_BSD3_RING_BASE 0x1d0000
895 #define GEN11_BSD4_RING_BASE 0x1d4000
896 #define XEHP_BSD5_RING_BASE 0x1e0000
897 #define XEHP_BSD6_RING_BASE 0x1e4000
898 #define XEHP_BSD7_RING_BASE 0x1f0000
899 #define XEHP_BSD8_RING_BASE 0x1f4000
900 #define VEBOX_RING_BASE 0x1a000
901 #define GEN11_VEBOX_RING_BASE 0x1c8000
902 #define GEN11_VEBOX2_RING_BASE 0x1d8000
903 #define XEHP_VEBOX3_RING_BASE 0x1e8000
904 #define XEHP_VEBOX4_RING_BASE 0x1f8000
905 #define MTL_GSC_RING_BASE 0x11a000
906 #define GEN12_COMPUTE0_RING_BASE 0x1a000
907 #define GEN12_COMPUTE1_RING_BASE 0x1c000
908 #define GEN12_COMPUTE2_RING_BASE 0x1e000
909 #define GEN12_COMPUTE3_RING_BASE 0x26000
910 #define BLT_RING_BASE 0x22000
911 #define XEHPC_BCS1_RING_BASE 0x3e0000
912 #define XEHPC_BCS2_RING_BASE 0x3e2000
913 #define XEHPC_BCS3_RING_BASE 0x3e4000
914 #define XEHPC_BCS4_RING_BASE 0x3e6000
915 #define XEHPC_BCS5_RING_BASE 0x3e8000
916 #define XEHPC_BCS6_RING_BASE 0x3ea000
917 #define XEHPC_BCS7_RING_BASE 0x3ec000
918 #define XEHPC_BCS8_RING_BASE 0x3ee000
919 #define DG1_GSC_HECI1_BASE 0x00258000
920 #define DG1_GSC_HECI2_BASE 0x00259000
921 #define DG2_GSC_HECI1_BASE 0x00373000
922 #define DG2_GSC_HECI2_BASE 0x00374000
926 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
927 #define GTT_CACHE_EN_ALL 0xF0007FFF
928 #define GEN7_WR_WATERMARK _MMIO(0x4028)
929 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
930 #define ARB_MODE _MMIO(0x4030)
931 #define ARB_MODE_SWIZZLE_SNB (1 << 4)
932 #define ARB_MODE_SWIZZLE_IVB (1 << 5)
933 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
934 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
935 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
936 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
937 #define GEN7_LRA_LIMITS_REG_NUM 13
938 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
939 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
941 #define GEN7_ERR_INT _MMIO(0x44040)
942 #define ERR_INT_POISON (1 << 31)
943 #define ERR_INT_MMIO_UNCLAIMED (1 << 13)
944 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
945 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
946 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
947 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
948 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
949 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
950 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
951 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
953 #define FPGA_DBG _MMIO(0x42300)
954 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
956 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
957 #define CLAIM_ER_CLR REG_BIT(31)
958 #define CLAIM_ER_OVERFLOW REG_BIT(16)
959 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
961 #define DERRMR _MMIO(0x44050)
962 /* Note that HBLANK events are reserved on bdw+ */
963 #define DERRMR_PIPEA_SCANLINE (1 << 0)
964 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
965 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
966 #define DERRMR_PIPEA_VBLANK (1 << 3)
967 #define DERRMR_PIPEA_HBLANK (1 << 5)
968 #define DERRMR_PIPEB_SCANLINE (1 << 8)
969 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
970 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
971 #define DERRMR_PIPEB_VBLANK (1 << 11)
972 #define DERRMR_PIPEB_HBLANK (1 << 13)
973 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
974 #define DERRMR_PIPEC_SCANLINE (1 << 14)
975 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
976 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
977 #define DERRMR_PIPEC_VBLANK (1 << 21)
978 #define DERRMR_PIPEC_HBLANK (1 << 22)
980 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
981 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
982 #define SCPD0 _MMIO(0x209c) /* 915+ only */
983 #define SCPD_FBC_IGNORE_3D (1 << 6)
984 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
985 #define GEN2_IER _MMIO(0x20a0)
986 #define GEN2_IIR _MMIO(0x20a4)
987 #define GEN2_IMR _MMIO(0x20a8)
988 #define GEN2_ISR _MMIO(0x20ac)
989 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
990 #define GINT_DIS (1 << 22)
991 #define GCFG_DIS (1 << 8)
992 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
993 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
994 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
995 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
996 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
997 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
998 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
999 #define VLV_PCBR_ADDR_SHIFT 12
1001 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
1002 #define EIR _MMIO(0x20b0)
1003 #define EMR _MMIO(0x20b4)
1004 #define ESR _MMIO(0x20b8)
1005 #define GM45_ERROR_PAGE_TABLE (1 << 5)
1006 #define GM45_ERROR_MEM_PRIV (1 << 4)
1007 #define I915_ERROR_PAGE_TABLE (1 << 4)
1008 #define GM45_ERROR_CP_PRIV (1 << 3)
1009 #define I915_ERROR_MEMORY_REFRESH (1 << 1)
1010 #define I915_ERROR_INSTRUCTION (1 << 0)
1011 #define INSTPM _MMIO(0x20c0)
1012 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */
1013 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
1014 will not assert AGPBUSY# and will only
1015 be delivered when out of C3. */
1016 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
1017 #define INSTPM_TLB_INVALIDATE (1 << 9)
1018 #define INSTPM_SYNC_FLUSH (1 << 5)
1019 #define MEM_MODE _MMIO(0x20cc)
1020 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
1021 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
1022 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
1023 #define FW_BLC _MMIO(0x20d8)
1024 #define FW_BLC2 _MMIO(0x20dc)
1025 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
1026 #define FW_BLC_SELF_EN_MASK (1 << 31)
1027 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
1028 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */
1029 #define MM_BURST_LENGTH 0x00700000
1030 #define MM_FIFO_WATERMARK 0x0001F000
1031 #define LM_BURST_LENGTH 0x00000700
1032 #define LM_FIFO_WATERMARK 0x0000001F
1033 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
1035 #define _MBUS_ABOX0_CTL 0x45038
1036 #define _MBUS_ABOX1_CTL 0x45048
1037 #define _MBUS_ABOX2_CTL 0x4504C
1038 #define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
1041 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
1042 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
1043 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
1044 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
1045 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
1046 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
1047 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
1048 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
1050 #define _PIPEA_MBUS_DBOX_CTL 0x7003C
1051 #define _PIPEB_MBUS_DBOX_CTL 0x7103C
1052 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
1053 _PIPEB_MBUS_DBOX_CTL)
1054 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */
1055 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)
1056 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */
1057 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)
1058 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
1059 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
1060 #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
1061 #define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)
1062 #define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)
1063 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
1064 #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
1065 #define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
1066 #define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)
1067 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
1068 #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
1070 #define MBUS_UBOX_CTL _MMIO(0x4503C)
1071 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
1072 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
1074 #define MBUS_CTL _MMIO(0x4438C)
1075 #define MBUS_JOIN REG_BIT(31)
1076 #define MBUS_HASHING_MODE_MASK REG_BIT(30)
1077 #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
1078 #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
1079 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
1080 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
1081 #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
1083 /* Make render/texture TLB fetches lower priorty than associated data
1084 * fetches. This is not turned on by default
1086 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1088 /* Isoch request wait on GTT enable (Display A/B/C streams).
1089 * Make isoch requests stall on the TLB update. May cause
1090 * display underruns (test mode only)
1092 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1094 /* Block grant count for isoch requests when block count is
1095 * set to a finite value.
1097 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1098 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1099 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1100 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1101 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1103 /* Enable render writes to complete in C2/C3/C4 power states.
1104 * If this isn't enabled, render writes are prevented in low
1105 * power states. That seems bad to me.
1107 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1109 /* This acknowledges an async flip immediately instead
1110 * of waiting for 2TLB fetches.
1112 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1114 /* Enables non-sequential data reads through arbiter
1116 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
1118 /* Disable FSB snooping of cacheable write cycles from binner/render
1121 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1123 /* Arbiter time slice for non-isoch streams */
1124 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
1125 #define MI_ARB_TIME_SLICE_1 (0 << 5)
1126 #define MI_ARB_TIME_SLICE_2 (1 << 5)
1127 #define MI_ARB_TIME_SLICE_4 (2 << 5)
1128 #define MI_ARB_TIME_SLICE_6 (3 << 5)
1129 #define MI_ARB_TIME_SLICE_8 (4 << 5)
1130 #define MI_ARB_TIME_SLICE_10 (5 << 5)
1131 #define MI_ARB_TIME_SLICE_14 (6 << 5)
1132 #define MI_ARB_TIME_SLICE_16 (7 << 5)
1134 /* Low priority grace period page size */
1135 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1136 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1138 /* Disable display A/B trickle feed */
1139 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1141 /* Set display plane priority */
1142 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1143 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1145 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
1146 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1147 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1149 /* On modern GEN architectures interrupt control consists of two sets
1150 * of registers. The first set pertains to the ring generating the
1151 * interrupt. The second control is for the functional block generating the
1152 * interrupt. These are PM, GT, DE, etc.
1154 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1155 * GT interrupt bits, so we don't need to duplicate the defines.
1157 * These defines should cover us well from SNB->HSW with minor exceptions
1158 * it can also work on ILK.
1160 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1161 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1162 #define GT_BLT_USER_INTERRUPT (1 << 22)
1163 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1164 #define GT_BSD_USER_INTERRUPT (1 << 12)
1165 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1166 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
1167 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
1168 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1169 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1170 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
1171 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1172 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1173 #define GT_RENDER_USER_INTERRUPT (1 << 0)
1175 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1176 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1178 #define GT_PARITY_ERROR(dev_priv) \
1179 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1180 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1182 /* These are all the "old" interrupts */
1183 #define ILK_BSD_USER_INTERRUPT (1 << 5)
1185 #define I915_PM_INTERRUPT (1 << 31)
1186 #define I915_ISP_INTERRUPT (1 << 22)
1187 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
1188 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
1189 #define I915_MIPIC_INTERRUPT (1 << 19)
1190 #define I915_MIPIA_INTERRUPT (1 << 18)
1191 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
1192 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
1193 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
1194 #define I915_MASTER_ERROR_INTERRUPT (1 << 15)
1195 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
1196 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
1197 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
1198 #define I915_HWB_OOM_INTERRUPT (1 << 13)
1199 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
1200 #define I915_SYNC_STATUS_INTERRUPT (1 << 12)
1201 #define I915_MISC_INTERRUPT (1 << 11)
1202 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
1203 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
1204 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
1205 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
1206 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
1207 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
1208 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
1209 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
1210 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
1211 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
1212 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
1213 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
1214 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
1215 #define I915_DEBUG_INTERRUPT (1 << 2)
1216 #define I915_WINVALID_INTERRUPT (1 << 1)
1217 #define I915_USER_INTERRUPT (1 << 1)
1218 #define I915_ASLE_INTERRUPT (1 << 0)
1219 #define I915_BSD_USER_INTERRUPT (1 << 25)
1221 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
1222 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000
1224 /* DisplayPort Audio w/ LPE */
1225 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
1226 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
1228 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
1229 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
1230 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
1231 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
1232 _VLV_AUD_PORT_EN_B_DBG, \
1233 _VLV_AUD_PORT_EN_C_DBG, \
1234 _VLV_AUD_PORT_EN_D_DBG)
1235 #define VLV_AMP_MUTE (1 << 1)
1237 #define GEN6_BSD_RNCID _MMIO(0x12198)
1239 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
1240 #define GEN7_FF_SCHED_MASK 0x0077070
1241 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
1242 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
1243 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
1244 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
1245 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
1246 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
1247 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
1248 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
1249 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
1250 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
1251 #define GEN7_FF_VS_SCHED_HW (0x0 << 12)
1252 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
1253 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
1254 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
1255 #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
1258 * Framebuffer compression (915+ only)
1261 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
1262 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
1263 #define FBC_CONTROL _MMIO(0x3208)
1264 #define FBC_CTL_EN REG_BIT(31)
1265 #define FBC_CTL_PERIODIC REG_BIT(30)
1266 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
1267 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
1268 #define FBC_CTL_STOP_ON_MOD REG_BIT(15)
1269 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
1270 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
1271 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
1272 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
1273 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
1274 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
1275 #define FBC_COMMAND _MMIO(0x320c)
1276 #define FBC_CMD_COMPRESS REG_BIT(0)
1277 #define FBC_STATUS _MMIO(0x3210)
1278 #define FBC_STAT_COMPRESSING REG_BIT(31)
1279 #define FBC_STAT_COMPRESSED REG_BIT(30)
1280 #define FBC_STAT_MODIFIED REG_BIT(29)
1281 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
1282 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
1283 #define FBC_CTL_FENCE_DBL REG_BIT(4)
1284 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
1285 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
1286 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
1287 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
1288 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
1289 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
1290 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
1291 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
1292 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
1293 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
1294 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
1295 #define FBC_MOD_NUM_VALID REG_BIT(0)
1296 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
1297 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
1298 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
1299 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
1300 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
1301 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
1303 #define FBC_LL_SIZE (1536)
1305 /* Framebuffer compression for GM45+ */
1306 #define DPFC_CB_BASE _MMIO(0x3200)
1307 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
1308 #define DPFC_CONTROL _MMIO(0x3208)
1309 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
1310 #define DPFC_CTL_EN REG_BIT(31)
1311 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
1312 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
1313 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
1314 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
1315 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
1316 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
1317 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
1318 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
1319 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
1320 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
1321 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
1322 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
1323 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
1324 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
1325 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
1326 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
1327 #define DPFC_RECOMP_CTL _MMIO(0x320c)
1328 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
1329 #define DPFC_RECOMP_STALL_EN REG_BIT(27)
1330 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
1331 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
1332 #define DPFC_STATUS _MMIO(0x3210)
1333 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
1334 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
1335 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
1336 #define DPFC_STATUS2 _MMIO(0x3214)
1337 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
1338 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
1339 #define DPFC_FENCE_YOFF _MMIO(0x3218)
1340 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
1341 #define DPFC_CHICKEN _MMIO(0x3224)
1342 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
1343 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
1344 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
1345 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
1346 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
1347 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
1349 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
1350 #define FBC_STRIDE_OVERRIDE REG_BIT(15)
1351 #define FBC_STRIDE_MASK REG_GENMASK(14, 0)
1352 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
1354 #define ILK_FBC_RT_BASE _MMIO(0x2128)
1355 #define ILK_FBC_RT_VALID REG_BIT(0)
1356 #define SNB_FBC_FRONT_BUFFER REG_BIT(1)
1358 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
1359 #define ILK_FBCQ_DIS (1 << 22)
1360 #define ILK_PABSTRETCH_DIS REG_BIT(21)
1361 #define ILK_SABSTRETCH_DIS REG_BIT(20)
1362 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
1363 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
1364 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
1365 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
1366 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
1367 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
1368 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
1369 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
1370 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
1371 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
1375 * Framebuffer compression for Sandybridge
1377 * The following two registers are of type GTTMMADR
1379 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
1380 #define SNB_DPFC_FENCE_EN REG_BIT(29)
1381 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
1382 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
1383 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
1385 /* Framebuffer compression for Ivybridge */
1386 #define IVB_FBC_RT_BASE _MMIO(0x7020)
1387 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
1389 #define IPS_CTL _MMIO(0x43408)
1390 #define IPS_ENABLE (1 << 31)
1392 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
1393 #define FBC_REND_NUKE REG_BIT(2)
1394 #define FBC_REND_CACHE_CLEAN REG_BIT(1)
1397 * Clock control & power management
1399 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
1400 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
1401 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
1402 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
1404 #define VGA0 _MMIO(0x6000)
1405 #define VGA1 _MMIO(0x6004)
1406 #define VGA_PD _MMIO(0x6010)
1407 #define VGA0_PD_P2_DIV_4 (1 << 7)
1408 #define VGA0_PD_P1_DIV_2 (1 << 5)
1409 #define VGA0_PD_P1_SHIFT 0
1410 #define VGA0_PD_P1_MASK (0x1f << 0)
1411 #define VGA1_PD_P2_DIV_4 (1 << 15)
1412 #define VGA1_PD_P1_DIV_2 (1 << 13)
1413 #define VGA1_PD_P1_SHIFT 8
1414 #define VGA1_PD_P1_MASK (0x1f << 8)
1415 #define DPLL_VCO_ENABLE (1 << 31)
1416 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
1417 #define DPLL_DVO_2X_MODE (1 << 30)
1418 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
1419 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
1420 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
1421 #define DPLL_VGA_MODE_DIS (1 << 28)
1422 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1423 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1424 #define DPLL_MODE_MASK (3 << 26)
1425 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1426 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1427 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1428 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1429 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1430 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1431 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
1432 #define DPLL_LOCK_VLV (1 << 15)
1433 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
1434 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
1435 #define DPLL_SSC_REF_CLK_CHV (1 << 13)
1436 #define DPLL_PORTC_READY_MASK (0xf << 4)
1437 #define DPLL_PORTB_READY_MASK (0xf)
1439 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1441 /* Additional CHV pll/phy registers */
1442 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
1443 #define DPLL_PORTD_READY_MASK (0xf)
1444 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
1445 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
1446 #define PHY_LDO_DELAY_0NS 0x0
1447 #define PHY_LDO_DELAY_200NS 0x1
1448 #define PHY_LDO_DELAY_600NS 0x2
1449 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
1450 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
1451 #define PHY_CH_SU_PSR 0x1
1452 #define PHY_CH_DEEP_PSR 0x7
1453 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
1454 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
1455 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
1456 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
1457 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
1458 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
1461 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1462 * this field (only one bit may be set).
1464 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1465 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1466 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1467 /* i830, required in DVO non-gang */
1468 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
1469 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1470 #define PLL_REF_INPUT_DREFCLK (0 << 13)
1471 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1472 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1473 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1474 #define PLL_REF_INPUT_MASK (3 << 13)
1475 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
1477 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1478 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1479 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
1480 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1481 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1484 * Parallel to Serial Load Pulse phase selection.
1485 * Selects the phase for the 10X DPLL clock for the PCIe
1486 * digital display port. The range is 4 to 13; 10 or more
1487 * is just a flip delay. The default is 6
1489 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1490 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1492 * SDVO multiplier for 945G/GM. Not used on 965.
1494 #define SDVO_MULTIPLIER_MASK 0x000000ff
1495 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
1496 #define SDVO_MULTIPLIER_SHIFT_VGA 0
1498 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
1499 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
1500 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
1501 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
1504 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1506 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1508 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1509 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
1510 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1511 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1512 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1514 * SDVO/UDI pixel multiplier.
1516 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1517 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1518 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1519 * dummy bytes in the datastream at an increased clock rate, with both sides of
1520 * the link knowing how many bytes are fill.
1522 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1523 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1524 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1525 * through an SDVO command.
1527 * This register field has values of multiplication factor minus 1, with
1528 * a maximum multiplier of 5 for SDVO.
1530 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1531 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1533 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1534 * This best be set to the default value (3) or the CRT won't work. No,
1535 * I don't entirely understand what this does...
1537 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1538 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1540 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
1542 #define _FPA0 0x6040
1543 #define _FPA1 0x6044
1544 #define _FPB0 0x6048
1545 #define _FPB1 0x604c
1546 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
1547 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
1548 #define FP_N_DIV_MASK 0x003f0000
1549 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1550 #define FP_N_DIV_SHIFT 16
1551 #define FP_M1_DIV_MASK 0x00003f00
1552 #define FP_M1_DIV_SHIFT 8
1553 #define FP_M2_DIV_MASK 0x0000003f
1554 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1555 #define FP_M2_DIV_SHIFT 0
1556 #define DPLL_TEST _MMIO(0x606c)
1557 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1558 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1559 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1560 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1561 #define DPLLB_TEST_N_BYPASS (1 << 19)
1562 #define DPLLB_TEST_M_BYPASS (1 << 18)
1563 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1564 #define DPLLA_TEST_N_BYPASS (1 << 3)
1565 #define DPLLA_TEST_M_BYPASS (1 << 2)
1566 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1567 #define D_STATE _MMIO(0x6104)
1568 #define DSTATE_GFX_RESET_I830 (1 << 6)
1569 #define DSTATE_PLL_D3_OFF (1 << 3)
1570 #define DSTATE_GFX_CLOCK_GATING (1 << 1)
1571 #define DSTATE_DOT_CLOCK_GATING (1 << 0)
1572 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
1573 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1574 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1575 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1576 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1577 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1578 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1579 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1580 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
1581 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1582 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1583 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1584 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1585 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1586 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1587 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1588 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1589 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1590 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1591 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1592 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1593 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1594 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1595 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1596 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1597 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1598 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1599 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1600 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1601 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1603 * This bit must be set on the 830 to prevent hangs when turning off the
1606 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1607 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1608 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1609 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1610 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1612 #define RENCLK_GATE_D1 _MMIO(0x6204)
1613 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1614 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1615 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1616 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1617 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1618 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1619 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1620 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1621 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1622 /* This bit must be unset on 855,865 */
1623 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1624 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1625 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1626 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1627 /* This bit must be set on 855,865. */
1628 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1629 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1630 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1631 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1632 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1633 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1634 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1635 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1636 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1637 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1638 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1639 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1640 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1641 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1642 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1643 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1644 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1645 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1647 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1648 /* This bit must always be set on 965G/965GM */
1649 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1650 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1651 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1652 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1653 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1654 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1655 /* This bit must always be set on 965G */
1656 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1657 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1658 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1659 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1660 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1661 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1662 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1663 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1664 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1665 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1666 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1667 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1668 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1669 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1670 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1671 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1672 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1673 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1674 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1676 #define RENCLK_GATE_D2 _MMIO(0x6208)
1677 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1678 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1679 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1681 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
1682 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
1684 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
1685 #define DEUC _MMIO(0x6214) /* CRL only */
1687 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
1688 #define FW_CSPWRDWNEN (1 << 15)
1690 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
1692 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
1693 #define CDCLK_FREQ_SHIFT 4
1694 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1695 #define CZCLK_FREQ_MASK 0xf
1697 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
1698 #define PFI_CREDIT_63 (9 << 28) /* chv only */
1699 #define PFI_CREDIT_31 (8 << 28) /* chv only */
1700 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
1701 #define PFI_CREDIT_RESEND (1 << 27)
1702 #define VGA_FAST_MODE_DISABLE (1 << 14)
1704 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
1709 #define _PALETTE_A 0xa000
1710 #define _PALETTE_B 0xa800
1711 #define _CHV_PALETTE_C 0xc000
1712 /* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
1713 #define PALETTE_RED_MASK REG_GENMASK(23, 16)
1714 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
1715 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
1716 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
1717 _PICK((pipe), _PALETTE_A, \
1718 _PALETTE_B, _CHV_PALETTE_C) + \
1721 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
1723 #define BXT_RP_STATE_CAP _MMIO(0x138170)
1724 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
1725 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
1726 #define PVC_RP_STATE_CAP _MMIO(0x281014)
1728 #define MTL_RP_STATE_CAP _MMIO(0x138000)
1729 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
1730 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
1731 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
1733 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
1734 #define MTL_MPE_FREQUENCY _MMIO(0x13802c)
1735 #define MTL_RPE_MASK REG_GENMASK(8, 0)
1737 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
1738 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3
1739 #define PROCHOT_MASK REG_BIT(0)
1740 #define THERMAL_LIMIT_MASK REG_BIT(1)
1741 #define RATL_MASK REG_BIT(5)
1742 #define VR_THERMALERT_MASK REG_BIT(6)
1743 #define VR_TDC_MASK REG_BIT(7)
1744 #define POWER_LIMIT_4_MASK REG_BIT(8)
1745 #define POWER_LIMIT_1_MASK REG_BIT(10)
1746 #define POWER_LIMIT_2_MASK REG_BIT(11)
1747 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
1748 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
1750 #define CHV_CLK_CTL1 _MMIO(0x101100)
1751 #define VLV_CLK_CTL2 _MMIO(0x101104)
1752 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1758 #define OVADD _MMIO(0x30000)
1759 #define DOVSTA _MMIO(0x30008)
1760 #define OC_BUF (0x3 << 20)
1761 #define OGAMC5 _MMIO(0x30010)
1762 #define OGAMC4 _MMIO(0x30014)
1763 #define OGAMC3 _MMIO(0x30018)
1764 #define OGAMC2 _MMIO(0x3001c)
1765 #define OGAMC1 _MMIO(0x30020)
1766 #define OGAMC0 _MMIO(0x30024)
1769 * GEN9 clock gating regs
1771 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
1772 #define DARBF_GATING_DIS (1 << 27)
1773 #define PWM2_GATING_DIS (1 << 14)
1774 #define PWM1_GATING_DIS (1 << 13)
1776 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
1777 #define TGL_VRH_GATING_DIS REG_BIT(31)
1778 #define DPT_GATING_DIS REG_BIT(22)
1780 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
1781 #define BXT_GMBUS_GATING_DIS (1 << 14)
1783 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
1784 #define DPCE_GATING_DIS REG_BIT(17)
1786 #define _CLKGATE_DIS_PSL_A 0x46520
1787 #define _CLKGATE_DIS_PSL_B 0x46524
1788 #define _CLKGATE_DIS_PSL_C 0x46528
1789 #define DUPS1_GATING_DIS (1 << 15)
1790 #define DUPS2_GATING_DIS (1 << 19)
1791 #define DUPS3_GATING_DIS (1 << 23)
1792 #define CURSOR_GATING_DIS REG_BIT(28)
1793 #define DPF_GATING_DIS (1 << 10)
1794 #define DPF_RAM_GATING_DIS (1 << 9)
1795 #define DPFR_GATING_DIS (1 << 8)
1797 #define CLKGATE_DIS_PSL(pipe) \
1798 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
1800 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C
1801 #define _CLKGATE_DIS_PSL_EXT_B 0x46550
1802 #define PIPEDMC_GATING_DIS REG_BIT(12)
1804 #define CLKGATE_DIS_PSL_EXT(pipe) \
1805 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
1808 * Display engine regs
1811 /* Pipe A CRC regs */
1812 #define _PIPE_CRC_CTL_A 0x60050
1813 #define PIPE_CRC_ENABLE REG_BIT(31)
1814 /* skl+ source selection */
1815 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28)
1816 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
1817 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
1818 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
1819 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
1820 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
1821 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
1822 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
1823 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
1824 /* ivb+ source selection */
1825 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29)
1826 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
1827 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
1828 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
1829 /* ilk+ source selection */
1830 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28)
1831 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
1832 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
1833 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
1834 /* embedded DP port on the north display block */
1835 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
1836 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
1837 /* vlv source selection */
1838 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27)
1839 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
1840 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
1841 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
1842 /* with DP port the pipe source is invalid */
1843 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
1844 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
1845 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
1846 /* gen3+ source selection */
1847 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28)
1848 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
1849 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
1850 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
1851 /* with DP/TV port the pipe source is invalid */
1852 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
1853 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
1854 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
1855 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
1856 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
1857 /* gen2 doesn't have source selection bits */
1858 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
1860 #define _PIPE_CRC_RES_1_A_IVB 0x60064
1861 #define _PIPE_CRC_RES_2_A_IVB 0x60068
1862 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
1863 #define _PIPE_CRC_RES_4_A_IVB 0x60070
1864 #define _PIPE_CRC_RES_5_A_IVB 0x60074
1866 #define _PIPE_CRC_RES_RED_A 0x60060
1867 #define _PIPE_CRC_RES_GREEN_A 0x60064
1868 #define _PIPE_CRC_RES_BLUE_A 0x60068
1869 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
1870 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
1872 /* Pipe B CRC regs */
1873 #define _PIPE_CRC_RES_1_B_IVB 0x61064
1874 #define _PIPE_CRC_RES_2_B_IVB 0x61068
1875 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
1876 #define _PIPE_CRC_RES_4_B_IVB 0x61070
1877 #define _PIPE_CRC_RES_5_B_IVB 0x61074
1879 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
1880 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
1881 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
1882 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
1883 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
1884 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
1886 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
1887 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
1888 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
1889 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
1890 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
1892 /* Pipe A timing regs */
1893 #define _HTOTAL_A 0x60000
1894 #define _HBLANK_A 0x60004
1895 #define _HSYNC_A 0x60008
1896 #define _VTOTAL_A 0x6000c
1897 #define _VBLANK_A 0x60010
1898 #define _VSYNC_A 0x60014
1899 #define _EXITLINE_A 0x60018
1900 #define _PIPEASRC 0x6001c
1901 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
1902 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
1903 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
1904 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
1905 #define _BCLRPAT_A 0x60020
1906 #define _VSYNCSHIFT_A 0x60028
1907 #define _PIPE_MULT_A 0x6002c
1909 /* Pipe B timing regs */
1910 #define _HTOTAL_B 0x61000
1911 #define _HBLANK_B 0x61004
1912 #define _HSYNC_B 0x61008
1913 #define _VTOTAL_B 0x6100c
1914 #define _VBLANK_B 0x61010
1915 #define _VSYNC_B 0x61014
1916 #define _PIPEBSRC 0x6101c
1917 #define _BCLRPAT_B 0x61020
1918 #define _VSYNCSHIFT_B 0x61028
1919 #define _PIPE_MULT_B 0x6102c
1921 /* DSI 0 timing regs */
1922 #define _HTOTAL_DSI0 0x6b000
1923 #define _HSYNC_DSI0 0x6b008
1924 #define _VTOTAL_DSI0 0x6b00c
1925 #define _VSYNC_DSI0 0x6b014
1926 #define _VSYNCSHIFT_DSI0 0x6b028
1928 /* DSI 1 timing regs */
1929 #define _HTOTAL_DSI1 0x6b800
1930 #define _HSYNC_DSI1 0x6b808
1931 #define _VTOTAL_DSI1 0x6b80c
1932 #define _VSYNC_DSI1 0x6b814
1933 #define _VSYNCSHIFT_DSI1 0x6b828
1935 #define TRANSCODER_A_OFFSET 0x60000
1936 #define TRANSCODER_B_OFFSET 0x61000
1937 #define TRANSCODER_C_OFFSET 0x62000
1938 #define CHV_TRANSCODER_C_OFFSET 0x63000
1939 #define TRANSCODER_D_OFFSET 0x63000
1940 #define TRANSCODER_EDP_OFFSET 0x6f000
1941 #define TRANSCODER_DSI0_OFFSET 0x6b000
1942 #define TRANSCODER_DSI1_OFFSET 0x6b800
1944 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
1945 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
1946 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
1947 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
1948 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
1949 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
1950 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
1951 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
1952 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
1953 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
1955 #define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
1956 #define EXITLINE_ENABLE REG_BIT(31)
1957 #define EXITLINE_MASK REG_GENMASK(12, 0)
1958 #define EXITLINE_SHIFT 0
1961 #define _TRANS_VRR_CTL_A 0x60420
1962 #define _TRANS_VRR_CTL_B 0x61420
1963 #define _TRANS_VRR_CTL_C 0x62420
1964 #define _TRANS_VRR_CTL_D 0x63420
1965 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
1966 #define VRR_CTL_VRR_ENABLE REG_BIT(31)
1967 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
1968 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
1969 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
1970 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
1971 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
1972 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
1973 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
1975 #define _TRANS_VRR_VMAX_A 0x60424
1976 #define _TRANS_VRR_VMAX_B 0x61424
1977 #define _TRANS_VRR_VMAX_C 0x62424
1978 #define _TRANS_VRR_VMAX_D 0x63424
1979 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
1980 #define VRR_VMAX_MASK REG_GENMASK(19, 0)
1982 #define _TRANS_VRR_VMIN_A 0x60434
1983 #define _TRANS_VRR_VMIN_B 0x61434
1984 #define _TRANS_VRR_VMIN_C 0x62434
1985 #define _TRANS_VRR_VMIN_D 0x63434
1986 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
1987 #define VRR_VMIN_MASK REG_GENMASK(15, 0)
1989 #define _TRANS_VRR_VMAXSHIFT_A 0x60428
1990 #define _TRANS_VRR_VMAXSHIFT_B 0x61428
1991 #define _TRANS_VRR_VMAXSHIFT_C 0x62428
1992 #define _TRANS_VRR_VMAXSHIFT_D 0x63428
1993 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \
1994 _TRANS_VRR_VMAXSHIFT_A)
1995 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
1996 #define VRR_VMAXSHIFT_DEC REG_BIT(16)
1997 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
1999 #define _TRANS_VRR_STATUS_A 0x6042C
2000 #define _TRANS_VRR_STATUS_B 0x6142C
2001 #define _TRANS_VRR_STATUS_C 0x6242C
2002 #define _TRANS_VRR_STATUS_D 0x6342C
2003 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
2004 #define VRR_STATUS_VMAX_REACHED REG_BIT(31)
2005 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
2006 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
2007 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
2008 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
2009 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
2010 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
2011 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
2012 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
2013 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
2014 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
2015 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
2016 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
2017 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
2019 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480
2020 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480
2021 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480
2022 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480
2023 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \
2024 _TRANS_VRR_VTOTAL_PREV_A)
2025 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
2026 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
2027 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
2028 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
2030 #define _TRANS_VRR_FLIPLINE_A 0x60438
2031 #define _TRANS_VRR_FLIPLINE_B 0x61438
2032 #define _TRANS_VRR_FLIPLINE_C 0x62438
2033 #define _TRANS_VRR_FLIPLINE_D 0x63438
2034 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \
2035 _TRANS_VRR_FLIPLINE_A)
2036 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
2038 #define _TRANS_VRR_STATUS2_A 0x6043C
2039 #define _TRANS_VRR_STATUS2_B 0x6143C
2040 #define _TRANS_VRR_STATUS2_C 0x6243C
2041 #define _TRANS_VRR_STATUS2_D 0x6343C
2042 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
2043 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
2045 #define _TRANS_PUSH_A 0x60A70
2046 #define _TRANS_PUSH_B 0x61A70
2047 #define _TRANS_PUSH_C 0x62A70
2048 #define _TRANS_PUSH_D 0x63A70
2049 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A)
2050 #define TRANS_PUSH_EN REG_BIT(31)
2051 #define TRANS_PUSH_SEND REG_BIT(30)
2054 * HSW+ eDP PSR registers
2056 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
2059 #define _SRD_CTL_A 0x60800
2060 #define _SRD_CTL_EDP 0x6f800
2061 #define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A)
2062 #define EDP_PSR_ENABLE (1 << 31)
2063 #define BDW_PSR_SINGLE_FRAME (1 << 30)
2064 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
2065 #define EDP_PSR_LINK_STANDBY (1 << 27)
2066 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
2067 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
2068 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
2069 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
2070 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
2071 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
2072 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
2073 #define EDP_PSR_TP1_TP2_SEL (0 << 11)
2074 #define EDP_PSR_TP1_TP3_SEL (1 << 11)
2075 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */
2076 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
2077 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
2078 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
2079 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
2080 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */
2081 #define EDP_PSR_TP1_TIME_500us (0 << 4)
2082 #define EDP_PSR_TP1_TIME_100us (1 << 4)
2083 #define EDP_PSR_TP1_TIME_2500us (2 << 4)
2084 #define EDP_PSR_TP1_TIME_0us (3 << 4)
2085 #define EDP_PSR_IDLE_FRAME_SHIFT 0
2088 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
2089 * to transcoder and bits defined for each one as if using no shift (i.e. as if
2090 * it was for TRANSCODER_EDP)
2092 #define EDP_PSR_IMR _MMIO(0x64834)
2093 #define EDP_PSR_IIR _MMIO(0x64838)
2094 #define _PSR_IMR_A 0x60814
2095 #define _PSR_IIR_A 0x60818
2096 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A)
2097 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
2098 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
2099 0 : ((trans) - TRANSCODER_A + 1) * 8)
2100 #define TGL_PSR_MASK REG_GENMASK(2, 0)
2101 #define TGL_PSR_ERROR REG_BIT(2)
2102 #define TGL_PSR_POST_EXIT REG_BIT(1)
2103 #define TGL_PSR_PRE_ENTRY REG_BIT(0)
2104 #define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \
2105 _EDP_PSR_TRANS_SHIFT(trans))
2106 #define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \
2107 _EDP_PSR_TRANS_SHIFT(trans))
2108 #define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \
2109 _EDP_PSR_TRANS_SHIFT(trans))
2110 #define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \
2111 _EDP_PSR_TRANS_SHIFT(trans))
2113 #define _SRD_AUX_DATA_A 0x60814
2114 #define _SRD_AUX_DATA_EDP 0x6f814
2115 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */
2117 #define _SRD_STATUS_A 0x60840
2118 #define _SRD_STATUS_EDP 0x6f840
2119 #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A)
2120 #define EDP_PSR_STATUS_STATE_MASK (7 << 29)
2121 #define EDP_PSR_STATUS_STATE_SHIFT 29
2122 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
2123 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
2124 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
2125 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
2126 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
2127 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
2128 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
2129 #define EDP_PSR_STATUS_LINK_MASK (3 << 26)
2130 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
2131 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
2132 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
2133 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2134 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2135 #define EDP_PSR_STATUS_COUNT_SHIFT 16
2136 #define EDP_PSR_STATUS_COUNT_MASK 0xf
2137 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
2138 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
2139 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
2140 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
2141 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
2142 #define EDP_PSR_STATUS_IDLE_MASK 0xf
2144 #define _SRD_PERF_CNT_A 0x60844
2145 #define _SRD_PERF_CNT_EDP 0x6f844
2146 #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A)
2147 #define EDP_PSR_PERF_CNT_MASK 0xffffff
2149 /* PSR_MASK on SKL+ */
2150 #define _SRD_DEBUG_A 0x60860
2151 #define _SRD_DEBUG_EDP 0x6f860
2152 #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A)
2153 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
2154 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
2155 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
2156 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
2157 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
2158 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
2160 #define _PSR2_CTL_A 0x60900
2161 #define _PSR2_CTL_EDP 0x6f900
2162 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
2163 #define EDP_PSR2_ENABLE (1 << 31)
2164 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
2165 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
2166 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
2167 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
2168 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */
2169 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
2170 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
2171 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8
2172 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
2173 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13)
2174 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
2175 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13
2176 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
2177 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13)
2178 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8
2179 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
2180 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11)
2181 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5
2182 #define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10
2183 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
2184 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10)
2185 #define EDP_PSR2_TP2_TIME_500us (0 << 8)
2186 #define EDP_PSR2_TP2_TIME_100us (1 << 8)
2187 #define EDP_PSR2_TP2_TIME_2500us (2 << 8)
2188 #define EDP_PSR2_TP2_TIME_50us (3 << 8)
2189 #define EDP_PSR2_TP2_TIME_MASK (3 << 8)
2190 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
2191 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
2192 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
2193 #define EDP_PSR2_IDLE_FRAME_MASK 0xf
2194 #define EDP_PSR2_IDLE_FRAME_SHIFT 0
2196 #define _PSR_EVENT_TRANS_A 0x60848
2197 #define _PSR_EVENT_TRANS_B 0x61848
2198 #define _PSR_EVENT_TRANS_C 0x62848
2199 #define _PSR_EVENT_TRANS_D 0x63848
2200 #define _PSR_EVENT_TRANS_EDP 0x6f848
2201 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
2202 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
2203 #define PSR_EVENT_PSR2_DISABLED (1 << 16)
2204 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
2205 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
2206 #define PSR_EVENT_GRAPHICS_RESET (1 << 12)
2207 #define PSR_EVENT_PCH_INTERRUPT (1 << 11)
2208 #define PSR_EVENT_MEMORY_UP (1 << 10)
2209 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
2210 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
2211 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
2212 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
2213 #define PSR_EVENT_HDCP_ENABLE (1 << 4)
2214 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
2215 #define PSR_EVENT_VBI_ENABLE (1 << 2)
2216 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
2217 #define PSR_EVENT_PSR_DISABLE (1 << 0)
2219 #define _PSR2_STATUS_A 0x60940
2220 #define _PSR2_STATUS_EDP 0x6f940
2221 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
2222 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
2223 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
2225 #define _PSR2_SU_STATUS_A 0x60914
2226 #define _PSR2_SU_STATUS_EDP 0x6f914
2227 #define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4)
2228 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
2229 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
2230 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
2231 #define PSR2_SU_STATUS_FRAMES 8
2233 #define _PSR2_MAN_TRK_CTL_A 0x60910
2234 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910
2235 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
2236 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
2237 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
2238 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
2239 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
2240 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
2241 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
2242 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
2243 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
2244 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
2245 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
2246 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
2247 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
2248 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
2249 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
2250 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
2252 /* Icelake DSC Rate Control Range Parameter Registers */
2253 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
2254 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
2255 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
2256 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
2257 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
2258 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
2259 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
2260 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
2261 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
2262 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
2263 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
2264 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
2265 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2266 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
2267 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
2268 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2269 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
2270 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
2271 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2272 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
2273 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
2274 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2275 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
2276 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
2277 #define RC_BPG_OFFSET_SHIFT 10
2278 #define RC_MAX_QP_SHIFT 5
2279 #define RC_MIN_QP_SHIFT 0
2281 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
2282 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
2283 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
2284 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
2285 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
2286 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
2287 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
2288 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
2289 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
2290 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
2291 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
2292 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
2293 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2294 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
2295 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
2296 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2297 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
2298 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
2299 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2300 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
2301 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
2302 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2303 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
2304 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
2306 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
2307 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
2308 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
2309 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
2310 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
2311 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
2312 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
2313 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
2314 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
2315 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
2316 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
2317 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
2318 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2319 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
2320 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
2321 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2322 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
2323 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
2324 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2325 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
2326 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
2327 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2328 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
2329 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
2331 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
2332 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
2333 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
2334 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
2335 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
2336 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
2337 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
2338 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
2339 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
2340 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
2341 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
2342 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
2343 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2344 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
2345 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
2346 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2347 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
2348 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
2349 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2350 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
2351 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
2352 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2353 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
2354 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
2356 /* VGA port control */
2357 #define ADPA _MMIO(0x61100)
2358 #define PCH_ADPA _MMIO(0xe1100)
2359 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
2361 #define ADPA_DAC_ENABLE (1 << 31)
2362 #define ADPA_DAC_DISABLE 0
2363 #define ADPA_PIPE_SEL_SHIFT 30
2364 #define ADPA_PIPE_SEL_MASK (1 << 30)
2365 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
2366 #define ADPA_PIPE_SEL_SHIFT_CPT 29
2367 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
2368 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2369 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2370 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
2371 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
2372 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
2373 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
2374 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
2375 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
2376 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
2377 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
2378 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
2379 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
2380 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
2381 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
2382 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
2383 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
2384 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
2385 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
2386 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
2387 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
2388 #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
2389 #define ADPA_SETS_HVPOLARITY 0
2390 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
2391 #define ADPA_VSYNC_CNTL_ENABLE 0
2392 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
2393 #define ADPA_HSYNC_CNTL_ENABLE 0
2394 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
2395 #define ADPA_VSYNC_ACTIVE_LOW 0
2396 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
2397 #define ADPA_HSYNC_ACTIVE_LOW 0
2398 #define ADPA_DPMS_MASK (~(3 << 10))
2399 #define ADPA_DPMS_ON (0 << 10)
2400 #define ADPA_DPMS_SUSPEND (1 << 10)
2401 #define ADPA_DPMS_STANDBY (2 << 10)
2402 #define ADPA_DPMS_OFF (3 << 10)
2405 /* Hotplug control (945+ only) */
2406 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
2407 #define PORTB_HOTPLUG_INT_EN (1 << 29)
2408 #define PORTC_HOTPLUG_INT_EN (1 << 28)
2409 #define PORTD_HOTPLUG_INT_EN (1 << 27)
2410 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
2411 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
2412 #define TV_HOTPLUG_INT_EN (1 << 18)
2413 #define CRT_HOTPLUG_INT_EN (1 << 9)
2414 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2415 PORTC_HOTPLUG_INT_EN | \
2416 PORTD_HOTPLUG_INT_EN | \
2417 SDVOC_HOTPLUG_INT_EN | \
2418 SDVOB_HOTPLUG_INT_EN | \
2420 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
2421 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2422 /* must use period 64 on GM45 according to docs */
2423 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2424 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2425 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2426 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2427 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2428 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2429 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2430 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2431 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2432 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2433 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2434 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
2436 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
2438 * HDMI/DP bits are g4x+
2440 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2441 * Please check the detailed lore in the commit message for for experimental
2444 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
2445 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
2446 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
2447 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
2448 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
2449 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2450 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2451 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2452 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2453 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
2454 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
2455 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2456 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
2457 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
2458 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
2459 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
2460 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
2461 /* CRT/TV common between gen3+ */
2462 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
2463 #define TV_HOTPLUG_INT_STATUS (1 << 10)
2464 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2465 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2466 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2467 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
2468 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2469 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2470 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2471 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2473 /* SDVO is different across gen3/4 */
2474 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2475 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
2477 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2478 * since reality corrobates that they're the same as on gen3. But keep these
2479 * bits here (and the comment!) to help any other lost wanderers back onto the
2482 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2483 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2484 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2485 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
2486 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2487 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2488 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2489 PORTB_HOTPLUG_INT_STATUS | \
2490 PORTC_HOTPLUG_INT_STATUS | \
2491 PORTD_HOTPLUG_INT_STATUS)
2493 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2494 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2495 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2496 PORTB_HOTPLUG_INT_STATUS | \
2497 PORTC_HOTPLUG_INT_STATUS | \
2498 PORTD_HOTPLUG_INT_STATUS)
2500 /* SDVO and HDMI port control.
2501 * The same register may be used for SDVO or HDMI */
2502 #define _GEN3_SDVOB 0x61140
2503 #define _GEN3_SDVOC 0x61160
2504 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
2505 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
2506 #define GEN4_HDMIB GEN3_SDVOB
2507 #define GEN4_HDMIC GEN3_SDVOC
2508 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
2509 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
2510 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
2511 #define PCH_SDVOB _MMIO(0xe1140)
2512 #define PCH_HDMIB PCH_SDVOB
2513 #define PCH_HDMIC _MMIO(0xe1150)
2514 #define PCH_HDMID _MMIO(0xe1160)
2516 #define PORT_DFT_I9XX _MMIO(0x61150)
2517 #define DC_BALANCE_RESET (1 << 25)
2518 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
2519 #define DC_BALANCE_RESET_VLV (1 << 31)
2520 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
2521 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
2522 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
2523 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
2525 /* Gen 3 SDVO bits: */
2526 #define SDVO_ENABLE (1 << 31)
2527 #define SDVO_PIPE_SEL_SHIFT 30
2528 #define SDVO_PIPE_SEL_MASK (1 << 30)
2529 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2530 #define SDVO_STALL_SELECT (1 << 29)
2531 #define SDVO_INTERRUPT_ENABLE (1 << 26)
2533 * 915G/GM SDVO pixel multiplier.
2534 * Programmed value is multiplier - 1, up to 5x.
2535 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2537 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
2538 #define SDVO_PORT_MULTIPLY_SHIFT 23
2539 #define SDVO_PHASE_SELECT_MASK (15 << 19)
2540 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2541 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2542 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2543 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2544 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2545 #define SDVO_DETECTED (1 << 2)
2546 /* Bits to be preserved when writing */
2547 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2548 SDVO_INTERRUPT_ENABLE)
2549 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2551 /* Gen 4 SDVO/HDMI bits: */
2552 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
2553 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
2554 #define SDVO_ENCODING_SDVO (0 << 10)
2555 #define SDVO_ENCODING_HDMI (2 << 10)
2556 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2557 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
2558 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
2559 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
2560 /* VSYNC/HSYNC bits new with 965, default is to be set */
2561 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2562 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2564 /* Gen 5 (IBX) SDVO/HDMI bits: */
2565 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
2566 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2568 /* Gen 6 (CPT) SDVO/HDMI bits: */
2569 #define SDVO_PIPE_SEL_SHIFT_CPT 29
2570 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
2571 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2573 /* CHV SDVO/HDMI bits: */
2574 #define SDVO_PIPE_SEL_SHIFT_CHV 24
2575 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
2576 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
2579 /* DVO port control */
2580 #define _DVOA 0x61120
2581 #define DVOA _MMIO(_DVOA)
2582 #define _DVOB 0x61140
2583 #define DVOB _MMIO(_DVOB)
2584 #define _DVOC 0x61160
2585 #define DVOC _MMIO(_DVOC)
2586 #define DVO_ENABLE (1 << 31)
2587 #define DVO_PIPE_SEL_SHIFT 30
2588 #define DVO_PIPE_SEL_MASK (1 << 30)
2589 #define DVO_PIPE_SEL(pipe) ((pipe) << 30)
2590 #define DVO_PIPE_STALL_UNUSED (0 << 28)
2591 #define DVO_PIPE_STALL (1 << 28)
2592 #define DVO_PIPE_STALL_TV (2 << 28)
2593 #define DVO_PIPE_STALL_MASK (3 << 28)
2594 #define DVO_USE_VGA_SYNC (1 << 15)
2595 #define DVO_DATA_ORDER_I740 (0 << 14)
2596 #define DVO_DATA_ORDER_FP (1 << 14)
2597 #define DVO_VSYNC_DISABLE (1 << 11)
2598 #define DVO_HSYNC_DISABLE (1 << 10)
2599 #define DVO_VSYNC_TRISTATE (1 << 9)
2600 #define DVO_HSYNC_TRISTATE (1 << 8)
2601 #define DVO_BORDER_ENABLE (1 << 7)
2602 #define DVO_DATA_ORDER_GBRG (1 << 6)
2603 #define DVO_DATA_ORDER_RGGB (0 << 6)
2604 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2605 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2606 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2607 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2608 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2609 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2610 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2611 #define DVO_PRESERVE_MASK (0x7 << 24)
2612 #define DVOA_SRCDIM _MMIO(0x61124)
2613 #define DVOB_SRCDIM _MMIO(0x61144)
2614 #define DVOC_SRCDIM _MMIO(0x61164)
2615 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2616 #define DVO_SRCDIM_VERTICAL_SHIFT 0
2618 /* LVDS port control */
2619 #define LVDS _MMIO(0x61180)
2621 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2622 * the DPLL semantics change when the LVDS is assigned to that pipe.
2624 #define LVDS_PORT_EN (1 << 31)
2625 /* Selects pipe B for LVDS data. Must be set on pre-965. */
2626 #define LVDS_PIPE_SEL_SHIFT 30
2627 #define LVDS_PIPE_SEL_MASK (1 << 30)
2628 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
2629 #define LVDS_PIPE_SEL_SHIFT_CPT 29
2630 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
2631 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2632 /* LVDS dithering flag on 965/g4x platform */
2633 #define LVDS_ENABLE_DITHER (1 << 25)
2634 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
2635 #define LVDS_VSYNC_POLARITY (1 << 21)
2636 #define LVDS_HSYNC_POLARITY (1 << 20)
2638 /* Enable border for unscaled (or aspect-scaled) display */
2639 #define LVDS_BORDER_ENABLE (1 << 15)
2641 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2644 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2645 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2646 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2648 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2649 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2652 #define LVDS_A3_POWER_MASK (3 << 6)
2653 #define LVDS_A3_POWER_DOWN (0 << 6)
2654 #define LVDS_A3_POWER_UP (3 << 6)
2656 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2659 #define LVDS_CLKB_POWER_MASK (3 << 4)
2660 #define LVDS_CLKB_POWER_DOWN (0 << 4)
2661 #define LVDS_CLKB_POWER_UP (3 << 4)
2663 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2664 * setting for whether we are in dual-channel mode. The B3 pair will
2665 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2667 #define LVDS_B0B3_POWER_MASK (3 << 2)
2668 #define LVDS_B0B3_POWER_DOWN (0 << 2)
2669 #define LVDS_B0B3_POWER_UP (3 << 2)
2671 /* Video Data Island Packet control */
2672 #define VIDEO_DIP_DATA _MMIO(0x61178)
2673 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
2674 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2675 * of the infoframe structure specified by CEA-861. */
2676 #define VIDEO_DIP_DATA_SIZE 32
2677 #define VIDEO_DIP_GMP_DATA_SIZE 36
2678 #define VIDEO_DIP_VSC_DATA_SIZE 36
2679 #define VIDEO_DIP_PPS_DATA_SIZE 132
2680 #define VIDEO_DIP_CTL _MMIO(0x61170)
2682 #define VIDEO_DIP_ENABLE (1 << 31)
2683 #define VIDEO_DIP_PORT(port) ((port) << 29)
2684 #define VIDEO_DIP_PORT_MASK (3 << 29)
2685 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
2686 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
2687 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
2688 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
2689 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
2690 #define VIDEO_DIP_SELECT_AVI (0 << 19)
2691 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2692 #define VIDEO_DIP_SELECT_GAMUT (2 << 19)
2693 #define VIDEO_DIP_SELECT_SPD (3 << 19)
2694 #define VIDEO_DIP_SELECT_MASK (3 << 19)
2695 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
2696 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2697 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
2698 #define VIDEO_DIP_FREQ_MASK (3 << 16)
2699 /* HSW and later: */
2700 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
2701 #define PSR_VSC_BIT_7_SET (1 << 27)
2702 #define VSC_SELECT_MASK (0x3 << 25)
2703 #define VSC_SELECT_SHIFT 25
2704 #define VSC_DIP_HW_HEA_DATA (0 << 25)
2705 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
2706 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
2707 #define VSC_DIP_SW_HEA_DATA (3 << 25)
2708 #define VDIP_ENABLE_PPS (1 << 24)
2709 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2710 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2711 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
2712 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2713 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2714 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
2716 /* Panel power sequencing */
2717 #define PPS_BASE 0x61200
2718 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
2719 #define PCH_PPS_BASE 0xC7200
2721 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \
2722 PPS_BASE + (reg) + \
2725 #define _PP_STATUS 0x61200
2726 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
2727 #define PP_ON REG_BIT(31)
2729 * Indicates that all dependencies of the panel are on:
2733 * - LVDS/DVOB/DVOC on
2735 #define PP_READY REG_BIT(30)
2736 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
2737 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
2738 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
2739 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
2740 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
2741 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
2742 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
2743 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
2744 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
2745 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
2746 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
2747 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
2748 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
2749 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
2750 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
2752 #define _PP_CONTROL 0x61204
2753 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
2754 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
2755 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
2756 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
2757 #define EDP_FORCE_VDD REG_BIT(3)
2758 #define EDP_BLC_ENABLE REG_BIT(2)
2759 #define PANEL_POWER_RESET REG_BIT(1)
2760 #define PANEL_POWER_ON REG_BIT(0)
2762 #define _PP_ON_DELAYS 0x61208
2763 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
2764 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
2765 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
2766 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
2767 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
2768 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
2769 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
2770 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
2771 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
2773 #define _PP_OFF_DELAYS 0x6120C
2774 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
2775 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
2776 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
2778 #define _PP_DIVISOR 0x61210
2779 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
2780 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
2781 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
2784 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
2785 #define PFIT_ENABLE (1 << 31)
2786 #define PFIT_PIPE_MASK (3 << 29)
2787 #define PFIT_PIPE_SHIFT 29
2788 #define PFIT_PIPE(pipe) ((pipe) << 29)
2789 #define VERT_INTERP_DISABLE (0 << 10)
2790 #define VERT_INTERP_BILINEAR (1 << 10)
2791 #define VERT_INTERP_MASK (3 << 10)
2792 #define VERT_AUTO_SCALE (1 << 9)
2793 #define HORIZ_INTERP_DISABLE (0 << 6)
2794 #define HORIZ_INTERP_BILINEAR (1 << 6)
2795 #define HORIZ_INTERP_MASK (3 << 6)
2796 #define HORIZ_AUTO_SCALE (1 << 5)
2797 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
2798 #define PFIT_FILTER_FUZZY (0 << 24)
2799 #define PFIT_SCALING_AUTO (0 << 26)
2800 #define PFIT_SCALING_PROGRAMMED (1 << 26)
2801 #define PFIT_SCALING_PILLAR (2 << 26)
2802 #define PFIT_SCALING_LETTER (3 << 26)
2803 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
2805 #define PFIT_VERT_SCALE_SHIFT 20
2806 #define PFIT_VERT_SCALE_MASK 0xfff00000
2807 #define PFIT_HORIZ_SCALE_SHIFT 4
2808 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2810 #define PFIT_VERT_SCALE_SHIFT_965 16
2811 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2812 #define PFIT_HORIZ_SCALE_SHIFT_965 0
2813 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2815 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
2817 #define PCH_GTC_CTL _MMIO(0xe7000)
2818 #define PCH_GTC_ENABLE (1 << 31)
2820 /* TV port control */
2821 #define TV_CTL _MMIO(0x68000)
2822 /* Enables the TV encoder */
2823 # define TV_ENC_ENABLE (1 << 31)
2824 /* Sources the TV encoder input from pipe B instead of A. */
2825 # define TV_ENC_PIPE_SEL_SHIFT 30
2826 # define TV_ENC_PIPE_SEL_MASK (1 << 30)
2827 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
2828 /* Outputs composite video (DAC A only) */
2829 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
2830 /* Outputs SVideo video (DAC B/C) */
2831 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
2832 /* Outputs Component video (DAC A/B/C) */
2833 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
2834 /* Outputs Composite and SVideo (DAC A/B/C) */
2835 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2836 # define TV_TRILEVEL_SYNC (1 << 21)
2837 /* Enables slow sync generation (945GM only) */
2838 # define TV_SLOW_SYNC (1 << 20)
2839 /* Selects 4x oversampling for 480i and 576p */
2840 # define TV_OVERSAMPLE_4X (0 << 18)
2841 /* Selects 2x oversampling for 720p and 1080i */
2842 # define TV_OVERSAMPLE_2X (1 << 18)
2843 /* Selects no oversampling for 1080p */
2844 # define TV_OVERSAMPLE_NONE (2 << 18)
2845 /* Selects 8x oversampling */
2846 # define TV_OVERSAMPLE_8X (3 << 18)
2847 # define TV_OVERSAMPLE_MASK (3 << 18)
2848 /* Selects progressive mode rather than interlaced */
2849 # define TV_PROGRESSIVE (1 << 17)
2850 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2851 # define TV_PAL_BURST (1 << 16)
2852 /* Field for setting delay of Y compared to C */
2853 # define TV_YC_SKEW_MASK (7 << 12)
2854 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
2855 # define TV_ENC_SDP_FIX (1 << 11)
2857 * Enables a fix for the 915GM only.
2859 * Not sure what it does.
2861 # define TV_ENC_C0_FIX (1 << 10)
2862 /* Bits that must be preserved by software */
2863 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2864 # define TV_FUSE_STATE_MASK (3 << 4)
2865 /* Read-only state that reports all features enabled */
2866 # define TV_FUSE_STATE_ENABLED (0 << 4)
2867 /* Read-only state that reports that Macrovision is disabled in hardware*/
2868 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2869 /* Read-only state that reports that TV-out is disabled in hardware. */
2870 # define TV_FUSE_STATE_DISABLED (2 << 4)
2871 /* Normal operation */
2872 # define TV_TEST_MODE_NORMAL (0 << 0)
2873 /* Encoder test pattern 1 - combo pattern */
2874 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
2875 /* Encoder test pattern 2 - full screen vertical 75% color bars */
2876 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
2877 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
2878 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
2879 /* Encoder test pattern 4 - random noise */
2880 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
2881 /* Encoder test pattern 5 - linear color ramps */
2882 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
2884 * This test mode forces the DACs to 50% of full output.
2886 * This is used for load detection in combination with TVDAC_SENSE_MASK
2888 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2889 # define TV_TEST_MODE_MASK (7 << 0)
2891 #define TV_DAC _MMIO(0x68004)
2892 # define TV_DAC_SAVE 0x00ffff00
2894 * Reports that DAC state change logic has reported change (RO).
2896 * This gets cleared when TV_DAC_STATE_EN is cleared
2898 # define TVDAC_STATE_CHG (1 << 31)
2899 # define TVDAC_SENSE_MASK (7 << 28)
2900 /* Reports that DAC A voltage is above the detect threshold */
2901 # define TVDAC_A_SENSE (1 << 30)
2902 /* Reports that DAC B voltage is above the detect threshold */
2903 # define TVDAC_B_SENSE (1 << 29)
2904 /* Reports that DAC C voltage is above the detect threshold */
2905 # define TVDAC_C_SENSE (1 << 28)
2907 * Enables DAC state detection logic, for load-based TV detection.
2909 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2910 * to off, for load detection to work.
2912 # define TVDAC_STATE_CHG_EN (1 << 27)
2913 /* Sets the DAC A sense value to high */
2914 # define TVDAC_A_SENSE_CTL (1 << 26)
2915 /* Sets the DAC B sense value to high */
2916 # define TVDAC_B_SENSE_CTL (1 << 25)
2917 /* Sets the DAC C sense value to high */
2918 # define TVDAC_C_SENSE_CTL (1 << 24)
2919 /* Overrides the ENC_ENABLE and DAC voltage levels */
2920 # define DAC_CTL_OVERRIDE (1 << 7)
2921 /* Sets the slew rate. Must be preserved in software */
2922 # define ENC_TVDAC_SLEW_FAST (1 << 6)
2923 # define DAC_A_1_3_V (0 << 4)
2924 # define DAC_A_1_1_V (1 << 4)
2925 # define DAC_A_0_7_V (2 << 4)
2926 # define DAC_A_MASK (3 << 4)
2927 # define DAC_B_1_3_V (0 << 2)
2928 # define DAC_B_1_1_V (1 << 2)
2929 # define DAC_B_0_7_V (2 << 2)
2930 # define DAC_B_MASK (3 << 2)
2931 # define DAC_C_1_3_V (0 << 0)
2932 # define DAC_C_1_1_V (1 << 0)
2933 # define DAC_C_0_7_V (2 << 0)
2934 # define DAC_C_MASK (3 << 0)
2937 * CSC coefficients are stored in a floating point format with 9 bits of
2938 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2939 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2940 * -1 (0x3) being the only legal negative value.
2942 #define TV_CSC_Y _MMIO(0x68010)
2943 # define TV_RY_MASK 0x07ff0000
2944 # define TV_RY_SHIFT 16
2945 # define TV_GY_MASK 0x00000fff
2946 # define TV_GY_SHIFT 0
2948 #define TV_CSC_Y2 _MMIO(0x68014)
2949 # define TV_BY_MASK 0x07ff0000
2950 # define TV_BY_SHIFT 16
2952 * Y attenuation for component video.
2954 * Stored in 1.9 fixed point.
2956 # define TV_AY_MASK 0x000003ff
2957 # define TV_AY_SHIFT 0
2959 #define TV_CSC_U _MMIO(0x68018)
2960 # define TV_RU_MASK 0x07ff0000
2961 # define TV_RU_SHIFT 16
2962 # define TV_GU_MASK 0x000007ff
2963 # define TV_GU_SHIFT 0
2965 #define TV_CSC_U2 _MMIO(0x6801c)
2966 # define TV_BU_MASK 0x07ff0000
2967 # define TV_BU_SHIFT 16
2969 * U attenuation for component video.
2971 * Stored in 1.9 fixed point.
2973 # define TV_AU_MASK 0x000003ff
2974 # define TV_AU_SHIFT 0
2976 #define TV_CSC_V _MMIO(0x68020)
2977 # define TV_RV_MASK 0x0fff0000
2978 # define TV_RV_SHIFT 16
2979 # define TV_GV_MASK 0x000007ff
2980 # define TV_GV_SHIFT 0
2982 #define TV_CSC_V2 _MMIO(0x68024)
2983 # define TV_BV_MASK 0x07ff0000
2984 # define TV_BV_SHIFT 16
2986 * V attenuation for component video.
2988 * Stored in 1.9 fixed point.
2990 # define TV_AV_MASK 0x000007ff
2991 # define TV_AV_SHIFT 0
2993 #define TV_CLR_KNOBS _MMIO(0x68028)
2994 /* 2s-complement brightness adjustment */
2995 # define TV_BRIGHTNESS_MASK 0xff000000
2996 # define TV_BRIGHTNESS_SHIFT 24
2997 /* Contrast adjustment, as a 2.6 unsigned floating point number */
2998 # define TV_CONTRAST_MASK 0x00ff0000
2999 # define TV_CONTRAST_SHIFT 16
3000 /* Saturation adjustment, as a 2.6 unsigned floating point number */
3001 # define TV_SATURATION_MASK 0x0000ff00
3002 # define TV_SATURATION_SHIFT 8
3003 /* Hue adjustment, as an integer phase angle in degrees */
3004 # define TV_HUE_MASK 0x000000ff
3005 # define TV_HUE_SHIFT 0
3007 #define TV_CLR_LEVEL _MMIO(0x6802c)
3008 /* Controls the DAC level for black */
3009 # define TV_BLACK_LEVEL_MASK 0x01ff0000
3010 # define TV_BLACK_LEVEL_SHIFT 16
3011 /* Controls the DAC level for blanking */
3012 # define TV_BLANK_LEVEL_MASK 0x000001ff
3013 # define TV_BLANK_LEVEL_SHIFT 0
3015 #define TV_H_CTL_1 _MMIO(0x68030)
3016 /* Number of pixels in the hsync. */
3017 # define TV_HSYNC_END_MASK 0x1fff0000
3018 # define TV_HSYNC_END_SHIFT 16
3019 /* Total number of pixels minus one in the line (display and blanking). */
3020 # define TV_HTOTAL_MASK 0x00001fff
3021 # define TV_HTOTAL_SHIFT 0
3023 #define TV_H_CTL_2 _MMIO(0x68034)
3024 /* Enables the colorburst (needed for non-component color) */
3025 # define TV_BURST_ENA (1 << 31)
3026 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
3027 # define TV_HBURST_START_SHIFT 16
3028 # define TV_HBURST_START_MASK 0x1fff0000
3029 /* Length of the colorburst */
3030 # define TV_HBURST_LEN_SHIFT 0
3031 # define TV_HBURST_LEN_MASK 0x0001fff
3033 #define TV_H_CTL_3 _MMIO(0x68038)
3034 /* End of hblank, measured in pixels minus one from start of hsync */
3035 # define TV_HBLANK_END_SHIFT 16
3036 # define TV_HBLANK_END_MASK 0x1fff0000
3037 /* Start of hblank, measured in pixels minus one from start of hsync */
3038 # define TV_HBLANK_START_SHIFT 0
3039 # define TV_HBLANK_START_MASK 0x0001fff
3041 #define TV_V_CTL_1 _MMIO(0x6803c)
3043 # define TV_NBR_END_SHIFT 16
3044 # define TV_NBR_END_MASK 0x07ff0000
3046 # define TV_VI_END_F1_SHIFT 8
3047 # define TV_VI_END_F1_MASK 0x00003f00
3049 # define TV_VI_END_F2_SHIFT 0
3050 # define TV_VI_END_F2_MASK 0x0000003f
3052 #define TV_V_CTL_2 _MMIO(0x68040)
3053 /* Length of vsync, in half lines */
3054 # define TV_VSYNC_LEN_MASK 0x07ff0000
3055 # define TV_VSYNC_LEN_SHIFT 16
3056 /* Offset of the start of vsync in field 1, measured in one less than the
3057 * number of half lines.
3059 # define TV_VSYNC_START_F1_MASK 0x00007f00
3060 # define TV_VSYNC_START_F1_SHIFT 8
3062 * Offset of the start of vsync in field 2, measured in one less than the
3063 * number of half lines.
3065 # define TV_VSYNC_START_F2_MASK 0x0000007f
3066 # define TV_VSYNC_START_F2_SHIFT 0
3068 #define TV_V_CTL_3 _MMIO(0x68044)
3069 /* Enables generation of the equalization signal */
3070 # define TV_EQUAL_ENA (1 << 31)
3071 /* Length of vsync, in half lines */
3072 # define TV_VEQ_LEN_MASK 0x007f0000
3073 # define TV_VEQ_LEN_SHIFT 16
3074 /* Offset of the start of equalization in field 1, measured in one less than
3075 * the number of half lines.
3077 # define TV_VEQ_START_F1_MASK 0x0007f00
3078 # define TV_VEQ_START_F1_SHIFT 8
3080 * Offset of the start of equalization in field 2, measured in one less than
3081 * the number of half lines.
3083 # define TV_VEQ_START_F2_MASK 0x000007f
3084 # define TV_VEQ_START_F2_SHIFT 0
3086 #define TV_V_CTL_4 _MMIO(0x68048)
3088 * Offset to start of vertical colorburst, measured in one less than the
3089 * number of lines from vertical start.
3091 # define TV_VBURST_START_F1_MASK 0x003f0000
3092 # define TV_VBURST_START_F1_SHIFT 16
3094 * Offset to the end of vertical colorburst, measured in one less than the
3095 * number of lines from the start of NBR.
3097 # define TV_VBURST_END_F1_MASK 0x000000ff
3098 # define TV_VBURST_END_F1_SHIFT 0
3100 #define TV_V_CTL_5 _MMIO(0x6804c)
3102 * Offset to start of vertical colorburst, measured in one less than the
3103 * number of lines from vertical start.
3105 # define TV_VBURST_START_F2_MASK 0x003f0000
3106 # define TV_VBURST_START_F2_SHIFT 16
3108 * Offset to the end of vertical colorburst, measured in one less than the
3109 * number of lines from the start of NBR.
3111 # define TV_VBURST_END_F2_MASK 0x000000ff
3112 # define TV_VBURST_END_F2_SHIFT 0
3114 #define TV_V_CTL_6 _MMIO(0x68050)
3116 * Offset to start of vertical colorburst, measured in one less than the
3117 * number of lines from vertical start.
3119 # define TV_VBURST_START_F3_MASK 0x003f0000
3120 # define TV_VBURST_START_F3_SHIFT 16
3122 * Offset to the end of vertical colorburst, measured in one less than the
3123 * number of lines from the start of NBR.
3125 # define TV_VBURST_END_F3_MASK 0x000000ff
3126 # define TV_VBURST_END_F3_SHIFT 0
3128 #define TV_V_CTL_7 _MMIO(0x68054)
3130 * Offset to start of vertical colorburst, measured in one less than the
3131 * number of lines from vertical start.
3133 # define TV_VBURST_START_F4_MASK 0x003f0000
3134 # define TV_VBURST_START_F4_SHIFT 16
3136 * Offset to the end of vertical colorburst, measured in one less than the
3137 * number of lines from the start of NBR.
3139 # define TV_VBURST_END_F4_MASK 0x000000ff
3140 # define TV_VBURST_END_F4_SHIFT 0
3142 #define TV_SC_CTL_1 _MMIO(0x68060)
3143 /* Turns on the first subcarrier phase generation DDA */
3144 # define TV_SC_DDA1_EN (1 << 31)
3145 /* Turns on the first subcarrier phase generation DDA */
3146 # define TV_SC_DDA2_EN (1 << 30)
3147 /* Turns on the first subcarrier phase generation DDA */
3148 # define TV_SC_DDA3_EN (1 << 29)
3149 /* Sets the subcarrier DDA to reset frequency every other field */
3150 # define TV_SC_RESET_EVERY_2 (0 << 24)
3151 /* Sets the subcarrier DDA to reset frequency every fourth field */
3152 # define TV_SC_RESET_EVERY_4 (1 << 24)
3153 /* Sets the subcarrier DDA to reset frequency every eighth field */
3154 # define TV_SC_RESET_EVERY_8 (2 << 24)
3155 /* Sets the subcarrier DDA to never reset the frequency */
3156 # define TV_SC_RESET_NEVER (3 << 24)
3157 /* Sets the peak amplitude of the colorburst.*/
3158 # define TV_BURST_LEVEL_MASK 0x00ff0000
3159 # define TV_BURST_LEVEL_SHIFT 16
3160 /* Sets the increment of the first subcarrier phase generation DDA */
3161 # define TV_SCDDA1_INC_MASK 0x00000fff
3162 # define TV_SCDDA1_INC_SHIFT 0
3164 #define TV_SC_CTL_2 _MMIO(0x68064)
3165 /* Sets the rollover for the second subcarrier phase generation DDA */
3166 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
3167 # define TV_SCDDA2_SIZE_SHIFT 16
3168 /* Sets the increent of the second subcarrier phase generation DDA */
3169 # define TV_SCDDA2_INC_MASK 0x00007fff
3170 # define TV_SCDDA2_INC_SHIFT 0
3172 #define TV_SC_CTL_3 _MMIO(0x68068)
3173 /* Sets the rollover for the third subcarrier phase generation DDA */
3174 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
3175 # define TV_SCDDA3_SIZE_SHIFT 16
3176 /* Sets the increent of the third subcarrier phase generation DDA */
3177 # define TV_SCDDA3_INC_MASK 0x00007fff
3178 # define TV_SCDDA3_INC_SHIFT 0
3180 #define TV_WIN_POS _MMIO(0x68070)
3181 /* X coordinate of the display from the start of horizontal active */
3182 # define TV_XPOS_MASK 0x1fff0000
3183 # define TV_XPOS_SHIFT 16
3184 /* Y coordinate of the display from the start of vertical active (NBR) */
3185 # define TV_YPOS_MASK 0x00000fff
3186 # define TV_YPOS_SHIFT 0
3188 #define TV_WIN_SIZE _MMIO(0x68074)
3189 /* Horizontal size of the display window, measured in pixels*/
3190 # define TV_XSIZE_MASK 0x1fff0000
3191 # define TV_XSIZE_SHIFT 16
3193 * Vertical size of the display window, measured in pixels.
3195 * Must be even for interlaced modes.
3197 # define TV_YSIZE_MASK 0x00000fff
3198 # define TV_YSIZE_SHIFT 0
3200 #define TV_FILTER_CTL_1 _MMIO(0x68080)
3202 * Enables automatic scaling calculation.
3204 * If set, the rest of the registers are ignored, and the calculated values can
3205 * be read back from the register.
3207 # define TV_AUTO_SCALE (1 << 31)
3209 * Disables the vertical filter.
3211 * This is required on modes more than 1024 pixels wide */
3212 # define TV_V_FILTER_BYPASS (1 << 29)
3213 /* Enables adaptive vertical filtering */
3214 # define TV_VADAPT (1 << 28)
3215 # define TV_VADAPT_MODE_MASK (3 << 26)
3216 /* Selects the least adaptive vertical filtering mode */
3217 # define TV_VADAPT_MODE_LEAST (0 << 26)
3218 /* Selects the moderately adaptive vertical filtering mode */
3219 # define TV_VADAPT_MODE_MODERATE (1 << 26)
3220 /* Selects the most adaptive vertical filtering mode */
3221 # define TV_VADAPT_MODE_MOST (3 << 26)
3223 * Sets the horizontal scaling factor.
3225 * This should be the fractional part of the horizontal scaling factor divided
3226 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
3228 * (src width - 1) / ((oversample * dest width) - 1)
3230 # define TV_HSCALE_FRAC_MASK 0x00003fff
3231 # define TV_HSCALE_FRAC_SHIFT 0
3233 #define TV_FILTER_CTL_2 _MMIO(0x68084)
3235 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3237 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
3239 # define TV_VSCALE_INT_MASK 0x00038000
3240 # define TV_VSCALE_INT_SHIFT 15
3242 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3244 * \sa TV_VSCALE_INT_MASK
3246 # define TV_VSCALE_FRAC_MASK 0x00007fff
3247 # define TV_VSCALE_FRAC_SHIFT 0
3249 #define TV_FILTER_CTL_3 _MMIO(0x68088)
3251 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3253 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
3255 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3257 # define TV_VSCALE_IP_INT_MASK 0x00038000
3258 # define TV_VSCALE_IP_INT_SHIFT 15
3260 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3262 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3264 * \sa TV_VSCALE_IP_INT_MASK
3266 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
3267 # define TV_VSCALE_IP_FRAC_SHIFT 0
3269 #define TV_CC_CONTROL _MMIO(0x68090)
3270 # define TV_CC_ENABLE (1 << 31)
3272 * Specifies which field to send the CC data in.
3274 * CC data is usually sent in field 0.
3276 # define TV_CC_FID_MASK (1 << 27)
3277 # define TV_CC_FID_SHIFT 27
3278 /* Sets the horizontal position of the CC data. Usually 135. */
3279 # define TV_CC_HOFF_MASK 0x03ff0000
3280 # define TV_CC_HOFF_SHIFT 16
3281 /* Sets the vertical position of the CC data. Usually 21 */
3282 # define TV_CC_LINE_MASK 0x0000003f
3283 # define TV_CC_LINE_SHIFT 0
3285 #define TV_CC_DATA _MMIO(0x68094)
3286 # define TV_CC_RDY (1 << 31)
3287 /* Second word of CC data to be transmitted. */
3288 # define TV_CC_DATA_2_MASK 0x007f0000
3289 # define TV_CC_DATA_2_SHIFT 16
3290 /* First word of CC data to be transmitted. */
3291 # define TV_CC_DATA_1_MASK 0x0000007f
3292 # define TV_CC_DATA_1_SHIFT 0
3294 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
3295 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
3296 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
3297 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
3300 #define DP_A _MMIO(0x64000) /* eDP */
3301 #define DP_B _MMIO(0x64100)
3302 #define DP_C _MMIO(0x64200)
3303 #define DP_D _MMIO(0x64300)
3305 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
3306 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
3307 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
3309 #define DP_PORT_EN (1 << 31)
3310 #define DP_PIPE_SEL_SHIFT 30
3311 #define DP_PIPE_SEL_MASK (1 << 30)
3312 #define DP_PIPE_SEL(pipe) ((pipe) << 30)
3313 #define DP_PIPE_SEL_SHIFT_IVB 29
3314 #define DP_PIPE_SEL_MASK_IVB (3 << 29)
3315 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
3316 #define DP_PIPE_SEL_SHIFT_CHV 16
3317 #define DP_PIPE_SEL_MASK_CHV (3 << 16)
3318 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
3320 /* Link training mode - select a suitable mode for each stage */
3321 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
3322 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
3323 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3324 #define DP_LINK_TRAIN_OFF (3 << 28)
3325 #define DP_LINK_TRAIN_MASK (3 << 28)
3326 #define DP_LINK_TRAIN_SHIFT 28
3328 /* CPT Link training mode */
3329 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3330 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3331 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3332 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3333 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3334 #define DP_LINK_TRAIN_SHIFT_CPT 8
3336 /* Signal voltages. These are mostly controlled by the other end */
3337 #define DP_VOLTAGE_0_4 (0 << 25)
3338 #define DP_VOLTAGE_0_6 (1 << 25)
3339 #define DP_VOLTAGE_0_8 (2 << 25)
3340 #define DP_VOLTAGE_1_2 (3 << 25)
3341 #define DP_VOLTAGE_MASK (7 << 25)
3342 #define DP_VOLTAGE_SHIFT 25
3344 /* Signal pre-emphasis levels, like voltages, the other end tells us what
3347 #define DP_PRE_EMPHASIS_0 (0 << 22)
3348 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
3349 #define DP_PRE_EMPHASIS_6 (2 << 22)
3350 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
3351 #define DP_PRE_EMPHASIS_MASK (7 << 22)
3352 #define DP_PRE_EMPHASIS_SHIFT 22
3354 /* How many wires to use. I guess 3 was too hard */
3355 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
3356 #define DP_PORT_WIDTH_MASK (7 << 19)
3357 #define DP_PORT_WIDTH_SHIFT 19
3359 /* Mystic DPCD version 1.1 special mode */
3360 #define DP_ENHANCED_FRAMING (1 << 18)
3363 #define DP_PLL_FREQ_270MHZ (0 << 16)
3364 #define DP_PLL_FREQ_162MHZ (1 << 16)
3365 #define DP_PLL_FREQ_MASK (3 << 16)
3367 /* locked once port is enabled */
3368 #define DP_PORT_REVERSAL (1 << 15)
3371 #define DP_PLL_ENABLE (1 << 14)
3373 /* sends the clock on lane 15 of the PEG for debug */
3374 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3376 #define DP_SCRAMBLING_DISABLE (1 << 12)
3377 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
3379 /* limit RGB values to avoid confusing TVs */
3380 #define DP_COLOR_RANGE_16_235 (1 << 8)
3382 /* Turn on the audio link */
3383 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3385 /* vs and hs sync polarity */
3386 #define DP_SYNC_VS_HIGH (1 << 4)
3387 #define DP_SYNC_HS_HIGH (1 << 3)
3390 #define DP_DETECTED (1 << 2)
3392 /* The aux channel provides a way to talk to the
3393 * signal sink for DDC etc. Max packet size supported
3394 * is 20 bytes in each direction, hence the 5 fixed
3397 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
3398 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
3400 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
3401 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
3403 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
3404 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
3406 #define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
3407 #define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
3408 #define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
3409 #define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
3411 #define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
3414 0, /* port/aux_ch C is non-existent */ \
3415 _XELPDP_USBC1_AUX_CH_CTL, \
3416 _XELPDP_USBC2_AUX_CH_CTL, \
3417 _XELPDP_USBC3_AUX_CH_CTL, \
3418 _XELPDP_USBC4_AUX_CH_CTL))
3420 #define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
3421 #define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
3422 #define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
3423 #define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
3425 #define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
3426 _DPA_AUX_CH_DATA1, \
3427 _DPB_AUX_CH_DATA1, \
3428 0, /* port/aux_ch C is non-existent */ \
3429 _XELPDP_USBC1_AUX_CH_DATA1, \
3430 _XELPDP_USBC2_AUX_CH_DATA1, \
3431 _XELPDP_USBC3_AUX_CH_DATA1, \
3432 _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
3434 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3435 #define DP_AUX_CH_CTL_DONE (1 << 30)
3436 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3437 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3438 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3439 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3440 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3441 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
3442 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3443 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3444 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3445 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3446 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19)
3447 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18)
3448 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3449 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3450 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3451 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3452 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3453 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3454 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3455 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3456 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3457 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
3458 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
3459 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
3460 #define DP_AUX_CH_CTL_TBT_IO (1 << 11)
3461 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
3462 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
3463 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
3466 * Computing GMCH M and N values for the Display Port link
3468 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3470 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3472 * The GMCH value is used internally
3474 * bytes_per_pixel is the number of bytes coming out of the plane,
3475 * which is after the LUTs, so we want the bytes for our color format.
3476 * For our current usage, this is always 3, one byte for R, G and B.
3478 #define _PIPEA_DATA_M_G4X 0x70050
3479 #define _PIPEB_DATA_M_G4X 0x71050
3481 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3482 #define TU_SIZE_MASK REG_GENMASK(30, 25)
3483 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
3485 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
3486 #define DATA_LINK_N_MAX (0x800000)
3488 #define _PIPEA_DATA_N_G4X 0x70054
3489 #define _PIPEB_DATA_N_G4X 0x71054
3492 * Computing Link M and N values for the Display Port link
3494 * Link M / N = pixel_clock / ls_clk
3496 * (the DP spec calls pixel_clock the 'strm_clk')
3498 * The Link value is transmitted in the Main Stream
3499 * Attributes and VB-ID.
3502 #define _PIPEA_LINK_M_G4X 0x70060
3503 #define _PIPEB_LINK_M_G4X 0x71060
3504 #define _PIPEA_LINK_N_G4X 0x70064
3505 #define _PIPEB_LINK_N_G4X 0x71064
3507 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3508 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3509 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3510 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
3512 /* Display & cursor control */
3515 #define _PIPEADSL 0x70000
3516 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
3517 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
3518 #define _PIPEACONF 0x70008
3519 #define PIPECONF_ENABLE REG_BIT(31)
3520 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
3521 #define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */
3522 #define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
3523 #define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
3524 #define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
3525 #define PIPECONF_PIPE_LOCKED REG_BIT(25)
3526 #define PIPECONF_FORCE_BORDER REG_BIT(25)
3527 #define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
3528 #define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
3529 #define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
3530 #define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
3531 #define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
3532 #define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
3533 #define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
3534 #define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
3535 #define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
3536 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
3537 #define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
3538 #define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
3539 #define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
3541 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
3542 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
3544 #define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
3545 #define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
3546 #define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
3547 #define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
3548 #define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
3549 #define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
3550 #define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
3551 #define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
3552 #define PIPECONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
3553 #define PIPECONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x))
3554 #define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16)
3555 #define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
3556 #define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13)
3557 #define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
3558 #define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
3559 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
3560 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
3561 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
3562 #define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
3563 #define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
3564 #define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
3565 #define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
3566 #define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
3567 #define PIPECONF_DITHER_EN REG_BIT(4)
3568 #define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
3569 #define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
3570 #define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
3571 #define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
3572 #define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
3573 #define _PIPEASTAT 0x70024
3574 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
3575 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
3576 #define PIPE_CRC_ERROR_ENABLE (1UL << 29)
3577 #define PIPE_CRC_DONE_ENABLE (1UL << 28)
3578 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
3579 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
3580 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
3581 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
3582 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
3583 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
3584 #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
3585 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
3586 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
3587 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
3588 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
3589 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
3590 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
3591 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
3592 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
3593 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
3594 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
3595 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
3596 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
3597 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
3598 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
3599 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
3600 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
3601 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
3602 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
3603 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
3604 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
3605 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
3606 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
3607 #define PIPE_DPST_EVENT_STATUS (1UL << 7)
3608 #define PIPE_A_PSR_STATUS_VLV (1UL << 6)
3609 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
3610 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
3611 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
3612 #define PIPE_B_PSR_STATUS_VLV (1UL << 3)
3613 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
3614 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
3615 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
3616 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
3617 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
3618 #define PIPE_HBLANK_INT_STATUS (1UL << 0)
3619 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
3621 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
3622 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
3624 #define PIPE_A_OFFSET 0x70000
3625 #define PIPE_B_OFFSET 0x71000
3626 #define PIPE_C_OFFSET 0x72000
3627 #define PIPE_D_OFFSET 0x73000
3628 #define CHV_PIPE_C_OFFSET 0x74000
3630 * There's actually no pipe EDP. Some pipe registers have
3631 * simply shifted from the pipe to the transcoder, while
3632 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
3633 * to access such registers in transcoder EDP.
3635 #define PIPE_EDP_OFFSET 0x7f000
3637 /* ICL DSI 0 and 1 */
3638 #define PIPE_DSI0_OFFSET 0x7b000
3639 #define PIPE_DSI1_OFFSET 0x7b800
3641 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
3642 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
3643 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
3644 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
3645 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
3647 #define _PIPEAGCMAX 0x70010
3648 #define _PIPEBGCMAX 0x71010
3649 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
3651 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
3652 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
3653 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
3655 #define _PIPE_MISC_A 0x70030
3656 #define _PIPE_MISC_B 0x71030
3657 #define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
3658 #define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
3659 #define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
3660 #define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
3661 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
3663 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
3664 * valid values of: 6, 8, 10 BPC.
3665 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
3668 #define PIPEMISC_BPC_MASK REG_GENMASK(7, 5)
3669 #define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
3670 #define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
3671 #define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
3672 #define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
3673 #define PIPEMISC_DITHER_ENABLE REG_BIT(4)
3674 #define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
3675 #define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
3676 #define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
3677 #define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
3678 #define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
3679 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
3681 #define _PIPE_MISC2_A 0x7002C
3682 #define _PIPE_MISC2_B 0x7102C
3683 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
3684 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
3685 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
3686 #define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A)
3688 /* Skylake+ pipe bottom (background) color */
3689 #define _SKL_BOTTOM_COLOR_A 0x70034
3690 #define _SKL_BOTTOM_COLOR_B 0x71034
3691 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
3692 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
3693 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
3695 #define _ICL_PIPE_A_STATUS 0x70058
3696 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
3697 #define PIPE_STATUS_UNDERRUN REG_BIT(31)
3698 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28)
3699 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)
3700 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
3702 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
3703 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
3704 #define PIPEB_HLINE_INT_EN REG_BIT(28)
3705 #define PIPEB_VBLANK_INT_EN REG_BIT(27)
3706 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
3707 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
3708 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
3709 #define PIPE_PSR_INT_EN REG_BIT(22)
3710 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
3711 #define PIPEA_HLINE_INT_EN REG_BIT(20)
3712 #define PIPEA_VBLANK_INT_EN REG_BIT(19)
3713 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
3714 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
3715 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
3716 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
3717 #define PIPEC_HLINE_INT_EN REG_BIT(12)
3718 #define PIPEC_VBLANK_INT_EN REG_BIT(11)
3719 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
3720 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
3721 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
3723 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
3724 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
3725 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
3726 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
3727 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
3728 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
3729 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
3730 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
3731 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
3732 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
3733 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
3734 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
3735 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
3736 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
3737 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
3738 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
3739 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
3740 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
3741 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
3742 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
3743 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
3744 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
3745 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
3746 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
3747 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
3748 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
3749 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
3750 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
3751 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
3753 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
3754 #define DSPARB_CSTART_MASK (0x7f << 7)
3755 #define DSPARB_CSTART_SHIFT 7
3756 #define DSPARB_BSTART_MASK (0x7f)
3757 #define DSPARB_BSTART_SHIFT 0
3758 #define DSPARB_BEND_SHIFT 9 /* on 855 */
3759 #define DSPARB_AEND_SHIFT 0
3760 #define DSPARB_SPRITEA_SHIFT_VLV 0
3761 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
3762 #define DSPARB_SPRITEB_SHIFT_VLV 8
3763 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
3764 #define DSPARB_SPRITEC_SHIFT_VLV 16
3765 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
3766 #define DSPARB_SPRITED_SHIFT_VLV 24
3767 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
3768 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
3769 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
3770 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
3771 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
3772 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
3773 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
3774 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
3775 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
3776 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
3777 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
3778 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
3779 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
3780 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
3781 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
3782 #define DSPARB_SPRITEE_SHIFT_VLV 0
3783 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
3784 #define DSPARB_SPRITEF_SHIFT_VLV 8
3785 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
3787 /* pnv/gen4/g4x/vlv/chv */
3788 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
3789 #define DSPFW_SR_SHIFT 23
3790 #define DSPFW_SR_MASK (0x1ff << 23)
3791 #define DSPFW_CURSORB_SHIFT 16
3792 #define DSPFW_CURSORB_MASK (0x3f << 16)
3793 #define DSPFW_PLANEB_SHIFT 8
3794 #define DSPFW_PLANEB_MASK (0x7f << 8)
3795 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
3796 #define DSPFW_PLANEA_SHIFT 0
3797 #define DSPFW_PLANEA_MASK (0x7f << 0)
3798 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
3799 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
3800 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
3801 #define DSPFW_FBC_SR_SHIFT 28
3802 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
3803 #define DSPFW_FBC_HPLL_SR_SHIFT 24
3804 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
3805 #define DSPFW_SPRITEB_SHIFT (16)
3806 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
3807 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
3808 #define DSPFW_CURSORA_SHIFT 8
3809 #define DSPFW_CURSORA_MASK (0x3f << 8)
3810 #define DSPFW_PLANEC_OLD_SHIFT 0
3811 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
3812 #define DSPFW_SPRITEA_SHIFT 0
3813 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
3814 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
3815 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
3816 #define DSPFW_HPLL_SR_EN (1 << 31)
3817 #define PINEVIEW_SELF_REFRESH_EN (1 << 30)
3818 #define DSPFW_CURSOR_SR_SHIFT 24
3819 #define DSPFW_CURSOR_SR_MASK (0x3f << 24)
3820 #define DSPFW_HPLL_CURSOR_SHIFT 16
3821 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
3822 #define DSPFW_HPLL_SR_SHIFT 0
3823 #define DSPFW_HPLL_SR_MASK (0x1ff << 0)
3826 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
3827 #define DSPFW_SPRITEB_WM1_SHIFT 16
3828 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
3829 #define DSPFW_CURSORA_WM1_SHIFT 8
3830 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
3831 #define DSPFW_SPRITEA_WM1_SHIFT 0
3832 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
3833 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
3834 #define DSPFW_PLANEB_WM1_SHIFT 24
3835 #define DSPFW_PLANEB_WM1_MASK (0xff << 24)
3836 #define DSPFW_PLANEA_WM1_SHIFT 16
3837 #define DSPFW_PLANEA_WM1_MASK (0xff << 16)
3838 #define DSPFW_CURSORB_WM1_SHIFT 8
3839 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
3840 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
3841 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
3842 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
3843 #define DSPFW_SR_WM1_SHIFT 0
3844 #define DSPFW_SR_WM1_MASK (0x1ff << 0)
3845 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
3846 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
3847 #define DSPFW_SPRITED_WM1_SHIFT 24
3848 #define DSPFW_SPRITED_WM1_MASK (0xff << 24)
3849 #define DSPFW_SPRITED_SHIFT 16
3850 #define DSPFW_SPRITED_MASK_VLV (0xff << 16)
3851 #define DSPFW_SPRITEC_WM1_SHIFT 8
3852 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
3853 #define DSPFW_SPRITEC_SHIFT 0
3854 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
3855 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
3856 #define DSPFW_SPRITEF_WM1_SHIFT 24
3857 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
3858 #define DSPFW_SPRITEF_SHIFT 16
3859 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
3860 #define DSPFW_SPRITEE_WM1_SHIFT 8
3861 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
3862 #define DSPFW_SPRITEE_SHIFT 0
3863 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
3864 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
3865 #define DSPFW_PLANEC_WM1_SHIFT 24
3866 #define DSPFW_PLANEC_WM1_MASK (0xff << 24)
3867 #define DSPFW_PLANEC_SHIFT 16
3868 #define DSPFW_PLANEC_MASK_VLV (0xff << 16)
3869 #define DSPFW_CURSORC_WM1_SHIFT 8
3870 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
3871 #define DSPFW_CURSORC_SHIFT 0
3872 #define DSPFW_CURSORC_MASK (0x3f << 0)
3874 /* vlv/chv high order bits */
3875 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
3876 #define DSPFW_SR_HI_SHIFT 24
3877 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
3878 #define DSPFW_SPRITEF_HI_SHIFT 23
3879 #define DSPFW_SPRITEF_HI_MASK (1 << 23)
3880 #define DSPFW_SPRITEE_HI_SHIFT 22
3881 #define DSPFW_SPRITEE_HI_MASK (1 << 22)
3882 #define DSPFW_PLANEC_HI_SHIFT 21
3883 #define DSPFW_PLANEC_HI_MASK (1 << 21)
3884 #define DSPFW_SPRITED_HI_SHIFT 20
3885 #define DSPFW_SPRITED_HI_MASK (1 << 20)
3886 #define DSPFW_SPRITEC_HI_SHIFT 16
3887 #define DSPFW_SPRITEC_HI_MASK (1 << 16)
3888 #define DSPFW_PLANEB_HI_SHIFT 12
3889 #define DSPFW_PLANEB_HI_MASK (1 << 12)
3890 #define DSPFW_SPRITEB_HI_SHIFT 8
3891 #define DSPFW_SPRITEB_HI_MASK (1 << 8)
3892 #define DSPFW_SPRITEA_HI_SHIFT 4
3893 #define DSPFW_SPRITEA_HI_MASK (1 << 4)
3894 #define DSPFW_PLANEA_HI_SHIFT 0
3895 #define DSPFW_PLANEA_HI_MASK (1 << 0)
3896 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
3897 #define DSPFW_SR_WM1_HI_SHIFT 24
3898 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
3899 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
3900 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
3901 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
3902 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
3903 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
3904 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
3905 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
3906 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
3907 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
3908 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
3909 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
3910 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
3911 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
3912 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
3913 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
3914 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
3915 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
3916 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
3918 /* drain latency register values*/
3919 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
3920 #define DDL_CURSOR_SHIFT 24
3921 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
3922 #define DDL_PLANE_SHIFT 0
3923 #define DDL_PRECISION_HIGH (1 << 7)
3924 #define DDL_PRECISION_LOW (0 << 7)
3925 #define DRAIN_LATENCY_MASK 0x7f
3927 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
3928 #define CBR_PND_DEADLINE_DISABLE (1 << 31)
3929 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
3931 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
3932 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
3934 /* FIFO watermark sizes etc */
3935 #define G4X_FIFO_LINE_SIZE 64
3936 #define I915_FIFO_LINE_SIZE 64
3937 #define I830_FIFO_LINE_SIZE 32
3939 #define VALLEYVIEW_FIFO_SIZE 255
3940 #define G4X_FIFO_SIZE 127
3941 #define I965_FIFO_SIZE 512
3942 #define I945_FIFO_SIZE 127
3943 #define I915_FIFO_SIZE 95
3944 #define I855GM_FIFO_SIZE 127 /* In cachelines */
3945 #define I830_FIFO_SIZE 95
3947 #define VALLEYVIEW_MAX_WM 0xff
3948 #define G4X_MAX_WM 0x3f
3949 #define I915_MAX_WM 0x3f
3951 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
3952 #define PINEVIEW_FIFO_LINE_SIZE 64
3953 #define PINEVIEW_MAX_WM 0x1ff
3954 #define PINEVIEW_DFT_WM 0x3f
3955 #define PINEVIEW_DFT_HPLLOFF_WM 0
3956 #define PINEVIEW_GUARD_WM 10
3957 #define PINEVIEW_CURSOR_FIFO 64
3958 #define PINEVIEW_CURSOR_MAX_WM 0x3f
3959 #define PINEVIEW_CURSOR_DFT_WM 0
3960 #define PINEVIEW_CURSOR_GUARD_WM 5
3962 #define VALLEYVIEW_CURSOR_MAX_WM 64
3963 #define I965_CURSOR_FIFO 64
3964 #define I965_CURSOR_MAX_WM 32
3965 #define I965_CURSOR_DFT_WM 8
3967 /* Watermark register definitions for SKL */
3968 #define _CUR_WM_A_0 0x70140
3969 #define _CUR_WM_B_0 0x71140
3970 #define _CUR_WM_SAGV_A 0x70158
3971 #define _CUR_WM_SAGV_B 0x71158
3972 #define _CUR_WM_SAGV_TRANS_A 0x7015C
3973 #define _CUR_WM_SAGV_TRANS_B 0x7115C
3974 #define _CUR_WM_TRANS_A 0x70168
3975 #define _CUR_WM_TRANS_B 0x71168
3976 #define _PLANE_WM_1_A_0 0x70240
3977 #define _PLANE_WM_1_B_0 0x71240
3978 #define _PLANE_WM_2_A_0 0x70340
3979 #define _PLANE_WM_2_B_0 0x71340
3980 #define _PLANE_WM_SAGV_1_A 0x70258
3981 #define _PLANE_WM_SAGV_1_B 0x71258
3982 #define _PLANE_WM_SAGV_2_A 0x70358
3983 #define _PLANE_WM_SAGV_2_B 0x71358
3984 #define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
3985 #define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
3986 #define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
3987 #define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
3988 #define _PLANE_WM_TRANS_1_A 0x70268
3989 #define _PLANE_WM_TRANS_1_B 0x71268
3990 #define _PLANE_WM_TRANS_2_A 0x70368
3991 #define _PLANE_WM_TRANS_2_B 0x71368
3992 #define PLANE_WM_EN (1 << 31)
3993 #define PLANE_WM_IGNORE_LINES (1 << 30)
3994 #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
3995 #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
3997 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
3998 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
3999 #define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
4000 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
4001 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
4002 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
4003 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
4004 #define _PLANE_WM_BASE(pipe, plane) \
4005 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4006 #define PLANE_WM(pipe, plane, level) \
4007 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4008 #define _PLANE_WM_SAGV_1(pipe) \
4009 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
4010 #define _PLANE_WM_SAGV_2(pipe) \
4011 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
4012 #define PLANE_WM_SAGV(pipe, plane) \
4013 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
4014 #define _PLANE_WM_SAGV_TRANS_1(pipe) \
4015 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
4016 #define _PLANE_WM_SAGV_TRANS_2(pipe) \
4017 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
4018 #define PLANE_WM_SAGV_TRANS(pipe, plane) \
4019 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
4020 #define _PLANE_WM_TRANS_1(pipe) \
4021 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
4022 #define _PLANE_WM_TRANS_2(pipe) \
4023 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
4024 #define PLANE_WM_TRANS(pipe, plane) \
4025 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
4027 /* define the Watermark register on Ironlake */
4028 #define _WM0_PIPEA_ILK 0x45100
4029 #define _WM0_PIPEB_ILK 0x45104
4030 #define _WM0_PIPEC_IVB 0x45200
4031 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
4032 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
4033 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
4034 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
4035 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
4036 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
4037 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
4038 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
4039 #define WM1_LP_ILK _MMIO(0x45108)
4040 #define WM2_LP_ILK _MMIO(0x4510c)
4041 #define WM3_LP_ILK _MMIO(0x45110)
4042 #define WM_LP_ENABLE REG_BIT(31)
4043 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
4044 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
4045 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
4046 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
4047 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
4048 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
4049 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
4050 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
4051 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
4052 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
4053 #define WM1S_LP_ILK _MMIO(0x45120)
4054 #define WM2S_LP_IVB _MMIO(0x45124)
4055 #define WM3S_LP_IVB _MMIO(0x45128)
4056 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
4057 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
4058 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
4061 * The two pipe frame counter registers are not synchronized, so
4062 * reading a stable value is somewhat tricky. The following code
4066 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4067 * PIPE_FRAME_HIGH_SHIFT;
4068 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4069 * PIPE_FRAME_LOW_SHIFT);
4070 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4071 * PIPE_FRAME_HIGH_SHIFT);
4072 * } while (high1 != high2);
4073 * frame = (high1 << 8) | low1;
4075 #define _PIPEAFRAMEHIGH 0x70040
4076 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
4077 #define PIPE_FRAME_HIGH_SHIFT 0
4078 #define _PIPEAFRAMEPIXEL 0x70044
4079 #define PIPE_FRAME_LOW_MASK 0xff000000
4080 #define PIPE_FRAME_LOW_SHIFT 24
4081 #define PIPE_PIXEL_MASK 0x00ffffff
4082 #define PIPE_PIXEL_SHIFT 0
4083 /* GM45+ just has to be different */
4084 #define _PIPEA_FRMCOUNT_G4X 0x70040
4085 #define _PIPEA_FLIPCOUNT_G4X 0x70044
4086 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
4087 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
4089 /* Cursor A & B regs */
4090 #define _CURACNTR 0x70080
4091 /* Old style CUR*CNTR flags (desktop 8xx) */
4092 #define CURSOR_ENABLE REG_BIT(31)
4093 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
4094 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
4095 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
4096 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
4097 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
4098 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
4099 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
4100 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
4101 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
4102 /* New style CUR*CNTR flags */
4103 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
4104 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
4105 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
4106 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
4107 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
4108 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
4109 #define MCURSOR_ROTATE_180 REG_BIT(15)
4110 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
4111 #define MCURSOR_MODE_MASK 0x27
4112 #define MCURSOR_MODE_DISABLE 0x00
4113 #define MCURSOR_MODE_128_32B_AX 0x02
4114 #define MCURSOR_MODE_256_32B_AX 0x03
4115 #define MCURSOR_MODE_64_32B_AX 0x07
4116 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
4117 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
4118 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
4119 #define _CURABASE 0x70084
4120 #define _CURAPOS 0x70088
4121 #define CURSOR_POS_Y_SIGN REG_BIT(31)
4122 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
4123 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
4124 #define CURSOR_POS_X_SIGN REG_BIT(15)
4125 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
4126 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
4127 #define _CURASIZE 0x700a0 /* 845/865 */
4128 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
4129 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
4130 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
4131 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
4132 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
4133 #define CUR_FBC_EN REG_BIT(31)
4134 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
4135 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
4136 #define _CURASURFLIVE 0x700ac /* g4x+ */
4137 #define _CURBCNTR 0x700c0
4138 #define _CURBBASE 0x700c4
4139 #define _CURBPOS 0x700c8
4141 #define _CURBCNTR_IVB 0x71080
4142 #define _CURBBASE_IVB 0x71084
4143 #define _CURBPOS_IVB 0x71088
4145 #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR)
4146 #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE)
4147 #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS)
4148 #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE)
4149 #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A)
4150 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
4152 #define CURSOR_A_OFFSET 0x70080
4153 #define CURSOR_B_OFFSET 0x700c0
4154 #define CHV_CURSOR_C_OFFSET 0x700e0
4155 #define IVB_CURSOR_B_OFFSET 0x71080
4156 #define IVB_CURSOR_C_OFFSET 0x72080
4157 #define TGL_CURSOR_D_OFFSET 0x73080
4159 /* Display A control */
4160 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */
4161 #define _DSPACNTR 0x70180
4162 #define DISP_ENABLE REG_BIT(31)
4163 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
4164 #define DISP_FORMAT_MASK REG_GENMASK(29, 26)
4165 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
4166 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
4167 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
4168 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
4169 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
4170 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
4171 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
4172 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
4173 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
4174 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
4175 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
4176 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
4177 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
4178 #define DISP_STEREO_ENABLE REG_BIT(25)
4179 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
4180 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
4181 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
4182 #define DISP_SRC_KEY_ENABLE REG_BIT(22)
4183 #define DISP_LINE_DOUBLE REG_BIT(20)
4184 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
4185 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
4186 #define DISP_ROTATE_180 REG_BIT(15)
4187 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
4188 #define DISP_TILED REG_BIT(10)
4189 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
4190 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
4191 #define _DSPAADDR 0x70184
4192 #define _DSPASTRIDE 0x70188
4193 #define _DSPAPOS 0x7018C /* reserved */
4194 #define DISP_POS_Y_MASK REG_GENMASK(31, 16)
4195 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
4196 #define DISP_POS_X_MASK REG_GENMASK(15, 0)
4197 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
4198 #define _DSPASIZE 0x70190
4199 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
4200 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
4201 #define DISP_WIDTH_MASK REG_GENMASK(15, 0)
4202 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
4203 #define _DSPASURF 0x7019C /* 965+ only */
4204 #define DISP_ADDR_MASK REG_GENMASK(31, 12)
4205 #define _DSPATILEOFF 0x701A4 /* 965+ only */
4206 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
4207 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
4208 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
4209 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
4210 #define _DSPAOFFSET 0x701A4 /* HSW */
4211 #define _DSPASURFLIVE 0x701AC
4212 #define _DSPAGAMC 0x701E0
4214 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV)
4215 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
4216 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
4217 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
4218 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
4219 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
4220 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
4221 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
4222 #define DSPLINOFF(plane) DSPADDR(plane)
4223 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
4224 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
4225 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
4227 /* CHV pipe B blender and primary plane */
4228 #define _CHV_BLEND_A 0x60a00
4229 #define CHV_BLEND_MASK REG_GENMASK(31, 30)
4230 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
4231 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
4232 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
4233 #define _CHV_CANVAS_A 0x60a04
4234 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
4235 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
4236 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
4237 #define _PRIMPOS_A 0x60a08
4238 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
4239 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
4240 #define PRIM_POS_X_MASK REG_GENMASK(15, 0)
4241 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
4242 #define _PRIMSIZE_A 0x60a0c
4243 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
4244 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
4245 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
4246 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
4247 #define _PRIMCNSTALPHA_A 0x60a10
4248 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
4249 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
4250 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
4252 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
4253 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
4254 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
4255 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
4256 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
4258 /* Display/Sprite base address macros */
4259 #define DISP_BASEADDR_MASK (0xfffff000)
4260 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
4261 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
4274 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
4275 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
4276 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
4277 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
4280 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
4281 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
4282 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
4283 #define _PIPEBFRAMEHIGH 0x71040
4284 #define _PIPEBFRAMEPIXEL 0x71044
4285 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
4286 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
4289 /* Display B control */
4290 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
4291 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15)
4292 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
4293 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
4294 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
4295 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
4296 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
4297 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
4298 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
4299 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
4300 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
4302 /* ICL DSI 0 and 1 */
4303 #define _PIPEDSI0CONF 0x7b008
4304 #define _PIPEDSI1CONF 0x7b808
4306 /* Sprite A control */
4307 #define _DVSACNTR 0x72180
4308 #define DVS_ENABLE REG_BIT(31)
4309 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
4310 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
4311 #define DVS_FORMAT_MASK REG_GENMASK(26, 25)
4312 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
4313 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
4314 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
4315 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
4316 #define DVS_PIPE_CSC_ENABLE REG_BIT(24)
4317 #define DVS_SOURCE_KEY REG_BIT(22)
4318 #define DVS_RGB_ORDER_XBGR REG_BIT(20)
4319 #define DVS_YUV_FORMAT_BT709 REG_BIT(18)
4320 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
4321 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
4322 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
4323 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
4324 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
4325 #define DVS_ROTATE_180 REG_BIT(15)
4326 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
4327 #define DVS_TILED REG_BIT(10)
4328 #define DVS_DEST_KEY REG_BIT(2)
4329 #define _DVSALINOFF 0x72184
4330 #define _DVSASTRIDE 0x72188
4331 #define _DVSAPOS 0x7218c
4332 #define DVS_POS_Y_MASK REG_GENMASK(31, 16)
4333 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
4334 #define DVS_POS_X_MASK REG_GENMASK(15, 0)
4335 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
4336 #define _DVSASIZE 0x72190
4337 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
4338 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
4339 #define DVS_WIDTH_MASK REG_GENMASK(15, 0)
4340 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
4341 #define _DVSAKEYVAL 0x72194
4342 #define _DVSAKEYMSK 0x72198
4343 #define _DVSASURF 0x7219c
4344 #define DVS_ADDR_MASK REG_GENMASK(31, 12)
4345 #define _DVSAKEYMAXVAL 0x721a0
4346 #define _DVSATILEOFF 0x721a4
4347 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
4348 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
4349 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
4350 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
4351 #define _DVSASURFLIVE 0x721ac
4352 #define _DVSAGAMC_G4X 0x721e0 /* g4x */
4353 #define _DVSASCALE 0x72204
4354 #define DVS_SCALE_ENABLE REG_BIT(31)
4355 #define DVS_FILTER_MASK REG_GENMASK(30, 29)
4356 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
4357 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
4358 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
4359 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
4360 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
4361 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
4362 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
4363 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
4364 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
4365 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
4366 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
4368 #define _DVSBCNTR 0x73180
4369 #define _DVSBLINOFF 0x73184
4370 #define _DVSBSTRIDE 0x73188
4371 #define _DVSBPOS 0x7318c
4372 #define _DVSBSIZE 0x73190
4373 #define _DVSBKEYVAL 0x73194
4374 #define _DVSBKEYMSK 0x73198
4375 #define _DVSBSURF 0x7319c
4376 #define _DVSBKEYMAXVAL 0x731a0
4377 #define _DVSBTILEOFF 0x731a4
4378 #define _DVSBSURFLIVE 0x731ac
4379 #define _DVSBGAMC_G4X 0x731e0 /* g4x */
4380 #define _DVSBSCALE 0x73204
4381 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
4382 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
4384 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
4385 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
4386 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
4387 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
4388 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
4389 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
4390 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
4391 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
4392 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
4393 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
4394 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
4395 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
4396 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
4397 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
4398 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
4400 #define _SPRA_CTL 0x70280
4401 #define SPRITE_ENABLE REG_BIT(31)
4402 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
4403 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4404 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
4405 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
4406 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
4407 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
4408 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
4409 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
4410 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
4411 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
4412 #define SPRITE_SOURCE_KEY REG_BIT(22)
4413 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
4414 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
4415 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
4416 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
4417 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
4418 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
4419 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
4420 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
4421 #define SPRITE_ROTATE_180 REG_BIT(15)
4422 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
4423 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
4424 #define SPRITE_TILED REG_BIT(10)
4425 #define SPRITE_DEST_KEY REG_BIT(2)
4426 #define _SPRA_LINOFF 0x70284
4427 #define _SPRA_STRIDE 0x70288
4428 #define _SPRA_POS 0x7028c
4429 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
4430 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
4431 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
4432 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
4433 #define _SPRA_SIZE 0x70290
4434 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
4435 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
4436 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
4437 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
4438 #define _SPRA_KEYVAL 0x70294
4439 #define _SPRA_KEYMSK 0x70298
4440 #define _SPRA_SURF 0x7029c
4441 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
4442 #define _SPRA_KEYMAX 0x702a0
4443 #define _SPRA_TILEOFF 0x702a4
4444 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
4445 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
4446 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
4447 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
4448 #define _SPRA_OFFSET 0x702a4
4449 #define _SPRA_SURFLIVE 0x702ac
4450 #define _SPRA_SCALE 0x70304
4451 #define SPRITE_SCALE_ENABLE REG_BIT(31)
4452 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
4453 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
4454 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
4455 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
4456 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
4457 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
4458 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
4459 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
4460 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
4461 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
4462 #define _SPRA_GAMC 0x70400
4463 #define _SPRA_GAMC16 0x70440
4464 #define _SPRA_GAMC17 0x7044c
4466 #define _SPRB_CTL 0x71280
4467 #define _SPRB_LINOFF 0x71284
4468 #define _SPRB_STRIDE 0x71288
4469 #define _SPRB_POS 0x7128c
4470 #define _SPRB_SIZE 0x71290
4471 #define _SPRB_KEYVAL 0x71294
4472 #define _SPRB_KEYMSK 0x71298
4473 #define _SPRB_SURF 0x7129c
4474 #define _SPRB_KEYMAX 0x712a0
4475 #define _SPRB_TILEOFF 0x712a4
4476 #define _SPRB_OFFSET 0x712a4
4477 #define _SPRB_SURFLIVE 0x712ac
4478 #define _SPRB_SCALE 0x71304
4479 #define _SPRB_GAMC 0x71400
4480 #define _SPRB_GAMC16 0x71440
4481 #define _SPRB_GAMC17 0x7144c
4483 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
4484 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
4485 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
4486 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
4487 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
4488 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
4489 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
4490 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
4491 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
4492 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
4493 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
4494 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
4495 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
4496 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
4497 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
4498 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
4500 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
4501 #define SP_ENABLE REG_BIT(31)
4502 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
4503 #define SP_FORMAT_MASK REG_GENMASK(29, 26)
4504 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
4505 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
4506 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
4507 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
4508 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
4509 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
4510 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
4511 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
4512 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
4513 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
4514 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
4515 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
4516 #define SP_SOURCE_KEY REG_BIT(22)
4517 #define SP_YUV_FORMAT_BT709 REG_BIT(18)
4518 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
4519 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
4520 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
4521 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
4522 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
4523 #define SP_ROTATE_180 REG_BIT(15)
4524 #define SP_TILED REG_BIT(10)
4525 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */
4526 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
4527 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
4528 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
4529 #define SP_POS_Y_MASK REG_GENMASK(31, 16)
4530 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
4531 #define SP_POS_X_MASK REG_GENMASK(15, 0)
4532 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
4533 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
4534 #define SP_HEIGHT_MASK REG_GENMASK(31, 16)
4535 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
4536 #define SP_WIDTH_MASK REG_GENMASK(15, 0)
4537 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
4538 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
4539 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
4540 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
4541 #define SP_ADDR_MASK REG_GENMASK(31, 12)
4542 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
4543 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
4544 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
4545 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
4546 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
4547 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
4548 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
4549 #define SP_CONST_ALPHA_ENABLE REG_BIT(31)
4550 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
4551 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
4552 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
4553 #define SP_CONTRAST_MASK REG_GENMASK(26, 18)
4554 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
4555 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
4556 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
4557 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
4558 #define SP_SH_SIN_MASK REG_GENMASK(26, 16)
4559 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
4560 #define SP_SH_COS_MASK REG_GENMASK(9, 0)
4561 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
4562 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
4564 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
4565 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
4566 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
4567 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
4568 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
4569 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
4570 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
4571 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
4572 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
4573 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
4574 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
4575 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
4576 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
4577 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
4579 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
4580 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
4581 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
4582 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
4584 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
4585 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
4586 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
4587 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
4588 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
4589 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
4590 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
4591 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
4592 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
4593 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
4594 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
4595 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
4596 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
4597 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
4600 * CHV pipe B sprite CSC
4602 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
4603 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
4604 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
4606 #define _MMIO_CHV_SPCSC(plane_id, reg) \
4607 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
4609 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
4610 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
4611 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
4612 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
4613 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
4614 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
4615 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
4617 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
4618 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
4619 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
4620 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
4621 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
4622 #define SPCSC_C1_MASK REG_GENMASK(30, 16)
4623 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
4624 #define SPCSC_C0_MASK REG_GENMASK(14, 0)
4625 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
4627 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
4628 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
4629 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
4630 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
4631 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
4632 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
4633 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
4635 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
4636 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
4637 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
4638 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
4639 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
4640 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
4641 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
4643 /* Skylake plane registers */
4645 #define _PLANE_CTL_1_A 0x70180
4646 #define _PLANE_CTL_2_A 0x70280
4647 #define _PLANE_CTL_3_A 0x70380
4648 #define PLANE_CTL_ENABLE REG_BIT(31)
4649 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
4650 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
4651 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
4652 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4654 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
4655 * expanded to include bit 23 as well. However, the shift-24 based values
4656 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
4658 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
4659 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
4660 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
4661 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
4662 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
4663 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
4664 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
4665 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
4666 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
4667 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
4668 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
4669 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
4670 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
4671 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
4672 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
4673 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
4674 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
4675 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
4676 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
4677 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
4678 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
4679 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
4680 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
4681 #define PLANE_CTL_ORDER_RGBX REG_BIT(20)
4682 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
4683 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
4684 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
4685 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
4686 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
4687 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
4688 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
4689 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
4690 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
4691 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
4692 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
4693 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
4694 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
4695 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
4696 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
4697 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
4698 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
4699 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
4700 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
4701 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
4702 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
4703 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
4704 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
4705 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
4706 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
4707 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
4708 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
4709 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
4710 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
4711 #define _PLANE_STRIDE_1_A 0x70188
4712 #define _PLANE_STRIDE_2_A 0x70288
4713 #define _PLANE_STRIDE_3_A 0x70388
4714 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
4715 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
4716 #define _PLANE_POS_1_A 0x7018c
4717 #define _PLANE_POS_2_A 0x7028c
4718 #define _PLANE_POS_3_A 0x7038c
4719 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
4720 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
4721 #define PLANE_POS_X_MASK REG_GENMASK(15, 0)
4722 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
4723 #define _PLANE_SIZE_1_A 0x70190
4724 #define _PLANE_SIZE_2_A 0x70290
4725 #define _PLANE_SIZE_3_A 0x70390
4726 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
4727 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
4728 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
4729 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
4730 #define _PLANE_SURF_1_A 0x7019c
4731 #define _PLANE_SURF_2_A 0x7029c
4732 #define _PLANE_SURF_3_A 0x7039c
4733 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
4734 #define PLANE_SURF_DECRYPT REG_BIT(2)
4735 #define _PLANE_OFFSET_1_A 0x701a4
4736 #define _PLANE_OFFSET_2_A 0x702a4
4737 #define _PLANE_OFFSET_3_A 0x703a4
4738 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
4739 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
4740 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
4741 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
4742 #define _PLANE_KEYVAL_1_A 0x70194
4743 #define _PLANE_KEYVAL_2_A 0x70294
4744 #define _PLANE_KEYMSK_1_A 0x70198
4745 #define _PLANE_KEYMSK_2_A 0x70298
4746 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
4747 #define _PLANE_KEYMAX_1_A 0x701a0
4748 #define _PLANE_KEYMAX_2_A 0x702a0
4749 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
4750 #define _PLANE_CC_VAL_1_A 0x701b4
4751 #define _PLANE_CC_VAL_2_A 0x702b4
4752 #define _PLANE_AUX_DIST_1_A 0x701c0
4753 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
4754 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
4755 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
4756 #define _PLANE_AUX_DIST_2_A 0x702c0
4757 #define _PLANE_AUX_OFFSET_1_A 0x701c4
4758 #define _PLANE_AUX_OFFSET_2_A 0x702c4
4759 #define _PLANE_CUS_CTL_1_A 0x701c8
4760 #define _PLANE_CUS_CTL_2_A 0x702c8
4761 #define PLANE_CUS_ENABLE REG_BIT(31)
4762 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
4763 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
4764 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
4765 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
4766 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
4767 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
4768 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
4769 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
4770 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
4771 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
4772 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
4773 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
4774 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
4775 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
4776 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
4777 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
4778 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
4779 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
4780 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
4781 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4782 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
4783 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
4784 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
4785 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
4786 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
4787 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
4788 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
4789 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
4790 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
4791 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
4792 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
4793 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
4794 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
4795 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
4796 #define _PLANE_BUF_CFG_1_A 0x7027c
4797 #define _PLANE_BUF_CFG_2_A 0x7037c
4798 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
4799 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
4801 #define _PLANE_CC_VAL_1_B 0x711b4
4802 #define _PLANE_CC_VAL_2_B 0x712b4
4803 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
4804 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
4805 #define PLANE_CC_VAL(pipe, plane, dw) \
4806 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
4808 /* Input CSC Register Definitions */
4809 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
4810 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
4812 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
4813 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
4815 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
4816 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
4817 _PLANE_INPUT_CSC_RY_GY_1_B)
4818 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
4819 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
4820 _PLANE_INPUT_CSC_RY_GY_2_B)
4822 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
4823 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
4824 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
4826 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
4827 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
4829 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
4830 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
4832 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
4833 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
4834 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
4835 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
4836 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
4837 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
4838 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
4839 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
4840 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
4842 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
4843 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
4845 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
4846 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
4848 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
4849 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
4850 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
4851 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
4852 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
4853 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
4854 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
4855 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
4856 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
4858 #define _PLANE_CTL_1_B 0x71180
4859 #define _PLANE_CTL_2_B 0x71280
4860 #define _PLANE_CTL_3_B 0x71380
4861 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
4862 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
4863 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
4864 #define PLANE_CTL(pipe, plane) \
4865 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
4867 #define _PLANE_STRIDE_1_B 0x71188
4868 #define _PLANE_STRIDE_2_B 0x71288
4869 #define _PLANE_STRIDE_3_B 0x71388
4870 #define _PLANE_STRIDE_1(pipe) \
4871 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
4872 #define _PLANE_STRIDE_2(pipe) \
4873 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
4874 #define _PLANE_STRIDE_3(pipe) \
4875 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
4876 #define PLANE_STRIDE(pipe, plane) \
4877 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
4879 #define _PLANE_POS_1_B 0x7118c
4880 #define _PLANE_POS_2_B 0x7128c
4881 #define _PLANE_POS_3_B 0x7138c
4882 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
4883 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
4884 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
4885 #define PLANE_POS(pipe, plane) \
4886 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
4888 #define _PLANE_SIZE_1_B 0x71190
4889 #define _PLANE_SIZE_2_B 0x71290
4890 #define _PLANE_SIZE_3_B 0x71390
4891 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
4892 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
4893 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
4894 #define PLANE_SIZE(pipe, plane) \
4895 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
4897 #define _PLANE_SURF_1_B 0x7119c
4898 #define _PLANE_SURF_2_B 0x7129c
4899 #define _PLANE_SURF_3_B 0x7139c
4900 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
4901 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
4902 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
4903 #define PLANE_SURF(pipe, plane) \
4904 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
4906 #define _PLANE_OFFSET_1_B 0x711a4
4907 #define _PLANE_OFFSET_2_B 0x712a4
4908 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
4909 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
4910 #define PLANE_OFFSET(pipe, plane) \
4911 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
4913 #define _PLANE_KEYVAL_1_B 0x71194
4914 #define _PLANE_KEYVAL_2_B 0x71294
4915 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
4916 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
4917 #define PLANE_KEYVAL(pipe, plane) \
4918 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
4920 #define _PLANE_KEYMSK_1_B 0x71198
4921 #define _PLANE_KEYMSK_2_B 0x71298
4922 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
4923 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
4924 #define PLANE_KEYMSK(pipe, plane) \
4925 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
4927 #define _PLANE_KEYMAX_1_B 0x711a0
4928 #define _PLANE_KEYMAX_2_B 0x712a0
4929 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
4930 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
4931 #define PLANE_KEYMAX(pipe, plane) \
4932 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
4934 #define _PLANE_BUF_CFG_1_B 0x7127c
4935 #define _PLANE_BUF_CFG_2_B 0x7137c
4936 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
4937 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
4938 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
4939 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
4940 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
4941 #define _PLANE_BUF_CFG_1(pipe) \
4942 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
4943 #define _PLANE_BUF_CFG_2(pipe) \
4944 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
4945 #define PLANE_BUF_CFG(pipe, plane) \
4946 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
4948 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
4949 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
4950 #define _PLANE_NV12_BUF_CFG_1(pipe) \
4951 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
4952 #define _PLANE_NV12_BUF_CFG_2(pipe) \
4953 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
4954 #define PLANE_NV12_BUF_CFG(pipe, plane) \
4955 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
4957 #define _PLANE_AUX_DIST_1_B 0x711c0
4958 #define _PLANE_AUX_DIST_2_B 0x712c0
4959 #define _PLANE_AUX_DIST_1(pipe) \
4960 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
4961 #define _PLANE_AUX_DIST_2(pipe) \
4962 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
4963 #define PLANE_AUX_DIST(pipe, plane) \
4964 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
4966 #define _PLANE_AUX_OFFSET_1_B 0x711c4
4967 #define _PLANE_AUX_OFFSET_2_B 0x712c4
4968 #define _PLANE_AUX_OFFSET_1(pipe) \
4969 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
4970 #define _PLANE_AUX_OFFSET_2(pipe) \
4971 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
4972 #define PLANE_AUX_OFFSET(pipe, plane) \
4973 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
4975 #define _PLANE_CUS_CTL_1_B 0x711c8
4976 #define _PLANE_CUS_CTL_2_B 0x712c8
4977 #define _PLANE_CUS_CTL_1(pipe) \
4978 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
4979 #define _PLANE_CUS_CTL_2(pipe) \
4980 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
4981 #define PLANE_CUS_CTL(pipe, plane) \
4982 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
4984 #define _PLANE_COLOR_CTL_1_B 0x711CC
4985 #define _PLANE_COLOR_CTL_2_B 0x712CC
4986 #define _PLANE_COLOR_CTL_3_B 0x713CC
4987 #define _PLANE_COLOR_CTL_1(pipe) \
4988 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
4989 #define _PLANE_COLOR_CTL_2(pipe) \
4990 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
4991 #define PLANE_COLOR_CTL(pipe, plane) \
4992 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
4994 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890
4995 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
4996 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
4997 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0
4998 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920
4999 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940
5000 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960
5001 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
5002 #define _SEL_FETCH_PLANE_BASE_1_B 0x71890
5004 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
5005 _SEL_FETCH_PLANE_BASE_1_A, \
5006 _SEL_FETCH_PLANE_BASE_2_A, \
5007 _SEL_FETCH_PLANE_BASE_3_A, \
5008 _SEL_FETCH_PLANE_BASE_4_A, \
5009 _SEL_FETCH_PLANE_BASE_5_A, \
5010 _SEL_FETCH_PLANE_BASE_6_A, \
5011 _SEL_FETCH_PLANE_BASE_7_A, \
5012 _SEL_FETCH_PLANE_BASE_CUR_A)
5013 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
5014 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
5015 _SEL_FETCH_PLANE_BASE_1_A + \
5016 _SEL_FETCH_PLANE_BASE_A(plane))
5018 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890
5019 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
5020 _SEL_FETCH_PLANE_CTL_1_A - \
5021 _SEL_FETCH_PLANE_BASE_1_A)
5022 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
5024 #define _SEL_FETCH_PLANE_POS_1_A 0x70894
5025 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
5026 _SEL_FETCH_PLANE_POS_1_A - \
5027 _SEL_FETCH_PLANE_BASE_1_A)
5029 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
5030 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
5031 _SEL_FETCH_PLANE_SIZE_1_A - \
5032 _SEL_FETCH_PLANE_BASE_1_A)
5034 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
5035 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
5036 _SEL_FETCH_PLANE_OFFSET_1_A - \
5037 _SEL_FETCH_PLANE_BASE_1_A)
5039 /* SKL new cursor registers */
5040 #define _CUR_BUF_CFG_A 0x7017c
5041 #define _CUR_BUF_CFG_B 0x7117c
5042 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
5045 #define VGACNTRL _MMIO(0x71400)
5046 # define VGA_DISP_DISABLE (1 << 31)
5047 # define VGA_2X_MODE (1 << 30)
5048 # define VGA_PIPE_B_SELECT (1 << 29)
5050 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
5054 #define CPU_VGACNTRL _MMIO(0x41000)
5056 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
5057 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
5058 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
5059 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
5060 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
5061 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
5062 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
5063 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
5064 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
5065 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
5066 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
5068 /* refresh rate hardware control */
5069 #define RR_HW_CTL _MMIO(0x45300)
5070 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
5071 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
5073 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
5074 #define FDI_PLL_FB_CLOCK_MASK 0xff
5075 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
5076 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
5077 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
5078 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
5079 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
5081 #define PCH_3DCGDIS0 _MMIO(0x46020)
5082 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
5083 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
5085 #define PCH_3DCGDIS1 _MMIO(0x46024)
5086 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
5088 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
5089 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
5090 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
5091 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
5094 #define _PIPEA_DATA_M1 0x60030
5095 #define _PIPEA_DATA_N1 0x60034
5096 #define _PIPEA_DATA_M2 0x60038
5097 #define _PIPEA_DATA_N2 0x6003c
5098 #define _PIPEA_LINK_M1 0x60040
5099 #define _PIPEA_LINK_N1 0x60044
5100 #define _PIPEA_LINK_M2 0x60048
5101 #define _PIPEA_LINK_N2 0x6004c
5103 /* PIPEB timing regs are same start from 0x61000 */
5105 #define _PIPEB_DATA_M1 0x61030
5106 #define _PIPEB_DATA_N1 0x61034
5107 #define _PIPEB_DATA_M2 0x61038
5108 #define _PIPEB_DATA_N2 0x6103c
5109 #define _PIPEB_LINK_M1 0x61040
5110 #define _PIPEB_LINK_N1 0x61044
5111 #define _PIPEB_LINK_M2 0x61048
5112 #define _PIPEB_LINK_N2 0x6104c
5114 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
5115 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
5116 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
5117 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
5118 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
5119 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
5120 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
5121 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
5123 /* CPU panel fitter */
5124 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5125 #define _PFA_CTL_1 0x68080
5126 #define _PFB_CTL_1 0x68880
5127 #define PF_ENABLE (1 << 31)
5128 #define PF_PIPE_SEL_MASK_IVB (3 << 29)
5129 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
5130 #define PF_FILTER_MASK (3 << 23)
5131 #define PF_FILTER_PROGRAMMED (0 << 23)
5132 #define PF_FILTER_MED_3x3 (1 << 23)
5133 #define PF_FILTER_EDGE_ENHANCE (2 << 23)
5134 #define PF_FILTER_EDGE_SOFTEN (3 << 23)
5135 #define _PFA_WIN_SZ 0x68074
5136 #define _PFB_WIN_SZ 0x68874
5137 #define _PFA_WIN_POS 0x68070
5138 #define _PFB_WIN_POS 0x68870
5139 #define _PFA_VSCALE 0x68084
5140 #define _PFB_VSCALE 0x68884
5141 #define _PFA_HSCALE 0x68090
5142 #define _PFB_HSCALE 0x68890
5144 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5145 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5146 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5147 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5148 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
5150 #define _PSA_CTL 0x68180
5151 #define _PSB_CTL 0x68980
5152 #define PS_ENABLE (1 << 31)
5153 #define _PSA_WIN_SZ 0x68174
5154 #define _PSB_WIN_SZ 0x68974
5155 #define _PSA_WIN_POS 0x68170
5156 #define _PSB_WIN_POS 0x68970
5158 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
5159 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5160 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5165 #define _PS_1A_CTRL 0x68180
5166 #define _PS_2A_CTRL 0x68280
5167 #define _PS_1B_CTRL 0x68980
5168 #define _PS_2B_CTRL 0x68A80
5169 #define _PS_1C_CTRL 0x69180
5170 #define PS_SCALER_EN (1 << 31)
5171 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
5172 #define SKL_PS_SCALER_MODE_DYN (0 << 28)
5173 #define SKL_PS_SCALER_MODE_HQ (1 << 28)
5174 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
5175 #define PS_SCALER_MODE_PLANAR (1 << 29)
5176 #define PS_SCALER_MODE_NORMAL (0 << 29)
5177 #define PS_PLANE_SEL_MASK (7 << 25)
5178 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
5179 #define PS_FILTER_MASK (3 << 23)
5180 #define PS_FILTER_MEDIUM (0 << 23)
5181 #define PS_FILTER_PROGRAMMED (1 << 23)
5182 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
5183 #define PS_FILTER_BILINEAR (3 << 23)
5184 #define PS_VERT3TAP (1 << 21)
5185 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5186 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
5187 #define PS_PWRUP_PROGRESS (1 << 17)
5188 #define PS_V_FILTER_BYPASS (1 << 8)
5189 #define PS_VADAPT_EN (1 << 7)
5190 #define PS_VADAPT_MODE_MASK (3 << 5)
5191 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5192 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
5193 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
5194 #define PS_PLANE_Y_SEL_MASK (7 << 5)
5195 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
5196 #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
5197 #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
5198 #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
5199 #define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1)
5201 #define _PS_PWR_GATE_1A 0x68160
5202 #define _PS_PWR_GATE_2A 0x68260
5203 #define _PS_PWR_GATE_1B 0x68960
5204 #define _PS_PWR_GATE_2B 0x68A60
5205 #define _PS_PWR_GATE_1C 0x69160
5206 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
5207 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
5208 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
5209 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
5210 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
5211 #define PS_PWR_GATE_SLPEN_8 0
5212 #define PS_PWR_GATE_SLPEN_16 1
5213 #define PS_PWR_GATE_SLPEN_24 2
5214 #define PS_PWR_GATE_SLPEN_32 3
5216 #define _PS_WIN_POS_1A 0x68170
5217 #define _PS_WIN_POS_2A 0x68270
5218 #define _PS_WIN_POS_1B 0x68970
5219 #define _PS_WIN_POS_2B 0x68A70
5220 #define _PS_WIN_POS_1C 0x69170
5222 #define _PS_WIN_SZ_1A 0x68174
5223 #define _PS_WIN_SZ_2A 0x68274
5224 #define _PS_WIN_SZ_1B 0x68974
5225 #define _PS_WIN_SZ_2B 0x68A74
5226 #define _PS_WIN_SZ_1C 0x69174
5228 #define _PS_VSCALE_1A 0x68184
5229 #define _PS_VSCALE_2A 0x68284
5230 #define _PS_VSCALE_1B 0x68984
5231 #define _PS_VSCALE_2B 0x68A84
5232 #define _PS_VSCALE_1C 0x69184
5234 #define _PS_HSCALE_1A 0x68190
5235 #define _PS_HSCALE_2A 0x68290
5236 #define _PS_HSCALE_1B 0x68990
5237 #define _PS_HSCALE_2B 0x68A90
5238 #define _PS_HSCALE_1C 0x69190
5240 #define _PS_VPHASE_1A 0x68188
5241 #define _PS_VPHASE_2A 0x68288
5242 #define _PS_VPHASE_1B 0x68988
5243 #define _PS_VPHASE_2B 0x68A88
5244 #define _PS_VPHASE_1C 0x69188
5245 #define PS_Y_PHASE(x) ((x) << 16)
5246 #define PS_UV_RGB_PHASE(x) ((x) << 0)
5247 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
5248 #define PS_PHASE_TRIP (1 << 0)
5250 #define _PS_HPHASE_1A 0x68194
5251 #define _PS_HPHASE_2A 0x68294
5252 #define _PS_HPHASE_1B 0x68994
5253 #define _PS_HPHASE_2B 0x68A94
5254 #define _PS_HPHASE_1C 0x69194
5256 #define _PS_ECC_STAT_1A 0x681D0
5257 #define _PS_ECC_STAT_2A 0x682D0
5258 #define _PS_ECC_STAT_1B 0x689D0
5259 #define _PS_ECC_STAT_2B 0x68AD0
5260 #define _PS_ECC_STAT_1C 0x691D0
5262 #define _PS_COEF_SET0_INDEX_1A 0x68198
5263 #define _PS_COEF_SET0_INDEX_2A 0x68298
5264 #define _PS_COEF_SET0_INDEX_1B 0x68998
5265 #define _PS_COEF_SET0_INDEX_2B 0x68A98
5266 #define PS_COEE_INDEX_AUTO_INC (1 << 10)
5268 #define _PS_COEF_SET0_DATA_1A 0x6819C
5269 #define _PS_COEF_SET0_DATA_2A 0x6829C
5270 #define _PS_COEF_SET0_DATA_1B 0x6899C
5271 #define _PS_COEF_SET0_DATA_2B 0x68A9C
5273 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
5274 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
5275 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
5276 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
5277 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
5278 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5279 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
5280 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
5281 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5282 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
5283 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
5284 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
5285 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
5286 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
5287 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
5288 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
5289 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
5290 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
5291 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
5292 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
5293 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
5294 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
5295 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
5296 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
5297 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
5298 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
5299 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
5300 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
5301 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
5302 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
5303 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
5305 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
5306 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
5307 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
5308 /* legacy palette */
5309 #define _LGC_PALETTE_A 0x4a000
5310 #define _LGC_PALETTE_B 0x4a800
5311 /* see PALETTE_* for the bits */
5312 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
5314 /* ilk/snb precision palette */
5315 #define _PREC_PALETTE_A 0x4b000
5316 #define _PREC_PALETTE_B 0x4c000
5318 #define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20)
5319 #define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10)
5320 #define PREC_PALETTE_10_BLUE_MASK REG_GENMASK(9, 0)
5321 /* 12.4 interpolated mode ldw */
5322 #define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24)
5323 #define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14)
5324 #define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4)
5325 /* 12.4 interpolated mode udw */
5326 #define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20)
5327 #define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10)
5328 #define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0)
5329 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
5331 #define _PREC_PIPEAGCMAX 0x4d000
5332 #define _PREC_PIPEBGCMAX 0x4d010
5333 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
5335 #define _GAMMA_MODE_A 0x4a480
5336 #define _GAMMA_MODE_B 0x4ac80
5337 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5338 #define PRE_CSC_GAMMA_ENABLE (1 << 31)
5339 #define POST_CSC_GAMMA_ENABLE (1 << 30)
5340 #define GAMMA_MODE_MODE_MASK (3 << 0)
5341 #define GAMMA_MODE_MODE_8BIT (0 << 0)
5342 #define GAMMA_MODE_MODE_10BIT (1 << 0)
5343 #define GAMMA_MODE_MODE_12BIT (2 << 0)
5344 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
5345 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
5347 /* Display Internal Timeout Register */
5348 #define RM_TIMEOUT _MMIO(0x42060)
5349 #define MMIO_TIMEOUT_US(us) ((us) << 0)
5352 #define DE_MASTER_IRQ_CONTROL (1 << 31)
5353 #define DE_SPRITEB_FLIP_DONE (1 << 29)
5354 #define DE_SPRITEA_FLIP_DONE (1 << 28)
5355 #define DE_PLANEB_FLIP_DONE (1 << 27)
5356 #define DE_PLANEA_FLIP_DONE (1 << 26)
5357 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
5358 #define DE_PCU_EVENT (1 << 25)
5359 #define DE_GTT_FAULT (1 << 24)
5360 #define DE_POISON (1 << 23)
5361 #define DE_PERFORM_COUNTER (1 << 22)
5362 #define DE_PCH_EVENT (1 << 21)
5363 #define DE_AUX_CHANNEL_A (1 << 20)
5364 #define DE_DP_A_HOTPLUG (1 << 19)
5365 #define DE_GSE (1 << 18)
5366 #define DE_PIPEB_VBLANK (1 << 15)
5367 #define DE_PIPEB_EVEN_FIELD (1 << 14)
5368 #define DE_PIPEB_ODD_FIELD (1 << 13)
5369 #define DE_PIPEB_LINE_COMPARE (1 << 12)
5370 #define DE_PIPEB_VSYNC (1 << 11)
5371 #define DE_PIPEB_CRC_DONE (1 << 10)
5372 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
5373 #define DE_PIPEA_VBLANK (1 << 7)
5374 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
5375 #define DE_PIPEA_EVEN_FIELD (1 << 6)
5376 #define DE_PIPEA_ODD_FIELD (1 << 5)
5377 #define DE_PIPEA_LINE_COMPARE (1 << 4)
5378 #define DE_PIPEA_VSYNC (1 << 3)
5379 #define DE_PIPEA_CRC_DONE (1 << 2)
5380 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
5381 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
5382 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
5384 /* More Ivybridge lolz */
5385 #define DE_ERR_INT_IVB (1 << 30)
5386 #define DE_GSE_IVB (1 << 29)
5387 #define DE_PCH_EVENT_IVB (1 << 28)
5388 #define DE_DP_A_HOTPLUG_IVB (1 << 27)
5389 #define DE_AUX_CHANNEL_A_IVB (1 << 26)
5390 #define DE_EDP_PSR_INT_HSW (1 << 19)
5391 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
5392 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
5393 #define DE_PIPEC_VBLANK_IVB (1 << 10)
5394 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
5395 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
5396 #define DE_PIPEB_VBLANK_IVB (1 << 5)
5397 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
5398 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
5399 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
5400 #define DE_PIPEA_VBLANK_IVB (1 << 0)
5401 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
5403 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
5404 #define MASTER_INTERRUPT_ENABLE (1 << 31)
5406 #define DEISR _MMIO(0x44000)
5407 #define DEIMR _MMIO(0x44004)
5408 #define DEIIR _MMIO(0x44008)
5409 #define DEIER _MMIO(0x4400c)
5411 #define GTISR _MMIO(0x44010)
5412 #define GTIMR _MMIO(0x44014)
5413 #define GTIIR _MMIO(0x44018)
5414 #define GTIER _MMIO(0x4401c)
5416 #define GEN8_MASTER_IRQ _MMIO(0x44200)
5417 #define GEN8_MASTER_IRQ_CONTROL (1 << 31)
5418 #define GEN8_PCU_IRQ (1 << 30)
5419 #define GEN8_DE_PCH_IRQ (1 << 23)
5420 #define GEN8_DE_MISC_IRQ (1 << 22)
5421 #define GEN8_DE_PORT_IRQ (1 << 20)
5422 #define GEN8_DE_PIPE_C_IRQ (1 << 18)
5423 #define GEN8_DE_PIPE_B_IRQ (1 << 17)
5424 #define GEN8_DE_PIPE_A_IRQ (1 << 16)
5425 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
5426 #define GEN8_GT_VECS_IRQ (1 << 6)
5427 #define GEN8_GT_GUC_IRQ (1 << 5)
5428 #define GEN8_GT_PM_IRQ (1 << 4)
5429 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
5430 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
5431 #define GEN8_GT_BCS_IRQ (1 << 1)
5432 #define GEN8_GT_RCS_IRQ (1 << 0)
5434 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
5436 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
5437 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
5438 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
5439 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
5441 #define GEN8_RCS_IRQ_SHIFT 0
5442 #define GEN8_BCS_IRQ_SHIFT 16
5443 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
5444 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
5445 #define GEN8_VECS_IRQ_SHIFT 0
5446 #define GEN8_WD_IRQ_SHIFT 16
5448 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
5449 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
5450 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
5451 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
5452 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
5453 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5454 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
5455 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22)
5456 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21)
5457 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
5458 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
5459 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
5460 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
5461 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
5462 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
5463 #define GEN8_PIPE_VSYNC (1 << 1)
5464 #define GEN8_PIPE_VBLANK (1 << 0)
5465 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
5466 #define GEN11_PIPE_PLANE7_FAULT (1 << 22)
5467 #define GEN11_PIPE_PLANE6_FAULT (1 << 21)
5468 #define GEN11_PIPE_PLANE5_FAULT (1 << 20)
5469 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
5470 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
5471 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
5472 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
5473 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
5474 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
5475 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
5476 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
5477 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
5478 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5479 (GEN8_PIPE_CURSOR_FAULT | \
5480 GEN8_PIPE_SPRITE_FAULT | \
5481 GEN8_PIPE_PRIMARY_FAULT)
5482 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5483 (GEN9_PIPE_CURSOR_FAULT | \
5484 GEN9_PIPE_PLANE4_FAULT | \
5485 GEN9_PIPE_PLANE3_FAULT | \
5486 GEN9_PIPE_PLANE2_FAULT | \
5487 GEN9_PIPE_PLANE1_FAULT)
5488 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
5489 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
5490 GEN11_PIPE_PLANE7_FAULT | \
5491 GEN11_PIPE_PLANE6_FAULT | \
5492 GEN11_PIPE_PLANE5_FAULT)
5493 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
5494 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
5495 GEN11_PIPE_PLANE5_FAULT)
5497 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
5498 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
5500 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
5501 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
5502 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
5503 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
5504 #define DSI1_NON_TE (1 << 31)
5505 #define DSI0_NON_TE (1 << 30)
5506 #define ICL_AUX_CHANNEL_E (1 << 29)
5507 #define ICL_AUX_CHANNEL_F (1 << 28)
5508 #define GEN9_AUX_CHANNEL_D (1 << 27)
5509 #define GEN9_AUX_CHANNEL_C (1 << 26)
5510 #define GEN9_AUX_CHANNEL_B (1 << 25)
5511 #define DSI1_TE (1 << 24)
5512 #define DSI0_TE (1 << 23)
5513 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
5514 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
5515 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
5516 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
5517 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
5518 #define BXT_DE_PORT_GMBUS (1 << 1)
5519 #define GEN8_AUX_CHANNEL_A (1 << 0)
5520 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
5521 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
5522 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
5523 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
5524 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
5525 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
5526 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
5527 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
5528 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
5529 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
5530 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
5532 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
5533 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
5534 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
5535 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
5536 #define GEN8_DE_MISC_GSE (1 << 27)
5537 #define GEN8_DE_EDP_PSR (1 << 19)
5539 #define GEN8_PCU_ISR _MMIO(0x444e0)
5540 #define GEN8_PCU_IMR _MMIO(0x444e4)
5541 #define GEN8_PCU_IIR _MMIO(0x444e8)
5542 #define GEN8_PCU_IER _MMIO(0x444ec)
5544 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
5545 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
5546 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
5547 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
5548 #define GEN11_GU_MISC_GSE (1 << 27)
5550 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
5551 #define GEN11_MASTER_IRQ (1 << 31)
5552 #define GEN11_PCU_IRQ (1 << 30)
5553 #define GEN11_GU_MISC_IRQ (1 << 29)
5554 #define GEN11_DISPLAY_IRQ (1 << 16)
5555 #define GEN11_GT_DW_IRQ(x) (1 << (x))
5556 #define GEN11_GT_DW1_IRQ (1 << 1)
5557 #define GEN11_GT_DW0_IRQ (1 << 0)
5559 #define DG1_MSTR_TILE_INTR _MMIO(0x190008)
5560 #define DG1_MSTR_IRQ REG_BIT(31)
5561 #define DG1_MSTR_TILE(t) REG_BIT(t)
5563 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
5564 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
5565 #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
5566 #define GEN11_DE_PCH_IRQ (1 << 23)
5567 #define GEN11_DE_MISC_IRQ (1 << 22)
5568 #define GEN11_DE_HPD_IRQ (1 << 21)
5569 #define GEN11_DE_PORT_IRQ (1 << 20)
5570 #define GEN11_DE_PIPE_C (1 << 18)
5571 #define GEN11_DE_PIPE_B (1 << 17)
5572 #define GEN11_DE_PIPE_A (1 << 16)
5574 #define GEN11_DE_HPD_ISR _MMIO(0x44470)
5575 #define GEN11_DE_HPD_IMR _MMIO(0x44474)
5576 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
5577 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
5578 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
5579 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
5580 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
5581 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
5582 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
5583 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
5584 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
5585 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
5586 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
5587 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
5588 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
5589 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
5590 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
5591 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
5593 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
5594 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
5595 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
5596 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
5597 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
5598 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
5600 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
5601 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
5602 #define ILK_ELPIN_409_SELECT (1 << 25)
5603 #define ILK_DPARB_GATE (1 << 22)
5604 #define ILK_VSDPFD_FULL (1 << 21)
5605 #define FUSE_STRAP _MMIO(0x42014)
5606 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
5607 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
5608 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
5609 #define IVB_PIPE_C_DISABLE (1 << 28)
5610 #define ILK_HDCP_DISABLE (1 << 25)
5611 #define ILK_eDP_A_DISABLE (1 << 24)
5612 #define HSW_CDCLK_LIMIT (1 << 24)
5613 #define ILK_DESKTOP (1 << 23)
5614 #define HSW_CPU_SSC_ENABLE (1 << 21)
5616 #define FUSE_STRAP3 _MMIO(0x42020)
5617 #define HSW_REF_CLK_SELECT (1 << 1)
5619 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
5620 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
5621 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
5622 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
5623 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
5624 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
5626 #define IVB_CHICKEN3 _MMIO(0x4200c)
5627 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
5628 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
5630 #define CHICKEN_PAR1_1 _MMIO(0x42080)
5631 #define IGNORE_KVMR_PIPE_A REG_BIT(23)
5632 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
5633 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
5634 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
5635 #define DPA_MASK_VBLANK_SRD (1 << 15)
5636 #define FORCE_ARB_IDLE_PLANES (1 << 14)
5637 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
5638 #define IGNORE_PSR2_HW_TRACKING (1 << 1)
5640 #define CHICKEN_PAR2_1 _MMIO(0x42090)
5641 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
5643 #define CHICKEN_MISC_2 _MMIO(0x42084)
5644 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
5645 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
5646 #define GLK_CL2_PWR_DOWN (1 << 12)
5647 #define GLK_CL1_PWR_DOWN (1 << 11)
5648 #define GLK_CL0_PWR_DOWN (1 << 10)
5650 #define CHICKEN_MISC_4 _MMIO(0x4208c)
5651 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
5652 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
5653 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
5655 #define _CHICKEN_PIPESL_1_A 0x420b0
5656 #define _CHICKEN_PIPESL_1_B 0x420b4
5657 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
5658 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
5659 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
5660 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
5661 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
5662 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
5663 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
5664 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
5665 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
5666 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
5667 #define HSW_FBCQ_DIS (1 << 22)
5668 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
5669 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
5670 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
5671 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
5672 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
5673 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
5674 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5676 #define _CHICKEN_TRANS_A 0x420c0
5677 #define _CHICKEN_TRANS_B 0x420c4
5678 #define _CHICKEN_TRANS_C 0x420c8
5679 #define _CHICKEN_TRANS_EDP 0x420cc
5680 #define _CHICKEN_TRANS_D 0x420d8
5681 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
5682 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
5683 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
5684 [TRANSCODER_B] = _CHICKEN_TRANS_B, \
5685 [TRANSCODER_C] = _CHICKEN_TRANS_C, \
5686 [TRANSCODER_D] = _CHICKEN_TRANS_D))
5688 #define _MTL_CHICKEN_TRANS_A 0x604e0
5689 #define _MTL_CHICKEN_TRANS_B 0x614e0
5690 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
5691 _MTL_CHICKEN_TRANS_A, \
5692 _MTL_CHICKEN_TRANS_B)
5694 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
5695 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
5696 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
5697 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
5698 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
5699 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
5700 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
5701 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
5702 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
5703 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
5704 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
5706 #define DISP_ARB_CTL _MMIO(0x45000)
5707 #define DISP_FBC_MEMORY_WAKE (1 << 31)
5708 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13)
5709 #define DISP_FBC_WM_DIS (1 << 15)
5710 #define DISP_ARB_CTL2 _MMIO(0x45004)
5711 #define DISP_DATA_PARTITION_5_6 (1 << 6)
5712 #define DISP_IPC_ENABLE (1 << 3)
5715 * The below are numbered starting from "S1" on gen11/gen12, but starting
5716 * with display 13, the bspec switches to a 0-based numbering scheme
5717 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
5718 * We'll just use the 0-based numbering here for all platforms since it's the
5719 * way things will be named by the hardware team going forward, plus it's more
5720 * consistent with how most of the rest of our registers are named.
5722 #define _DBUF_CTL_S0 0x45008
5723 #define _DBUF_CTL_S1 0x44FE8
5724 #define _DBUF_CTL_S2 0x44300
5725 #define _DBUF_CTL_S3 0x44304
5726 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
5731 #define DBUF_POWER_REQUEST REG_BIT(31)
5732 #define DBUF_POWER_STATE REG_BIT(30)
5733 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
5734 #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
5735 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
5736 #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
5738 #define GEN7_MSG_CTL _MMIO(0x45010)
5739 #define WAIT_FOR_PCH_RESET_ACK (1 << 1)
5740 #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
5742 #define _BW_BUDDY0_CTL 0x45130
5743 #define _BW_BUDDY1_CTL 0x45140
5744 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
5747 #define BW_BUDDY_DISABLE REG_BIT(31)
5748 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
5749 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
5751 #define _BW_BUDDY0_PAGE_MASK 0x45134
5752 #define _BW_BUDDY1_PAGE_MASK 0x45144
5753 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
5754 _BW_BUDDY0_PAGE_MASK, \
5755 _BW_BUDDY1_PAGE_MASK))
5757 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
5758 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
5759 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
5761 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
5762 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
5763 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
5764 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
5765 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
5766 #define ICL_DELAY_PMRSP REG_BIT(22)
5767 #define DISABLE_FLR_SRC REG_BIT(15)
5768 #define MASK_WAKEMEM REG_BIT(13)
5769 #define DDI_CLOCK_REG_ACCESS REG_BIT(7)
5771 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
5772 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
5773 #define DCPR_MASK_LPMODE REG_BIT(26)
5774 #define DCPR_SEND_RESP_IMM REG_BIT(25)
5775 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
5777 #define SKL_DFSM _MMIO(0x51000)
5778 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
5779 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
5780 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
5781 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
5782 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
5783 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
5784 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
5785 #define ICL_DFSM_DMC_DISABLE (1 << 23)
5786 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
5787 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
5788 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
5789 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
5790 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
5792 #define SKL_DSSM _MMIO(0x51004)
5793 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
5794 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
5795 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
5796 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
5798 #define GMD_ID_DISPLAY _MMIO(0x510a0)
5799 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
5800 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
5801 #define GMD_ID_STEP REG_GENMASK(5, 0)
5804 #define _PIPEA_CHICKEN 0x70038
5805 #define _PIPEB_CHICKEN 0x71038
5806 #define _PIPEC_CHICKEN 0x72038
5807 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
5809 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
5810 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
5811 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
5812 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
5813 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
5817 #define PCH_DISPLAY_BASE 0xc0000u
5819 /* south display engine interrupt: IBX */
5820 #define SDE_AUDIO_POWER_D (1 << 27)
5821 #define SDE_AUDIO_POWER_C (1 << 26)
5822 #define SDE_AUDIO_POWER_B (1 << 25)
5823 #define SDE_AUDIO_POWER_SHIFT (25)
5824 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
5825 #define SDE_GMBUS (1 << 24)
5826 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
5827 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
5828 #define SDE_AUDIO_HDCP_MASK (3 << 22)
5829 #define SDE_AUDIO_TRANSB (1 << 21)
5830 #define SDE_AUDIO_TRANSA (1 << 20)
5831 #define SDE_AUDIO_TRANS_MASK (3 << 20)
5832 #define SDE_POISON (1 << 19)
5834 #define SDE_FDI_RXB (1 << 17)
5835 #define SDE_FDI_RXA (1 << 16)
5836 #define SDE_FDI_MASK (3 << 16)
5837 #define SDE_AUXD (1 << 15)
5838 #define SDE_AUXC (1 << 14)
5839 #define SDE_AUXB (1 << 13)
5840 #define SDE_AUX_MASK (7 << 13)
5842 #define SDE_CRT_HOTPLUG (1 << 11)
5843 #define SDE_PORTD_HOTPLUG (1 << 10)
5844 #define SDE_PORTC_HOTPLUG (1 << 9)
5845 #define SDE_PORTB_HOTPLUG (1 << 8)
5846 #define SDE_SDVOB_HOTPLUG (1 << 6)
5847 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
5848 SDE_SDVOB_HOTPLUG | \
5849 SDE_PORTB_HOTPLUG | \
5850 SDE_PORTC_HOTPLUG | \
5852 #define SDE_TRANSB_CRC_DONE (1 << 5)
5853 #define SDE_TRANSB_CRC_ERR (1 << 4)
5854 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
5855 #define SDE_TRANSA_CRC_DONE (1 << 2)
5856 #define SDE_TRANSA_CRC_ERR (1 << 1)
5857 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
5858 #define SDE_TRANS_MASK (0x3f)
5860 /* south display engine interrupt: CPT - CNP */
5861 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
5862 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
5863 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
5864 #define SDE_AUDIO_POWER_SHIFT_CPT 29
5865 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
5866 #define SDE_AUXD_CPT (1 << 27)
5867 #define SDE_AUXC_CPT (1 << 26)
5868 #define SDE_AUXB_CPT (1 << 25)
5869 #define SDE_AUX_MASK_CPT (7 << 25)
5870 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
5871 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
5872 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
5873 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
5874 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
5875 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
5876 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
5877 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
5878 SDE_SDVOB_HOTPLUG_CPT | \
5879 SDE_PORTD_HOTPLUG_CPT | \
5880 SDE_PORTC_HOTPLUG_CPT | \
5881 SDE_PORTB_HOTPLUG_CPT)
5882 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
5883 SDE_PORTD_HOTPLUG_CPT | \
5884 SDE_PORTC_HOTPLUG_CPT | \
5885 SDE_PORTB_HOTPLUG_CPT | \
5886 SDE_PORTA_HOTPLUG_SPT)
5887 #define SDE_GMBUS_CPT (1 << 17)
5888 #define SDE_ERROR_CPT (1 << 16)
5889 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
5890 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
5891 #define SDE_FDI_RXC_CPT (1 << 8)
5892 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
5893 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
5894 #define SDE_FDI_RXB_CPT (1 << 4)
5895 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
5896 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
5897 #define SDE_FDI_RXA_CPT (1 << 0)
5898 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
5899 SDE_AUDIO_CP_REQ_B_CPT | \
5900 SDE_AUDIO_CP_REQ_A_CPT)
5901 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
5902 SDE_AUDIO_CP_CHG_B_CPT | \
5903 SDE_AUDIO_CP_CHG_A_CPT)
5904 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
5908 /* south display engine interrupt: ICP/TGP */
5909 #define SDE_GMBUS_ICP (1 << 23)
5910 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
5911 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
5912 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
5913 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
5914 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
5915 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
5916 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
5917 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
5918 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
5919 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
5920 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
5921 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
5922 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
5924 #define SDEISR _MMIO(0xc4000)
5925 #define SDEIMR _MMIO(0xc4004)
5926 #define SDEIIR _MMIO(0xc4008)
5927 #define SDEIER _MMIO(0xc400c)
5929 #define SERR_INT _MMIO(0xc4040)
5930 #define SERR_INT_POISON (1 << 31)
5931 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
5933 /* digital port hotplug */
5934 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
5935 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
5936 #define BXT_DDIA_HPD_INVERT (1 << 27)
5937 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
5938 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
5939 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
5940 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
5941 #define PORTD_HOTPLUG_ENABLE (1 << 20)
5942 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
5943 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
5944 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
5945 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
5946 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
5947 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
5948 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
5949 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
5950 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
5951 #define PORTC_HOTPLUG_ENABLE (1 << 12)
5952 #define BXT_DDIC_HPD_INVERT (1 << 11)
5953 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
5954 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
5955 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
5956 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
5957 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
5958 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
5959 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
5960 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
5961 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
5962 #define PORTB_HOTPLUG_ENABLE (1 << 4)
5963 #define BXT_DDIB_HPD_INVERT (1 << 3)
5964 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
5965 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
5966 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
5967 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
5968 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
5969 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
5970 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
5971 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
5972 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
5973 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
5974 BXT_DDIB_HPD_INVERT | \
5975 BXT_DDIC_HPD_INVERT)
5977 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
5978 #define PORTE_HOTPLUG_ENABLE (1 << 4)
5979 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
5980 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
5981 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
5982 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
5984 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
5985 * functionality covered in PCH_PORT_HOTPLUG is split into
5986 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
5989 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
5990 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
5991 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
5992 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
5993 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
5994 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
5995 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
5997 #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
5998 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
5999 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
6000 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
6002 #define SHPD_FILTER_CNT _MMIO(0xc4038)
6003 #define SHPD_FILTER_CNT_500_ADJ 0x001D9
6005 #define _PCH_DPLL_A 0xc6014
6006 #define _PCH_DPLL_B 0xc6018
6007 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
6009 #define _PCH_FPA0 0xc6040
6010 #define FP_CB_TUNE (0x3 << 22)
6011 #define _PCH_FPA1 0xc6044
6012 #define _PCH_FPB0 0xc6048
6013 #define _PCH_FPB1 0xc604c
6014 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
6015 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
6017 #define PCH_DPLL_TEST _MMIO(0xc606c)
6019 #define PCH_DREF_CONTROL _MMIO(0xC6200)
6020 #define DREF_CONTROL_MASK 0x7fc3
6021 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
6022 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
6023 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
6024 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
6025 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
6026 #define DREF_SSC_SOURCE_ENABLE (2 << 11)
6027 #define DREF_SSC_SOURCE_MASK (3 << 11)
6028 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
6029 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
6030 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
6031 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
6032 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
6033 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
6034 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
6035 #define DREF_SSC4_DOWNSPREAD (0 << 6)
6036 #define DREF_SSC4_CENTERSPREAD (1 << 6)
6037 #define DREF_SSC1_DISABLE (0 << 1)
6038 #define DREF_SSC1_ENABLE (1 << 1)
6039 #define DREF_SSC4_DISABLE (0)
6040 #define DREF_SSC4_ENABLE (1)
6042 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
6043 #define FDL_TP1_TIMER_SHIFT 12
6044 #define FDL_TP1_TIMER_MASK (3 << 12)
6045 #define FDL_TP2_TIMER_SHIFT 10
6046 #define FDL_TP2_TIMER_MASK (3 << 10)
6047 #define RAWCLK_FREQ_MASK 0x3ff
6048 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
6049 #define CNP_RAWCLK_DIV(div) ((div) << 16)
6050 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
6051 #define CNP_RAWCLK_DEN(den) ((den) << 26)
6052 #define ICP_RAWCLK_NUM(num) ((num) << 11)
6054 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
6056 #define PCH_SSC4_PARMS _MMIO(0xc6210)
6057 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
6059 #define PCH_DPLL_SEL _MMIO(0xc7000)
6060 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
6061 #define TRANS_DPLLA_SEL(pipe) 0
6062 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
6066 #define _PCH_TRANS_HTOTAL_A 0xe0000
6067 #define TRANS_HTOTAL_SHIFT 16
6068 #define TRANS_HACTIVE_SHIFT 0
6069 #define _PCH_TRANS_HBLANK_A 0xe0004
6070 #define TRANS_HBLANK_END_SHIFT 16
6071 #define TRANS_HBLANK_START_SHIFT 0
6072 #define _PCH_TRANS_HSYNC_A 0xe0008
6073 #define TRANS_HSYNC_END_SHIFT 16
6074 #define TRANS_HSYNC_START_SHIFT 0
6075 #define _PCH_TRANS_VTOTAL_A 0xe000c
6076 #define TRANS_VTOTAL_SHIFT 16
6077 #define TRANS_VACTIVE_SHIFT 0
6078 #define _PCH_TRANS_VBLANK_A 0xe0010
6079 #define TRANS_VBLANK_END_SHIFT 16
6080 #define TRANS_VBLANK_START_SHIFT 0
6081 #define _PCH_TRANS_VSYNC_A 0xe0014
6082 #define TRANS_VSYNC_END_SHIFT 16
6083 #define TRANS_VSYNC_START_SHIFT 0
6084 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
6086 #define _PCH_TRANSA_DATA_M1 0xe0030
6087 #define _PCH_TRANSA_DATA_N1 0xe0034
6088 #define _PCH_TRANSA_DATA_M2 0xe0038
6089 #define _PCH_TRANSA_DATA_N2 0xe003c
6090 #define _PCH_TRANSA_LINK_M1 0xe0040
6091 #define _PCH_TRANSA_LINK_N1 0xe0044
6092 #define _PCH_TRANSA_LINK_M2 0xe0048
6093 #define _PCH_TRANSA_LINK_N2 0xe004c
6095 /* Per-transcoder DIP controls (PCH) */
6096 #define _VIDEO_DIP_CTL_A 0xe0200
6097 #define _VIDEO_DIP_DATA_A 0xe0208
6098 #define _VIDEO_DIP_GCP_A 0xe0210
6099 #define GCP_COLOR_INDICATION (1 << 2)
6100 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
6101 #define GCP_AV_MUTE (1 << 0)
6103 #define _VIDEO_DIP_CTL_B 0xe1200
6104 #define _VIDEO_DIP_DATA_B 0xe1208
6105 #define _VIDEO_DIP_GCP_B 0xe1210
6107 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6108 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6109 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
6111 /* Per-transcoder DIP controls (VLV) */
6112 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6113 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6114 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
6116 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6117 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6118 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
6120 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6121 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6122 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
6124 #define VLV_TVIDEO_DIP_CTL(pipe) \
6125 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
6126 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
6127 #define VLV_TVIDEO_DIP_DATA(pipe) \
6128 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
6129 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
6130 #define VLV_TVIDEO_DIP_GCP(pipe) \
6131 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
6132 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
6134 /* Haswell DIP controls */
6136 #define _HSW_VIDEO_DIP_CTL_A 0x60200
6137 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
6138 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
6139 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
6140 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
6141 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
6142 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
6143 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
6144 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
6145 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
6146 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
6147 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
6148 #define _HSW_VIDEO_DIP_GCP_A 0x60210
6150 #define _HSW_VIDEO_DIP_CTL_B 0x61200
6151 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
6152 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
6153 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
6154 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
6155 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
6156 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
6157 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
6158 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
6159 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
6160 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
6161 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
6162 #define _HSW_VIDEO_DIP_GCP_B 0x61210
6164 /* Icelake PPS_DATA and _ECC DIP Registers.
6165 * These are available for transcoders B,C and eDP.
6166 * Adding the _A so as to reuse the _MMIO_TRANS2
6167 * definition, with which it offsets to the right location.
6170 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
6171 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
6172 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
6173 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
6175 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
6176 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
6177 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
6178 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
6179 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
6180 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
6181 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
6182 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
6183 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
6184 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
6186 #define _HSW_STEREO_3D_CTL_A 0x70020
6187 #define S3D_ENABLE (1 << 31)
6188 #define _HSW_STEREO_3D_CTL_B 0x71020
6190 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
6192 #define _PCH_TRANS_HTOTAL_B 0xe1000
6193 #define _PCH_TRANS_HBLANK_B 0xe1004
6194 #define _PCH_TRANS_HSYNC_B 0xe1008
6195 #define _PCH_TRANS_VTOTAL_B 0xe100c
6196 #define _PCH_TRANS_VBLANK_B 0xe1010
6197 #define _PCH_TRANS_VSYNC_B 0xe1014
6198 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
6200 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6201 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6202 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6203 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6204 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6205 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6206 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
6208 #define _PCH_TRANSB_DATA_M1 0xe1030
6209 #define _PCH_TRANSB_DATA_N1 0xe1034
6210 #define _PCH_TRANSB_DATA_M2 0xe1038
6211 #define _PCH_TRANSB_DATA_N2 0xe103c
6212 #define _PCH_TRANSB_LINK_M1 0xe1040
6213 #define _PCH_TRANSB_LINK_N1 0xe1044
6214 #define _PCH_TRANSB_LINK_M2 0xe1048
6215 #define _PCH_TRANSB_LINK_N2 0xe104c
6217 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6218 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6219 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6220 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6221 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6222 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6223 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6224 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
6226 #define _PCH_TRANSACONF 0xf0008
6227 #define _PCH_TRANSBCONF 0xf1008
6228 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6229 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
6230 #define TRANS_ENABLE REG_BIT(31)
6231 #define TRANS_STATE_ENABLE REG_BIT(30)
6232 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
6233 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
6234 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
6235 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
6236 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
6237 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
6238 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
6239 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
6240 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
6241 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
6242 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
6243 #define _TRANSA_CHICKEN1 0xf0060
6244 #define _TRANSB_CHICKEN1 0xf1060
6245 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
6246 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10)
6247 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)
6248 #define _TRANSA_CHICKEN2 0xf0064
6249 #define _TRANSB_CHICKEN2 0xf1064
6250 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
6251 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
6252 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
6253 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
6254 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
6255 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
6256 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
6258 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
6259 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
6260 #define FDIA_PHASE_SYNC_SHIFT_EN 18
6261 #define INVERT_DDID_HPD (1 << 18)
6262 #define INVERT_DDIC_HPD (1 << 17)
6263 #define INVERT_DDIB_HPD (1 << 16)
6264 #define INVERT_DDIA_HPD (1 << 15)
6265 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6266 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6267 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
6268 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
6269 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
6270 #define SBCLK_RUN_REFCLK_DIS (1 << 7)
6271 #define SPT_PWM_GRANULARITY (1 << 0)
6272 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
6273 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
6274 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
6275 #define LPT_PWM_GRANULARITY (1 << 5)
6276 #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
6278 #define _FDI_RXA_CHICKEN 0xc200c
6279 #define _FDI_RXB_CHICKEN 0xc2010
6280 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
6281 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
6282 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
6284 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
6285 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
6286 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
6287 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
6288 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
6289 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
6290 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
6291 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
6294 #define _FDI_TXA_CTL 0x60100
6295 #define _FDI_TXB_CTL 0x61100
6296 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
6297 #define FDI_TX_DISABLE (0 << 31)
6298 #define FDI_TX_ENABLE (1 << 31)
6299 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
6300 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
6301 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
6302 #define FDI_LINK_TRAIN_NONE (3 << 28)
6303 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
6304 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
6305 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
6306 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
6307 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
6308 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
6309 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
6310 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
6311 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6312 SNB has different settings. */
6313 /* SNB A-stepping */
6314 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
6315 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
6316 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
6317 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
6318 /* SNB B-stepping */
6319 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
6320 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
6321 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
6322 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
6323 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
6324 #define FDI_DP_PORT_WIDTH_SHIFT 19
6325 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
6326 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
6327 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
6328 /* Ironlake: hardwired to 1 */
6329 #define FDI_TX_PLL_ENABLE (1 << 14)
6331 /* Ivybridge has different bits for lolz */
6332 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
6333 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
6334 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
6335 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
6337 /* both Tx and Rx */
6338 #define FDI_COMPOSITE_SYNC (1 << 11)
6339 #define FDI_LINK_TRAIN_AUTO (1 << 10)
6340 #define FDI_SCRAMBLING_ENABLE (0 << 7)
6341 #define FDI_SCRAMBLING_DISABLE (1 << 7)
6343 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
6344 #define _FDI_RXA_CTL 0xf000c
6345 #define _FDI_RXB_CTL 0xf100c
6346 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
6347 #define FDI_RX_ENABLE (1 << 31)
6348 /* train, dp width same as FDI_TX */
6349 #define FDI_FS_ERRC_ENABLE (1 << 27)
6350 #define FDI_FE_ERRC_ENABLE (1 << 26)
6351 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
6352 #define FDI_8BPC (0 << 16)
6353 #define FDI_10BPC (1 << 16)
6354 #define FDI_6BPC (2 << 16)
6355 #define FDI_12BPC (3 << 16)
6356 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
6357 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
6358 #define FDI_RX_PLL_ENABLE (1 << 13)
6359 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
6360 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
6361 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
6362 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
6363 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
6364 #define FDI_PCDCLK (1 << 4)
6366 #define FDI_AUTO_TRAINING (1 << 10)
6367 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
6368 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
6369 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
6370 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
6371 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
6373 #define _FDI_RXA_MISC 0xf0010
6374 #define _FDI_RXB_MISC 0xf1010
6375 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
6376 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
6377 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
6378 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
6379 #define FDI_RX_TP1_TO_TP2_48 (2 << 20)
6380 #define FDI_RX_TP1_TO_TP2_64 (3 << 20)
6381 #define FDI_RX_FDI_DELAY_90 (0x90 << 0)
6382 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
6384 #define _FDI_RXA_TUSIZE1 0xf0030
6385 #define _FDI_RXA_TUSIZE2 0xf0038
6386 #define _FDI_RXB_TUSIZE1 0xf1030
6387 #define _FDI_RXB_TUSIZE2 0xf1038
6388 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6389 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
6391 /* FDI_RX interrupt register format */
6392 #define FDI_RX_INTER_LANE_ALIGN (1 << 10)
6393 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */
6394 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */
6395 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
6396 #define FDI_RX_FS_CODE_ERR (1 << 6)
6397 #define FDI_RX_FE_CODE_ERR (1 << 5)
6398 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
6399 #define FDI_RX_HDCP_LINK_FAIL (1 << 3)
6400 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
6401 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
6402 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
6404 #define _FDI_RXA_IIR 0xf0014
6405 #define _FDI_RXA_IMR 0xf0018
6406 #define _FDI_RXB_IIR 0xf1014
6407 #define _FDI_RXB_IMR 0xf1018
6408 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6409 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
6411 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
6412 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
6414 #define PCH_LVDS _MMIO(0xe1180)
6415 #define LVDS_DETECTED (1 << 1)
6417 #define _PCH_DP_B 0xe4100
6418 #define PCH_DP_B _MMIO(_PCH_DP_B)
6419 #define _PCH_DPB_AUX_CH_CTL 0xe4110
6420 #define _PCH_DPB_AUX_CH_DATA1 0xe4114
6421 #define _PCH_DPB_AUX_CH_DATA2 0xe4118
6422 #define _PCH_DPB_AUX_CH_DATA3 0xe411c
6423 #define _PCH_DPB_AUX_CH_DATA4 0xe4120
6424 #define _PCH_DPB_AUX_CH_DATA5 0xe4124
6426 #define _PCH_DP_C 0xe4200
6427 #define PCH_DP_C _MMIO(_PCH_DP_C)
6428 #define _PCH_DPC_AUX_CH_CTL 0xe4210
6429 #define _PCH_DPC_AUX_CH_DATA1 0xe4214
6430 #define _PCH_DPC_AUX_CH_DATA2 0xe4218
6431 #define _PCH_DPC_AUX_CH_DATA3 0xe421c
6432 #define _PCH_DPC_AUX_CH_DATA4 0xe4220
6433 #define _PCH_DPC_AUX_CH_DATA5 0xe4224
6435 #define _PCH_DP_D 0xe4300
6436 #define PCH_DP_D _MMIO(_PCH_DP_D)
6437 #define _PCH_DPD_AUX_CH_CTL 0xe4310
6438 #define _PCH_DPD_AUX_CH_DATA1 0xe4314
6439 #define _PCH_DPD_AUX_CH_DATA2 0xe4318
6440 #define _PCH_DPD_AUX_CH_DATA3 0xe431c
6441 #define _PCH_DPD_AUX_CH_DATA4 0xe4320
6442 #define _PCH_DPD_AUX_CH_DATA5 0xe4324
6444 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
6445 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
6448 #define _TRANS_DP_CTL_A 0xe0300
6449 #define _TRANS_DP_CTL_B 0xe1300
6450 #define _TRANS_DP_CTL_C 0xe2300
6451 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
6452 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
6453 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
6454 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
6455 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
6456 #define TRANS_DP_AUDIO_ONLY REG_BIT(26)
6457 #define TRANS_DP_ENH_FRAMING REG_BIT(18)
6458 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
6459 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
6460 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
6461 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
6462 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
6463 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
6464 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
6466 #define _TRANS_DP2_CTL_A 0x600a0
6467 #define _TRANS_DP2_CTL_B 0x610a0
6468 #define _TRANS_DP2_CTL_C 0x620a0
6469 #define _TRANS_DP2_CTL_D 0x630a0
6470 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
6471 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
6472 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
6473 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
6475 #define _TRANS_DP2_VFREQHIGH_A 0x600a4
6476 #define _TRANS_DP2_VFREQHIGH_B 0x610a4
6477 #define _TRANS_DP2_VFREQHIGH_C 0x620a4
6478 #define _TRANS_DP2_VFREQHIGH_D 0x630a4
6479 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
6480 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
6481 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
6483 #define _TRANS_DP2_VFREQLOW_A 0x600a8
6484 #define _TRANS_DP2_VFREQLOW_B 0x610a8
6485 #define _TRANS_DP2_VFREQLOW_C 0x620a8
6486 #define _TRANS_DP2_VFREQLOW_D 0x630a8
6487 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
6489 /* SNB eDP training params */
6490 /* SNB A-stepping */
6491 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
6492 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
6493 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
6494 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
6495 /* SNB B-stepping */
6496 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
6497 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
6498 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
6499 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
6500 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
6501 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
6504 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
6505 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
6506 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
6507 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
6508 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
6509 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
6510 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
6513 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
6514 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
6515 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
6516 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
6517 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
6519 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
6521 #define VLV_PMWGICZ _MMIO(0x1300a4)
6523 #define HSW_EDRAM_CAP _MMIO(0x120010)
6524 #define EDRAM_ENABLED 0x1
6525 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
6526 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
6527 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
6529 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
6530 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
6531 #define PIXEL_OVERLAP_CNT_SHIFT 30
6533 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
6534 #define GEN6_PCODE_READY (1 << 31)
6535 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
6536 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
6537 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
6538 #define GEN6_PCODE_ERROR_MASK 0xFF
6539 #define GEN6_PCODE_SUCCESS 0x0
6540 #define GEN6_PCODE_ILLEGAL_CMD 0x1
6541 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
6542 #define GEN6_PCODE_TIMEOUT 0x3
6543 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
6544 #define GEN7_PCODE_TIMEOUT 0x2
6545 #define GEN7_PCODE_ILLEGAL_DATA 0x3
6546 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
6547 #define GEN11_PCODE_LOCKED 0x6
6548 #define GEN11_PCODE_REJECTED 0x11
6549 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
6550 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
6551 #define GEN6_PCODE_READ_RC6VIDS 0x5
6552 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
6553 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
6554 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
6555 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
6556 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
6557 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
6558 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
6559 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
6560 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
6561 #define SKL_PCODE_CDCLK_CONTROL 0x7
6562 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
6563 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
6564 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
6565 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
6566 #define GEN6_READ_OC_PARAMS 0xc
6567 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
6568 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
6569 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
6570 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
6571 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
6572 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
6573 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
6574 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
6575 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
6576 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
6577 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
6578 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
6579 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
6580 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
6581 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
6582 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
6583 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
6584 #define GEN6_PCODE_READ_D_COMP 0x10
6585 #define GEN6_PCODE_WRITE_D_COMP 0x11
6586 #define ICL_PCODE_EXIT_TCCOLD 0x12
6587 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
6588 #define DISPLAY_IPS_CONTROL 0x19
6589 #define TGL_PCODE_TCCOLD 0x26
6590 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
6591 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
6592 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
6593 /* See also IPS_CTL */
6594 #define IPS_PCODE_CONTROL (1 << 30)
6595 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
6596 #define GEN9_PCODE_SAGV_CONTROL 0x21
6597 #define GEN9_SAGV_DISABLE 0x0
6598 #define GEN9_SAGV_IS_DISABLED 0x1
6599 #define GEN9_SAGV_ENABLE 0x3
6600 #define DG1_PCODE_STATUS 0x7E
6601 #define DG1_UNCORE_GET_INIT_STATUS 0x0
6602 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
6603 #define PCODE_POWER_SETUP 0x7C
6604 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
6605 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
6606 #define POWER_SETUP_I1_WATTS REG_BIT(31)
6607 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
6608 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
6609 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
6610 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
6611 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
6612 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
6613 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
6614 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
6615 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */
6616 #define PCODE_MBOX_DOMAIN_NONE 0x0
6617 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
6619 /* Wa_14017210380: mtl */
6620 #define PCODE_MBOX_GT_STATE 0x50
6621 /* sub-commands (param1) */
6622 #define PCODE_MBOX_GT_STATE_MEDIA_BUSY 0x1
6623 #define PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY 0x2
6625 #define PCODE_MBOX_GT_STATE_DOMAIN_MEDIA 0x1
6627 #define GEN6_PCODE_DATA _MMIO(0x138128)
6628 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
6629 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
6630 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
6633 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
6634 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
6635 #define GEN7_PARITY_ERROR_VALID (1 << 13)
6636 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
6637 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
6638 #define GEN7_PARITY_ERROR_ROW(reg) \
6639 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
6640 #define GEN7_PARITY_ERROR_BANK(reg) \
6641 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
6642 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
6643 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
6644 #define GEN7_L3CDERRST1_ENABLE (1 << 7)
6646 /* These are the 4 32-bit write offset registers for each stream
6647 * output buffer. It determines the offset from the
6648 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
6650 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
6653 * HSW - ICL power wells
6655 * Platforms have up to 3 power well control register sets, each set
6656 * controlling up to 16 power wells via a request/status HW flag tuple:
6657 * - main (HSW_PWR_WELL_CTL[1-4])
6658 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
6659 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
6660 * Each control register set consists of up to 4 registers used by different
6661 * sources that can request a power well to be enabled:
6662 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
6663 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
6664 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
6665 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
6667 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
6668 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
6669 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
6670 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
6671 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
6672 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
6674 /* HSW/BDW power well */
6675 #define HSW_PW_CTL_IDX_GLOBAL 15
6677 /* SKL/BXT/GLK power wells */
6678 #define SKL_PW_CTL_IDX_PW_2 15
6679 #define SKL_PW_CTL_IDX_PW_1 14
6680 #define GLK_PW_CTL_IDX_AUX_C 10
6681 #define GLK_PW_CTL_IDX_AUX_B 9
6682 #define GLK_PW_CTL_IDX_AUX_A 8
6683 #define SKL_PW_CTL_IDX_DDI_D 4
6684 #define SKL_PW_CTL_IDX_DDI_C 3
6685 #define SKL_PW_CTL_IDX_DDI_B 2
6686 #define SKL_PW_CTL_IDX_DDI_A_E 1
6687 #define GLK_PW_CTL_IDX_DDI_A 1
6688 #define SKL_PW_CTL_IDX_MISC_IO 0
6690 /* ICL/TGL - power wells */
6691 #define TGL_PW_CTL_IDX_PW_5 4
6692 #define ICL_PW_CTL_IDX_PW_4 3
6693 #define ICL_PW_CTL_IDX_PW_3 2
6694 #define ICL_PW_CTL_IDX_PW_2 1
6695 #define ICL_PW_CTL_IDX_PW_1 0
6697 /* XE_LPD - power wells */
6698 #define XELPD_PW_CTL_IDX_PW_D 8
6699 #define XELPD_PW_CTL_IDX_PW_C 7
6700 #define XELPD_PW_CTL_IDX_PW_B 6
6701 #define XELPD_PW_CTL_IDX_PW_A 5
6703 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
6704 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
6705 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
6706 #define TGL_PW_CTL_IDX_AUX_TBT6 14
6707 #define TGL_PW_CTL_IDX_AUX_TBT5 13
6708 #define TGL_PW_CTL_IDX_AUX_TBT4 12
6709 #define ICL_PW_CTL_IDX_AUX_TBT4 11
6710 #define TGL_PW_CTL_IDX_AUX_TBT3 11
6711 #define ICL_PW_CTL_IDX_AUX_TBT3 10
6712 #define TGL_PW_CTL_IDX_AUX_TBT2 10
6713 #define ICL_PW_CTL_IDX_AUX_TBT2 9
6714 #define TGL_PW_CTL_IDX_AUX_TBT1 9
6715 #define ICL_PW_CTL_IDX_AUX_TBT1 8
6716 #define TGL_PW_CTL_IDX_AUX_TC6 8
6717 #define XELPD_PW_CTL_IDX_AUX_E 8
6718 #define TGL_PW_CTL_IDX_AUX_TC5 7
6719 #define XELPD_PW_CTL_IDX_AUX_D 7
6720 #define TGL_PW_CTL_IDX_AUX_TC4 6
6721 #define ICL_PW_CTL_IDX_AUX_F 5
6722 #define TGL_PW_CTL_IDX_AUX_TC3 5
6723 #define ICL_PW_CTL_IDX_AUX_E 4
6724 #define TGL_PW_CTL_IDX_AUX_TC2 4
6725 #define ICL_PW_CTL_IDX_AUX_D 3
6726 #define TGL_PW_CTL_IDX_AUX_TC1 3
6727 #define ICL_PW_CTL_IDX_AUX_C 2
6728 #define ICL_PW_CTL_IDX_AUX_B 1
6729 #define ICL_PW_CTL_IDX_AUX_A 0
6731 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
6732 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
6733 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
6734 #define XELPD_PW_CTL_IDX_DDI_E 8
6735 #define TGL_PW_CTL_IDX_DDI_TC6 8
6736 #define XELPD_PW_CTL_IDX_DDI_D 7
6737 #define TGL_PW_CTL_IDX_DDI_TC5 7
6738 #define TGL_PW_CTL_IDX_DDI_TC4 6
6739 #define ICL_PW_CTL_IDX_DDI_F 5
6740 #define TGL_PW_CTL_IDX_DDI_TC3 5
6741 #define ICL_PW_CTL_IDX_DDI_E 4
6742 #define TGL_PW_CTL_IDX_DDI_TC2 4
6743 #define ICL_PW_CTL_IDX_DDI_D 3
6744 #define TGL_PW_CTL_IDX_DDI_TC1 3
6745 #define ICL_PW_CTL_IDX_DDI_C 2
6746 #define ICL_PW_CTL_IDX_DDI_B 1
6747 #define ICL_PW_CTL_IDX_DDI_A 0
6749 /* HSW - power well misc debug registers */
6750 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
6751 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
6752 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
6753 #define HSW_PWR_WELL_FORCE_ON (1 << 19)
6754 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
6756 /* SKL Fuse Status */
6757 enum skl_power_gate {
6765 #define SKL_FUSE_STATUS _MMIO(0x42000)
6766 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
6768 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
6769 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
6771 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
6772 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
6774 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
6775 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
6777 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
6778 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
6779 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
6781 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
6782 #define _ICL_AUX_ANAOVRD1_A 0x162398
6783 #define _ICL_AUX_ANAOVRD1_B 0x6C398
6784 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
6785 _ICL_AUX_ANAOVRD1_A, \
6786 _ICL_AUX_ANAOVRD1_B))
6787 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
6788 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
6790 /* Per-pipe DDI Function Control */
6791 #define _TRANS_DDI_FUNC_CTL_A 0x60400
6792 #define _TRANS_DDI_FUNC_CTL_B 0x61400
6793 #define _TRANS_DDI_FUNC_CTL_C 0x62400
6794 #define _TRANS_DDI_FUNC_CTL_D 0x63400
6795 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
6796 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
6797 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
6798 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
6800 #define TRANS_DDI_FUNC_ENABLE (1 << 31)
6801 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
6802 #define TRANS_DDI_PORT_SHIFT 28
6803 #define TGL_TRANS_DDI_PORT_SHIFT 27
6804 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
6805 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
6806 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
6807 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
6808 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
6809 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
6810 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
6811 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
6812 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
6813 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
6814 #define TRANS_DDI_BPC_MASK (7 << 20)
6815 #define TRANS_DDI_BPC_8 (0 << 20)
6816 #define TRANS_DDI_BPC_10 (1 << 20)
6817 #define TRANS_DDI_BPC_6 (2 << 20)
6818 #define TRANS_DDI_BPC_12 (3 << 20)
6819 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
6820 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
6821 #define TRANS_DDI_PVSYNC (1 << 17)
6822 #define TRANS_DDI_PHSYNC (1 << 16)
6823 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
6824 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
6825 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
6826 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
6827 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
6828 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
6829 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
6830 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
6831 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
6832 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
6833 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
6834 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
6835 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
6836 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
6837 #define TRANS_DDI_HDCP_SELECT REG_BIT(5)
6838 #define TRANS_DDI_BFI_ENABLE (1 << 4)
6839 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
6840 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
6841 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
6842 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
6843 | TRANS_DDI_HDMI_SCRAMBLING)
6845 #define _TRANS_DDI_FUNC_CTL2_A 0x60404
6846 #define _TRANS_DDI_FUNC_CTL2_B 0x61404
6847 #define _TRANS_DDI_FUNC_CTL2_C 0x62404
6848 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
6849 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
6850 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
6851 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
6852 #define PORT_SYNC_MODE_ENABLE REG_BIT(4)
6853 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
6854 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
6856 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
6857 #define DISABLE_DPT_CLK_GATING REG_BIT(1)
6859 /* DisplayPort Transport Control */
6860 #define _DP_TP_CTL_A 0x64040
6861 #define _DP_TP_CTL_B 0x64140
6862 #define _TGL_DP_TP_CTL_A 0x60540
6863 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
6864 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
6865 #define DP_TP_CTL_ENABLE (1 << 31)
6866 #define DP_TP_CTL_FEC_ENABLE (1 << 30)
6867 #define DP_TP_CTL_MODE_SST (0 << 27)
6868 #define DP_TP_CTL_MODE_MST (1 << 27)
6869 #define DP_TP_CTL_FORCE_ACT (1 << 25)
6870 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
6871 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
6872 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
6873 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
6874 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
6875 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
6876 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
6877 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
6878 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
6879 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
6881 /* DisplayPort Transport Status */
6882 #define _DP_TP_STATUS_A 0x64044
6883 #define _DP_TP_STATUS_B 0x64144
6884 #define _TGL_DP_TP_STATUS_A 0x60544
6885 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
6886 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
6887 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
6888 #define DP_TP_STATUS_IDLE_DONE (1 << 25)
6889 #define DP_TP_STATUS_ACT_SENT (1 << 24)
6890 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
6891 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
6892 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
6893 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
6894 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
6896 /* DDI Buffer Control */
6897 #define _DDI_BUF_CTL_A 0x64000
6898 #define _DDI_BUF_CTL_B 0x64100
6899 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
6900 #define DDI_BUF_CTL_ENABLE (1 << 31)
6901 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
6902 #define DDI_BUF_EMP_MASK (0xf << 24)
6903 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
6904 #define DDI_BUF_PORT_REVERSAL (1 << 16)
6905 #define DDI_BUF_IS_IDLE (1 << 7)
6906 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
6907 #define DDI_A_4_LANES (1 << 4)
6908 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
6909 #define DDI_PORT_WIDTH_MASK (7 << 1)
6910 #define DDI_PORT_WIDTH_SHIFT 1
6911 #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
6913 /* DDI Buffer Translations */
6914 #define _DDI_BUF_TRANS_A 0x64E00
6915 #define _DDI_BUF_TRANS_B 0x64E60
6916 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
6917 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
6918 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
6920 /* DDI DP Compliance Control */
6921 #define _DDI_DP_COMP_CTL_A 0x605F0
6922 #define _DDI_DP_COMP_CTL_B 0x615F0
6923 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
6924 #define DDI_DP_COMP_CTL_ENABLE (1 << 31)
6925 #define DDI_DP_COMP_CTL_D10_2 (0 << 28)
6926 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
6927 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
6928 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
6929 #define DDI_DP_COMP_CTL_HBR2 (4 << 28)
6930 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
6931 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
6933 /* DDI DP Compliance Pattern */
6934 #define _DDI_DP_COMP_PAT_A 0x605F4
6935 #define _DDI_DP_COMP_PAT_B 0x615F4
6936 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
6938 /* Sideband Interface (SBI) is programmed indirectly, via
6939 * SBI_ADDR, which contains the register offset; and SBI_DATA,
6940 * which contains the payload */
6941 #define SBI_ADDR _MMIO(0xC6000)
6942 #define SBI_DATA _MMIO(0xC6004)
6943 #define SBI_CTL_STAT _MMIO(0xC6008)
6944 #define SBI_CTL_DEST_ICLK (0x0 << 16)
6945 #define SBI_CTL_DEST_MPHY (0x1 << 16)
6946 #define SBI_CTL_OP_IORD (0x2 << 8)
6947 #define SBI_CTL_OP_IOWR (0x3 << 8)
6948 #define SBI_CTL_OP_CRRD (0x6 << 8)
6949 #define SBI_CTL_OP_CRWR (0x7 << 8)
6950 #define SBI_RESPONSE_FAIL (0x1 << 1)
6951 #define SBI_RESPONSE_SUCCESS (0x0 << 1)
6952 #define SBI_BUSY (0x1 << 0)
6953 #define SBI_READY (0x0 << 0)
6956 #define SBI_SSCDIVINTPHASE 0x0200
6957 #define SBI_SSCDIVINTPHASE6 0x0600
6958 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
6959 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
6960 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
6961 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
6962 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
6963 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
6964 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
6965 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
6966 #define SBI_SSCDITHPHASE 0x0204
6967 #define SBI_SSCCTL 0x020c
6968 #define SBI_SSCCTL6 0x060C
6969 #define SBI_SSCCTL_PATHALT (1 << 3)
6970 #define SBI_SSCCTL_DISABLE (1 << 0)
6971 #define SBI_SSCAUXDIV6 0x0610
6972 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
6973 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
6974 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
6975 #define SBI_DBUFF0 0x2a00
6976 #define SBI_GEN0 0x1f00
6977 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
6979 /* LPT PIXCLK_GATE */
6980 #define PIXCLK_GATE _MMIO(0xC6020)
6981 #define PIXCLK_GATE_UNGATE (1 << 0)
6982 #define PIXCLK_GATE_GATE (0 << 0)
6985 #define SPLL_CTL _MMIO(0x46020)
6986 #define SPLL_PLL_ENABLE (1 << 31)
6987 #define SPLL_REF_BCLK (0 << 28)
6988 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
6989 #define SPLL_REF_NON_SSC_HSW (2 << 28)
6990 #define SPLL_REF_PCH_SSC_BDW (2 << 28)
6991 #define SPLL_REF_LCPLL (3 << 28)
6992 #define SPLL_REF_MASK (3 << 28)
6993 #define SPLL_FREQ_810MHz (0 << 26)
6994 #define SPLL_FREQ_1350MHz (1 << 26)
6995 #define SPLL_FREQ_2700MHz (2 << 26)
6996 #define SPLL_FREQ_MASK (3 << 26)
6999 #define _WRPLL_CTL1 0x46040
7000 #define _WRPLL_CTL2 0x46060
7001 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
7002 #define WRPLL_PLL_ENABLE (1 << 31)
7003 #define WRPLL_REF_BCLK (0 << 28)
7004 #define WRPLL_REF_PCH_SSC (1 << 28)
7005 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
7006 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
7007 #define WRPLL_REF_LCPLL (3 << 28)
7008 #define WRPLL_REF_MASK (3 << 28)
7009 /* WRPLL divider programming */
7010 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
7011 #define WRPLL_DIVIDER_REF_MASK (0xff)
7012 #define WRPLL_DIVIDER_POST(x) ((x) << 8)
7013 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
7014 #define WRPLL_DIVIDER_POST_SHIFT 8
7015 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
7016 #define WRPLL_DIVIDER_FB_SHIFT 16
7017 #define WRPLL_DIVIDER_FB_MASK (0xff << 16)
7019 /* Port clock selection */
7020 #define _PORT_CLK_SEL_A 0x46100
7021 #define _PORT_CLK_SEL_B 0x46104
7022 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
7023 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
7024 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
7025 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
7026 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
7027 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
7028 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
7029 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
7030 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
7031 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
7033 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
7034 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
7035 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
7036 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
7037 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
7038 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
7039 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
7040 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
7041 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
7043 /* Transcoder clock selection */
7044 #define _TRANS_CLK_SEL_A 0x46140
7045 #define _TRANS_CLK_SEL_B 0x46144
7046 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
7047 /* For each transcoder, we need to select the corresponding port clock */
7048 #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
7049 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
7050 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
7051 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
7054 #define CDCLK_FREQ _MMIO(0x46200)
7056 #define _TRANSA_MSA_MISC 0x60410
7057 #define _TRANSB_MSA_MISC 0x61410
7058 #define _TRANSC_MSA_MISC 0x62410
7059 #define _TRANS_EDP_MSA_MISC 0x6f410
7060 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
7061 /* See DP_MSA_MISC_* for the bit definitions */
7063 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
7064 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
7065 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
7066 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
7067 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
7068 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
7069 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
7072 #define LCPLL_CTL _MMIO(0x130040)
7073 #define LCPLL_PLL_DISABLE (1 << 31)
7074 #define LCPLL_PLL_LOCK (1 << 30)
7075 #define LCPLL_REF_NON_SSC (0 << 28)
7076 #define LCPLL_REF_BCLK (2 << 28)
7077 #define LCPLL_REF_PCH_SSC (3 << 28)
7078 #define LCPLL_REF_MASK (3 << 28)
7079 #define LCPLL_CLK_FREQ_MASK (3 << 26)
7080 #define LCPLL_CLK_FREQ_450 (0 << 26)
7081 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
7082 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
7083 #define LCPLL_CLK_FREQ_675_BDW (3 << 26)
7084 #define LCPLL_CD_CLOCK_DISABLE (1 << 25)
7085 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
7086 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
7087 #define LCPLL_POWER_DOWN_ALLOW (1 << 22)
7088 #define LCPLL_CD_SOURCE_FCLK (1 << 21)
7089 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
7096 #define CDCLK_CTL _MMIO(0x46000)
7097 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
7098 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
7099 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
7100 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
7101 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
7102 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
7103 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
7104 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
7105 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
7106 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
7107 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
7108 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
7109 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
7110 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
7111 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
7112 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
7113 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
7114 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
7115 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
7117 /* CDCLK_SQUASH_CTL */
7118 #define CDCLK_SQUASH_CTL _MMIO(0x46008)
7119 #define CDCLK_SQUASH_ENABLE REG_BIT(31)
7120 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
7121 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
7122 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
7123 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
7126 #define LCPLL1_CTL _MMIO(0x46010)
7127 #define LCPLL2_CTL _MMIO(0x46014)
7128 #define LCPLL_PLL_ENABLE (1 << 31)
7131 #define DPLL_CTRL1 _MMIO(0x6C058)
7132 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
7133 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
7134 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
7135 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
7136 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
7137 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
7138 #define DPLL_CTRL1_LINK_RATE_2700 0
7139 #define DPLL_CTRL1_LINK_RATE_1350 1
7140 #define DPLL_CTRL1_LINK_RATE_810 2
7141 #define DPLL_CTRL1_LINK_RATE_1620 3
7142 #define DPLL_CTRL1_LINK_RATE_1080 4
7143 #define DPLL_CTRL1_LINK_RATE_2160 5
7146 #define DPLL_CTRL2 _MMIO(0x6C05C)
7147 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
7148 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
7149 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
7150 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
7151 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
7154 #define DPLL_STATUS _MMIO(0x6C060)
7155 #define DPLL_LOCK(id) (1 << ((id) * 8))
7158 #define _DPLL1_CFGCR1 0x6C040
7159 #define _DPLL2_CFGCR1 0x6C048
7160 #define _DPLL3_CFGCR1 0x6C050
7161 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
7162 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
7163 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
7164 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
7166 #define _DPLL1_CFGCR2 0x6C044
7167 #define _DPLL2_CFGCR2 0x6C04C
7168 #define _DPLL3_CFGCR2 0x6C054
7169 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
7170 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
7171 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
7172 #define DPLL_CFGCR2_KDIV_MASK (3 << 5)
7173 #define DPLL_CFGCR2_KDIV(x) ((x) << 5)
7174 #define DPLL_CFGCR2_KDIV_5 (0 << 5)
7175 #define DPLL_CFGCR2_KDIV_2 (1 << 5)
7176 #define DPLL_CFGCR2_KDIV_3 (2 << 5)
7177 #define DPLL_CFGCR2_KDIV_1 (3 << 5)
7178 #define DPLL_CFGCR2_PDIV_MASK (7 << 2)
7179 #define DPLL_CFGCR2_PDIV(x) ((x) << 2)
7180 #define DPLL_CFGCR2_PDIV_1 (0 << 2)
7181 #define DPLL_CFGCR2_PDIV_2 (1 << 2)
7182 #define DPLL_CFGCR2_PDIV_3 (2 << 2)
7183 #define DPLL_CFGCR2_PDIV_7 (4 << 2)
7184 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
7185 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
7187 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
7188 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
7191 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
7192 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
7193 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
7194 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
7196 (tc_port) - TC_PORT_4 + 21))
7197 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
7198 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7199 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7200 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
7201 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
7202 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7203 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
7204 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7208 * First registers controls the first A and B, while the second register
7209 * controls the phy C and D. The bits on these registers are the
7210 * same, but refer to different phys
7212 #define _DG1_DPCLKA_CFGCR0 0x164280
7213 #define _DG1_DPCLKA1_CFGCR0 0x16C280
7214 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
7215 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
7216 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
7217 _DG1_DPCLKA_CFGCR0, \
7218 _DG1_DPCLKA1_CFGCR0)
7219 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
7220 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
7221 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7222 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7225 #define _ADLS_DPCLKA_CFGCR0 0x164280
7226 #define _ADLS_DPCLKA_CFGCR1 0x1642BC
7227 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
7228 _ADLS_DPCLKA_CFGCR0, \
7229 _ADLS_DPCLKA_CFGCR1)
7230 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
7231 /* ADLS DPCLKA_CFGCR0 DDI mask */
7232 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
7233 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
7234 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
7235 /* ADLS DPCLKA_CFGCR1 DDI mask */
7236 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
7237 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
7238 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
7239 ADLS_DPCLKA_DDIA_SEL_MASK, \
7240 ADLS_DPCLKA_DDIB_SEL_MASK, \
7241 ADLS_DPCLKA_DDII_SEL_MASK, \
7242 ADLS_DPCLKA_DDIJ_SEL_MASK, \
7243 ADLS_DPCLKA_DDIK_SEL_MASK)
7246 #define DPLL0_ENABLE 0x46010
7247 #define DPLL1_ENABLE 0x46014
7248 #define _ADLS_DPLL2_ENABLE 0x46018
7249 #define _ADLS_DPLL3_ENABLE 0x46030
7250 #define PLL_ENABLE (1 << 31)
7251 #define PLL_LOCK (1 << 30)
7252 #define PLL_POWER_ENABLE (1 << 27)
7253 #define PLL_POWER_STATE (1 << 26)
7254 #define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
7255 _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
7257 #define _DG2_PLL3_ENABLE 0x4601C
7259 #define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
7260 _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
7262 #define TBT_PLL_ENABLE _MMIO(0x46020)
7264 #define _MG_PLL1_ENABLE 0x46030
7265 #define _MG_PLL2_ENABLE 0x46034
7266 #define _MG_PLL3_ENABLE 0x46038
7267 #define _MG_PLL4_ENABLE 0x4603C
7268 /* Bits are the same as DPLL0_ENABLE */
7269 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
7273 #define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
7274 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
7276 /* ADL-P Type C PLL */
7277 #define PORTTC1_PLL_ENABLE 0x46038
7278 #define PORTTC2_PLL_ENABLE 0x46040
7280 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
7281 PORTTC1_PLL_ENABLE, \
7284 #define _ICL_DPLL0_CFGCR0 0x164000
7285 #define _ICL_DPLL1_CFGCR0 0x164080
7286 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
7288 #define DPLL_CFGCR0_HDMI_MODE (1 << 30)
7289 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
7290 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
7291 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
7292 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
7293 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
7294 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
7295 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
7296 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
7297 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
7298 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
7299 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
7300 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
7301 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
7302 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
7303 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
7305 #define _ICL_DPLL0_CFGCR1 0x164004
7306 #define _ICL_DPLL1_CFGCR1 0x164084
7307 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
7309 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
7310 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
7311 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
7312 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
7313 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
7314 #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
7315 #define DPLL_CFGCR1_KDIV_SHIFT (6)
7316 #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
7317 #define DPLL_CFGCR1_KDIV_1 (1 << 6)
7318 #define DPLL_CFGCR1_KDIV_2 (2 << 6)
7319 #define DPLL_CFGCR1_KDIV_3 (4 << 6)
7320 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
7321 #define DPLL_CFGCR1_PDIV_SHIFT (2)
7322 #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
7323 #define DPLL_CFGCR1_PDIV_2 (1 << 2)
7324 #define DPLL_CFGCR1_PDIV_3 (2 << 2)
7325 #define DPLL_CFGCR1_PDIV_5 (4 << 2)
7326 #define DPLL_CFGCR1_PDIV_7 (8 << 2)
7327 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
7328 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
7329 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
7331 #define _TGL_DPLL0_CFGCR0 0x164284
7332 #define _TGL_DPLL1_CFGCR0 0x16428C
7333 #define _TGL_TBTPLL_CFGCR0 0x16429C
7334 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
7335 _TGL_DPLL1_CFGCR0, \
7337 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
7340 #define _TGL_DPLL0_DIV0 0x164B00
7341 #define _TGL_DPLL1_DIV0 0x164C00
7342 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
7343 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
7344 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
7346 #define _TGL_DPLL0_CFGCR1 0x164288
7347 #define _TGL_DPLL1_CFGCR1 0x164290
7348 #define _TGL_TBTPLL_CFGCR1 0x1642A0
7349 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
7350 _TGL_DPLL1_CFGCR1, \
7352 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
7355 #define _DG1_DPLL2_CFGCR0 0x16C284
7356 #define _DG1_DPLL3_CFGCR0 0x16C28C
7357 #define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
7358 _TGL_DPLL1_CFGCR0, \
7359 _DG1_DPLL2_CFGCR0, \
7362 #define _DG1_DPLL2_CFGCR1 0x16C288
7363 #define _DG1_DPLL3_CFGCR1 0x16C290
7364 #define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
7365 _TGL_DPLL1_CFGCR1, \
7366 _DG1_DPLL2_CFGCR1, \
7369 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
7370 #define _ADLS_DPLL3_CFGCR0 0x1642C0
7371 #define _ADLS_DPLL4_CFGCR0 0x164294
7372 #define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
7373 _TGL_DPLL1_CFGCR0, \
7374 _ADLS_DPLL4_CFGCR0, \
7377 #define _ADLS_DPLL3_CFGCR1 0x1642C4
7378 #define _ADLS_DPLL4_CFGCR1 0x164298
7379 #define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
7380 _TGL_DPLL1_CFGCR1, \
7381 _ADLS_DPLL4_CFGCR1, \
7384 /* BXT display engine PLL */
7385 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
7386 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
7387 #define BXT_DE_PLL_RATIO_MASK 0xff
7389 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
7390 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
7391 #define BXT_DE_PLL_LOCK (1 << 30)
7392 #define BXT_DE_PLL_FREQ_REQ (1 << 23)
7393 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
7394 #define ICL_CDCLK_PLL_RATIO(x) (x)
7395 #define ICL_CDCLK_PLL_RATIO_MASK 0xff
7398 #define DC_STATE_EN _MMIO(0x45504)
7399 #define DC_STATE_DISABLE 0
7400 #define DC_STATE_EN_DC3CO REG_BIT(30)
7401 #define DC_STATE_DC3CO_STATUS REG_BIT(29)
7402 #define DC_STATE_EN_UPTO_DC5 (1 << 0)
7403 #define DC_STATE_EN_DC9 (1 << 3)
7404 #define DC_STATE_EN_UPTO_DC6 (2 << 0)
7405 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
7407 #define DC_STATE_DEBUG _MMIO(0x45520)
7408 #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
7409 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
7411 #define D_COMP_BDW _MMIO(0x138144)
7413 /* Pipe WM_LINETIME - watermark line time */
7414 #define _WM_LINETIME_A 0x45270
7415 #define _WM_LINETIME_B 0x45274
7416 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
7417 #define HSW_LINETIME_MASK REG_GENMASK(8, 0)
7418 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
7419 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
7420 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
7423 #define SFUSE_STRAP _MMIO(0xc2014)
7424 #define SFUSE_STRAP_FUSE_LOCK (1 << 13)
7425 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
7426 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
7427 #define SFUSE_STRAP_CRT_DISABLED (1 << 6)
7428 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
7429 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
7430 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
7431 #define SFUSE_STRAP_DDID_DETECTED (1 << 0)
7433 #define WM_MISC _MMIO(0x45260)
7434 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
7436 #define WM_DBG _MMIO(0x45280)
7437 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
7438 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
7439 #define WM_DBG_DISALLOW_SPRITE (1 << 2)
7442 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
7443 #define _PIPE_A_CSC_COEFF_BY 0x49014
7444 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
7445 #define _PIPE_A_CSC_COEFF_BU 0x4901c
7446 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
7447 #define _PIPE_A_CSC_COEFF_BV 0x49024
7449 #define _PIPE_A_CSC_MODE 0x49028
7450 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */
7451 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */
7452 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */
7453 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
7454 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */
7456 #define _PIPE_A_CSC_PREOFF_HI 0x49030
7457 #define _PIPE_A_CSC_PREOFF_ME 0x49034
7458 #define _PIPE_A_CSC_PREOFF_LO 0x49038
7459 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
7460 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
7461 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
7463 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
7464 #define _PIPE_B_CSC_COEFF_BY 0x49114
7465 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
7466 #define _PIPE_B_CSC_COEFF_BU 0x4911c
7467 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
7468 #define _PIPE_B_CSC_COEFF_BV 0x49124
7469 #define _PIPE_B_CSC_MODE 0x49128
7470 #define _PIPE_B_CSC_PREOFF_HI 0x49130
7471 #define _PIPE_B_CSC_PREOFF_ME 0x49134
7472 #define _PIPE_B_CSC_PREOFF_LO 0x49138
7473 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
7474 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
7475 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
7477 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7478 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7479 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
7480 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
7481 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
7482 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
7483 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
7484 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
7485 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
7486 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
7487 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
7488 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
7489 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
7491 /* Pipe Output CSC */
7492 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
7493 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
7494 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
7495 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
7496 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
7497 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
7498 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
7499 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
7500 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
7501 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
7502 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
7503 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
7505 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
7506 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
7507 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
7508 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
7509 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
7510 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
7511 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
7512 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
7513 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
7514 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
7515 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
7516 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
7518 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
7519 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
7520 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
7521 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
7522 _PIPE_A_OUTPUT_CSC_COEFF_BY, \
7523 _PIPE_B_OUTPUT_CSC_COEFF_BY)
7524 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
7525 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
7526 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
7527 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
7528 _PIPE_A_OUTPUT_CSC_COEFF_BU, \
7529 _PIPE_B_OUTPUT_CSC_COEFF_BU)
7530 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
7531 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
7532 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
7533 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
7534 _PIPE_A_OUTPUT_CSC_COEFF_BV, \
7535 _PIPE_B_OUTPUT_CSC_COEFF_BV)
7536 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
7537 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
7538 _PIPE_B_OUTPUT_CSC_PREOFF_HI)
7539 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
7540 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
7541 _PIPE_B_OUTPUT_CSC_PREOFF_ME)
7542 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
7543 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
7544 _PIPE_B_OUTPUT_CSC_PREOFF_LO)
7545 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
7546 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
7547 _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
7548 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
7549 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
7550 _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
7551 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
7552 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
7553 _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
7555 /* pipe degamma/gamma LUTs on IVB+ */
7556 #define _PAL_PREC_INDEX_A 0x4A400
7557 #define _PAL_PREC_INDEX_B 0x4AC00
7558 #define _PAL_PREC_INDEX_C 0x4B400
7559 #define PAL_PREC_10_12_BIT (0 << 31)
7560 #define PAL_PREC_SPLIT_MODE (1 << 31)
7561 #define PAL_PREC_AUTO_INCREMENT (1 << 15)
7562 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
7563 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
7564 #define _PAL_PREC_DATA_A 0x4A404
7565 #define _PAL_PREC_DATA_B 0x4AC04
7566 #define _PAL_PREC_DATA_C 0x4B404
7567 /* see PREC_PALETTE_* for the bits */
7568 #define _PAL_PREC_GC_MAX_A 0x4A410
7569 #define _PAL_PREC_GC_MAX_B 0x4AC10
7570 #define _PAL_PREC_GC_MAX_C 0x4B410
7571 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
7572 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
7573 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
7574 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
7575 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
7576 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
7578 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
7579 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
7580 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
7581 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
7582 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
7584 #define _PRE_CSC_GAMC_INDEX_A 0x4A484
7585 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
7586 #define _PRE_CSC_GAMC_INDEX_C 0x4B484
7587 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
7588 #define _PRE_CSC_GAMC_DATA_A 0x4A488
7589 #define _PRE_CSC_GAMC_DATA_B 0x4AC88
7590 #define _PRE_CSC_GAMC_DATA_C 0x4B488
7592 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
7593 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
7595 /* ICL Multi segmented gamma */
7596 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
7597 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
7598 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
7599 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0)
7601 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
7602 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
7603 /* see PREC_PALETTE_12P4_* for the bits */
7605 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
7606 _PAL_PREC_MULTI_SEG_INDEX_A, \
7607 _PAL_PREC_MULTI_SEG_INDEX_B)
7608 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
7609 _PAL_PREC_MULTI_SEG_DATA_A, \
7610 _PAL_PREC_MULTI_SEG_DATA_B)
7612 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
7614 /* Plane CSC Registers */
7615 #define _PLANE_CSC_RY_GY_1_A 0x70210
7616 #define _PLANE_CSC_RY_GY_2_A 0x70310
7618 #define _PLANE_CSC_RY_GY_1_B 0x71210
7619 #define _PLANE_CSC_RY_GY_2_B 0x71310
7621 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
7622 _PLANE_CSC_RY_GY_1_B)
7623 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
7624 _PLANE_INPUT_CSC_RY_GY_2_B)
7625 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
7626 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
7627 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
7629 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228
7630 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328
7632 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228
7633 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328
7635 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
7636 _PLANE_CSC_PREOFF_HI_1_B)
7637 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
7638 _PLANE_CSC_PREOFF_HI_2_B)
7639 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
7640 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
7643 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
7644 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
7646 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
7647 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
7649 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
7650 _PLANE_CSC_POSTOFF_HI_1_B)
7651 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
7652 _PLANE_CSC_POSTOFF_HI_2_B)
7653 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
7654 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
7657 /* pipe CSC & degamma/gamma LUTs on CHV */
7658 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
7659 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
7660 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
7661 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
7662 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
7663 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
7664 /* cgm degamma ldw */
7665 #define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16)
7666 #define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0)
7667 /* cgm degamma udw */
7668 #define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0)
7669 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
7671 #define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16)
7672 #define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0)
7674 #define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0)
7675 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
7676 #define CGM_PIPE_MODE_GAMMA (1 << 2)
7677 #define CGM_PIPE_MODE_CSC (1 << 1)
7678 #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
7680 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
7681 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
7682 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
7683 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
7684 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
7685 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
7686 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
7687 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
7689 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
7690 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
7691 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
7692 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
7693 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
7694 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
7695 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
7696 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
7698 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
7699 #define GEN4_TIMESTAMP _MMIO(0x2358)
7700 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
7701 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
7703 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
7704 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
7705 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
7706 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
7707 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
7709 #define _PIPE_FRMTMSTMP_A 0x70048
7710 #define PIPE_FRMTMSTMP(pipe) \
7711 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
7713 /* Display Stream Splitter Control */
7714 #define DSS_CTL1 _MMIO(0x67400)
7715 #define SPLITTER_ENABLE (1 << 31)
7716 #define JOINER_ENABLE (1 << 30)
7717 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
7718 #define DUAL_LINK_MODE_FRONTBACK (0 << 24)
7719 #define OVERLAP_PIXELS_MASK (0xf << 16)
7720 #define OVERLAP_PIXELS(pixels) ((pixels) << 16)
7721 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
7722 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
7723 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
7725 #define DSS_CTL2 _MMIO(0x67404)
7726 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
7727 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
7728 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
7729 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
7731 #define _ICL_PIPE_DSS_CTL1_PB 0x78200
7732 #define _ICL_PIPE_DSS_CTL1_PC 0x78400
7733 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7734 _ICL_PIPE_DSS_CTL1_PB, \
7735 _ICL_PIPE_DSS_CTL1_PC)
7736 #define BIG_JOINER_ENABLE (1 << 29)
7737 #define MASTER_BIG_JOINER_ENABLE (1 << 28)
7738 #define VGA_CENTERING_ENABLE (1 << 27)
7739 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
7740 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
7741 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
7742 #define UNCOMPRESSED_JOINER_MASTER (1 << 21)
7743 #define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
7745 #define _ICL_PIPE_DSS_CTL2_PB 0x78204
7746 #define _ICL_PIPE_DSS_CTL2_PC 0x78404
7747 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7748 _ICL_PIPE_DSS_CTL2_PB, \
7749 _ICL_PIPE_DSS_CTL2_PC)
7751 #define GGC _MMIO(0x108040)
7752 #define GMS_MASK REG_GENMASK(15, 8)
7753 #define GGMS_MASK REG_GENMASK(7, 6)
7755 #define GEN12_GSMBASE _MMIO(0x108100)
7756 #define GEN12_DSMBASE _MMIO(0x1080C0)
7757 #define GEN12_BDSM_MASK REG_GENMASK64(63, 20)
7759 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
7760 #define SGSI_SIDECLK_DIS REG_BIT(17)
7761 #define SGGI_DIS REG_BIT(15)
7762 #define SGR_DIS REG_BIT(13)
7764 #define _ICL_PHY_MISC_A 0x64C00
7765 #define _ICL_PHY_MISC_B 0x64C04
7766 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
7767 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
7768 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
7770 #define ICL_PHY_MISC_MUX_DDID (1 << 28)
7771 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
7772 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
7774 /* Icelake Display Stream Compression Registers */
7775 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
7776 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
7777 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
7778 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
7779 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
7780 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
7781 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7782 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
7783 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
7784 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7785 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
7786 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
7787 #define DSC_ALT_ICH_SEL (1 << 20)
7788 #define DSC_VBR_ENABLE (1 << 19)
7789 #define DSC_422_ENABLE (1 << 18)
7790 #define DSC_COLOR_SPACE_CONVERSION (1 << 17)
7791 #define DSC_BLOCK_PREDICTION (1 << 16)
7792 #define DSC_LINE_BUF_DEPTH_SHIFT 12
7793 #define DSC_BPC_SHIFT 8
7794 #define DSC_VER_MIN_SHIFT 4
7795 #define DSC_VER_MAJ (0x1 << 0)
7797 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
7798 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
7799 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
7800 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
7801 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
7802 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
7803 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7804 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
7805 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
7806 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7807 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
7808 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
7809 #define DSC_BPP(bpp) ((bpp) << 0)
7811 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
7812 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
7813 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
7814 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
7815 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
7816 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
7817 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7818 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
7819 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
7820 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7821 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
7822 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
7823 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
7824 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
7826 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
7827 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
7828 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
7829 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
7830 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
7831 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
7832 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7833 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
7834 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
7835 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7836 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
7837 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
7838 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
7839 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
7841 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
7842 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
7843 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
7844 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
7845 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
7846 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
7847 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7848 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
7849 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
7850 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7851 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
7852 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
7853 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
7854 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
7856 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
7857 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
7858 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
7859 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
7860 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
7861 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
7862 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7863 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
7864 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
7865 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7866 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
7867 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
7868 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
7869 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
7871 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
7872 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
7873 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
7874 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
7875 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
7876 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
7877 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7878 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
7879 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
7880 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7881 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
7882 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
7883 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
7884 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
7885 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
7886 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
7888 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
7889 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
7890 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
7891 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
7892 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
7893 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
7894 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7895 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
7896 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
7897 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7898 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
7899 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
7900 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
7901 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
7903 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
7904 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
7905 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
7906 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
7907 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
7908 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
7909 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7910 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
7911 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
7912 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7913 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
7914 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
7915 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
7916 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
7918 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
7919 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
7920 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
7921 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
7922 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
7923 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
7924 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7925 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
7926 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
7927 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7928 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
7929 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
7930 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
7931 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
7933 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
7934 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
7935 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
7936 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
7937 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
7938 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
7939 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7940 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
7941 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
7942 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7943 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
7944 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
7945 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
7946 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
7947 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
7948 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
7950 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
7951 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
7952 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
7953 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
7954 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
7955 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
7956 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7957 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
7958 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
7959 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7960 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
7961 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
7963 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
7964 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
7965 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
7966 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
7967 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
7968 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
7969 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7970 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
7971 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
7972 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7973 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
7974 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
7976 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
7977 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
7978 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
7979 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
7980 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
7981 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
7982 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7983 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
7984 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
7985 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7986 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
7987 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
7989 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
7990 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
7991 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
7992 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
7993 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
7994 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
7995 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7996 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
7997 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
7998 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7999 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
8000 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
8002 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
8003 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
8004 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
8005 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
8006 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
8007 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
8008 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8009 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
8010 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
8011 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8012 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
8013 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
8015 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
8016 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
8017 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
8018 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
8019 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
8020 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
8021 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8022 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
8023 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
8024 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8025 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
8026 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
8027 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
8028 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
8029 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
8031 /* Icelake Rate Control Buffer Threshold Registers */
8032 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
8033 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
8034 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
8035 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
8036 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
8037 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
8038 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
8039 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
8040 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
8041 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
8042 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
8043 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
8044 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8045 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
8046 _ICL_DSC0_RC_BUF_THRESH_0_PC)
8047 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8048 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
8049 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
8050 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8051 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
8052 _ICL_DSC1_RC_BUF_THRESH_0_PC)
8053 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8054 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
8055 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
8057 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
8058 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
8059 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
8060 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
8061 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
8062 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
8063 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
8064 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
8065 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
8066 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
8067 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
8068 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
8069 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8070 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
8071 _ICL_DSC0_RC_BUF_THRESH_1_PC)
8072 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8073 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
8074 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
8075 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8076 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
8077 _ICL_DSC1_RC_BUF_THRESH_1_PC)
8078 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8079 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
8080 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
8082 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
8083 #define MODULAR_FIA_MASK (1 << 4)
8084 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
8085 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
8086 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
8087 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
8088 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
8090 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
8091 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
8093 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
8094 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
8096 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
8097 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
8098 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
8099 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
8101 #define _TCSS_DDI_STATUS_1 0x161500
8102 #define _TCSS_DDI_STATUS_2 0x161504
8103 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
8104 _TCSS_DDI_STATUS_1, \
8105 _TCSS_DDI_STATUS_2))
8106 #define TCSS_DDI_STATUS_READY REG_BIT(2)
8107 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
8108 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
8110 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
8111 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
8112 #define PRIMARY_SPI_REGIONID _MMIO(0x102084)
8113 #define SPI_STATIC_REGIONS _MMIO(0x102090)
8114 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
8115 #define OROM_OFFSET _MMIO(0x1020c0)
8116 #define OROM_OFFSET_MASK REG_GENMASK(20, 16)
8118 /* This register controls the Display State Buffer (DSB) engines. */
8119 #define _DSBSL_INSTANCE_BASE 0x70B00
8120 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
8121 (pipe) * 0x1000 + (id) * 0x100)
8122 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
8123 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
8124 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
8125 #define DSB_ENABLE (1 << 31)
8126 #define DSB_STATUS (1 << 0)
8128 #define CLKREQ_POLICY _MMIO(0x101038)
8129 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
8131 #define CLKGATE_DIS_MISC _MMIO(0x46534)
8132 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
8134 #define GEN12_CULLBIT1 _MMIO(0x6100)
8135 #define GEN12_CULLBIT2 _MMIO(0x7030)
8136 #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC)
8138 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
8139 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
8140 #define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A)
8141 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
8143 #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
8144 #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
8145 #define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
8146 #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
8147 #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
8149 #define MTL_LATENCY_SAGV _MMIO(0x4578b)
8150 #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
8152 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
8153 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
8154 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
8155 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
8157 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2)
8158 #define MTL_TRCD_MASK REG_GENMASK(31, 24)
8159 #define MTL_TRP_MASK REG_GENMASK(23, 16)
8160 #define MTL_DCLK_MASK REG_GENMASK(15, 0)
8162 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2)
8163 #define MTL_TRAS_MASK REG_GENMASK(16, 8)
8164 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
8166 #define MTL_MEDIA_GSI_BASE 0x380000
8168 #endif /* _I915_REG_H_ */