1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "i915_reg_defs.h"
29 #include "display/intel_display_reg_defs.h"
32 * DOC: The i915 register macro definition style guide
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
40 * Keep helper macros near the top. For example, _PIPE() and friends.
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
54 * For single registers, define the register offset first, followed by register
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
119 #define GU_CNTL _MMIO(0x101010)
120 #define LMEM_INIT REG_BIT(7)
121 #define DRIVERFLR REG_BIT(31)
122 #define GU_DEBUG _MMIO(0x101018)
123 #define DRIVERFLR_STATUS REG_BIT(31)
125 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
126 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
127 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
128 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
129 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
130 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
131 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
132 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
133 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
134 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
135 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
136 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
137 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
138 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
139 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
140 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
141 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
142 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
144 #define _VGA_MSR_WRITE _MMIO(0x3c2)
146 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
147 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
148 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
153 #define DEBUG_RESET_I830 _MMIO(0x6070)
154 #define DEBUG_RESET_FULL (1 << 7)
155 #define DEBUG_RESET_RENDER (1 << 8)
156 #define DEBUG_RESET_DISPLAY (1 << 9)
161 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
162 #define IOSF_DEVFN_SHIFT 24
163 #define IOSF_OPCODE_SHIFT 16
164 #define IOSF_PORT_SHIFT 8
165 #define IOSF_BYTE_ENABLES_SHIFT 4
166 #define IOSF_BAR_SHIFT 1
167 #define IOSF_SB_BUSY (1 << 0)
168 #define IOSF_PORT_BUNIT 0x03
169 #define IOSF_PORT_PUNIT 0x04
170 #define IOSF_PORT_NC 0x11
171 #define IOSF_PORT_DPIO 0x12
172 #define IOSF_PORT_GPIO_NC 0x13
173 #define IOSF_PORT_CCK 0x14
174 #define IOSF_PORT_DPIO_2 0x1a
175 #define IOSF_PORT_FLISDSI 0x1b
176 #define IOSF_PORT_GPIO_SC 0x48
177 #define IOSF_PORT_GPIO_SUS 0xa8
178 #define IOSF_PORT_CCU 0xa9
179 #define CHV_IOSF_PORT_GPIO_N 0x13
180 #define CHV_IOSF_PORT_GPIO_SE 0x48
181 #define CHV_IOSF_PORT_GPIO_E 0xa8
182 #define CHV_IOSF_PORT_GPIO_SW 0xb2
183 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
184 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
189 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
190 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
191 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
192 #define DPIO_SFR_BYPASS (1 << 1)
193 #define DPIO_CMNRST (1 << 0)
195 #define DPIO_PHY(pipe) ((pipe) >> 1)
198 * Per pipe/PLL DPIO regs
200 #define _VLV_PLL_DW3_CH0 0x800c
201 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
202 #define DPIO_POST_DIV_DAC 0
203 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
204 #define DPIO_POST_DIV_LVDS1 2
205 #define DPIO_POST_DIV_LVDS2 3
206 #define DPIO_K_SHIFT (24) /* 4 bits */
207 #define DPIO_P1_SHIFT (21) /* 3 bits */
208 #define DPIO_P2_SHIFT (16) /* 5 bits */
209 #define DPIO_N_SHIFT (12) /* 4 bits */
210 #define DPIO_ENABLE_CALIBRATION (1 << 11)
211 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
212 #define DPIO_M2DIV_MASK 0xff
213 #define _VLV_PLL_DW3_CH1 0x802c
214 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
216 #define _VLV_PLL_DW5_CH0 0x8014
217 #define DPIO_REFSEL_OVERRIDE 27
218 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
219 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
220 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
221 #define DPIO_PLL_REFCLK_SEL_MASK 3
222 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
223 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
224 #define _VLV_PLL_DW5_CH1 0x8034
225 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
227 #define _VLV_PLL_DW7_CH0 0x801c
228 #define _VLV_PLL_DW7_CH1 0x803c
229 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
231 #define _VLV_PLL_DW8_CH0 0x8040
232 #define _VLV_PLL_DW8_CH1 0x8060
233 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
235 #define VLV_PLL_DW9_BCAST 0xc044
236 #define _VLV_PLL_DW9_CH0 0x8044
237 #define _VLV_PLL_DW9_CH1 0x8064
238 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
240 #define _VLV_PLL_DW10_CH0 0x8048
241 #define _VLV_PLL_DW10_CH1 0x8068
242 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
244 #define _VLV_PLL_DW11_CH0 0x804c
245 #define _VLV_PLL_DW11_CH1 0x806c
246 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
248 /* Spec for ref block start counts at DW10 */
249 #define VLV_REF_DW13 0x80ac
251 #define VLV_CMN_DW0 0x8100
254 * Per DDI channel DPIO regs
257 #define _VLV_PCS_DW0_CH0 0x8200
258 #define _VLV_PCS_DW0_CH1 0x8400
259 #define DPIO_PCS_TX_LANE2_RESET (1 << 16)
260 #define DPIO_PCS_TX_LANE1_RESET (1 << 7)
261 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
262 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
263 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
265 #define _VLV_PCS01_DW0_CH0 0x200
266 #define _VLV_PCS23_DW0_CH0 0x400
267 #define _VLV_PCS01_DW0_CH1 0x2600
268 #define _VLV_PCS23_DW0_CH1 0x2800
269 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
270 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
272 #define _VLV_PCS_DW1_CH0 0x8204
273 #define _VLV_PCS_DW1_CH1 0x8404
274 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
275 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
276 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
277 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
278 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
279 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
281 #define _VLV_PCS01_DW1_CH0 0x204
282 #define _VLV_PCS23_DW1_CH0 0x404
283 #define _VLV_PCS01_DW1_CH1 0x2604
284 #define _VLV_PCS23_DW1_CH1 0x2804
285 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
286 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
288 #define _VLV_PCS_DW8_CH0 0x8220
289 #define _VLV_PCS_DW8_CH1 0x8420
290 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
291 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
292 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
294 #define _VLV_PCS01_DW8_CH0 0x0220
295 #define _VLV_PCS23_DW8_CH0 0x0420
296 #define _VLV_PCS01_DW8_CH1 0x2620
297 #define _VLV_PCS23_DW8_CH1 0x2820
298 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
299 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
301 #define _VLV_PCS_DW9_CH0 0x8224
302 #define _VLV_PCS_DW9_CH1 0x8424
303 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
304 #define DPIO_PCS_TX2MARGIN_000 (0 << 13)
305 #define DPIO_PCS_TX2MARGIN_101 (1 << 13)
306 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
307 #define DPIO_PCS_TX1MARGIN_000 (0 << 10)
308 #define DPIO_PCS_TX1MARGIN_101 (1 << 10)
309 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
311 #define _VLV_PCS01_DW9_CH0 0x224
312 #define _VLV_PCS23_DW9_CH0 0x424
313 #define _VLV_PCS01_DW9_CH1 0x2624
314 #define _VLV_PCS23_DW9_CH1 0x2824
315 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
316 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
318 #define _CHV_PCS_DW10_CH0 0x8228
319 #define _CHV_PCS_DW10_CH1 0x8428
320 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
321 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
322 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
323 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
324 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
325 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
326 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
327 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
328 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
330 #define _VLV_PCS01_DW10_CH0 0x0228
331 #define _VLV_PCS23_DW10_CH0 0x0428
332 #define _VLV_PCS01_DW10_CH1 0x2628
333 #define _VLV_PCS23_DW10_CH1 0x2828
334 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
335 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
337 #define _VLV_PCS_DW11_CH0 0x822c
338 #define _VLV_PCS_DW11_CH1 0x842c
339 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
340 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
341 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
342 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
343 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
345 #define _VLV_PCS01_DW11_CH0 0x022c
346 #define _VLV_PCS23_DW11_CH0 0x042c
347 #define _VLV_PCS01_DW11_CH1 0x262c
348 #define _VLV_PCS23_DW11_CH1 0x282c
349 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
350 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
352 #define _VLV_PCS01_DW12_CH0 0x0230
353 #define _VLV_PCS23_DW12_CH0 0x0430
354 #define _VLV_PCS01_DW12_CH1 0x2630
355 #define _VLV_PCS23_DW12_CH1 0x2830
356 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
357 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
359 #define _VLV_PCS_DW12_CH0 0x8230
360 #define _VLV_PCS_DW12_CH1 0x8430
361 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
362 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
363 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
364 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
365 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
366 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
368 #define _VLV_PCS_DW14_CH0 0x8238
369 #define _VLV_PCS_DW14_CH1 0x8438
370 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
372 #define _VLV_PCS_DW23_CH0 0x825c
373 #define _VLV_PCS_DW23_CH1 0x845c
374 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
376 #define _VLV_TX_DW2_CH0 0x8288
377 #define _VLV_TX_DW2_CH1 0x8488
378 #define DPIO_SWING_MARGIN000_SHIFT 16
379 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
380 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
381 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
383 #define _VLV_TX_DW3_CH0 0x828c
384 #define _VLV_TX_DW3_CH1 0x848c
385 /* The following bit for CHV phy */
386 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
387 #define DPIO_SWING_MARGIN101_SHIFT 16
388 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
389 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
391 #define _VLV_TX_DW4_CH0 0x8290
392 #define _VLV_TX_DW4_CH1 0x8490
393 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
394 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
395 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
396 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
397 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
399 #define _VLV_TX3_DW4_CH0 0x690
400 #define _VLV_TX3_DW4_CH1 0x2a90
401 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
403 #define _VLV_TX_DW5_CH0 0x8294
404 #define _VLV_TX_DW5_CH1 0x8494
405 #define DPIO_TX_OCALINIT_EN (1 << 31)
406 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
408 #define _VLV_TX_DW11_CH0 0x82ac
409 #define _VLV_TX_DW11_CH1 0x84ac
410 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
412 #define _VLV_TX_DW14_CH0 0x82b8
413 #define _VLV_TX_DW14_CH1 0x84b8
414 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
416 /* CHV dpPhy registers */
417 #define _CHV_PLL_DW0_CH0 0x8000
418 #define _CHV_PLL_DW0_CH1 0x8180
419 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
421 #define _CHV_PLL_DW1_CH0 0x8004
422 #define _CHV_PLL_DW1_CH1 0x8184
423 #define DPIO_CHV_N_DIV_SHIFT 8
424 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
425 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
427 #define _CHV_PLL_DW2_CH0 0x8008
428 #define _CHV_PLL_DW2_CH1 0x8188
429 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
431 #define _CHV_PLL_DW3_CH0 0x800c
432 #define _CHV_PLL_DW3_CH1 0x818c
433 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
434 #define DPIO_CHV_FIRST_MOD (0 << 8)
435 #define DPIO_CHV_SECOND_MOD (1 << 8)
436 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
437 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
438 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
440 #define _CHV_PLL_DW6_CH0 0x8018
441 #define _CHV_PLL_DW6_CH1 0x8198
442 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
443 #define DPIO_CHV_INT_COEFF_SHIFT 8
444 #define DPIO_CHV_PROP_COEFF_SHIFT 0
445 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
447 #define _CHV_PLL_DW8_CH0 0x8020
448 #define _CHV_PLL_DW8_CH1 0x81A0
449 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
450 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
451 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
453 #define _CHV_PLL_DW9_CH0 0x8024
454 #define _CHV_PLL_DW9_CH1 0x81A4
455 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
456 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
457 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
458 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
460 #define _CHV_CMN_DW0_CH0 0x8100
461 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
462 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
463 #define DPIO_ALLDL_POWERDOWN (1 << 1)
464 #define DPIO_ANYDL_POWERDOWN (1 << 0)
466 #define _CHV_CMN_DW5_CH0 0x8114
467 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
468 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
469 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
470 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
471 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
472 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
473 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
474 #define CHV_BUFLEFTENA1_MASK (3 << 22)
476 #define _CHV_CMN_DW13_CH0 0x8134
477 #define _CHV_CMN_DW0_CH1 0x8080
478 #define DPIO_CHV_S1_DIV_SHIFT 21
479 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
480 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
481 #define DPIO_CHV_K_DIV_SHIFT 4
482 #define DPIO_PLL_FREQLOCK (1 << 1)
483 #define DPIO_PLL_LOCK (1 << 0)
484 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
486 #define _CHV_CMN_DW14_CH0 0x8138
487 #define _CHV_CMN_DW1_CH1 0x8084
488 #define DPIO_AFC_RECAL (1 << 14)
489 #define DPIO_DCLKP_EN (1 << 13)
490 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
491 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
492 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
493 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
494 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
495 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
496 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
497 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
498 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
500 #define _CHV_CMN_DW19_CH0 0x814c
501 #define _CHV_CMN_DW6_CH1 0x8098
502 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
503 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
504 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
505 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
507 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
509 #define CHV_CMN_DW28 0x8170
510 #define DPIO_CL1POWERDOWNEN (1 << 23)
511 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
512 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
513 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
514 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
515 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
517 #define CHV_CMN_DW30 0x8178
518 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
519 #define DPIO_LRC_BYPASS (1 << 3)
521 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
522 (lane) * 0x200 + (offset))
524 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
525 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
526 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
527 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
528 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
529 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
530 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
531 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
532 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
533 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
534 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
535 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
536 #define DPIO_FRC_LATENCY_SHFIT 8
537 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
538 #define DPIO_UPAR_SHIFT 30
540 /* BXT PHY registers */
541 #define _BXT_PHY0_BASE 0x6C000
542 #define _BXT_PHY1_BASE 0x162000
543 #define _BXT_PHY2_BASE 0x163000
544 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
548 #define _BXT_PHY(phy, reg) \
549 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
551 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
552 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
553 (reg_ch1) - _BXT_PHY0_BASE))
554 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
555 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
557 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
558 #define MIPIO_RST_CTRL (1 << 2)
560 #define _BXT_PHY_CTL_DDI_A 0x64C00
561 #define _BXT_PHY_CTL_DDI_B 0x64C10
562 #define _BXT_PHY_CTL_DDI_C 0x64C20
563 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
564 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
565 #define BXT_PHY_LANE_ENABLED (1 << 8)
566 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
569 #define _PHY_CTL_FAMILY_EDP 0x64C80
570 #define _PHY_CTL_FAMILY_DDI 0x64C90
571 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
572 #define COMMON_RESET_DIS (1 << 31)
573 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
574 _PHY_CTL_FAMILY_EDP, \
575 _PHY_CTL_FAMILY_DDI_C)
577 /* BXT PHY PLL registers */
578 #define _PORT_PLL_A 0x46074
579 #define _PORT_PLL_B 0x46078
580 #define _PORT_PLL_C 0x4607c
581 #define PORT_PLL_ENABLE REG_BIT(31)
582 #define PORT_PLL_LOCK REG_BIT(30)
583 #define PORT_PLL_REF_SEL REG_BIT(27)
584 #define PORT_PLL_POWER_ENABLE REG_BIT(26)
585 #define PORT_PLL_POWER_STATE REG_BIT(25)
586 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
588 #define _PORT_PLL_EBB_0_A 0x162034
589 #define _PORT_PLL_EBB_0_B 0x6C034
590 #define _PORT_PLL_EBB_0_C 0x6C340
591 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
592 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
593 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
594 #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
595 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
599 #define _PORT_PLL_EBB_4_A 0x162038
600 #define _PORT_PLL_EBB_4_B 0x6C038
601 #define _PORT_PLL_EBB_4_C 0x6C344
602 #define PORT_PLL_RECALIBRATE REG_BIT(14)
603 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
604 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
608 #define _PORT_PLL_0_A 0x162100
609 #define _PORT_PLL_0_B 0x6C100
610 #define _PORT_PLL_0_C 0x6C380
612 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
613 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
615 #define PORT_PLL_N_MASK REG_GENMASK(11, 8)
616 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
618 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
619 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
621 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
623 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
624 #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
625 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
626 #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
627 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
628 #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
630 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
631 #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
633 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
634 #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
636 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
637 #define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10)
638 #define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
639 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
642 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
645 /* BXT PHY common lane registers */
646 #define _PORT_CL1CM_DW0_A 0x162000
647 #define _PORT_CL1CM_DW0_BC 0x6C000
648 #define PHY_POWER_GOOD (1 << 16)
649 #define PHY_RESERVED (1 << 7)
650 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
652 #define _PORT_CL1CM_DW9_A 0x162024
653 #define _PORT_CL1CM_DW9_BC 0x6C024
654 #define IREF0RC_OFFSET_SHIFT 8
655 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
656 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
658 #define _PORT_CL1CM_DW10_A 0x162028
659 #define _PORT_CL1CM_DW10_BC 0x6C028
660 #define IREF1RC_OFFSET_SHIFT 8
661 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
662 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
664 #define _PORT_CL1CM_DW28_A 0x162070
665 #define _PORT_CL1CM_DW28_BC 0x6C070
666 #define OCL1_POWER_DOWN_EN (1 << 23)
667 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
668 #define SUS_CLK_CONFIG 0x3
669 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
671 #define _PORT_CL1CM_DW30_A 0x162078
672 #define _PORT_CL1CM_DW30_BC 0x6C078
673 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
674 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
676 /* The spec defines this only for BXT PHY0, but lets assume that this
677 * would exist for PHY1 too if it had a second channel.
679 #define _PORT_CL2CM_DW6_A 0x162358
680 #define _PORT_CL2CM_DW6_BC 0x6C358
681 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
682 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
684 /* BXT PHY Ref registers */
685 #define _PORT_REF_DW3_A 0x16218C
686 #define _PORT_REF_DW3_BC 0x6C18C
687 #define GRC_DONE (1 << 22)
688 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
690 #define _PORT_REF_DW6_A 0x162198
691 #define _PORT_REF_DW6_BC 0x6C198
692 #define GRC_CODE_SHIFT 24
693 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
694 #define GRC_CODE_FAST_SHIFT 16
695 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
696 #define GRC_CODE_SLOW_SHIFT 8
697 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
698 #define GRC_CODE_NOM_MASK 0xFF
699 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
701 #define _PORT_REF_DW8_A 0x1621A0
702 #define _PORT_REF_DW8_BC 0x6C1A0
703 #define GRC_DIS (1 << 15)
704 #define GRC_RDY_OVRD (1 << 1)
705 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
707 /* BXT PHY PCS registers */
708 #define _PORT_PCS_DW10_LN01_A 0x162428
709 #define _PORT_PCS_DW10_LN01_B 0x6C428
710 #define _PORT_PCS_DW10_LN01_C 0x6C828
711 #define _PORT_PCS_DW10_GRP_A 0x162C28
712 #define _PORT_PCS_DW10_GRP_B 0x6CC28
713 #define _PORT_PCS_DW10_GRP_C 0x6CE28
714 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
715 _PORT_PCS_DW10_LN01_B, \
716 _PORT_PCS_DW10_LN01_C)
717 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
718 _PORT_PCS_DW10_GRP_B, \
719 _PORT_PCS_DW10_GRP_C)
721 #define TX2_SWING_CALC_INIT (1 << 31)
722 #define TX1_SWING_CALC_INIT (1 << 30)
724 #define _PORT_PCS_DW12_LN01_A 0x162430
725 #define _PORT_PCS_DW12_LN01_B 0x6C430
726 #define _PORT_PCS_DW12_LN01_C 0x6C830
727 #define _PORT_PCS_DW12_LN23_A 0x162630
728 #define _PORT_PCS_DW12_LN23_B 0x6C630
729 #define _PORT_PCS_DW12_LN23_C 0x6CA30
730 #define _PORT_PCS_DW12_GRP_A 0x162c30
731 #define _PORT_PCS_DW12_GRP_B 0x6CC30
732 #define _PORT_PCS_DW12_GRP_C 0x6CE30
733 #define LANESTAGGER_STRAP_OVRD (1 << 6)
734 #define LANE_STAGGER_MASK 0x1F
735 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
736 _PORT_PCS_DW12_LN01_B, \
737 _PORT_PCS_DW12_LN01_C)
738 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
739 _PORT_PCS_DW12_LN23_B, \
740 _PORT_PCS_DW12_LN23_C)
741 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
742 _PORT_PCS_DW12_GRP_B, \
743 _PORT_PCS_DW12_GRP_C)
745 /* BXT PHY TX registers */
746 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
749 #define _PORT_TX_DW2_LN0_A 0x162508
750 #define _PORT_TX_DW2_LN0_B 0x6C508
751 #define _PORT_TX_DW2_LN0_C 0x6C908
752 #define _PORT_TX_DW2_GRP_A 0x162D08
753 #define _PORT_TX_DW2_GRP_B 0x6CD08
754 #define _PORT_TX_DW2_GRP_C 0x6CF08
755 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
756 _PORT_TX_DW2_LN0_B, \
758 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
759 _PORT_TX_DW2_GRP_B, \
761 #define MARGIN_000_SHIFT 16
762 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
763 #define UNIQ_TRANS_SCALE_SHIFT 8
764 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
766 #define _PORT_TX_DW3_LN0_A 0x16250C
767 #define _PORT_TX_DW3_LN0_B 0x6C50C
768 #define _PORT_TX_DW3_LN0_C 0x6C90C
769 #define _PORT_TX_DW3_GRP_A 0x162D0C
770 #define _PORT_TX_DW3_GRP_B 0x6CD0C
771 #define _PORT_TX_DW3_GRP_C 0x6CF0C
772 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
773 _PORT_TX_DW3_LN0_B, \
775 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
776 _PORT_TX_DW3_GRP_B, \
778 #define SCALE_DCOMP_METHOD (1 << 26)
779 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
781 #define _PORT_TX_DW4_LN0_A 0x162510
782 #define _PORT_TX_DW4_LN0_B 0x6C510
783 #define _PORT_TX_DW4_LN0_C 0x6C910
784 #define _PORT_TX_DW4_GRP_A 0x162D10
785 #define _PORT_TX_DW4_GRP_B 0x6CD10
786 #define _PORT_TX_DW4_GRP_C 0x6CF10
787 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
788 _PORT_TX_DW4_LN0_B, \
790 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
791 _PORT_TX_DW4_GRP_B, \
793 #define DEEMPH_SHIFT 24
794 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
796 #define _PORT_TX_DW5_LN0_A 0x162514
797 #define _PORT_TX_DW5_LN0_B 0x6C514
798 #define _PORT_TX_DW5_LN0_C 0x6C914
799 #define _PORT_TX_DW5_GRP_A 0x162D14
800 #define _PORT_TX_DW5_GRP_B 0x6CD14
801 #define _PORT_TX_DW5_GRP_C 0x6CF14
802 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
803 _PORT_TX_DW5_LN0_B, \
805 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
806 _PORT_TX_DW5_GRP_B, \
808 #define DCC_DELAY_RANGE_1 (1 << 9)
809 #define DCC_DELAY_RANGE_2 (1 << 8)
811 #define _PORT_TX_DW14_LN0_A 0x162538
812 #define _PORT_TX_DW14_LN0_B 0x6C538
813 #define _PORT_TX_DW14_LN0_C 0x6C938
814 #define LATENCY_OPTIM_SHIFT 30
815 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
816 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
817 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
818 _PORT_TX_DW14_LN0_C) + \
819 _BXT_LANE_OFFSET(lane))
821 /* UAIMI scratch pad register 1 */
822 #define UAIMI_SPR1 _MMIO(0x4F074)
824 #define SKL_VCCIO_MASK 0x1
825 /* SKL balance leg register */
826 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
828 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
829 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
830 /* Balance leg disable bits */
831 #define BALANCE_LEG_DISABLE_SHIFT 23
832 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
836 * [0-7] @ 0x2000 gen2,gen3
837 * [8-15] @ 0x3000 945,g33,pnv
839 * [0-15] @ 0x3000 gen4,gen5
841 * [0-15] @ 0x100000 gen6,vlv,chv
842 * [0-31] @ 0x100000 gen7+
844 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
845 #define I830_FENCE_START_MASK 0x07f80000
846 #define I830_FENCE_TILING_Y_SHIFT 12
847 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
848 #define I830_FENCE_PITCH_SHIFT 4
849 #define I830_FENCE_REG_VALID (1 << 0)
850 #define I915_FENCE_MAX_PITCH_VAL 4
851 #define I830_FENCE_MAX_PITCH_VAL 6
852 #define I830_FENCE_MAX_SIZE_VAL (1 << 8)
854 #define I915_FENCE_START_MASK 0x0ff00000
855 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
857 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
858 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
859 #define I965_FENCE_PITCH_SHIFT 2
860 #define I965_FENCE_TILING_Y_SHIFT 1
861 #define I965_FENCE_REG_VALID (1 << 0)
862 #define I965_FENCE_MAX_PITCH_VAL 0x0400
864 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
865 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
866 #define GEN6_FENCE_PITCH_SHIFT 32
867 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
870 /* control register for cpu gtt access */
871 #define TILECTL _MMIO(0x101000)
872 #define TILECTL_SWZCTL (1 << 0)
873 #define TILECTL_TLBPF (1 << 1)
874 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
875 #define TILECTL_BACKSNOOP_DIS (1 << 3)
878 * Instruction and interrupt control regs
880 #define PGTBL_CTL _MMIO(0x02020)
881 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
882 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
883 #define PGTBL_ER _MMIO(0x02024)
884 #define PRB0_BASE (0x2030 - 0x30)
885 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
886 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
887 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
888 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
889 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
890 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
891 #define RENDER_RING_BASE 0x02000
892 #define BSD_RING_BASE 0x04000
893 #define GEN6_BSD_RING_BASE 0x12000
894 #define GEN8_BSD2_RING_BASE 0x1c000
895 #define GEN11_BSD_RING_BASE 0x1c0000
896 #define GEN11_BSD2_RING_BASE 0x1c4000
897 #define GEN11_BSD3_RING_BASE 0x1d0000
898 #define GEN11_BSD4_RING_BASE 0x1d4000
899 #define XEHP_BSD5_RING_BASE 0x1e0000
900 #define XEHP_BSD6_RING_BASE 0x1e4000
901 #define XEHP_BSD7_RING_BASE 0x1f0000
902 #define XEHP_BSD8_RING_BASE 0x1f4000
903 #define VEBOX_RING_BASE 0x1a000
904 #define GEN11_VEBOX_RING_BASE 0x1c8000
905 #define GEN11_VEBOX2_RING_BASE 0x1d8000
906 #define XEHP_VEBOX3_RING_BASE 0x1e8000
907 #define XEHP_VEBOX4_RING_BASE 0x1f8000
908 #define MTL_GSC_RING_BASE 0x11a000
909 #define GEN12_COMPUTE0_RING_BASE 0x1a000
910 #define GEN12_COMPUTE1_RING_BASE 0x1c000
911 #define GEN12_COMPUTE2_RING_BASE 0x1e000
912 #define GEN12_COMPUTE3_RING_BASE 0x26000
913 #define BLT_RING_BASE 0x22000
914 #define XEHPC_BCS1_RING_BASE 0x3e0000
915 #define XEHPC_BCS2_RING_BASE 0x3e2000
916 #define XEHPC_BCS3_RING_BASE 0x3e4000
917 #define XEHPC_BCS4_RING_BASE 0x3e6000
918 #define XEHPC_BCS5_RING_BASE 0x3e8000
919 #define XEHPC_BCS6_RING_BASE 0x3ea000
920 #define XEHPC_BCS7_RING_BASE 0x3ec000
921 #define XEHPC_BCS8_RING_BASE 0x3ee000
922 #define DG1_GSC_HECI1_BASE 0x00258000
923 #define DG1_GSC_HECI2_BASE 0x00259000
924 #define DG2_GSC_HECI1_BASE 0x00373000
925 #define DG2_GSC_HECI2_BASE 0x00374000
929 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
930 #define GTT_CACHE_EN_ALL 0xF0007FFF
931 #define GEN7_WR_WATERMARK _MMIO(0x4028)
932 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
933 #define ARB_MODE _MMIO(0x4030)
934 #define ARB_MODE_SWIZZLE_SNB (1 << 4)
935 #define ARB_MODE_SWIZZLE_IVB (1 << 5)
936 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
937 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
938 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
939 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
940 #define GEN7_LRA_LIMITS_REG_NUM 13
941 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
942 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
944 #define GEN7_ERR_INT _MMIO(0x44040)
945 #define ERR_INT_POISON (1 << 31)
946 #define ERR_INT_MMIO_UNCLAIMED (1 << 13)
947 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
948 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
949 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
950 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
951 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
952 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
953 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
954 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
956 #define FPGA_DBG _MMIO(0x42300)
957 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
959 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
960 #define CLAIM_ER_CLR REG_BIT(31)
961 #define CLAIM_ER_OVERFLOW REG_BIT(16)
962 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
964 #define DERRMR _MMIO(0x44050)
965 /* Note that HBLANK events are reserved on bdw+ */
966 #define DERRMR_PIPEA_SCANLINE (1 << 0)
967 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
968 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
969 #define DERRMR_PIPEA_VBLANK (1 << 3)
970 #define DERRMR_PIPEA_HBLANK (1 << 5)
971 #define DERRMR_PIPEB_SCANLINE (1 << 8)
972 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
973 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
974 #define DERRMR_PIPEB_VBLANK (1 << 11)
975 #define DERRMR_PIPEB_HBLANK (1 << 13)
976 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
977 #define DERRMR_PIPEC_SCANLINE (1 << 14)
978 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
979 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
980 #define DERRMR_PIPEC_VBLANK (1 << 21)
981 #define DERRMR_PIPEC_HBLANK (1 << 22)
983 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
984 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
985 #define SCPD0 _MMIO(0x209c) /* 915+ only */
986 #define SCPD_FBC_IGNORE_3D (1 << 6)
987 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
988 #define GEN2_IER _MMIO(0x20a0)
989 #define GEN2_IIR _MMIO(0x20a4)
990 #define GEN2_IMR _MMIO(0x20a8)
991 #define GEN2_ISR _MMIO(0x20ac)
992 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
993 #define GINT_DIS (1 << 22)
994 #define GCFG_DIS (1 << 8)
995 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
996 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
997 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
998 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
999 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
1000 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
1001 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
1002 #define VLV_PCBR_ADDR_SHIFT 12
1004 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
1005 #define EIR _MMIO(0x20b0)
1006 #define EMR _MMIO(0x20b4)
1007 #define ESR _MMIO(0x20b8)
1008 #define GM45_ERROR_PAGE_TABLE (1 << 5)
1009 #define GM45_ERROR_MEM_PRIV (1 << 4)
1010 #define I915_ERROR_PAGE_TABLE (1 << 4)
1011 #define GM45_ERROR_CP_PRIV (1 << 3)
1012 #define I915_ERROR_MEMORY_REFRESH (1 << 1)
1013 #define I915_ERROR_INSTRUCTION (1 << 0)
1014 #define INSTPM _MMIO(0x20c0)
1015 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */
1016 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
1017 will not assert AGPBUSY# and will only
1018 be delivered when out of C3. */
1019 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
1020 #define INSTPM_TLB_INVALIDATE (1 << 9)
1021 #define INSTPM_SYNC_FLUSH (1 << 5)
1022 #define MEM_MODE _MMIO(0x20cc)
1023 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
1024 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
1025 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
1026 #define FW_BLC _MMIO(0x20d8)
1027 #define FW_BLC2 _MMIO(0x20dc)
1028 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
1029 #define FW_BLC_SELF_EN_MASK (1 << 31)
1030 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
1031 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */
1032 #define MM_BURST_LENGTH 0x00700000
1033 #define MM_FIFO_WATERMARK 0x0001F000
1034 #define LM_BURST_LENGTH 0x00000700
1035 #define LM_FIFO_WATERMARK 0x0000001F
1036 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
1038 #define _MBUS_ABOX0_CTL 0x45038
1039 #define _MBUS_ABOX1_CTL 0x45048
1040 #define _MBUS_ABOX2_CTL 0x4504C
1041 #define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
1044 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
1045 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
1046 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
1047 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
1048 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
1049 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
1050 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
1051 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
1053 #define _PIPEA_MBUS_DBOX_CTL 0x7003C
1054 #define _PIPEB_MBUS_DBOX_CTL 0x7103C
1055 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
1056 _PIPEB_MBUS_DBOX_CTL)
1057 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */
1058 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)
1059 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */
1060 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)
1061 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
1062 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
1063 #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
1064 #define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)
1065 #define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)
1066 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
1067 #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
1068 #define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
1069 #define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)
1070 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
1071 #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
1073 #define MBUS_UBOX_CTL _MMIO(0x4503C)
1074 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
1075 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
1077 #define MBUS_CTL _MMIO(0x4438C)
1078 #define MBUS_JOIN REG_BIT(31)
1079 #define MBUS_HASHING_MODE_MASK REG_BIT(30)
1080 #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
1081 #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
1082 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
1083 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
1084 #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
1086 /* Make render/texture TLB fetches lower priorty than associated data
1087 * fetches. This is not turned on by default
1089 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1091 /* Isoch request wait on GTT enable (Display A/B/C streams).
1092 * Make isoch requests stall on the TLB update. May cause
1093 * display underruns (test mode only)
1095 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1097 /* Block grant count for isoch requests when block count is
1098 * set to a finite value.
1100 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1101 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1102 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1103 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1104 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1106 /* Enable render writes to complete in C2/C3/C4 power states.
1107 * If this isn't enabled, render writes are prevented in low
1108 * power states. That seems bad to me.
1110 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1112 /* This acknowledges an async flip immediately instead
1113 * of waiting for 2TLB fetches.
1115 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1117 /* Enables non-sequential data reads through arbiter
1119 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
1121 /* Disable FSB snooping of cacheable write cycles from binner/render
1124 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1126 /* Arbiter time slice for non-isoch streams */
1127 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
1128 #define MI_ARB_TIME_SLICE_1 (0 << 5)
1129 #define MI_ARB_TIME_SLICE_2 (1 << 5)
1130 #define MI_ARB_TIME_SLICE_4 (2 << 5)
1131 #define MI_ARB_TIME_SLICE_6 (3 << 5)
1132 #define MI_ARB_TIME_SLICE_8 (4 << 5)
1133 #define MI_ARB_TIME_SLICE_10 (5 << 5)
1134 #define MI_ARB_TIME_SLICE_14 (6 << 5)
1135 #define MI_ARB_TIME_SLICE_16 (7 << 5)
1137 /* Low priority grace period page size */
1138 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1139 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1141 /* Disable display A/B trickle feed */
1142 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1144 /* Set display plane priority */
1145 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1146 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1148 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
1149 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1150 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1152 /* On modern GEN architectures interrupt control consists of two sets
1153 * of registers. The first set pertains to the ring generating the
1154 * interrupt. The second control is for the functional block generating the
1155 * interrupt. These are PM, GT, DE, etc.
1157 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1158 * GT interrupt bits, so we don't need to duplicate the defines.
1160 * These defines should cover us well from SNB->HSW with minor exceptions
1161 * it can also work on ILK.
1163 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1164 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1165 #define GT_BLT_USER_INTERRUPT (1 << 22)
1166 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1167 #define GT_BSD_USER_INTERRUPT (1 << 12)
1168 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1169 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
1170 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
1171 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1172 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1173 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
1174 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1175 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1176 #define GT_RENDER_USER_INTERRUPT (1 << 0)
1178 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1179 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1181 #define GT_PARITY_ERROR(dev_priv) \
1182 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1183 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1185 /* These are all the "old" interrupts */
1186 #define ILK_BSD_USER_INTERRUPT (1 << 5)
1188 #define I915_PM_INTERRUPT (1 << 31)
1189 #define I915_ISP_INTERRUPT (1 << 22)
1190 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
1191 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
1192 #define I915_MIPIC_INTERRUPT (1 << 19)
1193 #define I915_MIPIA_INTERRUPT (1 << 18)
1194 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
1195 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
1196 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
1197 #define I915_MASTER_ERROR_INTERRUPT (1 << 15)
1198 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
1199 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
1200 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
1201 #define I915_HWB_OOM_INTERRUPT (1 << 13)
1202 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
1203 #define I915_SYNC_STATUS_INTERRUPT (1 << 12)
1204 #define I915_MISC_INTERRUPT (1 << 11)
1205 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
1206 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
1207 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
1208 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
1209 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
1210 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
1211 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
1212 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
1213 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
1214 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
1215 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
1216 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
1217 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
1218 #define I915_DEBUG_INTERRUPT (1 << 2)
1219 #define I915_WINVALID_INTERRUPT (1 << 1)
1220 #define I915_USER_INTERRUPT (1 << 1)
1221 #define I915_ASLE_INTERRUPT (1 << 0)
1222 #define I915_BSD_USER_INTERRUPT (1 << 25)
1224 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
1225 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000
1227 /* DisplayPort Audio w/ LPE */
1228 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
1229 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
1231 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
1232 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
1233 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
1234 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
1235 _VLV_AUD_PORT_EN_B_DBG, \
1236 _VLV_AUD_PORT_EN_C_DBG, \
1237 _VLV_AUD_PORT_EN_D_DBG)
1238 #define VLV_AMP_MUTE (1 << 1)
1240 #define GEN6_BSD_RNCID _MMIO(0x12198)
1242 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
1243 #define GEN7_FF_SCHED_MASK 0x0077070
1244 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
1245 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
1246 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
1247 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
1248 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
1249 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
1250 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
1251 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
1252 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
1253 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
1254 #define GEN7_FF_VS_SCHED_HW (0x0 << 12)
1255 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
1256 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
1257 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
1258 #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
1261 * Framebuffer compression (915+ only)
1264 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
1265 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
1266 #define FBC_CONTROL _MMIO(0x3208)
1267 #define FBC_CTL_EN REG_BIT(31)
1268 #define FBC_CTL_PERIODIC REG_BIT(30)
1269 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
1270 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
1271 #define FBC_CTL_STOP_ON_MOD REG_BIT(15)
1272 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
1273 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
1274 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
1275 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
1276 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
1277 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
1278 #define FBC_COMMAND _MMIO(0x320c)
1279 #define FBC_CMD_COMPRESS REG_BIT(0)
1280 #define FBC_STATUS _MMIO(0x3210)
1281 #define FBC_STAT_COMPRESSING REG_BIT(31)
1282 #define FBC_STAT_COMPRESSED REG_BIT(30)
1283 #define FBC_STAT_MODIFIED REG_BIT(29)
1284 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
1285 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
1286 #define FBC_CTL_FENCE_DBL REG_BIT(4)
1287 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
1288 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
1289 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
1290 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
1291 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
1292 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
1293 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
1294 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
1295 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
1296 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
1297 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
1298 #define FBC_MOD_NUM_VALID REG_BIT(0)
1299 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
1300 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
1301 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
1302 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
1303 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
1304 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
1306 #define FBC_LL_SIZE (1536)
1308 /* Framebuffer compression for GM45+ */
1309 #define DPFC_CB_BASE _MMIO(0x3200)
1310 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
1311 #define DPFC_CONTROL _MMIO(0x3208)
1312 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
1313 #define DPFC_CTL_EN REG_BIT(31)
1314 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
1315 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
1316 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
1317 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
1318 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
1319 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
1320 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
1321 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
1322 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
1323 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
1324 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
1325 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
1326 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
1327 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
1328 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
1329 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
1330 #define DPFC_RECOMP_CTL _MMIO(0x320c)
1331 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
1332 #define DPFC_RECOMP_STALL_EN REG_BIT(27)
1333 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
1334 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
1335 #define DPFC_STATUS _MMIO(0x3210)
1336 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
1337 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
1338 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
1339 #define DPFC_STATUS2 _MMIO(0x3214)
1340 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
1341 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
1342 #define DPFC_FENCE_YOFF _MMIO(0x3218)
1343 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
1344 #define DPFC_CHICKEN _MMIO(0x3224)
1345 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
1346 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
1347 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
1348 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
1349 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
1350 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
1352 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
1353 #define FBC_STRIDE_OVERRIDE REG_BIT(15)
1354 #define FBC_STRIDE_MASK REG_GENMASK(14, 0)
1355 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
1357 #define ILK_FBC_RT_BASE _MMIO(0x2128)
1358 #define ILK_FBC_RT_VALID REG_BIT(0)
1359 #define SNB_FBC_FRONT_BUFFER REG_BIT(1)
1361 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
1362 #define ILK_FBCQ_DIS (1 << 22)
1363 #define ILK_PABSTRETCH_DIS REG_BIT(21)
1364 #define ILK_SABSTRETCH_DIS REG_BIT(20)
1365 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
1366 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
1367 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
1368 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
1369 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
1370 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
1371 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
1372 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
1373 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
1374 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
1378 * Framebuffer compression for Sandybridge
1380 * The following two registers are of type GTTMMADR
1382 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
1383 #define SNB_DPFC_FENCE_EN REG_BIT(29)
1384 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
1385 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
1386 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
1388 /* Framebuffer compression for Ivybridge */
1389 #define IVB_FBC_RT_BASE _MMIO(0x7020)
1390 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
1392 #define IPS_CTL _MMIO(0x43408)
1393 #define IPS_ENABLE (1 << 31)
1395 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
1396 #define FBC_REND_NUKE REG_BIT(2)
1397 #define FBC_REND_CACHE_CLEAN REG_BIT(1)
1400 * Clock control & power management
1402 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
1403 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
1404 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
1405 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
1407 #define VGA0 _MMIO(0x6000)
1408 #define VGA1 _MMIO(0x6004)
1409 #define VGA_PD _MMIO(0x6010)
1410 #define VGA0_PD_P2_DIV_4 (1 << 7)
1411 #define VGA0_PD_P1_DIV_2 (1 << 5)
1412 #define VGA0_PD_P1_SHIFT 0
1413 #define VGA0_PD_P1_MASK (0x1f << 0)
1414 #define VGA1_PD_P2_DIV_4 (1 << 15)
1415 #define VGA1_PD_P1_DIV_2 (1 << 13)
1416 #define VGA1_PD_P1_SHIFT 8
1417 #define VGA1_PD_P1_MASK (0x1f << 8)
1418 #define DPLL_VCO_ENABLE (1 << 31)
1419 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
1420 #define DPLL_DVO_2X_MODE (1 << 30)
1421 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
1422 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
1423 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
1424 #define DPLL_VGA_MODE_DIS (1 << 28)
1425 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1426 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1427 #define DPLL_MODE_MASK (3 << 26)
1428 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1429 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1430 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1431 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1432 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1433 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1434 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
1435 #define DPLL_LOCK_VLV (1 << 15)
1436 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
1437 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
1438 #define DPLL_SSC_REF_CLK_CHV (1 << 13)
1439 #define DPLL_PORTC_READY_MASK (0xf << 4)
1440 #define DPLL_PORTB_READY_MASK (0xf)
1442 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1444 /* Additional CHV pll/phy registers */
1445 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
1446 #define DPLL_PORTD_READY_MASK (0xf)
1447 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
1448 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
1449 #define PHY_LDO_DELAY_0NS 0x0
1450 #define PHY_LDO_DELAY_200NS 0x1
1451 #define PHY_LDO_DELAY_600NS 0x2
1452 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
1453 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
1454 #define PHY_CH_SU_PSR 0x1
1455 #define PHY_CH_DEEP_PSR 0x7
1456 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
1457 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
1458 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
1459 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
1460 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
1461 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
1464 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1465 * this field (only one bit may be set).
1467 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1468 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1469 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1470 /* i830, required in DVO non-gang */
1471 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
1472 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1473 #define PLL_REF_INPUT_DREFCLK (0 << 13)
1474 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1475 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1476 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1477 #define PLL_REF_INPUT_MASK (3 << 13)
1478 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
1480 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1481 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1482 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
1483 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1484 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1487 * Parallel to Serial Load Pulse phase selection.
1488 * Selects the phase for the 10X DPLL clock for the PCIe
1489 * digital display port. The range is 4 to 13; 10 or more
1490 * is just a flip delay. The default is 6
1492 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1493 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1495 * SDVO multiplier for 945G/GM. Not used on 965.
1497 #define SDVO_MULTIPLIER_MASK 0x000000ff
1498 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
1499 #define SDVO_MULTIPLIER_SHIFT_VGA 0
1501 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
1502 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
1503 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
1504 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
1507 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1509 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1511 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1512 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
1513 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1514 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1515 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1517 * SDVO/UDI pixel multiplier.
1519 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1520 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1521 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1522 * dummy bytes in the datastream at an increased clock rate, with both sides of
1523 * the link knowing how many bytes are fill.
1525 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1526 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1527 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1528 * through an SDVO command.
1530 * This register field has values of multiplication factor minus 1, with
1531 * a maximum multiplier of 5 for SDVO.
1533 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1534 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1536 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1537 * This best be set to the default value (3) or the CRT won't work. No,
1538 * I don't entirely understand what this does...
1540 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1541 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1543 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
1545 #define _FPA0 0x6040
1546 #define _FPA1 0x6044
1547 #define _FPB0 0x6048
1548 #define _FPB1 0x604c
1549 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
1550 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
1551 #define FP_N_DIV_MASK 0x003f0000
1552 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1553 #define FP_N_DIV_SHIFT 16
1554 #define FP_M1_DIV_MASK 0x00003f00
1555 #define FP_M1_DIV_SHIFT 8
1556 #define FP_M2_DIV_MASK 0x0000003f
1557 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1558 #define FP_M2_DIV_SHIFT 0
1559 #define DPLL_TEST _MMIO(0x606c)
1560 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1561 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1562 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1563 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1564 #define DPLLB_TEST_N_BYPASS (1 << 19)
1565 #define DPLLB_TEST_M_BYPASS (1 << 18)
1566 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1567 #define DPLLA_TEST_N_BYPASS (1 << 3)
1568 #define DPLLA_TEST_M_BYPASS (1 << 2)
1569 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1570 #define D_STATE _MMIO(0x6104)
1571 #define DSTATE_GFX_RESET_I830 (1 << 6)
1572 #define DSTATE_PLL_D3_OFF (1 << 3)
1573 #define DSTATE_GFX_CLOCK_GATING (1 << 1)
1574 #define DSTATE_DOT_CLOCK_GATING (1 << 0)
1575 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
1576 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1577 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1578 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1579 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1580 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1581 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1582 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1583 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
1584 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1585 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1586 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1587 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1588 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1589 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1590 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1591 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1592 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1593 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1594 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1595 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1596 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1597 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1598 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1599 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1600 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1601 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1602 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1603 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1604 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1606 * This bit must be set on the 830 to prevent hangs when turning off the
1609 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1610 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1611 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1612 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1613 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1615 #define RENCLK_GATE_D1 _MMIO(0x6204)
1616 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1617 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1618 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1619 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1620 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1621 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1622 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1623 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1624 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1625 /* This bit must be unset on 855,865 */
1626 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1627 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1628 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1629 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1630 /* This bit must be set on 855,865. */
1631 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1632 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1633 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1634 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1635 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1636 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1637 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1638 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1639 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1640 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1641 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1642 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1643 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1644 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1645 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1646 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1647 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1648 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1650 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1651 /* This bit must always be set on 965G/965GM */
1652 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1653 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1654 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1655 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1656 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1657 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1658 /* This bit must always be set on 965G */
1659 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1660 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1661 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1662 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1663 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1664 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1665 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1666 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1667 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1668 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1669 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1670 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1671 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1672 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1673 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1674 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1675 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1676 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1677 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1679 #define RENCLK_GATE_D2 _MMIO(0x6208)
1680 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1681 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1682 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1684 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
1685 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
1687 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
1688 #define DEUC _MMIO(0x6214) /* CRL only */
1690 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
1691 #define FW_CSPWRDWNEN (1 << 15)
1693 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
1695 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
1696 #define CDCLK_FREQ_SHIFT 4
1697 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1698 #define CZCLK_FREQ_MASK 0xf
1700 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
1701 #define PFI_CREDIT_63 (9 << 28) /* chv only */
1702 #define PFI_CREDIT_31 (8 << 28) /* chv only */
1703 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
1704 #define PFI_CREDIT_RESEND (1 << 27)
1705 #define VGA_FAST_MODE_DISABLE (1 << 14)
1707 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
1712 #define _PALETTE_A 0xa000
1713 #define _PALETTE_B 0xa800
1714 #define _CHV_PALETTE_C 0xc000
1715 /* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
1716 #define PALETTE_RED_MASK REG_GENMASK(23, 16)
1717 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
1718 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
1719 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
1720 _PICK((pipe), _PALETTE_A, \
1721 _PALETTE_B, _CHV_PALETTE_C) + \
1724 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
1726 #define BXT_RP_STATE_CAP _MMIO(0x138170)
1727 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
1728 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
1729 #define PVC_RP_STATE_CAP _MMIO(0x281014)
1731 #define MTL_RP_STATE_CAP _MMIO(0x138000)
1732 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
1733 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
1734 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
1736 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
1737 #define MTL_MPE_FREQUENCY _MMIO(0x13802c)
1738 #define MTL_RPE_MASK REG_GENMASK(8, 0)
1740 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
1741 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3
1742 #define PROCHOT_MASK REG_BIT(0)
1743 #define THERMAL_LIMIT_MASK REG_BIT(1)
1744 #define RATL_MASK REG_BIT(5)
1745 #define VR_THERMALERT_MASK REG_BIT(6)
1746 #define VR_TDC_MASK REG_BIT(7)
1747 #define POWER_LIMIT_4_MASK REG_BIT(8)
1748 #define POWER_LIMIT_1_MASK REG_BIT(10)
1749 #define POWER_LIMIT_2_MASK REG_BIT(11)
1750 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
1751 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
1753 #define CHV_CLK_CTL1 _MMIO(0x101100)
1754 #define VLV_CLK_CTL2 _MMIO(0x101104)
1755 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1761 #define OVADD _MMIO(0x30000)
1762 #define DOVSTA _MMIO(0x30008)
1763 #define OC_BUF (0x3 << 20)
1764 #define OGAMC5 _MMIO(0x30010)
1765 #define OGAMC4 _MMIO(0x30014)
1766 #define OGAMC3 _MMIO(0x30018)
1767 #define OGAMC2 _MMIO(0x3001c)
1768 #define OGAMC1 _MMIO(0x30020)
1769 #define OGAMC0 _MMIO(0x30024)
1772 * GEN9 clock gating regs
1774 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
1775 #define DARBF_GATING_DIS (1 << 27)
1776 #define PWM2_GATING_DIS (1 << 14)
1777 #define PWM1_GATING_DIS (1 << 13)
1779 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
1780 #define TGL_VRH_GATING_DIS REG_BIT(31)
1781 #define DPT_GATING_DIS REG_BIT(22)
1783 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
1784 #define BXT_GMBUS_GATING_DIS (1 << 14)
1786 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
1787 #define DPCE_GATING_DIS REG_BIT(17)
1789 #define _CLKGATE_DIS_PSL_A 0x46520
1790 #define _CLKGATE_DIS_PSL_B 0x46524
1791 #define _CLKGATE_DIS_PSL_C 0x46528
1792 #define DUPS1_GATING_DIS (1 << 15)
1793 #define DUPS2_GATING_DIS (1 << 19)
1794 #define DUPS3_GATING_DIS (1 << 23)
1795 #define CURSOR_GATING_DIS REG_BIT(28)
1796 #define DPF_GATING_DIS (1 << 10)
1797 #define DPF_RAM_GATING_DIS (1 << 9)
1798 #define DPFR_GATING_DIS (1 << 8)
1800 #define CLKGATE_DIS_PSL(pipe) \
1801 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
1803 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C
1804 #define _CLKGATE_DIS_PSL_EXT_B 0x46550
1805 #define PIPEDMC_GATING_DIS REG_BIT(12)
1807 #define CLKGATE_DIS_PSL_EXT(pipe) \
1808 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
1811 * Display engine regs
1814 /* Pipe A CRC regs */
1815 #define _PIPE_CRC_CTL_A 0x60050
1816 #define PIPE_CRC_ENABLE REG_BIT(31)
1817 /* skl+ source selection */
1818 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28)
1819 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
1820 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
1821 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
1822 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
1823 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
1824 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
1825 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
1826 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
1827 /* ivb+ source selection */
1828 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29)
1829 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
1830 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
1831 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
1832 /* ilk+ source selection */
1833 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28)
1834 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
1835 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
1836 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
1837 /* embedded DP port on the north display block */
1838 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
1839 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
1840 /* vlv source selection */
1841 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27)
1842 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
1843 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
1844 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
1845 /* with DP port the pipe source is invalid */
1846 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
1847 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
1848 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
1849 /* gen3+ source selection */
1850 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28)
1851 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
1852 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
1853 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
1854 /* with DP/TV port the pipe source is invalid */
1855 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
1856 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
1857 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
1858 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
1859 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
1860 /* gen2 doesn't have source selection bits */
1861 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
1863 #define _PIPE_CRC_RES_1_A_IVB 0x60064
1864 #define _PIPE_CRC_RES_2_A_IVB 0x60068
1865 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
1866 #define _PIPE_CRC_RES_4_A_IVB 0x60070
1867 #define _PIPE_CRC_RES_5_A_IVB 0x60074
1869 #define _PIPE_CRC_RES_RED_A 0x60060
1870 #define _PIPE_CRC_RES_GREEN_A 0x60064
1871 #define _PIPE_CRC_RES_BLUE_A 0x60068
1872 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
1873 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
1875 /* Pipe B CRC regs */
1876 #define _PIPE_CRC_RES_1_B_IVB 0x61064
1877 #define _PIPE_CRC_RES_2_B_IVB 0x61068
1878 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
1879 #define _PIPE_CRC_RES_4_B_IVB 0x61070
1880 #define _PIPE_CRC_RES_5_B_IVB 0x61074
1882 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
1883 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
1884 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
1885 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
1886 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
1887 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
1889 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
1890 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
1891 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
1892 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
1893 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
1895 /* Pipe A timing regs */
1896 #define _HTOTAL_A 0x60000
1897 #define _HBLANK_A 0x60004
1898 #define _HSYNC_A 0x60008
1899 #define _VTOTAL_A 0x6000c
1900 #define _VBLANK_A 0x60010
1901 #define _VSYNC_A 0x60014
1902 #define _EXITLINE_A 0x60018
1903 #define _PIPEASRC 0x6001c
1904 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
1905 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
1906 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
1907 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
1908 #define _BCLRPAT_A 0x60020
1909 #define _VSYNCSHIFT_A 0x60028
1910 #define _PIPE_MULT_A 0x6002c
1912 /* Pipe B timing regs */
1913 #define _HTOTAL_B 0x61000
1914 #define _HBLANK_B 0x61004
1915 #define _HSYNC_B 0x61008
1916 #define _VTOTAL_B 0x6100c
1917 #define _VBLANK_B 0x61010
1918 #define _VSYNC_B 0x61014
1919 #define _PIPEBSRC 0x6101c
1920 #define _BCLRPAT_B 0x61020
1921 #define _VSYNCSHIFT_B 0x61028
1922 #define _PIPE_MULT_B 0x6102c
1924 /* DSI 0 timing regs */
1925 #define _HTOTAL_DSI0 0x6b000
1926 #define _HSYNC_DSI0 0x6b008
1927 #define _VTOTAL_DSI0 0x6b00c
1928 #define _VSYNC_DSI0 0x6b014
1929 #define _VSYNCSHIFT_DSI0 0x6b028
1931 /* DSI 1 timing regs */
1932 #define _HTOTAL_DSI1 0x6b800
1933 #define _HSYNC_DSI1 0x6b808
1934 #define _VTOTAL_DSI1 0x6b80c
1935 #define _VSYNC_DSI1 0x6b814
1936 #define _VSYNCSHIFT_DSI1 0x6b828
1938 #define TRANSCODER_A_OFFSET 0x60000
1939 #define TRANSCODER_B_OFFSET 0x61000
1940 #define TRANSCODER_C_OFFSET 0x62000
1941 #define CHV_TRANSCODER_C_OFFSET 0x63000
1942 #define TRANSCODER_D_OFFSET 0x63000
1943 #define TRANSCODER_EDP_OFFSET 0x6f000
1944 #define TRANSCODER_DSI0_OFFSET 0x6b000
1945 #define TRANSCODER_DSI1_OFFSET 0x6b800
1947 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
1948 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
1949 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
1950 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
1951 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
1952 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
1953 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
1954 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
1955 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
1956 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
1958 #define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
1959 #define EXITLINE_ENABLE REG_BIT(31)
1960 #define EXITLINE_MASK REG_GENMASK(12, 0)
1961 #define EXITLINE_SHIFT 0
1964 #define _TRANS_VRR_CTL_A 0x60420
1965 #define _TRANS_VRR_CTL_B 0x61420
1966 #define _TRANS_VRR_CTL_C 0x62420
1967 #define _TRANS_VRR_CTL_D 0x63420
1968 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
1969 #define VRR_CTL_VRR_ENABLE REG_BIT(31)
1970 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
1971 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
1972 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
1973 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
1974 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
1975 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
1976 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
1978 #define _TRANS_VRR_VMAX_A 0x60424
1979 #define _TRANS_VRR_VMAX_B 0x61424
1980 #define _TRANS_VRR_VMAX_C 0x62424
1981 #define _TRANS_VRR_VMAX_D 0x63424
1982 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
1983 #define VRR_VMAX_MASK REG_GENMASK(19, 0)
1985 #define _TRANS_VRR_VMIN_A 0x60434
1986 #define _TRANS_VRR_VMIN_B 0x61434
1987 #define _TRANS_VRR_VMIN_C 0x62434
1988 #define _TRANS_VRR_VMIN_D 0x63434
1989 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
1990 #define VRR_VMIN_MASK REG_GENMASK(15, 0)
1992 #define _TRANS_VRR_VMAXSHIFT_A 0x60428
1993 #define _TRANS_VRR_VMAXSHIFT_B 0x61428
1994 #define _TRANS_VRR_VMAXSHIFT_C 0x62428
1995 #define _TRANS_VRR_VMAXSHIFT_D 0x63428
1996 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \
1997 _TRANS_VRR_VMAXSHIFT_A)
1998 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
1999 #define VRR_VMAXSHIFT_DEC REG_BIT(16)
2000 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
2002 #define _TRANS_VRR_STATUS_A 0x6042C
2003 #define _TRANS_VRR_STATUS_B 0x6142C
2004 #define _TRANS_VRR_STATUS_C 0x6242C
2005 #define _TRANS_VRR_STATUS_D 0x6342C
2006 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
2007 #define VRR_STATUS_VMAX_REACHED REG_BIT(31)
2008 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
2009 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
2010 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
2011 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
2012 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
2013 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
2014 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
2015 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
2016 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
2017 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
2018 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
2019 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
2020 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
2022 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480
2023 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480
2024 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480
2025 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480
2026 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \
2027 _TRANS_VRR_VTOTAL_PREV_A)
2028 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
2029 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
2030 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
2031 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
2033 #define _TRANS_VRR_FLIPLINE_A 0x60438
2034 #define _TRANS_VRR_FLIPLINE_B 0x61438
2035 #define _TRANS_VRR_FLIPLINE_C 0x62438
2036 #define _TRANS_VRR_FLIPLINE_D 0x63438
2037 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \
2038 _TRANS_VRR_FLIPLINE_A)
2039 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
2041 #define _TRANS_VRR_STATUS2_A 0x6043C
2042 #define _TRANS_VRR_STATUS2_B 0x6143C
2043 #define _TRANS_VRR_STATUS2_C 0x6243C
2044 #define _TRANS_VRR_STATUS2_D 0x6343C
2045 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
2046 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
2048 #define _TRANS_PUSH_A 0x60A70
2049 #define _TRANS_PUSH_B 0x61A70
2050 #define _TRANS_PUSH_C 0x62A70
2051 #define _TRANS_PUSH_D 0x63A70
2052 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A)
2053 #define TRANS_PUSH_EN REG_BIT(31)
2054 #define TRANS_PUSH_SEND REG_BIT(30)
2057 * HSW+ eDP PSR registers
2059 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
2062 #define _SRD_CTL_A 0x60800
2063 #define _SRD_CTL_EDP 0x6f800
2064 #define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A)
2065 #define EDP_PSR_ENABLE (1 << 31)
2066 #define BDW_PSR_SINGLE_FRAME (1 << 30)
2067 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
2068 #define EDP_PSR_LINK_STANDBY (1 << 27)
2069 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
2070 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
2071 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
2072 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
2073 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
2074 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
2075 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
2076 #define EDP_PSR_TP1_TP2_SEL (0 << 11)
2077 #define EDP_PSR_TP1_TP3_SEL (1 << 11)
2078 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */
2079 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
2080 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
2081 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
2082 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
2083 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */
2084 #define EDP_PSR_TP1_TIME_500us (0 << 4)
2085 #define EDP_PSR_TP1_TIME_100us (1 << 4)
2086 #define EDP_PSR_TP1_TIME_2500us (2 << 4)
2087 #define EDP_PSR_TP1_TIME_0us (3 << 4)
2088 #define EDP_PSR_IDLE_FRAME_SHIFT 0
2091 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
2092 * to transcoder and bits defined for each one as if using no shift (i.e. as if
2093 * it was for TRANSCODER_EDP)
2095 #define EDP_PSR_IMR _MMIO(0x64834)
2096 #define EDP_PSR_IIR _MMIO(0x64838)
2097 #define _PSR_IMR_A 0x60814
2098 #define _PSR_IIR_A 0x60818
2099 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A)
2100 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
2101 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
2102 0 : ((trans) - TRANSCODER_A + 1) * 8)
2103 #define TGL_PSR_MASK REG_GENMASK(2, 0)
2104 #define TGL_PSR_ERROR REG_BIT(2)
2105 #define TGL_PSR_POST_EXIT REG_BIT(1)
2106 #define TGL_PSR_PRE_ENTRY REG_BIT(0)
2107 #define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \
2108 _EDP_PSR_TRANS_SHIFT(trans))
2109 #define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \
2110 _EDP_PSR_TRANS_SHIFT(trans))
2111 #define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \
2112 _EDP_PSR_TRANS_SHIFT(trans))
2113 #define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \
2114 _EDP_PSR_TRANS_SHIFT(trans))
2116 #define _SRD_AUX_DATA_A 0x60814
2117 #define _SRD_AUX_DATA_EDP 0x6f814
2118 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */
2120 #define _SRD_STATUS_A 0x60840
2121 #define _SRD_STATUS_EDP 0x6f840
2122 #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A)
2123 #define EDP_PSR_STATUS_STATE_MASK (7 << 29)
2124 #define EDP_PSR_STATUS_STATE_SHIFT 29
2125 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
2126 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
2127 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
2128 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
2129 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
2130 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
2131 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
2132 #define EDP_PSR_STATUS_LINK_MASK (3 << 26)
2133 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
2134 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
2135 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
2136 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2137 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2138 #define EDP_PSR_STATUS_COUNT_SHIFT 16
2139 #define EDP_PSR_STATUS_COUNT_MASK 0xf
2140 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
2141 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
2142 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
2143 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
2144 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
2145 #define EDP_PSR_STATUS_IDLE_MASK 0xf
2147 #define _SRD_PERF_CNT_A 0x60844
2148 #define _SRD_PERF_CNT_EDP 0x6f844
2149 #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A)
2150 #define EDP_PSR_PERF_CNT_MASK 0xffffff
2152 /* PSR_MASK on SKL+ */
2153 #define _SRD_DEBUG_A 0x60860
2154 #define _SRD_DEBUG_EDP 0x6f860
2155 #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A)
2156 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
2157 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
2158 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
2159 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
2160 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
2161 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
2163 #define _PSR2_CTL_A 0x60900
2164 #define _PSR2_CTL_EDP 0x6f900
2165 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
2166 #define EDP_PSR2_ENABLE (1 << 31)
2167 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
2168 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
2169 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
2170 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
2171 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */
2172 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
2173 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
2174 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8
2175 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
2176 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13)
2177 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
2178 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13
2179 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
2180 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13)
2181 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8
2182 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
2183 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11)
2184 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5
2185 #define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10
2186 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
2187 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10)
2188 #define EDP_PSR2_TP2_TIME_500us (0 << 8)
2189 #define EDP_PSR2_TP2_TIME_100us (1 << 8)
2190 #define EDP_PSR2_TP2_TIME_2500us (2 << 8)
2191 #define EDP_PSR2_TP2_TIME_50us (3 << 8)
2192 #define EDP_PSR2_TP2_TIME_MASK (3 << 8)
2193 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
2194 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
2195 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
2196 #define EDP_PSR2_IDLE_FRAME_MASK 0xf
2197 #define EDP_PSR2_IDLE_FRAME_SHIFT 0
2199 #define _PSR_EVENT_TRANS_A 0x60848
2200 #define _PSR_EVENT_TRANS_B 0x61848
2201 #define _PSR_EVENT_TRANS_C 0x62848
2202 #define _PSR_EVENT_TRANS_D 0x63848
2203 #define _PSR_EVENT_TRANS_EDP 0x6f848
2204 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
2205 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
2206 #define PSR_EVENT_PSR2_DISABLED (1 << 16)
2207 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
2208 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
2209 #define PSR_EVENT_GRAPHICS_RESET (1 << 12)
2210 #define PSR_EVENT_PCH_INTERRUPT (1 << 11)
2211 #define PSR_EVENT_MEMORY_UP (1 << 10)
2212 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
2213 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
2214 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
2215 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
2216 #define PSR_EVENT_HDCP_ENABLE (1 << 4)
2217 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
2218 #define PSR_EVENT_VBI_ENABLE (1 << 2)
2219 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
2220 #define PSR_EVENT_PSR_DISABLE (1 << 0)
2222 #define _PSR2_STATUS_A 0x60940
2223 #define _PSR2_STATUS_EDP 0x6f940
2224 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
2225 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
2226 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
2228 #define _PSR2_SU_STATUS_A 0x60914
2229 #define _PSR2_SU_STATUS_EDP 0x6f914
2230 #define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4)
2231 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
2232 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
2233 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
2234 #define PSR2_SU_STATUS_FRAMES 8
2236 #define _PSR2_MAN_TRK_CTL_A 0x60910
2237 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910
2238 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
2239 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
2240 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
2241 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
2242 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
2243 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
2244 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
2245 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
2246 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
2247 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
2248 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
2249 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
2250 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
2251 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
2252 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
2253 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
2255 /* Icelake DSC Rate Control Range Parameter Registers */
2256 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
2257 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
2258 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
2259 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
2260 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
2261 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
2262 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
2263 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
2264 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
2265 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
2266 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
2267 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
2268 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2269 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
2270 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
2271 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2272 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
2273 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
2274 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2275 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
2276 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
2277 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2278 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
2279 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
2280 #define RC_BPG_OFFSET_SHIFT 10
2281 #define RC_MAX_QP_SHIFT 5
2282 #define RC_MIN_QP_SHIFT 0
2284 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
2285 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
2286 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
2287 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
2288 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
2289 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
2290 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
2291 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
2292 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
2293 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
2294 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
2295 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
2296 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2297 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
2298 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
2299 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2300 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
2301 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
2302 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2303 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
2304 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
2305 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2306 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
2307 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
2309 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
2310 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
2311 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
2312 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
2313 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
2314 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
2315 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
2316 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
2317 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
2318 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
2319 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
2320 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
2321 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2322 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
2323 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
2324 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2325 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
2326 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
2327 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2328 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
2329 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
2330 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2331 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
2332 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
2334 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
2335 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
2336 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
2337 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
2338 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
2339 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
2340 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
2341 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
2342 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
2343 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
2344 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
2345 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
2346 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2347 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
2348 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
2349 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2350 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
2351 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
2352 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2353 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
2354 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
2355 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2356 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
2357 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
2359 /* VGA port control */
2360 #define ADPA _MMIO(0x61100)
2361 #define PCH_ADPA _MMIO(0xe1100)
2362 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
2364 #define ADPA_DAC_ENABLE (1 << 31)
2365 #define ADPA_DAC_DISABLE 0
2366 #define ADPA_PIPE_SEL_SHIFT 30
2367 #define ADPA_PIPE_SEL_MASK (1 << 30)
2368 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
2369 #define ADPA_PIPE_SEL_SHIFT_CPT 29
2370 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
2371 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2372 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2373 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
2374 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
2375 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
2376 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
2377 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
2378 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
2379 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
2380 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
2381 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
2382 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
2383 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
2384 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
2385 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
2386 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
2387 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
2388 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
2389 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
2390 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
2391 #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
2392 #define ADPA_SETS_HVPOLARITY 0
2393 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
2394 #define ADPA_VSYNC_CNTL_ENABLE 0
2395 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
2396 #define ADPA_HSYNC_CNTL_ENABLE 0
2397 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
2398 #define ADPA_VSYNC_ACTIVE_LOW 0
2399 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
2400 #define ADPA_HSYNC_ACTIVE_LOW 0
2401 #define ADPA_DPMS_MASK (~(3 << 10))
2402 #define ADPA_DPMS_ON (0 << 10)
2403 #define ADPA_DPMS_SUSPEND (1 << 10)
2404 #define ADPA_DPMS_STANDBY (2 << 10)
2405 #define ADPA_DPMS_OFF (3 << 10)
2408 /* Hotplug control (945+ only) */
2409 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
2410 #define PORTB_HOTPLUG_INT_EN (1 << 29)
2411 #define PORTC_HOTPLUG_INT_EN (1 << 28)
2412 #define PORTD_HOTPLUG_INT_EN (1 << 27)
2413 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
2414 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
2415 #define TV_HOTPLUG_INT_EN (1 << 18)
2416 #define CRT_HOTPLUG_INT_EN (1 << 9)
2417 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2418 PORTC_HOTPLUG_INT_EN | \
2419 PORTD_HOTPLUG_INT_EN | \
2420 SDVOC_HOTPLUG_INT_EN | \
2421 SDVOB_HOTPLUG_INT_EN | \
2423 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
2424 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2425 /* must use period 64 on GM45 according to docs */
2426 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2427 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2428 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2429 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2430 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2431 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2432 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2433 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2434 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2435 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2436 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2437 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
2439 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
2441 * HDMI/DP bits are g4x+
2443 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2444 * Please check the detailed lore in the commit message for for experimental
2447 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
2448 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
2449 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
2450 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
2451 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
2452 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2453 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2454 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2455 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2456 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
2457 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
2458 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2459 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
2460 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
2461 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
2462 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
2463 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
2464 /* CRT/TV common between gen3+ */
2465 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
2466 #define TV_HOTPLUG_INT_STATUS (1 << 10)
2467 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2468 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2469 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2470 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
2471 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2472 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2473 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2474 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2476 /* SDVO is different across gen3/4 */
2477 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2478 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
2480 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2481 * since reality corrobates that they're the same as on gen3. But keep these
2482 * bits here (and the comment!) to help any other lost wanderers back onto the
2485 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2486 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2487 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2488 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
2489 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2490 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2491 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2492 PORTB_HOTPLUG_INT_STATUS | \
2493 PORTC_HOTPLUG_INT_STATUS | \
2494 PORTD_HOTPLUG_INT_STATUS)
2496 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2497 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2498 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2499 PORTB_HOTPLUG_INT_STATUS | \
2500 PORTC_HOTPLUG_INT_STATUS | \
2501 PORTD_HOTPLUG_INT_STATUS)
2503 /* SDVO and HDMI port control.
2504 * The same register may be used for SDVO or HDMI */
2505 #define _GEN3_SDVOB 0x61140
2506 #define _GEN3_SDVOC 0x61160
2507 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
2508 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
2509 #define GEN4_HDMIB GEN3_SDVOB
2510 #define GEN4_HDMIC GEN3_SDVOC
2511 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
2512 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
2513 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
2514 #define PCH_SDVOB _MMIO(0xe1140)
2515 #define PCH_HDMIB PCH_SDVOB
2516 #define PCH_HDMIC _MMIO(0xe1150)
2517 #define PCH_HDMID _MMIO(0xe1160)
2519 #define PORT_DFT_I9XX _MMIO(0x61150)
2520 #define DC_BALANCE_RESET (1 << 25)
2521 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
2522 #define DC_BALANCE_RESET_VLV (1 << 31)
2523 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
2524 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
2525 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
2526 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
2528 /* Gen 3 SDVO bits: */
2529 #define SDVO_ENABLE (1 << 31)
2530 #define SDVO_PIPE_SEL_SHIFT 30
2531 #define SDVO_PIPE_SEL_MASK (1 << 30)
2532 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2533 #define SDVO_STALL_SELECT (1 << 29)
2534 #define SDVO_INTERRUPT_ENABLE (1 << 26)
2536 * 915G/GM SDVO pixel multiplier.
2537 * Programmed value is multiplier - 1, up to 5x.
2538 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2540 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
2541 #define SDVO_PORT_MULTIPLY_SHIFT 23
2542 #define SDVO_PHASE_SELECT_MASK (15 << 19)
2543 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2544 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2545 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2546 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2547 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2548 #define SDVO_DETECTED (1 << 2)
2549 /* Bits to be preserved when writing */
2550 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2551 SDVO_INTERRUPT_ENABLE)
2552 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2554 /* Gen 4 SDVO/HDMI bits: */
2555 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
2556 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
2557 #define SDVO_ENCODING_SDVO (0 << 10)
2558 #define SDVO_ENCODING_HDMI (2 << 10)
2559 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2560 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
2561 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
2562 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
2563 /* VSYNC/HSYNC bits new with 965, default is to be set */
2564 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2565 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2567 /* Gen 5 (IBX) SDVO/HDMI bits: */
2568 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
2569 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2571 /* Gen 6 (CPT) SDVO/HDMI bits: */
2572 #define SDVO_PIPE_SEL_SHIFT_CPT 29
2573 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
2574 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2576 /* CHV SDVO/HDMI bits: */
2577 #define SDVO_PIPE_SEL_SHIFT_CHV 24
2578 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
2579 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
2582 /* DVO port control */
2583 #define _DVOA 0x61120
2584 #define DVOA _MMIO(_DVOA)
2585 #define _DVOB 0x61140
2586 #define DVOB _MMIO(_DVOB)
2587 #define _DVOC 0x61160
2588 #define DVOC _MMIO(_DVOC)
2589 #define DVO_ENABLE (1 << 31)
2590 #define DVO_PIPE_SEL_SHIFT 30
2591 #define DVO_PIPE_SEL_MASK (1 << 30)
2592 #define DVO_PIPE_SEL(pipe) ((pipe) << 30)
2593 #define DVO_PIPE_STALL_UNUSED (0 << 28)
2594 #define DVO_PIPE_STALL (1 << 28)
2595 #define DVO_PIPE_STALL_TV (2 << 28)
2596 #define DVO_PIPE_STALL_MASK (3 << 28)
2597 #define DVO_USE_VGA_SYNC (1 << 15)
2598 #define DVO_DATA_ORDER_I740 (0 << 14)
2599 #define DVO_DATA_ORDER_FP (1 << 14)
2600 #define DVO_VSYNC_DISABLE (1 << 11)
2601 #define DVO_HSYNC_DISABLE (1 << 10)
2602 #define DVO_VSYNC_TRISTATE (1 << 9)
2603 #define DVO_HSYNC_TRISTATE (1 << 8)
2604 #define DVO_BORDER_ENABLE (1 << 7)
2605 #define DVO_DATA_ORDER_GBRG (1 << 6)
2606 #define DVO_DATA_ORDER_RGGB (0 << 6)
2607 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2608 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2609 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2610 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2611 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2612 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2613 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2614 #define DVO_PRESERVE_MASK (0x7 << 24)
2615 #define DVOA_SRCDIM _MMIO(0x61124)
2616 #define DVOB_SRCDIM _MMIO(0x61144)
2617 #define DVOC_SRCDIM _MMIO(0x61164)
2618 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2619 #define DVO_SRCDIM_VERTICAL_SHIFT 0
2621 /* LVDS port control */
2622 #define LVDS _MMIO(0x61180)
2624 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2625 * the DPLL semantics change when the LVDS is assigned to that pipe.
2627 #define LVDS_PORT_EN (1 << 31)
2628 /* Selects pipe B for LVDS data. Must be set on pre-965. */
2629 #define LVDS_PIPE_SEL_SHIFT 30
2630 #define LVDS_PIPE_SEL_MASK (1 << 30)
2631 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
2632 #define LVDS_PIPE_SEL_SHIFT_CPT 29
2633 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
2634 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2635 /* LVDS dithering flag on 965/g4x platform */
2636 #define LVDS_ENABLE_DITHER (1 << 25)
2637 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
2638 #define LVDS_VSYNC_POLARITY (1 << 21)
2639 #define LVDS_HSYNC_POLARITY (1 << 20)
2641 /* Enable border for unscaled (or aspect-scaled) display */
2642 #define LVDS_BORDER_ENABLE (1 << 15)
2644 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2647 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2648 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2649 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2651 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2652 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2655 #define LVDS_A3_POWER_MASK (3 << 6)
2656 #define LVDS_A3_POWER_DOWN (0 << 6)
2657 #define LVDS_A3_POWER_UP (3 << 6)
2659 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2662 #define LVDS_CLKB_POWER_MASK (3 << 4)
2663 #define LVDS_CLKB_POWER_DOWN (0 << 4)
2664 #define LVDS_CLKB_POWER_UP (3 << 4)
2666 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2667 * setting for whether we are in dual-channel mode. The B3 pair will
2668 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2670 #define LVDS_B0B3_POWER_MASK (3 << 2)
2671 #define LVDS_B0B3_POWER_DOWN (0 << 2)
2672 #define LVDS_B0B3_POWER_UP (3 << 2)
2674 /* Video Data Island Packet control */
2675 #define VIDEO_DIP_DATA _MMIO(0x61178)
2676 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
2677 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2678 * of the infoframe structure specified by CEA-861. */
2679 #define VIDEO_DIP_DATA_SIZE 32
2680 #define VIDEO_DIP_GMP_DATA_SIZE 36
2681 #define VIDEO_DIP_VSC_DATA_SIZE 36
2682 #define VIDEO_DIP_PPS_DATA_SIZE 132
2683 #define VIDEO_DIP_CTL _MMIO(0x61170)
2685 #define VIDEO_DIP_ENABLE (1 << 31)
2686 #define VIDEO_DIP_PORT(port) ((port) << 29)
2687 #define VIDEO_DIP_PORT_MASK (3 << 29)
2688 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
2689 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
2690 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
2691 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
2692 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
2693 #define VIDEO_DIP_SELECT_AVI (0 << 19)
2694 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2695 #define VIDEO_DIP_SELECT_GAMUT (2 << 19)
2696 #define VIDEO_DIP_SELECT_SPD (3 << 19)
2697 #define VIDEO_DIP_SELECT_MASK (3 << 19)
2698 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
2699 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2700 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
2701 #define VIDEO_DIP_FREQ_MASK (3 << 16)
2702 /* HSW and later: */
2703 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
2704 #define PSR_VSC_BIT_7_SET (1 << 27)
2705 #define VSC_SELECT_MASK (0x3 << 25)
2706 #define VSC_SELECT_SHIFT 25
2707 #define VSC_DIP_HW_HEA_DATA (0 << 25)
2708 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
2709 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
2710 #define VSC_DIP_SW_HEA_DATA (3 << 25)
2711 #define VDIP_ENABLE_PPS (1 << 24)
2712 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2713 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2714 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
2715 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2716 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2717 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
2719 /* Panel power sequencing */
2720 #define PPS_BASE 0x61200
2721 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
2722 #define PCH_PPS_BASE 0xC7200
2724 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \
2725 PPS_BASE + (reg) + \
2728 #define _PP_STATUS 0x61200
2729 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
2730 #define PP_ON REG_BIT(31)
2732 * Indicates that all dependencies of the panel are on:
2736 * - LVDS/DVOB/DVOC on
2738 #define PP_READY REG_BIT(30)
2739 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
2740 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
2741 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
2742 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
2743 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
2744 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
2745 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
2746 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
2747 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
2748 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
2749 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
2750 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
2751 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
2752 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
2753 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
2755 #define _PP_CONTROL 0x61204
2756 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
2757 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
2758 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
2759 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
2760 #define EDP_FORCE_VDD REG_BIT(3)
2761 #define EDP_BLC_ENABLE REG_BIT(2)
2762 #define PANEL_POWER_RESET REG_BIT(1)
2763 #define PANEL_POWER_ON REG_BIT(0)
2765 #define _PP_ON_DELAYS 0x61208
2766 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
2767 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
2768 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
2769 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
2770 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
2771 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
2772 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
2773 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
2774 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
2776 #define _PP_OFF_DELAYS 0x6120C
2777 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
2778 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
2779 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
2781 #define _PP_DIVISOR 0x61210
2782 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
2783 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
2784 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
2787 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
2788 #define PFIT_ENABLE (1 << 31)
2789 #define PFIT_PIPE_MASK (3 << 29)
2790 #define PFIT_PIPE_SHIFT 29
2791 #define PFIT_PIPE(pipe) ((pipe) << 29)
2792 #define VERT_INTERP_DISABLE (0 << 10)
2793 #define VERT_INTERP_BILINEAR (1 << 10)
2794 #define VERT_INTERP_MASK (3 << 10)
2795 #define VERT_AUTO_SCALE (1 << 9)
2796 #define HORIZ_INTERP_DISABLE (0 << 6)
2797 #define HORIZ_INTERP_BILINEAR (1 << 6)
2798 #define HORIZ_INTERP_MASK (3 << 6)
2799 #define HORIZ_AUTO_SCALE (1 << 5)
2800 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
2801 #define PFIT_FILTER_FUZZY (0 << 24)
2802 #define PFIT_SCALING_AUTO (0 << 26)
2803 #define PFIT_SCALING_PROGRAMMED (1 << 26)
2804 #define PFIT_SCALING_PILLAR (2 << 26)
2805 #define PFIT_SCALING_LETTER (3 << 26)
2806 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
2808 #define PFIT_VERT_SCALE_SHIFT 20
2809 #define PFIT_VERT_SCALE_MASK 0xfff00000
2810 #define PFIT_HORIZ_SCALE_SHIFT 4
2811 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2813 #define PFIT_VERT_SCALE_SHIFT_965 16
2814 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2815 #define PFIT_HORIZ_SCALE_SHIFT_965 0
2816 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2818 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
2820 #define PCH_GTC_CTL _MMIO(0xe7000)
2821 #define PCH_GTC_ENABLE (1 << 31)
2823 /* TV port control */
2824 #define TV_CTL _MMIO(0x68000)
2825 /* Enables the TV encoder */
2826 # define TV_ENC_ENABLE (1 << 31)
2827 /* Sources the TV encoder input from pipe B instead of A. */
2828 # define TV_ENC_PIPE_SEL_SHIFT 30
2829 # define TV_ENC_PIPE_SEL_MASK (1 << 30)
2830 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
2831 /* Outputs composite video (DAC A only) */
2832 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
2833 /* Outputs SVideo video (DAC B/C) */
2834 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
2835 /* Outputs Component video (DAC A/B/C) */
2836 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
2837 /* Outputs Composite and SVideo (DAC A/B/C) */
2838 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2839 # define TV_TRILEVEL_SYNC (1 << 21)
2840 /* Enables slow sync generation (945GM only) */
2841 # define TV_SLOW_SYNC (1 << 20)
2842 /* Selects 4x oversampling for 480i and 576p */
2843 # define TV_OVERSAMPLE_4X (0 << 18)
2844 /* Selects 2x oversampling for 720p and 1080i */
2845 # define TV_OVERSAMPLE_2X (1 << 18)
2846 /* Selects no oversampling for 1080p */
2847 # define TV_OVERSAMPLE_NONE (2 << 18)
2848 /* Selects 8x oversampling */
2849 # define TV_OVERSAMPLE_8X (3 << 18)
2850 # define TV_OVERSAMPLE_MASK (3 << 18)
2851 /* Selects progressive mode rather than interlaced */
2852 # define TV_PROGRESSIVE (1 << 17)
2853 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2854 # define TV_PAL_BURST (1 << 16)
2855 /* Field for setting delay of Y compared to C */
2856 # define TV_YC_SKEW_MASK (7 << 12)
2857 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
2858 # define TV_ENC_SDP_FIX (1 << 11)
2860 * Enables a fix for the 915GM only.
2862 * Not sure what it does.
2864 # define TV_ENC_C0_FIX (1 << 10)
2865 /* Bits that must be preserved by software */
2866 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2867 # define TV_FUSE_STATE_MASK (3 << 4)
2868 /* Read-only state that reports all features enabled */
2869 # define TV_FUSE_STATE_ENABLED (0 << 4)
2870 /* Read-only state that reports that Macrovision is disabled in hardware*/
2871 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2872 /* Read-only state that reports that TV-out is disabled in hardware. */
2873 # define TV_FUSE_STATE_DISABLED (2 << 4)
2874 /* Normal operation */
2875 # define TV_TEST_MODE_NORMAL (0 << 0)
2876 /* Encoder test pattern 1 - combo pattern */
2877 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
2878 /* Encoder test pattern 2 - full screen vertical 75% color bars */
2879 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
2880 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
2881 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
2882 /* Encoder test pattern 4 - random noise */
2883 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
2884 /* Encoder test pattern 5 - linear color ramps */
2885 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
2887 * This test mode forces the DACs to 50% of full output.
2889 * This is used for load detection in combination with TVDAC_SENSE_MASK
2891 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2892 # define TV_TEST_MODE_MASK (7 << 0)
2894 #define TV_DAC _MMIO(0x68004)
2895 # define TV_DAC_SAVE 0x00ffff00
2897 * Reports that DAC state change logic has reported change (RO).
2899 * This gets cleared when TV_DAC_STATE_EN is cleared
2901 # define TVDAC_STATE_CHG (1 << 31)
2902 # define TVDAC_SENSE_MASK (7 << 28)
2903 /* Reports that DAC A voltage is above the detect threshold */
2904 # define TVDAC_A_SENSE (1 << 30)
2905 /* Reports that DAC B voltage is above the detect threshold */
2906 # define TVDAC_B_SENSE (1 << 29)
2907 /* Reports that DAC C voltage is above the detect threshold */
2908 # define TVDAC_C_SENSE (1 << 28)
2910 * Enables DAC state detection logic, for load-based TV detection.
2912 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2913 * to off, for load detection to work.
2915 # define TVDAC_STATE_CHG_EN (1 << 27)
2916 /* Sets the DAC A sense value to high */
2917 # define TVDAC_A_SENSE_CTL (1 << 26)
2918 /* Sets the DAC B sense value to high */
2919 # define TVDAC_B_SENSE_CTL (1 << 25)
2920 /* Sets the DAC C sense value to high */
2921 # define TVDAC_C_SENSE_CTL (1 << 24)
2922 /* Overrides the ENC_ENABLE and DAC voltage levels */
2923 # define DAC_CTL_OVERRIDE (1 << 7)
2924 /* Sets the slew rate. Must be preserved in software */
2925 # define ENC_TVDAC_SLEW_FAST (1 << 6)
2926 # define DAC_A_1_3_V (0 << 4)
2927 # define DAC_A_1_1_V (1 << 4)
2928 # define DAC_A_0_7_V (2 << 4)
2929 # define DAC_A_MASK (3 << 4)
2930 # define DAC_B_1_3_V (0 << 2)
2931 # define DAC_B_1_1_V (1 << 2)
2932 # define DAC_B_0_7_V (2 << 2)
2933 # define DAC_B_MASK (3 << 2)
2934 # define DAC_C_1_3_V (0 << 0)
2935 # define DAC_C_1_1_V (1 << 0)
2936 # define DAC_C_0_7_V (2 << 0)
2937 # define DAC_C_MASK (3 << 0)
2940 * CSC coefficients are stored in a floating point format with 9 bits of
2941 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2942 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2943 * -1 (0x3) being the only legal negative value.
2945 #define TV_CSC_Y _MMIO(0x68010)
2946 # define TV_RY_MASK 0x07ff0000
2947 # define TV_RY_SHIFT 16
2948 # define TV_GY_MASK 0x00000fff
2949 # define TV_GY_SHIFT 0
2951 #define TV_CSC_Y2 _MMIO(0x68014)
2952 # define TV_BY_MASK 0x07ff0000
2953 # define TV_BY_SHIFT 16
2955 * Y attenuation for component video.
2957 * Stored in 1.9 fixed point.
2959 # define TV_AY_MASK 0x000003ff
2960 # define TV_AY_SHIFT 0
2962 #define TV_CSC_U _MMIO(0x68018)
2963 # define TV_RU_MASK 0x07ff0000
2964 # define TV_RU_SHIFT 16
2965 # define TV_GU_MASK 0x000007ff
2966 # define TV_GU_SHIFT 0
2968 #define TV_CSC_U2 _MMIO(0x6801c)
2969 # define TV_BU_MASK 0x07ff0000
2970 # define TV_BU_SHIFT 16
2972 * U attenuation for component video.
2974 * Stored in 1.9 fixed point.
2976 # define TV_AU_MASK 0x000003ff
2977 # define TV_AU_SHIFT 0
2979 #define TV_CSC_V _MMIO(0x68020)
2980 # define TV_RV_MASK 0x0fff0000
2981 # define TV_RV_SHIFT 16
2982 # define TV_GV_MASK 0x000007ff
2983 # define TV_GV_SHIFT 0
2985 #define TV_CSC_V2 _MMIO(0x68024)
2986 # define TV_BV_MASK 0x07ff0000
2987 # define TV_BV_SHIFT 16
2989 * V attenuation for component video.
2991 * Stored in 1.9 fixed point.
2993 # define TV_AV_MASK 0x000007ff
2994 # define TV_AV_SHIFT 0
2996 #define TV_CLR_KNOBS _MMIO(0x68028)
2997 /* 2s-complement brightness adjustment */
2998 # define TV_BRIGHTNESS_MASK 0xff000000
2999 # define TV_BRIGHTNESS_SHIFT 24
3000 /* Contrast adjustment, as a 2.6 unsigned floating point number */
3001 # define TV_CONTRAST_MASK 0x00ff0000
3002 # define TV_CONTRAST_SHIFT 16
3003 /* Saturation adjustment, as a 2.6 unsigned floating point number */
3004 # define TV_SATURATION_MASK 0x0000ff00
3005 # define TV_SATURATION_SHIFT 8
3006 /* Hue adjustment, as an integer phase angle in degrees */
3007 # define TV_HUE_MASK 0x000000ff
3008 # define TV_HUE_SHIFT 0
3010 #define TV_CLR_LEVEL _MMIO(0x6802c)
3011 /* Controls the DAC level for black */
3012 # define TV_BLACK_LEVEL_MASK 0x01ff0000
3013 # define TV_BLACK_LEVEL_SHIFT 16
3014 /* Controls the DAC level for blanking */
3015 # define TV_BLANK_LEVEL_MASK 0x000001ff
3016 # define TV_BLANK_LEVEL_SHIFT 0
3018 #define TV_H_CTL_1 _MMIO(0x68030)
3019 /* Number of pixels in the hsync. */
3020 # define TV_HSYNC_END_MASK 0x1fff0000
3021 # define TV_HSYNC_END_SHIFT 16
3022 /* Total number of pixels minus one in the line (display and blanking). */
3023 # define TV_HTOTAL_MASK 0x00001fff
3024 # define TV_HTOTAL_SHIFT 0
3026 #define TV_H_CTL_2 _MMIO(0x68034)
3027 /* Enables the colorburst (needed for non-component color) */
3028 # define TV_BURST_ENA (1 << 31)
3029 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
3030 # define TV_HBURST_START_SHIFT 16
3031 # define TV_HBURST_START_MASK 0x1fff0000
3032 /* Length of the colorburst */
3033 # define TV_HBURST_LEN_SHIFT 0
3034 # define TV_HBURST_LEN_MASK 0x0001fff
3036 #define TV_H_CTL_3 _MMIO(0x68038)
3037 /* End of hblank, measured in pixels minus one from start of hsync */
3038 # define TV_HBLANK_END_SHIFT 16
3039 # define TV_HBLANK_END_MASK 0x1fff0000
3040 /* Start of hblank, measured in pixels minus one from start of hsync */
3041 # define TV_HBLANK_START_SHIFT 0
3042 # define TV_HBLANK_START_MASK 0x0001fff
3044 #define TV_V_CTL_1 _MMIO(0x6803c)
3046 # define TV_NBR_END_SHIFT 16
3047 # define TV_NBR_END_MASK 0x07ff0000
3049 # define TV_VI_END_F1_SHIFT 8
3050 # define TV_VI_END_F1_MASK 0x00003f00
3052 # define TV_VI_END_F2_SHIFT 0
3053 # define TV_VI_END_F2_MASK 0x0000003f
3055 #define TV_V_CTL_2 _MMIO(0x68040)
3056 /* Length of vsync, in half lines */
3057 # define TV_VSYNC_LEN_MASK 0x07ff0000
3058 # define TV_VSYNC_LEN_SHIFT 16
3059 /* Offset of the start of vsync in field 1, measured in one less than the
3060 * number of half lines.
3062 # define TV_VSYNC_START_F1_MASK 0x00007f00
3063 # define TV_VSYNC_START_F1_SHIFT 8
3065 * Offset of the start of vsync in field 2, measured in one less than the
3066 * number of half lines.
3068 # define TV_VSYNC_START_F2_MASK 0x0000007f
3069 # define TV_VSYNC_START_F2_SHIFT 0
3071 #define TV_V_CTL_3 _MMIO(0x68044)
3072 /* Enables generation of the equalization signal */
3073 # define TV_EQUAL_ENA (1 << 31)
3074 /* Length of vsync, in half lines */
3075 # define TV_VEQ_LEN_MASK 0x007f0000
3076 # define TV_VEQ_LEN_SHIFT 16
3077 /* Offset of the start of equalization in field 1, measured in one less than
3078 * the number of half lines.
3080 # define TV_VEQ_START_F1_MASK 0x0007f00
3081 # define TV_VEQ_START_F1_SHIFT 8
3083 * Offset of the start of equalization in field 2, measured in one less than
3084 * the number of half lines.
3086 # define TV_VEQ_START_F2_MASK 0x000007f
3087 # define TV_VEQ_START_F2_SHIFT 0
3089 #define TV_V_CTL_4 _MMIO(0x68048)
3091 * Offset to start of vertical colorburst, measured in one less than the
3092 * number of lines from vertical start.
3094 # define TV_VBURST_START_F1_MASK 0x003f0000
3095 # define TV_VBURST_START_F1_SHIFT 16
3097 * Offset to the end of vertical colorburst, measured in one less than the
3098 * number of lines from the start of NBR.
3100 # define TV_VBURST_END_F1_MASK 0x000000ff
3101 # define TV_VBURST_END_F1_SHIFT 0
3103 #define TV_V_CTL_5 _MMIO(0x6804c)
3105 * Offset to start of vertical colorburst, measured in one less than the
3106 * number of lines from vertical start.
3108 # define TV_VBURST_START_F2_MASK 0x003f0000
3109 # define TV_VBURST_START_F2_SHIFT 16
3111 * Offset to the end of vertical colorburst, measured in one less than the
3112 * number of lines from the start of NBR.
3114 # define TV_VBURST_END_F2_MASK 0x000000ff
3115 # define TV_VBURST_END_F2_SHIFT 0
3117 #define TV_V_CTL_6 _MMIO(0x68050)
3119 * Offset to start of vertical colorburst, measured in one less than the
3120 * number of lines from vertical start.
3122 # define TV_VBURST_START_F3_MASK 0x003f0000
3123 # define TV_VBURST_START_F3_SHIFT 16
3125 * Offset to the end of vertical colorburst, measured in one less than the
3126 * number of lines from the start of NBR.
3128 # define TV_VBURST_END_F3_MASK 0x000000ff
3129 # define TV_VBURST_END_F3_SHIFT 0
3131 #define TV_V_CTL_7 _MMIO(0x68054)
3133 * Offset to start of vertical colorburst, measured in one less than the
3134 * number of lines from vertical start.
3136 # define TV_VBURST_START_F4_MASK 0x003f0000
3137 # define TV_VBURST_START_F4_SHIFT 16
3139 * Offset to the end of vertical colorburst, measured in one less than the
3140 * number of lines from the start of NBR.
3142 # define TV_VBURST_END_F4_MASK 0x000000ff
3143 # define TV_VBURST_END_F4_SHIFT 0
3145 #define TV_SC_CTL_1 _MMIO(0x68060)
3146 /* Turns on the first subcarrier phase generation DDA */
3147 # define TV_SC_DDA1_EN (1 << 31)
3148 /* Turns on the first subcarrier phase generation DDA */
3149 # define TV_SC_DDA2_EN (1 << 30)
3150 /* Turns on the first subcarrier phase generation DDA */
3151 # define TV_SC_DDA3_EN (1 << 29)
3152 /* Sets the subcarrier DDA to reset frequency every other field */
3153 # define TV_SC_RESET_EVERY_2 (0 << 24)
3154 /* Sets the subcarrier DDA to reset frequency every fourth field */
3155 # define TV_SC_RESET_EVERY_4 (1 << 24)
3156 /* Sets the subcarrier DDA to reset frequency every eighth field */
3157 # define TV_SC_RESET_EVERY_8 (2 << 24)
3158 /* Sets the subcarrier DDA to never reset the frequency */
3159 # define TV_SC_RESET_NEVER (3 << 24)
3160 /* Sets the peak amplitude of the colorburst.*/
3161 # define TV_BURST_LEVEL_MASK 0x00ff0000
3162 # define TV_BURST_LEVEL_SHIFT 16
3163 /* Sets the increment of the first subcarrier phase generation DDA */
3164 # define TV_SCDDA1_INC_MASK 0x00000fff
3165 # define TV_SCDDA1_INC_SHIFT 0
3167 #define TV_SC_CTL_2 _MMIO(0x68064)
3168 /* Sets the rollover for the second subcarrier phase generation DDA */
3169 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
3170 # define TV_SCDDA2_SIZE_SHIFT 16
3171 /* Sets the increent of the second subcarrier phase generation DDA */
3172 # define TV_SCDDA2_INC_MASK 0x00007fff
3173 # define TV_SCDDA2_INC_SHIFT 0
3175 #define TV_SC_CTL_3 _MMIO(0x68068)
3176 /* Sets the rollover for the third subcarrier phase generation DDA */
3177 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
3178 # define TV_SCDDA3_SIZE_SHIFT 16
3179 /* Sets the increent of the third subcarrier phase generation DDA */
3180 # define TV_SCDDA3_INC_MASK 0x00007fff
3181 # define TV_SCDDA3_INC_SHIFT 0
3183 #define TV_WIN_POS _MMIO(0x68070)
3184 /* X coordinate of the display from the start of horizontal active */
3185 # define TV_XPOS_MASK 0x1fff0000
3186 # define TV_XPOS_SHIFT 16
3187 /* Y coordinate of the display from the start of vertical active (NBR) */
3188 # define TV_YPOS_MASK 0x00000fff
3189 # define TV_YPOS_SHIFT 0
3191 #define TV_WIN_SIZE _MMIO(0x68074)
3192 /* Horizontal size of the display window, measured in pixels*/
3193 # define TV_XSIZE_MASK 0x1fff0000
3194 # define TV_XSIZE_SHIFT 16
3196 * Vertical size of the display window, measured in pixels.
3198 * Must be even for interlaced modes.
3200 # define TV_YSIZE_MASK 0x00000fff
3201 # define TV_YSIZE_SHIFT 0
3203 #define TV_FILTER_CTL_1 _MMIO(0x68080)
3205 * Enables automatic scaling calculation.
3207 * If set, the rest of the registers are ignored, and the calculated values can
3208 * be read back from the register.
3210 # define TV_AUTO_SCALE (1 << 31)
3212 * Disables the vertical filter.
3214 * This is required on modes more than 1024 pixels wide */
3215 # define TV_V_FILTER_BYPASS (1 << 29)
3216 /* Enables adaptive vertical filtering */
3217 # define TV_VADAPT (1 << 28)
3218 # define TV_VADAPT_MODE_MASK (3 << 26)
3219 /* Selects the least adaptive vertical filtering mode */
3220 # define TV_VADAPT_MODE_LEAST (0 << 26)
3221 /* Selects the moderately adaptive vertical filtering mode */
3222 # define TV_VADAPT_MODE_MODERATE (1 << 26)
3223 /* Selects the most adaptive vertical filtering mode */
3224 # define TV_VADAPT_MODE_MOST (3 << 26)
3226 * Sets the horizontal scaling factor.
3228 * This should be the fractional part of the horizontal scaling factor divided
3229 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
3231 * (src width - 1) / ((oversample * dest width) - 1)
3233 # define TV_HSCALE_FRAC_MASK 0x00003fff
3234 # define TV_HSCALE_FRAC_SHIFT 0
3236 #define TV_FILTER_CTL_2 _MMIO(0x68084)
3238 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3240 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
3242 # define TV_VSCALE_INT_MASK 0x00038000
3243 # define TV_VSCALE_INT_SHIFT 15
3245 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3247 * \sa TV_VSCALE_INT_MASK
3249 # define TV_VSCALE_FRAC_MASK 0x00007fff
3250 # define TV_VSCALE_FRAC_SHIFT 0
3252 #define TV_FILTER_CTL_3 _MMIO(0x68088)
3254 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3256 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
3258 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3260 # define TV_VSCALE_IP_INT_MASK 0x00038000
3261 # define TV_VSCALE_IP_INT_SHIFT 15
3263 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3265 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
3267 * \sa TV_VSCALE_IP_INT_MASK
3269 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
3270 # define TV_VSCALE_IP_FRAC_SHIFT 0
3272 #define TV_CC_CONTROL _MMIO(0x68090)
3273 # define TV_CC_ENABLE (1 << 31)
3275 * Specifies which field to send the CC data in.
3277 * CC data is usually sent in field 0.
3279 # define TV_CC_FID_MASK (1 << 27)
3280 # define TV_CC_FID_SHIFT 27
3281 /* Sets the horizontal position of the CC data. Usually 135. */
3282 # define TV_CC_HOFF_MASK 0x03ff0000
3283 # define TV_CC_HOFF_SHIFT 16
3284 /* Sets the vertical position of the CC data. Usually 21 */
3285 # define TV_CC_LINE_MASK 0x0000003f
3286 # define TV_CC_LINE_SHIFT 0
3288 #define TV_CC_DATA _MMIO(0x68094)
3289 # define TV_CC_RDY (1 << 31)
3290 /* Second word of CC data to be transmitted. */
3291 # define TV_CC_DATA_2_MASK 0x007f0000
3292 # define TV_CC_DATA_2_SHIFT 16
3293 /* First word of CC data to be transmitted. */
3294 # define TV_CC_DATA_1_MASK 0x0000007f
3295 # define TV_CC_DATA_1_SHIFT 0
3297 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
3298 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
3299 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
3300 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
3303 #define DP_A _MMIO(0x64000) /* eDP */
3304 #define DP_B _MMIO(0x64100)
3305 #define DP_C _MMIO(0x64200)
3306 #define DP_D _MMIO(0x64300)
3308 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
3309 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
3310 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
3312 #define DP_PORT_EN (1 << 31)
3313 #define DP_PIPE_SEL_SHIFT 30
3314 #define DP_PIPE_SEL_MASK (1 << 30)
3315 #define DP_PIPE_SEL(pipe) ((pipe) << 30)
3316 #define DP_PIPE_SEL_SHIFT_IVB 29
3317 #define DP_PIPE_SEL_MASK_IVB (3 << 29)
3318 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
3319 #define DP_PIPE_SEL_SHIFT_CHV 16
3320 #define DP_PIPE_SEL_MASK_CHV (3 << 16)
3321 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
3323 /* Link training mode - select a suitable mode for each stage */
3324 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
3325 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
3326 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3327 #define DP_LINK_TRAIN_OFF (3 << 28)
3328 #define DP_LINK_TRAIN_MASK (3 << 28)
3329 #define DP_LINK_TRAIN_SHIFT 28
3331 /* CPT Link training mode */
3332 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3333 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3334 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3335 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3336 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3337 #define DP_LINK_TRAIN_SHIFT_CPT 8
3339 /* Signal voltages. These are mostly controlled by the other end */
3340 #define DP_VOLTAGE_0_4 (0 << 25)
3341 #define DP_VOLTAGE_0_6 (1 << 25)
3342 #define DP_VOLTAGE_0_8 (2 << 25)
3343 #define DP_VOLTAGE_1_2 (3 << 25)
3344 #define DP_VOLTAGE_MASK (7 << 25)
3345 #define DP_VOLTAGE_SHIFT 25
3347 /* Signal pre-emphasis levels, like voltages, the other end tells us what
3350 #define DP_PRE_EMPHASIS_0 (0 << 22)
3351 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
3352 #define DP_PRE_EMPHASIS_6 (2 << 22)
3353 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
3354 #define DP_PRE_EMPHASIS_MASK (7 << 22)
3355 #define DP_PRE_EMPHASIS_SHIFT 22
3357 /* How many wires to use. I guess 3 was too hard */
3358 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
3359 #define DP_PORT_WIDTH_MASK (7 << 19)
3360 #define DP_PORT_WIDTH_SHIFT 19
3362 /* Mystic DPCD version 1.1 special mode */
3363 #define DP_ENHANCED_FRAMING (1 << 18)
3366 #define DP_PLL_FREQ_270MHZ (0 << 16)
3367 #define DP_PLL_FREQ_162MHZ (1 << 16)
3368 #define DP_PLL_FREQ_MASK (3 << 16)
3370 /* locked once port is enabled */
3371 #define DP_PORT_REVERSAL (1 << 15)
3374 #define DP_PLL_ENABLE (1 << 14)
3376 /* sends the clock on lane 15 of the PEG for debug */
3377 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3379 #define DP_SCRAMBLING_DISABLE (1 << 12)
3380 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
3382 /* limit RGB values to avoid confusing TVs */
3383 #define DP_COLOR_RANGE_16_235 (1 << 8)
3385 /* Turn on the audio link */
3386 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3388 /* vs and hs sync polarity */
3389 #define DP_SYNC_VS_HIGH (1 << 4)
3390 #define DP_SYNC_HS_HIGH (1 << 3)
3393 #define DP_DETECTED (1 << 2)
3395 /* The aux channel provides a way to talk to the
3396 * signal sink for DDC etc. Max packet size supported
3397 * is 20 bytes in each direction, hence the 5 fixed
3400 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
3401 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
3403 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
3404 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
3406 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
3407 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
3409 #define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
3410 #define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
3411 #define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
3412 #define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
3414 #define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
3417 0, /* port/aux_ch C is non-existent */ \
3418 _XELPDP_USBC1_AUX_CH_CTL, \
3419 _XELPDP_USBC2_AUX_CH_CTL, \
3420 _XELPDP_USBC3_AUX_CH_CTL, \
3421 _XELPDP_USBC4_AUX_CH_CTL))
3423 #define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
3424 #define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
3425 #define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
3426 #define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
3428 #define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
3429 _DPA_AUX_CH_DATA1, \
3430 _DPB_AUX_CH_DATA1, \
3431 0, /* port/aux_ch C is non-existent */ \
3432 _XELPDP_USBC1_AUX_CH_DATA1, \
3433 _XELPDP_USBC2_AUX_CH_DATA1, \
3434 _XELPDP_USBC3_AUX_CH_DATA1, \
3435 _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
3437 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3438 #define DP_AUX_CH_CTL_DONE (1 << 30)
3439 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3440 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3441 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3442 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3443 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3444 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
3445 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3446 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3447 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3448 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3449 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19)
3450 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18)
3451 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3452 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3453 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3454 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3455 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3456 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3457 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3458 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3459 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3460 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
3461 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
3462 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
3463 #define DP_AUX_CH_CTL_TBT_IO (1 << 11)
3464 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
3465 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
3466 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
3469 * Computing GMCH M and N values for the Display Port link
3471 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3473 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3475 * The GMCH value is used internally
3477 * bytes_per_pixel is the number of bytes coming out of the plane,
3478 * which is after the LUTs, so we want the bytes for our color format.
3479 * For our current usage, this is always 3, one byte for R, G and B.
3481 #define _PIPEA_DATA_M_G4X 0x70050
3482 #define _PIPEB_DATA_M_G4X 0x71050
3484 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3485 #define TU_SIZE_MASK REG_GENMASK(30, 25)
3486 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
3488 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
3489 #define DATA_LINK_N_MAX (0x800000)
3491 #define _PIPEA_DATA_N_G4X 0x70054
3492 #define _PIPEB_DATA_N_G4X 0x71054
3495 * Computing Link M and N values for the Display Port link
3497 * Link M / N = pixel_clock / ls_clk
3499 * (the DP spec calls pixel_clock the 'strm_clk')
3501 * The Link value is transmitted in the Main Stream
3502 * Attributes and VB-ID.
3505 #define _PIPEA_LINK_M_G4X 0x70060
3506 #define _PIPEB_LINK_M_G4X 0x71060
3507 #define _PIPEA_LINK_N_G4X 0x70064
3508 #define _PIPEB_LINK_N_G4X 0x71064
3510 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3511 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3512 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3513 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
3515 /* Display & cursor control */
3518 #define _PIPEADSL 0x70000
3519 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
3520 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
3521 #define _PIPEACONF 0x70008
3522 #define PIPECONF_ENABLE REG_BIT(31)
3523 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
3524 #define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */
3525 #define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
3526 #define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
3527 #define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
3528 #define PIPECONF_PIPE_LOCKED REG_BIT(25)
3529 #define PIPECONF_FORCE_BORDER REG_BIT(25)
3530 #define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
3531 #define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
3532 #define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
3533 #define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
3534 #define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
3535 #define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
3536 #define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
3537 #define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
3538 #define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
3539 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
3540 #define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
3541 #define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
3542 #define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
3544 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
3545 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
3547 #define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
3548 #define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
3549 #define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
3550 #define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
3551 #define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
3552 #define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
3553 #define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
3554 #define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
3555 #define PIPECONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
3556 #define PIPECONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x))
3557 #define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16)
3558 #define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
3559 #define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13)
3560 #define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
3561 #define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
3562 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
3563 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
3564 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
3565 #define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
3566 #define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
3567 #define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
3568 #define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
3569 #define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
3570 #define PIPECONF_DITHER_EN REG_BIT(4)
3571 #define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
3572 #define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
3573 #define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
3574 #define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
3575 #define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
3576 #define _PIPEASTAT 0x70024
3577 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
3578 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
3579 #define PIPE_CRC_ERROR_ENABLE (1UL << 29)
3580 #define PIPE_CRC_DONE_ENABLE (1UL << 28)
3581 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
3582 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
3583 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
3584 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
3585 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
3586 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
3587 #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
3588 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
3589 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
3590 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
3591 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
3592 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
3593 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
3594 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
3595 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
3596 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
3597 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
3598 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
3599 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
3600 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
3601 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
3602 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
3603 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
3604 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
3605 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
3606 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
3607 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
3608 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
3609 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
3610 #define PIPE_DPST_EVENT_STATUS (1UL << 7)
3611 #define PIPE_A_PSR_STATUS_VLV (1UL << 6)
3612 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
3613 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
3614 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
3615 #define PIPE_B_PSR_STATUS_VLV (1UL << 3)
3616 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
3617 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
3618 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
3619 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
3620 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
3621 #define PIPE_HBLANK_INT_STATUS (1UL << 0)
3622 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
3624 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
3625 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
3627 #define PIPE_A_OFFSET 0x70000
3628 #define PIPE_B_OFFSET 0x71000
3629 #define PIPE_C_OFFSET 0x72000
3630 #define PIPE_D_OFFSET 0x73000
3631 #define CHV_PIPE_C_OFFSET 0x74000
3633 * There's actually no pipe EDP. Some pipe registers have
3634 * simply shifted from the pipe to the transcoder, while
3635 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
3636 * to access such registers in transcoder EDP.
3638 #define PIPE_EDP_OFFSET 0x7f000
3640 /* ICL DSI 0 and 1 */
3641 #define PIPE_DSI0_OFFSET 0x7b000
3642 #define PIPE_DSI1_OFFSET 0x7b800
3644 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
3645 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
3646 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
3647 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
3648 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
3650 #define _PIPEAGCMAX 0x70010
3651 #define _PIPEBGCMAX 0x71010
3652 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
3654 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
3655 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
3656 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
3658 #define _PIPE_MISC_A 0x70030
3659 #define _PIPE_MISC_B 0x71030
3660 #define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
3661 #define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
3662 #define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
3663 #define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
3664 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
3666 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
3667 * valid values of: 6, 8, 10 BPC.
3668 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
3671 #define PIPEMISC_BPC_MASK REG_GENMASK(7, 5)
3672 #define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
3673 #define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
3674 #define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
3675 #define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
3676 #define PIPEMISC_DITHER_ENABLE REG_BIT(4)
3677 #define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
3678 #define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
3679 #define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
3680 #define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
3681 #define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
3682 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
3684 #define _PIPE_MISC2_A 0x7002C
3685 #define _PIPE_MISC2_B 0x7102C
3686 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
3687 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
3688 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
3689 #define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A)
3691 /* Skylake+ pipe bottom (background) color */
3692 #define _SKL_BOTTOM_COLOR_A 0x70034
3693 #define _SKL_BOTTOM_COLOR_B 0x71034
3694 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
3695 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
3696 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
3698 #define _ICL_PIPE_A_STATUS 0x70058
3699 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
3700 #define PIPE_STATUS_UNDERRUN REG_BIT(31)
3701 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28)
3702 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)
3703 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
3705 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
3706 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
3707 #define PIPEB_HLINE_INT_EN REG_BIT(28)
3708 #define PIPEB_VBLANK_INT_EN REG_BIT(27)
3709 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
3710 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
3711 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
3712 #define PIPE_PSR_INT_EN REG_BIT(22)
3713 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
3714 #define PIPEA_HLINE_INT_EN REG_BIT(20)
3715 #define PIPEA_VBLANK_INT_EN REG_BIT(19)
3716 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
3717 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
3718 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
3719 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
3720 #define PIPEC_HLINE_INT_EN REG_BIT(12)
3721 #define PIPEC_VBLANK_INT_EN REG_BIT(11)
3722 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
3723 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
3724 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
3726 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
3727 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
3728 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
3729 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
3730 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
3731 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
3732 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
3733 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
3734 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
3735 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
3736 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
3737 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
3738 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
3739 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
3740 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
3741 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
3742 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
3743 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
3744 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
3745 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
3746 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
3747 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
3748 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
3749 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
3750 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
3751 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
3752 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
3753 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
3754 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
3756 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
3757 #define DSPARB_CSTART_MASK (0x7f << 7)
3758 #define DSPARB_CSTART_SHIFT 7
3759 #define DSPARB_BSTART_MASK (0x7f)
3760 #define DSPARB_BSTART_SHIFT 0
3761 #define DSPARB_BEND_SHIFT 9 /* on 855 */
3762 #define DSPARB_AEND_SHIFT 0
3763 #define DSPARB_SPRITEA_SHIFT_VLV 0
3764 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
3765 #define DSPARB_SPRITEB_SHIFT_VLV 8
3766 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
3767 #define DSPARB_SPRITEC_SHIFT_VLV 16
3768 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
3769 #define DSPARB_SPRITED_SHIFT_VLV 24
3770 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
3771 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
3772 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
3773 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
3774 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
3775 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
3776 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
3777 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
3778 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
3779 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
3780 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
3781 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
3782 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
3783 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
3784 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
3785 #define DSPARB_SPRITEE_SHIFT_VLV 0
3786 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
3787 #define DSPARB_SPRITEF_SHIFT_VLV 8
3788 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
3790 /* pnv/gen4/g4x/vlv/chv */
3791 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
3792 #define DSPFW_SR_SHIFT 23
3793 #define DSPFW_SR_MASK (0x1ff << 23)
3794 #define DSPFW_CURSORB_SHIFT 16
3795 #define DSPFW_CURSORB_MASK (0x3f << 16)
3796 #define DSPFW_PLANEB_SHIFT 8
3797 #define DSPFW_PLANEB_MASK (0x7f << 8)
3798 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
3799 #define DSPFW_PLANEA_SHIFT 0
3800 #define DSPFW_PLANEA_MASK (0x7f << 0)
3801 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
3802 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
3803 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
3804 #define DSPFW_FBC_SR_SHIFT 28
3805 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
3806 #define DSPFW_FBC_HPLL_SR_SHIFT 24
3807 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
3808 #define DSPFW_SPRITEB_SHIFT (16)
3809 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
3810 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
3811 #define DSPFW_CURSORA_SHIFT 8
3812 #define DSPFW_CURSORA_MASK (0x3f << 8)
3813 #define DSPFW_PLANEC_OLD_SHIFT 0
3814 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
3815 #define DSPFW_SPRITEA_SHIFT 0
3816 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
3817 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
3818 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
3819 #define DSPFW_HPLL_SR_EN (1 << 31)
3820 #define PINEVIEW_SELF_REFRESH_EN (1 << 30)
3821 #define DSPFW_CURSOR_SR_SHIFT 24
3822 #define DSPFW_CURSOR_SR_MASK (0x3f << 24)
3823 #define DSPFW_HPLL_CURSOR_SHIFT 16
3824 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
3825 #define DSPFW_HPLL_SR_SHIFT 0
3826 #define DSPFW_HPLL_SR_MASK (0x1ff << 0)
3829 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
3830 #define DSPFW_SPRITEB_WM1_SHIFT 16
3831 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
3832 #define DSPFW_CURSORA_WM1_SHIFT 8
3833 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
3834 #define DSPFW_SPRITEA_WM1_SHIFT 0
3835 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
3836 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
3837 #define DSPFW_PLANEB_WM1_SHIFT 24
3838 #define DSPFW_PLANEB_WM1_MASK (0xff << 24)
3839 #define DSPFW_PLANEA_WM1_SHIFT 16
3840 #define DSPFW_PLANEA_WM1_MASK (0xff << 16)
3841 #define DSPFW_CURSORB_WM1_SHIFT 8
3842 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
3843 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
3844 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
3845 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
3846 #define DSPFW_SR_WM1_SHIFT 0
3847 #define DSPFW_SR_WM1_MASK (0x1ff << 0)
3848 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
3849 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
3850 #define DSPFW_SPRITED_WM1_SHIFT 24
3851 #define DSPFW_SPRITED_WM1_MASK (0xff << 24)
3852 #define DSPFW_SPRITED_SHIFT 16
3853 #define DSPFW_SPRITED_MASK_VLV (0xff << 16)
3854 #define DSPFW_SPRITEC_WM1_SHIFT 8
3855 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
3856 #define DSPFW_SPRITEC_SHIFT 0
3857 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
3858 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
3859 #define DSPFW_SPRITEF_WM1_SHIFT 24
3860 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
3861 #define DSPFW_SPRITEF_SHIFT 16
3862 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
3863 #define DSPFW_SPRITEE_WM1_SHIFT 8
3864 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
3865 #define DSPFW_SPRITEE_SHIFT 0
3866 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
3867 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
3868 #define DSPFW_PLANEC_WM1_SHIFT 24
3869 #define DSPFW_PLANEC_WM1_MASK (0xff << 24)
3870 #define DSPFW_PLANEC_SHIFT 16
3871 #define DSPFW_PLANEC_MASK_VLV (0xff << 16)
3872 #define DSPFW_CURSORC_WM1_SHIFT 8
3873 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
3874 #define DSPFW_CURSORC_SHIFT 0
3875 #define DSPFW_CURSORC_MASK (0x3f << 0)
3877 /* vlv/chv high order bits */
3878 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
3879 #define DSPFW_SR_HI_SHIFT 24
3880 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
3881 #define DSPFW_SPRITEF_HI_SHIFT 23
3882 #define DSPFW_SPRITEF_HI_MASK (1 << 23)
3883 #define DSPFW_SPRITEE_HI_SHIFT 22
3884 #define DSPFW_SPRITEE_HI_MASK (1 << 22)
3885 #define DSPFW_PLANEC_HI_SHIFT 21
3886 #define DSPFW_PLANEC_HI_MASK (1 << 21)
3887 #define DSPFW_SPRITED_HI_SHIFT 20
3888 #define DSPFW_SPRITED_HI_MASK (1 << 20)
3889 #define DSPFW_SPRITEC_HI_SHIFT 16
3890 #define DSPFW_SPRITEC_HI_MASK (1 << 16)
3891 #define DSPFW_PLANEB_HI_SHIFT 12
3892 #define DSPFW_PLANEB_HI_MASK (1 << 12)
3893 #define DSPFW_SPRITEB_HI_SHIFT 8
3894 #define DSPFW_SPRITEB_HI_MASK (1 << 8)
3895 #define DSPFW_SPRITEA_HI_SHIFT 4
3896 #define DSPFW_SPRITEA_HI_MASK (1 << 4)
3897 #define DSPFW_PLANEA_HI_SHIFT 0
3898 #define DSPFW_PLANEA_HI_MASK (1 << 0)
3899 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
3900 #define DSPFW_SR_WM1_HI_SHIFT 24
3901 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
3902 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
3903 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
3904 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
3905 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
3906 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
3907 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
3908 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
3909 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
3910 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
3911 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
3912 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
3913 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
3914 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
3915 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
3916 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
3917 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
3918 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
3919 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
3921 /* drain latency register values*/
3922 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
3923 #define DDL_CURSOR_SHIFT 24
3924 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
3925 #define DDL_PLANE_SHIFT 0
3926 #define DDL_PRECISION_HIGH (1 << 7)
3927 #define DDL_PRECISION_LOW (0 << 7)
3928 #define DRAIN_LATENCY_MASK 0x7f
3930 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
3931 #define CBR_PND_DEADLINE_DISABLE (1 << 31)
3932 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
3934 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
3935 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
3937 /* FIFO watermark sizes etc */
3938 #define G4X_FIFO_LINE_SIZE 64
3939 #define I915_FIFO_LINE_SIZE 64
3940 #define I830_FIFO_LINE_SIZE 32
3942 #define VALLEYVIEW_FIFO_SIZE 255
3943 #define G4X_FIFO_SIZE 127
3944 #define I965_FIFO_SIZE 512
3945 #define I945_FIFO_SIZE 127
3946 #define I915_FIFO_SIZE 95
3947 #define I855GM_FIFO_SIZE 127 /* In cachelines */
3948 #define I830_FIFO_SIZE 95
3950 #define VALLEYVIEW_MAX_WM 0xff
3951 #define G4X_MAX_WM 0x3f
3952 #define I915_MAX_WM 0x3f
3954 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
3955 #define PINEVIEW_FIFO_LINE_SIZE 64
3956 #define PINEVIEW_MAX_WM 0x1ff
3957 #define PINEVIEW_DFT_WM 0x3f
3958 #define PINEVIEW_DFT_HPLLOFF_WM 0
3959 #define PINEVIEW_GUARD_WM 10
3960 #define PINEVIEW_CURSOR_FIFO 64
3961 #define PINEVIEW_CURSOR_MAX_WM 0x3f
3962 #define PINEVIEW_CURSOR_DFT_WM 0
3963 #define PINEVIEW_CURSOR_GUARD_WM 5
3965 #define VALLEYVIEW_CURSOR_MAX_WM 64
3966 #define I965_CURSOR_FIFO 64
3967 #define I965_CURSOR_MAX_WM 32
3968 #define I965_CURSOR_DFT_WM 8
3970 /* Watermark register definitions for SKL */
3971 #define _CUR_WM_A_0 0x70140
3972 #define _CUR_WM_B_0 0x71140
3973 #define _CUR_WM_SAGV_A 0x70158
3974 #define _CUR_WM_SAGV_B 0x71158
3975 #define _CUR_WM_SAGV_TRANS_A 0x7015C
3976 #define _CUR_WM_SAGV_TRANS_B 0x7115C
3977 #define _CUR_WM_TRANS_A 0x70168
3978 #define _CUR_WM_TRANS_B 0x71168
3979 #define _PLANE_WM_1_A_0 0x70240
3980 #define _PLANE_WM_1_B_0 0x71240
3981 #define _PLANE_WM_2_A_0 0x70340
3982 #define _PLANE_WM_2_B_0 0x71340
3983 #define _PLANE_WM_SAGV_1_A 0x70258
3984 #define _PLANE_WM_SAGV_1_B 0x71258
3985 #define _PLANE_WM_SAGV_2_A 0x70358
3986 #define _PLANE_WM_SAGV_2_B 0x71358
3987 #define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
3988 #define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
3989 #define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
3990 #define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
3991 #define _PLANE_WM_TRANS_1_A 0x70268
3992 #define _PLANE_WM_TRANS_1_B 0x71268
3993 #define _PLANE_WM_TRANS_2_A 0x70368
3994 #define _PLANE_WM_TRANS_2_B 0x71368
3995 #define PLANE_WM_EN (1 << 31)
3996 #define PLANE_WM_IGNORE_LINES (1 << 30)
3997 #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
3998 #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
4000 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
4001 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
4002 #define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
4003 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
4004 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
4005 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
4006 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
4007 #define _PLANE_WM_BASE(pipe, plane) \
4008 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4009 #define PLANE_WM(pipe, plane, level) \
4010 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4011 #define _PLANE_WM_SAGV_1(pipe) \
4012 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
4013 #define _PLANE_WM_SAGV_2(pipe) \
4014 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
4015 #define PLANE_WM_SAGV(pipe, plane) \
4016 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
4017 #define _PLANE_WM_SAGV_TRANS_1(pipe) \
4018 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
4019 #define _PLANE_WM_SAGV_TRANS_2(pipe) \
4020 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
4021 #define PLANE_WM_SAGV_TRANS(pipe, plane) \
4022 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
4023 #define _PLANE_WM_TRANS_1(pipe) \
4024 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
4025 #define _PLANE_WM_TRANS_2(pipe) \
4026 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
4027 #define PLANE_WM_TRANS(pipe, plane) \
4028 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
4030 /* define the Watermark register on Ironlake */
4031 #define _WM0_PIPEA_ILK 0x45100
4032 #define _WM0_PIPEB_ILK 0x45104
4033 #define _WM0_PIPEC_IVB 0x45200
4034 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
4035 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
4036 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
4037 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
4038 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
4039 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
4040 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
4041 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
4042 #define WM1_LP_ILK _MMIO(0x45108)
4043 #define WM2_LP_ILK _MMIO(0x4510c)
4044 #define WM3_LP_ILK _MMIO(0x45110)
4045 #define WM_LP_ENABLE REG_BIT(31)
4046 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
4047 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
4048 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
4049 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
4050 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
4051 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
4052 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
4053 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
4054 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
4055 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
4056 #define WM1S_LP_ILK _MMIO(0x45120)
4057 #define WM2S_LP_IVB _MMIO(0x45124)
4058 #define WM3S_LP_IVB _MMIO(0x45128)
4059 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
4060 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
4061 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
4064 * The two pipe frame counter registers are not synchronized, so
4065 * reading a stable value is somewhat tricky. The following code
4069 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4070 * PIPE_FRAME_HIGH_SHIFT;
4071 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4072 * PIPE_FRAME_LOW_SHIFT);
4073 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4074 * PIPE_FRAME_HIGH_SHIFT);
4075 * } while (high1 != high2);
4076 * frame = (high1 << 8) | low1;
4078 #define _PIPEAFRAMEHIGH 0x70040
4079 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
4080 #define PIPE_FRAME_HIGH_SHIFT 0
4081 #define _PIPEAFRAMEPIXEL 0x70044
4082 #define PIPE_FRAME_LOW_MASK 0xff000000
4083 #define PIPE_FRAME_LOW_SHIFT 24
4084 #define PIPE_PIXEL_MASK 0x00ffffff
4085 #define PIPE_PIXEL_SHIFT 0
4086 /* GM45+ just has to be different */
4087 #define _PIPEA_FRMCOUNT_G4X 0x70040
4088 #define _PIPEA_FLIPCOUNT_G4X 0x70044
4089 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
4090 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
4092 /* Cursor A & B regs */
4093 #define _CURACNTR 0x70080
4094 /* Old style CUR*CNTR flags (desktop 8xx) */
4095 #define CURSOR_ENABLE REG_BIT(31)
4096 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
4097 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
4098 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
4099 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
4100 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
4101 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
4102 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
4103 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
4104 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
4105 /* New style CUR*CNTR flags */
4106 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
4107 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
4108 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
4109 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
4110 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
4111 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
4112 #define MCURSOR_ROTATE_180 REG_BIT(15)
4113 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
4114 #define MCURSOR_MODE_MASK 0x27
4115 #define MCURSOR_MODE_DISABLE 0x00
4116 #define MCURSOR_MODE_128_32B_AX 0x02
4117 #define MCURSOR_MODE_256_32B_AX 0x03
4118 #define MCURSOR_MODE_64_32B_AX 0x07
4119 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
4120 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
4121 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
4122 #define _CURABASE 0x70084
4123 #define _CURAPOS 0x70088
4124 #define CURSOR_POS_Y_SIGN REG_BIT(31)
4125 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
4126 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
4127 #define CURSOR_POS_X_SIGN REG_BIT(15)
4128 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
4129 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
4130 #define _CURASIZE 0x700a0 /* 845/865 */
4131 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
4132 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
4133 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
4134 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
4135 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
4136 #define CUR_FBC_EN REG_BIT(31)
4137 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
4138 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
4139 #define _CURASURFLIVE 0x700ac /* g4x+ */
4140 #define _CURBCNTR 0x700c0
4141 #define _CURBBASE 0x700c4
4142 #define _CURBPOS 0x700c8
4144 #define _CURBCNTR_IVB 0x71080
4145 #define _CURBBASE_IVB 0x71084
4146 #define _CURBPOS_IVB 0x71088
4148 #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR)
4149 #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE)
4150 #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS)
4151 #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE)
4152 #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A)
4153 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
4155 #define CURSOR_A_OFFSET 0x70080
4156 #define CURSOR_B_OFFSET 0x700c0
4157 #define CHV_CURSOR_C_OFFSET 0x700e0
4158 #define IVB_CURSOR_B_OFFSET 0x71080
4159 #define IVB_CURSOR_C_OFFSET 0x72080
4160 #define TGL_CURSOR_D_OFFSET 0x73080
4162 /* Display A control */
4163 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */
4164 #define _DSPACNTR 0x70180
4165 #define DISP_ENABLE REG_BIT(31)
4166 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
4167 #define DISP_FORMAT_MASK REG_GENMASK(29, 26)
4168 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
4169 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
4170 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
4171 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
4172 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
4173 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
4174 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
4175 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
4176 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
4177 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
4178 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
4179 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
4180 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
4181 #define DISP_STEREO_ENABLE REG_BIT(25)
4182 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
4183 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
4184 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
4185 #define DISP_SRC_KEY_ENABLE REG_BIT(22)
4186 #define DISP_LINE_DOUBLE REG_BIT(20)
4187 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
4188 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
4189 #define DISP_ROTATE_180 REG_BIT(15)
4190 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
4191 #define DISP_TILED REG_BIT(10)
4192 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
4193 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
4194 #define _DSPAADDR 0x70184
4195 #define _DSPASTRIDE 0x70188
4196 #define _DSPAPOS 0x7018C /* reserved */
4197 #define DISP_POS_Y_MASK REG_GENMASK(31, 16)
4198 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
4199 #define DISP_POS_X_MASK REG_GENMASK(15, 0)
4200 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
4201 #define _DSPASIZE 0x70190
4202 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
4203 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
4204 #define DISP_WIDTH_MASK REG_GENMASK(15, 0)
4205 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
4206 #define _DSPASURF 0x7019C /* 965+ only */
4207 #define DISP_ADDR_MASK REG_GENMASK(31, 12)
4208 #define _DSPATILEOFF 0x701A4 /* 965+ only */
4209 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
4210 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
4211 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
4212 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
4213 #define _DSPAOFFSET 0x701A4 /* HSW */
4214 #define _DSPASURFLIVE 0x701AC
4215 #define _DSPAGAMC 0x701E0
4217 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV)
4218 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
4219 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
4220 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
4221 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
4222 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
4223 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
4224 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
4225 #define DSPLINOFF(plane) DSPADDR(plane)
4226 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
4227 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
4228 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
4230 /* CHV pipe B blender and primary plane */
4231 #define _CHV_BLEND_A 0x60a00
4232 #define CHV_BLEND_MASK REG_GENMASK(31, 30)
4233 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
4234 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
4235 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
4236 #define _CHV_CANVAS_A 0x60a04
4237 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
4238 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
4239 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
4240 #define _PRIMPOS_A 0x60a08
4241 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
4242 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
4243 #define PRIM_POS_X_MASK REG_GENMASK(15, 0)
4244 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
4245 #define _PRIMSIZE_A 0x60a0c
4246 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
4247 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
4248 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
4249 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
4250 #define _PRIMCNSTALPHA_A 0x60a10
4251 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
4252 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
4253 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
4255 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
4256 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
4257 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
4258 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
4259 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
4261 /* Display/Sprite base address macros */
4262 #define DISP_BASEADDR_MASK (0xfffff000)
4263 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
4264 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
4277 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
4278 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
4279 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
4280 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
4283 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
4284 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
4285 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
4286 #define _PIPEBFRAMEHIGH 0x71040
4287 #define _PIPEBFRAMEPIXEL 0x71044
4288 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
4289 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
4292 /* Display B control */
4293 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
4294 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15)
4295 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
4296 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
4297 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
4298 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
4299 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
4300 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
4301 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
4302 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
4303 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
4305 /* ICL DSI 0 and 1 */
4306 #define _PIPEDSI0CONF 0x7b008
4307 #define _PIPEDSI1CONF 0x7b808
4309 /* Sprite A control */
4310 #define _DVSACNTR 0x72180
4311 #define DVS_ENABLE REG_BIT(31)
4312 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
4313 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
4314 #define DVS_FORMAT_MASK REG_GENMASK(26, 25)
4315 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
4316 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
4317 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
4318 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
4319 #define DVS_PIPE_CSC_ENABLE REG_BIT(24)
4320 #define DVS_SOURCE_KEY REG_BIT(22)
4321 #define DVS_RGB_ORDER_XBGR REG_BIT(20)
4322 #define DVS_YUV_FORMAT_BT709 REG_BIT(18)
4323 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
4324 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
4325 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
4326 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
4327 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
4328 #define DVS_ROTATE_180 REG_BIT(15)
4329 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
4330 #define DVS_TILED REG_BIT(10)
4331 #define DVS_DEST_KEY REG_BIT(2)
4332 #define _DVSALINOFF 0x72184
4333 #define _DVSASTRIDE 0x72188
4334 #define _DVSAPOS 0x7218c
4335 #define DVS_POS_Y_MASK REG_GENMASK(31, 16)
4336 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
4337 #define DVS_POS_X_MASK REG_GENMASK(15, 0)
4338 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
4339 #define _DVSASIZE 0x72190
4340 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
4341 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
4342 #define DVS_WIDTH_MASK REG_GENMASK(15, 0)
4343 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
4344 #define _DVSAKEYVAL 0x72194
4345 #define _DVSAKEYMSK 0x72198
4346 #define _DVSASURF 0x7219c
4347 #define DVS_ADDR_MASK REG_GENMASK(31, 12)
4348 #define _DVSAKEYMAXVAL 0x721a0
4349 #define _DVSATILEOFF 0x721a4
4350 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
4351 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
4352 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
4353 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
4354 #define _DVSASURFLIVE 0x721ac
4355 #define _DVSAGAMC_G4X 0x721e0 /* g4x */
4356 #define _DVSASCALE 0x72204
4357 #define DVS_SCALE_ENABLE REG_BIT(31)
4358 #define DVS_FILTER_MASK REG_GENMASK(30, 29)
4359 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
4360 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
4361 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
4362 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
4363 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
4364 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
4365 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
4366 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
4367 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
4368 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
4369 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
4371 #define _DVSBCNTR 0x73180
4372 #define _DVSBLINOFF 0x73184
4373 #define _DVSBSTRIDE 0x73188
4374 #define _DVSBPOS 0x7318c
4375 #define _DVSBSIZE 0x73190
4376 #define _DVSBKEYVAL 0x73194
4377 #define _DVSBKEYMSK 0x73198
4378 #define _DVSBSURF 0x7319c
4379 #define _DVSBKEYMAXVAL 0x731a0
4380 #define _DVSBTILEOFF 0x731a4
4381 #define _DVSBSURFLIVE 0x731ac
4382 #define _DVSBGAMC_G4X 0x731e0 /* g4x */
4383 #define _DVSBSCALE 0x73204
4384 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
4385 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
4387 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
4388 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
4389 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
4390 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
4391 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
4392 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
4393 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
4394 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
4395 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
4396 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
4397 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
4398 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
4399 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
4400 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
4401 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
4403 #define _SPRA_CTL 0x70280
4404 #define SPRITE_ENABLE REG_BIT(31)
4405 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
4406 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4407 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
4408 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
4409 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
4410 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
4411 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
4412 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
4413 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
4414 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
4415 #define SPRITE_SOURCE_KEY REG_BIT(22)
4416 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
4417 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
4418 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
4419 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
4420 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
4421 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
4422 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
4423 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
4424 #define SPRITE_ROTATE_180 REG_BIT(15)
4425 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
4426 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
4427 #define SPRITE_TILED REG_BIT(10)
4428 #define SPRITE_DEST_KEY REG_BIT(2)
4429 #define _SPRA_LINOFF 0x70284
4430 #define _SPRA_STRIDE 0x70288
4431 #define _SPRA_POS 0x7028c
4432 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
4433 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
4434 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
4435 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
4436 #define _SPRA_SIZE 0x70290
4437 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
4438 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
4439 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
4440 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
4441 #define _SPRA_KEYVAL 0x70294
4442 #define _SPRA_KEYMSK 0x70298
4443 #define _SPRA_SURF 0x7029c
4444 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
4445 #define _SPRA_KEYMAX 0x702a0
4446 #define _SPRA_TILEOFF 0x702a4
4447 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
4448 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
4449 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
4450 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
4451 #define _SPRA_OFFSET 0x702a4
4452 #define _SPRA_SURFLIVE 0x702ac
4453 #define _SPRA_SCALE 0x70304
4454 #define SPRITE_SCALE_ENABLE REG_BIT(31)
4455 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
4456 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
4457 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
4458 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
4459 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
4460 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
4461 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
4462 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
4463 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
4464 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
4465 #define _SPRA_GAMC 0x70400
4466 #define _SPRA_GAMC16 0x70440
4467 #define _SPRA_GAMC17 0x7044c
4469 #define _SPRB_CTL 0x71280
4470 #define _SPRB_LINOFF 0x71284
4471 #define _SPRB_STRIDE 0x71288
4472 #define _SPRB_POS 0x7128c
4473 #define _SPRB_SIZE 0x71290
4474 #define _SPRB_KEYVAL 0x71294
4475 #define _SPRB_KEYMSK 0x71298
4476 #define _SPRB_SURF 0x7129c
4477 #define _SPRB_KEYMAX 0x712a0
4478 #define _SPRB_TILEOFF 0x712a4
4479 #define _SPRB_OFFSET 0x712a4
4480 #define _SPRB_SURFLIVE 0x712ac
4481 #define _SPRB_SCALE 0x71304
4482 #define _SPRB_GAMC 0x71400
4483 #define _SPRB_GAMC16 0x71440
4484 #define _SPRB_GAMC17 0x7144c
4486 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
4487 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
4488 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
4489 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
4490 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
4491 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
4492 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
4493 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
4494 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
4495 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
4496 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
4497 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
4498 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
4499 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
4500 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
4501 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
4503 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
4504 #define SP_ENABLE REG_BIT(31)
4505 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
4506 #define SP_FORMAT_MASK REG_GENMASK(29, 26)
4507 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
4508 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
4509 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
4510 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
4511 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
4512 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
4513 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
4514 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
4515 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
4516 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
4517 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
4518 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
4519 #define SP_SOURCE_KEY REG_BIT(22)
4520 #define SP_YUV_FORMAT_BT709 REG_BIT(18)
4521 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
4522 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
4523 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
4524 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
4525 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
4526 #define SP_ROTATE_180 REG_BIT(15)
4527 #define SP_TILED REG_BIT(10)
4528 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */
4529 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
4530 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
4531 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
4532 #define SP_POS_Y_MASK REG_GENMASK(31, 16)
4533 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
4534 #define SP_POS_X_MASK REG_GENMASK(15, 0)
4535 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
4536 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
4537 #define SP_HEIGHT_MASK REG_GENMASK(31, 16)
4538 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
4539 #define SP_WIDTH_MASK REG_GENMASK(15, 0)
4540 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
4541 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
4542 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
4543 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
4544 #define SP_ADDR_MASK REG_GENMASK(31, 12)
4545 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
4546 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
4547 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
4548 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
4549 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
4550 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
4551 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
4552 #define SP_CONST_ALPHA_ENABLE REG_BIT(31)
4553 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
4554 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
4555 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
4556 #define SP_CONTRAST_MASK REG_GENMASK(26, 18)
4557 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
4558 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
4559 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
4560 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
4561 #define SP_SH_SIN_MASK REG_GENMASK(26, 16)
4562 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
4563 #define SP_SH_COS_MASK REG_GENMASK(9, 0)
4564 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
4565 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
4567 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
4568 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
4569 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
4570 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
4571 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
4572 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
4573 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
4574 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
4575 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
4576 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
4577 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
4578 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
4579 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
4580 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
4582 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
4583 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
4584 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
4585 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
4587 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
4588 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
4589 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
4590 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
4591 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
4592 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
4593 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
4594 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
4595 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
4596 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
4597 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
4598 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
4599 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
4600 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
4603 * CHV pipe B sprite CSC
4605 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
4606 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
4607 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
4609 #define _MMIO_CHV_SPCSC(plane_id, reg) \
4610 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
4612 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
4613 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
4614 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
4615 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
4616 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
4617 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
4618 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
4620 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
4621 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
4622 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
4623 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
4624 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
4625 #define SPCSC_C1_MASK REG_GENMASK(30, 16)
4626 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
4627 #define SPCSC_C0_MASK REG_GENMASK(14, 0)
4628 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
4630 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
4631 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
4632 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
4633 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
4634 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
4635 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
4636 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
4638 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
4639 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
4640 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
4641 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
4642 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
4643 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
4644 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
4646 /* Skylake plane registers */
4648 #define _PLANE_CTL_1_A 0x70180
4649 #define _PLANE_CTL_2_A 0x70280
4650 #define _PLANE_CTL_3_A 0x70380
4651 #define PLANE_CTL_ENABLE REG_BIT(31)
4652 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
4653 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
4654 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
4655 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4657 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
4658 * expanded to include bit 23 as well. However, the shift-24 based values
4659 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
4661 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
4662 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
4663 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
4664 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
4665 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
4666 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
4667 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
4668 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
4669 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
4670 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
4671 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
4672 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
4673 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
4674 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
4675 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
4676 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
4677 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
4678 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
4679 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
4680 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
4681 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
4682 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
4683 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
4684 #define PLANE_CTL_ORDER_RGBX REG_BIT(20)
4685 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
4686 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
4687 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
4688 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
4689 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
4690 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
4691 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
4692 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
4693 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
4694 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
4695 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
4696 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
4697 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
4698 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
4699 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
4700 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
4701 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
4702 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
4703 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
4704 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
4705 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
4706 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
4707 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
4708 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
4709 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
4710 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
4711 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
4712 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
4713 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
4714 #define _PLANE_STRIDE_1_A 0x70188
4715 #define _PLANE_STRIDE_2_A 0x70288
4716 #define _PLANE_STRIDE_3_A 0x70388
4717 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
4718 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
4719 #define _PLANE_POS_1_A 0x7018c
4720 #define _PLANE_POS_2_A 0x7028c
4721 #define _PLANE_POS_3_A 0x7038c
4722 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
4723 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
4724 #define PLANE_POS_X_MASK REG_GENMASK(15, 0)
4725 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
4726 #define _PLANE_SIZE_1_A 0x70190
4727 #define _PLANE_SIZE_2_A 0x70290
4728 #define _PLANE_SIZE_3_A 0x70390
4729 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
4730 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
4731 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
4732 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
4733 #define _PLANE_SURF_1_A 0x7019c
4734 #define _PLANE_SURF_2_A 0x7029c
4735 #define _PLANE_SURF_3_A 0x7039c
4736 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
4737 #define PLANE_SURF_DECRYPT REG_BIT(2)
4738 #define _PLANE_OFFSET_1_A 0x701a4
4739 #define _PLANE_OFFSET_2_A 0x702a4
4740 #define _PLANE_OFFSET_3_A 0x703a4
4741 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
4742 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
4743 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
4744 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
4745 #define _PLANE_KEYVAL_1_A 0x70194
4746 #define _PLANE_KEYVAL_2_A 0x70294
4747 #define _PLANE_KEYMSK_1_A 0x70198
4748 #define _PLANE_KEYMSK_2_A 0x70298
4749 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
4750 #define _PLANE_KEYMAX_1_A 0x701a0
4751 #define _PLANE_KEYMAX_2_A 0x702a0
4752 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
4753 #define _PLANE_CC_VAL_1_A 0x701b4
4754 #define _PLANE_CC_VAL_2_A 0x702b4
4755 #define _PLANE_AUX_DIST_1_A 0x701c0
4756 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
4757 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
4758 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
4759 #define _PLANE_AUX_DIST_2_A 0x702c0
4760 #define _PLANE_AUX_OFFSET_1_A 0x701c4
4761 #define _PLANE_AUX_OFFSET_2_A 0x702c4
4762 #define _PLANE_CUS_CTL_1_A 0x701c8
4763 #define _PLANE_CUS_CTL_2_A 0x702c8
4764 #define PLANE_CUS_ENABLE REG_BIT(31)
4765 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
4766 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
4767 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
4768 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
4769 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
4770 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
4771 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
4772 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
4773 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
4774 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
4775 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
4776 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
4777 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
4778 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
4779 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
4780 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
4781 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
4782 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
4783 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
4784 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4785 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
4786 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
4787 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
4788 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
4789 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
4790 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
4791 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
4792 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
4793 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
4794 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
4795 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
4796 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
4797 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
4798 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
4799 #define _PLANE_BUF_CFG_1_A 0x7027c
4800 #define _PLANE_BUF_CFG_2_A 0x7037c
4801 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
4802 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
4804 #define _PLANE_CC_VAL_1_B 0x711b4
4805 #define _PLANE_CC_VAL_2_B 0x712b4
4806 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
4807 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
4808 #define PLANE_CC_VAL(pipe, plane, dw) \
4809 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
4811 /* Input CSC Register Definitions */
4812 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
4813 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
4815 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
4816 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
4818 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
4819 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
4820 _PLANE_INPUT_CSC_RY_GY_1_B)
4821 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
4822 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
4823 _PLANE_INPUT_CSC_RY_GY_2_B)
4825 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
4826 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
4827 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
4829 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
4830 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
4832 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
4833 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
4835 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
4836 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
4837 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
4838 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
4839 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
4840 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
4841 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
4842 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
4843 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
4845 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
4846 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
4848 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
4849 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
4851 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
4852 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
4853 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
4854 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
4855 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
4856 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
4857 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
4858 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
4859 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
4861 #define _PLANE_CTL_1_B 0x71180
4862 #define _PLANE_CTL_2_B 0x71280
4863 #define _PLANE_CTL_3_B 0x71380
4864 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
4865 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
4866 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
4867 #define PLANE_CTL(pipe, plane) \
4868 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
4870 #define _PLANE_STRIDE_1_B 0x71188
4871 #define _PLANE_STRIDE_2_B 0x71288
4872 #define _PLANE_STRIDE_3_B 0x71388
4873 #define _PLANE_STRIDE_1(pipe) \
4874 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
4875 #define _PLANE_STRIDE_2(pipe) \
4876 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
4877 #define _PLANE_STRIDE_3(pipe) \
4878 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
4879 #define PLANE_STRIDE(pipe, plane) \
4880 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
4882 #define _PLANE_POS_1_B 0x7118c
4883 #define _PLANE_POS_2_B 0x7128c
4884 #define _PLANE_POS_3_B 0x7138c
4885 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
4886 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
4887 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
4888 #define PLANE_POS(pipe, plane) \
4889 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
4891 #define _PLANE_SIZE_1_B 0x71190
4892 #define _PLANE_SIZE_2_B 0x71290
4893 #define _PLANE_SIZE_3_B 0x71390
4894 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
4895 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
4896 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
4897 #define PLANE_SIZE(pipe, plane) \
4898 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
4900 #define _PLANE_SURF_1_B 0x7119c
4901 #define _PLANE_SURF_2_B 0x7129c
4902 #define _PLANE_SURF_3_B 0x7139c
4903 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
4904 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
4905 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
4906 #define PLANE_SURF(pipe, plane) \
4907 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
4909 #define _PLANE_OFFSET_1_B 0x711a4
4910 #define _PLANE_OFFSET_2_B 0x712a4
4911 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
4912 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
4913 #define PLANE_OFFSET(pipe, plane) \
4914 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
4916 #define _PLANE_KEYVAL_1_B 0x71194
4917 #define _PLANE_KEYVAL_2_B 0x71294
4918 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
4919 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
4920 #define PLANE_KEYVAL(pipe, plane) \
4921 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
4923 #define _PLANE_KEYMSK_1_B 0x71198
4924 #define _PLANE_KEYMSK_2_B 0x71298
4925 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
4926 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
4927 #define PLANE_KEYMSK(pipe, plane) \
4928 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
4930 #define _PLANE_KEYMAX_1_B 0x711a0
4931 #define _PLANE_KEYMAX_2_B 0x712a0
4932 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
4933 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
4934 #define PLANE_KEYMAX(pipe, plane) \
4935 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
4937 #define _PLANE_BUF_CFG_1_B 0x7127c
4938 #define _PLANE_BUF_CFG_2_B 0x7137c
4939 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
4940 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
4941 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
4942 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
4943 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
4944 #define _PLANE_BUF_CFG_1(pipe) \
4945 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
4946 #define _PLANE_BUF_CFG_2(pipe) \
4947 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
4948 #define PLANE_BUF_CFG(pipe, plane) \
4949 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
4951 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
4952 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
4953 #define _PLANE_NV12_BUF_CFG_1(pipe) \
4954 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
4955 #define _PLANE_NV12_BUF_CFG_2(pipe) \
4956 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
4957 #define PLANE_NV12_BUF_CFG(pipe, plane) \
4958 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
4960 #define _PLANE_AUX_DIST_1_B 0x711c0
4961 #define _PLANE_AUX_DIST_2_B 0x712c0
4962 #define _PLANE_AUX_DIST_1(pipe) \
4963 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
4964 #define _PLANE_AUX_DIST_2(pipe) \
4965 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
4966 #define PLANE_AUX_DIST(pipe, plane) \
4967 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
4969 #define _PLANE_AUX_OFFSET_1_B 0x711c4
4970 #define _PLANE_AUX_OFFSET_2_B 0x712c4
4971 #define _PLANE_AUX_OFFSET_1(pipe) \
4972 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
4973 #define _PLANE_AUX_OFFSET_2(pipe) \
4974 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
4975 #define PLANE_AUX_OFFSET(pipe, plane) \
4976 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
4978 #define _PLANE_CUS_CTL_1_B 0x711c8
4979 #define _PLANE_CUS_CTL_2_B 0x712c8
4980 #define _PLANE_CUS_CTL_1(pipe) \
4981 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
4982 #define _PLANE_CUS_CTL_2(pipe) \
4983 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
4984 #define PLANE_CUS_CTL(pipe, plane) \
4985 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
4987 #define _PLANE_COLOR_CTL_1_B 0x711CC
4988 #define _PLANE_COLOR_CTL_2_B 0x712CC
4989 #define _PLANE_COLOR_CTL_3_B 0x713CC
4990 #define _PLANE_COLOR_CTL_1(pipe) \
4991 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
4992 #define _PLANE_COLOR_CTL_2(pipe) \
4993 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
4994 #define PLANE_COLOR_CTL(pipe, plane) \
4995 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
4997 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890
4998 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
4999 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
5000 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0
5001 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920
5002 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940
5003 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960
5004 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
5005 #define _SEL_FETCH_PLANE_BASE_1_B 0x71890
5007 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
5008 _SEL_FETCH_PLANE_BASE_1_A, \
5009 _SEL_FETCH_PLANE_BASE_2_A, \
5010 _SEL_FETCH_PLANE_BASE_3_A, \
5011 _SEL_FETCH_PLANE_BASE_4_A, \
5012 _SEL_FETCH_PLANE_BASE_5_A, \
5013 _SEL_FETCH_PLANE_BASE_6_A, \
5014 _SEL_FETCH_PLANE_BASE_7_A, \
5015 _SEL_FETCH_PLANE_BASE_CUR_A)
5016 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
5017 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
5018 _SEL_FETCH_PLANE_BASE_1_A + \
5019 _SEL_FETCH_PLANE_BASE_A(plane))
5021 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890
5022 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
5023 _SEL_FETCH_PLANE_CTL_1_A - \
5024 _SEL_FETCH_PLANE_BASE_1_A)
5025 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
5027 #define _SEL_FETCH_PLANE_POS_1_A 0x70894
5028 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
5029 _SEL_FETCH_PLANE_POS_1_A - \
5030 _SEL_FETCH_PLANE_BASE_1_A)
5032 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
5033 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
5034 _SEL_FETCH_PLANE_SIZE_1_A - \
5035 _SEL_FETCH_PLANE_BASE_1_A)
5037 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
5038 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
5039 _SEL_FETCH_PLANE_OFFSET_1_A - \
5040 _SEL_FETCH_PLANE_BASE_1_A)
5042 /* SKL new cursor registers */
5043 #define _CUR_BUF_CFG_A 0x7017c
5044 #define _CUR_BUF_CFG_B 0x7117c
5045 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
5048 #define VGACNTRL _MMIO(0x71400)
5049 # define VGA_DISP_DISABLE (1 << 31)
5050 # define VGA_2X_MODE (1 << 30)
5051 # define VGA_PIPE_B_SELECT (1 << 29)
5053 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
5057 #define CPU_VGACNTRL _MMIO(0x41000)
5059 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
5060 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
5061 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
5062 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
5063 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
5064 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
5065 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
5066 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
5067 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
5068 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
5069 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
5071 /* refresh rate hardware control */
5072 #define RR_HW_CTL _MMIO(0x45300)
5073 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
5074 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
5076 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
5077 #define FDI_PLL_FB_CLOCK_MASK 0xff
5078 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
5079 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
5080 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
5081 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
5082 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
5084 #define PCH_3DCGDIS0 _MMIO(0x46020)
5085 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
5086 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
5088 #define PCH_3DCGDIS1 _MMIO(0x46024)
5089 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
5091 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
5092 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
5093 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
5094 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
5097 #define _PIPEA_DATA_M1 0x60030
5098 #define _PIPEA_DATA_N1 0x60034
5099 #define _PIPEA_DATA_M2 0x60038
5100 #define _PIPEA_DATA_N2 0x6003c
5101 #define _PIPEA_LINK_M1 0x60040
5102 #define _PIPEA_LINK_N1 0x60044
5103 #define _PIPEA_LINK_M2 0x60048
5104 #define _PIPEA_LINK_N2 0x6004c
5106 /* PIPEB timing regs are same start from 0x61000 */
5108 #define _PIPEB_DATA_M1 0x61030
5109 #define _PIPEB_DATA_N1 0x61034
5110 #define _PIPEB_DATA_M2 0x61038
5111 #define _PIPEB_DATA_N2 0x6103c
5112 #define _PIPEB_LINK_M1 0x61040
5113 #define _PIPEB_LINK_N1 0x61044
5114 #define _PIPEB_LINK_M2 0x61048
5115 #define _PIPEB_LINK_N2 0x6104c
5117 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
5118 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
5119 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
5120 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
5121 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
5122 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
5123 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
5124 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
5126 /* CPU panel fitter */
5127 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5128 #define _PFA_CTL_1 0x68080
5129 #define _PFB_CTL_1 0x68880
5130 #define PF_ENABLE (1 << 31)
5131 #define PF_PIPE_SEL_MASK_IVB (3 << 29)
5132 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
5133 #define PF_FILTER_MASK (3 << 23)
5134 #define PF_FILTER_PROGRAMMED (0 << 23)
5135 #define PF_FILTER_MED_3x3 (1 << 23)
5136 #define PF_FILTER_EDGE_ENHANCE (2 << 23)
5137 #define PF_FILTER_EDGE_SOFTEN (3 << 23)
5138 #define _PFA_WIN_SZ 0x68074
5139 #define _PFB_WIN_SZ 0x68874
5140 #define _PFA_WIN_POS 0x68070
5141 #define _PFB_WIN_POS 0x68870
5142 #define _PFA_VSCALE 0x68084
5143 #define _PFB_VSCALE 0x68884
5144 #define _PFA_HSCALE 0x68090
5145 #define _PFB_HSCALE 0x68890
5147 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5148 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5149 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5150 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5151 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
5153 #define _PSA_CTL 0x68180
5154 #define _PSB_CTL 0x68980
5155 #define PS_ENABLE (1 << 31)
5156 #define _PSA_WIN_SZ 0x68174
5157 #define _PSB_WIN_SZ 0x68974
5158 #define _PSA_WIN_POS 0x68170
5159 #define _PSB_WIN_POS 0x68970
5161 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
5162 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5163 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5168 #define _PS_1A_CTRL 0x68180
5169 #define _PS_2A_CTRL 0x68280
5170 #define _PS_1B_CTRL 0x68980
5171 #define _PS_2B_CTRL 0x68A80
5172 #define _PS_1C_CTRL 0x69180
5173 #define PS_SCALER_EN (1 << 31)
5174 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
5175 #define SKL_PS_SCALER_MODE_DYN (0 << 28)
5176 #define SKL_PS_SCALER_MODE_HQ (1 << 28)
5177 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
5178 #define PS_SCALER_MODE_PLANAR (1 << 29)
5179 #define PS_SCALER_MODE_NORMAL (0 << 29)
5180 #define PS_PLANE_SEL_MASK (7 << 25)
5181 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
5182 #define PS_FILTER_MASK (3 << 23)
5183 #define PS_FILTER_MEDIUM (0 << 23)
5184 #define PS_FILTER_PROGRAMMED (1 << 23)
5185 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
5186 #define PS_FILTER_BILINEAR (3 << 23)
5187 #define PS_VERT3TAP (1 << 21)
5188 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5189 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
5190 #define PS_PWRUP_PROGRESS (1 << 17)
5191 #define PS_V_FILTER_BYPASS (1 << 8)
5192 #define PS_VADAPT_EN (1 << 7)
5193 #define PS_VADAPT_MODE_MASK (3 << 5)
5194 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5195 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
5196 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
5197 #define PS_PLANE_Y_SEL_MASK (7 << 5)
5198 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
5199 #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
5200 #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
5201 #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
5202 #define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1)
5204 #define _PS_PWR_GATE_1A 0x68160
5205 #define _PS_PWR_GATE_2A 0x68260
5206 #define _PS_PWR_GATE_1B 0x68960
5207 #define _PS_PWR_GATE_2B 0x68A60
5208 #define _PS_PWR_GATE_1C 0x69160
5209 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
5210 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
5211 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
5212 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
5213 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
5214 #define PS_PWR_GATE_SLPEN_8 0
5215 #define PS_PWR_GATE_SLPEN_16 1
5216 #define PS_PWR_GATE_SLPEN_24 2
5217 #define PS_PWR_GATE_SLPEN_32 3
5219 #define _PS_WIN_POS_1A 0x68170
5220 #define _PS_WIN_POS_2A 0x68270
5221 #define _PS_WIN_POS_1B 0x68970
5222 #define _PS_WIN_POS_2B 0x68A70
5223 #define _PS_WIN_POS_1C 0x69170
5225 #define _PS_WIN_SZ_1A 0x68174
5226 #define _PS_WIN_SZ_2A 0x68274
5227 #define _PS_WIN_SZ_1B 0x68974
5228 #define _PS_WIN_SZ_2B 0x68A74
5229 #define _PS_WIN_SZ_1C 0x69174
5231 #define _PS_VSCALE_1A 0x68184
5232 #define _PS_VSCALE_2A 0x68284
5233 #define _PS_VSCALE_1B 0x68984
5234 #define _PS_VSCALE_2B 0x68A84
5235 #define _PS_VSCALE_1C 0x69184
5237 #define _PS_HSCALE_1A 0x68190
5238 #define _PS_HSCALE_2A 0x68290
5239 #define _PS_HSCALE_1B 0x68990
5240 #define _PS_HSCALE_2B 0x68A90
5241 #define _PS_HSCALE_1C 0x69190
5243 #define _PS_VPHASE_1A 0x68188
5244 #define _PS_VPHASE_2A 0x68288
5245 #define _PS_VPHASE_1B 0x68988
5246 #define _PS_VPHASE_2B 0x68A88
5247 #define _PS_VPHASE_1C 0x69188
5248 #define PS_Y_PHASE(x) ((x) << 16)
5249 #define PS_UV_RGB_PHASE(x) ((x) << 0)
5250 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
5251 #define PS_PHASE_TRIP (1 << 0)
5253 #define _PS_HPHASE_1A 0x68194
5254 #define _PS_HPHASE_2A 0x68294
5255 #define _PS_HPHASE_1B 0x68994
5256 #define _PS_HPHASE_2B 0x68A94
5257 #define _PS_HPHASE_1C 0x69194
5259 #define _PS_ECC_STAT_1A 0x681D0
5260 #define _PS_ECC_STAT_2A 0x682D0
5261 #define _PS_ECC_STAT_1B 0x689D0
5262 #define _PS_ECC_STAT_2B 0x68AD0
5263 #define _PS_ECC_STAT_1C 0x691D0
5265 #define _PS_COEF_SET0_INDEX_1A 0x68198
5266 #define _PS_COEF_SET0_INDEX_2A 0x68298
5267 #define _PS_COEF_SET0_INDEX_1B 0x68998
5268 #define _PS_COEF_SET0_INDEX_2B 0x68A98
5269 #define PS_COEE_INDEX_AUTO_INC (1 << 10)
5271 #define _PS_COEF_SET0_DATA_1A 0x6819C
5272 #define _PS_COEF_SET0_DATA_2A 0x6829C
5273 #define _PS_COEF_SET0_DATA_1B 0x6899C
5274 #define _PS_COEF_SET0_DATA_2B 0x68A9C
5276 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
5277 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
5278 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
5279 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
5280 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
5281 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5282 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
5283 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
5284 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5285 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
5286 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
5287 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
5288 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
5289 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
5290 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
5291 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
5292 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
5293 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
5294 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
5295 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
5296 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
5297 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
5298 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
5299 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
5300 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
5301 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
5302 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
5303 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
5304 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
5305 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
5306 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
5308 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
5309 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
5310 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
5311 /* legacy palette */
5312 #define _LGC_PALETTE_A 0x4a000
5313 #define _LGC_PALETTE_B 0x4a800
5314 /* see PALETTE_* for the bits */
5315 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
5317 /* ilk/snb precision palette */
5318 #define _PREC_PALETTE_A 0x4b000
5319 #define _PREC_PALETTE_B 0x4c000
5321 #define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20)
5322 #define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10)
5323 #define PREC_PALETTE_10_BLUE_MASK REG_GENMASK(9, 0)
5324 /* 12.4 interpolated mode ldw */
5325 #define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24)
5326 #define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14)
5327 #define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4)
5328 /* 12.4 interpolated mode udw */
5329 #define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20)
5330 #define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10)
5331 #define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0)
5332 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
5334 #define _PREC_PIPEAGCMAX 0x4d000
5335 #define _PREC_PIPEBGCMAX 0x4d010
5336 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
5338 #define _GAMMA_MODE_A 0x4a480
5339 #define _GAMMA_MODE_B 0x4ac80
5340 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5341 #define PRE_CSC_GAMMA_ENABLE (1 << 31)
5342 #define POST_CSC_GAMMA_ENABLE (1 << 30)
5343 #define GAMMA_MODE_MODE_MASK (3 << 0)
5344 #define GAMMA_MODE_MODE_8BIT (0 << 0)
5345 #define GAMMA_MODE_MODE_10BIT (1 << 0)
5346 #define GAMMA_MODE_MODE_12BIT (2 << 0)
5347 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
5348 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
5350 /* Display Internal Timeout Register */
5351 #define RM_TIMEOUT _MMIO(0x42060)
5352 #define MMIO_TIMEOUT_US(us) ((us) << 0)
5355 #define DE_MASTER_IRQ_CONTROL (1 << 31)
5356 #define DE_SPRITEB_FLIP_DONE (1 << 29)
5357 #define DE_SPRITEA_FLIP_DONE (1 << 28)
5358 #define DE_PLANEB_FLIP_DONE (1 << 27)
5359 #define DE_PLANEA_FLIP_DONE (1 << 26)
5360 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
5361 #define DE_PCU_EVENT (1 << 25)
5362 #define DE_GTT_FAULT (1 << 24)
5363 #define DE_POISON (1 << 23)
5364 #define DE_PERFORM_COUNTER (1 << 22)
5365 #define DE_PCH_EVENT (1 << 21)
5366 #define DE_AUX_CHANNEL_A (1 << 20)
5367 #define DE_DP_A_HOTPLUG (1 << 19)
5368 #define DE_GSE (1 << 18)
5369 #define DE_PIPEB_VBLANK (1 << 15)
5370 #define DE_PIPEB_EVEN_FIELD (1 << 14)
5371 #define DE_PIPEB_ODD_FIELD (1 << 13)
5372 #define DE_PIPEB_LINE_COMPARE (1 << 12)
5373 #define DE_PIPEB_VSYNC (1 << 11)
5374 #define DE_PIPEB_CRC_DONE (1 << 10)
5375 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
5376 #define DE_PIPEA_VBLANK (1 << 7)
5377 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
5378 #define DE_PIPEA_EVEN_FIELD (1 << 6)
5379 #define DE_PIPEA_ODD_FIELD (1 << 5)
5380 #define DE_PIPEA_LINE_COMPARE (1 << 4)
5381 #define DE_PIPEA_VSYNC (1 << 3)
5382 #define DE_PIPEA_CRC_DONE (1 << 2)
5383 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
5384 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
5385 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
5387 /* More Ivybridge lolz */
5388 #define DE_ERR_INT_IVB (1 << 30)
5389 #define DE_GSE_IVB (1 << 29)
5390 #define DE_PCH_EVENT_IVB (1 << 28)
5391 #define DE_DP_A_HOTPLUG_IVB (1 << 27)
5392 #define DE_AUX_CHANNEL_A_IVB (1 << 26)
5393 #define DE_EDP_PSR_INT_HSW (1 << 19)
5394 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
5395 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
5396 #define DE_PIPEC_VBLANK_IVB (1 << 10)
5397 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
5398 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
5399 #define DE_PIPEB_VBLANK_IVB (1 << 5)
5400 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
5401 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
5402 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
5403 #define DE_PIPEA_VBLANK_IVB (1 << 0)
5404 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
5406 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
5407 #define MASTER_INTERRUPT_ENABLE (1 << 31)
5409 #define DEISR _MMIO(0x44000)
5410 #define DEIMR _MMIO(0x44004)
5411 #define DEIIR _MMIO(0x44008)
5412 #define DEIER _MMIO(0x4400c)
5414 #define GTISR _MMIO(0x44010)
5415 #define GTIMR _MMIO(0x44014)
5416 #define GTIIR _MMIO(0x44018)
5417 #define GTIER _MMIO(0x4401c)
5419 #define GEN8_MASTER_IRQ _MMIO(0x44200)
5420 #define GEN8_MASTER_IRQ_CONTROL (1 << 31)
5421 #define GEN8_PCU_IRQ (1 << 30)
5422 #define GEN8_DE_PCH_IRQ (1 << 23)
5423 #define GEN8_DE_MISC_IRQ (1 << 22)
5424 #define GEN8_DE_PORT_IRQ (1 << 20)
5425 #define GEN8_DE_PIPE_C_IRQ (1 << 18)
5426 #define GEN8_DE_PIPE_B_IRQ (1 << 17)
5427 #define GEN8_DE_PIPE_A_IRQ (1 << 16)
5428 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
5429 #define GEN8_GT_VECS_IRQ (1 << 6)
5430 #define GEN8_GT_GUC_IRQ (1 << 5)
5431 #define GEN8_GT_PM_IRQ (1 << 4)
5432 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
5433 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
5434 #define GEN8_GT_BCS_IRQ (1 << 1)
5435 #define GEN8_GT_RCS_IRQ (1 << 0)
5437 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
5439 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
5440 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
5441 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
5442 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
5444 #define GEN8_RCS_IRQ_SHIFT 0
5445 #define GEN8_BCS_IRQ_SHIFT 16
5446 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
5447 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
5448 #define GEN8_VECS_IRQ_SHIFT 0
5449 #define GEN8_WD_IRQ_SHIFT 16
5451 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
5452 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
5453 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
5454 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
5455 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
5456 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5457 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
5458 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22)
5459 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21)
5460 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
5461 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
5462 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
5463 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
5464 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
5465 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
5466 #define GEN8_PIPE_VSYNC (1 << 1)
5467 #define GEN8_PIPE_VBLANK (1 << 0)
5468 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
5469 #define GEN11_PIPE_PLANE7_FAULT (1 << 22)
5470 #define GEN11_PIPE_PLANE6_FAULT (1 << 21)
5471 #define GEN11_PIPE_PLANE5_FAULT (1 << 20)
5472 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
5473 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
5474 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
5475 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
5476 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
5477 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
5478 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
5479 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
5480 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
5481 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5482 (GEN8_PIPE_CURSOR_FAULT | \
5483 GEN8_PIPE_SPRITE_FAULT | \
5484 GEN8_PIPE_PRIMARY_FAULT)
5485 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5486 (GEN9_PIPE_CURSOR_FAULT | \
5487 GEN9_PIPE_PLANE4_FAULT | \
5488 GEN9_PIPE_PLANE3_FAULT | \
5489 GEN9_PIPE_PLANE2_FAULT | \
5490 GEN9_PIPE_PLANE1_FAULT)
5491 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
5492 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
5493 GEN11_PIPE_PLANE7_FAULT | \
5494 GEN11_PIPE_PLANE6_FAULT | \
5495 GEN11_PIPE_PLANE5_FAULT)
5496 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
5497 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
5498 GEN11_PIPE_PLANE5_FAULT)
5500 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
5501 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
5503 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
5504 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
5505 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
5506 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
5507 #define DSI1_NON_TE (1 << 31)
5508 #define DSI0_NON_TE (1 << 30)
5509 #define ICL_AUX_CHANNEL_E (1 << 29)
5510 #define ICL_AUX_CHANNEL_F (1 << 28)
5511 #define GEN9_AUX_CHANNEL_D (1 << 27)
5512 #define GEN9_AUX_CHANNEL_C (1 << 26)
5513 #define GEN9_AUX_CHANNEL_B (1 << 25)
5514 #define DSI1_TE (1 << 24)
5515 #define DSI0_TE (1 << 23)
5516 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
5517 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
5518 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
5519 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
5520 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
5521 #define BXT_DE_PORT_GMBUS (1 << 1)
5522 #define GEN8_AUX_CHANNEL_A (1 << 0)
5523 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
5524 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
5525 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
5526 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
5527 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
5528 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
5529 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
5530 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
5531 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
5532 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
5533 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
5535 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
5536 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
5537 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
5538 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
5539 #define GEN8_DE_MISC_GSE (1 << 27)
5540 #define GEN8_DE_EDP_PSR (1 << 19)
5542 #define GEN8_PCU_ISR _MMIO(0x444e0)
5543 #define GEN8_PCU_IMR _MMIO(0x444e4)
5544 #define GEN8_PCU_IIR _MMIO(0x444e8)
5545 #define GEN8_PCU_IER _MMIO(0x444ec)
5547 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
5548 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
5549 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
5550 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
5551 #define GEN11_GU_MISC_GSE (1 << 27)
5553 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
5554 #define GEN11_MASTER_IRQ (1 << 31)
5555 #define GEN11_PCU_IRQ (1 << 30)
5556 #define GEN11_GU_MISC_IRQ (1 << 29)
5557 #define GEN11_DISPLAY_IRQ (1 << 16)
5558 #define GEN11_GT_DW_IRQ(x) (1 << (x))
5559 #define GEN11_GT_DW1_IRQ (1 << 1)
5560 #define GEN11_GT_DW0_IRQ (1 << 0)
5562 #define DG1_MSTR_TILE_INTR _MMIO(0x190008)
5563 #define DG1_MSTR_IRQ REG_BIT(31)
5564 #define DG1_MSTR_TILE(t) REG_BIT(t)
5566 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
5567 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
5568 #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
5569 #define GEN11_DE_PCH_IRQ (1 << 23)
5570 #define GEN11_DE_MISC_IRQ (1 << 22)
5571 #define GEN11_DE_HPD_IRQ (1 << 21)
5572 #define GEN11_DE_PORT_IRQ (1 << 20)
5573 #define GEN11_DE_PIPE_C (1 << 18)
5574 #define GEN11_DE_PIPE_B (1 << 17)
5575 #define GEN11_DE_PIPE_A (1 << 16)
5577 #define GEN11_DE_HPD_ISR _MMIO(0x44470)
5578 #define GEN11_DE_HPD_IMR _MMIO(0x44474)
5579 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
5580 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
5581 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
5582 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
5583 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
5584 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
5585 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
5586 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
5587 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
5588 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
5589 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
5590 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
5591 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
5592 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
5593 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
5594 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
5596 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
5597 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
5598 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
5599 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
5600 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
5601 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
5603 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
5604 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
5605 #define ILK_ELPIN_409_SELECT (1 << 25)
5606 #define ILK_DPARB_GATE (1 << 22)
5607 #define ILK_VSDPFD_FULL (1 << 21)
5608 #define FUSE_STRAP _MMIO(0x42014)
5609 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
5610 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
5611 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
5612 #define IVB_PIPE_C_DISABLE (1 << 28)
5613 #define ILK_HDCP_DISABLE (1 << 25)
5614 #define ILK_eDP_A_DISABLE (1 << 24)
5615 #define HSW_CDCLK_LIMIT (1 << 24)
5616 #define ILK_DESKTOP (1 << 23)
5617 #define HSW_CPU_SSC_ENABLE (1 << 21)
5619 #define FUSE_STRAP3 _MMIO(0x42020)
5620 #define HSW_REF_CLK_SELECT (1 << 1)
5622 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
5623 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
5624 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
5625 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
5626 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
5627 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
5629 #define IVB_CHICKEN3 _MMIO(0x4200c)
5630 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
5631 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
5633 #define CHICKEN_PAR1_1 _MMIO(0x42080)
5634 #define IGNORE_KVMR_PIPE_A REG_BIT(23)
5635 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
5636 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
5637 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
5638 #define DPA_MASK_VBLANK_SRD (1 << 15)
5639 #define FORCE_ARB_IDLE_PLANES (1 << 14)
5640 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
5641 #define IGNORE_PSR2_HW_TRACKING (1 << 1)
5643 #define CHICKEN_PAR2_1 _MMIO(0x42090)
5644 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
5646 #define CHICKEN_MISC_2 _MMIO(0x42084)
5647 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
5648 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
5649 #define GLK_CL2_PWR_DOWN (1 << 12)
5650 #define GLK_CL1_PWR_DOWN (1 << 11)
5651 #define GLK_CL0_PWR_DOWN (1 << 10)
5653 #define CHICKEN_MISC_4 _MMIO(0x4208c)
5654 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
5655 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
5656 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
5658 #define _CHICKEN_PIPESL_1_A 0x420b0
5659 #define _CHICKEN_PIPESL_1_B 0x420b4
5660 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
5661 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
5662 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
5663 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
5664 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
5665 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
5666 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
5667 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
5668 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
5669 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
5670 #define HSW_FBCQ_DIS (1 << 22)
5671 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
5672 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
5673 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
5674 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
5675 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
5676 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
5677 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5679 #define _CHICKEN_TRANS_A 0x420c0
5680 #define _CHICKEN_TRANS_B 0x420c4
5681 #define _CHICKEN_TRANS_C 0x420c8
5682 #define _CHICKEN_TRANS_EDP 0x420cc
5683 #define _CHICKEN_TRANS_D 0x420d8
5684 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
5685 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
5686 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
5687 [TRANSCODER_B] = _CHICKEN_TRANS_B, \
5688 [TRANSCODER_C] = _CHICKEN_TRANS_C, \
5689 [TRANSCODER_D] = _CHICKEN_TRANS_D))
5691 #define _MTL_CHICKEN_TRANS_A 0x604e0
5692 #define _MTL_CHICKEN_TRANS_B 0x614e0
5693 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
5694 _MTL_CHICKEN_TRANS_A, \
5695 _MTL_CHICKEN_TRANS_B)
5697 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
5698 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
5699 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
5700 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
5701 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
5702 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
5703 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
5704 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
5705 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
5706 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
5707 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
5709 #define DISP_ARB_CTL _MMIO(0x45000)
5710 #define DISP_FBC_MEMORY_WAKE (1 << 31)
5711 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13)
5712 #define DISP_FBC_WM_DIS (1 << 15)
5713 #define DISP_ARB_CTL2 _MMIO(0x45004)
5714 #define DISP_DATA_PARTITION_5_6 (1 << 6)
5715 #define DISP_IPC_ENABLE (1 << 3)
5718 * The below are numbered starting from "S1" on gen11/gen12, but starting
5719 * with display 13, the bspec switches to a 0-based numbering scheme
5720 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
5721 * We'll just use the 0-based numbering here for all platforms since it's the
5722 * way things will be named by the hardware team going forward, plus it's more
5723 * consistent with how most of the rest of our registers are named.
5725 #define _DBUF_CTL_S0 0x45008
5726 #define _DBUF_CTL_S1 0x44FE8
5727 #define _DBUF_CTL_S2 0x44300
5728 #define _DBUF_CTL_S3 0x44304
5729 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
5734 #define DBUF_POWER_REQUEST REG_BIT(31)
5735 #define DBUF_POWER_STATE REG_BIT(30)
5736 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
5737 #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
5738 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
5739 #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
5741 #define GEN7_MSG_CTL _MMIO(0x45010)
5742 #define WAIT_FOR_PCH_RESET_ACK (1 << 1)
5743 #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
5745 #define _BW_BUDDY0_CTL 0x45130
5746 #define _BW_BUDDY1_CTL 0x45140
5747 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
5750 #define BW_BUDDY_DISABLE REG_BIT(31)
5751 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
5752 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
5754 #define _BW_BUDDY0_PAGE_MASK 0x45134
5755 #define _BW_BUDDY1_PAGE_MASK 0x45144
5756 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
5757 _BW_BUDDY0_PAGE_MASK, \
5758 _BW_BUDDY1_PAGE_MASK))
5760 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
5761 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
5762 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
5764 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
5765 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
5766 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
5767 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
5768 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
5769 #define ICL_DELAY_PMRSP REG_BIT(22)
5770 #define DISABLE_FLR_SRC REG_BIT(15)
5771 #define MASK_WAKEMEM REG_BIT(13)
5772 #define DDI_CLOCK_REG_ACCESS REG_BIT(7)
5774 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
5775 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
5776 #define DCPR_MASK_LPMODE REG_BIT(26)
5777 #define DCPR_SEND_RESP_IMM REG_BIT(25)
5778 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
5780 #define SKL_DFSM _MMIO(0x51000)
5781 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
5782 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
5783 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
5784 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
5785 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
5786 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
5787 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
5788 #define ICL_DFSM_DMC_DISABLE (1 << 23)
5789 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
5790 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
5791 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
5792 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
5793 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
5795 #define SKL_DSSM _MMIO(0x51004)
5796 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
5797 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
5798 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
5799 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
5801 #define GMD_ID_DISPLAY _MMIO(0x510a0)
5802 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
5803 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
5804 #define GMD_ID_STEP REG_GENMASK(5, 0)
5807 #define _PIPEA_CHICKEN 0x70038
5808 #define _PIPEB_CHICKEN 0x71038
5809 #define _PIPEC_CHICKEN 0x72038
5810 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
5812 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
5813 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
5814 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
5815 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
5816 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
5820 #define PCH_DISPLAY_BASE 0xc0000u
5822 /* south display engine interrupt: IBX */
5823 #define SDE_AUDIO_POWER_D (1 << 27)
5824 #define SDE_AUDIO_POWER_C (1 << 26)
5825 #define SDE_AUDIO_POWER_B (1 << 25)
5826 #define SDE_AUDIO_POWER_SHIFT (25)
5827 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
5828 #define SDE_GMBUS (1 << 24)
5829 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
5830 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
5831 #define SDE_AUDIO_HDCP_MASK (3 << 22)
5832 #define SDE_AUDIO_TRANSB (1 << 21)
5833 #define SDE_AUDIO_TRANSA (1 << 20)
5834 #define SDE_AUDIO_TRANS_MASK (3 << 20)
5835 #define SDE_POISON (1 << 19)
5837 #define SDE_FDI_RXB (1 << 17)
5838 #define SDE_FDI_RXA (1 << 16)
5839 #define SDE_FDI_MASK (3 << 16)
5840 #define SDE_AUXD (1 << 15)
5841 #define SDE_AUXC (1 << 14)
5842 #define SDE_AUXB (1 << 13)
5843 #define SDE_AUX_MASK (7 << 13)
5845 #define SDE_CRT_HOTPLUG (1 << 11)
5846 #define SDE_PORTD_HOTPLUG (1 << 10)
5847 #define SDE_PORTC_HOTPLUG (1 << 9)
5848 #define SDE_PORTB_HOTPLUG (1 << 8)
5849 #define SDE_SDVOB_HOTPLUG (1 << 6)
5850 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
5851 SDE_SDVOB_HOTPLUG | \
5852 SDE_PORTB_HOTPLUG | \
5853 SDE_PORTC_HOTPLUG | \
5855 #define SDE_TRANSB_CRC_DONE (1 << 5)
5856 #define SDE_TRANSB_CRC_ERR (1 << 4)
5857 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
5858 #define SDE_TRANSA_CRC_DONE (1 << 2)
5859 #define SDE_TRANSA_CRC_ERR (1 << 1)
5860 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
5861 #define SDE_TRANS_MASK (0x3f)
5863 /* south display engine interrupt: CPT - CNP */
5864 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
5865 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
5866 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
5867 #define SDE_AUDIO_POWER_SHIFT_CPT 29
5868 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
5869 #define SDE_AUXD_CPT (1 << 27)
5870 #define SDE_AUXC_CPT (1 << 26)
5871 #define SDE_AUXB_CPT (1 << 25)
5872 #define SDE_AUX_MASK_CPT (7 << 25)
5873 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
5874 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
5875 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
5876 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
5877 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
5878 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
5879 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
5880 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
5881 SDE_SDVOB_HOTPLUG_CPT | \
5882 SDE_PORTD_HOTPLUG_CPT | \
5883 SDE_PORTC_HOTPLUG_CPT | \
5884 SDE_PORTB_HOTPLUG_CPT)
5885 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
5886 SDE_PORTD_HOTPLUG_CPT | \
5887 SDE_PORTC_HOTPLUG_CPT | \
5888 SDE_PORTB_HOTPLUG_CPT | \
5889 SDE_PORTA_HOTPLUG_SPT)
5890 #define SDE_GMBUS_CPT (1 << 17)
5891 #define SDE_ERROR_CPT (1 << 16)
5892 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
5893 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
5894 #define SDE_FDI_RXC_CPT (1 << 8)
5895 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
5896 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
5897 #define SDE_FDI_RXB_CPT (1 << 4)
5898 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
5899 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
5900 #define SDE_FDI_RXA_CPT (1 << 0)
5901 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
5902 SDE_AUDIO_CP_REQ_B_CPT | \
5903 SDE_AUDIO_CP_REQ_A_CPT)
5904 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
5905 SDE_AUDIO_CP_CHG_B_CPT | \
5906 SDE_AUDIO_CP_CHG_A_CPT)
5907 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
5911 /* south display engine interrupt: ICP/TGP */
5912 #define SDE_GMBUS_ICP (1 << 23)
5913 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
5914 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
5915 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
5916 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
5917 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
5918 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
5919 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
5920 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
5921 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
5922 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
5923 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
5924 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
5925 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
5927 #define SDEISR _MMIO(0xc4000)
5928 #define SDEIMR _MMIO(0xc4004)
5929 #define SDEIIR _MMIO(0xc4008)
5930 #define SDEIER _MMIO(0xc400c)
5932 #define SERR_INT _MMIO(0xc4040)
5933 #define SERR_INT_POISON (1 << 31)
5934 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
5936 /* digital port hotplug */
5937 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
5938 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
5939 #define BXT_DDIA_HPD_INVERT (1 << 27)
5940 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
5941 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
5942 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
5943 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
5944 #define PORTD_HOTPLUG_ENABLE (1 << 20)
5945 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
5946 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
5947 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
5948 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
5949 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
5950 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
5951 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
5952 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
5953 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
5954 #define PORTC_HOTPLUG_ENABLE (1 << 12)
5955 #define BXT_DDIC_HPD_INVERT (1 << 11)
5956 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
5957 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
5958 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
5959 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
5960 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
5961 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
5962 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
5963 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
5964 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
5965 #define PORTB_HOTPLUG_ENABLE (1 << 4)
5966 #define BXT_DDIB_HPD_INVERT (1 << 3)
5967 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
5968 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
5969 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
5970 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
5971 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
5972 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
5973 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
5974 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
5975 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
5976 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
5977 BXT_DDIB_HPD_INVERT | \
5978 BXT_DDIC_HPD_INVERT)
5980 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
5981 #define PORTE_HOTPLUG_ENABLE (1 << 4)
5982 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
5983 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
5984 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
5985 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
5987 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
5988 * functionality covered in PCH_PORT_HOTPLUG is split into
5989 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
5992 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
5993 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
5994 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
5995 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
5996 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
5997 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
5998 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
6000 #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
6001 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
6002 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
6003 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
6005 #define SHPD_FILTER_CNT _MMIO(0xc4038)
6006 #define SHPD_FILTER_CNT_500_ADJ 0x001D9
6008 #define _PCH_DPLL_A 0xc6014
6009 #define _PCH_DPLL_B 0xc6018
6010 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
6012 #define _PCH_FPA0 0xc6040
6013 #define FP_CB_TUNE (0x3 << 22)
6014 #define _PCH_FPA1 0xc6044
6015 #define _PCH_FPB0 0xc6048
6016 #define _PCH_FPB1 0xc604c
6017 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
6018 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
6020 #define PCH_DPLL_TEST _MMIO(0xc606c)
6022 #define PCH_DREF_CONTROL _MMIO(0xC6200)
6023 #define DREF_CONTROL_MASK 0x7fc3
6024 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
6025 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
6026 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
6027 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
6028 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
6029 #define DREF_SSC_SOURCE_ENABLE (2 << 11)
6030 #define DREF_SSC_SOURCE_MASK (3 << 11)
6031 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
6032 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
6033 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
6034 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
6035 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
6036 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
6037 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
6038 #define DREF_SSC4_DOWNSPREAD (0 << 6)
6039 #define DREF_SSC4_CENTERSPREAD (1 << 6)
6040 #define DREF_SSC1_DISABLE (0 << 1)
6041 #define DREF_SSC1_ENABLE (1 << 1)
6042 #define DREF_SSC4_DISABLE (0)
6043 #define DREF_SSC4_ENABLE (1)
6045 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
6046 #define FDL_TP1_TIMER_SHIFT 12
6047 #define FDL_TP1_TIMER_MASK (3 << 12)
6048 #define FDL_TP2_TIMER_SHIFT 10
6049 #define FDL_TP2_TIMER_MASK (3 << 10)
6050 #define RAWCLK_FREQ_MASK 0x3ff
6051 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
6052 #define CNP_RAWCLK_DIV(div) ((div) << 16)
6053 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
6054 #define CNP_RAWCLK_DEN(den) ((den) << 26)
6055 #define ICP_RAWCLK_NUM(num) ((num) << 11)
6057 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
6059 #define PCH_SSC4_PARMS _MMIO(0xc6210)
6060 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
6062 #define PCH_DPLL_SEL _MMIO(0xc7000)
6063 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
6064 #define TRANS_DPLLA_SEL(pipe) 0
6065 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
6069 #define _PCH_TRANS_HTOTAL_A 0xe0000
6070 #define TRANS_HTOTAL_SHIFT 16
6071 #define TRANS_HACTIVE_SHIFT 0
6072 #define _PCH_TRANS_HBLANK_A 0xe0004
6073 #define TRANS_HBLANK_END_SHIFT 16
6074 #define TRANS_HBLANK_START_SHIFT 0
6075 #define _PCH_TRANS_HSYNC_A 0xe0008
6076 #define TRANS_HSYNC_END_SHIFT 16
6077 #define TRANS_HSYNC_START_SHIFT 0
6078 #define _PCH_TRANS_VTOTAL_A 0xe000c
6079 #define TRANS_VTOTAL_SHIFT 16
6080 #define TRANS_VACTIVE_SHIFT 0
6081 #define _PCH_TRANS_VBLANK_A 0xe0010
6082 #define TRANS_VBLANK_END_SHIFT 16
6083 #define TRANS_VBLANK_START_SHIFT 0
6084 #define _PCH_TRANS_VSYNC_A 0xe0014
6085 #define TRANS_VSYNC_END_SHIFT 16
6086 #define TRANS_VSYNC_START_SHIFT 0
6087 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
6089 #define _PCH_TRANSA_DATA_M1 0xe0030
6090 #define _PCH_TRANSA_DATA_N1 0xe0034
6091 #define _PCH_TRANSA_DATA_M2 0xe0038
6092 #define _PCH_TRANSA_DATA_N2 0xe003c
6093 #define _PCH_TRANSA_LINK_M1 0xe0040
6094 #define _PCH_TRANSA_LINK_N1 0xe0044
6095 #define _PCH_TRANSA_LINK_M2 0xe0048
6096 #define _PCH_TRANSA_LINK_N2 0xe004c
6098 /* Per-transcoder DIP controls (PCH) */
6099 #define _VIDEO_DIP_CTL_A 0xe0200
6100 #define _VIDEO_DIP_DATA_A 0xe0208
6101 #define _VIDEO_DIP_GCP_A 0xe0210
6102 #define GCP_COLOR_INDICATION (1 << 2)
6103 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
6104 #define GCP_AV_MUTE (1 << 0)
6106 #define _VIDEO_DIP_CTL_B 0xe1200
6107 #define _VIDEO_DIP_DATA_B 0xe1208
6108 #define _VIDEO_DIP_GCP_B 0xe1210
6110 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6111 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6112 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
6114 /* Per-transcoder DIP controls (VLV) */
6115 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6116 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6117 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
6119 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6120 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6121 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
6123 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6124 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6125 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
6127 #define VLV_TVIDEO_DIP_CTL(pipe) \
6128 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
6129 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
6130 #define VLV_TVIDEO_DIP_DATA(pipe) \
6131 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
6132 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
6133 #define VLV_TVIDEO_DIP_GCP(pipe) \
6134 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
6135 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
6137 /* Haswell DIP controls */
6139 #define _HSW_VIDEO_DIP_CTL_A 0x60200
6140 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
6141 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
6142 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
6143 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
6144 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
6145 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
6146 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
6147 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
6148 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
6149 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
6150 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
6151 #define _HSW_VIDEO_DIP_GCP_A 0x60210
6153 #define _HSW_VIDEO_DIP_CTL_B 0x61200
6154 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
6155 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
6156 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
6157 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
6158 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
6159 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
6160 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
6161 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
6162 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
6163 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
6164 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
6165 #define _HSW_VIDEO_DIP_GCP_B 0x61210
6167 /* Icelake PPS_DATA and _ECC DIP Registers.
6168 * These are available for transcoders B,C and eDP.
6169 * Adding the _A so as to reuse the _MMIO_TRANS2
6170 * definition, with which it offsets to the right location.
6173 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
6174 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
6175 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
6176 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
6178 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
6179 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
6180 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
6181 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
6182 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
6183 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
6184 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
6185 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
6186 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
6187 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
6189 #define _HSW_STEREO_3D_CTL_A 0x70020
6190 #define S3D_ENABLE (1 << 31)
6191 #define _HSW_STEREO_3D_CTL_B 0x71020
6193 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
6195 #define _PCH_TRANS_HTOTAL_B 0xe1000
6196 #define _PCH_TRANS_HBLANK_B 0xe1004
6197 #define _PCH_TRANS_HSYNC_B 0xe1008
6198 #define _PCH_TRANS_VTOTAL_B 0xe100c
6199 #define _PCH_TRANS_VBLANK_B 0xe1010
6200 #define _PCH_TRANS_VSYNC_B 0xe1014
6201 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
6203 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6204 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6205 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6206 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6207 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6208 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6209 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
6211 #define _PCH_TRANSB_DATA_M1 0xe1030
6212 #define _PCH_TRANSB_DATA_N1 0xe1034
6213 #define _PCH_TRANSB_DATA_M2 0xe1038
6214 #define _PCH_TRANSB_DATA_N2 0xe103c
6215 #define _PCH_TRANSB_LINK_M1 0xe1040
6216 #define _PCH_TRANSB_LINK_N1 0xe1044
6217 #define _PCH_TRANSB_LINK_M2 0xe1048
6218 #define _PCH_TRANSB_LINK_N2 0xe104c
6220 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6221 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6222 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6223 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6224 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6225 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6226 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6227 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
6229 #define _PCH_TRANSACONF 0xf0008
6230 #define _PCH_TRANSBCONF 0xf1008
6231 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6232 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
6233 #define TRANS_ENABLE REG_BIT(31)
6234 #define TRANS_STATE_ENABLE REG_BIT(30)
6235 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
6236 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
6237 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
6238 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
6239 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
6240 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
6241 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
6242 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
6243 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
6244 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
6245 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
6246 #define _TRANSA_CHICKEN1 0xf0060
6247 #define _TRANSB_CHICKEN1 0xf1060
6248 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
6249 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10)
6250 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)
6251 #define _TRANSA_CHICKEN2 0xf0064
6252 #define _TRANSB_CHICKEN2 0xf1064
6253 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
6254 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
6255 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
6256 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
6257 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
6258 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
6259 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
6261 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
6262 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
6263 #define FDIA_PHASE_SYNC_SHIFT_EN 18
6264 #define INVERT_DDID_HPD (1 << 18)
6265 #define INVERT_DDIC_HPD (1 << 17)
6266 #define INVERT_DDIB_HPD (1 << 16)
6267 #define INVERT_DDIA_HPD (1 << 15)
6268 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6269 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6270 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
6271 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
6272 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
6273 #define SBCLK_RUN_REFCLK_DIS (1 << 7)
6274 #define SPT_PWM_GRANULARITY (1 << 0)
6275 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
6276 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
6277 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
6278 #define LPT_PWM_GRANULARITY (1 << 5)
6279 #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
6281 #define _FDI_RXA_CHICKEN 0xc200c
6282 #define _FDI_RXB_CHICKEN 0xc2010
6283 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
6284 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
6285 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
6287 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
6288 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
6289 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
6290 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
6291 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
6292 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
6293 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
6294 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
6297 #define _FDI_TXA_CTL 0x60100
6298 #define _FDI_TXB_CTL 0x61100
6299 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
6300 #define FDI_TX_DISABLE (0 << 31)
6301 #define FDI_TX_ENABLE (1 << 31)
6302 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
6303 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
6304 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
6305 #define FDI_LINK_TRAIN_NONE (3 << 28)
6306 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
6307 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
6308 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
6309 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
6310 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
6311 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
6312 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
6313 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
6314 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6315 SNB has different settings. */
6316 /* SNB A-stepping */
6317 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
6318 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
6319 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
6320 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
6321 /* SNB B-stepping */
6322 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
6323 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
6324 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
6325 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
6326 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
6327 #define FDI_DP_PORT_WIDTH_SHIFT 19
6328 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
6329 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
6330 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
6331 /* Ironlake: hardwired to 1 */
6332 #define FDI_TX_PLL_ENABLE (1 << 14)
6334 /* Ivybridge has different bits for lolz */
6335 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
6336 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
6337 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
6338 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
6340 /* both Tx and Rx */
6341 #define FDI_COMPOSITE_SYNC (1 << 11)
6342 #define FDI_LINK_TRAIN_AUTO (1 << 10)
6343 #define FDI_SCRAMBLING_ENABLE (0 << 7)
6344 #define FDI_SCRAMBLING_DISABLE (1 << 7)
6346 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
6347 #define _FDI_RXA_CTL 0xf000c
6348 #define _FDI_RXB_CTL 0xf100c
6349 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
6350 #define FDI_RX_ENABLE (1 << 31)
6351 /* train, dp width same as FDI_TX */
6352 #define FDI_FS_ERRC_ENABLE (1 << 27)
6353 #define FDI_FE_ERRC_ENABLE (1 << 26)
6354 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
6355 #define FDI_8BPC (0 << 16)
6356 #define FDI_10BPC (1 << 16)
6357 #define FDI_6BPC (2 << 16)
6358 #define FDI_12BPC (3 << 16)
6359 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
6360 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
6361 #define FDI_RX_PLL_ENABLE (1 << 13)
6362 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
6363 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
6364 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
6365 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
6366 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
6367 #define FDI_PCDCLK (1 << 4)
6369 #define FDI_AUTO_TRAINING (1 << 10)
6370 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
6371 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
6372 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
6373 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
6374 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
6376 #define _FDI_RXA_MISC 0xf0010
6377 #define _FDI_RXB_MISC 0xf1010
6378 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
6379 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
6380 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
6381 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
6382 #define FDI_RX_TP1_TO_TP2_48 (2 << 20)
6383 #define FDI_RX_TP1_TO_TP2_64 (3 << 20)
6384 #define FDI_RX_FDI_DELAY_90 (0x90 << 0)
6385 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
6387 #define _FDI_RXA_TUSIZE1 0xf0030
6388 #define _FDI_RXA_TUSIZE2 0xf0038
6389 #define _FDI_RXB_TUSIZE1 0xf1030
6390 #define _FDI_RXB_TUSIZE2 0xf1038
6391 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6392 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
6394 /* FDI_RX interrupt register format */
6395 #define FDI_RX_INTER_LANE_ALIGN (1 << 10)
6396 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */
6397 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */
6398 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
6399 #define FDI_RX_FS_CODE_ERR (1 << 6)
6400 #define FDI_RX_FE_CODE_ERR (1 << 5)
6401 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
6402 #define FDI_RX_HDCP_LINK_FAIL (1 << 3)
6403 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
6404 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
6405 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
6407 #define _FDI_RXA_IIR 0xf0014
6408 #define _FDI_RXA_IMR 0xf0018
6409 #define _FDI_RXB_IIR 0xf1014
6410 #define _FDI_RXB_IMR 0xf1018
6411 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6412 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
6414 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
6415 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
6417 #define PCH_LVDS _MMIO(0xe1180)
6418 #define LVDS_DETECTED (1 << 1)
6420 #define _PCH_DP_B 0xe4100
6421 #define PCH_DP_B _MMIO(_PCH_DP_B)
6422 #define _PCH_DPB_AUX_CH_CTL 0xe4110
6423 #define _PCH_DPB_AUX_CH_DATA1 0xe4114
6424 #define _PCH_DPB_AUX_CH_DATA2 0xe4118
6425 #define _PCH_DPB_AUX_CH_DATA3 0xe411c
6426 #define _PCH_DPB_AUX_CH_DATA4 0xe4120
6427 #define _PCH_DPB_AUX_CH_DATA5 0xe4124
6429 #define _PCH_DP_C 0xe4200
6430 #define PCH_DP_C _MMIO(_PCH_DP_C)
6431 #define _PCH_DPC_AUX_CH_CTL 0xe4210
6432 #define _PCH_DPC_AUX_CH_DATA1 0xe4214
6433 #define _PCH_DPC_AUX_CH_DATA2 0xe4218
6434 #define _PCH_DPC_AUX_CH_DATA3 0xe421c
6435 #define _PCH_DPC_AUX_CH_DATA4 0xe4220
6436 #define _PCH_DPC_AUX_CH_DATA5 0xe4224
6438 #define _PCH_DP_D 0xe4300
6439 #define PCH_DP_D _MMIO(_PCH_DP_D)
6440 #define _PCH_DPD_AUX_CH_CTL 0xe4310
6441 #define _PCH_DPD_AUX_CH_DATA1 0xe4314
6442 #define _PCH_DPD_AUX_CH_DATA2 0xe4318
6443 #define _PCH_DPD_AUX_CH_DATA3 0xe431c
6444 #define _PCH_DPD_AUX_CH_DATA4 0xe4320
6445 #define _PCH_DPD_AUX_CH_DATA5 0xe4324
6447 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
6448 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
6451 #define _TRANS_DP_CTL_A 0xe0300
6452 #define _TRANS_DP_CTL_B 0xe1300
6453 #define _TRANS_DP_CTL_C 0xe2300
6454 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
6455 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
6456 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
6457 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
6458 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
6459 #define TRANS_DP_AUDIO_ONLY REG_BIT(26)
6460 #define TRANS_DP_ENH_FRAMING REG_BIT(18)
6461 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
6462 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
6463 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
6464 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
6465 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
6466 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
6467 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
6469 #define _TRANS_DP2_CTL_A 0x600a0
6470 #define _TRANS_DP2_CTL_B 0x610a0
6471 #define _TRANS_DP2_CTL_C 0x620a0
6472 #define _TRANS_DP2_CTL_D 0x630a0
6473 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
6474 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
6475 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
6476 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
6478 #define _TRANS_DP2_VFREQHIGH_A 0x600a4
6479 #define _TRANS_DP2_VFREQHIGH_B 0x610a4
6480 #define _TRANS_DP2_VFREQHIGH_C 0x620a4
6481 #define _TRANS_DP2_VFREQHIGH_D 0x630a4
6482 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
6483 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
6484 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
6486 #define _TRANS_DP2_VFREQLOW_A 0x600a8
6487 #define _TRANS_DP2_VFREQLOW_B 0x610a8
6488 #define _TRANS_DP2_VFREQLOW_C 0x620a8
6489 #define _TRANS_DP2_VFREQLOW_D 0x630a8
6490 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
6492 /* SNB eDP training params */
6493 /* SNB A-stepping */
6494 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
6495 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
6496 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
6497 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
6498 /* SNB B-stepping */
6499 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
6500 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
6501 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
6502 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
6503 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
6504 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
6507 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
6508 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
6509 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
6510 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
6511 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
6512 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
6513 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
6516 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
6517 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
6518 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
6519 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
6520 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
6522 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
6524 #define VLV_PMWGICZ _MMIO(0x1300a4)
6526 #define HSW_EDRAM_CAP _MMIO(0x120010)
6527 #define EDRAM_ENABLED 0x1
6528 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
6529 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
6530 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
6532 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
6533 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
6534 #define PIXEL_OVERLAP_CNT_SHIFT 30
6536 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
6537 #define GEN6_PCODE_READY (1 << 31)
6538 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
6539 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
6540 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
6541 #define GEN6_PCODE_ERROR_MASK 0xFF
6542 #define GEN6_PCODE_SUCCESS 0x0
6543 #define GEN6_PCODE_ILLEGAL_CMD 0x1
6544 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
6545 #define GEN6_PCODE_TIMEOUT 0x3
6546 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
6547 #define GEN7_PCODE_TIMEOUT 0x2
6548 #define GEN7_PCODE_ILLEGAL_DATA 0x3
6549 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
6550 #define GEN11_PCODE_LOCKED 0x6
6551 #define GEN11_PCODE_REJECTED 0x11
6552 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
6553 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
6554 #define GEN6_PCODE_READ_RC6VIDS 0x5
6555 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
6556 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
6557 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
6558 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
6559 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
6560 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
6561 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
6562 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
6563 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
6564 #define SKL_PCODE_CDCLK_CONTROL 0x7
6565 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
6566 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
6567 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
6568 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
6569 #define GEN6_READ_OC_PARAMS 0xc
6570 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
6571 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
6572 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
6573 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
6574 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
6575 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
6576 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
6577 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
6578 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
6579 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
6580 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
6581 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
6582 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
6583 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
6584 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
6585 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
6586 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
6587 #define GEN6_PCODE_READ_D_COMP 0x10
6588 #define GEN6_PCODE_WRITE_D_COMP 0x11
6589 #define ICL_PCODE_EXIT_TCCOLD 0x12
6590 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
6591 #define DISPLAY_IPS_CONTROL 0x19
6592 #define TGL_PCODE_TCCOLD 0x26
6593 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
6594 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
6595 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
6596 /* See also IPS_CTL */
6597 #define IPS_PCODE_CONTROL (1 << 30)
6598 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
6599 #define GEN9_PCODE_SAGV_CONTROL 0x21
6600 #define GEN9_SAGV_DISABLE 0x0
6601 #define GEN9_SAGV_IS_DISABLED 0x1
6602 #define GEN9_SAGV_ENABLE 0x3
6603 #define DG1_PCODE_STATUS 0x7E
6604 #define DG1_UNCORE_GET_INIT_STATUS 0x0
6605 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
6606 #define PCODE_POWER_SETUP 0x7C
6607 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
6608 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
6609 #define POWER_SETUP_I1_WATTS REG_BIT(31)
6610 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
6611 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
6612 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
6613 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
6614 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
6615 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
6616 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
6617 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
6618 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */
6619 #define PCODE_MBOX_DOMAIN_NONE 0x0
6620 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
6622 /* Wa_14017210380: mtl */
6623 #define PCODE_MBOX_GT_STATE 0x50
6624 /* sub-commands (param1) */
6625 #define PCODE_MBOX_GT_STATE_MEDIA_BUSY 0x1
6626 #define PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY 0x2
6628 #define PCODE_MBOX_GT_STATE_DOMAIN_MEDIA 0x1
6630 #define GEN6_PCODE_DATA _MMIO(0x138128)
6631 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
6632 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
6633 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
6636 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
6637 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
6638 #define GEN7_PARITY_ERROR_VALID (1 << 13)
6639 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
6640 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
6641 #define GEN7_PARITY_ERROR_ROW(reg) \
6642 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
6643 #define GEN7_PARITY_ERROR_BANK(reg) \
6644 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
6645 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
6646 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
6647 #define GEN7_L3CDERRST1_ENABLE (1 << 7)
6649 /* These are the 4 32-bit write offset registers for each stream
6650 * output buffer. It determines the offset from the
6651 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
6653 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
6656 * HSW - ICL power wells
6658 * Platforms have up to 3 power well control register sets, each set
6659 * controlling up to 16 power wells via a request/status HW flag tuple:
6660 * - main (HSW_PWR_WELL_CTL[1-4])
6661 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
6662 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
6663 * Each control register set consists of up to 4 registers used by different
6664 * sources that can request a power well to be enabled:
6665 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
6666 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
6667 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
6668 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
6670 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
6671 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
6672 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
6673 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
6674 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
6675 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
6677 /* HSW/BDW power well */
6678 #define HSW_PW_CTL_IDX_GLOBAL 15
6680 /* SKL/BXT/GLK power wells */
6681 #define SKL_PW_CTL_IDX_PW_2 15
6682 #define SKL_PW_CTL_IDX_PW_1 14
6683 #define GLK_PW_CTL_IDX_AUX_C 10
6684 #define GLK_PW_CTL_IDX_AUX_B 9
6685 #define GLK_PW_CTL_IDX_AUX_A 8
6686 #define SKL_PW_CTL_IDX_DDI_D 4
6687 #define SKL_PW_CTL_IDX_DDI_C 3
6688 #define SKL_PW_CTL_IDX_DDI_B 2
6689 #define SKL_PW_CTL_IDX_DDI_A_E 1
6690 #define GLK_PW_CTL_IDX_DDI_A 1
6691 #define SKL_PW_CTL_IDX_MISC_IO 0
6693 /* ICL/TGL - power wells */
6694 #define TGL_PW_CTL_IDX_PW_5 4
6695 #define ICL_PW_CTL_IDX_PW_4 3
6696 #define ICL_PW_CTL_IDX_PW_3 2
6697 #define ICL_PW_CTL_IDX_PW_2 1
6698 #define ICL_PW_CTL_IDX_PW_1 0
6700 /* XE_LPD - power wells */
6701 #define XELPD_PW_CTL_IDX_PW_D 8
6702 #define XELPD_PW_CTL_IDX_PW_C 7
6703 #define XELPD_PW_CTL_IDX_PW_B 6
6704 #define XELPD_PW_CTL_IDX_PW_A 5
6706 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
6707 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
6708 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
6709 #define TGL_PW_CTL_IDX_AUX_TBT6 14
6710 #define TGL_PW_CTL_IDX_AUX_TBT5 13
6711 #define TGL_PW_CTL_IDX_AUX_TBT4 12
6712 #define ICL_PW_CTL_IDX_AUX_TBT4 11
6713 #define TGL_PW_CTL_IDX_AUX_TBT3 11
6714 #define ICL_PW_CTL_IDX_AUX_TBT3 10
6715 #define TGL_PW_CTL_IDX_AUX_TBT2 10
6716 #define ICL_PW_CTL_IDX_AUX_TBT2 9
6717 #define TGL_PW_CTL_IDX_AUX_TBT1 9
6718 #define ICL_PW_CTL_IDX_AUX_TBT1 8
6719 #define TGL_PW_CTL_IDX_AUX_TC6 8
6720 #define XELPD_PW_CTL_IDX_AUX_E 8
6721 #define TGL_PW_CTL_IDX_AUX_TC5 7
6722 #define XELPD_PW_CTL_IDX_AUX_D 7
6723 #define TGL_PW_CTL_IDX_AUX_TC4 6
6724 #define ICL_PW_CTL_IDX_AUX_F 5
6725 #define TGL_PW_CTL_IDX_AUX_TC3 5
6726 #define ICL_PW_CTL_IDX_AUX_E 4
6727 #define TGL_PW_CTL_IDX_AUX_TC2 4
6728 #define ICL_PW_CTL_IDX_AUX_D 3
6729 #define TGL_PW_CTL_IDX_AUX_TC1 3
6730 #define ICL_PW_CTL_IDX_AUX_C 2
6731 #define ICL_PW_CTL_IDX_AUX_B 1
6732 #define ICL_PW_CTL_IDX_AUX_A 0
6734 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
6735 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
6736 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
6737 #define XELPD_PW_CTL_IDX_DDI_E 8
6738 #define TGL_PW_CTL_IDX_DDI_TC6 8
6739 #define XELPD_PW_CTL_IDX_DDI_D 7
6740 #define TGL_PW_CTL_IDX_DDI_TC5 7
6741 #define TGL_PW_CTL_IDX_DDI_TC4 6
6742 #define ICL_PW_CTL_IDX_DDI_F 5
6743 #define TGL_PW_CTL_IDX_DDI_TC3 5
6744 #define ICL_PW_CTL_IDX_DDI_E 4
6745 #define TGL_PW_CTL_IDX_DDI_TC2 4
6746 #define ICL_PW_CTL_IDX_DDI_D 3
6747 #define TGL_PW_CTL_IDX_DDI_TC1 3
6748 #define ICL_PW_CTL_IDX_DDI_C 2
6749 #define ICL_PW_CTL_IDX_DDI_B 1
6750 #define ICL_PW_CTL_IDX_DDI_A 0
6752 /* HSW - power well misc debug registers */
6753 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
6754 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
6755 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
6756 #define HSW_PWR_WELL_FORCE_ON (1 << 19)
6757 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
6759 /* SKL Fuse Status */
6760 enum skl_power_gate {
6768 #define SKL_FUSE_STATUS _MMIO(0x42000)
6769 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
6771 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
6772 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
6774 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
6775 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
6777 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
6778 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
6780 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
6781 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
6782 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
6784 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
6785 #define _ICL_AUX_ANAOVRD1_A 0x162398
6786 #define _ICL_AUX_ANAOVRD1_B 0x6C398
6787 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
6788 _ICL_AUX_ANAOVRD1_A, \
6789 _ICL_AUX_ANAOVRD1_B))
6790 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
6791 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
6793 /* Per-pipe DDI Function Control */
6794 #define _TRANS_DDI_FUNC_CTL_A 0x60400
6795 #define _TRANS_DDI_FUNC_CTL_B 0x61400
6796 #define _TRANS_DDI_FUNC_CTL_C 0x62400
6797 #define _TRANS_DDI_FUNC_CTL_D 0x63400
6798 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
6799 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
6800 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
6801 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
6803 #define TRANS_DDI_FUNC_ENABLE (1 << 31)
6804 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
6805 #define TRANS_DDI_PORT_SHIFT 28
6806 #define TGL_TRANS_DDI_PORT_SHIFT 27
6807 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
6808 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
6809 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
6810 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
6811 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
6812 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
6813 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
6814 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
6815 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
6816 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
6817 #define TRANS_DDI_BPC_MASK (7 << 20)
6818 #define TRANS_DDI_BPC_8 (0 << 20)
6819 #define TRANS_DDI_BPC_10 (1 << 20)
6820 #define TRANS_DDI_BPC_6 (2 << 20)
6821 #define TRANS_DDI_BPC_12 (3 << 20)
6822 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
6823 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
6824 #define TRANS_DDI_PVSYNC (1 << 17)
6825 #define TRANS_DDI_PHSYNC (1 << 16)
6826 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
6827 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
6828 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
6829 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
6830 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
6831 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
6832 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
6833 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
6834 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
6835 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
6836 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
6837 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
6838 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
6839 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
6840 #define TRANS_DDI_HDCP_SELECT REG_BIT(5)
6841 #define TRANS_DDI_BFI_ENABLE (1 << 4)
6842 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
6843 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
6844 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
6845 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
6846 | TRANS_DDI_HDMI_SCRAMBLING)
6848 #define _TRANS_DDI_FUNC_CTL2_A 0x60404
6849 #define _TRANS_DDI_FUNC_CTL2_B 0x61404
6850 #define _TRANS_DDI_FUNC_CTL2_C 0x62404
6851 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
6852 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
6853 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
6854 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
6855 #define PORT_SYNC_MODE_ENABLE REG_BIT(4)
6856 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
6857 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
6859 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
6860 #define DISABLE_DPT_CLK_GATING REG_BIT(1)
6862 /* DisplayPort Transport Control */
6863 #define _DP_TP_CTL_A 0x64040
6864 #define _DP_TP_CTL_B 0x64140
6865 #define _TGL_DP_TP_CTL_A 0x60540
6866 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
6867 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
6868 #define DP_TP_CTL_ENABLE (1 << 31)
6869 #define DP_TP_CTL_FEC_ENABLE (1 << 30)
6870 #define DP_TP_CTL_MODE_SST (0 << 27)
6871 #define DP_TP_CTL_MODE_MST (1 << 27)
6872 #define DP_TP_CTL_FORCE_ACT (1 << 25)
6873 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
6874 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
6875 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
6876 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
6877 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
6878 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
6879 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
6880 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
6881 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
6882 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
6884 /* DisplayPort Transport Status */
6885 #define _DP_TP_STATUS_A 0x64044
6886 #define _DP_TP_STATUS_B 0x64144
6887 #define _TGL_DP_TP_STATUS_A 0x60544
6888 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
6889 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
6890 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
6891 #define DP_TP_STATUS_IDLE_DONE (1 << 25)
6892 #define DP_TP_STATUS_ACT_SENT (1 << 24)
6893 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
6894 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
6895 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
6896 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
6897 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
6899 /* DDI Buffer Control */
6900 #define _DDI_BUF_CTL_A 0x64000
6901 #define _DDI_BUF_CTL_B 0x64100
6902 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
6903 #define DDI_BUF_CTL_ENABLE (1 << 31)
6904 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
6905 #define DDI_BUF_EMP_MASK (0xf << 24)
6906 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
6907 #define DDI_BUF_PORT_REVERSAL (1 << 16)
6908 #define DDI_BUF_IS_IDLE (1 << 7)
6909 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
6910 #define DDI_A_4_LANES (1 << 4)
6911 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
6912 #define DDI_PORT_WIDTH_MASK (7 << 1)
6913 #define DDI_PORT_WIDTH_SHIFT 1
6914 #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
6916 /* DDI Buffer Translations */
6917 #define _DDI_BUF_TRANS_A 0x64E00
6918 #define _DDI_BUF_TRANS_B 0x64E60
6919 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
6920 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
6921 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
6923 /* DDI DP Compliance Control */
6924 #define _DDI_DP_COMP_CTL_A 0x605F0
6925 #define _DDI_DP_COMP_CTL_B 0x615F0
6926 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
6927 #define DDI_DP_COMP_CTL_ENABLE (1 << 31)
6928 #define DDI_DP_COMP_CTL_D10_2 (0 << 28)
6929 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
6930 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
6931 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
6932 #define DDI_DP_COMP_CTL_HBR2 (4 << 28)
6933 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
6934 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
6936 /* DDI DP Compliance Pattern */
6937 #define _DDI_DP_COMP_PAT_A 0x605F4
6938 #define _DDI_DP_COMP_PAT_B 0x615F4
6939 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
6941 /* Sideband Interface (SBI) is programmed indirectly, via
6942 * SBI_ADDR, which contains the register offset; and SBI_DATA,
6943 * which contains the payload */
6944 #define SBI_ADDR _MMIO(0xC6000)
6945 #define SBI_DATA _MMIO(0xC6004)
6946 #define SBI_CTL_STAT _MMIO(0xC6008)
6947 #define SBI_CTL_DEST_ICLK (0x0 << 16)
6948 #define SBI_CTL_DEST_MPHY (0x1 << 16)
6949 #define SBI_CTL_OP_IORD (0x2 << 8)
6950 #define SBI_CTL_OP_IOWR (0x3 << 8)
6951 #define SBI_CTL_OP_CRRD (0x6 << 8)
6952 #define SBI_CTL_OP_CRWR (0x7 << 8)
6953 #define SBI_RESPONSE_FAIL (0x1 << 1)
6954 #define SBI_RESPONSE_SUCCESS (0x0 << 1)
6955 #define SBI_BUSY (0x1 << 0)
6956 #define SBI_READY (0x0 << 0)
6959 #define SBI_SSCDIVINTPHASE 0x0200
6960 #define SBI_SSCDIVINTPHASE6 0x0600
6961 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
6962 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
6963 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
6964 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
6965 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
6966 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
6967 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
6968 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
6969 #define SBI_SSCDITHPHASE 0x0204
6970 #define SBI_SSCCTL 0x020c
6971 #define SBI_SSCCTL6 0x060C
6972 #define SBI_SSCCTL_PATHALT (1 << 3)
6973 #define SBI_SSCCTL_DISABLE (1 << 0)
6974 #define SBI_SSCAUXDIV6 0x0610
6975 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
6976 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
6977 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
6978 #define SBI_DBUFF0 0x2a00
6979 #define SBI_GEN0 0x1f00
6980 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
6982 /* LPT PIXCLK_GATE */
6983 #define PIXCLK_GATE _MMIO(0xC6020)
6984 #define PIXCLK_GATE_UNGATE (1 << 0)
6985 #define PIXCLK_GATE_GATE (0 << 0)
6988 #define SPLL_CTL _MMIO(0x46020)
6989 #define SPLL_PLL_ENABLE (1 << 31)
6990 #define SPLL_REF_BCLK (0 << 28)
6991 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
6992 #define SPLL_REF_NON_SSC_HSW (2 << 28)
6993 #define SPLL_REF_PCH_SSC_BDW (2 << 28)
6994 #define SPLL_REF_LCPLL (3 << 28)
6995 #define SPLL_REF_MASK (3 << 28)
6996 #define SPLL_FREQ_810MHz (0 << 26)
6997 #define SPLL_FREQ_1350MHz (1 << 26)
6998 #define SPLL_FREQ_2700MHz (2 << 26)
6999 #define SPLL_FREQ_MASK (3 << 26)
7002 #define _WRPLL_CTL1 0x46040
7003 #define _WRPLL_CTL2 0x46060
7004 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
7005 #define WRPLL_PLL_ENABLE (1 << 31)
7006 #define WRPLL_REF_BCLK (0 << 28)
7007 #define WRPLL_REF_PCH_SSC (1 << 28)
7008 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
7009 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
7010 #define WRPLL_REF_LCPLL (3 << 28)
7011 #define WRPLL_REF_MASK (3 << 28)
7012 /* WRPLL divider programming */
7013 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
7014 #define WRPLL_DIVIDER_REF_MASK (0xff)
7015 #define WRPLL_DIVIDER_POST(x) ((x) << 8)
7016 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
7017 #define WRPLL_DIVIDER_POST_SHIFT 8
7018 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
7019 #define WRPLL_DIVIDER_FB_SHIFT 16
7020 #define WRPLL_DIVIDER_FB_MASK (0xff << 16)
7022 /* Port clock selection */
7023 #define _PORT_CLK_SEL_A 0x46100
7024 #define _PORT_CLK_SEL_B 0x46104
7025 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
7026 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
7027 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
7028 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
7029 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
7030 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
7031 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
7032 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
7033 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
7034 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
7036 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
7037 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
7038 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
7039 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
7040 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
7041 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
7042 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
7043 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
7044 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
7046 /* Transcoder clock selection */
7047 #define _TRANS_CLK_SEL_A 0x46140
7048 #define _TRANS_CLK_SEL_B 0x46144
7049 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
7050 /* For each transcoder, we need to select the corresponding port clock */
7051 #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
7052 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
7053 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
7054 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
7057 #define CDCLK_FREQ _MMIO(0x46200)
7059 #define _TRANSA_MSA_MISC 0x60410
7060 #define _TRANSB_MSA_MISC 0x61410
7061 #define _TRANSC_MSA_MISC 0x62410
7062 #define _TRANS_EDP_MSA_MISC 0x6f410
7063 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
7064 /* See DP_MSA_MISC_* for the bit definitions */
7066 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
7067 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
7068 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
7069 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
7070 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
7071 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
7072 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
7075 #define LCPLL_CTL _MMIO(0x130040)
7076 #define LCPLL_PLL_DISABLE (1 << 31)
7077 #define LCPLL_PLL_LOCK (1 << 30)
7078 #define LCPLL_REF_NON_SSC (0 << 28)
7079 #define LCPLL_REF_BCLK (2 << 28)
7080 #define LCPLL_REF_PCH_SSC (3 << 28)
7081 #define LCPLL_REF_MASK (3 << 28)
7082 #define LCPLL_CLK_FREQ_MASK (3 << 26)
7083 #define LCPLL_CLK_FREQ_450 (0 << 26)
7084 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
7085 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
7086 #define LCPLL_CLK_FREQ_675_BDW (3 << 26)
7087 #define LCPLL_CD_CLOCK_DISABLE (1 << 25)
7088 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
7089 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
7090 #define LCPLL_POWER_DOWN_ALLOW (1 << 22)
7091 #define LCPLL_CD_SOURCE_FCLK (1 << 21)
7092 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
7099 #define CDCLK_CTL _MMIO(0x46000)
7100 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
7101 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
7102 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
7103 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
7104 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
7105 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
7106 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
7107 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
7108 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
7109 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
7110 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
7111 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
7112 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
7113 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
7114 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
7115 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
7116 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
7117 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
7118 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
7120 /* CDCLK_SQUASH_CTL */
7121 #define CDCLK_SQUASH_CTL _MMIO(0x46008)
7122 #define CDCLK_SQUASH_ENABLE REG_BIT(31)
7123 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
7124 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
7125 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
7126 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
7129 #define LCPLL1_CTL _MMIO(0x46010)
7130 #define LCPLL2_CTL _MMIO(0x46014)
7131 #define LCPLL_PLL_ENABLE (1 << 31)
7134 #define DPLL_CTRL1 _MMIO(0x6C058)
7135 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
7136 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
7137 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
7138 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
7139 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
7140 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
7141 #define DPLL_CTRL1_LINK_RATE_2700 0
7142 #define DPLL_CTRL1_LINK_RATE_1350 1
7143 #define DPLL_CTRL1_LINK_RATE_810 2
7144 #define DPLL_CTRL1_LINK_RATE_1620 3
7145 #define DPLL_CTRL1_LINK_RATE_1080 4
7146 #define DPLL_CTRL1_LINK_RATE_2160 5
7149 #define DPLL_CTRL2 _MMIO(0x6C05C)
7150 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
7151 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
7152 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
7153 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
7154 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
7157 #define DPLL_STATUS _MMIO(0x6C060)
7158 #define DPLL_LOCK(id) (1 << ((id) * 8))
7161 #define _DPLL1_CFGCR1 0x6C040
7162 #define _DPLL2_CFGCR1 0x6C048
7163 #define _DPLL3_CFGCR1 0x6C050
7164 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
7165 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
7166 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
7167 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
7169 #define _DPLL1_CFGCR2 0x6C044
7170 #define _DPLL2_CFGCR2 0x6C04C
7171 #define _DPLL3_CFGCR2 0x6C054
7172 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
7173 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
7174 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
7175 #define DPLL_CFGCR2_KDIV_MASK (3 << 5)
7176 #define DPLL_CFGCR2_KDIV(x) ((x) << 5)
7177 #define DPLL_CFGCR2_KDIV_5 (0 << 5)
7178 #define DPLL_CFGCR2_KDIV_2 (1 << 5)
7179 #define DPLL_CFGCR2_KDIV_3 (2 << 5)
7180 #define DPLL_CFGCR2_KDIV_1 (3 << 5)
7181 #define DPLL_CFGCR2_PDIV_MASK (7 << 2)
7182 #define DPLL_CFGCR2_PDIV(x) ((x) << 2)
7183 #define DPLL_CFGCR2_PDIV_1 (0 << 2)
7184 #define DPLL_CFGCR2_PDIV_2 (1 << 2)
7185 #define DPLL_CFGCR2_PDIV_3 (2 << 2)
7186 #define DPLL_CFGCR2_PDIV_7 (4 << 2)
7187 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
7188 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
7190 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
7191 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
7194 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
7195 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
7196 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
7197 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
7199 (tc_port) - TC_PORT_4 + 21))
7200 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
7201 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7202 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7203 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
7204 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
7205 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7206 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
7207 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7211 * First registers controls the first A and B, while the second register
7212 * controls the phy C and D. The bits on these registers are the
7213 * same, but refer to different phys
7215 #define _DG1_DPCLKA_CFGCR0 0x164280
7216 #define _DG1_DPCLKA1_CFGCR0 0x16C280
7217 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
7218 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
7219 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
7220 _DG1_DPCLKA_CFGCR0, \
7221 _DG1_DPCLKA1_CFGCR0)
7222 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
7223 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
7224 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7225 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
7228 #define _ADLS_DPCLKA_CFGCR0 0x164280
7229 #define _ADLS_DPCLKA_CFGCR1 0x1642BC
7230 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
7231 _ADLS_DPCLKA_CFGCR0, \
7232 _ADLS_DPCLKA_CFGCR1)
7233 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
7234 /* ADLS DPCLKA_CFGCR0 DDI mask */
7235 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
7236 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
7237 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
7238 /* ADLS DPCLKA_CFGCR1 DDI mask */
7239 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
7240 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
7241 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
7242 ADLS_DPCLKA_DDIA_SEL_MASK, \
7243 ADLS_DPCLKA_DDIB_SEL_MASK, \
7244 ADLS_DPCLKA_DDII_SEL_MASK, \
7245 ADLS_DPCLKA_DDIJ_SEL_MASK, \
7246 ADLS_DPCLKA_DDIK_SEL_MASK)
7249 #define DPLL0_ENABLE 0x46010
7250 #define DPLL1_ENABLE 0x46014
7251 #define _ADLS_DPLL2_ENABLE 0x46018
7252 #define _ADLS_DPLL3_ENABLE 0x46030
7253 #define PLL_ENABLE (1 << 31)
7254 #define PLL_LOCK (1 << 30)
7255 #define PLL_POWER_ENABLE (1 << 27)
7256 #define PLL_POWER_STATE (1 << 26)
7257 #define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
7258 _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
7260 #define _DG2_PLL3_ENABLE 0x4601C
7262 #define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
7263 _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
7265 #define TBT_PLL_ENABLE _MMIO(0x46020)
7267 #define _MG_PLL1_ENABLE 0x46030
7268 #define _MG_PLL2_ENABLE 0x46034
7269 #define _MG_PLL3_ENABLE 0x46038
7270 #define _MG_PLL4_ENABLE 0x4603C
7271 /* Bits are the same as DPLL0_ENABLE */
7272 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
7276 #define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
7277 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
7279 /* ADL-P Type C PLL */
7280 #define PORTTC1_PLL_ENABLE 0x46038
7281 #define PORTTC2_PLL_ENABLE 0x46040
7283 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
7284 PORTTC1_PLL_ENABLE, \
7287 #define _ICL_DPLL0_CFGCR0 0x164000
7288 #define _ICL_DPLL1_CFGCR0 0x164080
7289 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
7291 #define DPLL_CFGCR0_HDMI_MODE (1 << 30)
7292 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
7293 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
7294 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
7295 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
7296 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
7297 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
7298 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
7299 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
7300 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
7301 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
7302 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
7303 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
7304 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
7305 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
7306 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
7308 #define _ICL_DPLL0_CFGCR1 0x164004
7309 #define _ICL_DPLL1_CFGCR1 0x164084
7310 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
7312 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
7313 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
7314 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
7315 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
7316 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
7317 #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
7318 #define DPLL_CFGCR1_KDIV_SHIFT (6)
7319 #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
7320 #define DPLL_CFGCR1_KDIV_1 (1 << 6)
7321 #define DPLL_CFGCR1_KDIV_2 (2 << 6)
7322 #define DPLL_CFGCR1_KDIV_3 (4 << 6)
7323 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
7324 #define DPLL_CFGCR1_PDIV_SHIFT (2)
7325 #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
7326 #define DPLL_CFGCR1_PDIV_2 (1 << 2)
7327 #define DPLL_CFGCR1_PDIV_3 (2 << 2)
7328 #define DPLL_CFGCR1_PDIV_5 (4 << 2)
7329 #define DPLL_CFGCR1_PDIV_7 (8 << 2)
7330 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
7331 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
7332 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
7334 #define _TGL_DPLL0_CFGCR0 0x164284
7335 #define _TGL_DPLL1_CFGCR0 0x16428C
7336 #define _TGL_TBTPLL_CFGCR0 0x16429C
7337 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
7338 _TGL_DPLL1_CFGCR0, \
7340 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
7343 #define _TGL_DPLL0_DIV0 0x164B00
7344 #define _TGL_DPLL1_DIV0 0x164C00
7345 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
7346 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
7347 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
7349 #define _TGL_DPLL0_CFGCR1 0x164288
7350 #define _TGL_DPLL1_CFGCR1 0x164290
7351 #define _TGL_TBTPLL_CFGCR1 0x1642A0
7352 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
7353 _TGL_DPLL1_CFGCR1, \
7355 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
7358 #define _DG1_DPLL2_CFGCR0 0x16C284
7359 #define _DG1_DPLL3_CFGCR0 0x16C28C
7360 #define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
7361 _TGL_DPLL1_CFGCR0, \
7362 _DG1_DPLL2_CFGCR0, \
7365 #define _DG1_DPLL2_CFGCR1 0x16C288
7366 #define _DG1_DPLL3_CFGCR1 0x16C290
7367 #define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
7368 _TGL_DPLL1_CFGCR1, \
7369 _DG1_DPLL2_CFGCR1, \
7372 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
7373 #define _ADLS_DPLL3_CFGCR0 0x1642C0
7374 #define _ADLS_DPLL4_CFGCR0 0x164294
7375 #define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
7376 _TGL_DPLL1_CFGCR0, \
7377 _ADLS_DPLL4_CFGCR0, \
7380 #define _ADLS_DPLL3_CFGCR1 0x1642C4
7381 #define _ADLS_DPLL4_CFGCR1 0x164298
7382 #define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
7383 _TGL_DPLL1_CFGCR1, \
7384 _ADLS_DPLL4_CFGCR1, \
7387 /* BXT display engine PLL */
7388 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
7389 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
7390 #define BXT_DE_PLL_RATIO_MASK 0xff
7392 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
7393 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
7394 #define BXT_DE_PLL_LOCK (1 << 30)
7395 #define BXT_DE_PLL_FREQ_REQ (1 << 23)
7396 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
7397 #define ICL_CDCLK_PLL_RATIO(x) (x)
7398 #define ICL_CDCLK_PLL_RATIO_MASK 0xff
7401 #define DC_STATE_EN _MMIO(0x45504)
7402 #define DC_STATE_DISABLE 0
7403 #define DC_STATE_EN_DC3CO REG_BIT(30)
7404 #define DC_STATE_DC3CO_STATUS REG_BIT(29)
7405 #define DC_STATE_EN_UPTO_DC5 (1 << 0)
7406 #define DC_STATE_EN_DC9 (1 << 3)
7407 #define DC_STATE_EN_UPTO_DC6 (2 << 0)
7408 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
7410 #define DC_STATE_DEBUG _MMIO(0x45520)
7411 #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
7412 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
7414 #define D_COMP_BDW _MMIO(0x138144)
7416 /* Pipe WM_LINETIME - watermark line time */
7417 #define _WM_LINETIME_A 0x45270
7418 #define _WM_LINETIME_B 0x45274
7419 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
7420 #define HSW_LINETIME_MASK REG_GENMASK(8, 0)
7421 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
7422 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
7423 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
7426 #define SFUSE_STRAP _MMIO(0xc2014)
7427 #define SFUSE_STRAP_FUSE_LOCK (1 << 13)
7428 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
7429 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
7430 #define SFUSE_STRAP_CRT_DISABLED (1 << 6)
7431 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
7432 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
7433 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
7434 #define SFUSE_STRAP_DDID_DETECTED (1 << 0)
7436 #define WM_MISC _MMIO(0x45260)
7437 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
7439 #define WM_DBG _MMIO(0x45280)
7440 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
7441 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
7442 #define WM_DBG_DISALLOW_SPRITE (1 << 2)
7445 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
7446 #define _PIPE_A_CSC_COEFF_BY 0x49014
7447 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
7448 #define _PIPE_A_CSC_COEFF_BU 0x4901c
7449 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
7450 #define _PIPE_A_CSC_COEFF_BV 0x49024
7452 #define _PIPE_A_CSC_MODE 0x49028
7453 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */
7454 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */
7455 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */
7456 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
7457 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */
7459 #define _PIPE_A_CSC_PREOFF_HI 0x49030
7460 #define _PIPE_A_CSC_PREOFF_ME 0x49034
7461 #define _PIPE_A_CSC_PREOFF_LO 0x49038
7462 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
7463 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
7464 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
7466 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
7467 #define _PIPE_B_CSC_COEFF_BY 0x49114
7468 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
7469 #define _PIPE_B_CSC_COEFF_BU 0x4911c
7470 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
7471 #define _PIPE_B_CSC_COEFF_BV 0x49124
7472 #define _PIPE_B_CSC_MODE 0x49128
7473 #define _PIPE_B_CSC_PREOFF_HI 0x49130
7474 #define _PIPE_B_CSC_PREOFF_ME 0x49134
7475 #define _PIPE_B_CSC_PREOFF_LO 0x49138
7476 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
7477 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
7478 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
7480 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7481 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7482 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
7483 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
7484 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
7485 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
7486 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
7487 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
7488 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
7489 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
7490 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
7491 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
7492 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
7494 /* Pipe Output CSC */
7495 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
7496 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
7497 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
7498 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
7499 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
7500 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
7501 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
7502 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
7503 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
7504 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
7505 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
7506 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
7508 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
7509 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
7510 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
7511 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
7512 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
7513 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
7514 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
7515 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
7516 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
7517 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
7518 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
7519 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
7521 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
7522 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
7523 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
7524 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
7525 _PIPE_A_OUTPUT_CSC_COEFF_BY, \
7526 _PIPE_B_OUTPUT_CSC_COEFF_BY)
7527 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
7528 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
7529 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
7530 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
7531 _PIPE_A_OUTPUT_CSC_COEFF_BU, \
7532 _PIPE_B_OUTPUT_CSC_COEFF_BU)
7533 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
7534 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
7535 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
7536 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
7537 _PIPE_A_OUTPUT_CSC_COEFF_BV, \
7538 _PIPE_B_OUTPUT_CSC_COEFF_BV)
7539 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
7540 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
7541 _PIPE_B_OUTPUT_CSC_PREOFF_HI)
7542 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
7543 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
7544 _PIPE_B_OUTPUT_CSC_PREOFF_ME)
7545 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
7546 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
7547 _PIPE_B_OUTPUT_CSC_PREOFF_LO)
7548 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
7549 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
7550 _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
7551 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
7552 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
7553 _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
7554 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
7555 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
7556 _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
7558 /* pipe degamma/gamma LUTs on IVB+ */
7559 #define _PAL_PREC_INDEX_A 0x4A400
7560 #define _PAL_PREC_INDEX_B 0x4AC00
7561 #define _PAL_PREC_INDEX_C 0x4B400
7562 #define PAL_PREC_10_12_BIT (0 << 31)
7563 #define PAL_PREC_SPLIT_MODE (1 << 31)
7564 #define PAL_PREC_AUTO_INCREMENT (1 << 15)
7565 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
7566 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
7567 #define _PAL_PREC_DATA_A 0x4A404
7568 #define _PAL_PREC_DATA_B 0x4AC04
7569 #define _PAL_PREC_DATA_C 0x4B404
7570 /* see PREC_PALETTE_* for the bits */
7571 #define _PAL_PREC_GC_MAX_A 0x4A410
7572 #define _PAL_PREC_GC_MAX_B 0x4AC10
7573 #define _PAL_PREC_GC_MAX_C 0x4B410
7574 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
7575 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
7576 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
7577 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
7578 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
7579 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
7581 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
7582 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
7583 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
7584 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
7585 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
7587 #define _PRE_CSC_GAMC_INDEX_A 0x4A484
7588 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
7589 #define _PRE_CSC_GAMC_INDEX_C 0x4B484
7590 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
7591 #define _PRE_CSC_GAMC_DATA_A 0x4A488
7592 #define _PRE_CSC_GAMC_DATA_B 0x4AC88
7593 #define _PRE_CSC_GAMC_DATA_C 0x4B488
7595 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
7596 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
7598 /* ICL Multi segmented gamma */
7599 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
7600 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
7601 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
7602 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0)
7604 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
7605 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
7606 /* see PREC_PALETTE_12P4_* for the bits */
7608 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
7609 _PAL_PREC_MULTI_SEG_INDEX_A, \
7610 _PAL_PREC_MULTI_SEG_INDEX_B)
7611 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
7612 _PAL_PREC_MULTI_SEG_DATA_A, \
7613 _PAL_PREC_MULTI_SEG_DATA_B)
7615 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
7617 /* Plane CSC Registers */
7618 #define _PLANE_CSC_RY_GY_1_A 0x70210
7619 #define _PLANE_CSC_RY_GY_2_A 0x70310
7621 #define _PLANE_CSC_RY_GY_1_B 0x71210
7622 #define _PLANE_CSC_RY_GY_2_B 0x71310
7624 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
7625 _PLANE_CSC_RY_GY_1_B)
7626 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
7627 _PLANE_INPUT_CSC_RY_GY_2_B)
7628 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
7629 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
7630 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
7632 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228
7633 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328
7635 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228
7636 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328
7638 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
7639 _PLANE_CSC_PREOFF_HI_1_B)
7640 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
7641 _PLANE_CSC_PREOFF_HI_2_B)
7642 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
7643 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
7646 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
7647 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
7649 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
7650 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
7652 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
7653 _PLANE_CSC_POSTOFF_HI_1_B)
7654 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
7655 _PLANE_CSC_POSTOFF_HI_2_B)
7656 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
7657 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
7660 /* pipe CSC & degamma/gamma LUTs on CHV */
7661 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
7662 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
7663 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
7664 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
7665 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
7666 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
7667 /* cgm degamma ldw */
7668 #define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16)
7669 #define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0)
7670 /* cgm degamma udw */
7671 #define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0)
7672 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
7674 #define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16)
7675 #define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0)
7677 #define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0)
7678 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
7679 #define CGM_PIPE_MODE_GAMMA (1 << 2)
7680 #define CGM_PIPE_MODE_CSC (1 << 1)
7681 #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
7683 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
7684 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
7685 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
7686 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
7687 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
7688 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
7689 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
7690 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
7692 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
7693 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
7694 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
7695 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
7696 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
7697 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
7698 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
7699 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
7701 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
7702 #define GEN4_TIMESTAMP _MMIO(0x2358)
7703 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
7704 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
7706 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
7707 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
7708 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
7709 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
7710 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
7712 #define _PIPE_FRMTMSTMP_A 0x70048
7713 #define PIPE_FRMTMSTMP(pipe) \
7714 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
7716 /* Display Stream Splitter Control */
7717 #define DSS_CTL1 _MMIO(0x67400)
7718 #define SPLITTER_ENABLE (1 << 31)
7719 #define JOINER_ENABLE (1 << 30)
7720 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
7721 #define DUAL_LINK_MODE_FRONTBACK (0 << 24)
7722 #define OVERLAP_PIXELS_MASK (0xf << 16)
7723 #define OVERLAP_PIXELS(pixels) ((pixels) << 16)
7724 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
7725 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
7726 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
7728 #define DSS_CTL2 _MMIO(0x67404)
7729 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
7730 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
7731 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
7732 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
7734 #define _ICL_PIPE_DSS_CTL1_PB 0x78200
7735 #define _ICL_PIPE_DSS_CTL1_PC 0x78400
7736 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7737 _ICL_PIPE_DSS_CTL1_PB, \
7738 _ICL_PIPE_DSS_CTL1_PC)
7739 #define BIG_JOINER_ENABLE (1 << 29)
7740 #define MASTER_BIG_JOINER_ENABLE (1 << 28)
7741 #define VGA_CENTERING_ENABLE (1 << 27)
7742 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
7743 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
7744 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
7745 #define UNCOMPRESSED_JOINER_MASTER (1 << 21)
7746 #define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
7748 #define _ICL_PIPE_DSS_CTL2_PB 0x78204
7749 #define _ICL_PIPE_DSS_CTL2_PC 0x78404
7750 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7751 _ICL_PIPE_DSS_CTL2_PB, \
7752 _ICL_PIPE_DSS_CTL2_PC)
7754 #define GGC _MMIO(0x108040)
7755 #define GMS_MASK REG_GENMASK(15, 8)
7756 #define GGMS_MASK REG_GENMASK(7, 6)
7758 #define GEN12_GSMBASE _MMIO(0x108100)
7759 #define GEN12_DSMBASE _MMIO(0x1080C0)
7760 #define GEN12_BDSM_MASK REG_GENMASK64(63, 20)
7762 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
7763 #define SGSI_SIDECLK_DIS REG_BIT(17)
7764 #define SGGI_DIS REG_BIT(15)
7765 #define SGR_DIS REG_BIT(13)
7767 #define _ICL_PHY_MISC_A 0x64C00
7768 #define _ICL_PHY_MISC_B 0x64C04
7769 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
7770 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
7771 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
7773 #define ICL_PHY_MISC_MUX_DDID (1 << 28)
7774 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
7775 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
7777 /* Icelake Display Stream Compression Registers */
7778 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
7779 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
7780 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
7781 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
7782 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
7783 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
7784 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7785 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
7786 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
7787 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7788 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
7789 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
7790 #define DSC_ALT_ICH_SEL (1 << 20)
7791 #define DSC_VBR_ENABLE (1 << 19)
7792 #define DSC_422_ENABLE (1 << 18)
7793 #define DSC_COLOR_SPACE_CONVERSION (1 << 17)
7794 #define DSC_BLOCK_PREDICTION (1 << 16)
7795 #define DSC_LINE_BUF_DEPTH_SHIFT 12
7796 #define DSC_BPC_SHIFT 8
7797 #define DSC_VER_MIN_SHIFT 4
7798 #define DSC_VER_MAJ (0x1 << 0)
7800 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
7801 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
7802 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
7803 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
7804 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
7805 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
7806 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7807 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
7808 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
7809 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7810 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
7811 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
7812 #define DSC_BPP(bpp) ((bpp) << 0)
7814 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
7815 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
7816 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
7817 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
7818 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
7819 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
7820 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7821 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
7822 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
7823 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7824 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
7825 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
7826 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
7827 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
7829 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
7830 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
7831 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
7832 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
7833 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
7834 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
7835 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7836 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
7837 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
7838 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7839 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
7840 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
7841 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
7842 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
7844 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
7845 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
7846 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
7847 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
7848 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
7849 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
7850 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7851 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
7852 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
7853 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7854 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
7855 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
7856 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
7857 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
7859 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
7860 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
7861 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
7862 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
7863 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
7864 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
7865 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7866 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
7867 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
7868 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7869 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
7870 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
7871 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
7872 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
7874 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
7875 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
7876 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
7877 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
7878 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
7879 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
7880 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7881 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
7882 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
7883 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7884 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
7885 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
7886 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
7887 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
7888 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
7889 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
7891 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
7892 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
7893 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
7894 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
7895 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
7896 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
7897 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7898 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
7899 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
7900 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7901 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
7902 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
7903 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
7904 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
7906 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
7907 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
7908 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
7909 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
7910 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
7911 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
7912 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7913 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
7914 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
7915 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7916 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
7917 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
7918 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
7919 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
7921 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
7922 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
7923 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
7924 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
7925 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
7926 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
7927 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7928 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
7929 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
7930 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7931 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
7932 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
7933 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
7934 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
7936 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
7937 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
7938 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
7939 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
7940 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
7941 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
7942 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7943 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
7944 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
7945 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7946 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
7947 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
7948 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
7949 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
7950 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
7951 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
7953 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
7954 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
7955 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
7956 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
7957 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
7958 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
7959 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7960 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
7961 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
7962 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7963 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
7964 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
7966 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
7967 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
7968 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
7969 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
7970 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
7971 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
7972 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7973 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
7974 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
7975 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7976 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
7977 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
7979 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
7980 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
7981 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
7982 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
7983 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
7984 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
7985 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7986 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
7987 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
7988 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7989 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
7990 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
7992 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
7993 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
7994 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
7995 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
7996 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
7997 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
7998 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7999 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
8000 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
8001 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8002 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
8003 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
8005 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
8006 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
8007 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
8008 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
8009 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
8010 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
8011 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8012 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
8013 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
8014 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8015 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
8016 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
8018 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
8019 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
8020 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
8021 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
8022 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
8023 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
8024 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8025 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
8026 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
8027 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8028 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
8029 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
8030 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
8031 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
8032 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
8034 /* Icelake Rate Control Buffer Threshold Registers */
8035 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
8036 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
8037 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
8038 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
8039 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
8040 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
8041 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
8042 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
8043 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
8044 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
8045 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
8046 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
8047 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8048 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
8049 _ICL_DSC0_RC_BUF_THRESH_0_PC)
8050 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8051 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
8052 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
8053 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8054 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
8055 _ICL_DSC1_RC_BUF_THRESH_0_PC)
8056 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8057 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
8058 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
8060 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
8061 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
8062 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
8063 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
8064 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
8065 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
8066 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
8067 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
8068 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
8069 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
8070 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
8071 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
8072 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8073 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
8074 _ICL_DSC0_RC_BUF_THRESH_1_PC)
8075 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8076 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
8077 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
8078 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8079 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
8080 _ICL_DSC1_RC_BUF_THRESH_1_PC)
8081 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8082 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
8083 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
8085 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
8086 #define MODULAR_FIA_MASK (1 << 4)
8087 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
8088 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
8089 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
8090 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
8091 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
8093 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
8094 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
8096 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
8097 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
8099 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
8100 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
8101 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
8102 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
8104 #define _TCSS_DDI_STATUS_1 0x161500
8105 #define _TCSS_DDI_STATUS_2 0x161504
8106 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
8107 _TCSS_DDI_STATUS_1, \
8108 _TCSS_DDI_STATUS_2))
8109 #define TCSS_DDI_STATUS_READY REG_BIT(2)
8110 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
8111 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
8113 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
8114 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
8115 #define PRIMARY_SPI_REGIONID _MMIO(0x102084)
8116 #define SPI_STATIC_REGIONS _MMIO(0x102090)
8117 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
8118 #define OROM_OFFSET _MMIO(0x1020c0)
8119 #define OROM_OFFSET_MASK REG_GENMASK(20, 16)
8121 /* This register controls the Display State Buffer (DSB) engines. */
8122 #define _DSBSL_INSTANCE_BASE 0x70B00
8123 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
8124 (pipe) * 0x1000 + (id) * 0x100)
8125 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
8126 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
8127 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
8128 #define DSB_ENABLE (1 << 31)
8129 #define DSB_STATUS (1 << 0)
8131 #define CLKREQ_POLICY _MMIO(0x101038)
8132 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
8134 #define CLKGATE_DIS_MISC _MMIO(0x46534)
8135 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
8137 #define GEN12_CULLBIT1 _MMIO(0x6100)
8138 #define GEN12_CULLBIT2 _MMIO(0x7030)
8139 #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC)
8141 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
8142 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
8143 #define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A)
8144 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
8146 #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
8147 #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
8148 #define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
8149 #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
8150 #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
8152 #define MTL_LATENCY_SAGV _MMIO(0x4578b)
8153 #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
8155 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
8156 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
8157 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
8158 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
8160 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2)
8161 #define MTL_TRCD_MASK REG_GENMASK(31, 24)
8162 #define MTL_TRP_MASK REG_GENMASK(23, 16)
8163 #define MTL_DCLK_MASK REG_GENMASK(15, 0)
8165 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2)
8166 #define MTL_TRAS_MASK REG_GENMASK(16, 8)
8167 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
8169 #define MTL_MEDIA_GSI_BASE 0x380000
8171 #endif /* _I915_REG_H_ */