1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * DOC: The i915 register macro definition style guide
31 * Follow the style described here for new macros, and while changing existing
32 * macros. Do **not** mass change existing definitions just to update the style.
37 * Keep helper macros near the top. For example, _PIPE() and friends.
39 * Prefix macros that generally should not be used outside of this file with
40 * underscore '_'. For example, _PIPE() and friends, single instances of
41 * registers that are defined solely for the use by function-like macros.
43 * Avoid using the underscore prefixed macros outside of this file. There are
44 * exceptions, but keep them to a minimum.
46 * There are two basic types of register definitions: Single registers and
47 * register groups. Register groups are registers which have two or more
48 * instances, for example one per pipe, port, transcoder, etc. Register groups
49 * should be defined using function-like macros.
51 * For single registers, define the register offset first, followed by register
54 * For register groups, define the register instance offsets first, prefixed
55 * with underscore, followed by a function-like macro choosing the right
56 * instance based on the parameter, followed by register contents.
58 * Define the register contents (i.e. bit and bit field macros) from most
59 * significant to least significant bit. Indent the register content macros
60 * using two extra spaces between ``#define`` and the macro name.
62 * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
63 * contents so that they are already shifted in place, and can be directly
64 * OR'd. For convenience, function-like macros may be used to define bit fields,
65 * but do note that the macros may be needed to read as well as write the
68 * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
69 * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
72 * Group the register and its contents together without blank lines, separate
73 * from other registers and their contents with one blank line.
75 * Indent macro values from macro names using TABs. Align values vertically. Use
76 * braces in macro values as needed to avoid unintended precedence after macro
77 * substitution. Use spaces in macro values according to kernel coding
78 * style. Use lower case in hexadecimal values.
83 * Try to name registers according to the specs. If the register name changes in
84 * the specs from platform to another, stick to the original name.
86 * Try to re-use existing register macro definitions. Only add new macros for
87 * new register offsets, or when the register contents have changed enough to
88 * warrant a full redefinition.
90 * When a register macro changes for a new platform, prefix the new macro using
91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
92 * prefix signifies the start platform/generation using the register.
94 * When a bit (field) macro changes or gets added for a new platform, while
95 * retaining the existing register macro, add a platform acronym or generation
96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
101 * (Note that the values in the example are indented using spaces instead of
102 * TABs to avoid misalignment in generated documentation. Use TABs in the
105 * #define _FOO_A 0xf000
106 * #define _FOO_B 0xf001
107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
108 * #define FOO_ENABLE (1 << 31)
109 * #define FOO_MODE_MASK (0xf << 16)
110 * #define FOO_MODE_SHIFT 16
111 * #define FOO_MODE_BAR (0 << 16)
112 * #define FOO_MODE_BAZ (1 << 16)
113 * #define FOO_MODE_QUX_SNB (2 << 16)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
123 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
125 #define INVALID_MMIO_REG _MMIO(0)
127 static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
132 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
134 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
137 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
139 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
142 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
144 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
146 #define _PLANE(plane, a, b) _PIPE(plane, a, b)
147 #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
148 #define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
149 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
150 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
151 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
152 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
153 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
154 #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
155 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
156 #define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
157 #define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \
158 _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
159 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
160 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
162 #define _MASKED_FIELD(mask, value) ({ \
163 if (__builtin_constant_p(mask)) \
164 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
165 if (__builtin_constant_p(value)) \
166 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
167 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
168 BUILD_BUG_ON_MSG((value) & ~(mask), \
169 "Incorrect value for mask"); \
170 (mask) << 16 | (value); })
171 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
172 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
184 #define RENDER_CLASS 0
185 #define VIDEO_DECODE_CLASS 1
186 #define VIDEO_ENHANCEMENT_CLASS 2
187 #define COPY_ENGINE_CLASS 3
188 #define OTHER_CLASS 4
189 #define MAX_ENGINE_CLASS 4
191 #define MAX_ENGINE_INSTANCE 1
193 /* PCI config space */
195 #define MCHBAR_I915 0x44
196 #define MCHBAR_I965 0x48
197 #define MCHBAR_SIZE (4 * 4096)
200 #define DEVEN_MCHBAR_EN (1 << 28)
202 /* BSM in include/drm/i915_drm.h */
204 #define HPLLCC 0xc0 /* 85x only */
205 #define GC_CLOCK_CONTROL_MASK (0x7 << 0)
206 #define GC_CLOCK_133_200 (0 << 0)
207 #define GC_CLOCK_100_200 (1 << 0)
208 #define GC_CLOCK_100_133 (2 << 0)
209 #define GC_CLOCK_133_266 (3 << 0)
210 #define GC_CLOCK_133_200_2 (4 << 0)
211 #define GC_CLOCK_133_266_2 (5 << 0)
212 #define GC_CLOCK_166_266 (6 << 0)
213 #define GC_CLOCK_166_250 (7 << 0)
215 #define I915_GDRST 0xc0 /* PCI config register */
216 #define GRDOM_FULL (0 << 2)
217 #define GRDOM_RENDER (1 << 2)
218 #define GRDOM_MEDIA (3 << 2)
219 #define GRDOM_MASK (3 << 2)
220 #define GRDOM_RESET_STATUS (1 << 1)
221 #define GRDOM_RESET_ENABLE (1 << 0)
223 /* BSpec only has register offset, PCI device and bit found empirically */
224 #define I830_CLOCK_GATE 0xc8 /* device 0 */
225 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
227 #define GCDGMBUS 0xcc
230 #define GCFGC 0xf0 /* 915+ only */
231 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
232 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
233 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
234 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
235 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
236 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
237 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
238 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
239 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
240 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
241 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
242 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
243 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
244 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
245 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
246 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
247 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
248 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
249 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
250 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
251 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
252 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
253 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
254 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
255 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
256 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
257 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
258 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
259 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
265 #define SWSCI_SCISEL (1 << 15)
266 #define SWSCI_GSSCIE (1 << 0)
268 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
271 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
272 #define ILK_GRDOM_FULL (0<<1)
273 #define ILK_GRDOM_RENDER (1<<1)
274 #define ILK_GRDOM_MEDIA (3<<1)
275 #define ILK_GRDOM_MASK (3<<1)
276 #define ILK_GRDOM_RESET_ENABLE (1<<0)
278 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
279 #define GEN6_MBC_SNPCR_SHIFT 21
280 #define GEN6_MBC_SNPCR_MASK (3<<21)
281 #define GEN6_MBC_SNPCR_MAX (0<<21)
282 #define GEN6_MBC_SNPCR_MED (1<<21)
283 #define GEN6_MBC_SNPCR_LOW (2<<21)
284 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
286 #define VLV_G3DCTL _MMIO(0x9024)
287 #define VLV_GSCKGCTL _MMIO(0x9028)
289 #define GEN6_MBCTL _MMIO(0x0907c)
290 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
291 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
292 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
293 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
294 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
296 #define GEN6_GDRST _MMIO(0x941c)
297 #define GEN6_GRDOM_FULL (1 << 0)
298 #define GEN6_GRDOM_RENDER (1 << 1)
299 #define GEN6_GRDOM_MEDIA (1 << 2)
300 #define GEN6_GRDOM_BLT (1 << 3)
301 #define GEN6_GRDOM_VECS (1 << 4)
302 #define GEN9_GRDOM_GUC (1 << 5)
303 #define GEN8_GRDOM_MEDIA2 (1 << 7)
305 #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base+0x228)
306 #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base+0x518)
307 #define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base+0x220)
308 #define PP_DIR_DCLV_2G 0xffffffff
310 #define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8 + 4)
311 #define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8)
313 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
314 #define GEN8_RPCS_ENABLE (1 << 31)
315 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
316 #define GEN8_RPCS_S_CNT_SHIFT 15
317 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
318 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
319 #define GEN8_RPCS_SS_CNT_SHIFT 8
320 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
321 #define GEN8_RPCS_EU_MAX_SHIFT 4
322 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
323 #define GEN8_RPCS_EU_MIN_SHIFT 0
324 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
326 #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
328 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
329 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
330 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
331 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
333 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
334 #define HSW_RCS_CONTEXT_ENABLE (1 << 7)
335 #define HSW_RCS_INHIBIT (1 << 8)
337 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
338 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
339 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
340 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
341 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
342 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
343 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
344 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
345 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
346 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
348 #define GAM_ECOCHK _MMIO(0x4090)
349 #define BDW_DISABLE_HDC_INVALIDATION (1<<25)
350 #define ECOCHK_SNB_BIT (1<<10)
351 #define ECOCHK_DIS_TLB (1<<8)
352 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
353 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
354 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
355 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
356 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
357 #define ECOCHK_PPGTT_UC_HSW (0x1<<3)
358 #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
359 #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
361 #define GAC_ECO_BITS _MMIO(0x14090)
362 #define ECOBITS_SNB_BIT (1<<13)
363 #define ECOBITS_PPGTT_CACHE64B (3<<8)
364 #define ECOBITS_PPGTT_CACHE4B (0<<8)
366 #define GAB_CTL _MMIO(0x24000)
367 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
369 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
370 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
371 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
372 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
373 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
374 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
375 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
376 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
377 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
378 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
379 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
380 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
381 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
382 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
383 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
384 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
385 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
389 #define VGA_ST01_MDA 0x3ba
390 #define VGA_ST01_CGA 0x3da
392 #define _VGA_MSR_WRITE _MMIO(0x3c2)
393 #define VGA_MSR_WRITE 0x3c2
394 #define VGA_MSR_READ 0x3cc
395 #define VGA_MSR_MEM_EN (1<<1)
396 #define VGA_MSR_CGA_MODE (1<<0)
398 #define VGA_SR_INDEX 0x3c4
400 #define VGA_SR_DATA 0x3c5
402 #define VGA_AR_INDEX 0x3c0
403 #define VGA_AR_VID_EN (1<<5)
404 #define VGA_AR_DATA_WRITE 0x3c0
405 #define VGA_AR_DATA_READ 0x3c1
407 #define VGA_GR_INDEX 0x3ce
408 #define VGA_GR_DATA 0x3cf
410 #define VGA_GR_MEM_READ_MODE_SHIFT 3
411 #define VGA_GR_MEM_READ_MODE_PLANE 1
413 #define VGA_GR_MEM_MODE_MASK 0xc
414 #define VGA_GR_MEM_MODE_SHIFT 2
415 #define VGA_GR_MEM_A0000_AFFFF 0
416 #define VGA_GR_MEM_A0000_BFFFF 1
417 #define VGA_GR_MEM_B0000_B7FFF 2
418 #define VGA_GR_MEM_B0000_BFFFF 3
420 #define VGA_DACMASK 0x3c6
421 #define VGA_DACRX 0x3c7
422 #define VGA_DACWX 0x3c8
423 #define VGA_DACDATA 0x3c9
425 #define VGA_CR_INDEX_MDA 0x3b4
426 #define VGA_CR_DATA_MDA 0x3b5
427 #define VGA_CR_INDEX_CGA 0x3d4
428 #define VGA_CR_DATA_CGA 0x3d5
431 * Instruction field definitions used by the command parser
433 #define INSTR_CLIENT_SHIFT 29
434 #define INSTR_MI_CLIENT 0x0
435 #define INSTR_BC_CLIENT 0x2
436 #define INSTR_RC_CLIENT 0x3
437 #define INSTR_SUBCLIENT_SHIFT 27
438 #define INSTR_SUBCLIENT_MASK 0x18000000
439 #define INSTR_MEDIA_SUBCLIENT 0x2
440 #define INSTR_26_TO_24_MASK 0x7000000
441 #define INSTR_26_TO_24_SHIFT 24
444 * Memory interface instructions used by the kernel
446 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
447 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
448 #define MI_GLOBAL_GTT (1<<22)
450 #define MI_NOOP MI_INSTR(0, 0)
451 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
452 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
453 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
454 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
455 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
456 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
457 #define MI_FLUSH MI_INSTR(0x04, 0)
458 #define MI_READ_FLUSH (1 << 0)
459 #define MI_EXE_FLUSH (1 << 1)
460 #define MI_NO_WRITE_FLUSH (1 << 2)
461 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
462 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
463 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
464 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
465 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
466 #define MI_ARB_ENABLE (1<<0)
467 #define MI_ARB_DISABLE (0<<0)
468 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
469 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
470 #define MI_SUSPEND_FLUSH_EN (1<<0)
471 #define MI_SET_APPID MI_INSTR(0x0e, 0)
472 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
473 #define MI_OVERLAY_CONTINUE (0x0<<21)
474 #define MI_OVERLAY_ON (0x1<<21)
475 #define MI_OVERLAY_OFF (0x2<<21)
476 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
477 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
478 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
479 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
480 /* IVB has funny definitions for which plane to flip. */
481 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
482 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
483 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
484 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
485 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
486 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
488 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
489 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
490 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
491 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
492 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
493 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
494 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
495 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
496 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
497 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
498 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
499 #define MI_SEMAPHORE_UPDATE (1<<21)
500 #define MI_SEMAPHORE_COMPARE (1<<20)
501 #define MI_SEMAPHORE_REGISTER (1<<18)
502 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
503 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
504 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
505 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
506 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
507 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
508 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
509 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
510 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
511 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
512 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
513 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
514 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
515 #define MI_SEMAPHORE_SYNC_MASK (3<<16)
516 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
517 #define MI_MM_SPACE_GTT (1<<8)
518 #define MI_MM_SPACE_PHYSICAL (0<<8)
519 #define MI_SAVE_EXT_STATE_EN (1<<3)
520 #define MI_RESTORE_EXT_STATE_EN (1<<2)
521 #define MI_FORCE_RESTORE (1<<1)
522 #define MI_RESTORE_INHIBIT (1<<0)
523 #define HSW_MI_RS_SAVE_STATE_EN (1<<3)
524 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
525 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
526 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
527 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
528 #define MI_SEMAPHORE_POLL (1<<15)
529 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
530 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
531 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
532 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
533 #define MI_USE_GGTT (1 << 22) /* g4x+ */
534 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
535 #define MI_STORE_DWORD_INDEX_SHIFT 2
536 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
537 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
538 * simply ignores the register load under certain conditions.
539 * - One can actually load arbitrary many arbitrary registers: Simply issue x
540 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
542 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
543 #define MI_LRI_FORCE_POSTED (1<<12)
544 #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
545 #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
546 #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
547 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
548 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
549 #define MI_INVALIDATE_TLB (1<<18)
550 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
551 #define MI_FLUSH_DW_OP_MASK (3<<14)
552 #define MI_FLUSH_DW_NOTIFY (1<<8)
553 #define MI_INVALIDATE_BSD (1<<7)
554 #define MI_FLUSH_DW_USE_GTT (1<<2)
555 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
556 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
557 #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
558 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
559 #define MI_BATCH_NON_SECURE (1)
560 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
561 #define MI_BATCH_NON_SECURE_I965 (1<<8)
562 #define MI_BATCH_PPGTT_HSW (1<<8)
563 #define MI_BATCH_NON_SECURE_HSW (1<<13)
564 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
565 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
566 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
567 #define MI_BATCH_RESOURCE_STREAMER (1<<10)
569 #define MI_PREDICATE_SRC0 _MMIO(0x2400)
570 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
571 #define MI_PREDICATE_SRC1 _MMIO(0x2408)
572 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
574 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
575 #define LOWER_SLICE_ENABLED (1<<0)
576 #define LOWER_SLICE_DISABLED (0<<0)
579 * 3D instructions used by the kernel
581 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
583 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
584 #define GEN9_MEDIA_POOL_ENABLE (1 << 31)
585 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
586 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
587 #define SC_UPDATE_SCISSOR (0x1<<1)
588 #define SC_ENABLE_MASK (0x1<<0)
589 #define SC_ENABLE (0x1<<0)
590 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
591 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
592 #define SCI_YMIN_MASK (0xffff<<16)
593 #define SCI_XMIN_MASK (0xffff<<0)
594 #define SCI_YMAX_MASK (0xffff<<16)
595 #define SCI_XMAX_MASK (0xffff<<0)
596 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
597 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
598 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
599 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
600 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
601 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
602 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
603 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
604 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
606 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
607 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
608 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
609 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
610 #define BLT_WRITE_A (2<<20)
611 #define BLT_WRITE_RGB (1<<20)
612 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
613 #define BLT_DEPTH_8 (0<<24)
614 #define BLT_DEPTH_16_565 (1<<24)
615 #define BLT_DEPTH_16_1555 (2<<24)
616 #define BLT_DEPTH_32 (3<<24)
617 #define BLT_ROP_SRC_COPY (0xcc<<16)
618 #define BLT_ROP_COLOR_COPY (0xf0<<16)
619 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
620 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
621 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
622 #define ASYNC_FLIP (1<<22)
623 #define DISPLAY_PLANE_A (0<<20)
624 #define DISPLAY_PLANE_B (1<<20)
625 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
626 #define PIPE_CONTROL_FLUSH_L3 (1<<27)
627 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
628 #define PIPE_CONTROL_MMIO_WRITE (1<<23)
629 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
630 #define PIPE_CONTROL_CS_STALL (1<<20)
631 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
632 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
633 #define PIPE_CONTROL_QW_WRITE (1<<14)
634 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
635 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
636 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
637 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
638 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
639 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
640 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
641 #define PIPE_CONTROL_NOTIFY (1<<8)
642 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
643 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
644 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
645 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
646 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
647 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
648 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
649 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
652 * Commands used only by the command parser
654 #define MI_SET_PREDICATE MI_INSTR(0x01, 0)
655 #define MI_ARB_CHECK MI_INSTR(0x05, 0)
656 #define MI_RS_CONTROL MI_INSTR(0x06, 0)
657 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
658 #define MI_PREDICATE MI_INSTR(0x0C, 0)
659 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
660 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
661 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
662 #define MI_URB_CLEAR MI_INSTR(0x19, 0)
663 #define MI_UPDATE_GTT MI_INSTR(0x23, 0)
664 #define MI_CLFLUSH MI_INSTR(0x27, 0)
665 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
666 #define MI_REPORT_PERF_COUNT_GGTT (1<<0)
667 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
668 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
669 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
670 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
671 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
673 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
674 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
675 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
676 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
677 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
678 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
679 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
680 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
681 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
682 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
683 #define GFX_OP_3DSTATE_SO_DECL_LIST \
684 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
686 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
687 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
688 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
689 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
690 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
691 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
692 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
693 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
694 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
695 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
697 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
699 #define COLOR_BLT ((0x2<<29)|(0x40<<22))
700 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
703 * Registers used only by the command parser
705 #define BCS_SWCTRL _MMIO(0x22200)
707 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
708 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
709 #define HS_INVOCATION_COUNT _MMIO(0x2300)
710 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
711 #define DS_INVOCATION_COUNT _MMIO(0x2308)
712 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
713 #define IA_VERTICES_COUNT _MMIO(0x2310)
714 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
715 #define IA_PRIMITIVES_COUNT _MMIO(0x2318)
716 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
717 #define VS_INVOCATION_COUNT _MMIO(0x2320)
718 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
719 #define GS_INVOCATION_COUNT _MMIO(0x2328)
720 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
721 #define GS_PRIMITIVES_COUNT _MMIO(0x2330)
722 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
723 #define CL_INVOCATION_COUNT _MMIO(0x2338)
724 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
725 #define CL_PRIMITIVES_COUNT _MMIO(0x2340)
726 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
727 #define PS_INVOCATION_COUNT _MMIO(0x2348)
728 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
729 #define PS_DEPTH_COUNT _MMIO(0x2350)
730 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
732 /* There are the 4 64-bit counter registers, one for each stream output */
733 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
734 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
736 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
737 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
739 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
740 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
741 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
742 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
743 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
744 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
746 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
747 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
748 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
750 /* There are the 16 64-bit CS General Purpose Registers */
751 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
752 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
754 #define GEN7_OACONTROL _MMIO(0x2360)
755 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
756 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
757 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
758 #define GEN7_OACONTROL_TIMER_ENABLE (1<<5)
759 #define GEN7_OACONTROL_FORMAT_A13 (0<<2)
760 #define GEN7_OACONTROL_FORMAT_A29 (1<<2)
761 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2<<2)
762 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3<<2)
763 #define GEN7_OACONTROL_FORMAT_B4_C8 (4<<2)
764 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5<<2)
765 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6<<2)
766 #define GEN7_OACONTROL_FORMAT_C4_B8 (7<<2)
767 #define GEN7_OACONTROL_FORMAT_SHIFT 2
768 #define GEN7_OACONTROL_PER_CTX_ENABLE (1<<1)
769 #define GEN7_OACONTROL_ENABLE (1<<0)
771 #define GEN8_OACTXID _MMIO(0x2364)
773 #define GEN8_OA_DEBUG _MMIO(0x2B04)
774 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1<<5)
775 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1<<6)
776 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1<<2)
777 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1<<1)
779 #define GEN8_OACONTROL _MMIO(0x2B00)
780 #define GEN8_OA_REPORT_FORMAT_A12 (0<<2)
781 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2<<2)
782 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5<<2)
783 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7<<2)
784 #define GEN8_OA_REPORT_FORMAT_SHIFT 2
785 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1<<1)
786 #define GEN8_OA_COUNTER_ENABLE (1<<0)
788 #define GEN8_OACTXCONTROL _MMIO(0x2360)
789 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F
790 #define GEN8_OA_TIMER_PERIOD_SHIFT 2
791 #define GEN8_OA_TIMER_ENABLE (1<<1)
792 #define GEN8_OA_COUNTER_RESUME (1<<0)
794 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
795 #define GEN7_OABUFFER_OVERRUN_DISABLE (1<<3)
796 #define GEN7_OABUFFER_EDGE_TRIGGER (1<<2)
797 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1<<1)
798 #define GEN7_OABUFFER_RESUME (1<<0)
800 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
801 #define GEN8_OABUFFER _MMIO(0x2b14)
803 #define GEN7_OASTATUS1 _MMIO(0x2364)
804 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
805 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1<<2)
806 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1<<1)
807 #define GEN7_OASTATUS1_REPORT_LOST (1<<0)
809 #define GEN7_OASTATUS2 _MMIO(0x2368)
810 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
812 #define GEN8_OASTATUS _MMIO(0x2b08)
813 #define GEN8_OASTATUS_OVERRUN_STATUS (1<<3)
814 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1<<2)
815 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1<<1)
816 #define GEN8_OASTATUS_REPORT_LOST (1<<0)
818 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
819 #define GEN8_OAHEADPTR_MASK 0xffffffc0
820 #define GEN8_OATAILPTR _MMIO(0x2B10)
821 #define GEN8_OATAILPTR_MASK 0xffffffc0
823 #define OABUFFER_SIZE_128K (0<<3)
824 #define OABUFFER_SIZE_256K (1<<3)
825 #define OABUFFER_SIZE_512K (2<<3)
826 #define OABUFFER_SIZE_1M (3<<3)
827 #define OABUFFER_SIZE_2M (4<<3)
828 #define OABUFFER_SIZE_4M (5<<3)
829 #define OABUFFER_SIZE_8M (6<<3)
830 #define OABUFFER_SIZE_16M (7<<3)
832 #define OA_MEM_SELECT_GGTT (1<<0)
835 * Flexible, Aggregate EU Counter Registers.
836 * Note: these aren't contiguous
838 #define EU_PERF_CNTL0 _MMIO(0xe458)
839 #define EU_PERF_CNTL1 _MMIO(0xe558)
840 #define EU_PERF_CNTL2 _MMIO(0xe658)
841 #define EU_PERF_CNTL3 _MMIO(0xe758)
842 #define EU_PERF_CNTL4 _MMIO(0xe45c)
843 #define EU_PERF_CNTL5 _MMIO(0xe55c)
844 #define EU_PERF_CNTL6 _MMIO(0xe65c)
850 #define OASTARTTRIG1 _MMIO(0x2710)
851 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
852 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff
854 #define OASTARTTRIG2 _MMIO(0x2714)
855 #define OASTARTTRIG2_INVERT_A_0 (1<<0)
856 #define OASTARTTRIG2_INVERT_A_1 (1<<1)
857 #define OASTARTTRIG2_INVERT_A_2 (1<<2)
858 #define OASTARTTRIG2_INVERT_A_3 (1<<3)
859 #define OASTARTTRIG2_INVERT_A_4 (1<<4)
860 #define OASTARTTRIG2_INVERT_A_5 (1<<5)
861 #define OASTARTTRIG2_INVERT_A_6 (1<<6)
862 #define OASTARTTRIG2_INVERT_A_7 (1<<7)
863 #define OASTARTTRIG2_INVERT_A_8 (1<<8)
864 #define OASTARTTRIG2_INVERT_A_9 (1<<9)
865 #define OASTARTTRIG2_INVERT_A_10 (1<<10)
866 #define OASTARTTRIG2_INVERT_A_11 (1<<11)
867 #define OASTARTTRIG2_INVERT_A_12 (1<<12)
868 #define OASTARTTRIG2_INVERT_A_13 (1<<13)
869 #define OASTARTTRIG2_INVERT_A_14 (1<<14)
870 #define OASTARTTRIG2_INVERT_A_15 (1<<15)
871 #define OASTARTTRIG2_INVERT_B_0 (1<<16)
872 #define OASTARTTRIG2_INVERT_B_1 (1<<17)
873 #define OASTARTTRIG2_INVERT_B_2 (1<<18)
874 #define OASTARTTRIG2_INVERT_B_3 (1<<19)
875 #define OASTARTTRIG2_INVERT_C_0 (1<<20)
876 #define OASTARTTRIG2_INVERT_C_1 (1<<21)
877 #define OASTARTTRIG2_INVERT_D_0 (1<<22)
878 #define OASTARTTRIG2_THRESHOLD_ENABLE (1<<23)
879 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1<<24)
880 #define OASTARTTRIG2_EVENT_SELECT_0 (1<<28)
881 #define OASTARTTRIG2_EVENT_SELECT_1 (1<<29)
882 #define OASTARTTRIG2_EVENT_SELECT_2 (1<<30)
883 #define OASTARTTRIG2_EVENT_SELECT_3 (1<<31)
885 #define OASTARTTRIG3 _MMIO(0x2718)
886 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf
887 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
888 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
889 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
890 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
891 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
892 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
893 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
894 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
896 #define OASTARTTRIG4 _MMIO(0x271c)
897 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf
898 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
899 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
900 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
901 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
902 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
903 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
904 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
905 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
907 #define OASTARTTRIG5 _MMIO(0x2720)
908 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
909 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff
911 #define OASTARTTRIG6 _MMIO(0x2724)
912 #define OASTARTTRIG6_INVERT_A_0 (1<<0)
913 #define OASTARTTRIG6_INVERT_A_1 (1<<1)
914 #define OASTARTTRIG6_INVERT_A_2 (1<<2)
915 #define OASTARTTRIG6_INVERT_A_3 (1<<3)
916 #define OASTARTTRIG6_INVERT_A_4 (1<<4)
917 #define OASTARTTRIG6_INVERT_A_5 (1<<5)
918 #define OASTARTTRIG6_INVERT_A_6 (1<<6)
919 #define OASTARTTRIG6_INVERT_A_7 (1<<7)
920 #define OASTARTTRIG6_INVERT_A_8 (1<<8)
921 #define OASTARTTRIG6_INVERT_A_9 (1<<9)
922 #define OASTARTTRIG6_INVERT_A_10 (1<<10)
923 #define OASTARTTRIG6_INVERT_A_11 (1<<11)
924 #define OASTARTTRIG6_INVERT_A_12 (1<<12)
925 #define OASTARTTRIG6_INVERT_A_13 (1<<13)
926 #define OASTARTTRIG6_INVERT_A_14 (1<<14)
927 #define OASTARTTRIG6_INVERT_A_15 (1<<15)
928 #define OASTARTTRIG6_INVERT_B_0 (1<<16)
929 #define OASTARTTRIG6_INVERT_B_1 (1<<17)
930 #define OASTARTTRIG6_INVERT_B_2 (1<<18)
931 #define OASTARTTRIG6_INVERT_B_3 (1<<19)
932 #define OASTARTTRIG6_INVERT_C_0 (1<<20)
933 #define OASTARTTRIG6_INVERT_C_1 (1<<21)
934 #define OASTARTTRIG6_INVERT_D_0 (1<<22)
935 #define OASTARTTRIG6_THRESHOLD_ENABLE (1<<23)
936 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1<<24)
937 #define OASTARTTRIG6_EVENT_SELECT_4 (1<<28)
938 #define OASTARTTRIG6_EVENT_SELECT_5 (1<<29)
939 #define OASTARTTRIG6_EVENT_SELECT_6 (1<<30)
940 #define OASTARTTRIG6_EVENT_SELECT_7 (1<<31)
942 #define OASTARTTRIG7 _MMIO(0x2728)
943 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf
944 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
945 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
946 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
947 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
948 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
949 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
950 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
951 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
953 #define OASTARTTRIG8 _MMIO(0x272c)
954 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf
955 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
956 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
957 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
958 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
959 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
960 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
961 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
962 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
964 #define OAREPORTTRIG1 _MMIO(0x2740)
965 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
966 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
968 #define OAREPORTTRIG2 _MMIO(0x2744)
969 #define OAREPORTTRIG2_INVERT_A_0 (1<<0)
970 #define OAREPORTTRIG2_INVERT_A_1 (1<<1)
971 #define OAREPORTTRIG2_INVERT_A_2 (1<<2)
972 #define OAREPORTTRIG2_INVERT_A_3 (1<<3)
973 #define OAREPORTTRIG2_INVERT_A_4 (1<<4)
974 #define OAREPORTTRIG2_INVERT_A_5 (1<<5)
975 #define OAREPORTTRIG2_INVERT_A_6 (1<<6)
976 #define OAREPORTTRIG2_INVERT_A_7 (1<<7)
977 #define OAREPORTTRIG2_INVERT_A_8 (1<<8)
978 #define OAREPORTTRIG2_INVERT_A_9 (1<<9)
979 #define OAREPORTTRIG2_INVERT_A_10 (1<<10)
980 #define OAREPORTTRIG2_INVERT_A_11 (1<<11)
981 #define OAREPORTTRIG2_INVERT_A_12 (1<<12)
982 #define OAREPORTTRIG2_INVERT_A_13 (1<<13)
983 #define OAREPORTTRIG2_INVERT_A_14 (1<<14)
984 #define OAREPORTTRIG2_INVERT_A_15 (1<<15)
985 #define OAREPORTTRIG2_INVERT_B_0 (1<<16)
986 #define OAREPORTTRIG2_INVERT_B_1 (1<<17)
987 #define OAREPORTTRIG2_INVERT_B_2 (1<<18)
988 #define OAREPORTTRIG2_INVERT_B_3 (1<<19)
989 #define OAREPORTTRIG2_INVERT_C_0 (1<<20)
990 #define OAREPORTTRIG2_INVERT_C_1 (1<<21)
991 #define OAREPORTTRIG2_INVERT_D_0 (1<<22)
992 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23)
993 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31)
995 #define OAREPORTTRIG3 _MMIO(0x2748)
996 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
997 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
998 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
999 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
1000 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
1001 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
1002 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
1003 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
1004 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
1006 #define OAREPORTTRIG4 _MMIO(0x274c)
1007 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
1008 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
1009 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
1010 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
1011 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
1012 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
1013 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
1014 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
1015 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
1017 #define OAREPORTTRIG5 _MMIO(0x2750)
1018 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
1019 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
1021 #define OAREPORTTRIG6 _MMIO(0x2754)
1022 #define OAREPORTTRIG6_INVERT_A_0 (1<<0)
1023 #define OAREPORTTRIG6_INVERT_A_1 (1<<1)
1024 #define OAREPORTTRIG6_INVERT_A_2 (1<<2)
1025 #define OAREPORTTRIG6_INVERT_A_3 (1<<3)
1026 #define OAREPORTTRIG6_INVERT_A_4 (1<<4)
1027 #define OAREPORTTRIG6_INVERT_A_5 (1<<5)
1028 #define OAREPORTTRIG6_INVERT_A_6 (1<<6)
1029 #define OAREPORTTRIG6_INVERT_A_7 (1<<7)
1030 #define OAREPORTTRIG6_INVERT_A_8 (1<<8)
1031 #define OAREPORTTRIG6_INVERT_A_9 (1<<9)
1032 #define OAREPORTTRIG6_INVERT_A_10 (1<<10)
1033 #define OAREPORTTRIG6_INVERT_A_11 (1<<11)
1034 #define OAREPORTTRIG6_INVERT_A_12 (1<<12)
1035 #define OAREPORTTRIG6_INVERT_A_13 (1<<13)
1036 #define OAREPORTTRIG6_INVERT_A_14 (1<<14)
1037 #define OAREPORTTRIG6_INVERT_A_15 (1<<15)
1038 #define OAREPORTTRIG6_INVERT_B_0 (1<<16)
1039 #define OAREPORTTRIG6_INVERT_B_1 (1<<17)
1040 #define OAREPORTTRIG6_INVERT_B_2 (1<<18)
1041 #define OAREPORTTRIG6_INVERT_B_3 (1<<19)
1042 #define OAREPORTTRIG6_INVERT_C_0 (1<<20)
1043 #define OAREPORTTRIG6_INVERT_C_1 (1<<21)
1044 #define OAREPORTTRIG6_INVERT_D_0 (1<<22)
1045 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23)
1046 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31)
1048 #define OAREPORTTRIG7 _MMIO(0x2758)
1049 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
1050 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
1051 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
1052 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
1053 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
1054 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
1055 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
1056 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
1057 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
1059 #define OAREPORTTRIG8 _MMIO(0x275c)
1060 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
1061 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
1062 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
1063 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
1064 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
1065 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
1066 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
1067 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
1068 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
1071 #define OACEC_COMPARE_LESS_OR_EQUAL 6
1072 #define OACEC_COMPARE_NOT_EQUAL 5
1073 #define OACEC_COMPARE_LESS_THAN 4
1074 #define OACEC_COMPARE_GREATER_OR_EQUAL 3
1075 #define OACEC_COMPARE_EQUAL 2
1076 #define OACEC_COMPARE_GREATER_THAN 1
1077 #define OACEC_COMPARE_ANY_EQUAL 0
1079 #define OACEC_COMPARE_VALUE_MASK 0xffff
1080 #define OACEC_COMPARE_VALUE_SHIFT 3
1082 #define OACEC_SELECT_NOA (0<<19)
1083 #define OACEC_SELECT_PREV (1<<19)
1084 #define OACEC_SELECT_BOOLEAN (2<<19)
1087 #define OACEC_MASK_MASK 0xffff
1088 #define OACEC_CONSIDERATIONS_MASK 0xffff
1089 #define OACEC_CONSIDERATIONS_SHIFT 16
1091 #define OACEC0_0 _MMIO(0x2770)
1092 #define OACEC0_1 _MMIO(0x2774)
1093 #define OACEC1_0 _MMIO(0x2778)
1094 #define OACEC1_1 _MMIO(0x277c)
1095 #define OACEC2_0 _MMIO(0x2780)
1096 #define OACEC2_1 _MMIO(0x2784)
1097 #define OACEC3_0 _MMIO(0x2788)
1098 #define OACEC3_1 _MMIO(0x278c)
1099 #define OACEC4_0 _MMIO(0x2790)
1100 #define OACEC4_1 _MMIO(0x2794)
1101 #define OACEC5_0 _MMIO(0x2798)
1102 #define OACEC5_1 _MMIO(0x279c)
1103 #define OACEC6_0 _MMIO(0x27a0)
1104 #define OACEC6_1 _MMIO(0x27a4)
1105 #define OACEC7_0 _MMIO(0x27a8)
1106 #define OACEC7_1 _MMIO(0x27ac)
1108 /* OA perf counters */
1109 #define OA_PERFCNT1_LO _MMIO(0x91B8)
1110 #define OA_PERFCNT1_HI _MMIO(0x91BC)
1111 #define OA_PERFCNT2_LO _MMIO(0x91C0)
1112 #define OA_PERFCNT2_HI _MMIO(0x91C4)
1113 #define OA_PERFCNT3_LO _MMIO(0x91C8)
1114 #define OA_PERFCNT3_HI _MMIO(0x91CC)
1115 #define OA_PERFCNT4_LO _MMIO(0x91D8)
1116 #define OA_PERFCNT4_HI _MMIO(0x91DC)
1118 #define OA_PERFMATRIX_LO _MMIO(0x91C8)
1119 #define OA_PERFMATRIX_HI _MMIO(0x91CC)
1121 /* RPM unit config (Gen8+) */
1122 #define RPM_CONFIG0 _MMIO(0x0D00)
1123 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1124 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1125 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
1126 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
1127 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
1128 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1130 #define RPM_CONFIG1 _MMIO(0x0D04)
1131 #define GEN10_GT_NOA_ENABLE (1 << 9)
1133 /* GPM unit config (Gen9+) */
1134 #define CTC_MODE _MMIO(0xA26C)
1135 #define CTC_SOURCE_PARAMETER_MASK 1
1136 #define CTC_SOURCE_CRYSTAL_CLOCK 0
1137 #define CTC_SOURCE_DIVIDE_LOGIC 1
1138 #define CTC_SHIFT_PARAMETER_SHIFT 1
1139 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1141 /* RCP unit config (Gen8+) */
1142 #define RCP_CONFIG _MMIO(0x0D08)
1145 #define HSW_MBVID2_NOA0 _MMIO(0x9E80)
1146 #define HSW_MBVID2_NOA1 _MMIO(0x9E84)
1147 #define HSW_MBVID2_NOA2 _MMIO(0x9E88)
1148 #define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
1149 #define HSW_MBVID2_NOA4 _MMIO(0x9E90)
1150 #define HSW_MBVID2_NOA5 _MMIO(0x9E94)
1151 #define HSW_MBVID2_NOA6 _MMIO(0x9E98)
1152 #define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
1153 #define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
1154 #define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
1156 #define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
1159 #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
1161 #define MICRO_BP0_0 _MMIO(0x9800)
1162 #define MICRO_BP0_2 _MMIO(0x9804)
1163 #define MICRO_BP0_1 _MMIO(0x9808)
1165 #define MICRO_BP1_0 _MMIO(0x980C)
1166 #define MICRO_BP1_2 _MMIO(0x9810)
1167 #define MICRO_BP1_1 _MMIO(0x9814)
1169 #define MICRO_BP2_0 _MMIO(0x9818)
1170 #define MICRO_BP2_2 _MMIO(0x981C)
1171 #define MICRO_BP2_1 _MMIO(0x9820)
1173 #define MICRO_BP3_0 _MMIO(0x9824)
1174 #define MICRO_BP3_2 _MMIO(0x9828)
1175 #define MICRO_BP3_1 _MMIO(0x982C)
1177 #define MICRO_BP_TRIGGER _MMIO(0x9830)
1178 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
1179 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
1180 #define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
1182 #define GDT_CHICKEN_BITS _MMIO(0x9840)
1183 #define GT_NOA_ENABLE 0x00000080
1185 #define NOA_DATA _MMIO(0x986C)
1186 #define NOA_WRITE _MMIO(0x9888)
1188 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1189 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
1190 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1195 #define DEBUG_RESET_I830 _MMIO(0x6070)
1196 #define DEBUG_RESET_FULL (1<<7)
1197 #define DEBUG_RESET_RENDER (1<<8)
1198 #define DEBUG_RESET_DISPLAY (1<<9)
1203 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
1204 #define IOSF_DEVFN_SHIFT 24
1205 #define IOSF_OPCODE_SHIFT 16
1206 #define IOSF_PORT_SHIFT 8
1207 #define IOSF_BYTE_ENABLES_SHIFT 4
1208 #define IOSF_BAR_SHIFT 1
1209 #define IOSF_SB_BUSY (1<<0)
1210 #define IOSF_PORT_BUNIT 0x03
1211 #define IOSF_PORT_PUNIT 0x04
1212 #define IOSF_PORT_NC 0x11
1213 #define IOSF_PORT_DPIO 0x12
1214 #define IOSF_PORT_GPIO_NC 0x13
1215 #define IOSF_PORT_CCK 0x14
1216 #define IOSF_PORT_DPIO_2 0x1a
1217 #define IOSF_PORT_FLISDSI 0x1b
1218 #define IOSF_PORT_GPIO_SC 0x48
1219 #define IOSF_PORT_GPIO_SUS 0xa8
1220 #define IOSF_PORT_CCU 0xa9
1221 #define CHV_IOSF_PORT_GPIO_N 0x13
1222 #define CHV_IOSF_PORT_GPIO_SE 0x48
1223 #define CHV_IOSF_PORT_GPIO_E 0xa8
1224 #define CHV_IOSF_PORT_GPIO_SW 0xb2
1225 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1226 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1228 /* See configdb bunit SB addr map */
1229 #define BUNIT_REG_BISOC 0x11
1231 #define PUNIT_REG_DSPFREQ 0x36
1232 #define DSPFREQSTAT_SHIFT_CHV 24
1233 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1234 #define DSPFREQGUAR_SHIFT_CHV 8
1235 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1236 #define DSPFREQSTAT_SHIFT 30
1237 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1238 #define DSPFREQGUAR_SHIFT 14
1239 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1240 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1241 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1242 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
1243 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1244 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1245 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1246 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1247 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1248 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1249 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1250 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1251 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1252 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1253 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1254 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1257 * i915_power_well_id:
1259 * Platform specific IDs used to look up power wells and - except for custom
1260 * power wells - to define request/status register flag bit positions. As such
1261 * the set of IDs on a given platform must be unique and except for custom
1262 * power wells their value must stay fixed.
1264 enum i915_power_well_id {
1267 * - custom power well
1269 I830_DISP_PW_PIPES = 0,
1273 * - PUNIT_REG_PWRGT_CTRL (bit: id*2),
1274 * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
1276 PUNIT_POWER_WELL_RENDER = 0,
1277 PUNIT_POWER_WELL_MEDIA = 1,
1278 PUNIT_POWER_WELL_DISP2D = 3,
1279 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
1280 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
1281 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
1282 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
1283 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
1284 PUNIT_POWER_WELL_DPIO_RX0 = 10,
1285 PUNIT_POWER_WELL_DPIO_RX1 = 11,
1286 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
1287 /* - custom power well */
1288 CHV_DISP_PW_PIPE_A, /* 13 */
1292 * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
1294 HSW_DISP_PW_GLOBAL = 15,
1298 * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
1300 SKL_DISP_PW_MISC_IO = 0,
1301 SKL_DISP_PW_DDI_A_E,
1302 GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
1303 CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
1307 CNL_DISP_PW_DDI_F = 6,
1309 GLK_DISP_PW_AUX_A = 8,
1312 CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
1313 CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
1314 CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
1321 /* - custom power wells */
1325 GLK_DPIO_CMN_C, /* 19 */
1328 * Multiple platforms.
1329 * Must start following the highest ID of any platform.
1330 * - custom power wells
1332 I915_DISP_PW_ALWAYS_ON = 20,
1335 #define PUNIT_REG_PWRGT_CTRL 0x60
1336 #define PUNIT_REG_PWRGT_STATUS 0x61
1337 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
1338 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
1339 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
1340 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
1341 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
1343 #define PUNIT_REG_GPU_LFM 0xd3
1344 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
1345 #define PUNIT_REG_GPU_FREQ_STS 0xd8
1346 #define GPLLENABLE (1<<4)
1347 #define GENFREQSTATUS (1<<0)
1348 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1349 #define PUNIT_REG_CZ_TIMESTAMP 0xce
1351 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1352 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1354 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1355 #define FB_GFX_FREQ_FUSE_MASK 0xff
1356 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1357 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1358 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1360 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1361 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1363 #define PUNIT_REG_DDR_SETUP2 0x139
1364 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1365 #define FORCE_DDR_LOW_FREQ (1 << 1)
1366 #define FORCE_DDR_HIGH_FREQ (1 << 0)
1368 #define PUNIT_GPU_STATUS_REG 0xdb
1369 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1370 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1371 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1372 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1374 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1375 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1376 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1378 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1379 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1380 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1381 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1382 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1383 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1384 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1385 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1386 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1387 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1389 #define VLV_TURBO_SOC_OVERRIDE 0x04
1390 #define VLV_OVERRIDE_EN 1
1391 #define VLV_SOC_TDP_EN (1 << 1)
1392 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1393 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1395 /* vlv2 north clock has */
1396 #define CCK_FUSE_REG 0x8
1397 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
1398 #define CCK_REG_DSI_PLL_FUSE 0x44
1399 #define CCK_REG_DSI_PLL_CONTROL 0x48
1400 #define DSI_PLL_VCO_EN (1 << 31)
1401 #define DSI_PLL_LDO_GATE (1 << 30)
1402 #define DSI_PLL_P1_POST_DIV_SHIFT 17
1403 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1404 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1405 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1406 #define DSI_PLL_MUX_MASK (3 << 9)
1407 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1408 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1409 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1410 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1411 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1412 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1413 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1414 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1415 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1416 #define DSI_PLL_LOCK (1 << 0)
1417 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
1418 #define DSI_PLL_LFSR (1 << 31)
1419 #define DSI_PLL_FRACTION_EN (1 << 30)
1420 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
1421 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1422 #define DSI_PLL_USYNC_CNT_SHIFT 18
1423 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1424 #define DSI_PLL_N1_DIV_SHIFT 16
1425 #define DSI_PLL_N1_DIV_MASK (3 << 16)
1426 #define DSI_PLL_M1_DIV_SHIFT 0
1427 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1428 #define CCK_CZ_CLOCK_CONTROL 0x62
1429 #define CCK_GPLL_CLOCK_CONTROL 0x67
1430 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1431 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1432 #define CCK_TRUNK_FORCE_ON (1 << 17)
1433 #define CCK_TRUNK_FORCE_OFF (1 << 16)
1434 #define CCK_FREQUENCY_STATUS (0x1f << 8)
1435 #define CCK_FREQUENCY_STATUS_SHIFT 8
1436 #define CCK_FREQUENCY_VALUES (0x1f << 0)
1438 /* DPIO registers */
1439 #define DPIO_DEVFN 0
1441 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1442 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
1443 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
1444 #define DPIO_SFR_BYPASS (1<<1)
1445 #define DPIO_CMNRST (1<<0)
1447 #define DPIO_PHY(pipe) ((pipe) >> 1)
1448 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1451 * Per pipe/PLL DPIO regs
1453 #define _VLV_PLL_DW3_CH0 0x800c
1454 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
1455 #define DPIO_POST_DIV_DAC 0
1456 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1457 #define DPIO_POST_DIV_LVDS1 2
1458 #define DPIO_POST_DIV_LVDS2 3
1459 #define DPIO_K_SHIFT (24) /* 4 bits */
1460 #define DPIO_P1_SHIFT (21) /* 3 bits */
1461 #define DPIO_P2_SHIFT (16) /* 5 bits */
1462 #define DPIO_N_SHIFT (12) /* 4 bits */
1463 #define DPIO_ENABLE_CALIBRATION (1<<11)
1464 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
1465 #define DPIO_M2DIV_MASK 0xff
1466 #define _VLV_PLL_DW3_CH1 0x802c
1467 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1469 #define _VLV_PLL_DW5_CH0 0x8014
1470 #define DPIO_REFSEL_OVERRIDE 27
1471 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
1472 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
1473 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
1474 #define DPIO_PLL_REFCLK_SEL_MASK 3
1475 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1476 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
1477 #define _VLV_PLL_DW5_CH1 0x8034
1478 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1480 #define _VLV_PLL_DW7_CH0 0x801c
1481 #define _VLV_PLL_DW7_CH1 0x803c
1482 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1484 #define _VLV_PLL_DW8_CH0 0x8040
1485 #define _VLV_PLL_DW8_CH1 0x8060
1486 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1488 #define VLV_PLL_DW9_BCAST 0xc044
1489 #define _VLV_PLL_DW9_CH0 0x8044
1490 #define _VLV_PLL_DW9_CH1 0x8064
1491 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1493 #define _VLV_PLL_DW10_CH0 0x8048
1494 #define _VLV_PLL_DW10_CH1 0x8068
1495 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1497 #define _VLV_PLL_DW11_CH0 0x804c
1498 #define _VLV_PLL_DW11_CH1 0x806c
1499 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1501 /* Spec for ref block start counts at DW10 */
1502 #define VLV_REF_DW13 0x80ac
1504 #define VLV_CMN_DW0 0x8100
1507 * Per DDI channel DPIO regs
1510 #define _VLV_PCS_DW0_CH0 0x8200
1511 #define _VLV_PCS_DW0_CH1 0x8400
1512 #define DPIO_PCS_TX_LANE2_RESET (1<<16)
1513 #define DPIO_PCS_TX_LANE1_RESET (1<<7)
1514 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
1515 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
1516 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1518 #define _VLV_PCS01_DW0_CH0 0x200
1519 #define _VLV_PCS23_DW0_CH0 0x400
1520 #define _VLV_PCS01_DW0_CH1 0x2600
1521 #define _VLV_PCS23_DW0_CH1 0x2800
1522 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1523 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1525 #define _VLV_PCS_DW1_CH0 0x8204
1526 #define _VLV_PCS_DW1_CH1 0x8404
1527 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
1528 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
1529 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
1530 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1531 #define DPIO_PCS_CLK_SOFT_RESET (1<<5)
1532 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1534 #define _VLV_PCS01_DW1_CH0 0x204
1535 #define _VLV_PCS23_DW1_CH0 0x404
1536 #define _VLV_PCS01_DW1_CH1 0x2604
1537 #define _VLV_PCS23_DW1_CH1 0x2804
1538 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1539 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1541 #define _VLV_PCS_DW8_CH0 0x8220
1542 #define _VLV_PCS_DW8_CH1 0x8420
1543 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1544 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1545 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1547 #define _VLV_PCS01_DW8_CH0 0x0220
1548 #define _VLV_PCS23_DW8_CH0 0x0420
1549 #define _VLV_PCS01_DW8_CH1 0x2620
1550 #define _VLV_PCS23_DW8_CH1 0x2820
1551 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1552 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1554 #define _VLV_PCS_DW9_CH0 0x8224
1555 #define _VLV_PCS_DW9_CH1 0x8424
1556 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
1557 #define DPIO_PCS_TX2MARGIN_000 (0<<13)
1558 #define DPIO_PCS_TX2MARGIN_101 (1<<13)
1559 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
1560 #define DPIO_PCS_TX1MARGIN_000 (0<<10)
1561 #define DPIO_PCS_TX1MARGIN_101 (1<<10)
1562 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1564 #define _VLV_PCS01_DW9_CH0 0x224
1565 #define _VLV_PCS23_DW9_CH0 0x424
1566 #define _VLV_PCS01_DW9_CH1 0x2624
1567 #define _VLV_PCS23_DW9_CH1 0x2824
1568 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1569 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1571 #define _CHV_PCS_DW10_CH0 0x8228
1572 #define _CHV_PCS_DW10_CH1 0x8428
1573 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
1574 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
1575 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
1576 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
1577 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
1578 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
1579 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
1580 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
1581 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1583 #define _VLV_PCS01_DW10_CH0 0x0228
1584 #define _VLV_PCS23_DW10_CH0 0x0428
1585 #define _VLV_PCS01_DW10_CH1 0x2628
1586 #define _VLV_PCS23_DW10_CH1 0x2828
1587 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1588 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1590 #define _VLV_PCS_DW11_CH0 0x822c
1591 #define _VLV_PCS_DW11_CH1 0x842c
1592 #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24)
1593 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
1594 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
1595 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
1596 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1598 #define _VLV_PCS01_DW11_CH0 0x022c
1599 #define _VLV_PCS23_DW11_CH0 0x042c
1600 #define _VLV_PCS01_DW11_CH1 0x262c
1601 #define _VLV_PCS23_DW11_CH1 0x282c
1602 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1603 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1605 #define _VLV_PCS01_DW12_CH0 0x0230
1606 #define _VLV_PCS23_DW12_CH0 0x0430
1607 #define _VLV_PCS01_DW12_CH1 0x2630
1608 #define _VLV_PCS23_DW12_CH1 0x2830
1609 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1610 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1612 #define _VLV_PCS_DW12_CH0 0x8230
1613 #define _VLV_PCS_DW12_CH1 0x8430
1614 #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20)
1615 #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16)
1616 #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8)
1617 #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6)
1618 #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0)
1619 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1621 #define _VLV_PCS_DW14_CH0 0x8238
1622 #define _VLV_PCS_DW14_CH1 0x8438
1623 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1625 #define _VLV_PCS_DW23_CH0 0x825c
1626 #define _VLV_PCS_DW23_CH1 0x845c
1627 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1629 #define _VLV_TX_DW2_CH0 0x8288
1630 #define _VLV_TX_DW2_CH1 0x8488
1631 #define DPIO_SWING_MARGIN000_SHIFT 16
1632 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1633 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1634 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1636 #define _VLV_TX_DW3_CH0 0x828c
1637 #define _VLV_TX_DW3_CH1 0x848c
1638 /* The following bit for CHV phy */
1639 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
1640 #define DPIO_SWING_MARGIN101_SHIFT 16
1641 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1642 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1644 #define _VLV_TX_DW4_CH0 0x8290
1645 #define _VLV_TX_DW4_CH1 0x8490
1646 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
1647 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1648 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
1649 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1650 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1652 #define _VLV_TX3_DW4_CH0 0x690
1653 #define _VLV_TX3_DW4_CH1 0x2a90
1654 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1656 #define _VLV_TX_DW5_CH0 0x8294
1657 #define _VLV_TX_DW5_CH1 0x8494
1658 #define DPIO_TX_OCALINIT_EN (1<<31)
1659 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1661 #define _VLV_TX_DW11_CH0 0x82ac
1662 #define _VLV_TX_DW11_CH1 0x84ac
1663 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1665 #define _VLV_TX_DW14_CH0 0x82b8
1666 #define _VLV_TX_DW14_CH1 0x84b8
1667 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1669 /* CHV dpPhy registers */
1670 #define _CHV_PLL_DW0_CH0 0x8000
1671 #define _CHV_PLL_DW0_CH1 0x8180
1672 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1674 #define _CHV_PLL_DW1_CH0 0x8004
1675 #define _CHV_PLL_DW1_CH1 0x8184
1676 #define DPIO_CHV_N_DIV_SHIFT 8
1677 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1678 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1680 #define _CHV_PLL_DW2_CH0 0x8008
1681 #define _CHV_PLL_DW2_CH1 0x8188
1682 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1684 #define _CHV_PLL_DW3_CH0 0x800c
1685 #define _CHV_PLL_DW3_CH1 0x818c
1686 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1687 #define DPIO_CHV_FIRST_MOD (0 << 8)
1688 #define DPIO_CHV_SECOND_MOD (1 << 8)
1689 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1690 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1691 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1693 #define _CHV_PLL_DW6_CH0 0x8018
1694 #define _CHV_PLL_DW6_CH1 0x8198
1695 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
1696 #define DPIO_CHV_INT_COEFF_SHIFT 8
1697 #define DPIO_CHV_PROP_COEFF_SHIFT 0
1698 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1700 #define _CHV_PLL_DW8_CH0 0x8020
1701 #define _CHV_PLL_DW8_CH1 0x81A0
1702 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1703 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1704 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1706 #define _CHV_PLL_DW9_CH0 0x8024
1707 #define _CHV_PLL_DW9_CH1 0x81A4
1708 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1709 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1710 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1711 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1713 #define _CHV_CMN_DW0_CH0 0x8100
1714 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1715 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1716 #define DPIO_ALLDL_POWERDOWN (1 << 1)
1717 #define DPIO_ANYDL_POWERDOWN (1 << 0)
1719 #define _CHV_CMN_DW5_CH0 0x8114
1720 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1721 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1722 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1723 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
1724 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1725 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1726 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
1727 #define CHV_BUFLEFTENA1_MASK (3 << 22)
1729 #define _CHV_CMN_DW13_CH0 0x8134
1730 #define _CHV_CMN_DW0_CH1 0x8080
1731 #define DPIO_CHV_S1_DIV_SHIFT 21
1732 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1733 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1734 #define DPIO_CHV_K_DIV_SHIFT 4
1735 #define DPIO_PLL_FREQLOCK (1 << 1)
1736 #define DPIO_PLL_LOCK (1 << 0)
1737 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1739 #define _CHV_CMN_DW14_CH0 0x8138
1740 #define _CHV_CMN_DW1_CH1 0x8084
1741 #define DPIO_AFC_RECAL (1 << 14)
1742 #define DPIO_DCLKP_EN (1 << 13)
1743 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1744 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1745 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1746 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1747 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1748 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1749 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1750 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1751 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1753 #define _CHV_CMN_DW19_CH0 0x814c
1754 #define _CHV_CMN_DW6_CH1 0x8098
1755 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1756 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1757 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1758 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1760 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1762 #define CHV_CMN_DW28 0x8170
1763 #define DPIO_CL1POWERDOWNEN (1 << 23)
1764 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1765 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1766 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1767 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1768 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1770 #define CHV_CMN_DW30 0x8178
1771 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1772 #define DPIO_LRC_BYPASS (1 << 3)
1774 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1775 (lane) * 0x200 + (offset))
1777 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1778 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1779 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1780 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1781 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1782 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1783 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1784 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1785 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1786 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1787 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1788 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1789 #define DPIO_FRC_LATENCY_SHFIT 8
1790 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1791 #define DPIO_UPAR_SHIFT 30
1793 /* BXT PHY registers */
1794 #define _BXT_PHY0_BASE 0x6C000
1795 #define _BXT_PHY1_BASE 0x162000
1796 #define _BXT_PHY2_BASE 0x163000
1797 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1801 #define _BXT_PHY(phy, reg) \
1802 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1804 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1805 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1806 (reg_ch1) - _BXT_PHY0_BASE))
1807 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1808 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1810 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1811 #define MIPIO_RST_CTRL (1 << 2)
1813 #define _BXT_PHY_CTL_DDI_A 0x64C00
1814 #define _BXT_PHY_CTL_DDI_B 0x64C10
1815 #define _BXT_PHY_CTL_DDI_C 0x64C20
1816 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1817 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1818 #define BXT_PHY_LANE_ENABLED (1 << 8)
1819 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1822 #define _PHY_CTL_FAMILY_EDP 0x64C80
1823 #define _PHY_CTL_FAMILY_DDI 0x64C90
1824 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
1825 #define COMMON_RESET_DIS (1 << 31)
1826 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1827 _PHY_CTL_FAMILY_EDP, \
1828 _PHY_CTL_FAMILY_DDI_C)
1830 /* BXT PHY PLL registers */
1831 #define _PORT_PLL_A 0x46074
1832 #define _PORT_PLL_B 0x46078
1833 #define _PORT_PLL_C 0x4607c
1834 #define PORT_PLL_ENABLE (1 << 31)
1835 #define PORT_PLL_LOCK (1 << 30)
1836 #define PORT_PLL_REF_SEL (1 << 27)
1837 #define PORT_PLL_POWER_ENABLE (1 << 26)
1838 #define PORT_PLL_POWER_STATE (1 << 25)
1839 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1841 #define _PORT_PLL_EBB_0_A 0x162034
1842 #define _PORT_PLL_EBB_0_B 0x6C034
1843 #define _PORT_PLL_EBB_0_C 0x6C340
1844 #define PORT_PLL_P1_SHIFT 13
1845 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1846 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1847 #define PORT_PLL_P2_SHIFT 8
1848 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1849 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1850 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1851 _PORT_PLL_EBB_0_B, \
1854 #define _PORT_PLL_EBB_4_A 0x162038
1855 #define _PORT_PLL_EBB_4_B 0x6C038
1856 #define _PORT_PLL_EBB_4_C 0x6C344
1857 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1858 #define PORT_PLL_RECALIBRATE (1 << 14)
1859 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1860 _PORT_PLL_EBB_4_B, \
1863 #define _PORT_PLL_0_A 0x162100
1864 #define _PORT_PLL_0_B 0x6C100
1865 #define _PORT_PLL_0_C 0x6C380
1867 #define PORT_PLL_M2_MASK 0xFF
1869 #define PORT_PLL_N_SHIFT 8
1870 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1871 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1873 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1875 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1877 #define PORT_PLL_PROP_COEFF_MASK 0xF
1878 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1879 #define PORT_PLL_INT_COEFF(x) ((x) << 8)
1880 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1881 #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1883 #define PORT_PLL_TARGET_CNT_MASK 0x3FF
1885 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1886 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1888 #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
1889 #define PORT_PLL_DCO_AMP_DEFAULT 15
1890 #define PORT_PLL_DCO_AMP_MASK 0x3c00
1891 #define PORT_PLL_DCO_AMP(x) ((x)<<10)
1892 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1895 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1898 /* BXT PHY common lane registers */
1899 #define _PORT_CL1CM_DW0_A 0x162000
1900 #define _PORT_CL1CM_DW0_BC 0x6C000
1901 #define PHY_POWER_GOOD (1 << 16)
1902 #define PHY_RESERVED (1 << 7)
1903 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1905 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1906 #define CL_POWER_DOWN_ENABLE (1 << 4)
1907 #define SUS_CLOCK_CONFIG (3 << 0)
1909 #define _PORT_CL1CM_DW9_A 0x162024
1910 #define _PORT_CL1CM_DW9_BC 0x6C024
1911 #define IREF0RC_OFFSET_SHIFT 8
1912 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1913 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1915 #define _PORT_CL1CM_DW10_A 0x162028
1916 #define _PORT_CL1CM_DW10_BC 0x6C028
1917 #define IREF1RC_OFFSET_SHIFT 8
1918 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1919 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1921 #define _PORT_CL1CM_DW28_A 0x162070
1922 #define _PORT_CL1CM_DW28_BC 0x6C070
1923 #define OCL1_POWER_DOWN_EN (1 << 23)
1924 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1925 #define SUS_CLK_CONFIG 0x3
1926 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1928 #define _PORT_CL1CM_DW30_A 0x162078
1929 #define _PORT_CL1CM_DW30_BC 0x6C078
1930 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1931 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1933 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1934 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1935 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1936 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1937 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1938 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1939 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1940 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1941 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1942 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1943 #define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \
1944 _CNL_PORT_PCS_DW1_GRP_AE, \
1945 _CNL_PORT_PCS_DW1_GRP_B, \
1946 _CNL_PORT_PCS_DW1_GRP_C, \
1947 _CNL_PORT_PCS_DW1_GRP_D, \
1948 _CNL_PORT_PCS_DW1_GRP_AE, \
1949 _CNL_PORT_PCS_DW1_GRP_F)
1950 #define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \
1951 _CNL_PORT_PCS_DW1_LN0_AE, \
1952 _CNL_PORT_PCS_DW1_LN0_B, \
1953 _CNL_PORT_PCS_DW1_LN0_C, \
1954 _CNL_PORT_PCS_DW1_LN0_D, \
1955 _CNL_PORT_PCS_DW1_LN0_AE, \
1956 _CNL_PORT_PCS_DW1_LN0_F)
1957 #define COMMON_KEEPER_EN (1 << 26)
1959 #define _CNL_PORT_TX_DW2_GRP_AE 0x162348
1960 #define _CNL_PORT_TX_DW2_GRP_B 0x1623C8
1961 #define _CNL_PORT_TX_DW2_GRP_C 0x162B48
1962 #define _CNL_PORT_TX_DW2_GRP_D 0x162BC8
1963 #define _CNL_PORT_TX_DW2_GRP_F 0x162A48
1964 #define _CNL_PORT_TX_DW2_LN0_AE 0x162448
1965 #define _CNL_PORT_TX_DW2_LN0_B 0x162648
1966 #define _CNL_PORT_TX_DW2_LN0_C 0x162C48
1967 #define _CNL_PORT_TX_DW2_LN0_D 0x162E48
1968 #define _CNL_PORT_TX_DW2_LN0_F 0x162848
1969 #define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \
1970 _CNL_PORT_TX_DW2_GRP_AE, \
1971 _CNL_PORT_TX_DW2_GRP_B, \
1972 _CNL_PORT_TX_DW2_GRP_C, \
1973 _CNL_PORT_TX_DW2_GRP_D, \
1974 _CNL_PORT_TX_DW2_GRP_AE, \
1975 _CNL_PORT_TX_DW2_GRP_F)
1976 #define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \
1977 _CNL_PORT_TX_DW2_LN0_AE, \
1978 _CNL_PORT_TX_DW2_LN0_B, \
1979 _CNL_PORT_TX_DW2_LN0_C, \
1980 _CNL_PORT_TX_DW2_LN0_D, \
1981 _CNL_PORT_TX_DW2_LN0_AE, \
1982 _CNL_PORT_TX_DW2_LN0_F)
1983 #define SWING_SEL_UPPER(x) ((x >> 3) << 15)
1984 #define SWING_SEL_UPPER_MASK (1 << 15)
1985 #define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
1986 #define SWING_SEL_LOWER_MASK (0x7 << 11)
1987 #define RCOMP_SCALAR(x) ((x) << 0)
1988 #define RCOMP_SCALAR_MASK (0xFF << 0)
1990 #define _CNL_PORT_TX_DW4_GRP_AE 0x162350
1991 #define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
1992 #define _CNL_PORT_TX_DW4_GRP_C 0x162B50
1993 #define _CNL_PORT_TX_DW4_GRP_D 0x162BD0
1994 #define _CNL_PORT_TX_DW4_GRP_F 0x162A50
1995 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450
1996 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
1997 #define _CNL_PORT_TX_DW4_LN0_B 0x162650
1998 #define _CNL_PORT_TX_DW4_LN0_C 0x162C50
1999 #define _CNL_PORT_TX_DW4_LN0_D 0x162E50
2000 #define _CNL_PORT_TX_DW4_LN0_F 0x162850
2001 #define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \
2002 _CNL_PORT_TX_DW4_GRP_AE, \
2003 _CNL_PORT_TX_DW4_GRP_B, \
2004 _CNL_PORT_TX_DW4_GRP_C, \
2005 _CNL_PORT_TX_DW4_GRP_D, \
2006 _CNL_PORT_TX_DW4_GRP_AE, \
2007 _CNL_PORT_TX_DW4_GRP_F)
2008 #define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \
2009 _CNL_PORT_TX_DW4_LN0_AE, \
2010 _CNL_PORT_TX_DW4_LN1_AE, \
2011 _CNL_PORT_TX_DW4_LN0_B, \
2012 _CNL_PORT_TX_DW4_LN0_C, \
2013 _CNL_PORT_TX_DW4_LN0_D, \
2014 _CNL_PORT_TX_DW4_LN0_AE, \
2015 _CNL_PORT_TX_DW4_LN0_F)
2016 #define LOADGEN_SELECT (1 << 31)
2017 #define POST_CURSOR_1(x) ((x) << 12)
2018 #define POST_CURSOR_1_MASK (0x3F << 12)
2019 #define POST_CURSOR_2(x) ((x) << 6)
2020 #define POST_CURSOR_2_MASK (0x3F << 6)
2021 #define CURSOR_COEFF(x) ((x) << 0)
2022 #define CURSOR_COEFF_MASK (0x3F << 0)
2024 #define _CNL_PORT_TX_DW5_GRP_AE 0x162354
2025 #define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
2026 #define _CNL_PORT_TX_DW5_GRP_C 0x162B54
2027 #define _CNL_PORT_TX_DW5_GRP_D 0x162BD4
2028 #define _CNL_PORT_TX_DW5_GRP_F 0x162A54
2029 #define _CNL_PORT_TX_DW5_LN0_AE 0x162454
2030 #define _CNL_PORT_TX_DW5_LN0_B 0x162654
2031 #define _CNL_PORT_TX_DW5_LN0_C 0x162C54
2032 #define _CNL_PORT_TX_DW5_LN0_D 0x162ED4
2033 #define _CNL_PORT_TX_DW5_LN0_F 0x162854
2034 #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
2035 _CNL_PORT_TX_DW5_GRP_AE, \
2036 _CNL_PORT_TX_DW5_GRP_B, \
2037 _CNL_PORT_TX_DW5_GRP_C, \
2038 _CNL_PORT_TX_DW5_GRP_D, \
2039 _CNL_PORT_TX_DW5_GRP_AE, \
2040 _CNL_PORT_TX_DW5_GRP_F)
2041 #define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \
2042 _CNL_PORT_TX_DW5_LN0_AE, \
2043 _CNL_PORT_TX_DW5_LN0_B, \
2044 _CNL_PORT_TX_DW5_LN0_C, \
2045 _CNL_PORT_TX_DW5_LN0_D, \
2046 _CNL_PORT_TX_DW5_LN0_AE, \
2047 _CNL_PORT_TX_DW5_LN0_F)
2048 #define TX_TRAINING_EN (1 << 31)
2049 #define TAP3_DISABLE (1 << 29)
2050 #define SCALING_MODE_SEL(x) ((x) << 18)
2051 #define SCALING_MODE_SEL_MASK (0x7 << 18)
2052 #define RTERM_SELECT(x) ((x) << 3)
2053 #define RTERM_SELECT_MASK (0x7 << 3)
2055 #define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
2056 #define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
2057 #define _CNL_PORT_TX_DW7_GRP_C 0x162B5C
2058 #define _CNL_PORT_TX_DW7_GRP_D 0x162BDC
2059 #define _CNL_PORT_TX_DW7_GRP_F 0x162A5C
2060 #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
2061 #define _CNL_PORT_TX_DW7_LN0_B 0x16265C
2062 #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
2063 #define _CNL_PORT_TX_DW7_LN0_D 0x162EDC
2064 #define _CNL_PORT_TX_DW7_LN0_F 0x16285C
2065 #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
2066 _CNL_PORT_TX_DW7_GRP_AE, \
2067 _CNL_PORT_TX_DW7_GRP_B, \
2068 _CNL_PORT_TX_DW7_GRP_C, \
2069 _CNL_PORT_TX_DW7_GRP_D, \
2070 _CNL_PORT_TX_DW7_GRP_AE, \
2071 _CNL_PORT_TX_DW7_GRP_F)
2072 #define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \
2073 _CNL_PORT_TX_DW7_LN0_AE, \
2074 _CNL_PORT_TX_DW7_LN0_B, \
2075 _CNL_PORT_TX_DW7_LN0_C, \
2076 _CNL_PORT_TX_DW7_LN0_D, \
2077 _CNL_PORT_TX_DW7_LN0_AE, \
2078 _CNL_PORT_TX_DW7_LN0_F)
2079 #define N_SCALAR(x) ((x) << 24)
2080 #define N_SCALAR_MASK (0x7F << 24)
2082 /* The spec defines this only for BXT PHY0, but lets assume that this
2083 * would exist for PHY1 too if it had a second channel.
2085 #define _PORT_CL2CM_DW6_A 0x162358
2086 #define _PORT_CL2CM_DW6_BC 0x6C358
2087 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2088 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2090 #define CNL_PORT_COMP_DW0 _MMIO(0x162100)
2091 #define COMP_INIT (1 << 31)
2092 #define CNL_PORT_COMP_DW1 _MMIO(0x162104)
2093 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
2094 #define PROCESS_INFO_DOT_0 (0 << 26)
2095 #define PROCESS_INFO_DOT_1 (1 << 26)
2096 #define PROCESS_INFO_DOT_4 (2 << 26)
2097 #define PROCESS_INFO_MASK (7 << 26)
2098 #define PROCESS_INFO_SHIFT 26
2099 #define VOLTAGE_INFO_0_85V (0 << 24)
2100 #define VOLTAGE_INFO_0_95V (1 << 24)
2101 #define VOLTAGE_INFO_1_05V (2 << 24)
2102 #define VOLTAGE_INFO_MASK (3 << 24)
2103 #define VOLTAGE_INFO_SHIFT 24
2104 #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
2105 #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
2107 /* BXT PHY Ref registers */
2108 #define _PORT_REF_DW3_A 0x16218C
2109 #define _PORT_REF_DW3_BC 0x6C18C
2110 #define GRC_DONE (1 << 22)
2111 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
2113 #define _PORT_REF_DW6_A 0x162198
2114 #define _PORT_REF_DW6_BC 0x6C198
2115 #define GRC_CODE_SHIFT 24
2116 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
2117 #define GRC_CODE_FAST_SHIFT 16
2118 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
2119 #define GRC_CODE_SLOW_SHIFT 8
2120 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2121 #define GRC_CODE_NOM_MASK 0xFF
2122 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
2124 #define _PORT_REF_DW8_A 0x1621A0
2125 #define _PORT_REF_DW8_BC 0x6C1A0
2126 #define GRC_DIS (1 << 15)
2127 #define GRC_RDY_OVRD (1 << 1)
2128 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
2130 /* BXT PHY PCS registers */
2131 #define _PORT_PCS_DW10_LN01_A 0x162428
2132 #define _PORT_PCS_DW10_LN01_B 0x6C428
2133 #define _PORT_PCS_DW10_LN01_C 0x6C828
2134 #define _PORT_PCS_DW10_GRP_A 0x162C28
2135 #define _PORT_PCS_DW10_GRP_B 0x6CC28
2136 #define _PORT_PCS_DW10_GRP_C 0x6CE28
2137 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2138 _PORT_PCS_DW10_LN01_B, \
2139 _PORT_PCS_DW10_LN01_C)
2140 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2141 _PORT_PCS_DW10_GRP_B, \
2142 _PORT_PCS_DW10_GRP_C)
2144 #define TX2_SWING_CALC_INIT (1 << 31)
2145 #define TX1_SWING_CALC_INIT (1 << 30)
2147 #define _PORT_PCS_DW12_LN01_A 0x162430
2148 #define _PORT_PCS_DW12_LN01_B 0x6C430
2149 #define _PORT_PCS_DW12_LN01_C 0x6C830
2150 #define _PORT_PCS_DW12_LN23_A 0x162630
2151 #define _PORT_PCS_DW12_LN23_B 0x6C630
2152 #define _PORT_PCS_DW12_LN23_C 0x6CA30
2153 #define _PORT_PCS_DW12_GRP_A 0x162c30
2154 #define _PORT_PCS_DW12_GRP_B 0x6CC30
2155 #define _PORT_PCS_DW12_GRP_C 0x6CE30
2156 #define LANESTAGGER_STRAP_OVRD (1 << 6)
2157 #define LANE_STAGGER_MASK 0x1F
2158 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2159 _PORT_PCS_DW12_LN01_B, \
2160 _PORT_PCS_DW12_LN01_C)
2161 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2162 _PORT_PCS_DW12_LN23_B, \
2163 _PORT_PCS_DW12_LN23_C)
2164 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2165 _PORT_PCS_DW12_GRP_B, \
2166 _PORT_PCS_DW12_GRP_C)
2168 /* BXT PHY TX registers */
2169 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2170 ((lane) & 1) * 0x80)
2172 #define _PORT_TX_DW2_LN0_A 0x162508
2173 #define _PORT_TX_DW2_LN0_B 0x6C508
2174 #define _PORT_TX_DW2_LN0_C 0x6C908
2175 #define _PORT_TX_DW2_GRP_A 0x162D08
2176 #define _PORT_TX_DW2_GRP_B 0x6CD08
2177 #define _PORT_TX_DW2_GRP_C 0x6CF08
2178 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2179 _PORT_TX_DW2_LN0_B, \
2181 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2182 _PORT_TX_DW2_GRP_B, \
2184 #define MARGIN_000_SHIFT 16
2185 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2186 #define UNIQ_TRANS_SCALE_SHIFT 8
2187 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2189 #define _PORT_TX_DW3_LN0_A 0x16250C
2190 #define _PORT_TX_DW3_LN0_B 0x6C50C
2191 #define _PORT_TX_DW3_LN0_C 0x6C90C
2192 #define _PORT_TX_DW3_GRP_A 0x162D0C
2193 #define _PORT_TX_DW3_GRP_B 0x6CD0C
2194 #define _PORT_TX_DW3_GRP_C 0x6CF0C
2195 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2196 _PORT_TX_DW3_LN0_B, \
2198 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2199 _PORT_TX_DW3_GRP_B, \
2201 #define SCALE_DCOMP_METHOD (1 << 26)
2202 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
2204 #define _PORT_TX_DW4_LN0_A 0x162510
2205 #define _PORT_TX_DW4_LN0_B 0x6C510
2206 #define _PORT_TX_DW4_LN0_C 0x6C910
2207 #define _PORT_TX_DW4_GRP_A 0x162D10
2208 #define _PORT_TX_DW4_GRP_B 0x6CD10
2209 #define _PORT_TX_DW4_GRP_C 0x6CF10
2210 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2211 _PORT_TX_DW4_LN0_B, \
2213 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2214 _PORT_TX_DW4_GRP_B, \
2216 #define DEEMPH_SHIFT 24
2217 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2219 #define _PORT_TX_DW5_LN0_A 0x162514
2220 #define _PORT_TX_DW5_LN0_B 0x6C514
2221 #define _PORT_TX_DW5_LN0_C 0x6C914
2222 #define _PORT_TX_DW5_GRP_A 0x162D14
2223 #define _PORT_TX_DW5_GRP_B 0x6CD14
2224 #define _PORT_TX_DW5_GRP_C 0x6CF14
2225 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2226 _PORT_TX_DW5_LN0_B, \
2228 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2229 _PORT_TX_DW5_GRP_B, \
2231 #define DCC_DELAY_RANGE_1 (1 << 9)
2232 #define DCC_DELAY_RANGE_2 (1 << 8)
2234 #define _PORT_TX_DW14_LN0_A 0x162538
2235 #define _PORT_TX_DW14_LN0_B 0x6C538
2236 #define _PORT_TX_DW14_LN0_C 0x6C938
2237 #define LATENCY_OPTIM_SHIFT 30
2238 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
2239 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2240 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2241 _PORT_TX_DW14_LN0_C) + \
2242 _BXT_LANE_OFFSET(lane))
2244 /* UAIMI scratch pad register 1 */
2245 #define UAIMI_SPR1 _MMIO(0x4F074)
2246 /* SKL VccIO mask */
2247 #define SKL_VCCIO_MASK 0x1
2248 /* SKL balance leg register */
2249 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
2250 /* I_boost values */
2251 #define BALANCE_LEG_SHIFT(port) (8+3*(port))
2252 #define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
2253 /* Balance leg disable bits */
2254 #define BALANCE_LEG_DISABLE_SHIFT 23
2255 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
2259 * [0-7] @ 0x2000 gen2,gen3
2260 * [8-15] @ 0x3000 945,g33,pnv
2262 * [0-15] @ 0x3000 gen4,gen5
2264 * [0-15] @ 0x100000 gen6,vlv,chv
2265 * [0-31] @ 0x100000 gen7+
2267 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2268 #define I830_FENCE_START_MASK 0x07f80000
2269 #define I830_FENCE_TILING_Y_SHIFT 12
2270 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2271 #define I830_FENCE_PITCH_SHIFT 4
2272 #define I830_FENCE_REG_VALID (1<<0)
2273 #define I915_FENCE_MAX_PITCH_VAL 4
2274 #define I830_FENCE_MAX_PITCH_VAL 6
2275 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
2277 #define I915_FENCE_START_MASK 0x0ff00000
2278 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2280 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2281 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
2282 #define I965_FENCE_PITCH_SHIFT 2
2283 #define I965_FENCE_TILING_Y_SHIFT 1
2284 #define I965_FENCE_REG_VALID (1<<0)
2285 #define I965_FENCE_MAX_PITCH_VAL 0x0400
2287 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2288 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
2289 #define GEN6_FENCE_PITCH_SHIFT 32
2290 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
2293 /* control register for cpu gtt access */
2294 #define TILECTL _MMIO(0x101000)
2295 #define TILECTL_SWZCTL (1 << 0)
2296 #define TILECTL_TLBPF (1 << 1)
2297 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2298 #define TILECTL_BACKSNOOP_DIS (1 << 3)
2301 * Instruction and interrupt control regs
2303 #define PGTBL_CTL _MMIO(0x02020)
2304 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2305 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
2306 #define PGTBL_ER _MMIO(0x02024)
2307 #define PRB0_BASE (0x2030-0x30)
2308 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
2309 #define PRB2_BASE (0x2050-0x30) /* gen3 */
2310 #define SRB0_BASE (0x2100-0x30) /* gen2 */
2311 #define SRB1_BASE (0x2110-0x30) /* gen2 */
2312 #define SRB2_BASE (0x2120-0x30) /* 830 */
2313 #define SRB3_BASE (0x2130-0x30) /* 830 */
2314 #define RENDER_RING_BASE 0x02000
2315 #define BSD_RING_BASE 0x04000
2316 #define GEN6_BSD_RING_BASE 0x12000
2317 #define GEN8_BSD2_RING_BASE 0x1c000
2318 #define VEBOX_RING_BASE 0x1a000
2319 #define BLT_RING_BASE 0x22000
2320 #define RING_TAIL(base) _MMIO((base)+0x30)
2321 #define RING_HEAD(base) _MMIO((base)+0x34)
2322 #define RING_START(base) _MMIO((base)+0x38)
2323 #define RING_CTL(base) _MMIO((base)+0x3c)
2324 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2325 #define RING_SYNC_0(base) _MMIO((base)+0x40)
2326 #define RING_SYNC_1(base) _MMIO((base)+0x44)
2327 #define RING_SYNC_2(base) _MMIO((base)+0x48)
2328 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2329 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2330 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2331 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2332 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2333 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2334 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2335 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2336 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2337 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2338 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2339 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2340 #define GEN6_NOSYNC INVALID_MMIO_REG
2341 #define RING_PSMI_CTL(base) _MMIO((base)+0x50)
2342 #define RING_MAX_IDLE(base) _MMIO((base)+0x54)
2343 #define RING_HWS_PGA(base) _MMIO((base)+0x80)
2344 #define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080)
2345 #define RING_RESET_CTL(base) _MMIO((base)+0xd0)
2346 #define RESET_CTL_REQUEST_RESET (1 << 0)
2347 #define RESET_CTL_READY_TO_RESET (1 << 1)
2349 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
2350 #define GTT_CACHE_EN_ALL 0xF0007FFF
2351 #define GEN7_WR_WATERMARK _MMIO(0x4028)
2352 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2353 #define ARB_MODE _MMIO(0x4030)
2354 #define ARB_MODE_SWIZZLE_SNB (1<<4)
2355 #define ARB_MODE_SWIZZLE_IVB (1<<5)
2356 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2357 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
2358 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2359 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
2360 #define GEN7_LRA_LIMITS_REG_NUM 13
2361 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2362 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2364 #define GAMTARBMODE _MMIO(0x04a08)
2365 #define ARB_MODE_BWGTLB_DISABLE (1<<9)
2366 #define ARB_MODE_SWIZZLE_BDW (1<<1)
2367 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2368 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id)
2369 #define GEN8_RING_FAULT_REG _MMIO(0x4094)
2370 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2371 #define RING_FAULT_GTTSEL_MASK (1<<11)
2372 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2373 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2374 #define RING_FAULT_VALID (1<<0)
2375 #define DONE_REG _MMIO(0x40b0)
2376 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2377 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2378 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index)*4)
2379 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2380 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2381 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2382 #define RING_ACTHD(base) _MMIO((base)+0x74)
2383 #define RING_ACTHD_UDW(base) _MMIO((base)+0x5c)
2384 #define RING_NOPID(base) _MMIO((base)+0x94)
2385 #define RING_IMR(base) _MMIO((base)+0xa8)
2386 #define RING_HWSTAM(base) _MMIO((base)+0x98)
2387 #define RING_TIMESTAMP(base) _MMIO((base)+0x358)
2388 #define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4)
2389 #define TAIL_ADDR 0x001FFFF8
2390 #define HEAD_WRAP_COUNT 0xFFE00000
2391 #define HEAD_WRAP_ONE 0x00200000
2392 #define HEAD_ADDR 0x001FFFFC
2393 #define RING_NR_PAGES 0x001FF000
2394 #define RING_REPORT_MASK 0x00000006
2395 #define RING_REPORT_64K 0x00000002
2396 #define RING_REPORT_128K 0x00000004
2397 #define RING_NO_REPORT 0x00000000
2398 #define RING_VALID_MASK 0x00000001
2399 #define RING_VALID 0x00000001
2400 #define RING_INVALID 0x00000000
2401 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
2402 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
2403 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
2405 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4)
2406 #define RING_MAX_NONPRIV_SLOTS 12
2408 #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2410 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2411 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
2413 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2414 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2416 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2417 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
2418 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
2421 #define PRB0_TAIL _MMIO(0x2030)
2422 #define PRB0_HEAD _MMIO(0x2034)
2423 #define PRB0_START _MMIO(0x2038)
2424 #define PRB0_CTL _MMIO(0x203c)
2425 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2426 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2427 #define PRB1_START _MMIO(0x2048) /* 915+ only */
2428 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */
2430 #define IPEIR_I965 _MMIO(0x2064)
2431 #define IPEHR_I965 _MMIO(0x2068)
2432 #define GEN7_SC_INSTDONE _MMIO(0x7100)
2433 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2434 #define GEN7_ROW_INSTDONE _MMIO(0xe164)
2435 #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2436 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2437 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2438 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2439 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2440 #define RING_IPEIR(base) _MMIO((base)+0x64)
2441 #define RING_IPEHR(base) _MMIO((base)+0x68)
2443 * On GEN4, only the render ring INSTDONE exists and has a different
2444 * layout than the GEN7+ version.
2445 * The GEN2 counterpart of this register is GEN2_INSTDONE.
2447 #define RING_INSTDONE(base) _MMIO((base)+0x6c)
2448 #define RING_INSTPS(base) _MMIO((base)+0x70)
2449 #define RING_DMA_FADD(base) _MMIO((base)+0x78)
2450 #define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */
2451 #define RING_INSTPM(base) _MMIO((base)+0xc0)
2452 #define RING_MI_MODE(base) _MMIO((base)+0x9c)
2453 #define INSTPS _MMIO(0x2070) /* 965+ only */
2454 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2455 #define ACTHD_I965 _MMIO(0x2074)
2456 #define HWS_PGA _MMIO(0x2080)
2457 #define HWS_ADDRESS_MASK 0xfffff000
2458 #define HWS_START_ADDRESS_SHIFT 4
2459 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
2460 #define PWRCTX_EN (1<<0)
2461 #define IPEIR _MMIO(0x2088)
2462 #define IPEHR _MMIO(0x208c)
2463 #define GEN2_INSTDONE _MMIO(0x2090)
2464 #define NOPID _MMIO(0x2094)
2465 #define HWSTAM _MMIO(0x2098)
2466 #define DMA_FADD_I8XX _MMIO(0x20d0)
2467 #define RING_BBSTATE(base) _MMIO((base)+0x110)
2468 #define RING_BB_PPGTT (1 << 5)
2469 #define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */
2470 #define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */
2471 #define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */
2472 #define RING_BBADDR(base) _MMIO((base)+0x140)
2473 #define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */
2474 #define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */
2475 #define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */
2476 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */
2477 #define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */
2479 #define ERROR_GEN6 _MMIO(0x40a0)
2480 #define GEN7_ERR_INT _MMIO(0x44040)
2481 #define ERR_INT_POISON (1<<31)
2482 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
2483 #define ERR_INT_PIPE_CRC_DONE_C (1<<8)
2484 #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
2485 #define ERR_INT_PIPE_CRC_DONE_B (1<<5)
2486 #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
2487 #define ERR_INT_PIPE_CRC_DONE_A (1<<2)
2488 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3))
2489 #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
2490 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
2492 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2493 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2494 #define FAULT_VA_HIGH_BITS (0xf << 0)
2495 #define FAULT_GTT_SEL (1 << 4)
2497 #define FPGA_DBG _MMIO(0x42300)
2498 #define FPGA_DBG_RM_NOCLAIM (1<<31)
2500 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2501 #define CLAIM_ER_CLR (1 << 31)
2502 #define CLAIM_ER_OVERFLOW (1 << 16)
2503 #define CLAIM_ER_CTR_MASK 0xffff
2505 #define DERRMR _MMIO(0x44050)
2506 /* Note that HBLANK events are reserved on bdw+ */
2507 #define DERRMR_PIPEA_SCANLINE (1<<0)
2508 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
2509 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
2510 #define DERRMR_PIPEA_VBLANK (1<<3)
2511 #define DERRMR_PIPEA_HBLANK (1<<5)
2512 #define DERRMR_PIPEB_SCANLINE (1<<8)
2513 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
2514 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
2515 #define DERRMR_PIPEB_VBLANK (1<<11)
2516 #define DERRMR_PIPEB_HBLANK (1<<13)
2517 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2518 #define DERRMR_PIPEC_SCANLINE (1<<14)
2519 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
2520 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
2521 #define DERRMR_PIPEC_VBLANK (1<<21)
2522 #define DERRMR_PIPEC_HBLANK (1<<22)
2525 /* GM45+ chicken bits -- debug workaround bits that may be required
2526 * for various sorts of correct behavior. The top 16 bits of each are
2527 * the enables for writing to the corresponding low bit.
2529 #define _3D_CHICKEN _MMIO(0x2084)
2530 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2531 #define _3D_CHICKEN2 _MMIO(0x208c)
2532 /* Disables pipelining of read flushes past the SF-WIZ interface.
2533 * Required on all Ironlake steppings according to the B-Spec, but the
2534 * particular danger of not doing so is not specified.
2536 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2537 #define _3D_CHICKEN3 _MMIO(0x2090)
2538 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2539 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2540 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2541 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
2542 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
2544 #define MI_MODE _MMIO(0x209c)
2545 # define VS_TIMER_DISPATCH (1 << 6)
2546 # define MI_FLUSH_ENABLE (1 << 12)
2547 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2548 # define MODE_IDLE (1 << 9)
2549 # define STOP_RING (1 << 8)
2551 #define GEN6_GT_MODE _MMIO(0x20d0)
2552 #define GEN7_GT_MODE _MMIO(0x7008)
2553 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2554 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2555 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2556 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2557 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2558 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2559 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2560 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2562 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2563 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2564 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2566 /* WaClearTdlStateAckDirtyBits */
2567 #define GEN8_STATE_ACK _MMIO(0x20F0)
2568 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2569 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2570 #define GEN9_STATE_ACK_TDL0 (1 << 12)
2571 #define GEN9_STATE_ACK_TDL1 (1 << 13)
2572 #define GEN9_STATE_ACK_TDL2 (1 << 14)
2573 #define GEN9_STATE_ACK_TDL3 (1 << 15)
2574 #define GEN9_SUBSLICE_TDL_ACK_BITS \
2575 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2576 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2578 #define GFX_MODE _MMIO(0x2520)
2579 #define GFX_MODE_GEN7 _MMIO(0x229c)
2580 #define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base+0x29c)
2581 #define GFX_RUN_LIST_ENABLE (1<<15)
2582 #define GFX_INTERRUPT_STEERING (1<<14)
2583 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
2584 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
2585 #define GFX_REPLAY_MODE (1<<11)
2586 #define GFX_PSMI_GRANULARITY (1<<10)
2587 #define GFX_PPGTT_ENABLE (1<<9)
2588 #define GEN8_GFX_PPGTT_48B (1<<7)
2590 #define GFX_FORWARD_VBLANK_MASK (3<<5)
2591 #define GFX_FORWARD_VBLANK_NEVER (0<<5)
2592 #define GFX_FORWARD_VBLANK_ALWAYS (1<<5)
2593 #define GFX_FORWARD_VBLANK_COND (2<<5)
2595 #define GEN11_GFX_DISABLE_LEGACY_MODE (1<<3)
2597 #define VLV_DISPLAY_BASE 0x180000
2598 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
2599 #define BXT_MIPI_BASE 0x60000
2601 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2602 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2603 #define SCPD0 _MMIO(0x209c) /* 915+ only */
2604 #define IER _MMIO(0x20a0)
2605 #define IIR _MMIO(0x20a4)
2606 #define IMR _MMIO(0x20a8)
2607 #define ISR _MMIO(0x20ac)
2608 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2609 #define GINT_DIS (1<<22)
2610 #define GCFG_DIS (1<<8)
2611 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2612 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2613 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2614 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2615 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2616 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2617 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2618 #define VLV_PCBR_ADDR_SHIFT 12
2620 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
2621 #define EIR _MMIO(0x20b0)
2622 #define EMR _MMIO(0x20b4)
2623 #define ESR _MMIO(0x20b8)
2624 #define GM45_ERROR_PAGE_TABLE (1<<5)
2625 #define GM45_ERROR_MEM_PRIV (1<<4)
2626 #define I915_ERROR_PAGE_TABLE (1<<4)
2627 #define GM45_ERROR_CP_PRIV (1<<3)
2628 #define I915_ERROR_MEMORY_REFRESH (1<<1)
2629 #define I915_ERROR_INSTRUCTION (1<<0)
2630 #define INSTPM _MMIO(0x20c0)
2631 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
2632 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
2633 will not assert AGPBUSY# and will only
2634 be delivered when out of C3. */
2635 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
2636 #define INSTPM_TLB_INVALIDATE (1<<9)
2637 #define INSTPM_SYNC_FLUSH (1<<5)
2638 #define ACTHD _MMIO(0x20c8)
2639 #define MEM_MODE _MMIO(0x20cc)
2640 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
2641 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
2642 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
2643 #define FW_BLC _MMIO(0x20d8)
2644 #define FW_BLC2 _MMIO(0x20dc)
2645 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
2646 #define FW_BLC_SELF_EN_MASK (1<<31)
2647 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
2648 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
2649 #define MM_BURST_LENGTH 0x00700000
2650 #define MM_FIFO_WATERMARK 0x0001F000
2651 #define LM_BURST_LENGTH 0x00000700
2652 #define LM_FIFO_WATERMARK 0x0000001F
2653 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
2655 #define MBUS_ABOX_CTL _MMIO(0x45038)
2656 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
2657 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
2658 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
2659 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
2660 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
2661 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
2662 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
2663 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
2665 #define _PIPEA_MBUS_DBOX_CTL 0x7003C
2666 #define _PIPEB_MBUS_DBOX_CTL 0x7103C
2667 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2668 _PIPEB_MBUS_DBOX_CTL)
2669 #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
2670 #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
2671 #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
2672 #define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
2673 #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
2674 #define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
2676 #define MBUS_UBOX_CTL _MMIO(0x4503C)
2677 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
2678 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
2680 /* Make render/texture TLB fetches lower priorty than associated data
2681 * fetches. This is not turned on by default
2683 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
2685 /* Isoch request wait on GTT enable (Display A/B/C streams).
2686 * Make isoch requests stall on the TLB update. May cause
2687 * display underruns (test mode only)
2689 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
2691 /* Block grant count for isoch requests when block count is
2692 * set to a finite value.
2694 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
2695 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
2696 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
2697 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
2698 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
2700 /* Enable render writes to complete in C2/C3/C4 power states.
2701 * If this isn't enabled, render writes are prevented in low
2702 * power states. That seems bad to me.
2704 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
2706 /* This acknowledges an async flip immediately instead
2707 * of waiting for 2TLB fetches.
2709 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
2711 /* Enables non-sequential data reads through arbiter
2713 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
2715 /* Disable FSB snooping of cacheable write cycles from binner/render
2718 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
2720 /* Arbiter time slice for non-isoch streams */
2721 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
2722 #define MI_ARB_TIME_SLICE_1 (0 << 5)
2723 #define MI_ARB_TIME_SLICE_2 (1 << 5)
2724 #define MI_ARB_TIME_SLICE_4 (2 << 5)
2725 #define MI_ARB_TIME_SLICE_6 (3 << 5)
2726 #define MI_ARB_TIME_SLICE_8 (4 << 5)
2727 #define MI_ARB_TIME_SLICE_10 (5 << 5)
2728 #define MI_ARB_TIME_SLICE_14 (6 << 5)
2729 #define MI_ARB_TIME_SLICE_16 (7 << 5)
2731 /* Low priority grace period page size */
2732 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
2733 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
2735 /* Disable display A/B trickle feed */
2736 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2738 /* Set display plane priority */
2739 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
2740 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
2742 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
2743 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
2744 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
2746 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
2747 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
2748 #define CM0_IZ_OPT_DISABLE (1<<6)
2749 #define CM0_ZR_OPT_DISABLE (1<<5)
2750 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
2751 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
2752 #define CM0_COLOR_EVICT_DISABLE (1<<3)
2753 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
2754 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
2755 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
2756 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
2757 #define GFX_FLSH_CNTL_EN (1<<0)
2758 #define ECOSKPD _MMIO(0x21d0)
2759 #define ECO_GATING_CX_ONLY (1<<3)
2760 #define ECO_FLIP_DONE (1<<0)
2762 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
2763 #define RC_OP_FLUSH_ENABLE (1<<0)
2764 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
2765 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
2766 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
2767 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
2768 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
2770 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
2771 #define GEN6_BLITTER_LOCK_SHIFT 16
2772 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
2774 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
2775 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
2776 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2777 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
2779 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2780 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2782 /* Fuse readout registers for GT */
2783 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
2784 #define CHV_FGT_DISABLE_SS0 (1 << 10)
2785 #define CHV_FGT_DISABLE_SS1 (1 << 11)
2786 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2787 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2788 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2789 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2790 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2791 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2792 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2793 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2795 #define GEN8_FUSE2 _MMIO(0x9120)
2796 #define GEN8_F2_SS_DIS_SHIFT 21
2797 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
2798 #define GEN8_F2_S_ENA_SHIFT 25
2799 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2801 #define GEN9_F2_SS_DIS_SHIFT 20
2802 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2804 #define GEN10_F2_S_ENA_SHIFT 22
2805 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
2806 #define GEN10_F2_SS_DIS_SHIFT 18
2807 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
2809 #define GEN8_EU_DISABLE0 _MMIO(0x9134)
2810 #define GEN8_EU_DIS0_S0_MASK 0xffffff
2811 #define GEN8_EU_DIS0_S1_SHIFT 24
2812 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2814 #define GEN8_EU_DISABLE1 _MMIO(0x9138)
2815 #define GEN8_EU_DIS1_S1_MASK 0xffff
2816 #define GEN8_EU_DIS1_S2_SHIFT 16
2817 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2819 #define GEN8_EU_DISABLE2 _MMIO(0x913c)
2820 #define GEN8_EU_DIS2_S2_MASK 0xff
2822 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
2824 #define GEN10_EU_DISABLE3 _MMIO(0x9140)
2825 #define GEN10_EU_DIS_SS_MASK 0xff
2827 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
2828 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
2829 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
2830 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
2831 #define GEN6_BSD_GO_INDICATOR (1 << 4)
2833 /* On modern GEN architectures interrupt control consists of two sets
2834 * of registers. The first set pertains to the ring generating the
2835 * interrupt. The second control is for the functional block generating the
2836 * interrupt. These are PM, GT, DE, etc.
2838 * Luckily *knocks on wood* all the ring interrupt bits match up with the
2839 * GT interrupt bits, so we don't need to duplicate the defines.
2841 * These defines should cover us well from SNB->HSW with minor exceptions
2842 * it can also work on ILK.
2844 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2845 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2846 #define GT_BLT_USER_INTERRUPT (1 << 22)
2847 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2848 #define GT_BSD_USER_INTERRUPT (1 << 12)
2849 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2850 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
2851 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2852 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2853 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2854 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2855 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2856 #define GT_RENDER_USER_INTERRUPT (1 << 0)
2858 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
2859 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
2861 #define GT_PARITY_ERROR(dev_priv) \
2862 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
2863 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
2865 /* These are all the "old" interrupts */
2866 #define ILK_BSD_USER_INTERRUPT (1<<5)
2868 #define I915_PM_INTERRUPT (1<<31)
2869 #define I915_ISP_INTERRUPT (1<<22)
2870 #define I915_LPE_PIPE_B_INTERRUPT (1<<21)
2871 #define I915_LPE_PIPE_A_INTERRUPT (1<<20)
2872 #define I915_MIPIC_INTERRUPT (1<<19)
2873 #define I915_MIPIA_INTERRUPT (1<<18)
2874 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
2875 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
2876 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
2877 #define I915_MASTER_ERROR_INTERRUPT (1<<15)
2878 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
2879 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
2880 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
2881 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
2882 #define I915_HWB_OOM_INTERRUPT (1<<13)
2883 #define I915_LPE_PIPE_C_INTERRUPT (1<<12)
2884 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
2885 #define I915_MISC_INTERRUPT (1<<11)
2886 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
2887 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
2888 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
2889 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
2890 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
2891 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
2892 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
2893 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
2894 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
2895 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
2896 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
2897 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
2898 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
2899 #define I915_DEBUG_INTERRUPT (1<<2)
2900 #define I915_WINVALID_INTERRUPT (1<<1)
2901 #define I915_USER_INTERRUPT (1<<1)
2902 #define I915_ASLE_INTERRUPT (1<<0)
2903 #define I915_BSD_USER_INTERRUPT (1<<25)
2905 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
2906 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000
2908 /* DisplayPort Audio w/ LPE */
2909 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
2910 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
2912 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
2913 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
2914 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
2915 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
2916 _VLV_AUD_PORT_EN_B_DBG, \
2917 _VLV_AUD_PORT_EN_C_DBG, \
2918 _VLV_AUD_PORT_EN_D_DBG)
2919 #define VLV_AMP_MUTE (1 << 1)
2921 #define GEN6_BSD_RNCID _MMIO(0x12198)
2923 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
2924 #define GEN7_FF_SCHED_MASK 0x0077070
2925 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
2926 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
2927 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
2928 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
2929 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
2930 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
2931 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
2932 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
2933 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
2934 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
2935 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
2936 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
2937 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
2938 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
2941 * Framebuffer compression (915+ only)
2944 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2945 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2946 #define FBC_CONTROL _MMIO(0x3208)
2947 #define FBC_CTL_EN (1<<31)
2948 #define FBC_CTL_PERIODIC (1<<30)
2949 #define FBC_CTL_INTERVAL_SHIFT (16)
2950 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
2951 #define FBC_CTL_C3_IDLE (1<<13)
2952 #define FBC_CTL_STRIDE_SHIFT (5)
2953 #define FBC_CTL_FENCENO_SHIFT (0)
2954 #define FBC_COMMAND _MMIO(0x320c)
2955 #define FBC_CMD_COMPRESS (1<<0)
2956 #define FBC_STATUS _MMIO(0x3210)
2957 #define FBC_STAT_COMPRESSING (1<<31)
2958 #define FBC_STAT_COMPRESSED (1<<30)
2959 #define FBC_STAT_MODIFIED (1<<29)
2960 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
2961 #define FBC_CONTROL2 _MMIO(0x3214)
2962 #define FBC_CTL_FENCE_DBL (0<<4)
2963 #define FBC_CTL_IDLE_IMM (0<<2)
2964 #define FBC_CTL_IDLE_FULL (1<<2)
2965 #define FBC_CTL_IDLE_LINE (2<<2)
2966 #define FBC_CTL_IDLE_DEBUG (3<<2)
2967 #define FBC_CTL_CPU_FENCE (1<<1)
2968 #define FBC_CTL_PLANE(plane) ((plane)<<0)
2969 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
2970 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
2972 #define FBC_LL_SIZE (1536)
2974 #define FBC_LLC_READ_CTRL _MMIO(0x9044)
2975 #define FBC_LLC_FULLY_OPEN (1<<30)
2977 /* Framebuffer compression for GM45+ */
2978 #define DPFC_CB_BASE _MMIO(0x3200)
2979 #define DPFC_CONTROL _MMIO(0x3208)
2980 #define DPFC_CTL_EN (1<<31)
2981 #define DPFC_CTL_PLANE(plane) ((plane)<<30)
2982 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
2983 #define DPFC_CTL_FENCE_EN (1<<29)
2984 #define IVB_DPFC_CTL_FENCE_EN (1<<28)
2985 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
2986 #define DPFC_SR_EN (1<<10)
2987 #define DPFC_CTL_LIMIT_1X (0<<6)
2988 #define DPFC_CTL_LIMIT_2X (1<<6)
2989 #define DPFC_CTL_LIMIT_4X (2<<6)
2990 #define DPFC_RECOMP_CTL _MMIO(0x320c)
2991 #define DPFC_RECOMP_STALL_EN (1<<27)
2992 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
2993 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2994 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2995 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
2996 #define DPFC_STATUS _MMIO(0x3210)
2997 #define DPFC_INVAL_SEG_SHIFT (16)
2998 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
2999 #define DPFC_COMP_SEG_SHIFT (0)
3000 #define DPFC_COMP_SEG_MASK (0x000007ff)
3001 #define DPFC_STATUS2 _MMIO(0x3214)
3002 #define DPFC_FENCE_YOFF _MMIO(0x3218)
3003 #define DPFC_CHICKEN _MMIO(0x3224)
3004 #define DPFC_HT_MODIFY (1<<31)
3006 /* Framebuffer compression for Ironlake */
3007 #define ILK_DPFC_CB_BASE _MMIO(0x43200)
3008 #define ILK_DPFC_CONTROL _MMIO(0x43208)
3009 #define FBC_CTL_FALSE_COLOR (1<<10)
3010 /* The bit 28-8 is reserved */
3011 #define DPFC_RESERVED (0x1FFFFF00)
3012 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
3013 #define ILK_DPFC_STATUS _MMIO(0x43210)
3014 #define ILK_DPFC_COMP_SEG_MASK 0x7ff
3015 #define IVB_FBC_STATUS2 _MMIO(0x43214)
3016 #define IVB_FBC_COMP_SEG_MASK 0x7ff
3017 #define BDW_FBC_COMP_SEG_MASK 0xfff
3018 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3019 #define ILK_DPFC_CHICKEN _MMIO(0x43224)
3020 #define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
3021 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
3022 #define ILK_FBC_RT_BASE _MMIO(0x2128)
3023 #define ILK_FBC_RT_VALID (1<<0)
3024 #define SNB_FBC_FRONT_BUFFER (1<<1)
3026 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
3027 #define ILK_FBCQ_DIS (1<<22)
3028 #define ILK_PABSTRETCH_DIS (1<<21)
3032 * Framebuffer compression for Sandybridge
3034 * The following two registers are of type GTTMMADR
3036 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
3037 #define SNB_CPU_FENCE_ENABLE (1<<29)
3038 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
3040 /* Framebuffer compression for Ivybridge */
3041 #define IVB_FBC_RT_BASE _MMIO(0x7020)
3043 #define IPS_CTL _MMIO(0x43408)
3044 #define IPS_ENABLE (1 << 31)
3046 #define MSG_FBC_REND_STATE _MMIO(0x50380)
3047 #define FBC_REND_NUKE (1<<2)
3048 #define FBC_REND_CACHE_CLEAN (1<<1)
3053 #define GPIOA _MMIO(0x5010)
3054 #define GPIOB _MMIO(0x5014)
3055 #define GPIOC _MMIO(0x5018)
3056 #define GPIOD _MMIO(0x501c)
3057 #define GPIOE _MMIO(0x5020)
3058 #define GPIOF _MMIO(0x5024)
3059 #define GPIOG _MMIO(0x5028)
3060 #define GPIOH _MMIO(0x502c)
3061 # define GPIO_CLOCK_DIR_MASK (1 << 0)
3062 # define GPIO_CLOCK_DIR_IN (0 << 1)
3063 # define GPIO_CLOCK_DIR_OUT (1 << 1)
3064 # define GPIO_CLOCK_VAL_MASK (1 << 2)
3065 # define GPIO_CLOCK_VAL_OUT (1 << 3)
3066 # define GPIO_CLOCK_VAL_IN (1 << 4)
3067 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3068 # define GPIO_DATA_DIR_MASK (1 << 8)
3069 # define GPIO_DATA_DIR_IN (0 << 9)
3070 # define GPIO_DATA_DIR_OUT (1 << 9)
3071 # define GPIO_DATA_VAL_MASK (1 << 10)
3072 # define GPIO_DATA_VAL_OUT (1 << 11)
3073 # define GPIO_DATA_VAL_IN (1 << 12)
3074 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3076 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3077 #define GMBUS_RATE_100KHZ (0<<8)
3078 #define GMBUS_RATE_50KHZ (1<<8)
3079 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
3080 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
3081 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
3082 #define GMBUS_PIN_DISABLED 0
3083 #define GMBUS_PIN_SSC 1
3084 #define GMBUS_PIN_VGADDC 2
3085 #define GMBUS_PIN_PANEL 3
3086 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
3087 #define GMBUS_PIN_DPC 4 /* HDMIC */
3088 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
3089 #define GMBUS_PIN_DPD 6 /* HDMID */
3090 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */
3091 #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
3092 #define GMBUS_PIN_2_BXT 2
3093 #define GMBUS_PIN_3_BXT 3
3094 #define GMBUS_PIN_4_CNP 4
3095 #define GMBUS_PIN_9_TC1_ICP 9
3096 #define GMBUS_PIN_10_TC2_ICP 10
3097 #define GMBUS_PIN_11_TC3_ICP 11
3098 #define GMBUS_PIN_12_TC4_ICP 12
3100 #define GMBUS_NUM_PINS 13 /* including 0 */
3101 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3102 #define GMBUS_SW_CLR_INT (1<<31)
3103 #define GMBUS_SW_RDY (1<<30)
3104 #define GMBUS_ENT (1<<29) /* enable timeout */
3105 #define GMBUS_CYCLE_NONE (0<<25)
3106 #define GMBUS_CYCLE_WAIT (1<<25)
3107 #define GMBUS_CYCLE_INDEX (2<<25)
3108 #define GMBUS_CYCLE_STOP (4<<25)
3109 #define GMBUS_BYTE_COUNT_SHIFT 16
3110 #define GMBUS_BYTE_COUNT_MAX 256U
3111 #define GMBUS_SLAVE_INDEX_SHIFT 8
3112 #define GMBUS_SLAVE_ADDR_SHIFT 1
3113 #define GMBUS_SLAVE_READ (1<<0)
3114 #define GMBUS_SLAVE_WRITE (0<<0)
3115 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3116 #define GMBUS_INUSE (1<<15)
3117 #define GMBUS_HW_WAIT_PHASE (1<<14)
3118 #define GMBUS_STALL_TIMEOUT (1<<13)
3119 #define GMBUS_INT (1<<12)
3120 #define GMBUS_HW_RDY (1<<11)
3121 #define GMBUS_SATOER (1<<10)
3122 #define GMBUS_ACTIVE (1<<9)
3123 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3124 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3125 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
3126 #define GMBUS_NAK_EN (1<<3)
3127 #define GMBUS_IDLE_EN (1<<2)
3128 #define GMBUS_HW_WAIT_EN (1<<1)
3129 #define GMBUS_HW_RDY_EN (1<<0)
3130 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3131 #define GMBUS_2BYTE_INDEX_EN (1<<31)
3134 * Clock control & power management
3136 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
3137 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
3138 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
3139 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3141 #define VGA0 _MMIO(0x6000)
3142 #define VGA1 _MMIO(0x6004)
3143 #define VGA_PD _MMIO(0x6010)
3144 #define VGA0_PD_P2_DIV_4 (1 << 7)
3145 #define VGA0_PD_P1_DIV_2 (1 << 5)
3146 #define VGA0_PD_P1_SHIFT 0
3147 #define VGA0_PD_P1_MASK (0x1f << 0)
3148 #define VGA1_PD_P2_DIV_4 (1 << 15)
3149 #define VGA1_PD_P1_DIV_2 (1 << 13)
3150 #define VGA1_PD_P1_SHIFT 8
3151 #define VGA1_PD_P1_MASK (0x1f << 8)
3152 #define DPLL_VCO_ENABLE (1 << 31)
3153 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
3154 #define DPLL_DVO_2X_MODE (1 << 30)
3155 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
3156 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
3157 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
3158 #define DPLL_VGA_MODE_DIS (1 << 28)
3159 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
3160 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
3161 #define DPLL_MODE_MASK (3 << 26)
3162 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3163 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3164 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
3165 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
3166 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
3167 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
3168 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
3169 #define DPLL_LOCK_VLV (1<<15)
3170 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
3171 #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13)
3172 #define DPLL_SSC_REF_CLK_CHV (1<<13)
3173 #define DPLL_PORTC_READY_MASK (0xf << 4)
3174 #define DPLL_PORTB_READY_MASK (0xf)
3176 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
3178 /* Additional CHV pll/phy registers */
3179 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3180 #define DPLL_PORTD_READY_MASK (0xf)
3181 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3182 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27))
3183 #define PHY_LDO_DELAY_0NS 0x0
3184 #define PHY_LDO_DELAY_200NS 0x1
3185 #define PHY_LDO_DELAY_600NS 0x2
3186 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
3187 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11))
3188 #define PHY_CH_SU_PSR 0x1
3189 #define PHY_CH_DEEP_PSR 0x7
3190 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
3191 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
3192 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3193 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
3194 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch))))
3195 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline))))
3198 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3199 * this field (only one bit may be set).
3201 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3202 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
3203 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3204 /* i830, required in DVO non-gang */
3205 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
3206 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
3207 #define PLL_REF_INPUT_DREFCLK (0 << 13)
3208 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
3209 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
3210 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3211 #define PLL_REF_INPUT_MASK (3 << 13)
3212 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
3214 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3215 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3216 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
3217 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3218 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3221 * Parallel to Serial Load Pulse phase selection.
3222 * Selects the phase for the 10X DPLL clock for the PCIe
3223 * digital display port. The range is 4 to 13; 10 or more
3224 * is just a flip delay. The default is 6
3226 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3227 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3229 * SDVO multiplier for 945G/GM. Not used on 965.
3231 #define SDVO_MULTIPLIER_MASK 0x000000ff
3232 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
3233 #define SDVO_MULTIPLIER_SHIFT_VGA 0
3235 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
3236 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
3237 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
3238 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3241 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3243 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3245 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3246 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
3247 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3248 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3249 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3251 * SDVO/UDI pixel multiplier.
3253 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3254 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3255 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3256 * dummy bytes in the datastream at an increased clock rate, with both sides of
3257 * the link knowing how many bytes are fill.
3259 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3260 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3261 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3262 * through an SDVO command.
3264 * This register field has values of multiplication factor minus 1, with
3265 * a maximum multiplier of 5 for SDVO.
3267 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3268 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3270 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3271 * This best be set to the default value (3) or the CRT won't work. No,
3272 * I don't entirely understand what this does...
3274 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3275 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
3277 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3279 #define _FPA0 0x6040
3280 #define _FPA1 0x6044
3281 #define _FPB0 0x6048
3282 #define _FPB1 0x604c
3283 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3284 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3285 #define FP_N_DIV_MASK 0x003f0000
3286 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
3287 #define FP_N_DIV_SHIFT 16
3288 #define FP_M1_DIV_MASK 0x00003f00
3289 #define FP_M1_DIV_SHIFT 8
3290 #define FP_M2_DIV_MASK 0x0000003f
3291 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
3292 #define FP_M2_DIV_SHIFT 0
3293 #define DPLL_TEST _MMIO(0x606c)
3294 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3295 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3296 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3297 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3298 #define DPLLB_TEST_N_BYPASS (1 << 19)
3299 #define DPLLB_TEST_M_BYPASS (1 << 18)
3300 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3301 #define DPLLA_TEST_N_BYPASS (1 << 3)
3302 #define DPLLA_TEST_M_BYPASS (1 << 2)
3303 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
3304 #define D_STATE _MMIO(0x6104)
3305 #define DSTATE_GFX_RESET_I830 (1<<6)
3306 #define DSTATE_PLL_D3_OFF (1<<3)
3307 #define DSTATE_GFX_CLOCK_GATING (1<<1)
3308 #define DSTATE_DOT_CLOCK_GATING (1<<0)
3309 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
3310 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3311 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3312 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
3313 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
3314 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
3315 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
3316 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
3317 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
3318 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3319 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3320 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3321 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3322 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3323 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3324 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3325 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3326 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3327 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3328 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3329 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3330 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3331 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3332 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3333 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3334 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
3335 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3336 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3337 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3338 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
3340 * This bit must be set on the 830 to prevent hangs when turning off the
3343 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3344 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3345 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3346 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
3347 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
3349 #define RENCLK_GATE_D1 _MMIO(0x6204)
3350 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
3351 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
3352 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3353 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3354 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3355 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3356 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3357 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3358 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
3359 /* This bit must be unset on 855,865 */
3360 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
3361 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3362 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
3363 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
3364 /* This bit must be set on 855,865. */
3365 # define SV_CLOCK_GATE_DISABLE (1 << 0)
3366 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3367 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3368 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3369 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3370 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3371 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3372 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3373 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3374 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3375 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3376 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3377 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3378 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3379 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3380 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3381 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3382 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3384 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
3385 /* This bit must always be set on 965G/965GM */
3386 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3387 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3388 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3389 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3390 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3391 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
3392 /* This bit must always be set on 965G */
3393 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3394 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3395 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3396 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3397 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3398 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3399 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3400 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3401 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3402 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3403 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3404 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3405 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3406 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3407 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3408 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3409 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3410 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3411 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3413 #define RENCLK_GATE_D2 _MMIO(0x6208)
3414 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3415 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3416 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
3418 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
3419 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3421 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
3422 #define DEUC _MMIO(0x6214) /* CRL only */
3424 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3425 #define FW_CSPWRDWNEN (1<<15)
3427 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3429 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3430 #define CDCLK_FREQ_SHIFT 4
3431 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3432 #define CZCLK_FREQ_MASK 0xf
3434 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3435 #define PFI_CREDIT_63 (9 << 28) /* chv only */
3436 #define PFI_CREDIT_31 (8 << 28) /* chv only */
3437 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3438 #define PFI_CREDIT_RESEND (1 << 27)
3439 #define VGA_FAST_MODE_DISABLE (1 << 14)
3441 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
3446 #define PALETTE_A_OFFSET 0xa000
3447 #define PALETTE_B_OFFSET 0xa800
3448 #define CHV_PALETTE_C_OFFSET 0xc000
3449 #define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
3450 dev_priv->info.display_mmio_offset + (i) * 4)
3452 /* MCH MMIO space */
3457 * This mirrors the MCHBAR MMIO space whose location is determined by
3458 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3459 * every way. It is not accessible from the CP register read instructions.
3461 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3464 #define MCHBAR_MIRROR_BASE 0x10000
3466 #define MCHBAR_MIRROR_BASE_SNB 0x140000
3468 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3469 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3470 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3471 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
3472 #define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
3474 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3475 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3477 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3478 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3479 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3480 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3481 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3482 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
3483 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
3484 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
3485 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3486 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
3488 /* Pineview MCH register contains DDR3 setting */
3489 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3490 #define CSHRDDR3CTL_DDR3 (1 << 2)
3492 /* 965 MCH register controlling DRAM channel configuration */
3493 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3494 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3496 /* snb MCH registers for reading the DRAM channel configuration */
3497 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3498 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3499 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3500 #define MAD_DIMM_ECC_MASK (0x3 << 24)
3501 #define MAD_DIMM_ECC_OFF (0x0 << 24)
3502 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3503 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3504 #define MAD_DIMM_ECC_ON (0x3 << 24)
3505 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3506 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3507 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
3508 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
3509 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3510 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3511 #define MAD_DIMM_A_SELECT (0x1 << 16)
3512 /* DIMM sizes are in multiples of 256mb. */
3513 #define MAD_DIMM_B_SIZE_SHIFT 8
3514 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3515 #define MAD_DIMM_A_SIZE_SHIFT 0
3516 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3518 /* snb MCH registers for priority tuning */
3519 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3520 #define MCH_SSKPD_WM0_MASK 0x3f
3521 #define MCH_SSKPD_WM0_VAL 0xc
3523 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3525 /* Clocking configuration register */
3526 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3527 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
3528 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3529 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3530 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3531 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
3532 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
3533 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
3535 * Note that on at least on ELK the below value is reported for both
3536 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3537 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3539 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
3540 #define CLKCFG_FSB_MASK (7 << 0)
3541 #define CLKCFG_MEM_533 (1 << 4)
3542 #define CLKCFG_MEM_667 (2 << 4)
3543 #define CLKCFG_MEM_800 (3 << 4)
3544 #define CLKCFG_MEM_MASK (7 << 4)
3546 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3547 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3549 #define TSC1 _MMIO(0x11001)
3551 #define TR1 _MMIO(0x11006)
3552 #define TSFS _MMIO(0x11020)
3553 #define TSFS_SLOPE_MASK 0x0000ff00
3554 #define TSFS_SLOPE_SHIFT 8
3555 #define TSFS_INTR_MASK 0x000000ff
3557 #define CRSTANDVID _MMIO(0x11100)
3558 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3559 #define PXVFREQ_PX_MASK 0x7f000000
3560 #define PXVFREQ_PX_SHIFT 24
3561 #define VIDFREQ_BASE _MMIO(0x11110)
3562 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3563 #define VIDFREQ2 _MMIO(0x11114)
3564 #define VIDFREQ3 _MMIO(0x11118)
3565 #define VIDFREQ4 _MMIO(0x1111c)
3566 #define VIDFREQ_P0_MASK 0x1f000000
3567 #define VIDFREQ_P0_SHIFT 24
3568 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3569 #define VIDFREQ_P0_CSCLK_SHIFT 20
3570 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3571 #define VIDFREQ_P0_CRCLK_SHIFT 16
3572 #define VIDFREQ_P1_MASK 0x00001f00
3573 #define VIDFREQ_P1_SHIFT 8
3574 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3575 #define VIDFREQ_P1_CSCLK_SHIFT 4
3576 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3577 #define INTTOEXT_BASE_ILK _MMIO(0x11300)
3578 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3579 #define INTTOEXT_MAP3_SHIFT 24
3580 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
3581 #define INTTOEXT_MAP2_SHIFT 16
3582 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
3583 #define INTTOEXT_MAP1_SHIFT 8
3584 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
3585 #define INTTOEXT_MAP0_SHIFT 0
3586 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
3587 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
3588 #define MEMCTL_CMD_MASK 0xe000
3589 #define MEMCTL_CMD_SHIFT 13
3590 #define MEMCTL_CMD_RCLK_OFF 0
3591 #define MEMCTL_CMD_RCLK_ON 1
3592 #define MEMCTL_CMD_CHFREQ 2
3593 #define MEMCTL_CMD_CHVID 3
3594 #define MEMCTL_CMD_VMMOFF 4
3595 #define MEMCTL_CMD_VMMON 5
3596 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
3597 when command complete */
3598 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3599 #define MEMCTL_FREQ_SHIFT 8
3600 #define MEMCTL_SFCAVM (1<<7)
3601 #define MEMCTL_TGT_VID_MASK 0x007f
3602 #define MEMIHYST _MMIO(0x1117c)
3603 #define MEMINTREN _MMIO(0x11180) /* 16 bits */
3604 #define MEMINT_RSEXIT_EN (1<<8)
3605 #define MEMINT_CX_SUPR_EN (1<<7)
3606 #define MEMINT_CONT_BUSY_EN (1<<6)
3607 #define MEMINT_AVG_BUSY_EN (1<<5)
3608 #define MEMINT_EVAL_CHG_EN (1<<4)
3609 #define MEMINT_MON_IDLE_EN (1<<3)
3610 #define MEMINT_UP_EVAL_EN (1<<2)
3611 #define MEMINT_DOWN_EVAL_EN (1<<1)
3612 #define MEMINT_SW_CMD_EN (1<<0)
3613 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
3614 #define MEM_RSEXIT_MASK 0xc000
3615 #define MEM_RSEXIT_SHIFT 14
3616 #define MEM_CONT_BUSY_MASK 0x3000
3617 #define MEM_CONT_BUSY_SHIFT 12
3618 #define MEM_AVG_BUSY_MASK 0x0c00
3619 #define MEM_AVG_BUSY_SHIFT 10
3620 #define MEM_EVAL_CHG_MASK 0x0300
3621 #define MEM_EVAL_BUSY_SHIFT 8
3622 #define MEM_MON_IDLE_MASK 0x00c0
3623 #define MEM_MON_IDLE_SHIFT 6
3624 #define MEM_UP_EVAL_MASK 0x0030
3625 #define MEM_UP_EVAL_SHIFT 4
3626 #define MEM_DOWN_EVAL_MASK 0x000c
3627 #define MEM_DOWN_EVAL_SHIFT 2
3628 #define MEM_SW_CMD_MASK 0x0003
3629 #define MEM_INT_STEER_GFX 0
3630 #define MEM_INT_STEER_CMR 1
3631 #define MEM_INT_STEER_SMI 2
3632 #define MEM_INT_STEER_SCI 3
3633 #define MEMINTRSTS _MMIO(0x11184)
3634 #define MEMINT_RSEXIT (1<<7)
3635 #define MEMINT_CONT_BUSY (1<<6)
3636 #define MEMINT_AVG_BUSY (1<<5)
3637 #define MEMINT_EVAL_CHG (1<<4)
3638 #define MEMINT_MON_IDLE (1<<3)
3639 #define MEMINT_UP_EVAL (1<<2)
3640 #define MEMINT_DOWN_EVAL (1<<1)
3641 #define MEMINT_SW_CMD (1<<0)
3642 #define MEMMODECTL _MMIO(0x11190)
3643 #define MEMMODE_BOOST_EN (1<<31)
3644 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3645 #define MEMMODE_BOOST_FREQ_SHIFT 24
3646 #define MEMMODE_IDLE_MODE_MASK 0x00030000
3647 #define MEMMODE_IDLE_MODE_SHIFT 16
3648 #define MEMMODE_IDLE_MODE_EVAL 0
3649 #define MEMMODE_IDLE_MODE_CONT 1
3650 #define MEMMODE_HWIDLE_EN (1<<15)
3651 #define MEMMODE_SWMODE_EN (1<<14)
3652 #define MEMMODE_RCLK_GATE (1<<13)
3653 #define MEMMODE_HW_UPDATE (1<<12)
3654 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3655 #define MEMMODE_FSTART_SHIFT 8
3656 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3657 #define MEMMODE_FMAX_SHIFT 4
3658 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
3659 #define RCBMAXAVG _MMIO(0x1119c)
3660 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
3661 #define SWMEMCMD_RENDER_OFF (0 << 13)
3662 #define SWMEMCMD_RENDER_ON (1 << 13)
3663 #define SWMEMCMD_SWFREQ (2 << 13)
3664 #define SWMEMCMD_TARVID (3 << 13)
3665 #define SWMEMCMD_VRM_OFF (4 << 13)
3666 #define SWMEMCMD_VRM_ON (5 << 13)
3667 #define CMDSTS (1<<12)
3668 #define SFCAVM (1<<11)
3669 #define SWFREQ_MASK 0x0380 /* P0-7 */
3670 #define SWFREQ_SHIFT 7
3671 #define TARVID_MASK 0x001f
3672 #define MEMSTAT_CTG _MMIO(0x111a0)
3673 #define RCBMINAVG _MMIO(0x111a0)
3674 #define RCUPEI _MMIO(0x111b0)
3675 #define RCDNEI _MMIO(0x111b4)
3676 #define RSTDBYCTL _MMIO(0x111b8)
3677 #define RS1EN (1<<31)
3678 #define RS2EN (1<<30)
3679 #define RS3EN (1<<29)
3680 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
3681 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
3682 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
3683 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
3684 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
3685 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
3686 #define RSX_STATUS_MASK (7<<20)
3687 #define RSX_STATUS_ON (0<<20)
3688 #define RSX_STATUS_RC1 (1<<20)
3689 #define RSX_STATUS_RC1E (2<<20)
3690 #define RSX_STATUS_RS1 (3<<20)
3691 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
3692 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
3693 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
3694 #define RSX_STATUS_RSVD2 (7<<20)
3695 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
3696 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
3697 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
3698 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
3699 #define RS1CONTSAV_MASK (3<<14)
3700 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
3701 #define RS1CONTSAV_RSVD (1<<14)
3702 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
3703 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
3704 #define NORMSLEXLAT_MASK (3<<12)
3705 #define SLOW_RS123 (0<<12)
3706 #define SLOW_RS23 (1<<12)
3707 #define SLOW_RS3 (2<<12)
3708 #define NORMAL_RS123 (3<<12)
3709 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
3710 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3711 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
3712 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
3713 #define RS_CSTATE_MASK (3<<4)
3714 #define RS_CSTATE_C367_RS1 (0<<4)
3715 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
3716 #define RS_CSTATE_RSVD (2<<4)
3717 #define RS_CSTATE_C367_RS2 (3<<4)
3718 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
3719 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
3720 #define VIDCTL _MMIO(0x111c0)
3721 #define VIDSTS _MMIO(0x111c8)
3722 #define VIDSTART _MMIO(0x111cc) /* 8 bits */
3723 #define MEMSTAT_ILK _MMIO(0x111f8)
3724 #define MEMSTAT_VID_MASK 0x7f00
3725 #define MEMSTAT_VID_SHIFT 8
3726 #define MEMSTAT_PSTATE_MASK 0x00f8
3727 #define MEMSTAT_PSTATE_SHIFT 3
3728 #define MEMSTAT_MON_ACTV (1<<2)
3729 #define MEMSTAT_SRC_CTL_MASK 0x0003
3730 #define MEMSTAT_SRC_CTL_CORE 0
3731 #define MEMSTAT_SRC_CTL_TRB 1
3732 #define MEMSTAT_SRC_CTL_THM 2
3733 #define MEMSTAT_SRC_CTL_STDBY 3
3734 #define RCPREVBSYTUPAVG _MMIO(0x113b8)
3735 #define RCPREVBSYTDNAVG _MMIO(0x113bc)
3736 #define PMMISC _MMIO(0x11214)
3737 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
3738 #define SDEW _MMIO(0x1124c)
3739 #define CSIEW0 _MMIO(0x11250)
3740 #define CSIEW1 _MMIO(0x11254)
3741 #define CSIEW2 _MMIO(0x11258)
3742 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
3743 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
3744 #define MCHAFE _MMIO(0x112c0)
3745 #define CSIEC _MMIO(0x112e0)
3746 #define DMIEC _MMIO(0x112e4)
3747 #define DDREC _MMIO(0x112e8)
3748 #define PEG0EC _MMIO(0x112ec)
3749 #define PEG1EC _MMIO(0x112f0)
3750 #define GFXEC _MMIO(0x112f4)
3751 #define RPPREVBSYTUPAVG _MMIO(0x113b8)
3752 #define RPPREVBSYTDNAVG _MMIO(0x113bc)
3753 #define ECR _MMIO(0x11600)
3754 #define ECR_GPFE (1<<31)
3755 #define ECR_IMONE (1<<30)
3756 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
3757 #define OGW0 _MMIO(0x11608)
3758 #define OGW1 _MMIO(0x1160c)
3759 #define EG0 _MMIO(0x11610)
3760 #define EG1 _MMIO(0x11614)
3761 #define EG2 _MMIO(0x11618)
3762 #define EG3 _MMIO(0x1161c)
3763 #define EG4 _MMIO(0x11620)
3764 #define EG5 _MMIO(0x11624)
3765 #define EG6 _MMIO(0x11628)
3766 #define EG7 _MMIO(0x1162c)
3767 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
3768 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
3769 #define LCFUSE02 _MMIO(0x116c0)
3770 #define LCFUSE_HIV_MASK 0x000000ff
3771 #define CSIPLL0 _MMIO(0x12c10)
3772 #define DDRMPLL1 _MMIO(0X12c20)
3773 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
3775 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3776 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
3778 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3779 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3780 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3781 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3782 #define BXT_RP_STATE_CAP _MMIO(0x138170)
3785 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3786 * 8300) freezing up around GPU hangs. Looks as if even
3787 * scheduling/timer interrupts start misbehaving if the RPS
3788 * EI/thresholds are "bad", leading to a very sluggish or even
3791 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
3792 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
3793 #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
3794 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3795 (IS_GEN9_LP(dev_priv) ? \
3796 INTERVAL_0_833_US(us) : \
3797 INTERVAL_1_33_US(us)) : \
3798 INTERVAL_1_28_US(us))
3800 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3801 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3802 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
3803 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3804 (IS_GEN9_LP(dev_priv) ? \
3805 INTERVAL_0_833_TO_US(interval) : \
3806 INTERVAL_1_33_TO_US(interval)) : \
3807 INTERVAL_1_28_TO_US(interval))
3810 * Logical Context regs
3812 #define CCID _MMIO(0x2180)
3813 #define CCID_EN BIT(0)
3814 #define CCID_EXTENDED_STATE_RESTORE BIT(2)
3815 #define CCID_EXTENDED_STATE_SAVE BIT(3)
3817 * Notes on SNB/IVB/VLV context size:
3818 * - Power context is saved elsewhere (LLC or stolen)
3819 * - Ring/execlist context is saved on SNB, not on IVB
3820 * - Extended context size already includes render context size
3821 * - We always need to follow the extended context size.
3822 * SNB BSpec has comments indicating that we should use the
3823 * render context size instead if execlists are disabled, but
3824 * based on empirical testing that's just nonsense.
3825 * - Pipelined/VF state is saved on SNB/IVB respectively
3826 * - GT1 size just indicates how much of render context
3827 * doesn't need saving on GT1
3829 #define CXT_SIZE _MMIO(0x21a0)
3830 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
3831 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
3832 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
3833 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3834 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
3835 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
3836 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3837 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
3838 #define GEN7_CXT_SIZE _MMIO(0x21a8)
3839 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
3840 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
3841 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
3842 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3843 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
3844 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
3845 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3846 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
3849 INTEL_ADVANCED_CONTEXT = 0,
3850 INTEL_LEGACY_32B_CONTEXT,
3851 INTEL_ADVANCED_AD_CONTEXT,
3852 INTEL_LEGACY_64B_CONTEXT
3857 FAULT_AND_HALT, /* Debug only */
3859 FAULT_AND_CONTINUE /* Unsupported */
3862 #define GEN8_CTX_VALID (1<<0)
3863 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
3864 #define GEN8_CTX_FORCE_RESTORE (1<<2)
3865 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
3866 #define GEN8_CTX_PRIVILEGE (1<<8)
3867 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
3869 #define GEN8_CTX_ID_SHIFT 32
3870 #define GEN8_CTX_ID_WIDTH 21
3872 #define CHV_CLK_CTL1 _MMIO(0x101100)
3873 #define VLV_CLK_CTL2 _MMIO(0x101104)
3874 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
3880 #define OVADD _MMIO(0x30000)
3881 #define DOVSTA _MMIO(0x30008)
3882 #define OC_BUF (0x3<<20)
3883 #define OGAMC5 _MMIO(0x30010)
3884 #define OGAMC4 _MMIO(0x30014)
3885 #define OGAMC3 _MMIO(0x30018)
3886 #define OGAMC2 _MMIO(0x3001c)
3887 #define OGAMC1 _MMIO(0x30020)
3888 #define OGAMC0 _MMIO(0x30024)
3891 * GEN9 clock gating regs
3893 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
3894 #define DARBF_GATING_DIS (1 << 27)
3895 #define PWM2_GATING_DIS (1 << 14)
3896 #define PWM1_GATING_DIS (1 << 13)
3898 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
3899 #define BXT_GMBUS_GATING_DIS (1 << 14)
3901 #define _CLKGATE_DIS_PSL_A 0x46520
3902 #define _CLKGATE_DIS_PSL_B 0x46524
3903 #define _CLKGATE_DIS_PSL_C 0x46528
3904 #define DPF_GATING_DIS (1 << 10)
3905 #define DPF_RAM_GATING_DIS (1 << 9)
3906 #define DPFR_GATING_DIS (1 << 8)
3908 #define CLKGATE_DIS_PSL(pipe) \
3909 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
3912 * GEN10 clock gating regs
3914 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
3915 #define SARBUNIT_CLKGATE_DIS (1 << 5)
3916 #define RCCUNIT_CLKGATE_DIS (1 << 7)
3918 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
3919 #define VFUNIT_CLKGATE_DIS (1 << 20)
3922 * Display engine regs
3925 /* Pipe A CRC regs */
3926 #define _PIPE_CRC_CTL_A 0x60050
3927 #define PIPE_CRC_ENABLE (1 << 31)
3928 /* ivb+ source selection */
3929 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
3930 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
3931 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
3932 /* ilk+ source selection */
3933 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
3934 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
3935 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
3936 /* embedded DP port on the north display block, reserved on ivb */
3937 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
3938 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
3939 /* vlv source selection */
3940 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
3941 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
3942 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
3943 /* with DP port the pipe source is invalid */
3944 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
3945 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
3946 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
3947 /* gen3+ source selection */
3948 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
3949 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
3950 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
3951 /* with DP/TV port the pipe source is invalid */
3952 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
3953 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
3954 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
3955 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
3956 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
3957 /* gen2 doesn't have source selection bits */
3958 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
3960 #define _PIPE_CRC_RES_1_A_IVB 0x60064
3961 #define _PIPE_CRC_RES_2_A_IVB 0x60068
3962 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
3963 #define _PIPE_CRC_RES_4_A_IVB 0x60070
3964 #define _PIPE_CRC_RES_5_A_IVB 0x60074
3966 #define _PIPE_CRC_RES_RED_A 0x60060
3967 #define _PIPE_CRC_RES_GREEN_A 0x60064
3968 #define _PIPE_CRC_RES_BLUE_A 0x60068
3969 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
3970 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
3972 /* Pipe B CRC regs */
3973 #define _PIPE_CRC_RES_1_B_IVB 0x61064
3974 #define _PIPE_CRC_RES_2_B_IVB 0x61068
3975 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
3976 #define _PIPE_CRC_RES_4_B_IVB 0x61070
3977 #define _PIPE_CRC_RES_5_B_IVB 0x61074
3979 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
3980 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
3981 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
3982 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
3983 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
3984 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
3986 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
3987 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
3988 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
3989 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
3990 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
3992 /* Pipe A timing regs */
3993 #define _HTOTAL_A 0x60000
3994 #define _HBLANK_A 0x60004
3995 #define _HSYNC_A 0x60008
3996 #define _VTOTAL_A 0x6000c
3997 #define _VBLANK_A 0x60010
3998 #define _VSYNC_A 0x60014
3999 #define _PIPEASRC 0x6001c
4000 #define _BCLRPAT_A 0x60020
4001 #define _VSYNCSHIFT_A 0x60028
4002 #define _PIPE_MULT_A 0x6002c
4004 /* Pipe B timing regs */
4005 #define _HTOTAL_B 0x61000
4006 #define _HBLANK_B 0x61004
4007 #define _HSYNC_B 0x61008
4008 #define _VTOTAL_B 0x6100c
4009 #define _VBLANK_B 0x61010
4010 #define _VSYNC_B 0x61014
4011 #define _PIPEBSRC 0x6101c
4012 #define _BCLRPAT_B 0x61020
4013 #define _VSYNCSHIFT_B 0x61028
4014 #define _PIPE_MULT_B 0x6102c
4016 #define TRANSCODER_A_OFFSET 0x60000
4017 #define TRANSCODER_B_OFFSET 0x61000
4018 #define TRANSCODER_C_OFFSET 0x62000
4019 #define CHV_TRANSCODER_C_OFFSET 0x63000
4020 #define TRANSCODER_EDP_OFFSET 0x6f000
4022 #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
4023 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
4024 dev_priv->info.display_mmio_offset)
4026 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4027 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4028 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4029 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4030 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4031 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4032 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4033 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4034 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4035 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4037 /* VLV eDP PSR registers */
4038 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
4039 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
4040 #define VLV_EDP_PSR_ENABLE (1<<0)
4041 #define VLV_EDP_PSR_RESET (1<<1)
4042 #define VLV_EDP_PSR_MODE_MASK (7<<2)
4043 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
4044 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
4045 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
4046 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
4047 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
4048 #define VLV_EDP_PSR_DBL_FRAME (1<<10)
4049 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
4050 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
4051 #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
4053 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
4054 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
4055 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
4056 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
4057 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
4058 #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
4060 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
4061 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
4062 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
4063 #define VLV_EDP_PSR_CURR_STATE_MASK 7
4064 #define VLV_EDP_PSR_DISABLED (0<<0)
4065 #define VLV_EDP_PSR_INACTIVE (1<<0)
4066 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
4067 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
4068 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
4069 #define VLV_EDP_PSR_EXIT (5<<0)
4070 #define VLV_EDP_PSR_IN_TRANS (1<<7)
4071 #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
4073 /* HSW+ eDP PSR registers */
4074 #define HSW_EDP_PSR_BASE 0x64800
4075 #define BDW_EDP_PSR_BASE 0x6f800
4076 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
4077 #define EDP_PSR_ENABLE (1<<31)
4078 #define BDW_PSR_SINGLE_FRAME (1<<30)
4079 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */
4080 #define EDP_PSR_LINK_STANDBY (1<<27)
4081 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
4082 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
4083 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
4084 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
4085 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
4086 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4087 #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
4088 #define EDP_PSR_TP1_TP2_SEL (0<<11)
4089 #define EDP_PSR_TP1_TP3_SEL (1<<11)
4090 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
4091 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
4092 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
4093 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
4094 #define EDP_PSR_TP1_TIME_500us (0<<4)
4095 #define EDP_PSR_TP1_TIME_100us (1<<4)
4096 #define EDP_PSR_TP1_TIME_2500us (2<<4)
4097 #define EDP_PSR_TP1_TIME_0us (3<<4)
4098 #define EDP_PSR_IDLE_FRAME_SHIFT 0
4100 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4101 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
4103 #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
4104 #define EDP_PSR_STATUS_STATE_MASK (7<<29)
4105 #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
4106 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
4107 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
4108 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
4109 #define EDP_PSR_STATUS_STATE_BUFON (4<<29)
4110 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
4111 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
4112 #define EDP_PSR_STATUS_LINK_MASK (3<<26)
4113 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
4114 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
4115 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
4116 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4117 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4118 #define EDP_PSR_STATUS_COUNT_SHIFT 16
4119 #define EDP_PSR_STATUS_COUNT_MASK 0xf
4120 #define EDP_PSR_STATUS_AUX_ERROR (1<<15)
4121 #define EDP_PSR_STATUS_AUX_SENDING (1<<12)
4122 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
4123 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
4124 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
4125 #define EDP_PSR_STATUS_IDLE_MASK 0xf
4127 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
4128 #define EDP_PSR_PERF_CNT_MASK 0xffffff
4130 #define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60)
4131 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28)
4132 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
4133 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
4134 #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
4135 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1<<16)
4136 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
4138 #define EDP_PSR2_CTL _MMIO(0x6f900)
4139 #define EDP_PSR2_ENABLE (1<<31)
4140 #define EDP_SU_TRACK_ENABLE (1<<30)
4141 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
4142 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
4143 #define EDP_PSR2_TP2_TIME_500 (0<<8)
4144 #define EDP_PSR2_TP2_TIME_100 (1<<8)
4145 #define EDP_PSR2_TP2_TIME_2500 (2<<8)
4146 #define EDP_PSR2_TP2_TIME_50 (3<<8)
4147 #define EDP_PSR2_TP2_TIME_MASK (3<<8)
4148 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4149 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
4150 #define EDP_PSR2_IDLE_MASK 0xf
4151 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
4153 #define EDP_PSR2_STATUS _MMIO(0x6f940)
4154 #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
4155 #define EDP_PSR2_STATUS_STATE_SHIFT 28
4157 /* VGA port control */
4158 #define ADPA _MMIO(0x61100)
4159 #define PCH_ADPA _MMIO(0xe1100)
4160 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4162 #define ADPA_DAC_ENABLE (1<<31)
4163 #define ADPA_DAC_DISABLE 0
4164 #define ADPA_PIPE_SELECT_MASK (1<<30)
4165 #define ADPA_PIPE_A_SELECT 0
4166 #define ADPA_PIPE_B_SELECT (1<<30)
4167 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
4168 /* CPT uses bits 29:30 for pch transcoder select */
4169 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4170 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
4171 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
4172 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
4173 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
4174 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
4175 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
4176 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
4177 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
4178 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
4179 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
4180 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
4181 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
4182 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
4183 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
4184 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
4185 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
4186 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
4187 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
4188 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
4189 #define ADPA_SETS_HVPOLARITY 0
4190 #define ADPA_VSYNC_CNTL_DISABLE (1<<10)
4191 #define ADPA_VSYNC_CNTL_ENABLE 0
4192 #define ADPA_HSYNC_CNTL_DISABLE (1<<11)
4193 #define ADPA_HSYNC_CNTL_ENABLE 0
4194 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
4195 #define ADPA_VSYNC_ACTIVE_LOW 0
4196 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
4197 #define ADPA_HSYNC_ACTIVE_LOW 0
4198 #define ADPA_DPMS_MASK (~(3<<10))
4199 #define ADPA_DPMS_ON (0<<10)
4200 #define ADPA_DPMS_SUSPEND (1<<10)
4201 #define ADPA_DPMS_STANDBY (2<<10)
4202 #define ADPA_DPMS_OFF (3<<10)
4205 /* Hotplug control (945+ only) */
4206 #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
4207 #define PORTB_HOTPLUG_INT_EN (1 << 29)
4208 #define PORTC_HOTPLUG_INT_EN (1 << 28)
4209 #define PORTD_HOTPLUG_INT_EN (1 << 27)
4210 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
4211 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
4212 #define TV_HOTPLUG_INT_EN (1 << 18)
4213 #define CRT_HOTPLUG_INT_EN (1 << 9)
4214 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4215 PORTC_HOTPLUG_INT_EN | \
4216 PORTD_HOTPLUG_INT_EN | \
4217 SDVOC_HOTPLUG_INT_EN | \
4218 SDVOB_HOTPLUG_INT_EN | \
4220 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
4221 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
4222 /* must use period 64 on GM45 according to docs */
4223 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
4224 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
4225 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
4226 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
4227 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
4228 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
4229 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
4230 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
4231 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
4232 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
4233 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4234 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
4236 #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
4238 * HDMI/DP bits are g4x+
4240 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4241 * Please check the detailed lore in the commit message for for experimental
4244 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4245 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
4246 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
4247 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
4248 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4249 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
4250 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
4251 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
4252 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
4253 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
4254 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
4255 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
4256 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
4257 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
4258 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
4259 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
4260 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
4261 /* CRT/TV common between gen3+ */
4262 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
4263 #define TV_HOTPLUG_INT_STATUS (1 << 10)
4264 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
4265 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
4266 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
4267 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
4268 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
4269 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
4270 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
4271 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
4273 /* SDVO is different across gen3/4 */
4274 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
4275 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
4277 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4278 * since reality corrobates that they're the same as on gen3. But keep these
4279 * bits here (and the comment!) to help any other lost wanderers back onto the
4282 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
4283 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
4284 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
4285 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
4286 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
4287 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4288 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4289 PORTB_HOTPLUG_INT_STATUS | \
4290 PORTC_HOTPLUG_INT_STATUS | \
4291 PORTD_HOTPLUG_INT_STATUS)
4293 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
4294 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4295 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4296 PORTB_HOTPLUG_INT_STATUS | \
4297 PORTC_HOTPLUG_INT_STATUS | \
4298 PORTD_HOTPLUG_INT_STATUS)
4300 /* SDVO and HDMI port control.
4301 * The same register may be used for SDVO or HDMI */
4302 #define _GEN3_SDVOB 0x61140
4303 #define _GEN3_SDVOC 0x61160
4304 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
4305 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
4306 #define GEN4_HDMIB GEN3_SDVOB
4307 #define GEN4_HDMIC GEN3_SDVOC
4308 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4309 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4310 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4311 #define PCH_SDVOB _MMIO(0xe1140)
4312 #define PCH_HDMIB PCH_SDVOB
4313 #define PCH_HDMIC _MMIO(0xe1150)
4314 #define PCH_HDMID _MMIO(0xe1160)
4316 #define PORT_DFT_I9XX _MMIO(0x61150)
4317 #define DC_BALANCE_RESET (1 << 25)
4318 #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
4319 #define DC_BALANCE_RESET_VLV (1 << 31)
4320 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
4321 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
4322 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
4323 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
4325 /* Gen 3 SDVO bits: */
4326 #define SDVO_ENABLE (1 << 31)
4327 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
4328 #define SDVO_PIPE_SEL_MASK (1 << 30)
4329 #define SDVO_PIPE_B_SELECT (1 << 30)
4330 #define SDVO_STALL_SELECT (1 << 29)
4331 #define SDVO_INTERRUPT_ENABLE (1 << 26)
4333 * 915G/GM SDVO pixel multiplier.
4334 * Programmed value is multiplier - 1, up to 5x.
4335 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4337 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
4338 #define SDVO_PORT_MULTIPLY_SHIFT 23
4339 #define SDVO_PHASE_SELECT_MASK (15 << 19)
4340 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
4341 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
4342 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
4343 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
4344 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
4345 #define SDVO_DETECTED (1 << 2)
4346 /* Bits to be preserved when writing */
4347 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4348 SDVO_INTERRUPT_ENABLE)
4349 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4351 /* Gen 4 SDVO/HDMI bits: */
4352 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
4353 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
4354 #define SDVO_ENCODING_SDVO (0 << 10)
4355 #define SDVO_ENCODING_HDMI (2 << 10)
4356 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
4357 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
4358 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
4359 #define SDVO_AUDIO_ENABLE (1 << 6)
4360 /* VSYNC/HSYNC bits new with 965, default is to be set */
4361 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4362 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
4364 /* Gen 5 (IBX) SDVO/HDMI bits: */
4365 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
4366 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
4368 /* Gen 6 (CPT) SDVO/HDMI bits: */
4369 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4370 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
4372 /* CHV SDVO/HDMI bits: */
4373 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
4374 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
4377 /* DVO port control */
4378 #define _DVOA 0x61120
4379 #define DVOA _MMIO(_DVOA)
4380 #define _DVOB 0x61140
4381 #define DVOB _MMIO(_DVOB)
4382 #define _DVOC 0x61160
4383 #define DVOC _MMIO(_DVOC)
4384 #define DVO_ENABLE (1 << 31)
4385 #define DVO_PIPE_B_SELECT (1 << 30)
4386 #define DVO_PIPE_STALL_UNUSED (0 << 28)
4387 #define DVO_PIPE_STALL (1 << 28)
4388 #define DVO_PIPE_STALL_TV (2 << 28)
4389 #define DVO_PIPE_STALL_MASK (3 << 28)
4390 #define DVO_USE_VGA_SYNC (1 << 15)
4391 #define DVO_DATA_ORDER_I740 (0 << 14)
4392 #define DVO_DATA_ORDER_FP (1 << 14)
4393 #define DVO_VSYNC_DISABLE (1 << 11)
4394 #define DVO_HSYNC_DISABLE (1 << 10)
4395 #define DVO_VSYNC_TRISTATE (1 << 9)
4396 #define DVO_HSYNC_TRISTATE (1 << 8)
4397 #define DVO_BORDER_ENABLE (1 << 7)
4398 #define DVO_DATA_ORDER_GBRG (1 << 6)
4399 #define DVO_DATA_ORDER_RGGB (0 << 6)
4400 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
4401 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
4402 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
4403 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
4404 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
4405 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
4406 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
4407 #define DVO_PRESERVE_MASK (0x7<<24)
4408 #define DVOA_SRCDIM _MMIO(0x61124)
4409 #define DVOB_SRCDIM _MMIO(0x61144)
4410 #define DVOC_SRCDIM _MMIO(0x61164)
4411 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
4412 #define DVO_SRCDIM_VERTICAL_SHIFT 0
4414 /* LVDS port control */
4415 #define LVDS _MMIO(0x61180)
4417 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4418 * the DPLL semantics change when the LVDS is assigned to that pipe.
4420 #define LVDS_PORT_EN (1 << 31)
4421 /* Selects pipe B for LVDS data. Must be set on pre-965. */
4422 #define LVDS_PIPEB_SELECT (1 << 30)
4423 #define LVDS_PIPE_MASK (1 << 30)
4424 #define LVDS_PIPE(pipe) ((pipe) << 30)
4425 /* LVDS dithering flag on 965/g4x platform */
4426 #define LVDS_ENABLE_DITHER (1 << 25)
4427 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4428 #define LVDS_VSYNC_POLARITY (1 << 21)
4429 #define LVDS_HSYNC_POLARITY (1 << 20)
4431 /* Enable border for unscaled (or aspect-scaled) display */
4432 #define LVDS_BORDER_ENABLE (1 << 15)
4434 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4437 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
4438 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
4439 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
4441 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4442 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4445 #define LVDS_A3_POWER_MASK (3 << 6)
4446 #define LVDS_A3_POWER_DOWN (0 << 6)
4447 #define LVDS_A3_POWER_UP (3 << 6)
4449 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
4452 #define LVDS_CLKB_POWER_MASK (3 << 4)
4453 #define LVDS_CLKB_POWER_DOWN (0 << 4)
4454 #define LVDS_CLKB_POWER_UP (3 << 4)
4456 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
4457 * setting for whether we are in dual-channel mode. The B3 pair will
4458 * additionally only be powered up when LVDS_A3_POWER_UP is set.
4460 #define LVDS_B0B3_POWER_MASK (3 << 2)
4461 #define LVDS_B0B3_POWER_DOWN (0 << 2)
4462 #define LVDS_B0B3_POWER_UP (3 << 2)
4464 /* Video Data Island Packet control */
4465 #define VIDEO_DIP_DATA _MMIO(0x61178)
4466 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4467 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4468 * of the infoframe structure specified by CEA-861. */
4469 #define VIDEO_DIP_DATA_SIZE 32
4470 #define VIDEO_DIP_VSC_DATA_SIZE 36
4471 #define VIDEO_DIP_CTL _MMIO(0x61170)
4473 #define VIDEO_DIP_ENABLE (1 << 31)
4474 #define VIDEO_DIP_PORT(port) ((port) << 29)
4475 #define VIDEO_DIP_PORT_MASK (3 << 29)
4476 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
4477 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
4478 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
4479 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
4480 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
4481 #define VIDEO_DIP_SELECT_AVI (0 << 19)
4482 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
4483 #define VIDEO_DIP_SELECT_SPD (3 << 19)
4484 #define VIDEO_DIP_SELECT_MASK (3 << 19)
4485 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
4486 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
4487 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
4488 #define VIDEO_DIP_FREQ_MASK (3 << 16)
4489 /* HSW and later: */
4490 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4491 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
4492 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
4493 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
4494 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
4495 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
4497 /* Panel power sequencing */
4498 #define PPS_BASE 0x61200
4499 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
4500 #define PCH_PPS_BASE 0xC7200
4502 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
4503 PPS_BASE + (reg) + \
4506 #define _PP_STATUS 0x61200
4507 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
4508 #define PP_ON (1 << 31)
4510 * Indicates that all dependencies of the panel are on:
4514 * - LVDS/DVOB/DVOC on
4516 #define PP_READY (1 << 30)
4517 #define PP_SEQUENCE_NONE (0 << 28)
4518 #define PP_SEQUENCE_POWER_UP (1 << 28)
4519 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
4520 #define PP_SEQUENCE_MASK (3 << 28)
4521 #define PP_SEQUENCE_SHIFT 28
4522 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
4523 #define PP_SEQUENCE_STATE_MASK 0x0000000f
4524 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
4525 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
4526 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
4527 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
4528 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
4529 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
4530 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
4531 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
4532 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
4534 #define _PP_CONTROL 0x61204
4535 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
4536 #define PANEL_UNLOCK_REGS (0xabcd << 16)
4537 #define PANEL_UNLOCK_MASK (0xffff << 16)
4538 #define BXT_POWER_CYCLE_DELAY_MASK 0x1f0
4539 #define BXT_POWER_CYCLE_DELAY_SHIFT 4
4540 #define EDP_FORCE_VDD (1 << 3)
4541 #define EDP_BLC_ENABLE (1 << 2)
4542 #define PANEL_POWER_RESET (1 << 1)
4543 #define PANEL_POWER_OFF (0 << 0)
4544 #define PANEL_POWER_ON (1 << 0)
4546 #define _PP_ON_DELAYS 0x61208
4547 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4548 #define PANEL_PORT_SELECT_SHIFT 30
4549 #define PANEL_PORT_SELECT_MASK (3 << 30)
4550 #define PANEL_PORT_SELECT_LVDS (0 << 30)
4551 #define PANEL_PORT_SELECT_DPA (1 << 30)
4552 #define PANEL_PORT_SELECT_DPC (2 << 30)
4553 #define PANEL_PORT_SELECT_DPD (3 << 30)
4554 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
4555 #define PANEL_POWER_UP_DELAY_MASK 0x1fff0000
4556 #define PANEL_POWER_UP_DELAY_SHIFT 16
4557 #define PANEL_LIGHT_ON_DELAY_MASK 0x1fff
4558 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
4560 #define _PP_OFF_DELAYS 0x6120C
4561 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4562 #define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000
4563 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
4564 #define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff
4565 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4567 #define _PP_DIVISOR 0x61210
4568 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
4569 #define PP_REFERENCE_DIVIDER_MASK 0xffffff00
4570 #define PP_REFERENCE_DIVIDER_SHIFT 8
4571 #define PANEL_POWER_CYCLE_DELAY_MASK 0x1f
4572 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4575 #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
4576 #define PFIT_ENABLE (1 << 31)
4577 #define PFIT_PIPE_MASK (3 << 29)
4578 #define PFIT_PIPE_SHIFT 29
4579 #define VERT_INTERP_DISABLE (0 << 10)
4580 #define VERT_INTERP_BILINEAR (1 << 10)
4581 #define VERT_INTERP_MASK (3 << 10)
4582 #define VERT_AUTO_SCALE (1 << 9)
4583 #define HORIZ_INTERP_DISABLE (0 << 6)
4584 #define HORIZ_INTERP_BILINEAR (1 << 6)
4585 #define HORIZ_INTERP_MASK (3 << 6)
4586 #define HORIZ_AUTO_SCALE (1 << 5)
4587 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
4588 #define PFIT_FILTER_FUZZY (0 << 24)
4589 #define PFIT_SCALING_AUTO (0 << 26)
4590 #define PFIT_SCALING_PROGRAMMED (1 << 26)
4591 #define PFIT_SCALING_PILLAR (2 << 26)
4592 #define PFIT_SCALING_LETTER (3 << 26)
4593 #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
4595 #define PFIT_VERT_SCALE_SHIFT 20
4596 #define PFIT_VERT_SCALE_MASK 0xfff00000
4597 #define PFIT_HORIZ_SCALE_SHIFT 4
4598 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
4600 #define PFIT_VERT_SCALE_SHIFT_965 16
4601 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
4602 #define PFIT_HORIZ_SCALE_SHIFT_965 0
4603 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
4605 #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
4607 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
4608 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
4609 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4610 _VLV_BLC_PWM_CTL2_B)
4612 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
4613 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
4614 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4617 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
4618 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
4619 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4620 _VLV_BLC_HIST_CTL_B)
4622 /* Backlight control */
4623 #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
4624 #define BLM_PWM_ENABLE (1 << 31)
4625 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
4626 #define BLM_PIPE_SELECT (1 << 29)
4627 #define BLM_PIPE_SELECT_IVB (3 << 29)
4628 #define BLM_PIPE_A (0 << 29)
4629 #define BLM_PIPE_B (1 << 29)
4630 #define BLM_PIPE_C (2 << 29) /* ivb + */
4631 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
4632 #define BLM_TRANSCODER_B BLM_PIPE_B
4633 #define BLM_TRANSCODER_C BLM_PIPE_C
4634 #define BLM_TRANSCODER_EDP (3 << 29)
4635 #define BLM_PIPE(pipe) ((pipe) << 29)
4636 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
4637 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
4638 #define BLM_PHASE_IN_ENABLE (1 << 25)
4639 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
4640 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
4641 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
4642 #define BLM_PHASE_IN_COUNT_SHIFT (8)
4643 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
4644 #define BLM_PHASE_IN_INCR_SHIFT (0)
4645 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
4646 #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
4648 * This is the most significant 15 bits of the number of backlight cycles in a
4649 * complete cycle of the modulated backlight control.
4651 * The actual value is this field multiplied by two.
4653 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
4654 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
4655 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
4657 * This is the number of cycles out of the backlight modulation cycle for which
4658 * the backlight is on.
4660 * This field must be no greater than the number of cycles in the complete
4661 * backlight modulation cycle.
4663 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
4664 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
4665 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
4666 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
4668 #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
4669 #define BLM_HISTOGRAM_ENABLE (1 << 31)
4671 /* New registers for PCH-split platforms. Safe where new bits show up, the
4672 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
4673 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
4674 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
4676 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
4678 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
4679 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
4680 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
4681 #define BLM_PCH_PWM_ENABLE (1 << 31)
4682 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
4683 #define BLM_PCH_POLARITY (1 << 29)
4684 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
4686 #define UTIL_PIN_CTL _MMIO(0x48400)
4687 #define UTIL_PIN_ENABLE (1 << 31)
4689 #define UTIL_PIN_PIPE(x) ((x) << 29)
4690 #define UTIL_PIN_PIPE_MASK (3 << 29)
4691 #define UTIL_PIN_MODE_PWM (1 << 24)
4692 #define UTIL_PIN_MODE_MASK (0xf << 24)
4693 #define UTIL_PIN_POLARITY (1 << 22)
4695 /* BXT backlight register definition. */
4696 #define _BXT_BLC_PWM_CTL1 0xC8250
4697 #define BXT_BLC_PWM_ENABLE (1 << 31)
4698 #define BXT_BLC_PWM_POLARITY (1 << 29)
4699 #define _BXT_BLC_PWM_FREQ1 0xC8254
4700 #define _BXT_BLC_PWM_DUTY1 0xC8258
4702 #define _BXT_BLC_PWM_CTL2 0xC8350
4703 #define _BXT_BLC_PWM_FREQ2 0xC8354
4704 #define _BXT_BLC_PWM_DUTY2 0xC8358
4706 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
4707 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
4708 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
4709 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
4710 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
4711 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
4713 #define PCH_GTC_CTL _MMIO(0xe7000)
4714 #define PCH_GTC_ENABLE (1 << 31)
4716 /* TV port control */
4717 #define TV_CTL _MMIO(0x68000)
4718 /* Enables the TV encoder */
4719 # define TV_ENC_ENABLE (1 << 31)
4720 /* Sources the TV encoder input from pipe B instead of A. */
4721 # define TV_ENC_PIPEB_SELECT (1 << 30)
4722 /* Outputs composite video (DAC A only) */
4723 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
4724 /* Outputs SVideo video (DAC B/C) */
4725 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
4726 /* Outputs Component video (DAC A/B/C) */
4727 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
4728 /* Outputs Composite and SVideo (DAC A/B/C) */
4729 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
4730 # define TV_TRILEVEL_SYNC (1 << 21)
4731 /* Enables slow sync generation (945GM only) */
4732 # define TV_SLOW_SYNC (1 << 20)
4733 /* Selects 4x oversampling for 480i and 576p */
4734 # define TV_OVERSAMPLE_4X (0 << 18)
4735 /* Selects 2x oversampling for 720p and 1080i */
4736 # define TV_OVERSAMPLE_2X (1 << 18)
4737 /* Selects no oversampling for 1080p */
4738 # define TV_OVERSAMPLE_NONE (2 << 18)
4739 /* Selects 8x oversampling */
4740 # define TV_OVERSAMPLE_8X (3 << 18)
4741 /* Selects progressive mode rather than interlaced */
4742 # define TV_PROGRESSIVE (1 << 17)
4743 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
4744 # define TV_PAL_BURST (1 << 16)
4745 /* Field for setting delay of Y compared to C */
4746 # define TV_YC_SKEW_MASK (7 << 12)
4747 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
4748 # define TV_ENC_SDP_FIX (1 << 11)
4750 * Enables a fix for the 915GM only.
4752 * Not sure what it does.
4754 # define TV_ENC_C0_FIX (1 << 10)
4755 /* Bits that must be preserved by software */
4756 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
4757 # define TV_FUSE_STATE_MASK (3 << 4)
4758 /* Read-only state that reports all features enabled */
4759 # define TV_FUSE_STATE_ENABLED (0 << 4)
4760 /* Read-only state that reports that Macrovision is disabled in hardware*/
4761 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
4762 /* Read-only state that reports that TV-out is disabled in hardware. */
4763 # define TV_FUSE_STATE_DISABLED (2 << 4)
4764 /* Normal operation */
4765 # define TV_TEST_MODE_NORMAL (0 << 0)
4766 /* Encoder test pattern 1 - combo pattern */
4767 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
4768 /* Encoder test pattern 2 - full screen vertical 75% color bars */
4769 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
4770 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
4771 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
4772 /* Encoder test pattern 4 - random noise */
4773 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
4774 /* Encoder test pattern 5 - linear color ramps */
4775 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
4777 * This test mode forces the DACs to 50% of full output.
4779 * This is used for load detection in combination with TVDAC_SENSE_MASK
4781 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
4782 # define TV_TEST_MODE_MASK (7 << 0)
4784 #define TV_DAC _MMIO(0x68004)
4785 # define TV_DAC_SAVE 0x00ffff00
4787 * Reports that DAC state change logic has reported change (RO).
4789 * This gets cleared when TV_DAC_STATE_EN is cleared
4791 # define TVDAC_STATE_CHG (1 << 31)
4792 # define TVDAC_SENSE_MASK (7 << 28)
4793 /* Reports that DAC A voltage is above the detect threshold */
4794 # define TVDAC_A_SENSE (1 << 30)
4795 /* Reports that DAC B voltage is above the detect threshold */
4796 # define TVDAC_B_SENSE (1 << 29)
4797 /* Reports that DAC C voltage is above the detect threshold */
4798 # define TVDAC_C_SENSE (1 << 28)
4800 * Enables DAC state detection logic, for load-based TV detection.
4802 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
4803 * to off, for load detection to work.
4805 # define TVDAC_STATE_CHG_EN (1 << 27)
4806 /* Sets the DAC A sense value to high */
4807 # define TVDAC_A_SENSE_CTL (1 << 26)
4808 /* Sets the DAC B sense value to high */
4809 # define TVDAC_B_SENSE_CTL (1 << 25)
4810 /* Sets the DAC C sense value to high */
4811 # define TVDAC_C_SENSE_CTL (1 << 24)
4812 /* Overrides the ENC_ENABLE and DAC voltage levels */
4813 # define DAC_CTL_OVERRIDE (1 << 7)
4814 /* Sets the slew rate. Must be preserved in software */
4815 # define ENC_TVDAC_SLEW_FAST (1 << 6)
4816 # define DAC_A_1_3_V (0 << 4)
4817 # define DAC_A_1_1_V (1 << 4)
4818 # define DAC_A_0_7_V (2 << 4)
4819 # define DAC_A_MASK (3 << 4)
4820 # define DAC_B_1_3_V (0 << 2)
4821 # define DAC_B_1_1_V (1 << 2)
4822 # define DAC_B_0_7_V (2 << 2)
4823 # define DAC_B_MASK (3 << 2)
4824 # define DAC_C_1_3_V (0 << 0)
4825 # define DAC_C_1_1_V (1 << 0)
4826 # define DAC_C_0_7_V (2 << 0)
4827 # define DAC_C_MASK (3 << 0)
4830 * CSC coefficients are stored in a floating point format with 9 bits of
4831 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
4832 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
4833 * -1 (0x3) being the only legal negative value.
4835 #define TV_CSC_Y _MMIO(0x68010)
4836 # define TV_RY_MASK 0x07ff0000
4837 # define TV_RY_SHIFT 16
4838 # define TV_GY_MASK 0x00000fff
4839 # define TV_GY_SHIFT 0
4841 #define TV_CSC_Y2 _MMIO(0x68014)
4842 # define TV_BY_MASK 0x07ff0000
4843 # define TV_BY_SHIFT 16
4845 * Y attenuation for component video.
4847 * Stored in 1.9 fixed point.
4849 # define TV_AY_MASK 0x000003ff
4850 # define TV_AY_SHIFT 0
4852 #define TV_CSC_U _MMIO(0x68018)
4853 # define TV_RU_MASK 0x07ff0000
4854 # define TV_RU_SHIFT 16
4855 # define TV_GU_MASK 0x000007ff
4856 # define TV_GU_SHIFT 0
4858 #define TV_CSC_U2 _MMIO(0x6801c)
4859 # define TV_BU_MASK 0x07ff0000
4860 # define TV_BU_SHIFT 16
4862 * U attenuation for component video.
4864 * Stored in 1.9 fixed point.
4866 # define TV_AU_MASK 0x000003ff
4867 # define TV_AU_SHIFT 0
4869 #define TV_CSC_V _MMIO(0x68020)
4870 # define TV_RV_MASK 0x0fff0000
4871 # define TV_RV_SHIFT 16
4872 # define TV_GV_MASK 0x000007ff
4873 # define TV_GV_SHIFT 0
4875 #define TV_CSC_V2 _MMIO(0x68024)
4876 # define TV_BV_MASK 0x07ff0000
4877 # define TV_BV_SHIFT 16
4879 * V attenuation for component video.
4881 * Stored in 1.9 fixed point.
4883 # define TV_AV_MASK 0x000007ff
4884 # define TV_AV_SHIFT 0
4886 #define TV_CLR_KNOBS _MMIO(0x68028)
4887 /* 2s-complement brightness adjustment */
4888 # define TV_BRIGHTNESS_MASK 0xff000000
4889 # define TV_BRIGHTNESS_SHIFT 24
4890 /* Contrast adjustment, as a 2.6 unsigned floating point number */
4891 # define TV_CONTRAST_MASK 0x00ff0000
4892 # define TV_CONTRAST_SHIFT 16
4893 /* Saturation adjustment, as a 2.6 unsigned floating point number */
4894 # define TV_SATURATION_MASK 0x0000ff00
4895 # define TV_SATURATION_SHIFT 8
4896 /* Hue adjustment, as an integer phase angle in degrees */
4897 # define TV_HUE_MASK 0x000000ff
4898 # define TV_HUE_SHIFT 0
4900 #define TV_CLR_LEVEL _MMIO(0x6802c)
4901 /* Controls the DAC level for black */
4902 # define TV_BLACK_LEVEL_MASK 0x01ff0000
4903 # define TV_BLACK_LEVEL_SHIFT 16
4904 /* Controls the DAC level for blanking */
4905 # define TV_BLANK_LEVEL_MASK 0x000001ff
4906 # define TV_BLANK_LEVEL_SHIFT 0
4908 #define TV_H_CTL_1 _MMIO(0x68030)
4909 /* Number of pixels in the hsync. */
4910 # define TV_HSYNC_END_MASK 0x1fff0000
4911 # define TV_HSYNC_END_SHIFT 16
4912 /* Total number of pixels minus one in the line (display and blanking). */
4913 # define TV_HTOTAL_MASK 0x00001fff
4914 # define TV_HTOTAL_SHIFT 0
4916 #define TV_H_CTL_2 _MMIO(0x68034)
4917 /* Enables the colorburst (needed for non-component color) */
4918 # define TV_BURST_ENA (1 << 31)
4919 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
4920 # define TV_HBURST_START_SHIFT 16
4921 # define TV_HBURST_START_MASK 0x1fff0000
4922 /* Length of the colorburst */
4923 # define TV_HBURST_LEN_SHIFT 0
4924 # define TV_HBURST_LEN_MASK 0x0001fff
4926 #define TV_H_CTL_3 _MMIO(0x68038)
4927 /* End of hblank, measured in pixels minus one from start of hsync */
4928 # define TV_HBLANK_END_SHIFT 16
4929 # define TV_HBLANK_END_MASK 0x1fff0000
4930 /* Start of hblank, measured in pixels minus one from start of hsync */
4931 # define TV_HBLANK_START_SHIFT 0
4932 # define TV_HBLANK_START_MASK 0x0001fff
4934 #define TV_V_CTL_1 _MMIO(0x6803c)
4936 # define TV_NBR_END_SHIFT 16
4937 # define TV_NBR_END_MASK 0x07ff0000
4939 # define TV_VI_END_F1_SHIFT 8
4940 # define TV_VI_END_F1_MASK 0x00003f00
4942 # define TV_VI_END_F2_SHIFT 0
4943 # define TV_VI_END_F2_MASK 0x0000003f
4945 #define TV_V_CTL_2 _MMIO(0x68040)
4946 /* Length of vsync, in half lines */
4947 # define TV_VSYNC_LEN_MASK 0x07ff0000
4948 # define TV_VSYNC_LEN_SHIFT 16
4949 /* Offset of the start of vsync in field 1, measured in one less than the
4950 * number of half lines.
4952 # define TV_VSYNC_START_F1_MASK 0x00007f00
4953 # define TV_VSYNC_START_F1_SHIFT 8
4955 * Offset of the start of vsync in field 2, measured in one less than the
4956 * number of half lines.
4958 # define TV_VSYNC_START_F2_MASK 0x0000007f
4959 # define TV_VSYNC_START_F2_SHIFT 0
4961 #define TV_V_CTL_3 _MMIO(0x68044)
4962 /* Enables generation of the equalization signal */
4963 # define TV_EQUAL_ENA (1 << 31)
4964 /* Length of vsync, in half lines */
4965 # define TV_VEQ_LEN_MASK 0x007f0000
4966 # define TV_VEQ_LEN_SHIFT 16
4967 /* Offset of the start of equalization in field 1, measured in one less than
4968 * the number of half lines.
4970 # define TV_VEQ_START_F1_MASK 0x0007f00
4971 # define TV_VEQ_START_F1_SHIFT 8
4973 * Offset of the start of equalization in field 2, measured in one less than
4974 * the number of half lines.
4976 # define TV_VEQ_START_F2_MASK 0x000007f
4977 # define TV_VEQ_START_F2_SHIFT 0
4979 #define TV_V_CTL_4 _MMIO(0x68048)
4981 * Offset to start of vertical colorburst, measured in one less than the
4982 * number of lines from vertical start.
4984 # define TV_VBURST_START_F1_MASK 0x003f0000
4985 # define TV_VBURST_START_F1_SHIFT 16
4987 * Offset to the end of vertical colorburst, measured in one less than the
4988 * number of lines from the start of NBR.
4990 # define TV_VBURST_END_F1_MASK 0x000000ff
4991 # define TV_VBURST_END_F1_SHIFT 0
4993 #define TV_V_CTL_5 _MMIO(0x6804c)
4995 * Offset to start of vertical colorburst, measured in one less than the
4996 * number of lines from vertical start.
4998 # define TV_VBURST_START_F2_MASK 0x003f0000
4999 # define TV_VBURST_START_F2_SHIFT 16
5001 * Offset to the end of vertical colorburst, measured in one less than the
5002 * number of lines from the start of NBR.
5004 # define TV_VBURST_END_F2_MASK 0x000000ff
5005 # define TV_VBURST_END_F2_SHIFT 0
5007 #define TV_V_CTL_6 _MMIO(0x68050)
5009 * Offset to start of vertical colorburst, measured in one less than the
5010 * number of lines from vertical start.
5012 # define TV_VBURST_START_F3_MASK 0x003f0000
5013 # define TV_VBURST_START_F3_SHIFT 16
5015 * Offset to the end of vertical colorburst, measured in one less than the
5016 * number of lines from the start of NBR.
5018 # define TV_VBURST_END_F3_MASK 0x000000ff
5019 # define TV_VBURST_END_F3_SHIFT 0
5021 #define TV_V_CTL_7 _MMIO(0x68054)
5023 * Offset to start of vertical colorburst, measured in one less than the
5024 * number of lines from vertical start.
5026 # define TV_VBURST_START_F4_MASK 0x003f0000
5027 # define TV_VBURST_START_F4_SHIFT 16
5029 * Offset to the end of vertical colorburst, measured in one less than the
5030 * number of lines from the start of NBR.
5032 # define TV_VBURST_END_F4_MASK 0x000000ff
5033 # define TV_VBURST_END_F4_SHIFT 0
5035 #define TV_SC_CTL_1 _MMIO(0x68060)
5036 /* Turns on the first subcarrier phase generation DDA */
5037 # define TV_SC_DDA1_EN (1 << 31)
5038 /* Turns on the first subcarrier phase generation DDA */
5039 # define TV_SC_DDA2_EN (1 << 30)
5040 /* Turns on the first subcarrier phase generation DDA */
5041 # define TV_SC_DDA3_EN (1 << 29)
5042 /* Sets the subcarrier DDA to reset frequency every other field */
5043 # define TV_SC_RESET_EVERY_2 (0 << 24)
5044 /* Sets the subcarrier DDA to reset frequency every fourth field */
5045 # define TV_SC_RESET_EVERY_4 (1 << 24)
5046 /* Sets the subcarrier DDA to reset frequency every eighth field */
5047 # define TV_SC_RESET_EVERY_8 (2 << 24)
5048 /* Sets the subcarrier DDA to never reset the frequency */
5049 # define TV_SC_RESET_NEVER (3 << 24)
5050 /* Sets the peak amplitude of the colorburst.*/
5051 # define TV_BURST_LEVEL_MASK 0x00ff0000
5052 # define TV_BURST_LEVEL_SHIFT 16
5053 /* Sets the increment of the first subcarrier phase generation DDA */
5054 # define TV_SCDDA1_INC_MASK 0x00000fff
5055 # define TV_SCDDA1_INC_SHIFT 0
5057 #define TV_SC_CTL_2 _MMIO(0x68064)
5058 /* Sets the rollover for the second subcarrier phase generation DDA */
5059 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
5060 # define TV_SCDDA2_SIZE_SHIFT 16
5061 /* Sets the increent of the second subcarrier phase generation DDA */
5062 # define TV_SCDDA2_INC_MASK 0x00007fff
5063 # define TV_SCDDA2_INC_SHIFT 0
5065 #define TV_SC_CTL_3 _MMIO(0x68068)
5066 /* Sets the rollover for the third subcarrier phase generation DDA */
5067 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
5068 # define TV_SCDDA3_SIZE_SHIFT 16
5069 /* Sets the increent of the third subcarrier phase generation DDA */
5070 # define TV_SCDDA3_INC_MASK 0x00007fff
5071 # define TV_SCDDA3_INC_SHIFT 0
5073 #define TV_WIN_POS _MMIO(0x68070)
5074 /* X coordinate of the display from the start of horizontal active */
5075 # define TV_XPOS_MASK 0x1fff0000
5076 # define TV_XPOS_SHIFT 16
5077 /* Y coordinate of the display from the start of vertical active (NBR) */
5078 # define TV_YPOS_MASK 0x00000fff
5079 # define TV_YPOS_SHIFT 0
5081 #define TV_WIN_SIZE _MMIO(0x68074)
5082 /* Horizontal size of the display window, measured in pixels*/
5083 # define TV_XSIZE_MASK 0x1fff0000
5084 # define TV_XSIZE_SHIFT 16
5086 * Vertical size of the display window, measured in pixels.
5088 * Must be even for interlaced modes.
5090 # define TV_YSIZE_MASK 0x00000fff
5091 # define TV_YSIZE_SHIFT 0
5093 #define TV_FILTER_CTL_1 _MMIO(0x68080)
5095 * Enables automatic scaling calculation.
5097 * If set, the rest of the registers are ignored, and the calculated values can
5098 * be read back from the register.
5100 # define TV_AUTO_SCALE (1 << 31)
5102 * Disables the vertical filter.
5104 * This is required on modes more than 1024 pixels wide */
5105 # define TV_V_FILTER_BYPASS (1 << 29)
5106 /* Enables adaptive vertical filtering */
5107 # define TV_VADAPT (1 << 28)
5108 # define TV_VADAPT_MODE_MASK (3 << 26)
5109 /* Selects the least adaptive vertical filtering mode */
5110 # define TV_VADAPT_MODE_LEAST (0 << 26)
5111 /* Selects the moderately adaptive vertical filtering mode */
5112 # define TV_VADAPT_MODE_MODERATE (1 << 26)
5113 /* Selects the most adaptive vertical filtering mode */
5114 # define TV_VADAPT_MODE_MOST (3 << 26)
5116 * Sets the horizontal scaling factor.
5118 * This should be the fractional part of the horizontal scaling factor divided
5119 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5121 * (src width - 1) / ((oversample * dest width) - 1)
5123 # define TV_HSCALE_FRAC_MASK 0x00003fff
5124 # define TV_HSCALE_FRAC_SHIFT 0
5126 #define TV_FILTER_CTL_2 _MMIO(0x68084)
5128 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5130 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5132 # define TV_VSCALE_INT_MASK 0x00038000
5133 # define TV_VSCALE_INT_SHIFT 15
5135 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5137 * \sa TV_VSCALE_INT_MASK
5139 # define TV_VSCALE_FRAC_MASK 0x00007fff
5140 # define TV_VSCALE_FRAC_SHIFT 0
5142 #define TV_FILTER_CTL_3 _MMIO(0x68088)
5144 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5146 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5148 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5150 # define TV_VSCALE_IP_INT_MASK 0x00038000
5151 # define TV_VSCALE_IP_INT_SHIFT 15
5153 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5155 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5157 * \sa TV_VSCALE_IP_INT_MASK
5159 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5160 # define TV_VSCALE_IP_FRAC_SHIFT 0
5162 #define TV_CC_CONTROL _MMIO(0x68090)
5163 # define TV_CC_ENABLE (1 << 31)
5165 * Specifies which field to send the CC data in.
5167 * CC data is usually sent in field 0.
5169 # define TV_CC_FID_MASK (1 << 27)
5170 # define TV_CC_FID_SHIFT 27
5171 /* Sets the horizontal position of the CC data. Usually 135. */
5172 # define TV_CC_HOFF_MASK 0x03ff0000
5173 # define TV_CC_HOFF_SHIFT 16
5174 /* Sets the vertical position of the CC data. Usually 21 */
5175 # define TV_CC_LINE_MASK 0x0000003f
5176 # define TV_CC_LINE_SHIFT 0
5178 #define TV_CC_DATA _MMIO(0x68094)
5179 # define TV_CC_RDY (1 << 31)
5180 /* Second word of CC data to be transmitted. */
5181 # define TV_CC_DATA_2_MASK 0x007f0000
5182 # define TV_CC_DATA_2_SHIFT 16
5183 /* First word of CC data to be transmitted. */
5184 # define TV_CC_DATA_1_MASK 0x0000007f
5185 # define TV_CC_DATA_1_SHIFT 0
5187 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
5188 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
5189 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
5190 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
5193 #define DP_A _MMIO(0x64000) /* eDP */
5194 #define DP_B _MMIO(0x64100)
5195 #define DP_C _MMIO(0x64200)
5196 #define DP_D _MMIO(0x64300)
5198 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5199 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5200 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5202 #define DP_PORT_EN (1 << 31)
5203 #define DP_PIPEB_SELECT (1 << 30)
5204 #define DP_PIPE_MASK (1 << 30)
5205 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
5206 #define DP_PIPE_MASK_CHV (3 << 16)
5208 /* Link training mode - select a suitable mode for each stage */
5209 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
5210 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
5211 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
5212 #define DP_LINK_TRAIN_OFF (3 << 28)
5213 #define DP_LINK_TRAIN_MASK (3 << 28)
5214 #define DP_LINK_TRAIN_SHIFT 28
5215 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
5216 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
5218 /* CPT Link training mode */
5219 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
5220 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
5221 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
5222 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
5223 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
5224 #define DP_LINK_TRAIN_SHIFT_CPT 8
5226 /* Signal voltages. These are mostly controlled by the other end */
5227 #define DP_VOLTAGE_0_4 (0 << 25)
5228 #define DP_VOLTAGE_0_6 (1 << 25)
5229 #define DP_VOLTAGE_0_8 (2 << 25)
5230 #define DP_VOLTAGE_1_2 (3 << 25)
5231 #define DP_VOLTAGE_MASK (7 << 25)
5232 #define DP_VOLTAGE_SHIFT 25
5234 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5237 #define DP_PRE_EMPHASIS_0 (0 << 22)
5238 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
5239 #define DP_PRE_EMPHASIS_6 (2 << 22)
5240 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
5241 #define DP_PRE_EMPHASIS_MASK (7 << 22)
5242 #define DP_PRE_EMPHASIS_SHIFT 22
5244 /* How many wires to use. I guess 3 was too hard */
5245 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5246 #define DP_PORT_WIDTH_MASK (7 << 19)
5247 #define DP_PORT_WIDTH_SHIFT 19
5249 /* Mystic DPCD version 1.1 special mode */
5250 #define DP_ENHANCED_FRAMING (1 << 18)
5253 #define DP_PLL_FREQ_270MHZ (0 << 16)
5254 #define DP_PLL_FREQ_162MHZ (1 << 16)
5255 #define DP_PLL_FREQ_MASK (3 << 16)
5257 /* locked once port is enabled */
5258 #define DP_PORT_REVERSAL (1 << 15)
5261 #define DP_PLL_ENABLE (1 << 14)
5263 /* sends the clock on lane 15 of the PEG for debug */
5264 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
5266 #define DP_SCRAMBLING_DISABLE (1 << 12)
5267 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
5269 /* limit RGB values to avoid confusing TVs */
5270 #define DP_COLOR_RANGE_16_235 (1 << 8)
5272 /* Turn on the audio link */
5273 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
5275 /* vs and hs sync polarity */
5276 #define DP_SYNC_VS_HIGH (1 << 4)
5277 #define DP_SYNC_HS_HIGH (1 << 3)
5280 #define DP_DETECTED (1 << 2)
5282 /* The aux channel provides a way to talk to the
5283 * signal sink for DDC etc. Max packet size supported
5284 * is 20 bytes in each direction, hence the 5 fixed
5287 #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
5288 #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
5289 #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
5290 #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
5291 #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
5292 #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
5294 #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
5295 #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
5296 #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
5297 #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
5298 #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
5299 #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
5301 #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
5302 #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
5303 #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
5304 #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
5305 #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
5306 #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
5308 #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
5309 #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
5310 #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
5311 #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
5312 #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
5313 #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
5315 #define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
5316 #define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
5317 #define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
5318 #define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
5319 #define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
5320 #define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
5322 #define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5323 #define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5325 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
5326 #define DP_AUX_CH_CTL_DONE (1 << 30)
5327 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
5328 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
5329 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
5330 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
5331 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
5332 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
5333 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
5334 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
5335 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
5336 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
5337 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
5338 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
5339 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
5340 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
5341 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
5342 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
5343 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
5344 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
5345 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
5346 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5347 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5348 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
5349 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5350 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5351 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
5354 * Computing GMCH M and N values for the Display Port link
5356 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5358 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5360 * The GMCH value is used internally
5362 * bytes_per_pixel is the number of bytes coming out of the plane,
5363 * which is after the LUTs, so we want the bytes for our color format.
5364 * For our current usage, this is always 3, one byte for R, G and B.
5366 #define _PIPEA_DATA_M_G4X 0x70050
5367 #define _PIPEB_DATA_M_G4X 0x71050
5369 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5370 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
5371 #define TU_SIZE_SHIFT 25
5372 #define TU_SIZE_MASK (0x3f << 25)
5374 #define DATA_LINK_M_N_MASK (0xffffff)
5375 #define DATA_LINK_N_MAX (0x800000)
5377 #define _PIPEA_DATA_N_G4X 0x70054
5378 #define _PIPEB_DATA_N_G4X 0x71054
5379 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
5382 * Computing Link M and N values for the Display Port link
5384 * Link M / N = pixel_clock / ls_clk
5386 * (the DP spec calls pixel_clock the 'strm_clk')
5388 * The Link value is transmitted in the Main Stream
5389 * Attributes and VB-ID.
5392 #define _PIPEA_LINK_M_G4X 0x70060
5393 #define _PIPEB_LINK_M_G4X 0x71060
5394 #define PIPEA_DP_LINK_M_MASK (0xffffff)
5396 #define _PIPEA_LINK_N_G4X 0x70064
5397 #define _PIPEB_LINK_N_G4X 0x71064
5398 #define PIPEA_DP_LINK_N_MASK (0xffffff)
5400 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5401 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5402 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5403 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5405 /* Display & cursor control */
5408 #define _PIPEADSL 0x70000
5409 #define DSL_LINEMASK_GEN2 0x00000fff
5410 #define DSL_LINEMASK_GEN3 0x00001fff
5411 #define _PIPEACONF 0x70008
5412 #define PIPECONF_ENABLE (1<<31)
5413 #define PIPECONF_DISABLE 0
5414 #define PIPECONF_DOUBLE_WIDE (1<<30)
5415 #define I965_PIPECONF_ACTIVE (1<<30)
5416 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
5417 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
5418 #define PIPECONF_SINGLE_WIDE 0
5419 #define PIPECONF_PIPE_UNLOCKED 0
5420 #define PIPECONF_PIPE_LOCKED (1<<25)
5421 #define PIPECONF_PALETTE 0
5422 #define PIPECONF_GAMMA (1<<24)
5423 #define PIPECONF_FORCE_BORDER (1<<25)
5424 #define PIPECONF_INTERLACE_MASK (7 << 21)
5425 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
5426 /* Note that pre-gen3 does not support interlaced display directly. Panel
5427 * fitting must be disabled on pre-ilk for interlaced. */
5428 #define PIPECONF_PROGRESSIVE (0 << 21)
5429 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
5430 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
5431 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5432 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
5433 /* Ironlake and later have a complete new set of values for interlaced. PFIT
5434 * means panel fitter required, PF means progressive fetch, DBL means power
5435 * saving pixel doubling. */
5436 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
5437 #define PIPECONF_INTERLACED_ILK (3 << 21)
5438 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
5439 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
5440 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
5441 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
5442 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
5443 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
5444 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
5445 #define PIPECONF_BPC_MASK (0x7 << 5)
5446 #define PIPECONF_8BPC (0<<5)
5447 #define PIPECONF_10BPC (1<<5)
5448 #define PIPECONF_6BPC (2<<5)
5449 #define PIPECONF_12BPC (3<<5)
5450 #define PIPECONF_DITHER_EN (1<<4)
5451 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5452 #define PIPECONF_DITHER_TYPE_SP (0<<2)
5453 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
5454 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
5455 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
5456 #define _PIPEASTAT 0x70024
5457 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
5458 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
5459 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
5460 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
5461 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
5462 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
5463 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
5464 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
5465 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
5466 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
5467 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
5468 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
5469 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
5470 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
5471 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
5472 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
5473 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
5474 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
5475 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
5476 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
5477 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
5478 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
5479 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
5480 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
5481 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
5482 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
5483 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
5484 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
5485 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
5486 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
5487 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
5488 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
5489 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
5490 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
5491 #define PIPE_A_PSR_STATUS_VLV (1UL<<6)
5492 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
5493 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
5494 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
5495 #define PIPE_B_PSR_STATUS_VLV (1UL<<3)
5496 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
5497 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
5498 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
5499 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
5500 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
5501 #define PIPE_HBLANK_INT_STATUS (1UL<<0)
5502 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
5504 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
5505 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
5507 #define PIPE_A_OFFSET 0x70000
5508 #define PIPE_B_OFFSET 0x71000
5509 #define PIPE_C_OFFSET 0x72000
5510 #define CHV_PIPE_C_OFFSET 0x74000
5512 * There's actually no pipe EDP. Some pipe registers have
5513 * simply shifted from the pipe to the transcoder, while
5514 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5515 * to access such registers in transcoder EDP.
5517 #define PIPE_EDP_OFFSET 0x7f000
5519 #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
5520 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
5521 dev_priv->info.display_mmio_offset)
5523 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5524 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
5525 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5526 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5527 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
5529 #define _PIPE_MISC_A 0x70030
5530 #define _PIPE_MISC_B 0x71030
5531 #define PIPEMISC_YUV420_ENABLE (1<<27)
5532 #define PIPEMISC_YUV420_MODE_FULL_BLEND (1<<26)
5533 #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1<<11)
5534 #define PIPEMISC_DITHER_BPC_MASK (7<<5)
5535 #define PIPEMISC_DITHER_8_BPC (0<<5)
5536 #define PIPEMISC_DITHER_10_BPC (1<<5)
5537 #define PIPEMISC_DITHER_6_BPC (2<<5)
5538 #define PIPEMISC_DITHER_12_BPC (3<<5)
5539 #define PIPEMISC_DITHER_ENABLE (1<<4)
5540 #define PIPEMISC_DITHER_TYPE_MASK (3<<2)
5541 #define PIPEMISC_DITHER_TYPE_SP (0<<2)
5542 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
5544 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5545 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
5546 #define PIPEB_HLINE_INT_EN (1<<28)
5547 #define PIPEB_VBLANK_INT_EN (1<<27)
5548 #define SPRITED_FLIP_DONE_INT_EN (1<<26)
5549 #define SPRITEC_FLIP_DONE_INT_EN (1<<25)
5550 #define PLANEB_FLIP_DONE_INT_EN (1<<24)
5551 #define PIPE_PSR_INT_EN (1<<22)
5552 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
5553 #define PIPEA_HLINE_INT_EN (1<<20)
5554 #define PIPEA_VBLANK_INT_EN (1<<19)
5555 #define SPRITEB_FLIP_DONE_INT_EN (1<<18)
5556 #define SPRITEA_FLIP_DONE_INT_EN (1<<17)
5557 #define PLANEA_FLIPDONE_INT_EN (1<<16)
5558 #define PIPEC_LINE_COMPARE_INT_EN (1<<13)
5559 #define PIPEC_HLINE_INT_EN (1<<12)
5560 #define PIPEC_VBLANK_INT_EN (1<<11)
5561 #define SPRITEF_FLIPDONE_INT_EN (1<<10)
5562 #define SPRITEE_FLIPDONE_INT_EN (1<<9)
5563 #define PLANEC_FLIPDONE_INT_EN (1<<8)
5565 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5566 #define SPRITEF_INVALID_GTT_INT_EN (1<<27)
5567 #define SPRITEE_INVALID_GTT_INT_EN (1<<26)
5568 #define PLANEC_INVALID_GTT_INT_EN (1<<25)
5569 #define CURSORC_INVALID_GTT_INT_EN (1<<24)
5570 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
5571 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
5572 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
5573 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
5574 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
5575 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
5576 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
5577 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
5578 #define DPINVGTT_EN_MASK 0xff0000
5579 #define DPINVGTT_EN_MASK_CHV 0xfff0000
5580 #define SPRITEF_INVALID_GTT_STATUS (1<<11)
5581 #define SPRITEE_INVALID_GTT_STATUS (1<<10)
5582 #define PLANEC_INVALID_GTT_STATUS (1<<9)
5583 #define CURSORC_INVALID_GTT_STATUS (1<<8)
5584 #define CURSORB_INVALID_GTT_STATUS (1<<7)
5585 #define CURSORA_INVALID_GTT_STATUS (1<<6)
5586 #define SPRITED_INVALID_GTT_STATUS (1<<5)
5587 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
5588 #define PLANEB_INVALID_GTT_STATUS (1<<3)
5589 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
5590 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
5591 #define PLANEA_INVALID_GTT_STATUS (1<<0)
5592 #define DPINVGTT_STATUS_MASK 0xff
5593 #define DPINVGTT_STATUS_MASK_CHV 0xfff
5595 #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
5596 #define DSPARB_CSTART_MASK (0x7f << 7)
5597 #define DSPARB_CSTART_SHIFT 7
5598 #define DSPARB_BSTART_MASK (0x7f)
5599 #define DSPARB_BSTART_SHIFT 0
5600 #define DSPARB_BEND_SHIFT 9 /* on 855 */
5601 #define DSPARB_AEND_SHIFT 0
5602 #define DSPARB_SPRITEA_SHIFT_VLV 0
5603 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
5604 #define DSPARB_SPRITEB_SHIFT_VLV 8
5605 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
5606 #define DSPARB_SPRITEC_SHIFT_VLV 16
5607 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
5608 #define DSPARB_SPRITED_SHIFT_VLV 24
5609 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
5610 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5611 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
5612 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
5613 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
5614 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
5615 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
5616 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
5617 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
5618 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
5619 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
5620 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
5621 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
5622 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
5623 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5624 #define DSPARB_SPRITEE_SHIFT_VLV 0
5625 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
5626 #define DSPARB_SPRITEF_SHIFT_VLV 8
5627 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
5629 /* pnv/gen4/g4x/vlv/chv */
5630 #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
5631 #define DSPFW_SR_SHIFT 23
5632 #define DSPFW_SR_MASK (0x1ff<<23)
5633 #define DSPFW_CURSORB_SHIFT 16
5634 #define DSPFW_CURSORB_MASK (0x3f<<16)
5635 #define DSPFW_PLANEB_SHIFT 8
5636 #define DSPFW_PLANEB_MASK (0x7f<<8)
5637 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
5638 #define DSPFW_PLANEA_SHIFT 0
5639 #define DSPFW_PLANEA_MASK (0x7f<<0)
5640 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
5641 #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
5642 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */
5643 #define DSPFW_FBC_SR_SHIFT 28
5644 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
5645 #define DSPFW_FBC_HPLL_SR_SHIFT 24
5646 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
5647 #define DSPFW_SPRITEB_SHIFT (16)
5648 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
5649 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
5650 #define DSPFW_CURSORA_SHIFT 8
5651 #define DSPFW_CURSORA_MASK (0x3f<<8)
5652 #define DSPFW_PLANEC_OLD_SHIFT 0
5653 #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
5654 #define DSPFW_SPRITEA_SHIFT 0
5655 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
5656 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
5657 #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
5658 #define DSPFW_HPLL_SR_EN (1<<31)
5659 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
5660 #define DSPFW_CURSOR_SR_SHIFT 24
5661 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
5662 #define DSPFW_HPLL_CURSOR_SHIFT 16
5663 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
5664 #define DSPFW_HPLL_SR_SHIFT 0
5665 #define DSPFW_HPLL_SR_MASK (0x1ff<<0)
5668 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
5669 #define DSPFW_SPRITEB_WM1_SHIFT 16
5670 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
5671 #define DSPFW_CURSORA_WM1_SHIFT 8
5672 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
5673 #define DSPFW_SPRITEA_WM1_SHIFT 0
5674 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
5675 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
5676 #define DSPFW_PLANEB_WM1_SHIFT 24
5677 #define DSPFW_PLANEB_WM1_MASK (0xff<<24)
5678 #define DSPFW_PLANEA_WM1_SHIFT 16
5679 #define DSPFW_PLANEA_WM1_MASK (0xff<<16)
5680 #define DSPFW_CURSORB_WM1_SHIFT 8
5681 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
5682 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
5683 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
5684 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
5685 #define DSPFW_SR_WM1_SHIFT 0
5686 #define DSPFW_SR_WM1_MASK (0x1ff<<0)
5687 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5688 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5689 #define DSPFW_SPRITED_WM1_SHIFT 24
5690 #define DSPFW_SPRITED_WM1_MASK (0xff<<24)
5691 #define DSPFW_SPRITED_SHIFT 16
5692 #define DSPFW_SPRITED_MASK_VLV (0xff<<16)
5693 #define DSPFW_SPRITEC_WM1_SHIFT 8
5694 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
5695 #define DSPFW_SPRITEC_SHIFT 0
5696 #define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
5697 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5698 #define DSPFW_SPRITEF_WM1_SHIFT 24
5699 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
5700 #define DSPFW_SPRITEF_SHIFT 16
5701 #define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
5702 #define DSPFW_SPRITEE_WM1_SHIFT 8
5703 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
5704 #define DSPFW_SPRITEE_SHIFT 0
5705 #define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
5706 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5707 #define DSPFW_PLANEC_WM1_SHIFT 24
5708 #define DSPFW_PLANEC_WM1_MASK (0xff<<24)
5709 #define DSPFW_PLANEC_SHIFT 16
5710 #define DSPFW_PLANEC_MASK_VLV (0xff<<16)
5711 #define DSPFW_CURSORC_WM1_SHIFT 8
5712 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
5713 #define DSPFW_CURSORC_SHIFT 0
5714 #define DSPFW_CURSORC_MASK (0x3f<<0)
5716 /* vlv/chv high order bits */
5717 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
5718 #define DSPFW_SR_HI_SHIFT 24
5719 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
5720 #define DSPFW_SPRITEF_HI_SHIFT 23
5721 #define DSPFW_SPRITEF_HI_MASK (1<<23)
5722 #define DSPFW_SPRITEE_HI_SHIFT 22
5723 #define DSPFW_SPRITEE_HI_MASK (1<<22)
5724 #define DSPFW_PLANEC_HI_SHIFT 21
5725 #define DSPFW_PLANEC_HI_MASK (1<<21)
5726 #define DSPFW_SPRITED_HI_SHIFT 20
5727 #define DSPFW_SPRITED_HI_MASK (1<<20)
5728 #define DSPFW_SPRITEC_HI_SHIFT 16
5729 #define DSPFW_SPRITEC_HI_MASK (1<<16)
5730 #define DSPFW_PLANEB_HI_SHIFT 12
5731 #define DSPFW_PLANEB_HI_MASK (1<<12)
5732 #define DSPFW_SPRITEB_HI_SHIFT 8
5733 #define DSPFW_SPRITEB_HI_MASK (1<<8)
5734 #define DSPFW_SPRITEA_HI_SHIFT 4
5735 #define DSPFW_SPRITEA_HI_MASK (1<<4)
5736 #define DSPFW_PLANEA_HI_SHIFT 0
5737 #define DSPFW_PLANEA_HI_MASK (1<<0)
5738 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
5739 #define DSPFW_SR_WM1_HI_SHIFT 24
5740 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
5741 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
5742 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
5743 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
5744 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
5745 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
5746 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
5747 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
5748 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
5749 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
5750 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
5751 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
5752 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
5753 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
5754 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
5755 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
5756 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
5757 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
5758 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
5760 /* drain latency register values*/
5761 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5762 #define DDL_CURSOR_SHIFT 24
5763 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
5764 #define DDL_PLANE_SHIFT 0
5765 #define DDL_PRECISION_HIGH (1<<7)
5766 #define DDL_PRECISION_LOW (0<<7)
5767 #define DRAIN_LATENCY_MASK 0x7f
5769 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
5770 #define CBR_PND_DEADLINE_DISABLE (1<<31)
5771 #define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
5773 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
5774 #define CBR_DPLLBMD_PIPE(pipe) (1<<(7+(pipe)*11)) /* pipes B and C */
5776 /* FIFO watermark sizes etc */
5777 #define G4X_FIFO_LINE_SIZE 64
5778 #define I915_FIFO_LINE_SIZE 64
5779 #define I830_FIFO_LINE_SIZE 32
5781 #define VALLEYVIEW_FIFO_SIZE 255
5782 #define G4X_FIFO_SIZE 127
5783 #define I965_FIFO_SIZE 512
5784 #define I945_FIFO_SIZE 127
5785 #define I915_FIFO_SIZE 95
5786 #define I855GM_FIFO_SIZE 127 /* In cachelines */
5787 #define I830_FIFO_SIZE 95
5789 #define VALLEYVIEW_MAX_WM 0xff
5790 #define G4X_MAX_WM 0x3f
5791 #define I915_MAX_WM 0x3f
5793 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
5794 #define PINEVIEW_FIFO_LINE_SIZE 64
5795 #define PINEVIEW_MAX_WM 0x1ff
5796 #define PINEVIEW_DFT_WM 0x3f
5797 #define PINEVIEW_DFT_HPLLOFF_WM 0
5798 #define PINEVIEW_GUARD_WM 10
5799 #define PINEVIEW_CURSOR_FIFO 64
5800 #define PINEVIEW_CURSOR_MAX_WM 0x3f
5801 #define PINEVIEW_CURSOR_DFT_WM 0
5802 #define PINEVIEW_CURSOR_GUARD_WM 5
5804 #define VALLEYVIEW_CURSOR_MAX_WM 64
5805 #define I965_CURSOR_FIFO 64
5806 #define I965_CURSOR_MAX_WM 32
5807 #define I965_CURSOR_DFT_WM 8
5809 /* Watermark register definitions for SKL */
5810 #define _CUR_WM_A_0 0x70140
5811 #define _CUR_WM_B_0 0x71140
5812 #define _PLANE_WM_1_A_0 0x70240
5813 #define _PLANE_WM_1_B_0 0x71240
5814 #define _PLANE_WM_2_A_0 0x70340
5815 #define _PLANE_WM_2_B_0 0x71340
5816 #define _PLANE_WM_TRANS_1_A_0 0x70268
5817 #define _PLANE_WM_TRANS_1_B_0 0x71268
5818 #define _PLANE_WM_TRANS_2_A_0 0x70368
5819 #define _PLANE_WM_TRANS_2_B_0 0x71368
5820 #define _CUR_WM_TRANS_A_0 0x70168
5821 #define _CUR_WM_TRANS_B_0 0x71168
5822 #define PLANE_WM_EN (1 << 31)
5823 #define PLANE_WM_LINES_SHIFT 14
5824 #define PLANE_WM_LINES_MASK 0x1f
5825 #define PLANE_WM_BLOCKS_MASK 0x3ff
5827 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
5828 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
5829 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
5831 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
5832 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
5833 #define _PLANE_WM_BASE(pipe, plane) \
5834 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
5835 #define PLANE_WM(pipe, plane, level) \
5836 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
5837 #define _PLANE_WM_TRANS_1(pipe) \
5838 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
5839 #define _PLANE_WM_TRANS_2(pipe) \
5840 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
5841 #define PLANE_WM_TRANS(pipe, plane) \
5842 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
5844 /* define the Watermark register on Ironlake */
5845 #define WM0_PIPEA_ILK _MMIO(0x45100)
5846 #define WM0_PIPE_PLANE_MASK (0xffff<<16)
5847 #define WM0_PIPE_PLANE_SHIFT 16
5848 #define WM0_PIPE_SPRITE_MASK (0xff<<8)
5849 #define WM0_PIPE_SPRITE_SHIFT 8
5850 #define WM0_PIPE_CURSOR_MASK (0xff)
5852 #define WM0_PIPEB_ILK _MMIO(0x45104)
5853 #define WM0_PIPEC_IVB _MMIO(0x45200)
5854 #define WM1_LP_ILK _MMIO(0x45108)
5855 #define WM1_LP_SR_EN (1<<31)
5856 #define WM1_LP_LATENCY_SHIFT 24
5857 #define WM1_LP_LATENCY_MASK (0x7f<<24)
5858 #define WM1_LP_FBC_MASK (0xf<<20)
5859 #define WM1_LP_FBC_SHIFT 20
5860 #define WM1_LP_FBC_SHIFT_BDW 19
5861 #define WM1_LP_SR_MASK (0x7ff<<8)
5862 #define WM1_LP_SR_SHIFT 8
5863 #define WM1_LP_CURSOR_MASK (0xff)
5864 #define WM2_LP_ILK _MMIO(0x4510c)
5865 #define WM2_LP_EN (1<<31)
5866 #define WM3_LP_ILK _MMIO(0x45110)
5867 #define WM3_LP_EN (1<<31)
5868 #define WM1S_LP_ILK _MMIO(0x45120)
5869 #define WM2S_LP_IVB _MMIO(0x45124)
5870 #define WM3S_LP_IVB _MMIO(0x45128)
5871 #define WM1S_LP_EN (1<<31)
5873 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
5874 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
5875 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
5877 /* Memory latency timer register */
5878 #define MLTR_ILK _MMIO(0x11222)
5879 #define MLTR_WM1_SHIFT 0
5880 #define MLTR_WM2_SHIFT 8
5881 /* the unit of memory self-refresh latency time is 0.5us */
5882 #define ILK_SRLT_MASK 0x3f
5885 /* the address where we get all kinds of latency value */
5886 #define SSKPD _MMIO(0x5d10)
5887 #define SSKPD_WM_MASK 0x3f
5888 #define SSKPD_WM0_SHIFT 0
5889 #define SSKPD_WM1_SHIFT 8
5890 #define SSKPD_WM2_SHIFT 16
5891 #define SSKPD_WM3_SHIFT 24
5894 * The two pipe frame counter registers are not synchronized, so
5895 * reading a stable value is somewhat tricky. The following code
5899 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
5900 * PIPE_FRAME_HIGH_SHIFT;
5901 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
5902 * PIPE_FRAME_LOW_SHIFT);
5903 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
5904 * PIPE_FRAME_HIGH_SHIFT);
5905 * } while (high1 != high2);
5906 * frame = (high1 << 8) | low1;
5908 #define _PIPEAFRAMEHIGH 0x70040
5909 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
5910 #define PIPE_FRAME_HIGH_SHIFT 0
5911 #define _PIPEAFRAMEPIXEL 0x70044
5912 #define PIPE_FRAME_LOW_MASK 0xff000000
5913 #define PIPE_FRAME_LOW_SHIFT 24
5914 #define PIPE_PIXEL_MASK 0x00ffffff
5915 #define PIPE_PIXEL_SHIFT 0
5916 /* GM45+ just has to be different */
5917 #define _PIPEA_FRMCOUNT_G4X 0x70040
5918 #define _PIPEA_FLIPCOUNT_G4X 0x70044
5919 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
5920 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
5922 /* Cursor A & B regs */
5923 #define _CURACNTR 0x70080
5924 /* Old style CUR*CNTR flags (desktop 8xx) */
5925 #define CURSOR_ENABLE 0x80000000
5926 #define CURSOR_GAMMA_ENABLE 0x40000000
5927 #define CURSOR_STRIDE_SHIFT 28
5928 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
5929 #define CURSOR_PIPE_CSC_ENABLE (1<<24)
5930 #define CURSOR_FORMAT_SHIFT 24
5931 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
5932 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
5933 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
5934 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
5935 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
5936 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
5937 /* New style CUR*CNTR flags */
5938 #define CURSOR_MODE 0x27
5939 #define CURSOR_MODE_DISABLE 0x00
5940 #define CURSOR_MODE_128_32B_AX 0x02
5941 #define CURSOR_MODE_256_32B_AX 0x03
5942 #define CURSOR_MODE_64_32B_AX 0x07
5943 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
5944 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
5945 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
5946 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
5947 #define MCURSOR_GAMMA_ENABLE (1 << 26)
5948 #define CURSOR_ROTATE_180 (1<<15)
5949 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
5950 #define _CURABASE 0x70084
5951 #define _CURAPOS 0x70088
5952 #define CURSOR_POS_MASK 0x007FF
5953 #define CURSOR_POS_SIGN 0x8000
5954 #define CURSOR_X_SHIFT 0
5955 #define CURSOR_Y_SHIFT 16
5956 #define CURSIZE _MMIO(0x700a0) /* 845/865 */
5957 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
5958 #define CUR_FBC_CTL_EN (1 << 31)
5959 #define _CURBCNTR 0x700c0
5960 #define _CURBBASE 0x700c4
5961 #define _CURBPOS 0x700c8
5963 #define _CURBCNTR_IVB 0x71080
5964 #define _CURBBASE_IVB 0x71084
5965 #define _CURBPOS_IVB 0x71088
5967 #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
5968 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
5969 dev_priv->info.display_mmio_offset)
5971 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
5972 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
5973 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
5974 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
5976 #define CURSOR_A_OFFSET 0x70080
5977 #define CURSOR_B_OFFSET 0x700c0
5978 #define CHV_CURSOR_C_OFFSET 0x700e0
5979 #define IVB_CURSOR_B_OFFSET 0x71080
5980 #define IVB_CURSOR_C_OFFSET 0x72080
5982 /* Display A control */
5983 #define _DSPACNTR 0x70180
5984 #define DISPLAY_PLANE_ENABLE (1<<31)
5985 #define DISPLAY_PLANE_DISABLE 0
5986 #define DISPPLANE_GAMMA_ENABLE (1<<30)
5987 #define DISPPLANE_GAMMA_DISABLE 0
5988 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
5989 #define DISPPLANE_YUV422 (0x0<<26)
5990 #define DISPPLANE_8BPP (0x2<<26)
5991 #define DISPPLANE_BGRA555 (0x3<<26)
5992 #define DISPPLANE_BGRX555 (0x4<<26)
5993 #define DISPPLANE_BGRX565 (0x5<<26)
5994 #define DISPPLANE_BGRX888 (0x6<<26)
5995 #define DISPPLANE_BGRA888 (0x7<<26)
5996 #define DISPPLANE_RGBX101010 (0x8<<26)
5997 #define DISPPLANE_RGBA101010 (0x9<<26)
5998 #define DISPPLANE_BGRX101010 (0xa<<26)
5999 #define DISPPLANE_RGBX161616 (0xc<<26)
6000 #define DISPPLANE_RGBX888 (0xe<<26)
6001 #define DISPPLANE_RGBA888 (0xf<<26)
6002 #define DISPPLANE_STEREO_ENABLE (1<<25)
6003 #define DISPPLANE_STEREO_DISABLE 0
6004 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
6005 #define DISPPLANE_SEL_PIPE_SHIFT 24
6006 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
6007 #define DISPPLANE_SEL_PIPE(pipe) ((pipe)<<DISPPLANE_SEL_PIPE_SHIFT)
6008 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
6009 #define DISPPLANE_SRC_KEY_DISABLE 0
6010 #define DISPPLANE_LINE_DOUBLE (1<<20)
6011 #define DISPPLANE_NO_LINE_DOUBLE 0
6012 #define DISPPLANE_STEREO_POLARITY_FIRST 0
6013 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
6014 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
6015 #define DISPPLANE_ROTATE_180 (1<<15)
6016 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
6017 #define DISPPLANE_TILED (1<<10)
6018 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
6019 #define _DSPAADDR 0x70184
6020 #define _DSPASTRIDE 0x70188
6021 #define _DSPAPOS 0x7018C /* reserved */
6022 #define _DSPASIZE 0x70190
6023 #define _DSPASURF 0x7019C /* 965+ only */
6024 #define _DSPATILEOFF 0x701A4 /* 965+ only */
6025 #define _DSPAOFFSET 0x701A4 /* HSW */
6026 #define _DSPASURFLIVE 0x701AC
6028 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6029 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6030 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6031 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6032 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6033 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6034 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6035 #define DSPLINOFF(plane) DSPADDR(plane)
6036 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6037 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
6039 /* CHV pipe B blender and primary plane */
6040 #define _CHV_BLEND_A 0x60a00
6041 #define CHV_BLEND_LEGACY (0<<30)
6042 #define CHV_BLEND_ANDROID (1<<30)
6043 #define CHV_BLEND_MPO (2<<30)
6044 #define CHV_BLEND_MASK (3<<30)
6045 #define _CHV_CANVAS_A 0x60a04
6046 #define _PRIMPOS_A 0x60a08
6047 #define _PRIMSIZE_A 0x60a0c
6048 #define _PRIMCNSTALPHA_A 0x60a10
6049 #define PRIM_CONST_ALPHA_ENABLE (1<<31)
6051 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6052 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6053 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6054 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6055 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6057 /* Display/Sprite base address macros */
6058 #define DISP_BASEADDR_MASK (0xfffff000)
6059 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
6060 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
6073 #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
6074 #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
6075 #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
6076 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6079 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
6080 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
6081 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
6082 #define _PIPEBFRAMEHIGH 0x71040
6083 #define _PIPEBFRAMEPIXEL 0x71044
6084 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
6085 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
6088 /* Display B control */
6089 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
6090 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
6091 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
6092 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6093 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6094 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
6095 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
6096 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
6097 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
6098 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
6099 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
6100 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
6101 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
6103 /* Sprite A control */
6104 #define _DVSACNTR 0x72180
6105 #define DVS_ENABLE (1<<31)
6106 #define DVS_GAMMA_ENABLE (1<<30)
6107 #define DVS_PIXFORMAT_MASK (3<<25)
6108 #define DVS_FORMAT_YUV422 (0<<25)
6109 #define DVS_FORMAT_RGBX101010 (1<<25)
6110 #define DVS_FORMAT_RGBX888 (2<<25)
6111 #define DVS_FORMAT_RGBX161616 (3<<25)
6112 #define DVS_PIPE_CSC_ENABLE (1<<24)
6113 #define DVS_SOURCE_KEY (1<<22)
6114 #define DVS_RGB_ORDER_XBGR (1<<20)
6115 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
6116 #define DVS_YUV_ORDER_YUYV (0<<16)
6117 #define DVS_YUV_ORDER_UYVY (1<<16)
6118 #define DVS_YUV_ORDER_YVYU (2<<16)
6119 #define DVS_YUV_ORDER_VYUY (3<<16)
6120 #define DVS_ROTATE_180 (1<<15)
6121 #define DVS_DEST_KEY (1<<2)
6122 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
6123 #define DVS_TILED (1<<10)
6124 #define _DVSALINOFF 0x72184
6125 #define _DVSASTRIDE 0x72188
6126 #define _DVSAPOS 0x7218c
6127 #define _DVSASIZE 0x72190
6128 #define _DVSAKEYVAL 0x72194
6129 #define _DVSAKEYMSK 0x72198
6130 #define _DVSASURF 0x7219c
6131 #define _DVSAKEYMAXVAL 0x721a0
6132 #define _DVSATILEOFF 0x721a4
6133 #define _DVSASURFLIVE 0x721ac
6134 #define _DVSASCALE 0x72204
6135 #define DVS_SCALE_ENABLE (1<<31)
6136 #define DVS_FILTER_MASK (3<<29)
6137 #define DVS_FILTER_MEDIUM (0<<29)
6138 #define DVS_FILTER_ENHANCING (1<<29)
6139 #define DVS_FILTER_SOFTENING (2<<29)
6140 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
6141 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
6142 #define _DVSAGAMC 0x72300
6144 #define _DVSBCNTR 0x73180
6145 #define _DVSBLINOFF 0x73184
6146 #define _DVSBSTRIDE 0x73188
6147 #define _DVSBPOS 0x7318c
6148 #define _DVSBSIZE 0x73190
6149 #define _DVSBKEYVAL 0x73194
6150 #define _DVSBKEYMSK 0x73198
6151 #define _DVSBSURF 0x7319c
6152 #define _DVSBKEYMAXVAL 0x731a0
6153 #define _DVSBTILEOFF 0x731a4
6154 #define _DVSBSURFLIVE 0x731ac
6155 #define _DVSBSCALE 0x73204
6156 #define _DVSBGAMC 0x73300
6158 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6159 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6160 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6161 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6162 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6163 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6164 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6165 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6166 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6167 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6168 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6169 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6171 #define _SPRA_CTL 0x70280
6172 #define SPRITE_ENABLE (1<<31)
6173 #define SPRITE_GAMMA_ENABLE (1<<30)
6174 #define SPRITE_PIXFORMAT_MASK (7<<25)
6175 #define SPRITE_FORMAT_YUV422 (0<<25)
6176 #define SPRITE_FORMAT_RGBX101010 (1<<25)
6177 #define SPRITE_FORMAT_RGBX888 (2<<25)
6178 #define SPRITE_FORMAT_RGBX161616 (3<<25)
6179 #define SPRITE_FORMAT_YUV444 (4<<25)
6180 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
6181 #define SPRITE_PIPE_CSC_ENABLE (1<<24)
6182 #define SPRITE_SOURCE_KEY (1<<22)
6183 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
6184 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
6185 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
6186 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
6187 #define SPRITE_YUV_ORDER_YUYV (0<<16)
6188 #define SPRITE_YUV_ORDER_UYVY (1<<16)
6189 #define SPRITE_YUV_ORDER_YVYU (2<<16)
6190 #define SPRITE_YUV_ORDER_VYUY (3<<16)
6191 #define SPRITE_ROTATE_180 (1<<15)
6192 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
6193 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
6194 #define SPRITE_TILED (1<<10)
6195 #define SPRITE_DEST_KEY (1<<2)
6196 #define _SPRA_LINOFF 0x70284
6197 #define _SPRA_STRIDE 0x70288
6198 #define _SPRA_POS 0x7028c
6199 #define _SPRA_SIZE 0x70290
6200 #define _SPRA_KEYVAL 0x70294
6201 #define _SPRA_KEYMSK 0x70298
6202 #define _SPRA_SURF 0x7029c
6203 #define _SPRA_KEYMAX 0x702a0
6204 #define _SPRA_TILEOFF 0x702a4
6205 #define _SPRA_OFFSET 0x702a4
6206 #define _SPRA_SURFLIVE 0x702ac
6207 #define _SPRA_SCALE 0x70304
6208 #define SPRITE_SCALE_ENABLE (1<<31)
6209 #define SPRITE_FILTER_MASK (3<<29)
6210 #define SPRITE_FILTER_MEDIUM (0<<29)
6211 #define SPRITE_FILTER_ENHANCING (1<<29)
6212 #define SPRITE_FILTER_SOFTENING (2<<29)
6213 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
6214 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
6215 #define _SPRA_GAMC 0x70400
6217 #define _SPRB_CTL 0x71280
6218 #define _SPRB_LINOFF 0x71284
6219 #define _SPRB_STRIDE 0x71288
6220 #define _SPRB_POS 0x7128c
6221 #define _SPRB_SIZE 0x71290
6222 #define _SPRB_KEYVAL 0x71294
6223 #define _SPRB_KEYMSK 0x71298
6224 #define _SPRB_SURF 0x7129c
6225 #define _SPRB_KEYMAX 0x712a0
6226 #define _SPRB_TILEOFF 0x712a4
6227 #define _SPRB_OFFSET 0x712a4
6228 #define _SPRB_SURFLIVE 0x712ac
6229 #define _SPRB_SCALE 0x71304
6230 #define _SPRB_GAMC 0x71400
6232 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6233 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6234 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6235 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6236 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6237 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6238 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6239 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6240 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6241 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6242 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6243 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6244 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
6245 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6247 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6248 #define SP_ENABLE (1<<31)
6249 #define SP_GAMMA_ENABLE (1<<30)
6250 #define SP_PIXFORMAT_MASK (0xf<<26)
6251 #define SP_FORMAT_YUV422 (0<<26)
6252 #define SP_FORMAT_BGR565 (5<<26)
6253 #define SP_FORMAT_BGRX8888 (6<<26)
6254 #define SP_FORMAT_BGRA8888 (7<<26)
6255 #define SP_FORMAT_RGBX1010102 (8<<26)
6256 #define SP_FORMAT_RGBA1010102 (9<<26)
6257 #define SP_FORMAT_RGBX8888 (0xe<<26)
6258 #define SP_FORMAT_RGBA8888 (0xf<<26)
6259 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
6260 #define SP_SOURCE_KEY (1<<22)
6261 #define SP_YUV_BYTE_ORDER_MASK (3<<16)
6262 #define SP_YUV_ORDER_YUYV (0<<16)
6263 #define SP_YUV_ORDER_UYVY (1<<16)
6264 #define SP_YUV_ORDER_YVYU (2<<16)
6265 #define SP_YUV_ORDER_VYUY (3<<16)
6266 #define SP_ROTATE_180 (1<<15)
6267 #define SP_TILED (1<<10)
6268 #define SP_MIRROR (1<<8) /* CHV pipe B */
6269 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6270 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6271 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6272 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6273 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6274 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6275 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6276 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6277 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6278 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6279 #define SP_CONST_ALPHA_ENABLE (1<<31)
6280 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
6282 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6283 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6284 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6285 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6286 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6287 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6288 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6289 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6290 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6291 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6292 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6293 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
6295 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6296 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6298 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6299 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6300 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6301 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6302 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6303 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6304 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6305 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6306 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6307 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6308 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6309 #define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
6312 * CHV pipe B sprite CSC
6314 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
6315 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6316 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
6318 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6319 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6321 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6322 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6323 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6324 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
6325 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
6327 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6328 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6329 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6330 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6331 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6332 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
6333 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
6335 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6336 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6337 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6338 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
6339 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
6341 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6342 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6343 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6344 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
6345 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
6347 /* Skylake plane registers */
6349 #define _PLANE_CTL_1_A 0x70180
6350 #define _PLANE_CTL_2_A 0x70280
6351 #define _PLANE_CTL_3_A 0x70380
6352 #define PLANE_CTL_ENABLE (1 << 31)
6353 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
6355 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6356 * expanded to include bit 23 as well. However, the shift-24 based values
6357 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6359 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
6360 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
6361 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
6362 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
6363 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
6364 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
6365 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
6366 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
6367 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
6368 #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
6369 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
6370 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
6371 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
6372 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
6373 #define PLANE_CTL_ORDER_BGRX (0 << 20)
6374 #define PLANE_CTL_ORDER_RGBX (1 << 20)
6375 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6376 #define PLANE_CTL_YUV422_YUYV ( 0 << 16)
6377 #define PLANE_CTL_YUV422_UYVY ( 1 << 16)
6378 #define PLANE_CTL_YUV422_YVYU ( 2 << 16)
6379 #define PLANE_CTL_YUV422_VYUY ( 3 << 16)
6380 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
6381 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
6382 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
6383 #define PLANE_CTL_TILED_MASK (0x7 << 10)
6384 #define PLANE_CTL_TILED_LINEAR ( 0 << 10)
6385 #define PLANE_CTL_TILED_X ( 1 << 10)
6386 #define PLANE_CTL_TILED_Y ( 4 << 10)
6387 #define PLANE_CTL_TILED_YF ( 5 << 10)
6388 #define PLANE_CTL_FLIP_HORIZONTAL ( 1 << 8)
6389 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
6390 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
6391 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
6392 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
6393 #define PLANE_CTL_ROTATE_MASK 0x3
6394 #define PLANE_CTL_ROTATE_0 0x0
6395 #define PLANE_CTL_ROTATE_90 0x1
6396 #define PLANE_CTL_ROTATE_180 0x2
6397 #define PLANE_CTL_ROTATE_270 0x3
6398 #define _PLANE_STRIDE_1_A 0x70188
6399 #define _PLANE_STRIDE_2_A 0x70288
6400 #define _PLANE_STRIDE_3_A 0x70388
6401 #define _PLANE_POS_1_A 0x7018c
6402 #define _PLANE_POS_2_A 0x7028c
6403 #define _PLANE_POS_3_A 0x7038c
6404 #define _PLANE_SIZE_1_A 0x70190
6405 #define _PLANE_SIZE_2_A 0x70290
6406 #define _PLANE_SIZE_3_A 0x70390
6407 #define _PLANE_SURF_1_A 0x7019c
6408 #define _PLANE_SURF_2_A 0x7029c
6409 #define _PLANE_SURF_3_A 0x7039c
6410 #define _PLANE_OFFSET_1_A 0x701a4
6411 #define _PLANE_OFFSET_2_A 0x702a4
6412 #define _PLANE_OFFSET_3_A 0x703a4
6413 #define _PLANE_KEYVAL_1_A 0x70194
6414 #define _PLANE_KEYVAL_2_A 0x70294
6415 #define _PLANE_KEYMSK_1_A 0x70198
6416 #define _PLANE_KEYMSK_2_A 0x70298
6417 #define _PLANE_KEYMAX_1_A 0x701a0
6418 #define _PLANE_KEYMAX_2_A 0x702a0
6419 #define _PLANE_AUX_DIST_1_A 0x701c0
6420 #define _PLANE_AUX_DIST_2_A 0x702c0
6421 #define _PLANE_AUX_OFFSET_1_A 0x701c4
6422 #define _PLANE_AUX_OFFSET_2_A 0x702c4
6423 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
6424 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
6425 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
6426 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
6427 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
6428 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
6429 #define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
6430 #define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
6431 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
6432 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
6433 #define _PLANE_BUF_CFG_1_A 0x7027c
6434 #define _PLANE_BUF_CFG_2_A 0x7037c
6435 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
6436 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
6439 #define _PLANE_CTL_1_B 0x71180
6440 #define _PLANE_CTL_2_B 0x71280
6441 #define _PLANE_CTL_3_B 0x71380
6442 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6443 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6444 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6445 #define PLANE_CTL(pipe, plane) \
6446 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6448 #define _PLANE_STRIDE_1_B 0x71188
6449 #define _PLANE_STRIDE_2_B 0x71288
6450 #define _PLANE_STRIDE_3_B 0x71388
6451 #define _PLANE_STRIDE_1(pipe) \
6452 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6453 #define _PLANE_STRIDE_2(pipe) \
6454 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6455 #define _PLANE_STRIDE_3(pipe) \
6456 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6457 #define PLANE_STRIDE(pipe, plane) \
6458 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6460 #define _PLANE_POS_1_B 0x7118c
6461 #define _PLANE_POS_2_B 0x7128c
6462 #define _PLANE_POS_3_B 0x7138c
6463 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6464 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6465 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6466 #define PLANE_POS(pipe, plane) \
6467 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6469 #define _PLANE_SIZE_1_B 0x71190
6470 #define _PLANE_SIZE_2_B 0x71290
6471 #define _PLANE_SIZE_3_B 0x71390
6472 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6473 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6474 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6475 #define PLANE_SIZE(pipe, plane) \
6476 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6478 #define _PLANE_SURF_1_B 0x7119c
6479 #define _PLANE_SURF_2_B 0x7129c
6480 #define _PLANE_SURF_3_B 0x7139c
6481 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6482 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6483 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6484 #define PLANE_SURF(pipe, plane) \
6485 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6487 #define _PLANE_OFFSET_1_B 0x711a4
6488 #define _PLANE_OFFSET_2_B 0x712a4
6489 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6490 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6491 #define PLANE_OFFSET(pipe, plane) \
6492 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6494 #define _PLANE_KEYVAL_1_B 0x71194
6495 #define _PLANE_KEYVAL_2_B 0x71294
6496 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6497 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6498 #define PLANE_KEYVAL(pipe, plane) \
6499 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6501 #define _PLANE_KEYMSK_1_B 0x71198
6502 #define _PLANE_KEYMSK_2_B 0x71298
6503 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6504 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6505 #define PLANE_KEYMSK(pipe, plane) \
6506 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6508 #define _PLANE_KEYMAX_1_B 0x711a0
6509 #define _PLANE_KEYMAX_2_B 0x712a0
6510 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6511 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6512 #define PLANE_KEYMAX(pipe, plane) \
6513 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6515 #define _PLANE_BUF_CFG_1_B 0x7127c
6516 #define _PLANE_BUF_CFG_2_B 0x7137c
6517 #define _PLANE_BUF_CFG_1(pipe) \
6518 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6519 #define _PLANE_BUF_CFG_2(pipe) \
6520 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6521 #define PLANE_BUF_CFG(pipe, plane) \
6522 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
6524 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
6525 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
6526 #define _PLANE_NV12_BUF_CFG_1(pipe) \
6527 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6528 #define _PLANE_NV12_BUF_CFG_2(pipe) \
6529 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6530 #define PLANE_NV12_BUF_CFG(pipe, plane) \
6531 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6533 #define _PLANE_AUX_DIST_1_B 0x711c0
6534 #define _PLANE_AUX_DIST_2_B 0x712c0
6535 #define _PLANE_AUX_DIST_1(pipe) \
6536 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6537 #define _PLANE_AUX_DIST_2(pipe) \
6538 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6539 #define PLANE_AUX_DIST(pipe, plane) \
6540 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6542 #define _PLANE_AUX_OFFSET_1_B 0x711c4
6543 #define _PLANE_AUX_OFFSET_2_B 0x712c4
6544 #define _PLANE_AUX_OFFSET_1(pipe) \
6545 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6546 #define _PLANE_AUX_OFFSET_2(pipe) \
6547 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6548 #define PLANE_AUX_OFFSET(pipe, plane) \
6549 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6551 #define _PLANE_COLOR_CTL_1_B 0x711CC
6552 #define _PLANE_COLOR_CTL_2_B 0x712CC
6553 #define _PLANE_COLOR_CTL_3_B 0x713CC
6554 #define _PLANE_COLOR_CTL_1(pipe) \
6555 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6556 #define _PLANE_COLOR_CTL_2(pipe) \
6557 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6558 #define PLANE_COLOR_CTL(pipe, plane) \
6559 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6561 #/* SKL new cursor registers */
6562 #define _CUR_BUF_CFG_A 0x7017c
6563 #define _CUR_BUF_CFG_B 0x7117c
6564 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
6567 #define VGACNTRL _MMIO(0x71400)
6568 # define VGA_DISP_DISABLE (1 << 31)
6569 # define VGA_2X_MODE (1 << 30)
6570 # define VGA_PIPE_B_SELECT (1 << 29)
6572 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
6576 #define CPU_VGACNTRL _MMIO(0x41000)
6578 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
6579 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
6580 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
6581 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
6582 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
6583 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
6584 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
6585 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
6586 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
6587 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
6588 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
6590 /* refresh rate hardware control */
6591 #define RR_HW_CTL _MMIO(0x45300)
6592 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
6593 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
6595 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
6596 #define FDI_PLL_FB_CLOCK_MASK 0xff
6597 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
6598 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
6599 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
6600 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
6601 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
6603 #define PCH_3DCGDIS0 _MMIO(0x46020)
6604 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
6605 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
6607 #define PCH_3DCGDIS1 _MMIO(0x46024)
6608 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
6610 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
6611 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
6612 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
6613 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
6616 #define _PIPEA_DATA_M1 0x60030
6617 #define PIPE_DATA_M1_OFFSET 0
6618 #define _PIPEA_DATA_N1 0x60034
6619 #define PIPE_DATA_N1_OFFSET 0
6621 #define _PIPEA_DATA_M2 0x60038
6622 #define PIPE_DATA_M2_OFFSET 0
6623 #define _PIPEA_DATA_N2 0x6003c
6624 #define PIPE_DATA_N2_OFFSET 0
6626 #define _PIPEA_LINK_M1 0x60040
6627 #define PIPE_LINK_M1_OFFSET 0
6628 #define _PIPEA_LINK_N1 0x60044
6629 #define PIPE_LINK_N1_OFFSET 0
6631 #define _PIPEA_LINK_M2 0x60048
6632 #define PIPE_LINK_M2_OFFSET 0
6633 #define _PIPEA_LINK_N2 0x6004c
6634 #define PIPE_LINK_N2_OFFSET 0
6636 /* PIPEB timing regs are same start from 0x61000 */
6638 #define _PIPEB_DATA_M1 0x61030
6639 #define _PIPEB_DATA_N1 0x61034
6640 #define _PIPEB_DATA_M2 0x61038
6641 #define _PIPEB_DATA_N2 0x6103c
6642 #define _PIPEB_LINK_M1 0x61040
6643 #define _PIPEB_LINK_N1 0x61044
6644 #define _PIPEB_LINK_M2 0x61048
6645 #define _PIPEB_LINK_N2 0x6104c
6647 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
6648 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
6649 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
6650 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
6651 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
6652 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
6653 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
6654 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
6656 /* CPU panel fitter */
6657 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
6658 #define _PFA_CTL_1 0x68080
6659 #define _PFB_CTL_1 0x68880
6660 #define PF_ENABLE (1<<31)
6661 #define PF_PIPE_SEL_MASK_IVB (3<<29)
6662 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
6663 #define PF_FILTER_MASK (3<<23)
6664 #define PF_FILTER_PROGRAMMED (0<<23)
6665 #define PF_FILTER_MED_3x3 (1<<23)
6666 #define PF_FILTER_EDGE_ENHANCE (2<<23)
6667 #define PF_FILTER_EDGE_SOFTEN (3<<23)
6668 #define _PFA_WIN_SZ 0x68074
6669 #define _PFB_WIN_SZ 0x68874
6670 #define _PFA_WIN_POS 0x68070
6671 #define _PFB_WIN_POS 0x68870
6672 #define _PFA_VSCALE 0x68084
6673 #define _PFB_VSCALE 0x68884
6674 #define _PFA_HSCALE 0x68090
6675 #define _PFB_HSCALE 0x68890
6677 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
6678 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
6679 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
6680 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
6681 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
6683 #define _PSA_CTL 0x68180
6684 #define _PSB_CTL 0x68980
6685 #define PS_ENABLE (1<<31)
6686 #define _PSA_WIN_SZ 0x68174
6687 #define _PSB_WIN_SZ 0x68974
6688 #define _PSA_WIN_POS 0x68170
6689 #define _PSB_WIN_POS 0x68970
6691 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
6692 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
6693 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
6698 #define _PS_1A_CTRL 0x68180
6699 #define _PS_2A_CTRL 0x68280
6700 #define _PS_1B_CTRL 0x68980
6701 #define _PS_2B_CTRL 0x68A80
6702 #define _PS_1C_CTRL 0x69180
6703 #define PS_SCALER_EN (1 << 31)
6704 #define PS_SCALER_MODE_MASK (3 << 28)
6705 #define PS_SCALER_MODE_DYN (0 << 28)
6706 #define PS_SCALER_MODE_HQ (1 << 28)
6707 #define PS_PLANE_SEL_MASK (7 << 25)
6708 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
6709 #define PS_FILTER_MASK (3 << 23)
6710 #define PS_FILTER_MEDIUM (0 << 23)
6711 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
6712 #define PS_FILTER_BILINEAR (3 << 23)
6713 #define PS_VERT3TAP (1 << 21)
6714 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
6715 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
6716 #define PS_PWRUP_PROGRESS (1 << 17)
6717 #define PS_V_FILTER_BYPASS (1 << 8)
6718 #define PS_VADAPT_EN (1 << 7)
6719 #define PS_VADAPT_MODE_MASK (3 << 5)
6720 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
6721 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
6722 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
6724 #define _PS_PWR_GATE_1A 0x68160
6725 #define _PS_PWR_GATE_2A 0x68260
6726 #define _PS_PWR_GATE_1B 0x68960
6727 #define _PS_PWR_GATE_2B 0x68A60
6728 #define _PS_PWR_GATE_1C 0x69160
6729 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
6730 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
6731 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
6732 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
6733 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
6734 #define PS_PWR_GATE_SLPEN_8 0
6735 #define PS_PWR_GATE_SLPEN_16 1
6736 #define PS_PWR_GATE_SLPEN_24 2
6737 #define PS_PWR_GATE_SLPEN_32 3
6739 #define _PS_WIN_POS_1A 0x68170
6740 #define _PS_WIN_POS_2A 0x68270
6741 #define _PS_WIN_POS_1B 0x68970
6742 #define _PS_WIN_POS_2B 0x68A70
6743 #define _PS_WIN_POS_1C 0x69170
6745 #define _PS_WIN_SZ_1A 0x68174
6746 #define _PS_WIN_SZ_2A 0x68274
6747 #define _PS_WIN_SZ_1B 0x68974
6748 #define _PS_WIN_SZ_2B 0x68A74
6749 #define _PS_WIN_SZ_1C 0x69174
6751 #define _PS_VSCALE_1A 0x68184
6752 #define _PS_VSCALE_2A 0x68284
6753 #define _PS_VSCALE_1B 0x68984
6754 #define _PS_VSCALE_2B 0x68A84
6755 #define _PS_VSCALE_1C 0x69184
6757 #define _PS_HSCALE_1A 0x68190
6758 #define _PS_HSCALE_2A 0x68290
6759 #define _PS_HSCALE_1B 0x68990
6760 #define _PS_HSCALE_2B 0x68A90
6761 #define _PS_HSCALE_1C 0x69190
6763 #define _PS_VPHASE_1A 0x68188
6764 #define _PS_VPHASE_2A 0x68288
6765 #define _PS_VPHASE_1B 0x68988
6766 #define _PS_VPHASE_2B 0x68A88
6767 #define _PS_VPHASE_1C 0x69188
6769 #define _PS_HPHASE_1A 0x68194
6770 #define _PS_HPHASE_2A 0x68294
6771 #define _PS_HPHASE_1B 0x68994
6772 #define _PS_HPHASE_2B 0x68A94
6773 #define _PS_HPHASE_1C 0x69194
6775 #define _PS_ECC_STAT_1A 0x681D0
6776 #define _PS_ECC_STAT_2A 0x682D0
6777 #define _PS_ECC_STAT_1B 0x689D0
6778 #define _PS_ECC_STAT_2B 0x68AD0
6779 #define _PS_ECC_STAT_1C 0x691D0
6781 #define _ID(id, a, b) ((a) + (id)*((b)-(a)))
6782 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
6783 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
6784 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
6785 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
6786 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
6787 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
6788 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
6789 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
6790 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
6791 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
6792 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
6793 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
6794 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
6795 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
6796 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
6797 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
6798 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
6799 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
6800 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
6801 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
6802 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
6803 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
6804 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
6805 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
6806 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
6807 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
6808 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
6810 /* legacy palette */
6811 #define _LGC_PALETTE_A 0x4a000
6812 #define _LGC_PALETTE_B 0x4a800
6813 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
6815 #define _GAMMA_MODE_A 0x4a480
6816 #define _GAMMA_MODE_B 0x4ac80
6817 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
6818 #define GAMMA_MODE_MODE_MASK (3 << 0)
6819 #define GAMMA_MODE_MODE_8BIT (0 << 0)
6820 #define GAMMA_MODE_MODE_10BIT (1 << 0)
6821 #define GAMMA_MODE_MODE_12BIT (2 << 0)
6822 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
6825 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
6826 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
6827 #define CSR_HTP_ADDR_SKL 0x00500034
6828 #define CSR_SSP_BASE _MMIO(0x8F074)
6829 #define CSR_HTP_SKL _MMIO(0x8F004)
6830 #define CSR_LAST_WRITE _MMIO(0x8F034)
6831 #define CSR_LAST_WRITE_VALUE 0xc003b400
6832 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
6833 #define CSR_MMIO_START_RANGE 0x80000
6834 #define CSR_MMIO_END_RANGE 0x8FFFF
6835 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
6836 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
6837 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
6840 #define DE_MASTER_IRQ_CONTROL (1 << 31)
6841 #define DE_SPRITEB_FLIP_DONE (1 << 29)
6842 #define DE_SPRITEA_FLIP_DONE (1 << 28)
6843 #define DE_PLANEB_FLIP_DONE (1 << 27)
6844 #define DE_PLANEA_FLIP_DONE (1 << 26)
6845 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
6846 #define DE_PCU_EVENT (1 << 25)
6847 #define DE_GTT_FAULT (1 << 24)
6848 #define DE_POISON (1 << 23)
6849 #define DE_PERFORM_COUNTER (1 << 22)
6850 #define DE_PCH_EVENT (1 << 21)
6851 #define DE_AUX_CHANNEL_A (1 << 20)
6852 #define DE_DP_A_HOTPLUG (1 << 19)
6853 #define DE_GSE (1 << 18)
6854 #define DE_PIPEB_VBLANK (1 << 15)
6855 #define DE_PIPEB_EVEN_FIELD (1 << 14)
6856 #define DE_PIPEB_ODD_FIELD (1 << 13)
6857 #define DE_PIPEB_LINE_COMPARE (1 << 12)
6858 #define DE_PIPEB_VSYNC (1 << 11)
6859 #define DE_PIPEB_CRC_DONE (1 << 10)
6860 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
6861 #define DE_PIPEA_VBLANK (1 << 7)
6862 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
6863 #define DE_PIPEA_EVEN_FIELD (1 << 6)
6864 #define DE_PIPEA_ODD_FIELD (1 << 5)
6865 #define DE_PIPEA_LINE_COMPARE (1 << 4)
6866 #define DE_PIPEA_VSYNC (1 << 3)
6867 #define DE_PIPEA_CRC_DONE (1 << 2)
6868 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
6869 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
6870 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
6872 /* More Ivybridge lolz */
6873 #define DE_ERR_INT_IVB (1<<30)
6874 #define DE_GSE_IVB (1<<29)
6875 #define DE_PCH_EVENT_IVB (1<<28)
6876 #define DE_DP_A_HOTPLUG_IVB (1<<27)
6877 #define DE_AUX_CHANNEL_A_IVB (1<<26)
6878 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
6879 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
6880 #define DE_PIPEC_VBLANK_IVB (1<<10)
6881 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
6882 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
6883 #define DE_PIPEB_VBLANK_IVB (1<<5)
6884 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
6885 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
6886 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
6887 #define DE_PIPEA_VBLANK_IVB (1<<0)
6888 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
6890 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
6891 #define MASTER_INTERRUPT_ENABLE (1<<31)
6893 #define DEISR _MMIO(0x44000)
6894 #define DEIMR _MMIO(0x44004)
6895 #define DEIIR _MMIO(0x44008)
6896 #define DEIER _MMIO(0x4400c)
6898 #define GTISR _MMIO(0x44010)
6899 #define GTIMR _MMIO(0x44014)
6900 #define GTIIR _MMIO(0x44018)
6901 #define GTIER _MMIO(0x4401c)
6903 #define GEN8_MASTER_IRQ _MMIO(0x44200)
6904 #define GEN8_MASTER_IRQ_CONTROL (1<<31)
6905 #define GEN8_PCU_IRQ (1<<30)
6906 #define GEN8_DE_PCH_IRQ (1<<23)
6907 #define GEN8_DE_MISC_IRQ (1<<22)
6908 #define GEN8_DE_PORT_IRQ (1<<20)
6909 #define GEN8_DE_PIPE_C_IRQ (1<<18)
6910 #define GEN8_DE_PIPE_B_IRQ (1<<17)
6911 #define GEN8_DE_PIPE_A_IRQ (1<<16)
6912 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
6913 #define GEN8_GT_VECS_IRQ (1<<6)
6914 #define GEN8_GT_GUC_IRQ (1<<5)
6915 #define GEN8_GT_PM_IRQ (1<<4)
6916 #define GEN8_GT_VCS2_IRQ (1<<3)
6917 #define GEN8_GT_VCS1_IRQ (1<<2)
6918 #define GEN8_GT_BCS_IRQ (1<<1)
6919 #define GEN8_GT_RCS_IRQ (1<<0)
6921 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
6922 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
6923 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
6924 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
6926 #define GEN9_GUC_TO_HOST_INT_EVENT (1<<31)
6927 #define GEN9_GUC_EXEC_ERROR_EVENT (1<<30)
6928 #define GEN9_GUC_DISPLAY_EVENT (1<<29)
6929 #define GEN9_GUC_SEMA_SIGNAL_EVENT (1<<28)
6930 #define GEN9_GUC_IOMMU_MSG_EVENT (1<<27)
6931 #define GEN9_GUC_DB_RING_EVENT (1<<26)
6932 #define GEN9_GUC_DMA_DONE_EVENT (1<<25)
6933 #define GEN9_GUC_FATAL_ERROR_EVENT (1<<24)
6934 #define GEN9_GUC_NOTIFICATION_EVENT (1<<23)
6936 #define GEN8_RCS_IRQ_SHIFT 0
6937 #define GEN8_BCS_IRQ_SHIFT 16
6938 #define GEN8_VCS1_IRQ_SHIFT 0
6939 #define GEN8_VCS2_IRQ_SHIFT 16
6940 #define GEN8_VECS_IRQ_SHIFT 0
6941 #define GEN8_WD_IRQ_SHIFT 16
6943 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
6944 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
6945 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
6946 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
6947 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
6948 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
6949 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
6950 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
6951 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
6952 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
6953 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
6954 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
6955 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
6956 #define GEN8_PIPE_VSYNC (1 << 1)
6957 #define GEN8_PIPE_VBLANK (1 << 0)
6958 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
6959 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
6960 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
6961 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
6962 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
6963 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
6964 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
6965 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
6966 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
6967 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
6968 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
6969 (GEN8_PIPE_CURSOR_FAULT | \
6970 GEN8_PIPE_SPRITE_FAULT | \
6971 GEN8_PIPE_PRIMARY_FAULT)
6972 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
6973 (GEN9_PIPE_CURSOR_FAULT | \
6974 GEN9_PIPE_PLANE4_FAULT | \
6975 GEN9_PIPE_PLANE3_FAULT | \
6976 GEN9_PIPE_PLANE2_FAULT | \
6977 GEN9_PIPE_PLANE1_FAULT)
6979 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
6980 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
6981 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
6982 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
6983 #define CNL_AUX_CHANNEL_F (1 << 28)
6984 #define GEN9_AUX_CHANNEL_D (1 << 27)
6985 #define GEN9_AUX_CHANNEL_C (1 << 26)
6986 #define GEN9_AUX_CHANNEL_B (1 << 25)
6987 #define BXT_DE_PORT_HP_DDIC (1 << 5)
6988 #define BXT_DE_PORT_HP_DDIB (1 << 4)
6989 #define BXT_DE_PORT_HP_DDIA (1 << 3)
6990 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
6991 BXT_DE_PORT_HP_DDIB | \
6992 BXT_DE_PORT_HP_DDIC)
6993 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
6994 #define BXT_DE_PORT_GMBUS (1 << 1)
6995 #define GEN8_AUX_CHANNEL_A (1 << 0)
6997 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
6998 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
6999 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7000 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7001 #define GEN8_DE_MISC_GSE (1 << 27)
7003 #define GEN8_PCU_ISR _MMIO(0x444e0)
7004 #define GEN8_PCU_IMR _MMIO(0x444e4)
7005 #define GEN8_PCU_IIR _MMIO(0x444e8)
7006 #define GEN8_PCU_IER _MMIO(0x444ec)
7008 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
7009 #define GEN11_MASTER_IRQ (1 << 31)
7010 #define GEN11_PCU_IRQ (1 << 30)
7011 #define GEN11_DISPLAY_IRQ (1 << 16)
7012 #define GEN11_GT_DW_IRQ(x) (1 << (x))
7013 #define GEN11_GT_DW1_IRQ (1 << 1)
7014 #define GEN11_GT_DW0_IRQ (1 << 0)
7016 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
7017 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
7018 #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
7019 #define GEN11_DE_PCH_IRQ (1 << 23)
7020 #define GEN11_DE_MISC_IRQ (1 << 22)
7021 #define GEN11_DE_PORT_IRQ (1 << 20)
7022 #define GEN11_DE_PIPE_C (1 << 18)
7023 #define GEN11_DE_PIPE_B (1 << 17)
7024 #define GEN11_DE_PIPE_A (1 << 16)
7026 #define GEN11_GT_INTR_DW0 _MMIO(0x190018)
7027 #define GEN11_CSME (31)
7028 #define GEN11_GUNIT (28)
7029 #define GEN11_GUC (25)
7030 #define GEN11_WDPERF (20)
7031 #define GEN11_KCR (19)
7032 #define GEN11_GTPM (16)
7033 #define GEN11_BCS (15)
7034 #define GEN11_RCS0 (0)
7036 #define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
7037 #define GEN11_VECS(x) (31 - (x))
7038 #define GEN11_VCS(x) (x)
7040 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + (x * 4))
7042 #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
7043 #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
7044 #define GEN11_INTR_DATA_VALID (1 << 31)
7045 #define GEN11_INTR_ENGINE_MASK (0xffff)
7047 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + (x * 4))
7049 #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
7050 #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
7052 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + (x * 4))
7054 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
7055 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
7056 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
7057 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7058 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
7059 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
7061 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
7062 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
7063 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
7064 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
7065 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
7066 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
7067 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
7068 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7069 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7071 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
7072 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7073 #define ILK_ELPIN_409_SELECT (1 << 25)
7074 #define ILK_DPARB_GATE (1<<22)
7075 #define ILK_VSDPFD_FULL (1<<21)
7076 #define FUSE_STRAP _MMIO(0x42014)
7077 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
7078 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
7079 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
7080 #define IVB_PIPE_C_DISABLE (1 << 28)
7081 #define ILK_HDCP_DISABLE (1 << 25)
7082 #define ILK_eDP_A_DISABLE (1 << 24)
7083 #define HSW_CDCLK_LIMIT (1 << 24)
7084 #define ILK_DESKTOP (1 << 23)
7086 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
7087 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
7088 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
7089 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
7090 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
7091 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
7093 #define IVB_CHICKEN3 _MMIO(0x4200c)
7094 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
7095 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
7097 #define CHICKEN_PAR1_1 _MMIO(0x42080)
7098 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
7099 #define DPA_MASK_VBLANK_SRD (1 << 15)
7100 #define FORCE_ARB_IDLE_PLANES (1 << 14)
7101 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
7103 #define CHICKEN_PAR2_1 _MMIO(0x42090)
7104 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
7106 #define CHICKEN_MISC_2 _MMIO(0x42084)
7107 #define CNL_COMP_PWR_DOWN (1 << 23)
7108 #define GLK_CL2_PWR_DOWN (1 << 12)
7109 #define GLK_CL1_PWR_DOWN (1 << 11)
7110 #define GLK_CL0_PWR_DOWN (1 << 10)
7112 #define CHICKEN_MISC_4 _MMIO(0x4208c)
7113 #define FBC_STRIDE_OVERRIDE (1 << 13)
7114 #define FBC_STRIDE_MASK 0x1FFF
7116 #define _CHICKEN_PIPESL_1_A 0x420b0
7117 #define _CHICKEN_PIPESL_1_B 0x420b4
7118 #define HSW_FBCQ_DIS (1 << 22)
7119 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
7120 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7122 #define CHICKEN_TRANS_A 0x420c0
7123 #define CHICKEN_TRANS_B 0x420c4
7124 #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
7125 #define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
7126 #define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
7127 #define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
7128 #define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
7129 #define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
7130 #define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
7132 #define DISP_ARB_CTL _MMIO(0x45000)
7133 #define DISP_FBC_MEMORY_WAKE (1<<31)
7134 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
7135 #define DISP_FBC_WM_DIS (1<<15)
7136 #define DISP_ARB_CTL2 _MMIO(0x45004)
7137 #define DISP_DATA_PARTITION_5_6 (1<<6)
7138 #define DISP_IPC_ENABLE (1<<3)
7139 #define DBUF_CTL _MMIO(0x45008)
7140 #define DBUF_POWER_REQUEST (1<<31)
7141 #define DBUF_POWER_STATE (1<<30)
7142 #define GEN7_MSG_CTL _MMIO(0x45010)
7143 #define WAIT_FOR_PCH_RESET_ACK (1<<1)
7144 #define WAIT_FOR_PCH_FLR_ACK (1<<0)
7145 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
7146 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
7148 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
7149 #define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
7150 #define MASK_WAKEMEM (1<<13)
7152 #define SKL_DFSM _MMIO(0x51000)
7153 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
7154 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
7155 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
7156 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
7157 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
7158 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
7159 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
7160 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
7162 #define SKL_DSSM _MMIO(0x51004)
7163 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
7165 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
7166 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
7168 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
7169 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
7170 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1<<10)
7172 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
7173 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
7174 #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
7175 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1<<0)
7176 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
7177 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7178 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7179 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7180 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7183 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
7184 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
7185 # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
7186 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
7187 # define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
7188 # define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
7189 # define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
7190 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
7192 #define HIZ_CHICKEN _MMIO(0x7018)
7193 # define CHV_HZ_8X8_MODE_IN_1X (1<<15)
7194 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
7196 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
7197 #define DISABLE_PIXEL_MASK_CAMMING (1<<14)
7199 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7201 #define GEN7_L3SQCREG1 _MMIO(0xB010)
7202 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
7204 #define GEN8_L3SQCREG1 _MMIO(0xB100)
7206 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7207 * Using the formula in BSpec leads to a hang, while the formula here works
7208 * fine and matches the formulas for all other platforms. A BSpec change
7209 * request has been filed to clarify this.
7211 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
7212 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
7213 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
7215 #define GEN7_L3CNTLREG1 _MMIO(0xB01C)
7216 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
7217 #define GEN7_L3AGDIS (1<<19)
7218 #define GEN7_L3CNTLREG2 _MMIO(0xB020)
7219 #define GEN7_L3CNTLREG3 _MMIO(0xB024)
7221 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
7222 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
7224 #define GEN7_L3SQCREG4 _MMIO(0xb034)
7225 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
7227 #define GEN8_L3SQCREG4 _MMIO(0xb118)
7228 #define GEN8_LQSC_RO_PERF_DIS (1<<27)
7229 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
7232 #define HDC_CHICKEN0 _MMIO(0x7300)
7233 #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
7234 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
7235 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
7236 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
7237 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
7238 #define HDC_FORCE_NON_COHERENT (1<<4)
7239 #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
7241 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
7244 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
7245 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
7247 /* WaCatErrorRejectionIssue */
7248 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
7249 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
7251 #define HSW_SCRATCH1 _MMIO(0xb038)
7252 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
7254 #define BDW_SCRATCH1 _MMIO(0xb11c)
7255 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
7259 /* south display engine interrupt: IBX */
7260 #define SDE_AUDIO_POWER_D (1 << 27)
7261 #define SDE_AUDIO_POWER_C (1 << 26)
7262 #define SDE_AUDIO_POWER_B (1 << 25)
7263 #define SDE_AUDIO_POWER_SHIFT (25)
7264 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
7265 #define SDE_GMBUS (1 << 24)
7266 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
7267 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
7268 #define SDE_AUDIO_HDCP_MASK (3 << 22)
7269 #define SDE_AUDIO_TRANSB (1 << 21)
7270 #define SDE_AUDIO_TRANSA (1 << 20)
7271 #define SDE_AUDIO_TRANS_MASK (3 << 20)
7272 #define SDE_POISON (1 << 19)
7274 #define SDE_FDI_RXB (1 << 17)
7275 #define SDE_FDI_RXA (1 << 16)
7276 #define SDE_FDI_MASK (3 << 16)
7277 #define SDE_AUXD (1 << 15)
7278 #define SDE_AUXC (1 << 14)
7279 #define SDE_AUXB (1 << 13)
7280 #define SDE_AUX_MASK (7 << 13)
7282 #define SDE_CRT_HOTPLUG (1 << 11)
7283 #define SDE_PORTD_HOTPLUG (1 << 10)
7284 #define SDE_PORTC_HOTPLUG (1 << 9)
7285 #define SDE_PORTB_HOTPLUG (1 << 8)
7286 #define SDE_SDVOB_HOTPLUG (1 << 6)
7287 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
7288 SDE_SDVOB_HOTPLUG | \
7289 SDE_PORTB_HOTPLUG | \
7290 SDE_PORTC_HOTPLUG | \
7292 #define SDE_TRANSB_CRC_DONE (1 << 5)
7293 #define SDE_TRANSB_CRC_ERR (1 << 4)
7294 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
7295 #define SDE_TRANSA_CRC_DONE (1 << 2)
7296 #define SDE_TRANSA_CRC_ERR (1 << 1)
7297 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
7298 #define SDE_TRANS_MASK (0x3f)
7300 /* south display engine interrupt: CPT/PPT */
7301 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
7302 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
7303 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
7304 #define SDE_AUDIO_POWER_SHIFT_CPT 29
7305 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
7306 #define SDE_AUXD_CPT (1 << 27)
7307 #define SDE_AUXC_CPT (1 << 26)
7308 #define SDE_AUXB_CPT (1 << 25)
7309 #define SDE_AUX_MASK_CPT (7 << 25)
7310 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
7311 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
7312 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
7313 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
7314 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
7315 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
7316 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
7317 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
7318 SDE_SDVOB_HOTPLUG_CPT | \
7319 SDE_PORTD_HOTPLUG_CPT | \
7320 SDE_PORTC_HOTPLUG_CPT | \
7321 SDE_PORTB_HOTPLUG_CPT)
7322 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
7323 SDE_PORTD_HOTPLUG_CPT | \
7324 SDE_PORTC_HOTPLUG_CPT | \
7325 SDE_PORTB_HOTPLUG_CPT | \
7326 SDE_PORTA_HOTPLUG_SPT)
7327 #define SDE_GMBUS_CPT (1 << 17)
7328 #define SDE_ERROR_CPT (1 << 16)
7329 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
7330 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
7331 #define SDE_FDI_RXC_CPT (1 << 8)
7332 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
7333 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
7334 #define SDE_FDI_RXB_CPT (1 << 4)
7335 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
7336 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
7337 #define SDE_FDI_RXA_CPT (1 << 0)
7338 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
7339 SDE_AUDIO_CP_REQ_B_CPT | \
7340 SDE_AUDIO_CP_REQ_A_CPT)
7341 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
7342 SDE_AUDIO_CP_CHG_B_CPT | \
7343 SDE_AUDIO_CP_CHG_A_CPT)
7344 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
7348 #define SDEISR _MMIO(0xc4000)
7349 #define SDEIMR _MMIO(0xc4004)
7350 #define SDEIIR _MMIO(0xc4008)
7351 #define SDEIER _MMIO(0xc400c)
7353 #define SERR_INT _MMIO(0xc4040)
7354 #define SERR_INT_POISON (1<<31)
7355 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
7357 /* digital port hotplug */
7358 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
7359 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
7360 #define BXT_DDIA_HPD_INVERT (1 << 27)
7361 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
7362 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
7363 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
7364 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
7365 #define PORTD_HOTPLUG_ENABLE (1 << 20)
7366 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
7367 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
7368 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
7369 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
7370 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
7371 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
7372 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
7373 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
7374 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
7375 #define PORTC_HOTPLUG_ENABLE (1 << 12)
7376 #define BXT_DDIC_HPD_INVERT (1 << 11)
7377 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
7378 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
7379 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
7380 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
7381 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
7382 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
7383 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
7384 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
7385 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
7386 #define PORTB_HOTPLUG_ENABLE (1 << 4)
7387 #define BXT_DDIB_HPD_INVERT (1 << 3)
7388 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
7389 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
7390 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
7391 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
7392 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
7393 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
7394 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
7395 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
7396 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
7397 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
7398 BXT_DDIB_HPD_INVERT | \
7399 BXT_DDIC_HPD_INVERT)
7401 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
7402 #define PORTE_HOTPLUG_ENABLE (1 << 4)
7403 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
7404 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
7405 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
7406 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
7408 #define PCH_GPIOA _MMIO(0xc5010)
7409 #define PCH_GPIOB _MMIO(0xc5014)
7410 #define PCH_GPIOC _MMIO(0xc5018)
7411 #define PCH_GPIOD _MMIO(0xc501c)
7412 #define PCH_GPIOE _MMIO(0xc5020)
7413 #define PCH_GPIOF _MMIO(0xc5024)
7415 #define PCH_GMBUS0 _MMIO(0xc5100)
7416 #define PCH_GMBUS1 _MMIO(0xc5104)
7417 #define PCH_GMBUS2 _MMIO(0xc5108)
7418 #define PCH_GMBUS3 _MMIO(0xc510c)
7419 #define PCH_GMBUS4 _MMIO(0xc5110)
7420 #define PCH_GMBUS5 _MMIO(0xc5120)
7422 #define _PCH_DPLL_A 0xc6014
7423 #define _PCH_DPLL_B 0xc6018
7424 #define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
7426 #define _PCH_FPA0 0xc6040
7427 #define FP_CB_TUNE (0x3<<22)
7428 #define _PCH_FPA1 0xc6044
7429 #define _PCH_FPB0 0xc6048
7430 #define _PCH_FPB1 0xc604c
7431 #define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
7432 #define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
7434 #define PCH_DPLL_TEST _MMIO(0xc606c)
7436 #define PCH_DREF_CONTROL _MMIO(0xC6200)
7437 #define DREF_CONTROL_MASK 0x7fc3
7438 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
7439 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
7440 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
7441 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
7442 #define DREF_SSC_SOURCE_DISABLE (0<<11)
7443 #define DREF_SSC_SOURCE_ENABLE (2<<11)
7444 #define DREF_SSC_SOURCE_MASK (3<<11)
7445 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
7446 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
7447 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
7448 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
7449 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
7450 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
7451 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
7452 #define DREF_SSC4_DOWNSPREAD (0<<6)
7453 #define DREF_SSC4_CENTERSPREAD (1<<6)
7454 #define DREF_SSC1_DISABLE (0<<1)
7455 #define DREF_SSC1_ENABLE (1<<1)
7456 #define DREF_SSC4_DISABLE (0)
7457 #define DREF_SSC4_ENABLE (1)
7459 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
7460 #define FDL_TP1_TIMER_SHIFT 12
7461 #define FDL_TP1_TIMER_MASK (3<<12)
7462 #define FDL_TP2_TIMER_SHIFT 10
7463 #define FDL_TP2_TIMER_MASK (3<<10)
7464 #define RAWCLK_FREQ_MASK 0x3ff
7465 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
7466 #define CNP_RAWCLK_DIV(div) ((div) << 16)
7467 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
7468 #define CNP_RAWCLK_FRAC(frac) ((frac) << 26)
7469 #define ICP_RAWCLK_DEN(den) ((den) << 26)
7470 #define ICP_RAWCLK_NUM(num) ((num) << 11)
7472 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
7474 #define PCH_SSC4_PARMS _MMIO(0xc6210)
7475 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
7477 #define PCH_DPLL_SEL _MMIO(0xc7000)
7478 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
7479 #define TRANS_DPLLA_SEL(pipe) 0
7480 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
7484 #define _PCH_TRANS_HTOTAL_A 0xe0000
7485 #define TRANS_HTOTAL_SHIFT 16
7486 #define TRANS_HACTIVE_SHIFT 0
7487 #define _PCH_TRANS_HBLANK_A 0xe0004
7488 #define TRANS_HBLANK_END_SHIFT 16
7489 #define TRANS_HBLANK_START_SHIFT 0
7490 #define _PCH_TRANS_HSYNC_A 0xe0008
7491 #define TRANS_HSYNC_END_SHIFT 16
7492 #define TRANS_HSYNC_START_SHIFT 0
7493 #define _PCH_TRANS_VTOTAL_A 0xe000c
7494 #define TRANS_VTOTAL_SHIFT 16
7495 #define TRANS_VACTIVE_SHIFT 0
7496 #define _PCH_TRANS_VBLANK_A 0xe0010
7497 #define TRANS_VBLANK_END_SHIFT 16
7498 #define TRANS_VBLANK_START_SHIFT 0
7499 #define _PCH_TRANS_VSYNC_A 0xe0014
7500 #define TRANS_VSYNC_END_SHIFT 16
7501 #define TRANS_VSYNC_START_SHIFT 0
7502 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
7504 #define _PCH_TRANSA_DATA_M1 0xe0030
7505 #define _PCH_TRANSA_DATA_N1 0xe0034
7506 #define _PCH_TRANSA_DATA_M2 0xe0038
7507 #define _PCH_TRANSA_DATA_N2 0xe003c
7508 #define _PCH_TRANSA_LINK_M1 0xe0040
7509 #define _PCH_TRANSA_LINK_N1 0xe0044
7510 #define _PCH_TRANSA_LINK_M2 0xe0048
7511 #define _PCH_TRANSA_LINK_N2 0xe004c
7513 /* Per-transcoder DIP controls (PCH) */
7514 #define _VIDEO_DIP_CTL_A 0xe0200
7515 #define _VIDEO_DIP_DATA_A 0xe0208
7516 #define _VIDEO_DIP_GCP_A 0xe0210
7517 #define GCP_COLOR_INDICATION (1 << 2)
7518 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
7519 #define GCP_AV_MUTE (1 << 0)
7521 #define _VIDEO_DIP_CTL_B 0xe1200
7522 #define _VIDEO_DIP_DATA_B 0xe1208
7523 #define _VIDEO_DIP_GCP_B 0xe1210
7525 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
7526 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
7527 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
7529 /* Per-transcoder DIP controls (VLV) */
7530 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
7531 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
7532 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
7534 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
7535 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
7536 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
7538 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
7539 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
7540 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
7542 #define VLV_TVIDEO_DIP_CTL(pipe) \
7543 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
7544 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
7545 #define VLV_TVIDEO_DIP_DATA(pipe) \
7546 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
7547 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
7548 #define VLV_TVIDEO_DIP_GCP(pipe) \
7549 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
7550 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
7552 /* Haswell DIP controls */
7554 #define _HSW_VIDEO_DIP_CTL_A 0x60200
7555 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
7556 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
7557 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
7558 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
7559 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
7560 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
7561 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
7562 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
7563 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
7564 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
7565 #define _HSW_VIDEO_DIP_GCP_A 0x60210
7567 #define _HSW_VIDEO_DIP_CTL_B 0x61200
7568 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
7569 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
7570 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
7571 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
7572 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
7573 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
7574 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
7575 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
7576 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
7577 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
7578 #define _HSW_VIDEO_DIP_GCP_B 0x61210
7580 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
7581 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
7582 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
7583 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
7584 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
7585 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
7587 #define _HSW_STEREO_3D_CTL_A 0x70020
7588 #define S3D_ENABLE (1<<31)
7589 #define _HSW_STEREO_3D_CTL_B 0x71020
7591 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
7593 #define _PCH_TRANS_HTOTAL_B 0xe1000
7594 #define _PCH_TRANS_HBLANK_B 0xe1004
7595 #define _PCH_TRANS_HSYNC_B 0xe1008
7596 #define _PCH_TRANS_VTOTAL_B 0xe100c
7597 #define _PCH_TRANS_VBLANK_B 0xe1010
7598 #define _PCH_TRANS_VSYNC_B 0xe1014
7599 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
7601 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
7602 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
7603 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
7604 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
7605 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
7606 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
7607 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
7609 #define _PCH_TRANSB_DATA_M1 0xe1030
7610 #define _PCH_TRANSB_DATA_N1 0xe1034
7611 #define _PCH_TRANSB_DATA_M2 0xe1038
7612 #define _PCH_TRANSB_DATA_N2 0xe103c
7613 #define _PCH_TRANSB_LINK_M1 0xe1040
7614 #define _PCH_TRANSB_LINK_N1 0xe1044
7615 #define _PCH_TRANSB_LINK_M2 0xe1048
7616 #define _PCH_TRANSB_LINK_N2 0xe104c
7618 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
7619 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
7620 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
7621 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
7622 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
7623 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
7624 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
7625 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
7627 #define _PCH_TRANSACONF 0xf0008
7628 #define _PCH_TRANSBCONF 0xf1008
7629 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
7630 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
7631 #define TRANS_DISABLE (0<<31)
7632 #define TRANS_ENABLE (1<<31)
7633 #define TRANS_STATE_MASK (1<<30)
7634 #define TRANS_STATE_DISABLE (0<<30)
7635 #define TRANS_STATE_ENABLE (1<<30)
7636 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
7637 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
7638 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
7639 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
7640 #define TRANS_INTERLACE_MASK (7<<21)
7641 #define TRANS_PROGRESSIVE (0<<21)
7642 #define TRANS_INTERLACED (3<<21)
7643 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
7644 #define TRANS_8BPC (0<<5)
7645 #define TRANS_10BPC (1<<5)
7646 #define TRANS_6BPC (2<<5)
7647 #define TRANS_12BPC (3<<5)
7649 #define _TRANSA_CHICKEN1 0xf0060
7650 #define _TRANSB_CHICKEN1 0xf1060
7651 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
7652 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
7653 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
7654 #define _TRANSA_CHICKEN2 0xf0064
7655 #define _TRANSB_CHICKEN2 0xf1064
7656 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
7657 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
7658 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
7659 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
7660 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
7661 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
7663 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
7664 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
7665 #define FDIA_PHASE_SYNC_SHIFT_EN 18
7666 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
7667 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
7668 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
7669 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
7670 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
7671 #define SPT_PWM_GRANULARITY (1<<0)
7672 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
7673 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
7674 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
7675 #define LPT_PWM_GRANULARITY (1<<5)
7676 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
7678 #define _FDI_RXA_CHICKEN 0xc200c
7679 #define _FDI_RXB_CHICKEN 0xc2010
7680 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
7681 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
7682 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
7684 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
7685 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1<<31)
7686 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
7687 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
7688 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
7689 #define CNP_PWM_CGE_GATING_DISABLE (1<<13)
7690 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
7693 #define _FDI_TXA_CTL 0x60100
7694 #define _FDI_TXB_CTL 0x61100
7695 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
7696 #define FDI_TX_DISABLE (0<<31)
7697 #define FDI_TX_ENABLE (1<<31)
7698 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
7699 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
7700 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
7701 #define FDI_LINK_TRAIN_NONE (3<<28)
7702 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
7703 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
7704 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
7705 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
7706 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
7707 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
7708 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
7709 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
7710 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
7711 SNB has different settings. */
7712 /* SNB A-stepping */
7713 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
7714 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
7715 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
7716 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
7717 /* SNB B-stepping */
7718 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
7719 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
7720 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
7721 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
7722 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
7723 #define FDI_DP_PORT_WIDTH_SHIFT 19
7724 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
7725 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
7726 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
7727 /* Ironlake: hardwired to 1 */
7728 #define FDI_TX_PLL_ENABLE (1<<14)
7730 /* Ivybridge has different bits for lolz */
7731 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
7732 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
7733 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
7734 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
7736 /* both Tx and Rx */
7737 #define FDI_COMPOSITE_SYNC (1<<11)
7738 #define FDI_LINK_TRAIN_AUTO (1<<10)
7739 #define FDI_SCRAMBLING_ENABLE (0<<7)
7740 #define FDI_SCRAMBLING_DISABLE (1<<7)
7742 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
7743 #define _FDI_RXA_CTL 0xf000c
7744 #define _FDI_RXB_CTL 0xf100c
7745 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
7746 #define FDI_RX_ENABLE (1<<31)
7747 /* train, dp width same as FDI_TX */
7748 #define FDI_FS_ERRC_ENABLE (1<<27)
7749 #define FDI_FE_ERRC_ENABLE (1<<26)
7750 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
7751 #define FDI_8BPC (0<<16)
7752 #define FDI_10BPC (1<<16)
7753 #define FDI_6BPC (2<<16)
7754 #define FDI_12BPC (3<<16)
7755 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
7756 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
7757 #define FDI_RX_PLL_ENABLE (1<<13)
7758 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
7759 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
7760 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
7761 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
7762 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
7763 #define FDI_PCDCLK (1<<4)
7765 #define FDI_AUTO_TRAINING (1<<10)
7766 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
7767 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
7768 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
7769 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
7770 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
7772 #define _FDI_RXA_MISC 0xf0010
7773 #define _FDI_RXB_MISC 0xf1010
7774 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
7775 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
7776 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
7777 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
7778 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
7779 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
7780 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
7781 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
7783 #define _FDI_RXA_TUSIZE1 0xf0030
7784 #define _FDI_RXA_TUSIZE2 0xf0038
7785 #define _FDI_RXB_TUSIZE1 0xf1030
7786 #define _FDI_RXB_TUSIZE2 0xf1038
7787 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
7788 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
7790 /* FDI_RX interrupt register format */
7791 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
7792 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
7793 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
7794 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
7795 #define FDI_RX_FS_CODE_ERR (1<<6)
7796 #define FDI_RX_FE_CODE_ERR (1<<5)
7797 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
7798 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
7799 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
7800 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
7801 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
7803 #define _FDI_RXA_IIR 0xf0014
7804 #define _FDI_RXA_IMR 0xf0018
7805 #define _FDI_RXB_IIR 0xf1014
7806 #define _FDI_RXB_IMR 0xf1018
7807 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
7808 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
7810 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
7811 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
7813 #define PCH_LVDS _MMIO(0xe1180)
7814 #define LVDS_DETECTED (1 << 1)
7816 #define _PCH_DP_B 0xe4100
7817 #define PCH_DP_B _MMIO(_PCH_DP_B)
7818 #define _PCH_DPB_AUX_CH_CTL 0xe4110
7819 #define _PCH_DPB_AUX_CH_DATA1 0xe4114
7820 #define _PCH_DPB_AUX_CH_DATA2 0xe4118
7821 #define _PCH_DPB_AUX_CH_DATA3 0xe411c
7822 #define _PCH_DPB_AUX_CH_DATA4 0xe4120
7823 #define _PCH_DPB_AUX_CH_DATA5 0xe4124
7825 #define _PCH_DP_C 0xe4200
7826 #define PCH_DP_C _MMIO(_PCH_DP_C)
7827 #define _PCH_DPC_AUX_CH_CTL 0xe4210
7828 #define _PCH_DPC_AUX_CH_DATA1 0xe4214
7829 #define _PCH_DPC_AUX_CH_DATA2 0xe4218
7830 #define _PCH_DPC_AUX_CH_DATA3 0xe421c
7831 #define _PCH_DPC_AUX_CH_DATA4 0xe4220
7832 #define _PCH_DPC_AUX_CH_DATA5 0xe4224
7834 #define _PCH_DP_D 0xe4300
7835 #define PCH_DP_D _MMIO(_PCH_DP_D)
7836 #define _PCH_DPD_AUX_CH_CTL 0xe4310
7837 #define _PCH_DPD_AUX_CH_DATA1 0xe4314
7838 #define _PCH_DPD_AUX_CH_DATA2 0xe4318
7839 #define _PCH_DPD_AUX_CH_DATA3 0xe431c
7840 #define _PCH_DPD_AUX_CH_DATA4 0xe4320
7841 #define _PCH_DPD_AUX_CH_DATA5 0xe4324
7843 #define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
7844 #define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
7847 #define PORT_TRANS_A_SEL_CPT 0
7848 #define PORT_TRANS_B_SEL_CPT (1<<29)
7849 #define PORT_TRANS_C_SEL_CPT (2<<29)
7850 #define PORT_TRANS_SEL_MASK (3<<29)
7851 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
7852 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
7853 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
7854 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
7855 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
7857 #define _TRANS_DP_CTL_A 0xe0300
7858 #define _TRANS_DP_CTL_B 0xe1300
7859 #define _TRANS_DP_CTL_C 0xe2300
7860 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
7861 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
7862 #define TRANS_DP_PORT_SEL_B (0<<29)
7863 #define TRANS_DP_PORT_SEL_C (1<<29)
7864 #define TRANS_DP_PORT_SEL_D (2<<29)
7865 #define TRANS_DP_PORT_SEL_NONE (3<<29)
7866 #define TRANS_DP_PORT_SEL_MASK (3<<29)
7867 #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
7868 #define TRANS_DP_AUDIO_ONLY (1<<26)
7869 #define TRANS_DP_ENH_FRAMING (1<<18)
7870 #define TRANS_DP_8BPC (0<<9)
7871 #define TRANS_DP_10BPC (1<<9)
7872 #define TRANS_DP_6BPC (2<<9)
7873 #define TRANS_DP_12BPC (3<<9)
7874 #define TRANS_DP_BPC_MASK (3<<9)
7875 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
7876 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
7877 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
7878 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
7879 #define TRANS_DP_SYNC_MASK (3<<3)
7881 /* SNB eDP training params */
7882 /* SNB A-stepping */
7883 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
7884 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
7885 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
7886 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
7887 /* SNB B-stepping */
7888 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
7889 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
7890 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
7891 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
7892 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
7893 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
7896 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
7897 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
7898 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
7899 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
7900 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
7901 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
7902 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
7905 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
7906 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
7907 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
7908 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
7909 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
7911 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
7913 #define VLV_PMWGICZ _MMIO(0x1300a4)
7915 #define RC6_LOCATION _MMIO(0xD40)
7916 #define RC6_CTX_IN_DRAM (1 << 0)
7917 #define RC6_CTX_BASE _MMIO(0xD48)
7918 #define RC6_CTX_BASE_MASK 0xFFFFFFF0
7919 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
7920 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
7921 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
7922 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
7923 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
7924 #define IDLE_TIME_MASK 0xFFFFF
7925 #define FORCEWAKE _MMIO(0xA18C)
7926 #define FORCEWAKE_VLV _MMIO(0x1300b0)
7927 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
7928 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
7929 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
7930 #define FORCEWAKE_ACK_HSW _MMIO(0x130044)
7931 #define FORCEWAKE_ACK _MMIO(0x130090)
7932 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
7933 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
7934 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
7935 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
7937 #define VLV_GTLC_PW_STATUS _MMIO(0x130094)
7938 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
7939 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
7940 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
7941 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
7942 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
7943 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
7944 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
7945 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
7946 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
7947 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
7948 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
7949 #define FORCEWAKE_KERNEL BIT(0)
7950 #define FORCEWAKE_USER BIT(1)
7951 #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
7952 #define FORCEWAKE_MT_ACK _MMIO(0x130040)
7953 #define ECOBUS _MMIO(0xa180)
7954 #define FORCEWAKE_MT_ENABLE (1<<5)
7955 #define VLV_SPAREG2H _MMIO(0xA194)
7956 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
7957 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
7958 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
7960 #define GTFIFODBG _MMIO(0x120000)
7961 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
7962 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
7963 #define GT_FIFO_SBDROPERR (1<<6)
7964 #define GT_FIFO_BLOBDROPERR (1<<5)
7965 #define GT_FIFO_SB_READ_ABORTERR (1<<4)
7966 #define GT_FIFO_DROPERR (1<<3)
7967 #define GT_FIFO_OVFERR (1<<2)
7968 #define GT_FIFO_IAWRERR (1<<1)
7969 #define GT_FIFO_IARDERR (1<<0)
7971 #define GTFIFOCTL _MMIO(0x120008)
7972 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
7973 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
7974 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
7975 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
7977 #define HSW_IDICR _MMIO(0x9008)
7978 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
7979 #define HSW_EDRAM_CAP _MMIO(0x120010)
7980 #define EDRAM_ENABLED 0x1
7981 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
7982 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
7983 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
7985 #define GEN6_UCGCTL1 _MMIO(0x9400)
7986 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
7987 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
7988 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
7989 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
7991 #define GEN6_UCGCTL2 _MMIO(0x9404)
7992 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
7993 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
7994 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
7995 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
7996 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
7997 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
7999 #define GEN6_UCGCTL3 _MMIO(0x9408)
8000 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
8002 #define GEN7_UCGCTL4 _MMIO(0x940c)
8003 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
8004 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14)
8006 #define GEN6_RCGCTL1 _MMIO(0x9410)
8007 #define GEN6_RCGCTL2 _MMIO(0x9414)
8008 #define GEN6_RSTCTL _MMIO(0x9420)
8010 #define GEN8_UCGCTL6 _MMIO(0x9430)
8011 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
8012 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
8013 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
8015 #define GEN6_GFXPAUSE _MMIO(0xA000)
8016 #define GEN6_RPNSWREQ _MMIO(0xA008)
8017 #define GEN6_TURBO_DISABLE (1<<31)
8018 #define GEN6_FREQUENCY(x) ((x)<<25)
8019 #define HSW_FREQUENCY(x) ((x)<<24)
8020 #define GEN9_FREQUENCY(x) ((x)<<23)
8021 #define GEN6_OFFSET(x) ((x)<<19)
8022 #define GEN6_AGGRESSIVE_TURBO (0<<15)
8023 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
8024 #define GEN6_RC_CONTROL _MMIO(0xA090)
8025 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
8026 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
8027 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
8028 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
8029 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
8030 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
8031 #define GEN7_RC_CTL_TO_MODE (1<<28)
8032 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
8033 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
8034 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
8035 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
8036 #define GEN6_RPSTAT1 _MMIO(0xA01C)
8037 #define GEN6_CAGF_SHIFT 8
8038 #define HSW_CAGF_SHIFT 7
8039 #define GEN9_CAGF_SHIFT 23
8040 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
8041 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
8042 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
8043 #define GEN6_RP_CONTROL _MMIO(0xA024)
8044 #define GEN6_RP_MEDIA_TURBO (1<<11)
8045 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
8046 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
8047 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
8048 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
8049 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
8050 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
8051 #define GEN6_RP_ENABLE (1<<7)
8052 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
8053 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
8054 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
8055 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
8056 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
8057 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
8058 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
8059 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
8060 #define GEN6_RP_EI_MASK 0xffffff
8061 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
8062 #define GEN6_RP_CUR_UP _MMIO(0xA054)
8063 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
8064 #define GEN6_RP_PREV_UP _MMIO(0xA058)
8065 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
8066 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
8067 #define GEN6_RP_CUR_DOWN _MMIO(0xA060)
8068 #define GEN6_RP_PREV_DOWN _MMIO(0xA064)
8069 #define GEN6_RP_UP_EI _MMIO(0xA068)
8070 #define GEN6_RP_DOWN_EI _MMIO(0xA06C)
8071 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
8072 #define GEN6_RPDEUHWTC _MMIO(0xA080)
8073 #define GEN6_RPDEUC _MMIO(0xA084)
8074 #define GEN6_RPDEUCSW _MMIO(0xA088)
8075 #define GEN6_RC_STATE _MMIO(0xA094)
8076 #define RC_SW_TARGET_STATE_SHIFT 16
8077 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
8078 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
8079 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
8080 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8081 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8082 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
8083 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
8084 #define GEN6_RC_SLEEP _MMIO(0xA0B0)
8085 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
8086 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
8087 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
8088 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
8089 #define VLV_RCEDATA _MMIO(0xA0BC)
8090 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
8091 #define GEN6_PMINTRMSK _MMIO(0xA168)
8092 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1<<31)
8093 #define ARAT_EXPIRED_INTRMSK (1<<9)
8094 #define GEN8_MISC_CTRL0 _MMIO(0xA180)
8095 #define VLV_PWRDWNUPCTL _MMIO(0xA294)
8096 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
8097 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
8098 #define GEN9_PG_ENABLE _MMIO(0xA210)
8099 #define GEN9_RENDER_PG_ENABLE (1<<0)
8100 #define GEN9_MEDIA_PG_ENABLE (1<<1)
8101 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
8102 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
8103 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
8105 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8106 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
8107 #define PIXEL_OVERLAP_CNT_SHIFT 30
8109 #define GEN6_PMISR _MMIO(0x44020)
8110 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
8111 #define GEN6_PMIIR _MMIO(0x44028)
8112 #define GEN6_PMIER _MMIO(0x4402C)
8113 #define GEN6_PM_MBOX_EVENT (1<<25)
8114 #define GEN6_PM_THERMAL_EVENT (1<<24)
8115 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
8116 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
8117 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
8118 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
8119 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
8120 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
8121 GEN6_PM_RP_DOWN_THRESHOLD | \
8122 GEN6_PM_RP_DOWN_TIMEOUT)
8124 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
8125 #define GEN7_GT_SCRATCH_REG_NUM 8
8127 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
8128 #define VLV_GFX_CLK_STATUS_BIT (1<<3)
8129 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
8131 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
8132 #define VLV_COUNTER_CONTROL _MMIO(0x138104)
8133 #define VLV_COUNT_RANGE_HIGH (1<<15)
8134 #define VLV_MEDIA_RC0_COUNT_EN (1<<5)
8135 #define VLV_RENDER_RC0_COUNT_EN (1<<4)
8136 #define VLV_MEDIA_RC6_COUNT_EN (1<<1)
8137 #define VLV_RENDER_RC6_COUNT_EN (1<<0)
8138 #define GEN6_GT_GFX_RC6 _MMIO(0x138108)
8139 #define VLV_GT_RENDER_RC6 _MMIO(0x138108)
8140 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
8142 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
8143 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
8144 #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
8145 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
8147 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
8148 #define GEN6_PCODE_READY (1<<31)
8149 #define GEN6_PCODE_ERROR_MASK 0xFF
8150 #define GEN6_PCODE_SUCCESS 0x0
8151 #define GEN6_PCODE_ILLEGAL_CMD 0x1
8152 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8153 #define GEN6_PCODE_TIMEOUT 0x3
8154 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
8155 #define GEN7_PCODE_TIMEOUT 0x2
8156 #define GEN7_PCODE_ILLEGAL_DATA 0x3
8157 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8158 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
8159 #define GEN6_PCODE_READ_RC6VIDS 0x5
8160 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
8161 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
8162 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
8163 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
8164 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
8165 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
8166 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
8167 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
8168 #define SKL_PCODE_CDCLK_CONTROL 0x7
8169 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
8170 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
8171 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
8172 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
8173 #define GEN6_READ_OC_PARAMS 0xc
8174 #define GEN6_PCODE_READ_D_COMP 0x10
8175 #define GEN6_PCODE_WRITE_D_COMP 0x11
8176 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
8177 #define DISPLAY_IPS_CONTROL 0x19
8178 /* See also IPS_CTL */
8179 #define IPS_PCODE_CONTROL (1 << 30)
8180 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
8181 #define GEN9_PCODE_SAGV_CONTROL 0x21
8182 #define GEN9_SAGV_DISABLE 0x0
8183 #define GEN9_SAGV_IS_DISABLED 0x1
8184 #define GEN9_SAGV_ENABLE 0x3
8185 #define GEN6_PCODE_DATA _MMIO(0x138128)
8186 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
8187 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
8188 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
8190 #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
8191 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
8192 #define GEN6_RCn_MASK 7
8198 #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
8199 #define GEN8_LSLICESTAT_MASK 0x7
8201 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
8202 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
8203 #define CHV_SS_PG_ENABLE (1<<1)
8204 #define CHV_EU08_PG_ENABLE (1<<9)
8205 #define CHV_EU19_PG_ENABLE (1<<17)
8206 #define CHV_EU210_PG_ENABLE (1<<25)
8208 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
8209 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
8210 #define CHV_EU311_PG_ENABLE (1<<1)
8212 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
8213 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
8214 ((slice) % 3) * 0x4)
8215 #define GEN9_PGCTL_SLICE_ACK (1 << 0)
8216 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
8217 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
8219 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
8220 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
8221 ((slice) % 3) * 0x8)
8222 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
8223 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8224 ((slice) % 3) * 0x8)
8225 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
8226 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
8227 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
8228 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
8229 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
8230 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
8231 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
8232 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
8234 #define GEN7_MISCCPCTL _MMIO(0x9424)
8235 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
8236 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)
8237 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
8238 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
8240 #define GEN8_GARBCNTL _MMIO(0xB004)
8241 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
8244 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
8245 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
8246 #define GEN7_PARITY_ERROR_VALID (1<<13)
8247 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
8248 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
8249 #define GEN7_PARITY_ERROR_ROW(reg) \
8250 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8251 #define GEN7_PARITY_ERROR_BANK(reg) \
8252 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8253 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
8254 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8255 #define GEN7_L3CDERRST1_ENABLE (1<<7)
8257 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
8258 #define GEN7_L3LOG_SIZE 0x80
8260 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
8261 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
8262 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
8263 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
8264 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
8265 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
8267 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
8268 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
8269 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
8271 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
8272 #define FLOW_CONTROL_ENABLE (1<<15)
8273 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
8274 #define STALL_DOP_GATING_DISABLE (1<<5)
8275 #define THROTTLE_12_5 (7<<2)
8276 #define DISABLE_EARLY_EOT (1<<1)
8278 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
8279 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
8280 #define DOP_CLOCK_GATING_DISABLE (1<<0)
8281 #define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
8283 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
8284 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
8286 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
8287 #define GEN8_ST_PO_DISABLE (1<<13)
8289 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
8290 #define HSW_SAMPLE_C_PERFORMANCE (1<<9)
8291 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
8292 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
8293 #define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4)
8294 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
8296 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
8297 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1<<8)
8298 #define GEN9_ENABLE_YV12_BUGFIX (1<<4)
8299 #define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2)
8302 #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
8303 #define INTEL_AUDIO_DEVCL 0x808629FB
8304 #define INTEL_AUDIO_DEVBLC 0x80862801
8305 #define INTEL_AUDIO_DEVCTG 0x80862802
8307 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
8308 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
8309 #define G4X_ELDV_DEVCTG (1 << 14)
8310 #define G4X_ELD_ADDR_MASK (0xf << 5)
8311 #define G4X_ELD_ACK (1 << 4)
8312 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
8314 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
8315 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
8316 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
8317 _IBX_HDMIW_HDMIEDID_B)
8318 #define _IBX_AUD_CNTL_ST_A 0xE20B4
8319 #define _IBX_AUD_CNTL_ST_B 0xE21B4
8320 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
8322 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
8323 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
8324 #define IBX_ELD_ACK (1 << 4)
8325 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
8326 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
8327 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
8329 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
8330 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
8331 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
8332 #define _CPT_AUD_CNTL_ST_A 0xE50B4
8333 #define _CPT_AUD_CNTL_ST_B 0xE51B4
8334 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
8335 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
8337 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
8338 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
8339 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
8340 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
8341 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
8342 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
8343 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
8345 /* These are the 4 32-bit write offset registers for each stream
8346 * output buffer. It determines the offset from the
8347 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
8349 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
8351 #define _IBX_AUD_CONFIG_A 0xe2000
8352 #define _IBX_AUD_CONFIG_B 0xe2100
8353 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
8354 #define _CPT_AUD_CONFIG_A 0xe5000
8355 #define _CPT_AUD_CONFIG_B 0xe5100
8356 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
8357 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
8358 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
8359 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
8361 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
8362 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
8363 #define AUD_CONFIG_UPPER_N_SHIFT 20
8364 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
8365 #define AUD_CONFIG_LOWER_N_SHIFT 4
8366 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
8367 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
8368 #define AUD_CONFIG_N(n) \
8369 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
8370 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
8371 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
8372 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
8373 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
8374 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
8375 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
8376 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
8377 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
8378 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
8379 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
8380 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
8381 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
8382 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
8383 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
8386 #define _HSW_AUD_CONFIG_A 0x65000
8387 #define _HSW_AUD_CONFIG_B 0x65100
8388 #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
8390 #define _HSW_AUD_MISC_CTRL_A 0x65010
8391 #define _HSW_AUD_MISC_CTRL_B 0x65110
8392 #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
8394 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028
8395 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128
8396 #define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
8397 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
8398 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
8399 #define AUD_CONFIG_M_MASK 0xfffff
8401 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
8402 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
8403 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
8405 /* Audio Digital Converter */
8406 #define _HSW_AUD_DIG_CNVT_1 0x65080
8407 #define _HSW_AUD_DIG_CNVT_2 0x65180
8408 #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
8409 #define DIP_PORT_SEL_MASK 0x3
8411 #define _HSW_AUD_EDID_DATA_A 0x65050
8412 #define _HSW_AUD_EDID_DATA_B 0x65150
8413 #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
8415 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
8416 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
8417 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
8418 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
8419 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
8420 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
8422 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
8423 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
8425 /* HSW Power Wells */
8426 #define _HSW_PWR_WELL_CTL1 0x45400
8427 #define _HSW_PWR_WELL_CTL2 0x45404
8428 #define _HSW_PWR_WELL_CTL3 0x45408
8429 #define _HSW_PWR_WELL_CTL4 0x4540C
8432 * Each power well control register contains up to 16 (request, status) HW
8433 * flag tuples. The register index and HW flag shift is determined by the
8434 * power well ID (see i915_power_well_id). There are 4 possible sources of
8435 * power well requests each source having its own set of control registers:
8436 * BIOS, DRIVER, KVMR, DEBUG.
8438 #define _HSW_PW_REG_IDX(pw) ((pw) >> 4)
8439 #define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2)
8440 /* TODO: Add all PWR_WELL_CTL registers below for new platforms */
8441 #define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8442 _HSW_PWR_WELL_CTL1))
8443 #define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8444 _HSW_PWR_WELL_CTL2))
8445 #define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3)
8446 #define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8447 _HSW_PWR_WELL_CTL4))
8449 #define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1))
8450 #define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw))
8451 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
8452 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
8453 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
8454 #define HSW_PWR_WELL_FORCE_ON (1<<19)
8455 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
8457 /* SKL Fuse Status */
8458 enum skl_power_gate {
8464 #define SKL_FUSE_STATUS _MMIO(0x42000)
8465 #define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
8466 /* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
8467 #define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
8468 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
8470 #define _CNL_AUX_REG_IDX(pw) ((pw) - 9)
8471 #define _CNL_AUX_ANAOVRD1_B 0x162250
8472 #define _CNL_AUX_ANAOVRD1_C 0x162210
8473 #define _CNL_AUX_ANAOVRD1_D 0x1622D0
8474 #define _CNL_AUX_ANAOVRD1_F 0x162A90
8475 #define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
8476 _CNL_AUX_ANAOVRD1_B, \
8477 _CNL_AUX_ANAOVRD1_C, \
8478 _CNL_AUX_ANAOVRD1_D, \
8479 _CNL_AUX_ANAOVRD1_F))
8480 #define CNL_AUX_ANAOVRD1_ENABLE (1<<16)
8481 #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23)
8483 /* Per-pipe DDI Function Control */
8484 #define _TRANS_DDI_FUNC_CTL_A 0x60400
8485 #define _TRANS_DDI_FUNC_CTL_B 0x61400
8486 #define _TRANS_DDI_FUNC_CTL_C 0x62400
8487 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
8488 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
8490 #define TRANS_DDI_FUNC_ENABLE (1<<31)
8491 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
8492 #define TRANS_DDI_PORT_MASK (7<<28)
8493 #define TRANS_DDI_PORT_SHIFT 28
8494 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
8495 #define TRANS_DDI_PORT_NONE (0<<28)
8496 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
8497 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
8498 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
8499 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
8500 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
8501 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
8502 #define TRANS_DDI_BPC_MASK (7<<20)
8503 #define TRANS_DDI_BPC_8 (0<<20)
8504 #define TRANS_DDI_BPC_10 (1<<20)
8505 #define TRANS_DDI_BPC_6 (2<<20)
8506 #define TRANS_DDI_BPC_12 (3<<20)
8507 #define TRANS_DDI_PVSYNC (1<<17)
8508 #define TRANS_DDI_PHSYNC (1<<16)
8509 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
8510 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
8511 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
8512 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
8513 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
8514 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
8515 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7)
8516 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6)
8517 #define TRANS_DDI_BFI_ENABLE (1<<4)
8518 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1<<4)
8519 #define TRANS_DDI_HDMI_SCRAMBLING (1<<0)
8520 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
8521 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
8522 | TRANS_DDI_HDMI_SCRAMBLING)
8524 /* DisplayPort Transport Control */
8525 #define _DP_TP_CTL_A 0x64040
8526 #define _DP_TP_CTL_B 0x64140
8527 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
8528 #define DP_TP_CTL_ENABLE (1<<31)
8529 #define DP_TP_CTL_MODE_SST (0<<27)
8530 #define DP_TP_CTL_MODE_MST (1<<27)
8531 #define DP_TP_CTL_FORCE_ACT (1<<25)
8532 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
8533 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
8534 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
8535 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
8536 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
8537 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
8538 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
8539 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
8540 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
8542 /* DisplayPort Transport Status */
8543 #define _DP_TP_STATUS_A 0x64044
8544 #define _DP_TP_STATUS_B 0x64144
8545 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
8546 #define DP_TP_STATUS_IDLE_DONE (1<<25)
8547 #define DP_TP_STATUS_ACT_SENT (1<<24)
8548 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
8549 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
8550 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
8551 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
8552 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
8554 /* DDI Buffer Control */
8555 #define _DDI_BUF_CTL_A 0x64000
8556 #define _DDI_BUF_CTL_B 0x64100
8557 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
8558 #define DDI_BUF_CTL_ENABLE (1<<31)
8559 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
8560 #define DDI_BUF_EMP_MASK (0xf<<24)
8561 #define DDI_BUF_PORT_REVERSAL (1<<16)
8562 #define DDI_BUF_IS_IDLE (1<<7)
8563 #define DDI_A_4_LANES (1<<4)
8564 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
8565 #define DDI_PORT_WIDTH_MASK (7 << 1)
8566 #define DDI_PORT_WIDTH_SHIFT 1
8567 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
8569 /* DDI Buffer Translations */
8570 #define _DDI_BUF_TRANS_A 0x64E00
8571 #define _DDI_BUF_TRANS_B 0x64E60
8572 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
8573 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
8574 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
8576 /* Sideband Interface (SBI) is programmed indirectly, via
8577 * SBI_ADDR, which contains the register offset; and SBI_DATA,
8578 * which contains the payload */
8579 #define SBI_ADDR _MMIO(0xC6000)
8580 #define SBI_DATA _MMIO(0xC6004)
8581 #define SBI_CTL_STAT _MMIO(0xC6008)
8582 #define SBI_CTL_DEST_ICLK (0x0<<16)
8583 #define SBI_CTL_DEST_MPHY (0x1<<16)
8584 #define SBI_CTL_OP_IORD (0x2<<8)
8585 #define SBI_CTL_OP_IOWR (0x3<<8)
8586 #define SBI_CTL_OP_CRRD (0x6<<8)
8587 #define SBI_CTL_OP_CRWR (0x7<<8)
8588 #define SBI_RESPONSE_FAIL (0x1<<1)
8589 #define SBI_RESPONSE_SUCCESS (0x0<<1)
8590 #define SBI_BUSY (0x1<<0)
8591 #define SBI_READY (0x0<<0)
8594 #define SBI_SSCDIVINTPHASE 0x0200
8595 #define SBI_SSCDIVINTPHASE6 0x0600
8596 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
8597 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1)
8598 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
8599 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
8600 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8)
8601 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
8602 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
8603 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
8604 #define SBI_SSCDITHPHASE 0x0204
8605 #define SBI_SSCCTL 0x020c
8606 #define SBI_SSCCTL6 0x060C
8607 #define SBI_SSCCTL_PATHALT (1<<3)
8608 #define SBI_SSCCTL_DISABLE (1<<0)
8609 #define SBI_SSCAUXDIV6 0x0610
8610 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
8611 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4)
8612 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
8613 #define SBI_DBUFF0 0x2a00
8614 #define SBI_GEN0 0x1f00
8615 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
8617 /* LPT PIXCLK_GATE */
8618 #define PIXCLK_GATE _MMIO(0xC6020)
8619 #define PIXCLK_GATE_UNGATE (1<<0)
8620 #define PIXCLK_GATE_GATE (0<<0)
8623 #define SPLL_CTL _MMIO(0x46020)
8624 #define SPLL_PLL_ENABLE (1<<31)
8625 #define SPLL_PLL_SSC (1<<28)
8626 #define SPLL_PLL_NON_SSC (2<<28)
8627 #define SPLL_PLL_LCPLL (3<<28)
8628 #define SPLL_PLL_REF_MASK (3<<28)
8629 #define SPLL_PLL_FREQ_810MHz (0<<26)
8630 #define SPLL_PLL_FREQ_1350MHz (1<<26)
8631 #define SPLL_PLL_FREQ_2700MHz (2<<26)
8632 #define SPLL_PLL_FREQ_MASK (3<<26)
8635 #define _WRPLL_CTL1 0x46040
8636 #define _WRPLL_CTL2 0x46060
8637 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
8638 #define WRPLL_PLL_ENABLE (1<<31)
8639 #define WRPLL_PLL_SSC (1<<28)
8640 #define WRPLL_PLL_NON_SSC (2<<28)
8641 #define WRPLL_PLL_LCPLL (3<<28)
8642 #define WRPLL_PLL_REF_MASK (3<<28)
8643 /* WRPLL divider programming */
8644 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
8645 #define WRPLL_DIVIDER_REF_MASK (0xff)
8646 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
8647 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
8648 #define WRPLL_DIVIDER_POST_SHIFT 8
8649 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
8650 #define WRPLL_DIVIDER_FB_SHIFT 16
8651 #define WRPLL_DIVIDER_FB_MASK (0xff<<16)
8653 /* Port clock selection */
8654 #define _PORT_CLK_SEL_A 0x46100
8655 #define _PORT_CLK_SEL_B 0x46104
8656 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
8657 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
8658 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
8659 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
8660 #define PORT_CLK_SEL_SPLL (3<<29)
8661 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
8662 #define PORT_CLK_SEL_WRPLL1 (4<<29)
8663 #define PORT_CLK_SEL_WRPLL2 (5<<29)
8664 #define PORT_CLK_SEL_NONE (7<<29)
8665 #define PORT_CLK_SEL_MASK (7<<29)
8667 /* Transcoder clock selection */
8668 #define _TRANS_CLK_SEL_A 0x46140
8669 #define _TRANS_CLK_SEL_B 0x46144
8670 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
8671 /* For each transcoder, we need to select the corresponding port clock */
8672 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
8673 #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
8675 #define CDCLK_FREQ _MMIO(0x46200)
8677 #define _TRANSA_MSA_MISC 0x60410
8678 #define _TRANSB_MSA_MISC 0x61410
8679 #define _TRANSC_MSA_MISC 0x62410
8680 #define _TRANS_EDP_MSA_MISC 0x6f410
8681 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
8683 #define TRANS_MSA_SYNC_CLK (1<<0)
8684 #define TRANS_MSA_6_BPC (0<<5)
8685 #define TRANS_MSA_8_BPC (1<<5)
8686 #define TRANS_MSA_10_BPC (2<<5)
8687 #define TRANS_MSA_12_BPC (3<<5)
8688 #define TRANS_MSA_16_BPC (4<<5)
8691 #define LCPLL_CTL _MMIO(0x130040)
8692 #define LCPLL_PLL_DISABLE (1<<31)
8693 #define LCPLL_PLL_LOCK (1<<30)
8694 #define LCPLL_CLK_FREQ_MASK (3<<26)
8695 #define LCPLL_CLK_FREQ_450 (0<<26)
8696 #define LCPLL_CLK_FREQ_54O_BDW (1<<26)
8697 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
8698 #define LCPLL_CLK_FREQ_675_BDW (3<<26)
8699 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
8700 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24)
8701 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
8702 #define LCPLL_POWER_DOWN_ALLOW (1<<22)
8703 #define LCPLL_CD_SOURCE_FCLK (1<<21)
8704 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
8711 #define CDCLK_CTL _MMIO(0x46000)
8712 #define CDCLK_FREQ_SEL_MASK (3<<26)
8713 #define CDCLK_FREQ_450_432 (0<<26)
8714 #define CDCLK_FREQ_540 (1<<26)
8715 #define CDCLK_FREQ_337_308 (2<<26)
8716 #define CDCLK_FREQ_675_617 (3<<26)
8717 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
8718 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
8719 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
8720 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
8721 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
8722 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
8723 #define CDCLK_DIVMUX_CD_OVERRIDE (1<<19)
8724 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
8725 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
8726 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
8729 #define LCPLL1_CTL _MMIO(0x46010)
8730 #define LCPLL2_CTL _MMIO(0x46014)
8731 #define LCPLL_PLL_ENABLE (1<<31)
8734 #define DPLL_CTRL1 _MMIO(0x6C058)
8735 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
8736 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
8737 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
8738 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1)
8739 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
8740 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
8741 #define DPLL_CTRL1_LINK_RATE_2700 0
8742 #define DPLL_CTRL1_LINK_RATE_1350 1
8743 #define DPLL_CTRL1_LINK_RATE_810 2
8744 #define DPLL_CTRL1_LINK_RATE_1620 3
8745 #define DPLL_CTRL1_LINK_RATE_1080 4
8746 #define DPLL_CTRL1_LINK_RATE_2160 5
8749 #define DPLL_CTRL2 _MMIO(0x6C05C)
8750 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
8751 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
8752 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
8753 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1))
8754 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
8757 #define DPLL_STATUS _MMIO(0x6C060)
8758 #define DPLL_LOCK(id) (1<<((id)*8))
8761 #define _DPLL1_CFGCR1 0x6C040
8762 #define _DPLL2_CFGCR1 0x6C048
8763 #define _DPLL3_CFGCR1 0x6C050
8764 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
8765 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
8766 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
8767 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
8769 #define _DPLL1_CFGCR2 0x6C044
8770 #define _DPLL2_CFGCR2 0x6C04C
8771 #define _DPLL3_CFGCR2 0x6C054
8772 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
8773 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
8774 #define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
8775 #define DPLL_CFGCR2_KDIV_MASK (3<<5)
8776 #define DPLL_CFGCR2_KDIV(x) ((x)<<5)
8777 #define DPLL_CFGCR2_KDIV_5 (0<<5)
8778 #define DPLL_CFGCR2_KDIV_2 (1<<5)
8779 #define DPLL_CFGCR2_KDIV_3 (2<<5)
8780 #define DPLL_CFGCR2_KDIV_1 (3<<5)
8781 #define DPLL_CFGCR2_PDIV_MASK (7<<2)
8782 #define DPLL_CFGCR2_PDIV(x) ((x)<<2)
8783 #define DPLL_CFGCR2_PDIV_1 (0<<2)
8784 #define DPLL_CFGCR2_PDIV_2 (1<<2)
8785 #define DPLL_CFGCR2_PDIV_3 (2<<2)
8786 #define DPLL_CFGCR2_PDIV_7 (4<<2)
8787 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
8789 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
8790 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
8795 #define DPCLKA_CFGCR0 _MMIO(0x6C200)
8796 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
8798 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
8800 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
8801 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
8804 #define DPLL0_ENABLE 0x46010
8805 #define DPLL1_ENABLE 0x46014
8806 #define PLL_ENABLE (1 << 31)
8807 #define PLL_LOCK (1 << 30)
8808 #define PLL_POWER_ENABLE (1 << 27)
8809 #define PLL_POWER_STATE (1 << 26)
8810 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
8812 #define _CNL_DPLL0_CFGCR0 0x6C000
8813 #define _CNL_DPLL1_CFGCR0 0x6C080
8814 #define DPLL_CFGCR0_HDMI_MODE (1 << 30)
8815 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
8816 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
8817 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
8818 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
8819 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
8820 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
8821 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
8822 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
8823 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
8824 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
8825 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
8826 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
8827 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
8828 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
8829 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
8831 #define _CNL_DPLL0_CFGCR1 0x6C004
8832 #define _CNL_DPLL1_CFGCR1 0x6C084
8833 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
8834 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
8835 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
8836 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
8837 #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
8838 #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
8839 #define DPLL_CFGCR1_KDIV_1 (1 << 6)
8840 #define DPLL_CFGCR1_KDIV_2 (2 << 6)
8841 #define DPLL_CFGCR1_KDIV_4 (4 << 6)
8842 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
8843 #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
8844 #define DPLL_CFGCR1_PDIV_2 (1 << 2)
8845 #define DPLL_CFGCR1_PDIV_3 (2 << 2)
8846 #define DPLL_CFGCR1_PDIV_5 (4 << 2)
8847 #define DPLL_CFGCR1_PDIV_7 (8 << 2)
8848 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
8849 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
8851 /* BXT display engine PLL */
8852 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
8853 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
8854 #define BXT_DE_PLL_RATIO_MASK 0xff
8856 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
8857 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
8858 #define BXT_DE_PLL_LOCK (1 << 30)
8859 #define CNL_CDCLK_PLL_RATIO(x) (x)
8860 #define CNL_CDCLK_PLL_RATIO_MASK 0xff
8863 #define DC_STATE_EN _MMIO(0x45504)
8864 #define DC_STATE_DISABLE 0
8865 #define DC_STATE_EN_UPTO_DC5 (1<<0)
8866 #define DC_STATE_EN_DC9 (1<<3)
8867 #define DC_STATE_EN_UPTO_DC6 (2<<0)
8868 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
8870 #define DC_STATE_DEBUG _MMIO(0x45520)
8871 #define DC_STATE_DEBUG_MASK_CORES (1<<0)
8872 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
8874 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
8875 * since on HSW we can't write to it using I915_WRITE. */
8876 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
8877 #define D_COMP_BDW _MMIO(0x138144)
8878 #define D_COMP_RCOMP_IN_PROGRESS (1<<9)
8879 #define D_COMP_COMP_FORCE (1<<8)
8880 #define D_COMP_COMP_DISABLE (1<<0)
8882 /* Pipe WM_LINETIME - watermark line time */
8883 #define _PIPE_WM_LINETIME_A 0x45270
8884 #define _PIPE_WM_LINETIME_B 0x45274
8885 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
8886 #define PIPE_WM_LINETIME_MASK (0x1ff)
8887 #define PIPE_WM_LINETIME_TIME(x) ((x))
8888 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
8889 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
8892 #define SFUSE_STRAP _MMIO(0xc2014)
8893 #define SFUSE_STRAP_FUSE_LOCK (1<<13)
8894 #define SFUSE_STRAP_RAW_FREQUENCY (1<<8)
8895 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
8896 #define SFUSE_STRAP_CRT_DISABLED (1<<6)
8897 #define SFUSE_STRAP_DDIF_DETECTED (1<<3)
8898 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
8899 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
8900 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
8902 #define WM_MISC _MMIO(0x45260)
8903 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
8905 #define WM_DBG _MMIO(0x45280)
8906 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
8907 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
8908 #define WM_DBG_DISALLOW_SPRITE (1<<2)
8911 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
8912 #define _PIPE_A_CSC_COEFF_BY 0x49014
8913 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
8914 #define _PIPE_A_CSC_COEFF_BU 0x4901c
8915 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
8916 #define _PIPE_A_CSC_COEFF_BV 0x49024
8917 #define _PIPE_A_CSC_MODE 0x49028
8918 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
8919 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
8920 #define CSC_MODE_YUV_TO_RGB (1 << 0)
8921 #define _PIPE_A_CSC_PREOFF_HI 0x49030
8922 #define _PIPE_A_CSC_PREOFF_ME 0x49034
8923 #define _PIPE_A_CSC_PREOFF_LO 0x49038
8924 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
8925 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
8926 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
8928 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
8929 #define _PIPE_B_CSC_COEFF_BY 0x49114
8930 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
8931 #define _PIPE_B_CSC_COEFF_BU 0x4911c
8932 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
8933 #define _PIPE_B_CSC_COEFF_BV 0x49124
8934 #define _PIPE_B_CSC_MODE 0x49128
8935 #define _PIPE_B_CSC_PREOFF_HI 0x49130
8936 #define _PIPE_B_CSC_PREOFF_ME 0x49134
8937 #define _PIPE_B_CSC_PREOFF_LO 0x49138
8938 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
8939 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
8940 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
8942 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
8943 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
8944 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
8945 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
8946 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
8947 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
8948 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
8949 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
8950 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
8951 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
8952 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
8953 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
8954 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
8956 /* pipe degamma/gamma LUTs on IVB+ */
8957 #define _PAL_PREC_INDEX_A 0x4A400
8958 #define _PAL_PREC_INDEX_B 0x4AC00
8959 #define _PAL_PREC_INDEX_C 0x4B400
8960 #define PAL_PREC_10_12_BIT (0 << 31)
8961 #define PAL_PREC_SPLIT_MODE (1 << 31)
8962 #define PAL_PREC_AUTO_INCREMENT (1 << 15)
8963 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
8964 #define _PAL_PREC_DATA_A 0x4A404
8965 #define _PAL_PREC_DATA_B 0x4AC04
8966 #define _PAL_PREC_DATA_C 0x4B404
8967 #define _PAL_PREC_GC_MAX_A 0x4A410
8968 #define _PAL_PREC_GC_MAX_B 0x4AC10
8969 #define _PAL_PREC_GC_MAX_C 0x4B410
8970 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
8971 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
8972 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
8973 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
8974 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
8975 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
8977 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
8978 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
8979 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
8980 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
8982 #define _PRE_CSC_GAMC_INDEX_A 0x4A484
8983 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
8984 #define _PRE_CSC_GAMC_INDEX_C 0x4B484
8985 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
8986 #define _PRE_CSC_GAMC_DATA_A 0x4A488
8987 #define _PRE_CSC_GAMC_DATA_B 0x4AC88
8988 #define _PRE_CSC_GAMC_DATA_C 0x4B488
8990 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
8991 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
8993 /* pipe CSC & degamma/gamma LUTs on CHV */
8994 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
8995 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
8996 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
8997 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
8998 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
8999 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
9000 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
9001 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
9002 #define CGM_PIPE_MODE_GAMMA (1 << 2)
9003 #define CGM_PIPE_MODE_CSC (1 << 1)
9004 #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
9006 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
9007 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
9008 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
9009 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
9010 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
9011 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
9012 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
9013 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
9015 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
9016 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
9017 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
9018 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
9019 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
9020 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
9021 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
9022 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
9024 /* MIPI DSI registers */
9026 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
9027 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
9029 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
9030 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
9031 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
9032 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
9034 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
9035 #define GEN4_TIMESTAMP _MMIO(0x2358)
9036 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
9037 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
9039 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
9040 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
9041 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
9042 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
9043 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
9045 #define _PIPE_FRMTMSTMP_A 0x70048
9046 #define PIPE_FRMTMSTMP(pipe) \
9047 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
9049 /* BXT MIPI clock controls */
9050 #define BXT_MAX_VAR_OUTPUT_KHZ 39500
9052 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
9053 #define BXT_MIPI1_DIV_SHIFT 26
9054 #define BXT_MIPI2_DIV_SHIFT 10
9055 #define BXT_MIPI_DIV_SHIFT(port) \
9056 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
9057 BXT_MIPI2_DIV_SHIFT)
9059 /* TX control divider to select actual TX clock output from (8x/var) */
9060 #define BXT_MIPI1_TX_ESCLK_SHIFT 26
9061 #define BXT_MIPI2_TX_ESCLK_SHIFT 10
9062 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
9063 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
9064 BXT_MIPI2_TX_ESCLK_SHIFT)
9065 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
9066 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
9067 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
9068 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
9069 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
9070 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
9071 ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
9072 /* RX upper control divider to select actual RX clock output from 8x */
9073 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
9074 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
9075 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
9076 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
9077 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
9078 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
9079 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
9080 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
9081 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
9082 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
9083 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
9084 ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
9085 /* 8/3X divider to select the actual 8/3X clock output from 8x */
9086 #define BXT_MIPI1_8X_BY3_SHIFT 19
9087 #define BXT_MIPI2_8X_BY3_SHIFT 3
9088 #define BXT_MIPI_8X_BY3_SHIFT(port) \
9089 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
9090 BXT_MIPI2_8X_BY3_SHIFT)
9091 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
9092 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
9093 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
9094 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
9095 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
9096 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
9097 ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
9098 /* RX lower control divider to select actual RX clock output from 8x */
9099 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
9100 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
9101 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
9102 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
9103 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
9104 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
9105 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
9106 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
9107 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
9108 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
9109 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
9110 ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
9112 #define RX_DIVIDER_BIT_1_2 0x3
9113 #define RX_DIVIDER_BIT_3_4 0xC
9115 /* BXT MIPI mode configure */
9116 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
9117 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
9118 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
9119 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
9121 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
9122 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
9123 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
9124 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
9126 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
9127 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
9128 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
9129 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
9131 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
9132 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
9133 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9134 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9135 #define BXT_DSIC_16X_BY1 (0 << 10)
9136 #define BXT_DSIC_16X_BY2 (1 << 10)
9137 #define BXT_DSIC_16X_BY3 (2 << 10)
9138 #define BXT_DSIC_16X_BY4 (3 << 10)
9139 #define BXT_DSIC_16X_MASK (3 << 10)
9140 #define BXT_DSIA_16X_BY1 (0 << 8)
9141 #define BXT_DSIA_16X_BY2 (1 << 8)
9142 #define BXT_DSIA_16X_BY3 (2 << 8)
9143 #define BXT_DSIA_16X_BY4 (3 << 8)
9144 #define BXT_DSIA_16X_MASK (3 << 8)
9145 #define BXT_DSI_FREQ_SEL_SHIFT 8
9146 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
9148 #define BXT_DSI_PLL_RATIO_MAX 0x7D
9149 #define BXT_DSI_PLL_RATIO_MIN 0x22
9150 #define GLK_DSI_PLL_RATIO_MAX 0x6F
9151 #define GLK_DSI_PLL_RATIO_MIN 0x22
9152 #define BXT_DSI_PLL_RATIO_MASK 0xFF
9153 #define BXT_REF_CLOCK_KHZ 19200
9155 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
9156 #define BXT_DSI_PLL_DO_ENABLE (1 << 31)
9157 #define BXT_DSI_PLL_LOCKED (1 << 30)
9159 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
9160 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
9161 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
9163 /* BXT port control */
9164 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0
9165 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
9166 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
9168 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
9169 #define STAP_SELECT (1 << 0)
9171 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
9172 #define HS_IO_CTRL_SELECT (1 << 0)
9174 #define DPI_ENABLE (1 << 31) /* A + C */
9175 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
9176 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
9177 #define DUAL_LINK_MODE_SHIFT 26
9178 #define DUAL_LINK_MODE_MASK (1 << 26)
9179 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
9180 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
9181 #define DITHERING_ENABLE (1 << 25) /* A + C */
9182 #define FLOPPED_HSTX (1 << 23)
9183 #define DE_INVERT (1 << 19) /* XXX */
9184 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
9185 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
9186 #define AFE_LATCHOUT (1 << 17)
9187 #define LP_OUTPUT_HOLD (1 << 16)
9188 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
9189 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
9190 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
9191 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
9193 #define CSB_MASK (3 << 9)
9194 #define CSB_20MHZ (0 << 9)
9195 #define CSB_10MHZ (1 << 9)
9196 #define CSB_40MHZ (2 << 9)
9197 #define BANDGAP_MASK (1 << 8)
9198 #define BANDGAP_PNW_CIRCUIT (0 << 8)
9199 #define BANDGAP_LNC_CIRCUIT (1 << 8)
9200 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
9201 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
9202 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
9203 #define TEARING_EFFECT_SHIFT 2 /* A + C */
9204 #define TEARING_EFFECT_MASK (3 << 2)
9205 #define TEARING_EFFECT_OFF (0 << 2)
9206 #define TEARING_EFFECT_DSI (1 << 2)
9207 #define TEARING_EFFECT_GPIO (2 << 2)
9208 #define LANE_CONFIGURATION_SHIFT 0
9209 #define LANE_CONFIGURATION_MASK (3 << 0)
9210 #define LANE_CONFIGURATION_4LANE (0 << 0)
9211 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
9212 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
9214 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
9215 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
9216 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
9217 #define TEARING_EFFECT_DELAY_SHIFT 0
9218 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
9220 /* XXX: all bits reserved */
9221 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
9223 /* MIPI DSI Controller and D-PHY registers */
9225 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
9226 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
9227 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
9228 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
9229 #define ULPS_STATE_MASK (3 << 1)
9230 #define ULPS_STATE_ENTER (2 << 1)
9231 #define ULPS_STATE_EXIT (1 << 1)
9232 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
9233 #define DEVICE_READY (1 << 0)
9235 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
9236 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
9237 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
9238 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
9239 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
9240 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
9241 #define TEARING_EFFECT (1 << 31)
9242 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
9243 #define GEN_READ_DATA_AVAIL (1 << 29)
9244 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
9245 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
9246 #define RX_PROT_VIOLATION (1 << 26)
9247 #define RX_INVALID_TX_LENGTH (1 << 25)
9248 #define ACK_WITH_NO_ERROR (1 << 24)
9249 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
9250 #define LP_RX_TIMEOUT (1 << 22)
9251 #define HS_TX_TIMEOUT (1 << 21)
9252 #define DPI_FIFO_UNDERRUN (1 << 20)
9253 #define LOW_CONTENTION (1 << 19)
9254 #define HIGH_CONTENTION (1 << 18)
9255 #define TXDSI_VC_ID_INVALID (1 << 17)
9256 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
9257 #define TXCHECKSUM_ERROR (1 << 15)
9258 #define TXECC_MULTIBIT_ERROR (1 << 14)
9259 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
9260 #define TXFALSE_CONTROL_ERROR (1 << 12)
9261 #define RXDSI_VC_ID_INVALID (1 << 11)
9262 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
9263 #define RXCHECKSUM_ERROR (1 << 9)
9264 #define RXECC_MULTIBIT_ERROR (1 << 8)
9265 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
9266 #define RXFALSE_CONTROL_ERROR (1 << 6)
9267 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
9268 #define RX_LP_TX_SYNC_ERROR (1 << 4)
9269 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
9270 #define RXEOT_SYNC_ERROR (1 << 2)
9271 #define RXSOT_SYNC_ERROR (1 << 1)
9272 #define RXSOT_ERROR (1 << 0)
9274 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
9275 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
9276 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
9277 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
9278 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
9279 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
9280 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
9281 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
9282 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
9283 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
9284 #define VID_MODE_FORMAT_MASK (0xf << 7)
9285 #define VID_MODE_NOT_SUPPORTED (0 << 7)
9286 #define VID_MODE_FORMAT_RGB565 (1 << 7)
9287 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
9288 #define VID_MODE_FORMAT_RGB666 (3 << 7)
9289 #define VID_MODE_FORMAT_RGB888 (4 << 7)
9290 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
9291 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
9292 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
9293 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
9294 #define DATA_LANES_PRG_REG_SHIFT 0
9295 #define DATA_LANES_PRG_REG_MASK (7 << 0)
9297 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
9298 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
9299 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
9300 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
9302 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
9303 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
9304 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
9305 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
9307 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
9308 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
9309 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
9310 #define TURN_AROUND_TIMEOUT_MASK 0x3f
9312 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
9313 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
9314 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
9315 #define DEVICE_RESET_TIMER_MASK 0xffff
9317 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
9318 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
9319 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
9320 #define VERTICAL_ADDRESS_SHIFT 16
9321 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
9322 #define HORIZONTAL_ADDRESS_SHIFT 0
9323 #define HORIZONTAL_ADDRESS_MASK 0xffff
9325 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
9326 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
9327 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
9328 #define DBI_FIFO_EMPTY_HALF (0 << 0)
9329 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
9330 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
9332 /* regs below are bits 15:0 */
9333 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
9334 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
9335 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
9337 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
9338 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
9339 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
9341 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
9342 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
9343 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
9345 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
9346 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
9347 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
9349 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
9350 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
9351 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
9353 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
9354 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
9355 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
9357 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
9358 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
9359 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
9361 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
9362 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
9363 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
9365 /* regs above are bits 15:0 */
9367 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
9368 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
9369 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
9370 #define DPI_LP_MODE (1 << 6)
9371 #define BACKLIGHT_OFF (1 << 5)
9372 #define BACKLIGHT_ON (1 << 4)
9373 #define COLOR_MODE_OFF (1 << 3)
9374 #define COLOR_MODE_ON (1 << 2)
9375 #define TURN_ON (1 << 1)
9376 #define SHUTDOWN (1 << 0)
9378 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
9379 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
9380 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
9381 #define COMMAND_BYTE_SHIFT 0
9382 #define COMMAND_BYTE_MASK (0x3f << 0)
9384 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
9385 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
9386 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
9387 #define MASTER_INIT_TIMER_SHIFT 0
9388 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
9390 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
9391 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
9392 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
9393 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
9394 #define MAX_RETURN_PKT_SIZE_SHIFT 0
9395 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
9397 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
9398 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
9399 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
9400 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
9401 #define DISABLE_VIDEO_BTA (1 << 3)
9402 #define IP_TG_CONFIG (1 << 2)
9403 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
9404 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
9405 #define VIDEO_MODE_BURST (3 << 0)
9407 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
9408 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
9409 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
9410 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
9411 #define BXT_DPHY_DEFEATURE_EN (1 << 8)
9412 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
9413 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
9414 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
9415 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
9416 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
9417 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
9418 #define CLOCKSTOP (1 << 1)
9419 #define EOT_DISABLE (1 << 0)
9421 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
9422 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
9423 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
9424 #define LP_BYTECLK_SHIFT 0
9425 #define LP_BYTECLK_MASK (0xffff << 0)
9427 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
9428 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
9429 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
9431 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
9432 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
9433 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
9436 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
9437 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
9438 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
9441 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
9442 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
9443 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
9445 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
9446 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
9447 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
9448 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
9449 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
9450 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
9451 #define LONG_PACKET_WORD_COUNT_SHIFT 8
9452 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
9453 #define SHORT_PACKET_PARAM_SHIFT 8
9454 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
9455 #define VIRTUAL_CHANNEL_SHIFT 6
9456 #define VIRTUAL_CHANNEL_MASK (3 << 6)
9457 #define DATA_TYPE_SHIFT 0
9458 #define DATA_TYPE_MASK (0x3f << 0)
9459 /* data type values, see include/video/mipi_display.h */
9461 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
9462 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
9463 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
9464 #define DPI_FIFO_EMPTY (1 << 28)
9465 #define DBI_FIFO_EMPTY (1 << 27)
9466 #define LP_CTRL_FIFO_EMPTY (1 << 26)
9467 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
9468 #define LP_CTRL_FIFO_FULL (1 << 24)
9469 #define HS_CTRL_FIFO_EMPTY (1 << 18)
9470 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
9471 #define HS_CTRL_FIFO_FULL (1 << 16)
9472 #define LP_DATA_FIFO_EMPTY (1 << 10)
9473 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
9474 #define LP_DATA_FIFO_FULL (1 << 8)
9475 #define HS_DATA_FIFO_EMPTY (1 << 2)
9476 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
9477 #define HS_DATA_FIFO_FULL (1 << 0)
9479 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
9480 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
9481 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
9482 #define DBI_HS_LP_MODE_MASK (1 << 0)
9483 #define DBI_LP_MODE (1 << 0)
9484 #define DBI_HS_MODE (0 << 0)
9486 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
9487 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
9488 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
9489 #define EXIT_ZERO_COUNT_SHIFT 24
9490 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
9491 #define TRAIL_COUNT_SHIFT 16
9492 #define TRAIL_COUNT_MASK (0x1f << 16)
9493 #define CLK_ZERO_COUNT_SHIFT 8
9494 #define CLK_ZERO_COUNT_MASK (0xff << 8)
9495 #define PREPARE_COUNT_SHIFT 0
9496 #define PREPARE_COUNT_MASK (0x3f << 0)
9499 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
9500 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
9501 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
9503 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
9504 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
9505 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
9506 #define LP_HS_SSW_CNT_SHIFT 16
9507 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
9508 #define HS_LP_PWR_SW_CNT_SHIFT 0
9509 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
9511 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
9512 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
9513 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
9514 #define STOP_STATE_STALL_COUNTER_SHIFT 0
9515 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
9517 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
9518 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
9519 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
9520 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
9521 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
9522 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
9523 #define RX_CONTENTION_DETECTED (1 << 0)
9525 /* XXX: only pipe A ?!? */
9526 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
9527 #define DBI_TYPEC_ENABLE (1 << 31)
9528 #define DBI_TYPEC_WIP (1 << 30)
9529 #define DBI_TYPEC_OPTION_SHIFT 28
9530 #define DBI_TYPEC_OPTION_MASK (3 << 28)
9531 #define DBI_TYPEC_FREQ_SHIFT 24
9532 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
9533 #define DBI_TYPEC_OVERRIDE (1 << 8)
9534 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
9535 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
9538 /* MIPI adapter registers */
9540 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
9541 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
9542 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
9543 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
9544 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
9545 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
9546 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
9547 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
9548 #define READ_REQUEST_PRIORITY_SHIFT 3
9549 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
9550 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
9551 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
9552 #define RGB_FLIP_TO_BGR (1 << 2)
9554 #define BXT_PIPE_SELECT_SHIFT 7
9555 #define BXT_PIPE_SELECT_MASK (7 << 7)
9556 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
9557 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
9558 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
9559 #define GLK_MIPIIO_RESET_RELEASED (1 << 28)
9560 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
9561 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
9562 #define GLK_LP_WAKE (1 << 22)
9563 #define GLK_LP11_LOW_PWR_MODE (1 << 21)
9564 #define GLK_LP00_LOW_PWR_MODE (1 << 20)
9565 #define GLK_FIREWALL_ENABLE (1 << 16)
9566 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
9567 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
9568 #define BXT_DSC_ENABLE (1 << 3)
9569 #define BXT_RGB_FLIP (1 << 2)
9570 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
9571 #define GLK_MIPIIO_ENABLE (1 << 0)
9573 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
9574 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
9575 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
9576 #define DATA_MEM_ADDRESS_SHIFT 5
9577 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
9578 #define DATA_VALID (1 << 0)
9580 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
9581 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
9582 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
9583 #define DATA_LENGTH_SHIFT 0
9584 #define DATA_LENGTH_MASK (0xfffff << 0)
9586 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
9587 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
9588 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
9589 #define COMMAND_MEM_ADDRESS_SHIFT 5
9590 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
9591 #define AUTO_PWG_ENABLE (1 << 2)
9592 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
9593 #define COMMAND_VALID (1 << 0)
9595 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
9596 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
9597 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
9598 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
9599 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
9601 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
9602 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
9603 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
9605 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
9606 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
9607 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
9608 #define READ_DATA_VALID(n) (1 << (n))
9610 /* For UMS only (deprecated): */
9611 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
9612 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
9614 /* MOCS (Memory Object Control State) registers */
9615 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
9617 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
9618 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
9619 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
9620 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
9621 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
9624 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
9625 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
9626 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
9627 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
9628 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
9630 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
9631 #define MMCD_PCLA (1 << 31)
9632 #define MMCD_HOTSPOT_EN (1 << 27)
9634 #endif /* _I915_REG_H_ */