2 * SPDX-License-Identifier: MIT
4 * Copyright © 2017-2018 Intel Corporation
7 #include <linux/pm_runtime.h>
9 #include "gt/intel_engine.h"
10 #include "gt/intel_engine_pm.h"
11 #include "gt/intel_engine_regs.h"
12 #include "gt/intel_engine_user.h"
13 #include "gt/intel_gt.h"
14 #include "gt/intel_gt_pm.h"
15 #include "gt/intel_gt_regs.h"
16 #include "gt/intel_rc6.h"
17 #include "gt/intel_rps.h"
22 /* Frequency for the sampling timer for events which need it. */
24 #define PERIOD max_t(u64, 10000, NSEC_PER_SEC / FREQUENCY)
26 #define ENGINE_SAMPLE_MASK \
27 (BIT(I915_SAMPLE_BUSY) | \
28 BIT(I915_SAMPLE_WAIT) | \
29 BIT(I915_SAMPLE_SEMA))
31 static cpumask_t i915_pmu_cpumask;
32 static unsigned int i915_pmu_target_cpu = -1;
34 static u8 engine_config_sample(u64 config)
36 return config & I915_PMU_SAMPLE_MASK;
39 static u8 engine_event_sample(struct perf_event *event)
41 return engine_config_sample(event->attr.config);
44 static u8 engine_event_class(struct perf_event *event)
46 return (event->attr.config >> I915_PMU_CLASS_SHIFT) & 0xff;
49 static u8 engine_event_instance(struct perf_event *event)
51 return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
54 static bool is_engine_config(const u64 config)
56 return config < __I915_PMU_OTHER(0);
59 static unsigned int config_gt_id(const u64 config)
61 return config >> __I915_PMU_GT_SHIFT;
64 static u64 config_counter(const u64 config)
66 return config & ~(~0ULL << __I915_PMU_GT_SHIFT);
69 static unsigned int other_bit(const u64 config)
73 switch (config_counter(config)) {
74 case I915_PMU_ACTUAL_FREQUENCY:
75 val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
77 case I915_PMU_REQUESTED_FREQUENCY:
78 val = __I915_PMU_REQUESTED_FREQUENCY_ENABLED;
80 case I915_PMU_RC6_RESIDENCY:
81 val = __I915_PMU_RC6_RESIDENCY_ENABLED;
85 * Events that do not require sampling, or tracking state
86 * transitions between enabled and disabled can be ignored.
91 return I915_ENGINE_SAMPLE_COUNT +
92 config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
96 static unsigned int config_bit(const u64 config)
98 if (is_engine_config(config))
99 return engine_config_sample(config);
101 return other_bit(config);
104 static u32 config_mask(const u64 config)
106 unsigned int bit = config_bit(config);
108 if (__builtin_constant_p(config))
110 BITS_PER_TYPE(typeof_member(struct i915_pmu,
114 BITS_PER_TYPE(typeof_member(struct i915_pmu,
117 return BIT(config_bit(config));
120 static bool is_engine_event(struct perf_event *event)
122 return is_engine_config(event->attr.config);
125 static unsigned int event_bit(struct perf_event *event)
127 return config_bit(event->attr.config);
130 static u32 frequency_enabled_mask(void)
135 for (i = 0; i < I915_PMU_MAX_GT; i++)
136 mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
137 config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
142 static bool pmu_needs_timer(struct i915_pmu *pmu)
144 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
148 * Only some counters need the sampling timer.
150 * We start with a bitmask of all currently enabled events.
152 enable = pmu->enable;
155 * Mask out all the ones which do not need the timer, or in
156 * other words keep all the ones that could need the timer.
158 enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;
161 * Also there is software busyness tracking available we do not
162 * need the timer for I915_SAMPLE_BUSY counter.
164 if (i915->caps.scheduler & I915_SCHEDULER_CAP_ENGINE_BUSY_STATS)
165 enable &= ~BIT(I915_SAMPLE_BUSY);
168 * If some bits remain it means we need the sampling timer running.
173 static u64 __get_rc6(struct intel_gt *gt)
175 struct drm_i915_private *i915 = gt->i915;
178 val = intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6);
181 val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6p);
184 val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6pp);
189 static inline s64 ktime_since_raw(const ktime_t kt)
191 return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));
194 static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample)
196 return pmu->sample[gt_id][sample].cur;
200 store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
202 pmu->sample[gt_id][sample].cur = val;
206 add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val, u32 mul)
208 pmu->sample[gt_id][sample].cur += mul_u32_u32(val, mul);
211 static u64 get_rc6(struct intel_gt *gt)
213 struct drm_i915_private *i915 = gt->i915;
214 const unsigned int gt_id = gt->info.id;
215 struct i915_pmu *pmu = &i915->pmu;
220 if (intel_gt_pm_get_if_awake(gt)) {
222 intel_gt_pm_put_async(gt);
226 spin_lock_irqsave(&pmu->lock, flags);
229 store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
232 * We think we are runtime suspended.
234 * Report the delta from when the device was suspended to now,
235 * on top of the last known real value, as the approximated RC6
238 val = ktime_since_raw(pmu->sleep_last[gt_id]);
239 val += read_sample(pmu, gt_id, __I915_SAMPLE_RC6);
242 if (val < read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED))
243 val = read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED);
245 store_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED, val);
247 spin_unlock_irqrestore(&pmu->lock, flags);
252 static void init_rc6(struct i915_pmu *pmu)
254 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
258 for_each_gt(gt, i915, i) {
259 intel_wakeref_t wakeref;
261 with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
262 u64 val = __get_rc6(gt);
264 store_sample(pmu, i, __I915_SAMPLE_RC6, val);
265 store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED,
267 pmu->sleep_last[i] = ktime_get_raw();
272 static void park_rc6(struct intel_gt *gt)
274 struct i915_pmu *pmu = >->i915->pmu;
276 store_sample(pmu, gt->info.id, __I915_SAMPLE_RC6, __get_rc6(gt));
277 pmu->sleep_last[gt->info.id] = ktime_get_raw();
280 static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
282 if (!pmu->timer_enabled && pmu_needs_timer(pmu)) {
283 pmu->timer_enabled = true;
284 pmu->timer_last = ktime_get();
285 hrtimer_start_range_ns(&pmu->timer,
286 ns_to_ktime(PERIOD), 0,
287 HRTIMER_MODE_REL_PINNED);
291 void i915_pmu_gt_parked(struct intel_gt *gt)
293 struct i915_pmu *pmu = >->i915->pmu;
295 if (!pmu->base.event_init)
298 spin_lock_irq(&pmu->lock);
303 * Signal sampling timer to stop if only engine events are enabled and
306 pmu->unparked &= ~BIT(gt->info.id);
307 if (pmu->unparked == 0)
308 pmu->timer_enabled = false;
310 spin_unlock_irq(&pmu->lock);
313 void i915_pmu_gt_unparked(struct intel_gt *gt)
315 struct i915_pmu *pmu = >->i915->pmu;
317 if (!pmu->base.event_init)
320 spin_lock_irq(&pmu->lock);
323 * Re-enable sampling timer when GPU goes active.
325 if (pmu->unparked == 0)
326 __i915_pmu_maybe_start_timer(pmu);
328 pmu->unparked |= BIT(gt->info.id);
330 spin_unlock_irq(&pmu->lock);
334 add_sample(struct i915_pmu_sample *sample, u32 val)
339 static bool exclusive_mmio_access(const struct drm_i915_private *i915)
342 * We have to avoid concurrent mmio cache line access on gen7 or
343 * risk a machine hang. For a fun history lesson dig out the old
344 * userspace intel_gpu_top and run it on Ivybridge or Haswell!
346 return GRAPHICS_VER(i915) == 7;
349 static void engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)
351 struct intel_engine_pmu *pmu = &engine->pmu;
355 val = ENGINE_READ_FW(engine, RING_CTL);
356 if (val == 0) /* powerwell off => engine idle */
360 add_sample(&pmu->sample[I915_SAMPLE_WAIT], period_ns);
361 if (val & RING_WAIT_SEMAPHORE)
362 add_sample(&pmu->sample[I915_SAMPLE_SEMA], period_ns);
364 /* No need to sample when busy stats are supported. */
365 if (intel_engine_supports_stats(engine))
369 * While waiting on a semaphore or event, MI_MODE reports the
370 * ring as idle. However, previously using the seqno, and with
371 * execlists sampling, we account for the ring waiting as the
372 * engine being busy. Therefore, we record the sample as being
373 * busy if either waiting or !idle.
375 busy = val & (RING_WAIT_SEMAPHORE | RING_WAIT);
377 val = ENGINE_READ_FW(engine, RING_MI_MODE);
378 busy = !(val & MODE_IDLE);
381 add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns);
385 engines_sample(struct intel_gt *gt, unsigned int period_ns)
387 struct drm_i915_private *i915 = gt->i915;
388 struct intel_engine_cs *engine;
389 enum intel_engine_id id;
392 if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
395 if (!intel_gt_pm_is_awake(gt))
398 for_each_engine(engine, gt, id) {
399 if (!engine->pmu.enable)
402 if (!intel_engine_pm_get_if_awake(engine))
405 if (exclusive_mmio_access(i915)) {
406 spin_lock_irqsave(&engine->uncore->lock, flags);
407 engine_sample(engine, period_ns);
408 spin_unlock_irqrestore(&engine->uncore->lock, flags);
410 engine_sample(engine, period_ns);
413 intel_engine_pm_put_async(engine);
418 frequency_sampling_enabled(struct i915_pmu *pmu, unsigned int gt)
421 (config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt)) |
422 config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt)));
426 frequency_sample(struct intel_gt *gt, unsigned int period_ns)
428 struct drm_i915_private *i915 = gt->i915;
429 const unsigned int gt_id = gt->info.id;
430 struct i915_pmu *pmu = &i915->pmu;
431 struct intel_rps *rps = >->rps;
433 if (!frequency_sampling_enabled(pmu, gt_id))
436 /* Report 0/0 (actual/requested) frequency while parked. */
437 if (!intel_gt_pm_get_if_awake(gt))
440 if (pmu->enable & config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt_id))) {
444 * We take a quick peek here without using forcewake
445 * so that we don't perturb the system under observation
446 * (forcewake => !rc6 => increased power use). We expect
447 * that if the read fails because it is outside of the
448 * mmio power well, then it will return 0 -- in which
449 * case we assume the system is running at the intended
450 * frequency. Fortunately, the read should rarely fail!
452 val = intel_rps_read_actual_frequency_fw(rps);
454 val = intel_gpu_freq(rps, rps->cur_freq);
456 add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_ACT,
457 val, period_ns / 1000);
460 if (pmu->enable & config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt_id))) {
461 add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_REQ,
462 intel_rps_get_requested_frequency(rps),
466 intel_gt_pm_put_async(gt);
469 static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer)
471 struct drm_i915_private *i915 =
472 container_of(hrtimer, struct drm_i915_private, pmu.timer);
473 struct i915_pmu *pmu = &i915->pmu;
474 unsigned int period_ns;
479 if (!READ_ONCE(pmu->timer_enabled))
480 return HRTIMER_NORESTART;
483 period_ns = ktime_to_ns(ktime_sub(now, pmu->timer_last));
484 pmu->timer_last = now;
487 * Strictly speaking the passed in period may not be 100% accurate for
488 * all internal calculation, since some amount of time can be spent on
489 * grabbing the forcewake. However the potential error from timer call-
490 * back delay greatly dominates this so we keep it simple.
493 for_each_gt(gt, i915, i) {
494 if (!(pmu->unparked & BIT(i)))
497 engines_sample(gt, period_ns);
498 frequency_sample(gt, period_ns);
501 hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
503 return HRTIMER_RESTART;
506 static void i915_pmu_event_destroy(struct perf_event *event)
508 struct drm_i915_private *i915 =
509 container_of(event->pmu, typeof(*i915), pmu.base);
511 drm_WARN_ON(&i915->drm, event->parent);
513 drm_dev_put(&i915->drm);
517 engine_event_status(struct intel_engine_cs *engine,
518 enum drm_i915_pmu_engine_sample sample)
521 case I915_SAMPLE_BUSY:
522 case I915_SAMPLE_WAIT:
524 case I915_SAMPLE_SEMA:
525 if (GRAPHICS_VER(engine->i915) < 6)
536 config_status(struct drm_i915_private *i915, u64 config)
538 struct intel_gt *gt = to_gt(i915);
540 unsigned int gt_id = config_gt_id(config);
541 unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0;
543 if (gt_id > max_gt_id)
546 switch (config_counter(config)) {
547 case I915_PMU_ACTUAL_FREQUENCY:
548 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
549 /* Requires a mutex for sampling! */
552 case I915_PMU_REQUESTED_FREQUENCY:
553 if (GRAPHICS_VER(i915) < 6)
556 case I915_PMU_INTERRUPTS:
560 case I915_PMU_RC6_RESIDENCY:
561 if (!gt->rc6.supported)
564 case I915_PMU_SOFTWARE_GT_AWAKE_TIME:
573 static int engine_event_init(struct perf_event *event)
575 struct drm_i915_private *i915 =
576 container_of(event->pmu, typeof(*i915), pmu.base);
577 struct intel_engine_cs *engine;
579 engine = intel_engine_lookup_user(i915, engine_event_class(event),
580 engine_event_instance(event));
584 return engine_event_status(engine, engine_event_sample(event));
587 static int i915_pmu_event_init(struct perf_event *event)
589 struct drm_i915_private *i915 =
590 container_of(event->pmu, typeof(*i915), pmu.base);
591 struct i915_pmu *pmu = &i915->pmu;
597 if (event->attr.type != event->pmu->type)
600 /* unsupported modes and filters */
601 if (event->attr.sample_period) /* no sampling */
604 if (has_branch_stack(event))
610 /* only allow running on one cpu at a time */
611 if (!cpumask_test_cpu(event->cpu, &i915_pmu_cpumask))
614 if (is_engine_event(event))
615 ret = engine_event_init(event);
617 ret = config_status(i915, event->attr.config);
621 if (!event->parent) {
622 drm_dev_get(&i915->drm);
623 event->destroy = i915_pmu_event_destroy;
629 static u64 __i915_pmu_event_read(struct perf_event *event)
631 struct drm_i915_private *i915 =
632 container_of(event->pmu, typeof(*i915), pmu.base);
633 struct i915_pmu *pmu = &i915->pmu;
636 if (is_engine_event(event)) {
637 u8 sample = engine_event_sample(event);
638 struct intel_engine_cs *engine;
640 engine = intel_engine_lookup_user(i915,
641 engine_event_class(event),
642 engine_event_instance(event));
644 if (drm_WARN_ON_ONCE(&i915->drm, !engine)) {
646 } else if (sample == I915_SAMPLE_BUSY &&
647 intel_engine_supports_stats(engine)) {
650 val = ktime_to_ns(intel_engine_get_busy_time(engine,
653 val = engine->pmu.sample[sample].cur;
656 const unsigned int gt_id = config_gt_id(event->attr.config);
657 const u64 config = config_counter(event->attr.config);
660 case I915_PMU_ACTUAL_FREQUENCY:
662 div_u64(read_sample(pmu, gt_id,
663 __I915_SAMPLE_FREQ_ACT),
664 USEC_PER_SEC /* to MHz */);
666 case I915_PMU_REQUESTED_FREQUENCY:
668 div_u64(read_sample(pmu, gt_id,
669 __I915_SAMPLE_FREQ_REQ),
670 USEC_PER_SEC /* to MHz */);
672 case I915_PMU_INTERRUPTS:
673 val = READ_ONCE(pmu->irq_count);
675 case I915_PMU_RC6_RESIDENCY:
676 val = get_rc6(i915->gt[gt_id]);
678 case I915_PMU_SOFTWARE_GT_AWAKE_TIME:
679 val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915)));
687 static void i915_pmu_event_read(struct perf_event *event)
689 struct drm_i915_private *i915 =
690 container_of(event->pmu, typeof(*i915), pmu.base);
691 struct hw_perf_event *hwc = &event->hw;
692 struct i915_pmu *pmu = &i915->pmu;
696 event->hw.state = PERF_HES_STOPPED;
700 prev = local64_read(&hwc->prev_count);
701 new = __i915_pmu_event_read(event);
703 if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
706 local64_add(new - prev, &event->count);
709 static void i915_pmu_enable(struct perf_event *event)
711 struct drm_i915_private *i915 =
712 container_of(event->pmu, typeof(*i915), pmu.base);
713 const unsigned int bit = event_bit(event);
714 struct i915_pmu *pmu = &i915->pmu;
720 spin_lock_irqsave(&pmu->lock, flags);
723 * Update the bitmask of enabled events and increment
724 * the event reference counter.
726 BUILD_BUG_ON(ARRAY_SIZE(pmu->enable_count) != I915_PMU_MASK_BITS);
727 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
728 GEM_BUG_ON(pmu->enable_count[bit] == ~0);
730 pmu->enable |= BIT(bit);
731 pmu->enable_count[bit]++;
734 * Start the sampling timer if needed and not already enabled.
736 __i915_pmu_maybe_start_timer(pmu);
739 * For per-engine events the bitmask and reference counting
740 * is stored per engine.
742 if (is_engine_event(event)) {
743 u8 sample = engine_event_sample(event);
744 struct intel_engine_cs *engine;
746 engine = intel_engine_lookup_user(i915,
747 engine_event_class(event),
748 engine_event_instance(event));
750 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
751 I915_ENGINE_SAMPLE_COUNT);
752 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=
753 I915_ENGINE_SAMPLE_COUNT);
754 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
755 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
756 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
758 engine->pmu.enable |= BIT(sample);
759 engine->pmu.enable_count[sample]++;
762 spin_unlock_irqrestore(&pmu->lock, flags);
766 * Store the current counter value so we can report the correct delta
767 * for all listeners. Even when the event was already enabled and has
768 * an existing non-zero value.
770 local64_set(&event->hw.prev_count, __i915_pmu_event_read(event));
773 static void i915_pmu_disable(struct perf_event *event)
775 struct drm_i915_private *i915 =
776 container_of(event->pmu, typeof(*i915), pmu.base);
777 const unsigned int bit = event_bit(event);
778 struct i915_pmu *pmu = &i915->pmu;
784 spin_lock_irqsave(&pmu->lock, flags);
786 if (is_engine_event(event)) {
787 u8 sample = engine_event_sample(event);
788 struct intel_engine_cs *engine;
790 engine = intel_engine_lookup_user(i915,
791 engine_event_class(event),
792 engine_event_instance(event));
794 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
795 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
796 GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
799 * Decrement the reference count and clear the enabled
800 * bitmask when the last listener on an event goes away.
802 if (--engine->pmu.enable_count[sample] == 0)
803 engine->pmu.enable &= ~BIT(sample);
806 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
807 GEM_BUG_ON(pmu->enable_count[bit] == 0);
809 * Decrement the reference count and clear the enabled
810 * bitmask when the last listener on an event goes away.
812 if (--pmu->enable_count[bit] == 0) {
813 pmu->enable &= ~BIT(bit);
814 pmu->timer_enabled &= pmu_needs_timer(pmu);
817 spin_unlock_irqrestore(&pmu->lock, flags);
820 static void i915_pmu_event_start(struct perf_event *event, int flags)
822 struct drm_i915_private *i915 =
823 container_of(event->pmu, typeof(*i915), pmu.base);
824 struct i915_pmu *pmu = &i915->pmu;
829 i915_pmu_enable(event);
833 static void i915_pmu_event_stop(struct perf_event *event, int flags)
835 if (flags & PERF_EF_UPDATE)
836 i915_pmu_event_read(event);
837 i915_pmu_disable(event);
838 event->hw.state = PERF_HES_STOPPED;
841 static int i915_pmu_event_add(struct perf_event *event, int flags)
843 struct drm_i915_private *i915 =
844 container_of(event->pmu, typeof(*i915), pmu.base);
845 struct i915_pmu *pmu = &i915->pmu;
850 if (flags & PERF_EF_START)
851 i915_pmu_event_start(event, flags);
856 static void i915_pmu_event_del(struct perf_event *event, int flags)
858 i915_pmu_event_stop(event, PERF_EF_UPDATE);
861 static int i915_pmu_event_event_idx(struct perf_event *event)
866 struct i915_str_attribute {
867 struct device_attribute attr;
871 static ssize_t i915_pmu_format_show(struct device *dev,
872 struct device_attribute *attr, char *buf)
874 struct i915_str_attribute *eattr;
876 eattr = container_of(attr, struct i915_str_attribute, attr);
877 return sprintf(buf, "%s\n", eattr->str);
880 #define I915_PMU_FORMAT_ATTR(_name, _config) \
881 (&((struct i915_str_attribute[]) { \
882 { .attr = __ATTR(_name, 0444, i915_pmu_format_show, NULL), \
886 static struct attribute *i915_pmu_format_attrs[] = {
887 I915_PMU_FORMAT_ATTR(i915_eventid, "config:0-20"),
891 static const struct attribute_group i915_pmu_format_attr_group = {
893 .attrs = i915_pmu_format_attrs,
896 struct i915_ext_attribute {
897 struct device_attribute attr;
901 static ssize_t i915_pmu_event_show(struct device *dev,
902 struct device_attribute *attr, char *buf)
904 struct i915_ext_attribute *eattr;
906 eattr = container_of(attr, struct i915_ext_attribute, attr);
907 return sprintf(buf, "config=0x%lx\n", eattr->val);
910 static ssize_t cpumask_show(struct device *dev,
911 struct device_attribute *attr, char *buf)
913 return cpumap_print_to_pagebuf(true, buf, &i915_pmu_cpumask);
916 static DEVICE_ATTR_RO(cpumask);
918 static struct attribute *i915_cpumask_attrs[] = {
919 &dev_attr_cpumask.attr,
923 static const struct attribute_group i915_pmu_cpumask_attr_group = {
924 .attrs = i915_cpumask_attrs,
927 #define __event(__counter, __name, __unit) \
929 .counter = (__counter), \
935 #define __global_event(__counter, __name, __unit) \
937 .counter = (__counter), \
943 #define __engine_event(__sample, __name) \
945 .sample = (__sample), \
949 static struct i915_ext_attribute *
950 add_i915_attr(struct i915_ext_attribute *attr, const char *name, u64 config)
952 sysfs_attr_init(&attr->attr.attr);
953 attr->attr.attr.name = name;
954 attr->attr.attr.mode = 0444;
955 attr->attr.show = i915_pmu_event_show;
961 static struct perf_pmu_events_attr *
962 add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
965 sysfs_attr_init(&attr->attr.attr);
966 attr->attr.attr.name = name;
967 attr->attr.attr.mode = 0444;
968 attr->attr.show = perf_event_sysfs_show;
969 attr->event_str = str;
974 static struct attribute **
975 create_event_attributes(struct i915_pmu *pmu)
977 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
978 static const struct {
979 unsigned int counter;
984 __event(0, "actual-frequency", "M"),
985 __event(1, "requested-frequency", "M"),
986 __global_event(2, "interrupts", NULL),
987 __event(3, "rc6-residency", "ns"),
988 __event(4, "software-gt-awake-time", "ns"),
990 static const struct {
991 enum drm_i915_pmu_engine_sample sample;
993 } engine_events[] = {
994 __engine_event(I915_SAMPLE_BUSY, "busy"),
995 __engine_event(I915_SAMPLE_SEMA, "sema"),
996 __engine_event(I915_SAMPLE_WAIT, "wait"),
998 unsigned int count = 0;
999 struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
1000 struct i915_ext_attribute *i915_attr = NULL, *i915_iter;
1001 struct attribute **attr = NULL, **attr_iter;
1002 struct intel_engine_cs *engine;
1003 struct intel_gt *gt;
1006 /* Count how many counters we will be exposing. */
1007 for_each_gt(gt, i915, j) {
1008 for (i = 0; i < ARRAY_SIZE(events); i++) {
1009 u64 config = ___I915_PMU_OTHER(j, events[i].counter);
1011 if (!config_status(i915, config))
1016 for_each_uabi_engine(engine, i915) {
1017 for (i = 0; i < ARRAY_SIZE(engine_events); i++) {
1018 if (!engine_event_status(engine,
1019 engine_events[i].sample))
1024 /* Allocate attribute objects and table. */
1025 i915_attr = kcalloc(count, sizeof(*i915_attr), GFP_KERNEL);
1029 pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
1033 /* Max one pointer of each attribute type plus a termination entry. */
1034 attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
1038 i915_iter = i915_attr;
1039 pmu_iter = pmu_attr;
1042 /* Initialize supported non-engine counters. */
1043 for_each_gt(gt, i915, j) {
1044 for (i = 0; i < ARRAY_SIZE(events); i++) {
1045 u64 config = ___I915_PMU_OTHER(j, events[i].counter);
1048 if (config_status(i915, config))
1051 if (events[i].global || !HAS_EXTRA_GT_LIST(i915))
1052 str = kstrdup(events[i].name, GFP_KERNEL);
1054 str = kasprintf(GFP_KERNEL, "%s-gt%u",
1059 *attr_iter++ = &i915_iter->attr.attr;
1060 i915_iter = add_i915_attr(i915_iter, str, config);
1062 if (events[i].unit) {
1063 if (events[i].global || !HAS_EXTRA_GT_LIST(i915))
1064 str = kasprintf(GFP_KERNEL, "%s.unit",
1067 str = kasprintf(GFP_KERNEL, "%s-gt%u.unit",
1072 *attr_iter++ = &pmu_iter->attr.attr;
1073 pmu_iter = add_pmu_attr(pmu_iter, str,
1079 /* Initialize supported engine counters. */
1080 for_each_uabi_engine(engine, i915) {
1081 for (i = 0; i < ARRAY_SIZE(engine_events); i++) {
1084 if (engine_event_status(engine,
1085 engine_events[i].sample))
1088 str = kasprintf(GFP_KERNEL, "%s-%s",
1089 engine->name, engine_events[i].name);
1093 *attr_iter++ = &i915_iter->attr.attr;
1095 add_i915_attr(i915_iter, str,
1096 __I915_PMU_ENGINE(engine->uabi_class,
1097 engine->uabi_instance,
1098 engine_events[i].sample));
1100 str = kasprintf(GFP_KERNEL, "%s-%s.unit",
1101 engine->name, engine_events[i].name);
1105 *attr_iter++ = &pmu_iter->attr.attr;
1106 pmu_iter = add_pmu_attr(pmu_iter, str, "ns");
1110 pmu->i915_attr = i915_attr;
1111 pmu->pmu_attr = pmu_attr;
1116 for (attr_iter = attr; *attr_iter; attr_iter++)
1117 kfree((*attr_iter)->name);
1127 static void free_event_attributes(struct i915_pmu *pmu)
1129 struct attribute **attr_iter = pmu->events_attr_group.attrs;
1131 for (; *attr_iter; attr_iter++)
1132 kfree((*attr_iter)->name);
1134 kfree(pmu->events_attr_group.attrs);
1135 kfree(pmu->i915_attr);
1136 kfree(pmu->pmu_attr);
1138 pmu->events_attr_group.attrs = NULL;
1139 pmu->i915_attr = NULL;
1140 pmu->pmu_attr = NULL;
1143 static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
1145 struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
1147 GEM_BUG_ON(!pmu->base.event_init);
1149 /* Select the first online CPU as a designated reader. */
1150 if (cpumask_empty(&i915_pmu_cpumask))
1151 cpumask_set_cpu(cpu, &i915_pmu_cpumask);
1156 static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
1158 struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
1159 unsigned int target = i915_pmu_target_cpu;
1161 GEM_BUG_ON(!pmu->base.event_init);
1164 * Unregistering an instance generates a CPU offline event which we must
1165 * ignore to avoid incorrectly modifying the shared i915_pmu_cpumask.
1170 if (cpumask_test_and_clear_cpu(cpu, &i915_pmu_cpumask)) {
1171 target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
1173 /* Migrate events if there is a valid target */
1174 if (target < nr_cpu_ids) {
1175 cpumask_set_cpu(target, &i915_pmu_cpumask);
1176 i915_pmu_target_cpu = target;
1180 if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
1181 perf_pmu_migrate_context(&pmu->base, cpu, target);
1182 pmu->cpuhp.cpu = target;
1188 static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
1190 int i915_pmu_init(void)
1194 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
1195 "perf/x86/intel/i915:online",
1196 i915_pmu_cpu_online,
1197 i915_pmu_cpu_offline);
1199 pr_notice("Failed to setup cpuhp state for i915 PMU! (%d)\n",
1207 void i915_pmu_exit(void)
1209 if (cpuhp_slot != CPUHP_INVALID)
1210 cpuhp_remove_multi_state(cpuhp_slot);
1213 static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu)
1215 if (cpuhp_slot == CPUHP_INVALID)
1218 return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
1221 static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu)
1223 cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node);
1226 static bool is_igp(struct drm_i915_private *i915)
1228 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
1230 /* IGP is 0000:00:02.0 */
1231 return pci_domain_nr(pdev->bus) == 0 &&
1232 pdev->bus->number == 0 &&
1233 PCI_SLOT(pdev->devfn) == 2 &&
1234 PCI_FUNC(pdev->devfn) == 0;
1237 void i915_pmu_register(struct drm_i915_private *i915)
1239 struct i915_pmu *pmu = &i915->pmu;
1240 const struct attribute_group *attr_groups[] = {
1241 &i915_pmu_format_attr_group,
1242 &pmu->events_attr_group,
1243 &i915_pmu_cpumask_attr_group,
1249 if (GRAPHICS_VER(i915) <= 2) {
1250 drm_info(&i915->drm, "PMU not supported for this GPU.");
1254 spin_lock_init(&pmu->lock);
1255 hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1256 pmu->timer.function = i915_sample;
1257 pmu->cpuhp.cpu = -1;
1260 if (!is_igp(i915)) {
1261 pmu->name = kasprintf(GFP_KERNEL,
1263 dev_name(i915->drm.dev));
1265 /* tools/perf reserves colons as special. */
1266 strreplace((char *)pmu->name, ':', '_');
1274 pmu->events_attr_group.name = "events";
1275 pmu->events_attr_group.attrs = create_event_attributes(pmu);
1276 if (!pmu->events_attr_group.attrs)
1279 pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
1281 if (!pmu->base.attr_groups)
1284 pmu->base.module = THIS_MODULE;
1285 pmu->base.task_ctx_nr = perf_invalid_context;
1286 pmu->base.event_init = i915_pmu_event_init;
1287 pmu->base.add = i915_pmu_event_add;
1288 pmu->base.del = i915_pmu_event_del;
1289 pmu->base.start = i915_pmu_event_start;
1290 pmu->base.stop = i915_pmu_event_stop;
1291 pmu->base.read = i915_pmu_event_read;
1292 pmu->base.event_idx = i915_pmu_event_event_idx;
1294 ret = perf_pmu_register(&pmu->base, pmu->name, -1);
1298 ret = i915_pmu_register_cpuhp_state(pmu);
1305 perf_pmu_unregister(&pmu->base);
1307 kfree(pmu->base.attr_groups);
1309 pmu->base.event_init = NULL;
1310 free_event_attributes(pmu);
1315 drm_notice(&i915->drm, "Failed to register PMU!\n");
1318 void i915_pmu_unregister(struct drm_i915_private *i915)
1320 struct i915_pmu *pmu = &i915->pmu;
1322 if (!pmu->base.event_init)
1326 * "Disconnect" the PMU callbacks - since all are atomic synchronize_rcu
1327 * ensures all currently executing ones will have exited before we
1328 * proceed with unregistration.
1333 hrtimer_cancel(&pmu->timer);
1335 i915_pmu_unregister_cpuhp_state(pmu);
1337 perf_pmu_unregister(&pmu->base);
1338 pmu->base.event_init = NULL;
1339 kfree(pmu->base.attr_groups);
1342 free_event_attributes(pmu);