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24 * Robert Bragg <robert@sixbynine.org>
29 * DOC: i915 Perf Overview
31 * Gen graphics supports a large number of performance counters that can help
32 * driver and application developers understand and optimize their use of the
35 * This i915 perf interface enables userspace to configure and open a file
36 * descriptor representing a stream of GPU metrics which can then be read() as
37 * a stream of sample records.
39 * The interface is particularly suited to exposing buffered metrics that are
40 * captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.
42 * Streams representing a single context are accessible to applications with a
43 * corresponding drm file descriptor, such that OpenGL can use the interface
44 * without special privileges. Access to system-wide metrics requires root
45 * privileges by default, unless changed via the dev.i915.perf_event_paranoid
51 * DOC: i915 Perf History and Comparison with Core Perf
53 * The interface was initially inspired by the core Perf infrastructure but
54 * some notable differences are:
56 * i915 perf file descriptors represent a "stream" instead of an "event"; where
57 * a perf event primarily corresponds to a single 64bit value, while a stream
58 * might sample sets of tightly-coupled counters, depending on the
59 * configuration. For example the Gen OA unit isn't designed to support
60 * orthogonal configurations of individual counters; it's configured for a set
61 * of related counters. Samples for an i915 perf stream capturing OA metrics
62 * will include a set of counter values packed in a compact HW specific format.
63 * The OA unit supports a number of different packing formats which can be
64 * selected by the user opening the stream. Perf has support for grouping
65 * events, but each event in the group is configured, validated and
66 * authenticated individually with separate system calls.
68 * i915 perf stream configurations are provided as an array of u64 (key,value)
69 * pairs, instead of a fixed struct with multiple miscellaneous config members,
70 * interleaved with event-type specific members.
72 * i915 perf doesn't support exposing metrics via an mmap'd circular buffer.
73 * The supported metrics are being written to memory by the GPU unsynchronized
74 * with the CPU, using HW specific packing formats for counter sets. Sometimes
75 * the constraints on HW configuration require reports to be filtered before it
76 * would be acceptable to expose them to unprivileged applications - to hide
77 * the metrics of other processes/contexts. For these use cases a read() based
78 * interface is a good fit, and provides an opportunity to filter data as it
79 * gets copied from the GPU mapped buffers to userspace buffers.
82 * Issues hit with first prototype based on Core Perf
83 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
85 * The first prototype of this driver was based on the core perf
86 * infrastructure, and while we did make that mostly work, with some changes to
87 * perf, we found we were breaking or working around too many assumptions baked
88 * into perf's currently cpu centric design.
90 * In the end we didn't see a clear benefit to making perf's implementation and
91 * interface more complex by changing design assumptions while we knew we still
92 * wouldn't be able to use any existing perf based userspace tools.
94 * Also considering the Gen specific nature of the Observability hardware and
95 * how userspace will sometimes need to combine i915 perf OA metrics with
96 * side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're
97 * expecting the interface to be used by a platform specific userspace such as
98 * OpenGL or tools. This is to say; we aren't inherently missing out on having
99 * a standard vendor/architecture agnostic interface by not using perf.
102 * For posterity, in case we might re-visit trying to adapt core perf to be
103 * better suited to exposing i915 metrics these were the main pain points we
106 * - The perf based OA PMU driver broke some significant design assumptions:
108 * Existing perf pmus are used for profiling work on a cpu and we were
109 * introducing the idea of _IS_DEVICE pmus with different security
110 * implications, the need to fake cpu-related data (such as user/kernel
111 * registers) to fit with perf's current design, and adding _DEVICE records
112 * as a way to forward device-specific status records.
114 * The OA unit writes reports of counters into a circular buffer, without
115 * involvement from the CPU, making our PMU driver the first of a kind.
117 * Given the way we were periodically forward data from the GPU-mapped, OA
118 * buffer to perf's buffer, those bursts of sample writes looked to perf like
119 * we were sampling too fast and so we had to subvert its throttling checks.
121 * Perf supports groups of counters and allows those to be read via
122 * transactions internally but transactions currently seem designed to be
123 * explicitly initiated from the cpu (say in response to a userspace read())
124 * and while we could pull a report out of the OA buffer we can't
125 * trigger a report from the cpu on demand.
127 * Related to being report based; the OA counters are configured in HW as a
128 * set while perf generally expects counter configurations to be orthogonal.
129 * Although counters can be associated with a group leader as they are
130 * opened, there's no clear precedent for being able to provide group-wide
131 * configuration attributes (for example we want to let userspace choose the
132 * OA unit report format used to capture all counters in a set, or specify a
133 * GPU context to filter metrics on). We avoided using perf's grouping
134 * feature and forwarded OA reports to userspace via perf's 'raw' sample
135 * field. This suited our userspace well considering how coupled the counters
136 * are when dealing with normalizing. It would be inconvenient to split
137 * counters up into separate events, only to require userspace to recombine
138 * them. For Mesa it's also convenient to be forwarded raw, periodic reports
139 * for combining with the side-band raw reports it captures using
140 * MI_REPORT_PERF_COUNT commands.
142 * - As a side note on perf's grouping feature; there was also some concern
143 * that using PERF_FORMAT_GROUP as a way to pack together counter values
144 * would quite drastically inflate our sample sizes, which would likely
145 * lower the effective sampling resolutions we could use when the available
146 * memory bandwidth is limited.
148 * With the OA unit's report formats, counters are packed together as 32
149 * or 40bit values, with the largest report size being 256 bytes.
151 * PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a
152 * documented ordering to the values, implying PERF_FORMAT_ID must also be
153 * used to add a 64bit ID before each value; giving 16 bytes per counter.
155 * Related to counter orthogonality; we can't time share the OA unit, while
156 * event scheduling is a central design idea within perf for allowing
157 * userspace to open + enable more events than can be configured in HW at any
158 * one time. The OA unit is not designed to allow re-configuration while in
159 * use. We can't reconfigure the OA unit without losing internal OA unit
160 * state which we can't access explicitly to save and restore. Reconfiguring
161 * the OA unit is also relatively slow, involving ~100 register writes. From
162 * userspace Mesa also depends on a stable OA configuration when emitting
163 * MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be
164 * disabled while there are outstanding MI_RPC commands lest we hang the
167 * The contents of sample records aren't extensible by device drivers (i.e.
168 * the sample_type bits). As an example; Sourab Gupta had been looking to
169 * attach GPU timestamps to our OA samples. We were shoehorning OA reports
170 * into sample records by using the 'raw' field, but it's tricky to pack more
171 * than one thing into this field because events/core.c currently only lets a
172 * pmu give a single raw data pointer plus len which will be copied into the
173 * ring buffer. To include more than the OA report we'd have to copy the
174 * report into an intermediate larger buffer. I'd been considering allowing a
175 * vector of data+len values to be specified for copying the raw data, but
176 * it felt like a kludge to being using the raw field for this purpose.
178 * - It felt like our perf based PMU was making some technical compromises
179 * just for the sake of using perf:
181 * perf_event_open() requires events to either relate to a pid or a specific
182 * cpu core, while our device pmu related to neither. Events opened with a
183 * pid will be automatically enabled/disabled according to the scheduling of
184 * that process - so not appropriate for us. When an event is related to a
185 * cpu id, perf ensures pmu methods will be invoked via an inter process
186 * interrupt on that core. To avoid invasive changes our userspace opened OA
187 * perf events for a specific cpu. This was workable but it meant the
188 * majority of the OA driver ran in atomic context, including all OA report
189 * forwarding, which wasn't really necessary in our case and seems to make
190 * our locking requirements somewhat complex as we handled the interaction
191 * with the rest of the i915 driver.
194 #include <linux/anon_inodes.h>
195 #include <linux/sizes.h>
196 #include <linux/uuid.h>
198 #include "gem/i915_gem_context.h"
199 #include "gem/i915_gem_internal.h"
200 #include "gt/intel_engine_pm.h"
201 #include "gt/intel_engine_regs.h"
202 #include "gt/intel_engine_user.h"
203 #include "gt/intel_execlists_submission.h"
204 #include "gt/intel_gpu_commands.h"
205 #include "gt/intel_gt.h"
206 #include "gt/intel_gt_clock_utils.h"
207 #include "gt/intel_gt_mcr.h"
208 #include "gt/intel_gt_regs.h"
209 #include "gt/intel_lrc.h"
210 #include "gt/intel_lrc_reg.h"
211 #include "gt/intel_ring.h"
212 #include "gt/uc/intel_guc_slpc.h"
214 #include "i915_drv.h"
215 #include "i915_file_private.h"
216 #include "i915_perf.h"
217 #include "i915_perf_oa_regs.h"
218 #include "i915_reg.h"
220 /* HW requires this to be a power of two, between 128k and 16M, though driver
221 * is currently generally designed assuming the largest 16M size is used such
222 * that the overflow cases are unlikely in normal operation.
224 #define OA_BUFFER_SIZE SZ_16M
226 #define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
229 * DOC: OA Tail Pointer Race
231 * There's a HW race condition between OA unit tail pointer register updates and
232 * writes to memory whereby the tail pointer can sometimes get ahead of what's
233 * been written out to the OA buffer so far (in terms of what's visible to the
236 * Although this can be observed explicitly while copying reports to userspace
237 * by checking for a zeroed report-id field in tail reports, we want to account
238 * for this earlier, as part of the oa_buffer_check_unlocked to avoid lots of
239 * redundant read() attempts.
241 * We workaround this issue in oa_buffer_check_unlocked() by reading the reports
242 * in the OA buffer, starting from the tail reported by the HW until we find a
243 * report with its first 2 dwords not 0 meaning its previous report is
244 * completely in memory and ready to be read. Those dwords are also set to 0
245 * once read and the whole buffer is cleared upon OA buffer initialization. The
246 * first dword is the reason for this report while the second is the timestamp,
247 * making the chances of having those 2 fields at 0 fairly unlikely. A more
248 * detailed explanation is available in oa_buffer_check_unlocked().
250 * Most of the implementation details for this workaround are in
251 * oa_buffer_check_unlocked() and _append_oa_reports()
253 * Note for posterity: previously the driver used to define an effective tail
254 * pointer that lagged the real pointer by a 'tail margin' measured in bytes
255 * derived from %OA_TAIL_MARGIN_NSEC and the configured sampling frequency.
256 * This was flawed considering that the OA unit may also automatically generate
257 * non-periodic reports (such as on context switch) or the OA unit may be
258 * enabled without any periodic sampling.
260 #define OA_TAIL_MARGIN_NSEC 100000ULL
261 #define INVALID_TAIL_PTR 0xffffffff
263 /* The default frequency for checking whether the OA unit has written new
264 * reports to the circular OA buffer...
266 #define DEFAULT_POLL_FREQUENCY_HZ 200
267 #define DEFAULT_POLL_PERIOD_NS (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY_HZ)
269 /* for sysctl proc_dointvec_minmax of dev.i915.perf_stream_paranoid */
270 static u32 i915_perf_stream_paranoid = true;
272 /* The maximum exponent the hardware accepts is 63 (essentially it selects one
273 * of the 64bit timestamp bits to trigger reports from) but there's currently
274 * no known use case for sampling as infrequently as once per 47 thousand years.
276 * Since the timestamps included in OA reports are only 32bits it seems
277 * reasonable to limit the OA exponent where it's still possible to account for
278 * overflow in OA report timestamps.
280 #define OA_EXPONENT_MAX 31
282 #define INVALID_CTX_ID 0xffffffff
284 /* On Gen8+ automatically triggered OA reports include a 'reason' field... */
285 #define OAREPORT_REASON_MASK 0x3f
286 #define OAREPORT_REASON_MASK_EXTENDED 0x7f
287 #define OAREPORT_REASON_SHIFT 19
288 #define OAREPORT_REASON_TIMER (1<<0)
289 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
290 #define OAREPORT_REASON_CLK_RATIO (1<<5)
292 #define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
294 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
296 * The highest sampling frequency we can theoretically program the OA unit
297 * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell.
299 * Initialized just before we register the sysctl parameter.
301 static int oa_sample_rate_hard_limit;
303 /* Theoretically we can program the OA unit to sample every 160ns but don't
304 * allow that by default unless root...
306 * The default threshold of 100000Hz is based on perf's similar
307 * kernel.perf_event_max_sample_rate sysctl parameter.
309 static u32 i915_oa_max_sample_rate = 100000;
311 /* XXX: beware if future OA HW adds new report formats that the current
312 * code assumes all reports have a power-of-two size and ~(size - 1) can
313 * be used as a mask to align the OA tail pointer.
315 static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
316 [I915_OA_FORMAT_A13] = { 0, 64 },
317 [I915_OA_FORMAT_A29] = { 1, 128 },
318 [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 },
319 /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */
320 [I915_OA_FORMAT_B4_C8] = { 4, 64 },
321 [I915_OA_FORMAT_A45_B8_C8] = { 5, 256 },
322 [I915_OA_FORMAT_B4_C8_A16] = { 6, 128 },
323 [I915_OA_FORMAT_C4_B8] = { 7, 64 },
324 [I915_OA_FORMAT_A12] = { 0, 64 },
325 [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
326 [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
327 [I915_OAR_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
328 [I915_OA_FORMAT_A24u40_A14u32_B8_C8] = { 5, 256 },
331 #define SAMPLE_OA_REPORT (1<<0)
334 * struct perf_open_properties - for validated properties given to open a stream
335 * @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
336 * @single_context: Whether a single or all gpu contexts should be monitored
337 * @hold_preemption: Whether the preemption is disabled for the filtered
339 * @ctx_handle: A gem ctx handle for use with @single_context
340 * @metrics_set: An ID for an OA unit metric set advertised via sysfs
341 * @oa_format: An OA unit HW report format
342 * @oa_periodic: Whether to enable periodic OA unit sampling
343 * @oa_period_exponent: The OA unit sampling period is derived from this
344 * @engine: The engine (typically rcs0) being monitored by the OA unit
345 * @has_sseu: Whether @sseu was specified by userspace
346 * @sseu: internal SSEU configuration computed either from the userspace
347 * specified configuration in the opening parameters or a default value
348 * (see get_default_sseu_config())
349 * @poll_oa_period: The period in nanoseconds at which the CPU will check for OA
352 * As read_properties_unlocked() enumerates and validates the properties given
353 * to open a stream of metrics the configuration is built up in the structure
354 * which starts out zero initialized.
356 struct perf_open_properties {
359 u64 single_context:1;
360 u64 hold_preemption:1;
363 /* OA sampling state */
367 int oa_period_exponent;
369 struct intel_engine_cs *engine;
372 struct intel_sseu sseu;
377 struct i915_oa_config_bo {
378 struct llist_node node;
380 struct i915_oa_config *oa_config;
381 struct i915_vma *vma;
384 static struct ctl_table_header *sysctl_header;
386 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
388 void i915_oa_config_release(struct kref *ref)
390 struct i915_oa_config *oa_config =
391 container_of(ref, typeof(*oa_config), ref);
393 kfree(oa_config->flex_regs);
394 kfree(oa_config->b_counter_regs);
395 kfree(oa_config->mux_regs);
397 kfree_rcu(oa_config, rcu);
400 struct i915_oa_config *
401 i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set)
403 struct i915_oa_config *oa_config;
406 oa_config = idr_find(&perf->metrics_idr, metrics_set);
408 oa_config = i915_oa_config_get(oa_config);
414 static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
416 i915_oa_config_put(oa_bo->oa_config);
417 i915_vma_put(oa_bo->vma);
421 static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)
423 struct intel_uncore *uncore = stream->uncore;
425 return intel_uncore_read(uncore, GEN12_OAG_OATAILPTR) &
426 GEN12_OAG_OATAILPTR_MASK;
429 static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
431 struct intel_uncore *uncore = stream->uncore;
433 return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
436 static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
438 struct intel_uncore *uncore = stream->uncore;
439 u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
441 return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
445 * oa_buffer_check_unlocked - check for data and update tail ptr state
446 * @stream: i915 stream instance
448 * This is either called via fops (for blocking reads in user ctx) or the poll
449 * check hrtimer (atomic ctx) to check the OA buffer tail pointer and check
450 * if there is data available for userspace to read.
452 * This function is central to providing a workaround for the OA unit tail
453 * pointer having a race with respect to what data is visible to the CPU.
454 * It is responsible for reading tail pointers from the hardware and giving
455 * the pointers time to 'age' before they are made available for reading.
456 * (See description of OA_TAIL_MARGIN_NSEC above for further details.)
458 * Besides returning true when there is data available to read() this function
459 * also updates the tail, aging_tail and aging_timestamp in the oa_buffer
462 * Note: It's safe to read OA config state here unlocked, assuming that this is
463 * only called while the stream is enabled, while the global OA configuration
466 * Returns: %true if the OA buffer contains data, else %false
468 static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
470 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
471 int report_size = stream->oa_buffer.format->size;
477 /* We have to consider the (unlikely) possibility that read() errors
478 * could result in an OA buffer reset which might reset the head and
481 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
483 hw_tail = stream->perf->ops.oa_hw_tail_read(stream);
485 /* The tail pointer increases in 64 byte increments,
486 * not in report_size steps...
488 hw_tail &= ~(report_size - 1);
490 now = ktime_get_mono_fast_ns();
492 if (hw_tail == stream->oa_buffer.aging_tail &&
493 (now - stream->oa_buffer.aging_timestamp) > OA_TAIL_MARGIN_NSEC) {
494 /* If the HW tail hasn't move since the last check and the HW
495 * tail has been aging for long enough, declare it the new
498 stream->oa_buffer.tail = stream->oa_buffer.aging_tail;
500 u32 head, tail, aged_tail;
502 /* NB: The head we observe here might effectively be a little
503 * out of date. If a read() is in progress, the head could be
504 * anywhere between this head and stream->oa_buffer.tail.
506 head = stream->oa_buffer.head - gtt_offset;
507 aged_tail = stream->oa_buffer.tail - gtt_offset;
509 hw_tail -= gtt_offset;
512 /* Walk the stream backward until we find a report with dword 0
513 * & 1 not at 0. Since the circular buffer pointers progress by
514 * increments of 64 bytes and that reports can be up to 256
515 * bytes long, we can't tell whether a report has fully landed
516 * in memory before the first 2 dwords of the following report
517 * have effectively landed.
519 * This is assuming that the writes of the OA unit land in
520 * memory in the order they were written to.
521 * If not : (╯°□°)╯︵ ┻━┻
523 while (OA_TAKEN(tail, aged_tail) >= report_size) {
524 u32 *report32 = (void *)(stream->oa_buffer.vaddr + tail);
526 if (report32[0] != 0 || report32[1] != 0)
529 tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
532 if (OA_TAKEN(hw_tail, tail) > report_size &&
533 __ratelimit(&stream->perf->tail_pointer_race))
534 drm_notice(&stream->uncore->i915->drm,
535 "unlanded report(s) head=0x%x tail=0x%x hw_tail=0x%x\n",
536 head, tail, hw_tail);
538 stream->oa_buffer.tail = gtt_offset + tail;
539 stream->oa_buffer.aging_tail = gtt_offset + hw_tail;
540 stream->oa_buffer.aging_timestamp = now;
543 pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset,
544 stream->oa_buffer.head - gtt_offset) >= report_size;
546 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
552 * append_oa_status - Appends a status record to a userspace read() buffer.
553 * @stream: An i915-perf stream opened for OA metrics
554 * @buf: destination buffer given by userspace
555 * @count: the number of bytes userspace wants to read
556 * @offset: (inout): the current position for writing into @buf
557 * @type: The kind of status to report to userspace
559 * Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`)
560 * into the userspace read() buffer.
562 * The @buf @offset will only be updated on success.
564 * Returns: 0 on success, negative error code on failure.
566 static int append_oa_status(struct i915_perf_stream *stream,
570 enum drm_i915_perf_record_type type)
572 struct drm_i915_perf_record_header header = { type, 0, sizeof(header) };
574 if ((count - *offset) < header.size)
577 if (copy_to_user(buf + *offset, &header, sizeof(header)))
580 (*offset) += header.size;
586 * append_oa_sample - Copies single OA report into userspace read() buffer.
587 * @stream: An i915-perf stream opened for OA metrics
588 * @buf: destination buffer given by userspace
589 * @count: the number of bytes userspace wants to read
590 * @offset: (inout): the current position for writing into @buf
591 * @report: A single OA report to (optionally) include as part of the sample
593 * The contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*`
594 * properties when opening a stream, tracked as `stream->sample_flags`. This
595 * function copies the requested components of a single sample to the given
598 * The @buf @offset will only be updated on success.
600 * Returns: 0 on success, negative error code on failure.
602 static int append_oa_sample(struct i915_perf_stream *stream,
608 int report_size = stream->oa_buffer.format->size;
609 struct drm_i915_perf_record_header header;
611 header.type = DRM_I915_PERF_RECORD_SAMPLE;
613 header.size = stream->sample_size;
615 if ((count - *offset) < header.size)
619 if (copy_to_user(buf, &header, sizeof(header)))
621 buf += sizeof(header);
623 if (copy_to_user(buf, report, report_size))
626 (*offset) += header.size;
632 * gen8_append_oa_reports - Copies all buffered OA reports into
633 * userspace read() buffer.
634 * @stream: An i915-perf stream opened for OA metrics
635 * @buf: destination buffer given by userspace
636 * @count: the number of bytes userspace wants to read
637 * @offset: (inout): the current position for writing into @buf
639 * Notably any error condition resulting in a short read (-%ENOSPC or
640 * -%EFAULT) will be returned even though one or more records may
641 * have been successfully copied. In this case it's up to the caller
642 * to decide if the error should be squashed before returning to
645 * Note: reports are consumed from the head, and appended to the
646 * tail, so the tail chases the head?... If you think that's mad
647 * and back-to-front you're not alone, but this follows the
648 * Gen PRM naming convention.
650 * Returns: 0 on success, negative error code on failure.
652 static int gen8_append_oa_reports(struct i915_perf_stream *stream,
657 struct intel_uncore *uncore = stream->uncore;
658 int report_size = stream->oa_buffer.format->size;
659 u8 *oa_buf_base = stream->oa_buffer.vaddr;
660 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
661 u32 mask = (OA_BUFFER_SIZE - 1);
662 size_t start_offset = *offset;
667 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
670 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
672 head = stream->oa_buffer.head;
673 tail = stream->oa_buffer.tail;
675 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
678 * NB: oa_buffer.head/tail include the gtt_offset which we don't want
679 * while indexing relative to oa_buf_base.
685 * An out of bounds or misaligned head or tail pointer implies a driver
686 * bug since we validate + align the tail pointers we read from the
687 * hardware and we are in full control of the head pointer which should
688 * only be incremented by multiples of the report size (notably also
689 * all a power of two).
691 if (drm_WARN_ONCE(&uncore->i915->drm,
692 head > OA_BUFFER_SIZE || head % report_size ||
693 tail > OA_BUFFER_SIZE || tail % report_size,
694 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
700 OA_TAKEN(tail, head);
701 head = (head + report_size) & mask) {
702 u8 *report = oa_buf_base + head;
703 u32 *report32 = (void *)report;
708 * All the report sizes factor neatly into the buffer
709 * size so we never expect to see a report split
710 * between the beginning and end of the buffer.
712 * Given the initial alignment check a misalignment
713 * here would imply a driver bug that would result
716 if (drm_WARN_ON(&uncore->i915->drm,
717 (OA_BUFFER_SIZE - head) < report_size)) {
718 drm_err(&uncore->i915->drm,
719 "Spurious OA head ptr: non-integral report offset\n");
724 * The reason field includes flags identifying what
725 * triggered this specific report (mostly timer
726 * triggered or e.g. due to a context switch).
728 * This field is never expected to be zero so we can
729 * check that the report isn't invalid before copying
732 reason = ((report32[0] >> OAREPORT_REASON_SHIFT) &
733 (GRAPHICS_VER(stream->perf->i915) == 12 ?
734 OAREPORT_REASON_MASK_EXTENDED :
735 OAREPORT_REASON_MASK));
737 ctx_id = report32[2] & stream->specific_ctx_id_mask;
740 * Squash whatever is in the CTX_ID field if it's marked as
741 * invalid to be sure we avoid false-positive, single-context
744 * Note: that we don't clear the valid_ctx_bit so userspace can
745 * understand that the ID has been squashed by the kernel.
747 if (!(report32[0] & stream->perf->gen8_valid_ctx_bit) &&
748 GRAPHICS_VER(stream->perf->i915) <= 11)
749 ctx_id = report32[2] = INVALID_CTX_ID;
752 * NB: For Gen 8 the OA unit no longer supports clock gating
753 * off for a specific context and the kernel can't securely
754 * stop the counters from updating as system-wide / global
757 * Automatic reports now include a context ID so reports can be
758 * filtered on the cpu but it's not worth trying to
759 * automatically subtract/hide counter progress for other
760 * contexts while filtering since we can't stop userspace
761 * issuing MI_REPORT_PERF_COUNT commands which would still
762 * provide a side-band view of the real values.
764 * To allow userspace (such as Mesa/GL_INTEL_performance_query)
765 * to normalize counters for a single filtered context then it
766 * needs be forwarded bookend context-switch reports so that it
767 * can track switches in between MI_REPORT_PERF_COUNT commands
768 * and can itself subtract/ignore the progress of counters
769 * associated with other contexts. Note that the hardware
770 * automatically triggers reports when switching to a new
771 * context which are tagged with the ID of the newly active
772 * context. To avoid the complexity (and likely fragility) of
773 * reading ahead while parsing reports to try and minimize
774 * forwarding redundant context switch reports (i.e. between
775 * other, unrelated contexts) we simply elect to forward them
778 * We don't rely solely on the reason field to identify context
779 * switches since it's not-uncommon for periodic samples to
780 * identify a switch before any 'context switch' report.
783 stream->specific_ctx_id == ctx_id ||
784 stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
785 reason & OAREPORT_REASON_CTX_SWITCH) {
788 * While filtering for a single context we avoid
789 * leaking the IDs of other contexts.
792 stream->specific_ctx_id != ctx_id) {
793 report32[2] = INVALID_CTX_ID;
796 ret = append_oa_sample(stream, buf, count, offset,
801 stream->oa_buffer.last_ctx_id = ctx_id;
805 * Clear out the first 2 dword as a mean to detect unlanded
812 if (start_offset != *offset) {
813 i915_reg_t oaheadptr;
815 oaheadptr = GRAPHICS_VER(stream->perf->i915) == 12 ?
816 GEN12_OAG_OAHEADPTR : GEN8_OAHEADPTR;
818 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
821 * We removed the gtt_offset for the copy loop above, indexing
822 * relative to oa_buf_base so put back here...
825 intel_uncore_write(uncore, oaheadptr,
826 head & GEN12_OAG_OAHEADPTR_MASK);
827 stream->oa_buffer.head = head;
829 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
836 * gen8_oa_read - copy status records then buffered OA reports
837 * @stream: An i915-perf stream opened for OA metrics
838 * @buf: destination buffer given by userspace
839 * @count: the number of bytes userspace wants to read
840 * @offset: (inout): the current position for writing into @buf
842 * Checks OA unit status registers and if necessary appends corresponding
843 * status records for userspace (such as for a buffer full condition) and then
844 * initiate appending any buffered OA reports.
846 * Updates @offset according to the number of bytes successfully copied into
847 * the userspace buffer.
849 * NB: some data may be successfully copied to the userspace buffer
850 * even if an error is returned, and this is reflected in the
853 * Returns: zero on success or a negative error code
855 static int gen8_oa_read(struct i915_perf_stream *stream,
860 struct intel_uncore *uncore = stream->uncore;
862 i915_reg_t oastatus_reg;
865 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
868 oastatus_reg = GRAPHICS_VER(stream->perf->i915) == 12 ?
869 GEN12_OAG_OASTATUS : GEN8_OASTATUS;
871 oastatus = intel_uncore_read(uncore, oastatus_reg);
874 * We treat OABUFFER_OVERFLOW as a significant error:
876 * Although theoretically we could handle this more gracefully
877 * sometimes, some Gens don't correctly suppress certain
878 * automatically triggered reports in this condition and so we
879 * have to assume that old reports are now being trampled
882 * Considering how we don't currently give userspace control
883 * over the OA buffer size and always configure a large 16MB
884 * buffer, then a buffer overflow does anyway likely indicate
885 * that something has gone quite badly wrong.
887 if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
888 ret = append_oa_status(stream, buf, count, offset,
889 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
893 drm_dbg(&stream->perf->i915->drm,
894 "OA buffer overflow (exponent = %d): force restart\n",
895 stream->period_exponent);
897 stream->perf->ops.oa_disable(stream);
898 stream->perf->ops.oa_enable(stream);
901 * Note: .oa_enable() is expected to re-init the oabuffer and
902 * reset GEN8_OASTATUS for us
904 oastatus = intel_uncore_read(uncore, oastatus_reg);
907 if (oastatus & GEN8_OASTATUS_REPORT_LOST) {
908 ret = append_oa_status(stream, buf, count, offset,
909 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
913 intel_uncore_rmw(uncore, oastatus_reg,
914 GEN8_OASTATUS_COUNTER_OVERFLOW |
915 GEN8_OASTATUS_REPORT_LOST,
916 IS_GRAPHICS_VER(uncore->i915, 8, 11) ?
917 (GEN8_OASTATUS_HEAD_POINTER_WRAP |
918 GEN8_OASTATUS_TAIL_POINTER_WRAP) : 0);
921 return gen8_append_oa_reports(stream, buf, count, offset);
925 * gen7_append_oa_reports - Copies all buffered OA reports into
926 * userspace read() buffer.
927 * @stream: An i915-perf stream opened for OA metrics
928 * @buf: destination buffer given by userspace
929 * @count: the number of bytes userspace wants to read
930 * @offset: (inout): the current position for writing into @buf
932 * Notably any error condition resulting in a short read (-%ENOSPC or
933 * -%EFAULT) will be returned even though one or more records may
934 * have been successfully copied. In this case it's up to the caller
935 * to decide if the error should be squashed before returning to
938 * Note: reports are consumed from the head, and appended to the
939 * tail, so the tail chases the head?... If you think that's mad
940 * and back-to-front you're not alone, but this follows the
941 * Gen PRM naming convention.
943 * Returns: 0 on success, negative error code on failure.
945 static int gen7_append_oa_reports(struct i915_perf_stream *stream,
950 struct intel_uncore *uncore = stream->uncore;
951 int report_size = stream->oa_buffer.format->size;
952 u8 *oa_buf_base = stream->oa_buffer.vaddr;
953 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
954 u32 mask = (OA_BUFFER_SIZE - 1);
955 size_t start_offset = *offset;
960 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
963 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
965 head = stream->oa_buffer.head;
966 tail = stream->oa_buffer.tail;
968 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
970 /* NB: oa_buffer.head/tail include the gtt_offset which we don't want
971 * while indexing relative to oa_buf_base.
976 /* An out of bounds or misaligned head or tail pointer implies a driver
977 * bug since we validate + align the tail pointers we read from the
978 * hardware and we are in full control of the head pointer which should
979 * only be incremented by multiples of the report size (notably also
980 * all a power of two).
982 if (drm_WARN_ONCE(&uncore->i915->drm,
983 head > OA_BUFFER_SIZE || head % report_size ||
984 tail > OA_BUFFER_SIZE || tail % report_size,
985 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
991 OA_TAKEN(tail, head);
992 head = (head + report_size) & mask) {
993 u8 *report = oa_buf_base + head;
994 u32 *report32 = (void *)report;
996 /* All the report sizes factor neatly into the buffer
997 * size so we never expect to see a report split
998 * between the beginning and end of the buffer.
1000 * Given the initial alignment check a misalignment
1001 * here would imply a driver bug that would result
1004 if (drm_WARN_ON(&uncore->i915->drm,
1005 (OA_BUFFER_SIZE - head) < report_size)) {
1006 drm_err(&uncore->i915->drm,
1007 "Spurious OA head ptr: non-integral report offset\n");
1011 /* The report-ID field for periodic samples includes
1012 * some undocumented flags related to what triggered
1013 * the report and is never expected to be zero so we
1014 * can check that the report isn't invalid before
1015 * copying it to userspace...
1017 if (report32[0] == 0) {
1018 if (__ratelimit(&stream->perf->spurious_report_rs))
1019 drm_notice(&uncore->i915->drm,
1020 "Skipping spurious, invalid OA report\n");
1024 ret = append_oa_sample(stream, buf, count, offset, report);
1028 /* Clear out the first 2 dwords as a mean to detect unlanded
1035 if (start_offset != *offset) {
1036 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1038 /* We removed the gtt_offset for the copy loop above, indexing
1039 * relative to oa_buf_base so put back here...
1043 intel_uncore_write(uncore, GEN7_OASTATUS2,
1044 (head & GEN7_OASTATUS2_HEAD_MASK) |
1045 GEN7_OASTATUS2_MEM_SELECT_GGTT);
1046 stream->oa_buffer.head = head;
1048 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1055 * gen7_oa_read - copy status records then buffered OA reports
1056 * @stream: An i915-perf stream opened for OA metrics
1057 * @buf: destination buffer given by userspace
1058 * @count: the number of bytes userspace wants to read
1059 * @offset: (inout): the current position for writing into @buf
1061 * Checks Gen 7 specific OA unit status registers and if necessary appends
1062 * corresponding status records for userspace (such as for a buffer full
1063 * condition) and then initiate appending any buffered OA reports.
1065 * Updates @offset according to the number of bytes successfully copied into
1066 * the userspace buffer.
1068 * Returns: zero on success or a negative error code
1070 static int gen7_oa_read(struct i915_perf_stream *stream,
1075 struct intel_uncore *uncore = stream->uncore;
1079 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
1082 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1084 /* XXX: On Haswell we don't have a safe way to clear oastatus1
1085 * bits while the OA unit is enabled (while the tail pointer
1086 * may be updated asynchronously) so we ignore status bits
1087 * that have already been reported to userspace.
1089 oastatus1 &= ~stream->perf->gen7_latched_oastatus1;
1091 /* We treat OABUFFER_OVERFLOW as a significant error:
1093 * - The status can be interpreted to mean that the buffer is
1094 * currently full (with a higher precedence than OA_TAKEN()
1095 * which will start to report a near-empty buffer after an
1096 * overflow) but it's awkward that we can't clear the status
1097 * on Haswell, so without a reset we won't be able to catch
1100 * - Since it also implies the HW has started overwriting old
1101 * reports it may also affect our sanity checks for invalid
1102 * reports when copying to userspace that assume new reports
1103 * are being written to cleared memory.
1105 * - In the future we may want to introduce a flight recorder
1106 * mode where the driver will automatically maintain a safe
1107 * guard band between head/tail, avoiding this overflow
1108 * condition, but we avoid the added driver complexity for
1111 if (unlikely(oastatus1 & GEN7_OASTATUS1_OABUFFER_OVERFLOW)) {
1112 ret = append_oa_status(stream, buf, count, offset,
1113 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
1117 drm_dbg(&stream->perf->i915->drm,
1118 "OA buffer overflow (exponent = %d): force restart\n",
1119 stream->period_exponent);
1121 stream->perf->ops.oa_disable(stream);
1122 stream->perf->ops.oa_enable(stream);
1124 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1127 if (unlikely(oastatus1 & GEN7_OASTATUS1_REPORT_LOST)) {
1128 ret = append_oa_status(stream, buf, count, offset,
1129 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
1132 stream->perf->gen7_latched_oastatus1 |=
1133 GEN7_OASTATUS1_REPORT_LOST;
1136 return gen7_append_oa_reports(stream, buf, count, offset);
1140 * i915_oa_wait_unlocked - handles blocking IO until OA data available
1141 * @stream: An i915-perf stream opened for OA metrics
1143 * Called when userspace tries to read() from a blocking stream FD opened
1144 * for OA metrics. It waits until the hrtimer callback finds a non-empty
1145 * OA buffer and wakes us.
1147 * Note: it's acceptable to have this return with some false positives
1148 * since any subsequent read handling will return -EAGAIN if there isn't
1149 * really data ready for userspace yet.
1151 * Returns: zero on success or a negative error code
1153 static int i915_oa_wait_unlocked(struct i915_perf_stream *stream)
1155 /* We would wait indefinitely if periodic sampling is not enabled */
1156 if (!stream->periodic)
1159 return wait_event_interruptible(stream->poll_wq,
1160 oa_buffer_check_unlocked(stream));
1164 * i915_oa_poll_wait - call poll_wait() for an OA stream poll()
1165 * @stream: An i915-perf stream opened for OA metrics
1166 * @file: An i915 perf stream file
1167 * @wait: poll() state table
1169 * For handling userspace polling on an i915 perf stream opened for OA metrics,
1170 * this starts a poll_wait with the wait queue that our hrtimer callback wakes
1171 * when it sees data ready to read in the circular OA buffer.
1173 static void i915_oa_poll_wait(struct i915_perf_stream *stream,
1177 poll_wait(file, &stream->poll_wq, wait);
1181 * i915_oa_read - just calls through to &i915_oa_ops->read
1182 * @stream: An i915-perf stream opened for OA metrics
1183 * @buf: destination buffer given by userspace
1184 * @count: the number of bytes userspace wants to read
1185 * @offset: (inout): the current position for writing into @buf
1187 * Updates @offset according to the number of bytes successfully copied into
1188 * the userspace buffer.
1190 * Returns: zero on success or a negative error code
1192 static int i915_oa_read(struct i915_perf_stream *stream,
1197 return stream->perf->ops.read(stream, buf, count, offset);
1200 static struct intel_context *oa_pin_context(struct i915_perf_stream *stream)
1202 struct i915_gem_engines_iter it;
1203 struct i915_gem_context *ctx = stream->ctx;
1204 struct intel_context *ce;
1205 struct i915_gem_ww_ctx ww;
1208 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1209 if (ce->engine != stream->engine) /* first match! */
1215 i915_gem_context_unlock_engines(ctx);
1218 return ERR_PTR(err);
1220 i915_gem_ww_ctx_init(&ww, true);
1223 * As the ID is the gtt offset of the context's vma we
1224 * pin the vma to ensure the ID remains fixed.
1226 err = intel_context_pin_ww(ce, &ww);
1227 if (err == -EDEADLK) {
1228 err = i915_gem_ww_ctx_backoff(&ww);
1232 i915_gem_ww_ctx_fini(&ww);
1235 return ERR_PTR(err);
1237 stream->pinned_ctx = ce;
1238 return stream->pinned_ctx;
1242 __store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
1246 cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1247 if (GRAPHICS_VER(rq->engine->i915) >= 8)
1250 cs = intel_ring_begin(rq, 4);
1255 *cs++ = i915_mmio_reg_offset(reg);
1256 *cs++ = ggtt_offset;
1259 intel_ring_advance(rq, cs);
1265 __read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
1267 struct i915_request *rq;
1270 rq = i915_request_create(ce);
1274 i915_request_get(rq);
1276 err = __store_reg_to_mem(rq, reg, ggtt_offset);
1278 i915_request_add(rq);
1279 if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
1282 i915_request_put(rq);
1288 gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
1290 struct i915_vma *scratch;
1294 scratch = __vm_create_scratch_for_read_pinned(&ce->engine->gt->ggtt->vm, 4);
1295 if (IS_ERR(scratch))
1296 return PTR_ERR(scratch);
1298 err = i915_vma_sync(scratch);
1302 err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),
1303 i915_ggtt_offset(scratch));
1307 val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
1314 i915_gem_object_unpin_map(scratch->obj);
1317 i915_vma_unpin_and_release(&scratch, 0);
1322 * For execlist mode of submission, pick an unused context id
1323 * 0 - (NUM_CONTEXT_TAG -1) are used by other contexts
1324 * XXX_MAX_CONTEXT_HW_ID is used by idle context
1326 * For GuC mode of submission read context id from the upper dword of the
1327 * EXECLIST_STATUS register. Note that we read this value only once and expect
1328 * that the value stays fixed for the entire OA use case. There are cases where
1329 * GuC KMD implementation may deregister a context to reuse it's context id, but
1330 * we prevent that from happening to the OA context by pinning it.
1332 static int gen12_get_render_context_id(struct i915_perf_stream *stream)
1337 if (intel_engine_uses_guc(stream->engine)) {
1338 ret = gen12_guc_sw_ctx_id(stream->pinned_ctx, &ctx_id);
1342 mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
1343 (GEN12_GUC_SW_CTX_ID_SHIFT - 32);
1344 } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
1345 ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
1346 (XEHP_SW_CTX_ID_SHIFT - 32);
1348 mask = ((1U << XEHP_SW_CTX_ID_WIDTH) - 1) <<
1349 (XEHP_SW_CTX_ID_SHIFT - 32);
1351 ctx_id = (GEN12_MAX_CONTEXT_HW_ID - 1) <<
1352 (GEN11_SW_CTX_ID_SHIFT - 32);
1354 mask = ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
1355 (GEN11_SW_CTX_ID_SHIFT - 32);
1357 stream->specific_ctx_id = ctx_id & mask;
1358 stream->specific_ctx_id_mask = mask;
1363 static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
1366 u32 len = min(MI_LRI_LEN(state[idx]) + idx, end);
1370 for (; idx < len; idx += 2) {
1371 if (state[idx] == reg) {
1381 static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
1383 u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
1384 u32 *state = ce->lrc_reg_state;
1386 if (drm_WARN_ON(&ce->engine->i915->drm, !state))
1389 for (offset = 0; offset < len; ) {
1390 if (IS_MI_LRI_CMD(state[offset])) {
1392 * We expect reg-value pairs in MI_LRI command, so
1393 * MI_LRI_LEN() should be even, if not, issue a warning.
1395 drm_WARN_ON(&ce->engine->i915->drm,
1396 MI_LRI_LEN(state[offset]) & 0x1);
1398 if (oa_find_reg_in_lri(state, reg, &offset, len))
1405 return offset < len ? offset : U32_MAX;
1408 static int set_oa_ctx_ctrl_offset(struct intel_context *ce)
1410 i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
1411 struct i915_perf *perf = &ce->engine->i915->perf;
1412 u32 offset = perf->ctx_oactxctrl_offset;
1414 /* Do this only once. Failure is stored as offset of U32_MAX */
1418 offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));
1419 perf->ctx_oactxctrl_offset = offset;
1421 drm_dbg(&ce->engine->i915->drm,
1422 "%s oa ctx control at 0x%08x dword offset\n",
1423 ce->engine->name, offset);
1426 return offset && offset != U32_MAX ? 0 : -ENODEV;
1429 static bool engine_supports_mi_query(struct intel_engine_cs *engine)
1431 return engine->class == RENDER_CLASS;
1435 * oa_get_render_ctx_id - determine and hold ctx hw id
1436 * @stream: An i915-perf stream opened for OA metrics
1438 * Determine the render context hw id, and ensure it remains fixed for the
1439 * lifetime of the stream. This ensures that we don't have to worry about
1440 * updating the context ID in OACONTROL on the fly.
1442 * Returns: zero on success or a negative error code
1444 static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
1446 struct intel_context *ce;
1449 ce = oa_pin_context(stream);
1453 if (engine_supports_mi_query(stream->engine) &&
1454 HAS_LOGICAL_RING_CONTEXTS(stream->perf->i915)) {
1456 * We are enabling perf query here. If we don't find the context
1457 * offset here, just return an error.
1459 ret = set_oa_ctx_ctrl_offset(ce);
1461 intel_context_unpin(ce);
1462 drm_err(&stream->perf->i915->drm,
1463 "Enabling perf query failed for %s\n",
1464 stream->engine->name);
1469 switch (GRAPHICS_VER(ce->engine->i915)) {
1472 * On Haswell we don't do any post processing of the reports
1473 * and don't need to use the mask.
1475 stream->specific_ctx_id = i915_ggtt_offset(ce->state);
1476 stream->specific_ctx_id_mask = 0;
1482 if (intel_engine_uses_guc(ce->engine)) {
1484 * When using GuC, the context descriptor we write in
1485 * i915 is read by GuC and rewritten before it's
1486 * actually written into the hardware. The LRCA is
1487 * what is put into the context id field of the
1488 * context descriptor by GuC. Because it's aligned to
1489 * a page, the lower 12bits are always at 0 and
1490 * dropped by GuC. They won't be part of the context
1491 * ID in the OA reports, so squash those lower bits.
1493 stream->specific_ctx_id = ce->lrc.lrca >> 12;
1496 * GuC uses the top bit to signal proxy submission, so
1499 stream->specific_ctx_id_mask =
1500 (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
1502 stream->specific_ctx_id_mask =
1503 (1U << GEN8_CTX_ID_WIDTH) - 1;
1504 stream->specific_ctx_id = stream->specific_ctx_id_mask;
1510 ret = gen12_get_render_context_id(stream);
1514 MISSING_CASE(GRAPHICS_VER(ce->engine->i915));
1517 ce->tag = stream->specific_ctx_id;
1519 drm_dbg(&stream->perf->i915->drm,
1520 "filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
1521 stream->specific_ctx_id,
1522 stream->specific_ctx_id_mask);
1528 * oa_put_render_ctx_id - counterpart to oa_get_render_ctx_id releases hold
1529 * @stream: An i915-perf stream opened for OA metrics
1531 * In case anything needed doing to ensure the context HW ID would remain valid
1532 * for the lifetime of the stream, then that can be undone here.
1534 static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
1536 struct intel_context *ce;
1538 ce = fetch_and_zero(&stream->pinned_ctx);
1540 ce->tag = 0; /* recomputed on next submission after parking */
1541 intel_context_unpin(ce);
1544 stream->specific_ctx_id = INVALID_CTX_ID;
1545 stream->specific_ctx_id_mask = 0;
1549 free_oa_buffer(struct i915_perf_stream *stream)
1551 i915_vma_unpin_and_release(&stream->oa_buffer.vma,
1552 I915_VMA_RELEASE_MAP);
1554 stream->oa_buffer.vaddr = NULL;
1558 free_oa_configs(struct i915_perf_stream *stream)
1560 struct i915_oa_config_bo *oa_bo, *tmp;
1562 i915_oa_config_put(stream->oa_config);
1563 llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node)
1564 free_oa_config_bo(oa_bo);
1568 free_noa_wait(struct i915_perf_stream *stream)
1570 i915_vma_unpin_and_release(&stream->noa_wait, 0);
1573 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
1575 struct i915_perf *perf = stream->perf;
1576 struct intel_gt *gt = stream->engine->gt;
1578 if (WARN_ON(stream != gt->perf.exclusive_stream))
1582 * Unset exclusive_stream first, it will be checked while disabling
1583 * the metric set on gen8+.
1585 * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
1587 WRITE_ONCE(gt->perf.exclusive_stream, NULL);
1588 perf->ops.disable_metric_set(stream);
1590 free_oa_buffer(stream);
1593 * Wa_16011777198:dg2: Unset the override of GUCRC mode to enable rc6.
1595 if (intel_uc_uses_guc_rc(>->uc) &&
1596 (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
1597 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)))
1598 drm_WARN_ON(>->i915->drm,
1599 intel_guc_slpc_unset_gucrc_mode(>->uc.guc.slpc));
1601 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
1602 intel_engine_pm_put(stream->engine);
1605 oa_put_render_ctx_id(stream);
1607 free_oa_configs(stream);
1608 free_noa_wait(stream);
1610 if (perf->spurious_report_rs.missed) {
1611 drm_notice(>->i915->drm,
1612 "%d spurious OA report notices suppressed due to ratelimiting\n",
1613 perf->spurious_report_rs.missed);
1617 static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
1619 struct intel_uncore *uncore = stream->uncore;
1620 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1621 unsigned long flags;
1623 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1625 /* Pre-DevBDW: OABUFFER must be set with counters off,
1626 * before OASTATUS1, but after OASTATUS2
1628 intel_uncore_write(uncore, GEN7_OASTATUS2, /* head */
1629 gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT);
1630 stream->oa_buffer.head = gtt_offset;
1632 intel_uncore_write(uncore, GEN7_OABUFFER, gtt_offset);
1634 intel_uncore_write(uncore, GEN7_OASTATUS1, /* tail */
1635 gtt_offset | OABUFFER_SIZE_16M);
1637 /* Mark that we need updated tail pointers to read from... */
1638 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1639 stream->oa_buffer.tail = gtt_offset;
1641 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1643 /* On Haswell we have to track which OASTATUS1 flags we've
1644 * already seen since they can't be cleared while periodic
1645 * sampling is enabled.
1647 stream->perf->gen7_latched_oastatus1 = 0;
1649 /* NB: although the OA buffer will initially be allocated
1650 * zeroed via shmfs (and so this memset is redundant when
1651 * first allocating), we may re-init the OA buffer, either
1652 * when re-enabling a stream or in error/reset paths.
1654 * The reason we clear the buffer for each re-init is for the
1655 * sanity check in gen7_append_oa_reports() that looks at the
1656 * report-id field to make sure it's non-zero which relies on
1657 * the assumption that new reports are being written to zeroed
1660 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1663 static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
1665 struct intel_uncore *uncore = stream->uncore;
1666 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1667 unsigned long flags;
1669 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1671 intel_uncore_write(uncore, GEN8_OASTATUS, 0);
1672 intel_uncore_write(uncore, GEN8_OAHEADPTR, gtt_offset);
1673 stream->oa_buffer.head = gtt_offset;
1675 intel_uncore_write(uncore, GEN8_OABUFFER_UDW, 0);
1680 * "This MMIO must be set before the OATAILPTR
1681 * register and after the OAHEADPTR register. This is
1682 * to enable proper functionality of the overflow
1685 intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset |
1686 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1687 intel_uncore_write(uncore, GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
1689 /* Mark that we need updated tail pointers to read from... */
1690 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1691 stream->oa_buffer.tail = gtt_offset;
1694 * Reset state used to recognise context switches, affecting which
1695 * reports we will forward to userspace while filtering for a single
1698 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1700 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1703 * NB: although the OA buffer will initially be allocated
1704 * zeroed via shmfs (and so this memset is redundant when
1705 * first allocating), we may re-init the OA buffer, either
1706 * when re-enabling a stream or in error/reset paths.
1708 * The reason we clear the buffer for each re-init is for the
1709 * sanity check in gen8_append_oa_reports() that looks at the
1710 * reason field to make sure it's non-zero which relies on
1711 * the assumption that new reports are being written to zeroed
1714 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1717 static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
1719 struct intel_uncore *uncore = stream->uncore;
1720 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1721 unsigned long flags;
1723 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1725 intel_uncore_write(uncore, GEN12_OAG_OASTATUS, 0);
1726 intel_uncore_write(uncore, GEN12_OAG_OAHEADPTR,
1727 gtt_offset & GEN12_OAG_OAHEADPTR_MASK);
1728 stream->oa_buffer.head = gtt_offset;
1733 * "This MMIO must be set before the OATAILPTR
1734 * register and after the OAHEADPTR register. This is
1735 * to enable proper functionality of the overflow
1738 intel_uncore_write(uncore, GEN12_OAG_OABUFFER, gtt_offset |
1739 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1740 intel_uncore_write(uncore, GEN12_OAG_OATAILPTR,
1741 gtt_offset & GEN12_OAG_OATAILPTR_MASK);
1743 /* Mark that we need updated tail pointers to read from... */
1744 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1745 stream->oa_buffer.tail = gtt_offset;
1748 * Reset state used to recognise context switches, affecting which
1749 * reports we will forward to userspace while filtering for a single
1752 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1754 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1757 * NB: although the OA buffer will initially be allocated
1758 * zeroed via shmfs (and so this memset is redundant when
1759 * first allocating), we may re-init the OA buffer, either
1760 * when re-enabling a stream or in error/reset paths.
1762 * The reason we clear the buffer for each re-init is for the
1763 * sanity check in gen8_append_oa_reports() that looks at the
1764 * reason field to make sure it's non-zero which relies on
1765 * the assumption that new reports are being written to zeroed
1768 memset(stream->oa_buffer.vaddr, 0,
1769 stream->oa_buffer.vma->size);
1772 static int alloc_oa_buffer(struct i915_perf_stream *stream)
1774 struct drm_i915_private *i915 = stream->perf->i915;
1775 struct intel_gt *gt = stream->engine->gt;
1776 struct drm_i915_gem_object *bo;
1777 struct i915_vma *vma;
1780 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.vma))
1783 BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
1784 BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
1786 bo = i915_gem_object_create_shmem(stream->perf->i915, OA_BUFFER_SIZE);
1788 drm_err(&i915->drm, "Failed to allocate OA buffer\n");
1792 i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
1794 /* PreHSW required 512K alignment, HSW requires 16M */
1795 vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
1802 * PreHSW required 512K alignment.
1803 * HSW and onwards, align to requested size of OA buffer.
1805 ret = i915_vma_pin(vma, 0, SZ_16M, PIN_GLOBAL | PIN_HIGH);
1807 drm_err(>->i915->drm, "Failed to pin OA buffer %d\n", ret);
1811 stream->oa_buffer.vma = vma;
1813 stream->oa_buffer.vaddr =
1814 i915_gem_object_pin_map_unlocked(bo, I915_MAP_WB);
1815 if (IS_ERR(stream->oa_buffer.vaddr)) {
1816 ret = PTR_ERR(stream->oa_buffer.vaddr);
1823 __i915_vma_unpin(vma);
1826 i915_gem_object_put(bo);
1828 stream->oa_buffer.vaddr = NULL;
1829 stream->oa_buffer.vma = NULL;
1834 static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
1835 bool save, i915_reg_t reg, u32 offset,
1841 cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
1842 cmd |= MI_SRM_LRM_GLOBAL_GTT;
1843 if (GRAPHICS_VER(stream->perf->i915) >= 8)
1846 for (d = 0; d < dword_count; d++) {
1848 *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
1849 *cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;
1856 static int alloc_noa_wait(struct i915_perf_stream *stream)
1858 struct drm_i915_private *i915 = stream->perf->i915;
1859 struct intel_gt *gt = stream->engine->gt;
1860 struct drm_i915_gem_object *bo;
1861 struct i915_vma *vma;
1862 const u64 delay_ticks = 0xffffffffffffffff -
1863 intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
1864 atomic64_read(&stream->perf->noa_programming_delay));
1865 const u32 base = stream->engine->mmio_base;
1866 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
1867 u32 *batch, *ts0, *cs, *jump;
1868 struct i915_gem_ww_ctx ww;
1878 i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?
1879 MI_PREDICATE_RESULT_2_ENGINE(base) :
1880 MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
1883 * gt->scratch was being used to save/restore the GPR registers, but on
1884 * MTL the scratch uses stolen lmem. An MI_SRM to this memory region
1885 * causes an engine hang. Instead allocate an additional page here to
1886 * save/restore GPR registers
1888 bo = i915_gem_object_create_internal(i915, 8192);
1891 "Failed to allocate NOA wait batchbuffer\n");
1895 i915_gem_ww_ctx_init(&ww, true);
1897 ret = i915_gem_object_lock(bo, &ww);
1902 * We pin in GGTT because we jump into this buffer now because
1903 * multiple OA config BOs will have a jump to this address and it
1904 * needs to be fixed during the lifetime of the i915/perf stream.
1906 vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
1912 ret = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
1916 batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
1917 if (IS_ERR(batch)) {
1918 ret = PTR_ERR(batch);
1922 stream->noa_wait = vma;
1924 #define GPR_SAVE_OFFSET 4096
1925 #define PREDICATE_SAVE_OFFSET 4160
1927 /* Save registers. */
1928 for (i = 0; i < N_CS_GPR; i++)
1929 cs = save_restore_register(
1930 stream, cs, true /* save */, CS_GPR(i),
1931 GPR_SAVE_OFFSET + 8 * i, 2);
1932 cs = save_restore_register(
1933 stream, cs, true /* save */, mi_predicate_result,
1934 PREDICATE_SAVE_OFFSET, 1);
1936 /* First timestamp snapshot location. */
1940 * Initial snapshot of the timestamp register to implement the wait.
1941 * We work with 32b values, so clear out the top 32b bits of the
1942 * register because the ALU works 64bits.
1944 *cs++ = MI_LOAD_REGISTER_IMM(1);
1945 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;
1947 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1948 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1949 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));
1952 * This is the location we're going to jump back into until the
1953 * required amount of time has passed.
1958 * Take another snapshot of the timestamp register. Take care to clear
1959 * up the top 32bits of CS_GPR(1) as we're using it for other
1962 *cs++ = MI_LOAD_REGISTER_IMM(1);
1963 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;
1965 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1966 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1967 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));
1970 * Do a diff between the 2 timestamps and store the result back into
1974 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
1975 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
1976 *cs++ = MI_MATH_SUB;
1977 *cs++ = MI_MATH_STORE(MI_MATH_REG(DELTA_TS), MI_MATH_REG_ACCU);
1978 *cs++ = MI_MATH_STORE(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
1981 * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
1982 * timestamp have rolled over the 32bits) into the predicate register
1983 * to be used for the predicated jump.
1985 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1986 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1987 *cs++ = i915_mmio_reg_offset(mi_predicate_result);
1989 if (HAS_MI_SET_PREDICATE(i915))
1990 *cs++ = MI_SET_PREDICATE | 1;
1992 /* Restart from the beginning if we had timestamps roll over. */
1993 *cs++ = (GRAPHICS_VER(i915) < 8 ?
1994 MI_BATCH_BUFFER_START :
1995 MI_BATCH_BUFFER_START_GEN8) |
1997 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
2000 if (HAS_MI_SET_PREDICATE(i915))
2001 *cs++ = MI_SET_PREDICATE;
2004 * Now add the diff between to previous timestamps and add it to :
2005 * (((1 * << 64) - 1) - delay_ns)
2007 * When the Carry Flag contains 1 this means the elapsed time is
2008 * longer than the expected delay, and we can exit the wait loop.
2010 *cs++ = MI_LOAD_REGISTER_IMM(2);
2011 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET));
2012 *cs++ = lower_32_bits(delay_ticks);
2013 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4;
2014 *cs++ = upper_32_bits(delay_ticks);
2017 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(DELTA_TS));
2018 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(DELTA_TARGET));
2019 *cs++ = MI_MATH_ADD;
2020 *cs++ = MI_MATH_STOREINV(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
2022 *cs++ = MI_ARB_CHECK;
2025 * Transfer the result into the predicate register to be used for the
2028 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
2029 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
2030 *cs++ = i915_mmio_reg_offset(mi_predicate_result);
2032 if (HAS_MI_SET_PREDICATE(i915))
2033 *cs++ = MI_SET_PREDICATE | 1;
2035 /* Predicate the jump. */
2036 *cs++ = (GRAPHICS_VER(i915) < 8 ?
2037 MI_BATCH_BUFFER_START :
2038 MI_BATCH_BUFFER_START_GEN8) |
2040 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
2043 if (HAS_MI_SET_PREDICATE(i915))
2044 *cs++ = MI_SET_PREDICATE;
2046 /* Restore registers. */
2047 for (i = 0; i < N_CS_GPR; i++)
2048 cs = save_restore_register(
2049 stream, cs, false /* restore */, CS_GPR(i),
2050 GPR_SAVE_OFFSET + 8 * i, 2);
2051 cs = save_restore_register(
2052 stream, cs, false /* restore */, mi_predicate_result,
2053 PREDICATE_SAVE_OFFSET, 1);
2055 /* And return to the ring. */
2056 *cs++ = MI_BATCH_BUFFER_END;
2058 GEM_BUG_ON(cs - batch > PAGE_SIZE / sizeof(*batch));
2060 i915_gem_object_flush_map(bo);
2061 __i915_gem_object_release_map(bo);
2066 i915_vma_unpin_and_release(&vma, 0);
2068 if (ret == -EDEADLK) {
2069 ret = i915_gem_ww_ctx_backoff(&ww);
2073 i915_gem_ww_ctx_fini(&ww);
2075 i915_gem_object_put(bo);
2079 static u32 *write_cs_mi_lri(u32 *cs,
2080 const struct i915_oa_reg *reg_data,
2085 for (i = 0; i < n_regs; i++) {
2086 if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
2087 u32 n_lri = min_t(u32,
2089 MI_LOAD_REGISTER_IMM_MAX_REGS);
2091 *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
2093 *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
2094 *cs++ = reg_data[i].value;
2100 static int num_lri_dwords(int num_regs)
2105 count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS);
2106 count += num_regs * 2;
2112 static struct i915_oa_config_bo *
2113 alloc_oa_config_buffer(struct i915_perf_stream *stream,
2114 struct i915_oa_config *oa_config)
2116 struct drm_i915_gem_object *obj;
2117 struct i915_oa_config_bo *oa_bo;
2118 struct i915_gem_ww_ctx ww;
2119 size_t config_length = 0;
2123 oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
2125 return ERR_PTR(-ENOMEM);
2127 config_length += num_lri_dwords(oa_config->mux_regs_len);
2128 config_length += num_lri_dwords(oa_config->b_counter_regs_len);
2129 config_length += num_lri_dwords(oa_config->flex_regs_len);
2130 config_length += 3; /* MI_BATCH_BUFFER_START */
2131 config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
2133 obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
2139 i915_gem_ww_ctx_init(&ww, true);
2141 err = i915_gem_object_lock(obj, &ww);
2145 cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
2151 cs = write_cs_mi_lri(cs,
2152 oa_config->mux_regs,
2153 oa_config->mux_regs_len);
2154 cs = write_cs_mi_lri(cs,
2155 oa_config->b_counter_regs,
2156 oa_config->b_counter_regs_len);
2157 cs = write_cs_mi_lri(cs,
2158 oa_config->flex_regs,
2159 oa_config->flex_regs_len);
2161 /* Jump into the active wait. */
2162 *cs++ = (GRAPHICS_VER(stream->perf->i915) < 8 ?
2163 MI_BATCH_BUFFER_START :
2164 MI_BATCH_BUFFER_START_GEN8);
2165 *cs++ = i915_ggtt_offset(stream->noa_wait);
2168 i915_gem_object_flush_map(obj);
2169 __i915_gem_object_release_map(obj);
2171 oa_bo->vma = i915_vma_instance(obj,
2172 &stream->engine->gt->ggtt->vm,
2174 if (IS_ERR(oa_bo->vma)) {
2175 err = PTR_ERR(oa_bo->vma);
2179 oa_bo->oa_config = i915_oa_config_get(oa_config);
2180 llist_add(&oa_bo->node, &stream->oa_config_bos);
2183 if (err == -EDEADLK) {
2184 err = i915_gem_ww_ctx_backoff(&ww);
2188 i915_gem_ww_ctx_fini(&ww);
2191 i915_gem_object_put(obj);
2195 return ERR_PTR(err);
2200 static struct i915_vma *
2201 get_oa_vma(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
2203 struct i915_oa_config_bo *oa_bo;
2206 * Look for the buffer in the already allocated BOs attached
2209 llist_for_each_entry(oa_bo, stream->oa_config_bos.first, node) {
2210 if (oa_bo->oa_config == oa_config &&
2211 memcmp(oa_bo->oa_config->uuid,
2213 sizeof(oa_config->uuid)) == 0)
2217 oa_bo = alloc_oa_config_buffer(stream, oa_config);
2219 return ERR_CAST(oa_bo);
2222 return i915_vma_get(oa_bo->vma);
2226 emit_oa_config(struct i915_perf_stream *stream,
2227 struct i915_oa_config *oa_config,
2228 struct intel_context *ce,
2229 struct i915_active *active)
2231 struct i915_request *rq;
2232 struct i915_vma *vma;
2233 struct i915_gem_ww_ctx ww;
2236 vma = get_oa_vma(stream, oa_config);
2238 return PTR_ERR(vma);
2240 i915_gem_ww_ctx_init(&ww, true);
2242 err = i915_gem_object_lock(vma->obj, &ww);
2246 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
2250 intel_engine_pm_get(ce->engine);
2251 rq = i915_request_create(ce);
2252 intel_engine_pm_put(ce->engine);
2258 if (!IS_ERR_OR_NULL(active)) {
2259 /* After all individual context modifications */
2260 err = i915_request_await_active(rq, active,
2261 I915_ACTIVE_AWAIT_ACTIVE);
2263 goto err_add_request;
2265 err = i915_active_add_request(active, rq);
2267 goto err_add_request;
2270 err = i915_vma_move_to_active(vma, rq, 0);
2272 goto err_add_request;
2274 err = rq->engine->emit_bb_start(rq,
2275 i915_vma_offset(vma), 0,
2276 I915_DISPATCH_SECURE);
2278 goto err_add_request;
2281 i915_request_add(rq);
2283 i915_vma_unpin(vma);
2285 if (err == -EDEADLK) {
2286 err = i915_gem_ww_ctx_backoff(&ww);
2291 i915_gem_ww_ctx_fini(&ww);
2296 static struct intel_context *oa_context(struct i915_perf_stream *stream)
2298 return stream->pinned_ctx ?: stream->engine->kernel_context;
2302 hsw_enable_metric_set(struct i915_perf_stream *stream,
2303 struct i915_active *active)
2305 struct intel_uncore *uncore = stream->uncore;
2310 * OA unit is using “crclk” for its functionality. When trunk
2311 * level clock gating takes place, OA clock would be gated,
2312 * unable to count the events from non-render clock domain.
2313 * Render clock gating must be disabled when OA is enabled to
2314 * count the events from non-render domain. Unit level clock
2315 * gating for RCS should also be disabled.
2317 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2318 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
2319 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2320 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
2322 return emit_oa_config(stream,
2323 stream->oa_config, oa_context(stream),
2327 static void hsw_disable_metric_set(struct i915_perf_stream *stream)
2329 struct intel_uncore *uncore = stream->uncore;
2331 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2332 GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0);
2333 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2334 0, GEN7_DOP_CLOCK_GATE_ENABLE);
2336 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2339 static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
2342 u32 mmio = i915_mmio_reg_offset(reg);
2346 * This arbitrary default will select the 'EU FPU0 Pipeline
2347 * Active' event. In the future it's anticipated that there
2348 * will be an explicit 'No Event' we can select, but not yet...
2353 for (i = 0; i < oa_config->flex_regs_len; i++) {
2354 if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
2355 return oa_config->flex_regs[i].value;
2361 * NB: It must always remain pointer safe to run this even if the OA unit
2362 * has been disabled.
2364 * It's fine to put out-of-date values into these per-context registers
2365 * in the case that the OA unit has been disabled.
2368 gen8_update_reg_state_unlocked(const struct intel_context *ce,
2369 const struct i915_perf_stream *stream)
2371 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2372 u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2373 /* The MMIO offsets for Flex EU registers aren't contiguous */
2374 static const i915_reg_t flex_regs[] = {
2383 u32 *reg_state = ce->lrc_reg_state;
2386 reg_state[ctx_oactxctrl + 1] =
2387 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2388 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2389 GEN8_OA_COUNTER_RESUME;
2391 for (i = 0; i < ARRAY_SIZE(flex_regs); i++)
2392 reg_state[ctx_flexeu0 + i * 2 + 1] =
2393 oa_config_flex_reg(stream->oa_config, flex_regs[i]);
2403 gen8_store_flex(struct i915_request *rq,
2404 struct intel_context *ce,
2405 const struct flex *flex, unsigned int count)
2410 cs = intel_ring_begin(rq, 4 * count);
2414 offset = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET;
2416 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
2417 *cs++ = offset + flex->offset * sizeof(u32);
2419 *cs++ = flex->value;
2420 } while (flex++, --count);
2422 intel_ring_advance(rq, cs);
2428 gen8_load_flex(struct i915_request *rq,
2429 struct intel_context *ce,
2430 const struct flex *flex, unsigned int count)
2434 GEM_BUG_ON(!count || count > 63);
2436 cs = intel_ring_begin(rq, 2 * count + 2);
2440 *cs++ = MI_LOAD_REGISTER_IMM(count);
2442 *cs++ = i915_mmio_reg_offset(flex->reg);
2443 *cs++ = flex->value;
2444 } while (flex++, --count);
2447 intel_ring_advance(rq, cs);
2452 static int gen8_modify_context(struct intel_context *ce,
2453 const struct flex *flex, unsigned int count)
2455 struct i915_request *rq;
2458 rq = intel_engine_create_kernel_request(ce->engine);
2462 /* Serialise with the remote context */
2463 err = intel_context_prepare_remote_request(ce, rq);
2465 err = gen8_store_flex(rq, ce, flex, count);
2467 i915_request_add(rq);
2472 gen8_modify_self(struct intel_context *ce,
2473 const struct flex *flex, unsigned int count,
2474 struct i915_active *active)
2476 struct i915_request *rq;
2479 intel_engine_pm_get(ce->engine);
2480 rq = i915_request_create(ce);
2481 intel_engine_pm_put(ce->engine);
2485 if (!IS_ERR_OR_NULL(active)) {
2486 err = i915_active_add_request(active, rq);
2488 goto err_add_request;
2491 err = gen8_load_flex(rq, ce, flex, count);
2493 goto err_add_request;
2496 i915_request_add(rq);
2500 static int gen8_configure_context(struct i915_gem_context *ctx,
2501 struct flex *flex, unsigned int count)
2503 struct i915_gem_engines_iter it;
2504 struct intel_context *ce;
2507 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
2508 GEM_BUG_ON(ce == ce->engine->kernel_context);
2510 if (ce->engine->class != RENDER_CLASS)
2513 /* Otherwise OA settings will be set upon first use */
2514 if (!intel_context_pin_if_active(ce))
2517 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
2518 err = gen8_modify_context(ce, flex, count);
2520 intel_context_unpin(ce);
2524 i915_gem_context_unlock_engines(ctx);
2529 static int gen12_configure_oar_context(struct i915_perf_stream *stream,
2530 struct i915_active *active)
2533 struct intel_context *ce = stream->pinned_ctx;
2534 u32 format = stream->oa_buffer.format->format;
2535 u32 offset = stream->perf->ctx_oactxctrl_offset;
2536 struct flex regs_context[] = {
2540 active ? GEN8_OA_COUNTER_RESUME : 0,
2543 /* Offsets in regs_lri are not used since this configuration is only
2544 * applied using LRI. Initialize the correct offsets for posterity.
2546 #define GEN12_OAR_OACONTROL_OFFSET 0x5B0
2547 struct flex regs_lri[] = {
2549 GEN12_OAR_OACONTROL,
2550 GEN12_OAR_OACONTROL_OFFSET + 1,
2551 (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
2552 (active ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0)
2555 RING_CONTEXT_CONTROL(ce->engine->mmio_base),
2556 CTX_CONTEXT_CONTROL,
2557 _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
2559 GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE :
2564 /* Modify the context image of pinned context with regs_context */
2565 err = intel_context_lock_pinned(ce);
2569 err = gen8_modify_context(ce, regs_context,
2570 ARRAY_SIZE(regs_context));
2571 intel_context_unlock_pinned(ce);
2575 /* Apply regs_lri using LRI with pinned context */
2576 return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), active);
2580 * Manages updating the per-context aspects of the OA stream
2581 * configuration across all contexts.
2583 * The awkward consideration here is that OACTXCONTROL controls the
2584 * exponent for periodic sampling which is primarily used for system
2585 * wide profiling where we'd like a consistent sampling period even in
2586 * the face of context switches.
2588 * Our approach of updating the register state context (as opposed to
2589 * say using a workaround batch buffer) ensures that the hardware
2590 * won't automatically reload an out-of-date timer exponent even
2591 * transiently before a WA BB could be parsed.
2593 * This function needs to:
2594 * - Ensure the currently running context's per-context OA state is
2596 * - Ensure that all existing contexts will have the correct per-context
2597 * OA state if they are scheduled for use.
2598 * - Ensure any new contexts will be initialized with the correct
2599 * per-context OA state.
2601 * Note: it's only the RCS/Render context that has any OA state.
2602 * Note: the first flex register passed must always be R_PWR_CLK_STATE
2605 oa_configure_all_contexts(struct i915_perf_stream *stream,
2608 struct i915_active *active)
2610 struct drm_i915_private *i915 = stream->perf->i915;
2611 struct intel_engine_cs *engine;
2612 struct intel_gt *gt = stream->engine->gt;
2613 struct i915_gem_context *ctx, *cn;
2616 lockdep_assert_held(>->perf.lock);
2619 * The OA register config is setup through the context image. This image
2620 * might be written to by the GPU on context switch (in particular on
2621 * lite-restore). This means we can't safely update a context's image,
2622 * if this context is scheduled/submitted to run on the GPU.
2624 * We could emit the OA register config through the batch buffer but
2625 * this might leave small interval of time where the OA unit is
2626 * configured at an invalid sampling period.
2628 * Note that since we emit all requests from a single ring, there
2629 * is still an implicit global barrier here that may cause a high
2630 * priority context to wait for an otherwise independent low priority
2631 * context. Contexts idle at the time of reconfiguration are not
2632 * trapped behind the barrier.
2634 spin_lock(&i915->gem.contexts.lock);
2635 list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
2636 if (!kref_get_unless_zero(&ctx->ref))
2639 spin_unlock(&i915->gem.contexts.lock);
2641 err = gen8_configure_context(ctx, regs, num_regs);
2643 i915_gem_context_put(ctx);
2647 spin_lock(&i915->gem.contexts.lock);
2648 list_safe_reset_next(ctx, cn, link);
2649 i915_gem_context_put(ctx);
2651 spin_unlock(&i915->gem.contexts.lock);
2654 * After updating all other contexts, we need to modify ourselves.
2655 * If we don't modify the kernel_context, we do not get events while
2658 for_each_uabi_engine(engine, i915) {
2659 struct intel_context *ce = engine->kernel_context;
2661 if (engine->class != RENDER_CLASS)
2664 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
2666 err = gen8_modify_self(ce, regs, num_regs, active);
2675 gen12_configure_all_contexts(struct i915_perf_stream *stream,
2676 const struct i915_oa_config *oa_config,
2677 struct i915_active *active)
2679 struct flex regs[] = {
2681 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
2682 CTX_R_PWR_CLK_STATE,
2686 return oa_configure_all_contexts(stream,
2687 regs, ARRAY_SIZE(regs),
2692 lrc_configure_all_contexts(struct i915_perf_stream *stream,
2693 const struct i915_oa_config *oa_config,
2694 struct i915_active *active)
2696 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2697 /* The MMIO offsets for Flex EU registers aren't contiguous */
2698 const u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2699 #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
2700 struct flex regs[] = {
2702 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
2703 CTX_R_PWR_CLK_STATE,
2709 { EU_PERF_CNTL0, ctx_flexeuN(0) },
2710 { EU_PERF_CNTL1, ctx_flexeuN(1) },
2711 { EU_PERF_CNTL2, ctx_flexeuN(2) },
2712 { EU_PERF_CNTL3, ctx_flexeuN(3) },
2713 { EU_PERF_CNTL4, ctx_flexeuN(4) },
2714 { EU_PERF_CNTL5, ctx_flexeuN(5) },
2715 { EU_PERF_CNTL6, ctx_flexeuN(6) },
2721 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2722 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2723 GEN8_OA_COUNTER_RESUME;
2725 for (i = 2; i < ARRAY_SIZE(regs); i++)
2726 regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
2728 return oa_configure_all_contexts(stream,
2729 regs, ARRAY_SIZE(regs),
2734 gen8_enable_metric_set(struct i915_perf_stream *stream,
2735 struct i915_active *active)
2737 struct intel_uncore *uncore = stream->uncore;
2738 struct i915_oa_config *oa_config = stream->oa_config;
2742 * We disable slice/unslice clock ratio change reports on SKL since
2743 * they are too noisy. The HW generates a lot of redundant reports
2744 * where the ratio hasn't really changed causing a lot of redundant
2745 * work to processes and increasing the chances we'll hit buffer
2748 * Although we don't currently use the 'disable overrun' OABUFFER
2749 * feature it's worth noting that clock ratio reports have to be
2750 * disabled before considering to use that feature since the HW doesn't
2751 * correctly block these reports.
2753 * Currently none of the high-level metrics we have depend on knowing
2754 * this ratio to normalize.
2756 * Note: This register is not power context saved and restored, but
2757 * that's OK considering that we disable RC6 while the OA unit is
2760 * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to
2761 * be read back from automatically triggered reports, as part of the
2764 if (IS_GRAPHICS_VER(stream->perf->i915, 9, 11)) {
2765 intel_uncore_write(uncore, GEN8_OA_DEBUG,
2766 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2767 GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
2771 * Update all contexts prior writing the mux configurations as we need
2772 * to make sure all slices/subslices are ON before writing to NOA
2775 ret = lrc_configure_all_contexts(stream, oa_config, active);
2779 return emit_oa_config(stream,
2780 stream->oa_config, oa_context(stream),
2784 static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream)
2786 return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
2787 (stream->sample_flags & SAMPLE_OA_REPORT) ?
2788 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
2792 gen12_enable_metric_set(struct i915_perf_stream *stream,
2793 struct i915_active *active)
2795 struct drm_i915_private *i915 = stream->perf->i915;
2796 struct intel_uncore *uncore = stream->uncore;
2797 struct i915_oa_config *oa_config = stream->oa_config;
2798 bool periodic = stream->periodic;
2799 u32 period_exponent = stream->period_exponent;
2804 * Wa_1508761755:xehpsdv, dg2
2805 * EU NOA signals behave incorrectly if EU clock gating is enabled.
2806 * Disable thread stall DOP gating and EU DOP gating.
2808 if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
2809 intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
2810 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
2811 intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
2812 _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
2815 intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
2816 /* Disable clk ratio reports, like previous Gens. */
2817 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2818 GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
2820 * If the user didn't require OA reports, instruct
2821 * the hardware not to emit ctx switch reports.
2823 oag_report_ctx_switches(stream));
2825 intel_uncore_write(uncore, GEN12_OAG_OAGLBCTXCTRL, periodic ?
2826 (GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME |
2827 GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE |
2828 (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
2832 * Initialize Super Queue Internal Cnt Register
2833 * Set PMON Enable in order to collect valid metrics.
2834 * Enable byets per clock reporting in OA for XEHPSDV onward.
2836 sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
2837 (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
2839 intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
2842 * Update all contexts prior writing the mux configurations as we need
2843 * to make sure all slices/subslices are ON before writing to NOA
2846 ret = gen12_configure_all_contexts(stream, oa_config, active);
2851 * For Gen12, performance counters are context
2852 * saved/restored. Only enable it for the context that
2856 ret = gen12_configure_oar_context(stream, active);
2861 return emit_oa_config(stream,
2862 stream->oa_config, oa_context(stream),
2866 static void gen8_disable_metric_set(struct i915_perf_stream *stream)
2868 struct intel_uncore *uncore = stream->uncore;
2870 /* Reset all contexts' slices/subslices configurations. */
2871 lrc_configure_all_contexts(stream, NULL, NULL);
2873 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2876 static void gen11_disable_metric_set(struct i915_perf_stream *stream)
2878 struct intel_uncore *uncore = stream->uncore;
2880 /* Reset all contexts' slices/subslices configurations. */
2881 lrc_configure_all_contexts(stream, NULL, NULL);
2883 /* Make sure we disable noa to save power. */
2884 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2887 static void gen12_disable_metric_set(struct i915_perf_stream *stream)
2889 struct intel_uncore *uncore = stream->uncore;
2890 struct drm_i915_private *i915 = stream->perf->i915;
2894 * Wa_1508761755:xehpsdv, dg2
2895 * Enable thread stall DOP gating and EU DOP gating.
2897 if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
2898 intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
2899 _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
2900 intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
2901 _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
2904 /* Reset all contexts' slices/subslices configurations. */
2905 gen12_configure_all_contexts(stream, NULL, NULL);
2907 /* disable the context save/restore or OAR counters */
2909 gen12_configure_oar_context(stream, NULL);
2911 /* Make sure we disable noa to save power. */
2912 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2914 sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
2915 (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
2917 /* Reset PMON Enable to save power. */
2918 intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0);
2921 static void gen7_oa_enable(struct i915_perf_stream *stream)
2923 struct intel_uncore *uncore = stream->uncore;
2924 struct i915_gem_context *ctx = stream->ctx;
2925 u32 ctx_id = stream->specific_ctx_id;
2926 bool periodic = stream->periodic;
2927 u32 period_exponent = stream->period_exponent;
2928 u32 report_format = stream->oa_buffer.format->format;
2931 * Reset buf pointers so we don't forward reports from before now.
2933 * Think carefully if considering trying to avoid this, since it
2934 * also ensures status flags and the buffer itself are cleared
2935 * in error paths, and we have checks for invalid reports based
2936 * on the assumption that certain fields are written to zeroed
2937 * memory which this helps maintains.
2939 gen7_init_oa_buffer(stream);
2941 intel_uncore_write(uncore, GEN7_OACONTROL,
2942 (ctx_id & GEN7_OACONTROL_CTX_MASK) |
2944 GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
2945 (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) |
2946 (report_format << GEN7_OACONTROL_FORMAT_SHIFT) |
2947 (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
2948 GEN7_OACONTROL_ENABLE);
2951 static void gen8_oa_enable(struct i915_perf_stream *stream)
2953 struct intel_uncore *uncore = stream->uncore;
2954 u32 report_format = stream->oa_buffer.format->format;
2957 * Reset buf pointers so we don't forward reports from before now.
2959 * Think carefully if considering trying to avoid this, since it
2960 * also ensures status flags and the buffer itself are cleared
2961 * in error paths, and we have checks for invalid reports based
2962 * on the assumption that certain fields are written to zeroed
2963 * memory which this helps maintains.
2965 gen8_init_oa_buffer(stream);
2968 * Note: we don't rely on the hardware to perform single context
2969 * filtering and instead filter on the cpu based on the context-id
2972 intel_uncore_write(uncore, GEN8_OACONTROL,
2973 (report_format << GEN8_OA_REPORT_FORMAT_SHIFT) |
2974 GEN8_OA_COUNTER_ENABLE);
2977 static void gen12_oa_enable(struct i915_perf_stream *stream)
2979 struct intel_uncore *uncore = stream->uncore;
2980 u32 report_format = stream->oa_buffer.format->format;
2983 * If we don't want OA reports from the OA buffer, then we don't even
2984 * need to program the OAG unit.
2986 if (!(stream->sample_flags & SAMPLE_OA_REPORT))
2989 gen12_init_oa_buffer(stream);
2991 intel_uncore_write(uncore, GEN12_OAG_OACONTROL,
2992 (report_format << GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT) |
2993 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE);
2997 * i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream
2998 * @stream: An i915 perf stream opened for OA metrics
3000 * [Re]enables hardware periodic sampling according to the period configured
3001 * when opening the stream. This also starts a hrtimer that will periodically
3002 * check for data in the circular OA buffer for notifying userspace (e.g.
3003 * during a read() or poll()).
3005 static void i915_oa_stream_enable(struct i915_perf_stream *stream)
3007 stream->pollin = false;
3009 stream->perf->ops.oa_enable(stream);
3011 if (stream->sample_flags & SAMPLE_OA_REPORT)
3012 hrtimer_start(&stream->poll_check_timer,
3013 ns_to_ktime(stream->poll_oa_period),
3014 HRTIMER_MODE_REL_PINNED);
3017 static void gen7_oa_disable(struct i915_perf_stream *stream)
3019 struct intel_uncore *uncore = stream->uncore;
3021 intel_uncore_write(uncore, GEN7_OACONTROL, 0);
3022 if (intel_wait_for_register(uncore,
3023 GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,
3025 drm_err(&stream->perf->i915->drm,
3026 "wait for OA to be disabled timed out\n");
3029 static void gen8_oa_disable(struct i915_perf_stream *stream)
3031 struct intel_uncore *uncore = stream->uncore;
3033 intel_uncore_write(uncore, GEN8_OACONTROL, 0);
3034 if (intel_wait_for_register(uncore,
3035 GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,
3037 drm_err(&stream->perf->i915->drm,
3038 "wait for OA to be disabled timed out\n");
3041 static void gen12_oa_disable(struct i915_perf_stream *stream)
3043 struct intel_uncore *uncore = stream->uncore;
3045 intel_uncore_write(uncore, GEN12_OAG_OACONTROL, 0);
3046 if (intel_wait_for_register(uncore,
3047 GEN12_OAG_OACONTROL,
3048 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE, 0,
3050 drm_err(&stream->perf->i915->drm,
3051 "wait for OA to be disabled timed out\n");
3053 intel_uncore_write(uncore, GEN12_OA_TLB_INV_CR, 1);
3054 if (intel_wait_for_register(uncore,
3055 GEN12_OA_TLB_INV_CR,
3058 drm_err(&stream->perf->i915->drm,
3059 "wait for OA tlb invalidate timed out\n");
3063 * i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream
3064 * @stream: An i915 perf stream opened for OA metrics
3066 * Stops the OA unit from periodically writing counter reports into the
3067 * circular OA buffer. This also stops the hrtimer that periodically checks for
3068 * data in the circular OA buffer, for notifying userspace.
3070 static void i915_oa_stream_disable(struct i915_perf_stream *stream)
3072 stream->perf->ops.oa_disable(stream);
3074 if (stream->sample_flags & SAMPLE_OA_REPORT)
3075 hrtimer_cancel(&stream->poll_check_timer);
3078 static const struct i915_perf_stream_ops i915_oa_stream_ops = {
3079 .destroy = i915_oa_stream_destroy,
3080 .enable = i915_oa_stream_enable,
3081 .disable = i915_oa_stream_disable,
3082 .wait_unlocked = i915_oa_wait_unlocked,
3083 .poll_wait = i915_oa_poll_wait,
3084 .read = i915_oa_read,
3087 static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
3089 struct i915_active *active;
3092 active = i915_active_create();
3096 err = stream->perf->ops.enable_metric_set(stream, active);
3098 __i915_active_wait(active, TASK_UNINTERRUPTIBLE);
3100 i915_active_put(active);
3105 get_default_sseu_config(struct intel_sseu *out_sseu,
3106 struct intel_engine_cs *engine)
3108 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
3110 *out_sseu = intel_sseu_from_device_info(devinfo_sseu);
3112 if (GRAPHICS_VER(engine->i915) == 11) {
3114 * We only need subslice count so it doesn't matter which ones
3115 * we select - just turn off low bits in the amount of half of
3116 * all available subslices per slice.
3118 out_sseu->subslice_mask =
3119 ~(~0 << (hweight8(out_sseu->subslice_mask) / 2));
3120 out_sseu->slice_mask = 0x1;
3125 get_sseu_config(struct intel_sseu *out_sseu,
3126 struct intel_engine_cs *engine,
3127 const struct drm_i915_gem_context_param_sseu *drm_sseu)
3129 if (drm_sseu->engine.engine_class != engine->uabi_class ||
3130 drm_sseu->engine.engine_instance != engine->uabi_instance)
3133 return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
3137 * OA timestamp frequency = CS timestamp frequency in most platforms. On some
3138 * platforms OA unit ignores the CTC_SHIFT and the 2 timestamps differ. In such
3139 * cases, return the adjusted CS timestamp frequency to the user.
3141 u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
3144 * Wa_18013179988:dg2
3145 * Wa_14015846243:mtl
3147 if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
3148 intel_wakeref_t wakeref;
3151 with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref)
3152 reg = intel_uncore_read(to_gt(i915)->uncore, RPM_CONFIG0);
3154 shift = REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK,
3157 return to_gt(i915)->clock_frequency << (3 - shift);
3160 return to_gt(i915)->clock_frequency;
3164 * i915_oa_stream_init - validate combined props for OA stream and init
3165 * @stream: An i915 perf stream
3166 * @param: The open parameters passed to `DRM_I915_PERF_OPEN`
3167 * @props: The property state that configures stream (individually validated)
3169 * While read_properties_unlocked() validates properties in isolation it
3170 * doesn't ensure that the combination necessarily makes sense.
3172 * At this point it has been determined that userspace wants a stream of
3173 * OA metrics, but still we need to further validate the combined
3174 * properties are OK.
3176 * If the configuration makes sense then we can allocate memory for
3177 * a circular OA buffer and apply the requested metric set configuration.
3179 * Returns: zero on success or a negative error code.
3181 static int i915_oa_stream_init(struct i915_perf_stream *stream,
3182 struct drm_i915_perf_open_param *param,
3183 struct perf_open_properties *props)
3185 struct drm_i915_private *i915 = stream->perf->i915;
3186 struct i915_perf *perf = stream->perf;
3187 struct intel_gt *gt;
3190 if (!props->engine) {
3191 drm_dbg(&stream->perf->i915->drm,
3192 "OA engine not specified\n");
3195 gt = props->engine->gt;
3198 * If the sysfs metrics/ directory wasn't registered for some
3199 * reason then don't let userspace try their luck with config
3202 if (!perf->metrics_kobj) {
3203 drm_dbg(&stream->perf->i915->drm,
3204 "OA metrics weren't advertised via sysfs\n");
3208 if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
3209 (GRAPHICS_VER(perf->i915) < 12 || !stream->ctx)) {
3210 drm_dbg(&stream->perf->i915->drm,
3211 "Only OA report sampling supported\n");
3215 if (!perf->ops.enable_metric_set) {
3216 drm_dbg(&stream->perf->i915->drm,
3217 "OA unit not supported\n");
3222 * To avoid the complexity of having to accurately filter
3223 * counter reports and marshal to the appropriate client
3224 * we currently only allow exclusive access
3226 if (gt->perf.exclusive_stream) {
3227 drm_dbg(&stream->perf->i915->drm,
3228 "OA unit already in use\n");
3232 if (!props->oa_format) {
3233 drm_dbg(&stream->perf->i915->drm,
3234 "OA report format not specified\n");
3238 stream->engine = props->engine;
3239 stream->uncore = stream->engine->gt->uncore;
3241 stream->sample_size = sizeof(struct drm_i915_perf_record_header);
3243 stream->oa_buffer.format = &perf->oa_formats[props->oa_format];
3244 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.format->size == 0))
3247 stream->sample_flags = props->sample_flags;
3248 stream->sample_size += stream->oa_buffer.format->size;
3250 stream->hold_preemption = props->hold_preemption;
3252 stream->periodic = props->oa_periodic;
3253 if (stream->periodic)
3254 stream->period_exponent = props->oa_period_exponent;
3257 ret = oa_get_render_ctx_id(stream);
3259 drm_dbg(&stream->perf->i915->drm,
3260 "Invalid context id to filter with\n");
3265 ret = alloc_noa_wait(stream);
3267 drm_dbg(&stream->perf->i915->drm,
3268 "Unable to allocate NOA wait batch buffer\n");
3269 goto err_noa_wait_alloc;
3272 stream->oa_config = i915_perf_get_oa_config(perf, props->metrics_set);
3273 if (!stream->oa_config) {
3274 drm_dbg(&stream->perf->i915->drm,
3275 "Invalid OA config id=%i\n", props->metrics_set);
3280 /* PRM - observability performance counters:
3282 * OACONTROL, performance counter enable, note:
3284 * "When this bit is set, in order to have coherent counts,
3285 * RC6 power state and trunk clock gating must be disabled.
3286 * This can be achieved by programming MMIO registers as
3287 * 0xA094=0 and 0xA090[31]=1"
3289 * In our case we are expecting that taking pm + FORCEWAKE
3290 * references will effectively disable RC6.
3292 intel_engine_pm_get(stream->engine);
3293 intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
3296 * Wa_16011777198:dg2: GuC resets render as part of the Wa. This causes
3297 * OA to lose the configuration state. Prevent this by overriding GUCRC
3300 if (intel_uc_uses_guc_rc(>->uc) &&
3301 (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
3302 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))) {
3303 ret = intel_guc_slpc_override_gucrc_mode(>->uc.guc.slpc,
3304 SLPC_GUCRC_MODE_GUCRC_NO_RC6);
3306 drm_dbg(&stream->perf->i915->drm,
3307 "Unable to override gucrc mode\n");
3312 ret = alloc_oa_buffer(stream);
3314 goto err_oa_buf_alloc;
3316 stream->ops = &i915_oa_stream_ops;
3318 stream->engine->gt->perf.sseu = props->sseu;
3319 WRITE_ONCE(gt->perf.exclusive_stream, stream);
3321 ret = i915_perf_stream_enable_sync(stream);
3323 drm_dbg(&stream->perf->i915->drm,
3324 "Unable to enable metric set\n");
3328 drm_dbg(&stream->perf->i915->drm,
3329 "opening stream oa config uuid=%s\n",
3330 stream->oa_config->uuid);
3332 hrtimer_init(&stream->poll_check_timer,
3333 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3334 stream->poll_check_timer.function = oa_poll_check_timer_cb;
3335 init_waitqueue_head(&stream->poll_wq);
3336 spin_lock_init(&stream->oa_buffer.ptr_lock);
3337 mutex_init(&stream->lock);
3342 WRITE_ONCE(gt->perf.exclusive_stream, NULL);
3343 perf->ops.disable_metric_set(stream);
3345 free_oa_buffer(stream);
3348 free_oa_configs(stream);
3350 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
3351 intel_engine_pm_put(stream->engine);
3354 free_noa_wait(stream);
3358 oa_put_render_ctx_id(stream);
3363 void i915_oa_init_reg_state(const struct intel_context *ce,
3364 const struct intel_engine_cs *engine)
3366 struct i915_perf_stream *stream;
3368 if (engine->class != RENDER_CLASS)
3371 /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
3372 stream = READ_ONCE(engine->gt->perf.exclusive_stream);
3373 if (stream && GRAPHICS_VER(stream->perf->i915) < 12)
3374 gen8_update_reg_state_unlocked(ce, stream);
3378 * i915_perf_read - handles read() FOP for i915 perf stream FDs
3379 * @file: An i915 perf stream file
3380 * @buf: destination buffer given by userspace
3381 * @count: the number of bytes userspace wants to read
3382 * @ppos: (inout) file seek position (unused)
3384 * The entry point for handling a read() on a stream file descriptor from
3385 * userspace. Most of the work is left to the i915_perf_read_locked() and
3386 * &i915_perf_stream_ops->read but to save having stream implementations (of
3387 * which we might have multiple later) we handle blocking read here.
3389 * We can also consistently treat trying to read from a disabled stream
3390 * as an IO error so implementations can assume the stream is enabled
3393 * Returns: The number of bytes copied or a negative error code on failure.
3395 static ssize_t i915_perf_read(struct file *file,
3400 struct i915_perf_stream *stream = file->private_data;
3404 /* To ensure it's handled consistently we simply treat all reads of a
3405 * disabled stream as an error. In particular it might otherwise lead
3406 * to a deadlock for blocking file descriptors...
3408 if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT))
3411 if (!(file->f_flags & O_NONBLOCK)) {
3412 /* There's the small chance of false positives from
3413 * stream->ops->wait_unlocked.
3415 * E.g. with single context filtering since we only wait until
3416 * oabuffer has >= 1 report we don't immediately know whether
3417 * any reports really belong to the current context
3420 ret = stream->ops->wait_unlocked(stream);
3424 mutex_lock(&stream->lock);
3425 ret = stream->ops->read(stream, buf, count, &offset);
3426 mutex_unlock(&stream->lock);
3427 } while (!offset && !ret);
3429 mutex_lock(&stream->lock);
3430 ret = stream->ops->read(stream, buf, count, &offset);
3431 mutex_unlock(&stream->lock);
3434 /* We allow the poll checking to sometimes report false positive EPOLLIN
3435 * events where we might actually report EAGAIN on read() if there's
3436 * not really any data available. In this situation though we don't
3437 * want to enter a busy loop between poll() reporting a EPOLLIN event
3438 * and read() returning -EAGAIN. Clearing the oa.pollin state here
3439 * effectively ensures we back off until the next hrtimer callback
3440 * before reporting another EPOLLIN event.
3441 * The exception to this is if ops->read() returned -ENOSPC which means
3442 * that more OA data is available than could fit in the user provided
3443 * buffer. In this case we want the next poll() call to not block.
3446 stream->pollin = false;
3448 /* Possible values for ret are 0, -EFAULT, -ENOSPC, -EIO, ... */
3449 return offset ?: (ret ?: -EAGAIN);
3452 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer)
3454 struct i915_perf_stream *stream =
3455 container_of(hrtimer, typeof(*stream), poll_check_timer);
3457 if (oa_buffer_check_unlocked(stream)) {
3458 stream->pollin = true;
3459 wake_up(&stream->poll_wq);
3462 hrtimer_forward_now(hrtimer,
3463 ns_to_ktime(stream->poll_oa_period));
3465 return HRTIMER_RESTART;
3469 * i915_perf_poll_locked - poll_wait() with a suitable wait queue for stream
3470 * @stream: An i915 perf stream
3471 * @file: An i915 perf stream file
3472 * @wait: poll() state table
3474 * For handling userspace polling on an i915 perf stream, this calls through to
3475 * &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
3476 * will be woken for new stream data.
3478 * Returns: any poll events that are ready without sleeping
3480 static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
3484 __poll_t events = 0;
3486 stream->ops->poll_wait(stream, file, wait);
3488 /* Note: we don't explicitly check whether there's something to read
3489 * here since this path may be very hot depending on what else
3490 * userspace is polling, or on the timeout in use. We rely solely on
3491 * the hrtimer/oa_poll_check_timer_cb to notify us when there are
3501 * i915_perf_poll - call poll_wait() with a suitable wait queue for stream
3502 * @file: An i915 perf stream file
3503 * @wait: poll() state table
3505 * For handling userspace polling on an i915 perf stream, this ensures
3506 * poll_wait() gets called with a wait queue that will be woken for new stream
3509 * Note: Implementation deferred to i915_perf_poll_locked()
3511 * Returns: any poll events that are ready without sleeping
3513 static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
3515 struct i915_perf_stream *stream = file->private_data;
3518 mutex_lock(&stream->lock);
3519 ret = i915_perf_poll_locked(stream, file, wait);
3520 mutex_unlock(&stream->lock);
3526 * i915_perf_enable_locked - handle `I915_PERF_IOCTL_ENABLE` ioctl
3527 * @stream: A disabled i915 perf stream
3529 * [Re]enables the associated capture of data for this stream.
3531 * If a stream was previously enabled then there's currently no intention
3532 * to provide userspace any guarantee about the preservation of previously
3535 static void i915_perf_enable_locked(struct i915_perf_stream *stream)
3537 if (stream->enabled)
3540 /* Allow stream->ops->enable() to refer to this */
3541 stream->enabled = true;
3543 if (stream->ops->enable)
3544 stream->ops->enable(stream);
3546 if (stream->hold_preemption)
3547 intel_context_set_nopreempt(stream->pinned_ctx);
3551 * i915_perf_disable_locked - handle `I915_PERF_IOCTL_DISABLE` ioctl
3552 * @stream: An enabled i915 perf stream
3554 * Disables the associated capture of data for this stream.
3556 * The intention is that disabling an re-enabling a stream will ideally be
3557 * cheaper than destroying and re-opening a stream with the same configuration,
3558 * though there are no formal guarantees about what state or buffered data
3559 * must be retained between disabling and re-enabling a stream.
3561 * Note: while a stream is disabled it's considered an error for userspace
3562 * to attempt to read from the stream (-EIO).
3564 static void i915_perf_disable_locked(struct i915_perf_stream *stream)
3566 if (!stream->enabled)
3569 /* Allow stream->ops->disable() to refer to this */
3570 stream->enabled = false;
3572 if (stream->hold_preemption)
3573 intel_context_clear_nopreempt(stream->pinned_ctx);
3575 if (stream->ops->disable)
3576 stream->ops->disable(stream);
3579 static long i915_perf_config_locked(struct i915_perf_stream *stream,
3580 unsigned long metrics_set)
3582 struct i915_oa_config *config;
3583 long ret = stream->oa_config->id;
3585 config = i915_perf_get_oa_config(stream->perf, metrics_set);
3589 if (config != stream->oa_config) {
3593 * If OA is bound to a specific context, emit the
3594 * reconfiguration inline from that context. The update
3595 * will then be ordered with respect to submission on that
3598 * When set globally, we use a low priority kernel context,
3599 * so it will effectively take effect when idle.
3601 err = emit_oa_config(stream, config, oa_context(stream), NULL);
3603 config = xchg(&stream->oa_config, config);
3608 i915_oa_config_put(config);
3614 * i915_perf_ioctl_locked - support ioctl() usage with i915 perf stream FDs
3615 * @stream: An i915 perf stream
3616 * @cmd: the ioctl request
3617 * @arg: the ioctl data
3619 * Returns: zero on success or a negative error code. Returns -EINVAL for
3620 * an unknown ioctl request.
3622 static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
3627 case I915_PERF_IOCTL_ENABLE:
3628 i915_perf_enable_locked(stream);
3630 case I915_PERF_IOCTL_DISABLE:
3631 i915_perf_disable_locked(stream);
3633 case I915_PERF_IOCTL_CONFIG:
3634 return i915_perf_config_locked(stream, arg);
3641 * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
3642 * @file: An i915 perf stream file
3643 * @cmd: the ioctl request
3644 * @arg: the ioctl data
3646 * Implementation deferred to i915_perf_ioctl_locked().
3648 * Returns: zero on success or a negative error code. Returns -EINVAL for
3649 * an unknown ioctl request.
3651 static long i915_perf_ioctl(struct file *file,
3655 struct i915_perf_stream *stream = file->private_data;
3658 mutex_lock(&stream->lock);
3659 ret = i915_perf_ioctl_locked(stream, cmd, arg);
3660 mutex_unlock(&stream->lock);
3666 * i915_perf_destroy_locked - destroy an i915 perf stream
3667 * @stream: An i915 perf stream
3669 * Frees all resources associated with the given i915 perf @stream, disabling
3670 * any associated data capture in the process.
3672 * Note: The >->perf.lock mutex has been taken to serialize
3673 * with any non-file-operation driver hooks.
3675 static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
3677 if (stream->enabled)
3678 i915_perf_disable_locked(stream);
3680 if (stream->ops->destroy)
3681 stream->ops->destroy(stream);
3684 i915_gem_context_put(stream->ctx);
3690 * i915_perf_release - handles userspace close() of a stream file
3691 * @inode: anonymous inode associated with file
3692 * @file: An i915 perf stream file
3694 * Cleans up any resources associated with an open i915 perf stream file.
3696 * NB: close() can't really fail from the userspace point of view.
3698 * Returns: zero on success or a negative error code.
3700 static int i915_perf_release(struct inode *inode, struct file *file)
3702 struct i915_perf_stream *stream = file->private_data;
3703 struct i915_perf *perf = stream->perf;
3704 struct intel_gt *gt = stream->engine->gt;
3707 * Within this call, we know that the fd is being closed and we have no
3708 * other user of stream->lock. Use the perf lock to destroy the stream
3711 mutex_lock(>->perf.lock);
3712 i915_perf_destroy_locked(stream);
3713 mutex_unlock(>->perf.lock);
3715 /* Release the reference the perf stream kept on the driver. */
3716 drm_dev_put(&perf->i915->drm);
3722 static const struct file_operations fops = {
3723 .owner = THIS_MODULE,
3724 .llseek = no_llseek,
3725 .release = i915_perf_release,
3726 .poll = i915_perf_poll,
3727 .read = i915_perf_read,
3728 .unlocked_ioctl = i915_perf_ioctl,
3729 /* Our ioctl have no arguments, so it's safe to use the same function
3730 * to handle 32bits compatibility.
3732 .compat_ioctl = i915_perf_ioctl,
3737 * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD
3738 * @perf: i915 perf instance
3739 * @param: The open parameters passed to 'DRM_I915_PERF_OPEN`
3740 * @props: individually validated u64 property value pairs
3743 * See i915_perf_ioctl_open() for interface details.
3745 * Implements further stream config validation and stream initialization on
3746 * behalf of i915_perf_open_ioctl() with the >->perf.lock mutex
3747 * taken to serialize with any non-file-operation driver hooks.
3749 * Note: at this point the @props have only been validated in isolation and
3750 * it's still necessary to validate that the combination of properties makes
3753 * In the case where userspace is interested in OA unit metrics then further
3754 * config validation and stream initialization details will be handled by
3755 * i915_oa_stream_init(). The code here should only validate config state that
3756 * will be relevant to all stream types / backends.
3758 * Returns: zero on success or a negative error code.
3761 i915_perf_open_ioctl_locked(struct i915_perf *perf,
3762 struct drm_i915_perf_open_param *param,
3763 struct perf_open_properties *props,
3764 struct drm_file *file)
3766 struct i915_gem_context *specific_ctx = NULL;
3767 struct i915_perf_stream *stream = NULL;
3768 unsigned long f_flags = 0;
3769 bool privileged_op = true;
3773 if (props->single_context) {
3774 u32 ctx_handle = props->ctx_handle;
3775 struct drm_i915_file_private *file_priv = file->driver_priv;
3777 specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle);
3778 if (IS_ERR(specific_ctx)) {
3779 drm_dbg(&perf->i915->drm,
3780 "Failed to look up context with ID %u for opening perf stream\n",
3782 ret = PTR_ERR(specific_ctx);
3788 * On Haswell the OA unit supports clock gating off for a specific
3789 * context and in this mode there's no visibility of metrics for the
3790 * rest of the system, which we consider acceptable for a
3791 * non-privileged client.
3793 * For Gen8->11 the OA unit no longer supports clock gating off for a
3794 * specific context and the kernel can't securely stop the counters
3795 * from updating as system-wide / global values. Even though we can
3796 * filter reports based on the included context ID we can't block
3797 * clients from seeing the raw / global counter values via
3798 * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
3799 * enable the OA unit by default.
3801 * For Gen12+ we gain a new OAR unit that only monitors the RCS on a
3802 * per context basis. So we can relax requirements there if the user
3803 * doesn't request global stream access (i.e. query based sampling
3804 * using MI_RECORD_PERF_COUNT.
3806 if (IS_HASWELL(perf->i915) && specific_ctx)
3807 privileged_op = false;
3808 else if (GRAPHICS_VER(perf->i915) == 12 && specific_ctx &&
3809 (props->sample_flags & SAMPLE_OA_REPORT) == 0)
3810 privileged_op = false;
3812 if (props->hold_preemption) {
3813 if (!props->single_context) {
3814 drm_dbg(&perf->i915->drm,
3815 "preemption disable with no context\n");
3819 privileged_op = true;
3823 * Asking for SSEU configuration is a priviliged operation.
3825 if (props->has_sseu)
3826 privileged_op = true;
3828 get_default_sseu_config(&props->sseu, props->engine);
3830 /* Similar to perf's kernel.perf_paranoid_cpu sysctl option
3831 * we check a dev.i915.perf_stream_paranoid sysctl option
3832 * to determine if it's ok to access system wide OA counters
3833 * without CAP_PERFMON or CAP_SYS_ADMIN privileges.
3835 if (privileged_op &&
3836 i915_perf_stream_paranoid && !perfmon_capable()) {
3837 drm_dbg(&perf->i915->drm,
3838 "Insufficient privileges to open i915 perf stream\n");
3843 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
3849 stream->perf = perf;
3850 stream->ctx = specific_ctx;
3851 stream->poll_oa_period = props->poll_oa_period;
3853 ret = i915_oa_stream_init(stream, param, props);
3857 /* we avoid simply assigning stream->sample_flags = props->sample_flags
3858 * to have _stream_init check the combination of sample flags more
3859 * thoroughly, but still this is the expected result at this point.
3861 if (WARN_ON(stream->sample_flags != props->sample_flags)) {
3866 if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
3867 f_flags |= O_CLOEXEC;
3868 if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
3869 f_flags |= O_NONBLOCK;
3871 stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags);
3872 if (stream_fd < 0) {
3877 if (!(param->flags & I915_PERF_FLAG_DISABLED))
3878 i915_perf_enable_locked(stream);
3880 /* Take a reference on the driver that will be kept with stream_fd
3881 * until its release.
3883 drm_dev_get(&perf->i915->drm);
3888 if (stream->ops->destroy)
3889 stream->ops->destroy(stream);
3894 i915_gem_context_put(specific_ctx);
3899 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
3901 u64 nom = (2ULL << exponent) * NSEC_PER_SEC;
3902 u32 den = i915_perf_oa_timestamp_frequency(perf->i915);
3904 return div_u64(nom + den - 1, den);
3907 static __always_inline bool
3908 oa_format_valid(struct i915_perf *perf, enum drm_i915_oa_format format)
3910 return test_bit(format, perf->format_mask);
3913 static __always_inline void
3914 oa_format_add(struct i915_perf *perf, enum drm_i915_oa_format format)
3916 __set_bit(format, perf->format_mask);
3920 * read_properties_unlocked - validate + copy userspace stream open properties
3921 * @perf: i915 perf instance
3922 * @uprops: The array of u64 key value pairs given by userspace
3923 * @n_props: The number of key value pairs expected in @uprops
3924 * @props: The stream configuration built up while validating properties
3926 * Note this function only validates properties in isolation it doesn't
3927 * validate that the combination of properties makes sense or that all
3928 * properties necessary for a particular kind of stream have been set.
3930 * Note that there currently aren't any ordering requirements for properties so
3931 * we shouldn't validate or assume anything about ordering here. This doesn't
3932 * rule out defining new properties with ordering requirements in the future.
3934 static int read_properties_unlocked(struct i915_perf *perf,
3937 struct perf_open_properties *props)
3939 u64 __user *uprop = uprops;
3943 memset(props, 0, sizeof(struct perf_open_properties));
3944 props->poll_oa_period = DEFAULT_POLL_PERIOD_NS;
3947 drm_dbg(&perf->i915->drm,
3948 "No i915 perf properties given\n");
3952 /* At the moment we only support using i915-perf on the RCS. */
3953 props->engine = intel_engine_lookup_user(perf->i915,
3954 I915_ENGINE_CLASS_RENDER,
3956 if (!props->engine) {
3957 drm_dbg(&perf->i915->drm,
3958 "No RENDER-capable engines\n");
3962 /* Considering that ID = 0 is reserved and assuming that we don't
3963 * (currently) expect any configurations to ever specify duplicate
3964 * values for a particular property ID then the last _PROP_MAX value is
3965 * one greater than the maximum number of properties we expect to get
3968 if (n_props >= DRM_I915_PERF_PROP_MAX) {
3969 drm_dbg(&perf->i915->drm,
3970 "More i915 perf properties specified than exist\n");
3974 for (i = 0; i < n_props; i++) {
3975 u64 oa_period, oa_freq_hz;
3978 ret = get_user(id, uprop);
3982 ret = get_user(value, uprop + 1);
3986 if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) {
3987 drm_dbg(&perf->i915->drm,
3988 "Unknown i915 perf property ID\n");
3992 switch ((enum drm_i915_perf_property_id)id) {
3993 case DRM_I915_PERF_PROP_CTX_HANDLE:
3994 props->single_context = 1;
3995 props->ctx_handle = value;
3997 case DRM_I915_PERF_PROP_SAMPLE_OA:
3999 props->sample_flags |= SAMPLE_OA_REPORT;
4001 case DRM_I915_PERF_PROP_OA_METRICS_SET:
4003 drm_dbg(&perf->i915->drm,
4004 "Unknown OA metric set ID\n");
4007 props->metrics_set = value;
4009 case DRM_I915_PERF_PROP_OA_FORMAT:
4010 if (value == 0 || value >= I915_OA_FORMAT_MAX) {
4011 drm_dbg(&perf->i915->drm,
4012 "Out-of-range OA report format %llu\n",
4016 if (!oa_format_valid(perf, value)) {
4017 drm_dbg(&perf->i915->drm,
4018 "Unsupported OA report format %llu\n",
4022 props->oa_format = value;
4024 case DRM_I915_PERF_PROP_OA_EXPONENT:
4025 if (value > OA_EXPONENT_MAX) {
4026 drm_dbg(&perf->i915->drm,
4027 "OA timer exponent too high (> %u)\n",
4032 /* Theoretically we can program the OA unit to sample
4033 * e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns
4034 * for BXT. We don't allow such high sampling
4035 * frequencies by default unless root.
4038 BUILD_BUG_ON(sizeof(oa_period) != 8);
4039 oa_period = oa_exponent_to_ns(perf, value);
4041 /* This check is primarily to ensure that oa_period <=
4042 * UINT32_MAX (before passing to do_div which only
4043 * accepts a u32 denominator), but we can also skip
4044 * checking anything < 1Hz which implicitly can't be
4045 * limited via an integer oa_max_sample_rate.
4047 if (oa_period <= NSEC_PER_SEC) {
4048 u64 tmp = NSEC_PER_SEC;
4049 do_div(tmp, oa_period);
4054 if (oa_freq_hz > i915_oa_max_sample_rate && !perfmon_capable()) {
4055 drm_dbg(&perf->i915->drm,
4056 "OA exponent would exceed the max sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without CAP_PERFMON or CAP_SYS_ADMIN privileges\n",
4057 i915_oa_max_sample_rate);
4061 props->oa_periodic = true;
4062 props->oa_period_exponent = value;
4064 case DRM_I915_PERF_PROP_HOLD_PREEMPTION:
4065 props->hold_preemption = !!value;
4067 case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
4068 struct drm_i915_gem_context_param_sseu user_sseu;
4070 if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
4071 drm_dbg(&perf->i915->drm,
4072 "SSEU config not supported on gfx %x\n",
4073 GRAPHICS_VER_FULL(perf->i915));
4077 if (copy_from_user(&user_sseu,
4078 u64_to_user_ptr(value),
4079 sizeof(user_sseu))) {
4080 drm_dbg(&perf->i915->drm,
4081 "Unable to copy global sseu parameter\n");
4085 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
4087 drm_dbg(&perf->i915->drm,
4088 "Invalid SSEU configuration\n");
4091 props->has_sseu = true;
4094 case DRM_I915_PERF_PROP_POLL_OA_PERIOD:
4095 if (value < 100000 /* 100us */) {
4096 drm_dbg(&perf->i915->drm,
4097 "OA availability timer too small (%lluns < 100us)\n",
4101 props->poll_oa_period = value;
4103 case DRM_I915_PERF_PROP_MAX:
4115 * i915_perf_open_ioctl - DRM ioctl() for userspace to open a stream FD
4117 * @data: ioctl data copied from userspace (unvalidated)
4120 * Validates the stream open parameters given by userspace including flags
4121 * and an array of u64 key, value pair properties.
4123 * Very little is assumed up front about the nature of the stream being
4124 * opened (for instance we don't assume it's for periodic OA unit metrics). An
4125 * i915-perf stream is expected to be a suitable interface for other forms of
4126 * buffered data written by the GPU besides periodic OA metrics.
4128 * Note we copy the properties from userspace outside of the i915 perf
4129 * mutex to avoid an awkward lockdep with mmap_lock.
4131 * Most of the implementation details are handled by
4132 * i915_perf_open_ioctl_locked() after taking the >->perf.lock
4133 * mutex for serializing with any non-file-operation driver hooks.
4135 * Return: A newly opened i915 Perf stream file descriptor or negative
4136 * error code on failure.
4138 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
4139 struct drm_file *file)
4141 struct i915_perf *perf = &to_i915(dev)->perf;
4142 struct drm_i915_perf_open_param *param = data;
4143 struct intel_gt *gt;
4144 struct perf_open_properties props;
4145 u32 known_open_flags;
4149 drm_dbg(&perf->i915->drm,
4150 "i915 perf interface not available for this system\n");
4154 known_open_flags = I915_PERF_FLAG_FD_CLOEXEC |
4155 I915_PERF_FLAG_FD_NONBLOCK |
4156 I915_PERF_FLAG_DISABLED;
4157 if (param->flags & ~known_open_flags) {
4158 drm_dbg(&perf->i915->drm,
4159 "Unknown drm_i915_perf_open_param flag\n");
4163 ret = read_properties_unlocked(perf,
4164 u64_to_user_ptr(param->properties_ptr),
4165 param->num_properties,
4170 gt = props.engine->gt;
4172 mutex_lock(>->perf.lock);
4173 ret = i915_perf_open_ioctl_locked(perf, param, &props, file);
4174 mutex_unlock(>->perf.lock);
4180 * i915_perf_register - exposes i915-perf to userspace
4181 * @i915: i915 device instance
4183 * In particular OA metric sets are advertised under a sysfs metrics/
4184 * directory allowing userspace to enumerate valid IDs that can be
4185 * used to open an i915-perf stream.
4187 void i915_perf_register(struct drm_i915_private *i915)
4189 struct i915_perf *perf = &i915->perf;
4190 struct intel_gt *gt = to_gt(i915);
4195 /* To be sure we're synchronized with an attempted
4196 * i915_perf_open_ioctl(); considering that we register after
4197 * being exposed to userspace.
4199 mutex_lock(>->perf.lock);
4201 perf->metrics_kobj =
4202 kobject_create_and_add("metrics",
4203 &i915->drm.primary->kdev->kobj);
4205 mutex_unlock(>->perf.lock);
4209 * i915_perf_unregister - hide i915-perf from userspace
4210 * @i915: i915 device instance
4212 * i915-perf state cleanup is split up into an 'unregister' and
4213 * 'deinit' phase where the interface is first hidden from
4214 * userspace by i915_perf_unregister() before cleaning up
4215 * remaining state in i915_perf_fini().
4217 void i915_perf_unregister(struct drm_i915_private *i915)
4219 struct i915_perf *perf = &i915->perf;
4221 if (!perf->metrics_kobj)
4224 kobject_put(perf->metrics_kobj);
4225 perf->metrics_kobj = NULL;
4228 static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)
4230 static const i915_reg_t flex_eu_regs[] = {
4241 for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
4242 if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)
4248 static bool reg_in_range_table(u32 addr, const struct i915_range *table)
4250 while (table->start || table->end) {
4251 if (addr >= table->start && addr <= table->end)
4260 #define REG_EQUAL(addr, mmio) \
4261 ((addr) == i915_mmio_reg_offset(mmio))
4263 static const struct i915_range gen7_oa_b_counters[] = {
4264 { .start = 0x2710, .end = 0x272c }, /* OASTARTTRIG[1-8] */
4265 { .start = 0x2740, .end = 0x275c }, /* OAREPORTTRIG[1-8] */
4266 { .start = 0x2770, .end = 0x27ac }, /* OACEC[0-7][0-1] */
4270 static const struct i915_range gen12_oa_b_counters[] = {
4271 { .start = 0x2b2c, .end = 0x2b2c }, /* GEN12_OAG_OA_PESS */
4272 { .start = 0xd900, .end = 0xd91c }, /* GEN12_OAG_OASTARTTRIG[1-8] */
4273 { .start = 0xd920, .end = 0xd93c }, /* GEN12_OAG_OAREPORTTRIG1[1-8] */
4274 { .start = 0xd940, .end = 0xd97c }, /* GEN12_OAG_CEC[0-7][0-1] */
4275 { .start = 0xdc00, .end = 0xdc3c }, /* GEN12_OAG_SCEC[0-7][0-1] */
4276 { .start = 0xdc40, .end = 0xdc40 }, /* GEN12_OAG_SPCTR_CNF */
4277 { .start = 0xdc44, .end = 0xdc44 }, /* GEN12_OAA_DBG_REG */
4281 static const struct i915_range xehp_oa_b_counters[] = {
4282 { .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */
4283 { .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG */
4286 static const struct i915_range gen7_oa_mux_regs[] = {
4287 { .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], OA_PERFMATRIX */
4288 { .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
4289 { .start = 0xe180, .end = 0xe180 }, /* HALF_SLICE_CHICKEN2 */
4293 static const struct i915_range hsw_oa_mux_regs[] = {
4294 { .start = 0x09e80, .end = 0x09ea4 }, /* HSW_MBVID2_NOA[0-9] */
4295 { .start = 0x09ec0, .end = 0x09ec0 }, /* HSW_MBVID2_MISR0 */
4296 { .start = 0x25100, .end = 0x2ff90 },
4300 static const struct i915_range chv_oa_mux_regs[] = {
4301 { .start = 0x182300, .end = 0x1823a4 },
4305 static const struct i915_range gen8_oa_mux_regs[] = {
4306 { .start = 0x0d00, .end = 0x0d2c }, /* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */
4307 { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
4311 static const struct i915_range gen11_oa_mux_regs[] = {
4312 { .start = 0x91c8, .end = 0x91dc }, /* OA_PERFCNT[3-4] */
4316 static const struct i915_range gen12_oa_mux_regs[] = {
4317 { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
4318 { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
4319 { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
4320 { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
4321 { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
4327 * 0x20cc is repurposed on MTL, so use a separate array for MTL.
4329 static const struct i915_range mtl_oa_mux_regs[] = {
4330 { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
4331 { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
4332 { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
4333 { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
4336 static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4338 return reg_in_range_table(addr, gen7_oa_b_counters);
4341 static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4343 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4344 reg_in_range_table(addr, gen8_oa_mux_regs);
4347 static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4349 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4350 reg_in_range_table(addr, gen8_oa_mux_regs) ||
4351 reg_in_range_table(addr, gen11_oa_mux_regs);
4354 static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4356 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4357 reg_in_range_table(addr, hsw_oa_mux_regs);
4360 static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4362 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4363 reg_in_range_table(addr, chv_oa_mux_regs);
4366 static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4368 return reg_in_range_table(addr, gen12_oa_b_counters);
4371 static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4373 return reg_in_range_table(addr, xehp_oa_b_counters) ||
4374 reg_in_range_table(addr, gen12_oa_b_counters);
4377 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4379 if (IS_METEORLAKE(perf->i915))
4380 return reg_in_range_table(addr, mtl_oa_mux_regs);
4382 return reg_in_range_table(addr, gen12_oa_mux_regs);
4385 static u32 mask_reg_value(u32 reg, u32 val)
4387 /* HALF_SLICE_CHICKEN2 is programmed with a the
4388 * WaDisableSTUnitPowerOptimization workaround. Make sure the value
4389 * programmed by userspace doesn't change this.
4391 if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
4392 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
4394 /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function
4395 * indicated by its name and a bunch of selection fields used by OA
4398 if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
4399 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
4404 static struct i915_oa_reg *alloc_oa_regs(struct i915_perf *perf,
4405 bool (*is_valid)(struct i915_perf *perf, u32 addr),
4409 struct i915_oa_reg *oa_regs;
4416 /* No is_valid function means we're not allowing any register to be programmed. */
4417 GEM_BUG_ON(!is_valid);
4419 return ERR_PTR(-EINVAL);
4421 oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL);
4423 return ERR_PTR(-ENOMEM);
4425 for (i = 0; i < n_regs; i++) {
4428 err = get_user(addr, regs);
4432 if (!is_valid(perf, addr)) {
4433 drm_dbg(&perf->i915->drm,
4434 "Invalid oa_reg address: %X\n", addr);
4439 err = get_user(value, regs + 1);
4443 oa_regs[i].addr = _MMIO(addr);
4444 oa_regs[i].value = mask_reg_value(addr, value);
4453 return ERR_PTR(err);
4456 static ssize_t show_dynamic_id(struct kobject *kobj,
4457 struct kobj_attribute *attr,
4460 struct i915_oa_config *oa_config =
4461 container_of(attr, typeof(*oa_config), sysfs_metric_id);
4463 return sprintf(buf, "%d\n", oa_config->id);
4466 static int create_dynamic_oa_sysfs_entry(struct i915_perf *perf,
4467 struct i915_oa_config *oa_config)
4469 sysfs_attr_init(&oa_config->sysfs_metric_id.attr);
4470 oa_config->sysfs_metric_id.attr.name = "id";
4471 oa_config->sysfs_metric_id.attr.mode = S_IRUGO;
4472 oa_config->sysfs_metric_id.show = show_dynamic_id;
4473 oa_config->sysfs_metric_id.store = NULL;
4475 oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr;
4476 oa_config->attrs[1] = NULL;
4478 oa_config->sysfs_metric.name = oa_config->uuid;
4479 oa_config->sysfs_metric.attrs = oa_config->attrs;
4481 return sysfs_create_group(perf->metrics_kobj,
4482 &oa_config->sysfs_metric);
4486 * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config
4488 * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from
4489 * userspace (unvalidated)
4492 * Validates the submitted OA register to be saved into a new OA config that
4493 * can then be used for programming the OA unit and its NOA network.
4495 * Returns: A new allocated config number to be used with the perf open ioctl
4496 * or a negative error code on failure.
4498 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
4499 struct drm_file *file)
4501 struct i915_perf *perf = &to_i915(dev)->perf;
4502 struct drm_i915_perf_oa_config *args = data;
4503 struct i915_oa_config *oa_config, *tmp;
4504 struct i915_oa_reg *regs;
4508 drm_dbg(&perf->i915->drm,
4509 "i915 perf interface not available for this system\n");
4513 if (!perf->metrics_kobj) {
4514 drm_dbg(&perf->i915->drm,
4515 "OA metrics weren't advertised via sysfs\n");
4519 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4520 drm_dbg(&perf->i915->drm,
4521 "Insufficient privileges to add i915 OA config\n");
4525 if ((!args->mux_regs_ptr || !args->n_mux_regs) &&
4526 (!args->boolean_regs_ptr || !args->n_boolean_regs) &&
4527 (!args->flex_regs_ptr || !args->n_flex_regs)) {
4528 drm_dbg(&perf->i915->drm,
4529 "No OA registers given\n");
4533 oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL);
4535 drm_dbg(&perf->i915->drm,
4536 "Failed to allocate memory for the OA config\n");
4540 oa_config->perf = perf;
4541 kref_init(&oa_config->ref);
4543 if (!uuid_is_valid(args->uuid)) {
4544 drm_dbg(&perf->i915->drm,
4545 "Invalid uuid format for OA config\n");
4550 /* Last character in oa_config->uuid will be 0 because oa_config is
4553 memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid));
4555 oa_config->mux_regs_len = args->n_mux_regs;
4556 regs = alloc_oa_regs(perf,
4557 perf->ops.is_valid_mux_reg,
4558 u64_to_user_ptr(args->mux_regs_ptr),
4562 drm_dbg(&perf->i915->drm,
4563 "Failed to create OA config for mux_regs\n");
4564 err = PTR_ERR(regs);
4567 oa_config->mux_regs = regs;
4569 oa_config->b_counter_regs_len = args->n_boolean_regs;
4570 regs = alloc_oa_regs(perf,
4571 perf->ops.is_valid_b_counter_reg,
4572 u64_to_user_ptr(args->boolean_regs_ptr),
4573 args->n_boolean_regs);
4576 drm_dbg(&perf->i915->drm,
4577 "Failed to create OA config for b_counter_regs\n");
4578 err = PTR_ERR(regs);
4581 oa_config->b_counter_regs = regs;
4583 if (GRAPHICS_VER(perf->i915) < 8) {
4584 if (args->n_flex_regs != 0) {
4589 oa_config->flex_regs_len = args->n_flex_regs;
4590 regs = alloc_oa_regs(perf,
4591 perf->ops.is_valid_flex_reg,
4592 u64_to_user_ptr(args->flex_regs_ptr),
4596 drm_dbg(&perf->i915->drm,
4597 "Failed to create OA config for flex_regs\n");
4598 err = PTR_ERR(regs);
4601 oa_config->flex_regs = regs;
4604 err = mutex_lock_interruptible(&perf->metrics_lock);
4608 /* We shouldn't have too many configs, so this iteration shouldn't be
4611 idr_for_each_entry(&perf->metrics_idr, tmp, id) {
4612 if (!strcmp(tmp->uuid, oa_config->uuid)) {
4613 drm_dbg(&perf->i915->drm,
4614 "OA config already exists with this uuid\n");
4620 err = create_dynamic_oa_sysfs_entry(perf, oa_config);
4622 drm_dbg(&perf->i915->drm,
4623 "Failed to create sysfs entry for OA config\n");
4627 /* Config id 0 is invalid, id 1 for kernel stored test config. */
4628 oa_config->id = idr_alloc(&perf->metrics_idr,
4631 if (oa_config->id < 0) {
4632 drm_dbg(&perf->i915->drm,
4633 "Failed to create sysfs entry for OA config\n");
4634 err = oa_config->id;
4638 mutex_unlock(&perf->metrics_lock);
4640 drm_dbg(&perf->i915->drm,
4641 "Added config %s id=%i\n", oa_config->uuid, oa_config->id);
4643 return oa_config->id;
4646 mutex_unlock(&perf->metrics_lock);
4648 i915_oa_config_put(oa_config);
4649 drm_dbg(&perf->i915->drm,
4650 "Failed to add new OA config\n");
4655 * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config
4657 * @data: ioctl data (pointer to u64 integer) copied from userspace
4660 * Configs can be removed while being used, the will stop appearing in sysfs
4661 * and their content will be freed when the stream using the config is closed.
4663 * Returns: 0 on success or a negative error code on failure.
4665 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
4666 struct drm_file *file)
4668 struct i915_perf *perf = &to_i915(dev)->perf;
4670 struct i915_oa_config *oa_config;
4674 drm_dbg(&perf->i915->drm,
4675 "i915 perf interface not available for this system\n");
4679 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4680 drm_dbg(&perf->i915->drm,
4681 "Insufficient privileges to remove i915 OA config\n");
4685 ret = mutex_lock_interruptible(&perf->metrics_lock);
4689 oa_config = idr_find(&perf->metrics_idr, *arg);
4691 drm_dbg(&perf->i915->drm,
4692 "Failed to remove unknown OA config\n");
4697 GEM_BUG_ON(*arg != oa_config->id);
4699 sysfs_remove_group(perf->metrics_kobj, &oa_config->sysfs_metric);
4701 idr_remove(&perf->metrics_idr, *arg);
4703 mutex_unlock(&perf->metrics_lock);
4705 drm_dbg(&perf->i915->drm,
4706 "Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
4708 i915_oa_config_put(oa_config);
4713 mutex_unlock(&perf->metrics_lock);
4717 static struct ctl_table oa_table[] = {
4719 .procname = "perf_stream_paranoid",
4720 .data = &i915_perf_stream_paranoid,
4721 .maxlen = sizeof(i915_perf_stream_paranoid),
4723 .proc_handler = proc_dointvec_minmax,
4724 .extra1 = SYSCTL_ZERO,
4725 .extra2 = SYSCTL_ONE,
4728 .procname = "oa_max_sample_rate",
4729 .data = &i915_oa_max_sample_rate,
4730 .maxlen = sizeof(i915_oa_max_sample_rate),
4732 .proc_handler = proc_dointvec_minmax,
4733 .extra1 = SYSCTL_ZERO,
4734 .extra2 = &oa_sample_rate_hard_limit,
4739 static void oa_init_supported_formats(struct i915_perf *perf)
4741 struct drm_i915_private *i915 = perf->i915;
4742 enum intel_platform platform = INTEL_INFO(i915)->platform;
4746 oa_format_add(perf, I915_OA_FORMAT_A13);
4747 oa_format_add(perf, I915_OA_FORMAT_A13);
4748 oa_format_add(perf, I915_OA_FORMAT_A29);
4749 oa_format_add(perf, I915_OA_FORMAT_A13_B8_C8);
4750 oa_format_add(perf, I915_OA_FORMAT_B4_C8);
4751 oa_format_add(perf, I915_OA_FORMAT_A45_B8_C8);
4752 oa_format_add(perf, I915_OA_FORMAT_B4_C8_A16);
4753 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
4756 case INTEL_BROADWELL:
4757 case INTEL_CHERRYVIEW:
4760 case INTEL_KABYLAKE:
4761 case INTEL_GEMINILAKE:
4762 case INTEL_COFFEELAKE:
4763 case INTEL_COMETLAKE:
4765 case INTEL_ELKHARTLAKE:
4766 case INTEL_JASPERLAKE:
4767 case INTEL_TIGERLAKE:
4768 case INTEL_ROCKETLAKE:
4770 case INTEL_ALDERLAKE_S:
4771 case INTEL_ALDERLAKE_P:
4772 oa_format_add(perf, I915_OA_FORMAT_A12);
4773 oa_format_add(perf, I915_OA_FORMAT_A12_B8_C8);
4774 oa_format_add(perf, I915_OA_FORMAT_A32u40_A4u32_B8_C8);
4775 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
4779 case INTEL_METEORLAKE:
4780 oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
4781 oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
4785 MISSING_CASE(platform);
4789 static void i915_perf_init_info(struct drm_i915_private *i915)
4791 struct i915_perf *perf = &i915->perf;
4793 switch (GRAPHICS_VER(i915)) {
4795 perf->ctx_oactxctrl_offset = 0x120;
4796 perf->ctx_flexeu0_offset = 0x2ce;
4797 perf->gen8_valid_ctx_bit = BIT(25);
4800 perf->ctx_oactxctrl_offset = 0x128;
4801 perf->ctx_flexeu0_offset = 0x3de;
4802 perf->gen8_valid_ctx_bit = BIT(16);
4805 perf->ctx_oactxctrl_offset = 0x124;
4806 perf->ctx_flexeu0_offset = 0x78e;
4807 perf->gen8_valid_ctx_bit = BIT(16);
4811 * Calculate offset at runtime in oa_pin_context for gen12 and
4812 * cache the value in perf->ctx_oactxctrl_offset.
4816 MISSING_CASE(GRAPHICS_VER(i915));
4821 * i915_perf_init - initialize i915-perf state on module bind
4822 * @i915: i915 device instance
4824 * Initializes i915-perf state without exposing anything to userspace.
4826 * Note: i915-perf initialization is split into an 'init' and 'register'
4827 * phase with the i915_perf_register() exposing state to userspace.
4829 void i915_perf_init(struct drm_i915_private *i915)
4831 struct i915_perf *perf = &i915->perf;
4833 perf->oa_formats = oa_formats;
4834 if (IS_HASWELL(i915)) {
4835 perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
4836 perf->ops.is_valid_mux_reg = hsw_is_valid_mux_addr;
4837 perf->ops.is_valid_flex_reg = NULL;
4838 perf->ops.enable_metric_set = hsw_enable_metric_set;
4839 perf->ops.disable_metric_set = hsw_disable_metric_set;
4840 perf->ops.oa_enable = gen7_oa_enable;
4841 perf->ops.oa_disable = gen7_oa_disable;
4842 perf->ops.read = gen7_oa_read;
4843 perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
4844 } else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
4845 /* Note: that although we could theoretically also support the
4846 * legacy ringbuffer mode on BDW (and earlier iterations of
4847 * this driver, before upstreaming did this) it didn't seem
4848 * worth the complexity to maintain now that BDW+ enable
4849 * execlist mode by default.
4851 perf->ops.read = gen8_oa_read;
4852 i915_perf_init_info(i915);
4854 if (IS_GRAPHICS_VER(i915, 8, 9)) {
4855 perf->ops.is_valid_b_counter_reg =
4856 gen7_is_valid_b_counter_addr;
4857 perf->ops.is_valid_mux_reg =
4858 gen8_is_valid_mux_addr;
4859 perf->ops.is_valid_flex_reg =
4860 gen8_is_valid_flex_addr;
4862 if (IS_CHERRYVIEW(i915)) {
4863 perf->ops.is_valid_mux_reg =
4864 chv_is_valid_mux_addr;
4867 perf->ops.oa_enable = gen8_oa_enable;
4868 perf->ops.oa_disable = gen8_oa_disable;
4869 perf->ops.enable_metric_set = gen8_enable_metric_set;
4870 perf->ops.disable_metric_set = gen8_disable_metric_set;
4871 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
4872 } else if (GRAPHICS_VER(i915) == 11) {
4873 perf->ops.is_valid_b_counter_reg =
4874 gen7_is_valid_b_counter_addr;
4875 perf->ops.is_valid_mux_reg =
4876 gen11_is_valid_mux_addr;
4877 perf->ops.is_valid_flex_reg =
4878 gen8_is_valid_flex_addr;
4880 perf->ops.oa_enable = gen8_oa_enable;
4881 perf->ops.oa_disable = gen8_oa_disable;
4882 perf->ops.enable_metric_set = gen8_enable_metric_set;
4883 perf->ops.disable_metric_set = gen11_disable_metric_set;
4884 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
4885 } else if (GRAPHICS_VER(i915) == 12) {
4886 perf->ops.is_valid_b_counter_reg =
4887 HAS_OA_SLICE_CONTRIB_LIMITS(i915) ?
4888 xehp_is_valid_b_counter_addr :
4889 gen12_is_valid_b_counter_addr;
4890 perf->ops.is_valid_mux_reg =
4891 gen12_is_valid_mux_addr;
4892 perf->ops.is_valid_flex_reg =
4893 gen8_is_valid_flex_addr;
4895 perf->ops.oa_enable = gen12_oa_enable;
4896 perf->ops.oa_disable = gen12_oa_disable;
4897 perf->ops.enable_metric_set = gen12_enable_metric_set;
4898 perf->ops.disable_metric_set = gen12_disable_metric_set;
4899 perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
4903 if (perf->ops.enable_metric_set) {
4904 struct intel_gt *gt;
4907 for_each_gt(gt, i915, i)
4908 mutex_init(>->perf.lock);
4910 /* Choose a representative limit */
4911 oa_sample_rate_hard_limit = to_gt(i915)->clock_frequency / 2;
4913 mutex_init(&perf->metrics_lock);
4914 idr_init_base(&perf->metrics_idr, 1);
4916 /* We set up some ratelimit state to potentially throttle any
4917 * _NOTES about spurious, invalid OA reports which we don't
4918 * forward to userspace.
4920 * We print a _NOTE about any throttling when closing the
4921 * stream instead of waiting until driver _fini which no one
4924 * Using the same limiting factors as printk_ratelimit()
4926 ratelimit_state_init(&perf->spurious_report_rs, 5 * HZ, 10);
4927 /* Since we use a DRM_NOTE for spurious reports it would be
4928 * inconsistent to let __ratelimit() automatically print a
4929 * warning for throttling.
4931 ratelimit_set_flags(&perf->spurious_report_rs,
4932 RATELIMIT_MSG_ON_RELEASE);
4934 ratelimit_state_init(&perf->tail_pointer_race,
4936 ratelimit_set_flags(&perf->tail_pointer_race,
4937 RATELIMIT_MSG_ON_RELEASE);
4939 atomic64_set(&perf->noa_programming_delay,
4940 500 * 1000 /* 500us */);
4944 oa_init_supported_formats(perf);
4948 static int destroy_config(int id, void *p, void *data)
4950 i915_oa_config_put(p);
4954 int i915_perf_sysctl_register(void)
4956 sysctl_header = register_sysctl("dev/i915", oa_table);
4960 void i915_perf_sysctl_unregister(void)
4962 unregister_sysctl_table(sysctl_header);
4966 * i915_perf_fini - Counter part to i915_perf_init()
4967 * @i915: i915 device instance
4969 void i915_perf_fini(struct drm_i915_private *i915)
4971 struct i915_perf *perf = &i915->perf;
4976 idr_for_each(&perf->metrics_idr, destroy_config, perf);
4977 idr_destroy(&perf->metrics_idr);
4979 memset(&perf->ops, 0, sizeof(perf->ops));
4984 * i915_perf_ioctl_version - Version of the i915-perf subsystem
4986 * This version number is used by userspace to detect available features.
4988 int i915_perf_ioctl_version(void)
4991 * 1: Initial version
4992 * I915_PERF_IOCTL_ENABLE
4993 * I915_PERF_IOCTL_DISABLE
4995 * 2: Added runtime modification of OA config.
4996 * I915_PERF_IOCTL_CONFIG
4998 * 3: Add DRM_I915_PERF_PROP_HOLD_PREEMPTION parameter to hold
4999 * preemption on a particular context so that performance data is
5000 * accessible from a delta of MI_RPC reports without looking at the
5003 * 4: Add DRM_I915_PERF_PROP_ALLOWED_SSEU to limit what contexts can
5004 * be run for the duration of the performance recording based on
5005 * their SSEU configuration.
5007 * 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
5008 * interval for the hrtimer used to check for OA data.
5013 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5014 #include "selftests/i915_perf.c"