2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <drm/drm_color_mgmt.h>
26 #include <drm/drm_drv.h>
27 #include <drm/i915_pciids.h>
29 #include "i915_driver.h"
34 #define PLATFORM(x) .platform = (x)
36 .graphics.ver = (x), \
40 #define I845_PIPE_OFFSETS \
42 [TRANSCODER_A] = PIPE_A_OFFSET, \
45 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
48 #define I9XX_PIPE_OFFSETS \
50 [TRANSCODER_A] = PIPE_A_OFFSET, \
51 [TRANSCODER_B] = PIPE_B_OFFSET, \
54 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
55 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
58 #define IVB_PIPE_OFFSETS \
60 [TRANSCODER_A] = PIPE_A_OFFSET, \
61 [TRANSCODER_B] = PIPE_B_OFFSET, \
62 [TRANSCODER_C] = PIPE_C_OFFSET, \
65 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
66 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
67 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
70 #define HSW_PIPE_OFFSETS \
72 [TRANSCODER_A] = PIPE_A_OFFSET, \
73 [TRANSCODER_B] = PIPE_B_OFFSET, \
74 [TRANSCODER_C] = PIPE_C_OFFSET, \
75 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
78 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
79 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
80 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
81 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
84 #define CHV_PIPE_OFFSETS \
86 [TRANSCODER_A] = PIPE_A_OFFSET, \
87 [TRANSCODER_B] = PIPE_B_OFFSET, \
88 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
91 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
92 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
93 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
96 #define I845_CURSOR_OFFSETS \
98 [PIPE_A] = CURSOR_A_OFFSET, \
101 #define I9XX_CURSOR_OFFSETS \
102 .cursor_offsets = { \
103 [PIPE_A] = CURSOR_A_OFFSET, \
104 [PIPE_B] = CURSOR_B_OFFSET, \
107 #define CHV_CURSOR_OFFSETS \
108 .cursor_offsets = { \
109 [PIPE_A] = CURSOR_A_OFFSET, \
110 [PIPE_B] = CURSOR_B_OFFSET, \
111 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
114 #define IVB_CURSOR_OFFSETS \
115 .cursor_offsets = { \
116 [PIPE_A] = CURSOR_A_OFFSET, \
117 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
118 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
121 #define TGL_CURSOR_OFFSETS \
122 .cursor_offsets = { \
123 [PIPE_A] = CURSOR_A_OFFSET, \
124 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
125 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
126 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
129 #define I9XX_COLORS \
130 .color = { .gamma_lut_size = 256 }
131 #define I965_COLORS \
132 .color = { .gamma_lut_size = 129, \
133 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
136 .color = { .gamma_lut_size = 1024 }
138 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
140 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
141 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
142 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
145 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
146 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
147 DRM_COLOR_LUT_EQUAL_CHANNELS, \
150 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145, \
151 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
152 DRM_COLOR_LUT_EQUAL_CHANNELS, \
153 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
156 /* Keep in gen based order, and chronological order within a gen */
158 #define GEN_DEFAULT_PAGE_SIZES \
159 .page_sizes = I915_GTT_PAGE_SIZE_4K
161 #define GEN_DEFAULT_REGIONS \
162 .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
164 #define I830_FEATURES \
167 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
168 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
169 .display.has_overlay = 1, \
170 .display.cursor_needs_physical = 1, \
171 .display.overlay_needs_physical = 1, \
172 .display.has_gmch = 1, \
173 .gpu_reset_clobbers_display = true, \
174 .has_3d_pipeline = 1, \
175 .hws_needs_physical = 1, \
176 .unfenced_needs_alignment = 1, \
177 .platform_engine_mask = BIT(RCS0), \
179 .has_coherent_ggtt = false, \
180 .dma_mask_size = 32, \
182 I9XX_CURSOR_OFFSETS, \
184 GEN_DEFAULT_PAGE_SIZES, \
187 #define I845_FEATURES \
189 .display.pipe_mask = BIT(PIPE_A), \
190 .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \
191 .display.has_overlay = 1, \
192 .display.overlay_needs_physical = 1, \
193 .display.has_gmch = 1, \
194 .has_3d_pipeline = 1, \
195 .gpu_reset_clobbers_display = true, \
196 .hws_needs_physical = 1, \
197 .unfenced_needs_alignment = 1, \
198 .platform_engine_mask = BIT(RCS0), \
200 .has_coherent_ggtt = false, \
201 .dma_mask_size = 32, \
203 I845_CURSOR_OFFSETS, \
205 GEN_DEFAULT_PAGE_SIZES, \
208 static const struct intel_device_info i830_info = {
210 PLATFORM(INTEL_I830),
213 static const struct intel_device_info i845g_info = {
215 PLATFORM(INTEL_I845G),
218 static const struct intel_device_info i85x_info = {
220 PLATFORM(INTEL_I85X),
221 .display.fbc_mask = BIT(INTEL_FBC_A),
224 static const struct intel_device_info i865g_info = {
226 PLATFORM(INTEL_I865G),
227 .display.fbc_mask = BIT(INTEL_FBC_A),
230 #define GEN3_FEATURES \
232 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
233 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
234 .display.has_gmch = 1, \
235 .gpu_reset_clobbers_display = true, \
236 .platform_engine_mask = BIT(RCS0), \
237 .has_3d_pipeline = 1, \
239 .has_coherent_ggtt = true, \
240 .dma_mask_size = 32, \
242 I9XX_CURSOR_OFFSETS, \
244 GEN_DEFAULT_PAGE_SIZES, \
247 static const struct intel_device_info i915g_info = {
249 PLATFORM(INTEL_I915G),
250 .has_coherent_ggtt = false,
251 .display.cursor_needs_physical = 1,
252 .display.has_overlay = 1,
253 .display.overlay_needs_physical = 1,
254 .hws_needs_physical = 1,
255 .unfenced_needs_alignment = 1,
258 static const struct intel_device_info i915gm_info = {
260 PLATFORM(INTEL_I915GM),
262 .display.cursor_needs_physical = 1,
263 .display.has_overlay = 1,
264 .display.overlay_needs_physical = 1,
265 .display.supports_tv = 1,
266 .display.fbc_mask = BIT(INTEL_FBC_A),
267 .hws_needs_physical = 1,
268 .unfenced_needs_alignment = 1,
271 static const struct intel_device_info i945g_info = {
273 PLATFORM(INTEL_I945G),
274 .display.has_hotplug = 1,
275 .display.cursor_needs_physical = 1,
276 .display.has_overlay = 1,
277 .display.overlay_needs_physical = 1,
278 .hws_needs_physical = 1,
279 .unfenced_needs_alignment = 1,
282 static const struct intel_device_info i945gm_info = {
284 PLATFORM(INTEL_I945GM),
286 .display.has_hotplug = 1,
287 .display.cursor_needs_physical = 1,
288 .display.has_overlay = 1,
289 .display.overlay_needs_physical = 1,
290 .display.supports_tv = 1,
291 .display.fbc_mask = BIT(INTEL_FBC_A),
292 .hws_needs_physical = 1,
293 .unfenced_needs_alignment = 1,
296 static const struct intel_device_info g33_info = {
299 .display.has_hotplug = 1,
300 .display.has_overlay = 1,
304 static const struct intel_device_info pnv_g_info = {
306 PLATFORM(INTEL_PINEVIEW),
307 .display.has_hotplug = 1,
308 .display.has_overlay = 1,
312 static const struct intel_device_info pnv_m_info = {
314 PLATFORM(INTEL_PINEVIEW),
316 .display.has_hotplug = 1,
317 .display.has_overlay = 1,
321 #define GEN4_FEATURES \
323 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
324 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
325 .display.has_hotplug = 1, \
326 .display.has_gmch = 1, \
327 .gpu_reset_clobbers_display = true, \
328 .platform_engine_mask = BIT(RCS0), \
329 .has_3d_pipeline = 1, \
331 .has_coherent_ggtt = true, \
332 .dma_mask_size = 36, \
334 I9XX_CURSOR_OFFSETS, \
336 GEN_DEFAULT_PAGE_SIZES, \
339 static const struct intel_device_info i965g_info = {
341 PLATFORM(INTEL_I965G),
342 .display.has_overlay = 1,
343 .hws_needs_physical = 1,
347 static const struct intel_device_info i965gm_info = {
349 PLATFORM(INTEL_I965GM),
351 .display.fbc_mask = BIT(INTEL_FBC_A),
352 .display.has_overlay = 1,
353 .display.supports_tv = 1,
354 .hws_needs_physical = 1,
358 static const struct intel_device_info g45_info = {
361 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
362 .gpu_reset_clobbers_display = false,
365 static const struct intel_device_info gm45_info = {
367 PLATFORM(INTEL_GM45),
369 .display.fbc_mask = BIT(INTEL_FBC_A),
370 .display.supports_tv = 1,
371 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
372 .gpu_reset_clobbers_display = false,
375 #define GEN5_FEATURES \
377 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
378 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
379 .display.has_hotplug = 1, \
380 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
381 .has_3d_pipeline = 1, \
383 .has_coherent_ggtt = true, \
384 /* ilk does support rc6, but we do not implement [power] contexts */ \
386 .dma_mask_size = 36, \
388 I9XX_CURSOR_OFFSETS, \
390 GEN_DEFAULT_PAGE_SIZES, \
393 static const struct intel_device_info ilk_d_info = {
395 PLATFORM(INTEL_IRONLAKE),
398 static const struct intel_device_info ilk_m_info = {
400 PLATFORM(INTEL_IRONLAKE),
403 .display.fbc_mask = BIT(INTEL_FBC_A),
406 #define GEN6_FEATURES \
408 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
409 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
410 .display.has_hotplug = 1, \
411 .display.fbc_mask = BIT(INTEL_FBC_A), \
412 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
413 .has_3d_pipeline = 1, \
414 .has_coherent_ggtt = true, \
419 .dma_mask_size = 40, \
420 .ppgtt_type = INTEL_PPGTT_ALIASING, \
423 I9XX_CURSOR_OFFSETS, \
425 GEN_DEFAULT_PAGE_SIZES, \
428 #define SNB_D_PLATFORM \
430 PLATFORM(INTEL_SANDYBRIDGE)
432 static const struct intel_device_info snb_d_gt1_info = {
437 static const struct intel_device_info snb_d_gt2_info = {
442 #define SNB_M_PLATFORM \
444 PLATFORM(INTEL_SANDYBRIDGE), \
448 static const struct intel_device_info snb_m_gt1_info = {
453 static const struct intel_device_info snb_m_gt2_info = {
458 #define GEN7_FEATURES \
460 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
461 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
462 .display.has_hotplug = 1, \
463 .display.fbc_mask = BIT(INTEL_FBC_A), \
464 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
465 .has_3d_pipeline = 1, \
466 .has_coherent_ggtt = true, \
470 .has_reset_engine = true, \
472 .dma_mask_size = 40, \
473 .ppgtt_type = INTEL_PPGTT_ALIASING, \
476 IVB_CURSOR_OFFSETS, \
478 GEN_DEFAULT_PAGE_SIZES, \
481 #define IVB_D_PLATFORM \
483 PLATFORM(INTEL_IVYBRIDGE), \
486 static const struct intel_device_info ivb_d_gt1_info = {
491 static const struct intel_device_info ivb_d_gt2_info = {
496 #define IVB_M_PLATFORM \
498 PLATFORM(INTEL_IVYBRIDGE), \
502 static const struct intel_device_info ivb_m_gt1_info = {
507 static const struct intel_device_info ivb_m_gt2_info = {
512 static const struct intel_device_info ivb_q_info = {
514 PLATFORM(INTEL_IVYBRIDGE),
516 .display.pipe_mask = 0, /* legal, last one wins */
517 .display.cpu_transcoder_mask = 0,
521 static const struct intel_device_info vlv_info = {
522 PLATFORM(INTEL_VALLEYVIEW),
525 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
526 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
529 .has_reset_engine = true,
531 .display.has_gmch = 1,
532 .display.has_hotplug = 1,
534 .ppgtt_type = INTEL_PPGTT_ALIASING,
537 .has_coherent_ggtt = false,
538 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
539 .display_mmio_offset = VLV_DISPLAY_BASE,
543 GEN_DEFAULT_PAGE_SIZES,
547 #define G75_FEATURES \
549 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
550 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
551 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
552 .display.has_ddi = 1, \
553 .display.has_fpga_dbg = 1, \
554 .display.has_dp_mst = 1, \
555 .has_rc6p = 0 /* RC6p removed-by HSW */, \
559 #define HSW_PLATFORM \
561 PLATFORM(INTEL_HASWELL), \
564 static const struct intel_device_info hsw_gt1_info = {
569 static const struct intel_device_info hsw_gt2_info = {
574 static const struct intel_device_info hsw_gt3_info = {
579 #define GEN8_FEATURES \
582 .has_logical_ring_contexts = 1, \
583 .dma_mask_size = 39, \
584 .ppgtt_type = INTEL_PPGTT_FULL, \
588 #define BDW_PLATFORM \
590 PLATFORM(INTEL_BROADWELL)
592 static const struct intel_device_info bdw_gt1_info = {
597 static const struct intel_device_info bdw_gt2_info = {
602 static const struct intel_device_info bdw_rsvd_info = {
605 /* According to the device ID those devices are GT3, they were
606 * previously treated as not GT3, keep it like that.
610 static const struct intel_device_info bdw_gt3_info = {
613 .platform_engine_mask =
614 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
617 static const struct intel_device_info chv_info = {
618 PLATFORM(INTEL_CHERRYVIEW),
620 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
621 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
622 .display.has_hotplug = 1,
624 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
625 .has_64bit_reloc = 1,
629 .has_logical_ring_contexts = 1,
630 .display.has_gmch = 1,
632 .ppgtt_type = INTEL_PPGTT_FULL,
634 .has_reset_engine = 1,
636 .has_coherent_ggtt = false,
637 .display_mmio_offset = VLV_DISPLAY_BASE,
641 GEN_DEFAULT_PAGE_SIZES,
645 #define GEN9_DEFAULT_PAGE_SIZES \
646 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
647 I915_GTT_PAGE_SIZE_64K
649 #define GEN9_FEATURES \
652 GEN9_DEFAULT_PAGE_SIZES, \
653 .display.has_dmc = 1, \
655 .display.has_hdcp = 1, \
656 .display.has_ipc = 1, \
657 .display.has_psr = 1, \
658 .display.has_psr_hw_tracking = 1, \
659 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
660 .dbuf.slice_mask = BIT(DBUF_S1)
662 #define SKL_PLATFORM \
664 PLATFORM(INTEL_SKYLAKE)
666 static const struct intel_device_info skl_gt1_info = {
671 static const struct intel_device_info skl_gt2_info = {
676 #define SKL_GT3_PLUS_PLATFORM \
678 .platform_engine_mask = \
679 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
682 static const struct intel_device_info skl_gt3_info = {
683 SKL_GT3_PLUS_PLATFORM,
687 static const struct intel_device_info skl_gt4_info = {
688 SKL_GT3_PLUS_PLATFORM,
692 #define GEN9_LP_FEATURES \
695 .dbuf.slice_mask = BIT(DBUF_S1), \
696 .display.has_hotplug = 1, \
697 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
698 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
699 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
700 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
701 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
702 .has_3d_pipeline = 1, \
703 .has_64bit_reloc = 1, \
704 .display.has_ddi = 1, \
705 .display.has_fpga_dbg = 1, \
706 .display.fbc_mask = BIT(INTEL_FBC_A), \
707 .display.has_hdcp = 1, \
708 .display.has_psr = 1, \
709 .display.has_psr_hw_tracking = 1, \
710 .has_runtime_pm = 1, \
711 .display.has_dmc = 1, \
714 .display.has_dp_mst = 1, \
715 .has_logical_ring_contexts = 1, \
717 .dma_mask_size = 39, \
718 .ppgtt_type = INTEL_PPGTT_FULL, \
720 .has_reset_engine = 1, \
722 .has_coherent_ggtt = false, \
723 .display.has_ipc = 1, \
725 IVB_CURSOR_OFFSETS, \
727 GEN9_DEFAULT_PAGE_SIZES, \
730 static const struct intel_device_info bxt_info = {
732 PLATFORM(INTEL_BROXTON),
733 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
736 static const struct intel_device_info glk_info = {
738 PLATFORM(INTEL_GEMINILAKE),
740 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
744 #define KBL_PLATFORM \
746 PLATFORM(INTEL_KABYLAKE)
748 static const struct intel_device_info kbl_gt1_info = {
753 static const struct intel_device_info kbl_gt2_info = {
758 static const struct intel_device_info kbl_gt3_info = {
761 .platform_engine_mask =
762 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
765 #define CFL_PLATFORM \
767 PLATFORM(INTEL_COFFEELAKE)
769 static const struct intel_device_info cfl_gt1_info = {
774 static const struct intel_device_info cfl_gt2_info = {
779 static const struct intel_device_info cfl_gt3_info = {
782 .platform_engine_mask =
783 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
786 #define CML_PLATFORM \
788 PLATFORM(INTEL_COMETLAKE)
790 static const struct intel_device_info cml_gt1_info = {
795 static const struct intel_device_info cml_gt2_info = {
800 #define GEN11_DEFAULT_PAGE_SIZES \
801 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
802 I915_GTT_PAGE_SIZE_64K | \
803 I915_GTT_PAGE_SIZE_2M
805 #define GEN11_FEATURES \
807 GEN11_DEFAULT_PAGE_SIZES, \
808 .display.abox_mask = BIT(0), \
809 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
810 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
811 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
813 [TRANSCODER_A] = PIPE_A_OFFSET, \
814 [TRANSCODER_B] = PIPE_B_OFFSET, \
815 [TRANSCODER_C] = PIPE_C_OFFSET, \
816 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
817 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
818 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
821 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
822 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
823 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
824 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
825 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
826 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
831 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
832 .display.has_dsc = 1, \
833 .has_coherent_ggtt = false, \
834 .has_logical_ring_elsq = 1
836 static const struct intel_device_info icl_info = {
838 PLATFORM(INTEL_ICELAKE),
839 .platform_engine_mask =
840 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
843 static const struct intel_device_info ehl_info = {
845 PLATFORM(INTEL_ELKHARTLAKE),
846 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
850 static const struct intel_device_info jsl_info = {
852 PLATFORM(INTEL_JASPERLAKE),
853 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
857 #define GEN12_FEATURES \
860 .display.abox_mask = GENMASK(2, 1), \
861 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
862 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
863 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
864 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
866 [TRANSCODER_A] = PIPE_A_OFFSET, \
867 [TRANSCODER_B] = PIPE_B_OFFSET, \
868 [TRANSCODER_C] = PIPE_C_OFFSET, \
869 [TRANSCODER_D] = PIPE_D_OFFSET, \
870 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
871 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
874 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
875 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
876 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
877 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
878 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
879 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
881 TGL_CURSOR_OFFSETS, \
882 .has_global_mocs = 1, \
884 .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
886 static const struct intel_device_info tgl_info = {
888 PLATFORM(INTEL_TIGERLAKE),
889 .display.has_modular_fia = 1,
890 .platform_engine_mask =
891 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
894 static const struct intel_device_info rkl_info = {
896 PLATFORM(INTEL_ROCKETLAKE),
897 .display.abox_mask = BIT(0),
898 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
899 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
901 .display.has_hti = 1,
902 .display.has_psr_hw_tracking = 0,
903 .platform_engine_mask =
904 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
907 #define DGFX_FEATURES \
908 .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
915 static const struct intel_device_info dg1_info = {
920 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
921 .require_force_probe = 1,
922 .platform_engine_mask =
923 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
924 BIT(VCS0) | BIT(VCS2),
929 static const struct intel_device_info adl_s_info = {
931 PLATFORM(INTEL_ALDERLAKE_S),
932 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
933 .display.has_hti = 1,
934 .display.has_psr_hw_tracking = 0,
935 .platform_engine_mask =
936 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
940 #define XE_LPD_CURSOR_OFFSETS \
941 .cursor_offsets = { \
942 [PIPE_A] = CURSOR_A_OFFSET, \
943 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
944 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
945 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
948 #define XE_LPD_FEATURES \
949 .display.abox_mask = GENMASK(1, 0), \
950 .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024, \
951 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
952 DRM_COLOR_LUT_EQUAL_CHANNELS, \
955 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
957 .display.has_ddi = 1, \
958 .display.has_dmc = 1, \
959 .display.has_dp_mst = 1, \
960 .display.has_dsb = 1, \
961 .display.has_dsc = 1, \
962 .display.fbc_mask = BIT(INTEL_FBC_A), \
963 .display.has_fpga_dbg = 1, \
964 .display.has_hdcp = 1, \
965 .display.has_hotplug = 1, \
966 .display.has_ipc = 1, \
967 .display.has_psr = 1, \
969 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
971 [TRANSCODER_A] = PIPE_A_OFFSET, \
972 [TRANSCODER_B] = PIPE_B_OFFSET, \
973 [TRANSCODER_C] = PIPE_C_OFFSET, \
974 [TRANSCODER_D] = PIPE_D_OFFSET, \
975 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
976 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
979 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
980 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
981 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
982 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
983 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
984 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
986 XE_LPD_CURSOR_OFFSETS
988 static const struct intel_device_info adl_p_info = {
991 PLATFORM(INTEL_ALDERLAKE_P),
992 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
993 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
994 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
995 .display.has_cdclk_crawl = 1,
996 .display.has_modular_fia = 1,
997 .display.has_psr_hw_tracking = 0,
998 .platform_engine_mask =
999 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
1001 .dma_mask_size = 39,
1006 #define XE_HP_PAGE_SIZES \
1007 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
1008 I915_GTT_PAGE_SIZE_64K | \
1009 I915_GTT_PAGE_SIZE_2M
1011 #define XE_HP_FEATURES \
1012 .graphics.ver = 12, \
1013 .graphics.rel = 50, \
1015 .dma_mask_size = 46, \
1016 .has_3d_pipeline = 1, \
1017 .has_64bit_reloc = 1, \
1018 .has_flat_ccs = 1, \
1019 .has_global_mocs = 1, \
1022 .has_logical_ring_contexts = 1, \
1023 .has_logical_ring_elsq = 1, \
1024 .has_mslice_steering = 1, \
1026 .has_reset_engine = 1, \
1028 .has_runtime_pm = 1, \
1030 .ppgtt_type = INTEL_PPGTT_FULL
1032 #define XE_HPM_FEATURES \
1037 static const struct intel_device_info xehpsdv_info = {
1041 PLATFORM(INTEL_XEHPSDV),
1044 .needs_compact_pt = 1,
1045 .has_media_ratio_mode = 1,
1046 .platform_engine_mask =
1047 BIT(RCS0) | BIT(BCS0) |
1048 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1049 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1050 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
1051 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1052 .require_force_probe = 1,
1055 #define DG2_FEATURES \
1059 .graphics.rel = 55, \
1061 PLATFORM(INTEL_DG2), \
1063 .has_64k_pages = 1, \
1064 .has_guc_deprivilege = 1, \
1065 .has_heci_pxp = 1, \
1066 .needs_compact_pt = 1, \
1067 .has_media_ratio_mode = 1, \
1068 .platform_engine_mask = \
1069 BIT(RCS0) | BIT(BCS0) | \
1070 BIT(VECS0) | BIT(VECS1) | \
1071 BIT(VCS0) | BIT(VCS2) | \
1072 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
1074 static const struct intel_device_info dg2_info = {
1077 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1078 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1079 .require_force_probe = 1,
1082 static const struct intel_device_info ats_m_info = {
1085 .require_force_probe = 1,
1088 #define XE_HPC_FEATURES \
1090 .dma_mask_size = 52, \
1091 .has_3d_pipeline = 0, \
1092 .has_guc_deprivilege = 1, \
1093 .has_l3_ccs_read = 1, \
1094 .has_mslice_steering = 0, \
1095 .has_one_eu_per_fuse_bit = 1
1098 static const struct intel_device_info pvc_info = {
1104 PLATFORM(INTEL_PONTEVECCHIO),
1107 .platform_engine_mask =
1110 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1111 .require_force_probe = 1,
1114 #define XE_LPDP_FEATURES \
1116 .display.ver = 14, \
1117 .display.has_cdclk_crawl = 1
1120 static const struct intel_device_info mtl_info = {
1124 * Real graphics IP version will be obtained from hardware GMD_ID
1125 * register. Value provided here is just for sanity checking.
1130 PLATFORM(INTEL_METEORLAKE),
1131 .display.has_modular_fia = 1,
1134 .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
1135 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
1136 .require_force_probe = 1,
1142 * Make sure any device matches here are from most specific to most
1143 * general. For example, since the Quanta match is based on the subsystem
1144 * and subvendor IDs, we need it to come before the more general IVB
1145 * PCI ID matches, otherwise we'll use the wrong info struct above.
1147 static const struct pci_device_id pciidlist[] = {
1148 INTEL_I830_IDS(&i830_info),
1149 INTEL_I845G_IDS(&i845g_info),
1150 INTEL_I85X_IDS(&i85x_info),
1151 INTEL_I865G_IDS(&i865g_info),
1152 INTEL_I915G_IDS(&i915g_info),
1153 INTEL_I915GM_IDS(&i915gm_info),
1154 INTEL_I945G_IDS(&i945g_info),
1155 INTEL_I945GM_IDS(&i945gm_info),
1156 INTEL_I965G_IDS(&i965g_info),
1157 INTEL_G33_IDS(&g33_info),
1158 INTEL_I965GM_IDS(&i965gm_info),
1159 INTEL_GM45_IDS(&gm45_info),
1160 INTEL_G45_IDS(&g45_info),
1161 INTEL_PINEVIEW_G_IDS(&pnv_g_info),
1162 INTEL_PINEVIEW_M_IDS(&pnv_m_info),
1163 INTEL_IRONLAKE_D_IDS(&ilk_d_info),
1164 INTEL_IRONLAKE_M_IDS(&ilk_m_info),
1165 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
1166 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
1167 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
1168 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
1169 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
1170 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
1171 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
1172 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1173 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1174 INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1175 INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1176 INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1177 INTEL_VLV_IDS(&vlv_info),
1178 INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1179 INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1180 INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1181 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1182 INTEL_CHV_IDS(&chv_info),
1183 INTEL_SKL_GT1_IDS(&skl_gt1_info),
1184 INTEL_SKL_GT2_IDS(&skl_gt2_info),
1185 INTEL_SKL_GT3_IDS(&skl_gt3_info),
1186 INTEL_SKL_GT4_IDS(&skl_gt4_info),
1187 INTEL_BXT_IDS(&bxt_info),
1188 INTEL_GLK_IDS(&glk_info),
1189 INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1190 INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1191 INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1192 INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1193 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1194 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1195 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1196 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1197 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1198 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1199 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1200 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1201 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1202 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1203 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1204 INTEL_CML_GT1_IDS(&cml_gt1_info),
1205 INTEL_CML_GT2_IDS(&cml_gt2_info),
1206 INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1207 INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1208 INTEL_ICL_11_IDS(&icl_info),
1209 INTEL_EHL_IDS(&ehl_info),
1210 INTEL_JSL_IDS(&jsl_info),
1211 INTEL_TGL_12_IDS(&tgl_info),
1212 INTEL_RKL_IDS(&rkl_info),
1213 INTEL_ADLS_IDS(&adl_s_info),
1214 INTEL_ADLP_IDS(&adl_p_info),
1215 INTEL_ADLN_IDS(&adl_p_info),
1216 INTEL_DG1_IDS(&dg1_info),
1217 INTEL_RPLS_IDS(&adl_s_info),
1218 INTEL_RPLP_IDS(&adl_p_info),
1219 INTEL_DG2_IDS(&dg2_info),
1220 INTEL_ATS_M_IDS(&ats_m_info),
1223 MODULE_DEVICE_TABLE(pci, pciidlist);
1225 static void i915_pci_remove(struct pci_dev *pdev)
1227 struct drm_i915_private *i915;
1229 i915 = pci_get_drvdata(pdev);
1230 if (!i915) /* driver load aborted, nothing to cleanup */
1233 i915_driver_remove(i915);
1234 pci_set_drvdata(pdev, NULL);
1237 /* is device_id present in comma separated list of ids */
1238 static bool force_probe(u16 device_id, const char *devices)
1243 if (!devices || !*devices)
1246 /* match everything */
1247 if (strcmp(devices, "*") == 0)
1250 s = kstrdup(devices, GFP_KERNEL);
1254 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1257 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1268 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1270 struct intel_device_info *intel_info =
1271 (struct intel_device_info *) ent->driver_data;
1274 if (intel_info->require_force_probe &&
1275 !force_probe(pdev->device, i915_modparams.force_probe)) {
1276 dev_info(&pdev->dev,
1277 "Your graphics device %04x is not properly supported by the driver in this\n"
1278 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1279 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1280 "or (recommended) check for kernel updates.\n",
1281 pdev->device, pdev->device, pdev->device);
1285 /* Only bind to function 0 of the device. Early generations
1286 * used function 1 as a placeholder for multi-head. This causes
1287 * us confusion instead, especially on the systems where both
1288 * functions have the same PCI-ID!
1290 if (PCI_FUNC(pdev->devfn))
1293 /* Detect if we need to wait for other drivers early on */
1294 if (intel_modeset_probe_defer(pdev))
1295 return -EPROBE_DEFER;
1297 err = i915_driver_probe(pdev, ent);
1301 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1302 i915_pci_remove(pdev);
1306 err = i915_live_selftests(pdev);
1308 i915_pci_remove(pdev);
1309 return err > 0 ? -ENOTTY : err;
1312 err = i915_perf_selftests(pdev);
1314 i915_pci_remove(pdev);
1315 return err > 0 ? -ENOTTY : err;
1321 static void i915_pci_shutdown(struct pci_dev *pdev)
1323 struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1325 i915_driver_shutdown(i915);
1328 static struct pci_driver i915_pci_driver = {
1329 .name = DRIVER_NAME,
1330 .id_table = pciidlist,
1331 .probe = i915_pci_probe,
1332 .remove = i915_pci_remove,
1333 .shutdown = i915_pci_shutdown,
1334 .driver.pm = &i915_pm_ops,
1337 int i915_pci_register_driver(void)
1339 return pci_register_driver(&i915_pci_driver);
1342 void i915_pci_unregister_driver(void)
1344 pci_unregister_driver(&i915_pci_driver);