2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vga_switcheroo.h>
28 #include <drm/drm_drv.h>
29 #include <drm/i915_pciids.h>
31 #include "display/intel_fbdev.h"
34 #include "i915_perf.h"
35 #include "i915_globals.h"
36 #include "i915_selftest.h"
38 #define PLATFORM(x) .platform = (x)
39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
41 #define I845_PIPE_OFFSETS \
43 [TRANSCODER_A] = PIPE_A_OFFSET, \
46 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
49 #define I9XX_PIPE_OFFSETS \
51 [TRANSCODER_A] = PIPE_A_OFFSET, \
52 [TRANSCODER_B] = PIPE_B_OFFSET, \
55 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
56 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
59 #define IVB_PIPE_OFFSETS \
61 [TRANSCODER_A] = PIPE_A_OFFSET, \
62 [TRANSCODER_B] = PIPE_B_OFFSET, \
63 [TRANSCODER_C] = PIPE_C_OFFSET, \
66 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
67 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
68 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
71 #define HSW_PIPE_OFFSETS \
73 [TRANSCODER_A] = PIPE_A_OFFSET, \
74 [TRANSCODER_B] = PIPE_B_OFFSET, \
75 [TRANSCODER_C] = PIPE_C_OFFSET, \
76 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
79 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
80 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
81 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
82 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
85 #define CHV_PIPE_OFFSETS \
87 [TRANSCODER_A] = PIPE_A_OFFSET, \
88 [TRANSCODER_B] = PIPE_B_OFFSET, \
89 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
92 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
93 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
94 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
97 #define I845_CURSOR_OFFSETS \
99 [PIPE_A] = CURSOR_A_OFFSET, \
102 #define I9XX_CURSOR_OFFSETS \
103 .cursor_offsets = { \
104 [PIPE_A] = CURSOR_A_OFFSET, \
105 [PIPE_B] = CURSOR_B_OFFSET, \
108 #define CHV_CURSOR_OFFSETS \
109 .cursor_offsets = { \
110 [PIPE_A] = CURSOR_A_OFFSET, \
111 [PIPE_B] = CURSOR_B_OFFSET, \
112 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
115 #define IVB_CURSOR_OFFSETS \
116 .cursor_offsets = { \
117 [PIPE_A] = CURSOR_A_OFFSET, \
118 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
119 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
122 #define TGL_CURSOR_OFFSETS \
123 .cursor_offsets = { \
124 [PIPE_A] = CURSOR_A_OFFSET, \
125 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
126 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
127 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
130 #define I9XX_COLORS \
131 .color = { .gamma_lut_size = 256 }
132 #define I965_COLORS \
133 .color = { .gamma_lut_size = 129, \
134 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
137 .color = { .gamma_lut_size = 1024 }
139 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
141 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
142 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
143 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
146 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
147 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
148 DRM_COLOR_LUT_EQUAL_CHANNELS, \
151 /* Keep in gen based order, and chronological order within a gen */
153 #define GEN_DEFAULT_PAGE_SIZES \
154 .page_sizes = I915_GTT_PAGE_SIZE_4K
156 #define GEN_DEFAULT_REGIONS \
157 .memory_regions = REGION_SMEM | REGION_STOLEN
159 #define I830_FEATURES \
162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
163 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
164 .display.has_overlay = 1, \
165 .display.cursor_needs_physical = 1, \
166 .display.overlay_needs_physical = 1, \
167 .display.has_gmch = 1, \
168 .gpu_reset_clobbers_display = true, \
169 .hws_needs_physical = 1, \
170 .unfenced_needs_alignment = 1, \
171 .engine_mask = BIT(RCS0), \
173 .has_coherent_ggtt = false, \
174 .dma_mask_size = 32, \
176 I9XX_CURSOR_OFFSETS, \
178 GEN_DEFAULT_PAGE_SIZES, \
181 #define I845_FEATURES \
183 .pipe_mask = BIT(PIPE_A), \
184 .cpu_transcoder_mask = BIT(TRANSCODER_A), \
185 .display.has_overlay = 1, \
186 .display.overlay_needs_physical = 1, \
187 .display.has_gmch = 1, \
188 .gpu_reset_clobbers_display = true, \
189 .hws_needs_physical = 1, \
190 .unfenced_needs_alignment = 1, \
191 .engine_mask = BIT(RCS0), \
193 .has_coherent_ggtt = false, \
194 .dma_mask_size = 32, \
196 I845_CURSOR_OFFSETS, \
198 GEN_DEFAULT_PAGE_SIZES, \
201 static const struct intel_device_info i830_info = {
203 PLATFORM(INTEL_I830),
206 static const struct intel_device_info i845g_info = {
208 PLATFORM(INTEL_I845G),
211 static const struct intel_device_info i85x_info = {
213 PLATFORM(INTEL_I85X),
214 .display.has_fbc = 1,
217 static const struct intel_device_info i865g_info = {
219 PLATFORM(INTEL_I865G),
222 #define GEN3_FEATURES \
224 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
225 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
226 .display.has_gmch = 1, \
227 .gpu_reset_clobbers_display = true, \
228 .engine_mask = BIT(RCS0), \
230 .has_coherent_ggtt = true, \
231 .dma_mask_size = 32, \
233 I9XX_CURSOR_OFFSETS, \
235 GEN_DEFAULT_PAGE_SIZES, \
238 static const struct intel_device_info i915g_info = {
240 PLATFORM(INTEL_I915G),
241 .has_coherent_ggtt = false,
242 .display.cursor_needs_physical = 1,
243 .display.has_overlay = 1,
244 .display.overlay_needs_physical = 1,
245 .hws_needs_physical = 1,
246 .unfenced_needs_alignment = 1,
249 static const struct intel_device_info i915gm_info = {
251 PLATFORM(INTEL_I915GM),
253 .display.cursor_needs_physical = 1,
254 .display.has_overlay = 1,
255 .display.overlay_needs_physical = 1,
256 .display.supports_tv = 1,
257 .display.has_fbc = 1,
258 .hws_needs_physical = 1,
259 .unfenced_needs_alignment = 1,
262 static const struct intel_device_info i945g_info = {
264 PLATFORM(INTEL_I945G),
265 .display.has_hotplug = 1,
266 .display.cursor_needs_physical = 1,
267 .display.has_overlay = 1,
268 .display.overlay_needs_physical = 1,
269 .hws_needs_physical = 1,
270 .unfenced_needs_alignment = 1,
273 static const struct intel_device_info i945gm_info = {
275 PLATFORM(INTEL_I945GM),
277 .display.has_hotplug = 1,
278 .display.cursor_needs_physical = 1,
279 .display.has_overlay = 1,
280 .display.overlay_needs_physical = 1,
281 .display.supports_tv = 1,
282 .display.has_fbc = 1,
283 .hws_needs_physical = 1,
284 .unfenced_needs_alignment = 1,
287 static const struct intel_device_info g33_info = {
290 .display.has_hotplug = 1,
291 .display.has_overlay = 1,
295 static const struct intel_device_info pnv_g_info = {
297 PLATFORM(INTEL_PINEVIEW),
298 .display.has_hotplug = 1,
299 .display.has_overlay = 1,
303 static const struct intel_device_info pnv_m_info = {
305 PLATFORM(INTEL_PINEVIEW),
307 .display.has_hotplug = 1,
308 .display.has_overlay = 1,
312 #define GEN4_FEATURES \
314 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
315 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
316 .display.has_hotplug = 1, \
317 .display.has_gmch = 1, \
318 .gpu_reset_clobbers_display = true, \
319 .engine_mask = BIT(RCS0), \
321 .has_coherent_ggtt = true, \
322 .dma_mask_size = 36, \
324 I9XX_CURSOR_OFFSETS, \
326 GEN_DEFAULT_PAGE_SIZES, \
329 static const struct intel_device_info i965g_info = {
331 PLATFORM(INTEL_I965G),
332 .display.has_overlay = 1,
333 .hws_needs_physical = 1,
337 static const struct intel_device_info i965gm_info = {
339 PLATFORM(INTEL_I965GM),
341 .display.has_fbc = 1,
342 .display.has_overlay = 1,
343 .display.supports_tv = 1,
344 .hws_needs_physical = 1,
348 static const struct intel_device_info g45_info = {
351 .engine_mask = BIT(RCS0) | BIT(VCS0),
352 .gpu_reset_clobbers_display = false,
355 static const struct intel_device_info gm45_info = {
357 PLATFORM(INTEL_GM45),
359 .display.has_fbc = 1,
360 .display.supports_tv = 1,
361 .engine_mask = BIT(RCS0) | BIT(VCS0),
362 .gpu_reset_clobbers_display = false,
365 #define GEN5_FEATURES \
367 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
368 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
369 .display.has_hotplug = 1, \
370 .engine_mask = BIT(RCS0) | BIT(VCS0), \
372 .has_coherent_ggtt = true, \
373 /* ilk does support rc6, but we do not implement [power] contexts */ \
375 .dma_mask_size = 36, \
377 I9XX_CURSOR_OFFSETS, \
379 GEN_DEFAULT_PAGE_SIZES, \
382 static const struct intel_device_info ilk_d_info = {
384 PLATFORM(INTEL_IRONLAKE),
387 static const struct intel_device_info ilk_m_info = {
389 PLATFORM(INTEL_IRONLAKE),
391 .display.has_fbc = 1,
394 #define GEN6_FEATURES \
396 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
397 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
398 .display.has_hotplug = 1, \
399 .display.has_fbc = 1, \
400 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
401 .has_coherent_ggtt = true, \
406 .dma_mask_size = 40, \
407 .ppgtt_type = INTEL_PPGTT_ALIASING, \
410 I9XX_CURSOR_OFFSETS, \
412 GEN_DEFAULT_PAGE_SIZES, \
415 #define SNB_D_PLATFORM \
417 PLATFORM(INTEL_SANDYBRIDGE)
419 static const struct intel_device_info snb_d_gt1_info = {
424 static const struct intel_device_info snb_d_gt2_info = {
429 #define SNB_M_PLATFORM \
431 PLATFORM(INTEL_SANDYBRIDGE), \
435 static const struct intel_device_info snb_m_gt1_info = {
440 static const struct intel_device_info snb_m_gt2_info = {
445 #define GEN7_FEATURES \
447 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
448 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
449 .display.has_hotplug = 1, \
450 .display.has_fbc = 1, \
451 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
452 .has_coherent_ggtt = true, \
457 .dma_mask_size = 40, \
458 .ppgtt_type = INTEL_PPGTT_ALIASING, \
461 IVB_CURSOR_OFFSETS, \
463 GEN_DEFAULT_PAGE_SIZES, \
466 #define IVB_D_PLATFORM \
468 PLATFORM(INTEL_IVYBRIDGE), \
471 static const struct intel_device_info ivb_d_gt1_info = {
476 static const struct intel_device_info ivb_d_gt2_info = {
481 #define IVB_M_PLATFORM \
483 PLATFORM(INTEL_IVYBRIDGE), \
487 static const struct intel_device_info ivb_m_gt1_info = {
492 static const struct intel_device_info ivb_m_gt2_info = {
497 static const struct intel_device_info ivb_q_info = {
499 PLATFORM(INTEL_IVYBRIDGE),
501 .pipe_mask = 0, /* legal, last one wins */
502 .cpu_transcoder_mask = 0,
506 static const struct intel_device_info vlv_info = {
507 PLATFORM(INTEL_VALLEYVIEW),
510 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
511 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
515 .display.has_gmch = 1,
516 .display.has_hotplug = 1,
518 .ppgtt_type = INTEL_PPGTT_ALIASING,
521 .has_coherent_ggtt = false,
522 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
523 .display_mmio_offset = VLV_DISPLAY_BASE,
527 GEN_DEFAULT_PAGE_SIZES,
531 #define G75_FEATURES \
533 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
534 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
535 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
536 .display.has_ddi = 1, \
538 .display.has_psr = 1, \
539 .display.has_dp_mst = 1, \
540 .has_rc6p = 0 /* RC6p removed-by HSW */, \
544 #define HSW_PLATFORM \
546 PLATFORM(INTEL_HASWELL), \
549 static const struct intel_device_info hsw_gt1_info = {
554 static const struct intel_device_info hsw_gt2_info = {
559 static const struct intel_device_info hsw_gt3_info = {
564 #define GEN8_FEATURES \
567 .has_logical_ring_contexts = 1, \
568 .dma_mask_size = 39, \
569 .ppgtt_type = INTEL_PPGTT_FULL, \
571 .has_64bit_reloc = 1, \
572 .has_reset_engine = 1
574 #define BDW_PLATFORM \
576 PLATFORM(INTEL_BROADWELL)
578 static const struct intel_device_info bdw_gt1_info = {
583 static const struct intel_device_info bdw_gt2_info = {
588 static const struct intel_device_info bdw_rsvd_info = {
591 /* According to the device ID those devices are GT3, they were
592 * previously treated as not GT3, keep it like that.
596 static const struct intel_device_info bdw_gt3_info = {
600 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
603 static const struct intel_device_info chv_info = {
604 PLATFORM(INTEL_CHERRYVIEW),
606 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
607 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
608 .display.has_hotplug = 1,
610 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
611 .has_64bit_reloc = 1,
615 .has_logical_ring_contexts = 1,
616 .display.has_gmch = 1,
618 .ppgtt_type = INTEL_PPGTT_FULL,
620 .has_reset_engine = 1,
622 .has_coherent_ggtt = false,
623 .display_mmio_offset = VLV_DISPLAY_BASE,
627 GEN_DEFAULT_PAGE_SIZES,
631 #define GEN9_DEFAULT_PAGE_SIZES \
632 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
633 I915_GTT_PAGE_SIZE_64K
635 #define GEN9_FEATURES \
638 GEN9_DEFAULT_PAGE_SIZES, \
639 .has_logical_ring_preemption = 1, \
640 .display.has_csr = 1, \
642 .display.has_hdcp = 1, \
643 .display.has_ipc = 1, \
645 .num_supported_dbuf_slices = 1
647 #define SKL_PLATFORM \
649 PLATFORM(INTEL_SKYLAKE)
651 static const struct intel_device_info skl_gt1_info = {
656 static const struct intel_device_info skl_gt2_info = {
661 #define SKL_GT3_PLUS_PLATFORM \
664 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
667 static const struct intel_device_info skl_gt3_info = {
668 SKL_GT3_PLUS_PLATFORM,
672 static const struct intel_device_info skl_gt4_info = {
673 SKL_GT3_PLUS_PLATFORM,
677 #define GEN9_LP_FEATURES \
680 .num_supported_dbuf_slices = 1, \
681 .display.has_hotplug = 1, \
682 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
683 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
684 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
685 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
686 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
687 .has_64bit_reloc = 1, \
688 .display.has_ddi = 1, \
690 .display.has_fbc = 1, \
691 .display.has_hdcp = 1, \
692 .display.has_psr = 1, \
693 .has_runtime_pm = 1, \
694 .display.has_csr = 1, \
697 .display.has_dp_mst = 1, \
698 .has_logical_ring_contexts = 1, \
699 .has_logical_ring_preemption = 1, \
701 .dma_mask_size = 39, \
702 .ppgtt_type = INTEL_PPGTT_FULL, \
704 .has_reset_engine = 1, \
706 .has_coherent_ggtt = false, \
707 .display.has_ipc = 1, \
709 IVB_CURSOR_OFFSETS, \
711 GEN9_DEFAULT_PAGE_SIZES, \
714 static const struct intel_device_info bxt_info = {
716 PLATFORM(INTEL_BROXTON),
720 static const struct intel_device_info glk_info = {
722 PLATFORM(INTEL_GEMINILAKE),
727 #define KBL_PLATFORM \
729 PLATFORM(INTEL_KABYLAKE)
731 static const struct intel_device_info kbl_gt1_info = {
736 static const struct intel_device_info kbl_gt2_info = {
741 static const struct intel_device_info kbl_gt3_info = {
745 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
748 #define CFL_PLATFORM \
750 PLATFORM(INTEL_COFFEELAKE)
752 static const struct intel_device_info cfl_gt1_info = {
757 static const struct intel_device_info cfl_gt2_info = {
762 static const struct intel_device_info cfl_gt3_info = {
766 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
769 #define GEN10_FEATURES \
773 .display.has_dsc = 1, \
774 .has_coherent_ggtt = false, \
777 static const struct intel_device_info cnl_info = {
779 PLATFORM(INTEL_CANNONLAKE),
783 #define GEN11_DEFAULT_PAGE_SIZES \
784 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
785 I915_GTT_PAGE_SIZE_64K | \
786 I915_GTT_PAGE_SIZE_2M
788 #define GEN11_FEATURES \
790 GEN11_DEFAULT_PAGE_SIZES, \
791 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
792 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
793 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
795 [TRANSCODER_A] = PIPE_A_OFFSET, \
796 [TRANSCODER_B] = PIPE_B_OFFSET, \
797 [TRANSCODER_C] = PIPE_C_OFFSET, \
798 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
799 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
800 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
803 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
804 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
805 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
806 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
807 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
808 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
812 .num_supported_dbuf_slices = 2, \
813 .has_logical_ring_elsq = 1, \
814 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
816 static const struct intel_device_info icl_info = {
818 PLATFORM(INTEL_ICELAKE),
820 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
823 static const struct intel_device_info ehl_info = {
825 PLATFORM(INTEL_ELKHARTLAKE),
826 .require_force_probe = 1,
827 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
831 #define GEN12_FEATURES \
834 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
835 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
836 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
837 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
839 [TRANSCODER_A] = PIPE_A_OFFSET, \
840 [TRANSCODER_B] = PIPE_B_OFFSET, \
841 [TRANSCODER_C] = PIPE_C_OFFSET, \
842 [TRANSCODER_D] = PIPE_D_OFFSET, \
843 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
844 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
847 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
848 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
849 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
850 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
851 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
852 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
854 TGL_CURSOR_OFFSETS, \
855 .has_global_mocs = 1, \
858 static const struct intel_device_info tgl_info = {
860 PLATFORM(INTEL_TIGERLAKE),
861 .display.has_modular_fia = 1,
863 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
866 #define GEN12_DGFX_FEATURES \
874 * Make sure any device matches here are from most specific to most
875 * general. For example, since the Quanta match is based on the subsystem
876 * and subvendor IDs, we need it to come before the more general IVB
877 * PCI ID matches, otherwise we'll use the wrong info struct above.
879 static const struct pci_device_id pciidlist[] = {
880 INTEL_I830_IDS(&i830_info),
881 INTEL_I845G_IDS(&i845g_info),
882 INTEL_I85X_IDS(&i85x_info),
883 INTEL_I865G_IDS(&i865g_info),
884 INTEL_I915G_IDS(&i915g_info),
885 INTEL_I915GM_IDS(&i915gm_info),
886 INTEL_I945G_IDS(&i945g_info),
887 INTEL_I945GM_IDS(&i945gm_info),
888 INTEL_I965G_IDS(&i965g_info),
889 INTEL_G33_IDS(&g33_info),
890 INTEL_I965GM_IDS(&i965gm_info),
891 INTEL_GM45_IDS(&gm45_info),
892 INTEL_G45_IDS(&g45_info),
893 INTEL_PINEVIEW_G_IDS(&pnv_g_info),
894 INTEL_PINEVIEW_M_IDS(&pnv_m_info),
895 INTEL_IRONLAKE_D_IDS(&ilk_d_info),
896 INTEL_IRONLAKE_M_IDS(&ilk_m_info),
897 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
898 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
899 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
900 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
901 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
902 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
903 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
904 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
905 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
906 INTEL_HSW_GT1_IDS(&hsw_gt1_info),
907 INTEL_HSW_GT2_IDS(&hsw_gt2_info),
908 INTEL_HSW_GT3_IDS(&hsw_gt3_info),
909 INTEL_VLV_IDS(&vlv_info),
910 INTEL_BDW_GT1_IDS(&bdw_gt1_info),
911 INTEL_BDW_GT2_IDS(&bdw_gt2_info),
912 INTEL_BDW_GT3_IDS(&bdw_gt3_info),
913 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
914 INTEL_CHV_IDS(&chv_info),
915 INTEL_SKL_GT1_IDS(&skl_gt1_info),
916 INTEL_SKL_GT2_IDS(&skl_gt2_info),
917 INTEL_SKL_GT3_IDS(&skl_gt3_info),
918 INTEL_SKL_GT4_IDS(&skl_gt4_info),
919 INTEL_BXT_IDS(&bxt_info),
920 INTEL_GLK_IDS(&glk_info),
921 INTEL_KBL_GT1_IDS(&kbl_gt1_info),
922 INTEL_KBL_GT2_IDS(&kbl_gt2_info),
923 INTEL_KBL_GT3_IDS(&kbl_gt3_info),
924 INTEL_KBL_GT4_IDS(&kbl_gt3_info),
925 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
926 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
927 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
928 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
929 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
930 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
931 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
932 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
933 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
934 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
935 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
936 INTEL_CML_GT1_IDS(&cfl_gt1_info),
937 INTEL_CML_GT2_IDS(&cfl_gt2_info),
938 INTEL_CML_U_GT1_IDS(&cfl_gt1_info),
939 INTEL_CML_U_GT2_IDS(&cfl_gt2_info),
940 INTEL_CNL_IDS(&cnl_info),
941 INTEL_ICL_11_IDS(&icl_info),
942 INTEL_EHL_IDS(&ehl_info),
943 INTEL_TGL_12_IDS(&tgl_info),
946 MODULE_DEVICE_TABLE(pci, pciidlist);
948 static void i915_pci_remove(struct pci_dev *pdev)
950 struct drm_i915_private *i915;
952 i915 = pci_get_drvdata(pdev);
953 if (!i915) /* driver load aborted, nothing to cleanup */
956 i915_driver_remove(i915);
957 pci_set_drvdata(pdev, NULL);
960 /* is device_id present in comma separated list of ids */
961 static bool force_probe(u16 device_id, const char *devices)
966 if (!devices || !*devices)
969 /* match everything */
970 if (strcmp(devices, "*") == 0)
973 s = kstrdup(devices, GFP_KERNEL);
977 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
980 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
991 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
993 struct intel_device_info *intel_info =
994 (struct intel_device_info *) ent->driver_data;
997 if (intel_info->require_force_probe &&
998 !force_probe(pdev->device, i915_modparams.force_probe)) {
1000 "Your graphics device %04x is not properly supported by the driver in this\n"
1001 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1002 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1003 "or (recommended) check for kernel updates.\n",
1004 pdev->device, pdev->device, pdev->device);
1008 /* Only bind to function 0 of the device. Early generations
1009 * used function 1 as a placeholder for multi-head. This causes
1010 * us confusion instead, especially on the systems where both
1011 * functions have the same PCI-ID!
1013 if (PCI_FUNC(pdev->devfn))
1017 * apple-gmux is needed on dual GPU MacBook Pro
1018 * to probe the panel if we're the inactive GPU.
1020 if (vga_switcheroo_client_probe_defer(pdev))
1021 return -EPROBE_DEFER;
1023 err = i915_driver_probe(pdev, ent);
1027 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1028 i915_pci_remove(pdev);
1032 err = i915_live_selftests(pdev);
1034 i915_pci_remove(pdev);
1035 return err > 0 ? -ENOTTY : err;
1038 err = i915_perf_selftests(pdev);
1040 i915_pci_remove(pdev);
1041 return err > 0 ? -ENOTTY : err;
1047 static struct pci_driver i915_pci_driver = {
1048 .name = DRIVER_NAME,
1049 .id_table = pciidlist,
1050 .probe = i915_pci_probe,
1051 .remove = i915_pci_remove,
1052 .driver.pm = &i915_pm_ops,
1055 static int __init i915_init(void)
1057 bool use_kms = true;
1060 err = i915_globals_init();
1064 err = i915_mock_selftests();
1066 return err > 0 ? 0 : err;
1069 * Enable KMS by default, unless explicitly overriden by
1070 * either the i915.modeset prarameter or by the
1071 * vga_text_mode_force boot option.
1074 if (i915_modparams.modeset == 0)
1077 if (vgacon_text_force() && i915_modparams.modeset == -1)
1081 /* Silently fail loading to not upset userspace. */
1082 DRM_DEBUG_DRIVER("KMS disabled.\n");
1086 err = pci_register_driver(&i915_pci_driver);
1090 i915_perf_sysctl_register();
1094 static void __exit i915_exit(void)
1096 if (!i915_pci_driver.driver.owner)
1099 i915_perf_sysctl_unregister();
1100 pci_unregister_driver(&i915_pci_driver);
1101 i915_globals_exit();
1104 module_init(i915_init);
1105 module_exit(i915_exit);
1107 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1108 MODULE_AUTHOR("Intel Corporation");
1110 MODULE_DESCRIPTION(DRIVER_DESC);
1111 MODULE_LICENSE("GPL and additional rights");