drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_drv.h"
  30 #include "i915_selftest.h"
  31
  32 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
  33 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
  34
  35 #define GEN_DEFAULT_PIPEOFFSETS \
  36         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  37                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  38         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  39                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }
  40
  41 #define GEN_CHV_PIPEOFFSETS \
  42         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  43                           CHV_PIPE_C_OFFSET }, \
  44         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  45                            CHV_TRANSCODER_C_OFFSET }
  46
  47 #define CURSOR_OFFSETS \
  48         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  49
  50 #define IVB_CURSOR_OFFSETS \
  51         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  52
  53 #define BDW_COLORS \
  54         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  55 #define CHV_COLORS \
  56         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  57 #define GLK_COLORS \
  58         .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
  59
  60 /* Keep in gen based order, and chronological order within a gen */
  61
  62 #define GEN_DEFAULT_PAGE_SIZES \
  63         .page_sizes = I915_GTT_PAGE_SIZE_4K
  64
  65 #define GEN2_FEATURES \
  66         GEN(2), \
  67         .num_pipes = 1, \
  68         .has_overlay = 1, .overlay_needs_physical = 1, \
  69         .has_gmch_display = 1, \
  70         .hws_needs_physical = 1, \
  71         .unfenced_needs_alignment = 1, \
  72         .ring_mask = RENDER_RING, \
  73         .has_snoop = true, \
  74         .has_coherent_ggtt = false, \
  75         GEN_DEFAULT_PIPEOFFSETS, \
  76         GEN_DEFAULT_PAGE_SIZES, \
  77         CURSOR_OFFSETS
  78
  79 static const struct intel_device_info intel_i830_info = {
  80         GEN2_FEATURES,
  81         PLATFORM(INTEL_I830),
  82         .is_mobile = 1, .cursor_needs_physical = 1,
  83         .num_pipes = 2, /* legal, last one wins */
  84 };
  85
  86 static const struct intel_device_info intel_i845g_info = {
  87         GEN2_FEATURES,
  88         PLATFORM(INTEL_I845G),
  89 };
  90
  91 static const struct intel_device_info intel_i85x_info = {
  92         GEN2_FEATURES,
  93         PLATFORM(INTEL_I85X),
  94         .is_mobile = 1,
  95         .num_pipes = 2, /* legal, last one wins */
  96         .cursor_needs_physical = 1,
  97         .has_fbc = 1,
  98 };
  99
 100 static const struct intel_device_info intel_i865g_info = {
 101         GEN2_FEATURES,
 102         PLATFORM(INTEL_I865G),
 103 };
 104
 105 #define GEN3_FEATURES \
 106         GEN(3), \
 107         .num_pipes = 2, \
 108         .has_gmch_display = 1, \
 109         .ring_mask = RENDER_RING, \
 110         .has_snoop = true, \
 111         .has_coherent_ggtt = true, \
 112         GEN_DEFAULT_PIPEOFFSETS, \
 113         GEN_DEFAULT_PAGE_SIZES, \
 114         CURSOR_OFFSETS
 115
 116 static const struct intel_device_info intel_i915g_info = {
 117         GEN3_FEATURES,
 118         PLATFORM(INTEL_I915G),
 119         .has_coherent_ggtt = false,
 120         .cursor_needs_physical = 1,
 121         .has_overlay = 1, .overlay_needs_physical = 1,
 122         .hws_needs_physical = 1,
 123         .unfenced_needs_alignment = 1,
 124 };
 125
 126 static const struct intel_device_info intel_i915gm_info = {
 127         GEN3_FEATURES,
 128         PLATFORM(INTEL_I915GM),
 129         .is_mobile = 1,
 130         .cursor_needs_physical = 1,
 131         .has_overlay = 1, .overlay_needs_physical = 1,
 132         .supports_tv = 1,
 133         .has_fbc = 1,
 134         .hws_needs_physical = 1,
 135         .unfenced_needs_alignment = 1,
 136 };
 137
 138 static const struct intel_device_info intel_i945g_info = {
 139         GEN3_FEATURES,
 140         PLATFORM(INTEL_I945G),
 141         .has_hotplug = 1, .cursor_needs_physical = 1,
 142         .has_overlay = 1, .overlay_needs_physical = 1,
 143         .hws_needs_physical = 1,
 144         .unfenced_needs_alignment = 1,
 145 };
 146
 147 static const struct intel_device_info intel_i945gm_info = {
 148         GEN3_FEATURES,
 149         PLATFORM(INTEL_I945GM),
 150         .is_mobile = 1,
 151         .has_hotplug = 1, .cursor_needs_physical = 1,
 152         .has_overlay = 1, .overlay_needs_physical = 1,
 153         .supports_tv = 1,
 154         .has_fbc = 1,
 155         .hws_needs_physical = 1,
 156         .unfenced_needs_alignment = 1,
 157 };
 158
 159 static const struct intel_device_info intel_g33_info = {
 160         GEN3_FEATURES,
 161         PLATFORM(INTEL_G33),
 162         .has_hotplug = 1,
 163         .has_overlay = 1,
 164 };
 165
 166 static const struct intel_device_info intel_pineview_info = {
 167         GEN3_FEATURES,
 168         PLATFORM(INTEL_PINEVIEW),
 169         .is_mobile = 1,
 170         .has_hotplug = 1,
 171         .has_overlay = 1,
 172 };
 173
 174 #define GEN4_FEATURES \
 175         GEN(4), \
 176         .num_pipes = 2, \
 177         .has_hotplug = 1, \
 178         .has_gmch_display = 1, \
 179         .ring_mask = RENDER_RING, \
 180         .has_snoop = true, \
 181         .has_coherent_ggtt = true, \
 182         GEN_DEFAULT_PIPEOFFSETS, \
 183         GEN_DEFAULT_PAGE_SIZES, \
 184         CURSOR_OFFSETS
 185
 186 static const struct intel_device_info intel_i965g_info = {
 187         GEN4_FEATURES,
 188         PLATFORM(INTEL_I965G),
 189         .has_overlay = 1,
 190         .hws_needs_physical = 1,
 191         .has_snoop = false,
 192 };
 193
 194 static const struct intel_device_info intel_i965gm_info = {
 195         GEN4_FEATURES,
 196         PLATFORM(INTEL_I965GM),
 197         .is_mobile = 1, .has_fbc = 1,
 198         .has_overlay = 1,
 199         .supports_tv = 1,
 200         .hws_needs_physical = 1,
 201         .has_snoop = false,
 202 };
 203
 204 static const struct intel_device_info intel_g45_info = {
 205         GEN4_FEATURES,
 206         PLATFORM(INTEL_G45),
 207         .ring_mask = RENDER_RING | BSD_RING,
 208 };
 209
 210 static const struct intel_device_info intel_gm45_info = {
 211         GEN4_FEATURES,
 212         PLATFORM(INTEL_GM45),
 213         .is_mobile = 1, .has_fbc = 1,
 214         .supports_tv = 1,
 215         .ring_mask = RENDER_RING | BSD_RING,
 216 };
 217
 218 #define GEN5_FEATURES \
 219         GEN(5), \
 220         .num_pipes = 2, \
 221         .has_hotplug = 1, \
 222         .ring_mask = RENDER_RING | BSD_RING, \
 223         .has_snoop = true, \
 224         .has_coherent_ggtt = true, \
 225         /* ilk does support rc6, but we do not implement [power] contexts */ \
 226         .has_rc6 = 0, \
 227         GEN_DEFAULT_PIPEOFFSETS, \
 228         GEN_DEFAULT_PAGE_SIZES, \
 229         CURSOR_OFFSETS
 230
 231 static const struct intel_device_info intel_ironlake_d_info = {
 232         GEN5_FEATURES,
 233         PLATFORM(INTEL_IRONLAKE),
 234 };
 235
 236 static const struct intel_device_info intel_ironlake_m_info = {
 237         GEN5_FEATURES,
 238         PLATFORM(INTEL_IRONLAKE),
 239         .is_mobile = 1, .has_fbc = 1,
 240 };
 241
 242 #define GEN6_FEATURES \
 243         GEN(6), \
 244         .num_pipes = 2, \
 245         .has_hotplug = 1, \
 246         .has_fbc = 1, \
 247         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 248         .has_coherent_ggtt = true, \
 249         .has_llc = 1, \
 250         .has_rc6 = 1, \
 251         .has_rc6p = 1, \
 252         .ppgtt = INTEL_PPGTT_ALIASING, \
 253         GEN_DEFAULT_PIPEOFFSETS, \
 254         GEN_DEFAULT_PAGE_SIZES, \
 255         CURSOR_OFFSETS
 256
 257 #define SNB_D_PLATFORM \
 258         GEN6_FEATURES, \
 259         PLATFORM(INTEL_SANDYBRIDGE)
 260
 261 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
 262         SNB_D_PLATFORM,
 263         .gt = 1,
 264 };
 265
 266 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
 267         SNB_D_PLATFORM,
 268         .gt = 2,
 269 };
 270
 271 #define SNB_M_PLATFORM \
 272         GEN6_FEATURES, \
 273         PLATFORM(INTEL_SANDYBRIDGE), \
 274         .is_mobile = 1
 275
 276
 277 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
 278         SNB_M_PLATFORM,
 279         .gt = 1,
 280 };
 281
 282 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 283         SNB_M_PLATFORM,
 284         .gt = 2,
 285 };
 286
 287 #define GEN7_FEATURES  \
 288         GEN(7), \
 289         .num_pipes = 3, \
 290         .has_hotplug = 1, \
 291         .has_fbc = 1, \
 292         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 293         .has_coherent_ggtt = true, \
 294         .has_llc = 1, \
 295         .has_rc6 = 1, \
 296         .has_rc6p = 1, \
 297         .ppgtt = INTEL_PPGTT_FULL, \
 298         GEN_DEFAULT_PIPEOFFSETS, \
 299         GEN_DEFAULT_PAGE_SIZES, \
 300         IVB_CURSOR_OFFSETS
 301
 302 #define IVB_D_PLATFORM \
 303         GEN7_FEATURES, \
 304         PLATFORM(INTEL_IVYBRIDGE), \
 305         .has_l3_dpf = 1
 306
 307 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
 308         IVB_D_PLATFORM,
 309         .gt = 1,
 310 };
 311
 312 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
 313         IVB_D_PLATFORM,
 314         .gt = 2,
 315 };
 316
 317 #define IVB_M_PLATFORM \
 318         GEN7_FEATURES, \
 319         PLATFORM(INTEL_IVYBRIDGE), \
 320         .is_mobile = 1, \
 321         .has_l3_dpf = 1
 322
 323 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
 324         IVB_M_PLATFORM,
 325         .gt = 1,
 326 };
 327
 328 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
 329         IVB_M_PLATFORM,
 330         .gt = 2,
 331 };
 332
 333 static const struct intel_device_info intel_ivybridge_q_info = {
 334         GEN7_FEATURES,
 335         PLATFORM(INTEL_IVYBRIDGE),
 336         .gt = 2,
 337         .num_pipes = 0, /* legal, last one wins */
 338         .has_l3_dpf = 1,
 339 };
 340
 341 static const struct intel_device_info intel_valleyview_info = {
 342         PLATFORM(INTEL_VALLEYVIEW),
 343         GEN(7),
 344         .is_lp = 1,
 345         .num_pipes = 2,
 346         .has_runtime_pm = 1,
 347         .has_rc6 = 1,
 348         .has_gmch_display = 1,
 349         .has_hotplug = 1,
 350         .ppgtt = INTEL_PPGTT_FULL,
 351         .has_snoop = true,
 352         .has_coherent_ggtt = false,
 353         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 354         .display_mmio_offset = VLV_DISPLAY_BASE,
 355         GEN_DEFAULT_PAGE_SIZES,
 356         GEN_DEFAULT_PIPEOFFSETS,
 357         CURSOR_OFFSETS
 358 };
 359
 360 #define G75_FEATURES  \
 361         GEN7_FEATURES, \
 362         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 363         .has_ddi = 1, \
 364         .has_fpga_dbg = 1, \
 365         .has_psr = 1, \
 366         .has_dp_mst = 1, \
 367         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 368         .has_runtime_pm = 1
 369
 370 #define HSW_PLATFORM \
 371         G75_FEATURES, \
 372         PLATFORM(INTEL_HASWELL), \
 373         .has_l3_dpf = 1
 374
 375 static const struct intel_device_info intel_haswell_gt1_info = {
 376         HSW_PLATFORM,
 377         .gt = 1,
 378 };
 379
 380 static const struct intel_device_info intel_haswell_gt2_info = {
 381         HSW_PLATFORM,
 382         .gt = 2,
 383 };
 384
 385 static const struct intel_device_info intel_haswell_gt3_info = {
 386         HSW_PLATFORM,
 387         .gt = 3,
 388 };
 389
 390 #define GEN8_FEATURES \
 391         G75_FEATURES, \
 392         GEN(8), \
 393         BDW_COLORS, \
 394         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 395                       I915_GTT_PAGE_SIZE_2M, \
 396         .has_logical_ring_contexts = 1, \
 397         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
 398         .has_64bit_reloc = 1, \
 399         .has_reset_engine = 1
 400
 401 #define BDW_PLATFORM \
 402         GEN8_FEATURES, \
 403         PLATFORM(INTEL_BROADWELL)
 404
 405 static const struct intel_device_info intel_broadwell_gt1_info = {
 406         BDW_PLATFORM,
 407         .gt = 1,
 408 };
 409
 410 static const struct intel_device_info intel_broadwell_gt2_info = {
 411         BDW_PLATFORM,
 412         .gt = 2,
 413 };
 414
 415 static const struct intel_device_info intel_broadwell_rsvd_info = {
 416         BDW_PLATFORM,
 417         .gt = 3,
 418         /* According to the device ID those devices are GT3, they were
 419          * previously treated as not GT3, keep it like that.
 420          */
 421 };
 422
 423 static const struct intel_device_info intel_broadwell_gt3_info = {
 424         BDW_PLATFORM,
 425         .gt = 3,
 426         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 427 };
 428
 429 static const struct intel_device_info intel_cherryview_info = {
 430         PLATFORM(INTEL_CHERRYVIEW),
 431         GEN(8),
 432         .num_pipes = 3,
 433         .has_hotplug = 1,
 434         .is_lp = 1,
 435         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 436         .has_64bit_reloc = 1,
 437         .has_runtime_pm = 1,
 438         .has_rc6 = 1,
 439         .has_logical_ring_contexts = 1,
 440         .has_gmch_display = 1,
 441         .ppgtt = INTEL_PPGTT_FULL,
 442         .has_reset_engine = 1,
 443         .has_snoop = true,
 444         .has_coherent_ggtt = false,
 445         .display_mmio_offset = VLV_DISPLAY_BASE,
 446         GEN_DEFAULT_PAGE_SIZES,
 447         GEN_CHV_PIPEOFFSETS,
 448         CURSOR_OFFSETS,
 449         CHV_COLORS,
 450 };
 451
 452 #define GEN9_DEFAULT_PAGE_SIZES \
 453         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 454                       I915_GTT_PAGE_SIZE_64K | \
 455                       I915_GTT_PAGE_SIZE_2M
 456
 457 #define GEN9_FEATURES \
 458         GEN8_FEATURES, \
 459         GEN(9), \
 460         GEN9_DEFAULT_PAGE_SIZES, \
 461         .has_logical_ring_preemption = 1, \
 462         .has_csr = 1, \
 463         .has_guc = 1, \
 464         .has_ipc = 1, \
 465         .ddb_size = 896
 466
 467 #define SKL_PLATFORM \
 468         GEN9_FEATURES, \
 469         /* Display WA #0477 WaDisableIPC: skl */ \
 470         .has_ipc = 0, \
 471         PLATFORM(INTEL_SKYLAKE)
 472
 473 static const struct intel_device_info intel_skylake_gt1_info = {
 474         SKL_PLATFORM,
 475         .gt = 1,
 476 };
 477
 478 static const struct intel_device_info intel_skylake_gt2_info = {
 479         SKL_PLATFORM,
 480         .gt = 2,
 481 };
 482
 483 #define SKL_GT3_PLUS_PLATFORM \
 484         SKL_PLATFORM, \
 485         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
 486
 487
 488 static const struct intel_device_info intel_skylake_gt3_info = {
 489         SKL_GT3_PLUS_PLATFORM,
 490         .gt = 3,
 491 };
 492
 493 static const struct intel_device_info intel_skylake_gt4_info = {
 494         SKL_GT3_PLUS_PLATFORM,
 495         .gt = 4,
 496 };
 497
 498 #define GEN9_LP_FEATURES \
 499         GEN(9), \
 500         .is_lp = 1, \
 501         .has_hotplug = 1, \
 502         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 503         .num_pipes = 3, \
 504         .has_64bit_reloc = 1, \
 505         .has_ddi = 1, \
 506         .has_fpga_dbg = 1, \
 507         .has_fbc = 1, \
 508         .has_psr = 1, \
 509         .has_runtime_pm = 1, \
 510         .has_pooled_eu = 0, \
 511         .has_csr = 1, \
 512         .has_rc6 = 1, \
 513         .has_dp_mst = 1, \
 514         .has_logical_ring_contexts = 1, \
 515         .has_logical_ring_preemption = 1, \
 516         .has_guc = 1, \
 517         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
 518         .has_reset_engine = 1, \
 519         .has_snoop = true, \
 520         .has_coherent_ggtt = false, \
 521         .has_ipc = 1, \
 522         GEN9_DEFAULT_PAGE_SIZES, \
 523         GEN_DEFAULT_PIPEOFFSETS, \
 524         IVB_CURSOR_OFFSETS, \
 525         BDW_COLORS
 526
 527 static const struct intel_device_info intel_broxton_info = {
 528         GEN9_LP_FEATURES,
 529         PLATFORM(INTEL_BROXTON),
 530         .ddb_size = 512,
 531 };
 532
 533 static const struct intel_device_info intel_geminilake_info = {
 534         GEN9_LP_FEATURES,
 535         PLATFORM(INTEL_GEMINILAKE),
 536         .ddb_size = 1024,
 537         GLK_COLORS,
 538 };
 539
 540 #define KBL_PLATFORM \
 541         GEN9_FEATURES, \
 542         PLATFORM(INTEL_KABYLAKE)
 543
 544 static const struct intel_device_info intel_kabylake_gt1_info = {
 545         KBL_PLATFORM,
 546         .gt = 1,
 547 };
 548
 549 static const struct intel_device_info intel_kabylake_gt2_info = {
 550         KBL_PLATFORM,
 551         .gt = 2,
 552 };
 553
 554 static const struct intel_device_info intel_kabylake_gt3_info = {
 555         KBL_PLATFORM,
 556         .gt = 3,
 557         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 558 };
 559
 560 #define CFL_PLATFORM \
 561         GEN9_FEATURES, \
 562         PLATFORM(INTEL_COFFEELAKE)
 563
 564 static const struct intel_device_info intel_coffeelake_gt1_info = {
 565         CFL_PLATFORM,
 566         .gt = 1,
 567 };
 568
 569 static const struct intel_device_info intel_coffeelake_gt2_info = {
 570         CFL_PLATFORM,
 571         .gt = 2,
 572 };
 573
 574 static const struct intel_device_info intel_coffeelake_gt3_info = {
 575         CFL_PLATFORM,
 576         .gt = 3,
 577         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 578 };
 579
 580 #define GEN10_FEATURES \
 581         GEN9_FEATURES, \
 582         GEN(10), \
 583         .ddb_size = 1024, \
 584         .has_coherent_ggtt = false, \
 585         GLK_COLORS
 586
 587 static const struct intel_device_info intel_cannonlake_info = {
 588         GEN10_FEATURES,
 589         PLATFORM(INTEL_CANNONLAKE),
 590         .gt = 2,
 591 };
 592
 593 #define GEN11_FEATURES \
 594         GEN10_FEATURES, \
 595         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
 596                           PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
 597                           PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
 598         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
 599                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
 600                            TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
 601         GEN(11), \
 602         .ddb_size = 2048, \
 603         .has_logical_ring_elsq = 1
 604
 605 static const struct intel_device_info intel_icelake_11_info = {
 606         GEN11_FEATURES,
 607         PLATFORM(INTEL_ICELAKE),
 608         .is_alpha_support = 1,
 609         .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
 610 };
 611
 612 #undef GEN
 613 #undef PLATFORM
 614
 615 /*
 616  * Make sure any device matches here are from most specific to most
 617  * general.  For example, since the Quanta match is based on the subsystem
 618  * and subvendor IDs, we need it to come before the more general IVB
 619  * PCI ID matches, otherwise we'll use the wrong info struct above.
 620  */
 621 static const struct pci_device_id pciidlist[] = {
 622         INTEL_I830_IDS(&intel_i830_info),
 623         INTEL_I845G_IDS(&intel_i845g_info),
 624         INTEL_I85X_IDS(&intel_i85x_info),
 625         INTEL_I865G_IDS(&intel_i865g_info),
 626         INTEL_I915G_IDS(&intel_i915g_info),
 627         INTEL_I915GM_IDS(&intel_i915gm_info),
 628         INTEL_I945G_IDS(&intel_i945g_info),
 629         INTEL_I945GM_IDS(&intel_i945gm_info),
 630         INTEL_I965G_IDS(&intel_i965g_info),
 631         INTEL_G33_IDS(&intel_g33_info),
 632         INTEL_I965GM_IDS(&intel_i965gm_info),
 633         INTEL_GM45_IDS(&intel_gm45_info),
 634         INTEL_G45_IDS(&intel_g45_info),
 635         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 636         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 637         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 638         INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 639         INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 640         INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 641         INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 642         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 643         INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 644         INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 645         INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 646         INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
 647         INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 648         INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 649         INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
 650         INTEL_VLV_IDS(&intel_valleyview_info),
 651         INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 652         INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 653         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 654         INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
 655         INTEL_CHV_IDS(&intel_cherryview_info),
 656         INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 657         INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 658         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 659         INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
 660         INTEL_BXT_IDS(&intel_broxton_info),
 661         INTEL_GLK_IDS(&intel_geminilake_info),
 662         INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 663         INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 664         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 665         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 666         INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 667         INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 668         INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 669         INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
 670         INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 671         INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 672         INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
 673         INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 674         INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
 675         INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 676         INTEL_CNL_IDS(&intel_cannonlake_info),
 677         INTEL_ICL_11_IDS(&intel_icelake_11_info),
 678         {0, 0, 0}
 679 };
 680 MODULE_DEVICE_TABLE(pci, pciidlist);
 681
 682 static void i915_pci_remove(struct pci_dev *pdev)
 683 {
 684         struct drm_device *dev;
 685
 686         dev = pci_get_drvdata(pdev);
 687         if (!dev) /* driver load aborted, nothing to cleanup */
 688                 return;
 689
 690         i915_driver_unload(dev);
 691         drm_dev_put(dev);
 692
 693         pci_set_drvdata(pdev, NULL);
 694 }
 695
 696 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 697 {
 698         struct intel_device_info *intel_info =
 699                 (struct intel_device_info *) ent->driver_data;
 700         int err;
 701
 702         if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
 703                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 704                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 705                          "to enable support in this kernel version, or check for kernel updates.\n");
 706                 return -ENODEV;
 707         }
 708
 709         /* Only bind to function 0 of the device. Early generations
 710          * used function 1 as a placeholder for multi-head. This causes
 711          * us confusion instead, especially on the systems where both
 712          * functions have the same PCI-ID!
 713          */
 714         if (PCI_FUNC(pdev->devfn))
 715                 return -ENODEV;
 716
 717         /*
 718          * apple-gmux is needed on dual GPU MacBook Pro
 719          * to probe the panel if we're the inactive GPU.
 720          */
 721         if (vga_switcheroo_client_probe_defer(pdev))
 722                 return -EPROBE_DEFER;
 723
 724         err = i915_driver_load(pdev, ent);
 725         if (err)
 726                 return err;
 727
 728         if (i915_inject_load_failure()) {
 729                 i915_pci_remove(pdev);
 730                 return -ENODEV;
 731         }
 732
 733         err = i915_live_selftests(pdev);
 734         if (err) {
 735                 i915_pci_remove(pdev);
 736                 return err > 0 ? -ENOTTY : err;
 737         }
 738
 739         return 0;
 740 }
 741
 742 static struct pci_driver i915_pci_driver = {
 743         .name = DRIVER_NAME,
 744         .id_table = pciidlist,
 745         .probe = i915_pci_probe,
 746         .remove = i915_pci_remove,
 747         .driver.pm = &i915_pm_ops,
 748 };
 749
 750 static int __init i915_init(void)
 751 {
 752         bool use_kms = true;
 753         int err;
 754
 755         err = i915_mock_selftests();
 756         if (err)
 757                 return err > 0 ? 0 : err;
 758
 759         /*
 760          * Enable KMS by default, unless explicitly overriden by
 761          * either the i915.modeset prarameter or by the
 762          * vga_text_mode_force boot option.
 763          */
 764
 765         if (i915_modparams.modeset == 0)
 766                 use_kms = false;
 767
 768         if (vgacon_text_force() && i915_modparams.modeset == -1)
 769                 use_kms = false;
 770
 771         if (!use_kms) {
 772                 /* Silently fail loading to not upset userspace. */
 773                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 774                 return 0;
 775         }
 776
 777         return pci_register_driver(&i915_pci_driver);
 778 }
 779
 780 static void __exit i915_exit(void)
 781 {
 782         if (!i915_pci_driver.driver.owner)
 783                 return;
 784
 785         pci_unregister_driver(&i915_pci_driver);
 786 }
 787
 788 module_init(i915_init);
 789 module_exit(i915_exit);
 790
 791 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 792 MODULE_AUTHOR("Intel Corporation");
 793
 794 MODULE_DESCRIPTION(DRIVER_DESC);
 795 MODULE_LICENSE("GPL and additional rights");