drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_color_mgmt.h>
  26 #include <drm/drm_drv.h>
  27 #include <drm/i915_pciids.h>
  28
  29 #include "i915_driver.h"
  30 #include "i915_drv.h"
  31 #include "i915_pci.h"
  32 #include "i915_reg.h"
  33 #include "intel_pci_config.h"
  34
  35 #define PLATFORM(x) .platform = (x)
  36 #define GEN(x) \
  37         .__runtime.graphics.ip.ver = (x), \
  38         .__runtime.media.ip.ver = (x), \
  39         .__runtime.display.ip.ver = (x)
  40
  41 #define NO_DISPLAY .__runtime.pipe_mask = 0
  42
  43 #define I845_PIPE_OFFSETS \
  44         .display.pipe_offsets = { \
  45                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  46         }, \
  47         .display.trans_offsets = { \
  48                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  49         }
  50
  51 #define I9XX_PIPE_OFFSETS \
  52         .display.pipe_offsets = { \
  53                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  54                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  55         }, \
  56         .display.trans_offsets = { \
  57                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  58                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  59         }
  60
  61 #define IVB_PIPE_OFFSETS \
  62         .display.pipe_offsets = { \
  63                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  64                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  65                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  66         }, \
  67         .display.trans_offsets = { \
  68                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  69                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  70                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  71         }
  72
  73 #define HSW_PIPE_OFFSETS \
  74         .display.pipe_offsets = { \
  75                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  76                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  77                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  78                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  79         }, \
  80         .display.trans_offsets = { \
  81                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  82                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  83                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  84                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  85         }
  86
  87 #define CHV_PIPE_OFFSETS \
  88         .display.pipe_offsets = { \
  89                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  90                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  91                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  92         }, \
  93         .display.trans_offsets = { \
  94                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  95                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  96                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  97         }
  98
  99 #define I845_CURSOR_OFFSETS \
 100         .display.cursor_offsets = { \
 101                 [PIPE_A] = CURSOR_A_OFFSET, \
 102         }
 103
 104 #define I9XX_CURSOR_OFFSETS \
 105         .display.cursor_offsets = { \
 106                 [PIPE_A] = CURSOR_A_OFFSET, \
 107                 [PIPE_B] = CURSOR_B_OFFSET, \
 108         }
 109
 110 #define CHV_CURSOR_OFFSETS \
 111         .display.cursor_offsets = { \
 112                 [PIPE_A] = CURSOR_A_OFFSET, \
 113                 [PIPE_B] = CURSOR_B_OFFSET, \
 114                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 115         }
 116
 117 #define IVB_CURSOR_OFFSETS \
 118         .display.cursor_offsets = { \
 119                 [PIPE_A] = CURSOR_A_OFFSET, \
 120                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 121                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 122         }
 123
 124 #define TGL_CURSOR_OFFSETS \
 125         .display.cursor_offsets = { \
 126                 [PIPE_A] = CURSOR_A_OFFSET, \
 127                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 128                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 129                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 130         }
 131
 132 #define I9XX_COLORS \
 133         .display.color = { .gamma_lut_size = 256 }
 134 #define I965_COLORS \
 135         .display.color = { .gamma_lut_size = 129, \
 136                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 137         }
 138 #define ILK_COLORS \
 139         .display.color = { .gamma_lut_size = 1024 }
 140 #define IVB_COLORS \
 141         .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 142 #define CHV_COLORS \
 143         .display.color = { \
 144                 .degamma_lut_size = 65, .gamma_lut_size = 257, \
 145                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 146                 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 147         }
 148 #define GLK_COLORS \
 149         .display.color = { \
 150                 .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 151                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 152                                      DRM_COLOR_LUT_EQUAL_CHANNELS, \
 153         }
 154 #define ICL_COLORS \
 155         .display.color = { \
 156                 .degamma_lut_size = 33, .gamma_lut_size = 262145, \
 157                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 158                                      DRM_COLOR_LUT_EQUAL_CHANNELS, \
 159                 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 160         }
 161
 162 /* Keep in gen based order, and chronological order within a gen */
 163
 164 #define GEN_DEFAULT_PAGE_SIZES \
 165         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K
 166
 167 #define GEN_DEFAULT_REGIONS \
 168         .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
 169
 170 #define I830_FEATURES \
 171         GEN(2), \
 172         .is_mobile = 1, \
 173         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 174         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 175         .display.has_overlay = 1, \
 176         .display.cursor_needs_physical = 1, \
 177         .display.overlay_needs_physical = 1, \
 178         .display.has_gmch = 1, \
 179         .gpu_reset_clobbers_display = true, \
 180         .has_3d_pipeline = 1, \
 181         .hws_needs_physical = 1, \
 182         .unfenced_needs_alignment = 1, \
 183         .__runtime.platform_engine_mask = BIT(RCS0), \
 184         .has_snoop = true, \
 185         .has_coherent_ggtt = false, \
 186         .dma_mask_size = 32, \
 187         I9XX_PIPE_OFFSETS, \
 188         I9XX_CURSOR_OFFSETS, \
 189         I9XX_COLORS, \
 190         GEN_DEFAULT_PAGE_SIZES, \
 191         GEN_DEFAULT_REGIONS
 192
 193 #define I845_FEATURES \
 194         GEN(2), \
 195         .__runtime.pipe_mask = BIT(PIPE_A), \
 196         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
 197         .display.has_overlay = 1, \
 198         .display.overlay_needs_physical = 1, \
 199         .display.has_gmch = 1, \
 200         .has_3d_pipeline = 1, \
 201         .gpu_reset_clobbers_display = true, \
 202         .hws_needs_physical = 1, \
 203         .unfenced_needs_alignment = 1, \
 204         .__runtime.platform_engine_mask = BIT(RCS0), \
 205         .has_snoop = true, \
 206         .has_coherent_ggtt = false, \
 207         .dma_mask_size = 32, \
 208         I845_PIPE_OFFSETS, \
 209         I845_CURSOR_OFFSETS, \
 210         I9XX_COLORS, \
 211         GEN_DEFAULT_PAGE_SIZES, \
 212         GEN_DEFAULT_REGIONS
 213
 214 static const struct intel_device_info i830_info = {
 215         I830_FEATURES,
 216         PLATFORM(INTEL_I830),
 217 };
 218
 219 static const struct intel_device_info i845g_info = {
 220         I845_FEATURES,
 221         PLATFORM(INTEL_I845G),
 222 };
 223
 224 static const struct intel_device_info i85x_info = {
 225         I830_FEATURES,
 226         PLATFORM(INTEL_I85X),
 227         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 228 };
 229
 230 static const struct intel_device_info i865g_info = {
 231         I845_FEATURES,
 232         PLATFORM(INTEL_I865G),
 233         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 234 };
 235
 236 #define GEN3_FEATURES \
 237         GEN(3), \
 238         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 239         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 240         .display.has_gmch = 1, \
 241         .gpu_reset_clobbers_display = true, \
 242         .__runtime.platform_engine_mask = BIT(RCS0), \
 243         .has_3d_pipeline = 1, \
 244         .has_snoop = true, \
 245         .has_coherent_ggtt = true, \
 246         .dma_mask_size = 32, \
 247         I9XX_PIPE_OFFSETS, \
 248         I9XX_CURSOR_OFFSETS, \
 249         I9XX_COLORS, \
 250         GEN_DEFAULT_PAGE_SIZES, \
 251         GEN_DEFAULT_REGIONS
 252
 253 static const struct intel_device_info i915g_info = {
 254         GEN3_FEATURES,
 255         PLATFORM(INTEL_I915G),
 256         .has_coherent_ggtt = false,
 257         .display.cursor_needs_physical = 1,
 258         .display.has_overlay = 1,
 259         .display.overlay_needs_physical = 1,
 260         .hws_needs_physical = 1,
 261         .unfenced_needs_alignment = 1,
 262 };
 263
 264 static const struct intel_device_info i915gm_info = {
 265         GEN3_FEATURES,
 266         PLATFORM(INTEL_I915GM),
 267         .is_mobile = 1,
 268         .display.cursor_needs_physical = 1,
 269         .display.has_overlay = 1,
 270         .display.overlay_needs_physical = 1,
 271         .display.supports_tv = 1,
 272         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 273         .hws_needs_physical = 1,
 274         .unfenced_needs_alignment = 1,
 275 };
 276
 277 static const struct intel_device_info i945g_info = {
 278         GEN3_FEATURES,
 279         PLATFORM(INTEL_I945G),
 280         .display.has_hotplug = 1,
 281         .display.cursor_needs_physical = 1,
 282         .display.has_overlay = 1,
 283         .display.overlay_needs_physical = 1,
 284         .hws_needs_physical = 1,
 285         .unfenced_needs_alignment = 1,
 286 };
 287
 288 static const struct intel_device_info i945gm_info = {
 289         GEN3_FEATURES,
 290         PLATFORM(INTEL_I945GM),
 291         .is_mobile = 1,
 292         .display.has_hotplug = 1,
 293         .display.cursor_needs_physical = 1,
 294         .display.has_overlay = 1,
 295         .display.overlay_needs_physical = 1,
 296         .display.supports_tv = 1,
 297         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 298         .hws_needs_physical = 1,
 299         .unfenced_needs_alignment = 1,
 300 };
 301
 302 static const struct intel_device_info g33_info = {
 303         GEN3_FEATURES,
 304         PLATFORM(INTEL_G33),
 305         .display.has_hotplug = 1,
 306         .display.has_overlay = 1,
 307         .dma_mask_size = 36,
 308 };
 309
 310 static const struct intel_device_info pnv_g_info = {
 311         GEN3_FEATURES,
 312         PLATFORM(INTEL_PINEVIEW),
 313         .display.has_hotplug = 1,
 314         .display.has_overlay = 1,
 315         .dma_mask_size = 36,
 316 };
 317
 318 static const struct intel_device_info pnv_m_info = {
 319         GEN3_FEATURES,
 320         PLATFORM(INTEL_PINEVIEW),
 321         .is_mobile = 1,
 322         .display.has_hotplug = 1,
 323         .display.has_overlay = 1,
 324         .dma_mask_size = 36,
 325 };
 326
 327 #define GEN4_FEATURES \
 328         GEN(4), \
 329         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 330         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 331         .display.has_hotplug = 1, \
 332         .display.has_gmch = 1, \
 333         .gpu_reset_clobbers_display = true, \
 334         .__runtime.platform_engine_mask = BIT(RCS0), \
 335         .has_3d_pipeline = 1, \
 336         .has_snoop = true, \
 337         .has_coherent_ggtt = true, \
 338         .dma_mask_size = 36, \
 339         I9XX_PIPE_OFFSETS, \
 340         I9XX_CURSOR_OFFSETS, \
 341         I965_COLORS, \
 342         GEN_DEFAULT_PAGE_SIZES, \
 343         GEN_DEFAULT_REGIONS
 344
 345 static const struct intel_device_info i965g_info = {
 346         GEN4_FEATURES,
 347         PLATFORM(INTEL_I965G),
 348         .display.has_overlay = 1,
 349         .hws_needs_physical = 1,
 350         .has_snoop = false,
 351 };
 352
 353 static const struct intel_device_info i965gm_info = {
 354         GEN4_FEATURES,
 355         PLATFORM(INTEL_I965GM),
 356         .is_mobile = 1,
 357         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 358         .display.has_overlay = 1,
 359         .display.supports_tv = 1,
 360         .hws_needs_physical = 1,
 361         .has_snoop = false,
 362 };
 363
 364 static const struct intel_device_info g45_info = {
 365         GEN4_FEATURES,
 366         PLATFORM(INTEL_G45),
 367         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 368         .gpu_reset_clobbers_display = false,
 369 };
 370
 371 static const struct intel_device_info gm45_info = {
 372         GEN4_FEATURES,
 373         PLATFORM(INTEL_GM45),
 374         .is_mobile = 1,
 375         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 376         .display.supports_tv = 1,
 377         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 378         .gpu_reset_clobbers_display = false,
 379 };
 380
 381 #define GEN5_FEATURES \
 382         GEN(5), \
 383         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 384         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 385         .display.has_hotplug = 1, \
 386         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 387         .has_3d_pipeline = 1, \
 388         .has_snoop = true, \
 389         .has_coherent_ggtt = true, \
 390         /* ilk does support rc6, but we do not implement [power] contexts */ \
 391         .has_rc6 = 0, \
 392         .dma_mask_size = 36, \
 393         I9XX_PIPE_OFFSETS, \
 394         I9XX_CURSOR_OFFSETS, \
 395         ILK_COLORS, \
 396         GEN_DEFAULT_PAGE_SIZES, \
 397         GEN_DEFAULT_REGIONS
 398
 399 static const struct intel_device_info ilk_d_info = {
 400         GEN5_FEATURES,
 401         PLATFORM(INTEL_IRONLAKE),
 402 };
 403
 404 static const struct intel_device_info ilk_m_info = {
 405         GEN5_FEATURES,
 406         PLATFORM(INTEL_IRONLAKE),
 407         .is_mobile = 1,
 408         .has_rps = true,
 409         .__runtime.fbc_mask = BIT(INTEL_FBC_A),
 410 };
 411
 412 #define GEN6_FEATURES \
 413         GEN(6), \
 414         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 415         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 416         .display.has_hotplug = 1, \
 417         .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 418         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 419         .has_3d_pipeline = 1, \
 420         .has_coherent_ggtt = true, \
 421         .has_llc = 1, \
 422         .has_rc6 = 1, \
 423         .has_rc6p = 1, \
 424         .has_rps = true, \
 425         .dma_mask_size = 40, \
 426         .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
 427         .__runtime.ppgtt_size = 31, \
 428         I9XX_PIPE_OFFSETS, \
 429         I9XX_CURSOR_OFFSETS, \
 430         ILK_COLORS, \
 431         GEN_DEFAULT_PAGE_SIZES, \
 432         GEN_DEFAULT_REGIONS
 433
 434 #define SNB_D_PLATFORM \
 435         GEN6_FEATURES, \
 436         PLATFORM(INTEL_SANDYBRIDGE)
 437
 438 static const struct intel_device_info snb_d_gt1_info = {
 439         SNB_D_PLATFORM,
 440         .gt = 1,
 441 };
 442
 443 static const struct intel_device_info snb_d_gt2_info = {
 444         SNB_D_PLATFORM,
 445         .gt = 2,
 446 };
 447
 448 #define SNB_M_PLATFORM \
 449         GEN6_FEATURES, \
 450         PLATFORM(INTEL_SANDYBRIDGE), \
 451         .is_mobile = 1
 452
 453
 454 static const struct intel_device_info snb_m_gt1_info = {
 455         SNB_M_PLATFORM,
 456         .gt = 1,
 457 };
 458
 459 static const struct intel_device_info snb_m_gt2_info = {
 460         SNB_M_PLATFORM,
 461         .gt = 2,
 462 };
 463
 464 #define GEN7_FEATURES  \
 465         GEN(7), \
 466         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 467         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
 468         .display.has_hotplug = 1, \
 469         .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 470         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 471         .has_3d_pipeline = 1, \
 472         .has_coherent_ggtt = true, \
 473         .has_llc = 1, \
 474         .has_rc6 = 1, \
 475         .has_rc6p = 1, \
 476         .has_reset_engine = true, \
 477         .has_rps = true, \
 478         .dma_mask_size = 40, \
 479         .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
 480         .__runtime.ppgtt_size = 31, \
 481         IVB_PIPE_OFFSETS, \
 482         IVB_CURSOR_OFFSETS, \
 483         IVB_COLORS, \
 484         GEN_DEFAULT_PAGE_SIZES, \
 485         GEN_DEFAULT_REGIONS
 486
 487 #define IVB_D_PLATFORM \
 488         GEN7_FEATURES, \
 489         PLATFORM(INTEL_IVYBRIDGE), \
 490         .has_l3_dpf = 1
 491
 492 static const struct intel_device_info ivb_d_gt1_info = {
 493         IVB_D_PLATFORM,
 494         .gt = 1,
 495 };
 496
 497 static const struct intel_device_info ivb_d_gt2_info = {
 498         IVB_D_PLATFORM,
 499         .gt = 2,
 500 };
 501
 502 #define IVB_M_PLATFORM \
 503         GEN7_FEATURES, \
 504         PLATFORM(INTEL_IVYBRIDGE), \
 505         .is_mobile = 1, \
 506         .has_l3_dpf = 1
 507
 508 static const struct intel_device_info ivb_m_gt1_info = {
 509         IVB_M_PLATFORM,
 510         .gt = 1,
 511 };
 512
 513 static const struct intel_device_info ivb_m_gt2_info = {
 514         IVB_M_PLATFORM,
 515         .gt = 2,
 516 };
 517
 518 static const struct intel_device_info ivb_q_info = {
 519         GEN7_FEATURES,
 520         PLATFORM(INTEL_IVYBRIDGE),
 521         NO_DISPLAY,
 522         .gt = 2,
 523         .has_l3_dpf = 1,
 524 };
 525
 526 static const struct intel_device_info vlv_info = {
 527         PLATFORM(INTEL_VALLEYVIEW),
 528         GEN(7),
 529         .is_lp = 1,
 530         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 531         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 532         .has_runtime_pm = 1,
 533         .has_rc6 = 1,
 534         .has_reset_engine = true,
 535         .has_rps = true,
 536         .display.has_gmch = 1,
 537         .display.has_hotplug = 1,
 538         .dma_mask_size = 40,
 539         .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
 540         .__runtime.ppgtt_size = 31,
 541         .has_snoop = true,
 542         .has_coherent_ggtt = false,
 543         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 544         .display.mmio_offset = VLV_DISPLAY_BASE,
 545         I9XX_PIPE_OFFSETS,
 546         I9XX_CURSOR_OFFSETS,
 547         I965_COLORS,
 548         GEN_DEFAULT_PAGE_SIZES,
 549         GEN_DEFAULT_REGIONS,
 550 };
 551
 552 #define G75_FEATURES  \
 553         GEN7_FEATURES, \
 554         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 555         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 556                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 557         .display.has_ddi = 1, \
 558         .display.has_fpga_dbg = 1, \
 559         .display.has_dp_mst = 1, \
 560         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 561         HSW_PIPE_OFFSETS, \
 562         .has_runtime_pm = 1
 563
 564 #define HSW_PLATFORM \
 565         G75_FEATURES, \
 566         PLATFORM(INTEL_HASWELL), \
 567         .has_l3_dpf = 1
 568
 569 static const struct intel_device_info hsw_gt1_info = {
 570         HSW_PLATFORM,
 571         .gt = 1,
 572 };
 573
 574 static const struct intel_device_info hsw_gt2_info = {
 575         HSW_PLATFORM,
 576         .gt = 2,
 577 };
 578
 579 static const struct intel_device_info hsw_gt3_info = {
 580         HSW_PLATFORM,
 581         .gt = 3,
 582 };
 583
 584 #define GEN8_FEATURES \
 585         G75_FEATURES, \
 586         GEN(8), \
 587         .has_logical_ring_contexts = 1, \
 588         .dma_mask_size = 39, \
 589         .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
 590         .__runtime.ppgtt_size = 48, \
 591         .has_64bit_reloc = 1
 592
 593 #define BDW_PLATFORM \
 594         GEN8_FEATURES, \
 595         PLATFORM(INTEL_BROADWELL)
 596
 597 static const struct intel_device_info bdw_gt1_info = {
 598         BDW_PLATFORM,
 599         .gt = 1,
 600 };
 601
 602 static const struct intel_device_info bdw_gt2_info = {
 603         BDW_PLATFORM,
 604         .gt = 2,
 605 };
 606
 607 static const struct intel_device_info bdw_rsvd_info = {
 608         BDW_PLATFORM,
 609         .gt = 3,
 610         /* According to the device ID those devices are GT3, they were
 611          * previously treated as not GT3, keep it like that.
 612          */
 613 };
 614
 615 static const struct intel_device_info bdw_gt3_info = {
 616         BDW_PLATFORM,
 617         .gt = 3,
 618         .__runtime.platform_engine_mask =
 619                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 620 };
 621
 622 static const struct intel_device_info chv_info = {
 623         PLATFORM(INTEL_CHERRYVIEW),
 624         GEN(8),
 625         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 626         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 627         .display.has_hotplug = 1,
 628         .is_lp = 1,
 629         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 630         .has_64bit_reloc = 1,
 631         .has_runtime_pm = 1,
 632         .has_rc6 = 1,
 633         .has_rps = true,
 634         .has_logical_ring_contexts = 1,
 635         .display.has_gmch = 1,
 636         .dma_mask_size = 39,
 637         .__runtime.ppgtt_type = INTEL_PPGTT_FULL,
 638         .__runtime.ppgtt_size = 32,
 639         .has_reset_engine = 1,
 640         .has_snoop = true,
 641         .has_coherent_ggtt = false,
 642         .display.mmio_offset = VLV_DISPLAY_BASE,
 643         CHV_PIPE_OFFSETS,
 644         CHV_CURSOR_OFFSETS,
 645         CHV_COLORS,
 646         GEN_DEFAULT_PAGE_SIZES,
 647         GEN_DEFAULT_REGIONS,
 648 };
 649
 650 #define GEN9_DEFAULT_PAGE_SIZES \
 651         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 652                 I915_GTT_PAGE_SIZE_64K
 653
 654 #define GEN9_FEATURES \
 655         GEN8_FEATURES, \
 656         GEN(9), \
 657         GEN9_DEFAULT_PAGE_SIZES, \
 658         .__runtime.has_dmc = 1, \
 659         .has_gt_uc = 1, \
 660         .__runtime.has_hdcp = 1, \
 661         .display.has_ipc = 1, \
 662         .display.has_psr = 1, \
 663         .display.has_psr_hw_tracking = 1, \
 664         .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
 665         .display.dbuf.slice_mask = BIT(DBUF_S1)
 666
 667 #define SKL_PLATFORM \
 668         GEN9_FEATURES, \
 669         PLATFORM(INTEL_SKYLAKE)
 670
 671 static const struct intel_device_info skl_gt1_info = {
 672         SKL_PLATFORM,
 673         .gt = 1,
 674 };
 675
 676 static const struct intel_device_info skl_gt2_info = {
 677         SKL_PLATFORM,
 678         .gt = 2,
 679 };
 680
 681 #define SKL_GT3_PLUS_PLATFORM \
 682         SKL_PLATFORM, \
 683         .__runtime.platform_engine_mask = \
 684                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
 685
 686
 687 static const struct intel_device_info skl_gt3_info = {
 688         SKL_GT3_PLUS_PLATFORM,
 689         .gt = 3,
 690 };
 691
 692 static const struct intel_device_info skl_gt4_info = {
 693         SKL_GT3_PLUS_PLATFORM,
 694         .gt = 4,
 695 };
 696
 697 #define GEN9_LP_FEATURES \
 698         GEN(9), \
 699         .is_lp = 1, \
 700         .display.dbuf.slice_mask = BIT(DBUF_S1), \
 701         .display.has_hotplug = 1, \
 702         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 703         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 704         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 705                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 706                 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 707         .has_3d_pipeline = 1, \
 708         .has_64bit_reloc = 1, \
 709         .display.has_ddi = 1, \
 710         .display.has_fpga_dbg = 1, \
 711         .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
 712         .__runtime.has_hdcp = 1, \
 713         .display.has_psr = 1, \
 714         .display.has_psr_hw_tracking = 1, \
 715         .has_runtime_pm = 1, \
 716         .__runtime.has_dmc = 1, \
 717         .has_rc6 = 1, \
 718         .has_rps = true, \
 719         .display.has_dp_mst = 1, \
 720         .has_logical_ring_contexts = 1, \
 721         .has_gt_uc = 1, \
 722         .dma_mask_size = 39, \
 723         .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
 724         .__runtime.ppgtt_size = 48, \
 725         .has_reset_engine = 1, \
 726         .has_snoop = true, \
 727         .has_coherent_ggtt = false, \
 728         .display.has_ipc = 1, \
 729         HSW_PIPE_OFFSETS, \
 730         IVB_CURSOR_OFFSETS, \
 731         IVB_COLORS, \
 732         GEN9_DEFAULT_PAGE_SIZES, \
 733         GEN_DEFAULT_REGIONS
 734
 735 static const struct intel_device_info bxt_info = {
 736         GEN9_LP_FEATURES,
 737         PLATFORM(INTEL_BROXTON),
 738         .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
 739 };
 740
 741 static const struct intel_device_info glk_info = {
 742         GEN9_LP_FEATURES,
 743         PLATFORM(INTEL_GEMINILAKE),
 744         .__runtime.display.ip.ver = 10,
 745         .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
 746         GLK_COLORS,
 747 };
 748
 749 #define KBL_PLATFORM \
 750         GEN9_FEATURES, \
 751         PLATFORM(INTEL_KABYLAKE)
 752
 753 static const struct intel_device_info kbl_gt1_info = {
 754         KBL_PLATFORM,
 755         .gt = 1,
 756 };
 757
 758 static const struct intel_device_info kbl_gt2_info = {
 759         KBL_PLATFORM,
 760         .gt = 2,
 761 };
 762
 763 static const struct intel_device_info kbl_gt3_info = {
 764         KBL_PLATFORM,
 765         .gt = 3,
 766         .__runtime.platform_engine_mask =
 767                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 768 };
 769
 770 #define CFL_PLATFORM \
 771         GEN9_FEATURES, \
 772         PLATFORM(INTEL_COFFEELAKE)
 773
 774 static const struct intel_device_info cfl_gt1_info = {
 775         CFL_PLATFORM,
 776         .gt = 1,
 777 };
 778
 779 static const struct intel_device_info cfl_gt2_info = {
 780         CFL_PLATFORM,
 781         .gt = 2,
 782 };
 783
 784 static const struct intel_device_info cfl_gt3_info = {
 785         CFL_PLATFORM,
 786         .gt = 3,
 787         .__runtime.platform_engine_mask =
 788                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 789 };
 790
 791 #define CML_PLATFORM \
 792         GEN9_FEATURES, \
 793         PLATFORM(INTEL_COMETLAKE)
 794
 795 static const struct intel_device_info cml_gt1_info = {
 796         CML_PLATFORM,
 797         .gt = 1,
 798 };
 799
 800 static const struct intel_device_info cml_gt2_info = {
 801         CML_PLATFORM,
 802         .gt = 2,
 803 };
 804
 805 #define GEN11_DEFAULT_PAGE_SIZES \
 806         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 807                 I915_GTT_PAGE_SIZE_64K |                \
 808                 I915_GTT_PAGE_SIZE_2M
 809
 810 #define GEN11_FEATURES \
 811         GEN9_FEATURES, \
 812         GEN11_DEFAULT_PAGE_SIZES, \
 813         .display.abox_mask = BIT(0), \
 814         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 815                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 816                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 817         .display.pipe_offsets = { \
 818                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 819                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 820                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 821                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 822                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 823                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 824         }, \
 825         .display.trans_offsets = { \
 826                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 827                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 828                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 829                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 830                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 831                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 832         }, \
 833         GEN(11), \
 834         ICL_COLORS, \
 835         .display.dbuf.size = 2048, \
 836         .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
 837         .__runtime.has_dsc = 1, \
 838         .has_coherent_ggtt = false, \
 839         .has_logical_ring_elsq = 1
 840
 841 static const struct intel_device_info icl_info = {
 842         GEN11_FEATURES,
 843         PLATFORM(INTEL_ICELAKE),
 844         .__runtime.platform_engine_mask =
 845                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 846 };
 847
 848 static const struct intel_device_info ehl_info = {
 849         GEN11_FEATURES,
 850         PLATFORM(INTEL_ELKHARTLAKE),
 851         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 852         .__runtime.ppgtt_size = 36,
 853 };
 854
 855 static const struct intel_device_info jsl_info = {
 856         GEN11_FEATURES,
 857         PLATFORM(INTEL_JASPERLAKE),
 858         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 859         .__runtime.ppgtt_size = 36,
 860 };
 861
 862 #define GEN12_FEATURES \
 863         GEN11_FEATURES, \
 864         GEN(12), \
 865         .display.abox_mask = GENMASK(2, 1), \
 866         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
 867         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 868                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 869                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 870         .display.pipe_offsets = { \
 871                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 872                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 873                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 874                 [TRANSCODER_D] = PIPE_D_OFFSET, \
 875                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 876                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 877         }, \
 878         .display.trans_offsets = { \
 879                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 880                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 881                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 882                 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
 883                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 884                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 885         }, \
 886         TGL_CURSOR_OFFSETS, \
 887         .has_global_mocs = 1, \
 888         .has_pxp = 1, \
 889         .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
 890
 891 static const struct intel_device_info tgl_info = {
 892         GEN12_FEATURES,
 893         PLATFORM(INTEL_TIGERLAKE),
 894         .display.has_modular_fia = 1,
 895         .__runtime.platform_engine_mask =
 896                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 897 };
 898
 899 static const struct intel_device_info rkl_info = {
 900         GEN12_FEATURES,
 901         PLATFORM(INTEL_ROCKETLAKE),
 902         .display.abox_mask = BIT(0),
 903         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 904         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 905                 BIT(TRANSCODER_C),
 906         .display.has_hti = 1,
 907         .display.has_psr_hw_tracking = 0,
 908         .__runtime.platform_engine_mask =
 909                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 910 };
 911
 912 #define DGFX_FEATURES \
 913         .__runtime.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
 914         .has_llc = 0, \
 915         .has_pxp = 0, \
 916         .has_snoop = 1, \
 917         .is_dgfx = 1, \
 918         .has_heci_gscfi = 1
 919
 920 static const struct intel_device_info dg1_info = {
 921         GEN12_FEATURES,
 922         DGFX_FEATURES,
 923         .__runtime.graphics.ip.rel = 10,
 924         PLATFORM(INTEL_DG1),
 925         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 926         .require_force_probe = 1,
 927         .__runtime.platform_engine_mask =
 928                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
 929                 BIT(VCS0) | BIT(VCS2),
 930         /* Wa_16011227922 */
 931         .__runtime.ppgtt_size = 47,
 932 };
 933
 934 static const struct intel_device_info adl_s_info = {
 935         GEN12_FEATURES,
 936         PLATFORM(INTEL_ALDERLAKE_S),
 937         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 938         .display.has_hti = 1,
 939         .display.has_psr_hw_tracking = 0,
 940         .__runtime.platform_engine_mask =
 941                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 942         .dma_mask_size = 39,
 943 };
 944
 945 #define XE_LPD_FEATURES \
 946         .display.abox_mask = GENMASK(1, 0),                                     \
 947         .display.color = {                                                      \
 948                 .degamma_lut_size = 128, .gamma_lut_size = 1024,                \
 949                 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |             \
 950                                      DRM_COLOR_LUT_EQUAL_CHANNELS,              \
 951         },                                                                      \
 952         .display.dbuf.size = 4096,                                              \
 953         .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
 954                 BIT(DBUF_S4),                                                   \
 955         .display.has_ddi = 1,                                                   \
 956         .__runtime.has_dmc = 1,                                                 \
 957         .display.has_dp_mst = 1,                                                \
 958         .display.has_dsb = 1,                                                   \
 959         .__runtime.has_dsc = 1,                                                 \
 960         .__runtime.fbc_mask = BIT(INTEL_FBC_A),                                 \
 961         .display.has_fpga_dbg = 1,                                              \
 962         .__runtime.has_hdcp = 1,                                                \
 963         .display.has_hotplug = 1,                                               \
 964         .display.has_ipc = 1,                                                   \
 965         .display.has_psr = 1,                                                   \
 966         .__runtime.display.ip.ver = 13,                                                 \
 967         .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),   \
 968         .display.pipe_offsets = {                                               \
 969                 [TRANSCODER_A] = PIPE_A_OFFSET,                                 \
 970                 [TRANSCODER_B] = PIPE_B_OFFSET,                                 \
 971                 [TRANSCODER_C] = PIPE_C_OFFSET,                                 \
 972                 [TRANSCODER_D] = PIPE_D_OFFSET,                                 \
 973                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,                          \
 974                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,                          \
 975         },                                                                      \
 976         .display.trans_offsets = {                                              \
 977                 [TRANSCODER_A] = TRANSCODER_A_OFFSET,                           \
 978                 [TRANSCODER_B] = TRANSCODER_B_OFFSET,                           \
 979                 [TRANSCODER_C] = TRANSCODER_C_OFFSET,                           \
 980                 [TRANSCODER_D] = TRANSCODER_D_OFFSET,                           \
 981                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,                    \
 982                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,                    \
 983         },                                                                      \
 984         TGL_CURSOR_OFFSETS
 985
 986 static const struct intel_device_info adl_p_info = {
 987         GEN12_FEATURES,
 988         XE_LPD_FEATURES,
 989         PLATFORM(INTEL_ALDERLAKE_P),
 990         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 991                                BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
 992                                BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
 993         .display.has_cdclk_crawl = 1,
 994         .display.has_modular_fia = 1,
 995         .display.has_psr_hw_tracking = 0,
 996         .__runtime.platform_engine_mask =
 997                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 998         .__runtime.ppgtt_size = 48,
 999         .dma_mask_size = 39,
1000 };
1001
1002 #undef GEN
1003
1004 #define XE_HP_PAGE_SIZES \
1005         .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
1006                 I915_GTT_PAGE_SIZE_64K |                \
1007                 I915_GTT_PAGE_SIZE_2M
1008
1009 #define XE_HP_FEATURES \
1010         .__runtime.graphics.ip.ver = 12, \
1011         .__runtime.graphics.ip.rel = 50, \
1012         XE_HP_PAGE_SIZES, \
1013         .dma_mask_size = 46, \
1014         .has_3d_pipeline = 1, \
1015         .has_64bit_reloc = 1, \
1016         .has_flat_ccs = 1, \
1017         .has_global_mocs = 1, \
1018         .has_gt_uc = 1, \
1019         .has_llc = 1, \
1020         .has_logical_ring_contexts = 1, \
1021         .has_logical_ring_elsq = 1, \
1022         .has_mslice_steering = 1, \
1023         .has_rc6 = 1, \
1024         .has_reset_engine = 1, \
1025         .has_rps = 1, \
1026         .has_runtime_pm = 1, \
1027         .__runtime.ppgtt_size = 48, \
1028         .__runtime.ppgtt_type = INTEL_PPGTT_FULL
1029
1030 #define XE_HPM_FEATURES \
1031         .__runtime.media.ip.ver = 12, \
1032         .__runtime.media.ip.rel = 50
1033
1034 __maybe_unused
1035 static const struct intel_device_info xehpsdv_info = {
1036         XE_HP_FEATURES,
1037         XE_HPM_FEATURES,
1038         DGFX_FEATURES,
1039         PLATFORM(INTEL_XEHPSDV),
1040         NO_DISPLAY,
1041         .has_64k_pages = 1,
1042         .needs_compact_pt = 1,
1043         .has_media_ratio_mode = 1,
1044         .__runtime.platform_engine_mask =
1045                 BIT(RCS0) | BIT(BCS0) |
1046                 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1047                 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1048                 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
1049                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1050         .require_force_probe = 1,
1051 };
1052
1053 #define DG2_FEATURES \
1054         XE_HP_FEATURES, \
1055         XE_HPM_FEATURES, \
1056         DGFX_FEATURES, \
1057         .__runtime.graphics.ip.rel = 55, \
1058         .__runtime.media.ip.rel = 55, \
1059         PLATFORM(INTEL_DG2), \
1060         .has_4tile = 1, \
1061         .has_64k_pages = 1, \
1062         .has_guc_deprivilege = 1, \
1063         .has_heci_pxp = 1, \
1064         .needs_compact_pt = 1, \
1065         .has_media_ratio_mode = 1, \
1066         .display.has_cdclk_squash = 1, \
1067         .__runtime.platform_engine_mask = \
1068                 BIT(RCS0) | BIT(BCS0) | \
1069                 BIT(VECS0) | BIT(VECS1) | \
1070                 BIT(VCS0) | BIT(VCS2) | \
1071                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
1072
1073 static const struct intel_device_info dg2_info = {
1074         DG2_FEATURES,
1075         XE_LPD_FEATURES,
1076         .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1077                                BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1078         .require_force_probe = 1,
1079 };
1080
1081 static const struct intel_device_info ats_m_info = {
1082         DG2_FEATURES,
1083         NO_DISPLAY,
1084         .require_force_probe = 1,
1085 };
1086
1087 #define XE_HPC_FEATURES \
1088         XE_HP_FEATURES, \
1089         .dma_mask_size = 52, \
1090         .has_3d_pipeline = 0, \
1091         .has_guc_deprivilege = 1, \
1092         .has_l3_ccs_read = 1, \
1093         .has_mslice_steering = 0, \
1094         .has_one_eu_per_fuse_bit = 1
1095
1096 __maybe_unused
1097 static const struct intel_device_info pvc_info = {
1098         XE_HPC_FEATURES,
1099         XE_HPM_FEATURES,
1100         DGFX_FEATURES,
1101         .__runtime.graphics.ip.rel = 60,
1102         .__runtime.media.ip.rel = 60,
1103         PLATFORM(INTEL_PONTEVECCHIO),
1104         NO_DISPLAY,
1105         .has_flat_ccs = 0,
1106         .__runtime.platform_engine_mask =
1107                 BIT(BCS0) |
1108                 BIT(VCS0) |
1109                 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1110         .require_force_probe = 1,
1111 };
1112
1113 #define XE_LPDP_FEATURES        \
1114         XE_LPD_FEATURES,        \
1115         .__runtime.display.ip.ver = 14, \
1116         .display.has_cdclk_crawl = 1, \
1117         .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
1118
1119 __maybe_unused
1120 static const struct intel_device_info mtl_info = {
1121         XE_HP_FEATURES,
1122         XE_LPDP_FEATURES,
1123         /*
1124          * Real graphics IP version will be obtained from hardware GMD_ID
1125          * register.  Value provided here is just for sanity checking.
1126          */
1127         .__runtime.graphics.ip.ver = 12,
1128         .__runtime.graphics.ip.rel = 70,
1129         .__runtime.media.ip.ver = 13,
1130         PLATFORM(INTEL_METEORLAKE),
1131         .display.has_modular_fia = 1,
1132         .has_flat_ccs = 0,
1133         .has_gmd_id = 1,
1134         .has_snoop = 1,
1135         .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
1136         .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
1137         .require_force_probe = 1,
1138 };
1139
1140 #undef PLATFORM
1141
1142 /*
1143  * Make sure any device matches here are from most specific to most
1144  * general.  For example, since the Quanta match is based on the subsystem
1145  * and subvendor IDs, we need it to come before the more general IVB
1146  * PCI ID matches, otherwise we'll use the wrong info struct above.
1147  */
1148 static const struct pci_device_id pciidlist[] = {
1149         INTEL_I830_IDS(&i830_info),
1150         INTEL_I845G_IDS(&i845g_info),
1151         INTEL_I85X_IDS(&i85x_info),
1152         INTEL_I865G_IDS(&i865g_info),
1153         INTEL_I915G_IDS(&i915g_info),
1154         INTEL_I915GM_IDS(&i915gm_info),
1155         INTEL_I945G_IDS(&i945g_info),
1156         INTEL_I945GM_IDS(&i945gm_info),
1157         INTEL_I965G_IDS(&i965g_info),
1158         INTEL_G33_IDS(&g33_info),
1159         INTEL_I965GM_IDS(&i965gm_info),
1160         INTEL_GM45_IDS(&gm45_info),
1161         INTEL_G45_IDS(&g45_info),
1162         INTEL_PINEVIEW_G_IDS(&pnv_g_info),
1163         INTEL_PINEVIEW_M_IDS(&pnv_m_info),
1164         INTEL_IRONLAKE_D_IDS(&ilk_d_info),
1165         INTEL_IRONLAKE_M_IDS(&ilk_m_info),
1166         INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
1167         INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
1168         INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
1169         INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
1170         INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
1171         INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
1172         INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
1173         INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1174         INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1175         INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1176         INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1177         INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1178         INTEL_VLV_IDS(&vlv_info),
1179         INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1180         INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1181         INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1182         INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1183         INTEL_CHV_IDS(&chv_info),
1184         INTEL_SKL_GT1_IDS(&skl_gt1_info),
1185         INTEL_SKL_GT2_IDS(&skl_gt2_info),
1186         INTEL_SKL_GT3_IDS(&skl_gt3_info),
1187         INTEL_SKL_GT4_IDS(&skl_gt4_info),
1188         INTEL_BXT_IDS(&bxt_info),
1189         INTEL_GLK_IDS(&glk_info),
1190         INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1191         INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1192         INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1193         INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1194         INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1195         INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1196         INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1197         INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1198         INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1199         INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1200         INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1201         INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1202         INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1203         INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1204         INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1205         INTEL_CML_GT1_IDS(&cml_gt1_info),
1206         INTEL_CML_GT2_IDS(&cml_gt2_info),
1207         INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1208         INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1209         INTEL_ICL_11_IDS(&icl_info),
1210         INTEL_EHL_IDS(&ehl_info),
1211         INTEL_JSL_IDS(&jsl_info),
1212         INTEL_TGL_12_IDS(&tgl_info),
1213         INTEL_RKL_IDS(&rkl_info),
1214         INTEL_ADLS_IDS(&adl_s_info),
1215         INTEL_ADLP_IDS(&adl_p_info),
1216         INTEL_ADLN_IDS(&adl_p_info),
1217         INTEL_DG1_IDS(&dg1_info),
1218         INTEL_RPLS_IDS(&adl_s_info),
1219         INTEL_RPLP_IDS(&adl_p_info),
1220         INTEL_DG2_IDS(&dg2_info),
1221         INTEL_ATS_M_IDS(&ats_m_info),
1222         INTEL_MTL_IDS(&mtl_info),
1223         {0, 0, 0}
1224 };
1225 MODULE_DEVICE_TABLE(pci, pciidlist);
1226
1227 static void i915_pci_remove(struct pci_dev *pdev)
1228 {
1229         struct drm_i915_private *i915;
1230
1231         i915 = pci_get_drvdata(pdev);
1232         if (!i915) /* driver load aborted, nothing to cleanup */
1233                 return;
1234
1235         i915_driver_remove(i915);
1236         pci_set_drvdata(pdev, NULL);
1237 }
1238
1239 /* is device_id present in comma separated list of ids */
1240 static bool force_probe(u16 device_id, const char *devices)
1241 {
1242         char *s, *p, *tok;
1243         bool ret;
1244
1245         if (!devices || !*devices)
1246                 return false;
1247
1248         /* match everything */
1249         if (strcmp(devices, "*") == 0)
1250                 return true;
1251
1252         s = kstrdup(devices, GFP_KERNEL);
1253         if (!s)
1254                 return false;
1255
1256         for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1257                 u16 val;
1258
1259                 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1260                         ret = true;
1261                         break;
1262                 }
1263         }
1264
1265         kfree(s);
1266
1267         return ret;
1268 }
1269
1270 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
1271 {
1272         if (!pci_resource_flags(pdev, bar))
1273                 return false;
1274
1275         if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
1276                 return false;
1277
1278         if (!pci_resource_len(pdev, bar))
1279                 return false;
1280
1281         return true;
1282 }
1283
1284 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
1285 {
1286         int gttmmaddr_bar = intel_info->__runtime.graphics.ip.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
1287
1288         return i915_pci_resource_valid(pdev, gttmmaddr_bar);
1289 }
1290
1291 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1292 {
1293         struct intel_device_info *intel_info =
1294                 (struct intel_device_info *) ent->driver_data;
1295         int err;
1296
1297         if (intel_info->require_force_probe &&
1298             !force_probe(pdev->device, i915_modparams.force_probe)) {
1299                 dev_info(&pdev->dev,
1300                          "Your graphics device %04x is not properly supported by the driver in this\n"
1301                          "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1302                          "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1303                          "or (recommended) check for kernel updates.\n",
1304                          pdev->device, pdev->device, pdev->device);
1305                 return -ENODEV;
1306         }
1307
1308         /* Only bind to function 0 of the device. Early generations
1309          * used function 1 as a placeholder for multi-head. This causes
1310          * us confusion instead, especially on the systems where both
1311          * functions have the same PCI-ID!
1312          */
1313         if (PCI_FUNC(pdev->devfn))
1314                 return -ENODEV;
1315
1316         if (!intel_mmio_bar_valid(pdev, intel_info))
1317                 return -ENXIO;
1318
1319         /* Detect if we need to wait for other drivers early on */
1320         if (intel_modeset_probe_defer(pdev))
1321                 return -EPROBE_DEFER;
1322
1323         err = i915_driver_probe(pdev, ent);
1324         if (err)
1325                 return err;
1326
1327         if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1328                 i915_pci_remove(pdev);
1329                 return -ENODEV;
1330         }
1331
1332         err = i915_live_selftests(pdev);
1333         if (err) {
1334                 i915_pci_remove(pdev);
1335                 return err > 0 ? -ENOTTY : err;
1336         }
1337
1338         err = i915_perf_selftests(pdev);
1339         if (err) {
1340                 i915_pci_remove(pdev);
1341                 return err > 0 ? -ENOTTY : err;
1342         }
1343
1344         return 0;
1345 }
1346
1347 static void i915_pci_shutdown(struct pci_dev *pdev)
1348 {
1349         struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1350
1351         i915_driver_shutdown(i915);
1352 }
1353
1354 static struct pci_driver i915_pci_driver = {
1355         .name = DRIVER_NAME,
1356         .id_table = pciidlist,
1357         .probe = i915_pci_probe,
1358         .remove = i915_pci_remove,
1359         .shutdown = i915_pci_shutdown,
1360         .driver.pm = &i915_pm_ops,
1361 };
1362
1363 int i915_pci_register_driver(void)
1364 {
1365         return pci_register_driver(&i915_pci_driver);
1366 }
1367
1368 void i915_pci_unregister_driver(void)
1369 {
1370         pci_unregister_driver(&i915_pci_driver);
1371 }