drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_g4x[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* IIR can theoretically queue up two events. Be paranoid. */
  84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
  85         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
  86         POSTING_READ(GEN8_##type##_IMR(which)); \
  87         I915_WRITE(GEN8_##type##_IER(which), 0); \
  88         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  89         POSTING_READ(GEN8_##type##_IIR(which)); \
  90         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  91         POSTING_READ(GEN8_##type##_IIR(which)); \
  92 } while (0)
  93
  94 #define GEN5_IRQ_RESET(type) do { \
  95         I915_WRITE(type##IMR, 0xffffffff); \
  96         POSTING_READ(type##IMR); \
  97         I915_WRITE(type##IER, 0); \
  98         I915_WRITE(type##IIR, 0xffffffff); \
  99         POSTING_READ(type##IIR); \
 100         I915_WRITE(type##IIR, 0xffffffff); \
 101         POSTING_READ(type##IIR); \
 102 } while (0)
 103
 104 /*
 105  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 106  */
 107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
 108         u32 val = I915_READ(reg); \
 109         if (val) { \
 110                 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
 111                      (reg), val); \
 112                 I915_WRITE((reg), 0xffffffff); \
 113                 POSTING_READ(reg); \
 114                 I915_WRITE((reg), 0xffffffff); \
 115                 POSTING_READ(reg); \
 116         } \
 117 } while (0)
 118
 119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 120         GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
 121         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 122         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 123         POSTING_READ(GEN8_##type##_IER(which)); \
 124 } while (0)
 125
 126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 127         GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
 128         I915_WRITE(type##IMR, (imr_val)); \
 129         I915_WRITE(type##IER, (ier_val)); \
 130         POSTING_READ(type##IER); \
 131 } while (0)
 132
 133 /* For display hotplug interrupt */
 134 static void
 135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 136 {
 137         assert_spin_locked(&dev_priv->irq_lock);
 138
 139         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 140                 return;
 141
 142         if ((dev_priv->irq_mask & mask) != 0) {
 143                 dev_priv->irq_mask &= ~mask;
 144                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 145                 POSTING_READ(DEIMR);
 146         }
 147 }
 148
 149 static void
 150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 151 {
 152         assert_spin_locked(&dev_priv->irq_lock);
 153
 154         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 155                 return;
 156
 157         if ((dev_priv->irq_mask & mask) != mask) {
 158                 dev_priv->irq_mask |= mask;
 159                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 160                 POSTING_READ(DEIMR);
 161         }
 162 }
 163
 164 /**
 165  * ilk_update_gt_irq - update GTIMR
 166  * @dev_priv: driver private
 167  * @interrupt_mask: mask of interrupt bits to update
 168  * @enabled_irq_mask: mask of interrupt bits to enable
 169  */
 170 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 171                               uint32_t interrupt_mask,
 172                               uint32_t enabled_irq_mask)
 173 {
 174         assert_spin_locked(&dev_priv->irq_lock);
 175
 176         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 177                 return;
 178
 179         dev_priv->gt_irq_mask &= ~interrupt_mask;
 180         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 181         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 182         POSTING_READ(GTIMR);
 183 }
 184
 185 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 186 {
 187         ilk_update_gt_irq(dev_priv, mask, mask);
 188 }
 189
 190 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 191 {
 192         ilk_update_gt_irq(dev_priv, mask, 0);
 193 }
 194
 195 /**
 196   * snb_update_pm_irq - update GEN6_PMIMR
 197   * @dev_priv: driver private
 198   * @interrupt_mask: mask of interrupt bits to update
 199   * @enabled_irq_mask: mask of interrupt bits to enable
 200   */
 201 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 202                               uint32_t interrupt_mask,
 203                               uint32_t enabled_irq_mask)
 204 {
 205         uint32_t new_val;
 206
 207         assert_spin_locked(&dev_priv->irq_lock);
 208
 209         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 210                 return;
 211
 212         new_val = dev_priv->pm_irq_mask;
 213         new_val &= ~interrupt_mask;
 214         new_val |= (~enabled_irq_mask & interrupt_mask);
 215
 216         if (new_val != dev_priv->pm_irq_mask) {
 217                 dev_priv->pm_irq_mask = new_val;
 218                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 219                 POSTING_READ(GEN6_PMIMR);
 220         }
 221 }
 222
 223 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 224 {
 225         snb_update_pm_irq(dev_priv, mask, mask);
 226 }
 227
 228 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 229 {
 230         snb_update_pm_irq(dev_priv, mask, 0);
 231 }
 232
 233 static bool ivb_can_enable_err_int(struct drm_device *dev)
 234 {
 235         struct drm_i915_private *dev_priv = dev->dev_private;
 236         struct intel_crtc *crtc;
 237         enum pipe pipe;
 238
 239         assert_spin_locked(&dev_priv->irq_lock);
 240
 241         for_each_pipe(pipe) {
 242                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 243
 244                 if (crtc->cpu_fifo_underrun_disabled)
 245                         return false;
 246         }
 247
 248         return true;
 249 }
 250
 251 /**
 252   * bdw_update_pm_irq - update GT interrupt 2
 253   * @dev_priv: driver private
 254   * @interrupt_mask: mask of interrupt bits to update
 255   * @enabled_irq_mask: mask of interrupt bits to enable
 256   *
 257   * Copied from the snb function, updated with relevant register offsets
 258   */
 259 static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
 260                               uint32_t interrupt_mask,
 261                               uint32_t enabled_irq_mask)
 262 {
 263         uint32_t new_val;
 264
 265         assert_spin_locked(&dev_priv->irq_lock);
 266
 267         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 268                 return;
 269
 270         new_val = dev_priv->pm_irq_mask;
 271         new_val &= ~interrupt_mask;
 272         new_val |= (~enabled_irq_mask & interrupt_mask);
 273
 274         if (new_val != dev_priv->pm_irq_mask) {
 275                 dev_priv->pm_irq_mask = new_val;
 276                 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
 277                 POSTING_READ(GEN8_GT_IMR(2));
 278         }
 279 }
 280
 281 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 282 {
 283         bdw_update_pm_irq(dev_priv, mask, mask);
 284 }
 285
 286 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 287 {
 288         bdw_update_pm_irq(dev_priv, mask, 0);
 289 }
 290
 291 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 292 {
 293         struct drm_i915_private *dev_priv = dev->dev_private;
 294         enum pipe pipe;
 295         struct intel_crtc *crtc;
 296
 297         assert_spin_locked(&dev_priv->irq_lock);
 298
 299         for_each_pipe(pipe) {
 300                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 301
 302                 if (crtc->pch_fifo_underrun_disabled)
 303                         return false;
 304         }
 305
 306         return true;
 307 }
 308
 309 void i9xx_check_fifo_underruns(struct drm_device *dev)
 310 {
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312         struct intel_crtc *crtc;
 313         unsigned long flags;
 314
 315         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 316
 317         for_each_intel_crtc(dev, crtc) {
 318                 u32 reg = PIPESTAT(crtc->pipe);
 319                 u32 pipestat;
 320
 321                 if (crtc->cpu_fifo_underrun_disabled)
 322                         continue;
 323
 324                 pipestat = I915_READ(reg) & 0xffff0000;
 325                 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
 326                         continue;
 327
 328                 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
 329                 POSTING_READ(reg);
 330
 331                 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
 332         }
 333
 334         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 335 }
 336
 337 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
 338                                              enum pipe pipe,
 339                                              bool enable, bool old)
 340 {
 341         struct drm_i915_private *dev_priv = dev->dev_private;
 342         u32 reg = PIPESTAT(pipe);
 343         u32 pipestat = I915_READ(reg) & 0xffff0000;
 344
 345         assert_spin_locked(&dev_priv->irq_lock);
 346
 347         if (enable) {
 348                 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
 349                 POSTING_READ(reg);
 350         } else {
 351                 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
 352                         DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
 353         }
 354 }
 355
 356 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 357                                                  enum pipe pipe, bool enable)
 358 {
 359         struct drm_i915_private *dev_priv = dev->dev_private;
 360         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 361                                           DE_PIPEB_FIFO_UNDERRUN;
 362
 363         if (enable)
 364                 ironlake_enable_display_irq(dev_priv, bit);
 365         else
 366                 ironlake_disable_display_irq(dev_priv, bit);
 367 }
 368
 369 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 370                                                   enum pipe pipe,
 371                                                   bool enable, bool old)
 372 {
 373         struct drm_i915_private *dev_priv = dev->dev_private;
 374         if (enable) {
 375                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 376
 377                 if (!ivb_can_enable_err_int(dev))
 378                         return;
 379
 380                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 381         } else {
 382                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 383
 384                 if (old &&
 385                     I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
 386                         DRM_ERROR("uncleared fifo underrun on pipe %c\n",
 387                                   pipe_name(pipe));
 388                 }
 389         }
 390 }
 391
 392 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 393                                                   enum pipe pipe, bool enable)
 394 {
 395         struct drm_i915_private *dev_priv = dev->dev_private;
 396
 397         assert_spin_locked(&dev_priv->irq_lock);
 398
 399         if (enable)
 400                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 401         else
 402                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 403         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 404         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 405 }
 406
 407 /**
 408  * ibx_display_interrupt_update - update SDEIMR
 409  * @dev_priv: driver private
 410  * @interrupt_mask: mask of interrupt bits to update
 411  * @enabled_irq_mask: mask of interrupt bits to enable
 412  */
 413 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 414                                          uint32_t interrupt_mask,
 415                                          uint32_t enabled_irq_mask)
 416 {
 417         uint32_t sdeimr = I915_READ(SDEIMR);
 418         sdeimr &= ~interrupt_mask;
 419         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 420
 421         assert_spin_locked(&dev_priv->irq_lock);
 422
 423         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 424                 return;
 425
 426         I915_WRITE(SDEIMR, sdeimr);
 427         POSTING_READ(SDEIMR);
 428 }
 429 #define ibx_enable_display_interrupt(dev_priv, bits) \
 430         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 431 #define ibx_disable_display_interrupt(dev_priv, bits) \
 432         ibx_display_interrupt_update((dev_priv), (bits), 0)
 433
 434 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 435                                             enum transcoder pch_transcoder,
 436                                             bool enable)
 437 {
 438         struct drm_i915_private *dev_priv = dev->dev_private;
 439         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 440                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 441
 442         if (enable)
 443                 ibx_enable_display_interrupt(dev_priv, bit);
 444         else
 445                 ibx_disable_display_interrupt(dev_priv, bit);
 446 }
 447
 448 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 449                                             enum transcoder pch_transcoder,
 450                                             bool enable, bool old)
 451 {
 452         struct drm_i915_private *dev_priv = dev->dev_private;
 453
 454         if (enable) {
 455                 I915_WRITE(SERR_INT,
 456                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 457
 458                 if (!cpt_can_enable_serr_int(dev))
 459                         return;
 460
 461                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 462         } else {
 463                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 464
 465                 if (old && I915_READ(SERR_INT) &
 466                     SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
 467                         DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
 468                                   transcoder_name(pch_transcoder));
 469                 }
 470         }
 471 }
 472
 473 /**
 474  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 475  * @dev: drm device
 476  * @pipe: pipe
 477  * @enable: true if we want to report FIFO underrun errors, false otherwise
 478  *
 479  * This function makes us disable or enable CPU fifo underruns for a specific
 480  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 481  * reporting for one pipe may also disable all the other CPU error interruts for
 482  * the other pipes, due to the fact that there's just one interrupt mask/enable
 483  * bit for all the pipes.
 484  *
 485  * Returns the previous state of underrun reporting.
 486  */
 487 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 488                                                     enum pipe pipe, bool enable)
 489 {
 490         struct drm_i915_private *dev_priv = dev->dev_private;
 491         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 493         bool old;
 494
 495         assert_spin_locked(&dev_priv->irq_lock);
 496
 497         old = !intel_crtc->cpu_fifo_underrun_disabled;
 498         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 499
 500         if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
 501                 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
 502         else if (IS_GEN5(dev) || IS_GEN6(dev))
 503                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 504         else if (IS_GEN7(dev))
 505                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
 506         else if (IS_GEN8(dev))
 507                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 508
 509         return old;
 510 }
 511
 512 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 513                                            enum pipe pipe, bool enable)
 514 {
 515         struct drm_i915_private *dev_priv = dev->dev_private;
 516         unsigned long flags;
 517         bool ret;
 518
 519         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 520         ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
 521         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 522
 523         return ret;
 524 }
 525
 526 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
 527                                                   enum pipe pipe)
 528 {
 529         struct drm_i915_private *dev_priv = dev->dev_private;
 530         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 531         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 532
 533         return !intel_crtc->cpu_fifo_underrun_disabled;
 534 }
 535
 536 /**
 537  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 538  * @dev: drm device
 539  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 540  * @enable: true if we want to report FIFO underrun errors, false otherwise
 541  *
 542  * This function makes us disable or enable PCH fifo underruns for a specific
 543  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 544  * underrun reporting for one transcoder may also disable all the other PCH
 545  * error interruts for the other transcoders, due to the fact that there's just
 546  * one interrupt mask/enable bit for all the transcoders.
 547  *
 548  * Returns the previous state of underrun reporting.
 549  */
 550 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 551                                            enum transcoder pch_transcoder,
 552                                            bool enable)
 553 {
 554         struct drm_i915_private *dev_priv = dev->dev_private;
 555         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 556         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 557         unsigned long flags;
 558         bool old;
 559
 560         /*
 561          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 562          * has only one pch transcoder A that all pipes can use. To avoid racy
 563          * pch transcoder -> pipe lookups from interrupt code simply store the
 564          * underrun statistics in crtc A. Since we never expose this anywhere
 565          * nor use it outside of the fifo underrun code here using the "wrong"
 566          * crtc on LPT won't cause issues.
 567          */
 568
 569         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 570
 571         old = !intel_crtc->pch_fifo_underrun_disabled;
 572         intel_crtc->pch_fifo_underrun_disabled = !enable;
 573
 574         if (HAS_PCH_IBX(dev))
 575                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 576         else
 577                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
 578
 579         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 580         return old;
 581 }
 582
 583
 584 static void
 585 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 586                        u32 enable_mask, u32 status_mask)
 587 {
 588         u32 reg = PIPESTAT(pipe);
 589         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 590
 591         assert_spin_locked(&dev_priv->irq_lock);
 592
 593         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 594                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 595                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 596                       pipe_name(pipe), enable_mask, status_mask))
 597                 return;
 598
 599         if ((pipestat & enable_mask) == enable_mask)
 600                 return;
 601
 602         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 603
 604         /* Enable the interrupt, clear any pending status */
 605         pipestat |= enable_mask | status_mask;
 606         I915_WRITE(reg, pipestat);
 607         POSTING_READ(reg);
 608 }
 609
 610 static void
 611 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 612                         u32 enable_mask, u32 status_mask)
 613 {
 614         u32 reg = PIPESTAT(pipe);
 615         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 616
 617         assert_spin_locked(&dev_priv->irq_lock);
 618
 619         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 620                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 621                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 622                       pipe_name(pipe), enable_mask, status_mask))
 623                 return;
 624
 625         if ((pipestat & enable_mask) == 0)
 626                 return;
 627
 628         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 629
 630         pipestat &= ~enable_mask;
 631         I915_WRITE(reg, pipestat);
 632         POSTING_READ(reg);
 633 }
 634
 635 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 636 {
 637         u32 enable_mask = status_mask << 16;
 638
 639         /*
 640          * On pipe A we don't support the PSR interrupt yet,
 641          * on pipe B and C the same bit MBZ.
 642          */
 643         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 644                 return 0;
 645         /*
 646          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 647          * A the same bit is for perf counters which we don't use either.
 648          */
 649         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 650                 return 0;
 651
 652         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 653                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 654                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 655         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 656                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 657         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 658                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 659
 660         return enable_mask;
 661 }
 662
 663 void
 664 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 665                      u32 status_mask)
 666 {
 667         u32 enable_mask;
 668
 669         if (IS_VALLEYVIEW(dev_priv->dev))
 670                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 671                                                            status_mask);
 672         else
 673                 enable_mask = status_mask << 16;
 674         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 675 }
 676
 677 void
 678 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 679                       u32 status_mask)
 680 {
 681         u32 enable_mask;
 682
 683         if (IS_VALLEYVIEW(dev_priv->dev))
 684                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 685                                                            status_mask);
 686         else
 687                 enable_mask = status_mask << 16;
 688         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 689 }
 690
 691 /**
 692  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 693  */
 694 static void i915_enable_asle_pipestat(struct drm_device *dev)
 695 {
 696         struct drm_i915_private *dev_priv = dev->dev_private;
 697         unsigned long irqflags;
 698
 699         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 700                 return;
 701
 702         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 703
 704         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 705         if (INTEL_INFO(dev)->gen >= 4)
 706                 i915_enable_pipestat(dev_priv, PIPE_A,
 707                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 708
 709         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 710 }
 711
 712 /**
 713  * i915_pipe_enabled - check if a pipe is enabled
 714  * @dev: DRM device
 715  * @pipe: pipe to check
 716  *
 717  * Reading certain registers when the pipe is disabled can hang the chip.
 718  * Use this routine to make sure the PLL is running and the pipe is active
 719  * before reading such registers if unsure.
 720  */
 721 static int
 722 i915_pipe_enabled(struct drm_device *dev, int pipe)
 723 {
 724         struct drm_i915_private *dev_priv = dev->dev_private;
 725
 726         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 727                 /* Locking is horribly broken here, but whatever. */
 728                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 729                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 730
 731                 return intel_crtc->active;
 732         } else {
 733                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 734         }
 735 }
 736
 737 /*
 738  * This timing diagram depicts the video signal in and
 739  * around the vertical blanking period.
 740  *
 741  * Assumptions about the fictitious mode used in this example:
 742  *  vblank_start >= 3
 743  *  vsync_start = vblank_start + 1
 744  *  vsync_end = vblank_start + 2
 745  *  vtotal = vblank_start + 3
 746  *
 747  *           start of vblank:
 748  *           latch double buffered registers
 749  *           increment frame counter (ctg+)
 750  *           generate start of vblank interrupt (gen4+)
 751  *           |
 752  *           |          frame start:
 753  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 754  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 755  *           |          |
 756  *           |          |  start of vsync:
 757  *           |          |  generate vsync interrupt
 758  *           |          |  |
 759  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 760  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 761  * ----va---> <-----------------vb--------------------> <--------va-------------
 762  *       |          |       <----vs----->                     |
 763  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 764  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 765  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 766  *       |          |                                         |
 767  *       last visible pixel                                   first visible pixel
 768  *                  |                                         increment frame counter (gen3/4)
 769  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 770  *
 771  * x  = horizontal active
 772  * _  = horizontal blanking
 773  * hs = horizontal sync
 774  * va = vertical active
 775  * vb = vertical blanking
 776  * vs = vertical sync
 777  * vbs = vblank_start (number)
 778  *
 779  * Summary:
 780  * - most events happen at the start of horizontal sync
 781  * - frame start happens at the start of horizontal blank, 1-4 lines
 782  *   (depending on PIPECONF settings) after the start of vblank
 783  * - gen3/4 pixel and frame counter are synchronized with the start
 784  *   of horizontal active on the first line of vertical active
 785  */
 786
 787 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 788 {
 789         /* Gen2 doesn't have a hardware frame counter */
 790         return 0;
 791 }
 792
 793 /* Called from drm generic code, passed a 'crtc', which
 794  * we use as a pipe index
 795  */
 796 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 797 {
 798         struct drm_i915_private *dev_priv = dev->dev_private;
 799         unsigned long high_frame;
 800         unsigned long low_frame;
 801         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 802
 803         if (!i915_pipe_enabled(dev, pipe)) {
 804                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 805                                 "pipe %c\n", pipe_name(pipe));
 806                 return 0;
 807         }
 808
 809         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 810                 struct intel_crtc *intel_crtc =
 811                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 812                 const struct drm_display_mode *mode =
 813                         &intel_crtc->config.adjusted_mode;
 814
 815                 htotal = mode->crtc_htotal;
 816                 hsync_start = mode->crtc_hsync_start;
 817                 vbl_start = mode->crtc_vblank_start;
 818                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 819                         vbl_start = DIV_ROUND_UP(vbl_start, 2);
 820         } else {
 821                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
 822
 823                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 824                 hsync_start = (I915_READ(HSYNC(cpu_transcoder))  & 0x1fff) + 1;
 825                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 826                 if ((I915_READ(PIPECONF(cpu_transcoder)) &
 827                      PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
 828                         vbl_start = DIV_ROUND_UP(vbl_start, 2);
 829         }
 830
 831         /* Convert to pixel count */
 832         vbl_start *= htotal;
 833
 834         /* Start of vblank event occurs at start of hsync */
 835         vbl_start -= htotal - hsync_start;
 836
 837         high_frame = PIPEFRAME(pipe);
 838         low_frame = PIPEFRAMEPIXEL(pipe);
 839
 840         /*
 841          * High & low register fields aren't synchronized, so make sure
 842          * we get a low value that's stable across two reads of the high
 843          * register.
 844          */
 845         do {
 846                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 847                 low   = I915_READ(low_frame);
 848                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 849         } while (high1 != high2);
 850
 851         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 852         pixel = low & PIPE_PIXEL_MASK;
 853         low >>= PIPE_FRAME_LOW_SHIFT;
 854
 855         /*
 856          * The frame counter increments at beginning of active.
 857          * Cook up a vblank counter by also checking the pixel
 858          * counter against vblank start.
 859          */
 860         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 861 }
 862
 863 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         int reg = PIPE_FRMCOUNT_GM45(pipe);
 867
 868         if (!i915_pipe_enabled(dev, pipe)) {
 869                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 870                                  "pipe %c\n", pipe_name(pipe));
 871                 return 0;
 872         }
 873
 874         return I915_READ(reg);
 875 }
 876
 877 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 878 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 879
 880 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 881 {
 882         struct drm_device *dev = crtc->base.dev;
 883         struct drm_i915_private *dev_priv = dev->dev_private;
 884         const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
 885         enum pipe pipe = crtc->pipe;
 886         int position, vtotal;
 887
 888         vtotal = mode->crtc_vtotal;
 889         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 890                 vtotal /= 2;
 891
 892         if (IS_GEN2(dev))
 893                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 894         else
 895                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 896
 897         /*
 898          * See update_scanline_offset() for the details on the
 899          * scanline_offset adjustment.
 900          */
 901         return (position + crtc->scanline_offset) % vtotal;
 902 }
 903
 904 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 905                                     unsigned int flags, int *vpos, int *hpos,
 906                                     ktime_t *stime, ktime_t *etime)
 907 {
 908         struct drm_i915_private *dev_priv = dev->dev_private;
 909         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 911         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 912         int position;
 913         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 914         bool in_vbl = true;
 915         int ret = 0;
 916         unsigned long irqflags;
 917
 918         if (!intel_crtc->active) {
 919                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 920                                  "pipe %c\n", pipe_name(pipe));
 921                 return 0;
 922         }
 923
 924         htotal = mode->crtc_htotal;
 925         hsync_start = mode->crtc_hsync_start;
 926         vtotal = mode->crtc_vtotal;
 927         vbl_start = mode->crtc_vblank_start;
 928         vbl_end = mode->crtc_vblank_end;
 929
 930         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 931                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 932                 vbl_end /= 2;
 933                 vtotal /= 2;
 934         }
 935
 936         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 937
 938         /*
 939          * Lock uncore.lock, as we will do multiple timing critical raw
 940          * register reads, potentially with preemption disabled, so the
 941          * following code must not block on uncore.lock.
 942          */
 943         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 944
 945         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 946
 947         /* Get optional system timestamp before query. */
 948         if (stime)
 949                 *stime = ktime_get();
 950
 951         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 952                 /* No obvious pixelcount register. Only query vertical
 953                  * scanout position from Display scan line register.
 954                  */
 955                 position = __intel_get_crtc_scanline(intel_crtc);
 956         } else {
 957                 /* Have access to pixelcount since start of frame.
 958                  * We can split this into vertical and horizontal
 959                  * scanout position.
 960                  */
 961                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 962
 963                 /* convert to pixel counts */
 964                 vbl_start *= htotal;
 965                 vbl_end *= htotal;
 966                 vtotal *= htotal;
 967
 968                 /*
 969                  * In interlaced modes, the pixel counter counts all pixels,
 970                  * so one field will have htotal more pixels. In order to avoid
 971                  * the reported position from jumping backwards when the pixel
 972                  * counter is beyond the length of the shorter field, just
 973                  * clamp the position the length of the shorter field. This
 974                  * matches how the scanline counter based position works since
 975                  * the scanline counter doesn't count the two half lines.
 976                  */
 977                 if (position >= vtotal)
 978                         position = vtotal - 1;
 979
 980                 /*
 981                  * Start of vblank interrupt is triggered at start of hsync,
 982                  * just prior to the first active line of vblank. However we
 983                  * consider lines to start at the leading edge of horizontal
 984                  * active. So, should we get here before we've crossed into
 985                  * the horizontal active of the first line in vblank, we would
 986                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 987                  * always add htotal-hsync_start to the current pixel position.
 988                  */
 989                 position = (position + htotal - hsync_start) % vtotal;
 990         }
 991
 992         /* Get optional system timestamp after query. */
 993         if (etime)
 994                 *etime = ktime_get();
 995
 996         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 997
 998         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 999
1000         in_vbl = position >= vbl_start && position < vbl_end;
1001
1002         /*
1003          * While in vblank, position will be negative
1004          * counting up towards 0 at vbl_end. And outside
1005          * vblank, position will be positive counting
1006          * up since vbl_end.
1007          */
1008         if (position >= vbl_start)
1009                 position -= vbl_end;
1010         else
1011                 position += vtotal - vbl_end;
1012
1013         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
1014                 *vpos = position;
1015                 *hpos = 0;
1016         } else {
1017                 *vpos = position / htotal;
1018                 *hpos = position - (*vpos * htotal);
1019         }
1020
1021         /* In vblank? */
1022         if (in_vbl)
1023                 ret |= DRM_SCANOUTPOS_INVBL;
1024
1025         return ret;
1026 }
1027
1028 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1029 {
1030         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1031         unsigned long irqflags;
1032         int position;
1033
1034         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1035         position = __intel_get_crtc_scanline(crtc);
1036         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1037
1038         return position;
1039 }
1040
1041 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
1042                               int *max_error,
1043                               struct timeval *vblank_time,
1044                               unsigned flags)
1045 {
1046         struct drm_crtc *crtc;
1047
1048         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
1049                 DRM_ERROR("Invalid crtc %d\n", pipe);
1050                 return -EINVAL;
1051         }
1052
1053         /* Get drm_crtc to timestamp: */
1054         crtc = intel_get_crtc_for_pipe(dev, pipe);
1055         if (crtc == NULL) {
1056                 DRM_ERROR("Invalid crtc %d\n", pipe);
1057                 return -EINVAL;
1058         }
1059
1060         if (!crtc->enabled) {
1061                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1062                 return -EBUSY;
1063         }
1064
1065         /* Helper routine in DRM core does all the work: */
1066         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
1067                                                      vblank_time, flags,
1068                                                      crtc,
1069                                                      &to_intel_crtc(crtc)->config.adjusted_mode);
1070 }
1071
1072 static bool intel_hpd_irq_event(struct drm_device *dev,
1073                                 struct drm_connector *connector)
1074 {
1075         enum drm_connector_status old_status;
1076
1077         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1078         old_status = connector->status;
1079
1080         connector->status = connector->funcs->detect(connector, false);
1081         if (old_status == connector->status)
1082                 return false;
1083
1084         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
1085                       connector->base.id,
1086                       connector->name,
1087                       drm_get_connector_status_name(old_status),
1088                       drm_get_connector_status_name(connector->status));
1089
1090         return true;
1091 }
1092
1093 static void i915_digport_work_func(struct work_struct *work)
1094 {
1095         struct drm_i915_private *dev_priv =
1096                 container_of(work, struct drm_i915_private, dig_port_work);
1097         unsigned long irqflags;
1098         u32 long_port_mask, short_port_mask;
1099         struct intel_digital_port *intel_dig_port;
1100         int i, ret;
1101         u32 old_bits = 0;
1102
1103         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1104         long_port_mask = dev_priv->long_hpd_port_mask;
1105         dev_priv->long_hpd_port_mask = 0;
1106         short_port_mask = dev_priv->short_hpd_port_mask;
1107         dev_priv->short_hpd_port_mask = 0;
1108         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1109
1110         for (i = 0; i < I915_MAX_PORTS; i++) {
1111                 bool valid = false;
1112                 bool long_hpd = false;
1113                 intel_dig_port = dev_priv->hpd_irq_port[i];
1114                 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
1115                         continue;
1116
1117                 if (long_port_mask & (1 << i))  {
1118                         valid = true;
1119                         long_hpd = true;
1120                 } else if (short_port_mask & (1 << i))
1121                         valid = true;
1122
1123                 if (valid) {
1124                         ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
1125                         if (ret == true) {
1126                                 /* if we get true fallback to old school hpd */
1127                                 old_bits |= (1 << intel_dig_port->base.hpd_pin);
1128                         }
1129                 }
1130         }
1131
1132         if (old_bits) {
1133                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1134                 dev_priv->hpd_event_bits |= old_bits;
1135                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1136                 schedule_work(&dev_priv->hotplug_work);
1137         }
1138 }
1139
1140 /*
1141  * Handle hotplug events outside the interrupt handler proper.
1142  */
1143 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1144
1145 static void i915_hotplug_work_func(struct work_struct *work)
1146 {
1147         struct drm_i915_private *dev_priv =
1148                 container_of(work, struct drm_i915_private, hotplug_work);
1149         struct drm_device *dev = dev_priv->dev;
1150         struct drm_mode_config *mode_config = &dev->mode_config;
1151         struct intel_connector *intel_connector;
1152         struct intel_encoder *intel_encoder;
1153         struct drm_connector *connector;
1154         unsigned long irqflags;
1155         bool hpd_disabled = false;
1156         bool changed = false;
1157         u32 hpd_event_bits;
1158
1159         mutex_lock(&mode_config->mutex);
1160         DRM_DEBUG_KMS("running encoder hotplug functions\n");
1161
1162         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1163
1164         hpd_event_bits = dev_priv->hpd_event_bits;
1165         dev_priv->hpd_event_bits = 0;
1166         list_for_each_entry(connector, &mode_config->connector_list, head) {
1167                 intel_connector = to_intel_connector(connector);
1168                 if (!intel_connector->encoder)
1169                         continue;
1170                 intel_encoder = intel_connector->encoder;
1171                 if (intel_encoder->hpd_pin > HPD_NONE &&
1172                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1173                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
1174                         DRM_INFO("HPD interrupt storm detected on connector %s: "
1175                                  "switching from hotplug detection to polling\n",
1176                                 connector->name);
1177                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1178                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
1179                                 | DRM_CONNECTOR_POLL_DISCONNECT;
1180                         hpd_disabled = true;
1181                 }
1182                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1183                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1184                                       connector->name, intel_encoder->hpd_pin);
1185                 }
1186         }
1187          /* if there were no outputs to poll, poll was disabled,
1188           * therefore make sure it's enabled when disabling HPD on
1189           * some connectors */
1190         if (hpd_disabled) {
1191                 drm_kms_helper_poll_enable(dev);
1192                 mod_timer(&dev_priv->hotplug_reenable_timer,
1193                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1194         }
1195
1196         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1197
1198         list_for_each_entry(connector, &mode_config->connector_list, head) {
1199                 intel_connector = to_intel_connector(connector);
1200                 if (!intel_connector->encoder)
1201                         continue;
1202                 intel_encoder = intel_connector->encoder;
1203                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1204                         if (intel_encoder->hot_plug)
1205                                 intel_encoder->hot_plug(intel_encoder);
1206                         if (intel_hpd_irq_event(dev, connector))
1207                                 changed = true;
1208                 }
1209         }
1210         mutex_unlock(&mode_config->mutex);
1211
1212         if (changed)
1213                 drm_kms_helper_hotplug_event(dev);
1214 }
1215
1216 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1217 {
1218         del_timer_sync(&dev_priv->hotplug_reenable_timer);
1219 }
1220
1221 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1222 {
1223         struct drm_i915_private *dev_priv = dev->dev_private;
1224         u32 busy_up, busy_down, max_avg, min_avg;
1225         u8 new_delay;
1226
1227         spin_lock(&mchdev_lock);
1228
1229         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1230
1231         new_delay = dev_priv->ips.cur_delay;
1232
1233         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1234         busy_up = I915_READ(RCPREVBSYTUPAVG);
1235         busy_down = I915_READ(RCPREVBSYTDNAVG);
1236         max_avg = I915_READ(RCBMAXAVG);
1237         min_avg = I915_READ(RCBMINAVG);
1238
1239         /* Handle RCS change request from hw */
1240         if (busy_up > max_avg) {
1241                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1242                         new_delay = dev_priv->ips.cur_delay - 1;
1243                 if (new_delay < dev_priv->ips.max_delay)
1244                         new_delay = dev_priv->ips.max_delay;
1245         } else if (busy_down < min_avg) {
1246                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1247                         new_delay = dev_priv->ips.cur_delay + 1;
1248                 if (new_delay > dev_priv->ips.min_delay)
1249                         new_delay = dev_priv->ips.min_delay;
1250         }
1251
1252         if (ironlake_set_drps(dev, new_delay))
1253                 dev_priv->ips.cur_delay = new_delay;
1254
1255         spin_unlock(&mchdev_lock);
1256
1257         return;
1258 }
1259
1260 static void notify_ring(struct drm_device *dev,
1261                         struct intel_engine_cs *ring)
1262 {
1263         if (!intel_ring_initialized(ring))
1264                 return;
1265
1266         trace_i915_gem_request_complete(ring);
1267
1268         if (drm_core_check_feature(dev, DRIVER_MODESET))
1269                 intel_notify_mmio_flip(ring);
1270
1271         wake_up_all(&ring->irq_queue);
1272         i915_queue_hangcheck(dev);
1273 }
1274
1275 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
1276                             struct intel_rps_ei *rps_ei)
1277 {
1278         u32 cz_ts, cz_freq_khz;
1279         u32 render_count, media_count;
1280         u32 elapsed_render, elapsed_media, elapsed_time;
1281         u32 residency = 0;
1282
1283         cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1284         cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1285
1286         render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1287         media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1288
1289         if (rps_ei->cz_clock == 0) {
1290                 rps_ei->cz_clock = cz_ts;
1291                 rps_ei->render_c0 = render_count;
1292                 rps_ei->media_c0 = media_count;
1293
1294                 return dev_priv->rps.cur_freq;
1295         }
1296
1297         elapsed_time = cz_ts - rps_ei->cz_clock;
1298         rps_ei->cz_clock = cz_ts;
1299
1300         elapsed_render = render_count - rps_ei->render_c0;
1301         rps_ei->render_c0 = render_count;
1302
1303         elapsed_media = media_count - rps_ei->media_c0;
1304         rps_ei->media_c0 = media_count;
1305
1306         /* Convert all the counters into common unit of milli sec */
1307         elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1308         elapsed_render /=  cz_freq_khz;
1309         elapsed_media /= cz_freq_khz;
1310
1311         /*
1312          * Calculate overall C0 residency percentage
1313          * only if elapsed time is non zero
1314          */
1315         if (elapsed_time) {
1316                 residency =
1317                         ((max(elapsed_render, elapsed_media) * 100)
1318                                 / elapsed_time);
1319         }
1320
1321         return residency;
1322 }
1323
1324 /**
1325  * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1326  * busy-ness calculated from C0 counters of render & media power wells
1327  * @dev_priv: DRM device private
1328  *
1329  */
1330 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1331 {
1332         u32 residency_C0_up = 0, residency_C0_down = 0;
1333         int new_delay, adj;
1334
1335         dev_priv->rps.ei_interrupt_count++;
1336
1337         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1338
1339
1340         if (dev_priv->rps.up_ei.cz_clock == 0) {
1341                 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1342                 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1343                 return dev_priv->rps.cur_freq;
1344         }
1345
1346
1347         /*
1348          * To down throttle, C0 residency should be less than down threshold
1349          * for continous EI intervals. So calculate down EI counters
1350          * once in VLV_INT_COUNT_FOR_DOWN_EI
1351          */
1352         if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1353
1354                 dev_priv->rps.ei_interrupt_count = 0;
1355
1356                 residency_C0_down = vlv_c0_residency(dev_priv,
1357                                                      &dev_priv->rps.down_ei);
1358         } else {
1359                 residency_C0_up = vlv_c0_residency(dev_priv,
1360                                                    &dev_priv->rps.up_ei);
1361         }
1362
1363         new_delay = dev_priv->rps.cur_freq;
1364
1365         adj = dev_priv->rps.last_adj;
1366         /* C0 residency is greater than UP threshold. Increase Frequency */
1367         if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1368                 if (adj > 0)
1369                         adj *= 2;
1370                 else
1371                         adj = 1;
1372
1373                 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1374                         new_delay = dev_priv->rps.cur_freq + adj;
1375
1376                 /*
1377                  * For better performance, jump directly
1378                  * to RPe if we're below it.
1379                  */
1380                 if (new_delay < dev_priv->rps.efficient_freq)
1381                         new_delay = dev_priv->rps.efficient_freq;
1382
1383         } else if (!dev_priv->rps.ei_interrupt_count &&
1384                         (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1385                 if (adj < 0)
1386                         adj *= 2;
1387                 else
1388                         adj = -1;
1389                 /*
1390                  * This means, C0 residency is less than down threshold over
1391                  * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1392                  */
1393                 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1394                         new_delay = dev_priv->rps.cur_freq + adj;
1395         }
1396
1397         return new_delay;
1398 }
1399
1400 static void gen6_pm_rps_work(struct work_struct *work)
1401 {
1402         struct drm_i915_private *dev_priv =
1403                 container_of(work, struct drm_i915_private, rps.work);
1404         u32 pm_iir;
1405         int new_delay, adj;
1406
1407         spin_lock_irq(&dev_priv->irq_lock);
1408         pm_iir = dev_priv->rps.pm_iir;
1409         dev_priv->rps.pm_iir = 0;
1410         if (INTEL_INFO(dev_priv->dev)->gen >= 8)
1411                 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1412         else {
1413                 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1414                 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1415         }
1416         spin_unlock_irq(&dev_priv->irq_lock);
1417
1418         /* Make sure we didn't queue anything we're not going to process. */
1419         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1420
1421         if ((pm_iir & dev_priv->pm_rps_events) == 0)
1422                 return;
1423
1424         mutex_lock(&dev_priv->rps.hw_lock);
1425
1426         adj = dev_priv->rps.last_adj;
1427         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1428                 if (adj > 0)
1429                         adj *= 2;
1430                 else {
1431                         /* CHV needs even encode values */
1432                         adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1433                 }
1434                 new_delay = dev_priv->rps.cur_freq + adj;
1435
1436                 /*
1437                  * For better performance, jump directly
1438                  * to RPe if we're below it.
1439                  */
1440                 if (new_delay < dev_priv->rps.efficient_freq)
1441                         new_delay = dev_priv->rps.efficient_freq;
1442         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1443                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1444                         new_delay = dev_priv->rps.efficient_freq;
1445                 else
1446                         new_delay = dev_priv->rps.min_freq_softlimit;
1447                 adj = 0;
1448         } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1449                 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1450         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1451                 if (adj < 0)
1452                         adj *= 2;
1453                 else {
1454                         /* CHV needs even encode values */
1455                         adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1456                 }
1457                 new_delay = dev_priv->rps.cur_freq + adj;
1458         } else { /* unknown event */
1459                 new_delay = dev_priv->rps.cur_freq;
1460         }
1461
1462         /* sysfs frequency interfaces may have snuck in while servicing the
1463          * interrupt
1464          */
1465         new_delay = clamp_t(int, new_delay,
1466                             dev_priv->rps.min_freq_softlimit,
1467                             dev_priv->rps.max_freq_softlimit);
1468
1469         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1470
1471         if (IS_VALLEYVIEW(dev_priv->dev))
1472                 valleyview_set_rps(dev_priv->dev, new_delay);
1473         else
1474                 gen6_set_rps(dev_priv->dev, new_delay);
1475
1476         mutex_unlock(&dev_priv->rps.hw_lock);
1477 }
1478
1479
1480 /**
1481  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1482  * occurred.
1483  * @work: workqueue struct
1484  *
1485  * Doesn't actually do anything except notify userspace. As a consequence of
1486  * this event, userspace should try to remap the bad rows since statistically
1487  * it is likely the same row is more likely to go bad again.
1488  */
1489 static void ivybridge_parity_work(struct work_struct *work)
1490 {
1491         struct drm_i915_private *dev_priv =
1492                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1493         u32 error_status, row, bank, subbank;
1494         char *parity_event[6];
1495         uint32_t misccpctl;
1496         unsigned long flags;
1497         uint8_t slice = 0;
1498
1499         /* We must turn off DOP level clock gating to access the L3 registers.
1500          * In order to prevent a get/put style interface, acquire struct mutex
1501          * any time we access those registers.
1502          */
1503         mutex_lock(&dev_priv->dev->struct_mutex);
1504
1505         /* If we've screwed up tracking, just let the interrupt fire again */
1506         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1507                 goto out;
1508
1509         misccpctl = I915_READ(GEN7_MISCCPCTL);
1510         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1511         POSTING_READ(GEN7_MISCCPCTL);
1512
1513         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1514                 u32 reg;
1515
1516                 slice--;
1517                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1518                         break;
1519
1520                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1521
1522                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1523
1524                 error_status = I915_READ(reg);
1525                 row = GEN7_PARITY_ERROR_ROW(error_status);
1526                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1527                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1528
1529                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1530                 POSTING_READ(reg);
1531
1532                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1533                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1534                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1535                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1536                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1537                 parity_event[5] = NULL;
1538
1539                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1540                                    KOBJ_CHANGE, parity_event);
1541
1542                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1543                           slice, row, bank, subbank);
1544
1545                 kfree(parity_event[4]);
1546                 kfree(parity_event[3]);
1547                 kfree(parity_event[2]);
1548                 kfree(parity_event[1]);
1549         }
1550
1551         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1552
1553 out:
1554         WARN_ON(dev_priv->l3_parity.which_slice);
1555         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1556         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1557         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1558
1559         mutex_unlock(&dev_priv->dev->struct_mutex);
1560 }
1561
1562 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1563 {
1564         struct drm_i915_private *dev_priv = dev->dev_private;
1565
1566         if (!HAS_L3_DPF(dev))
1567                 return;
1568
1569         spin_lock(&dev_priv->irq_lock);
1570         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1571         spin_unlock(&dev_priv->irq_lock);
1572
1573         iir &= GT_PARITY_ERROR(dev);
1574         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1575                 dev_priv->l3_parity.which_slice |= 1 << 1;
1576
1577         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1578                 dev_priv->l3_parity.which_slice |= 1 << 0;
1579
1580         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1581 }
1582
1583 static void ilk_gt_irq_handler(struct drm_device *dev,
1584                                struct drm_i915_private *dev_priv,
1585                                u32 gt_iir)
1586 {
1587         if (gt_iir &
1588             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1589                 notify_ring(dev, &dev_priv->ring[RCS]);
1590         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1591                 notify_ring(dev, &dev_priv->ring[VCS]);
1592 }
1593
1594 static void snb_gt_irq_handler(struct drm_device *dev,
1595                                struct drm_i915_private *dev_priv,
1596                                u32 gt_iir)
1597 {
1598
1599         if (gt_iir &
1600             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1601                 notify_ring(dev, &dev_priv->ring[RCS]);
1602         if (gt_iir & GT_BSD_USER_INTERRUPT)
1603                 notify_ring(dev, &dev_priv->ring[VCS]);
1604         if (gt_iir & GT_BLT_USER_INTERRUPT)
1605                 notify_ring(dev, &dev_priv->ring[BCS]);
1606
1607         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1608                       GT_BSD_CS_ERROR_INTERRUPT |
1609                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1610                 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1611                                   gt_iir);
1612         }
1613
1614         if (gt_iir & GT_PARITY_ERROR(dev))
1615                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1616 }
1617
1618 static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1619 {
1620         if ((pm_iir & dev_priv->pm_rps_events) == 0)
1621                 return;
1622
1623         spin_lock(&dev_priv->irq_lock);
1624         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1625         gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1626         spin_unlock(&dev_priv->irq_lock);
1627
1628         queue_work(dev_priv->wq, &dev_priv->rps.work);
1629 }
1630
1631 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1632                                        struct drm_i915_private *dev_priv,
1633                                        u32 master_ctl)
1634 {
1635         u32 rcs, bcs, vcs;
1636         uint32_t tmp = 0;
1637         irqreturn_t ret = IRQ_NONE;
1638
1639         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1640                 tmp = I915_READ(GEN8_GT_IIR(0));
1641                 if (tmp) {
1642                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1643                         ret = IRQ_HANDLED;
1644                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1645                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1646                         if (rcs & GT_RENDER_USER_INTERRUPT)
1647                                 notify_ring(dev, &dev_priv->ring[RCS]);
1648                         if (bcs & GT_RENDER_USER_INTERRUPT)
1649                                 notify_ring(dev, &dev_priv->ring[BCS]);
1650                         if ((rcs | bcs) & GT_CONTEXT_SWITCH_INTERRUPT)
1651                                 DRM_DEBUG_DRIVER("TODO: Context switch\n");
1652                 } else
1653                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1654         }
1655
1656         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1657                 tmp = I915_READ(GEN8_GT_IIR(1));
1658                 if (tmp) {
1659                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1660                         ret = IRQ_HANDLED;
1661                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1662                         if (vcs & GT_RENDER_USER_INTERRUPT)
1663                                 notify_ring(dev, &dev_priv->ring[VCS]);
1664                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1665                                 DRM_DEBUG_DRIVER("TODO: Context switch\n");
1666                         vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1667                         if (vcs & GT_RENDER_USER_INTERRUPT)
1668                                 notify_ring(dev, &dev_priv->ring[VCS2]);
1669                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1670                                 DRM_DEBUG_DRIVER("TODO: Context switch\n");
1671                 } else
1672                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1673         }
1674
1675         if (master_ctl & GEN8_GT_PM_IRQ) {
1676                 tmp = I915_READ(GEN8_GT_IIR(2));
1677                 if (tmp & dev_priv->pm_rps_events) {
1678                         I915_WRITE(GEN8_GT_IIR(2),
1679                                    tmp & dev_priv->pm_rps_events);
1680                         ret = IRQ_HANDLED;
1681                         gen8_rps_irq_handler(dev_priv, tmp);
1682                 } else
1683                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1684         }
1685
1686         if (master_ctl & GEN8_GT_VECS_IRQ) {
1687                 tmp = I915_READ(GEN8_GT_IIR(3));
1688                 if (tmp) {
1689                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1690                         ret = IRQ_HANDLED;
1691                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1692                         if (vcs & GT_RENDER_USER_INTERRUPT)
1693                                 notify_ring(dev, &dev_priv->ring[VECS]);
1694                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1695                                 DRM_DEBUG_DRIVER("TODO: Context switch\n");
1696                 } else
1697                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1698         }
1699
1700         return ret;
1701 }
1702
1703 #define HPD_STORM_DETECT_PERIOD 1000
1704 #define HPD_STORM_THRESHOLD 5
1705
1706 static int ilk_port_to_hotplug_shift(enum port port)
1707 {
1708         switch (port) {
1709         case PORT_A:
1710         case PORT_E:
1711         default:
1712                 return -1;
1713         case PORT_B:
1714                 return 0;
1715         case PORT_C:
1716                 return 8;
1717         case PORT_D:
1718                 return 16;
1719         }
1720 }
1721
1722 static int g4x_port_to_hotplug_shift(enum port port)
1723 {
1724         switch (port) {
1725         case PORT_A:
1726         case PORT_E:
1727         default:
1728                 return -1;
1729         case PORT_B:
1730                 return 17;
1731         case PORT_C:
1732                 return 19;
1733         case PORT_D:
1734                 return 21;
1735         }
1736 }
1737
1738 static inline enum port get_port_from_pin(enum hpd_pin pin)
1739 {
1740         switch (pin) {
1741         case HPD_PORT_B:
1742                 return PORT_B;
1743         case HPD_PORT_C:
1744                 return PORT_C;
1745         case HPD_PORT_D:
1746                 return PORT_D;
1747         default:
1748                 return PORT_A; /* no hpd */
1749         }
1750 }
1751
1752 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1753                                          u32 hotplug_trigger,
1754                                          u32 dig_hotplug_reg,
1755                                          const u32 *hpd)
1756 {
1757         struct drm_i915_private *dev_priv = dev->dev_private;
1758         int i;
1759         enum port port;
1760         bool storm_detected = false;
1761         bool queue_dig = false, queue_hp = false;
1762         u32 dig_shift;
1763         u32 dig_port_mask = 0;
1764
1765         if (!hotplug_trigger)
1766                 return;
1767
1768         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1769                          hotplug_trigger, dig_hotplug_reg);
1770
1771         spin_lock(&dev_priv->irq_lock);
1772         for (i = 1; i < HPD_NUM_PINS; i++) {
1773                 if (!(hpd[i] & hotplug_trigger))
1774                         continue;
1775
1776                 port = get_port_from_pin(i);
1777                 if (port && dev_priv->hpd_irq_port[port]) {
1778                         bool long_hpd;
1779
1780                         if (IS_G4X(dev)) {
1781                                 dig_shift = g4x_port_to_hotplug_shift(port);
1782                                 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1783                         } else {
1784                                 dig_shift = ilk_port_to_hotplug_shift(port);
1785                                 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1786                         }
1787
1788                         DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1789                                          port_name(port),
1790                                          long_hpd ? "long" : "short");
1791                         /* for long HPD pulses we want to have the digital queue happen,
1792                            but we still want HPD storm detection to function. */
1793                         if (long_hpd) {
1794                                 dev_priv->long_hpd_port_mask |= (1 << port);
1795                                 dig_port_mask |= hpd[i];
1796                         } else {
1797                                 /* for short HPD just trigger the digital queue */
1798                                 dev_priv->short_hpd_port_mask |= (1 << port);
1799                                 hotplug_trigger &= ~hpd[i];
1800                         }
1801                         queue_dig = true;
1802                 }
1803         }
1804
1805         for (i = 1; i < HPD_NUM_PINS; i++) {
1806                 if (hpd[i] & hotplug_trigger &&
1807                     dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1808                         /*
1809                          * On GMCH platforms the interrupt mask bits only
1810                          * prevent irq generation, not the setting of the
1811                          * hotplug bits itself. So only WARN about unexpected
1812                          * interrupts on saner platforms.
1813                          */
1814                         WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1815                                   "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1816                                   hotplug_trigger, i, hpd[i]);
1817
1818                         continue;
1819                 }
1820
1821                 if (!(hpd[i] & hotplug_trigger) ||
1822                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1823                         continue;
1824
1825                 if (!(dig_port_mask & hpd[i])) {
1826                         dev_priv->hpd_event_bits |= (1 << i);
1827                         queue_hp = true;
1828                 }
1829
1830                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1831                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1832                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1833                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1834                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1835                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1836                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1837                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1838                         dev_priv->hpd_event_bits &= ~(1 << i);
1839                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1840                         storm_detected = true;
1841                 } else {
1842                         dev_priv->hpd_stats[i].hpd_cnt++;
1843                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1844                                       dev_priv->hpd_stats[i].hpd_cnt);
1845                 }
1846         }
1847
1848         if (storm_detected)
1849                 dev_priv->display.hpd_irq_setup(dev);
1850         spin_unlock(&dev_priv->irq_lock);
1851
1852         /*
1853          * Our hotplug handler can grab modeset locks (by calling down into the
1854          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1855          * queue for otherwise the flush_work in the pageflip code will
1856          * deadlock.
1857          */
1858         if (queue_dig)
1859                 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1860         if (queue_hp)
1861                 schedule_work(&dev_priv->hotplug_work);
1862 }
1863
1864 static void gmbus_irq_handler(struct drm_device *dev)
1865 {
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867
1868         wake_up_all(&dev_priv->gmbus_wait_queue);
1869 }
1870
1871 static void dp_aux_irq_handler(struct drm_device *dev)
1872 {
1873         struct drm_i915_private *dev_priv = dev->dev_private;
1874
1875         wake_up_all(&dev_priv->gmbus_wait_queue);
1876 }
1877
1878 #if defined(CONFIG_DEBUG_FS)
1879 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1880                                          uint32_t crc0, uint32_t crc1,
1881                                          uint32_t crc2, uint32_t crc3,
1882                                          uint32_t crc4)
1883 {
1884         struct drm_i915_private *dev_priv = dev->dev_private;
1885         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1886         struct intel_pipe_crc_entry *entry;
1887         int head, tail;
1888
1889         spin_lock(&pipe_crc->lock);
1890
1891         if (!pipe_crc->entries) {
1892                 spin_unlock(&pipe_crc->lock);
1893                 DRM_ERROR("spurious interrupt\n");
1894                 return;
1895         }
1896
1897         head = pipe_crc->head;
1898         tail = pipe_crc->tail;
1899
1900         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1901                 spin_unlock(&pipe_crc->lock);
1902                 DRM_ERROR("CRC buffer overflowing\n");
1903                 return;
1904         }
1905
1906         entry = &pipe_crc->entries[head];
1907
1908         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1909         entry->crc[0] = crc0;
1910         entry->crc[1] = crc1;
1911         entry->crc[2] = crc2;
1912         entry->crc[3] = crc3;
1913         entry->crc[4] = crc4;
1914
1915         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1916         pipe_crc->head = head;
1917
1918         spin_unlock(&pipe_crc->lock);
1919
1920         wake_up_interruptible(&pipe_crc->wq);
1921 }
1922 #else
1923 static inline void
1924 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1925                              uint32_t crc0, uint32_t crc1,
1926                              uint32_t crc2, uint32_t crc3,
1927                              uint32_t crc4) {}
1928 #endif
1929
1930
1931 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1932 {
1933         struct drm_i915_private *dev_priv = dev->dev_private;
1934
1935         display_pipe_crc_irq_handler(dev, pipe,
1936                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1937                                      0, 0, 0, 0);
1938 }
1939
1940 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1941 {
1942         struct drm_i915_private *dev_priv = dev->dev_private;
1943
1944         display_pipe_crc_irq_handler(dev, pipe,
1945                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1946                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1947                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1948                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1949                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1950 }
1951
1952 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1953 {
1954         struct drm_i915_private *dev_priv = dev->dev_private;
1955         uint32_t res1, res2;
1956
1957         if (INTEL_INFO(dev)->gen >= 3)
1958                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1959         else
1960                 res1 = 0;
1961
1962         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1963                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1964         else
1965                 res2 = 0;
1966
1967         display_pipe_crc_irq_handler(dev, pipe,
1968                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1969                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1970                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1971                                      res1, res2);
1972 }
1973
1974 /* The RPS events need forcewake, so we add them to a work queue and mask their
1975  * IMR bits until the work is done. Other interrupts can be processed without
1976  * the work queue. */
1977 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1978 {
1979         if (pm_iir & dev_priv->pm_rps_events) {
1980                 spin_lock(&dev_priv->irq_lock);
1981                 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1982                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1983                 spin_unlock(&dev_priv->irq_lock);
1984
1985                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1986         }
1987
1988         if (HAS_VEBOX(dev_priv->dev)) {
1989                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1990                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1991
1992                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1993                         i915_handle_error(dev_priv->dev, false,
1994                                           "VEBOX CS error interrupt 0x%08x",
1995                                           pm_iir);
1996                 }
1997         }
1998 }
1999
2000 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
2001 {
2002         if (!drm_handle_vblank(dev, pipe))
2003                 return false;
2004
2005         return true;
2006 }
2007
2008 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
2009 {
2010         struct drm_i915_private *dev_priv = dev->dev_private;
2011         u32 pipe_stats[I915_MAX_PIPES] = { };
2012         int pipe;
2013
2014         spin_lock(&dev_priv->irq_lock);
2015         for_each_pipe(pipe) {
2016                 int reg;
2017                 u32 mask, iir_bit = 0;
2018
2019                 /*
2020                  * PIPESTAT bits get signalled even when the interrupt is
2021                  * disabled with the mask bits, and some of the status bits do
2022                  * not generate interrupts at all (like the underrun bit). Hence
2023                  * we need to be careful that we only handle what we want to
2024                  * handle.
2025                  */
2026                 mask = 0;
2027                 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
2028                         mask |= PIPE_FIFO_UNDERRUN_STATUS;
2029
2030                 switch (pipe) {
2031                 case PIPE_A:
2032                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
2033                         break;
2034                 case PIPE_B:
2035                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
2036                         break;
2037                 case PIPE_C:
2038                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2039                         break;
2040                 }
2041                 if (iir & iir_bit)
2042                         mask |= dev_priv->pipestat_irq_mask[pipe];
2043
2044                 if (!mask)
2045                         continue;
2046
2047                 reg = PIPESTAT(pipe);
2048                 mask |= PIPESTAT_INT_ENABLE_MASK;
2049                 pipe_stats[pipe] = I915_READ(reg) & mask;
2050
2051                 /*
2052                  * Clear the PIPE*STAT regs before the IIR
2053                  */
2054                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
2055                                         PIPESTAT_INT_STATUS_MASK))
2056                         I915_WRITE(reg, pipe_stats[pipe]);
2057         }
2058         spin_unlock(&dev_priv->irq_lock);
2059
2060         for_each_pipe(pipe) {
2061                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
2062                         intel_pipe_handle_vblank(dev, pipe);
2063
2064                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
2065                         intel_prepare_page_flip(dev, pipe);
2066                         intel_finish_page_flip(dev, pipe);
2067                 }
2068
2069                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2070                         i9xx_pipe_crc_irq_handler(dev, pipe);
2071
2072                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
2073                     intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
2074                         DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
2075         }
2076
2077         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2078                 gmbus_irq_handler(dev);
2079 }
2080
2081 static void i9xx_hpd_irq_handler(struct drm_device *dev)
2082 {
2083         struct drm_i915_private *dev_priv = dev->dev_private;
2084         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2085
2086         if (hotplug_status) {
2087                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2088                 /*
2089                  * Make sure hotplug status is cleared before we clear IIR, or else we
2090                  * may miss hotplug events.
2091                  */
2092                 POSTING_READ(PORT_HOTPLUG_STAT);
2093
2094                 if (IS_G4X(dev)) {
2095                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
2096
2097                         intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
2098                 } else {
2099                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2100
2101                         intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
2102                 }
2103
2104                 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
2105                     hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
2106                         dp_aux_irq_handler(dev);
2107         }
2108 }
2109
2110 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
2111 {
2112         struct drm_device *dev = arg;
2113         struct drm_i915_private *dev_priv = dev->dev_private;
2114         u32 iir, gt_iir, pm_iir;
2115         irqreturn_t ret = IRQ_NONE;
2116
2117         while (true) {
2118                 /* Find, clear, then process each source of interrupt */
2119
2120                 gt_iir = I915_READ(GTIIR);
2121                 if (gt_iir)
2122                         I915_WRITE(GTIIR, gt_iir);
2123
2124                 pm_iir = I915_READ(GEN6_PMIIR);
2125                 if (pm_iir)
2126                         I915_WRITE(GEN6_PMIIR, pm_iir);
2127
2128                 iir = I915_READ(VLV_IIR);
2129                 if (iir) {
2130                         /* Consume port before clearing IIR or we'll miss events */
2131                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
2132                                 i9xx_hpd_irq_handler(dev);
2133                         I915_WRITE(VLV_IIR, iir);
2134                 }
2135
2136                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
2137                         goto out;
2138
2139                 ret = IRQ_HANDLED;
2140
2141                 if (gt_iir)
2142                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
2143                 if (pm_iir)
2144                         gen6_rps_irq_handler(dev_priv, pm_iir);
2145                 /* Call regardless, as some status bits might not be
2146                  * signalled in iir */
2147                 valleyview_pipestat_irq_handler(dev, iir);
2148         }
2149
2150 out:
2151         return ret;
2152 }
2153
2154 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2155 {
2156         struct drm_device *dev = arg;
2157         struct drm_i915_private *dev_priv = dev->dev_private;
2158         u32 master_ctl, iir;
2159         irqreturn_t ret = IRQ_NONE;
2160
2161         for (;;) {
2162                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2163                 iir = I915_READ(VLV_IIR);
2164
2165                 if (master_ctl == 0 && iir == 0)
2166                         break;
2167
2168                 ret = IRQ_HANDLED;
2169
2170                 I915_WRITE(GEN8_MASTER_IRQ, 0);
2171
2172                 /* Find, clear, then process each source of interrupt */
2173
2174                 if (iir) {
2175                         /* Consume port before clearing IIR or we'll miss events */
2176                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
2177                                 i9xx_hpd_irq_handler(dev);
2178                         I915_WRITE(VLV_IIR, iir);
2179                 }
2180
2181                 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2182
2183                 /* Call regardless, as some status bits might not be
2184                  * signalled in iir */
2185                 valleyview_pipestat_irq_handler(dev, iir);
2186
2187                 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
2188                 POSTING_READ(GEN8_MASTER_IRQ);
2189         }
2190
2191         return ret;
2192 }
2193
2194 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
2195 {
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197         int pipe;
2198         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2199         u32 dig_hotplug_reg;
2200
2201         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2202         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2203
2204         intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
2205
2206         if (pch_iir & SDE_AUDIO_POWER_MASK) {
2207                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2208                                SDE_AUDIO_POWER_SHIFT);
2209                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2210                                  port_name(port));
2211         }
2212
2213         if (pch_iir & SDE_AUX_MASK)
2214                 dp_aux_irq_handler(dev);
2215
2216         if (pch_iir & SDE_GMBUS)
2217                 gmbus_irq_handler(dev);
2218
2219         if (pch_iir & SDE_AUDIO_HDCP_MASK)
2220                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2221
2222         if (pch_iir & SDE_AUDIO_TRANS_MASK)
2223                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2224
2225         if (pch_iir & SDE_POISON)
2226                 DRM_ERROR("PCH poison interrupt\n");
2227
2228         if (pch_iir & SDE_FDI_MASK)
2229                 for_each_pipe(pipe)
2230                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2231                                          pipe_name(pipe),
2232                                          I915_READ(FDI_RX_IIR(pipe)));
2233
2234         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2235                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2236
2237         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2238                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2239
2240         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2241                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
2242                                                           false))
2243                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
2244
2245         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2246                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2247                                                           false))
2248                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
2249 }
2250
2251 static void ivb_err_int_handler(struct drm_device *dev)
2252 {
2253         struct drm_i915_private *dev_priv = dev->dev_private;
2254         u32 err_int = I915_READ(GEN7_ERR_INT);
2255         enum pipe pipe;
2256
2257         if (err_int & ERR_INT_POISON)
2258                 DRM_ERROR("Poison interrupt\n");
2259
2260         for_each_pipe(pipe) {
2261                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
2262                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2263                                                                   false))
2264                                 DRM_ERROR("Pipe %c FIFO underrun\n",
2265                                           pipe_name(pipe));
2266                 }
2267
2268                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2269                         if (IS_IVYBRIDGE(dev))
2270                                 ivb_pipe_crc_irq_handler(dev, pipe);
2271                         else
2272                                 hsw_pipe_crc_irq_handler(dev, pipe);
2273                 }
2274         }
2275
2276         I915_WRITE(GEN7_ERR_INT, err_int);
2277 }
2278
2279 static void cpt_serr_int_handler(struct drm_device *dev)
2280 {
2281         struct drm_i915_private *dev_priv = dev->dev_private;
2282         u32 serr_int = I915_READ(SERR_INT);
2283
2284         if (serr_int & SERR_INT_POISON)
2285                 DRM_ERROR("PCH poison interrupt\n");
2286
2287         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2288                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
2289                                                           false))
2290                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
2291
2292         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2293                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2294                                                           false))
2295                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
2296
2297         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2298                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
2299                                                           false))
2300                         DRM_ERROR("PCH transcoder C FIFO underrun\n");
2301
2302         I915_WRITE(SERR_INT, serr_int);
2303 }
2304
2305 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2306 {
2307         struct drm_i915_private *dev_priv = dev->dev_private;
2308         int pipe;
2309         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2310         u32 dig_hotplug_reg;
2311
2312         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2313         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2314
2315         intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2316
2317         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2318                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2319                                SDE_AUDIO_POWER_SHIFT_CPT);
2320                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2321                                  port_name(port));
2322         }
2323
2324         if (pch_iir & SDE_AUX_MASK_CPT)
2325                 dp_aux_irq_handler(dev);
2326
2327         if (pch_iir & SDE_GMBUS_CPT)
2328                 gmbus_irq_handler(dev);
2329
2330         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2331                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2332
2333         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2334                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2335
2336         if (pch_iir & SDE_FDI_MASK_CPT)
2337                 for_each_pipe(pipe)
2338                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2339                                          pipe_name(pipe),
2340                                          I915_READ(FDI_RX_IIR(pipe)));
2341
2342         if (pch_iir & SDE_ERROR_CPT)
2343                 cpt_serr_int_handler(dev);
2344 }
2345
2346 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2347 {
2348         struct drm_i915_private *dev_priv = dev->dev_private;
2349         enum pipe pipe;
2350
2351         if (de_iir & DE_AUX_CHANNEL_A)
2352                 dp_aux_irq_handler(dev);
2353
2354         if (de_iir & DE_GSE)
2355                 intel_opregion_asle_intr(dev);
2356
2357         if (de_iir & DE_POISON)
2358                 DRM_ERROR("Poison interrupt\n");
2359
2360         for_each_pipe(pipe) {
2361                 if (de_iir & DE_PIPE_VBLANK(pipe))
2362                         intel_pipe_handle_vblank(dev, pipe);
2363
2364                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2365                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
2366                                 DRM_ERROR("Pipe %c FIFO underrun\n",
2367                                           pipe_name(pipe));
2368
2369                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2370                         i9xx_pipe_crc_irq_handler(dev, pipe);
2371
2372                 /* plane/pipes map 1:1 on ilk+ */
2373                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2374                         intel_prepare_page_flip(dev, pipe);
2375                         intel_finish_page_flip_plane(dev, pipe);
2376                 }
2377         }
2378
2379         /* check event from PCH */
2380         if (de_iir & DE_PCH_EVENT) {
2381                 u32 pch_iir = I915_READ(SDEIIR);
2382
2383                 if (HAS_PCH_CPT(dev))
2384                         cpt_irq_handler(dev, pch_iir);
2385                 else
2386                         ibx_irq_handler(dev, pch_iir);
2387
2388                 /* should clear PCH hotplug event before clear CPU irq */
2389                 I915_WRITE(SDEIIR, pch_iir);
2390         }
2391
2392         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2393                 ironlake_rps_change_irq_handler(dev);
2394 }
2395
2396 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2397 {
2398         struct drm_i915_private *dev_priv = dev->dev_private;
2399         enum pipe pipe;
2400
2401         if (de_iir & DE_ERR_INT_IVB)
2402                 ivb_err_int_handler(dev);
2403
2404         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2405                 dp_aux_irq_handler(dev);
2406
2407         if (de_iir & DE_GSE_IVB)
2408                 intel_opregion_asle_intr(dev);
2409
2410         for_each_pipe(pipe) {
2411                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2412                         intel_pipe_handle_vblank(dev, pipe);
2413
2414                 /* plane/pipes map 1:1 on ilk+ */
2415                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2416                         intel_prepare_page_flip(dev, pipe);
2417                         intel_finish_page_flip_plane(dev, pipe);
2418                 }
2419         }
2420
2421         /* check event from PCH */
2422         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2423                 u32 pch_iir = I915_READ(SDEIIR);
2424
2425                 cpt_irq_handler(dev, pch_iir);
2426
2427                 /* clear PCH hotplug event before clear CPU irq */
2428                 I915_WRITE(SDEIIR, pch_iir);
2429         }
2430 }
2431
2432 /*
2433  * To handle irqs with the minimum potential races with fresh interrupts, we:
2434  * 1 - Disable Master Interrupt Control.
2435  * 2 - Find the source(s) of the interrupt.
2436  * 3 - Clear the Interrupt Identity bits (IIR).
2437  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2438  * 5 - Re-enable Master Interrupt Control.
2439  */
2440 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2441 {
2442         struct drm_device *dev = arg;
2443         struct drm_i915_private *dev_priv = dev->dev_private;
2444         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2445         irqreturn_t ret = IRQ_NONE;
2446
2447         /* We get interrupts on unclaimed registers, so check for this before we
2448          * do any I915_{READ,WRITE}. */
2449         intel_uncore_check_errors(dev);
2450
2451         /* disable master interrupt before clearing iir  */
2452         de_ier = I915_READ(DEIER);
2453         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2454         POSTING_READ(DEIER);
2455
2456         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2457          * interrupts will will be stored on its back queue, and then we'll be
2458          * able to process them after we restore SDEIER (as soon as we restore
2459          * it, we'll get an interrupt if SDEIIR still has something to process
2460          * due to its back queue). */
2461         if (!HAS_PCH_NOP(dev)) {
2462                 sde_ier = I915_READ(SDEIER);
2463                 I915_WRITE(SDEIER, 0);
2464                 POSTING_READ(SDEIER);
2465         }
2466
2467         /* Find, clear, then process each source of interrupt */
2468
2469         gt_iir = I915_READ(GTIIR);
2470         if (gt_iir) {
2471                 I915_WRITE(GTIIR, gt_iir);
2472                 ret = IRQ_HANDLED;
2473                 if (INTEL_INFO(dev)->gen >= 6)
2474                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
2475                 else
2476                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2477         }
2478
2479         de_iir = I915_READ(DEIIR);
2480         if (de_iir) {
2481                 I915_WRITE(DEIIR, de_iir);
2482                 ret = IRQ_HANDLED;
2483                 if (INTEL_INFO(dev)->gen >= 7)
2484                         ivb_display_irq_handler(dev, de_iir);
2485                 else
2486                         ilk_display_irq_handler(dev, de_iir);
2487         }
2488
2489         if (INTEL_INFO(dev)->gen >= 6) {
2490                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2491                 if (pm_iir) {
2492                         I915_WRITE(GEN6_PMIIR, pm_iir);
2493                         ret = IRQ_HANDLED;
2494                         gen6_rps_irq_handler(dev_priv, pm_iir);
2495                 }
2496         }
2497
2498         I915_WRITE(DEIER, de_ier);
2499         POSTING_READ(DEIER);
2500         if (!HAS_PCH_NOP(dev)) {
2501                 I915_WRITE(SDEIER, sde_ier);
2502                 POSTING_READ(SDEIER);
2503         }
2504
2505         return ret;
2506 }
2507
2508 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2509 {
2510         struct drm_device *dev = arg;
2511         struct drm_i915_private *dev_priv = dev->dev_private;
2512         u32 master_ctl;
2513         irqreturn_t ret = IRQ_NONE;
2514         uint32_t tmp = 0;
2515         enum pipe pipe;
2516
2517         master_ctl = I915_READ(GEN8_MASTER_IRQ);
2518         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2519         if (!master_ctl)
2520                 return IRQ_NONE;
2521
2522         I915_WRITE(GEN8_MASTER_IRQ, 0);
2523         POSTING_READ(GEN8_MASTER_IRQ);
2524
2525         /* Find, clear, then process each source of interrupt */
2526
2527         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2528
2529         if (master_ctl & GEN8_DE_MISC_IRQ) {
2530                 tmp = I915_READ(GEN8_DE_MISC_IIR);
2531                 if (tmp) {
2532                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2533                         ret = IRQ_HANDLED;
2534                         if (tmp & GEN8_DE_MISC_GSE)
2535                                 intel_opregion_asle_intr(dev);
2536                         else
2537                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2538                 }
2539                 else
2540                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2541         }
2542
2543         if (master_ctl & GEN8_DE_PORT_IRQ) {
2544                 tmp = I915_READ(GEN8_DE_PORT_IIR);
2545                 if (tmp) {
2546                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2547                         ret = IRQ_HANDLED;
2548                         if (tmp & GEN8_AUX_CHANNEL_A)
2549                                 dp_aux_irq_handler(dev);
2550                         else
2551                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2552                 }
2553                 else
2554                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2555         }
2556
2557         for_each_pipe(pipe) {
2558                 uint32_t pipe_iir;
2559
2560                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2561                         continue;
2562
2563                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2564                 if (pipe_iir) {
2565                         ret = IRQ_HANDLED;
2566                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2567                         if (pipe_iir & GEN8_PIPE_VBLANK)
2568                                 intel_pipe_handle_vblank(dev, pipe);
2569
2570                         if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
2571                                 intel_prepare_page_flip(dev, pipe);
2572                                 intel_finish_page_flip_plane(dev, pipe);
2573                         }
2574
2575                         if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2576                                 hsw_pipe_crc_irq_handler(dev, pipe);
2577
2578                         if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2579                                 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2580                                                                           false))
2581                                         DRM_ERROR("Pipe %c FIFO underrun\n",
2582                                                   pipe_name(pipe));
2583                         }
2584
2585                         if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2586                                 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2587                                           pipe_name(pipe),
2588                                           pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2589                         }
2590                 } else
2591                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2592         }
2593
2594         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2595                 /*
2596                  * FIXME(BDW): Assume for now that the new interrupt handling
2597                  * scheme also closed the SDE interrupt handling race we've seen
2598                  * on older pch-split platforms. But this needs testing.
2599                  */
2600                 u32 pch_iir = I915_READ(SDEIIR);
2601                 if (pch_iir) {
2602                         I915_WRITE(SDEIIR, pch_iir);
2603                         ret = IRQ_HANDLED;
2604                         cpt_irq_handler(dev, pch_iir);
2605                 } else
2606                         DRM_ERROR("The master control interrupt lied (SDE)!\n");
2607
2608         }
2609
2610         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2611         POSTING_READ(GEN8_MASTER_IRQ);
2612
2613         return ret;
2614 }
2615
2616 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2617                                bool reset_completed)
2618 {
2619         struct intel_engine_cs *ring;
2620         int i;
2621
2622         /*
2623          * Notify all waiters for GPU completion events that reset state has
2624          * been changed, and that they need to restart their wait after
2625          * checking for potential errors (and bail out to drop locks if there is
2626          * a gpu reset pending so that i915_error_work_func can acquire them).
2627          */
2628
2629         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2630         for_each_ring(ring, dev_priv, i)
2631                 wake_up_all(&ring->irq_queue);
2632
2633         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2634         wake_up_all(&dev_priv->pending_flip_queue);
2635
2636         /*
2637          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2638          * reset state is cleared.
2639          */
2640         if (reset_completed)
2641                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2642 }
2643
2644 /**
2645  * i915_error_work_func - do process context error handling work
2646  * @work: work struct
2647  *
2648  * Fire an error uevent so userspace can see that a hang or error
2649  * was detected.
2650  */
2651 static void i915_error_work_func(struct work_struct *work)
2652 {
2653         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2654                                                     work);
2655         struct drm_i915_private *dev_priv =
2656                 container_of(error, struct drm_i915_private, gpu_error);
2657         struct drm_device *dev = dev_priv->dev;
2658         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2659         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2660         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2661         int ret;
2662
2663         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2664
2665         /*
2666          * Note that there's only one work item which does gpu resets, so we
2667          * need not worry about concurrent gpu resets potentially incrementing
2668          * error->reset_counter twice. We only need to take care of another
2669          * racing irq/hangcheck declaring the gpu dead for a second time. A
2670          * quick check for that is good enough: schedule_work ensures the
2671          * correct ordering between hang detection and this work item, and since
2672          * the reset in-progress bit is only ever set by code outside of this
2673          * work we don't need to worry about any other races.
2674          */
2675         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2676                 DRM_DEBUG_DRIVER("resetting chip\n");
2677                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2678                                    reset_event);
2679
2680                 /*
2681                  * In most cases it's guaranteed that we get here with an RPM
2682                  * reference held, for example because there is a pending GPU
2683                  * request that won't finish until the reset is done. This
2684                  * isn't the case at least when we get here by doing a
2685                  * simulated reset via debugs, so get an RPM reference.
2686                  */
2687                 intel_runtime_pm_get(dev_priv);
2688                 /*
2689                  * All state reset _must_ be completed before we update the
2690                  * reset counter, for otherwise waiters might miss the reset
2691                  * pending state and not properly drop locks, resulting in
2692                  * deadlocks with the reset work.
2693                  */
2694                 ret = i915_reset(dev);
2695
2696                 intel_display_handle_reset(dev);
2697
2698                 intel_runtime_pm_put(dev_priv);
2699
2700                 if (ret == 0) {
2701                         /*
2702                          * After all the gem state is reset, increment the reset
2703                          * counter and wake up everyone waiting for the reset to
2704                          * complete.
2705                          *
2706                          * Since unlock operations are a one-sided barrier only,
2707                          * we need to insert a barrier here to order any seqno
2708                          * updates before
2709                          * the counter increment.
2710                          */
2711                         smp_mb__before_atomic();
2712                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2713
2714                         kobject_uevent_env(&dev->primary->kdev->kobj,
2715                                            KOBJ_CHANGE, reset_done_event);
2716                 } else {
2717                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2718                 }
2719
2720                 /*
2721                  * Note: The wake_up also serves as a memory barrier so that
2722                  * waiters see the update value of the reset counter atomic_t.
2723                  */
2724                 i915_error_wake_up(dev_priv, true);
2725         }
2726 }
2727
2728 static void i915_report_and_clear_eir(struct drm_device *dev)
2729 {
2730         struct drm_i915_private *dev_priv = dev->dev_private;
2731         uint32_t instdone[I915_NUM_INSTDONE_REG];
2732         u32 eir = I915_READ(EIR);
2733         int pipe, i;
2734
2735         if (!eir)
2736                 return;
2737
2738         pr_err("render error detected, EIR: 0x%08x\n", eir);
2739
2740         i915_get_extra_instdone(dev, instdone);
2741
2742         if (IS_G4X(dev)) {
2743                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2744                         u32 ipeir = I915_READ(IPEIR_I965);
2745
2746                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2747                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2748                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2749                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2750                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2751                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2752                         I915_WRITE(IPEIR_I965, ipeir);
2753                         POSTING_READ(IPEIR_I965);
2754                 }
2755                 if (eir & GM45_ERROR_PAGE_TABLE) {
2756                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2757                         pr_err("page table error\n");
2758                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2759                         I915_WRITE(PGTBL_ER, pgtbl_err);
2760                         POSTING_READ(PGTBL_ER);
2761                 }
2762         }
2763
2764         if (!IS_GEN2(dev)) {
2765                 if (eir & I915_ERROR_PAGE_TABLE) {
2766                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2767                         pr_err("page table error\n");
2768                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2769                         I915_WRITE(PGTBL_ER, pgtbl_err);
2770                         POSTING_READ(PGTBL_ER);
2771                 }
2772         }
2773
2774         if (eir & I915_ERROR_MEMORY_REFRESH) {
2775                 pr_err("memory refresh error:\n");
2776                 for_each_pipe(pipe)
2777                         pr_err("pipe %c stat: 0x%08x\n",
2778                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2779                 /* pipestat has already been acked */
2780         }
2781         if (eir & I915_ERROR_INSTRUCTION) {
2782                 pr_err("instruction error\n");
2783                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2784                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2785                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2786                 if (INTEL_INFO(dev)->gen < 4) {
2787                         u32 ipeir = I915_READ(IPEIR);
2788
2789                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2790                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2791                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2792                         I915_WRITE(IPEIR, ipeir);
2793                         POSTING_READ(IPEIR);
2794                 } else {
2795                         u32 ipeir = I915_READ(IPEIR_I965);
2796
2797                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2798                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2799                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2800                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2801                         I915_WRITE(IPEIR_I965, ipeir);
2802                         POSTING_READ(IPEIR_I965);
2803                 }
2804         }
2805
2806         I915_WRITE(EIR, eir);
2807         POSTING_READ(EIR);
2808         eir = I915_READ(EIR);
2809         if (eir) {
2810                 /*
2811                  * some errors might have become stuck,
2812                  * mask them.
2813                  */
2814                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2815                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2816                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2817         }
2818 }
2819
2820 /**
2821  * i915_handle_error - handle an error interrupt
2822  * @dev: drm device
2823  *
2824  * Do some basic checking of regsiter state at error interrupt time and
2825  * dump it to the syslog.  Also call i915_capture_error_state() to make
2826  * sure we get a record and make it available in debugfs.  Fire a uevent
2827  * so userspace knows something bad happened (should trigger collection
2828  * of a ring dump etc.).
2829  */
2830 void i915_handle_error(struct drm_device *dev, bool wedged,
2831                        const char *fmt, ...)
2832 {
2833         struct drm_i915_private *dev_priv = dev->dev_private;
2834         va_list args;
2835         char error_msg[80];
2836
2837         va_start(args, fmt);
2838         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2839         va_end(args);
2840
2841         i915_capture_error_state(dev, wedged, error_msg);
2842         i915_report_and_clear_eir(dev);
2843
2844         if (wedged) {
2845                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2846                                 &dev_priv->gpu_error.reset_counter);
2847
2848                 /*
2849                  * Wakeup waiting processes so that the reset work function
2850                  * i915_error_work_func doesn't deadlock trying to grab various
2851                  * locks. By bumping the reset counter first, the woken
2852                  * processes will see a reset in progress and back off,
2853                  * releasing their locks and then wait for the reset completion.
2854                  * We must do this for _all_ gpu waiters that might hold locks
2855                  * that the reset work needs to acquire.
2856                  *
2857                  * Note: The wake_up serves as the required memory barrier to
2858                  * ensure that the waiters see the updated value of the reset
2859                  * counter atomic_t.
2860                  */
2861                 i915_error_wake_up(dev_priv, false);
2862         }
2863
2864         /*
2865          * Our reset work can grab modeset locks (since it needs to reset the
2866          * state of outstanding pagelips). Hence it must not be run on our own
2867          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2868          * code will deadlock.
2869          */
2870         schedule_work(&dev_priv->gpu_error.work);
2871 }
2872
2873 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2874 {
2875         struct drm_i915_private *dev_priv = dev->dev_private;
2876         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878         struct drm_i915_gem_object *obj;
2879         struct intel_unpin_work *work;
2880         unsigned long flags;
2881         bool stall_detected;
2882
2883         /* Ignore early vblank irqs */
2884         if (intel_crtc == NULL)
2885                 return;
2886
2887         spin_lock_irqsave(&dev->event_lock, flags);
2888         work = intel_crtc->unpin_work;
2889
2890         if (work == NULL ||
2891             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2892             !work->enable_stall_check) {
2893                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2894                 spin_unlock_irqrestore(&dev->event_lock, flags);
2895                 return;
2896         }
2897
2898         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2899         obj = work->pending_flip_obj;
2900         if (INTEL_INFO(dev)->gen >= 4) {
2901                 int dspsurf = DSPSURF(intel_crtc->plane);
2902                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2903                                         i915_gem_obj_ggtt_offset(obj);
2904         } else {
2905                 int dspaddr = DSPADDR(intel_crtc->plane);
2906                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2907                                                         crtc->y * crtc->primary->fb->pitches[0] +
2908                                                         crtc->x * crtc->primary->fb->bits_per_pixel/8);
2909         }
2910
2911         spin_unlock_irqrestore(&dev->event_lock, flags);
2912
2913         if (stall_detected) {
2914                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2915                 intel_prepare_page_flip(dev, intel_crtc->plane);
2916         }
2917 }
2918
2919 /* Called from drm generic code, passed 'crtc' which
2920  * we use as a pipe index
2921  */
2922 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2923 {
2924         struct drm_i915_private *dev_priv = dev->dev_private;
2925         unsigned long irqflags;
2926
2927         if (!i915_pipe_enabled(dev, pipe))
2928                 return -EINVAL;
2929
2930         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2931         if (INTEL_INFO(dev)->gen >= 4)
2932                 i915_enable_pipestat(dev_priv, pipe,
2933                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2934         else
2935                 i915_enable_pipestat(dev_priv, pipe,
2936                                      PIPE_VBLANK_INTERRUPT_STATUS);
2937         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2938
2939         return 0;
2940 }
2941
2942 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2943 {
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945         unsigned long irqflags;
2946         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2947                                                      DE_PIPE_VBLANK(pipe);
2948
2949         if (!i915_pipe_enabled(dev, pipe))
2950                 return -EINVAL;
2951
2952         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2953         ironlake_enable_display_irq(dev_priv, bit);
2954         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2955
2956         return 0;
2957 }
2958
2959 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2960 {
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         unsigned long irqflags;
2963
2964         if (!i915_pipe_enabled(dev, pipe))
2965                 return -EINVAL;
2966
2967         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2968         i915_enable_pipestat(dev_priv, pipe,
2969                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2970         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2971
2972         return 0;
2973 }
2974
2975 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2976 {
2977         struct drm_i915_private *dev_priv = dev->dev_private;
2978         unsigned long irqflags;
2979
2980         if (!i915_pipe_enabled(dev, pipe))
2981                 return -EINVAL;
2982
2983         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2984         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2985         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2986         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2987         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2988         return 0;
2989 }
2990
2991 /* Called from drm generic code, passed 'crtc' which
2992  * we use as a pipe index
2993  */
2994 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2995 {
2996         struct drm_i915_private *dev_priv = dev->dev_private;
2997         unsigned long irqflags;
2998
2999         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3000         i915_disable_pipestat(dev_priv, pipe,
3001                               PIPE_VBLANK_INTERRUPT_STATUS |
3002                               PIPE_START_VBLANK_INTERRUPT_STATUS);
3003         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3004 }
3005
3006 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
3007 {
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         unsigned long irqflags;
3010         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
3011                                                      DE_PIPE_VBLANK(pipe);
3012
3013         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3014         ironlake_disable_display_irq(dev_priv, bit);
3015         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3016 }
3017
3018 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
3019 {
3020         struct drm_i915_private *dev_priv = dev->dev_private;
3021         unsigned long irqflags;
3022
3023         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3024         i915_disable_pipestat(dev_priv, pipe,
3025                               PIPE_START_VBLANK_INTERRUPT_STATUS);
3026         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3027 }
3028
3029 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
3030 {
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         unsigned long irqflags;
3033
3034         if (!i915_pipe_enabled(dev, pipe))
3035                 return;
3036
3037         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3038         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
3039         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
3040         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
3041         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3042 }
3043
3044 static u32
3045 ring_last_seqno(struct intel_engine_cs *ring)
3046 {
3047         return list_entry(ring->request_list.prev,
3048                           struct drm_i915_gem_request, list)->seqno;
3049 }
3050
3051 static bool
3052 ring_idle(struct intel_engine_cs *ring, u32 seqno)
3053 {
3054         return (list_empty(&ring->request_list) ||
3055                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
3056 }
3057
3058 static bool
3059 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
3060 {
3061         if (INTEL_INFO(dev)->gen >= 8) {
3062                 return (ipehr >> 23) == 0x1c;
3063         } else {
3064                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
3065                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
3066                                  MI_SEMAPHORE_REGISTER);
3067         }
3068 }
3069
3070 static struct intel_engine_cs *
3071 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
3072 {
3073         struct drm_i915_private *dev_priv = ring->dev->dev_private;
3074         struct intel_engine_cs *signaller;
3075         int i;
3076
3077         if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
3078                 for_each_ring(signaller, dev_priv, i) {
3079                         if (ring == signaller)
3080                                 continue;
3081
3082                         if (offset == signaller->semaphore.signal_ggtt[ring->id])
3083                                 return signaller;
3084                 }
3085         } else {
3086                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
3087
3088                 for_each_ring(signaller, dev_priv, i) {
3089                         if(ring == signaller)
3090                                 continue;
3091
3092                         if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
3093                                 return signaller;
3094                 }
3095         }
3096
3097         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
3098                   ring->id, ipehr, offset);
3099
3100         return NULL;
3101 }
3102
3103 static struct intel_engine_cs *
3104 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
3105 {
3106         struct drm_i915_private *dev_priv = ring->dev->dev_private;
3107         u32 cmd, ipehr, head;
3108         u64 offset = 0;
3109         int i, backwards;
3110
3111         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
3112         if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
3113                 return NULL;
3114
3115         /*
3116          * HEAD is likely pointing to the dword after the actual command,
3117          * so scan backwards until we find the MBOX. But limit it to just 3
3118          * or 4 dwords depending on the semaphore wait command size.
3119          * Note that we don't care about ACTHD here since that might
3120          * point at at batch, and semaphores are always emitted into the
3121          * ringbuffer itself.
3122          */
3123         head = I915_READ_HEAD(ring) & HEAD_ADDR;
3124         backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
3125
3126         for (i = backwards; i; --i) {
3127                 /*
3128                  * Be paranoid and presume the hw has gone off into the wild -
3129                  * our ring is smaller than what the hardware (and hence
3130                  * HEAD_ADDR) allows. Also handles wrap-around.
3131                  */
3132                 head &= ring->buffer->size - 1;
3133
3134                 /* This here seems to blow up */
3135                 cmd = ioread32(ring->buffer->virtual_start + head);
3136                 if (cmd == ipehr)
3137                         break;
3138
3139                 head -= 4;
3140         }
3141
3142         if (!i)
3143                 return NULL;
3144
3145         *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
3146         if (INTEL_INFO(ring->dev)->gen >= 8) {
3147                 offset = ioread32(ring->buffer->virtual_start + head + 12);
3148                 offset <<= 32;
3149                 offset = ioread32(ring->buffer->virtual_start + head + 8);
3150         }
3151         return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
3152 }
3153
3154 static int semaphore_passed(struct intel_engine_cs *ring)
3155 {
3156         struct drm_i915_private *dev_priv = ring->dev->dev_private;
3157         struct intel_engine_cs *signaller;
3158         u32 seqno;
3159
3160         ring->hangcheck.deadlock++;
3161
3162         signaller = semaphore_waits_for(ring, &seqno);
3163         if (signaller == NULL)
3164                 return -1;
3165
3166         /* Prevent pathological recursion due to driver bugs */
3167         if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
3168                 return -1;
3169
3170         if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
3171                 return 1;
3172
3173         /* cursory check for an unkickable deadlock */
3174         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
3175             semaphore_passed(signaller) < 0)
3176                 return -1;
3177
3178         return 0;
3179 }
3180
3181 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
3182 {
3183         struct intel_engine_cs *ring;
3184         int i;
3185
3186         for_each_ring(ring, dev_priv, i)
3187                 ring->hangcheck.deadlock = 0;
3188 }
3189
3190 static enum intel_ring_hangcheck_action
3191 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
3192 {
3193         struct drm_device *dev = ring->dev;
3194         struct drm_i915_private *dev_priv = dev->dev_private;
3195         u32 tmp;
3196
3197         if (acthd != ring->hangcheck.acthd) {
3198                 if (acthd > ring->hangcheck.max_acthd) {
3199                         ring->hangcheck.max_acthd = acthd;
3200                         return HANGCHECK_ACTIVE;
3201                 }
3202
3203                 return HANGCHECK_ACTIVE_LOOP;
3204         }
3205
3206         if (IS_GEN2(dev))
3207                 return HANGCHECK_HUNG;
3208
3209         /* Is the chip hanging on a WAIT_FOR_EVENT?
3210          * If so we can simply poke the RB_WAIT bit
3211          * and break the hang. This should work on
3212          * all but the second generation chipsets.
3213          */
3214         tmp = I915_READ_CTL(ring);
3215         if (tmp & RING_WAIT) {
3216                 i915_handle_error(dev, false,
3217                                   "Kicking stuck wait on %s",
3218                                   ring->name);
3219                 I915_WRITE_CTL(ring, tmp);
3220                 return HANGCHECK_KICK;
3221         }
3222
3223         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3224                 switch (semaphore_passed(ring)) {
3225                 default:
3226                         return HANGCHECK_HUNG;
3227                 case 1:
3228                         i915_handle_error(dev, false,
3229                                           "Kicking stuck semaphore on %s",
3230                                           ring->name);
3231                         I915_WRITE_CTL(ring, tmp);
3232                         return HANGCHECK_KICK;
3233                 case 0:
3234                         return HANGCHECK_WAIT;
3235                 }
3236         }
3237
3238         return HANGCHECK_HUNG;
3239 }
3240
3241 /**
3242  * This is called when the chip hasn't reported back with completed
3243  * batchbuffers in a long time. We keep track per ring seqno progress and
3244  * if there are no progress, hangcheck score for that ring is increased.
3245  * Further, acthd is inspected to see if the ring is stuck. On stuck case
3246  * we kick the ring. If we see no progress on three subsequent calls
3247  * we assume chip is wedged and try to fix it by resetting the chip.
3248  */
3249 static void i915_hangcheck_elapsed(unsigned long data)
3250 {
3251         struct drm_device *dev = (struct drm_device *)data;
3252         struct drm_i915_private *dev_priv = dev->dev_private;
3253         struct intel_engine_cs *ring;
3254         int i;
3255         int busy_count = 0, rings_hung = 0;
3256         bool stuck[I915_NUM_RINGS] = { 0 };
3257 #define BUSY 1
3258 #define KICK 5
3259 #define HUNG 20
3260
3261         if (!i915.enable_hangcheck)
3262                 return;
3263
3264         for_each_ring(ring, dev_priv, i) {
3265                 u64 acthd;
3266                 u32 seqno;
3267                 bool busy = true;
3268
3269                 semaphore_clear_deadlocks(dev_priv);
3270
3271                 seqno = ring->get_seqno(ring, false);
3272                 acthd = intel_ring_get_active_head(ring);
3273
3274                 if (ring->hangcheck.seqno == seqno) {
3275                         if (ring_idle(ring, seqno)) {
3276                                 ring->hangcheck.action = HANGCHECK_IDLE;
3277
3278                                 if (waitqueue_active(&ring->irq_queue)) {
3279                                         /* Issue a wake-up to catch stuck h/w. */
3280                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
3281                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
3282                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3283                                                                   ring->name);
3284                                                 else
3285                                                         DRM_INFO("Fake missed irq on %s\n",
3286                                                                  ring->name);
3287                                                 wake_up_all(&ring->irq_queue);
3288                                         }
3289                                         /* Safeguard against driver failure */
3290                                         ring->hangcheck.score += BUSY;
3291                                 } else
3292                                         busy = false;
3293                         } else {
3294                                 /* We always increment the hangcheck score
3295                                  * if the ring is busy and still processing
3296                                  * the same request, so that no single request
3297                                  * can run indefinitely (such as a chain of
3298                                  * batches). The only time we do not increment
3299                                  * the hangcheck score on this ring, if this
3300                                  * ring is in a legitimate wait for another
3301                                  * ring. In that case the waiting ring is a
3302                                  * victim and we want to be sure we catch the
3303                                  * right culprit. Then every time we do kick
3304                                  * the ring, add a small increment to the
3305                                  * score so that we can catch a batch that is
3306                                  * being repeatedly kicked and so responsible
3307                                  * for stalling the machine.
3308                                  */
3309                                 ring->hangcheck.action = ring_stuck(ring,
3310                                                                     acthd);
3311
3312                                 switch (ring->hangcheck.action) {
3313                                 case HANGCHECK_IDLE:
3314                                 case HANGCHECK_WAIT:
3315                                 case HANGCHECK_ACTIVE:
3316                                         break;
3317                                 case HANGCHECK_ACTIVE_LOOP:
3318                                         ring->hangcheck.score += BUSY;
3319                                         break;
3320                                 case HANGCHECK_KICK:
3321                                         ring->hangcheck.score += KICK;
3322                                         break;
3323                                 case HANGCHECK_HUNG:
3324                                         ring->hangcheck.score += HUNG;
3325                                         stuck[i] = true;
3326                                         break;
3327                                 }
3328                         }
3329                 } else {
3330                         ring->hangcheck.action = HANGCHECK_ACTIVE;
3331
3332                         /* Gradually reduce the count so that we catch DoS
3333                          * attempts across multiple batches.
3334                          */
3335                         if (ring->hangcheck.score > 0)
3336                                 ring->hangcheck.score--;
3337
3338                         ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3339                 }
3340
3341                 ring->hangcheck.seqno = seqno;
3342                 ring->hangcheck.acthd = acthd;
3343                 busy_count += busy;
3344         }
3345
3346         for_each_ring(ring, dev_priv, i) {
3347                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3348                         DRM_INFO("%s on %s\n",
3349                                  stuck[i] ? "stuck" : "no progress",
3350                                  ring->name);
3351                         rings_hung++;
3352                 }
3353         }
3354
3355         if (rings_hung)
3356                 return i915_handle_error(dev, true, "Ring hung");
3357
3358         if (busy_count)
3359                 /* Reset timer case chip hangs without another request
3360                  * being added */
3361                 i915_queue_hangcheck(dev);
3362 }
3363
3364 void i915_queue_hangcheck(struct drm_device *dev)
3365 {
3366         struct drm_i915_private *dev_priv = dev->dev_private;
3367         if (!i915.enable_hangcheck)
3368                 return;
3369
3370         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3371                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3372 }
3373
3374 static void ibx_irq_reset(struct drm_device *dev)
3375 {
3376         struct drm_i915_private *dev_priv = dev->dev_private;
3377
3378         if (HAS_PCH_NOP(dev))
3379                 return;
3380
3381         GEN5_IRQ_RESET(SDE);
3382
3383         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3384                 I915_WRITE(SERR_INT, 0xffffffff);
3385 }
3386
3387 /*
3388  * SDEIER is also touched by the interrupt handler to work around missed PCH
3389  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3390  * instead we unconditionally enable all PCH interrupt sources here, but then
3391  * only unmask them as needed with SDEIMR.
3392  *
3393  * This function needs to be called before interrupts are enabled.
3394  */
3395 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3396 {
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398
3399         if (HAS_PCH_NOP(dev))
3400                 return;
3401
3402         WARN_ON(I915_READ(SDEIER) != 0);
3403         I915_WRITE(SDEIER, 0xffffffff);
3404         POSTING_READ(SDEIER);
3405 }
3406
3407 static void gen5_gt_irq_reset(struct drm_device *dev)
3408 {
3409         struct drm_i915_private *dev_priv = dev->dev_private;
3410
3411         GEN5_IRQ_RESET(GT);
3412         if (INTEL_INFO(dev)->gen >= 6)
3413                 GEN5_IRQ_RESET(GEN6_PM);
3414 }
3415
3416 /* drm_dma.h hooks
3417 */
3418 static void ironlake_irq_reset(struct drm_device *dev)
3419 {
3420         struct drm_i915_private *dev_priv = dev->dev_private;
3421
3422         I915_WRITE(HWSTAM, 0xffffffff);
3423
3424         GEN5_IRQ_RESET(DE);
3425         if (IS_GEN7(dev))
3426                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3427
3428         gen5_gt_irq_reset(dev);
3429
3430         ibx_irq_reset(dev);
3431 }
3432
3433 static void valleyview_irq_preinstall(struct drm_device *dev)
3434 {
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436         int pipe;
3437
3438         /* VLV magic */
3439         I915_WRITE(VLV_IMR, 0);
3440         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3441         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3442         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3443
3444         /* and GT */
3445         I915_WRITE(GTIIR, I915_READ(GTIIR));
3446         I915_WRITE(GTIIR, I915_READ(GTIIR));
3447
3448         gen5_gt_irq_reset(dev);
3449
3450         I915_WRITE(DPINVGTT, 0xff);
3451
3452         I915_WRITE(PORT_HOTPLUG_EN, 0);
3453         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3454         for_each_pipe(pipe)
3455                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3456         I915_WRITE(VLV_IIR, 0xffffffff);
3457         I915_WRITE(VLV_IMR, 0xffffffff);
3458         I915_WRITE(VLV_IER, 0x0);
3459         POSTING_READ(VLV_IER);
3460 }
3461
3462 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3463 {
3464         GEN8_IRQ_RESET_NDX(GT, 0);
3465         GEN8_IRQ_RESET_NDX(GT, 1);
3466         GEN8_IRQ_RESET_NDX(GT, 2);
3467         GEN8_IRQ_RESET_NDX(GT, 3);
3468 }
3469
3470 static void gen8_irq_reset(struct drm_device *dev)
3471 {
3472         struct drm_i915_private *dev_priv = dev->dev_private;
3473         int pipe;
3474
3475         I915_WRITE(GEN8_MASTER_IRQ, 0);
3476         POSTING_READ(GEN8_MASTER_IRQ);
3477
3478         gen8_gt_irq_reset(dev_priv);
3479
3480         for_each_pipe(pipe)
3481                 if (intel_display_power_enabled(dev_priv,
3482                                                 POWER_DOMAIN_PIPE(pipe)))
3483                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3484
3485         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3486         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3487         GEN5_IRQ_RESET(GEN8_PCU_);
3488
3489         ibx_irq_reset(dev);
3490 }
3491
3492 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3493 {
3494         unsigned long irqflags;
3495
3496         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3497         GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3498                           ~dev_priv->de_irq_mask[PIPE_B]);
3499         GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3500                           ~dev_priv->de_irq_mask[PIPE_C]);
3501         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3502 }
3503
3504 static void cherryview_irq_preinstall(struct drm_device *dev)
3505 {
3506         struct drm_i915_private *dev_priv = dev->dev_private;
3507         int pipe;
3508
3509         I915_WRITE(GEN8_MASTER_IRQ, 0);
3510         POSTING_READ(GEN8_MASTER_IRQ);
3511
3512         gen8_gt_irq_reset(dev_priv);
3513
3514         GEN5_IRQ_RESET(GEN8_PCU_);
3515
3516         POSTING_READ(GEN8_PCU_IIR);
3517
3518         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3519
3520         I915_WRITE(PORT_HOTPLUG_EN, 0);
3521         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3522
3523         for_each_pipe(pipe)
3524                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3525
3526         I915_WRITE(VLV_IMR, 0xffffffff);
3527         I915_WRITE(VLV_IER, 0x0);
3528         I915_WRITE(VLV_IIR, 0xffffffff);
3529         POSTING_READ(VLV_IIR);
3530 }
3531
3532 static void ibx_hpd_irq_setup(struct drm_device *dev)
3533 {
3534         struct drm_i915_private *dev_priv = dev->dev_private;
3535         struct intel_encoder *intel_encoder;
3536         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3537
3538         if (HAS_PCH_IBX(dev)) {
3539                 hotplug_irqs = SDE_HOTPLUG_MASK;
3540                 for_each_intel_encoder(dev, intel_encoder)
3541                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3542                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3543         } else {
3544                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3545                 for_each_intel_encoder(dev, intel_encoder)
3546                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3547                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3548         }
3549
3550         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3551
3552         /*
3553          * Enable digital hotplug on the PCH, and configure the DP short pulse
3554          * duration to 2ms (which is the minimum in the Display Port spec)
3555          *
3556          * This register is the same on all known PCH chips.
3557          */
3558         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3559         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3560         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3561         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3562         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3563         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3564 }
3565
3566 static void ibx_irq_postinstall(struct drm_device *dev)
3567 {
3568         struct drm_i915_private *dev_priv = dev->dev_private;
3569         u32 mask;
3570
3571         if (HAS_PCH_NOP(dev))
3572                 return;
3573
3574         if (HAS_PCH_IBX(dev))
3575                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3576         else
3577                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3578
3579         GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3580         I915_WRITE(SDEIMR, ~mask);
3581 }
3582
3583 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3584 {
3585         struct drm_i915_private *dev_priv = dev->dev_private;
3586         u32 pm_irqs, gt_irqs;
3587
3588         pm_irqs = gt_irqs = 0;
3589
3590         dev_priv->gt_irq_mask = ~0;
3591         if (HAS_L3_DPF(dev)) {
3592                 /* L3 parity interrupt is always unmasked. */
3593                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3594                 gt_irqs |= GT_PARITY_ERROR(dev);
3595         }
3596
3597         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3598         if (IS_GEN5(dev)) {
3599                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3600                            ILK_BSD_USER_INTERRUPT;
3601         } else {
3602                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3603         }
3604
3605         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3606
3607         if (INTEL_INFO(dev)->gen >= 6) {
3608                 pm_irqs |= dev_priv->pm_rps_events;
3609
3610                 if (HAS_VEBOX(dev))
3611                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3612
3613                 dev_priv->pm_irq_mask = 0xffffffff;
3614                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3615         }
3616 }
3617
3618 static int ironlake_irq_postinstall(struct drm_device *dev)
3619 {
3620         unsigned long irqflags;
3621         struct drm_i915_private *dev_priv = dev->dev_private;
3622         u32 display_mask, extra_mask;
3623
3624         if (INTEL_INFO(dev)->gen >= 7) {
3625                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3626                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3627                                 DE_PLANEB_FLIP_DONE_IVB |
3628                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3629                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3630                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3631         } else {
3632                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3633                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3634                                 DE_AUX_CHANNEL_A |
3635                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3636                                 DE_POISON);
3637                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3638                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3639         }
3640
3641         dev_priv->irq_mask = ~display_mask;
3642
3643         I915_WRITE(HWSTAM, 0xeffe);
3644
3645         ibx_irq_pre_postinstall(dev);
3646
3647         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3648
3649         gen5_gt_irq_postinstall(dev);
3650
3651         ibx_irq_postinstall(dev);
3652
3653         if (IS_IRONLAKE_M(dev)) {
3654                 /* Enable PCU event interrupts
3655                  *
3656                  * spinlocking not required here for correctness since interrupt
3657                  * setup is guaranteed to run in single-threaded context. But we
3658                  * need it to make the assert_spin_locked happy. */
3659                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3660                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3661                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3662         }
3663
3664         return 0;
3665 }
3666
3667 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3668 {
3669         u32 pipestat_mask;
3670         u32 iir_mask;
3671
3672         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3673                         PIPE_FIFO_UNDERRUN_STATUS;
3674
3675         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3676         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3677         POSTING_READ(PIPESTAT(PIPE_A));
3678
3679         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3680                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3681
3682         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3683                                                PIPE_GMBUS_INTERRUPT_STATUS);
3684         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3685
3686         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3687                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3688                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3689         dev_priv->irq_mask &= ~iir_mask;
3690
3691         I915_WRITE(VLV_IIR, iir_mask);
3692         I915_WRITE(VLV_IIR, iir_mask);
3693         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3694         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3695         POSTING_READ(VLV_IER);
3696 }
3697
3698 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3699 {
3700         u32 pipestat_mask;
3701         u32 iir_mask;
3702
3703         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3704                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3705                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3706
3707         dev_priv->irq_mask |= iir_mask;
3708         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3709         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3710         I915_WRITE(VLV_IIR, iir_mask);
3711         I915_WRITE(VLV_IIR, iir_mask);
3712         POSTING_READ(VLV_IIR);
3713
3714         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3715                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3716
3717         i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3718                                                 PIPE_GMBUS_INTERRUPT_STATUS);
3719         i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3720
3721         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3722                         PIPE_FIFO_UNDERRUN_STATUS;
3723         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3724         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3725         POSTING_READ(PIPESTAT(PIPE_A));
3726 }
3727
3728 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3729 {
3730         assert_spin_locked(&dev_priv->irq_lock);
3731
3732         if (dev_priv->display_irqs_enabled)
3733                 return;
3734
3735         dev_priv->display_irqs_enabled = true;
3736
3737         if (dev_priv->dev->irq_enabled)
3738                 valleyview_display_irqs_install(dev_priv);
3739 }
3740
3741 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3742 {
3743         assert_spin_locked(&dev_priv->irq_lock);
3744
3745         if (!dev_priv->display_irqs_enabled)
3746                 return;
3747
3748         dev_priv->display_irqs_enabled = false;
3749
3750         if (dev_priv->dev->irq_enabled)
3751                 valleyview_display_irqs_uninstall(dev_priv);
3752 }
3753
3754 static int valleyview_irq_postinstall(struct drm_device *dev)
3755 {
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757         unsigned long irqflags;
3758
3759         dev_priv->irq_mask = ~0;
3760
3761         I915_WRITE(PORT_HOTPLUG_EN, 0);
3762         POSTING_READ(PORT_HOTPLUG_EN);
3763
3764         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3765         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3766         I915_WRITE(VLV_IIR, 0xffffffff);
3767         POSTING_READ(VLV_IER);
3768
3769         /* Interrupt setup is already guaranteed to be single-threaded, this is
3770          * just to make the assert_spin_locked check happy. */
3771         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3772         if (dev_priv->display_irqs_enabled)
3773                 valleyview_display_irqs_install(dev_priv);
3774         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3775
3776         I915_WRITE(VLV_IIR, 0xffffffff);
3777         I915_WRITE(VLV_IIR, 0xffffffff);
3778
3779         gen5_gt_irq_postinstall(dev);
3780
3781         /* ack & enable invalid PTE error interrupts */
3782 #if 0 /* FIXME: add support to irq handler for checking these bits */
3783         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3784         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3785 #endif
3786
3787         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3788
3789         return 0;
3790 }
3791
3792 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3793 {
3794         int i;
3795
3796         /* These are interrupts we'll toggle with the ring mask register */
3797         uint32_t gt_interrupts[] = {
3798                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3799                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3800                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3801                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3802                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3803                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3804                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3805                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3806                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3807                 0,
3808                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3809                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3810                 };
3811
3812         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3813                 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3814
3815         dev_priv->pm_irq_mask = 0xffffffff;
3816 }
3817
3818 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3819 {
3820         struct drm_device *dev = dev_priv->dev;
3821         uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
3822                 GEN8_PIPE_CDCLK_CRC_DONE |
3823                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3824         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3825                 GEN8_PIPE_FIFO_UNDERRUN;
3826         int pipe;
3827         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3828         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3829         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3830
3831         for_each_pipe(pipe)
3832                 if (intel_display_power_enabled(dev_priv,
3833                                 POWER_DOMAIN_PIPE(pipe)))
3834                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3835                                           dev_priv->de_irq_mask[pipe],
3836                                           de_pipe_enables);
3837
3838         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3839 }
3840
3841 static int gen8_irq_postinstall(struct drm_device *dev)
3842 {
3843         struct drm_i915_private *dev_priv = dev->dev_private;
3844
3845         ibx_irq_pre_postinstall(dev);
3846
3847         gen8_gt_irq_postinstall(dev_priv);
3848         gen8_de_irq_postinstall(dev_priv);
3849
3850         ibx_irq_postinstall(dev);
3851
3852         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3853         POSTING_READ(GEN8_MASTER_IRQ);
3854
3855         return 0;
3856 }
3857
3858 static int cherryview_irq_postinstall(struct drm_device *dev)
3859 {
3860         struct drm_i915_private *dev_priv = dev->dev_private;
3861         u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3862                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3863                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3864                 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3865         u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3866                 PIPE_CRC_DONE_INTERRUPT_STATUS;
3867         unsigned long irqflags;
3868         int pipe;
3869
3870         /*
3871          * Leave vblank interrupts masked initially.  enable/disable will
3872          * toggle them based on usage.
3873          */
3874         dev_priv->irq_mask = ~enable_mask;
3875
3876         for_each_pipe(pipe)
3877                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3878
3879         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3880         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3881         for_each_pipe(pipe)
3882                 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3883         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3884
3885         I915_WRITE(VLV_IIR, 0xffffffff);
3886         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3887         I915_WRITE(VLV_IER, enable_mask);
3888
3889         gen8_gt_irq_postinstall(dev_priv);
3890
3891         I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3892         POSTING_READ(GEN8_MASTER_IRQ);
3893
3894         return 0;
3895 }
3896
3897 static void gen8_irq_uninstall(struct drm_device *dev)
3898 {
3899         struct drm_i915_private *dev_priv = dev->dev_private;
3900
3901         if (!dev_priv)
3902                 return;
3903
3904         intel_hpd_irq_uninstall(dev_priv);
3905
3906         gen8_irq_reset(dev);
3907 }
3908
3909 static void valleyview_irq_uninstall(struct drm_device *dev)
3910 {
3911         struct drm_i915_private *dev_priv = dev->dev_private;
3912         unsigned long irqflags;
3913         int pipe;
3914
3915         if (!dev_priv)
3916                 return;
3917
3918         I915_WRITE(VLV_MASTER_IER, 0);
3919
3920         intel_hpd_irq_uninstall(dev_priv);
3921
3922         for_each_pipe(pipe)
3923                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3924
3925         I915_WRITE(HWSTAM, 0xffffffff);
3926         I915_WRITE(PORT_HOTPLUG_EN, 0);
3927         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3928
3929         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3930         if (dev_priv->display_irqs_enabled)
3931                 valleyview_display_irqs_uninstall(dev_priv);
3932         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3933
3934         dev_priv->irq_mask = 0;
3935
3936         I915_WRITE(VLV_IIR, 0xffffffff);
3937         I915_WRITE(VLV_IMR, 0xffffffff);
3938         I915_WRITE(VLV_IER, 0x0);
3939         POSTING_READ(VLV_IER);
3940 }
3941
3942 static void cherryview_irq_uninstall(struct drm_device *dev)
3943 {
3944         struct drm_i915_private *dev_priv = dev->dev_private;
3945         int pipe;
3946
3947         if (!dev_priv)
3948                 return;
3949
3950         I915_WRITE(GEN8_MASTER_IRQ, 0);
3951         POSTING_READ(GEN8_MASTER_IRQ);
3952
3953 #define GEN8_IRQ_FINI_NDX(type, which)                          \
3954 do {                                                            \
3955         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);       \
3956         I915_WRITE(GEN8_##type##_IER(which), 0);                \
3957         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);       \
3958         POSTING_READ(GEN8_##type##_IIR(which));                 \
3959         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);       \
3960 } while (0)
3961
3962 #define GEN8_IRQ_FINI(type)                             \
3963 do {                                                    \
3964         I915_WRITE(GEN8_##type##_IMR, 0xffffffff);      \
3965         I915_WRITE(GEN8_##type##_IER, 0);               \
3966         I915_WRITE(GEN8_##type##_IIR, 0xffffffff);      \
3967         POSTING_READ(GEN8_##type##_IIR);                \
3968         I915_WRITE(GEN8_##type##_IIR, 0xffffffff);      \
3969 } while (0)
3970
3971         GEN8_IRQ_FINI_NDX(GT, 0);
3972         GEN8_IRQ_FINI_NDX(GT, 1);
3973         GEN8_IRQ_FINI_NDX(GT, 2);
3974         GEN8_IRQ_FINI_NDX(GT, 3);
3975
3976         GEN8_IRQ_FINI(PCU);
3977
3978 #undef GEN8_IRQ_FINI
3979 #undef GEN8_IRQ_FINI_NDX
3980
3981         I915_WRITE(PORT_HOTPLUG_EN, 0);
3982         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3983
3984         for_each_pipe(pipe)
3985                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3986
3987         I915_WRITE(VLV_IMR, 0xffffffff);
3988         I915_WRITE(VLV_IER, 0x0);
3989         I915_WRITE(VLV_IIR, 0xffffffff);
3990         POSTING_READ(VLV_IIR);
3991 }
3992
3993 static void ironlake_irq_uninstall(struct drm_device *dev)
3994 {
3995         struct drm_i915_private *dev_priv = dev->dev_private;
3996
3997         if (!dev_priv)
3998                 return;
3999
4000         intel_hpd_irq_uninstall(dev_priv);
4001
4002         ironlake_irq_reset(dev);
4003 }
4004
4005 static void i8xx_irq_preinstall(struct drm_device * dev)
4006 {
4007         struct drm_i915_private *dev_priv = dev->dev_private;
4008         int pipe;
4009
4010         for_each_pipe(pipe)
4011                 I915_WRITE(PIPESTAT(pipe), 0);
4012         I915_WRITE16(IMR, 0xffff);
4013         I915_WRITE16(IER, 0x0);
4014         POSTING_READ16(IER);
4015 }
4016
4017 static int i8xx_irq_postinstall(struct drm_device *dev)
4018 {
4019         struct drm_i915_private *dev_priv = dev->dev_private;
4020         unsigned long irqflags;
4021
4022         I915_WRITE16(EMR,
4023                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4024
4025         /* Unmask the interrupts that we always want on. */
4026         dev_priv->irq_mask =
4027                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4028                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4029                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4030                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4031                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4032         I915_WRITE16(IMR, dev_priv->irq_mask);
4033
4034         I915_WRITE16(IER,
4035                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4036                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4037                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
4038                      I915_USER_INTERRUPT);
4039         POSTING_READ16(IER);
4040
4041         /* Interrupt setup is already guaranteed to be single-threaded, this is
4042          * just to make the assert_spin_locked check happy. */
4043         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4044         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4045         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4046         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4047
4048         return 0;
4049 }
4050
4051 /*
4052  * Returns true when a page flip has completed.
4053  */
4054 static bool i8xx_handle_vblank(struct drm_device *dev,
4055                                int plane, int pipe, u32 iir)
4056 {
4057         struct drm_i915_private *dev_priv = dev->dev_private;
4058         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4059
4060         if (!intel_pipe_handle_vblank(dev, pipe))
4061                 return false;
4062
4063         if ((iir & flip_pending) == 0)
4064                 return false;
4065
4066         intel_prepare_page_flip(dev, plane);
4067
4068         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4069          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4070          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4071          * the flip is completed (no longer pending). Since this doesn't raise
4072          * an interrupt per se, we watch for the change at vblank.
4073          */
4074         if (I915_READ16(ISR) & flip_pending)
4075                 return false;
4076
4077         intel_finish_page_flip(dev, pipe);
4078
4079         return true;
4080 }
4081
4082 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4083 {
4084         struct drm_device *dev = arg;
4085         struct drm_i915_private *dev_priv = dev->dev_private;
4086         u16 iir, new_iir;
4087         u32 pipe_stats[2];
4088         unsigned long irqflags;
4089         int pipe;
4090         u16 flip_mask =
4091                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4092                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4093
4094         iir = I915_READ16(IIR);
4095         if (iir == 0)
4096                 return IRQ_NONE;
4097
4098         while (iir & ~flip_mask) {
4099                 /* Can't rely on pipestat interrupt bit in iir as it might
4100                  * have been cleared after the pipestat interrupt was received.
4101                  * It doesn't set the bit in iir again, but it still produces
4102                  * interrupts (for non-MSI).
4103                  */
4104                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4105                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4106                         i915_handle_error(dev, false,
4107                                           "Command parser error, iir 0x%08x",
4108                                           iir);
4109
4110                 for_each_pipe(pipe) {
4111                         int reg = PIPESTAT(pipe);
4112                         pipe_stats[pipe] = I915_READ(reg);
4113
4114                         /*
4115                          * Clear the PIPE*STAT regs before the IIR
4116                          */
4117                         if (pipe_stats[pipe] & 0x8000ffff)
4118                                 I915_WRITE(reg, pipe_stats[pipe]);
4119                 }
4120                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4121
4122                 I915_WRITE16(IIR, iir & ~flip_mask);
4123                 new_iir = I915_READ16(IIR); /* Flush posted writes */
4124
4125                 i915_update_dri1_breadcrumb(dev);
4126
4127                 if (iir & I915_USER_INTERRUPT)
4128                         notify_ring(dev, &dev_priv->ring[RCS]);
4129
4130                 for_each_pipe(pipe) {
4131                         int plane = pipe;
4132                         if (HAS_FBC(dev))
4133                                 plane = !plane;
4134
4135                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4136                             i8xx_handle_vblank(dev, plane, pipe, iir))
4137                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4138
4139                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4140                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4141
4142                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4143                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4144                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4145                 }
4146
4147                 iir = new_iir;
4148         }
4149
4150         return IRQ_HANDLED;
4151 }
4152
4153 static void i8xx_irq_uninstall(struct drm_device * dev)
4154 {
4155         struct drm_i915_private *dev_priv = dev->dev_private;
4156         int pipe;
4157
4158         for_each_pipe(pipe) {
4159                 /* Clear enable bits; then clear status bits */
4160                 I915_WRITE(PIPESTAT(pipe), 0);
4161                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4162         }
4163         I915_WRITE16(IMR, 0xffff);
4164         I915_WRITE16(IER, 0x0);
4165         I915_WRITE16(IIR, I915_READ16(IIR));
4166 }
4167
4168 static void i915_irq_preinstall(struct drm_device * dev)
4169 {
4170         struct drm_i915_private *dev_priv = dev->dev_private;
4171         int pipe;
4172
4173         if (I915_HAS_HOTPLUG(dev)) {
4174                 I915_WRITE(PORT_HOTPLUG_EN, 0);
4175                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4176         }
4177
4178         I915_WRITE16(HWSTAM, 0xeffe);
4179         for_each_pipe(pipe)
4180                 I915_WRITE(PIPESTAT(pipe), 0);
4181         I915_WRITE(IMR, 0xffffffff);
4182         I915_WRITE(IER, 0x0);
4183         POSTING_READ(IER);
4184 }
4185
4186 static int i915_irq_postinstall(struct drm_device *dev)
4187 {
4188         struct drm_i915_private *dev_priv = dev->dev_private;
4189         u32 enable_mask;
4190         unsigned long irqflags;
4191
4192         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4193
4194         /* Unmask the interrupts that we always want on. */
4195         dev_priv->irq_mask =
4196                 ~(I915_ASLE_INTERRUPT |
4197                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4198                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4199                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4200                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4201                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4202
4203         enable_mask =
4204                 I915_ASLE_INTERRUPT |
4205                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4206                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4207                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
4208                 I915_USER_INTERRUPT;
4209
4210         if (I915_HAS_HOTPLUG(dev)) {
4211                 I915_WRITE(PORT_HOTPLUG_EN, 0);
4212                 POSTING_READ(PORT_HOTPLUG_EN);
4213
4214                 /* Enable in IER... */
4215                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4216                 /* and unmask in IMR */
4217                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4218         }
4219
4220         I915_WRITE(IMR, dev_priv->irq_mask);
4221         I915_WRITE(IER, enable_mask);
4222         POSTING_READ(IER);
4223
4224         i915_enable_asle_pipestat(dev);
4225
4226         /* Interrupt setup is already guaranteed to be single-threaded, this is
4227          * just to make the assert_spin_locked check happy. */
4228         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4229         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4230         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4231         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4232
4233         return 0;
4234 }
4235
4236 /*
4237  * Returns true when a page flip has completed.
4238  */
4239 static bool i915_handle_vblank(struct drm_device *dev,
4240                                int plane, int pipe, u32 iir)
4241 {
4242         struct drm_i915_private *dev_priv = dev->dev_private;
4243         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4244
4245         if (!intel_pipe_handle_vblank(dev, pipe))
4246                 return false;
4247
4248         if ((iir & flip_pending) == 0)
4249                 return false;
4250
4251         intel_prepare_page_flip(dev, plane);
4252
4253         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4254          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4255          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4256          * the flip is completed (no longer pending). Since this doesn't raise
4257          * an interrupt per se, we watch for the change at vblank.
4258          */
4259         if (I915_READ(ISR) & flip_pending)
4260                 return false;
4261
4262         intel_finish_page_flip(dev, pipe);
4263
4264         return true;
4265 }
4266
4267 static irqreturn_t i915_irq_handler(int irq, void *arg)
4268 {
4269         struct drm_device *dev = arg;
4270         struct drm_i915_private *dev_priv = dev->dev_private;
4271         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4272         unsigned long irqflags;
4273         u32 flip_mask =
4274                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4275                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4276         int pipe, ret = IRQ_NONE;
4277
4278         iir = I915_READ(IIR);
4279         do {
4280                 bool irq_received = (iir & ~flip_mask) != 0;
4281                 bool blc_event = false;
4282
4283                 /* Can't rely on pipestat interrupt bit in iir as it might
4284                  * have been cleared after the pipestat interrupt was received.
4285                  * It doesn't set the bit in iir again, but it still produces
4286                  * interrupts (for non-MSI).
4287                  */
4288                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4289                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4290                         i915_handle_error(dev, false,
4291                                           "Command parser error, iir 0x%08x",
4292                                           iir);
4293
4294                 for_each_pipe(pipe) {
4295                         int reg = PIPESTAT(pipe);
4296                         pipe_stats[pipe] = I915_READ(reg);
4297
4298                         /* Clear the PIPE*STAT regs before the IIR */
4299                         if (pipe_stats[pipe] & 0x8000ffff) {
4300                                 I915_WRITE(reg, pipe_stats[pipe]);
4301                                 irq_received = true;
4302                         }
4303                 }
4304                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4305
4306                 if (!irq_received)
4307                         break;
4308
4309                 /* Consume port.  Then clear IIR or we'll miss events */
4310                 if (I915_HAS_HOTPLUG(dev) &&
4311                     iir & I915_DISPLAY_PORT_INTERRUPT)
4312                         i9xx_hpd_irq_handler(dev);
4313
4314                 I915_WRITE(IIR, iir & ~flip_mask);
4315                 new_iir = I915_READ(IIR); /* Flush posted writes */
4316
4317                 if (iir & I915_USER_INTERRUPT)
4318                         notify_ring(dev, &dev_priv->ring[RCS]);
4319
4320                 for_each_pipe(pipe) {
4321                         int plane = pipe;
4322                         if (HAS_FBC(dev))
4323                                 plane = !plane;
4324
4325                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4326                             i915_handle_vblank(dev, plane, pipe, iir))
4327                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4328
4329                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4330                                 blc_event = true;
4331
4332                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4333                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4334
4335                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4336                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4337                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4338                 }
4339
4340                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4341                         intel_opregion_asle_intr(dev);
4342
4343                 /* With MSI, interrupts are only generated when iir
4344                  * transitions from zero to nonzero.  If another bit got
4345                  * set while we were handling the existing iir bits, then
4346                  * we would never get another interrupt.
4347                  *
4348                  * This is fine on non-MSI as well, as if we hit this path
4349                  * we avoid exiting the interrupt handler only to generate
4350                  * another one.
4351                  *
4352                  * Note that for MSI this could cause a stray interrupt report
4353                  * if an interrupt landed in the time between writing IIR and
4354                  * the posting read.  This should be rare enough to never
4355                  * trigger the 99% of 100,000 interrupts test for disabling
4356                  * stray interrupts.
4357                  */
4358                 ret = IRQ_HANDLED;
4359                 iir = new_iir;
4360         } while (iir & ~flip_mask);
4361
4362         i915_update_dri1_breadcrumb(dev);
4363
4364         return ret;
4365 }
4366
4367 static void i915_irq_uninstall(struct drm_device * dev)
4368 {
4369         struct drm_i915_private *dev_priv = dev->dev_private;
4370         int pipe;
4371
4372         intel_hpd_irq_uninstall(dev_priv);
4373
4374         if (I915_HAS_HOTPLUG(dev)) {
4375                 I915_WRITE(PORT_HOTPLUG_EN, 0);
4376                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4377         }
4378
4379         I915_WRITE16(HWSTAM, 0xffff);
4380         for_each_pipe(pipe) {
4381                 /* Clear enable bits; then clear status bits */
4382                 I915_WRITE(PIPESTAT(pipe), 0);
4383                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4384         }
4385         I915_WRITE(IMR, 0xffffffff);
4386         I915_WRITE(IER, 0x0);
4387
4388         I915_WRITE(IIR, I915_READ(IIR));
4389 }
4390
4391 static void i965_irq_preinstall(struct drm_device * dev)
4392 {
4393         struct drm_i915_private *dev_priv = dev->dev_private;
4394         int pipe;
4395
4396         I915_WRITE(PORT_HOTPLUG_EN, 0);
4397         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4398
4399         I915_WRITE(HWSTAM, 0xeffe);
4400         for_each_pipe(pipe)
4401                 I915_WRITE(PIPESTAT(pipe), 0);
4402         I915_WRITE(IMR, 0xffffffff);
4403         I915_WRITE(IER, 0x0);
4404         POSTING_READ(IER);
4405 }
4406
4407 static int i965_irq_postinstall(struct drm_device *dev)
4408 {
4409         struct drm_i915_private *dev_priv = dev->dev_private;
4410         u32 enable_mask;
4411         u32 error_mask;
4412         unsigned long irqflags;
4413
4414         /* Unmask the interrupts that we always want on. */
4415         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4416                                I915_DISPLAY_PORT_INTERRUPT |
4417                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4418                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4419                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4420                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4421                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4422
4423         enable_mask = ~dev_priv->irq_mask;
4424         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4425                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4426         enable_mask |= I915_USER_INTERRUPT;
4427
4428         if (IS_G4X(dev))
4429                 enable_mask |= I915_BSD_USER_INTERRUPT;
4430
4431         /* Interrupt setup is already guaranteed to be single-threaded, this is
4432          * just to make the assert_spin_locked check happy. */
4433         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4434         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4435         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4436         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4437         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4438
4439         /*
4440          * Enable some error detection, note the instruction error mask
4441          * bit is reserved, so we leave it masked.
4442          */
4443         if (IS_G4X(dev)) {
4444                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4445                                GM45_ERROR_MEM_PRIV |
4446                                GM45_ERROR_CP_PRIV |
4447                                I915_ERROR_MEMORY_REFRESH);
4448         } else {
4449                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4450                                I915_ERROR_MEMORY_REFRESH);
4451         }
4452         I915_WRITE(EMR, error_mask);
4453
4454         I915_WRITE(IMR, dev_priv->irq_mask);
4455         I915_WRITE(IER, enable_mask);
4456         POSTING_READ(IER);
4457
4458         I915_WRITE(PORT_HOTPLUG_EN, 0);
4459         POSTING_READ(PORT_HOTPLUG_EN);
4460
4461         i915_enable_asle_pipestat(dev);
4462
4463         return 0;
4464 }
4465
4466 static void i915_hpd_irq_setup(struct drm_device *dev)
4467 {
4468         struct drm_i915_private *dev_priv = dev->dev_private;
4469         struct intel_encoder *intel_encoder;
4470         u32 hotplug_en;
4471
4472         assert_spin_locked(&dev_priv->irq_lock);
4473
4474         if (I915_HAS_HOTPLUG(dev)) {
4475                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4476                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4477                 /* Note HDMI and DP share hotplug bits */
4478                 /* enable bits are the same for all generations */
4479                 for_each_intel_encoder(dev, intel_encoder)
4480                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4481                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4482                 /* Programming the CRT detection parameters tends
4483                    to generate a spurious hotplug event about three
4484                    seconds later.  So just do it once.
4485                 */
4486                 if (IS_G4X(dev))
4487                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4488                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4489                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4490
4491                 /* Ignore TV since it's buggy */
4492                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4493         }
4494 }
4495
4496 static irqreturn_t i965_irq_handler(int irq, void *arg)
4497 {
4498         struct drm_device *dev = arg;
4499         struct drm_i915_private *dev_priv = dev->dev_private;
4500         u32 iir, new_iir;
4501         u32 pipe_stats[I915_MAX_PIPES];
4502         unsigned long irqflags;
4503         int ret = IRQ_NONE, pipe;
4504         u32 flip_mask =
4505                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4506                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4507
4508         iir = I915_READ(IIR);
4509
4510         for (;;) {
4511                 bool irq_received = (iir & ~flip_mask) != 0;
4512                 bool blc_event = false;
4513
4514                 /* Can't rely on pipestat interrupt bit in iir as it might
4515                  * have been cleared after the pipestat interrupt was received.
4516                  * It doesn't set the bit in iir again, but it still produces
4517                  * interrupts (for non-MSI).
4518                  */
4519                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4520                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4521                         i915_handle_error(dev, false,
4522                                           "Command parser error, iir 0x%08x",
4523                                           iir);
4524
4525                 for_each_pipe(pipe) {
4526                         int reg = PIPESTAT(pipe);
4527                         pipe_stats[pipe] = I915_READ(reg);
4528
4529                         /*
4530                          * Clear the PIPE*STAT regs before the IIR
4531                          */
4532                         if (pipe_stats[pipe] & 0x8000ffff) {
4533                                 I915_WRITE(reg, pipe_stats[pipe]);
4534                                 irq_received = true;
4535                         }
4536                 }
4537                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4538
4539                 if (!irq_received)
4540                         break;
4541
4542                 ret = IRQ_HANDLED;
4543
4544                 /* Consume port.  Then clear IIR or we'll miss events */
4545                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4546                         i9xx_hpd_irq_handler(dev);
4547
4548                 I915_WRITE(IIR, iir & ~flip_mask);
4549                 new_iir = I915_READ(IIR); /* Flush posted writes */
4550
4551                 if (iir & I915_USER_INTERRUPT)
4552                         notify_ring(dev, &dev_priv->ring[RCS]);
4553                 if (iir & I915_BSD_USER_INTERRUPT)
4554                         notify_ring(dev, &dev_priv->ring[VCS]);
4555
4556                 for_each_pipe(pipe) {
4557                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4558                             i915_handle_vblank(dev, pipe, pipe, iir))
4559                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4560
4561                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4562                                 blc_event = true;
4563
4564                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4565                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4566
4567                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4568                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4569                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4570                 }
4571
4572                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4573                         intel_opregion_asle_intr(dev);
4574
4575                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4576                         gmbus_irq_handler(dev);
4577
4578                 /* With MSI, interrupts are only generated when iir
4579                  * transitions from zero to nonzero.  If another bit got
4580                  * set while we were handling the existing iir bits, then
4581                  * we would never get another interrupt.
4582                  *
4583                  * This is fine on non-MSI as well, as if we hit this path
4584                  * we avoid exiting the interrupt handler only to generate
4585                  * another one.
4586                  *
4587                  * Note that for MSI this could cause a stray interrupt report
4588                  * if an interrupt landed in the time between writing IIR and
4589                  * the posting read.  This should be rare enough to never
4590                  * trigger the 99% of 100,000 interrupts test for disabling
4591                  * stray interrupts.
4592                  */
4593                 iir = new_iir;
4594         }
4595
4596         i915_update_dri1_breadcrumb(dev);
4597
4598         return ret;
4599 }
4600
4601 static void i965_irq_uninstall(struct drm_device * dev)
4602 {
4603         struct drm_i915_private *dev_priv = dev->dev_private;
4604         int pipe;
4605
4606         if (!dev_priv)
4607                 return;
4608
4609         intel_hpd_irq_uninstall(dev_priv);
4610
4611         I915_WRITE(PORT_HOTPLUG_EN, 0);
4612         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4613
4614         I915_WRITE(HWSTAM, 0xffffffff);
4615         for_each_pipe(pipe)
4616                 I915_WRITE(PIPESTAT(pipe), 0);
4617         I915_WRITE(IMR, 0xffffffff);
4618         I915_WRITE(IER, 0x0);
4619
4620         for_each_pipe(pipe)
4621                 I915_WRITE(PIPESTAT(pipe),
4622                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4623         I915_WRITE(IIR, I915_READ(IIR));
4624 }
4625
4626 static void intel_hpd_irq_reenable(unsigned long data)
4627 {
4628         struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
4629         struct drm_device *dev = dev_priv->dev;
4630         struct drm_mode_config *mode_config = &dev->mode_config;
4631         unsigned long irqflags;
4632         int i;
4633
4634         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4635         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4636                 struct drm_connector *connector;
4637
4638                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4639                         continue;
4640
4641                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4642
4643                 list_for_each_entry(connector, &mode_config->connector_list, head) {
4644                         struct intel_connector *intel_connector = to_intel_connector(connector);
4645
4646                         if (intel_connector->encoder->hpd_pin == i) {
4647                                 if (connector->polled != intel_connector->polled)
4648                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4649                                                          connector->name);
4650                                 connector->polled = intel_connector->polled;
4651                                 if (!connector->polled)
4652                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4653                         }
4654                 }
4655         }
4656         if (dev_priv->display.hpd_irq_setup)
4657                 dev_priv->display.hpd_irq_setup(dev);
4658         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4659 }
4660
4661 void intel_irq_init(struct drm_device *dev)
4662 {
4663         struct drm_i915_private *dev_priv = dev->dev_private;
4664
4665         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4666         INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4667         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4668         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4669         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4670
4671         /* Let's track the enabled rps events */
4672         if (IS_VALLEYVIEW(dev))
4673                 /* WaGsvRC0ResidenncyMethod:VLV */
4674                 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4675         else
4676                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4677
4678         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4679                     i915_hangcheck_elapsed,
4680                     (unsigned long) dev);
4681         setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4682                     (unsigned long) dev_priv);
4683
4684         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4685
4686         /* Haven't installed the IRQ handler yet */
4687         dev_priv->pm._irqs_disabled = true;
4688
4689         if (IS_GEN2(dev)) {
4690                 dev->max_vblank_count = 0;
4691                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4692         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4693                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4694                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4695         } else {
4696                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4697                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4698         }
4699
4700         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4701                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4702                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4703         }
4704
4705         if (IS_CHERRYVIEW(dev)) {
4706                 dev->driver->irq_handler = cherryview_irq_handler;
4707                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4708                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4709                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4710                 dev->driver->enable_vblank = valleyview_enable_vblank;
4711                 dev->driver->disable_vblank = valleyview_disable_vblank;
4712                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4713         } else if (IS_VALLEYVIEW(dev)) {
4714                 dev->driver->irq_handler = valleyview_irq_handler;
4715                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4716                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4717                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4718                 dev->driver->enable_vblank = valleyview_enable_vblank;
4719                 dev->driver->disable_vblank = valleyview_disable_vblank;
4720                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4721         } else if (IS_GEN8(dev)) {
4722                 dev->driver->irq_handler = gen8_irq_handler;
4723                 dev->driver->irq_preinstall = gen8_irq_reset;
4724                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4725                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4726                 dev->driver->enable_vblank = gen8_enable_vblank;
4727                 dev->driver->disable_vblank = gen8_disable_vblank;
4728                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4729         } else if (HAS_PCH_SPLIT(dev)) {
4730                 dev->driver->irq_handler = ironlake_irq_handler;
4731                 dev->driver->irq_preinstall = ironlake_irq_reset;
4732                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4733                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4734                 dev->driver->enable_vblank = ironlake_enable_vblank;
4735                 dev->driver->disable_vblank = ironlake_disable_vblank;
4736                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4737         } else {
4738                 if (INTEL_INFO(dev)->gen == 2) {
4739                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4740                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4741                         dev->driver->irq_handler = i8xx_irq_handler;
4742                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4743                 } else if (INTEL_INFO(dev)->gen == 3) {
4744                         dev->driver->irq_preinstall = i915_irq_preinstall;
4745                         dev->driver->irq_postinstall = i915_irq_postinstall;
4746                         dev->driver->irq_uninstall = i915_irq_uninstall;
4747                         dev->driver->irq_handler = i915_irq_handler;
4748                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4749                 } else {
4750                         dev->driver->irq_preinstall = i965_irq_preinstall;
4751                         dev->driver->irq_postinstall = i965_irq_postinstall;
4752                         dev->driver->irq_uninstall = i965_irq_uninstall;
4753                         dev->driver->irq_handler = i965_irq_handler;
4754                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4755                 }
4756                 dev->driver->enable_vblank = i915_enable_vblank;
4757                 dev->driver->disable_vblank = i915_disable_vblank;
4758         }
4759 }
4760
4761 void intel_hpd_init(struct drm_device *dev)
4762 {
4763         struct drm_i915_private *dev_priv = dev->dev_private;
4764         struct drm_mode_config *mode_config = &dev->mode_config;
4765         struct drm_connector *connector;
4766         unsigned long irqflags;
4767         int i;
4768
4769         for (i = 1; i < HPD_NUM_PINS; i++) {
4770                 dev_priv->hpd_stats[i].hpd_cnt = 0;
4771                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4772         }
4773         list_for_each_entry(connector, &mode_config->connector_list, head) {
4774                 struct intel_connector *intel_connector = to_intel_connector(connector);
4775                 connector->polled = intel_connector->polled;
4776                 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4777                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4778                 if (intel_connector->mst_port)
4779                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4780         }
4781
4782         /* Interrupt setup is already guaranteed to be single-threaded, this is
4783          * just to make the assert_spin_locked checks happy. */
4784         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4785         if (dev_priv->display.hpd_irq_setup)
4786                 dev_priv->display.hpd_irq_setup(dev);
4787         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4788 }
4789
4790 /* Disable interrupts so we can allow runtime PM. */
4791 void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
4792 {
4793         struct drm_i915_private *dev_priv = dev->dev_private;
4794
4795         dev->driver->irq_uninstall(dev);
4796         dev_priv->pm._irqs_disabled = true;
4797 }
4798
4799 /* Restore interrupts so we can recover from runtime PM. */
4800 void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
4801 {
4802         struct drm_i915_private *dev_priv = dev->dev_private;
4803
4804         dev_priv->pm._irqs_disabled = false;
4805         dev->driver->irq_preinstall(dev);
4806         dev->driver->irq_postinstall(dev);
4807 }