1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt[HPD_NUM_PINS] = {
77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
143 u32 val = I915_READ(reg); \
145 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
147 I915_WRITE((reg), 0xffffffff); \
149 I915_WRITE((reg), 0xffffffff); \
154 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
155 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
156 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
157 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
158 POSTING_READ(GEN8_##type##_IMR(which)); \
161 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
162 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
163 I915_WRITE(type##IER, (ier_val)); \
164 I915_WRITE(type##IMR, (imr_val)); \
165 POSTING_READ(type##IMR); \
168 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
170 /* For display hotplug interrupt */
172 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
178 assert_spin_locked(&dev_priv->irq_lock);
179 WARN_ON(bits & ~mask);
181 val = I915_READ(PORT_HOTPLUG_EN);
184 I915_WRITE(PORT_HOTPLUG_EN, val);
188 * i915_hotplug_interrupt_update - update hotplug interrupt enable
189 * @dev_priv: driver private
190 * @mask: bits to update
191 * @bits: bits to enable
192 * NOTE: the HPD enable bits are modified both inside and outside
193 * of an interrupt context. To avoid that read-modify-write cycles
194 * interfer, these bits are protected by a spinlock. Since this
195 * function is usually not called from a context where the lock is
196 * held already, this function acquires the lock itself. A non-locking
197 * version is also available.
199 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
203 spin_lock_irq(&dev_priv->irq_lock);
204 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
205 spin_unlock_irq(&dev_priv->irq_lock);
209 * ilk_update_display_irq - update DEIMR
210 * @dev_priv: driver private
211 * @interrupt_mask: mask of interrupt bits to update
212 * @enabled_irq_mask: mask of interrupt bits to enable
214 static void ilk_update_display_irq(struct drm_i915_private *dev_priv,
215 uint32_t interrupt_mask,
216 uint32_t enabled_irq_mask)
220 assert_spin_locked(&dev_priv->irq_lock);
222 WARN_ON(enabled_irq_mask & ~interrupt_mask);
224 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
227 new_val = dev_priv->irq_mask;
228 new_val &= ~interrupt_mask;
229 new_val |= (~enabled_irq_mask & interrupt_mask);
231 if (new_val != dev_priv->irq_mask) {
232 dev_priv->irq_mask = new_val;
233 I915_WRITE(DEIMR, dev_priv->irq_mask);
239 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
241 ilk_update_display_irq(dev_priv, mask, mask);
245 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
247 ilk_update_display_irq(dev_priv, mask, 0);
251 * ilk_update_gt_irq - update GTIMR
252 * @dev_priv: driver private
253 * @interrupt_mask: mask of interrupt bits to update
254 * @enabled_irq_mask: mask of interrupt bits to enable
256 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
257 uint32_t interrupt_mask,
258 uint32_t enabled_irq_mask)
260 assert_spin_locked(&dev_priv->irq_lock);
262 WARN_ON(enabled_irq_mask & ~interrupt_mask);
264 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
267 dev_priv->gt_irq_mask &= ~interrupt_mask;
268 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
269 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
273 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
275 ilk_update_gt_irq(dev_priv, mask, mask);
278 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
280 ilk_update_gt_irq(dev_priv, mask, 0);
283 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
285 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
288 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
290 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
293 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
295 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
299 * snb_update_pm_irq - update GEN6_PMIMR
300 * @dev_priv: driver private
301 * @interrupt_mask: mask of interrupt bits to update
302 * @enabled_irq_mask: mask of interrupt bits to enable
304 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
305 uint32_t interrupt_mask,
306 uint32_t enabled_irq_mask)
310 WARN_ON(enabled_irq_mask & ~interrupt_mask);
312 assert_spin_locked(&dev_priv->irq_lock);
314 new_val = dev_priv->pm_irq_mask;
315 new_val &= ~interrupt_mask;
316 new_val |= (~enabled_irq_mask & interrupt_mask);
318 if (new_val != dev_priv->pm_irq_mask) {
319 dev_priv->pm_irq_mask = new_val;
320 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
321 POSTING_READ(gen6_pm_imr(dev_priv));
325 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
327 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
330 snb_update_pm_irq(dev_priv, mask, mask);
333 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
336 snb_update_pm_irq(dev_priv, mask, 0);
339 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
341 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
344 __gen6_disable_pm_irq(dev_priv, mask);
347 void gen6_reset_rps_interrupts(struct drm_device *dev)
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 uint32_t reg = gen6_pm_iir(dev_priv);
352 spin_lock_irq(&dev_priv->irq_lock);
353 I915_WRITE(reg, dev_priv->pm_rps_events);
354 I915_WRITE(reg, dev_priv->pm_rps_events);
356 dev_priv->rps.pm_iir = 0;
357 spin_unlock_irq(&dev_priv->irq_lock);
360 void gen6_enable_rps_interrupts(struct drm_device *dev)
362 struct drm_i915_private *dev_priv = dev->dev_private;
364 spin_lock_irq(&dev_priv->irq_lock);
366 WARN_ON(dev_priv->rps.pm_iir);
367 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
368 dev_priv->rps.interrupts_enabled = true;
369 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
370 dev_priv->pm_rps_events);
371 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
373 spin_unlock_irq(&dev_priv->irq_lock);
376 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
379 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
380 * if GEN6_PM_UP_EI_EXPIRED is masked.
382 * TODO: verify if this can be reproduced on VLV,CHV.
384 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
385 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
387 if (INTEL_INFO(dev_priv)->gen >= 8)
388 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
393 void gen6_disable_rps_interrupts(struct drm_device *dev)
395 struct drm_i915_private *dev_priv = dev->dev_private;
397 spin_lock_irq(&dev_priv->irq_lock);
398 dev_priv->rps.interrupts_enabled = false;
399 spin_unlock_irq(&dev_priv->irq_lock);
401 cancel_work_sync(&dev_priv->rps.work);
403 spin_lock_irq(&dev_priv->irq_lock);
405 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
407 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
408 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
409 ~dev_priv->pm_rps_events);
411 spin_unlock_irq(&dev_priv->irq_lock);
413 synchronize_irq(dev->irq);
417 * bdw_update_port_irq - update DE port interrupt
418 * @dev_priv: driver private
419 * @interrupt_mask: mask of interrupt bits to update
420 * @enabled_irq_mask: mask of interrupt bits to enable
422 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
423 uint32_t interrupt_mask,
424 uint32_t enabled_irq_mask)
429 assert_spin_locked(&dev_priv->irq_lock);
431 WARN_ON(enabled_irq_mask & ~interrupt_mask);
433 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
436 old_val = I915_READ(GEN8_DE_PORT_IMR);
439 new_val &= ~interrupt_mask;
440 new_val |= (~enabled_irq_mask & interrupt_mask);
442 if (new_val != old_val) {
443 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
444 POSTING_READ(GEN8_DE_PORT_IMR);
449 * ibx_display_interrupt_update - update SDEIMR
450 * @dev_priv: driver private
451 * @interrupt_mask: mask of interrupt bits to update
452 * @enabled_irq_mask: mask of interrupt bits to enable
454 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
455 uint32_t interrupt_mask,
456 uint32_t enabled_irq_mask)
458 uint32_t sdeimr = I915_READ(SDEIMR);
459 sdeimr &= ~interrupt_mask;
460 sdeimr |= (~enabled_irq_mask & interrupt_mask);
462 WARN_ON(enabled_irq_mask & ~interrupt_mask);
464 assert_spin_locked(&dev_priv->irq_lock);
466 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
469 I915_WRITE(SDEIMR, sdeimr);
470 POSTING_READ(SDEIMR);
474 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
475 u32 enable_mask, u32 status_mask)
477 u32 reg = PIPESTAT(pipe);
478 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
480 assert_spin_locked(&dev_priv->irq_lock);
481 WARN_ON(!intel_irqs_enabled(dev_priv));
483 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
484 status_mask & ~PIPESTAT_INT_STATUS_MASK,
485 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
486 pipe_name(pipe), enable_mask, status_mask))
489 if ((pipestat & enable_mask) == enable_mask)
492 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
494 /* Enable the interrupt, clear any pending status */
495 pipestat |= enable_mask | status_mask;
496 I915_WRITE(reg, pipestat);
501 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
502 u32 enable_mask, u32 status_mask)
504 u32 reg = PIPESTAT(pipe);
505 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
507 assert_spin_locked(&dev_priv->irq_lock);
508 WARN_ON(!intel_irqs_enabled(dev_priv));
510 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
511 status_mask & ~PIPESTAT_INT_STATUS_MASK,
512 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
513 pipe_name(pipe), enable_mask, status_mask))
516 if ((pipestat & enable_mask) == 0)
519 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
521 pipestat &= ~enable_mask;
522 I915_WRITE(reg, pipestat);
526 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
528 u32 enable_mask = status_mask << 16;
531 * On pipe A we don't support the PSR interrupt yet,
532 * on pipe B and C the same bit MBZ.
534 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
537 * On pipe B and C we don't support the PSR interrupt yet, on pipe
538 * A the same bit is for perf counters which we don't use either.
540 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
543 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
544 SPRITE0_FLIP_DONE_INT_EN_VLV |
545 SPRITE1_FLIP_DONE_INT_EN_VLV);
546 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
547 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
548 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
549 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
555 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
560 if (IS_VALLEYVIEW(dev_priv->dev))
561 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
564 enable_mask = status_mask << 16;
565 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
569 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
574 if (IS_VALLEYVIEW(dev_priv->dev))
575 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
578 enable_mask = status_mask << 16;
579 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
583 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
585 static void i915_enable_asle_pipestat(struct drm_device *dev)
587 struct drm_i915_private *dev_priv = dev->dev_private;
589 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
592 spin_lock_irq(&dev_priv->irq_lock);
594 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
595 if (INTEL_INFO(dev)->gen >= 4)
596 i915_enable_pipestat(dev_priv, PIPE_A,
597 PIPE_LEGACY_BLC_EVENT_STATUS);
599 spin_unlock_irq(&dev_priv->irq_lock);
603 * This timing diagram depicts the video signal in and
604 * around the vertical blanking period.
606 * Assumptions about the fictitious mode used in this example:
608 * vsync_start = vblank_start + 1
609 * vsync_end = vblank_start + 2
610 * vtotal = vblank_start + 3
613 * latch double buffered registers
614 * increment frame counter (ctg+)
615 * generate start of vblank interrupt (gen4+)
618 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
619 * | may be shifted forward 1-3 extra lines via PIPECONF
621 * | | start of vsync:
622 * | | generate vsync interrupt
624 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
625 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
626 * ----va---> <-----------------vb--------------------> <--------va-------------
627 * | | <----vs-----> |
628 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
629 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
630 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
632 * last visible pixel first visible pixel
633 * | increment frame counter (gen3/4)
634 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
636 * x = horizontal active
637 * _ = horizontal blanking
638 * hs = horizontal sync
639 * va = vertical active
640 * vb = vertical blanking
642 * vbs = vblank_start (number)
645 * - most events happen at the start of horizontal sync
646 * - frame start happens at the start of horizontal blank, 1-4 lines
647 * (depending on PIPECONF settings) after the start of vblank
648 * - gen3/4 pixel and frame counter are synchronized with the start
649 * of horizontal active on the first line of vertical active
652 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
654 /* Gen2 doesn't have a hardware frame counter */
658 /* Called from drm generic code, passed a 'crtc', which
659 * we use as a pipe index
661 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
663 struct drm_i915_private *dev_priv = dev->dev_private;
664 unsigned long high_frame;
665 unsigned long low_frame;
666 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
667 struct intel_crtc *intel_crtc =
668 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
669 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
671 htotal = mode->crtc_htotal;
672 hsync_start = mode->crtc_hsync_start;
673 vbl_start = mode->crtc_vblank_start;
674 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
675 vbl_start = DIV_ROUND_UP(vbl_start, 2);
677 /* Convert to pixel count */
680 /* Start of vblank event occurs at start of hsync */
681 vbl_start -= htotal - hsync_start;
683 high_frame = PIPEFRAME(pipe);
684 low_frame = PIPEFRAMEPIXEL(pipe);
687 * High & low register fields aren't synchronized, so make sure
688 * we get a low value that's stable across two reads of the high
692 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
693 low = I915_READ(low_frame);
694 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
695 } while (high1 != high2);
697 high1 >>= PIPE_FRAME_HIGH_SHIFT;
698 pixel = low & PIPE_PIXEL_MASK;
699 low >>= PIPE_FRAME_LOW_SHIFT;
702 * The frame counter increments at beginning of active.
703 * Cook up a vblank counter by also checking the pixel
704 * counter against vblank start.
706 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
709 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
711 struct drm_i915_private *dev_priv = dev->dev_private;
712 int reg = PIPE_FRMCOUNT_GM45(pipe);
714 return I915_READ(reg);
717 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
718 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
720 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
722 struct drm_device *dev = crtc->base.dev;
723 struct drm_i915_private *dev_priv = dev->dev_private;
724 const struct drm_display_mode *mode = &crtc->base.hwmode;
725 enum pipe pipe = crtc->pipe;
726 int position, vtotal;
728 vtotal = mode->crtc_vtotal;
729 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
733 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
735 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
738 * On HSW, the DSL reg (0x70000) appears to return 0 if we
739 * read it just before the start of vblank. So try it again
740 * so we don't accidentally end up spanning a vblank frame
741 * increment, causing the pipe_update_end() code to squak at us.
743 * The nature of this problem means we can't simply check the ISR
744 * bit and return the vblank start value; nor can we use the scanline
745 * debug register in the transcoder as it appears to have the same
746 * problem. We may need to extend this to include other platforms,
747 * but so far testing only shows the problem on HSW.
749 if (IS_HASWELL(dev) && !position) {
752 for (i = 0; i < 100; i++) {
754 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
756 if (temp != position) {
764 * See update_scanline_offset() for the details on the
765 * scanline_offset adjustment.
767 return (position + crtc->scanline_offset) % vtotal;
770 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
771 unsigned int flags, int *vpos, int *hpos,
772 ktime_t *stime, ktime_t *etime,
773 const struct drm_display_mode *mode)
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
779 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
782 unsigned long irqflags;
784 if (WARN_ON(!mode->crtc_clock)) {
785 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
786 "pipe %c\n", pipe_name(pipe));
790 htotal = mode->crtc_htotal;
791 hsync_start = mode->crtc_hsync_start;
792 vtotal = mode->crtc_vtotal;
793 vbl_start = mode->crtc_vblank_start;
794 vbl_end = mode->crtc_vblank_end;
796 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
797 vbl_start = DIV_ROUND_UP(vbl_start, 2);
802 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
805 * Lock uncore.lock, as we will do multiple timing critical raw
806 * register reads, potentially with preemption disabled, so the
807 * following code must not block on uncore.lock.
809 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
811 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
813 /* Get optional system timestamp before query. */
815 *stime = ktime_get();
817 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
818 /* No obvious pixelcount register. Only query vertical
819 * scanout position from Display scan line register.
821 position = __intel_get_crtc_scanline(intel_crtc);
823 /* Have access to pixelcount since start of frame.
824 * We can split this into vertical and horizontal
827 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
829 /* convert to pixel counts */
835 * In interlaced modes, the pixel counter counts all pixels,
836 * so one field will have htotal more pixels. In order to avoid
837 * the reported position from jumping backwards when the pixel
838 * counter is beyond the length of the shorter field, just
839 * clamp the position the length of the shorter field. This
840 * matches how the scanline counter based position works since
841 * the scanline counter doesn't count the two half lines.
843 if (position >= vtotal)
844 position = vtotal - 1;
847 * Start of vblank interrupt is triggered at start of hsync,
848 * just prior to the first active line of vblank. However we
849 * consider lines to start at the leading edge of horizontal
850 * active. So, should we get here before we've crossed into
851 * the horizontal active of the first line in vblank, we would
852 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
853 * always add htotal-hsync_start to the current pixel position.
855 position = (position + htotal - hsync_start) % vtotal;
858 /* Get optional system timestamp after query. */
860 *etime = ktime_get();
862 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
864 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
866 in_vbl = position >= vbl_start && position < vbl_end;
869 * While in vblank, position will be negative
870 * counting up towards 0 at vbl_end. And outside
871 * vblank, position will be positive counting
874 if (position >= vbl_start)
877 position += vtotal - vbl_end;
879 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
883 *vpos = position / htotal;
884 *hpos = position - (*vpos * htotal);
889 ret |= DRM_SCANOUTPOS_IN_VBLANK;
894 int intel_get_crtc_scanline(struct intel_crtc *crtc)
896 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
897 unsigned long irqflags;
900 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
901 position = __intel_get_crtc_scanline(crtc);
902 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
907 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
909 struct timeval *vblank_time,
912 struct drm_crtc *crtc;
914 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
915 DRM_ERROR("Invalid crtc %d\n", pipe);
919 /* Get drm_crtc to timestamp: */
920 crtc = intel_get_crtc_for_pipe(dev, pipe);
922 DRM_ERROR("Invalid crtc %d\n", pipe);
926 if (!crtc->hwmode.crtc_clock) {
927 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
931 /* Helper routine in DRM core does all the work: */
932 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
937 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
939 struct drm_i915_private *dev_priv = dev->dev_private;
940 u32 busy_up, busy_down, max_avg, min_avg;
943 spin_lock(&mchdev_lock);
945 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
947 new_delay = dev_priv->ips.cur_delay;
949 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
950 busy_up = I915_READ(RCPREVBSYTUPAVG);
951 busy_down = I915_READ(RCPREVBSYTDNAVG);
952 max_avg = I915_READ(RCBMAXAVG);
953 min_avg = I915_READ(RCBMINAVG);
955 /* Handle RCS change request from hw */
956 if (busy_up > max_avg) {
957 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
958 new_delay = dev_priv->ips.cur_delay - 1;
959 if (new_delay < dev_priv->ips.max_delay)
960 new_delay = dev_priv->ips.max_delay;
961 } else if (busy_down < min_avg) {
962 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
963 new_delay = dev_priv->ips.cur_delay + 1;
964 if (new_delay > dev_priv->ips.min_delay)
965 new_delay = dev_priv->ips.min_delay;
968 if (ironlake_set_drps(dev, new_delay))
969 dev_priv->ips.cur_delay = new_delay;
971 spin_unlock(&mchdev_lock);
976 static void notify_ring(struct intel_engine_cs *ring)
978 if (!intel_ring_initialized(ring))
981 trace_i915_gem_request_notify(ring);
983 wake_up_all(&ring->irq_queue);
986 static void vlv_c0_read(struct drm_i915_private *dev_priv,
987 struct intel_rps_ei *ei)
989 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
990 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
991 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
994 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
995 const struct intel_rps_ei *old,
996 const struct intel_rps_ei *now,
1001 if (old->cz_clock == 0)
1004 time = now->cz_clock - old->cz_clock;
1005 time *= threshold * dev_priv->mem_freq;
1007 /* Workload can be split between render + media, e.g. SwapBuffers
1008 * being blitted in X after being rendered in mesa. To account for
1009 * this we need to combine both engines into our activity counter.
1011 c0 = now->render_c0 - old->render_c0;
1012 c0 += now->media_c0 - old->media_c0;
1013 c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000;
1018 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1020 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1021 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1024 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1026 struct intel_rps_ei now;
1029 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1032 vlv_c0_read(dev_priv, &now);
1033 if (now.cz_clock == 0)
1036 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1037 if (!vlv_c0_above(dev_priv,
1038 &dev_priv->rps.down_ei, &now,
1039 dev_priv->rps.down_threshold))
1040 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1041 dev_priv->rps.down_ei = now;
1044 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1045 if (vlv_c0_above(dev_priv,
1046 &dev_priv->rps.up_ei, &now,
1047 dev_priv->rps.up_threshold))
1048 events |= GEN6_PM_RP_UP_THRESHOLD;
1049 dev_priv->rps.up_ei = now;
1055 static bool any_waiters(struct drm_i915_private *dev_priv)
1057 struct intel_engine_cs *ring;
1060 for_each_ring(ring, dev_priv, i)
1061 if (ring->irq_refcount)
1067 static void gen6_pm_rps_work(struct work_struct *work)
1069 struct drm_i915_private *dev_priv =
1070 container_of(work, struct drm_i915_private, rps.work);
1072 int new_delay, adj, min, max;
1075 spin_lock_irq(&dev_priv->irq_lock);
1076 /* Speed up work cancelation during disabling rps interrupts. */
1077 if (!dev_priv->rps.interrupts_enabled) {
1078 spin_unlock_irq(&dev_priv->irq_lock);
1081 pm_iir = dev_priv->rps.pm_iir;
1082 dev_priv->rps.pm_iir = 0;
1083 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1084 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1085 client_boost = dev_priv->rps.client_boost;
1086 dev_priv->rps.client_boost = false;
1087 spin_unlock_irq(&dev_priv->irq_lock);
1089 /* Make sure we didn't queue anything we're not going to process. */
1090 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1092 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1095 mutex_lock(&dev_priv->rps.hw_lock);
1097 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1099 adj = dev_priv->rps.last_adj;
1100 new_delay = dev_priv->rps.cur_freq;
1101 min = dev_priv->rps.min_freq_softlimit;
1102 max = dev_priv->rps.max_freq_softlimit;
1105 new_delay = dev_priv->rps.max_freq_softlimit;
1107 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1110 else /* CHV needs even encode values */
1111 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1113 * For better performance, jump directly
1114 * to RPe if we're below it.
1116 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1117 new_delay = dev_priv->rps.efficient_freq;
1120 } else if (any_waiters(dev_priv)) {
1122 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1123 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1124 new_delay = dev_priv->rps.efficient_freq;
1126 new_delay = dev_priv->rps.min_freq_softlimit;
1128 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1131 else /* CHV needs even encode values */
1132 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1133 } else { /* unknown event */
1137 dev_priv->rps.last_adj = adj;
1139 /* sysfs frequency interfaces may have snuck in while servicing the
1143 new_delay = clamp_t(int, new_delay, min, max);
1145 intel_set_rps(dev_priv->dev, new_delay);
1147 mutex_unlock(&dev_priv->rps.hw_lock);
1152 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1154 * @work: workqueue struct
1156 * Doesn't actually do anything except notify userspace. As a consequence of
1157 * this event, userspace should try to remap the bad rows since statistically
1158 * it is likely the same row is more likely to go bad again.
1160 static void ivybridge_parity_work(struct work_struct *work)
1162 struct drm_i915_private *dev_priv =
1163 container_of(work, struct drm_i915_private, l3_parity.error_work);
1164 u32 error_status, row, bank, subbank;
1165 char *parity_event[6];
1169 /* We must turn off DOP level clock gating to access the L3 registers.
1170 * In order to prevent a get/put style interface, acquire struct mutex
1171 * any time we access those registers.
1173 mutex_lock(&dev_priv->dev->struct_mutex);
1175 /* If we've screwed up tracking, just let the interrupt fire again */
1176 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1179 misccpctl = I915_READ(GEN7_MISCCPCTL);
1180 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1181 POSTING_READ(GEN7_MISCCPCTL);
1183 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1187 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1190 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1192 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1194 error_status = I915_READ(reg);
1195 row = GEN7_PARITY_ERROR_ROW(error_status);
1196 bank = GEN7_PARITY_ERROR_BANK(error_status);
1197 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1199 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1202 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1203 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1204 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1205 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1206 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1207 parity_event[5] = NULL;
1209 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1210 KOBJ_CHANGE, parity_event);
1212 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1213 slice, row, bank, subbank);
1215 kfree(parity_event[4]);
1216 kfree(parity_event[3]);
1217 kfree(parity_event[2]);
1218 kfree(parity_event[1]);
1221 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1224 WARN_ON(dev_priv->l3_parity.which_slice);
1225 spin_lock_irq(&dev_priv->irq_lock);
1226 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1227 spin_unlock_irq(&dev_priv->irq_lock);
1229 mutex_unlock(&dev_priv->dev->struct_mutex);
1232 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1236 if (!HAS_L3_DPF(dev))
1239 spin_lock(&dev_priv->irq_lock);
1240 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1241 spin_unlock(&dev_priv->irq_lock);
1243 iir &= GT_PARITY_ERROR(dev);
1244 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1245 dev_priv->l3_parity.which_slice |= 1 << 1;
1247 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1248 dev_priv->l3_parity.which_slice |= 1 << 0;
1250 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1253 static void ilk_gt_irq_handler(struct drm_device *dev,
1254 struct drm_i915_private *dev_priv,
1258 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1259 notify_ring(&dev_priv->ring[RCS]);
1260 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1261 notify_ring(&dev_priv->ring[VCS]);
1264 static void snb_gt_irq_handler(struct drm_device *dev,
1265 struct drm_i915_private *dev_priv,
1270 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1271 notify_ring(&dev_priv->ring[RCS]);
1272 if (gt_iir & GT_BSD_USER_INTERRUPT)
1273 notify_ring(&dev_priv->ring[VCS]);
1274 if (gt_iir & GT_BLT_USER_INTERRUPT)
1275 notify_ring(&dev_priv->ring[BCS]);
1277 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1278 GT_BSD_CS_ERROR_INTERRUPT |
1279 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1280 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1282 if (gt_iir & GT_PARITY_ERROR(dev))
1283 ivybridge_parity_error_irq_handler(dev, gt_iir);
1286 static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1289 irqreturn_t ret = IRQ_NONE;
1291 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1292 u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
1294 I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
1297 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1298 intel_lrc_irq_handler(&dev_priv->ring[RCS]);
1299 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1300 notify_ring(&dev_priv->ring[RCS]);
1302 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1303 intel_lrc_irq_handler(&dev_priv->ring[BCS]);
1304 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1305 notify_ring(&dev_priv->ring[BCS]);
1307 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1310 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1311 u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
1313 I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
1316 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1317 intel_lrc_irq_handler(&dev_priv->ring[VCS]);
1318 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1319 notify_ring(&dev_priv->ring[VCS]);
1321 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1322 intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
1323 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1324 notify_ring(&dev_priv->ring[VCS2]);
1326 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1329 if (master_ctl & GEN8_GT_VECS_IRQ) {
1330 u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
1332 I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
1335 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1336 intel_lrc_irq_handler(&dev_priv->ring[VECS]);
1337 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1338 notify_ring(&dev_priv->ring[VECS]);
1340 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1343 if (master_ctl & GEN8_GT_PM_IRQ) {
1344 u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
1345 if (tmp & dev_priv->pm_rps_events) {
1346 I915_WRITE_FW(GEN8_GT_IIR(2),
1347 tmp & dev_priv->pm_rps_events);
1349 gen6_rps_irq_handler(dev_priv, tmp);
1351 DRM_ERROR("The master control interrupt lied (PM)!\n");
1357 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1361 return val & PORTA_HOTPLUG_LONG_DETECT;
1363 return val & PORTB_HOTPLUG_LONG_DETECT;
1365 return val & PORTC_HOTPLUG_LONG_DETECT;
1371 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1375 return val & PORTE_HOTPLUG_LONG_DETECT;
1381 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1385 return val & PORTA_HOTPLUG_LONG_DETECT;
1387 return val & PORTB_HOTPLUG_LONG_DETECT;
1389 return val & PORTC_HOTPLUG_LONG_DETECT;
1391 return val & PORTD_HOTPLUG_LONG_DETECT;
1397 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1401 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1407 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1411 return val & PORTB_HOTPLUG_LONG_DETECT;
1413 return val & PORTC_HOTPLUG_LONG_DETECT;
1415 return val & PORTD_HOTPLUG_LONG_DETECT;
1421 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1425 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1427 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1429 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1436 * Get a bit mask of pins that have triggered, and which ones may be long.
1437 * This can be called multiple times with the same masks to accumulate
1438 * hotplug detection results from several registers.
1440 * Note that the caller is expected to zero out the masks initially.
1442 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1443 u32 hotplug_trigger, u32 dig_hotplug_reg,
1444 const u32 hpd[HPD_NUM_PINS],
1445 bool long_pulse_detect(enum port port, u32 val))
1450 for_each_hpd_pin(i) {
1451 if ((hpd[i] & hotplug_trigger) == 0)
1454 *pin_mask |= BIT(i);
1456 if (!intel_hpd_pin_to_port(i, &port))
1459 if (long_pulse_detect(port, dig_hotplug_reg))
1460 *long_mask |= BIT(i);
1463 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1464 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1468 static void gmbus_irq_handler(struct drm_device *dev)
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1472 wake_up_all(&dev_priv->gmbus_wait_queue);
1475 static void dp_aux_irq_handler(struct drm_device *dev)
1477 struct drm_i915_private *dev_priv = dev->dev_private;
1479 wake_up_all(&dev_priv->gmbus_wait_queue);
1482 #if defined(CONFIG_DEBUG_FS)
1483 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1484 uint32_t crc0, uint32_t crc1,
1485 uint32_t crc2, uint32_t crc3,
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1490 struct intel_pipe_crc_entry *entry;
1493 spin_lock(&pipe_crc->lock);
1495 if (!pipe_crc->entries) {
1496 spin_unlock(&pipe_crc->lock);
1497 DRM_DEBUG_KMS("spurious interrupt\n");
1501 head = pipe_crc->head;
1502 tail = pipe_crc->tail;
1504 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1505 spin_unlock(&pipe_crc->lock);
1506 DRM_ERROR("CRC buffer overflowing\n");
1510 entry = &pipe_crc->entries[head];
1512 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1513 entry->crc[0] = crc0;
1514 entry->crc[1] = crc1;
1515 entry->crc[2] = crc2;
1516 entry->crc[3] = crc3;
1517 entry->crc[4] = crc4;
1519 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1520 pipe_crc->head = head;
1522 spin_unlock(&pipe_crc->lock);
1524 wake_up_interruptible(&pipe_crc->wq);
1528 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1529 uint32_t crc0, uint32_t crc1,
1530 uint32_t crc2, uint32_t crc3,
1535 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1539 display_pipe_crc_irq_handler(dev, pipe,
1540 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1544 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1548 display_pipe_crc_irq_handler(dev, pipe,
1549 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1550 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1551 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1552 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1553 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1556 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 uint32_t res1, res2;
1561 if (INTEL_INFO(dev)->gen >= 3)
1562 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1566 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1567 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1571 display_pipe_crc_irq_handler(dev, pipe,
1572 I915_READ(PIPE_CRC_RES_RED(pipe)),
1573 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1574 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1578 /* The RPS events need forcewake, so we add them to a work queue and mask their
1579 * IMR bits until the work is done. Other interrupts can be processed without
1580 * the work queue. */
1581 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1583 if (pm_iir & dev_priv->pm_rps_events) {
1584 spin_lock(&dev_priv->irq_lock);
1585 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1586 if (dev_priv->rps.interrupts_enabled) {
1587 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1588 queue_work(dev_priv->wq, &dev_priv->rps.work);
1590 spin_unlock(&dev_priv->irq_lock);
1593 if (INTEL_INFO(dev_priv)->gen >= 8)
1596 if (HAS_VEBOX(dev_priv->dev)) {
1597 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1598 notify_ring(&dev_priv->ring[VECS]);
1600 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1601 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1605 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1607 if (!drm_handle_vblank(dev, pipe))
1613 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 u32 pipe_stats[I915_MAX_PIPES] = { };
1619 spin_lock(&dev_priv->irq_lock);
1620 for_each_pipe(dev_priv, pipe) {
1622 u32 mask, iir_bit = 0;
1625 * PIPESTAT bits get signalled even when the interrupt is
1626 * disabled with the mask bits, and some of the status bits do
1627 * not generate interrupts at all (like the underrun bit). Hence
1628 * we need to be careful that we only handle what we want to
1632 /* fifo underruns are filterered in the underrun handler. */
1633 mask = PIPE_FIFO_UNDERRUN_STATUS;
1637 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1640 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1643 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1647 mask |= dev_priv->pipestat_irq_mask[pipe];
1652 reg = PIPESTAT(pipe);
1653 mask |= PIPESTAT_INT_ENABLE_MASK;
1654 pipe_stats[pipe] = I915_READ(reg) & mask;
1657 * Clear the PIPE*STAT regs before the IIR
1659 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1660 PIPESTAT_INT_STATUS_MASK))
1661 I915_WRITE(reg, pipe_stats[pipe]);
1663 spin_unlock(&dev_priv->irq_lock);
1665 for_each_pipe(dev_priv, pipe) {
1666 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1667 intel_pipe_handle_vblank(dev, pipe))
1668 intel_check_page_flip(dev, pipe);
1670 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1671 intel_prepare_page_flip(dev, pipe);
1672 intel_finish_page_flip(dev, pipe);
1675 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1676 i9xx_pipe_crc_irq_handler(dev, pipe);
1678 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1679 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1682 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1683 gmbus_irq_handler(dev);
1686 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1689 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1690 u32 pin_mask = 0, long_mask = 0;
1692 if (!hotplug_status)
1695 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1697 * Make sure hotplug status is cleared before we clear IIR, or else we
1698 * may miss hotplug events.
1700 POSTING_READ(PORT_HOTPLUG_STAT);
1702 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
1703 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1705 if (hotplug_trigger) {
1706 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1707 hotplug_trigger, hpd_status_g4x,
1708 i9xx_port_hotplug_long_detect);
1710 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1713 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1714 dp_aux_irq_handler(dev);
1716 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1718 if (hotplug_trigger) {
1719 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1720 hotplug_trigger, hpd_status_i915,
1721 i9xx_port_hotplug_long_detect);
1722 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1727 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1729 struct drm_device *dev = arg;
1730 struct drm_i915_private *dev_priv = dev->dev_private;
1731 u32 iir, gt_iir, pm_iir;
1732 irqreturn_t ret = IRQ_NONE;
1734 if (!intel_irqs_enabled(dev_priv))
1738 /* Find, clear, then process each source of interrupt */
1740 gt_iir = I915_READ(GTIIR);
1742 I915_WRITE(GTIIR, gt_iir);
1744 pm_iir = I915_READ(GEN6_PMIIR);
1746 I915_WRITE(GEN6_PMIIR, pm_iir);
1748 iir = I915_READ(VLV_IIR);
1750 /* Consume port before clearing IIR or we'll miss events */
1751 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1752 i9xx_hpd_irq_handler(dev);
1753 I915_WRITE(VLV_IIR, iir);
1756 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1762 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1764 gen6_rps_irq_handler(dev_priv, pm_iir);
1765 /* Call regardless, as some status bits might not be
1766 * signalled in iir */
1767 valleyview_pipestat_irq_handler(dev, iir);
1774 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1776 struct drm_device *dev = arg;
1777 struct drm_i915_private *dev_priv = dev->dev_private;
1778 u32 master_ctl, iir;
1779 irqreturn_t ret = IRQ_NONE;
1781 if (!intel_irqs_enabled(dev_priv))
1785 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1786 iir = I915_READ(VLV_IIR);
1788 if (master_ctl == 0 && iir == 0)
1793 I915_WRITE(GEN8_MASTER_IRQ, 0);
1795 /* Find, clear, then process each source of interrupt */
1798 /* Consume port before clearing IIR or we'll miss events */
1799 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1800 i9xx_hpd_irq_handler(dev);
1801 I915_WRITE(VLV_IIR, iir);
1804 gen8_gt_irq_handler(dev_priv, master_ctl);
1806 /* Call regardless, as some status bits might not be
1807 * signalled in iir */
1808 valleyview_pipestat_irq_handler(dev, iir);
1810 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1811 POSTING_READ(GEN8_MASTER_IRQ);
1817 static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
1818 const u32 hpd[HPD_NUM_PINS])
1820 struct drm_i915_private *dev_priv = to_i915(dev);
1821 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1823 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1824 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1826 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1827 dig_hotplug_reg, hpd,
1828 pch_port_hotplug_long_detect);
1830 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1833 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1837 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1839 if (hotplug_trigger)
1840 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1842 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1843 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1844 SDE_AUDIO_POWER_SHIFT);
1845 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1849 if (pch_iir & SDE_AUX_MASK)
1850 dp_aux_irq_handler(dev);
1852 if (pch_iir & SDE_GMBUS)
1853 gmbus_irq_handler(dev);
1855 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1856 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1858 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1859 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1861 if (pch_iir & SDE_POISON)
1862 DRM_ERROR("PCH poison interrupt\n");
1864 if (pch_iir & SDE_FDI_MASK)
1865 for_each_pipe(dev_priv, pipe)
1866 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1868 I915_READ(FDI_RX_IIR(pipe)));
1870 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1871 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1873 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1874 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1876 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1877 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1879 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1880 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1883 static void ivb_err_int_handler(struct drm_device *dev)
1885 struct drm_i915_private *dev_priv = dev->dev_private;
1886 u32 err_int = I915_READ(GEN7_ERR_INT);
1889 if (err_int & ERR_INT_POISON)
1890 DRM_ERROR("Poison interrupt\n");
1892 for_each_pipe(dev_priv, pipe) {
1893 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1894 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1896 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1897 if (IS_IVYBRIDGE(dev))
1898 ivb_pipe_crc_irq_handler(dev, pipe);
1900 hsw_pipe_crc_irq_handler(dev, pipe);
1904 I915_WRITE(GEN7_ERR_INT, err_int);
1907 static void cpt_serr_int_handler(struct drm_device *dev)
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 u32 serr_int = I915_READ(SERR_INT);
1912 if (serr_int & SERR_INT_POISON)
1913 DRM_ERROR("PCH poison interrupt\n");
1915 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1916 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1918 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1919 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1921 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1922 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
1924 I915_WRITE(SERR_INT, serr_int);
1927 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1929 struct drm_i915_private *dev_priv = dev->dev_private;
1931 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1933 if (hotplug_trigger)
1934 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1936 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1937 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1938 SDE_AUDIO_POWER_SHIFT_CPT);
1939 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1943 if (pch_iir & SDE_AUX_MASK_CPT)
1944 dp_aux_irq_handler(dev);
1946 if (pch_iir & SDE_GMBUS_CPT)
1947 gmbus_irq_handler(dev);
1949 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1950 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1952 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1953 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1955 if (pch_iir & SDE_FDI_MASK_CPT)
1956 for_each_pipe(dev_priv, pipe)
1957 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1959 I915_READ(FDI_RX_IIR(pipe)));
1961 if (pch_iir & SDE_ERROR_CPT)
1962 cpt_serr_int_handler(dev);
1965 static void spt_irq_handler(struct drm_device *dev, u32 pch_iir)
1967 struct drm_i915_private *dev_priv = dev->dev_private;
1968 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1969 ~SDE_PORTE_HOTPLUG_SPT;
1970 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1971 u32 pin_mask = 0, long_mask = 0;
1973 if (hotplug_trigger) {
1974 u32 dig_hotplug_reg;
1976 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1977 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1979 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1980 dig_hotplug_reg, hpd_spt,
1981 spt_port_hotplug_long_detect);
1984 if (hotplug2_trigger) {
1985 u32 dig_hotplug_reg;
1987 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
1988 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
1990 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
1991 dig_hotplug_reg, hpd_spt,
1992 spt_port_hotplug2_long_detect);
1996 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1998 if (pch_iir & SDE_GMBUS_CPT)
1999 gmbus_irq_handler(dev);
2002 static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2003 const u32 hpd[HPD_NUM_PINS])
2005 struct drm_i915_private *dev_priv = to_i915(dev);
2006 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2008 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2009 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2011 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2012 dig_hotplug_reg, hpd,
2013 ilk_port_hotplug_long_detect);
2015 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2018 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2022 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2024 if (hotplug_trigger)
2025 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk);
2027 if (de_iir & DE_AUX_CHANNEL_A)
2028 dp_aux_irq_handler(dev);
2030 if (de_iir & DE_GSE)
2031 intel_opregion_asle_intr(dev);
2033 if (de_iir & DE_POISON)
2034 DRM_ERROR("Poison interrupt\n");
2036 for_each_pipe(dev_priv, pipe) {
2037 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2038 intel_pipe_handle_vblank(dev, pipe))
2039 intel_check_page_flip(dev, pipe);
2041 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2042 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2044 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2045 i9xx_pipe_crc_irq_handler(dev, pipe);
2047 /* plane/pipes map 1:1 on ilk+ */
2048 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2049 intel_prepare_page_flip(dev, pipe);
2050 intel_finish_page_flip_plane(dev, pipe);
2054 /* check event from PCH */
2055 if (de_iir & DE_PCH_EVENT) {
2056 u32 pch_iir = I915_READ(SDEIIR);
2058 if (HAS_PCH_CPT(dev))
2059 cpt_irq_handler(dev, pch_iir);
2061 ibx_irq_handler(dev, pch_iir);
2063 /* should clear PCH hotplug event before clear CPU irq */
2064 I915_WRITE(SDEIIR, pch_iir);
2067 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2068 ironlake_rps_change_irq_handler(dev);
2071 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2073 struct drm_i915_private *dev_priv = dev->dev_private;
2075 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2077 if (hotplug_trigger)
2078 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb);
2080 if (de_iir & DE_ERR_INT_IVB)
2081 ivb_err_int_handler(dev);
2083 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2084 dp_aux_irq_handler(dev);
2086 if (de_iir & DE_GSE_IVB)
2087 intel_opregion_asle_intr(dev);
2089 for_each_pipe(dev_priv, pipe) {
2090 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2091 intel_pipe_handle_vblank(dev, pipe))
2092 intel_check_page_flip(dev, pipe);
2094 /* plane/pipes map 1:1 on ilk+ */
2095 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2096 intel_prepare_page_flip(dev, pipe);
2097 intel_finish_page_flip_plane(dev, pipe);
2101 /* check event from PCH */
2102 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2103 u32 pch_iir = I915_READ(SDEIIR);
2105 cpt_irq_handler(dev, pch_iir);
2107 /* clear PCH hotplug event before clear CPU irq */
2108 I915_WRITE(SDEIIR, pch_iir);
2113 * To handle irqs with the minimum potential races with fresh interrupts, we:
2114 * 1 - Disable Master Interrupt Control.
2115 * 2 - Find the source(s) of the interrupt.
2116 * 3 - Clear the Interrupt Identity bits (IIR).
2117 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2118 * 5 - Re-enable Master Interrupt Control.
2120 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2122 struct drm_device *dev = arg;
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2125 irqreturn_t ret = IRQ_NONE;
2127 if (!intel_irqs_enabled(dev_priv))
2130 /* We get interrupts on unclaimed registers, so check for this before we
2131 * do any I915_{READ,WRITE}. */
2132 intel_uncore_check_errors(dev);
2134 /* disable master interrupt before clearing iir */
2135 de_ier = I915_READ(DEIER);
2136 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2137 POSTING_READ(DEIER);
2139 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2140 * interrupts will will be stored on its back queue, and then we'll be
2141 * able to process them after we restore SDEIER (as soon as we restore
2142 * it, we'll get an interrupt if SDEIIR still has something to process
2143 * due to its back queue). */
2144 if (!HAS_PCH_NOP(dev)) {
2145 sde_ier = I915_READ(SDEIER);
2146 I915_WRITE(SDEIER, 0);
2147 POSTING_READ(SDEIER);
2150 /* Find, clear, then process each source of interrupt */
2152 gt_iir = I915_READ(GTIIR);
2154 I915_WRITE(GTIIR, gt_iir);
2156 if (INTEL_INFO(dev)->gen >= 6)
2157 snb_gt_irq_handler(dev, dev_priv, gt_iir);
2159 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2162 de_iir = I915_READ(DEIIR);
2164 I915_WRITE(DEIIR, de_iir);
2166 if (INTEL_INFO(dev)->gen >= 7)
2167 ivb_display_irq_handler(dev, de_iir);
2169 ilk_display_irq_handler(dev, de_iir);
2172 if (INTEL_INFO(dev)->gen >= 6) {
2173 u32 pm_iir = I915_READ(GEN6_PMIIR);
2175 I915_WRITE(GEN6_PMIIR, pm_iir);
2177 gen6_rps_irq_handler(dev_priv, pm_iir);
2181 I915_WRITE(DEIER, de_ier);
2182 POSTING_READ(DEIER);
2183 if (!HAS_PCH_NOP(dev)) {
2184 I915_WRITE(SDEIER, sde_ier);
2185 POSTING_READ(SDEIER);
2191 static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2192 const u32 hpd[HPD_NUM_PINS])
2194 struct drm_i915_private *dev_priv = to_i915(dev);
2195 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2197 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2198 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2200 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2201 dig_hotplug_reg, hpd,
2202 bxt_port_hotplug_long_detect);
2204 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2207 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2209 struct drm_device *dev = arg;
2210 struct drm_i915_private *dev_priv = dev->dev_private;
2212 irqreturn_t ret = IRQ_NONE;
2215 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2217 if (!intel_irqs_enabled(dev_priv))
2220 if (INTEL_INFO(dev_priv)->gen >= 9)
2221 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2224 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2225 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2229 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2231 /* Find, clear, then process each source of interrupt */
2233 ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2235 if (master_ctl & GEN8_DE_MISC_IRQ) {
2236 tmp = I915_READ(GEN8_DE_MISC_IIR);
2238 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2240 if (tmp & GEN8_DE_MISC_GSE)
2241 intel_opregion_asle_intr(dev);
2243 DRM_ERROR("Unexpected DE Misc interrupt\n");
2246 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2249 if (master_ctl & GEN8_DE_PORT_IRQ) {
2250 tmp = I915_READ(GEN8_DE_PORT_IIR);
2253 u32 hotplug_trigger = 0;
2255 if (IS_BROXTON(dev_priv))
2256 hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK;
2257 else if (IS_BROADWELL(dev_priv))
2258 hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG;
2260 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2263 if (tmp & aux_mask) {
2264 dp_aux_irq_handler(dev);
2268 if (hotplug_trigger) {
2269 if (IS_BROXTON(dev))
2270 bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt);
2272 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw);
2276 if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
2277 gmbus_irq_handler(dev);
2282 DRM_ERROR("Unexpected DE Port interrupt\n");
2285 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2288 for_each_pipe(dev_priv, pipe) {
2289 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2291 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2294 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2297 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2299 if (pipe_iir & GEN8_PIPE_VBLANK &&
2300 intel_pipe_handle_vblank(dev, pipe))
2301 intel_check_page_flip(dev, pipe);
2303 if (INTEL_INFO(dev_priv)->gen >= 9)
2304 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2306 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2309 intel_prepare_page_flip(dev, pipe);
2310 intel_finish_page_flip_plane(dev, pipe);
2313 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2314 hsw_pipe_crc_irq_handler(dev, pipe);
2316 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2317 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2321 if (INTEL_INFO(dev_priv)->gen >= 9)
2322 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2324 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2327 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2329 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2331 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2334 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2335 master_ctl & GEN8_DE_PCH_IRQ) {
2337 * FIXME(BDW): Assume for now that the new interrupt handling
2338 * scheme also closed the SDE interrupt handling race we've seen
2339 * on older pch-split platforms. But this needs testing.
2341 u32 pch_iir = I915_READ(SDEIIR);
2343 I915_WRITE(SDEIIR, pch_iir);
2346 if (HAS_PCH_SPT(dev_priv))
2347 spt_irq_handler(dev, pch_iir);
2349 cpt_irq_handler(dev, pch_iir);
2351 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2355 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2356 POSTING_READ_FW(GEN8_MASTER_IRQ);
2361 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2362 bool reset_completed)
2364 struct intel_engine_cs *ring;
2368 * Notify all waiters for GPU completion events that reset state has
2369 * been changed, and that they need to restart their wait after
2370 * checking for potential errors (and bail out to drop locks if there is
2371 * a gpu reset pending so that i915_error_work_func can acquire them).
2374 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2375 for_each_ring(ring, dev_priv, i)
2376 wake_up_all(&ring->irq_queue);
2378 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2379 wake_up_all(&dev_priv->pending_flip_queue);
2382 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2383 * reset state is cleared.
2385 if (reset_completed)
2386 wake_up_all(&dev_priv->gpu_error.reset_queue);
2390 * i915_reset_and_wakeup - do process context error handling work
2392 * Fire an error uevent so userspace can see that a hang or error
2395 static void i915_reset_and_wakeup(struct drm_device *dev)
2397 struct drm_i915_private *dev_priv = to_i915(dev);
2398 struct i915_gpu_error *error = &dev_priv->gpu_error;
2399 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2400 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2401 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2404 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2407 * Note that there's only one work item which does gpu resets, so we
2408 * need not worry about concurrent gpu resets potentially incrementing
2409 * error->reset_counter twice. We only need to take care of another
2410 * racing irq/hangcheck declaring the gpu dead for a second time. A
2411 * quick check for that is good enough: schedule_work ensures the
2412 * correct ordering between hang detection and this work item, and since
2413 * the reset in-progress bit is only ever set by code outside of this
2414 * work we don't need to worry about any other races.
2416 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2417 DRM_DEBUG_DRIVER("resetting chip\n");
2418 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2422 * In most cases it's guaranteed that we get here with an RPM
2423 * reference held, for example because there is a pending GPU
2424 * request that won't finish until the reset is done. This
2425 * isn't the case at least when we get here by doing a
2426 * simulated reset via debugs, so get an RPM reference.
2428 intel_runtime_pm_get(dev_priv);
2430 intel_prepare_reset(dev);
2433 * All state reset _must_ be completed before we update the
2434 * reset counter, for otherwise waiters might miss the reset
2435 * pending state and not properly drop locks, resulting in
2436 * deadlocks with the reset work.
2438 ret = i915_reset(dev);
2440 intel_finish_reset(dev);
2442 intel_runtime_pm_put(dev_priv);
2446 * After all the gem state is reset, increment the reset
2447 * counter and wake up everyone waiting for the reset to
2450 * Since unlock operations are a one-sided barrier only,
2451 * we need to insert a barrier here to order any seqno
2453 * the counter increment.
2455 smp_mb__before_atomic();
2456 atomic_inc(&dev_priv->gpu_error.reset_counter);
2458 kobject_uevent_env(&dev->primary->kdev->kobj,
2459 KOBJ_CHANGE, reset_done_event);
2461 atomic_or(I915_WEDGED, &error->reset_counter);
2465 * Note: The wake_up also serves as a memory barrier so that
2466 * waiters see the update value of the reset counter atomic_t.
2468 i915_error_wake_up(dev_priv, true);
2472 static void i915_report_and_clear_eir(struct drm_device *dev)
2474 struct drm_i915_private *dev_priv = dev->dev_private;
2475 uint32_t instdone[I915_NUM_INSTDONE_REG];
2476 u32 eir = I915_READ(EIR);
2482 pr_err("render error detected, EIR: 0x%08x\n", eir);
2484 i915_get_extra_instdone(dev, instdone);
2487 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2488 u32 ipeir = I915_READ(IPEIR_I965);
2490 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2491 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2492 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2493 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2494 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2495 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2496 I915_WRITE(IPEIR_I965, ipeir);
2497 POSTING_READ(IPEIR_I965);
2499 if (eir & GM45_ERROR_PAGE_TABLE) {
2500 u32 pgtbl_err = I915_READ(PGTBL_ER);
2501 pr_err("page table error\n");
2502 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2503 I915_WRITE(PGTBL_ER, pgtbl_err);
2504 POSTING_READ(PGTBL_ER);
2508 if (!IS_GEN2(dev)) {
2509 if (eir & I915_ERROR_PAGE_TABLE) {
2510 u32 pgtbl_err = I915_READ(PGTBL_ER);
2511 pr_err("page table error\n");
2512 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2513 I915_WRITE(PGTBL_ER, pgtbl_err);
2514 POSTING_READ(PGTBL_ER);
2518 if (eir & I915_ERROR_MEMORY_REFRESH) {
2519 pr_err("memory refresh error:\n");
2520 for_each_pipe(dev_priv, pipe)
2521 pr_err("pipe %c stat: 0x%08x\n",
2522 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2523 /* pipestat has already been acked */
2525 if (eir & I915_ERROR_INSTRUCTION) {
2526 pr_err("instruction error\n");
2527 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2528 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2529 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2530 if (INTEL_INFO(dev)->gen < 4) {
2531 u32 ipeir = I915_READ(IPEIR);
2533 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2534 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2535 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2536 I915_WRITE(IPEIR, ipeir);
2537 POSTING_READ(IPEIR);
2539 u32 ipeir = I915_READ(IPEIR_I965);
2541 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2542 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2543 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2544 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2545 I915_WRITE(IPEIR_I965, ipeir);
2546 POSTING_READ(IPEIR_I965);
2550 I915_WRITE(EIR, eir);
2552 eir = I915_READ(EIR);
2555 * some errors might have become stuck,
2558 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2559 I915_WRITE(EMR, I915_READ(EMR) | eir);
2560 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2565 * i915_handle_error - handle a gpu error
2568 * Do some basic checking of regsiter state at error time and
2569 * dump it to the syslog. Also call i915_capture_error_state() to make
2570 * sure we get a record and make it available in debugfs. Fire a uevent
2571 * so userspace knows something bad happened (should trigger collection
2572 * of a ring dump etc.).
2574 void i915_handle_error(struct drm_device *dev, bool wedged,
2575 const char *fmt, ...)
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2581 va_start(args, fmt);
2582 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2585 i915_capture_error_state(dev, wedged, error_msg);
2586 i915_report_and_clear_eir(dev);
2589 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2590 &dev_priv->gpu_error.reset_counter);
2593 * Wakeup waiting processes so that the reset function
2594 * i915_reset_and_wakeup doesn't deadlock trying to grab
2595 * various locks. By bumping the reset counter first, the woken
2596 * processes will see a reset in progress and back off,
2597 * releasing their locks and then wait for the reset completion.
2598 * We must do this for _all_ gpu waiters that might hold locks
2599 * that the reset work needs to acquire.
2601 * Note: The wake_up serves as the required memory barrier to
2602 * ensure that the waiters see the updated value of the reset
2605 i915_error_wake_up(dev_priv, false);
2608 i915_reset_and_wakeup(dev);
2611 /* Called from drm generic code, passed 'crtc' which
2612 * we use as a pipe index
2614 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2616 struct drm_i915_private *dev_priv = dev->dev_private;
2617 unsigned long irqflags;
2619 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2620 if (INTEL_INFO(dev)->gen >= 4)
2621 i915_enable_pipestat(dev_priv, pipe,
2622 PIPE_START_VBLANK_INTERRUPT_STATUS);
2624 i915_enable_pipestat(dev_priv, pipe,
2625 PIPE_VBLANK_INTERRUPT_STATUS);
2626 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2631 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 unsigned long irqflags;
2635 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2636 DE_PIPE_VBLANK(pipe);
2638 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2639 ironlake_enable_display_irq(dev_priv, bit);
2640 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2645 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2647 struct drm_i915_private *dev_priv = dev->dev_private;
2648 unsigned long irqflags;
2650 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2651 i915_enable_pipestat(dev_priv, pipe,
2652 PIPE_START_VBLANK_INTERRUPT_STATUS);
2653 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2658 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661 unsigned long irqflags;
2663 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2664 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2665 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2666 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2667 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2671 /* Called from drm generic code, passed 'crtc' which
2672 * we use as a pipe index
2674 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 unsigned long irqflags;
2679 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2680 i915_disable_pipestat(dev_priv, pipe,
2681 PIPE_VBLANK_INTERRUPT_STATUS |
2682 PIPE_START_VBLANK_INTERRUPT_STATUS);
2683 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2686 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2689 unsigned long irqflags;
2690 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2691 DE_PIPE_VBLANK(pipe);
2693 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2694 ironlake_disable_display_irq(dev_priv, bit);
2695 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2698 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2700 struct drm_i915_private *dev_priv = dev->dev_private;
2701 unsigned long irqflags;
2703 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2704 i915_disable_pipestat(dev_priv, pipe,
2705 PIPE_START_VBLANK_INTERRUPT_STATUS);
2706 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2709 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 unsigned long irqflags;
2714 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2715 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2716 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2717 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2718 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2722 ring_idle(struct intel_engine_cs *ring, u32 seqno)
2724 return (list_empty(&ring->request_list) ||
2725 i915_seqno_passed(seqno, ring->last_submitted_seqno));
2729 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2731 if (INTEL_INFO(dev)->gen >= 8) {
2732 return (ipehr >> 23) == 0x1c;
2734 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2735 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2736 MI_SEMAPHORE_REGISTER);
2740 static struct intel_engine_cs *
2741 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2743 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2744 struct intel_engine_cs *signaller;
2747 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2748 for_each_ring(signaller, dev_priv, i) {
2749 if (ring == signaller)
2752 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2756 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2758 for_each_ring(signaller, dev_priv, i) {
2759 if(ring == signaller)
2762 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2767 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2768 ring->id, ipehr, offset);
2773 static struct intel_engine_cs *
2774 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2776 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2777 u32 cmd, ipehr, head;
2781 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2782 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2786 * HEAD is likely pointing to the dword after the actual command,
2787 * so scan backwards until we find the MBOX. But limit it to just 3
2788 * or 4 dwords depending on the semaphore wait command size.
2789 * Note that we don't care about ACTHD here since that might
2790 * point at at batch, and semaphores are always emitted into the
2791 * ringbuffer itself.
2793 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2794 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2796 for (i = backwards; i; --i) {
2798 * Be paranoid and presume the hw has gone off into the wild -
2799 * our ring is smaller than what the hardware (and hence
2800 * HEAD_ADDR) allows. Also handles wrap-around.
2802 head &= ring->buffer->size - 1;
2804 /* This here seems to blow up */
2805 cmd = ioread32(ring->buffer->virtual_start + head);
2815 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2816 if (INTEL_INFO(ring->dev)->gen >= 8) {
2817 offset = ioread32(ring->buffer->virtual_start + head + 12);
2819 offset = ioread32(ring->buffer->virtual_start + head + 8);
2821 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2824 static int semaphore_passed(struct intel_engine_cs *ring)
2826 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2827 struct intel_engine_cs *signaller;
2830 ring->hangcheck.deadlock++;
2832 signaller = semaphore_waits_for(ring, &seqno);
2833 if (signaller == NULL)
2836 /* Prevent pathological recursion due to driver bugs */
2837 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2840 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2843 /* cursory check for an unkickable deadlock */
2844 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2845 semaphore_passed(signaller) < 0)
2851 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2853 struct intel_engine_cs *ring;
2856 for_each_ring(ring, dev_priv, i)
2857 ring->hangcheck.deadlock = 0;
2860 static enum intel_ring_hangcheck_action
2861 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2863 struct drm_device *dev = ring->dev;
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2867 if (acthd != ring->hangcheck.acthd) {
2868 if (acthd > ring->hangcheck.max_acthd) {
2869 ring->hangcheck.max_acthd = acthd;
2870 return HANGCHECK_ACTIVE;
2873 return HANGCHECK_ACTIVE_LOOP;
2877 return HANGCHECK_HUNG;
2879 /* Is the chip hanging on a WAIT_FOR_EVENT?
2880 * If so we can simply poke the RB_WAIT bit
2881 * and break the hang. This should work on
2882 * all but the second generation chipsets.
2884 tmp = I915_READ_CTL(ring);
2885 if (tmp & RING_WAIT) {
2886 i915_handle_error(dev, false,
2887 "Kicking stuck wait on %s",
2889 I915_WRITE_CTL(ring, tmp);
2890 return HANGCHECK_KICK;
2893 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2894 switch (semaphore_passed(ring)) {
2896 return HANGCHECK_HUNG;
2898 i915_handle_error(dev, false,
2899 "Kicking stuck semaphore on %s",
2901 I915_WRITE_CTL(ring, tmp);
2902 return HANGCHECK_KICK;
2904 return HANGCHECK_WAIT;
2908 return HANGCHECK_HUNG;
2912 * This is called when the chip hasn't reported back with completed
2913 * batchbuffers in a long time. We keep track per ring seqno progress and
2914 * if there are no progress, hangcheck score for that ring is increased.
2915 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2916 * we kick the ring. If we see no progress on three subsequent calls
2917 * we assume chip is wedged and try to fix it by resetting the chip.
2919 static void i915_hangcheck_elapsed(struct work_struct *work)
2921 struct drm_i915_private *dev_priv =
2922 container_of(work, typeof(*dev_priv),
2923 gpu_error.hangcheck_work.work);
2924 struct drm_device *dev = dev_priv->dev;
2925 struct intel_engine_cs *ring;
2927 int busy_count = 0, rings_hung = 0;
2928 bool stuck[I915_NUM_RINGS] = { 0 };
2933 if (!i915.enable_hangcheck)
2936 for_each_ring(ring, dev_priv, i) {
2941 semaphore_clear_deadlocks(dev_priv);
2943 seqno = ring->get_seqno(ring, false);
2944 acthd = intel_ring_get_active_head(ring);
2946 if (ring->hangcheck.seqno == seqno) {
2947 if (ring_idle(ring, seqno)) {
2948 ring->hangcheck.action = HANGCHECK_IDLE;
2950 if (waitqueue_active(&ring->irq_queue)) {
2951 /* Issue a wake-up to catch stuck h/w. */
2952 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2953 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2954 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2957 DRM_INFO("Fake missed irq on %s\n",
2959 wake_up_all(&ring->irq_queue);
2961 /* Safeguard against driver failure */
2962 ring->hangcheck.score += BUSY;
2966 /* We always increment the hangcheck score
2967 * if the ring is busy and still processing
2968 * the same request, so that no single request
2969 * can run indefinitely (such as a chain of
2970 * batches). The only time we do not increment
2971 * the hangcheck score on this ring, if this
2972 * ring is in a legitimate wait for another
2973 * ring. In that case the waiting ring is a
2974 * victim and we want to be sure we catch the
2975 * right culprit. Then every time we do kick
2976 * the ring, add a small increment to the
2977 * score so that we can catch a batch that is
2978 * being repeatedly kicked and so responsible
2979 * for stalling the machine.
2981 ring->hangcheck.action = ring_stuck(ring,
2984 switch (ring->hangcheck.action) {
2985 case HANGCHECK_IDLE:
2986 case HANGCHECK_WAIT:
2987 case HANGCHECK_ACTIVE:
2989 case HANGCHECK_ACTIVE_LOOP:
2990 ring->hangcheck.score += BUSY;
2992 case HANGCHECK_KICK:
2993 ring->hangcheck.score += KICK;
2995 case HANGCHECK_HUNG:
2996 ring->hangcheck.score += HUNG;
3002 ring->hangcheck.action = HANGCHECK_ACTIVE;
3004 /* Gradually reduce the count so that we catch DoS
3005 * attempts across multiple batches.
3007 if (ring->hangcheck.score > 0)
3008 ring->hangcheck.score--;
3010 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3013 ring->hangcheck.seqno = seqno;
3014 ring->hangcheck.acthd = acthd;
3018 for_each_ring(ring, dev_priv, i) {
3019 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3020 DRM_INFO("%s on %s\n",
3021 stuck[i] ? "stuck" : "no progress",
3028 return i915_handle_error(dev, true, "Ring hung");
3031 /* Reset timer case chip hangs without another request
3033 i915_queue_hangcheck(dev);
3036 void i915_queue_hangcheck(struct drm_device *dev)
3038 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3040 if (!i915.enable_hangcheck)
3043 /* Don't continually defer the hangcheck so that it is always run at
3044 * least once after work has been scheduled on any ring. Otherwise,
3045 * we will ignore a hung ring if a second ring is kept busy.
3048 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3049 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3052 static void ibx_irq_reset(struct drm_device *dev)
3054 struct drm_i915_private *dev_priv = dev->dev_private;
3056 if (HAS_PCH_NOP(dev))
3059 GEN5_IRQ_RESET(SDE);
3061 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3062 I915_WRITE(SERR_INT, 0xffffffff);
3066 * SDEIER is also touched by the interrupt handler to work around missed PCH
3067 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3068 * instead we unconditionally enable all PCH interrupt sources here, but then
3069 * only unmask them as needed with SDEIMR.
3071 * This function needs to be called before interrupts are enabled.
3073 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3075 struct drm_i915_private *dev_priv = dev->dev_private;
3077 if (HAS_PCH_NOP(dev))
3080 WARN_ON(I915_READ(SDEIER) != 0);
3081 I915_WRITE(SDEIER, 0xffffffff);
3082 POSTING_READ(SDEIER);
3085 static void gen5_gt_irq_reset(struct drm_device *dev)
3087 struct drm_i915_private *dev_priv = dev->dev_private;
3090 if (INTEL_INFO(dev)->gen >= 6)
3091 GEN5_IRQ_RESET(GEN6_PM);
3096 static void ironlake_irq_reset(struct drm_device *dev)
3098 struct drm_i915_private *dev_priv = dev->dev_private;
3100 I915_WRITE(HWSTAM, 0xffffffff);
3104 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3106 gen5_gt_irq_reset(dev);
3111 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3115 i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
3116 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3118 for_each_pipe(dev_priv, pipe)
3119 I915_WRITE(PIPESTAT(pipe), 0xffff);
3121 GEN5_IRQ_RESET(VLV_);
3124 static void valleyview_irq_preinstall(struct drm_device *dev)
3126 struct drm_i915_private *dev_priv = dev->dev_private;
3129 I915_WRITE(VLV_IMR, 0);
3130 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3131 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3132 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3134 gen5_gt_irq_reset(dev);
3136 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3138 vlv_display_irq_reset(dev_priv);
3141 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3143 GEN8_IRQ_RESET_NDX(GT, 0);
3144 GEN8_IRQ_RESET_NDX(GT, 1);
3145 GEN8_IRQ_RESET_NDX(GT, 2);
3146 GEN8_IRQ_RESET_NDX(GT, 3);
3149 static void gen8_irq_reset(struct drm_device *dev)
3151 struct drm_i915_private *dev_priv = dev->dev_private;
3154 I915_WRITE(GEN8_MASTER_IRQ, 0);
3155 POSTING_READ(GEN8_MASTER_IRQ);
3157 gen8_gt_irq_reset(dev_priv);
3159 for_each_pipe(dev_priv, pipe)
3160 if (intel_display_power_is_enabled(dev_priv,
3161 POWER_DOMAIN_PIPE(pipe)))
3162 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3164 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3165 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3166 GEN5_IRQ_RESET(GEN8_PCU_);
3168 if (HAS_PCH_SPLIT(dev))
3172 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3173 unsigned int pipe_mask)
3175 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3177 spin_lock_irq(&dev_priv->irq_lock);
3178 if (pipe_mask & 1 << PIPE_A)
3179 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
3180 dev_priv->de_irq_mask[PIPE_A],
3181 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
3182 if (pipe_mask & 1 << PIPE_B)
3183 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
3184 dev_priv->de_irq_mask[PIPE_B],
3185 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3186 if (pipe_mask & 1 << PIPE_C)
3187 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
3188 dev_priv->de_irq_mask[PIPE_C],
3189 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3190 spin_unlock_irq(&dev_priv->irq_lock);
3193 static void cherryview_irq_preinstall(struct drm_device *dev)
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3197 I915_WRITE(GEN8_MASTER_IRQ, 0);
3198 POSTING_READ(GEN8_MASTER_IRQ);
3200 gen8_gt_irq_reset(dev_priv);
3202 GEN5_IRQ_RESET(GEN8_PCU_);
3204 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3206 vlv_display_irq_reset(dev_priv);
3209 static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
3210 const u32 hpd[HPD_NUM_PINS])
3212 struct drm_i915_private *dev_priv = to_i915(dev);
3213 struct intel_encoder *encoder;
3214 u32 enabled_irqs = 0;
3216 for_each_intel_encoder(dev, encoder)
3217 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3218 enabled_irqs |= hpd[encoder->hpd_pin];
3220 return enabled_irqs;
3223 static void ibx_hpd_irq_setup(struct drm_device *dev)
3225 struct drm_i915_private *dev_priv = dev->dev_private;
3226 u32 hotplug_irqs, hotplug, enabled_irqs;
3228 if (HAS_PCH_IBX(dev)) {
3229 hotplug_irqs = SDE_HOTPLUG_MASK;
3230 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
3232 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3233 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
3236 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3239 * Enable digital hotplug on the PCH, and configure the DP short pulse
3240 * duration to 2ms (which is the minimum in the Display Port spec).
3241 * The pulse duration bits are reserved on LPT+.
3243 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3244 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3245 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3246 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3247 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3249 * When CPU and PCH are on the same package, port A
3250 * HPD must be enabled in both north and south.
3252 if (HAS_PCH_LPT_LP(dev))
3253 hotplug |= PORTA_HOTPLUG_ENABLE;
3254 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3257 static void spt_hpd_irq_setup(struct drm_device *dev)
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 u32 hotplug_irqs, hotplug, enabled_irqs;
3262 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3263 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);
3265 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3267 /* Enable digital hotplug on the PCH */
3268 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3269 hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3270 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3271 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3273 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3274 hotplug |= PORTE_HOTPLUG_ENABLE;
3275 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3278 static void ilk_hpd_irq_setup(struct drm_device *dev)
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 u32 hotplug_irqs, hotplug, enabled_irqs;
3283 if (INTEL_INFO(dev)->gen >= 8) {
3284 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3285 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw);
3287 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3288 } else if (INTEL_INFO(dev)->gen >= 7) {
3289 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3290 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb);
3292 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3294 hotplug_irqs = DE_DP_A_HOTPLUG;
3295 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk);
3297 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3301 * Enable digital hotplug on the CPU, and configure the DP short pulse
3302 * duration to 2ms (which is the minimum in the Display Port spec)
3303 * The pulse duration bits are reserved on HSW+.
3305 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3306 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3307 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3308 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3310 ibx_hpd_irq_setup(dev);
3313 static void bxt_hpd_irq_setup(struct drm_device *dev)
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 u32 hotplug_irqs, hotplug, enabled_irqs;
3318 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt);
3319 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3321 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3323 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3324 hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3325 PORTA_HOTPLUG_ENABLE;
3326 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3329 static void ibx_irq_postinstall(struct drm_device *dev)
3331 struct drm_i915_private *dev_priv = dev->dev_private;
3334 if (HAS_PCH_NOP(dev))
3337 if (HAS_PCH_IBX(dev))
3338 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3340 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3342 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3343 I915_WRITE(SDEIMR, ~mask);
3346 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349 u32 pm_irqs, gt_irqs;
3351 pm_irqs = gt_irqs = 0;
3353 dev_priv->gt_irq_mask = ~0;
3354 if (HAS_L3_DPF(dev)) {
3355 /* L3 parity interrupt is always unmasked. */
3356 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3357 gt_irqs |= GT_PARITY_ERROR(dev);
3360 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3362 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3363 ILK_BSD_USER_INTERRUPT;
3365 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3368 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3370 if (INTEL_INFO(dev)->gen >= 6) {
3372 * RPS interrupts will get enabled/disabled on demand when RPS
3373 * itself is enabled/disabled.
3376 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3378 dev_priv->pm_irq_mask = 0xffffffff;
3379 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3383 static int ironlake_irq_postinstall(struct drm_device *dev)
3385 struct drm_i915_private *dev_priv = dev->dev_private;
3386 u32 display_mask, extra_mask;
3388 if (INTEL_INFO(dev)->gen >= 7) {
3389 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3390 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3391 DE_PLANEB_FLIP_DONE_IVB |
3392 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3393 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3394 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3395 DE_DP_A_HOTPLUG_IVB);
3397 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3398 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3400 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3402 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3403 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3407 dev_priv->irq_mask = ~display_mask;
3409 I915_WRITE(HWSTAM, 0xeffe);
3411 ibx_irq_pre_postinstall(dev);
3413 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3415 gen5_gt_irq_postinstall(dev);
3417 ibx_irq_postinstall(dev);
3419 if (IS_IRONLAKE_M(dev)) {
3420 /* Enable PCU event interrupts
3422 * spinlocking not required here for correctness since interrupt
3423 * setup is guaranteed to run in single-threaded context. But we
3424 * need it to make the assert_spin_locked happy. */
3425 spin_lock_irq(&dev_priv->irq_lock);
3426 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3427 spin_unlock_irq(&dev_priv->irq_lock);
3433 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3439 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3440 PIPE_FIFO_UNDERRUN_STATUS;
3442 for_each_pipe(dev_priv, pipe)
3443 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3444 POSTING_READ(PIPESTAT(PIPE_A));
3446 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3447 PIPE_CRC_DONE_INTERRUPT_STATUS;
3449 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3450 for_each_pipe(dev_priv, pipe)
3451 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3453 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3454 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3455 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3456 if (IS_CHERRYVIEW(dev_priv))
3457 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3458 dev_priv->irq_mask &= ~iir_mask;
3460 I915_WRITE(VLV_IIR, iir_mask);
3461 I915_WRITE(VLV_IIR, iir_mask);
3462 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3463 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3464 POSTING_READ(VLV_IMR);
3467 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3473 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3474 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3475 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3476 if (IS_CHERRYVIEW(dev_priv))
3477 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3479 dev_priv->irq_mask |= iir_mask;
3480 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3481 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3482 I915_WRITE(VLV_IIR, iir_mask);
3483 I915_WRITE(VLV_IIR, iir_mask);
3484 POSTING_READ(VLV_IIR);
3486 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3487 PIPE_CRC_DONE_INTERRUPT_STATUS;
3489 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3490 for_each_pipe(dev_priv, pipe)
3491 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3493 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3494 PIPE_FIFO_UNDERRUN_STATUS;
3496 for_each_pipe(dev_priv, pipe)
3497 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3498 POSTING_READ(PIPESTAT(PIPE_A));
3501 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3503 assert_spin_locked(&dev_priv->irq_lock);
3505 if (dev_priv->display_irqs_enabled)
3508 dev_priv->display_irqs_enabled = true;
3510 if (intel_irqs_enabled(dev_priv))
3511 valleyview_display_irqs_install(dev_priv);
3514 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3516 assert_spin_locked(&dev_priv->irq_lock);
3518 if (!dev_priv->display_irqs_enabled)
3521 dev_priv->display_irqs_enabled = false;
3523 if (intel_irqs_enabled(dev_priv))
3524 valleyview_display_irqs_uninstall(dev_priv);
3527 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3529 dev_priv->irq_mask = ~0;
3531 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3532 POSTING_READ(PORT_HOTPLUG_EN);
3534 I915_WRITE(VLV_IIR, 0xffffffff);
3535 I915_WRITE(VLV_IIR, 0xffffffff);
3536 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3537 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3538 POSTING_READ(VLV_IMR);
3540 /* Interrupt setup is already guaranteed to be single-threaded, this is
3541 * just to make the assert_spin_locked check happy. */
3542 spin_lock_irq(&dev_priv->irq_lock);
3543 if (dev_priv->display_irqs_enabled)
3544 valleyview_display_irqs_install(dev_priv);
3545 spin_unlock_irq(&dev_priv->irq_lock);
3548 static int valleyview_irq_postinstall(struct drm_device *dev)
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3552 vlv_display_irq_postinstall(dev_priv);
3554 gen5_gt_irq_postinstall(dev);
3556 /* ack & enable invalid PTE error interrupts */
3557 #if 0 /* FIXME: add support to irq handler for checking these bits */
3558 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3559 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3562 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3567 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3569 /* These are interrupts we'll toggle with the ring mask register */
3570 uint32_t gt_interrupts[] = {
3571 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3572 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3573 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3574 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3575 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3576 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3577 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3578 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3579 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3581 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3582 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3585 dev_priv->pm_irq_mask = 0xffffffff;
3586 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3587 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3589 * RPS interrupts will get enabled/disabled on demand when RPS itself
3590 * is enabled/disabled.
3592 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3593 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3596 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3598 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3599 uint32_t de_pipe_enables;
3600 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3601 u32 de_port_enables;
3604 if (INTEL_INFO(dev_priv)->gen >= 9) {
3605 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3606 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3607 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3609 if (IS_BROXTON(dev_priv))
3610 de_port_masked |= BXT_DE_PORT_GMBUS;
3612 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3613 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3616 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3617 GEN8_PIPE_FIFO_UNDERRUN;
3619 de_port_enables = de_port_masked;
3620 if (IS_BROXTON(dev_priv))
3621 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3622 else if (IS_BROADWELL(dev_priv))
3623 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3625 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3626 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3627 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3629 for_each_pipe(dev_priv, pipe)
3630 if (intel_display_power_is_enabled(dev_priv,
3631 POWER_DOMAIN_PIPE(pipe)))
3632 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3633 dev_priv->de_irq_mask[pipe],
3636 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3639 static int gen8_irq_postinstall(struct drm_device *dev)
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3643 if (HAS_PCH_SPLIT(dev))
3644 ibx_irq_pre_postinstall(dev);
3646 gen8_gt_irq_postinstall(dev_priv);
3647 gen8_de_irq_postinstall(dev_priv);
3649 if (HAS_PCH_SPLIT(dev))
3650 ibx_irq_postinstall(dev);
3652 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3653 POSTING_READ(GEN8_MASTER_IRQ);
3658 static int cherryview_irq_postinstall(struct drm_device *dev)
3660 struct drm_i915_private *dev_priv = dev->dev_private;
3662 vlv_display_irq_postinstall(dev_priv);
3664 gen8_gt_irq_postinstall(dev_priv);
3666 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3667 POSTING_READ(GEN8_MASTER_IRQ);
3672 static void gen8_irq_uninstall(struct drm_device *dev)
3674 struct drm_i915_private *dev_priv = dev->dev_private;
3679 gen8_irq_reset(dev);
3682 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3684 /* Interrupt setup is already guaranteed to be single-threaded, this is
3685 * just to make the assert_spin_locked check happy. */
3686 spin_lock_irq(&dev_priv->irq_lock);
3687 if (dev_priv->display_irqs_enabled)
3688 valleyview_display_irqs_uninstall(dev_priv);
3689 spin_unlock_irq(&dev_priv->irq_lock);
3691 vlv_display_irq_reset(dev_priv);
3693 dev_priv->irq_mask = ~0;
3696 static void valleyview_irq_uninstall(struct drm_device *dev)
3698 struct drm_i915_private *dev_priv = dev->dev_private;
3703 I915_WRITE(VLV_MASTER_IER, 0);
3705 gen5_gt_irq_reset(dev);
3707 I915_WRITE(HWSTAM, 0xffffffff);
3709 vlv_display_irq_uninstall(dev_priv);
3712 static void cherryview_irq_uninstall(struct drm_device *dev)
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3719 I915_WRITE(GEN8_MASTER_IRQ, 0);
3720 POSTING_READ(GEN8_MASTER_IRQ);
3722 gen8_gt_irq_reset(dev_priv);
3724 GEN5_IRQ_RESET(GEN8_PCU_);
3726 vlv_display_irq_uninstall(dev_priv);
3729 static void ironlake_irq_uninstall(struct drm_device *dev)
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3736 ironlake_irq_reset(dev);
3739 static void i8xx_irq_preinstall(struct drm_device * dev)
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3744 for_each_pipe(dev_priv, pipe)
3745 I915_WRITE(PIPESTAT(pipe), 0);
3746 I915_WRITE16(IMR, 0xffff);
3747 I915_WRITE16(IER, 0x0);
3748 POSTING_READ16(IER);
3751 static int i8xx_irq_postinstall(struct drm_device *dev)
3753 struct drm_i915_private *dev_priv = dev->dev_private;
3756 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3758 /* Unmask the interrupts that we always want on. */
3759 dev_priv->irq_mask =
3760 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3761 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3762 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3763 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3764 I915_WRITE16(IMR, dev_priv->irq_mask);
3767 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3768 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3769 I915_USER_INTERRUPT);
3770 POSTING_READ16(IER);
3772 /* Interrupt setup is already guaranteed to be single-threaded, this is
3773 * just to make the assert_spin_locked check happy. */
3774 spin_lock_irq(&dev_priv->irq_lock);
3775 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3776 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3777 spin_unlock_irq(&dev_priv->irq_lock);
3783 * Returns true when a page flip has completed.
3785 static bool i8xx_handle_vblank(struct drm_device *dev,
3786 int plane, int pipe, u32 iir)
3788 struct drm_i915_private *dev_priv = dev->dev_private;
3789 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3791 if (!intel_pipe_handle_vblank(dev, pipe))
3794 if ((iir & flip_pending) == 0)
3795 goto check_page_flip;
3797 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3798 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3799 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3800 * the flip is completed (no longer pending). Since this doesn't raise
3801 * an interrupt per se, we watch for the change at vblank.
3803 if (I915_READ16(ISR) & flip_pending)
3804 goto check_page_flip;
3806 intel_prepare_page_flip(dev, plane);
3807 intel_finish_page_flip(dev, pipe);
3811 intel_check_page_flip(dev, pipe);
3815 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3817 struct drm_device *dev = arg;
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3823 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3824 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3826 if (!intel_irqs_enabled(dev_priv))
3829 iir = I915_READ16(IIR);
3833 while (iir & ~flip_mask) {
3834 /* Can't rely on pipestat interrupt bit in iir as it might
3835 * have been cleared after the pipestat interrupt was received.
3836 * It doesn't set the bit in iir again, but it still produces
3837 * interrupts (for non-MSI).
3839 spin_lock(&dev_priv->irq_lock);
3840 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3841 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3843 for_each_pipe(dev_priv, pipe) {
3844 int reg = PIPESTAT(pipe);
3845 pipe_stats[pipe] = I915_READ(reg);
3848 * Clear the PIPE*STAT regs before the IIR
3850 if (pipe_stats[pipe] & 0x8000ffff)
3851 I915_WRITE(reg, pipe_stats[pipe]);
3853 spin_unlock(&dev_priv->irq_lock);
3855 I915_WRITE16(IIR, iir & ~flip_mask);
3856 new_iir = I915_READ16(IIR); /* Flush posted writes */
3858 if (iir & I915_USER_INTERRUPT)
3859 notify_ring(&dev_priv->ring[RCS]);
3861 for_each_pipe(dev_priv, pipe) {
3866 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3867 i8xx_handle_vblank(dev, plane, pipe, iir))
3868 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3870 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3871 i9xx_pipe_crc_irq_handler(dev, pipe);
3873 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3874 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3884 static void i8xx_irq_uninstall(struct drm_device * dev)
3886 struct drm_i915_private *dev_priv = dev->dev_private;
3889 for_each_pipe(dev_priv, pipe) {
3890 /* Clear enable bits; then clear status bits */
3891 I915_WRITE(PIPESTAT(pipe), 0);
3892 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3894 I915_WRITE16(IMR, 0xffff);
3895 I915_WRITE16(IER, 0x0);
3896 I915_WRITE16(IIR, I915_READ16(IIR));
3899 static void i915_irq_preinstall(struct drm_device * dev)
3901 struct drm_i915_private *dev_priv = dev->dev_private;
3904 if (I915_HAS_HOTPLUG(dev)) {
3905 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3906 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3909 I915_WRITE16(HWSTAM, 0xeffe);
3910 for_each_pipe(dev_priv, pipe)
3911 I915_WRITE(PIPESTAT(pipe), 0);
3912 I915_WRITE(IMR, 0xffffffff);
3913 I915_WRITE(IER, 0x0);
3917 static int i915_irq_postinstall(struct drm_device *dev)
3919 struct drm_i915_private *dev_priv = dev->dev_private;
3922 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3924 /* Unmask the interrupts that we always want on. */
3925 dev_priv->irq_mask =
3926 ~(I915_ASLE_INTERRUPT |
3927 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3928 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3929 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3930 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3933 I915_ASLE_INTERRUPT |
3934 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3935 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3936 I915_USER_INTERRUPT;
3938 if (I915_HAS_HOTPLUG(dev)) {
3939 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3940 POSTING_READ(PORT_HOTPLUG_EN);
3942 /* Enable in IER... */
3943 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3944 /* and unmask in IMR */
3945 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3948 I915_WRITE(IMR, dev_priv->irq_mask);
3949 I915_WRITE(IER, enable_mask);
3952 i915_enable_asle_pipestat(dev);
3954 /* Interrupt setup is already guaranteed to be single-threaded, this is
3955 * just to make the assert_spin_locked check happy. */
3956 spin_lock_irq(&dev_priv->irq_lock);
3957 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3958 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3959 spin_unlock_irq(&dev_priv->irq_lock);
3965 * Returns true when a page flip has completed.
3967 static bool i915_handle_vblank(struct drm_device *dev,
3968 int plane, int pipe, u32 iir)
3970 struct drm_i915_private *dev_priv = dev->dev_private;
3971 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3973 if (!intel_pipe_handle_vblank(dev, pipe))
3976 if ((iir & flip_pending) == 0)
3977 goto check_page_flip;
3979 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3980 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3981 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3982 * the flip is completed (no longer pending). Since this doesn't raise
3983 * an interrupt per se, we watch for the change at vblank.
3985 if (I915_READ(ISR) & flip_pending)
3986 goto check_page_flip;
3988 intel_prepare_page_flip(dev, plane);
3989 intel_finish_page_flip(dev, pipe);
3993 intel_check_page_flip(dev, pipe);
3997 static irqreturn_t i915_irq_handler(int irq, void *arg)
3999 struct drm_device *dev = arg;
4000 struct drm_i915_private *dev_priv = dev->dev_private;
4001 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4003 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4004 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4005 int pipe, ret = IRQ_NONE;
4007 if (!intel_irqs_enabled(dev_priv))
4010 iir = I915_READ(IIR);
4012 bool irq_received = (iir & ~flip_mask) != 0;
4013 bool blc_event = false;
4015 /* Can't rely on pipestat interrupt bit in iir as it might
4016 * have been cleared after the pipestat interrupt was received.
4017 * It doesn't set the bit in iir again, but it still produces
4018 * interrupts (for non-MSI).
4020 spin_lock(&dev_priv->irq_lock);
4021 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4022 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4024 for_each_pipe(dev_priv, pipe) {
4025 int reg = PIPESTAT(pipe);
4026 pipe_stats[pipe] = I915_READ(reg);
4028 /* Clear the PIPE*STAT regs before the IIR */
4029 if (pipe_stats[pipe] & 0x8000ffff) {
4030 I915_WRITE(reg, pipe_stats[pipe]);
4031 irq_received = true;
4034 spin_unlock(&dev_priv->irq_lock);
4039 /* Consume port. Then clear IIR or we'll miss events */
4040 if (I915_HAS_HOTPLUG(dev) &&
4041 iir & I915_DISPLAY_PORT_INTERRUPT)
4042 i9xx_hpd_irq_handler(dev);
4044 I915_WRITE(IIR, iir & ~flip_mask);
4045 new_iir = I915_READ(IIR); /* Flush posted writes */
4047 if (iir & I915_USER_INTERRUPT)
4048 notify_ring(&dev_priv->ring[RCS]);
4050 for_each_pipe(dev_priv, pipe) {
4055 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4056 i915_handle_vblank(dev, plane, pipe, iir))
4057 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4059 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4062 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4063 i9xx_pipe_crc_irq_handler(dev, pipe);
4065 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4066 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4070 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4071 intel_opregion_asle_intr(dev);
4073 /* With MSI, interrupts are only generated when iir
4074 * transitions from zero to nonzero. If another bit got
4075 * set while we were handling the existing iir bits, then
4076 * we would never get another interrupt.
4078 * This is fine on non-MSI as well, as if we hit this path
4079 * we avoid exiting the interrupt handler only to generate
4082 * Note that for MSI this could cause a stray interrupt report
4083 * if an interrupt landed in the time between writing IIR and
4084 * the posting read. This should be rare enough to never
4085 * trigger the 99% of 100,000 interrupts test for disabling
4090 } while (iir & ~flip_mask);
4095 static void i915_irq_uninstall(struct drm_device * dev)
4097 struct drm_i915_private *dev_priv = dev->dev_private;
4100 if (I915_HAS_HOTPLUG(dev)) {
4101 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4102 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4105 I915_WRITE16(HWSTAM, 0xffff);
4106 for_each_pipe(dev_priv, pipe) {
4107 /* Clear enable bits; then clear status bits */
4108 I915_WRITE(PIPESTAT(pipe), 0);
4109 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4111 I915_WRITE(IMR, 0xffffffff);
4112 I915_WRITE(IER, 0x0);
4114 I915_WRITE(IIR, I915_READ(IIR));
4117 static void i965_irq_preinstall(struct drm_device * dev)
4119 struct drm_i915_private *dev_priv = dev->dev_private;
4122 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4123 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4125 I915_WRITE(HWSTAM, 0xeffe);
4126 for_each_pipe(dev_priv, pipe)
4127 I915_WRITE(PIPESTAT(pipe), 0);
4128 I915_WRITE(IMR, 0xffffffff);
4129 I915_WRITE(IER, 0x0);
4133 static int i965_irq_postinstall(struct drm_device *dev)
4135 struct drm_i915_private *dev_priv = dev->dev_private;
4139 /* Unmask the interrupts that we always want on. */
4140 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4141 I915_DISPLAY_PORT_INTERRUPT |
4142 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4143 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4144 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4145 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4146 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4148 enable_mask = ~dev_priv->irq_mask;
4149 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4150 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4151 enable_mask |= I915_USER_INTERRUPT;
4154 enable_mask |= I915_BSD_USER_INTERRUPT;
4156 /* Interrupt setup is already guaranteed to be single-threaded, this is
4157 * just to make the assert_spin_locked check happy. */
4158 spin_lock_irq(&dev_priv->irq_lock);
4159 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4160 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4161 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4162 spin_unlock_irq(&dev_priv->irq_lock);
4165 * Enable some error detection, note the instruction error mask
4166 * bit is reserved, so we leave it masked.
4169 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4170 GM45_ERROR_MEM_PRIV |
4171 GM45_ERROR_CP_PRIV |
4172 I915_ERROR_MEMORY_REFRESH);
4174 error_mask = ~(I915_ERROR_PAGE_TABLE |
4175 I915_ERROR_MEMORY_REFRESH);
4177 I915_WRITE(EMR, error_mask);
4179 I915_WRITE(IMR, dev_priv->irq_mask);
4180 I915_WRITE(IER, enable_mask);
4183 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4184 POSTING_READ(PORT_HOTPLUG_EN);
4186 i915_enable_asle_pipestat(dev);
4191 static void i915_hpd_irq_setup(struct drm_device *dev)
4193 struct drm_i915_private *dev_priv = dev->dev_private;
4196 assert_spin_locked(&dev_priv->irq_lock);
4198 /* Note HDMI and DP share hotplug bits */
4199 /* enable bits are the same for all generations */
4200 hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915);
4201 /* Programming the CRT detection parameters tends
4202 to generate a spurious hotplug event about three
4203 seconds later. So just do it once.
4206 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4207 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4209 /* Ignore TV since it's buggy */
4210 i915_hotplug_interrupt_update_locked(dev_priv,
4211 (HOTPLUG_INT_EN_MASK
4212 | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK),
4216 static irqreturn_t i965_irq_handler(int irq, void *arg)
4218 struct drm_device *dev = arg;
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4221 u32 pipe_stats[I915_MAX_PIPES];
4222 int ret = IRQ_NONE, pipe;
4224 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4225 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4227 if (!intel_irqs_enabled(dev_priv))
4230 iir = I915_READ(IIR);
4233 bool irq_received = (iir & ~flip_mask) != 0;
4234 bool blc_event = false;
4236 /* Can't rely on pipestat interrupt bit in iir as it might
4237 * have been cleared after the pipestat interrupt was received.
4238 * It doesn't set the bit in iir again, but it still produces
4239 * interrupts (for non-MSI).
4241 spin_lock(&dev_priv->irq_lock);
4242 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4243 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4245 for_each_pipe(dev_priv, pipe) {
4246 int reg = PIPESTAT(pipe);
4247 pipe_stats[pipe] = I915_READ(reg);
4250 * Clear the PIPE*STAT regs before the IIR
4252 if (pipe_stats[pipe] & 0x8000ffff) {
4253 I915_WRITE(reg, pipe_stats[pipe]);
4254 irq_received = true;
4257 spin_unlock(&dev_priv->irq_lock);
4264 /* Consume port. Then clear IIR or we'll miss events */
4265 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4266 i9xx_hpd_irq_handler(dev);
4268 I915_WRITE(IIR, iir & ~flip_mask);
4269 new_iir = I915_READ(IIR); /* Flush posted writes */
4271 if (iir & I915_USER_INTERRUPT)
4272 notify_ring(&dev_priv->ring[RCS]);
4273 if (iir & I915_BSD_USER_INTERRUPT)
4274 notify_ring(&dev_priv->ring[VCS]);
4276 for_each_pipe(dev_priv, pipe) {
4277 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4278 i915_handle_vblank(dev, pipe, pipe, iir))
4279 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4281 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4284 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4285 i9xx_pipe_crc_irq_handler(dev, pipe);
4287 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4288 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4291 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4292 intel_opregion_asle_intr(dev);
4294 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4295 gmbus_irq_handler(dev);
4297 /* With MSI, interrupts are only generated when iir
4298 * transitions from zero to nonzero. If another bit got
4299 * set while we were handling the existing iir bits, then
4300 * we would never get another interrupt.
4302 * This is fine on non-MSI as well, as if we hit this path
4303 * we avoid exiting the interrupt handler only to generate
4306 * Note that for MSI this could cause a stray interrupt report
4307 * if an interrupt landed in the time between writing IIR and
4308 * the posting read. This should be rare enough to never
4309 * trigger the 99% of 100,000 interrupts test for disabling
4318 static void i965_irq_uninstall(struct drm_device * dev)
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4326 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4327 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4329 I915_WRITE(HWSTAM, 0xffffffff);
4330 for_each_pipe(dev_priv, pipe)
4331 I915_WRITE(PIPESTAT(pipe), 0);
4332 I915_WRITE(IMR, 0xffffffff);
4333 I915_WRITE(IER, 0x0);
4335 for_each_pipe(dev_priv, pipe)
4336 I915_WRITE(PIPESTAT(pipe),
4337 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4338 I915_WRITE(IIR, I915_READ(IIR));
4342 * intel_irq_init - initializes irq support
4343 * @dev_priv: i915 device instance
4345 * This function initializes all the irq support including work items, timers
4346 * and all the vtables. It does not setup the interrupt itself though.
4348 void intel_irq_init(struct drm_i915_private *dev_priv)
4350 struct drm_device *dev = dev_priv->dev;
4352 intel_hpd_init_work(dev_priv);
4354 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4355 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4357 /* Let's track the enabled rps events */
4358 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4359 /* WaGsvRC0ResidencyMethod:vlv */
4360 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4362 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4364 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4365 i915_hangcheck_elapsed);
4367 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4369 if (IS_GEN2(dev_priv)) {
4370 dev->max_vblank_count = 0;
4371 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4372 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4373 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4374 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4376 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4377 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4381 * Opt out of the vblank disable timer on everything except gen2.
4382 * Gen2 doesn't have a hardware frame counter and so depends on
4383 * vblank interrupts to produce sane vblank seuquence numbers.
4385 if (!IS_GEN2(dev_priv))
4386 dev->vblank_disable_immediate = true;
4388 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4389 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4391 if (IS_CHERRYVIEW(dev_priv)) {
4392 dev->driver->irq_handler = cherryview_irq_handler;
4393 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4394 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4395 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4396 dev->driver->enable_vblank = valleyview_enable_vblank;
4397 dev->driver->disable_vblank = valleyview_disable_vblank;
4398 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4399 } else if (IS_VALLEYVIEW(dev_priv)) {
4400 dev->driver->irq_handler = valleyview_irq_handler;
4401 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4402 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4403 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4404 dev->driver->enable_vblank = valleyview_enable_vblank;
4405 dev->driver->disable_vblank = valleyview_disable_vblank;
4406 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4407 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4408 dev->driver->irq_handler = gen8_irq_handler;
4409 dev->driver->irq_preinstall = gen8_irq_reset;
4410 dev->driver->irq_postinstall = gen8_irq_postinstall;
4411 dev->driver->irq_uninstall = gen8_irq_uninstall;
4412 dev->driver->enable_vblank = gen8_enable_vblank;
4413 dev->driver->disable_vblank = gen8_disable_vblank;
4414 if (IS_BROXTON(dev))
4415 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4416 else if (HAS_PCH_SPT(dev))
4417 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4419 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4420 } else if (HAS_PCH_SPLIT(dev)) {
4421 dev->driver->irq_handler = ironlake_irq_handler;
4422 dev->driver->irq_preinstall = ironlake_irq_reset;
4423 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4424 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4425 dev->driver->enable_vblank = ironlake_enable_vblank;
4426 dev->driver->disable_vblank = ironlake_disable_vblank;
4427 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4429 if (INTEL_INFO(dev_priv)->gen == 2) {
4430 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4431 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4432 dev->driver->irq_handler = i8xx_irq_handler;
4433 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4434 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4435 dev->driver->irq_preinstall = i915_irq_preinstall;
4436 dev->driver->irq_postinstall = i915_irq_postinstall;
4437 dev->driver->irq_uninstall = i915_irq_uninstall;
4438 dev->driver->irq_handler = i915_irq_handler;
4440 dev->driver->irq_preinstall = i965_irq_preinstall;
4441 dev->driver->irq_postinstall = i965_irq_postinstall;
4442 dev->driver->irq_uninstall = i965_irq_uninstall;
4443 dev->driver->irq_handler = i965_irq_handler;
4445 if (I915_HAS_HOTPLUG(dev_priv))
4446 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4447 dev->driver->enable_vblank = i915_enable_vblank;
4448 dev->driver->disable_vblank = i915_disable_vblank;
4453 * intel_irq_install - enables the hardware interrupt
4454 * @dev_priv: i915 device instance
4456 * This function enables the hardware interrupt handling, but leaves the hotplug
4457 * handling still disabled. It is called after intel_irq_init().
4459 * In the driver load and resume code we need working interrupts in a few places
4460 * but don't want to deal with the hassle of concurrent probe and hotplug
4461 * workers. Hence the split into this two-stage approach.
4463 int intel_irq_install(struct drm_i915_private *dev_priv)
4466 * We enable some interrupt sources in our postinstall hooks, so mark
4467 * interrupts as enabled _before_ actually enabling them to avoid
4468 * special cases in our ordering checks.
4470 dev_priv->pm.irqs_enabled = true;
4472 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4476 * intel_irq_uninstall - finilizes all irq handling
4477 * @dev_priv: i915 device instance
4479 * This stops interrupt and hotplug handling and unregisters and frees all
4480 * resources acquired in the init functions.
4482 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4484 drm_irq_uninstall(dev_priv->dev);
4485 intel_hpd_cancel_work(dev_priv);
4486 dev_priv->pm.irqs_enabled = false;
4490 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4491 * @dev_priv: i915 device instance
4493 * This function is used to disable interrupts at runtime, both in the runtime
4494 * pm and the system suspend/resume code.
4496 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4498 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4499 dev_priv->pm.irqs_enabled = false;
4500 synchronize_irq(dev_priv->dev->irq);
4504 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4505 * @dev_priv: i915 device instance
4507 * This function is used to enable interrupts at runtime, both in the runtime
4508 * pm and the system suspend/resume code.
4510 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4512 dev_priv->pm.irqs_enabled = true;
4513 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4514 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);