drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173
 174 /* For display hotplug interrupt */
 175 static inline void
 176 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 177                                      uint32_t mask,
 178                                      uint32_t bits)
 179 {
 180         uint32_t val;
 181
 182         assert_spin_locked(&dev_priv->irq_lock);
 183         WARN_ON(bits & ~mask);
 184
 185         val = I915_READ(PORT_HOTPLUG_EN);
 186         val &= ~mask;
 187         val |= bits;
 188         I915_WRITE(PORT_HOTPLUG_EN, val);
 189 }
 190
 191 /**
 192  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 193  * @dev_priv: driver private
 194  * @mask: bits to update
 195  * @bits: bits to enable
 196  * NOTE: the HPD enable bits are modified both inside and outside
 197  * of an interrupt context. To avoid that read-modify-write cycles
 198  * interfer, these bits are protected by a spinlock. Since this
 199  * function is usually not called from a context where the lock is
 200  * held already, this function acquires the lock itself. A non-locking
 201  * version is also available.
 202  */
 203 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 204                                    uint32_t mask,
 205                                    uint32_t bits)
 206 {
 207         spin_lock_irq(&dev_priv->irq_lock);
 208         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 209         spin_unlock_irq(&dev_priv->irq_lock);
 210 }
 211
 212 /**
 213  * ilk_update_display_irq - update DEIMR
 214  * @dev_priv: driver private
 215  * @interrupt_mask: mask of interrupt bits to update
 216  * @enabled_irq_mask: mask of interrupt bits to enable
 217  */
 218 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 219                             uint32_t interrupt_mask,
 220                             uint32_t enabled_irq_mask)
 221 {
 222         uint32_t new_val;
 223
 224         assert_spin_locked(&dev_priv->irq_lock);
 225
 226         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 227
 228         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 229                 return;
 230
 231         new_val = dev_priv->irq_mask;
 232         new_val &= ~interrupt_mask;
 233         new_val |= (~enabled_irq_mask & interrupt_mask);
 234
 235         if (new_val != dev_priv->irq_mask) {
 236                 dev_priv->irq_mask = new_val;
 237                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 238                 POSTING_READ(DEIMR);
 239         }
 240 }
 241
 242 /**
 243  * ilk_update_gt_irq - update GTIMR
 244  * @dev_priv: driver private
 245  * @interrupt_mask: mask of interrupt bits to update
 246  * @enabled_irq_mask: mask of interrupt bits to enable
 247  */
 248 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 249                               uint32_t interrupt_mask,
 250                               uint32_t enabled_irq_mask)
 251 {
 252         assert_spin_locked(&dev_priv->irq_lock);
 253
 254         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 255
 256         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 257                 return;
 258
 259         dev_priv->gt_irq_mask &= ~interrupt_mask;
 260         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 261         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 262 }
 263
 264 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 265 {
 266         ilk_update_gt_irq(dev_priv, mask, mask);
 267         POSTING_READ_FW(GTIMR);
 268 }
 269
 270 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 271 {
 272         ilk_update_gt_irq(dev_priv, mask, 0);
 273 }
 274
 275 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 276 {
 277         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 278 }
 279
 280 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 281 {
 282         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 283 }
 284
 285 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 286 {
 287         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 288 }
 289
 290 /**
 291  * snb_update_pm_irq - update GEN6_PMIMR
 292  * @dev_priv: driver private
 293  * @interrupt_mask: mask of interrupt bits to update
 294  * @enabled_irq_mask: mask of interrupt bits to enable
 295  */
 296 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 297                               uint32_t interrupt_mask,
 298                               uint32_t enabled_irq_mask)
 299 {
 300         uint32_t new_val;
 301
 302         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 303
 304         assert_spin_locked(&dev_priv->irq_lock);
 305
 306         new_val = dev_priv->pm_irq_mask;
 307         new_val &= ~interrupt_mask;
 308         new_val |= (~enabled_irq_mask & interrupt_mask);
 309
 310         if (new_val != dev_priv->pm_irq_mask) {
 311                 dev_priv->pm_irq_mask = new_val;
 312                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 313                 POSTING_READ(gen6_pm_imr(dev_priv));
 314         }
 315 }
 316
 317 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 318 {
 319         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 320                 return;
 321
 322         snb_update_pm_irq(dev_priv, mask, mask);
 323 }
 324
 325 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 326                                   uint32_t mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_disable_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         spin_lock_irq(&dev_priv->irq_lock);
 344         I915_WRITE(reg, dev_priv->pm_rps_events);
 345         I915_WRITE(reg, dev_priv->pm_rps_events);
 346         POSTING_READ(reg);
 347         dev_priv->rps.pm_iir = 0;
 348         spin_unlock_irq(&dev_priv->irq_lock);
 349 }
 350
 351 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 352 {
 353         spin_lock_irq(&dev_priv->irq_lock);
 354         WARN_ON_ONCE(dev_priv->rps.pm_iir);
 355         WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 356         dev_priv->rps.interrupts_enabled = true;
 357         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 358                                 dev_priv->pm_rps_events);
 359         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 360
 361         spin_unlock_irq(&dev_priv->irq_lock);
 362 }
 363
 364 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 365 {
 366         return (mask & ~dev_priv->rps.pm_intr_keep);
 367 }
 368
 369 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 370 {
 371         spin_lock_irq(&dev_priv->irq_lock);
 372         dev_priv->rps.interrupts_enabled = false;
 373
 374         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 375
 376         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 377         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 378                                 ~dev_priv->pm_rps_events);
 379
 380         spin_unlock_irq(&dev_priv->irq_lock);
 381         synchronize_irq(dev_priv->drm.irq);
 382
 383         /* Now that we will not be generating any more work, flush any
 384          * outsanding tasks. As we are called on the RPS idle path,
 385          * we will reset the GPU to minimum frequencies, so the current
 386          * state of the worker can be discarded.
 387          */
 388         cancel_work_sync(&dev_priv->rps.work);
 389         gen6_reset_rps_interrupts(dev_priv);
 390 }
 391
 392 /**
 393  * bdw_update_port_irq - update DE port interrupt
 394  * @dev_priv: driver private
 395  * @interrupt_mask: mask of interrupt bits to update
 396  * @enabled_irq_mask: mask of interrupt bits to enable
 397  */
 398 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 399                                 uint32_t interrupt_mask,
 400                                 uint32_t enabled_irq_mask)
 401 {
 402         uint32_t new_val;
 403         uint32_t old_val;
 404
 405         assert_spin_locked(&dev_priv->irq_lock);
 406
 407         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 408
 409         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 410                 return;
 411
 412         old_val = I915_READ(GEN8_DE_PORT_IMR);
 413
 414         new_val = old_val;
 415         new_val &= ~interrupt_mask;
 416         new_val |= (~enabled_irq_mask & interrupt_mask);
 417
 418         if (new_val != old_val) {
 419                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 420                 POSTING_READ(GEN8_DE_PORT_IMR);
 421         }
 422 }
 423
 424 /**
 425  * bdw_update_pipe_irq - update DE pipe interrupt
 426  * @dev_priv: driver private
 427  * @pipe: pipe whose interrupt to update
 428  * @interrupt_mask: mask of interrupt bits to update
 429  * @enabled_irq_mask: mask of interrupt bits to enable
 430  */
 431 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 432                          enum pipe pipe,
 433                          uint32_t interrupt_mask,
 434                          uint32_t enabled_irq_mask)
 435 {
 436         uint32_t new_val;
 437
 438         assert_spin_locked(&dev_priv->irq_lock);
 439
 440         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 441
 442         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 443                 return;
 444
 445         new_val = dev_priv->de_irq_mask[pipe];
 446         new_val &= ~interrupt_mask;
 447         new_val |= (~enabled_irq_mask & interrupt_mask);
 448
 449         if (new_val != dev_priv->de_irq_mask[pipe]) {
 450                 dev_priv->de_irq_mask[pipe] = new_val;
 451                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 452                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 453         }
 454 }
 455
 456 /**
 457  * ibx_display_interrupt_update - update SDEIMR
 458  * @dev_priv: driver private
 459  * @interrupt_mask: mask of interrupt bits to update
 460  * @enabled_irq_mask: mask of interrupt bits to enable
 461  */
 462 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 463                                   uint32_t interrupt_mask,
 464                                   uint32_t enabled_irq_mask)
 465 {
 466         uint32_t sdeimr = I915_READ(SDEIMR);
 467         sdeimr &= ~interrupt_mask;
 468         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 469
 470         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 471
 472         assert_spin_locked(&dev_priv->irq_lock);
 473
 474         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 475                 return;
 476
 477         I915_WRITE(SDEIMR, sdeimr);
 478         POSTING_READ(SDEIMR);
 479 }
 480
 481 static void
 482 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 483                        u32 enable_mask, u32 status_mask)
 484 {
 485         i915_reg_t reg = PIPESTAT(pipe);
 486         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 487
 488         assert_spin_locked(&dev_priv->irq_lock);
 489         WARN_ON(!intel_irqs_enabled(dev_priv));
 490
 491         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 492                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 493                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 494                       pipe_name(pipe), enable_mask, status_mask))
 495                 return;
 496
 497         if ((pipestat & enable_mask) == enable_mask)
 498                 return;
 499
 500         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 501
 502         /* Enable the interrupt, clear any pending status */
 503         pipestat |= enable_mask | status_mask;
 504         I915_WRITE(reg, pipestat);
 505         POSTING_READ(reg);
 506 }
 507
 508 static void
 509 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 510                         u32 enable_mask, u32 status_mask)
 511 {
 512         i915_reg_t reg = PIPESTAT(pipe);
 513         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 514
 515         assert_spin_locked(&dev_priv->irq_lock);
 516         WARN_ON(!intel_irqs_enabled(dev_priv));
 517
 518         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 519                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 520                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 521                       pipe_name(pipe), enable_mask, status_mask))
 522                 return;
 523
 524         if ((pipestat & enable_mask) == 0)
 525                 return;
 526
 527         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 528
 529         pipestat &= ~enable_mask;
 530         I915_WRITE(reg, pipestat);
 531         POSTING_READ(reg);
 532 }
 533
 534 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 535 {
 536         u32 enable_mask = status_mask << 16;
 537
 538         /*
 539          * On pipe A we don't support the PSR interrupt yet,
 540          * on pipe B and C the same bit MBZ.
 541          */
 542         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 543                 return 0;
 544         /*
 545          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 546          * A the same bit is for perf counters which we don't use either.
 547          */
 548         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 549                 return 0;
 550
 551         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 552                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 553                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 554         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 555                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 556         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 557                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 558
 559         return enable_mask;
 560 }
 561
 562 void
 563 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 564                      u32 status_mask)
 565 {
 566         u32 enable_mask;
 567
 568         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 569                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 570                                                            status_mask);
 571         else
 572                 enable_mask = status_mask << 16;
 573         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 574 }
 575
 576 void
 577 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 578                       u32 status_mask)
 579 {
 580         u32 enable_mask;
 581
 582         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 583                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 584                                                            status_mask);
 585         else
 586                 enable_mask = status_mask << 16;
 587         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 588 }
 589
 590 /**
 591  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 592  * @dev_priv: i915 device private
 593  */
 594 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 595 {
 596         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 597                 return;
 598
 599         spin_lock_irq(&dev_priv->irq_lock);
 600
 601         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 602         if (INTEL_GEN(dev_priv) >= 4)
 603                 i915_enable_pipestat(dev_priv, PIPE_A,
 604                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 605
 606         spin_unlock_irq(&dev_priv->irq_lock);
 607 }
 608
 609 /*
 610  * This timing diagram depicts the video signal in and
 611  * around the vertical blanking period.
 612  *
 613  * Assumptions about the fictitious mode used in this example:
 614  *  vblank_start >= 3
 615  *  vsync_start = vblank_start + 1
 616  *  vsync_end = vblank_start + 2
 617  *  vtotal = vblank_start + 3
 618  *
 619  *           start of vblank:
 620  *           latch double buffered registers
 621  *           increment frame counter (ctg+)
 622  *           generate start of vblank interrupt (gen4+)
 623  *           |
 624  *           |          frame start:
 625  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 626  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 627  *           |          |
 628  *           |          |  start of vsync:
 629  *           |          |  generate vsync interrupt
 630  *           |          |  |
 631  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 632  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 633  * ----va---> <-----------------vb--------------------> <--------va-------------
 634  *       |          |       <----vs----->                     |
 635  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 636  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 637  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 638  *       |          |                                         |
 639  *       last visible pixel                                   first visible pixel
 640  *                  |                                         increment frame counter (gen3/4)
 641  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 642  *
 643  * x  = horizontal active
 644  * _  = horizontal blanking
 645  * hs = horizontal sync
 646  * va = vertical active
 647  * vb = vertical blanking
 648  * vs = vertical sync
 649  * vbs = vblank_start (number)
 650  *
 651  * Summary:
 652  * - most events happen at the start of horizontal sync
 653  * - frame start happens at the start of horizontal blank, 1-4 lines
 654  *   (depending on PIPECONF settings) after the start of vblank
 655  * - gen3/4 pixel and frame counter are synchronized with the start
 656  *   of horizontal active on the first line of vertical active
 657  */
 658
 659 /* Called from drm generic code, passed a 'crtc', which
 660  * we use as a pipe index
 661  */
 662 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 663 {
 664         struct drm_i915_private *dev_priv = to_i915(dev);
 665         i915_reg_t high_frame, low_frame;
 666         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 667         struct intel_crtc *intel_crtc =
 668                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 669         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 670
 671         htotal = mode->crtc_htotal;
 672         hsync_start = mode->crtc_hsync_start;
 673         vbl_start = mode->crtc_vblank_start;
 674         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 675                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 676
 677         /* Convert to pixel count */
 678         vbl_start *= htotal;
 679
 680         /* Start of vblank event occurs at start of hsync */
 681         vbl_start -= htotal - hsync_start;
 682
 683         high_frame = PIPEFRAME(pipe);
 684         low_frame = PIPEFRAMEPIXEL(pipe);
 685
 686         /*
 687          * High & low register fields aren't synchronized, so make sure
 688          * we get a low value that's stable across two reads of the high
 689          * register.
 690          */
 691         do {
 692                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 693                 low   = I915_READ(low_frame);
 694                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 695         } while (high1 != high2);
 696
 697         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 698         pixel = low & PIPE_PIXEL_MASK;
 699         low >>= PIPE_FRAME_LOW_SHIFT;
 700
 701         /*
 702          * The frame counter increments at beginning of active.
 703          * Cook up a vblank counter by also checking the pixel
 704          * counter against vblank start.
 705          */
 706         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 707 }
 708
 709 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 710 {
 711         struct drm_i915_private *dev_priv = to_i915(dev);
 712
 713         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 714 }
 715
 716 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 717 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 718 {
 719         struct drm_device *dev = crtc->base.dev;
 720         struct drm_i915_private *dev_priv = to_i915(dev);
 721         const struct drm_display_mode *mode = &crtc->base.hwmode;
 722         enum pipe pipe = crtc->pipe;
 723         int position, vtotal;
 724
 725         vtotal = mode->crtc_vtotal;
 726         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 727                 vtotal /= 2;
 728
 729         if (IS_GEN2(dev_priv))
 730                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 731         else
 732                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 733
 734         /*
 735          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 736          * read it just before the start of vblank.  So try it again
 737          * so we don't accidentally end up spanning a vblank frame
 738          * increment, causing the pipe_update_end() code to squak at us.
 739          *
 740          * The nature of this problem means we can't simply check the ISR
 741          * bit and return the vblank start value; nor can we use the scanline
 742          * debug register in the transcoder as it appears to have the same
 743          * problem.  We may need to extend this to include other platforms,
 744          * but so far testing only shows the problem on HSW.
 745          */
 746         if (HAS_DDI(dev_priv) && !position) {
 747                 int i, temp;
 748
 749                 for (i = 0; i < 100; i++) {
 750                         udelay(1);
 751                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 752                                 DSL_LINEMASK_GEN3;
 753                         if (temp != position) {
 754                                 position = temp;
 755                                 break;
 756                         }
 757                 }
 758         }
 759
 760         /*
 761          * See update_scanline_offset() for the details on the
 762          * scanline_offset adjustment.
 763          */
 764         return (position + crtc->scanline_offset) % vtotal;
 765 }
 766
 767 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 768                                     unsigned int flags, int *vpos, int *hpos,
 769                                     ktime_t *stime, ktime_t *etime,
 770                                     const struct drm_display_mode *mode)
 771 {
 772         struct drm_i915_private *dev_priv = to_i915(dev);
 773         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 775         int position;
 776         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 777         bool in_vbl = true;
 778         int ret = 0;
 779         unsigned long irqflags;
 780
 781         if (WARN_ON(!mode->crtc_clock)) {
 782                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 783                                  "pipe %c\n", pipe_name(pipe));
 784                 return 0;
 785         }
 786
 787         htotal = mode->crtc_htotal;
 788         hsync_start = mode->crtc_hsync_start;
 789         vtotal = mode->crtc_vtotal;
 790         vbl_start = mode->crtc_vblank_start;
 791         vbl_end = mode->crtc_vblank_end;
 792
 793         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 794                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 795                 vbl_end /= 2;
 796                 vtotal /= 2;
 797         }
 798
 799         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 800
 801         /*
 802          * Lock uncore.lock, as we will do multiple timing critical raw
 803          * register reads, potentially with preemption disabled, so the
 804          * following code must not block on uncore.lock.
 805          */
 806         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 807
 808         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 809
 810         /* Get optional system timestamp before query. */
 811         if (stime)
 812                 *stime = ktime_get();
 813
 814         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 815                 /* No obvious pixelcount register. Only query vertical
 816                  * scanout position from Display scan line register.
 817                  */
 818                 position = __intel_get_crtc_scanline(intel_crtc);
 819         } else {
 820                 /* Have access to pixelcount since start of frame.
 821                  * We can split this into vertical and horizontal
 822                  * scanout position.
 823                  */
 824                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 825
 826                 /* convert to pixel counts */
 827                 vbl_start *= htotal;
 828                 vbl_end *= htotal;
 829                 vtotal *= htotal;
 830
 831                 /*
 832                  * In interlaced modes, the pixel counter counts all pixels,
 833                  * so one field will have htotal more pixels. In order to avoid
 834                  * the reported position from jumping backwards when the pixel
 835                  * counter is beyond the length of the shorter field, just
 836                  * clamp the position the length of the shorter field. This
 837                  * matches how the scanline counter based position works since
 838                  * the scanline counter doesn't count the two half lines.
 839                  */
 840                 if (position >= vtotal)
 841                         position = vtotal - 1;
 842
 843                 /*
 844                  * Start of vblank interrupt is triggered at start of hsync,
 845                  * just prior to the first active line of vblank. However we
 846                  * consider lines to start at the leading edge of horizontal
 847                  * active. So, should we get here before we've crossed into
 848                  * the horizontal active of the first line in vblank, we would
 849                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 850                  * always add htotal-hsync_start to the current pixel position.
 851                  */
 852                 position = (position + htotal - hsync_start) % vtotal;
 853         }
 854
 855         /* Get optional system timestamp after query. */
 856         if (etime)
 857                 *etime = ktime_get();
 858
 859         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 860
 861         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 862
 863         in_vbl = position >= vbl_start && position < vbl_end;
 864
 865         /*
 866          * While in vblank, position will be negative
 867          * counting up towards 0 at vbl_end. And outside
 868          * vblank, position will be positive counting
 869          * up since vbl_end.
 870          */
 871         if (position >= vbl_start)
 872                 position -= vbl_end;
 873         else
 874                 position += vtotal - vbl_end;
 875
 876         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 877                 *vpos = position;
 878                 *hpos = 0;
 879         } else {
 880                 *vpos = position / htotal;
 881                 *hpos = position - (*vpos * htotal);
 882         }
 883
 884         /* In vblank? */
 885         if (in_vbl)
 886                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 887
 888         return ret;
 889 }
 890
 891 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 892 {
 893         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 894         unsigned long irqflags;
 895         int position;
 896
 897         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 898         position = __intel_get_crtc_scanline(crtc);
 899         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 900
 901         return position;
 902 }
 903
 904 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 905                               int *max_error,
 906                               struct timeval *vblank_time,
 907                               unsigned flags)
 908 {
 909         struct drm_crtc *crtc;
 910
 911         if (pipe >= INTEL_INFO(dev)->num_pipes) {
 912                 DRM_ERROR("Invalid crtc %u\n", pipe);
 913                 return -EINVAL;
 914         }
 915
 916         /* Get drm_crtc to timestamp: */
 917         crtc = intel_get_crtc_for_pipe(dev, pipe);
 918         if (crtc == NULL) {
 919                 DRM_ERROR("Invalid crtc %u\n", pipe);
 920                 return -EINVAL;
 921         }
 922
 923         if (!crtc->hwmode.crtc_clock) {
 924                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 925                 return -EBUSY;
 926         }
 927
 928         /* Helper routine in DRM core does all the work: */
 929         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 930                                                      vblank_time, flags,
 931                                                      &crtc->hwmode);
 932 }
 933
 934 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 935 {
 936         u32 busy_up, busy_down, max_avg, min_avg;
 937         u8 new_delay;
 938
 939         spin_lock(&mchdev_lock);
 940
 941         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 942
 943         new_delay = dev_priv->ips.cur_delay;
 944
 945         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 946         busy_up = I915_READ(RCPREVBSYTUPAVG);
 947         busy_down = I915_READ(RCPREVBSYTDNAVG);
 948         max_avg = I915_READ(RCBMAXAVG);
 949         min_avg = I915_READ(RCBMINAVG);
 950
 951         /* Handle RCS change request from hw */
 952         if (busy_up > max_avg) {
 953                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 954                         new_delay = dev_priv->ips.cur_delay - 1;
 955                 if (new_delay < dev_priv->ips.max_delay)
 956                         new_delay = dev_priv->ips.max_delay;
 957         } else if (busy_down < min_avg) {
 958                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 959                         new_delay = dev_priv->ips.cur_delay + 1;
 960                 if (new_delay > dev_priv->ips.min_delay)
 961                         new_delay = dev_priv->ips.min_delay;
 962         }
 963
 964         if (ironlake_set_drps(dev_priv, new_delay))
 965                 dev_priv->ips.cur_delay = new_delay;
 966
 967         spin_unlock(&mchdev_lock);
 968
 969         return;
 970 }
 971
 972 static void notify_ring(struct intel_engine_cs *engine)
 973 {
 974         smp_store_mb(engine->breadcrumbs.irq_posted, true);
 975         if (intel_engine_wakeup(engine))
 976                 trace_i915_gem_request_notify(engine);
 977 }
 978
 979 static void vlv_c0_read(struct drm_i915_private *dev_priv,
 980                         struct intel_rps_ei *ei)
 981 {
 982         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
 983         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
 984         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
 985 }
 986
 987 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
 988                          const struct intel_rps_ei *old,
 989                          const struct intel_rps_ei *now,
 990                          int threshold)
 991 {
 992         u64 time, c0;
 993         unsigned int mul = 100;
 994
 995         if (old->cz_clock == 0)
 996                 return false;
 997
 998         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
 999                 mul <<= 8;
1000
1001         time = now->cz_clock - old->cz_clock;
1002         time *= threshold * dev_priv->czclk_freq;
1003
1004         /* Workload can be split between render + media, e.g. SwapBuffers
1005          * being blitted in X after being rendered in mesa. To account for
1006          * this we need to combine both engines into our activity counter.
1007          */
1008         c0 = now->render_c0 - old->render_c0;
1009         c0 += now->media_c0 - old->media_c0;
1010         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1011
1012         return c0 >= time;
1013 }
1014
1015 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1016 {
1017         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1018         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1019 }
1020
1021 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1022 {
1023         struct intel_rps_ei now;
1024         u32 events = 0;
1025
1026         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1027                 return 0;
1028
1029         vlv_c0_read(dev_priv, &now);
1030         if (now.cz_clock == 0)
1031                 return 0;
1032
1033         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1034                 if (!vlv_c0_above(dev_priv,
1035                                   &dev_priv->rps.down_ei, &now,
1036                                   dev_priv->rps.down_threshold))
1037                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1038                 dev_priv->rps.down_ei = now;
1039         }
1040
1041         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1042                 if (vlv_c0_above(dev_priv,
1043                                  &dev_priv->rps.up_ei, &now,
1044                                  dev_priv->rps.up_threshold))
1045                         events |= GEN6_PM_RP_UP_THRESHOLD;
1046                 dev_priv->rps.up_ei = now;
1047         }
1048
1049         return events;
1050 }
1051
1052 static bool any_waiters(struct drm_i915_private *dev_priv)
1053 {
1054         struct intel_engine_cs *engine;
1055
1056         for_each_engine(engine, dev_priv)
1057                 if (intel_engine_has_waiter(engine))
1058                         return true;
1059
1060         return false;
1061 }
1062
1063 static void gen6_pm_rps_work(struct work_struct *work)
1064 {
1065         struct drm_i915_private *dev_priv =
1066                 container_of(work, struct drm_i915_private, rps.work);
1067         bool client_boost;
1068         int new_delay, adj, min, max;
1069         u32 pm_iir;
1070
1071         spin_lock_irq(&dev_priv->irq_lock);
1072         /* Speed up work cancelation during disabling rps interrupts. */
1073         if (!dev_priv->rps.interrupts_enabled) {
1074                 spin_unlock_irq(&dev_priv->irq_lock);
1075                 return;
1076         }
1077
1078         pm_iir = dev_priv->rps.pm_iir;
1079         dev_priv->rps.pm_iir = 0;
1080         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1081         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1082         client_boost = dev_priv->rps.client_boost;
1083         dev_priv->rps.client_boost = false;
1084         spin_unlock_irq(&dev_priv->irq_lock);
1085
1086         /* Make sure we didn't queue anything we're not going to process. */
1087         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1088
1089         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1090                 return;
1091
1092         mutex_lock(&dev_priv->rps.hw_lock);
1093
1094         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1095
1096         adj = dev_priv->rps.last_adj;
1097         new_delay = dev_priv->rps.cur_freq;
1098         min = dev_priv->rps.min_freq_softlimit;
1099         max = dev_priv->rps.max_freq_softlimit;
1100         if (client_boost || any_waiters(dev_priv))
1101                 max = dev_priv->rps.max_freq;
1102         if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1103                 new_delay = dev_priv->rps.boost_freq;
1104                 adj = 0;
1105         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1106                 if (adj > 0)
1107                         adj *= 2;
1108                 else /* CHV needs even encode values */
1109                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1110                 /*
1111                  * For better performance, jump directly
1112                  * to RPe if we're below it.
1113                  */
1114                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1115                         new_delay = dev_priv->rps.efficient_freq;
1116                         adj = 0;
1117                 }
1118         } else if (client_boost || any_waiters(dev_priv)) {
1119                 adj = 0;
1120         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1121                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1122                         new_delay = dev_priv->rps.efficient_freq;
1123                 else
1124                         new_delay = dev_priv->rps.min_freq_softlimit;
1125                 adj = 0;
1126         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1127                 if (adj < 0)
1128                         adj *= 2;
1129                 else /* CHV needs even encode values */
1130                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1131         } else { /* unknown event */
1132                 adj = 0;
1133         }
1134
1135         dev_priv->rps.last_adj = adj;
1136
1137         /* sysfs frequency interfaces may have snuck in while servicing the
1138          * interrupt
1139          */
1140         new_delay += adj;
1141         new_delay = clamp_t(int, new_delay, min, max);
1142
1143         intel_set_rps(dev_priv, new_delay);
1144
1145         mutex_unlock(&dev_priv->rps.hw_lock);
1146 }
1147
1148
1149 /**
1150  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1151  * occurred.
1152  * @work: workqueue struct
1153  *
1154  * Doesn't actually do anything except notify userspace. As a consequence of
1155  * this event, userspace should try to remap the bad rows since statistically
1156  * it is likely the same row is more likely to go bad again.
1157  */
1158 static void ivybridge_parity_work(struct work_struct *work)
1159 {
1160         struct drm_i915_private *dev_priv =
1161                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1162         u32 error_status, row, bank, subbank;
1163         char *parity_event[6];
1164         uint32_t misccpctl;
1165         uint8_t slice = 0;
1166
1167         /* We must turn off DOP level clock gating to access the L3 registers.
1168          * In order to prevent a get/put style interface, acquire struct mutex
1169          * any time we access those registers.
1170          */
1171         mutex_lock(&dev_priv->drm.struct_mutex);
1172
1173         /* If we've screwed up tracking, just let the interrupt fire again */
1174         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1175                 goto out;
1176
1177         misccpctl = I915_READ(GEN7_MISCCPCTL);
1178         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1179         POSTING_READ(GEN7_MISCCPCTL);
1180
1181         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1182                 i915_reg_t reg;
1183
1184                 slice--;
1185                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1186                         break;
1187
1188                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1189
1190                 reg = GEN7_L3CDERRST1(slice);
1191
1192                 error_status = I915_READ(reg);
1193                 row = GEN7_PARITY_ERROR_ROW(error_status);
1194                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1195                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1196
1197                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1198                 POSTING_READ(reg);
1199
1200                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1201                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1202                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1203                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1204                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1205                 parity_event[5] = NULL;
1206
1207                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1208                                    KOBJ_CHANGE, parity_event);
1209
1210                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1211                           slice, row, bank, subbank);
1212
1213                 kfree(parity_event[4]);
1214                 kfree(parity_event[3]);
1215                 kfree(parity_event[2]);
1216                 kfree(parity_event[1]);
1217         }
1218
1219         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1220
1221 out:
1222         WARN_ON(dev_priv->l3_parity.which_slice);
1223         spin_lock_irq(&dev_priv->irq_lock);
1224         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1225         spin_unlock_irq(&dev_priv->irq_lock);
1226
1227         mutex_unlock(&dev_priv->drm.struct_mutex);
1228 }
1229
1230 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1231                                                u32 iir)
1232 {
1233         if (!HAS_L3_DPF(dev_priv))
1234                 return;
1235
1236         spin_lock(&dev_priv->irq_lock);
1237         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1238         spin_unlock(&dev_priv->irq_lock);
1239
1240         iir &= GT_PARITY_ERROR(dev_priv);
1241         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1242                 dev_priv->l3_parity.which_slice |= 1 << 1;
1243
1244         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1245                 dev_priv->l3_parity.which_slice |= 1 << 0;
1246
1247         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1248 }
1249
1250 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1251                                u32 gt_iir)
1252 {
1253         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1254                 notify_ring(&dev_priv->engine[RCS]);
1255         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1256                 notify_ring(&dev_priv->engine[VCS]);
1257 }
1258
1259 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1260                                u32 gt_iir)
1261 {
1262         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1263                 notify_ring(&dev_priv->engine[RCS]);
1264         if (gt_iir & GT_BSD_USER_INTERRUPT)
1265                 notify_ring(&dev_priv->engine[VCS]);
1266         if (gt_iir & GT_BLT_USER_INTERRUPT)
1267                 notify_ring(&dev_priv->engine[BCS]);
1268
1269         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1270                       GT_BSD_CS_ERROR_INTERRUPT |
1271                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1272                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1273
1274         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1275                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1276 }
1277
1278 static __always_inline void
1279 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1280 {
1281         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1282                 notify_ring(engine);
1283         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1284                 tasklet_schedule(&engine->irq_tasklet);
1285 }
1286
1287 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1288                                    u32 master_ctl,
1289                                    u32 gt_iir[4])
1290 {
1291         irqreturn_t ret = IRQ_NONE;
1292
1293         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1294                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1295                 if (gt_iir[0]) {
1296                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1297                         ret = IRQ_HANDLED;
1298                 } else
1299                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1300         }
1301
1302         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1303                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1304                 if (gt_iir[1]) {
1305                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1306                         ret = IRQ_HANDLED;
1307                 } else
1308                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1309         }
1310
1311         if (master_ctl & GEN8_GT_VECS_IRQ) {
1312                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1313                 if (gt_iir[3]) {
1314                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1315                         ret = IRQ_HANDLED;
1316                 } else
1317                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1318         }
1319
1320         if (master_ctl & GEN8_GT_PM_IRQ) {
1321                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1322                 if (gt_iir[2] & dev_priv->pm_rps_events) {
1323                         I915_WRITE_FW(GEN8_GT_IIR(2),
1324                                       gt_iir[2] & dev_priv->pm_rps_events);
1325                         ret = IRQ_HANDLED;
1326                 } else
1327                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1328         }
1329
1330         return ret;
1331 }
1332
1333 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1334                                 u32 gt_iir[4])
1335 {
1336         if (gt_iir[0]) {
1337                 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1338                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1339                 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1340                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1341         }
1342
1343         if (gt_iir[1]) {
1344                 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1345                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1346                 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1347                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1348         }
1349
1350         if (gt_iir[3])
1351                 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1352                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1353
1354         if (gt_iir[2] & dev_priv->pm_rps_events)
1355                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1356 }
1357
1358 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1359 {
1360         switch (port) {
1361         case PORT_A:
1362                 return val & PORTA_HOTPLUG_LONG_DETECT;
1363         case PORT_B:
1364                 return val & PORTB_HOTPLUG_LONG_DETECT;
1365         case PORT_C:
1366                 return val & PORTC_HOTPLUG_LONG_DETECT;
1367         default:
1368                 return false;
1369         }
1370 }
1371
1372 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1373 {
1374         switch (port) {
1375         case PORT_E:
1376                 return val & PORTE_HOTPLUG_LONG_DETECT;
1377         default:
1378                 return false;
1379         }
1380 }
1381
1382 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1383 {
1384         switch (port) {
1385         case PORT_A:
1386                 return val & PORTA_HOTPLUG_LONG_DETECT;
1387         case PORT_B:
1388                 return val & PORTB_HOTPLUG_LONG_DETECT;
1389         case PORT_C:
1390                 return val & PORTC_HOTPLUG_LONG_DETECT;
1391         case PORT_D:
1392                 return val & PORTD_HOTPLUG_LONG_DETECT;
1393         default:
1394                 return false;
1395         }
1396 }
1397
1398 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1399 {
1400         switch (port) {
1401         case PORT_A:
1402                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1403         default:
1404                 return false;
1405         }
1406 }
1407
1408 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1409 {
1410         switch (port) {
1411         case PORT_B:
1412                 return val & PORTB_HOTPLUG_LONG_DETECT;
1413         case PORT_C:
1414                 return val & PORTC_HOTPLUG_LONG_DETECT;
1415         case PORT_D:
1416                 return val & PORTD_HOTPLUG_LONG_DETECT;
1417         default:
1418                 return false;
1419         }
1420 }
1421
1422 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1423 {
1424         switch (port) {
1425         case PORT_B:
1426                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1427         case PORT_C:
1428                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1429         case PORT_D:
1430                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1431         default:
1432                 return false;
1433         }
1434 }
1435
1436 /*
1437  * Get a bit mask of pins that have triggered, and which ones may be long.
1438  * This can be called multiple times with the same masks to accumulate
1439  * hotplug detection results from several registers.
1440  *
1441  * Note that the caller is expected to zero out the masks initially.
1442  */
1443 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1444                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1445                              const u32 hpd[HPD_NUM_PINS],
1446                              bool long_pulse_detect(enum port port, u32 val))
1447 {
1448         enum port port;
1449         int i;
1450
1451         for_each_hpd_pin(i) {
1452                 if ((hpd[i] & hotplug_trigger) == 0)
1453                         continue;
1454
1455                 *pin_mask |= BIT(i);
1456
1457                 if (!intel_hpd_pin_to_port(i, &port))
1458                         continue;
1459
1460                 if (long_pulse_detect(port, dig_hotplug_reg))
1461                         *long_mask |= BIT(i);
1462         }
1463
1464         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1465                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1466
1467 }
1468
1469 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1470 {
1471         wake_up_all(&dev_priv->gmbus_wait_queue);
1472 }
1473
1474 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1475 {
1476         wake_up_all(&dev_priv->gmbus_wait_queue);
1477 }
1478
1479 #if defined(CONFIG_DEBUG_FS)
1480 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1481                                          enum pipe pipe,
1482                                          uint32_t crc0, uint32_t crc1,
1483                                          uint32_t crc2, uint32_t crc3,
1484                                          uint32_t crc4)
1485 {
1486         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1487         struct intel_pipe_crc_entry *entry;
1488         int head, tail;
1489
1490         spin_lock(&pipe_crc->lock);
1491
1492         if (!pipe_crc->entries) {
1493                 spin_unlock(&pipe_crc->lock);
1494                 DRM_DEBUG_KMS("spurious interrupt\n");
1495                 return;
1496         }
1497
1498         head = pipe_crc->head;
1499         tail = pipe_crc->tail;
1500
1501         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1502                 spin_unlock(&pipe_crc->lock);
1503                 DRM_ERROR("CRC buffer overflowing\n");
1504                 return;
1505         }
1506
1507         entry = &pipe_crc->entries[head];
1508
1509         entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm,
1510                                                                  pipe);
1511         entry->crc[0] = crc0;
1512         entry->crc[1] = crc1;
1513         entry->crc[2] = crc2;
1514         entry->crc[3] = crc3;
1515         entry->crc[4] = crc4;
1516
1517         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1518         pipe_crc->head = head;
1519
1520         spin_unlock(&pipe_crc->lock);
1521
1522         wake_up_interruptible(&pipe_crc->wq);
1523 }
1524 #else
1525 static inline void
1526 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1527                              enum pipe pipe,
1528                              uint32_t crc0, uint32_t crc1,
1529                              uint32_t crc2, uint32_t crc3,
1530                              uint32_t crc4) {}
1531 #endif
1532
1533
1534 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1535                                      enum pipe pipe)
1536 {
1537         display_pipe_crc_irq_handler(dev_priv, pipe,
1538                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1539                                      0, 0, 0, 0);
1540 }
1541
1542 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1543                                      enum pipe pipe)
1544 {
1545         display_pipe_crc_irq_handler(dev_priv, pipe,
1546                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1547                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1548                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1549                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1550                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1551 }
1552
1553 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1554                                       enum pipe pipe)
1555 {
1556         uint32_t res1, res2;
1557
1558         if (INTEL_GEN(dev_priv) >= 3)
1559                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1560         else
1561                 res1 = 0;
1562
1563         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1564                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1565         else
1566                 res2 = 0;
1567
1568         display_pipe_crc_irq_handler(dev_priv, pipe,
1569                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1570                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1571                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1572                                      res1, res2);
1573 }
1574
1575 /* The RPS events need forcewake, so we add them to a work queue and mask their
1576  * IMR bits until the work is done. Other interrupts can be processed without
1577  * the work queue. */
1578 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1579 {
1580         if (pm_iir & dev_priv->pm_rps_events) {
1581                 spin_lock(&dev_priv->irq_lock);
1582                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1583                 if (dev_priv->rps.interrupts_enabled) {
1584                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1585                         schedule_work(&dev_priv->rps.work);
1586                 }
1587                 spin_unlock(&dev_priv->irq_lock);
1588         }
1589
1590         if (INTEL_INFO(dev_priv)->gen >= 8)
1591                 return;
1592
1593         if (HAS_VEBOX(dev_priv)) {
1594                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1595                         notify_ring(&dev_priv->engine[VECS]);
1596
1597                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1598                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1599         }
1600 }
1601
1602 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1603                                      enum pipe pipe)
1604 {
1605         bool ret;
1606
1607         ret = drm_handle_vblank(&dev_priv->drm, pipe);
1608         if (ret)
1609                 intel_finish_page_flip_mmio(dev_priv, pipe);
1610
1611         return ret;
1612 }
1613
1614 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1615                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1616 {
1617         int pipe;
1618
1619         spin_lock(&dev_priv->irq_lock);
1620
1621         if (!dev_priv->display_irqs_enabled) {
1622                 spin_unlock(&dev_priv->irq_lock);
1623                 return;
1624         }
1625
1626         for_each_pipe(dev_priv, pipe) {
1627                 i915_reg_t reg;
1628                 u32 mask, iir_bit = 0;
1629
1630                 /*
1631                  * PIPESTAT bits get signalled even when the interrupt is
1632                  * disabled with the mask bits, and some of the status bits do
1633                  * not generate interrupts at all (like the underrun bit). Hence
1634                  * we need to be careful that we only handle what we want to
1635                  * handle.
1636                  */
1637
1638                 /* fifo underruns are filterered in the underrun handler. */
1639                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1640
1641                 switch (pipe) {
1642                 case PIPE_A:
1643                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1644                         break;
1645                 case PIPE_B:
1646                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1647                         break;
1648                 case PIPE_C:
1649                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1650                         break;
1651                 }
1652                 if (iir & iir_bit)
1653                         mask |= dev_priv->pipestat_irq_mask[pipe];
1654
1655                 if (!mask)
1656                         continue;
1657
1658                 reg = PIPESTAT(pipe);
1659                 mask |= PIPESTAT_INT_ENABLE_MASK;
1660                 pipe_stats[pipe] = I915_READ(reg) & mask;
1661
1662                 /*
1663                  * Clear the PIPE*STAT regs before the IIR
1664                  */
1665                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1666                                         PIPESTAT_INT_STATUS_MASK))
1667                         I915_WRITE(reg, pipe_stats[pipe]);
1668         }
1669         spin_unlock(&dev_priv->irq_lock);
1670 }
1671
1672 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1673                                             u32 pipe_stats[I915_MAX_PIPES])
1674 {
1675         enum pipe pipe;
1676
1677         for_each_pipe(dev_priv, pipe) {
1678                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1679                     intel_pipe_handle_vblank(dev_priv, pipe))
1680                         intel_check_page_flip(dev_priv, pipe);
1681
1682                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1683                         intel_finish_page_flip_cs(dev_priv, pipe);
1684
1685                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1686                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1687
1688                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1689                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1690         }
1691
1692         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1693                 gmbus_irq_handler(dev_priv);
1694 }
1695
1696 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1697 {
1698         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1699
1700         if (hotplug_status)
1701                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1702
1703         return hotplug_status;
1704 }
1705
1706 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1707                                  u32 hotplug_status)
1708 {
1709         u32 pin_mask = 0, long_mask = 0;
1710
1711         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1712             IS_CHERRYVIEW(dev_priv)) {
1713                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1714
1715                 if (hotplug_trigger) {
1716                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1717                                            hotplug_trigger, hpd_status_g4x,
1718                                            i9xx_port_hotplug_long_detect);
1719
1720                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1721                 }
1722
1723                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1724                         dp_aux_irq_handler(dev_priv);
1725         } else {
1726                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1727
1728                 if (hotplug_trigger) {
1729                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1730                                            hotplug_trigger, hpd_status_i915,
1731                                            i9xx_port_hotplug_long_detect);
1732                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1733                 }
1734         }
1735 }
1736
1737 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1738 {
1739         struct drm_device *dev = arg;
1740         struct drm_i915_private *dev_priv = to_i915(dev);
1741         irqreturn_t ret = IRQ_NONE;
1742
1743         if (!intel_irqs_enabled(dev_priv))
1744                 return IRQ_NONE;
1745
1746         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1747         disable_rpm_wakeref_asserts(dev_priv);
1748
1749         do {
1750                 u32 iir, gt_iir, pm_iir;
1751                 u32 pipe_stats[I915_MAX_PIPES] = {};
1752                 u32 hotplug_status = 0;
1753                 u32 ier = 0;
1754
1755                 gt_iir = I915_READ(GTIIR);
1756                 pm_iir = I915_READ(GEN6_PMIIR);
1757                 iir = I915_READ(VLV_IIR);
1758
1759                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1760                         break;
1761
1762                 ret = IRQ_HANDLED;
1763
1764                 /*
1765                  * Theory on interrupt generation, based on empirical evidence:
1766                  *
1767                  * x = ((VLV_IIR & VLV_IER) ||
1768                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1769                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1770                  *
1771                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1772                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1773                  * guarantee the CPU interrupt will be raised again even if we
1774                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1775                  * bits this time around.
1776                  */
1777                 I915_WRITE(VLV_MASTER_IER, 0);
1778                 ier = I915_READ(VLV_IER);
1779                 I915_WRITE(VLV_IER, 0);
1780
1781                 if (gt_iir)
1782                         I915_WRITE(GTIIR, gt_iir);
1783                 if (pm_iir)
1784                         I915_WRITE(GEN6_PMIIR, pm_iir);
1785
1786                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1787                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1788
1789                 /* Call regardless, as some status bits might not be
1790                  * signalled in iir */
1791                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1792
1793                 /*
1794                  * VLV_IIR is single buffered, and reflects the level
1795                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1796                  */
1797                 if (iir)
1798                         I915_WRITE(VLV_IIR, iir);
1799
1800                 I915_WRITE(VLV_IER, ier);
1801                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1802                 POSTING_READ(VLV_MASTER_IER);
1803
1804                 if (gt_iir)
1805                         snb_gt_irq_handler(dev_priv, gt_iir);
1806                 if (pm_iir)
1807                         gen6_rps_irq_handler(dev_priv, pm_iir);
1808
1809                 if (hotplug_status)
1810                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1811
1812                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1813         } while (0);
1814
1815         enable_rpm_wakeref_asserts(dev_priv);
1816
1817         return ret;
1818 }
1819
1820 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1821 {
1822         struct drm_device *dev = arg;
1823         struct drm_i915_private *dev_priv = to_i915(dev);
1824         irqreturn_t ret = IRQ_NONE;
1825
1826         if (!intel_irqs_enabled(dev_priv))
1827                 return IRQ_NONE;
1828
1829         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1830         disable_rpm_wakeref_asserts(dev_priv);
1831
1832         do {
1833                 u32 master_ctl, iir;
1834                 u32 gt_iir[4] = {};
1835                 u32 pipe_stats[I915_MAX_PIPES] = {};
1836                 u32 hotplug_status = 0;
1837                 u32 ier = 0;
1838
1839                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1840                 iir = I915_READ(VLV_IIR);
1841
1842                 if (master_ctl == 0 && iir == 0)
1843                         break;
1844
1845                 ret = IRQ_HANDLED;
1846
1847                 /*
1848                  * Theory on interrupt generation, based on empirical evidence:
1849                  *
1850                  * x = ((VLV_IIR & VLV_IER) ||
1851                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1852                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1853                  *
1854                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1855                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1856                  * guarantee the CPU interrupt will be raised again even if we
1857                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1858                  * bits this time around.
1859                  */
1860                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1861                 ier = I915_READ(VLV_IER);
1862                 I915_WRITE(VLV_IER, 0);
1863
1864                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1865
1866                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1867                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1868
1869                 /* Call regardless, as some status bits might not be
1870                  * signalled in iir */
1871                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1872
1873                 /*
1874                  * VLV_IIR is single buffered, and reflects the level
1875                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1876                  */
1877                 if (iir)
1878                         I915_WRITE(VLV_IIR, iir);
1879
1880                 I915_WRITE(VLV_IER, ier);
1881                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1882                 POSTING_READ(GEN8_MASTER_IRQ);
1883
1884                 gen8_gt_irq_handler(dev_priv, gt_iir);
1885
1886                 if (hotplug_status)
1887                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1888
1889                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1890         } while (0);
1891
1892         enable_rpm_wakeref_asserts(dev_priv);
1893
1894         return ret;
1895 }
1896
1897 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1898                                 u32 hotplug_trigger,
1899                                 const u32 hpd[HPD_NUM_PINS])
1900 {
1901         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1902
1903         /*
1904          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1905          * unless we touch the hotplug register, even if hotplug_trigger is
1906          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1907          * errors.
1908          */
1909         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1910         if (!hotplug_trigger) {
1911                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1912                         PORTD_HOTPLUG_STATUS_MASK |
1913                         PORTC_HOTPLUG_STATUS_MASK |
1914                         PORTB_HOTPLUG_STATUS_MASK;
1915                 dig_hotplug_reg &= ~mask;
1916         }
1917
1918         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1919         if (!hotplug_trigger)
1920                 return;
1921
1922         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1923                            dig_hotplug_reg, hpd,
1924                            pch_port_hotplug_long_detect);
1925
1926         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1927 }
1928
1929 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1930 {
1931         int pipe;
1932         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1933
1934         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1935
1936         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1937                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1938                                SDE_AUDIO_POWER_SHIFT);
1939                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1940                                  port_name(port));
1941         }
1942
1943         if (pch_iir & SDE_AUX_MASK)
1944                 dp_aux_irq_handler(dev_priv);
1945
1946         if (pch_iir & SDE_GMBUS)
1947                 gmbus_irq_handler(dev_priv);
1948
1949         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1950                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1951
1952         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1953                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1954
1955         if (pch_iir & SDE_POISON)
1956                 DRM_ERROR("PCH poison interrupt\n");
1957
1958         if (pch_iir & SDE_FDI_MASK)
1959                 for_each_pipe(dev_priv, pipe)
1960                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1961                                          pipe_name(pipe),
1962                                          I915_READ(FDI_RX_IIR(pipe)));
1963
1964         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1965                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1966
1967         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1968                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1969
1970         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1971                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1972
1973         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1974                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1975 }
1976
1977 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1978 {
1979         u32 err_int = I915_READ(GEN7_ERR_INT);
1980         enum pipe pipe;
1981
1982         if (err_int & ERR_INT_POISON)
1983                 DRM_ERROR("Poison interrupt\n");
1984
1985         for_each_pipe(dev_priv, pipe) {
1986                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1987                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1988
1989                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1990                         if (IS_IVYBRIDGE(dev_priv))
1991                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1992                         else
1993                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1994                 }
1995         }
1996
1997         I915_WRITE(GEN7_ERR_INT, err_int);
1998 }
1999
2000 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2001 {
2002         u32 serr_int = I915_READ(SERR_INT);
2003
2004         if (serr_int & SERR_INT_POISON)
2005                 DRM_ERROR("PCH poison interrupt\n");
2006
2007         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2008                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2009
2010         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2011                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2012
2013         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2014                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2015
2016         I915_WRITE(SERR_INT, serr_int);
2017 }
2018
2019 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2020 {
2021         int pipe;
2022         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2023
2024         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2025
2026         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2027                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2028                                SDE_AUDIO_POWER_SHIFT_CPT);
2029                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2030                                  port_name(port));
2031         }
2032
2033         if (pch_iir & SDE_AUX_MASK_CPT)
2034                 dp_aux_irq_handler(dev_priv);
2035
2036         if (pch_iir & SDE_GMBUS_CPT)
2037                 gmbus_irq_handler(dev_priv);
2038
2039         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2040                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2041
2042         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2043                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2044
2045         if (pch_iir & SDE_FDI_MASK_CPT)
2046                 for_each_pipe(dev_priv, pipe)
2047                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2048                                          pipe_name(pipe),
2049                                          I915_READ(FDI_RX_IIR(pipe)));
2050
2051         if (pch_iir & SDE_ERROR_CPT)
2052                 cpt_serr_int_handler(dev_priv);
2053 }
2054
2055 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2056 {
2057         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2058                 ~SDE_PORTE_HOTPLUG_SPT;
2059         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2060         u32 pin_mask = 0, long_mask = 0;
2061
2062         if (hotplug_trigger) {
2063                 u32 dig_hotplug_reg;
2064
2065                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2066                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2067
2068                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2069                                    dig_hotplug_reg, hpd_spt,
2070                                    spt_port_hotplug_long_detect);
2071         }
2072
2073         if (hotplug2_trigger) {
2074                 u32 dig_hotplug_reg;
2075
2076                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2077                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2078
2079                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2080                                    dig_hotplug_reg, hpd_spt,
2081                                    spt_port_hotplug2_long_detect);
2082         }
2083
2084         if (pin_mask)
2085                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2086
2087         if (pch_iir & SDE_GMBUS_CPT)
2088                 gmbus_irq_handler(dev_priv);
2089 }
2090
2091 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2092                                 u32 hotplug_trigger,
2093                                 const u32 hpd[HPD_NUM_PINS])
2094 {
2095         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2096
2097         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2098         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2099
2100         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2101                            dig_hotplug_reg, hpd,
2102                            ilk_port_hotplug_long_detect);
2103
2104         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2105 }
2106
2107 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2108                                     u32 de_iir)
2109 {
2110         enum pipe pipe;
2111         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2112
2113         if (hotplug_trigger)
2114                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2115
2116         if (de_iir & DE_AUX_CHANNEL_A)
2117                 dp_aux_irq_handler(dev_priv);
2118
2119         if (de_iir & DE_GSE)
2120                 intel_opregion_asle_intr(dev_priv);
2121
2122         if (de_iir & DE_POISON)
2123                 DRM_ERROR("Poison interrupt\n");
2124
2125         for_each_pipe(dev_priv, pipe) {
2126                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2127                     intel_pipe_handle_vblank(dev_priv, pipe))
2128                         intel_check_page_flip(dev_priv, pipe);
2129
2130                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2131                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2132
2133                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2134                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2135
2136                 /* plane/pipes map 1:1 on ilk+ */
2137                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2138                         intel_finish_page_flip_cs(dev_priv, pipe);
2139         }
2140
2141         /* check event from PCH */
2142         if (de_iir & DE_PCH_EVENT) {
2143                 u32 pch_iir = I915_READ(SDEIIR);
2144
2145                 if (HAS_PCH_CPT(dev_priv))
2146                         cpt_irq_handler(dev_priv, pch_iir);
2147                 else
2148                         ibx_irq_handler(dev_priv, pch_iir);
2149
2150                 /* should clear PCH hotplug event before clear CPU irq */
2151                 I915_WRITE(SDEIIR, pch_iir);
2152         }
2153
2154         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2155                 ironlake_rps_change_irq_handler(dev_priv);
2156 }
2157
2158 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2159                                     u32 de_iir)
2160 {
2161         enum pipe pipe;
2162         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2163
2164         if (hotplug_trigger)
2165                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2166
2167         if (de_iir & DE_ERR_INT_IVB)
2168                 ivb_err_int_handler(dev_priv);
2169
2170         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2171                 dp_aux_irq_handler(dev_priv);
2172
2173         if (de_iir & DE_GSE_IVB)
2174                 intel_opregion_asle_intr(dev_priv);
2175
2176         for_each_pipe(dev_priv, pipe) {
2177                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2178                     intel_pipe_handle_vblank(dev_priv, pipe))
2179                         intel_check_page_flip(dev_priv, pipe);
2180
2181                 /* plane/pipes map 1:1 on ilk+ */
2182                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2183                         intel_finish_page_flip_cs(dev_priv, pipe);
2184         }
2185
2186         /* check event from PCH */
2187         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2188                 u32 pch_iir = I915_READ(SDEIIR);
2189
2190                 cpt_irq_handler(dev_priv, pch_iir);
2191
2192                 /* clear PCH hotplug event before clear CPU irq */
2193                 I915_WRITE(SDEIIR, pch_iir);
2194         }
2195 }
2196
2197 /*
2198  * To handle irqs with the minimum potential races with fresh interrupts, we:
2199  * 1 - Disable Master Interrupt Control.
2200  * 2 - Find the source(s) of the interrupt.
2201  * 3 - Clear the Interrupt Identity bits (IIR).
2202  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2203  * 5 - Re-enable Master Interrupt Control.
2204  */
2205 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2206 {
2207         struct drm_device *dev = arg;
2208         struct drm_i915_private *dev_priv = to_i915(dev);
2209         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2210         irqreturn_t ret = IRQ_NONE;
2211
2212         if (!intel_irqs_enabled(dev_priv))
2213                 return IRQ_NONE;
2214
2215         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2216         disable_rpm_wakeref_asserts(dev_priv);
2217
2218         /* disable master interrupt before clearing iir  */
2219         de_ier = I915_READ(DEIER);
2220         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2221         POSTING_READ(DEIER);
2222
2223         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2224          * interrupts will will be stored on its back queue, and then we'll be
2225          * able to process them after we restore SDEIER (as soon as we restore
2226          * it, we'll get an interrupt if SDEIIR still has something to process
2227          * due to its back queue). */
2228         if (!HAS_PCH_NOP(dev_priv)) {
2229                 sde_ier = I915_READ(SDEIER);
2230                 I915_WRITE(SDEIER, 0);
2231                 POSTING_READ(SDEIER);
2232         }
2233
2234         /* Find, clear, then process each source of interrupt */
2235
2236         gt_iir = I915_READ(GTIIR);
2237         if (gt_iir) {
2238                 I915_WRITE(GTIIR, gt_iir);
2239                 ret = IRQ_HANDLED;
2240                 if (INTEL_GEN(dev_priv) >= 6)
2241                         snb_gt_irq_handler(dev_priv, gt_iir);
2242                 else
2243                         ilk_gt_irq_handler(dev_priv, gt_iir);
2244         }
2245
2246         de_iir = I915_READ(DEIIR);
2247         if (de_iir) {
2248                 I915_WRITE(DEIIR, de_iir);
2249                 ret = IRQ_HANDLED;
2250                 if (INTEL_GEN(dev_priv) >= 7)
2251                         ivb_display_irq_handler(dev_priv, de_iir);
2252                 else
2253                         ilk_display_irq_handler(dev_priv, de_iir);
2254         }
2255
2256         if (INTEL_GEN(dev_priv) >= 6) {
2257                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2258                 if (pm_iir) {
2259                         I915_WRITE(GEN6_PMIIR, pm_iir);
2260                         ret = IRQ_HANDLED;
2261                         gen6_rps_irq_handler(dev_priv, pm_iir);
2262                 }
2263         }
2264
2265         I915_WRITE(DEIER, de_ier);
2266         POSTING_READ(DEIER);
2267         if (!HAS_PCH_NOP(dev_priv)) {
2268                 I915_WRITE(SDEIER, sde_ier);
2269                 POSTING_READ(SDEIER);
2270         }
2271
2272         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2273         enable_rpm_wakeref_asserts(dev_priv);
2274
2275         return ret;
2276 }
2277
2278 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2279                                 u32 hotplug_trigger,
2280                                 const u32 hpd[HPD_NUM_PINS])
2281 {
2282         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2283
2284         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2285         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2286
2287         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2288                            dig_hotplug_reg, hpd,
2289                            bxt_port_hotplug_long_detect);
2290
2291         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2292 }
2293
2294 static irqreturn_t
2295 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2296 {
2297         irqreturn_t ret = IRQ_NONE;
2298         u32 iir;
2299         enum pipe pipe;
2300
2301         if (master_ctl & GEN8_DE_MISC_IRQ) {
2302                 iir = I915_READ(GEN8_DE_MISC_IIR);
2303                 if (iir) {
2304                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2305                         ret = IRQ_HANDLED;
2306                         if (iir & GEN8_DE_MISC_GSE)
2307                                 intel_opregion_asle_intr(dev_priv);
2308                         else
2309                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2310                 }
2311                 else
2312                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2313         }
2314
2315         if (master_ctl & GEN8_DE_PORT_IRQ) {
2316                 iir = I915_READ(GEN8_DE_PORT_IIR);
2317                 if (iir) {
2318                         u32 tmp_mask;
2319                         bool found = false;
2320
2321                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2322                         ret = IRQ_HANDLED;
2323
2324                         tmp_mask = GEN8_AUX_CHANNEL_A;
2325                         if (INTEL_INFO(dev_priv)->gen >= 9)
2326                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2327                                             GEN9_AUX_CHANNEL_C |
2328                                             GEN9_AUX_CHANNEL_D;
2329
2330                         if (iir & tmp_mask) {
2331                                 dp_aux_irq_handler(dev_priv);
2332                                 found = true;
2333                         }
2334
2335                         if (IS_BROXTON(dev_priv)) {
2336                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2337                                 if (tmp_mask) {
2338                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2339                                                             hpd_bxt);
2340                                         found = true;
2341                                 }
2342                         } else if (IS_BROADWELL(dev_priv)) {
2343                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2344                                 if (tmp_mask) {
2345                                         ilk_hpd_irq_handler(dev_priv,
2346                                                             tmp_mask, hpd_bdw);
2347                                         found = true;
2348                                 }
2349                         }
2350
2351                         if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2352                                 gmbus_irq_handler(dev_priv);
2353                                 found = true;
2354                         }
2355
2356                         if (!found)
2357                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2358                 }
2359                 else
2360                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2361         }
2362
2363         for_each_pipe(dev_priv, pipe) {
2364                 u32 flip_done, fault_errors;
2365
2366                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2367                         continue;
2368
2369                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2370                 if (!iir) {
2371                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2372                         continue;
2373                 }
2374
2375                 ret = IRQ_HANDLED;
2376                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2377
2378                 if (iir & GEN8_PIPE_VBLANK &&
2379                     intel_pipe_handle_vblank(dev_priv, pipe))
2380                         intel_check_page_flip(dev_priv, pipe);
2381
2382                 flip_done = iir;
2383                 if (INTEL_INFO(dev_priv)->gen >= 9)
2384                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2385                 else
2386                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2387
2388                 if (flip_done)
2389                         intel_finish_page_flip_cs(dev_priv, pipe);
2390
2391                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2392                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2393
2394                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2395                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2396
2397                 fault_errors = iir;
2398                 if (INTEL_INFO(dev_priv)->gen >= 9)
2399                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2400                 else
2401                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2402
2403                 if (fault_errors)
2404                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2405                                   pipe_name(pipe),
2406                                   fault_errors);
2407         }
2408
2409         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2410             master_ctl & GEN8_DE_PCH_IRQ) {
2411                 /*
2412                  * FIXME(BDW): Assume for now that the new interrupt handling
2413                  * scheme also closed the SDE interrupt handling race we've seen
2414                  * on older pch-split platforms. But this needs testing.
2415                  */
2416                 iir = I915_READ(SDEIIR);
2417                 if (iir) {
2418                         I915_WRITE(SDEIIR, iir);
2419                         ret = IRQ_HANDLED;
2420
2421                         if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2422                                 spt_irq_handler(dev_priv, iir);
2423                         else
2424                                 cpt_irq_handler(dev_priv, iir);
2425                 } else {
2426                         /*
2427                          * Like on previous PCH there seems to be something
2428                          * fishy going on with forwarding PCH interrupts.
2429                          */
2430                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2431                 }
2432         }
2433
2434         return ret;
2435 }
2436
2437 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2438 {
2439         struct drm_device *dev = arg;
2440         struct drm_i915_private *dev_priv = to_i915(dev);
2441         u32 master_ctl;
2442         u32 gt_iir[4] = {};
2443         irqreturn_t ret;
2444
2445         if (!intel_irqs_enabled(dev_priv))
2446                 return IRQ_NONE;
2447
2448         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2449         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2450         if (!master_ctl)
2451                 return IRQ_NONE;
2452
2453         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2454
2455         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2456         disable_rpm_wakeref_asserts(dev_priv);
2457
2458         /* Find, clear, then process each source of interrupt */
2459         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2460         gen8_gt_irq_handler(dev_priv, gt_iir);
2461         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2462
2463         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2464         POSTING_READ_FW(GEN8_MASTER_IRQ);
2465
2466         enable_rpm_wakeref_asserts(dev_priv);
2467
2468         return ret;
2469 }
2470
2471 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2472 {
2473         /*
2474          * Notify all waiters for GPU completion events that reset state has
2475          * been changed, and that they need to restart their wait after
2476          * checking for potential errors (and bail out to drop locks if there is
2477          * a gpu reset pending so that i915_error_work_func can acquire them).
2478          */
2479
2480         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2481         wake_up_all(&dev_priv->gpu_error.wait_queue);
2482
2483         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2484         wake_up_all(&dev_priv->pending_flip_queue);
2485 }
2486
2487 /**
2488  * i915_reset_and_wakeup - do process context error handling work
2489  * @dev_priv: i915 device private
2490  *
2491  * Fire an error uevent so userspace can see that a hang or error
2492  * was detected.
2493  */
2494 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2495 {
2496         struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2497         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2498         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2499         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2500
2501         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2502
2503         DRM_DEBUG_DRIVER("resetting chip\n");
2504         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2505
2506         /*
2507          * In most cases it's guaranteed that we get here with an RPM
2508          * reference held, for example because there is a pending GPU
2509          * request that won't finish until the reset is done. This
2510          * isn't the case at least when we get here by doing a
2511          * simulated reset via debugs, so get an RPM reference.
2512          */
2513         intel_runtime_pm_get(dev_priv);
2514         intel_prepare_reset(dev_priv);
2515
2516         do {
2517                 /*
2518                  * All state reset _must_ be completed before we update the
2519                  * reset counter, for otherwise waiters might miss the reset
2520                  * pending state and not properly drop locks, resulting in
2521                  * deadlocks with the reset work.
2522                  */
2523                 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2524                         i915_reset(dev_priv);
2525                         mutex_unlock(&dev_priv->drm.struct_mutex);
2526                 }
2527
2528                 /* We need to wait for anyone holding the lock to wakeup */
2529         } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2530                                      I915_RESET_IN_PROGRESS,
2531                                      TASK_UNINTERRUPTIBLE,
2532                                      HZ));
2533
2534         intel_finish_reset(dev_priv);
2535         intel_runtime_pm_put(dev_priv);
2536
2537         if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2538                 kobject_uevent_env(kobj,
2539                                    KOBJ_CHANGE, reset_done_event);
2540
2541         /*
2542          * Note: The wake_up also serves as a memory barrier so that
2543          * waiters see the updated value of the dev_priv->gpu_error.
2544          */
2545         wake_up_all(&dev_priv->gpu_error.reset_queue);
2546 }
2547
2548 static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2549 {
2550         uint32_t instdone[I915_NUM_INSTDONE_REG];
2551         u32 eir = I915_READ(EIR);
2552         int pipe, i;
2553
2554         if (!eir)
2555                 return;
2556
2557         pr_err("render error detected, EIR: 0x%08x\n", eir);
2558
2559         i915_get_extra_instdone(dev_priv, instdone);
2560
2561         if (IS_G4X(dev_priv)) {
2562                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2563                         u32 ipeir = I915_READ(IPEIR_I965);
2564
2565                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2566                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2567                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2568                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2569                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2570                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2571                         I915_WRITE(IPEIR_I965, ipeir);
2572                         POSTING_READ(IPEIR_I965);
2573                 }
2574                 if (eir & GM45_ERROR_PAGE_TABLE) {
2575                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2576                         pr_err("page table error\n");
2577                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2578                         I915_WRITE(PGTBL_ER, pgtbl_err);
2579                         POSTING_READ(PGTBL_ER);
2580                 }
2581         }
2582
2583         if (!IS_GEN2(dev_priv)) {
2584                 if (eir & I915_ERROR_PAGE_TABLE) {
2585                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2586                         pr_err("page table error\n");
2587                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2588                         I915_WRITE(PGTBL_ER, pgtbl_err);
2589                         POSTING_READ(PGTBL_ER);
2590                 }
2591         }
2592
2593         if (eir & I915_ERROR_MEMORY_REFRESH) {
2594                 pr_err("memory refresh error:\n");
2595                 for_each_pipe(dev_priv, pipe)
2596                         pr_err("pipe %c stat: 0x%08x\n",
2597                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2598                 /* pipestat has already been acked */
2599         }
2600         if (eir & I915_ERROR_INSTRUCTION) {
2601                 pr_err("instruction error\n");
2602                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2603                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2604                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2605                 if (INTEL_GEN(dev_priv) < 4) {
2606                         u32 ipeir = I915_READ(IPEIR);
2607
2608                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2609                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2610                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2611                         I915_WRITE(IPEIR, ipeir);
2612                         POSTING_READ(IPEIR);
2613                 } else {
2614                         u32 ipeir = I915_READ(IPEIR_I965);
2615
2616                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2617                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2618                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2619                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2620                         I915_WRITE(IPEIR_I965, ipeir);
2621                         POSTING_READ(IPEIR_I965);
2622                 }
2623         }
2624
2625         I915_WRITE(EIR, eir);
2626         POSTING_READ(EIR);
2627         eir = I915_READ(EIR);
2628         if (eir) {
2629                 /*
2630                  * some errors might have become stuck,
2631                  * mask them.
2632                  */
2633                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2634                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2635                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2636         }
2637 }
2638
2639 /**
2640  * i915_handle_error - handle a gpu error
2641  * @dev_priv: i915 device private
2642  * @engine_mask: mask representing engines that are hung
2643  * Do some basic checking of register state at error time and
2644  * dump it to the syslog.  Also call i915_capture_error_state() to make
2645  * sure we get a record and make it available in debugfs.  Fire a uevent
2646  * so userspace knows something bad happened (should trigger collection
2647  * of a ring dump etc.).
2648  * @fmt: Error message format string
2649  */
2650 void i915_handle_error(struct drm_i915_private *dev_priv,
2651                        u32 engine_mask,
2652                        const char *fmt, ...)
2653 {
2654         va_list args;
2655         char error_msg[80];
2656
2657         va_start(args, fmt);
2658         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2659         va_end(args);
2660
2661         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2662         i915_report_and_clear_eir(dev_priv);
2663
2664         if (!engine_mask)
2665                 return;
2666
2667         if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2668                              &dev_priv->gpu_error.flags))
2669                 return;
2670
2671         /*
2672          * Wakeup waiting processes so that the reset function
2673          * i915_reset_and_wakeup doesn't deadlock trying to grab
2674          * various locks. By bumping the reset counter first, the woken
2675          * processes will see a reset in progress and back off,
2676          * releasing their locks and then wait for the reset completion.
2677          * We must do this for _all_ gpu waiters that might hold locks
2678          * that the reset work needs to acquire.
2679          *
2680          * Note: The wake_up also provides a memory barrier to ensure that the
2681          * waiters see the updated value of the reset flags.
2682          */
2683         i915_error_wake_up(dev_priv);
2684
2685         i915_reset_and_wakeup(dev_priv);
2686 }
2687
2688 /* Called from drm generic code, passed 'crtc' which
2689  * we use as a pipe index
2690  */
2691 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2692 {
2693         struct drm_i915_private *dev_priv = to_i915(dev);
2694         unsigned long irqflags;
2695
2696         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2697         if (INTEL_INFO(dev)->gen >= 4)
2698                 i915_enable_pipestat(dev_priv, pipe,
2699                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2700         else
2701                 i915_enable_pipestat(dev_priv, pipe,
2702                                      PIPE_VBLANK_INTERRUPT_STATUS);
2703         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2704
2705         return 0;
2706 }
2707
2708 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2709 {
2710         struct drm_i915_private *dev_priv = to_i915(dev);
2711         unsigned long irqflags;
2712         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2713                                                      DE_PIPE_VBLANK(pipe);
2714
2715         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2716         ilk_enable_display_irq(dev_priv, bit);
2717         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2718
2719         return 0;
2720 }
2721
2722 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2723 {
2724         struct drm_i915_private *dev_priv = to_i915(dev);
2725         unsigned long irqflags;
2726
2727         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2728         i915_enable_pipestat(dev_priv, pipe,
2729                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2730         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2731
2732         return 0;
2733 }
2734
2735 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2736 {
2737         struct drm_i915_private *dev_priv = to_i915(dev);
2738         unsigned long irqflags;
2739
2740         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2741         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2742         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2743
2744         return 0;
2745 }
2746
2747 /* Called from drm generic code, passed 'crtc' which
2748  * we use as a pipe index
2749  */
2750 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2751 {
2752         struct drm_i915_private *dev_priv = to_i915(dev);
2753         unsigned long irqflags;
2754
2755         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2756         i915_disable_pipestat(dev_priv, pipe,
2757                               PIPE_VBLANK_INTERRUPT_STATUS |
2758                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2759         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2760 }
2761
2762 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2763 {
2764         struct drm_i915_private *dev_priv = to_i915(dev);
2765         unsigned long irqflags;
2766         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2767                                                      DE_PIPE_VBLANK(pipe);
2768
2769         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2770         ilk_disable_display_irq(dev_priv, bit);
2771         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2772 }
2773
2774 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2775 {
2776         struct drm_i915_private *dev_priv = to_i915(dev);
2777         unsigned long irqflags;
2778
2779         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2780         i915_disable_pipestat(dev_priv, pipe,
2781                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2782         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2783 }
2784
2785 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2786 {
2787         struct drm_i915_private *dev_priv = to_i915(dev);
2788         unsigned long irqflags;
2789
2790         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2791         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2792         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2793 }
2794
2795 static bool
2796 ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2797 {
2798         if (INTEL_GEN(engine->i915) >= 8) {
2799                 return (ipehr >> 23) == 0x1c;
2800         } else {
2801                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2802                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2803                                  MI_SEMAPHORE_REGISTER);
2804         }
2805 }
2806
2807 static struct intel_engine_cs *
2808 semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2809                                  u64 offset)
2810 {
2811         struct drm_i915_private *dev_priv = engine->i915;
2812         struct intel_engine_cs *signaller;
2813
2814         if (INTEL_GEN(dev_priv) >= 8) {
2815                 for_each_engine(signaller, dev_priv) {
2816                         if (engine == signaller)
2817                                 continue;
2818
2819                         if (offset == signaller->semaphore.signal_ggtt[engine->id])
2820                                 return signaller;
2821                 }
2822         } else {
2823                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2824
2825                 for_each_engine(signaller, dev_priv) {
2826                         if(engine == signaller)
2827                                 continue;
2828
2829                         if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2830                                 return signaller;
2831                 }
2832         }
2833
2834         DRM_DEBUG_DRIVER("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2835                          engine->id, ipehr, offset);
2836
2837         return ERR_PTR(-ENODEV);
2838 }
2839
2840 static struct intel_engine_cs *
2841 semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2842 {
2843         struct drm_i915_private *dev_priv = engine->i915;
2844         void __iomem *vaddr;
2845         u32 cmd, ipehr, head;
2846         u64 offset = 0;
2847         int i, backwards;
2848
2849         /*
2850          * This function does not support execlist mode - any attempt to
2851          * proceed further into this function will result in a kernel panic
2852          * when dereferencing ring->buffer, which is not set up in execlist
2853          * mode.
2854          *
2855          * The correct way of doing it would be to derive the currently
2856          * executing ring buffer from the current context, which is derived
2857          * from the currently running request. Unfortunately, to get the
2858          * current request we would have to grab the struct_mutex before doing
2859          * anything else, which would be ill-advised since some other thread
2860          * might have grabbed it already and managed to hang itself, causing
2861          * the hang checker to deadlock.
2862          *
2863          * Therefore, this function does not support execlist mode in its
2864          * current form. Just return NULL and move on.
2865          */
2866         if (engine->buffer == NULL)
2867                 return NULL;
2868
2869         ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2870         if (!ipehr_is_semaphore_wait(engine, ipehr))
2871                 return NULL;
2872
2873         /*
2874          * HEAD is likely pointing to the dword after the actual command,
2875          * so scan backwards until we find the MBOX. But limit it to just 3
2876          * or 4 dwords depending on the semaphore wait command size.
2877          * Note that we don't care about ACTHD here since that might
2878          * point at at batch, and semaphores are always emitted into the
2879          * ringbuffer itself.
2880          */
2881         head = I915_READ_HEAD(engine) & HEAD_ADDR;
2882         backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2883         vaddr = (void __iomem *)engine->buffer->vaddr;
2884
2885         for (i = backwards; i; --i) {
2886                 /*
2887                  * Be paranoid and presume the hw has gone off into the wild -
2888                  * our ring is smaller than what the hardware (and hence
2889                  * HEAD_ADDR) allows. Also handles wrap-around.
2890                  */
2891                 head &= engine->buffer->size - 1;
2892
2893                 /* This here seems to blow up */
2894                 cmd = ioread32(vaddr + head);
2895                 if (cmd == ipehr)
2896                         break;
2897
2898                 head -= 4;
2899         }
2900
2901         if (!i)
2902                 return NULL;
2903
2904         *seqno = ioread32(vaddr + head + 4) + 1;
2905         if (INTEL_GEN(dev_priv) >= 8) {
2906                 offset = ioread32(vaddr + head + 12);
2907                 offset <<= 32;
2908                 offset |= ioread32(vaddr + head + 8);
2909         }
2910         return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2911 }
2912
2913 static int semaphore_passed(struct intel_engine_cs *engine)
2914 {
2915         struct drm_i915_private *dev_priv = engine->i915;
2916         struct intel_engine_cs *signaller;
2917         u32 seqno;
2918
2919         engine->hangcheck.deadlock++;
2920
2921         signaller = semaphore_waits_for(engine, &seqno);
2922         if (signaller == NULL)
2923                 return -1;
2924
2925         if (IS_ERR(signaller))
2926                 return 0;
2927
2928         /* Prevent pathological recursion due to driver bugs */
2929         if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2930                 return -1;
2931
2932         if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
2933                 return 1;
2934
2935         /* cursory check for an unkickable deadlock */
2936         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2937             semaphore_passed(signaller) < 0)
2938                 return -1;
2939
2940         return 0;
2941 }
2942
2943 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2944 {
2945         struct intel_engine_cs *engine;
2946
2947         for_each_engine(engine, dev_priv)
2948                 engine->hangcheck.deadlock = 0;
2949 }
2950
2951 static bool subunits_stuck(struct intel_engine_cs *engine)
2952 {
2953         u32 instdone[I915_NUM_INSTDONE_REG];
2954         bool stuck;
2955         int i;
2956
2957         if (engine->id != RCS)
2958                 return true;
2959
2960         i915_get_extra_instdone(engine->i915, instdone);
2961
2962         /* There might be unstable subunit states even when
2963          * actual head is not moving. Filter out the unstable ones by
2964          * accumulating the undone -> done transitions and only
2965          * consider those as progress.
2966          */
2967         stuck = true;
2968         for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2969                 const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
2970
2971                 if (tmp != engine->hangcheck.instdone[i])
2972                         stuck = false;
2973
2974                 engine->hangcheck.instdone[i] |= tmp;
2975         }
2976
2977         return stuck;
2978 }
2979
2980 static enum intel_engine_hangcheck_action
2981 head_stuck(struct intel_engine_cs *engine, u64 acthd)
2982 {
2983         if (acthd != engine->hangcheck.acthd) {
2984
2985                 /* Clear subunit states on head movement */
2986                 memset(engine->hangcheck.instdone, 0,
2987                        sizeof(engine->hangcheck.instdone));
2988
2989                 return HANGCHECK_ACTIVE;
2990         }
2991
2992         if (!subunits_stuck(engine))
2993                 return HANGCHECK_ACTIVE;
2994
2995         return HANGCHECK_HUNG;
2996 }
2997
2998 static enum intel_engine_hangcheck_action
2999 engine_stuck(struct intel_engine_cs *engine, u64 acthd)
3000 {
3001         struct drm_i915_private *dev_priv = engine->i915;
3002         enum intel_engine_hangcheck_action ha;
3003         u32 tmp;
3004
3005         ha = head_stuck(engine, acthd);
3006         if (ha != HANGCHECK_HUNG)
3007                 return ha;
3008
3009         if (IS_GEN2(dev_priv))
3010                 return HANGCHECK_HUNG;
3011
3012         /* Is the chip hanging on a WAIT_FOR_EVENT?
3013          * If so we can simply poke the RB_WAIT bit
3014          * and break the hang. This should work on
3015          * all but the second generation chipsets.
3016          */
3017         tmp = I915_READ_CTL(engine);
3018         if (tmp & RING_WAIT) {
3019                 i915_handle_error(dev_priv, 0,
3020                                   "Kicking stuck wait on %s",
3021                                   engine->name);
3022                 I915_WRITE_CTL(engine, tmp);
3023                 return HANGCHECK_KICK;
3024         }
3025
3026         if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3027                 switch (semaphore_passed(engine)) {
3028                 default:
3029                         return HANGCHECK_HUNG;
3030                 case 1:
3031                         i915_handle_error(dev_priv, 0,
3032                                           "Kicking stuck semaphore on %s",
3033                                           engine->name);
3034                         I915_WRITE_CTL(engine, tmp);
3035                         return HANGCHECK_KICK;
3036                 case 0:
3037                         return HANGCHECK_WAIT;
3038                 }
3039         }
3040
3041         return HANGCHECK_HUNG;
3042 }
3043
3044 /*
3045  * This is called when the chip hasn't reported back with completed
3046  * batchbuffers in a long time. We keep track per ring seqno progress and
3047  * if there are no progress, hangcheck score for that ring is increased.
3048  * Further, acthd is inspected to see if the ring is stuck. On stuck case
3049  * we kick the ring. If we see no progress on three subsequent calls
3050  * we assume chip is wedged and try to fix it by resetting the chip.
3051  */
3052 static void i915_hangcheck_elapsed(struct work_struct *work)
3053 {
3054         struct drm_i915_private *dev_priv =
3055                 container_of(work, typeof(*dev_priv),
3056                              gpu_error.hangcheck_work.work);
3057         struct intel_engine_cs *engine;
3058         unsigned int hung = 0, stuck = 0;
3059         int busy_count = 0;
3060 #define BUSY 1
3061 #define KICK 5
3062 #define HUNG 20
3063 #define ACTIVE_DECAY 15
3064
3065         if (!i915.enable_hangcheck)
3066                 return;
3067
3068         if (!READ_ONCE(dev_priv->gt.awake))
3069                 return;
3070
3071         /* As enabling the GPU requires fairly extensive mmio access,
3072          * periodically arm the mmio checker to see if we are triggering
3073          * any invalid access.
3074          */
3075         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3076
3077         for_each_engine(engine, dev_priv) {
3078                 bool busy = intel_engine_has_waiter(engine);
3079                 u64 acthd;
3080                 u32 seqno;
3081                 u32 submit;
3082
3083                 semaphore_clear_deadlocks(dev_priv);
3084
3085                 /* We don't strictly need an irq-barrier here, as we are not
3086                  * serving an interrupt request, be paranoid in case the
3087                  * barrier has side-effects (such as preventing a broken
3088                  * cacheline snoop) and so be sure that we can see the seqno
3089                  * advance. If the seqno should stick, due to a stale
3090                  * cacheline, we would erroneously declare the GPU hung.
3091                  */
3092                 if (engine->irq_seqno_barrier)
3093                         engine->irq_seqno_barrier(engine);
3094
3095                 acthd = intel_engine_get_active_head(engine);
3096                 seqno = intel_engine_get_seqno(engine);
3097                 submit = READ_ONCE(engine->last_submitted_seqno);
3098
3099                 if (engine->hangcheck.seqno == seqno) {
3100                         if (i915_seqno_passed(seqno, submit)) {
3101                                 engine->hangcheck.action = HANGCHECK_IDLE;
3102                         } else {
3103                                 /* We always increment the hangcheck score
3104                                  * if the engine is busy and still processing
3105                                  * the same request, so that no single request
3106                                  * can run indefinitely (such as a chain of
3107                                  * batches). The only time we do not increment
3108                                  * the hangcheck score on this ring, if this
3109                                  * engine is in a legitimate wait for another
3110                                  * engine. In that case the waiting engine is a
3111                                  * victim and we want to be sure we catch the
3112                                  * right culprit. Then every time we do kick
3113                                  * the ring, add a small increment to the
3114                                  * score so that we can catch a batch that is
3115                                  * being repeatedly kicked and so responsible
3116                                  * for stalling the machine.
3117                                  */
3118                                 engine->hangcheck.action =
3119                                         engine_stuck(engine, acthd);
3120
3121                                 switch (engine->hangcheck.action) {
3122                                 case HANGCHECK_IDLE:
3123                                 case HANGCHECK_WAIT:
3124                                         break;
3125                                 case HANGCHECK_ACTIVE:
3126                                         engine->hangcheck.score += BUSY;
3127                                         break;
3128                                 case HANGCHECK_KICK:
3129                                         engine->hangcheck.score += KICK;
3130                                         break;
3131                                 case HANGCHECK_HUNG:
3132                                         engine->hangcheck.score += HUNG;
3133                                         break;
3134                                 }
3135                         }
3136
3137                         if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3138                                 hung |= intel_engine_flag(engine);
3139                                 if (engine->hangcheck.action != HANGCHECK_HUNG)
3140                                         stuck |= intel_engine_flag(engine);
3141                         }
3142                 } else {
3143                         engine->hangcheck.action = HANGCHECK_ACTIVE;
3144
3145                         /* Gradually reduce the count so that we catch DoS
3146                          * attempts across multiple batches.
3147                          */
3148                         if (engine->hangcheck.score > 0)
3149                                 engine->hangcheck.score -= ACTIVE_DECAY;
3150                         if (engine->hangcheck.score < 0)
3151                                 engine->hangcheck.score = 0;
3152
3153                         /* Clear head and subunit states on seqno movement */
3154                         acthd = 0;
3155
3156                         memset(engine->hangcheck.instdone, 0,
3157                                sizeof(engine->hangcheck.instdone));
3158                 }
3159
3160                 engine->hangcheck.seqno = seqno;
3161                 engine->hangcheck.acthd = acthd;
3162                 busy_count += busy;
3163         }
3164
3165         if (hung) {
3166                 char msg[80];
3167                 unsigned int tmp;
3168                 int len;
3169
3170                 /* If some rings hung but others were still busy, only
3171                  * blame the hanging rings in the synopsis.
3172                  */
3173                 if (stuck != hung)
3174                         hung &= ~stuck;
3175                 len = scnprintf(msg, sizeof(msg),
3176                                 "%s on ", stuck == hung ? "No progress" : "Hang");
3177                 for_each_engine_masked(engine, dev_priv, hung, tmp)
3178                         len += scnprintf(msg + len, sizeof(msg) - len,
3179                                          "%s, ", engine->name);
3180                 msg[len-2] = '\0';
3181
3182                 return i915_handle_error(dev_priv, hung, msg);
3183         }
3184
3185         /* Reset timer in case GPU hangs without another request being added */
3186         if (busy_count)
3187                 i915_queue_hangcheck(dev_priv);
3188 }
3189
3190 static void ibx_irq_reset(struct drm_device *dev)
3191 {
3192         struct drm_i915_private *dev_priv = to_i915(dev);
3193
3194         if (HAS_PCH_NOP(dev))
3195                 return;
3196
3197         GEN5_IRQ_RESET(SDE);
3198
3199         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3200                 I915_WRITE(SERR_INT, 0xffffffff);
3201 }
3202
3203 /*
3204  * SDEIER is also touched by the interrupt handler to work around missed PCH
3205  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3206  * instead we unconditionally enable all PCH interrupt sources here, but then
3207  * only unmask them as needed with SDEIMR.
3208  *
3209  * This function needs to be called before interrupts are enabled.
3210  */
3211 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3212 {
3213         struct drm_i915_private *dev_priv = to_i915(dev);
3214
3215         if (HAS_PCH_NOP(dev))
3216                 return;
3217
3218         WARN_ON(I915_READ(SDEIER) != 0);
3219         I915_WRITE(SDEIER, 0xffffffff);
3220         POSTING_READ(SDEIER);
3221 }
3222
3223 static void gen5_gt_irq_reset(struct drm_device *dev)
3224 {
3225         struct drm_i915_private *dev_priv = to_i915(dev);
3226
3227         GEN5_IRQ_RESET(GT);
3228         if (INTEL_INFO(dev)->gen >= 6)
3229                 GEN5_IRQ_RESET(GEN6_PM);
3230 }
3231
3232 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3233 {
3234         enum pipe pipe;
3235
3236         if (IS_CHERRYVIEW(dev_priv))
3237                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3238         else
3239                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3240
3241         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3242         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3243
3244         for_each_pipe(dev_priv, pipe) {
3245                 I915_WRITE(PIPESTAT(pipe),
3246                            PIPE_FIFO_UNDERRUN_STATUS |
3247                            PIPESTAT_INT_STATUS_MASK);
3248                 dev_priv->pipestat_irq_mask[pipe] = 0;
3249         }
3250
3251         GEN5_IRQ_RESET(VLV_);
3252         dev_priv->irq_mask = ~0;
3253 }
3254
3255 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3256 {
3257         u32 pipestat_mask;
3258         u32 enable_mask;
3259         enum pipe pipe;
3260
3261         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3262                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3263
3264         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3265         for_each_pipe(dev_priv, pipe)
3266                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3267
3268         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3269                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3270                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3271         if (IS_CHERRYVIEW(dev_priv))
3272                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3273
3274         WARN_ON(dev_priv->irq_mask != ~0);
3275
3276         dev_priv->irq_mask = ~enable_mask;
3277
3278         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3279 }
3280
3281 /* drm_dma.h hooks
3282 */
3283 static void ironlake_irq_reset(struct drm_device *dev)
3284 {
3285         struct drm_i915_private *dev_priv = to_i915(dev);
3286
3287         I915_WRITE(HWSTAM, 0xffffffff);
3288
3289         GEN5_IRQ_RESET(DE);
3290         if (IS_GEN7(dev))
3291                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3292
3293         gen5_gt_irq_reset(dev);
3294
3295         ibx_irq_reset(dev);
3296 }
3297
3298 static void valleyview_irq_preinstall(struct drm_device *dev)
3299 {
3300         struct drm_i915_private *dev_priv = to_i915(dev);
3301
3302         I915_WRITE(VLV_MASTER_IER, 0);
3303         POSTING_READ(VLV_MASTER_IER);
3304
3305         gen5_gt_irq_reset(dev);
3306
3307         spin_lock_irq(&dev_priv->irq_lock);
3308         if (dev_priv->display_irqs_enabled)
3309                 vlv_display_irq_reset(dev_priv);
3310         spin_unlock_irq(&dev_priv->irq_lock);
3311 }
3312
3313 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3314 {
3315         GEN8_IRQ_RESET_NDX(GT, 0);
3316         GEN8_IRQ_RESET_NDX(GT, 1);
3317         GEN8_IRQ_RESET_NDX(GT, 2);
3318         GEN8_IRQ_RESET_NDX(GT, 3);
3319 }
3320
3321 static void gen8_irq_reset(struct drm_device *dev)
3322 {
3323         struct drm_i915_private *dev_priv = to_i915(dev);
3324         int pipe;
3325
3326         I915_WRITE(GEN8_MASTER_IRQ, 0);
3327         POSTING_READ(GEN8_MASTER_IRQ);
3328
3329         gen8_gt_irq_reset(dev_priv);
3330
3331         for_each_pipe(dev_priv, pipe)
3332                 if (intel_display_power_is_enabled(dev_priv,
3333                                                    POWER_DOMAIN_PIPE(pipe)))
3334                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3335
3336         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3337         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3338         GEN5_IRQ_RESET(GEN8_PCU_);
3339
3340         if (HAS_PCH_SPLIT(dev))
3341                 ibx_irq_reset(dev);
3342 }
3343
3344 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3345                                      unsigned int pipe_mask)
3346 {
3347         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3348         enum pipe pipe;
3349
3350         spin_lock_irq(&dev_priv->irq_lock);
3351         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3352                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3353                                   dev_priv->de_irq_mask[pipe],
3354                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3355         spin_unlock_irq(&dev_priv->irq_lock);
3356 }
3357
3358 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3359                                      unsigned int pipe_mask)
3360 {
3361         enum pipe pipe;
3362
3363         spin_lock_irq(&dev_priv->irq_lock);
3364         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3365                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3366         spin_unlock_irq(&dev_priv->irq_lock);
3367
3368         /* make sure we're done processing display irqs */
3369         synchronize_irq(dev_priv->drm.irq);
3370 }
3371
3372 static void cherryview_irq_preinstall(struct drm_device *dev)
3373 {
3374         struct drm_i915_private *dev_priv = to_i915(dev);
3375
3376         I915_WRITE(GEN8_MASTER_IRQ, 0);
3377         POSTING_READ(GEN8_MASTER_IRQ);
3378
3379         gen8_gt_irq_reset(dev_priv);
3380
3381         GEN5_IRQ_RESET(GEN8_PCU_);
3382
3383         spin_lock_irq(&dev_priv->irq_lock);
3384         if (dev_priv->display_irqs_enabled)
3385                 vlv_display_irq_reset(dev_priv);
3386         spin_unlock_irq(&dev_priv->irq_lock);
3387 }
3388
3389 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3390                                   const u32 hpd[HPD_NUM_PINS])
3391 {
3392         struct intel_encoder *encoder;
3393         u32 enabled_irqs = 0;
3394
3395         for_each_intel_encoder(&dev_priv->drm, encoder)
3396                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3397                         enabled_irqs |= hpd[encoder->hpd_pin];
3398
3399         return enabled_irqs;
3400 }
3401
3402 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3403 {
3404         u32 hotplug_irqs, hotplug, enabled_irqs;
3405
3406         if (HAS_PCH_IBX(dev_priv)) {
3407                 hotplug_irqs = SDE_HOTPLUG_MASK;
3408                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3409         } else {
3410                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3411                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3412         }
3413
3414         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3415
3416         /*
3417          * Enable digital hotplug on the PCH, and configure the DP short pulse
3418          * duration to 2ms (which is the minimum in the Display Port spec).
3419          * The pulse duration bits are reserved on LPT+.
3420          */
3421         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3422         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3423         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3424         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3425         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3426         /*
3427          * When CPU and PCH are on the same package, port A
3428          * HPD must be enabled in both north and south.
3429          */
3430         if (HAS_PCH_LPT_LP(dev_priv))
3431                 hotplug |= PORTA_HOTPLUG_ENABLE;
3432         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3433 }
3434
3435 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3436 {
3437         u32 hotplug_irqs, hotplug, enabled_irqs;
3438
3439         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3440         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3441
3442         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3443
3444         /* Enable digital hotplug on the PCH */
3445         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3446         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3447                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3448         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3449
3450         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3451         hotplug |= PORTE_HOTPLUG_ENABLE;
3452         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3453 }
3454
3455 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3456 {
3457         u32 hotplug_irqs, hotplug, enabled_irqs;
3458
3459         if (INTEL_GEN(dev_priv) >= 8) {
3460                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3461                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3462
3463                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3464         } else if (INTEL_GEN(dev_priv) >= 7) {
3465                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3466                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3467
3468                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3469         } else {
3470                 hotplug_irqs = DE_DP_A_HOTPLUG;
3471                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3472
3473                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3474         }
3475
3476         /*
3477          * Enable digital hotplug on the CPU, and configure the DP short pulse
3478          * duration to 2ms (which is the minimum in the Display Port spec)
3479          * The pulse duration bits are reserved on HSW+.
3480          */
3481         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3482         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3483         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3484         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3485
3486         ibx_hpd_irq_setup(dev_priv);
3487 }
3488
3489 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3490 {
3491         u32 hotplug_irqs, hotplug, enabled_irqs;
3492
3493         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3494         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3495
3496         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3497
3498         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3499         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3500                 PORTA_HOTPLUG_ENABLE;
3501
3502         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3503                       hotplug, enabled_irqs);
3504         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3505
3506         /*
3507          * For BXT invert bit has to be set based on AOB design
3508          * for HPD detection logic, update it based on VBT fields.
3509          */
3510
3511         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3512             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3513                 hotplug |= BXT_DDIA_HPD_INVERT;
3514         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3515             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3516                 hotplug |= BXT_DDIB_HPD_INVERT;
3517         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3518             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3519                 hotplug |= BXT_DDIC_HPD_INVERT;
3520
3521         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3522 }
3523
3524 static void ibx_irq_postinstall(struct drm_device *dev)
3525 {
3526         struct drm_i915_private *dev_priv = to_i915(dev);
3527         u32 mask;
3528
3529         if (HAS_PCH_NOP(dev))
3530                 return;
3531
3532         if (HAS_PCH_IBX(dev))
3533                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3534         else
3535                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3536
3537         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3538         I915_WRITE(SDEIMR, ~mask);
3539 }
3540
3541 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3542 {
3543         struct drm_i915_private *dev_priv = to_i915(dev);
3544         u32 pm_irqs, gt_irqs;
3545
3546         pm_irqs = gt_irqs = 0;
3547
3548         dev_priv->gt_irq_mask = ~0;
3549         if (HAS_L3_DPF(dev)) {
3550                 /* L3 parity interrupt is always unmasked. */
3551                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3552                 gt_irqs |= GT_PARITY_ERROR(dev);
3553         }
3554
3555         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3556         if (IS_GEN5(dev)) {
3557                 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3558         } else {
3559                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3560         }
3561
3562         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3563
3564         if (INTEL_INFO(dev)->gen >= 6) {
3565                 /*
3566                  * RPS interrupts will get enabled/disabled on demand when RPS
3567                  * itself is enabled/disabled.
3568                  */
3569                 if (HAS_VEBOX(dev))
3570                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3571
3572                 dev_priv->pm_irq_mask = 0xffffffff;
3573                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3574         }
3575 }
3576
3577 static int ironlake_irq_postinstall(struct drm_device *dev)
3578 {
3579         struct drm_i915_private *dev_priv = to_i915(dev);
3580         u32 display_mask, extra_mask;
3581
3582         if (INTEL_INFO(dev)->gen >= 7) {
3583                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3584                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3585                                 DE_PLANEB_FLIP_DONE_IVB |
3586                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3587                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3588                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3589                               DE_DP_A_HOTPLUG_IVB);
3590         } else {
3591                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3592                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3593                                 DE_AUX_CHANNEL_A |
3594                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3595                                 DE_POISON);
3596                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3597                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3598                               DE_DP_A_HOTPLUG);
3599         }
3600
3601         dev_priv->irq_mask = ~display_mask;
3602
3603         I915_WRITE(HWSTAM, 0xeffe);
3604
3605         ibx_irq_pre_postinstall(dev);
3606
3607         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3608
3609         gen5_gt_irq_postinstall(dev);
3610
3611         ibx_irq_postinstall(dev);
3612
3613         if (IS_IRONLAKE_M(dev)) {
3614                 /* Enable PCU event interrupts
3615                  *
3616                  * spinlocking not required here for correctness since interrupt
3617                  * setup is guaranteed to run in single-threaded context. But we
3618                  * need it to make the assert_spin_locked happy. */
3619                 spin_lock_irq(&dev_priv->irq_lock);
3620                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3621                 spin_unlock_irq(&dev_priv->irq_lock);
3622         }
3623
3624         return 0;
3625 }
3626
3627 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3628 {
3629         assert_spin_locked(&dev_priv->irq_lock);
3630
3631         if (dev_priv->display_irqs_enabled)
3632                 return;
3633
3634         dev_priv->display_irqs_enabled = true;
3635
3636         if (intel_irqs_enabled(dev_priv)) {
3637                 vlv_display_irq_reset(dev_priv);
3638                 vlv_display_irq_postinstall(dev_priv);
3639         }
3640 }
3641
3642 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3643 {
3644         assert_spin_locked(&dev_priv->irq_lock);
3645
3646         if (!dev_priv->display_irqs_enabled)
3647                 return;
3648
3649         dev_priv->display_irqs_enabled = false;
3650
3651         if (intel_irqs_enabled(dev_priv))
3652                 vlv_display_irq_reset(dev_priv);
3653 }
3654
3655
3656 static int valleyview_irq_postinstall(struct drm_device *dev)
3657 {
3658         struct drm_i915_private *dev_priv = to_i915(dev);
3659
3660         gen5_gt_irq_postinstall(dev);
3661
3662         spin_lock_irq(&dev_priv->irq_lock);
3663         if (dev_priv->display_irqs_enabled)
3664                 vlv_display_irq_postinstall(dev_priv);
3665         spin_unlock_irq(&dev_priv->irq_lock);
3666
3667         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3668         POSTING_READ(VLV_MASTER_IER);
3669
3670         return 0;
3671 }
3672
3673 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3674 {
3675         /* These are interrupts we'll toggle with the ring mask register */
3676         uint32_t gt_interrupts[] = {
3677                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3678                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3679                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3680                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3681                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3682                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3683                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3684                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3685                 0,
3686                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3687                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3688                 };
3689
3690         if (HAS_L3_DPF(dev_priv))
3691                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3692
3693         dev_priv->pm_irq_mask = 0xffffffff;
3694         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3695         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3696         /*
3697          * RPS interrupts will get enabled/disabled on demand when RPS itself
3698          * is enabled/disabled.
3699          */
3700         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3701         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3702 }
3703
3704 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3705 {
3706         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3707         uint32_t de_pipe_enables;
3708         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3709         u32 de_port_enables;
3710         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3711         enum pipe pipe;
3712
3713         if (INTEL_INFO(dev_priv)->gen >= 9) {
3714                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3715                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3716                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3717                                   GEN9_AUX_CHANNEL_D;
3718                 if (IS_BROXTON(dev_priv))
3719                         de_port_masked |= BXT_DE_PORT_GMBUS;
3720         } else {
3721                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3722                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3723         }
3724
3725         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3726                                            GEN8_PIPE_FIFO_UNDERRUN;
3727
3728         de_port_enables = de_port_masked;
3729         if (IS_BROXTON(dev_priv))
3730                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3731         else if (IS_BROADWELL(dev_priv))
3732                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3733
3734         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3735         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3736         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3737
3738         for_each_pipe(dev_priv, pipe)
3739                 if (intel_display_power_is_enabled(dev_priv,
3740                                 POWER_DOMAIN_PIPE(pipe)))
3741                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3742                                           dev_priv->de_irq_mask[pipe],
3743                                           de_pipe_enables);
3744
3745         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3746         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3747 }
3748
3749 static int gen8_irq_postinstall(struct drm_device *dev)
3750 {
3751         struct drm_i915_private *dev_priv = to_i915(dev);
3752
3753         if (HAS_PCH_SPLIT(dev))
3754                 ibx_irq_pre_postinstall(dev);
3755
3756         gen8_gt_irq_postinstall(dev_priv);
3757         gen8_de_irq_postinstall(dev_priv);
3758
3759         if (HAS_PCH_SPLIT(dev))
3760                 ibx_irq_postinstall(dev);
3761
3762         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3763         POSTING_READ(GEN8_MASTER_IRQ);
3764
3765         return 0;
3766 }
3767
3768 static int cherryview_irq_postinstall(struct drm_device *dev)
3769 {
3770         struct drm_i915_private *dev_priv = to_i915(dev);
3771
3772         gen8_gt_irq_postinstall(dev_priv);
3773
3774         spin_lock_irq(&dev_priv->irq_lock);
3775         if (dev_priv->display_irqs_enabled)
3776                 vlv_display_irq_postinstall(dev_priv);
3777         spin_unlock_irq(&dev_priv->irq_lock);
3778
3779         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3780         POSTING_READ(GEN8_MASTER_IRQ);
3781
3782         return 0;
3783 }
3784
3785 static void gen8_irq_uninstall(struct drm_device *dev)
3786 {
3787         struct drm_i915_private *dev_priv = to_i915(dev);
3788
3789         if (!dev_priv)
3790                 return;
3791
3792         gen8_irq_reset(dev);
3793 }
3794
3795 static void valleyview_irq_uninstall(struct drm_device *dev)
3796 {
3797         struct drm_i915_private *dev_priv = to_i915(dev);
3798
3799         if (!dev_priv)
3800                 return;
3801
3802         I915_WRITE(VLV_MASTER_IER, 0);
3803         POSTING_READ(VLV_MASTER_IER);
3804
3805         gen5_gt_irq_reset(dev);
3806
3807         I915_WRITE(HWSTAM, 0xffffffff);
3808
3809         spin_lock_irq(&dev_priv->irq_lock);
3810         if (dev_priv->display_irqs_enabled)
3811                 vlv_display_irq_reset(dev_priv);
3812         spin_unlock_irq(&dev_priv->irq_lock);
3813 }
3814
3815 static void cherryview_irq_uninstall(struct drm_device *dev)
3816 {
3817         struct drm_i915_private *dev_priv = to_i915(dev);
3818
3819         if (!dev_priv)
3820                 return;
3821
3822         I915_WRITE(GEN8_MASTER_IRQ, 0);
3823         POSTING_READ(GEN8_MASTER_IRQ);
3824
3825         gen8_gt_irq_reset(dev_priv);
3826
3827         GEN5_IRQ_RESET(GEN8_PCU_);
3828
3829         spin_lock_irq(&dev_priv->irq_lock);
3830         if (dev_priv->display_irqs_enabled)
3831                 vlv_display_irq_reset(dev_priv);
3832         spin_unlock_irq(&dev_priv->irq_lock);
3833 }
3834
3835 static void ironlake_irq_uninstall(struct drm_device *dev)
3836 {
3837         struct drm_i915_private *dev_priv = to_i915(dev);
3838
3839         if (!dev_priv)
3840                 return;
3841
3842         ironlake_irq_reset(dev);
3843 }
3844
3845 static void i8xx_irq_preinstall(struct drm_device * dev)
3846 {
3847         struct drm_i915_private *dev_priv = to_i915(dev);
3848         int pipe;
3849
3850         for_each_pipe(dev_priv, pipe)
3851                 I915_WRITE(PIPESTAT(pipe), 0);
3852         I915_WRITE16(IMR, 0xffff);
3853         I915_WRITE16(IER, 0x0);
3854         POSTING_READ16(IER);
3855 }
3856
3857 static int i8xx_irq_postinstall(struct drm_device *dev)
3858 {
3859         struct drm_i915_private *dev_priv = to_i915(dev);
3860
3861         I915_WRITE16(EMR,
3862                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3863
3864         /* Unmask the interrupts that we always want on. */
3865         dev_priv->irq_mask =
3866                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3867                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3868                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3869                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3870         I915_WRITE16(IMR, dev_priv->irq_mask);
3871
3872         I915_WRITE16(IER,
3873                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3874                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3875                      I915_USER_INTERRUPT);
3876         POSTING_READ16(IER);
3877
3878         /* Interrupt setup is already guaranteed to be single-threaded, this is
3879          * just to make the assert_spin_locked check happy. */
3880         spin_lock_irq(&dev_priv->irq_lock);
3881         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3882         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3883         spin_unlock_irq(&dev_priv->irq_lock);
3884
3885         return 0;
3886 }
3887
3888 /*
3889  * Returns true when a page flip has completed.
3890  */
3891 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3892                                int plane, int pipe, u32 iir)
3893 {
3894         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3895
3896         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3897                 return false;
3898
3899         if ((iir & flip_pending) == 0)
3900                 goto check_page_flip;
3901
3902         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3903          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3904          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3905          * the flip is completed (no longer pending). Since this doesn't raise
3906          * an interrupt per se, we watch for the change at vblank.
3907          */
3908         if (I915_READ16(ISR) & flip_pending)
3909                 goto check_page_flip;
3910
3911         intel_finish_page_flip_cs(dev_priv, pipe);
3912         return true;
3913
3914 check_page_flip:
3915         intel_check_page_flip(dev_priv, pipe);
3916         return false;
3917 }
3918
3919 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3920 {
3921         struct drm_device *dev = arg;
3922         struct drm_i915_private *dev_priv = to_i915(dev);
3923         u16 iir, new_iir;
3924         u32 pipe_stats[2];
3925         int pipe;
3926         u16 flip_mask =
3927                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3928                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3929         irqreturn_t ret;
3930
3931         if (!intel_irqs_enabled(dev_priv))
3932                 return IRQ_NONE;
3933
3934         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3935         disable_rpm_wakeref_asserts(dev_priv);
3936
3937         ret = IRQ_NONE;
3938         iir = I915_READ16(IIR);
3939         if (iir == 0)
3940                 goto out;
3941
3942         while (iir & ~flip_mask) {
3943                 /* Can't rely on pipestat interrupt bit in iir as it might
3944                  * have been cleared after the pipestat interrupt was received.
3945                  * It doesn't set the bit in iir again, but it still produces
3946                  * interrupts (for non-MSI).
3947                  */
3948                 spin_lock(&dev_priv->irq_lock);
3949                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3950                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3951
3952                 for_each_pipe(dev_priv, pipe) {
3953                         i915_reg_t reg = PIPESTAT(pipe);
3954                         pipe_stats[pipe] = I915_READ(reg);
3955
3956                         /*
3957                          * Clear the PIPE*STAT regs before the IIR
3958                          */
3959                         if (pipe_stats[pipe] & 0x8000ffff)
3960                                 I915_WRITE(reg, pipe_stats[pipe]);
3961                 }
3962                 spin_unlock(&dev_priv->irq_lock);
3963
3964                 I915_WRITE16(IIR, iir & ~flip_mask);
3965                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3966
3967                 if (iir & I915_USER_INTERRUPT)
3968                         notify_ring(&dev_priv->engine[RCS]);
3969
3970                 for_each_pipe(dev_priv, pipe) {
3971                         int plane = pipe;
3972                         if (HAS_FBC(dev_priv))
3973                                 plane = !plane;
3974
3975                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3976                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
3977                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3978
3979                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3980                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3981
3982                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3983                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3984                                                                     pipe);
3985                 }
3986
3987                 iir = new_iir;
3988         }
3989         ret = IRQ_HANDLED;
3990
3991 out:
3992         enable_rpm_wakeref_asserts(dev_priv);
3993
3994         return ret;
3995 }
3996
3997 static void i8xx_irq_uninstall(struct drm_device * dev)
3998 {
3999         struct drm_i915_private *dev_priv = to_i915(dev);
4000         int pipe;
4001
4002         for_each_pipe(dev_priv, pipe) {
4003                 /* Clear enable bits; then clear status bits */
4004                 I915_WRITE(PIPESTAT(pipe), 0);
4005                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4006         }
4007         I915_WRITE16(IMR, 0xffff);
4008         I915_WRITE16(IER, 0x0);
4009         I915_WRITE16(IIR, I915_READ16(IIR));
4010 }
4011
4012 static void i915_irq_preinstall(struct drm_device * dev)
4013 {
4014         struct drm_i915_private *dev_priv = to_i915(dev);
4015         int pipe;
4016
4017         if (I915_HAS_HOTPLUG(dev)) {
4018                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4019                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4020         }
4021
4022         I915_WRITE16(HWSTAM, 0xeffe);
4023         for_each_pipe(dev_priv, pipe)
4024                 I915_WRITE(PIPESTAT(pipe), 0);
4025         I915_WRITE(IMR, 0xffffffff);
4026         I915_WRITE(IER, 0x0);
4027         POSTING_READ(IER);
4028 }
4029
4030 static int i915_irq_postinstall(struct drm_device *dev)
4031 {
4032         struct drm_i915_private *dev_priv = to_i915(dev);
4033         u32 enable_mask;
4034
4035         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4036
4037         /* Unmask the interrupts that we always want on. */
4038         dev_priv->irq_mask =
4039                 ~(I915_ASLE_INTERRUPT |
4040                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4041                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4042                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4043                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4044
4045         enable_mask =
4046                 I915_ASLE_INTERRUPT |
4047                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4048                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4049                 I915_USER_INTERRUPT;
4050
4051         if (I915_HAS_HOTPLUG(dev)) {
4052                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4053                 POSTING_READ(PORT_HOTPLUG_EN);
4054
4055                 /* Enable in IER... */
4056                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4057                 /* and unmask in IMR */
4058                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4059         }
4060
4061         I915_WRITE(IMR, dev_priv->irq_mask);
4062         I915_WRITE(IER, enable_mask);
4063         POSTING_READ(IER);
4064
4065         i915_enable_asle_pipestat(dev_priv);
4066
4067         /* Interrupt setup is already guaranteed to be single-threaded, this is
4068          * just to make the assert_spin_locked check happy. */
4069         spin_lock_irq(&dev_priv->irq_lock);
4070         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4071         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4072         spin_unlock_irq(&dev_priv->irq_lock);
4073
4074         return 0;
4075 }
4076
4077 /*
4078  * Returns true when a page flip has completed.
4079  */
4080 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4081                                int plane, int pipe, u32 iir)
4082 {
4083         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4084
4085         if (!intel_pipe_handle_vblank(dev_priv, pipe))
4086                 return false;
4087
4088         if ((iir & flip_pending) == 0)
4089                 goto check_page_flip;
4090
4091         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4092          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4093          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4094          * the flip is completed (no longer pending). Since this doesn't raise
4095          * an interrupt per se, we watch for the change at vblank.
4096          */
4097         if (I915_READ(ISR) & flip_pending)
4098                 goto check_page_flip;
4099
4100         intel_finish_page_flip_cs(dev_priv, pipe);
4101         return true;
4102
4103 check_page_flip:
4104         intel_check_page_flip(dev_priv, pipe);
4105         return false;
4106 }
4107
4108 static irqreturn_t i915_irq_handler(int irq, void *arg)
4109 {
4110         struct drm_device *dev = arg;
4111         struct drm_i915_private *dev_priv = to_i915(dev);
4112         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4113         u32 flip_mask =
4114                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4115                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4116         int pipe, ret = IRQ_NONE;
4117
4118         if (!intel_irqs_enabled(dev_priv))
4119                 return IRQ_NONE;
4120
4121         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4122         disable_rpm_wakeref_asserts(dev_priv);
4123
4124         iir = I915_READ(IIR);
4125         do {
4126                 bool irq_received = (iir & ~flip_mask) != 0;
4127                 bool blc_event = false;
4128
4129                 /* Can't rely on pipestat interrupt bit in iir as it might
4130                  * have been cleared after the pipestat interrupt was received.
4131                  * It doesn't set the bit in iir again, but it still produces
4132                  * interrupts (for non-MSI).
4133                  */
4134                 spin_lock(&dev_priv->irq_lock);
4135                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4136                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4137
4138                 for_each_pipe(dev_priv, pipe) {
4139                         i915_reg_t reg = PIPESTAT(pipe);
4140                         pipe_stats[pipe] = I915_READ(reg);
4141
4142                         /* Clear the PIPE*STAT regs before the IIR */
4143                         if (pipe_stats[pipe] & 0x8000ffff) {
4144                                 I915_WRITE(reg, pipe_stats[pipe]);
4145                                 irq_received = true;
4146                         }
4147                 }
4148                 spin_unlock(&dev_priv->irq_lock);
4149
4150                 if (!irq_received)
4151                         break;
4152
4153                 /* Consume port.  Then clear IIR or we'll miss events */
4154                 if (I915_HAS_HOTPLUG(dev_priv) &&
4155                     iir & I915_DISPLAY_PORT_INTERRUPT) {
4156                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4157                         if (hotplug_status)
4158                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4159                 }
4160
4161                 I915_WRITE(IIR, iir & ~flip_mask);
4162                 new_iir = I915_READ(IIR); /* Flush posted writes */
4163
4164                 if (iir & I915_USER_INTERRUPT)
4165                         notify_ring(&dev_priv->engine[RCS]);
4166
4167                 for_each_pipe(dev_priv, pipe) {
4168                         int plane = pipe;
4169                         if (HAS_FBC(dev_priv))
4170                                 plane = !plane;
4171
4172                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4173                             i915_handle_vblank(dev_priv, plane, pipe, iir))
4174                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4175
4176                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4177                                 blc_event = true;
4178
4179                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4180                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4181
4182                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4183                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4184                                                                     pipe);
4185                 }
4186
4187                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4188                         intel_opregion_asle_intr(dev_priv);
4189
4190                 /* With MSI, interrupts are only generated when iir
4191                  * transitions from zero to nonzero.  If another bit got
4192                  * set while we were handling the existing iir bits, then
4193                  * we would never get another interrupt.
4194                  *
4195                  * This is fine on non-MSI as well, as if we hit this path
4196                  * we avoid exiting the interrupt handler only to generate
4197                  * another one.
4198                  *
4199                  * Note that for MSI this could cause a stray interrupt report
4200                  * if an interrupt landed in the time between writing IIR and
4201                  * the posting read.  This should be rare enough to never
4202                  * trigger the 99% of 100,000 interrupts test for disabling
4203                  * stray interrupts.
4204                  */
4205                 ret = IRQ_HANDLED;
4206                 iir = new_iir;
4207         } while (iir & ~flip_mask);
4208
4209         enable_rpm_wakeref_asserts(dev_priv);
4210
4211         return ret;
4212 }
4213
4214 static void i915_irq_uninstall(struct drm_device * dev)
4215 {
4216         struct drm_i915_private *dev_priv = to_i915(dev);
4217         int pipe;
4218
4219         if (I915_HAS_HOTPLUG(dev)) {
4220                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4221                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4222         }
4223
4224         I915_WRITE16(HWSTAM, 0xffff);
4225         for_each_pipe(dev_priv, pipe) {
4226                 /* Clear enable bits; then clear status bits */
4227                 I915_WRITE(PIPESTAT(pipe), 0);
4228                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4229         }
4230         I915_WRITE(IMR, 0xffffffff);
4231         I915_WRITE(IER, 0x0);
4232
4233         I915_WRITE(IIR, I915_READ(IIR));
4234 }
4235
4236 static void i965_irq_preinstall(struct drm_device * dev)
4237 {
4238         struct drm_i915_private *dev_priv = to_i915(dev);
4239         int pipe;
4240
4241         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4242         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4243
4244         I915_WRITE(HWSTAM, 0xeffe);
4245         for_each_pipe(dev_priv, pipe)
4246                 I915_WRITE(PIPESTAT(pipe), 0);
4247         I915_WRITE(IMR, 0xffffffff);
4248         I915_WRITE(IER, 0x0);
4249         POSTING_READ(IER);
4250 }
4251
4252 static int i965_irq_postinstall(struct drm_device *dev)
4253 {
4254         struct drm_i915_private *dev_priv = to_i915(dev);
4255         u32 enable_mask;
4256         u32 error_mask;
4257
4258         /* Unmask the interrupts that we always want on. */
4259         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4260                                I915_DISPLAY_PORT_INTERRUPT |
4261                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4262                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4263                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4264                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4265                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4266
4267         enable_mask = ~dev_priv->irq_mask;
4268         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4269                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4270         enable_mask |= I915_USER_INTERRUPT;
4271
4272         if (IS_G4X(dev_priv))
4273                 enable_mask |= I915_BSD_USER_INTERRUPT;
4274
4275         /* Interrupt setup is already guaranteed to be single-threaded, this is
4276          * just to make the assert_spin_locked check happy. */
4277         spin_lock_irq(&dev_priv->irq_lock);
4278         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4279         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4280         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4281         spin_unlock_irq(&dev_priv->irq_lock);
4282
4283         /*
4284          * Enable some error detection, note the instruction error mask
4285          * bit is reserved, so we leave it masked.
4286          */
4287         if (IS_G4X(dev_priv)) {
4288                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4289                                GM45_ERROR_MEM_PRIV |
4290                                GM45_ERROR_CP_PRIV |
4291                                I915_ERROR_MEMORY_REFRESH);
4292         } else {
4293                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4294                                I915_ERROR_MEMORY_REFRESH);
4295         }
4296         I915_WRITE(EMR, error_mask);
4297
4298         I915_WRITE(IMR, dev_priv->irq_mask);
4299         I915_WRITE(IER, enable_mask);
4300         POSTING_READ(IER);
4301
4302         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4303         POSTING_READ(PORT_HOTPLUG_EN);
4304
4305         i915_enable_asle_pipestat(dev_priv);
4306
4307         return 0;
4308 }
4309
4310 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4311 {
4312         u32 hotplug_en;
4313
4314         assert_spin_locked(&dev_priv->irq_lock);
4315
4316         /* Note HDMI and DP share hotplug bits */
4317         /* enable bits are the same for all generations */
4318         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4319         /* Programming the CRT detection parameters tends
4320            to generate a spurious hotplug event about three
4321            seconds later.  So just do it once.
4322         */
4323         if (IS_G4X(dev_priv))
4324                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4325         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4326
4327         /* Ignore TV since it's buggy */
4328         i915_hotplug_interrupt_update_locked(dev_priv,
4329                                              HOTPLUG_INT_EN_MASK |
4330                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4331                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4332                                              hotplug_en);
4333 }
4334
4335 static irqreturn_t i965_irq_handler(int irq, void *arg)
4336 {
4337         struct drm_device *dev = arg;
4338         struct drm_i915_private *dev_priv = to_i915(dev);
4339         u32 iir, new_iir;
4340         u32 pipe_stats[I915_MAX_PIPES];
4341         int ret = IRQ_NONE, pipe;
4342         u32 flip_mask =
4343                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4344                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4345
4346         if (!intel_irqs_enabled(dev_priv))
4347                 return IRQ_NONE;
4348
4349         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4350         disable_rpm_wakeref_asserts(dev_priv);
4351
4352         iir = I915_READ(IIR);
4353
4354         for (;;) {
4355                 bool irq_received = (iir & ~flip_mask) != 0;
4356                 bool blc_event = false;
4357
4358                 /* Can't rely on pipestat interrupt bit in iir as it might
4359                  * have been cleared after the pipestat interrupt was received.
4360                  * It doesn't set the bit in iir again, but it still produces
4361                  * interrupts (for non-MSI).
4362                  */
4363                 spin_lock(&dev_priv->irq_lock);
4364                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4365                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4366
4367                 for_each_pipe(dev_priv, pipe) {
4368                         i915_reg_t reg = PIPESTAT(pipe);
4369                         pipe_stats[pipe] = I915_READ(reg);
4370
4371                         /*
4372                          * Clear the PIPE*STAT regs before the IIR
4373                          */
4374                         if (pipe_stats[pipe] & 0x8000ffff) {
4375                                 I915_WRITE(reg, pipe_stats[pipe]);
4376                                 irq_received = true;
4377                         }
4378                 }
4379                 spin_unlock(&dev_priv->irq_lock);
4380
4381                 if (!irq_received)
4382                         break;
4383
4384                 ret = IRQ_HANDLED;
4385
4386                 /* Consume port.  Then clear IIR or we'll miss events */
4387                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4388                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4389                         if (hotplug_status)
4390                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4391                 }
4392
4393                 I915_WRITE(IIR, iir & ~flip_mask);
4394                 new_iir = I915_READ(IIR); /* Flush posted writes */
4395
4396                 if (iir & I915_USER_INTERRUPT)
4397                         notify_ring(&dev_priv->engine[RCS]);
4398                 if (iir & I915_BSD_USER_INTERRUPT)
4399                         notify_ring(&dev_priv->engine[VCS]);
4400
4401                 for_each_pipe(dev_priv, pipe) {
4402                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4403                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4404                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4405
4406                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4407                                 blc_event = true;
4408
4409                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4410                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4411
4412                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4413                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4414                 }
4415
4416                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4417                         intel_opregion_asle_intr(dev_priv);
4418
4419                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4420                         gmbus_irq_handler(dev_priv);
4421
4422                 /* With MSI, interrupts are only generated when iir
4423                  * transitions from zero to nonzero.  If another bit got
4424                  * set while we were handling the existing iir bits, then
4425                  * we would never get another interrupt.
4426                  *
4427                  * This is fine on non-MSI as well, as if we hit this path
4428                  * we avoid exiting the interrupt handler only to generate
4429                  * another one.
4430                  *
4431                  * Note that for MSI this could cause a stray interrupt report
4432                  * if an interrupt landed in the time between writing IIR and
4433                  * the posting read.  This should be rare enough to never
4434                  * trigger the 99% of 100,000 interrupts test for disabling
4435                  * stray interrupts.
4436                  */
4437                 iir = new_iir;
4438         }
4439
4440         enable_rpm_wakeref_asserts(dev_priv);
4441
4442         return ret;
4443 }
4444
4445 static void i965_irq_uninstall(struct drm_device * dev)
4446 {
4447         struct drm_i915_private *dev_priv = to_i915(dev);
4448         int pipe;
4449
4450         if (!dev_priv)
4451                 return;
4452
4453         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4454         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4455
4456         I915_WRITE(HWSTAM, 0xffffffff);
4457         for_each_pipe(dev_priv, pipe)
4458                 I915_WRITE(PIPESTAT(pipe), 0);
4459         I915_WRITE(IMR, 0xffffffff);
4460         I915_WRITE(IER, 0x0);
4461
4462         for_each_pipe(dev_priv, pipe)
4463                 I915_WRITE(PIPESTAT(pipe),
4464                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4465         I915_WRITE(IIR, I915_READ(IIR));
4466 }
4467
4468 /**
4469  * intel_irq_init - initializes irq support
4470  * @dev_priv: i915 device instance
4471  *
4472  * This function initializes all the irq support including work items, timers
4473  * and all the vtables. It does not setup the interrupt itself though.
4474  */
4475 void intel_irq_init(struct drm_i915_private *dev_priv)
4476 {
4477         struct drm_device *dev = &dev_priv->drm;
4478
4479         intel_hpd_init_work(dev_priv);
4480
4481         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4482         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4483
4484         /* Let's track the enabled rps events */
4485         if (IS_VALLEYVIEW(dev_priv))
4486                 /* WaGsvRC0ResidencyMethod:vlv */
4487                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4488         else
4489                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4490
4491         dev_priv->rps.pm_intr_keep = 0;
4492
4493         /*
4494          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4495          * if GEN6_PM_UP_EI_EXPIRED is masked.
4496          *
4497          * TODO: verify if this can be reproduced on VLV,CHV.
4498          */
4499         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4500                 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4501
4502         if (INTEL_INFO(dev_priv)->gen >= 8)
4503                 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
4504
4505         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4506                           i915_hangcheck_elapsed);
4507
4508         if (IS_GEN2(dev_priv)) {
4509                 /* Gen2 doesn't have a hardware frame counter */
4510                 dev->max_vblank_count = 0;
4511                 dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
4512         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4513                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4514                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4515         } else {
4516                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4517                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4518         }
4519
4520         /*
4521          * Opt out of the vblank disable timer on everything except gen2.
4522          * Gen2 doesn't have a hardware frame counter and so depends on
4523          * vblank interrupts to produce sane vblank seuquence numbers.
4524          */
4525         if (!IS_GEN2(dev_priv))
4526                 dev->vblank_disable_immediate = true;
4527
4528         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4529         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4530
4531         if (IS_CHERRYVIEW(dev_priv)) {
4532                 dev->driver->irq_handler = cherryview_irq_handler;
4533                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4534                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4535                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4536                 dev->driver->enable_vblank = valleyview_enable_vblank;
4537                 dev->driver->disable_vblank = valleyview_disable_vblank;
4538                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4539         } else if (IS_VALLEYVIEW(dev_priv)) {
4540                 dev->driver->irq_handler = valleyview_irq_handler;
4541                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4542                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4543                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4544                 dev->driver->enable_vblank = valleyview_enable_vblank;
4545                 dev->driver->disable_vblank = valleyview_disable_vblank;
4546                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4547         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4548                 dev->driver->irq_handler = gen8_irq_handler;
4549                 dev->driver->irq_preinstall = gen8_irq_reset;
4550                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4551                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4552                 dev->driver->enable_vblank = gen8_enable_vblank;
4553                 dev->driver->disable_vblank = gen8_disable_vblank;
4554                 if (IS_BROXTON(dev))
4555                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4556                 else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
4557                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4558                 else
4559                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4560         } else if (HAS_PCH_SPLIT(dev)) {
4561                 dev->driver->irq_handler = ironlake_irq_handler;
4562                 dev->driver->irq_preinstall = ironlake_irq_reset;
4563                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4564                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4565                 dev->driver->enable_vblank = ironlake_enable_vblank;
4566                 dev->driver->disable_vblank = ironlake_disable_vblank;
4567                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4568         } else {
4569                 if (IS_GEN2(dev_priv)) {
4570                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4571                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4572                         dev->driver->irq_handler = i8xx_irq_handler;
4573                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4574                 } else if (IS_GEN3(dev_priv)) {
4575                         dev->driver->irq_preinstall = i915_irq_preinstall;
4576                         dev->driver->irq_postinstall = i915_irq_postinstall;
4577                         dev->driver->irq_uninstall = i915_irq_uninstall;
4578                         dev->driver->irq_handler = i915_irq_handler;
4579                 } else {
4580                         dev->driver->irq_preinstall = i965_irq_preinstall;
4581                         dev->driver->irq_postinstall = i965_irq_postinstall;
4582                         dev->driver->irq_uninstall = i965_irq_uninstall;
4583                         dev->driver->irq_handler = i965_irq_handler;
4584                 }
4585                 if (I915_HAS_HOTPLUG(dev_priv))
4586                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4587                 dev->driver->enable_vblank = i915_enable_vblank;
4588                 dev->driver->disable_vblank = i915_disable_vblank;
4589         }
4590 }
4591
4592 /**
4593  * intel_irq_install - enables the hardware interrupt
4594  * @dev_priv: i915 device instance
4595  *
4596  * This function enables the hardware interrupt handling, but leaves the hotplug
4597  * handling still disabled. It is called after intel_irq_init().
4598  *
4599  * In the driver load and resume code we need working interrupts in a few places
4600  * but don't want to deal with the hassle of concurrent probe and hotplug
4601  * workers. Hence the split into this two-stage approach.
4602  */
4603 int intel_irq_install(struct drm_i915_private *dev_priv)
4604 {
4605         /*
4606          * We enable some interrupt sources in our postinstall hooks, so mark
4607          * interrupts as enabled _before_ actually enabling them to avoid
4608          * special cases in our ordering checks.
4609          */
4610         dev_priv->pm.irqs_enabled = true;
4611
4612         return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4613 }
4614
4615 /**
4616  * intel_irq_uninstall - finilizes all irq handling
4617  * @dev_priv: i915 device instance
4618  *
4619  * This stops interrupt and hotplug handling and unregisters and frees all
4620  * resources acquired in the init functions.
4621  */
4622 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4623 {
4624         drm_irq_uninstall(&dev_priv->drm);
4625         intel_hpd_cancel_work(dev_priv);
4626         dev_priv->pm.irqs_enabled = false;
4627 }
4628
4629 /**
4630  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4631  * @dev_priv: i915 device instance
4632  *
4633  * This function is used to disable interrupts at runtime, both in the runtime
4634  * pm and the system suspend/resume code.
4635  */
4636 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4637 {
4638         dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4639         dev_priv->pm.irqs_enabled = false;
4640         synchronize_irq(dev_priv->drm.irq);
4641 }
4642
4643 /**
4644  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4645  * @dev_priv: i915 device instance
4646  *
4647  * This function is used to enable interrupts at runtime, both in the runtime
4648  * pm and the system suspend/resume code.
4649  */
4650 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4651 {
4652         dev_priv->pm.irqs_enabled = true;
4653         dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4654         dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4655 }