1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/circ_buf.h>
32 #include <linux/slab.h>
33 #include <linux/sysrq.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_irq.h>
38 #include "display/intel_de.h"
39 #include "display/intel_display_types.h"
40 #include "display/intel_fifo_underrun.h"
41 #include "display/intel_hotplug.h"
42 #include "display/intel_lpe_audio.h"
43 #include "display/intel_psr.h"
45 #include "gt/intel_breadcrumbs.h"
46 #include "gt/intel_gt.h"
47 #include "gt/intel_gt_irq.h"
48 #include "gt/intel_gt_pm_irq.h"
49 #include "gt/intel_rps.h"
53 #include "i915_trace.h"
57 * DOC: interrupt handling
59 * These functions provide the basic support for enabling and disabling the
60 * interrupt handling support. There's a lot more functionality in i915_irq.c
61 * and related files, but that will be described in separate chapters.
65 * Interrupt statistic for PMU. Increments the counter only if the
66 * interrupt originated from the the GPU so interrupts from a device which
67 * shares the interrupt line are not accounted.
69 static inline void pmu_irq_stats(struct drm_i915_private *i915,
72 if (unlikely(res != IRQ_HANDLED))
76 * A clever compiler translates that into INC. A not so clever one
77 * should at least prevent store tearing.
79 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1);
82 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
83 typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
86 static const u32 hpd_ilk[HPD_NUM_PINS] = {
87 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
90 static const u32 hpd_ivb[HPD_NUM_PINS] = {
91 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
94 static const u32 hpd_bdw[HPD_NUM_PINS] = {
95 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
98 static const u32 hpd_ibx[HPD_NUM_PINS] = {
99 [HPD_CRT] = SDE_CRT_HOTPLUG,
100 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
101 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
102 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
103 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
106 static const u32 hpd_cpt[HPD_NUM_PINS] = {
107 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
108 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
109 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
110 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
111 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
114 static const u32 hpd_spt[HPD_NUM_PINS] = {
115 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
116 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
117 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
118 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
119 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
122 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
123 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
124 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
125 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
126 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
127 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
128 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
131 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
132 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
133 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
134 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
135 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
136 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
137 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
140 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
141 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
142 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
143 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
144 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
145 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
146 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
149 static const u32 hpd_bxt[HPD_NUM_PINS] = {
150 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
151 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
152 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
155 static const u32 hpd_gen11[HPD_NUM_PINS] = {
156 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
157 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
158 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
159 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
160 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
161 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
164 static const u32 hpd_icp[HPD_NUM_PINS] = {
165 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
166 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
167 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
168 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
169 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
170 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
171 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
172 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
173 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
176 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
177 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
178 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
179 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
180 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
183 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
185 struct i915_hotplug *hpd = &dev_priv->hotplug;
187 if (HAS_GMCH(dev_priv)) {
188 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
189 IS_CHERRYVIEW(dev_priv))
190 hpd->hpd = hpd_status_g4x;
192 hpd->hpd = hpd_status_i915;
196 if (DISPLAY_VER(dev_priv) >= 11)
197 hpd->hpd = hpd_gen11;
198 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
200 else if (DISPLAY_VER(dev_priv) >= 8)
202 else if (DISPLAY_VER(dev_priv) >= 7)
207 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
208 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
211 if (HAS_PCH_DG1(dev_priv))
212 hpd->pch_hpd = hpd_sde_dg1;
213 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
214 hpd->pch_hpd = hpd_icp;
215 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
216 hpd->pch_hpd = hpd_spt;
217 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
218 hpd->pch_hpd = hpd_cpt;
219 else if (HAS_PCH_IBX(dev_priv))
220 hpd->pch_hpd = hpd_ibx;
222 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
226 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
228 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
230 drm_crtc_handle_vblank(&crtc->base);
233 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
234 i915_reg_t iir, i915_reg_t ier)
236 intel_uncore_write(uncore, imr, 0xffffffff);
237 intel_uncore_posting_read(uncore, imr);
239 intel_uncore_write(uncore, ier, 0);
241 /* IIR can theoretically queue up two events. Be paranoid. */
242 intel_uncore_write(uncore, iir, 0xffffffff);
243 intel_uncore_posting_read(uncore, iir);
244 intel_uncore_write(uncore, iir, 0xffffffff);
245 intel_uncore_posting_read(uncore, iir);
248 void gen2_irq_reset(struct intel_uncore *uncore)
250 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
251 intel_uncore_posting_read16(uncore, GEN2_IMR);
253 intel_uncore_write16(uncore, GEN2_IER, 0);
255 /* IIR can theoretically queue up two events. Be paranoid. */
256 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
257 intel_uncore_posting_read16(uncore, GEN2_IIR);
258 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
259 intel_uncore_posting_read16(uncore, GEN2_IIR);
263 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
265 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
267 u32 val = intel_uncore_read(uncore, reg);
272 drm_WARN(&uncore->i915->drm, 1,
273 "Interrupt register 0x%x is not zero: 0x%08x\n",
274 i915_mmio_reg_offset(reg), val);
275 intel_uncore_write(uncore, reg, 0xffffffff);
276 intel_uncore_posting_read(uncore, reg);
277 intel_uncore_write(uncore, reg, 0xffffffff);
278 intel_uncore_posting_read(uncore, reg);
281 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
283 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
288 drm_WARN(&uncore->i915->drm, 1,
289 "Interrupt register 0x%x is not zero: 0x%08x\n",
290 i915_mmio_reg_offset(GEN2_IIR), val);
291 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
292 intel_uncore_posting_read16(uncore, GEN2_IIR);
293 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
294 intel_uncore_posting_read16(uncore, GEN2_IIR);
297 void gen3_irq_init(struct intel_uncore *uncore,
298 i915_reg_t imr, u32 imr_val,
299 i915_reg_t ier, u32 ier_val,
302 gen3_assert_iir_is_zero(uncore, iir);
304 intel_uncore_write(uncore, ier, ier_val);
305 intel_uncore_write(uncore, imr, imr_val);
306 intel_uncore_posting_read(uncore, imr);
309 void gen2_irq_init(struct intel_uncore *uncore,
310 u32 imr_val, u32 ier_val)
312 gen2_assert_iir_is_zero(uncore);
314 intel_uncore_write16(uncore, GEN2_IER, ier_val);
315 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
316 intel_uncore_posting_read16(uncore, GEN2_IMR);
319 /* For display hotplug interrupt */
321 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
327 lockdep_assert_held(&dev_priv->irq_lock);
328 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
330 val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN);
333 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val);
337 * i915_hotplug_interrupt_update - update hotplug interrupt enable
338 * @dev_priv: driver private
339 * @mask: bits to update
340 * @bits: bits to enable
341 * NOTE: the HPD enable bits are modified both inside and outside
342 * of an interrupt context. To avoid that read-modify-write cycles
343 * interfer, these bits are protected by a spinlock. Since this
344 * function is usually not called from a context where the lock is
345 * held already, this function acquires the lock itself. A non-locking
346 * version is also available.
348 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
352 spin_lock_irq(&dev_priv->irq_lock);
353 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
354 spin_unlock_irq(&dev_priv->irq_lock);
358 * ilk_update_display_irq - update DEIMR
359 * @dev_priv: driver private
360 * @interrupt_mask: mask of interrupt bits to update
361 * @enabled_irq_mask: mask of interrupt bits to enable
363 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
365 u32 enabled_irq_mask)
369 lockdep_assert_held(&dev_priv->irq_lock);
370 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
372 new_val = dev_priv->irq_mask;
373 new_val &= ~interrupt_mask;
374 new_val |= (~enabled_irq_mask & interrupt_mask);
376 if (new_val != dev_priv->irq_mask &&
377 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
378 dev_priv->irq_mask = new_val;
379 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask);
380 intel_uncore_posting_read(&dev_priv->uncore, DEIMR);
385 * bdw_update_port_irq - update DE port interrupt
386 * @dev_priv: driver private
387 * @interrupt_mask: mask of interrupt bits to update
388 * @enabled_irq_mask: mask of interrupt bits to enable
390 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
392 u32 enabled_irq_mask)
397 lockdep_assert_held(&dev_priv->irq_lock);
399 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
401 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
404 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
407 new_val &= ~interrupt_mask;
408 new_val |= (~enabled_irq_mask & interrupt_mask);
410 if (new_val != old_val) {
411 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val);
412 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);
417 * bdw_update_pipe_irq - update DE pipe interrupt
418 * @dev_priv: driver private
419 * @pipe: pipe whose interrupt to update
420 * @interrupt_mask: mask of interrupt bits to update
421 * @enabled_irq_mask: mask of interrupt bits to enable
423 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
426 u32 enabled_irq_mask)
430 lockdep_assert_held(&dev_priv->irq_lock);
432 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
434 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
437 new_val = dev_priv->de_irq_mask[pipe];
438 new_val &= ~interrupt_mask;
439 new_val |= (~enabled_irq_mask & interrupt_mask);
441 if (new_val != dev_priv->de_irq_mask[pipe]) {
442 dev_priv->de_irq_mask[pipe] = new_val;
443 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
444 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe));
449 * ibx_display_interrupt_update - update SDEIMR
450 * @dev_priv: driver private
451 * @interrupt_mask: mask of interrupt bits to update
452 * @enabled_irq_mask: mask of interrupt bits to enable
454 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
456 u32 enabled_irq_mask)
458 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR);
459 sdeimr &= ~interrupt_mask;
460 sdeimr |= (~enabled_irq_mask & interrupt_mask);
462 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
464 lockdep_assert_held(&dev_priv->irq_lock);
466 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
469 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr);
470 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR);
473 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
476 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
477 u32 enable_mask = status_mask << 16;
479 lockdep_assert_held(&dev_priv->irq_lock);
481 if (DISPLAY_VER(dev_priv) < 5)
485 * On pipe A we don't support the PSR interrupt yet,
486 * on pipe B and C the same bit MBZ.
488 if (drm_WARN_ON_ONCE(&dev_priv->drm,
489 status_mask & PIPE_A_PSR_STATUS_VLV))
492 * On pipe B and C we don't support the PSR interrupt yet, on pipe
493 * A the same bit is for perf counters which we don't use either.
495 if (drm_WARN_ON_ONCE(&dev_priv->drm,
496 status_mask & PIPE_B_PSR_STATUS_VLV))
499 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
500 SPRITE0_FLIP_DONE_INT_EN_VLV |
501 SPRITE1_FLIP_DONE_INT_EN_VLV);
502 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
503 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
504 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
505 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
508 drm_WARN_ONCE(&dev_priv->drm,
509 enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
510 status_mask & ~PIPESTAT_INT_STATUS_MASK,
511 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
512 pipe_name(pipe), enable_mask, status_mask);
517 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
518 enum pipe pipe, u32 status_mask)
520 i915_reg_t reg = PIPESTAT(pipe);
523 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
524 "pipe %c: status_mask=0x%x\n",
525 pipe_name(pipe), status_mask);
527 lockdep_assert_held(&dev_priv->irq_lock);
528 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
530 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
533 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
534 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
536 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
537 intel_uncore_posting_read(&dev_priv->uncore, reg);
540 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
541 enum pipe pipe, u32 status_mask)
543 i915_reg_t reg = PIPESTAT(pipe);
546 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
547 "pipe %c: status_mask=0x%x\n",
548 pipe_name(pipe), status_mask);
550 lockdep_assert_held(&dev_priv->irq_lock);
551 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
553 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
556 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
557 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
559 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);
560 intel_uncore_posting_read(&dev_priv->uncore, reg);
563 static bool i915_has_asle(struct drm_i915_private *dev_priv)
565 if (!dev_priv->opregion.asle)
568 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
572 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
573 * @dev_priv: i915 device private
575 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
577 if (!i915_has_asle(dev_priv))
580 spin_lock_irq(&dev_priv->irq_lock);
582 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
583 if (DISPLAY_VER(dev_priv) >= 4)
584 i915_enable_pipestat(dev_priv, PIPE_A,
585 PIPE_LEGACY_BLC_EVENT_STATUS);
587 spin_unlock_irq(&dev_priv->irq_lock);
591 * This timing diagram depicts the video signal in and
592 * around the vertical blanking period.
594 * Assumptions about the fictitious mode used in this example:
596 * vsync_start = vblank_start + 1
597 * vsync_end = vblank_start + 2
598 * vtotal = vblank_start + 3
601 * latch double buffered registers
602 * increment frame counter (ctg+)
603 * generate start of vblank interrupt (gen4+)
606 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
607 * | may be shifted forward 1-3 extra lines via PIPECONF
609 * | | start of vsync:
610 * | | generate vsync interrupt
612 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
613 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
614 * ----va---> <-----------------vb--------------------> <--------va-------------
615 * | | <----vs-----> |
616 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
617 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
618 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
620 * last visible pixel first visible pixel
621 * | increment frame counter (gen3/4)
622 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
624 * x = horizontal active
625 * _ = horizontal blanking
626 * hs = horizontal sync
627 * va = vertical active
628 * vb = vertical blanking
630 * vbs = vblank_start (number)
633 * - most events happen at the start of horizontal sync
634 * - frame start happens at the start of horizontal blank, 1-4 lines
635 * (depending on PIPECONF settings) after the start of vblank
636 * - gen3/4 pixel and frame counter are synchronized with the start
637 * of horizontal active on the first line of vertical active
640 /* Called from drm generic code, passed a 'crtc', which
641 * we use as a pipe index
643 u32 i915_get_vblank_counter(struct drm_crtc *crtc)
645 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
646 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
647 const struct drm_display_mode *mode = &vblank->hwmode;
648 enum pipe pipe = to_intel_crtc(crtc)->pipe;
649 i915_reg_t high_frame, low_frame;
650 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
651 unsigned long irqflags;
654 * On i965gm TV output the frame counter only works up to
655 * the point when we enable the TV encoder. After that the
656 * frame counter ceases to work and reads zero. We need a
657 * vblank wait before enabling the TV encoder and so we
658 * have to enable vblank interrupts while the frame counter
659 * is still in a working state. However the core vblank code
660 * does not like us returning non-zero frame counter values
661 * when we've told it that we don't have a working frame
662 * counter. Thus we must stop non-zero values leaking out.
664 if (!vblank->max_vblank_count)
667 htotal = mode->crtc_htotal;
668 hsync_start = mode->crtc_hsync_start;
669 vbl_start = mode->crtc_vblank_start;
670 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
671 vbl_start = DIV_ROUND_UP(vbl_start, 2);
673 /* Convert to pixel count */
676 /* Start of vblank event occurs at start of hsync */
677 vbl_start -= htotal - hsync_start;
679 high_frame = PIPEFRAME(pipe);
680 low_frame = PIPEFRAMEPIXEL(pipe);
682 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
685 * High & low register fields aren't synchronized, so make sure
686 * we get a low value that's stable across two reads of the high
690 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
691 low = intel_de_read_fw(dev_priv, low_frame);
692 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
693 } while (high1 != high2);
695 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
697 high1 >>= PIPE_FRAME_HIGH_SHIFT;
698 pixel = low & PIPE_PIXEL_MASK;
699 low >>= PIPE_FRAME_LOW_SHIFT;
702 * The frame counter increments at beginning of active.
703 * Cook up a vblank counter by also checking the pixel
704 * counter against vblank start.
706 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
709 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
711 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
712 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
713 enum pipe pipe = to_intel_crtc(crtc)->pipe;
715 if (!vblank->max_vblank_count)
718 return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));
721 static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
723 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
724 struct drm_vblank_crtc *vblank =
725 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
726 const struct drm_display_mode *mode = &vblank->hwmode;
727 u32 htotal = mode->crtc_htotal;
728 u32 clock = mode->crtc_clock;
729 u32 scan_prev_time, scan_curr_time, scan_post_time;
732 * To avoid the race condition where we might cross into the
733 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
734 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
735 * during the same frame.
739 * This field provides read back of the display
740 * pipe frame time stamp. The time stamp value
741 * is sampled at every start of vertical blank.
743 scan_prev_time = intel_de_read_fw(dev_priv,
744 PIPE_FRMTMSTMP(crtc->pipe));
747 * The TIMESTAMP_CTR register has the current
750 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
752 scan_post_time = intel_de_read_fw(dev_priv,
753 PIPE_FRMTMSTMP(crtc->pipe));
754 } while (scan_post_time != scan_prev_time);
756 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
757 clock), 1000 * htotal);
761 * On certain encoders on certain platforms, pipe
762 * scanline register will not work to get the scanline,
763 * since the timings are driven from the PORT or issues
764 * with scanline register updates.
765 * This function will use Framestamp and current
766 * timestamp registers to calculate the scanline.
768 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
770 struct drm_vblank_crtc *vblank =
771 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
772 const struct drm_display_mode *mode = &vblank->hwmode;
773 u32 vblank_start = mode->crtc_vblank_start;
774 u32 vtotal = mode->crtc_vtotal;
777 scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
778 scanline = min(scanline, vtotal - 1);
779 scanline = (scanline + vblank_start) % vtotal;
785 * intel_de_read_fw(), only for fast reads of display block, no need for
788 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
790 struct drm_device *dev = crtc->base.dev;
791 struct drm_i915_private *dev_priv = to_i915(dev);
792 const struct drm_display_mode *mode;
793 struct drm_vblank_crtc *vblank;
794 enum pipe pipe = crtc->pipe;
795 int position, vtotal;
800 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
801 mode = &vblank->hwmode;
803 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
804 return __intel_get_crtc_scanline_from_timestamp(crtc);
806 vtotal = mode->crtc_vtotal;
807 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
810 if (DISPLAY_VER(dev_priv) == 2)
811 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
813 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
816 * On HSW, the DSL reg (0x70000) appears to return 0 if we
817 * read it just before the start of vblank. So try it again
818 * so we don't accidentally end up spanning a vblank frame
819 * increment, causing the pipe_update_end() code to squak at us.
821 * The nature of this problem means we can't simply check the ISR
822 * bit and return the vblank start value; nor can we use the scanline
823 * debug register in the transcoder as it appears to have the same
824 * problem. We may need to extend this to include other platforms,
825 * but so far testing only shows the problem on HSW.
827 if (HAS_DDI(dev_priv) && !position) {
830 for (i = 0; i < 100; i++) {
832 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
833 if (temp != position) {
841 * See update_scanline_offset() for the details on the
842 * scanline_offset adjustment.
844 return (position + crtc->scanline_offset) % vtotal;
847 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
849 int *vpos, int *hpos,
850 ktime_t *stime, ktime_t *etime,
851 const struct drm_display_mode *mode)
853 struct drm_device *dev = _crtc->dev;
854 struct drm_i915_private *dev_priv = to_i915(dev);
855 struct intel_crtc *crtc = to_intel_crtc(_crtc);
856 enum pipe pipe = crtc->pipe;
858 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
859 unsigned long irqflags;
860 bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
861 IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
862 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
864 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
865 drm_dbg(&dev_priv->drm,
866 "trying to get scanoutpos for disabled "
867 "pipe %c\n", pipe_name(pipe));
871 htotal = mode->crtc_htotal;
872 hsync_start = mode->crtc_hsync_start;
873 vtotal = mode->crtc_vtotal;
874 vbl_start = mode->crtc_vblank_start;
875 vbl_end = mode->crtc_vblank_end;
877 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
878 vbl_start = DIV_ROUND_UP(vbl_start, 2);
884 * Lock uncore.lock, as we will do multiple timing critical raw
885 * register reads, potentially with preemption disabled, so the
886 * following code must not block on uncore.lock.
888 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
890 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
892 /* Get optional system timestamp before query. */
894 *stime = ktime_get();
896 if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
897 int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
899 position = __intel_get_crtc_scanline(crtc);
902 * Already exiting vblank? If so, shift our position
903 * so it looks like we're already apporaching the full
904 * vblank end. This should make the generated timestamp
905 * more or less match when the active portion will start.
907 if (position >= vbl_start && scanlines < position)
908 position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
909 } else if (use_scanline_counter) {
910 /* No obvious pixelcount register. Only query vertical
911 * scanout position from Display scan line register.
913 position = __intel_get_crtc_scanline(crtc);
915 /* Have access to pixelcount since start of frame.
916 * We can split this into vertical and horizontal
919 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
921 /* convert to pixel counts */
927 * In interlaced modes, the pixel counter counts all pixels,
928 * so one field will have htotal more pixels. In order to avoid
929 * the reported position from jumping backwards when the pixel
930 * counter is beyond the length of the shorter field, just
931 * clamp the position the length of the shorter field. This
932 * matches how the scanline counter based position works since
933 * the scanline counter doesn't count the two half lines.
935 if (position >= vtotal)
936 position = vtotal - 1;
939 * Start of vblank interrupt is triggered at start of hsync,
940 * just prior to the first active line of vblank. However we
941 * consider lines to start at the leading edge of horizontal
942 * active. So, should we get here before we've crossed into
943 * the horizontal active of the first line in vblank, we would
944 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
945 * always add htotal-hsync_start to the current pixel position.
947 position = (position + htotal - hsync_start) % vtotal;
950 /* Get optional system timestamp after query. */
952 *etime = ktime_get();
954 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
956 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
959 * While in vblank, position will be negative
960 * counting up towards 0 at vbl_end. And outside
961 * vblank, position will be positive counting
964 if (position >= vbl_start)
967 position += vtotal - vbl_end;
969 if (use_scanline_counter) {
973 *vpos = position / htotal;
974 *hpos = position - (*vpos * htotal);
980 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
981 ktime_t *vblank_time, bool in_vblank_irq)
983 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
984 crtc, max_error, vblank_time, in_vblank_irq,
985 i915_get_crtc_scanoutpos);
988 int intel_get_crtc_scanline(struct intel_crtc *crtc)
990 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
991 unsigned long irqflags;
994 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
995 position = __intel_get_crtc_scanline(crtc);
996 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1002 * ivb_parity_work - Workqueue called when a parity error interrupt
1004 * @work: workqueue struct
1006 * Doesn't actually do anything except notify userspace. As a consequence of
1007 * this event, userspace should try to remap the bad rows since statistically
1008 * it is likely the same row is more likely to go bad again.
1010 static void ivb_parity_work(struct work_struct *work)
1012 struct drm_i915_private *dev_priv =
1013 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1014 struct intel_gt *gt = &dev_priv->gt;
1015 u32 error_status, row, bank, subbank;
1016 char *parity_event[6];
1020 /* We must turn off DOP level clock gating to access the L3 registers.
1021 * In order to prevent a get/put style interface, acquire struct mutex
1022 * any time we access those registers.
1024 mutex_lock(&dev_priv->drm.struct_mutex);
1026 /* If we've screwed up tracking, just let the interrupt fire again */
1027 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
1030 misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
1031 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1032 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);
1034 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1038 if (drm_WARN_ON_ONCE(&dev_priv->drm,
1039 slice >= NUM_L3_SLICES(dev_priv)))
1042 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1044 reg = GEN7_L3CDERRST1(slice);
1046 error_status = intel_uncore_read(&dev_priv->uncore, reg);
1047 row = GEN7_PARITY_ERROR_ROW(error_status);
1048 bank = GEN7_PARITY_ERROR_BANK(error_status);
1049 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1051 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1052 intel_uncore_posting_read(&dev_priv->uncore, reg);
1054 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1055 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1056 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1057 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1058 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1059 parity_event[5] = NULL;
1061 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1062 KOBJ_CHANGE, parity_event);
1064 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1065 slice, row, bank, subbank);
1067 kfree(parity_event[4]);
1068 kfree(parity_event[3]);
1069 kfree(parity_event[2]);
1070 kfree(parity_event[1]);
1073 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
1076 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
1077 spin_lock_irq(>->irq_lock);
1078 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1079 spin_unlock_irq(>->irq_lock);
1081 mutex_unlock(&dev_priv->drm.struct_mutex);
1084 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1093 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
1099 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1103 return val & PORTA_HOTPLUG_LONG_DETECT;
1105 return val & PORTB_HOTPLUG_LONG_DETECT;
1107 return val & PORTC_HOTPLUG_LONG_DETECT;
1113 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1120 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
1126 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1135 return val & ICP_TC_HPD_LONG_DETECT(pin);
1141 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1145 return val & PORTE_HOTPLUG_LONG_DETECT;
1151 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1155 return val & PORTA_HOTPLUG_LONG_DETECT;
1157 return val & PORTB_HOTPLUG_LONG_DETECT;
1159 return val & PORTC_HOTPLUG_LONG_DETECT;
1161 return val & PORTD_HOTPLUG_LONG_DETECT;
1167 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1171 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1177 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1181 return val & PORTB_HOTPLUG_LONG_DETECT;
1183 return val & PORTC_HOTPLUG_LONG_DETECT;
1185 return val & PORTD_HOTPLUG_LONG_DETECT;
1191 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1195 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1197 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1199 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1206 * Get a bit mask of pins that have triggered, and which ones may be long.
1207 * This can be called multiple times with the same masks to accumulate
1208 * hotplug detection results from several registers.
1210 * Note that the caller is expected to zero out the masks initially.
1212 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1213 u32 *pin_mask, u32 *long_mask,
1214 u32 hotplug_trigger, u32 dig_hotplug_reg,
1215 const u32 hpd[HPD_NUM_PINS],
1216 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1220 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1222 for_each_hpd_pin(pin) {
1223 if ((hpd[pin] & hotplug_trigger) == 0)
1226 *pin_mask |= BIT(pin);
1228 if (long_pulse_detect(pin, dig_hotplug_reg))
1229 *long_mask |= BIT(pin);
1232 drm_dbg(&dev_priv->drm,
1233 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1234 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1238 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
1239 const u32 hpd[HPD_NUM_PINS])
1241 struct intel_encoder *encoder;
1242 u32 enabled_irqs = 0;
1244 for_each_intel_encoder(&dev_priv->drm, encoder)
1245 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
1246 enabled_irqs |= hpd[encoder->hpd_pin];
1248 return enabled_irqs;
1251 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
1252 const u32 hpd[HPD_NUM_PINS])
1254 struct intel_encoder *encoder;
1255 u32 hotplug_irqs = 0;
1257 for_each_intel_encoder(&dev_priv->drm, encoder)
1258 hotplug_irqs |= hpd[encoder->hpd_pin];
1260 return hotplug_irqs;
1263 static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
1264 hotplug_enables_func hotplug_enables)
1266 struct intel_encoder *encoder;
1269 for_each_intel_encoder(&i915->drm, encoder)
1270 hotplug |= hotplug_enables(i915, encoder->hpd_pin);
1275 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1277 wake_up_all(&dev_priv->gmbus_wait_queue);
1280 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1282 wake_up_all(&dev_priv->gmbus_wait_queue);
1285 #if defined(CONFIG_DEBUG_FS)
1286 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1292 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1293 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
1294 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1296 trace_intel_pipe_crc(crtc, crcs);
1298 spin_lock(&pipe_crc->lock);
1300 * For some not yet identified reason, the first CRC is
1301 * bonkers. So let's just wait for the next vblank and read
1302 * out the buggy result.
1304 * On GEN8+ sometimes the second CRC is bonkers as well, so
1305 * don't trust that one either.
1307 if (pipe_crc->skipped <= 0 ||
1308 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1309 pipe_crc->skipped++;
1310 spin_unlock(&pipe_crc->lock);
1313 spin_unlock(&pipe_crc->lock);
1315 drm_crtc_add_crc_entry(&crtc->base, true,
1316 drm_crtc_accurate_vblank_count(&crtc->base),
1321 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1328 static void flip_done_handler(struct drm_i915_private *i915,
1331 struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, pipe);
1332 struct drm_crtc_state *crtc_state = crtc->base.state;
1333 struct drm_pending_vblank_event *e = crtc_state->event;
1334 struct drm_device *dev = &i915->drm;
1335 unsigned long irqflags;
1337 spin_lock_irqsave(&dev->event_lock, irqflags);
1339 crtc_state->event = NULL;
1341 drm_crtc_send_vblank_event(&crtc->base, e);
1343 spin_unlock_irqrestore(&dev->event_lock, irqflags);
1346 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1349 display_pipe_crc_irq_handler(dev_priv, pipe,
1350 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
1354 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1357 display_pipe_crc_irq_handler(dev_priv, pipe,
1358 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
1359 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),
1360 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),
1361 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),
1362 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));
1365 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1370 if (DISPLAY_VER(dev_priv) >= 3)
1371 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe));
1375 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
1376 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe));
1380 display_pipe_crc_irq_handler(dev_priv, pipe,
1381 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)),
1382 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)),
1383 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)),
1387 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1391 for_each_pipe(dev_priv, pipe) {
1392 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),
1393 PIPESTAT_INT_STATUS_MASK |
1394 PIPE_FIFO_UNDERRUN_STATUS);
1396 dev_priv->pipestat_irq_mask[pipe] = 0;
1400 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1401 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1405 spin_lock(&dev_priv->irq_lock);
1407 if (!dev_priv->display_irqs_enabled) {
1408 spin_unlock(&dev_priv->irq_lock);
1412 for_each_pipe(dev_priv, pipe) {
1414 u32 status_mask, enable_mask, iir_bit = 0;
1417 * PIPESTAT bits get signalled even when the interrupt is
1418 * disabled with the mask bits, and some of the status bits do
1419 * not generate interrupts at all (like the underrun bit). Hence
1420 * we need to be careful that we only handle what we want to
1424 /* fifo underruns are filterered in the underrun handler. */
1425 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1430 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1433 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1436 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1440 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1445 reg = PIPESTAT(pipe);
1446 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;
1447 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1450 * Clear the PIPE*STAT regs before the IIR
1452 * Toggle the enable bits to make sure we get an
1453 * edge in the ISR pipe event bit if we don't clear
1454 * all the enabled status bits. Otherwise the edge
1455 * triggered IIR on i965/g4x wouldn't notice that
1456 * an interrupt is still pending.
1458 if (pipe_stats[pipe]) {
1459 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]);
1460 intel_uncore_write(&dev_priv->uncore, reg, enable_mask);
1463 spin_unlock(&dev_priv->irq_lock);
1466 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1467 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1471 for_each_pipe(dev_priv, pipe) {
1472 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1473 intel_handle_vblank(dev_priv, pipe);
1475 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1476 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1478 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1479 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1483 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1484 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1486 bool blc_event = false;
1489 for_each_pipe(dev_priv, pipe) {
1490 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1491 intel_handle_vblank(dev_priv, pipe);
1493 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1496 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1497 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1499 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1500 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1503 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1504 intel_opregion_asle_intr(dev_priv);
1507 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1508 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1510 bool blc_event = false;
1513 for_each_pipe(dev_priv, pipe) {
1514 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1515 intel_handle_vblank(dev_priv, pipe);
1517 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1520 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1521 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1523 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1524 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1527 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1528 intel_opregion_asle_intr(dev_priv);
1530 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1531 gmbus_irq_handler(dev_priv);
1534 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1535 u32 pipe_stats[I915_MAX_PIPES])
1539 for_each_pipe(dev_priv, pipe) {
1540 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1541 intel_handle_vblank(dev_priv, pipe);
1543 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1544 flip_done_handler(dev_priv, pipe);
1546 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1547 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1549 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1550 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1553 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1554 gmbus_irq_handler(dev_priv);
1557 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1559 u32 hotplug_status = 0, hotplug_status_mask;
1562 if (IS_G4X(dev_priv) ||
1563 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1564 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1565 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1567 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1570 * We absolutely have to clear all the pending interrupt
1571 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1572 * interrupt bit won't have an edge, and the i965/g4x
1573 * edge triggered IIR will not notice that an interrupt
1574 * is still pending. We can't use PORT_HOTPLUG_EN to
1575 * guarantee the edge as the act of toggling the enable
1576 * bits can itself generate a new hotplug interrupt :(
1578 for (i = 0; i < 10; i++) {
1579 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;
1582 return hotplug_status;
1584 hotplug_status |= tmp;
1585 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);
1588 drm_WARN_ONCE(&dev_priv->drm, 1,
1589 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1590 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
1592 return hotplug_status;
1595 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1598 u32 pin_mask = 0, long_mask = 0;
1599 u32 hotplug_trigger;
1601 if (IS_G4X(dev_priv) ||
1602 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1603 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1605 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1607 if (hotplug_trigger) {
1608 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1609 hotplug_trigger, hotplug_trigger,
1610 dev_priv->hotplug.hpd,
1611 i9xx_port_hotplug_long_detect);
1613 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1616 if ((IS_G4X(dev_priv) ||
1617 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1618 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1619 dp_aux_irq_handler(dev_priv);
1622 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1624 struct drm_i915_private *dev_priv = arg;
1625 irqreturn_t ret = IRQ_NONE;
1627 if (!intel_irqs_enabled(dev_priv))
1630 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1631 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1634 u32 iir, gt_iir, pm_iir;
1635 u32 pipe_stats[I915_MAX_PIPES] = {};
1636 u32 hotplug_status = 0;
1639 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
1640 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
1641 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
1643 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1649 * Theory on interrupt generation, based on empirical evidence:
1651 * x = ((VLV_IIR & VLV_IER) ||
1652 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1653 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1655 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1656 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1657 * guarantee the CPU interrupt will be raised again even if we
1658 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1659 * bits this time around.
1661 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
1662 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);
1663 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);
1666 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir);
1668 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
1670 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1671 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1673 /* Call regardless, as some status bits might not be
1674 * signalled in iir */
1675 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1677 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1678 I915_LPE_PIPE_B_INTERRUPT))
1679 intel_lpe_audio_irq_handler(dev_priv);
1682 * VLV_IIR is single buffered, and reflects the level
1683 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1686 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
1688 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
1689 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1692 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
1694 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
1697 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1699 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1702 pmu_irq_stats(dev_priv, ret);
1704 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1709 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1711 struct drm_i915_private *dev_priv = arg;
1712 irqreturn_t ret = IRQ_NONE;
1714 if (!intel_irqs_enabled(dev_priv))
1717 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1718 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1721 u32 master_ctl, iir;
1722 u32 pipe_stats[I915_MAX_PIPES] = {};
1723 u32 hotplug_status = 0;
1726 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1727 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
1729 if (master_ctl == 0 && iir == 0)
1735 * Theory on interrupt generation, based on empirical evidence:
1737 * x = ((VLV_IIR & VLV_IER) ||
1738 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1739 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1741 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1742 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1743 * guarantee the CPU interrupt will be raised again even if we
1744 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1745 * bits this time around.
1747 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
1748 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER);
1749 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0);
1751 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
1753 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1754 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1756 /* Call regardless, as some status bits might not be
1757 * signalled in iir */
1758 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1760 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1761 I915_LPE_PIPE_B_INTERRUPT |
1762 I915_LPE_PIPE_C_INTERRUPT))
1763 intel_lpe_audio_irq_handler(dev_priv);
1766 * VLV_IIR is single buffered, and reflects the level
1767 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1770 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
1772 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
1773 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1776 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1778 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1781 pmu_irq_stats(dev_priv, ret);
1783 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1788 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1789 u32 hotplug_trigger)
1791 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1794 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1795 * unless we touch the hotplug register, even if hotplug_trigger is
1796 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1799 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
1800 if (!hotplug_trigger) {
1801 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1802 PORTD_HOTPLUG_STATUS_MASK |
1803 PORTC_HOTPLUG_STATUS_MASK |
1804 PORTB_HOTPLUG_STATUS_MASK;
1805 dig_hotplug_reg &= ~mask;
1808 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
1809 if (!hotplug_trigger)
1812 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1813 hotplug_trigger, dig_hotplug_reg,
1814 dev_priv->hotplug.pch_hpd,
1815 pch_port_hotplug_long_detect);
1817 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1820 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1823 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1825 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1827 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1828 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1829 SDE_AUDIO_POWER_SHIFT);
1830 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
1834 if (pch_iir & SDE_AUX_MASK)
1835 dp_aux_irq_handler(dev_priv);
1837 if (pch_iir & SDE_GMBUS)
1838 gmbus_irq_handler(dev_priv);
1840 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1841 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
1843 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1844 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
1846 if (pch_iir & SDE_POISON)
1847 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1849 if (pch_iir & SDE_FDI_MASK) {
1850 for_each_pipe(dev_priv, pipe)
1851 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1853 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
1856 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1857 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
1859 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1860 drm_dbg(&dev_priv->drm,
1861 "PCH transcoder CRC error interrupt\n");
1863 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1864 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1866 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1867 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1870 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1872 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT);
1875 if (err_int & ERR_INT_POISON)
1876 drm_err(&dev_priv->drm, "Poison interrupt\n");
1878 for_each_pipe(dev_priv, pipe) {
1879 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1880 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1882 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1883 if (IS_IVYBRIDGE(dev_priv))
1884 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1886 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1890 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int);
1893 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1895 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT);
1898 if (serr_int & SERR_INT_POISON)
1899 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1901 for_each_pipe(dev_priv, pipe)
1902 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1903 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1905 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int);
1908 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1911 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1913 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1915 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1916 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1917 SDE_AUDIO_POWER_SHIFT_CPT);
1918 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
1922 if (pch_iir & SDE_AUX_MASK_CPT)
1923 dp_aux_irq_handler(dev_priv);
1925 if (pch_iir & SDE_GMBUS_CPT)
1926 gmbus_irq_handler(dev_priv);
1928 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1929 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
1931 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1932 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
1934 if (pch_iir & SDE_FDI_MASK_CPT) {
1935 for_each_pipe(dev_priv, pipe)
1936 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1938 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));
1941 if (pch_iir & SDE_ERROR_CPT)
1942 cpt_serr_int_handler(dev_priv);
1945 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1947 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
1948 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
1949 u32 pin_mask = 0, long_mask = 0;
1951 if (ddi_hotplug_trigger) {
1952 u32 dig_hotplug_reg;
1954 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
1955 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg);
1957 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1958 ddi_hotplug_trigger, dig_hotplug_reg,
1959 dev_priv->hotplug.pch_hpd,
1960 icp_ddi_port_hotplug_long_detect);
1963 if (tc_hotplug_trigger) {
1964 u32 dig_hotplug_reg;
1966 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
1967 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg);
1969 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1970 tc_hotplug_trigger, dig_hotplug_reg,
1971 dev_priv->hotplug.pch_hpd,
1972 icp_tc_port_hotplug_long_detect);
1976 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1978 if (pch_iir & SDE_GMBUS_ICP)
1979 gmbus_irq_handler(dev_priv);
1982 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1984 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1985 ~SDE_PORTE_HOTPLUG_SPT;
1986 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1987 u32 pin_mask = 0, long_mask = 0;
1989 if (hotplug_trigger) {
1990 u32 dig_hotplug_reg;
1992 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
1993 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
1995 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1996 hotplug_trigger, dig_hotplug_reg,
1997 dev_priv->hotplug.pch_hpd,
1998 spt_port_hotplug_long_detect);
2001 if (hotplug2_trigger) {
2002 u32 dig_hotplug_reg;
2004 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);
2005 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2007 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2008 hotplug2_trigger, dig_hotplug_reg,
2009 dev_priv->hotplug.pch_hpd,
2010 spt_port_hotplug2_long_detect);
2014 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2016 if (pch_iir & SDE_GMBUS_CPT)
2017 gmbus_irq_handler(dev_priv);
2020 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2021 u32 hotplug_trigger)
2023 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2025 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);
2026 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2028 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2029 hotplug_trigger, dig_hotplug_reg,
2030 dev_priv->hotplug.hpd,
2031 ilk_port_hotplug_long_detect);
2033 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2036 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2040 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2042 if (hotplug_trigger)
2043 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2045 if (de_iir & DE_AUX_CHANNEL_A)
2046 dp_aux_irq_handler(dev_priv);
2048 if (de_iir & DE_GSE)
2049 intel_opregion_asle_intr(dev_priv);
2051 if (de_iir & DE_POISON)
2052 drm_err(&dev_priv->drm, "Poison interrupt\n");
2054 for_each_pipe(dev_priv, pipe) {
2055 if (de_iir & DE_PIPE_VBLANK(pipe))
2056 intel_handle_vblank(dev_priv, pipe);
2058 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2059 flip_done_handler(dev_priv, pipe);
2061 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2062 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2064 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2065 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2068 /* check event from PCH */
2069 if (de_iir & DE_PCH_EVENT) {
2070 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2072 if (HAS_PCH_CPT(dev_priv))
2073 cpt_irq_handler(dev_priv, pch_iir);
2075 ibx_irq_handler(dev_priv, pch_iir);
2077 /* should clear PCH hotplug event before clear CPU irq */
2078 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
2081 if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)
2082 gen5_rps_irq_handler(&dev_priv->gt.rps);
2085 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2089 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2091 if (hotplug_trigger)
2092 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2094 if (de_iir & DE_ERR_INT_IVB)
2095 ivb_err_int_handler(dev_priv);
2097 if (de_iir & DE_EDP_PSR_INT_HSW) {
2098 struct intel_encoder *encoder;
2100 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2101 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2103 u32 psr_iir = intel_uncore_read(&dev_priv->uncore,
2106 intel_psr_irq_handler(intel_dp, psr_iir);
2107 intel_uncore_write(&dev_priv->uncore,
2108 EDP_PSR_IIR, psr_iir);
2113 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2114 dp_aux_irq_handler(dev_priv);
2116 if (de_iir & DE_GSE_IVB)
2117 intel_opregion_asle_intr(dev_priv);
2119 for_each_pipe(dev_priv, pipe) {
2120 if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
2121 intel_handle_vblank(dev_priv, pipe);
2123 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2124 flip_done_handler(dev_priv, pipe);
2127 /* check event from PCH */
2128 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2129 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2131 cpt_irq_handler(dev_priv, pch_iir);
2133 /* clear PCH hotplug event before clear CPU irq */
2134 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
2139 * To handle irqs with the minimum potential races with fresh interrupts, we:
2140 * 1 - Disable Master Interrupt Control.
2141 * 2 - Find the source(s) of the interrupt.
2142 * 3 - Clear the Interrupt Identity bits (IIR).
2143 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2144 * 5 - Re-enable Master Interrupt Control.
2146 static irqreturn_t ilk_irq_handler(int irq, void *arg)
2148 struct drm_i915_private *i915 = arg;
2149 void __iomem * const regs = i915->uncore.regs;
2150 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2151 irqreturn_t ret = IRQ_NONE;
2153 if (unlikely(!intel_irqs_enabled(i915)))
2156 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2157 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2159 /* disable master interrupt before clearing iir */
2160 de_ier = raw_reg_read(regs, DEIER);
2161 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2163 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2164 * interrupts will will be stored on its back queue, and then we'll be
2165 * able to process them after we restore SDEIER (as soon as we restore
2166 * it, we'll get an interrupt if SDEIIR still has something to process
2167 * due to its back queue). */
2168 if (!HAS_PCH_NOP(i915)) {
2169 sde_ier = raw_reg_read(regs, SDEIER);
2170 raw_reg_write(regs, SDEIER, 0);
2173 /* Find, clear, then process each source of interrupt */
2175 gt_iir = raw_reg_read(regs, GTIIR);
2177 raw_reg_write(regs, GTIIR, gt_iir);
2178 if (INTEL_GEN(i915) >= 6)
2179 gen6_gt_irq_handler(&i915->gt, gt_iir);
2181 gen5_gt_irq_handler(&i915->gt, gt_iir);
2185 de_iir = raw_reg_read(regs, DEIIR);
2187 raw_reg_write(regs, DEIIR, de_iir);
2188 if (DISPLAY_VER(i915) >= 7)
2189 ivb_display_irq_handler(i915, de_iir);
2191 ilk_display_irq_handler(i915, de_iir);
2195 if (INTEL_GEN(i915) >= 6) {
2196 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2198 raw_reg_write(regs, GEN6_PMIIR, pm_iir);
2199 gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2204 raw_reg_write(regs, DEIER, de_ier);
2206 raw_reg_write(regs, SDEIER, sde_ier);
2208 pmu_irq_stats(i915, ret);
2210 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2211 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2216 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2217 u32 hotplug_trigger)
2219 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2221 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
2222 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg);
2224 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2225 hotplug_trigger, dig_hotplug_reg,
2226 dev_priv->hotplug.hpd,
2227 bxt_port_hotplug_long_detect);
2229 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2232 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2234 u32 pin_mask = 0, long_mask = 0;
2235 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2236 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2239 u32 dig_hotplug_reg;
2241 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
2242 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2244 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2245 trigger_tc, dig_hotplug_reg,
2246 dev_priv->hotplug.hpd,
2247 gen11_port_hotplug_long_detect);
2251 u32 dig_hotplug_reg;
2253 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
2254 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2256 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2257 trigger_tbt, dig_hotplug_reg,
2258 dev_priv->hotplug.hpd,
2259 gen11_port_hotplug_long_detect);
2263 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2265 drm_err(&dev_priv->drm,
2266 "Unexpected DE HPD interrupt 0x%08x\n", iir);
2269 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2273 if (DISPLAY_VER(dev_priv) >= 13)
2274 return TGL_DE_PORT_AUX_DDIA |
2275 TGL_DE_PORT_AUX_DDIB |
2276 TGL_DE_PORT_AUX_DDIC |
2277 XELPD_DE_PORT_AUX_DDID |
2278 XELPD_DE_PORT_AUX_DDIE |
2279 TGL_DE_PORT_AUX_USBC1 |
2280 TGL_DE_PORT_AUX_USBC2 |
2281 TGL_DE_PORT_AUX_USBC3 |
2282 TGL_DE_PORT_AUX_USBC4;
2283 else if (DISPLAY_VER(dev_priv) >= 12)
2284 return TGL_DE_PORT_AUX_DDIA |
2285 TGL_DE_PORT_AUX_DDIB |
2286 TGL_DE_PORT_AUX_DDIC |
2287 TGL_DE_PORT_AUX_USBC1 |
2288 TGL_DE_PORT_AUX_USBC2 |
2289 TGL_DE_PORT_AUX_USBC3 |
2290 TGL_DE_PORT_AUX_USBC4 |
2291 TGL_DE_PORT_AUX_USBC5 |
2292 TGL_DE_PORT_AUX_USBC6;
2295 mask = GEN8_AUX_CHANNEL_A;
2296 if (DISPLAY_VER(dev_priv) >= 9)
2297 mask |= GEN9_AUX_CHANNEL_B |
2298 GEN9_AUX_CHANNEL_C |
2301 if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
2302 mask |= CNL_AUX_CHANNEL_F;
2304 if (DISPLAY_VER(dev_priv) == 11)
2305 mask |= ICL_AUX_CHANNEL_E;
2310 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2312 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
2313 return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
2314 else if (DISPLAY_VER(dev_priv) >= 11)
2315 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
2316 else if (DISPLAY_VER(dev_priv) >= 9)
2317 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2319 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2323 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2327 if (iir & GEN8_DE_MISC_GSE) {
2328 intel_opregion_asle_intr(dev_priv);
2332 if (iir & GEN8_DE_EDP_PSR) {
2333 struct intel_encoder *encoder;
2337 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2338 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2340 if (DISPLAY_VER(dev_priv) >= 12)
2341 iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder);
2343 iir_reg = EDP_PSR_IIR;
2345 psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg);
2346 intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir);
2351 intel_psr_irq_handler(intel_dp, psr_iir);
2353 /* prior GEN12 only have one EDP PSR */
2354 if (DISPLAY_VER(dev_priv) < 12)
2360 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2363 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
2366 enum pipe pipe = INVALID_PIPE;
2367 enum transcoder dsi_trans;
2372 * Incase of dual link, TE comes from DSI_1
2373 * this is to check if dual link is enabled
2375 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
2376 val &= PORT_SYNC_MODE_ENABLE;
2379 * if dual link is enabled, then read DSI_0
2380 * transcoder registers
2382 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
2384 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
2386 /* Check if DSI configured in command mode */
2387 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans));
2388 val = val & OP_MODE_MASK;
2390 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
2391 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
2395 /* Get PIPE for handling VBLANK event */
2396 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));
2397 switch (val & TRANS_DDI_EDP_INPUT_MASK) {
2398 case TRANS_DDI_EDP_INPUT_A_ON:
2401 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2404 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2408 drm_err(&dev_priv->drm, "Invalid PIPE\n");
2412 intel_handle_vblank(dev_priv, pipe);
2414 /* clear TE in dsi IIR */
2415 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
2416 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
2417 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
2420 static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
2422 if (DISPLAY_VER(i915) >= 9)
2423 return GEN9_PIPE_PLANE1_FLIP_DONE;
2425 return GEN8_PIPE_PRIMARY_FLIP_DONE;
2429 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2431 irqreturn_t ret = IRQ_NONE;
2435 drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));
2437 if (master_ctl & GEN8_DE_MISC_IRQ) {
2438 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);
2440 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);
2442 gen8_de_misc_irq_handler(dev_priv, iir);
2444 drm_err(&dev_priv->drm,
2445 "The master control interrupt lied (DE MISC)!\n");
2449 if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2450 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);
2452 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);
2454 gen11_hpd_irq_handler(dev_priv, iir);
2456 drm_err(&dev_priv->drm,
2457 "The master control interrupt lied, (DE HPD)!\n");
2461 if (master_ctl & GEN8_DE_PORT_IRQ) {
2462 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);
2466 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);
2469 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2470 dp_aux_irq_handler(dev_priv);
2474 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
2475 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
2477 if (hotplug_trigger) {
2478 bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
2481 } else if (IS_BROADWELL(dev_priv)) {
2482 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
2484 if (hotplug_trigger) {
2485 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2490 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
2491 (iir & BXT_DE_PORT_GMBUS)) {
2492 gmbus_irq_handler(dev_priv);
2496 if (DISPLAY_VER(dev_priv) >= 11) {
2497 u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
2500 gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
2506 drm_err(&dev_priv->drm,
2507 "Unexpected DE Port interrupt\n");
2510 drm_err(&dev_priv->drm,
2511 "The master control interrupt lied (DE PORT)!\n");
2514 for_each_pipe(dev_priv, pipe) {
2517 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2520 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));
2522 drm_err(&dev_priv->drm,
2523 "The master control interrupt lied (DE PIPE)!\n");
2528 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);
2530 if (iir & GEN8_PIPE_VBLANK)
2531 intel_handle_vblank(dev_priv, pipe);
2533 if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
2534 flip_done_handler(dev_priv, pipe);
2536 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2537 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2539 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2540 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2542 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2544 drm_err(&dev_priv->drm,
2545 "Fault errors on pipe %c: 0x%08x\n",
2550 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2551 master_ctl & GEN8_DE_PCH_IRQ) {
2553 * FIXME(BDW): Assume for now that the new interrupt handling
2554 * scheme also closed the SDE interrupt handling race we've seen
2555 * on older pch-split platforms. But this needs testing.
2557 iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);
2559 intel_uncore_write(&dev_priv->uncore, SDEIIR, iir);
2562 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2563 icp_irq_handler(dev_priv, iir);
2564 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2565 spt_irq_handler(dev_priv, iir);
2567 cpt_irq_handler(dev_priv, iir);
2570 * Like on previous PCH there seems to be something
2571 * fishy going on with forwarding PCH interrupts.
2573 drm_dbg(&dev_priv->drm,
2574 "The master control interrupt lied (SDE)!\n");
2581 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2583 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2586 * Now with master disabled, get a sample of level indications
2587 * for this interrupt. Indications will be cleared on related acks.
2588 * New indications can and will light up during processing,
2589 * and will generate new interrupt after enabling master.
2591 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2594 static inline void gen8_master_intr_enable(void __iomem * const regs)
2596 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2599 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2601 struct drm_i915_private *dev_priv = arg;
2602 void __iomem * const regs = dev_priv->uncore.regs;
2605 if (!intel_irqs_enabled(dev_priv))
2608 master_ctl = gen8_master_intr_disable(regs);
2610 gen8_master_intr_enable(regs);
2614 /* Find, queue (onto bottom-halves), then clear each source */
2615 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2617 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2618 if (master_ctl & ~GEN8_GT_IRQS) {
2619 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2620 gen8_de_irq_handler(dev_priv, master_ctl);
2621 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2624 gen8_master_intr_enable(regs);
2626 pmu_irq_stats(dev_priv, IRQ_HANDLED);
2632 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2634 void __iomem * const regs = gt->uncore->regs;
2637 if (!(master_ctl & GEN11_GU_MISC_IRQ))
2640 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2642 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2648 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2650 if (iir & GEN11_GU_MISC_GSE)
2651 intel_opregion_asle_intr(gt->i915);
2654 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2656 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2659 * Now with master disabled, get a sample of level indications
2660 * for this interrupt. Indications will be cleared on related acks.
2661 * New indications can and will light up during processing,
2662 * and will generate new interrupt after enabling master.
2664 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2667 static inline void gen11_master_intr_enable(void __iomem * const regs)
2669 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2673 gen11_display_irq_handler(struct drm_i915_private *i915)
2675 void __iomem * const regs = i915->uncore.regs;
2676 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2678 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2680 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2681 * for the display related bits.
2683 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
2684 gen8_de_irq_handler(i915, disp_ctl);
2685 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
2686 GEN11_DISPLAY_IRQ_ENABLE);
2688 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2691 static __always_inline irqreturn_t
2692 __gen11_irq_handler(struct drm_i915_private * const i915,
2693 u32 (*intr_disable)(void __iomem * const regs),
2694 void (*intr_enable)(void __iomem * const regs))
2696 void __iomem * const regs = i915->uncore.regs;
2697 struct intel_gt *gt = &i915->gt;
2701 if (!intel_irqs_enabled(i915))
2704 master_ctl = intr_disable(regs);
2710 /* Find, queue (onto bottom-halves), then clear each source */
2711 gen11_gt_irq_handler(gt, master_ctl);
2713 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2714 if (master_ctl & GEN11_DISPLAY_IRQ)
2715 gen11_display_irq_handler(i915);
2717 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2721 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2723 pmu_irq_stats(i915, IRQ_HANDLED);
2728 static irqreturn_t gen11_irq_handler(int irq, void *arg)
2730 return __gen11_irq_handler(arg,
2731 gen11_master_intr_disable,
2732 gen11_master_intr_enable);
2735 static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
2739 /* First disable interrupts */
2740 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
2742 /* Get the indication levels and ack the master unit */
2743 val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
2747 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
2750 * Now with master disabled, get a sample of level indications
2751 * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
2752 * out as this bit doesn't exist anymore for DG1
2754 val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
2758 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
2763 static inline void dg1_master_intr_enable(void __iomem * const regs)
2765 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
2768 static irqreturn_t dg1_irq_handler(int irq, void *arg)
2770 return __gen11_irq_handler(arg,
2771 dg1_master_intr_disable_and_ack,
2772 dg1_master_intr_enable);
2775 /* Called from drm generic code, passed 'crtc' which
2776 * we use as a pipe index
2778 int i8xx_enable_vblank(struct drm_crtc *crtc)
2780 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2781 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2782 unsigned long irqflags;
2784 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2785 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2786 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2791 int i915gm_enable_vblank(struct drm_crtc *crtc)
2793 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2796 * Vblank interrupts fail to wake the device up from C2+.
2797 * Disabling render clock gating during C-states avoids
2798 * the problem. There is a small power cost so we do this
2799 * only when vblank interrupts are actually enabled.
2801 if (dev_priv->vblank_enabled++ == 0)
2802 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2804 return i8xx_enable_vblank(crtc);
2807 int i965_enable_vblank(struct drm_crtc *crtc)
2809 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2810 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2811 unsigned long irqflags;
2813 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2814 i915_enable_pipestat(dev_priv, pipe,
2815 PIPE_START_VBLANK_INTERRUPT_STATUS);
2816 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2821 int ilk_enable_vblank(struct drm_crtc *crtc)
2823 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2824 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2825 unsigned long irqflags;
2826 u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
2827 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2829 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2830 ilk_enable_display_irq(dev_priv, bit);
2831 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2833 /* Even though there is no DMC, frame counter can get stuck when
2834 * PSR is active as no frames are generated.
2836 if (HAS_PSR(dev_priv))
2837 drm_crtc_vblank_restore(crtc);
2842 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
2845 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
2849 if (!(intel_crtc->mode_flags &
2850 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
2853 /* for dual link cases we consider TE from slave */
2854 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
2859 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port));
2861 tmp &= ~DSI_TE_EVENT;
2863 tmp |= DSI_TE_EVENT;
2865 intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp);
2867 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port));
2868 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
2873 int bdw_enable_vblank(struct drm_crtc *crtc)
2875 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2877 enum pipe pipe = intel_crtc->pipe;
2878 unsigned long irqflags;
2880 if (gen11_dsi_configure_te(intel_crtc, true))
2883 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2884 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2885 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2887 /* Even if there is no DMC, frame counter can get stuck when
2888 * PSR is active as no frames are generated, so check only for PSR.
2890 if (HAS_PSR(dev_priv))
2891 drm_crtc_vblank_restore(crtc);
2896 /* Called from drm generic code, passed 'crtc' which
2897 * we use as a pipe index
2899 void i8xx_disable_vblank(struct drm_crtc *crtc)
2901 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2902 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2903 unsigned long irqflags;
2905 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2906 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2907 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2910 void i915gm_disable_vblank(struct drm_crtc *crtc)
2912 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2914 i8xx_disable_vblank(crtc);
2916 if (--dev_priv->vblank_enabled == 0)
2917 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2920 void i965_disable_vblank(struct drm_crtc *crtc)
2922 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2923 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2924 unsigned long irqflags;
2926 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2927 i915_disable_pipestat(dev_priv, pipe,
2928 PIPE_START_VBLANK_INTERRUPT_STATUS);
2929 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2932 void ilk_disable_vblank(struct drm_crtc *crtc)
2934 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2935 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2936 unsigned long irqflags;
2937 u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
2938 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2940 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2941 ilk_disable_display_irq(dev_priv, bit);
2942 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2945 void bdw_disable_vblank(struct drm_crtc *crtc)
2947 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2949 enum pipe pipe = intel_crtc->pipe;
2950 unsigned long irqflags;
2952 if (gen11_dsi_configure_te(intel_crtc, false))
2955 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2956 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2957 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2960 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2962 struct intel_uncore *uncore = &dev_priv->uncore;
2964 if (HAS_PCH_NOP(dev_priv))
2967 GEN3_IRQ_RESET(uncore, SDE);
2969 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2970 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);
2973 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2975 struct intel_uncore *uncore = &dev_priv->uncore;
2977 if (IS_CHERRYVIEW(dev_priv))
2978 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2980 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
2982 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2983 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
2985 i9xx_pipestat_irq_reset(dev_priv);
2987 GEN3_IRQ_RESET(uncore, VLV_);
2988 dev_priv->irq_mask = ~0u;
2991 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2993 struct intel_uncore *uncore = &dev_priv->uncore;
2999 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
3001 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3002 for_each_pipe(dev_priv, pipe)
3003 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3005 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3006 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3007 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3008 I915_LPE_PIPE_A_INTERRUPT |
3009 I915_LPE_PIPE_B_INTERRUPT;
3011 if (IS_CHERRYVIEW(dev_priv))
3012 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
3013 I915_LPE_PIPE_C_INTERRUPT;
3015 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
3017 dev_priv->irq_mask = ~enable_mask;
3019 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
3024 static void ilk_irq_reset(struct drm_i915_private *dev_priv)
3026 struct intel_uncore *uncore = &dev_priv->uncore;
3028 GEN3_IRQ_RESET(uncore, DE);
3029 dev_priv->irq_mask = ~0u;
3031 if (IS_GEN(dev_priv, 7))
3032 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
3034 if (IS_HASWELL(dev_priv)) {
3035 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3036 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3039 gen5_gt_irq_reset(&dev_priv->gt);
3041 ibx_irq_reset(dev_priv);
3044 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
3046 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
3047 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
3049 gen5_gt_irq_reset(&dev_priv->gt);
3051 spin_lock_irq(&dev_priv->irq_lock);
3052 if (dev_priv->display_irqs_enabled)
3053 vlv_display_irq_reset(dev_priv);
3054 spin_unlock_irq(&dev_priv->irq_lock);
3057 static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
3059 struct intel_uncore *uncore = &dev_priv->uncore;
3062 * Wa_14010685332:cnp/cmp,tgp,adp
3063 * TODO: Clarify which platforms this applies to
3064 * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
3065 * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
3067 if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
3068 (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
3069 intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
3070 SBCLK_RUN_REFCLK_DIS);
3071 intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
3075 static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
3077 struct intel_uncore *uncore = &dev_priv->uncore;
3080 if (!HAS_DISPLAY(dev_priv))
3083 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3084 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3086 for_each_pipe(dev_priv, pipe)
3087 if (intel_display_power_is_enabled(dev_priv,
3088 POWER_DOMAIN_PIPE(pipe)))
3089 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3091 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3092 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3095 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
3097 struct intel_uncore *uncore = &dev_priv->uncore;
3099 gen8_master_intr_disable(dev_priv->uncore.regs);
3101 gen8_gt_irq_reset(&dev_priv->gt);
3102 gen8_display_irq_reset(dev_priv);
3103 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3105 if (HAS_PCH_SPLIT(dev_priv))
3106 ibx_irq_reset(dev_priv);
3108 cnp_display_clock_wa(dev_priv);
3111 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
3113 struct intel_uncore *uncore = &dev_priv->uncore;
3115 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3116 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3118 if (!HAS_DISPLAY(dev_priv))
3121 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3123 if (DISPLAY_VER(dev_priv) >= 12) {
3124 enum transcoder trans;
3126 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3127 enum intel_display_power_domain domain;
3129 domain = POWER_DOMAIN_TRANSCODER(trans);
3130 if (!intel_display_power_is_enabled(dev_priv, domain))
3133 intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
3134 intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
3137 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3138 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3141 for_each_pipe(dev_priv, pipe)
3142 if (intel_display_power_is_enabled(dev_priv,
3143 POWER_DOMAIN_PIPE(pipe)))
3144 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3146 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3147 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3148 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3150 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3151 GEN3_IRQ_RESET(uncore, SDE);
3153 cnp_display_clock_wa(dev_priv);
3156 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
3158 struct intel_uncore *uncore = &dev_priv->uncore;
3160 if (HAS_MASTER_UNIT_IRQ(dev_priv))
3161 dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
3163 gen11_master_intr_disable(dev_priv->uncore.regs);
3165 gen11_gt_irq_reset(&dev_priv->gt);
3166 gen11_display_irq_reset(dev_priv);
3168 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3169 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3172 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3175 struct intel_uncore *uncore = &dev_priv->uncore;
3176 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
3177 gen8_de_pipe_flip_done_mask(dev_priv);
3180 spin_lock_irq(&dev_priv->irq_lock);
3182 if (!intel_irqs_enabled(dev_priv)) {
3183 spin_unlock_irq(&dev_priv->irq_lock);
3187 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3188 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3189 dev_priv->de_irq_mask[pipe],
3190 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3192 spin_unlock_irq(&dev_priv->irq_lock);
3195 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3198 struct intel_uncore *uncore = &dev_priv->uncore;
3201 spin_lock_irq(&dev_priv->irq_lock);
3203 if (!intel_irqs_enabled(dev_priv)) {
3204 spin_unlock_irq(&dev_priv->irq_lock);
3208 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3209 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3211 spin_unlock_irq(&dev_priv->irq_lock);
3213 /* make sure we're done processing display irqs */
3214 intel_synchronize_irq(dev_priv);
3217 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3219 struct intel_uncore *uncore = &dev_priv->uncore;
3221 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
3222 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
3224 gen8_gt_irq_reset(&dev_priv->gt);
3226 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3228 spin_lock_irq(&dev_priv->irq_lock);
3229 if (dev_priv->display_irqs_enabled)
3230 vlv_display_irq_reset(dev_priv);
3231 spin_unlock_irq(&dev_priv->irq_lock);
3234 static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
3240 * When CPU and PCH are on the same package, port A
3241 * HPD must be enabled in both north and south.
3243 return HAS_PCH_LPT_LP(i915) ?
3244 PORTA_HOTPLUG_ENABLE : 0;
3246 return PORTB_HOTPLUG_ENABLE |
3247 PORTB_PULSE_DURATION_2ms;
3249 return PORTC_HOTPLUG_ENABLE |
3250 PORTC_PULSE_DURATION_2ms;
3252 return PORTD_HOTPLUG_ENABLE |
3253 PORTD_PULSE_DURATION_2ms;
3259 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3264 * Enable digital hotplug on the PCH, and configure the DP short pulse
3265 * duration to 2ms (which is the minimum in the Display Port spec).
3266 * The pulse duration bits are reserved on LPT+.
3268 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3269 hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3270 PORTB_HOTPLUG_ENABLE |
3271 PORTC_HOTPLUG_ENABLE |
3272 PORTD_HOTPLUG_ENABLE |
3273 PORTB_PULSE_DURATION_MASK |
3274 PORTC_PULSE_DURATION_MASK |
3275 PORTD_PULSE_DURATION_MASK);
3276 hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
3277 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3280 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3282 u32 hotplug_irqs, enabled_irqs;
3284 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3285 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3287 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3289 ibx_hpd_detection_setup(dev_priv);
3292 static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
3300 return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
3306 static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
3316 return ICP_TC_HPD_ENABLE(pin);
3322 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
3326 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
3327 hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
3328 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
3329 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) |
3330 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D));
3331 hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);
3332 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug);
3335 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
3339 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
3340 hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
3341 ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
3342 ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
3343 ICP_TC_HPD_ENABLE(HPD_PORT_TC4) |
3344 ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
3345 ICP_TC_HPD_ENABLE(HPD_PORT_TC6));
3346 hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);
3347 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug);
3350 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3352 u32 hotplug_irqs, enabled_irqs;
3354 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3355 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3357 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
3358 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3360 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3362 icp_ddi_hpd_detection_setup(dev_priv);
3363 icp_tc_hpd_detection_setup(dev_priv);
3366 static u32 gen11_hotplug_enables(struct drm_i915_private *i915,
3376 return GEN11_HOTPLUG_CTL_ENABLE(pin);
3382 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
3386 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);
3387 val |= (INVERT_DDIA_HPD |
3391 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);
3393 icp_hpd_irq_setup(dev_priv);
3396 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
3400 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL);
3401 hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
3402 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
3403 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
3404 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
3405 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
3406 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
3407 hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
3408 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug);
3411 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3415 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL);
3416 hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
3417 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
3418 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
3419 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
3420 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
3421 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
3422 hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
3423 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug);
3426 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3428 u32 hotplug_irqs, enabled_irqs;
3431 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3432 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3434 val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
3435 val &= ~hotplug_irqs;
3436 val |= ~enabled_irqs & hotplug_irqs;
3437 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val);
3438 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
3440 gen11_tc_hpd_detection_setup(dev_priv);
3441 gen11_tbt_hpd_detection_setup(dev_priv);
3443 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3444 icp_hpd_irq_setup(dev_priv);
3447 static u32 spt_hotplug_enables(struct drm_i915_private *i915,
3452 return PORTA_HOTPLUG_ENABLE;
3454 return PORTB_HOTPLUG_ENABLE;
3456 return PORTC_HOTPLUG_ENABLE;
3458 return PORTD_HOTPLUG_ENABLE;
3464 static u32 spt_hotplug2_enables(struct drm_i915_private *i915,
3469 return PORTE_HOTPLUG_ENABLE;
3475 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3479 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3480 if (HAS_PCH_CNP(dev_priv)) {
3481 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1);
3482 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3483 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3484 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val);
3487 /* Enable digital hotplug on the PCH */
3488 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3489 hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3490 PORTB_HOTPLUG_ENABLE |
3491 PORTC_HOTPLUG_ENABLE |
3492 PORTD_HOTPLUG_ENABLE);
3493 hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);
3494 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3496 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2);
3497 hotplug &= ~PORTE_HOTPLUG_ENABLE;
3498 hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);
3499 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug);
3502 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3504 u32 hotplug_irqs, enabled_irqs;
3506 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3507 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3509 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3510 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3512 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3514 spt_hpd_detection_setup(dev_priv);
3517 static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
3522 return DIGITAL_PORTA_HOTPLUG_ENABLE |
3523 DIGITAL_PORTA_PULSE_DURATION_2ms;
3529 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3534 * Enable digital hotplug on the CPU, and configure the DP short pulse
3535 * duration to 2ms (which is the minimum in the Display Port spec)
3536 * The pulse duration bits are reserved on HSW+.
3538 hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL);
3539 hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE |
3540 DIGITAL_PORTA_PULSE_DURATION_MASK);
3541 hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);
3542 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3545 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3547 u32 hotplug_irqs, enabled_irqs;
3549 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3550 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3552 if (DISPLAY_VER(dev_priv) >= 8)
3553 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3555 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3557 ilk_hpd_detection_setup(dev_priv);
3559 ibx_hpd_irq_setup(dev_priv);
3562 static u32 bxt_hotplug_enables(struct drm_i915_private *i915,
3569 hotplug = PORTA_HOTPLUG_ENABLE;
3570 if (intel_bios_is_port_hpd_inverted(i915, PORT_A))
3571 hotplug |= BXT_DDIA_HPD_INVERT;
3574 hotplug = PORTB_HOTPLUG_ENABLE;
3575 if (intel_bios_is_port_hpd_inverted(i915, PORT_B))
3576 hotplug |= BXT_DDIB_HPD_INVERT;
3579 hotplug = PORTC_HOTPLUG_ENABLE;
3580 if (intel_bios_is_port_hpd_inverted(i915, PORT_C))
3581 hotplug |= BXT_DDIC_HPD_INVERT;
3588 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3592 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG);
3593 hotplug &= ~(PORTA_HOTPLUG_ENABLE |
3594 PORTB_HOTPLUG_ENABLE |
3595 PORTC_HOTPLUG_ENABLE |
3596 BXT_DDIA_HPD_INVERT |
3597 BXT_DDIB_HPD_INVERT |
3598 BXT_DDIC_HPD_INVERT);
3599 hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);
3600 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug);
3603 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3605 u32 hotplug_irqs, enabled_irqs;
3607 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3608 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3610 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3612 bxt_hpd_detection_setup(dev_priv);
3616 * SDEIER is also touched by the interrupt handler to work around missed PCH
3617 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3618 * instead we unconditionally enable all PCH interrupt sources here, but then
3619 * only unmask them as needed with SDEIMR.
3621 * Note that we currently do this after installing the interrupt handler,
3622 * but before we enable the master interrupt. That should be sufficient
3623 * to avoid races with the irq handler, assuming we have MSI. Shared legacy
3624 * interrupts could still race.
3626 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3628 struct intel_uncore *uncore = &dev_priv->uncore;
3631 if (HAS_PCH_NOP(dev_priv))
3634 if (HAS_PCH_IBX(dev_priv))
3635 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3636 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3637 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3639 mask = SDE_GMBUS_CPT;
3641 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
3644 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3646 struct intel_uncore *uncore = &dev_priv->uncore;
3647 u32 display_mask, extra_mask;
3649 if (INTEL_GEN(dev_priv) >= 7) {
3650 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3651 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3652 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3653 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3654 DE_PLANE_FLIP_DONE_IVB(PLANE_C) |
3655 DE_PLANE_FLIP_DONE_IVB(PLANE_B) |
3656 DE_PLANE_FLIP_DONE_IVB(PLANE_A) |
3657 DE_DP_A_HOTPLUG_IVB);
3659 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3660 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3661 DE_PIPEA_CRC_DONE | DE_POISON);
3662 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
3663 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3664 DE_PLANE_FLIP_DONE(PLANE_A) |
3665 DE_PLANE_FLIP_DONE(PLANE_B) |
3669 if (IS_HASWELL(dev_priv)) {
3670 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3671 display_mask |= DE_EDP_PSR_INT_HSW;
3674 if (IS_IRONLAKE_M(dev_priv))
3675 extra_mask |= DE_PCU_EVENT;
3677 dev_priv->irq_mask = ~display_mask;
3679 ibx_irq_postinstall(dev_priv);
3681 gen5_gt_irq_postinstall(&dev_priv->gt);
3683 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3684 display_mask | extra_mask);
3687 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3689 lockdep_assert_held(&dev_priv->irq_lock);
3691 if (dev_priv->display_irqs_enabled)
3694 dev_priv->display_irqs_enabled = true;
3696 if (intel_irqs_enabled(dev_priv)) {
3697 vlv_display_irq_reset(dev_priv);
3698 vlv_display_irq_postinstall(dev_priv);
3702 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3704 lockdep_assert_held(&dev_priv->irq_lock);
3706 if (!dev_priv->display_irqs_enabled)
3709 dev_priv->display_irqs_enabled = false;
3711 if (intel_irqs_enabled(dev_priv))
3712 vlv_display_irq_reset(dev_priv);
3716 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3718 gen5_gt_irq_postinstall(&dev_priv->gt);
3720 spin_lock_irq(&dev_priv->irq_lock);
3721 if (dev_priv->display_irqs_enabled)
3722 vlv_display_irq_postinstall(dev_priv);
3723 spin_unlock_irq(&dev_priv->irq_lock);
3725 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3726 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
3729 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3731 struct intel_uncore *uncore = &dev_priv->uncore;
3733 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3734 GEN8_PIPE_CDCLK_CRC_DONE;
3735 u32 de_pipe_enables;
3736 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
3737 u32 de_port_enables;
3738 u32 de_misc_masked = GEN8_DE_EDP_PSR;
3739 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3740 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3743 if (!HAS_DISPLAY(dev_priv))
3746 if (DISPLAY_VER(dev_priv) <= 10)
3747 de_misc_masked |= GEN8_DE_MISC_GSE;
3749 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3750 de_port_masked |= BXT_DE_PORT_GMBUS;
3752 if (DISPLAY_VER(dev_priv) >= 11) {
3755 if (intel_bios_is_dsi_present(dev_priv, &port))
3756 de_port_masked |= DSI0_TE | DSI1_TE;
3759 de_pipe_enables = de_pipe_masked |
3760 GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
3761 gen8_de_pipe_flip_done_mask(dev_priv);
3763 de_port_enables = de_port_masked;
3764 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3765 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3766 else if (IS_BROADWELL(dev_priv))
3767 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
3769 if (DISPLAY_VER(dev_priv) >= 12) {
3770 enum transcoder trans;
3772 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3773 enum intel_display_power_domain domain;
3775 domain = POWER_DOMAIN_TRANSCODER(trans);
3776 if (!intel_display_power_is_enabled(dev_priv, domain))
3779 gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
3782 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3785 for_each_pipe(dev_priv, pipe) {
3786 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3788 if (intel_display_power_is_enabled(dev_priv,
3789 POWER_DOMAIN_PIPE(pipe)))
3790 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3791 dev_priv->de_irq_mask[pipe],
3795 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3796 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3798 if (DISPLAY_VER(dev_priv) >= 11) {
3799 u32 de_hpd_masked = 0;
3800 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3801 GEN11_DE_TBT_HOTPLUG_MASK;
3803 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3808 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3810 struct intel_uncore *uncore = &dev_priv->uncore;
3811 u32 mask = SDE_GMBUS_ICP;
3813 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
3816 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3818 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3819 icp_irq_postinstall(dev_priv);
3820 else if (HAS_PCH_SPLIT(dev_priv))
3821 ibx_irq_postinstall(dev_priv);
3823 gen8_gt_irq_postinstall(&dev_priv->gt);
3824 gen8_de_irq_postinstall(dev_priv);
3826 gen8_master_intr_enable(dev_priv->uncore.regs);
3829 static void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)
3831 if (!HAS_DISPLAY(dev_priv))
3834 gen8_de_irq_postinstall(dev_priv);
3836 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,
3837 GEN11_DISPLAY_IRQ_ENABLE);
3840 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3842 struct intel_uncore *uncore = &dev_priv->uncore;
3843 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3845 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3846 icp_irq_postinstall(dev_priv);
3848 gen11_gt_irq_postinstall(&dev_priv->gt);
3849 gen11_de_irq_postinstall(dev_priv);
3851 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3853 if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
3854 dg1_master_intr_enable(uncore->regs);
3855 intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR);
3857 gen11_master_intr_enable(uncore->regs);
3858 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
3862 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3864 gen8_gt_irq_postinstall(&dev_priv->gt);
3866 spin_lock_irq(&dev_priv->irq_lock);
3867 if (dev_priv->display_irqs_enabled)
3868 vlv_display_irq_postinstall(dev_priv);
3869 spin_unlock_irq(&dev_priv->irq_lock);
3871 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3872 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
3875 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3877 struct intel_uncore *uncore = &dev_priv->uncore;
3879 i9xx_pipestat_irq_reset(dev_priv);
3881 GEN2_IRQ_RESET(uncore);
3882 dev_priv->irq_mask = ~0u;
3885 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3887 struct intel_uncore *uncore = &dev_priv->uncore;
3890 intel_uncore_write16(uncore,
3892 ~(I915_ERROR_PAGE_TABLE |
3893 I915_ERROR_MEMORY_REFRESH));
3895 /* Unmask the interrupts that we always want on. */
3896 dev_priv->irq_mask =
3897 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3898 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3899 I915_MASTER_ERROR_INTERRUPT);
3902 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3903 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3904 I915_MASTER_ERROR_INTERRUPT |
3905 I915_USER_INTERRUPT;
3907 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3909 /* Interrupt setup is already guaranteed to be single-threaded, this is
3910 * just to make the assert_spin_locked check happy. */
3911 spin_lock_irq(&dev_priv->irq_lock);
3912 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3913 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3914 spin_unlock_irq(&dev_priv->irq_lock);
3917 static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3918 u16 *eir, u16 *eir_stuck)
3920 struct intel_uncore *uncore = &i915->uncore;
3923 *eir = intel_uncore_read16(uncore, EIR);
3926 intel_uncore_write16(uncore, EIR, *eir);
3928 *eir_stuck = intel_uncore_read16(uncore, EIR);
3929 if (*eir_stuck == 0)
3933 * Toggle all EMR bits to make sure we get an edge
3934 * in the ISR master error bit if we don't clear
3935 * all the EIR bits. Otherwise the edge triggered
3936 * IIR on i965/g4x wouldn't notice that an interrupt
3937 * is still pending. Also some EIR bits can't be
3938 * cleared except by handling the underlying error
3939 * (or by a GPU reset) so we mask any bit that
3942 emr = intel_uncore_read16(uncore, EMR);
3943 intel_uncore_write16(uncore, EMR, 0xffff);
3944 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3947 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3948 u16 eir, u16 eir_stuck)
3950 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3953 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
3957 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3958 u32 *eir, u32 *eir_stuck)
3962 *eir = intel_uncore_read(&dev_priv->uncore, EIR);
3964 intel_uncore_write(&dev_priv->uncore, EIR, *eir);
3966 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);
3967 if (*eir_stuck == 0)
3971 * Toggle all EMR bits to make sure we get an edge
3972 * in the ISR master error bit if we don't clear
3973 * all the EIR bits. Otherwise the edge triggered
3974 * IIR on i965/g4x wouldn't notice that an interrupt
3975 * is still pending. Also some EIR bits can't be
3976 * cleared except by handling the underlying error
3977 * (or by a GPU reset) so we mask any bit that
3980 emr = intel_uncore_read(&dev_priv->uncore, EMR);
3981 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);
3982 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);
3985 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
3986 u32 eir, u32 eir_stuck)
3988 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
3991 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
3995 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3997 struct drm_i915_private *dev_priv = arg;
3998 irqreturn_t ret = IRQ_NONE;
4000 if (!intel_irqs_enabled(dev_priv))
4003 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4004 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4007 u32 pipe_stats[I915_MAX_PIPES] = {};
4008 u16 eir = 0, eir_stuck = 0;
4011 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
4017 /* Call regardless, as some status bits might not be
4018 * signalled in iir */
4019 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4021 if (iir & I915_MASTER_ERROR_INTERRUPT)
4022 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4024 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
4026 if (iir & I915_USER_INTERRUPT)
4027 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir);
4029 if (iir & I915_MASTER_ERROR_INTERRUPT)
4030 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
4032 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4035 pmu_irq_stats(dev_priv, ret);
4037 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4042 static void i915_irq_reset(struct drm_i915_private *dev_priv)
4044 struct intel_uncore *uncore = &dev_priv->uncore;
4046 if (I915_HAS_HOTPLUG(dev_priv)) {
4047 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4048 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
4051 i9xx_pipestat_irq_reset(dev_priv);
4053 GEN3_IRQ_RESET(uncore, GEN2_);
4054 dev_priv->irq_mask = ~0u;
4057 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
4059 struct intel_uncore *uncore = &dev_priv->uncore;
4062 intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE |
4063 I915_ERROR_MEMORY_REFRESH));
4065 /* Unmask the interrupts that we always want on. */
4066 dev_priv->irq_mask =
4067 ~(I915_ASLE_INTERRUPT |
4068 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4069 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4070 I915_MASTER_ERROR_INTERRUPT);
4073 I915_ASLE_INTERRUPT |
4074 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4075 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4076 I915_MASTER_ERROR_INTERRUPT |
4077 I915_USER_INTERRUPT;
4079 if (I915_HAS_HOTPLUG(dev_priv)) {
4080 /* Enable in IER... */
4081 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4082 /* and unmask in IMR */
4083 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4086 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4088 /* Interrupt setup is already guaranteed to be single-threaded, this is
4089 * just to make the assert_spin_locked check happy. */
4090 spin_lock_irq(&dev_priv->irq_lock);
4091 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4092 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4093 spin_unlock_irq(&dev_priv->irq_lock);
4095 i915_enable_asle_pipestat(dev_priv);
4098 static irqreturn_t i915_irq_handler(int irq, void *arg)
4100 struct drm_i915_private *dev_priv = arg;
4101 irqreturn_t ret = IRQ_NONE;
4103 if (!intel_irqs_enabled(dev_priv))
4106 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4107 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4110 u32 pipe_stats[I915_MAX_PIPES] = {};
4111 u32 eir = 0, eir_stuck = 0;
4112 u32 hotplug_status = 0;
4115 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
4121 if (I915_HAS_HOTPLUG(dev_priv) &&
4122 iir & I915_DISPLAY_PORT_INTERRUPT)
4123 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4125 /* Call regardless, as some status bits might not be
4126 * signalled in iir */
4127 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4129 if (iir & I915_MASTER_ERROR_INTERRUPT)
4130 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4132 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
4134 if (iir & I915_USER_INTERRUPT)
4135 intel_engine_cs_irq(dev_priv->gt.engine[RCS0], iir);
4137 if (iir & I915_MASTER_ERROR_INTERRUPT)
4138 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4141 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4143 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4146 pmu_irq_stats(dev_priv, ret);
4148 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4153 static void i965_irq_reset(struct drm_i915_private *dev_priv)
4155 struct intel_uncore *uncore = &dev_priv->uncore;
4157 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4158 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
4160 i9xx_pipestat_irq_reset(dev_priv);
4162 GEN3_IRQ_RESET(uncore, GEN2_);
4163 dev_priv->irq_mask = ~0u;
4166 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
4168 struct intel_uncore *uncore = &dev_priv->uncore;
4173 * Enable some error detection, note the instruction error mask
4174 * bit is reserved, so we leave it masked.
4176 if (IS_G4X(dev_priv)) {
4177 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4178 GM45_ERROR_MEM_PRIV |
4179 GM45_ERROR_CP_PRIV |
4180 I915_ERROR_MEMORY_REFRESH);
4182 error_mask = ~(I915_ERROR_PAGE_TABLE |
4183 I915_ERROR_MEMORY_REFRESH);
4185 intel_uncore_write(&dev_priv->uncore, EMR, error_mask);
4187 /* Unmask the interrupts that we always want on. */
4188 dev_priv->irq_mask =
4189 ~(I915_ASLE_INTERRUPT |
4190 I915_DISPLAY_PORT_INTERRUPT |
4191 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4192 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4193 I915_MASTER_ERROR_INTERRUPT);
4196 I915_ASLE_INTERRUPT |
4197 I915_DISPLAY_PORT_INTERRUPT |
4198 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4199 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4200 I915_MASTER_ERROR_INTERRUPT |
4201 I915_USER_INTERRUPT;
4203 if (IS_G4X(dev_priv))
4204 enable_mask |= I915_BSD_USER_INTERRUPT;
4206 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4208 /* Interrupt setup is already guaranteed to be single-threaded, this is
4209 * just to make the assert_spin_locked check happy. */
4210 spin_lock_irq(&dev_priv->irq_lock);
4211 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4212 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4213 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4214 spin_unlock_irq(&dev_priv->irq_lock);
4216 i915_enable_asle_pipestat(dev_priv);
4219 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4223 lockdep_assert_held(&dev_priv->irq_lock);
4225 /* Note HDMI and DP share hotplug bits */
4226 /* enable bits are the same for all generations */
4227 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4228 /* Programming the CRT detection parameters tends
4229 to generate a spurious hotplug event about three
4230 seconds later. So just do it once.
4232 if (IS_G4X(dev_priv))
4233 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4234 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4236 /* Ignore TV since it's buggy */
4237 i915_hotplug_interrupt_update_locked(dev_priv,
4238 HOTPLUG_INT_EN_MASK |
4239 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4240 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4244 static irqreturn_t i965_irq_handler(int irq, void *arg)
4246 struct drm_i915_private *dev_priv = arg;
4247 irqreturn_t ret = IRQ_NONE;
4249 if (!intel_irqs_enabled(dev_priv))
4252 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4253 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4256 u32 pipe_stats[I915_MAX_PIPES] = {};
4257 u32 eir = 0, eir_stuck = 0;
4258 u32 hotplug_status = 0;
4261 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
4267 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4268 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4270 /* Call regardless, as some status bits might not be
4271 * signalled in iir */
4272 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4274 if (iir & I915_MASTER_ERROR_INTERRUPT)
4275 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4277 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
4279 if (iir & I915_USER_INTERRUPT)
4280 intel_engine_cs_irq(dev_priv->gt.engine[RCS0],
4283 if (iir & I915_BSD_USER_INTERRUPT)
4284 intel_engine_cs_irq(dev_priv->gt.engine[VCS0],
4287 if (iir & I915_MASTER_ERROR_INTERRUPT)
4288 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4291 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4293 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4296 pmu_irq_stats(dev_priv, IRQ_HANDLED);
4298 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4304 * intel_irq_init - initializes irq support
4305 * @dev_priv: i915 device instance
4307 * This function initializes all the irq support including work items, timers
4308 * and all the vtables. It does not setup the interrupt itself though.
4310 void intel_irq_init(struct drm_i915_private *dev_priv)
4312 struct drm_device *dev = &dev_priv->drm;
4315 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4316 for (i = 0; i < MAX_L3_SLICES; ++i)
4317 dev_priv->l3_parity.remap_info[i] = NULL;
4319 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
4320 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
4321 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4323 if (!HAS_DISPLAY(dev_priv))
4326 intel_hpd_init_pins(dev_priv);
4328 intel_hpd_init_work(dev_priv);
4330 dev->vblank_disable_immediate = true;
4332 /* Most platforms treat the display irq block as an always-on
4333 * power domain. vlv/chv can disable it at runtime and need
4334 * special care to avoid writing any of the display block registers
4335 * outside of the power domain. We defer setting up the display irqs
4336 * in this case to the runtime pm.
4338 dev_priv->display_irqs_enabled = true;
4339 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4340 dev_priv->display_irqs_enabled = false;
4342 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4343 /* If we have MST support, we want to avoid doing short HPD IRQ storm
4344 * detection, as short HPD storms will occur as a natural part of
4345 * sideband messaging with MST.
4346 * On older platforms however, IRQ storms can occur with both long and
4347 * short pulses, as seen on some G4x systems.
4349 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4351 if (HAS_GMCH(dev_priv)) {
4352 if (I915_HAS_HOTPLUG(dev_priv))
4353 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4355 if (HAS_PCH_DG1(dev_priv))
4356 dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
4357 else if (DISPLAY_VER(dev_priv) >= 11)
4358 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4359 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4360 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4361 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
4362 dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
4363 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4364 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4366 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4371 * intel_irq_fini - deinitializes IRQ support
4372 * @i915: i915 device instance
4374 * This function deinitializes all the IRQ support.
4376 void intel_irq_fini(struct drm_i915_private *i915)
4380 for (i = 0; i < MAX_L3_SLICES; ++i)
4381 kfree(i915->l3_parity.remap_info[i]);
4384 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4386 if (HAS_GMCH(dev_priv)) {
4387 if (IS_CHERRYVIEW(dev_priv))
4388 return cherryview_irq_handler;
4389 else if (IS_VALLEYVIEW(dev_priv))
4390 return valleyview_irq_handler;
4391 else if (IS_GEN(dev_priv, 4))
4392 return i965_irq_handler;
4393 else if (IS_GEN(dev_priv, 3))
4394 return i915_irq_handler;
4396 return i8xx_irq_handler;
4398 if (HAS_MASTER_UNIT_IRQ(dev_priv))
4399 return dg1_irq_handler;
4400 if (INTEL_GEN(dev_priv) >= 11)
4401 return gen11_irq_handler;
4402 else if (INTEL_GEN(dev_priv) >= 8)
4403 return gen8_irq_handler;
4405 return ilk_irq_handler;
4409 static void intel_irq_reset(struct drm_i915_private *dev_priv)
4411 if (HAS_GMCH(dev_priv)) {
4412 if (IS_CHERRYVIEW(dev_priv))
4413 cherryview_irq_reset(dev_priv);
4414 else if (IS_VALLEYVIEW(dev_priv))
4415 valleyview_irq_reset(dev_priv);
4416 else if (IS_GEN(dev_priv, 4))
4417 i965_irq_reset(dev_priv);
4418 else if (IS_GEN(dev_priv, 3))
4419 i915_irq_reset(dev_priv);
4421 i8xx_irq_reset(dev_priv);
4423 if (INTEL_GEN(dev_priv) >= 11)
4424 gen11_irq_reset(dev_priv);
4425 else if (INTEL_GEN(dev_priv) >= 8)
4426 gen8_irq_reset(dev_priv);
4428 ilk_irq_reset(dev_priv);
4432 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4434 if (HAS_GMCH(dev_priv)) {
4435 if (IS_CHERRYVIEW(dev_priv))
4436 cherryview_irq_postinstall(dev_priv);
4437 else if (IS_VALLEYVIEW(dev_priv))
4438 valleyview_irq_postinstall(dev_priv);
4439 else if (IS_GEN(dev_priv, 4))
4440 i965_irq_postinstall(dev_priv);
4441 else if (IS_GEN(dev_priv, 3))
4442 i915_irq_postinstall(dev_priv);
4444 i8xx_irq_postinstall(dev_priv);
4446 if (INTEL_GEN(dev_priv) >= 11)
4447 gen11_irq_postinstall(dev_priv);
4448 else if (INTEL_GEN(dev_priv) >= 8)
4449 gen8_irq_postinstall(dev_priv);
4451 ilk_irq_postinstall(dev_priv);
4456 * intel_irq_install - enables the hardware interrupt
4457 * @dev_priv: i915 device instance
4459 * This function enables the hardware interrupt handling, but leaves the hotplug
4460 * handling still disabled. It is called after intel_irq_init().
4462 * In the driver load and resume code we need working interrupts in a few places
4463 * but don't want to deal with the hassle of concurrent probe and hotplug
4464 * workers. Hence the split into this two-stage approach.
4466 int intel_irq_install(struct drm_i915_private *dev_priv)
4468 int irq = to_pci_dev(dev_priv->drm.dev)->irq;
4472 * We enable some interrupt sources in our postinstall hooks, so mark
4473 * interrupts as enabled _before_ actually enabling them to avoid
4474 * special cases in our ordering checks.
4476 dev_priv->runtime_pm.irqs_enabled = true;
4478 dev_priv->drm.irq_enabled = true;
4480 intel_irq_reset(dev_priv);
4482 ret = request_irq(irq, intel_irq_handler(dev_priv),
4483 IRQF_SHARED, DRIVER_NAME, dev_priv);
4485 dev_priv->drm.irq_enabled = false;
4489 intel_irq_postinstall(dev_priv);
4495 * intel_irq_uninstall - finilizes all irq handling
4496 * @dev_priv: i915 device instance
4498 * This stops interrupt and hotplug handling and unregisters and frees all
4499 * resources acquired in the init functions.
4501 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4503 int irq = to_pci_dev(dev_priv->drm.dev)->irq;
4506 * FIXME we can get called twice during driver probe
4507 * error handling as well as during driver remove due to
4508 * intel_modeset_driver_remove() calling us out of sequence.
4509 * Would be nice if it didn't do that...
4511 if (!dev_priv->drm.irq_enabled)
4514 dev_priv->drm.irq_enabled = false;
4516 intel_irq_reset(dev_priv);
4518 free_irq(irq, dev_priv);
4520 intel_hpd_cancel_work(dev_priv);
4521 dev_priv->runtime_pm.irqs_enabled = false;
4525 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4526 * @dev_priv: i915 device instance
4528 * This function is used to disable interrupts at runtime, both in the runtime
4529 * pm and the system suspend/resume code.
4531 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4533 intel_irq_reset(dev_priv);
4534 dev_priv->runtime_pm.irqs_enabled = false;
4535 intel_synchronize_irq(dev_priv);
4539 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4540 * @dev_priv: i915 device instance
4542 * This function is used to enable interrupts at runtime, both in the runtime
4543 * pm and the system suspend/resume code.
4545 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4547 dev_priv->runtime_pm.irqs_enabled = true;
4548 intel_irq_reset(dev_priv);
4549 intel_irq_postinstall(dev_priv);
4552 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4555 * We only use drm_irq_uninstall() at unload and VT switch, so
4556 * this is the only thing we need to check.
4558 return dev_priv->runtime_pm.irqs_enabled;
4561 void intel_synchronize_irq(struct drm_i915_private *i915)
4563 synchronize_irq(to_pci_dev(i915->drm.dev)->irq);