drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #define MAX_NOPID ((u32)~0)
  38
  39 /**
  40  * Interrupts that are always left unmasked.
  41  *
  42  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  43  * we leave them always unmasked in IMR and then control enabling them through
  44  * PIPESTAT alone.
  45  */
  46 #define I915_INTERRUPT_ENABLE_FIX                       \
  47         (I915_ASLE_INTERRUPT |                          \
  48          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  49          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  51          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  52          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  53
  54 /** Interrupts that we mask and unmask at runtime. */
  55 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  56
  57 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  58                                  PIPE_VBLANK_INTERRUPT_STATUS)
  59
  60 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  61                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  62
  63 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  64                                          DRM_I915_VBLANK_PIPE_B)
  65
  66 void
  67 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  68 {
  69         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  70                 dev_priv->gt_irq_mask_reg &= ~mask;
  71                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  72                 (void) I915_READ(GTIMR);
  73         }
  74 }
  75
  76 static inline void
  77 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  78 {
  79         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  80                 dev_priv->gt_irq_mask_reg |= mask;
  81                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  82                 (void) I915_READ(GTIMR);
  83         }
  84 }
  85
  86 /* For display hotplug interrupt */
  87 void
  88 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  89 {
  90         if ((dev_priv->irq_mask_reg & mask) != 0) {
  91                 dev_priv->irq_mask_reg &= ~mask;
  92                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  93                 (void) I915_READ(DEIMR);
  94         }
  95 }
  96
  97 static inline void
  98 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  99 {
 100         if ((dev_priv->irq_mask_reg & mask) != mask) {
 101                 dev_priv->irq_mask_reg |= mask;
 102                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 103                 (void) I915_READ(DEIMR);
 104         }
 105 }
 106
 107 void
 108 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 109 {
 110         if ((dev_priv->irq_mask_reg & mask) != 0) {
 111                 dev_priv->irq_mask_reg &= ~mask;
 112                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 113                 (void) I915_READ(IMR);
 114         }
 115 }
 116
 117 static inline void
 118 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 119 {
 120         if ((dev_priv->irq_mask_reg & mask) != mask) {
 121                 dev_priv->irq_mask_reg |= mask;
 122                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 123                 (void) I915_READ(IMR);
 124         }
 125 }
 126
 127 static inline u32
 128 i915_pipestat(int pipe)
 129 {
 130         if (pipe == 0)
 131                 return PIPEASTAT;
 132         if (pipe == 1)
 133                 return PIPEBSTAT;
 134         BUG();
 135 }
 136
 137 void
 138 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 139 {
 140         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 141                 u32 reg = i915_pipestat(pipe);
 142
 143                 dev_priv->pipestat[pipe] |= mask;
 144                 /* Enable the interrupt, clear any pending status */
 145                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 146                 (void) I915_READ(reg);
 147         }
 148 }
 149
 150 void
 151 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 152 {
 153         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 154                 u32 reg = i915_pipestat(pipe);
 155
 156                 dev_priv->pipestat[pipe] &= ~mask;
 157                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 158                 (void) I915_READ(reg);
 159         }
 160 }
 161
 162 /**
 163  * intel_enable_asle - enable ASLE interrupt for OpRegion
 164  */
 165 void intel_enable_asle (struct drm_device *dev)
 166 {
 167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 168
 169         if (IS_IRONLAKE(dev))
 170                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 171         else
 172                 i915_enable_pipestat(dev_priv, 1,
 173                                      I915_LEGACY_BLC_EVENT_ENABLE);
 174 }
 175
 176 /**
 177  * i915_pipe_enabled - check if a pipe is enabled
 178  * @dev: DRM device
 179  * @pipe: pipe to check
 180  *
 181  * Reading certain registers when the pipe is disabled can hang the chip.
 182  * Use this routine to make sure the PLL is running and the pipe is active
 183  * before reading such registers if unsure.
 184  */
 185 static int
 186 i915_pipe_enabled(struct drm_device *dev, int pipe)
 187 {
 188         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 189         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 190
 191         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 192                 return 1;
 193
 194         return 0;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low, count;
 206
 207         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 208         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 212                                 "pipe %d\n", pipe);
 213                 return 0;
 214         }
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 223                          PIPE_FRAME_HIGH_SHIFT);
 224                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 225                         PIPE_FRAME_LOW_SHIFT);
 226                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 227                          PIPE_FRAME_HIGH_SHIFT);
 228         } while (high1 != high2);
 229
 230         count = (high1 << 8) | low;
 231
 232         return count;
 233 }
 234
 235 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 236 {
 237         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 238         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 239
 240         if (!i915_pipe_enabled(dev, pipe)) {
 241                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 242                                         "pipe %d\n", pipe);
 243                 return 0;
 244         }
 245
 246         return I915_READ(reg);
 247 }
 248
 249 /*
 250  * Handle hotplug events outside the interrupt handler proper.
 251  */
 252 static void i915_hotplug_work_func(struct work_struct *work)
 253 {
 254         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 255                                                     hotplug_work);
 256         struct drm_device *dev = dev_priv->dev;
 257         struct drm_mode_config *mode_config = &dev->mode_config;
 258         struct drm_connector *connector;
 259
 260         if (mode_config->num_connector) {
 261                 list_for_each_entry(connector, &mode_config->connector_list, head) {
 262                         struct intel_output *intel_output = to_intel_output(connector);
 263
 264                         if (intel_output->hot_plug)
 265                                 (*intel_output->hot_plug) (intel_output);
 266                 }
 267         }
 268         /* Just fire off a uevent and let userspace tell us what to do */
 269         drm_sysfs_hotplug_event(dev);
 270 }
 271
 272 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 273 {
 274         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 275         int ret = IRQ_NONE;
 276         u32 de_iir, gt_iir, de_ier, pch_iir;
 277         struct drm_i915_master_private *master_priv;
 278
 279         /* disable master interrupt before clearing iir  */
 280         de_ier = I915_READ(DEIER);
 281         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 282         (void)I915_READ(DEIER);
 283
 284         de_iir = I915_READ(DEIIR);
 285         gt_iir = I915_READ(GTIIR);
 286         pch_iir = I915_READ(SDEIIR);
 287
 288         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 289                 goto done;
 290
 291         ret = IRQ_HANDLED;
 292
 293         if (dev->primary->master) {
 294                 master_priv = dev->primary->master->driver_priv;
 295                 if (master_priv->sarea_priv)
 296                         master_priv->sarea_priv->last_dispatch =
 297                                 READ_BREADCRUMB(dev_priv);
 298         }
 299
 300         if (gt_iir & GT_USER_INTERRUPT) {
 301                 u32 seqno = i915_get_gem_seqno(dev);
 302                 dev_priv->mm.irq_gem_seqno = seqno;
 303                 trace_i915_gem_request_complete(dev, seqno);
 304                 DRM_WAKEUP(&dev_priv->irq_queue);
 305                 dev_priv->hangcheck_count = 0;
 306                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 307         }
 308
 309         if (de_iir & DE_GSE)
 310                 ironlake_opregion_gse_intr(dev);
 311
 312         /* check event from PCH */
 313         if ((de_iir & DE_PCH_EVENT) &&
 314             (pch_iir & SDE_HOTPLUG_MASK)) {
 315                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 316         }
 317
 318         /* should clear PCH hotplug event before clear CPU irq */
 319         I915_WRITE(SDEIIR, pch_iir);
 320         I915_WRITE(GTIIR, gt_iir);
 321         I915_WRITE(DEIIR, de_iir);
 322
 323 done:
 324         I915_WRITE(DEIER, de_ier);
 325         (void)I915_READ(DEIER);
 326
 327         return ret;
 328 }
 329
 330 /**
 331  * i915_error_work_func - do process context error handling work
 332  * @work: work struct
 333  *
 334  * Fire an error uevent so userspace can see that a hang or error
 335  * was detected.
 336  */
 337 static void i915_error_work_func(struct work_struct *work)
 338 {
 339         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 340                                                     error_work);
 341         struct drm_device *dev = dev_priv->dev;
 342         char *error_event[] = { "ERROR=1", NULL };
 343         char *reset_event[] = { "RESET=1", NULL };
 344         char *reset_done_event[] = { "ERROR=0", NULL };
 345
 346         DRM_DEBUG_DRIVER("generating error event\n");
 347         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 348
 349         if (atomic_read(&dev_priv->mm.wedged)) {
 350                 if (IS_I965G(dev)) {
 351                         DRM_DEBUG_DRIVER("resetting chip\n");
 352                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 353                         if (!i965_reset(dev, GDRST_RENDER)) {
 354                                 atomic_set(&dev_priv->mm.wedged, 0);
 355                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 356                         }
 357                 } else {
 358                         DRM_DEBUG_DRIVER("reboot required\n");
 359                 }
 360         }
 361 }
 362
 363 /**
 364  * i915_capture_error_state - capture an error record for later analysis
 365  * @dev: drm device
 366  *
 367  * Should be called when an error is detected (either a hang or an error
 368  * interrupt) to capture error state from the time of the error.  Fills
 369  * out a structure which becomes available in debugfs for user level tools
 370  * to pick up.
 371  */
 372 static void i915_capture_error_state(struct drm_device *dev)
 373 {
 374         struct drm_i915_private *dev_priv = dev->dev_private;
 375         struct drm_i915_error_state *error;
 376         unsigned long flags;
 377
 378         spin_lock_irqsave(&dev_priv->error_lock, flags);
 379         if (dev_priv->first_error)
 380                 goto out;
 381
 382         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 383         if (!error) {
 384                 DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n");
 385                 goto out;
 386         }
 387
 388         error->eir = I915_READ(EIR);
 389         error->pgtbl_er = I915_READ(PGTBL_ER);
 390         error->pipeastat = I915_READ(PIPEASTAT);
 391         error->pipebstat = I915_READ(PIPEBSTAT);
 392         error->instpm = I915_READ(INSTPM);
 393         if (!IS_I965G(dev)) {
 394                 error->ipeir = I915_READ(IPEIR);
 395                 error->ipehr = I915_READ(IPEHR);
 396                 error->instdone = I915_READ(INSTDONE);
 397                 error->acthd = I915_READ(ACTHD);
 398         } else {
 399                 error->ipeir = I915_READ(IPEIR_I965);
 400                 error->ipehr = I915_READ(IPEHR_I965);
 401                 error->instdone = I915_READ(INSTDONE_I965);
 402                 error->instps = I915_READ(INSTPS);
 403                 error->instdone1 = I915_READ(INSTDONE1);
 404                 error->acthd = I915_READ(ACTHD_I965);
 405         }
 406
 407         do_gettimeofday(&error->time);
 408
 409         dev_priv->first_error = error;
 410
 411 out:
 412         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 413 }
 414
 415 /**
 416  * i915_handle_error - handle an error interrupt
 417  * @dev: drm device
 418  *
 419  * Do some basic checking of regsiter state at error interrupt time and
 420  * dump it to the syslog.  Also call i915_capture_error_state() to make
 421  * sure we get a record and make it available in debugfs.  Fire a uevent
 422  * so userspace knows something bad happened (should trigger collection
 423  * of a ring dump etc.).
 424  */
 425 static void i915_handle_error(struct drm_device *dev, bool wedged)
 426 {
 427         struct drm_i915_private *dev_priv = dev->dev_private;
 428         u32 eir = I915_READ(EIR);
 429         u32 pipea_stats = I915_READ(PIPEASTAT);
 430         u32 pipeb_stats = I915_READ(PIPEBSTAT);
 431
 432         i915_capture_error_state(dev);
 433
 434         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 435                eir);
 436
 437         if (IS_G4X(dev)) {
 438                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 439                         u32 ipeir = I915_READ(IPEIR_I965);
 440
 441                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 442                                I915_READ(IPEIR_I965));
 443                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 444                                I915_READ(IPEHR_I965));
 445                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 446                                I915_READ(INSTDONE_I965));
 447                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 448                                I915_READ(INSTPS));
 449                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 450                                I915_READ(INSTDONE1));
 451                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 452                                I915_READ(ACTHD_I965));
 453                         I915_WRITE(IPEIR_I965, ipeir);
 454                         (void)I915_READ(IPEIR_I965);
 455                 }
 456                 if (eir & GM45_ERROR_PAGE_TABLE) {
 457                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 458                         printk(KERN_ERR "page table error\n");
 459                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 460                                pgtbl_err);
 461                         I915_WRITE(PGTBL_ER, pgtbl_err);
 462                         (void)I915_READ(PGTBL_ER);
 463                 }
 464         }
 465
 466         if (IS_I9XX(dev)) {
 467                 if (eir & I915_ERROR_PAGE_TABLE) {
 468                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 469                         printk(KERN_ERR "page table error\n");
 470                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 471                                pgtbl_err);
 472                         I915_WRITE(PGTBL_ER, pgtbl_err);
 473                         (void)I915_READ(PGTBL_ER);
 474                 }
 475         }
 476
 477         if (eir & I915_ERROR_MEMORY_REFRESH) {
 478                 printk(KERN_ERR "memory refresh error\n");
 479                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 480                        pipea_stats);
 481                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 482                        pipeb_stats);
 483                 /* pipestat has already been acked */
 484         }
 485         if (eir & I915_ERROR_INSTRUCTION) {
 486                 printk(KERN_ERR "instruction error\n");
 487                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 488                        I915_READ(INSTPM));
 489                 if (!IS_I965G(dev)) {
 490                         u32 ipeir = I915_READ(IPEIR);
 491
 492                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 493                                I915_READ(IPEIR));
 494                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 495                                I915_READ(IPEHR));
 496                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 497                                I915_READ(INSTDONE));
 498                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 499                                I915_READ(ACTHD));
 500                         I915_WRITE(IPEIR, ipeir);
 501                         (void)I915_READ(IPEIR);
 502                 } else {
 503                         u32 ipeir = I915_READ(IPEIR_I965);
 504
 505                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 506                                I915_READ(IPEIR_I965));
 507                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 508                                I915_READ(IPEHR_I965));
 509                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 510                                I915_READ(INSTDONE_I965));
 511                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 512                                I915_READ(INSTPS));
 513                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 514                                I915_READ(INSTDONE1));
 515                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 516                                I915_READ(ACTHD_I965));
 517                         I915_WRITE(IPEIR_I965, ipeir);
 518                         (void)I915_READ(IPEIR_I965);
 519                 }
 520         }
 521
 522         I915_WRITE(EIR, eir);
 523         (void)I915_READ(EIR);
 524         eir = I915_READ(EIR);
 525         if (eir) {
 526                 /*
 527                  * some errors might have become stuck,
 528                  * mask them.
 529                  */
 530                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 531                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 532                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 533         }
 534
 535         if (wedged) {
 536                 atomic_set(&dev_priv->mm.wedged, 1);
 537
 538                 /*
 539                  * Wakeup waiting processes so they don't hang
 540                  */
 541                 DRM_WAKEUP(&dev_priv->irq_queue);
 542         }
 543
 544         queue_work(dev_priv->wq, &dev_priv->error_work);
 545 }
 546
 547 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 548 {
 549         struct drm_device *dev = (struct drm_device *) arg;
 550         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 551         struct drm_i915_master_private *master_priv;
 552         u32 iir, new_iir;
 553         u32 pipea_stats, pipeb_stats;
 554         u32 vblank_status;
 555         u32 vblank_enable;
 556         int vblank = 0;
 557         unsigned long irqflags;
 558         int irq_received;
 559         int ret = IRQ_NONE;
 560
 561         atomic_inc(&dev_priv->irq_received);
 562
 563         if (IS_IRONLAKE(dev))
 564                 return ironlake_irq_handler(dev);
 565
 566         iir = I915_READ(IIR);
 567
 568         if (IS_I965G(dev)) {
 569                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 570                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 571         } else {
 572                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 573                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 574         }
 575
 576         for (;;) {
 577                 irq_received = iir != 0;
 578
 579                 /* Can't rely on pipestat interrupt bit in iir as it might
 580                  * have been cleared after the pipestat interrupt was received.
 581                  * It doesn't set the bit in iir again, but it still produces
 582                  * interrupts (for non-MSI).
 583                  */
 584                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 585                 pipea_stats = I915_READ(PIPEASTAT);
 586                 pipeb_stats = I915_READ(PIPEBSTAT);
 587
 588                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 589                         i915_handle_error(dev, false);
 590
 591                 /*
 592                  * Clear the PIPE(A|B)STAT regs before the IIR
 593                  */
 594                 if (pipea_stats & 0x8000ffff) {
 595                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 596                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 597                         I915_WRITE(PIPEASTAT, pipea_stats);
 598                         irq_received = 1;
 599                 }
 600
 601                 if (pipeb_stats & 0x8000ffff) {
 602                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 603                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 604                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 605                         irq_received = 1;
 606                 }
 607                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 608
 609                 if (!irq_received)
 610                         break;
 611
 612                 ret = IRQ_HANDLED;
 613
 614                 /* Consume port.  Then clear IIR or we'll miss events */
 615                 if ((I915_HAS_HOTPLUG(dev)) &&
 616                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 617                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 618
 619                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 620                                   hotplug_status);
 621                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 622                                 queue_work(dev_priv->wq,
 623                                            &dev_priv->hotplug_work);
 624
 625                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 626                         I915_READ(PORT_HOTPLUG_STAT);
 627                 }
 628
 629                 I915_WRITE(IIR, iir);
 630                 new_iir = I915_READ(IIR); /* Flush posted writes */
 631
 632                 if (dev->primary->master) {
 633                         master_priv = dev->primary->master->driver_priv;
 634                         if (master_priv->sarea_priv)
 635                                 master_priv->sarea_priv->last_dispatch =
 636                                         READ_BREADCRUMB(dev_priv);
 637                 }
 638
 639                 if (iir & I915_USER_INTERRUPT) {
 640                         u32 seqno = i915_get_gem_seqno(dev);
 641                         dev_priv->mm.irq_gem_seqno = seqno;
 642                         trace_i915_gem_request_complete(dev, seqno);
 643                         DRM_WAKEUP(&dev_priv->irq_queue);
 644                         dev_priv->hangcheck_count = 0;
 645                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 646                 }
 647
 648                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
 649                         intel_prepare_page_flip(dev, 0);
 650
 651                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 652                         intel_prepare_page_flip(dev, 1);
 653
 654                 if (pipea_stats & vblank_status) {
 655                         vblank++;
 656                         drm_handle_vblank(dev, 0);
 657                         intel_finish_page_flip(dev, 0);
 658                 }
 659
 660                 if (pipeb_stats & vblank_status) {
 661                         vblank++;
 662                         drm_handle_vblank(dev, 1);
 663                         intel_finish_page_flip(dev, 1);
 664                 }
 665
 666                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 667                     (iir & I915_ASLE_INTERRUPT))
 668                         opregion_asle_intr(dev);
 669
 670                 /* With MSI, interrupts are only generated when iir
 671                  * transitions from zero to nonzero.  If another bit got
 672                  * set while we were handling the existing iir bits, then
 673                  * we would never get another interrupt.
 674                  *
 675                  * This is fine on non-MSI as well, as if we hit this path
 676                  * we avoid exiting the interrupt handler only to generate
 677                  * another one.
 678                  *
 679                  * Note that for MSI this could cause a stray interrupt report
 680                  * if an interrupt landed in the time between writing IIR and
 681                  * the posting read.  This should be rare enough to never
 682                  * trigger the 99% of 100,000 interrupts test for disabling
 683                  * stray interrupts.
 684                  */
 685                 iir = new_iir;
 686         }
 687
 688         return ret;
 689 }
 690
 691 static int i915_emit_irq(struct drm_device * dev)
 692 {
 693         drm_i915_private_t *dev_priv = dev->dev_private;
 694         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 695         RING_LOCALS;
 696
 697         i915_kernel_lost_context(dev);
 698
 699         DRM_DEBUG_DRIVER("\n");
 700
 701         dev_priv->counter++;
 702         if (dev_priv->counter > 0x7FFFFFFFUL)
 703                 dev_priv->counter = 1;
 704         if (master_priv->sarea_priv)
 705                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 706
 707         BEGIN_LP_RING(4);
 708         OUT_RING(MI_STORE_DWORD_INDEX);
 709         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 710         OUT_RING(dev_priv->counter);
 711         OUT_RING(MI_USER_INTERRUPT);
 712         ADVANCE_LP_RING();
 713
 714         return dev_priv->counter;
 715 }
 716
 717 void i915_user_irq_get(struct drm_device *dev)
 718 {
 719         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 720         unsigned long irqflags;
 721
 722         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 723         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
 724                 if (IS_IRONLAKE(dev))
 725                         ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
 726                 else
 727                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 728         }
 729         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 730 }
 731
 732 void i915_user_irq_put(struct drm_device *dev)
 733 {
 734         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 735         unsigned long irqflags;
 736
 737         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 738         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 739         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
 740                 if (IS_IRONLAKE(dev))
 741                         ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
 742                 else
 743                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 744         }
 745         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 746 }
 747
 748 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
 749 {
 750         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 751
 752         if (dev_priv->trace_irq_seqno == 0)
 753                 i915_user_irq_get(dev);
 754
 755         dev_priv->trace_irq_seqno = seqno;
 756 }
 757
 758 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 759 {
 760         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 761         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 762         int ret = 0;
 763
 764         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 765                   READ_BREADCRUMB(dev_priv));
 766
 767         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 768                 if (master_priv->sarea_priv)
 769                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 770                 return 0;
 771         }
 772
 773         if (master_priv->sarea_priv)
 774                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 775
 776         i915_user_irq_get(dev);
 777         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 778                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 779         i915_user_irq_put(dev);
 780
 781         if (ret == -EBUSY) {
 782                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 783                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 784         }
 785
 786         return ret;
 787 }
 788
 789 /* Needs the lock as it touches the ring.
 790  */
 791 int i915_irq_emit(struct drm_device *dev, void *data,
 792                          struct drm_file *file_priv)
 793 {
 794         drm_i915_private_t *dev_priv = dev->dev_private;
 795         drm_i915_irq_emit_t *emit = data;
 796         int result;
 797
 798         if (!dev_priv || !dev_priv->ring.virtual_start) {
 799                 DRM_ERROR("called with no initialization\n");
 800                 return -EINVAL;
 801         }
 802
 803         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 804
 805         mutex_lock(&dev->struct_mutex);
 806         result = i915_emit_irq(dev);
 807         mutex_unlock(&dev->struct_mutex);
 808
 809         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 810                 DRM_ERROR("copy_to_user\n");
 811                 return -EFAULT;
 812         }
 813
 814         return 0;
 815 }
 816
 817 /* Doesn't need the hardware lock.
 818  */
 819 int i915_irq_wait(struct drm_device *dev, void *data,
 820                          struct drm_file *file_priv)
 821 {
 822         drm_i915_private_t *dev_priv = dev->dev_private;
 823         drm_i915_irq_wait_t *irqwait = data;
 824
 825         if (!dev_priv) {
 826                 DRM_ERROR("called with no initialization\n");
 827                 return -EINVAL;
 828         }
 829
 830         return i915_wait_irq(dev, irqwait->irq_seq);
 831 }
 832
 833 /* Called from drm generic code, passed 'crtc' which
 834  * we use as a pipe index
 835  */
 836 int i915_enable_vblank(struct drm_device *dev, int pipe)
 837 {
 838         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 839         unsigned long irqflags;
 840         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 841         u32 pipeconf;
 842
 843         pipeconf = I915_READ(pipeconf_reg);
 844         if (!(pipeconf & PIPEACONF_ENABLE))
 845                 return -EINVAL;
 846
 847         if (IS_IRONLAKE(dev))
 848                 return 0;
 849
 850         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 851         if (IS_I965G(dev))
 852                 i915_enable_pipestat(dev_priv, pipe,
 853                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 854         else
 855                 i915_enable_pipestat(dev_priv, pipe,
 856                                      PIPE_VBLANK_INTERRUPT_ENABLE);
 857         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 858         return 0;
 859 }
 860
 861 /* Called from drm generic code, passed 'crtc' which
 862  * we use as a pipe index
 863  */
 864 void i915_disable_vblank(struct drm_device *dev, int pipe)
 865 {
 866         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 867         unsigned long irqflags;
 868
 869         if (IS_IRONLAKE(dev))
 870                 return;
 871
 872         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 873         i915_disable_pipestat(dev_priv, pipe,
 874                               PIPE_VBLANK_INTERRUPT_ENABLE |
 875                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
 876         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 877 }
 878
 879 void i915_enable_interrupt (struct drm_device *dev)
 880 {
 881         struct drm_i915_private *dev_priv = dev->dev_private;
 882
 883         if (!IS_IRONLAKE(dev))
 884                 opregion_enable_asle(dev);
 885         dev_priv->irq_enabled = 1;
 886 }
 887
 888
 889 /* Set the vblank monitor pipe
 890  */
 891 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 892                          struct drm_file *file_priv)
 893 {
 894         drm_i915_private_t *dev_priv = dev->dev_private;
 895
 896         if (!dev_priv) {
 897                 DRM_ERROR("called with no initialization\n");
 898                 return -EINVAL;
 899         }
 900
 901         return 0;
 902 }
 903
 904 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 905                          struct drm_file *file_priv)
 906 {
 907         drm_i915_private_t *dev_priv = dev->dev_private;
 908         drm_i915_vblank_pipe_t *pipe = data;
 909
 910         if (!dev_priv) {
 911                 DRM_ERROR("called with no initialization\n");
 912                 return -EINVAL;
 913         }
 914
 915         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 916
 917         return 0;
 918 }
 919
 920 /**
 921  * Schedule buffer swap at given vertical blank.
 922  */
 923 int i915_vblank_swap(struct drm_device *dev, void *data,
 924                      struct drm_file *file_priv)
 925 {
 926         /* The delayed swap mechanism was fundamentally racy, and has been
 927          * removed.  The model was that the client requested a delayed flip/swap
 928          * from the kernel, then waited for vblank before continuing to perform
 929          * rendering.  The problem was that the kernel might wake the client
 930          * up before it dispatched the vblank swap (since the lock has to be
 931          * held while touching the ringbuffer), in which case the client would
 932          * clear and start the next frame before the swap occurred, and
 933          * flicker would occur in addition to likely missing the vblank.
 934          *
 935          * In the absence of this ioctl, userland falls back to a correct path
 936          * of waiting for a vblank, then dispatching the swap on its own.
 937          * Context switching to userland and back is plenty fast enough for
 938          * meeting the requirements of vblank swapping.
 939          */
 940         return -EINVAL;
 941 }
 942
 943 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
 944         drm_i915_private_t *dev_priv = dev->dev_private;
 945         return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
 946 }
 947
 948 /**
 949  * This is called when the chip hasn't reported back with completed
 950  * batchbuffers in a long time. The first time this is called we simply record
 951  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
 952  * again, we assume the chip is wedged and try to fix it.
 953  */
 954 void i915_hangcheck_elapsed(unsigned long data)
 955 {
 956         struct drm_device *dev = (struct drm_device *)data;
 957         drm_i915_private_t *dev_priv = dev->dev_private;
 958         uint32_t acthd;
 959
 960         if (!IS_I965G(dev))
 961                 acthd = I915_READ(ACTHD);
 962         else
 963                 acthd = I915_READ(ACTHD_I965);
 964
 965         /* If all work is done then ACTHD clearly hasn't advanced. */
 966         if (list_empty(&dev_priv->mm.request_list) ||
 967                        i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
 968                 dev_priv->hangcheck_count = 0;
 969                 return;
 970         }
 971
 972         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
 973                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
 974                 i915_handle_error(dev, true);
 975                 return;
 976         }
 977
 978         /* Reset timer case chip hangs without another request being added */
 979         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 980
 981         if (acthd != dev_priv->last_acthd)
 982                 dev_priv->hangcheck_count = 0;
 983         else
 984                 dev_priv->hangcheck_count++;
 985
 986         dev_priv->last_acthd = acthd;
 987 }
 988
 989 /* drm_dma.h hooks
 990 */
 991 static void ironlake_irq_preinstall(struct drm_device *dev)
 992 {
 993         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 994
 995         I915_WRITE(HWSTAM, 0xeffe);
 996
 997         /* XXX hotplug from PCH */
 998
 999         I915_WRITE(DEIMR, 0xffffffff);
1000         I915_WRITE(DEIER, 0x0);
1001         (void) I915_READ(DEIER);
1002
1003         /* and GT */
1004         I915_WRITE(GTIMR, 0xffffffff);
1005         I915_WRITE(GTIER, 0x0);
1006         (void) I915_READ(GTIER);
1007
1008         /* south display irq */
1009         I915_WRITE(SDEIMR, 0xffffffff);
1010         I915_WRITE(SDEIER, 0x0);
1011         (void) I915_READ(SDEIER);
1012 }
1013
1014 static int ironlake_irq_postinstall(struct drm_device *dev)
1015 {
1016         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1017         /* enable kind of interrupts always enabled */
1018         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT;
1019         u32 render_mask = GT_USER_INTERRUPT;
1020         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1021                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1022
1023         dev_priv->irq_mask_reg = ~display_mask;
1024         dev_priv->de_irq_enable_reg = display_mask;
1025
1026         /* should always can generate irq */
1027         I915_WRITE(DEIIR, I915_READ(DEIIR));
1028         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1029         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1030         (void) I915_READ(DEIER);
1031
1032         /* user interrupt should be enabled, but masked initial */
1033         dev_priv->gt_irq_mask_reg = 0xffffffff;
1034         dev_priv->gt_irq_enable_reg = render_mask;
1035
1036         I915_WRITE(GTIIR, I915_READ(GTIIR));
1037         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1038         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1039         (void) I915_READ(GTIER);
1040
1041         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1042         dev_priv->pch_irq_enable_reg = hotplug_mask;
1043
1044         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1045         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1046         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1047         (void) I915_READ(SDEIER);
1048
1049         return 0;
1050 }
1051
1052 void i915_driver_irq_preinstall(struct drm_device * dev)
1053 {
1054         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1055
1056         atomic_set(&dev_priv->irq_received, 0);
1057
1058         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1059         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1060
1061         if (IS_IRONLAKE(dev)) {
1062                 ironlake_irq_preinstall(dev);
1063                 return;
1064         }
1065
1066         if (I915_HAS_HOTPLUG(dev)) {
1067                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1068                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1069         }
1070
1071         I915_WRITE(HWSTAM, 0xeffe);
1072         I915_WRITE(PIPEASTAT, 0);
1073         I915_WRITE(PIPEBSTAT, 0);
1074         I915_WRITE(IMR, 0xffffffff);
1075         I915_WRITE(IER, 0x0);
1076         (void) I915_READ(IER);
1077 }
1078
1079 /*
1080  * Must be called after intel_modeset_init or hotplug interrupts won't be
1081  * enabled correctly.
1082  */
1083 int i915_driver_irq_postinstall(struct drm_device *dev)
1084 {
1085         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1086         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1087         u32 error_mask;
1088
1089         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1090
1091         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1092
1093         if (IS_IRONLAKE(dev))
1094                 return ironlake_irq_postinstall(dev);
1095
1096         /* Unmask the interrupts that we always want on. */
1097         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1098
1099         dev_priv->pipestat[0] = 0;
1100         dev_priv->pipestat[1] = 0;
1101
1102         if (I915_HAS_HOTPLUG(dev)) {
1103                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1104
1105                 /* Note HDMI and DP share bits */
1106                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1107                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1108                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1109                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1110                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1111                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1112                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1113                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1114                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1115                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1116                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1117                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1118                 /* Ignore TV since it's buggy */
1119
1120                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1121
1122                 /* Enable in IER... */
1123                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1124                 /* and unmask in IMR */
1125                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1126         }
1127
1128         /*
1129          * Enable some error detection, note the instruction error mask
1130          * bit is reserved, so we leave it masked.
1131          */
1132         if (IS_G4X(dev)) {
1133                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1134                                GM45_ERROR_MEM_PRIV |
1135                                GM45_ERROR_CP_PRIV |
1136                                I915_ERROR_MEMORY_REFRESH);
1137         } else {
1138                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1139                                I915_ERROR_MEMORY_REFRESH);
1140         }
1141         I915_WRITE(EMR, error_mask);
1142
1143         /* Disable pipe interrupt enables, clear pending pipe status */
1144         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1145         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1146         /* Clear pending interrupt status */
1147         I915_WRITE(IIR, I915_READ(IIR));
1148
1149         I915_WRITE(IER, enable_mask);
1150         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1151         (void) I915_READ(IER);
1152
1153         opregion_enable_asle(dev);
1154
1155         return 0;
1156 }
1157
1158 static void ironlake_irq_uninstall(struct drm_device *dev)
1159 {
1160         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1161         I915_WRITE(HWSTAM, 0xffffffff);
1162
1163         I915_WRITE(DEIMR, 0xffffffff);
1164         I915_WRITE(DEIER, 0x0);
1165         I915_WRITE(DEIIR, I915_READ(DEIIR));
1166
1167         I915_WRITE(GTIMR, 0xffffffff);
1168         I915_WRITE(GTIER, 0x0);
1169         I915_WRITE(GTIIR, I915_READ(GTIIR));
1170 }
1171
1172 void i915_driver_irq_uninstall(struct drm_device * dev)
1173 {
1174         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1175
1176         if (!dev_priv)
1177                 return;
1178
1179         dev_priv->vblank_pipe = 0;
1180
1181         if (IS_IRONLAKE(dev)) {
1182                 ironlake_irq_uninstall(dev);
1183                 return;
1184         }
1185
1186         if (I915_HAS_HOTPLUG(dev)) {
1187                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1188                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1189         }
1190
1191         I915_WRITE(HWSTAM, 0xffffffff);
1192         I915_WRITE(PIPEASTAT, 0);
1193         I915_WRITE(PIPEBSTAT, 0);
1194         I915_WRITE(IMR, 0xffffffff);
1195         I915_WRITE(IER, 0x0);
1196
1197         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1198         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1199         I915_WRITE(IIR, I915_READ(IIR));
1200 }