1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt[HPD_NUM_PINS] = {
77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
145 u32 val = I915_READ(reg);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg), val);
152 I915_WRITE(reg, 0xffffffff);
154 I915_WRITE(reg, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
174 /* For display hotplug interrupt */
176 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
182 assert_spin_locked(&dev_priv->irq_lock);
183 WARN_ON(bits & ~mask);
185 val = I915_READ(PORT_HOTPLUG_EN);
188 I915_WRITE(PORT_HOTPLUG_EN, val);
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
203 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
207 spin_lock_irq(&dev_priv->irq_lock);
208 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
209 spin_unlock_irq(&dev_priv->irq_lock);
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
218 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
219 uint32_t interrupt_mask,
220 uint32_t enabled_irq_mask)
224 assert_spin_locked(&dev_priv->irq_lock);
226 WARN_ON(enabled_irq_mask & ~interrupt_mask);
228 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
231 new_val = dev_priv->irq_mask;
232 new_val &= ~interrupt_mask;
233 new_val |= (~enabled_irq_mask & interrupt_mask);
235 if (new_val != dev_priv->irq_mask) {
236 dev_priv->irq_mask = new_val;
237 I915_WRITE(DEIMR, dev_priv->irq_mask);
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
248 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
249 uint32_t interrupt_mask,
250 uint32_t enabled_irq_mask)
252 assert_spin_locked(&dev_priv->irq_lock);
254 WARN_ON(enabled_irq_mask & ~interrupt_mask);
256 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
259 dev_priv->gt_irq_mask &= ~interrupt_mask;
260 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
261 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
264 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
266 ilk_update_gt_irq(dev_priv, mask, mask);
267 POSTING_READ_FW(GTIMR);
270 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
272 ilk_update_gt_irq(dev_priv, mask, 0);
275 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
277 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
280 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
282 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
285 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
287 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
296 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
297 uint32_t interrupt_mask,
298 uint32_t enabled_irq_mask)
302 WARN_ON(enabled_irq_mask & ~interrupt_mask);
304 assert_spin_locked(&dev_priv->irq_lock);
306 new_val = dev_priv->pm_irq_mask;
307 new_val &= ~interrupt_mask;
308 new_val |= (~enabled_irq_mask & interrupt_mask);
310 if (new_val != dev_priv->pm_irq_mask) {
311 dev_priv->pm_irq_mask = new_val;
312 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
313 POSTING_READ(gen6_pm_imr(dev_priv));
317 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
319 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
322 snb_update_pm_irq(dev_priv, mask, mask);
325 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
328 snb_update_pm_irq(dev_priv, mask, 0);
331 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
336 __gen6_disable_pm_irq(dev_priv, mask);
339 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
341 i915_reg_t reg = gen6_pm_iir(dev_priv);
343 spin_lock_irq(&dev_priv->irq_lock);
344 I915_WRITE(reg, dev_priv->pm_rps_events);
345 I915_WRITE(reg, dev_priv->pm_rps_events);
347 dev_priv->rps.pm_iir = 0;
348 spin_unlock_irq(&dev_priv->irq_lock);
351 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
353 spin_lock_irq(&dev_priv->irq_lock);
354 WARN_ON_ONCE(dev_priv->rps.pm_iir);
355 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
356 dev_priv->rps.interrupts_enabled = true;
357 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
358 dev_priv->pm_rps_events);
359 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
361 spin_unlock_irq(&dev_priv->irq_lock);
364 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
366 return (mask & ~dev_priv->rps.pm_intr_keep);
369 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
371 spin_lock_irq(&dev_priv->irq_lock);
372 dev_priv->rps.interrupts_enabled = false;
374 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
376 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
377 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
378 ~dev_priv->pm_rps_events);
380 spin_unlock_irq(&dev_priv->irq_lock);
381 synchronize_irq(dev_priv->drm.irq);
383 /* Now that we will not be generating any more work, flush any
384 * outsanding tasks. As we are called on the RPS idle path,
385 * we will reset the GPU to minimum frequencies, so the current
386 * state of the worker can be discarded.
388 cancel_work_sync(&dev_priv->rps.work);
389 gen6_reset_rps_interrupts(dev_priv);
393 * bdw_update_port_irq - update DE port interrupt
394 * @dev_priv: driver private
395 * @interrupt_mask: mask of interrupt bits to update
396 * @enabled_irq_mask: mask of interrupt bits to enable
398 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
399 uint32_t interrupt_mask,
400 uint32_t enabled_irq_mask)
405 assert_spin_locked(&dev_priv->irq_lock);
407 WARN_ON(enabled_irq_mask & ~interrupt_mask);
409 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
412 old_val = I915_READ(GEN8_DE_PORT_IMR);
415 new_val &= ~interrupt_mask;
416 new_val |= (~enabled_irq_mask & interrupt_mask);
418 if (new_val != old_val) {
419 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
420 POSTING_READ(GEN8_DE_PORT_IMR);
425 * bdw_update_pipe_irq - update DE pipe interrupt
426 * @dev_priv: driver private
427 * @pipe: pipe whose interrupt to update
428 * @interrupt_mask: mask of interrupt bits to update
429 * @enabled_irq_mask: mask of interrupt bits to enable
431 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
433 uint32_t interrupt_mask,
434 uint32_t enabled_irq_mask)
438 assert_spin_locked(&dev_priv->irq_lock);
440 WARN_ON(enabled_irq_mask & ~interrupt_mask);
442 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
445 new_val = dev_priv->de_irq_mask[pipe];
446 new_val &= ~interrupt_mask;
447 new_val |= (~enabled_irq_mask & interrupt_mask);
449 if (new_val != dev_priv->de_irq_mask[pipe]) {
450 dev_priv->de_irq_mask[pipe] = new_val;
451 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
452 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
457 * ibx_display_interrupt_update - update SDEIMR
458 * @dev_priv: driver private
459 * @interrupt_mask: mask of interrupt bits to update
460 * @enabled_irq_mask: mask of interrupt bits to enable
462 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
463 uint32_t interrupt_mask,
464 uint32_t enabled_irq_mask)
466 uint32_t sdeimr = I915_READ(SDEIMR);
467 sdeimr &= ~interrupt_mask;
468 sdeimr |= (~enabled_irq_mask & interrupt_mask);
470 WARN_ON(enabled_irq_mask & ~interrupt_mask);
472 assert_spin_locked(&dev_priv->irq_lock);
474 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
477 I915_WRITE(SDEIMR, sdeimr);
478 POSTING_READ(SDEIMR);
482 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
483 u32 enable_mask, u32 status_mask)
485 i915_reg_t reg = PIPESTAT(pipe);
486 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
488 assert_spin_locked(&dev_priv->irq_lock);
489 WARN_ON(!intel_irqs_enabled(dev_priv));
491 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
492 status_mask & ~PIPESTAT_INT_STATUS_MASK,
493 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
494 pipe_name(pipe), enable_mask, status_mask))
497 if ((pipestat & enable_mask) == enable_mask)
500 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
502 /* Enable the interrupt, clear any pending status */
503 pipestat |= enable_mask | status_mask;
504 I915_WRITE(reg, pipestat);
509 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
510 u32 enable_mask, u32 status_mask)
512 i915_reg_t reg = PIPESTAT(pipe);
513 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
515 assert_spin_locked(&dev_priv->irq_lock);
516 WARN_ON(!intel_irqs_enabled(dev_priv));
518 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
519 status_mask & ~PIPESTAT_INT_STATUS_MASK,
520 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
521 pipe_name(pipe), enable_mask, status_mask))
524 if ((pipestat & enable_mask) == 0)
527 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
529 pipestat &= ~enable_mask;
530 I915_WRITE(reg, pipestat);
534 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
536 u32 enable_mask = status_mask << 16;
539 * On pipe A we don't support the PSR interrupt yet,
540 * on pipe B and C the same bit MBZ.
542 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
545 * On pipe B and C we don't support the PSR interrupt yet, on pipe
546 * A the same bit is for perf counters which we don't use either.
548 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
551 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
552 SPRITE0_FLIP_DONE_INT_EN_VLV |
553 SPRITE1_FLIP_DONE_INT_EN_VLV);
554 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
555 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
556 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
557 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
563 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
568 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
569 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
572 enable_mask = status_mask << 16;
573 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
577 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
582 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
583 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
586 enable_mask = status_mask << 16;
587 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
591 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
592 * @dev_priv: i915 device private
594 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
596 if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
599 spin_lock_irq(&dev_priv->irq_lock);
601 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
602 if (INTEL_GEN(dev_priv) >= 4)
603 i915_enable_pipestat(dev_priv, PIPE_A,
604 PIPE_LEGACY_BLC_EVENT_STATUS);
606 spin_unlock_irq(&dev_priv->irq_lock);
610 * This timing diagram depicts the video signal in and
611 * around the vertical blanking period.
613 * Assumptions about the fictitious mode used in this example:
615 * vsync_start = vblank_start + 1
616 * vsync_end = vblank_start + 2
617 * vtotal = vblank_start + 3
620 * latch double buffered registers
621 * increment frame counter (ctg+)
622 * generate start of vblank interrupt (gen4+)
625 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
626 * | may be shifted forward 1-3 extra lines via PIPECONF
628 * | | start of vsync:
629 * | | generate vsync interrupt
631 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
632 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
633 * ----va---> <-----------------vb--------------------> <--------va-------------
634 * | | <----vs-----> |
635 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
636 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
637 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
639 * last visible pixel first visible pixel
640 * | increment frame counter (gen3/4)
641 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
643 * x = horizontal active
644 * _ = horizontal blanking
645 * hs = horizontal sync
646 * va = vertical active
647 * vb = vertical blanking
649 * vbs = vblank_start (number)
652 * - most events happen at the start of horizontal sync
653 * - frame start happens at the start of horizontal blank, 1-4 lines
654 * (depending on PIPECONF settings) after the start of vblank
655 * - gen3/4 pixel and frame counter are synchronized with the start
656 * of horizontal active on the first line of vertical active
659 /* Called from drm generic code, passed a 'crtc', which
660 * we use as a pipe index
662 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
664 struct drm_i915_private *dev_priv = to_i915(dev);
665 i915_reg_t high_frame, low_frame;
666 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
667 struct intel_crtc *intel_crtc =
668 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
669 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
671 htotal = mode->crtc_htotal;
672 hsync_start = mode->crtc_hsync_start;
673 vbl_start = mode->crtc_vblank_start;
674 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
675 vbl_start = DIV_ROUND_UP(vbl_start, 2);
677 /* Convert to pixel count */
680 /* Start of vblank event occurs at start of hsync */
681 vbl_start -= htotal - hsync_start;
683 high_frame = PIPEFRAME(pipe);
684 low_frame = PIPEFRAMEPIXEL(pipe);
687 * High & low register fields aren't synchronized, so make sure
688 * we get a low value that's stable across two reads of the high
692 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
693 low = I915_READ(low_frame);
694 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
695 } while (high1 != high2);
697 high1 >>= PIPE_FRAME_HIGH_SHIFT;
698 pixel = low & PIPE_PIXEL_MASK;
699 low >>= PIPE_FRAME_LOW_SHIFT;
702 * The frame counter increments at beginning of active.
703 * Cook up a vblank counter by also checking the pixel
704 * counter against vblank start.
706 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
709 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
711 struct drm_i915_private *dev_priv = to_i915(dev);
713 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
716 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
717 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
719 struct drm_device *dev = crtc->base.dev;
720 struct drm_i915_private *dev_priv = to_i915(dev);
721 const struct drm_display_mode *mode = &crtc->base.hwmode;
722 enum pipe pipe = crtc->pipe;
723 int position, vtotal;
725 vtotal = mode->crtc_vtotal;
726 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
729 if (IS_GEN2(dev_priv))
730 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
732 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
735 * On HSW, the DSL reg (0x70000) appears to return 0 if we
736 * read it just before the start of vblank. So try it again
737 * so we don't accidentally end up spanning a vblank frame
738 * increment, causing the pipe_update_end() code to squak at us.
740 * The nature of this problem means we can't simply check the ISR
741 * bit and return the vblank start value; nor can we use the scanline
742 * debug register in the transcoder as it appears to have the same
743 * problem. We may need to extend this to include other platforms,
744 * but so far testing only shows the problem on HSW.
746 if (HAS_DDI(dev_priv) && !position) {
749 for (i = 0; i < 100; i++) {
751 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
753 if (temp != position) {
761 * See update_scanline_offset() for the details on the
762 * scanline_offset adjustment.
764 return (position + crtc->scanline_offset) % vtotal;
767 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
768 unsigned int flags, int *vpos, int *hpos,
769 ktime_t *stime, ktime_t *etime,
770 const struct drm_display_mode *mode)
772 struct drm_i915_private *dev_priv = to_i915(dev);
773 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
776 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
779 unsigned long irqflags;
781 if (WARN_ON(!mode->crtc_clock)) {
782 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
783 "pipe %c\n", pipe_name(pipe));
787 htotal = mode->crtc_htotal;
788 hsync_start = mode->crtc_hsync_start;
789 vtotal = mode->crtc_vtotal;
790 vbl_start = mode->crtc_vblank_start;
791 vbl_end = mode->crtc_vblank_end;
793 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
794 vbl_start = DIV_ROUND_UP(vbl_start, 2);
799 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
802 * Lock uncore.lock, as we will do multiple timing critical raw
803 * register reads, potentially with preemption disabled, so the
804 * following code must not block on uncore.lock.
806 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
808 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
810 /* Get optional system timestamp before query. */
812 *stime = ktime_get();
814 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
815 /* No obvious pixelcount register. Only query vertical
816 * scanout position from Display scan line register.
818 position = __intel_get_crtc_scanline(intel_crtc);
820 /* Have access to pixelcount since start of frame.
821 * We can split this into vertical and horizontal
824 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
826 /* convert to pixel counts */
832 * In interlaced modes, the pixel counter counts all pixels,
833 * so one field will have htotal more pixels. In order to avoid
834 * the reported position from jumping backwards when the pixel
835 * counter is beyond the length of the shorter field, just
836 * clamp the position the length of the shorter field. This
837 * matches how the scanline counter based position works since
838 * the scanline counter doesn't count the two half lines.
840 if (position >= vtotal)
841 position = vtotal - 1;
844 * Start of vblank interrupt is triggered at start of hsync,
845 * just prior to the first active line of vblank. However we
846 * consider lines to start at the leading edge of horizontal
847 * active. So, should we get here before we've crossed into
848 * the horizontal active of the first line in vblank, we would
849 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
850 * always add htotal-hsync_start to the current pixel position.
852 position = (position + htotal - hsync_start) % vtotal;
855 /* Get optional system timestamp after query. */
857 *etime = ktime_get();
859 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
861 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
863 in_vbl = position >= vbl_start && position < vbl_end;
866 * While in vblank, position will be negative
867 * counting up towards 0 at vbl_end. And outside
868 * vblank, position will be positive counting
871 if (position >= vbl_start)
874 position += vtotal - vbl_end;
876 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
880 *vpos = position / htotal;
881 *hpos = position - (*vpos * htotal);
886 ret |= DRM_SCANOUTPOS_IN_VBLANK;
891 int intel_get_crtc_scanline(struct intel_crtc *crtc)
893 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
894 unsigned long irqflags;
897 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
898 position = __intel_get_crtc_scanline(crtc);
899 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
904 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
906 struct timeval *vblank_time,
909 struct drm_crtc *crtc;
911 if (pipe >= INTEL_INFO(dev)->num_pipes) {
912 DRM_ERROR("Invalid crtc %u\n", pipe);
916 /* Get drm_crtc to timestamp: */
917 crtc = intel_get_crtc_for_pipe(dev, pipe);
919 DRM_ERROR("Invalid crtc %u\n", pipe);
923 if (!crtc->hwmode.crtc_clock) {
924 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
928 /* Helper routine in DRM core does all the work: */
929 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
934 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
936 u32 busy_up, busy_down, max_avg, min_avg;
939 spin_lock(&mchdev_lock);
941 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
943 new_delay = dev_priv->ips.cur_delay;
945 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
946 busy_up = I915_READ(RCPREVBSYTUPAVG);
947 busy_down = I915_READ(RCPREVBSYTDNAVG);
948 max_avg = I915_READ(RCBMAXAVG);
949 min_avg = I915_READ(RCBMINAVG);
951 /* Handle RCS change request from hw */
952 if (busy_up > max_avg) {
953 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
954 new_delay = dev_priv->ips.cur_delay - 1;
955 if (new_delay < dev_priv->ips.max_delay)
956 new_delay = dev_priv->ips.max_delay;
957 } else if (busy_down < min_avg) {
958 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
959 new_delay = dev_priv->ips.cur_delay + 1;
960 if (new_delay > dev_priv->ips.min_delay)
961 new_delay = dev_priv->ips.min_delay;
964 if (ironlake_set_drps(dev_priv, new_delay))
965 dev_priv->ips.cur_delay = new_delay;
967 spin_unlock(&mchdev_lock);
972 static void notify_ring(struct intel_engine_cs *engine)
974 smp_store_mb(engine->breadcrumbs.irq_posted, true);
975 if (intel_engine_wakeup(engine))
976 trace_i915_gem_request_notify(engine);
979 static void vlv_c0_read(struct drm_i915_private *dev_priv,
980 struct intel_rps_ei *ei)
982 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
983 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
984 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
987 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
988 const struct intel_rps_ei *old,
989 const struct intel_rps_ei *now,
993 unsigned int mul = 100;
995 if (old->cz_clock == 0)
998 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1001 time = now->cz_clock - old->cz_clock;
1002 time *= threshold * dev_priv->czclk_freq;
1004 /* Workload can be split between render + media, e.g. SwapBuffers
1005 * being blitted in X after being rendered in mesa. To account for
1006 * this we need to combine both engines into our activity counter.
1008 c0 = now->render_c0 - old->render_c0;
1009 c0 += now->media_c0 - old->media_c0;
1010 c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1015 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1017 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1018 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1021 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1023 struct intel_rps_ei now;
1026 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1029 vlv_c0_read(dev_priv, &now);
1030 if (now.cz_clock == 0)
1033 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1034 if (!vlv_c0_above(dev_priv,
1035 &dev_priv->rps.down_ei, &now,
1036 dev_priv->rps.down_threshold))
1037 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1038 dev_priv->rps.down_ei = now;
1041 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1042 if (vlv_c0_above(dev_priv,
1043 &dev_priv->rps.up_ei, &now,
1044 dev_priv->rps.up_threshold))
1045 events |= GEN6_PM_RP_UP_THRESHOLD;
1046 dev_priv->rps.up_ei = now;
1052 static bool any_waiters(struct drm_i915_private *dev_priv)
1054 struct intel_engine_cs *engine;
1056 for_each_engine(engine, dev_priv)
1057 if (intel_engine_has_waiter(engine))
1063 static void gen6_pm_rps_work(struct work_struct *work)
1065 struct drm_i915_private *dev_priv =
1066 container_of(work, struct drm_i915_private, rps.work);
1068 int new_delay, adj, min, max;
1071 spin_lock_irq(&dev_priv->irq_lock);
1072 /* Speed up work cancelation during disabling rps interrupts. */
1073 if (!dev_priv->rps.interrupts_enabled) {
1074 spin_unlock_irq(&dev_priv->irq_lock);
1078 pm_iir = dev_priv->rps.pm_iir;
1079 dev_priv->rps.pm_iir = 0;
1080 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1081 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1082 client_boost = dev_priv->rps.client_boost;
1083 dev_priv->rps.client_boost = false;
1084 spin_unlock_irq(&dev_priv->irq_lock);
1086 /* Make sure we didn't queue anything we're not going to process. */
1087 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1089 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1092 mutex_lock(&dev_priv->rps.hw_lock);
1094 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1096 adj = dev_priv->rps.last_adj;
1097 new_delay = dev_priv->rps.cur_freq;
1098 min = dev_priv->rps.min_freq_softlimit;
1099 max = dev_priv->rps.max_freq_softlimit;
1100 if (client_boost || any_waiters(dev_priv))
1101 max = dev_priv->rps.max_freq;
1102 if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1103 new_delay = dev_priv->rps.boost_freq;
1105 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1108 else /* CHV needs even encode values */
1109 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1111 * For better performance, jump directly
1112 * to RPe if we're below it.
1114 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1115 new_delay = dev_priv->rps.efficient_freq;
1118 } else if (client_boost || any_waiters(dev_priv)) {
1120 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1121 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1122 new_delay = dev_priv->rps.efficient_freq;
1124 new_delay = dev_priv->rps.min_freq_softlimit;
1126 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1129 else /* CHV needs even encode values */
1130 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1131 } else { /* unknown event */
1135 dev_priv->rps.last_adj = adj;
1137 /* sysfs frequency interfaces may have snuck in while servicing the
1141 new_delay = clamp_t(int, new_delay, min, max);
1143 intel_set_rps(dev_priv, new_delay);
1145 mutex_unlock(&dev_priv->rps.hw_lock);
1150 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1152 * @work: workqueue struct
1154 * Doesn't actually do anything except notify userspace. As a consequence of
1155 * this event, userspace should try to remap the bad rows since statistically
1156 * it is likely the same row is more likely to go bad again.
1158 static void ivybridge_parity_work(struct work_struct *work)
1160 struct drm_i915_private *dev_priv =
1161 container_of(work, struct drm_i915_private, l3_parity.error_work);
1162 u32 error_status, row, bank, subbank;
1163 char *parity_event[6];
1167 /* We must turn off DOP level clock gating to access the L3 registers.
1168 * In order to prevent a get/put style interface, acquire struct mutex
1169 * any time we access those registers.
1171 mutex_lock(&dev_priv->drm.struct_mutex);
1173 /* If we've screwed up tracking, just let the interrupt fire again */
1174 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1177 misccpctl = I915_READ(GEN7_MISCCPCTL);
1178 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1179 POSTING_READ(GEN7_MISCCPCTL);
1181 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1185 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1188 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1190 reg = GEN7_L3CDERRST1(slice);
1192 error_status = I915_READ(reg);
1193 row = GEN7_PARITY_ERROR_ROW(error_status);
1194 bank = GEN7_PARITY_ERROR_BANK(error_status);
1195 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1197 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1200 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1201 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1202 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1203 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1204 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1205 parity_event[5] = NULL;
1207 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1208 KOBJ_CHANGE, parity_event);
1210 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1211 slice, row, bank, subbank);
1213 kfree(parity_event[4]);
1214 kfree(parity_event[3]);
1215 kfree(parity_event[2]);
1216 kfree(parity_event[1]);
1219 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1222 WARN_ON(dev_priv->l3_parity.which_slice);
1223 spin_lock_irq(&dev_priv->irq_lock);
1224 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1225 spin_unlock_irq(&dev_priv->irq_lock);
1227 mutex_unlock(&dev_priv->drm.struct_mutex);
1230 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1233 if (!HAS_L3_DPF(dev_priv))
1236 spin_lock(&dev_priv->irq_lock);
1237 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1238 spin_unlock(&dev_priv->irq_lock);
1240 iir &= GT_PARITY_ERROR(dev_priv);
1241 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1242 dev_priv->l3_parity.which_slice |= 1 << 1;
1244 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1245 dev_priv->l3_parity.which_slice |= 1 << 0;
1247 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1250 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1253 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1254 notify_ring(&dev_priv->engine[RCS]);
1255 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1256 notify_ring(&dev_priv->engine[VCS]);
1259 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1262 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1263 notify_ring(&dev_priv->engine[RCS]);
1264 if (gt_iir & GT_BSD_USER_INTERRUPT)
1265 notify_ring(&dev_priv->engine[VCS]);
1266 if (gt_iir & GT_BLT_USER_INTERRUPT)
1267 notify_ring(&dev_priv->engine[BCS]);
1269 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1270 GT_BSD_CS_ERROR_INTERRUPT |
1271 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1272 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1274 if (gt_iir & GT_PARITY_ERROR(dev_priv))
1275 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1278 static __always_inline void
1279 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1281 if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1282 notify_ring(engine);
1283 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1284 tasklet_schedule(&engine->irq_tasklet);
1287 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1291 irqreturn_t ret = IRQ_NONE;
1293 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1294 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1296 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1299 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1302 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1303 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1305 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1308 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1311 if (master_ctl & GEN8_GT_VECS_IRQ) {
1312 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1314 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1317 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1320 if (master_ctl & GEN8_GT_PM_IRQ) {
1321 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1322 if (gt_iir[2] & dev_priv->pm_rps_events) {
1323 I915_WRITE_FW(GEN8_GT_IIR(2),
1324 gt_iir[2] & dev_priv->pm_rps_events);
1327 DRM_ERROR("The master control interrupt lied (PM)!\n");
1333 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1337 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1338 gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1339 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1340 gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1344 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1345 gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1346 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1347 gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1351 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1352 gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1354 if (gt_iir[2] & dev_priv->pm_rps_events)
1355 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1358 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1362 return val & PORTA_HOTPLUG_LONG_DETECT;
1364 return val & PORTB_HOTPLUG_LONG_DETECT;
1366 return val & PORTC_HOTPLUG_LONG_DETECT;
1372 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1376 return val & PORTE_HOTPLUG_LONG_DETECT;
1382 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1386 return val & PORTA_HOTPLUG_LONG_DETECT;
1388 return val & PORTB_HOTPLUG_LONG_DETECT;
1390 return val & PORTC_HOTPLUG_LONG_DETECT;
1392 return val & PORTD_HOTPLUG_LONG_DETECT;
1398 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1402 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1408 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1412 return val & PORTB_HOTPLUG_LONG_DETECT;
1414 return val & PORTC_HOTPLUG_LONG_DETECT;
1416 return val & PORTD_HOTPLUG_LONG_DETECT;
1422 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1426 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1428 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1430 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1437 * Get a bit mask of pins that have triggered, and which ones may be long.
1438 * This can be called multiple times with the same masks to accumulate
1439 * hotplug detection results from several registers.
1441 * Note that the caller is expected to zero out the masks initially.
1443 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1444 u32 hotplug_trigger, u32 dig_hotplug_reg,
1445 const u32 hpd[HPD_NUM_PINS],
1446 bool long_pulse_detect(enum port port, u32 val))
1451 for_each_hpd_pin(i) {
1452 if ((hpd[i] & hotplug_trigger) == 0)
1455 *pin_mask |= BIT(i);
1457 if (!intel_hpd_pin_to_port(i, &port))
1460 if (long_pulse_detect(port, dig_hotplug_reg))
1461 *long_mask |= BIT(i);
1464 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1465 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1469 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1471 wake_up_all(&dev_priv->gmbus_wait_queue);
1474 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1476 wake_up_all(&dev_priv->gmbus_wait_queue);
1479 #if defined(CONFIG_DEBUG_FS)
1480 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1482 uint32_t crc0, uint32_t crc1,
1483 uint32_t crc2, uint32_t crc3,
1486 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1487 struct intel_pipe_crc_entry *entry;
1490 spin_lock(&pipe_crc->lock);
1492 if (!pipe_crc->entries) {
1493 spin_unlock(&pipe_crc->lock);
1494 DRM_DEBUG_KMS("spurious interrupt\n");
1498 head = pipe_crc->head;
1499 tail = pipe_crc->tail;
1501 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1502 spin_unlock(&pipe_crc->lock);
1503 DRM_ERROR("CRC buffer overflowing\n");
1507 entry = &pipe_crc->entries[head];
1509 entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm,
1511 entry->crc[0] = crc0;
1512 entry->crc[1] = crc1;
1513 entry->crc[2] = crc2;
1514 entry->crc[3] = crc3;
1515 entry->crc[4] = crc4;
1517 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1518 pipe_crc->head = head;
1520 spin_unlock(&pipe_crc->lock);
1522 wake_up_interruptible(&pipe_crc->wq);
1526 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1528 uint32_t crc0, uint32_t crc1,
1529 uint32_t crc2, uint32_t crc3,
1534 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1537 display_pipe_crc_irq_handler(dev_priv, pipe,
1538 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1542 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1545 display_pipe_crc_irq_handler(dev_priv, pipe,
1546 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1547 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1548 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1549 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1550 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1553 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1556 uint32_t res1, res2;
1558 if (INTEL_GEN(dev_priv) >= 3)
1559 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1563 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1564 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1568 display_pipe_crc_irq_handler(dev_priv, pipe,
1569 I915_READ(PIPE_CRC_RES_RED(pipe)),
1570 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1571 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1575 /* The RPS events need forcewake, so we add them to a work queue and mask their
1576 * IMR bits until the work is done. Other interrupts can be processed without
1577 * the work queue. */
1578 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1580 if (pm_iir & dev_priv->pm_rps_events) {
1581 spin_lock(&dev_priv->irq_lock);
1582 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1583 if (dev_priv->rps.interrupts_enabled) {
1584 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1585 schedule_work(&dev_priv->rps.work);
1587 spin_unlock(&dev_priv->irq_lock);
1590 if (INTEL_INFO(dev_priv)->gen >= 8)
1593 if (HAS_VEBOX(dev_priv)) {
1594 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1595 notify_ring(&dev_priv->engine[VECS]);
1597 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1598 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1602 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1607 ret = drm_handle_vblank(&dev_priv->drm, pipe);
1609 intel_finish_page_flip_mmio(dev_priv, pipe);
1614 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1615 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1619 spin_lock(&dev_priv->irq_lock);
1621 if (!dev_priv->display_irqs_enabled) {
1622 spin_unlock(&dev_priv->irq_lock);
1626 for_each_pipe(dev_priv, pipe) {
1628 u32 mask, iir_bit = 0;
1631 * PIPESTAT bits get signalled even when the interrupt is
1632 * disabled with the mask bits, and some of the status bits do
1633 * not generate interrupts at all (like the underrun bit). Hence
1634 * we need to be careful that we only handle what we want to
1638 /* fifo underruns are filterered in the underrun handler. */
1639 mask = PIPE_FIFO_UNDERRUN_STATUS;
1643 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1646 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1649 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1653 mask |= dev_priv->pipestat_irq_mask[pipe];
1658 reg = PIPESTAT(pipe);
1659 mask |= PIPESTAT_INT_ENABLE_MASK;
1660 pipe_stats[pipe] = I915_READ(reg) & mask;
1663 * Clear the PIPE*STAT regs before the IIR
1665 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1666 PIPESTAT_INT_STATUS_MASK))
1667 I915_WRITE(reg, pipe_stats[pipe]);
1669 spin_unlock(&dev_priv->irq_lock);
1672 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1673 u32 pipe_stats[I915_MAX_PIPES])
1677 for_each_pipe(dev_priv, pipe) {
1678 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1679 intel_pipe_handle_vblank(dev_priv, pipe))
1680 intel_check_page_flip(dev_priv, pipe);
1682 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1683 intel_finish_page_flip_cs(dev_priv, pipe);
1685 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1686 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1688 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1689 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1692 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1693 gmbus_irq_handler(dev_priv);
1696 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1698 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1701 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1703 return hotplug_status;
1706 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1709 u32 pin_mask = 0, long_mask = 0;
1711 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1712 IS_CHERRYVIEW(dev_priv)) {
1713 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1715 if (hotplug_trigger) {
1716 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1717 hotplug_trigger, hpd_status_g4x,
1718 i9xx_port_hotplug_long_detect);
1720 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1723 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1724 dp_aux_irq_handler(dev_priv);
1726 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1728 if (hotplug_trigger) {
1729 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1730 hotplug_trigger, hpd_status_i915,
1731 i9xx_port_hotplug_long_detect);
1732 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1737 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1739 struct drm_device *dev = arg;
1740 struct drm_i915_private *dev_priv = to_i915(dev);
1741 irqreturn_t ret = IRQ_NONE;
1743 if (!intel_irqs_enabled(dev_priv))
1746 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1747 disable_rpm_wakeref_asserts(dev_priv);
1750 u32 iir, gt_iir, pm_iir;
1751 u32 pipe_stats[I915_MAX_PIPES] = {};
1752 u32 hotplug_status = 0;
1755 gt_iir = I915_READ(GTIIR);
1756 pm_iir = I915_READ(GEN6_PMIIR);
1757 iir = I915_READ(VLV_IIR);
1759 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1765 * Theory on interrupt generation, based on empirical evidence:
1767 * x = ((VLV_IIR & VLV_IER) ||
1768 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1769 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1771 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1772 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1773 * guarantee the CPU interrupt will be raised again even if we
1774 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1775 * bits this time around.
1777 I915_WRITE(VLV_MASTER_IER, 0);
1778 ier = I915_READ(VLV_IER);
1779 I915_WRITE(VLV_IER, 0);
1782 I915_WRITE(GTIIR, gt_iir);
1784 I915_WRITE(GEN6_PMIIR, pm_iir);
1786 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1787 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1789 /* Call regardless, as some status bits might not be
1790 * signalled in iir */
1791 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1794 * VLV_IIR is single buffered, and reflects the level
1795 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1798 I915_WRITE(VLV_IIR, iir);
1800 I915_WRITE(VLV_IER, ier);
1801 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1802 POSTING_READ(VLV_MASTER_IER);
1805 snb_gt_irq_handler(dev_priv, gt_iir);
1807 gen6_rps_irq_handler(dev_priv, pm_iir);
1810 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1812 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1815 enable_rpm_wakeref_asserts(dev_priv);
1820 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1822 struct drm_device *dev = arg;
1823 struct drm_i915_private *dev_priv = to_i915(dev);
1824 irqreturn_t ret = IRQ_NONE;
1826 if (!intel_irqs_enabled(dev_priv))
1829 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1830 disable_rpm_wakeref_asserts(dev_priv);
1833 u32 master_ctl, iir;
1835 u32 pipe_stats[I915_MAX_PIPES] = {};
1836 u32 hotplug_status = 0;
1839 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1840 iir = I915_READ(VLV_IIR);
1842 if (master_ctl == 0 && iir == 0)
1848 * Theory on interrupt generation, based on empirical evidence:
1850 * x = ((VLV_IIR & VLV_IER) ||
1851 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1852 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1854 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1855 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1856 * guarantee the CPU interrupt will be raised again even if we
1857 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1858 * bits this time around.
1860 I915_WRITE(GEN8_MASTER_IRQ, 0);
1861 ier = I915_READ(VLV_IER);
1862 I915_WRITE(VLV_IER, 0);
1864 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1866 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1867 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1869 /* Call regardless, as some status bits might not be
1870 * signalled in iir */
1871 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1874 * VLV_IIR is single buffered, and reflects the level
1875 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1878 I915_WRITE(VLV_IIR, iir);
1880 I915_WRITE(VLV_IER, ier);
1881 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1882 POSTING_READ(GEN8_MASTER_IRQ);
1884 gen8_gt_irq_handler(dev_priv, gt_iir);
1887 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1889 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1892 enable_rpm_wakeref_asserts(dev_priv);
1897 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1898 u32 hotplug_trigger,
1899 const u32 hpd[HPD_NUM_PINS])
1901 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1904 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1905 * unless we touch the hotplug register, even if hotplug_trigger is
1906 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1909 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1910 if (!hotplug_trigger) {
1911 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1912 PORTD_HOTPLUG_STATUS_MASK |
1913 PORTC_HOTPLUG_STATUS_MASK |
1914 PORTB_HOTPLUG_STATUS_MASK;
1915 dig_hotplug_reg &= ~mask;
1918 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1919 if (!hotplug_trigger)
1922 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1923 dig_hotplug_reg, hpd,
1924 pch_port_hotplug_long_detect);
1926 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1929 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1932 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1934 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1936 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1937 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1938 SDE_AUDIO_POWER_SHIFT);
1939 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1943 if (pch_iir & SDE_AUX_MASK)
1944 dp_aux_irq_handler(dev_priv);
1946 if (pch_iir & SDE_GMBUS)
1947 gmbus_irq_handler(dev_priv);
1949 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1950 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1952 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1953 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1955 if (pch_iir & SDE_POISON)
1956 DRM_ERROR("PCH poison interrupt\n");
1958 if (pch_iir & SDE_FDI_MASK)
1959 for_each_pipe(dev_priv, pipe)
1960 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1962 I915_READ(FDI_RX_IIR(pipe)));
1964 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1965 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1967 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1968 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1970 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1971 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1973 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1974 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1977 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1979 u32 err_int = I915_READ(GEN7_ERR_INT);
1982 if (err_int & ERR_INT_POISON)
1983 DRM_ERROR("Poison interrupt\n");
1985 for_each_pipe(dev_priv, pipe) {
1986 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1987 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1989 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1990 if (IS_IVYBRIDGE(dev_priv))
1991 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1993 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1997 I915_WRITE(GEN7_ERR_INT, err_int);
2000 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2002 u32 serr_int = I915_READ(SERR_INT);
2004 if (serr_int & SERR_INT_POISON)
2005 DRM_ERROR("PCH poison interrupt\n");
2007 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2008 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2010 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2011 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2013 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2014 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2016 I915_WRITE(SERR_INT, serr_int);
2019 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2022 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2024 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2026 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2027 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2028 SDE_AUDIO_POWER_SHIFT_CPT);
2029 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2033 if (pch_iir & SDE_AUX_MASK_CPT)
2034 dp_aux_irq_handler(dev_priv);
2036 if (pch_iir & SDE_GMBUS_CPT)
2037 gmbus_irq_handler(dev_priv);
2039 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2040 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2042 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2043 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2045 if (pch_iir & SDE_FDI_MASK_CPT)
2046 for_each_pipe(dev_priv, pipe)
2047 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2049 I915_READ(FDI_RX_IIR(pipe)));
2051 if (pch_iir & SDE_ERROR_CPT)
2052 cpt_serr_int_handler(dev_priv);
2055 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2057 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2058 ~SDE_PORTE_HOTPLUG_SPT;
2059 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2060 u32 pin_mask = 0, long_mask = 0;
2062 if (hotplug_trigger) {
2063 u32 dig_hotplug_reg;
2065 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2066 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2068 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2069 dig_hotplug_reg, hpd_spt,
2070 spt_port_hotplug_long_detect);
2073 if (hotplug2_trigger) {
2074 u32 dig_hotplug_reg;
2076 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2077 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2079 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2080 dig_hotplug_reg, hpd_spt,
2081 spt_port_hotplug2_long_detect);
2085 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2087 if (pch_iir & SDE_GMBUS_CPT)
2088 gmbus_irq_handler(dev_priv);
2091 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2092 u32 hotplug_trigger,
2093 const u32 hpd[HPD_NUM_PINS])
2095 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2097 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2098 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2100 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2101 dig_hotplug_reg, hpd,
2102 ilk_port_hotplug_long_detect);
2104 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2107 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2111 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2113 if (hotplug_trigger)
2114 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2116 if (de_iir & DE_AUX_CHANNEL_A)
2117 dp_aux_irq_handler(dev_priv);
2119 if (de_iir & DE_GSE)
2120 intel_opregion_asle_intr(dev_priv);
2122 if (de_iir & DE_POISON)
2123 DRM_ERROR("Poison interrupt\n");
2125 for_each_pipe(dev_priv, pipe) {
2126 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2127 intel_pipe_handle_vblank(dev_priv, pipe))
2128 intel_check_page_flip(dev_priv, pipe);
2130 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2131 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2133 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2134 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2136 /* plane/pipes map 1:1 on ilk+ */
2137 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2138 intel_finish_page_flip_cs(dev_priv, pipe);
2141 /* check event from PCH */
2142 if (de_iir & DE_PCH_EVENT) {
2143 u32 pch_iir = I915_READ(SDEIIR);
2145 if (HAS_PCH_CPT(dev_priv))
2146 cpt_irq_handler(dev_priv, pch_iir);
2148 ibx_irq_handler(dev_priv, pch_iir);
2150 /* should clear PCH hotplug event before clear CPU irq */
2151 I915_WRITE(SDEIIR, pch_iir);
2154 if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2155 ironlake_rps_change_irq_handler(dev_priv);
2158 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2162 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2164 if (hotplug_trigger)
2165 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2167 if (de_iir & DE_ERR_INT_IVB)
2168 ivb_err_int_handler(dev_priv);
2170 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2171 dp_aux_irq_handler(dev_priv);
2173 if (de_iir & DE_GSE_IVB)
2174 intel_opregion_asle_intr(dev_priv);
2176 for_each_pipe(dev_priv, pipe) {
2177 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2178 intel_pipe_handle_vblank(dev_priv, pipe))
2179 intel_check_page_flip(dev_priv, pipe);
2181 /* plane/pipes map 1:1 on ilk+ */
2182 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2183 intel_finish_page_flip_cs(dev_priv, pipe);
2186 /* check event from PCH */
2187 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2188 u32 pch_iir = I915_READ(SDEIIR);
2190 cpt_irq_handler(dev_priv, pch_iir);
2192 /* clear PCH hotplug event before clear CPU irq */
2193 I915_WRITE(SDEIIR, pch_iir);
2198 * To handle irqs with the minimum potential races with fresh interrupts, we:
2199 * 1 - Disable Master Interrupt Control.
2200 * 2 - Find the source(s) of the interrupt.
2201 * 3 - Clear the Interrupt Identity bits (IIR).
2202 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2203 * 5 - Re-enable Master Interrupt Control.
2205 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2207 struct drm_device *dev = arg;
2208 struct drm_i915_private *dev_priv = to_i915(dev);
2209 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2210 irqreturn_t ret = IRQ_NONE;
2212 if (!intel_irqs_enabled(dev_priv))
2215 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2216 disable_rpm_wakeref_asserts(dev_priv);
2218 /* disable master interrupt before clearing iir */
2219 de_ier = I915_READ(DEIER);
2220 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2221 POSTING_READ(DEIER);
2223 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2224 * interrupts will will be stored on its back queue, and then we'll be
2225 * able to process them after we restore SDEIER (as soon as we restore
2226 * it, we'll get an interrupt if SDEIIR still has something to process
2227 * due to its back queue). */
2228 if (!HAS_PCH_NOP(dev_priv)) {
2229 sde_ier = I915_READ(SDEIER);
2230 I915_WRITE(SDEIER, 0);
2231 POSTING_READ(SDEIER);
2234 /* Find, clear, then process each source of interrupt */
2236 gt_iir = I915_READ(GTIIR);
2238 I915_WRITE(GTIIR, gt_iir);
2240 if (INTEL_GEN(dev_priv) >= 6)
2241 snb_gt_irq_handler(dev_priv, gt_iir);
2243 ilk_gt_irq_handler(dev_priv, gt_iir);
2246 de_iir = I915_READ(DEIIR);
2248 I915_WRITE(DEIIR, de_iir);
2250 if (INTEL_GEN(dev_priv) >= 7)
2251 ivb_display_irq_handler(dev_priv, de_iir);
2253 ilk_display_irq_handler(dev_priv, de_iir);
2256 if (INTEL_GEN(dev_priv) >= 6) {
2257 u32 pm_iir = I915_READ(GEN6_PMIIR);
2259 I915_WRITE(GEN6_PMIIR, pm_iir);
2261 gen6_rps_irq_handler(dev_priv, pm_iir);
2265 I915_WRITE(DEIER, de_ier);
2266 POSTING_READ(DEIER);
2267 if (!HAS_PCH_NOP(dev_priv)) {
2268 I915_WRITE(SDEIER, sde_ier);
2269 POSTING_READ(SDEIER);
2272 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2273 enable_rpm_wakeref_asserts(dev_priv);
2278 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2279 u32 hotplug_trigger,
2280 const u32 hpd[HPD_NUM_PINS])
2282 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2284 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2285 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2287 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2288 dig_hotplug_reg, hpd,
2289 bxt_port_hotplug_long_detect);
2291 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2295 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2297 irqreturn_t ret = IRQ_NONE;
2301 if (master_ctl & GEN8_DE_MISC_IRQ) {
2302 iir = I915_READ(GEN8_DE_MISC_IIR);
2304 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2306 if (iir & GEN8_DE_MISC_GSE)
2307 intel_opregion_asle_intr(dev_priv);
2309 DRM_ERROR("Unexpected DE Misc interrupt\n");
2312 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2315 if (master_ctl & GEN8_DE_PORT_IRQ) {
2316 iir = I915_READ(GEN8_DE_PORT_IIR);
2321 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2324 tmp_mask = GEN8_AUX_CHANNEL_A;
2325 if (INTEL_INFO(dev_priv)->gen >= 9)
2326 tmp_mask |= GEN9_AUX_CHANNEL_B |
2327 GEN9_AUX_CHANNEL_C |
2330 if (iir & tmp_mask) {
2331 dp_aux_irq_handler(dev_priv);
2335 if (IS_BROXTON(dev_priv)) {
2336 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2338 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2342 } else if (IS_BROADWELL(dev_priv)) {
2343 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2345 ilk_hpd_irq_handler(dev_priv,
2351 if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2352 gmbus_irq_handler(dev_priv);
2357 DRM_ERROR("Unexpected DE Port interrupt\n");
2360 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2363 for_each_pipe(dev_priv, pipe) {
2364 u32 flip_done, fault_errors;
2366 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2369 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2371 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2376 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2378 if (iir & GEN8_PIPE_VBLANK &&
2379 intel_pipe_handle_vblank(dev_priv, pipe))
2380 intel_check_page_flip(dev_priv, pipe);
2383 if (INTEL_INFO(dev_priv)->gen >= 9)
2384 flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2386 flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2389 intel_finish_page_flip_cs(dev_priv, pipe);
2391 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2392 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2394 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2395 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2398 if (INTEL_INFO(dev_priv)->gen >= 9)
2399 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2401 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2404 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2409 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2410 master_ctl & GEN8_DE_PCH_IRQ) {
2412 * FIXME(BDW): Assume for now that the new interrupt handling
2413 * scheme also closed the SDE interrupt handling race we've seen
2414 * on older pch-split platforms. But this needs testing.
2416 iir = I915_READ(SDEIIR);
2418 I915_WRITE(SDEIIR, iir);
2421 if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2422 spt_irq_handler(dev_priv, iir);
2424 cpt_irq_handler(dev_priv, iir);
2427 * Like on previous PCH there seems to be something
2428 * fishy going on with forwarding PCH interrupts.
2430 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2437 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2439 struct drm_device *dev = arg;
2440 struct drm_i915_private *dev_priv = to_i915(dev);
2445 if (!intel_irqs_enabled(dev_priv))
2448 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2449 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2453 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2455 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2456 disable_rpm_wakeref_asserts(dev_priv);
2458 /* Find, clear, then process each source of interrupt */
2459 ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2460 gen8_gt_irq_handler(dev_priv, gt_iir);
2461 ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2463 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2464 POSTING_READ_FW(GEN8_MASTER_IRQ);
2466 enable_rpm_wakeref_asserts(dev_priv);
2471 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2474 * Notify all waiters for GPU completion events that reset state has
2475 * been changed, and that they need to restart their wait after
2476 * checking for potential errors (and bail out to drop locks if there is
2477 * a gpu reset pending so that i915_error_work_func can acquire them).
2480 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2481 wake_up_all(&dev_priv->gpu_error.wait_queue);
2483 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2484 wake_up_all(&dev_priv->pending_flip_queue);
2488 * i915_reset_and_wakeup - do process context error handling work
2489 * @dev_priv: i915 device private
2491 * Fire an error uevent so userspace can see that a hang or error
2494 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2496 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2497 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2498 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2499 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2501 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2503 DRM_DEBUG_DRIVER("resetting chip\n");
2504 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2507 * In most cases it's guaranteed that we get here with an RPM
2508 * reference held, for example because there is a pending GPU
2509 * request that won't finish until the reset is done. This
2510 * isn't the case at least when we get here by doing a
2511 * simulated reset via debugs, so get an RPM reference.
2513 intel_runtime_pm_get(dev_priv);
2514 intel_prepare_reset(dev_priv);
2518 * All state reset _must_ be completed before we update the
2519 * reset counter, for otherwise waiters might miss the reset
2520 * pending state and not properly drop locks, resulting in
2521 * deadlocks with the reset work.
2523 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2524 i915_reset(dev_priv);
2525 mutex_unlock(&dev_priv->drm.struct_mutex);
2528 /* We need to wait for anyone holding the lock to wakeup */
2529 } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2530 I915_RESET_IN_PROGRESS,
2531 TASK_UNINTERRUPTIBLE,
2534 intel_finish_reset(dev_priv);
2535 intel_runtime_pm_put(dev_priv);
2537 if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2538 kobject_uevent_env(kobj,
2539 KOBJ_CHANGE, reset_done_event);
2542 * Note: The wake_up also serves as a memory barrier so that
2543 * waiters see the updated value of the dev_priv->gpu_error.
2545 wake_up_all(&dev_priv->gpu_error.reset_queue);
2549 i915_err_print_instdone(struct drm_i915_private *dev_priv,
2550 struct intel_instdone *instdone)
2552 pr_err(" INSTDONE: 0x%08x\n", instdone->instdone);
2554 if (INTEL_GEN(dev_priv) <= 3)
2557 pr_err(" SC_INSTDONE: 0x%08x\n", instdone->slice_common);
2559 if (INTEL_GEN(dev_priv) <= 6)
2562 pr_err(" SAMPLER_INSTDONE: 0x%08x\n", instdone->sampler);
2563 pr_err(" ROW_INSTDONE: 0x%08x\n", instdone->row);
2566 static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2568 struct intel_instdone instdone;
2569 u32 eir = I915_READ(EIR);
2575 pr_err("render error detected, EIR: 0x%08x\n", eir);
2577 i915_get_engine_instdone(dev_priv, RCS, &instdone);
2579 if (IS_G4X(dev_priv)) {
2580 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2581 u32 ipeir = I915_READ(IPEIR_I965);
2583 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2584 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2585 i915_err_print_instdone(dev_priv, &instdone);
2586 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2587 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2588 I915_WRITE(IPEIR_I965, ipeir);
2589 POSTING_READ(IPEIR_I965);
2591 if (eir & GM45_ERROR_PAGE_TABLE) {
2592 u32 pgtbl_err = I915_READ(PGTBL_ER);
2593 pr_err("page table error\n");
2594 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2595 I915_WRITE(PGTBL_ER, pgtbl_err);
2596 POSTING_READ(PGTBL_ER);
2600 if (!IS_GEN2(dev_priv)) {
2601 if (eir & I915_ERROR_PAGE_TABLE) {
2602 u32 pgtbl_err = I915_READ(PGTBL_ER);
2603 pr_err("page table error\n");
2604 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2605 I915_WRITE(PGTBL_ER, pgtbl_err);
2606 POSTING_READ(PGTBL_ER);
2610 if (eir & I915_ERROR_MEMORY_REFRESH) {
2611 pr_err("memory refresh error:\n");
2612 for_each_pipe(dev_priv, pipe)
2613 pr_err("pipe %c stat: 0x%08x\n",
2614 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2615 /* pipestat has already been acked */
2617 if (eir & I915_ERROR_INSTRUCTION) {
2618 pr_err("instruction error\n");
2619 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2620 i915_err_print_instdone(dev_priv, &instdone);
2621 if (INTEL_GEN(dev_priv) < 4) {
2622 u32 ipeir = I915_READ(IPEIR);
2624 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2625 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2626 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2627 I915_WRITE(IPEIR, ipeir);
2628 POSTING_READ(IPEIR);
2630 u32 ipeir = I915_READ(IPEIR_I965);
2632 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2633 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2634 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2635 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2636 I915_WRITE(IPEIR_I965, ipeir);
2637 POSTING_READ(IPEIR_I965);
2641 I915_WRITE(EIR, eir);
2643 eir = I915_READ(EIR);
2646 * some errors might have become stuck,
2649 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2650 I915_WRITE(EMR, I915_READ(EMR) | eir);
2651 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2656 * i915_handle_error - handle a gpu error
2657 * @dev_priv: i915 device private
2658 * @engine_mask: mask representing engines that are hung
2659 * Do some basic checking of register state at error time and
2660 * dump it to the syslog. Also call i915_capture_error_state() to make
2661 * sure we get a record and make it available in debugfs. Fire a uevent
2662 * so userspace knows something bad happened (should trigger collection
2663 * of a ring dump etc.).
2664 * @fmt: Error message format string
2666 void i915_handle_error(struct drm_i915_private *dev_priv,
2668 const char *fmt, ...)
2673 va_start(args, fmt);
2674 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2677 i915_capture_error_state(dev_priv, engine_mask, error_msg);
2678 i915_report_and_clear_eir(dev_priv);
2683 if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2684 &dev_priv->gpu_error.flags))
2688 * Wakeup waiting processes so that the reset function
2689 * i915_reset_and_wakeup doesn't deadlock trying to grab
2690 * various locks. By bumping the reset counter first, the woken
2691 * processes will see a reset in progress and back off,
2692 * releasing their locks and then wait for the reset completion.
2693 * We must do this for _all_ gpu waiters that might hold locks
2694 * that the reset work needs to acquire.
2696 * Note: The wake_up also provides a memory barrier to ensure that the
2697 * waiters see the updated value of the reset flags.
2699 i915_error_wake_up(dev_priv);
2701 i915_reset_and_wakeup(dev_priv);
2704 /* Called from drm generic code, passed 'crtc' which
2705 * we use as a pipe index
2707 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2709 struct drm_i915_private *dev_priv = to_i915(dev);
2710 unsigned long irqflags;
2712 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2713 if (INTEL_INFO(dev)->gen >= 4)
2714 i915_enable_pipestat(dev_priv, pipe,
2715 PIPE_START_VBLANK_INTERRUPT_STATUS);
2717 i915_enable_pipestat(dev_priv, pipe,
2718 PIPE_VBLANK_INTERRUPT_STATUS);
2719 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2724 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2726 struct drm_i915_private *dev_priv = to_i915(dev);
2727 unsigned long irqflags;
2728 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2729 DE_PIPE_VBLANK(pipe);
2731 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2732 ilk_enable_display_irq(dev_priv, bit);
2733 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2738 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2740 struct drm_i915_private *dev_priv = to_i915(dev);
2741 unsigned long irqflags;
2743 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2744 i915_enable_pipestat(dev_priv, pipe,
2745 PIPE_START_VBLANK_INTERRUPT_STATUS);
2746 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2751 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2753 struct drm_i915_private *dev_priv = to_i915(dev);
2754 unsigned long irqflags;
2756 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2757 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2758 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2763 /* Called from drm generic code, passed 'crtc' which
2764 * we use as a pipe index
2766 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2768 struct drm_i915_private *dev_priv = to_i915(dev);
2769 unsigned long irqflags;
2771 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2772 i915_disable_pipestat(dev_priv, pipe,
2773 PIPE_VBLANK_INTERRUPT_STATUS |
2774 PIPE_START_VBLANK_INTERRUPT_STATUS);
2775 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2778 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2780 struct drm_i915_private *dev_priv = to_i915(dev);
2781 unsigned long irqflags;
2782 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2783 DE_PIPE_VBLANK(pipe);
2785 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2786 ilk_disable_display_irq(dev_priv, bit);
2787 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2790 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2792 struct drm_i915_private *dev_priv = to_i915(dev);
2793 unsigned long irqflags;
2795 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2796 i915_disable_pipestat(dev_priv, pipe,
2797 PIPE_START_VBLANK_INTERRUPT_STATUS);
2798 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2801 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2803 struct drm_i915_private *dev_priv = to_i915(dev);
2804 unsigned long irqflags;
2806 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2807 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2808 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2812 ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2814 if (INTEL_GEN(engine->i915) >= 8) {
2815 return (ipehr >> 23) == 0x1c;
2817 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2818 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2819 MI_SEMAPHORE_REGISTER);
2823 static struct intel_engine_cs *
2824 semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2827 struct drm_i915_private *dev_priv = engine->i915;
2828 struct intel_engine_cs *signaller;
2830 if (INTEL_GEN(dev_priv) >= 8) {
2831 for_each_engine(signaller, dev_priv) {
2832 if (engine == signaller)
2835 if (offset == signaller->semaphore.signal_ggtt[engine->id])
2839 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2841 for_each_engine(signaller, dev_priv) {
2842 if(engine == signaller)
2845 if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2850 DRM_DEBUG_DRIVER("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2851 engine->id, ipehr, offset);
2853 return ERR_PTR(-ENODEV);
2856 static struct intel_engine_cs *
2857 semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2859 struct drm_i915_private *dev_priv = engine->i915;
2860 void __iomem *vaddr;
2861 u32 cmd, ipehr, head;
2866 * This function does not support execlist mode - any attempt to
2867 * proceed further into this function will result in a kernel panic
2868 * when dereferencing ring->buffer, which is not set up in execlist
2871 * The correct way of doing it would be to derive the currently
2872 * executing ring buffer from the current context, which is derived
2873 * from the currently running request. Unfortunately, to get the
2874 * current request we would have to grab the struct_mutex before doing
2875 * anything else, which would be ill-advised since some other thread
2876 * might have grabbed it already and managed to hang itself, causing
2877 * the hang checker to deadlock.
2879 * Therefore, this function does not support execlist mode in its
2880 * current form. Just return NULL and move on.
2882 if (engine->buffer == NULL)
2885 ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2886 if (!ipehr_is_semaphore_wait(engine, ipehr))
2890 * HEAD is likely pointing to the dword after the actual command,
2891 * so scan backwards until we find the MBOX. But limit it to just 3
2892 * or 4 dwords depending on the semaphore wait command size.
2893 * Note that we don't care about ACTHD here since that might
2894 * point at at batch, and semaphores are always emitted into the
2895 * ringbuffer itself.
2897 head = I915_READ_HEAD(engine) & HEAD_ADDR;
2898 backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2899 vaddr = (void __iomem *)engine->buffer->vaddr;
2901 for (i = backwards; i; --i) {
2903 * Be paranoid and presume the hw has gone off into the wild -
2904 * our ring is smaller than what the hardware (and hence
2905 * HEAD_ADDR) allows. Also handles wrap-around.
2907 head &= engine->buffer->size - 1;
2909 /* This here seems to blow up */
2910 cmd = ioread32(vaddr + head);
2920 *seqno = ioread32(vaddr + head + 4) + 1;
2921 if (INTEL_GEN(dev_priv) >= 8) {
2922 offset = ioread32(vaddr + head + 12);
2924 offset |= ioread32(vaddr + head + 8);
2926 return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2929 static int semaphore_passed(struct intel_engine_cs *engine)
2931 struct drm_i915_private *dev_priv = engine->i915;
2932 struct intel_engine_cs *signaller;
2935 engine->hangcheck.deadlock++;
2937 signaller = semaphore_waits_for(engine, &seqno);
2938 if (signaller == NULL)
2941 if (IS_ERR(signaller))
2944 /* Prevent pathological recursion due to driver bugs */
2945 if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2948 if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
2951 /* cursory check for an unkickable deadlock */
2952 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2953 semaphore_passed(signaller) < 0)
2959 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2961 struct intel_engine_cs *engine;
2963 for_each_engine(engine, dev_priv)
2964 engine->hangcheck.deadlock = 0;
2967 static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
2969 u32 tmp = current_instdone | *old_instdone;
2972 unchanged = tmp == *old_instdone;
2973 *old_instdone |= tmp;
2978 static bool subunits_stuck(struct intel_engine_cs *engine)
2980 struct drm_i915_private *dev_priv = engine->i915;
2981 struct intel_instdone instdone;
2982 struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
2985 if (engine->id != RCS)
2988 i915_get_engine_instdone(dev_priv, RCS, &instdone);
2990 /* There might be unstable subunit states even when
2991 * actual head is not moving. Filter out the unstable ones by
2992 * accumulating the undone -> done transitions and only
2993 * consider those as progress.
2995 stuck = instdone_unchanged(instdone.instdone,
2996 &accu_instdone->instdone);
2997 stuck &= instdone_unchanged(instdone.slice_common,
2998 &accu_instdone->slice_common);
2999 stuck &= instdone_unchanged(instdone.sampler,
3000 &accu_instdone->sampler);
3001 stuck &= instdone_unchanged(instdone.row,
3002 &accu_instdone->row);
3007 static enum intel_engine_hangcheck_action
3008 head_stuck(struct intel_engine_cs *engine, u64 acthd)
3010 if (acthd != engine->hangcheck.acthd) {
3012 /* Clear subunit states on head movement */
3013 memset(&engine->hangcheck.instdone, 0,
3014 sizeof(engine->hangcheck.instdone));
3016 return HANGCHECK_ACTIVE;
3019 if (!subunits_stuck(engine))
3020 return HANGCHECK_ACTIVE;
3022 return HANGCHECK_HUNG;
3025 static enum intel_engine_hangcheck_action
3026 engine_stuck(struct intel_engine_cs *engine, u64 acthd)
3028 struct drm_i915_private *dev_priv = engine->i915;
3029 enum intel_engine_hangcheck_action ha;
3032 ha = head_stuck(engine, acthd);
3033 if (ha != HANGCHECK_HUNG)
3036 if (IS_GEN2(dev_priv))
3037 return HANGCHECK_HUNG;
3039 /* Is the chip hanging on a WAIT_FOR_EVENT?
3040 * If so we can simply poke the RB_WAIT bit
3041 * and break the hang. This should work on
3042 * all but the second generation chipsets.
3044 tmp = I915_READ_CTL(engine);
3045 if (tmp & RING_WAIT) {
3046 i915_handle_error(dev_priv, 0,
3047 "Kicking stuck wait on %s",
3049 I915_WRITE_CTL(engine, tmp);
3050 return HANGCHECK_KICK;
3053 if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3054 switch (semaphore_passed(engine)) {
3056 return HANGCHECK_HUNG;
3058 i915_handle_error(dev_priv, 0,
3059 "Kicking stuck semaphore on %s",
3061 I915_WRITE_CTL(engine, tmp);
3062 return HANGCHECK_KICK;
3064 return HANGCHECK_WAIT;
3068 return HANGCHECK_HUNG;
3072 * This is called when the chip hasn't reported back with completed
3073 * batchbuffers in a long time. We keep track per ring seqno progress and
3074 * if there are no progress, hangcheck score for that ring is increased.
3075 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3076 * we kick the ring. If we see no progress on three subsequent calls
3077 * we assume chip is wedged and try to fix it by resetting the chip.
3079 static void i915_hangcheck_elapsed(struct work_struct *work)
3081 struct drm_i915_private *dev_priv =
3082 container_of(work, typeof(*dev_priv),
3083 gpu_error.hangcheck_work.work);
3084 struct intel_engine_cs *engine;
3085 unsigned int hung = 0, stuck = 0;
3090 #define ACTIVE_DECAY 15
3092 if (!i915.enable_hangcheck)
3095 if (!READ_ONCE(dev_priv->gt.awake))
3098 /* As enabling the GPU requires fairly extensive mmio access,
3099 * periodically arm the mmio checker to see if we are triggering
3100 * any invalid access.
3102 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3104 for_each_engine(engine, dev_priv) {
3105 bool busy = intel_engine_has_waiter(engine);
3110 semaphore_clear_deadlocks(dev_priv);
3112 /* We don't strictly need an irq-barrier here, as we are not
3113 * serving an interrupt request, be paranoid in case the
3114 * barrier has side-effects (such as preventing a broken
3115 * cacheline snoop) and so be sure that we can see the seqno
3116 * advance. If the seqno should stick, due to a stale
3117 * cacheline, we would erroneously declare the GPU hung.
3119 if (engine->irq_seqno_barrier)
3120 engine->irq_seqno_barrier(engine);
3122 acthd = intel_engine_get_active_head(engine);
3123 seqno = intel_engine_get_seqno(engine);
3124 submit = READ_ONCE(engine->last_submitted_seqno);
3126 if (engine->hangcheck.seqno == seqno) {
3127 if (i915_seqno_passed(seqno, submit)) {
3128 engine->hangcheck.action = HANGCHECK_IDLE;
3130 /* We always increment the hangcheck score
3131 * if the engine is busy and still processing
3132 * the same request, so that no single request
3133 * can run indefinitely (such as a chain of
3134 * batches). The only time we do not increment
3135 * the hangcheck score on this ring, if this
3136 * engine is in a legitimate wait for another
3137 * engine. In that case the waiting engine is a
3138 * victim and we want to be sure we catch the
3139 * right culprit. Then every time we do kick
3140 * the ring, add a small increment to the
3141 * score so that we can catch a batch that is
3142 * being repeatedly kicked and so responsible
3143 * for stalling the machine.
3145 engine->hangcheck.action =
3146 engine_stuck(engine, acthd);
3148 switch (engine->hangcheck.action) {
3149 case HANGCHECK_IDLE:
3150 case HANGCHECK_WAIT:
3152 case HANGCHECK_ACTIVE:
3153 engine->hangcheck.score += BUSY;
3155 case HANGCHECK_KICK:
3156 engine->hangcheck.score += KICK;
3158 case HANGCHECK_HUNG:
3159 engine->hangcheck.score += HUNG;
3164 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3165 hung |= intel_engine_flag(engine);
3166 if (engine->hangcheck.action != HANGCHECK_HUNG)
3167 stuck |= intel_engine_flag(engine);
3170 engine->hangcheck.action = HANGCHECK_ACTIVE;
3172 /* Gradually reduce the count so that we catch DoS
3173 * attempts across multiple batches.
3175 if (engine->hangcheck.score > 0)
3176 engine->hangcheck.score -= ACTIVE_DECAY;
3177 if (engine->hangcheck.score < 0)
3178 engine->hangcheck.score = 0;
3180 /* Clear head and subunit states on seqno movement */
3183 memset(&engine->hangcheck.instdone, 0,
3184 sizeof(engine->hangcheck.instdone));
3187 engine->hangcheck.seqno = seqno;
3188 engine->hangcheck.acthd = acthd;
3197 /* If some rings hung but others were still busy, only
3198 * blame the hanging rings in the synopsis.
3202 len = scnprintf(msg, sizeof(msg),
3203 "%s on ", stuck == hung ? "No progress" : "Hang");
3204 for_each_engine_masked(engine, dev_priv, hung, tmp)
3205 len += scnprintf(msg + len, sizeof(msg) - len,
3206 "%s, ", engine->name);
3209 return i915_handle_error(dev_priv, hung, msg);
3212 /* Reset timer in case GPU hangs without another request being added */
3214 i915_queue_hangcheck(dev_priv);
3217 static void ibx_irq_reset(struct drm_device *dev)
3219 struct drm_i915_private *dev_priv = to_i915(dev);
3221 if (HAS_PCH_NOP(dev))
3224 GEN5_IRQ_RESET(SDE);
3226 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3227 I915_WRITE(SERR_INT, 0xffffffff);
3231 * SDEIER is also touched by the interrupt handler to work around missed PCH
3232 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3233 * instead we unconditionally enable all PCH interrupt sources here, but then
3234 * only unmask them as needed with SDEIMR.
3236 * This function needs to be called before interrupts are enabled.
3238 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3240 struct drm_i915_private *dev_priv = to_i915(dev);
3242 if (HAS_PCH_NOP(dev))
3245 WARN_ON(I915_READ(SDEIER) != 0);
3246 I915_WRITE(SDEIER, 0xffffffff);
3247 POSTING_READ(SDEIER);
3250 static void gen5_gt_irq_reset(struct drm_device *dev)
3252 struct drm_i915_private *dev_priv = to_i915(dev);
3255 if (INTEL_INFO(dev)->gen >= 6)
3256 GEN5_IRQ_RESET(GEN6_PM);
3259 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3263 if (IS_CHERRYVIEW(dev_priv))
3264 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3266 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3268 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3269 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3271 for_each_pipe(dev_priv, pipe) {
3272 I915_WRITE(PIPESTAT(pipe),
3273 PIPE_FIFO_UNDERRUN_STATUS |
3274 PIPESTAT_INT_STATUS_MASK);
3275 dev_priv->pipestat_irq_mask[pipe] = 0;
3278 GEN5_IRQ_RESET(VLV_);
3279 dev_priv->irq_mask = ~0;
3282 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3288 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3289 PIPE_CRC_DONE_INTERRUPT_STATUS;
3291 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3292 for_each_pipe(dev_priv, pipe)
3293 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3295 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3296 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3297 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3298 if (IS_CHERRYVIEW(dev_priv))
3299 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3301 WARN_ON(dev_priv->irq_mask != ~0);
3303 dev_priv->irq_mask = ~enable_mask;
3305 GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3310 static void ironlake_irq_reset(struct drm_device *dev)
3312 struct drm_i915_private *dev_priv = to_i915(dev);
3314 I915_WRITE(HWSTAM, 0xffffffff);
3318 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3320 gen5_gt_irq_reset(dev);
3325 static void valleyview_irq_preinstall(struct drm_device *dev)
3327 struct drm_i915_private *dev_priv = to_i915(dev);
3329 I915_WRITE(VLV_MASTER_IER, 0);
3330 POSTING_READ(VLV_MASTER_IER);
3332 gen5_gt_irq_reset(dev);
3334 spin_lock_irq(&dev_priv->irq_lock);
3335 if (dev_priv->display_irqs_enabled)
3336 vlv_display_irq_reset(dev_priv);
3337 spin_unlock_irq(&dev_priv->irq_lock);
3340 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3342 GEN8_IRQ_RESET_NDX(GT, 0);
3343 GEN8_IRQ_RESET_NDX(GT, 1);
3344 GEN8_IRQ_RESET_NDX(GT, 2);
3345 GEN8_IRQ_RESET_NDX(GT, 3);
3348 static void gen8_irq_reset(struct drm_device *dev)
3350 struct drm_i915_private *dev_priv = to_i915(dev);
3353 I915_WRITE(GEN8_MASTER_IRQ, 0);
3354 POSTING_READ(GEN8_MASTER_IRQ);
3356 gen8_gt_irq_reset(dev_priv);
3358 for_each_pipe(dev_priv, pipe)
3359 if (intel_display_power_is_enabled(dev_priv,
3360 POWER_DOMAIN_PIPE(pipe)))
3361 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3363 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3364 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3365 GEN5_IRQ_RESET(GEN8_PCU_);
3367 if (HAS_PCH_SPLIT(dev))
3371 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3372 unsigned int pipe_mask)
3374 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3377 spin_lock_irq(&dev_priv->irq_lock);
3378 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3379 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3380 dev_priv->de_irq_mask[pipe],
3381 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3382 spin_unlock_irq(&dev_priv->irq_lock);
3385 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3386 unsigned int pipe_mask)
3390 spin_lock_irq(&dev_priv->irq_lock);
3391 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3392 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3393 spin_unlock_irq(&dev_priv->irq_lock);
3395 /* make sure we're done processing display irqs */
3396 synchronize_irq(dev_priv->drm.irq);
3399 static void cherryview_irq_preinstall(struct drm_device *dev)
3401 struct drm_i915_private *dev_priv = to_i915(dev);
3403 I915_WRITE(GEN8_MASTER_IRQ, 0);
3404 POSTING_READ(GEN8_MASTER_IRQ);
3406 gen8_gt_irq_reset(dev_priv);
3408 GEN5_IRQ_RESET(GEN8_PCU_);
3410 spin_lock_irq(&dev_priv->irq_lock);
3411 if (dev_priv->display_irqs_enabled)
3412 vlv_display_irq_reset(dev_priv);
3413 spin_unlock_irq(&dev_priv->irq_lock);
3416 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3417 const u32 hpd[HPD_NUM_PINS])
3419 struct intel_encoder *encoder;
3420 u32 enabled_irqs = 0;
3422 for_each_intel_encoder(&dev_priv->drm, encoder)
3423 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3424 enabled_irqs |= hpd[encoder->hpd_pin];
3426 return enabled_irqs;
3429 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3431 u32 hotplug_irqs, hotplug, enabled_irqs;
3433 if (HAS_PCH_IBX(dev_priv)) {
3434 hotplug_irqs = SDE_HOTPLUG_MASK;
3435 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3437 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3438 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3441 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3444 * Enable digital hotplug on the PCH, and configure the DP short pulse
3445 * duration to 2ms (which is the minimum in the Display Port spec).
3446 * The pulse duration bits are reserved on LPT+.
3448 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3449 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3450 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3451 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3452 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3454 * When CPU and PCH are on the same package, port A
3455 * HPD must be enabled in both north and south.
3457 if (HAS_PCH_LPT_LP(dev_priv))
3458 hotplug |= PORTA_HOTPLUG_ENABLE;
3459 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3462 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3464 u32 hotplug_irqs, hotplug, enabled_irqs;
3466 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3467 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3469 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3471 /* Enable digital hotplug on the PCH */
3472 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3473 hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3474 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3475 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3477 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3478 hotplug |= PORTE_HOTPLUG_ENABLE;
3479 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3482 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3484 u32 hotplug_irqs, hotplug, enabled_irqs;
3486 if (INTEL_GEN(dev_priv) >= 8) {
3487 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3488 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3490 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3491 } else if (INTEL_GEN(dev_priv) >= 7) {
3492 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3493 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3495 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3497 hotplug_irqs = DE_DP_A_HOTPLUG;
3498 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3500 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3504 * Enable digital hotplug on the CPU, and configure the DP short pulse
3505 * duration to 2ms (which is the minimum in the Display Port spec)
3506 * The pulse duration bits are reserved on HSW+.
3508 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3509 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3510 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3511 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3513 ibx_hpd_irq_setup(dev_priv);
3516 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3518 u32 hotplug_irqs, hotplug, enabled_irqs;
3520 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3521 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3523 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3525 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3526 hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3527 PORTA_HOTPLUG_ENABLE;
3529 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3530 hotplug, enabled_irqs);
3531 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3534 * For BXT invert bit has to be set based on AOB design
3535 * for HPD detection logic, update it based on VBT fields.
3538 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3539 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3540 hotplug |= BXT_DDIA_HPD_INVERT;
3541 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3542 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3543 hotplug |= BXT_DDIB_HPD_INVERT;
3544 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3545 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3546 hotplug |= BXT_DDIC_HPD_INVERT;
3548 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3551 static void ibx_irq_postinstall(struct drm_device *dev)
3553 struct drm_i915_private *dev_priv = to_i915(dev);
3556 if (HAS_PCH_NOP(dev))
3559 if (HAS_PCH_IBX(dev))
3560 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3562 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3564 gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3565 I915_WRITE(SDEIMR, ~mask);
3568 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3570 struct drm_i915_private *dev_priv = to_i915(dev);
3571 u32 pm_irqs, gt_irqs;
3573 pm_irqs = gt_irqs = 0;
3575 dev_priv->gt_irq_mask = ~0;
3576 if (HAS_L3_DPF(dev)) {
3577 /* L3 parity interrupt is always unmasked. */
3578 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3579 gt_irqs |= GT_PARITY_ERROR(dev);
3582 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3584 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3586 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3589 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3591 if (INTEL_INFO(dev)->gen >= 6) {
3593 * RPS interrupts will get enabled/disabled on demand when RPS
3594 * itself is enabled/disabled.
3597 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3599 dev_priv->pm_irq_mask = 0xffffffff;
3600 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3604 static int ironlake_irq_postinstall(struct drm_device *dev)
3606 struct drm_i915_private *dev_priv = to_i915(dev);
3607 u32 display_mask, extra_mask;
3609 if (INTEL_INFO(dev)->gen >= 7) {
3610 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3611 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3612 DE_PLANEB_FLIP_DONE_IVB |
3613 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3614 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3615 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3616 DE_DP_A_HOTPLUG_IVB);
3618 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3619 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3621 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3623 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3624 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3628 dev_priv->irq_mask = ~display_mask;
3630 I915_WRITE(HWSTAM, 0xeffe);
3632 ibx_irq_pre_postinstall(dev);
3634 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3636 gen5_gt_irq_postinstall(dev);
3638 ibx_irq_postinstall(dev);
3640 if (IS_IRONLAKE_M(dev)) {
3641 /* Enable PCU event interrupts
3643 * spinlocking not required here for correctness since interrupt
3644 * setup is guaranteed to run in single-threaded context. But we
3645 * need it to make the assert_spin_locked happy. */
3646 spin_lock_irq(&dev_priv->irq_lock);
3647 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3648 spin_unlock_irq(&dev_priv->irq_lock);
3654 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3656 assert_spin_locked(&dev_priv->irq_lock);
3658 if (dev_priv->display_irqs_enabled)
3661 dev_priv->display_irqs_enabled = true;
3663 if (intel_irqs_enabled(dev_priv)) {
3664 vlv_display_irq_reset(dev_priv);
3665 vlv_display_irq_postinstall(dev_priv);
3669 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3671 assert_spin_locked(&dev_priv->irq_lock);
3673 if (!dev_priv->display_irqs_enabled)
3676 dev_priv->display_irqs_enabled = false;
3678 if (intel_irqs_enabled(dev_priv))
3679 vlv_display_irq_reset(dev_priv);
3683 static int valleyview_irq_postinstall(struct drm_device *dev)
3685 struct drm_i915_private *dev_priv = to_i915(dev);
3687 gen5_gt_irq_postinstall(dev);
3689 spin_lock_irq(&dev_priv->irq_lock);
3690 if (dev_priv->display_irqs_enabled)
3691 vlv_display_irq_postinstall(dev_priv);
3692 spin_unlock_irq(&dev_priv->irq_lock);
3694 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3695 POSTING_READ(VLV_MASTER_IER);
3700 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3702 /* These are interrupts we'll toggle with the ring mask register */
3703 uint32_t gt_interrupts[] = {
3704 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3705 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3706 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3707 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3708 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3709 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3710 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3711 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3713 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3714 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3717 if (HAS_L3_DPF(dev_priv))
3718 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3720 dev_priv->pm_irq_mask = 0xffffffff;
3721 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3722 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3724 * RPS interrupts will get enabled/disabled on demand when RPS itself
3725 * is enabled/disabled.
3727 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3728 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3731 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3733 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3734 uint32_t de_pipe_enables;
3735 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3736 u32 de_port_enables;
3737 u32 de_misc_masked = GEN8_DE_MISC_GSE;
3740 if (INTEL_INFO(dev_priv)->gen >= 9) {
3741 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3742 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3743 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3745 if (IS_BROXTON(dev_priv))
3746 de_port_masked |= BXT_DE_PORT_GMBUS;
3748 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3749 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3752 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3753 GEN8_PIPE_FIFO_UNDERRUN;
3755 de_port_enables = de_port_masked;
3756 if (IS_BROXTON(dev_priv))
3757 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3758 else if (IS_BROADWELL(dev_priv))
3759 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3761 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3762 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3763 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3765 for_each_pipe(dev_priv, pipe)
3766 if (intel_display_power_is_enabled(dev_priv,
3767 POWER_DOMAIN_PIPE(pipe)))
3768 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3769 dev_priv->de_irq_mask[pipe],
3772 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3773 GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3776 static int gen8_irq_postinstall(struct drm_device *dev)
3778 struct drm_i915_private *dev_priv = to_i915(dev);
3780 if (HAS_PCH_SPLIT(dev))
3781 ibx_irq_pre_postinstall(dev);
3783 gen8_gt_irq_postinstall(dev_priv);
3784 gen8_de_irq_postinstall(dev_priv);
3786 if (HAS_PCH_SPLIT(dev))
3787 ibx_irq_postinstall(dev);
3789 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3790 POSTING_READ(GEN8_MASTER_IRQ);
3795 static int cherryview_irq_postinstall(struct drm_device *dev)
3797 struct drm_i915_private *dev_priv = to_i915(dev);
3799 gen8_gt_irq_postinstall(dev_priv);
3801 spin_lock_irq(&dev_priv->irq_lock);
3802 if (dev_priv->display_irqs_enabled)
3803 vlv_display_irq_postinstall(dev_priv);
3804 spin_unlock_irq(&dev_priv->irq_lock);
3806 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3807 POSTING_READ(GEN8_MASTER_IRQ);
3812 static void gen8_irq_uninstall(struct drm_device *dev)
3814 struct drm_i915_private *dev_priv = to_i915(dev);
3819 gen8_irq_reset(dev);
3822 static void valleyview_irq_uninstall(struct drm_device *dev)
3824 struct drm_i915_private *dev_priv = to_i915(dev);
3829 I915_WRITE(VLV_MASTER_IER, 0);
3830 POSTING_READ(VLV_MASTER_IER);
3832 gen5_gt_irq_reset(dev);
3834 I915_WRITE(HWSTAM, 0xffffffff);
3836 spin_lock_irq(&dev_priv->irq_lock);
3837 if (dev_priv->display_irqs_enabled)
3838 vlv_display_irq_reset(dev_priv);
3839 spin_unlock_irq(&dev_priv->irq_lock);
3842 static void cherryview_irq_uninstall(struct drm_device *dev)
3844 struct drm_i915_private *dev_priv = to_i915(dev);
3849 I915_WRITE(GEN8_MASTER_IRQ, 0);
3850 POSTING_READ(GEN8_MASTER_IRQ);
3852 gen8_gt_irq_reset(dev_priv);
3854 GEN5_IRQ_RESET(GEN8_PCU_);
3856 spin_lock_irq(&dev_priv->irq_lock);
3857 if (dev_priv->display_irqs_enabled)
3858 vlv_display_irq_reset(dev_priv);
3859 spin_unlock_irq(&dev_priv->irq_lock);
3862 static void ironlake_irq_uninstall(struct drm_device *dev)
3864 struct drm_i915_private *dev_priv = to_i915(dev);
3869 ironlake_irq_reset(dev);
3872 static void i8xx_irq_preinstall(struct drm_device * dev)
3874 struct drm_i915_private *dev_priv = to_i915(dev);
3877 for_each_pipe(dev_priv, pipe)
3878 I915_WRITE(PIPESTAT(pipe), 0);
3879 I915_WRITE16(IMR, 0xffff);
3880 I915_WRITE16(IER, 0x0);
3881 POSTING_READ16(IER);
3884 static int i8xx_irq_postinstall(struct drm_device *dev)
3886 struct drm_i915_private *dev_priv = to_i915(dev);
3889 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3891 /* Unmask the interrupts that we always want on. */
3892 dev_priv->irq_mask =
3893 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3894 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3895 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3896 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3897 I915_WRITE16(IMR, dev_priv->irq_mask);
3900 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3901 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3902 I915_USER_INTERRUPT);
3903 POSTING_READ16(IER);
3905 /* Interrupt setup is already guaranteed to be single-threaded, this is
3906 * just to make the assert_spin_locked check happy. */
3907 spin_lock_irq(&dev_priv->irq_lock);
3908 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3909 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3910 spin_unlock_irq(&dev_priv->irq_lock);
3916 * Returns true when a page flip has completed.
3918 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3919 int plane, int pipe, u32 iir)
3921 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3923 if (!intel_pipe_handle_vblank(dev_priv, pipe))
3926 if ((iir & flip_pending) == 0)
3927 goto check_page_flip;
3929 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3930 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3931 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3932 * the flip is completed (no longer pending). Since this doesn't raise
3933 * an interrupt per se, we watch for the change at vblank.
3935 if (I915_READ16(ISR) & flip_pending)
3936 goto check_page_flip;
3938 intel_finish_page_flip_cs(dev_priv, pipe);
3942 intel_check_page_flip(dev_priv, pipe);
3946 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3948 struct drm_device *dev = arg;
3949 struct drm_i915_private *dev_priv = to_i915(dev);
3954 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3955 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3958 if (!intel_irqs_enabled(dev_priv))
3961 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3962 disable_rpm_wakeref_asserts(dev_priv);
3965 iir = I915_READ16(IIR);
3969 while (iir & ~flip_mask) {
3970 /* Can't rely on pipestat interrupt bit in iir as it might
3971 * have been cleared after the pipestat interrupt was received.
3972 * It doesn't set the bit in iir again, but it still produces
3973 * interrupts (for non-MSI).
3975 spin_lock(&dev_priv->irq_lock);
3976 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3977 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3979 for_each_pipe(dev_priv, pipe) {
3980 i915_reg_t reg = PIPESTAT(pipe);
3981 pipe_stats[pipe] = I915_READ(reg);
3984 * Clear the PIPE*STAT regs before the IIR
3986 if (pipe_stats[pipe] & 0x8000ffff)
3987 I915_WRITE(reg, pipe_stats[pipe]);
3989 spin_unlock(&dev_priv->irq_lock);
3991 I915_WRITE16(IIR, iir & ~flip_mask);
3992 new_iir = I915_READ16(IIR); /* Flush posted writes */
3994 if (iir & I915_USER_INTERRUPT)
3995 notify_ring(&dev_priv->engine[RCS]);
3997 for_each_pipe(dev_priv, pipe) {
3999 if (HAS_FBC(dev_priv))
4002 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4003 i8xx_handle_vblank(dev_priv, plane, pipe, iir))
4004 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4006 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4007 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4009 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4010 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4019 enable_rpm_wakeref_asserts(dev_priv);
4024 static void i8xx_irq_uninstall(struct drm_device * dev)
4026 struct drm_i915_private *dev_priv = to_i915(dev);
4029 for_each_pipe(dev_priv, pipe) {
4030 /* Clear enable bits; then clear status bits */
4031 I915_WRITE(PIPESTAT(pipe), 0);
4032 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4034 I915_WRITE16(IMR, 0xffff);
4035 I915_WRITE16(IER, 0x0);
4036 I915_WRITE16(IIR, I915_READ16(IIR));
4039 static void i915_irq_preinstall(struct drm_device * dev)
4041 struct drm_i915_private *dev_priv = to_i915(dev);
4044 if (I915_HAS_HOTPLUG(dev)) {
4045 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4046 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4049 I915_WRITE16(HWSTAM, 0xeffe);
4050 for_each_pipe(dev_priv, pipe)
4051 I915_WRITE(PIPESTAT(pipe), 0);
4052 I915_WRITE(IMR, 0xffffffff);
4053 I915_WRITE(IER, 0x0);
4057 static int i915_irq_postinstall(struct drm_device *dev)
4059 struct drm_i915_private *dev_priv = to_i915(dev);
4062 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4064 /* Unmask the interrupts that we always want on. */
4065 dev_priv->irq_mask =
4066 ~(I915_ASLE_INTERRUPT |
4067 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4068 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4069 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4070 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4073 I915_ASLE_INTERRUPT |
4074 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4075 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4076 I915_USER_INTERRUPT;
4078 if (I915_HAS_HOTPLUG(dev)) {
4079 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4080 POSTING_READ(PORT_HOTPLUG_EN);
4082 /* Enable in IER... */
4083 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4084 /* and unmask in IMR */
4085 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4088 I915_WRITE(IMR, dev_priv->irq_mask);
4089 I915_WRITE(IER, enable_mask);
4092 i915_enable_asle_pipestat(dev_priv);
4094 /* Interrupt setup is already guaranteed to be single-threaded, this is
4095 * just to make the assert_spin_locked check happy. */
4096 spin_lock_irq(&dev_priv->irq_lock);
4097 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4098 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4099 spin_unlock_irq(&dev_priv->irq_lock);
4105 * Returns true when a page flip has completed.
4107 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4108 int plane, int pipe, u32 iir)
4110 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4112 if (!intel_pipe_handle_vblank(dev_priv, pipe))
4115 if ((iir & flip_pending) == 0)
4116 goto check_page_flip;
4118 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4119 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4120 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4121 * the flip is completed (no longer pending). Since this doesn't raise
4122 * an interrupt per se, we watch for the change at vblank.
4124 if (I915_READ(ISR) & flip_pending)
4125 goto check_page_flip;
4127 intel_finish_page_flip_cs(dev_priv, pipe);
4131 intel_check_page_flip(dev_priv, pipe);
4135 static irqreturn_t i915_irq_handler(int irq, void *arg)
4137 struct drm_device *dev = arg;
4138 struct drm_i915_private *dev_priv = to_i915(dev);
4139 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4141 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4142 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4143 int pipe, ret = IRQ_NONE;
4145 if (!intel_irqs_enabled(dev_priv))
4148 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4149 disable_rpm_wakeref_asserts(dev_priv);
4151 iir = I915_READ(IIR);
4153 bool irq_received = (iir & ~flip_mask) != 0;
4154 bool blc_event = false;
4156 /* Can't rely on pipestat interrupt bit in iir as it might
4157 * have been cleared after the pipestat interrupt was received.
4158 * It doesn't set the bit in iir again, but it still produces
4159 * interrupts (for non-MSI).
4161 spin_lock(&dev_priv->irq_lock);
4162 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4163 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4165 for_each_pipe(dev_priv, pipe) {
4166 i915_reg_t reg = PIPESTAT(pipe);
4167 pipe_stats[pipe] = I915_READ(reg);
4169 /* Clear the PIPE*STAT regs before the IIR */
4170 if (pipe_stats[pipe] & 0x8000ffff) {
4171 I915_WRITE(reg, pipe_stats[pipe]);
4172 irq_received = true;
4175 spin_unlock(&dev_priv->irq_lock);
4180 /* Consume port. Then clear IIR or we'll miss events */
4181 if (I915_HAS_HOTPLUG(dev_priv) &&
4182 iir & I915_DISPLAY_PORT_INTERRUPT) {
4183 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4185 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4188 I915_WRITE(IIR, iir & ~flip_mask);
4189 new_iir = I915_READ(IIR); /* Flush posted writes */
4191 if (iir & I915_USER_INTERRUPT)
4192 notify_ring(&dev_priv->engine[RCS]);
4194 for_each_pipe(dev_priv, pipe) {
4196 if (HAS_FBC(dev_priv))
4199 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4200 i915_handle_vblank(dev_priv, plane, pipe, iir))
4201 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4203 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4206 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4207 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4209 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4210 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4214 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4215 intel_opregion_asle_intr(dev_priv);
4217 /* With MSI, interrupts are only generated when iir
4218 * transitions from zero to nonzero. If another bit got
4219 * set while we were handling the existing iir bits, then
4220 * we would never get another interrupt.
4222 * This is fine on non-MSI as well, as if we hit this path
4223 * we avoid exiting the interrupt handler only to generate
4226 * Note that for MSI this could cause a stray interrupt report
4227 * if an interrupt landed in the time between writing IIR and
4228 * the posting read. This should be rare enough to never
4229 * trigger the 99% of 100,000 interrupts test for disabling
4234 } while (iir & ~flip_mask);
4236 enable_rpm_wakeref_asserts(dev_priv);
4241 static void i915_irq_uninstall(struct drm_device * dev)
4243 struct drm_i915_private *dev_priv = to_i915(dev);
4246 if (I915_HAS_HOTPLUG(dev)) {
4247 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4248 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4251 I915_WRITE16(HWSTAM, 0xffff);
4252 for_each_pipe(dev_priv, pipe) {
4253 /* Clear enable bits; then clear status bits */
4254 I915_WRITE(PIPESTAT(pipe), 0);
4255 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4257 I915_WRITE(IMR, 0xffffffff);
4258 I915_WRITE(IER, 0x0);
4260 I915_WRITE(IIR, I915_READ(IIR));
4263 static void i965_irq_preinstall(struct drm_device * dev)
4265 struct drm_i915_private *dev_priv = to_i915(dev);
4268 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4269 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4271 I915_WRITE(HWSTAM, 0xeffe);
4272 for_each_pipe(dev_priv, pipe)
4273 I915_WRITE(PIPESTAT(pipe), 0);
4274 I915_WRITE(IMR, 0xffffffff);
4275 I915_WRITE(IER, 0x0);
4279 static int i965_irq_postinstall(struct drm_device *dev)
4281 struct drm_i915_private *dev_priv = to_i915(dev);
4285 /* Unmask the interrupts that we always want on. */
4286 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4287 I915_DISPLAY_PORT_INTERRUPT |
4288 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4289 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4290 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4291 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4292 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4294 enable_mask = ~dev_priv->irq_mask;
4295 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4296 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4297 enable_mask |= I915_USER_INTERRUPT;
4299 if (IS_G4X(dev_priv))
4300 enable_mask |= I915_BSD_USER_INTERRUPT;
4302 /* Interrupt setup is already guaranteed to be single-threaded, this is
4303 * just to make the assert_spin_locked check happy. */
4304 spin_lock_irq(&dev_priv->irq_lock);
4305 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4306 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4307 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4308 spin_unlock_irq(&dev_priv->irq_lock);
4311 * Enable some error detection, note the instruction error mask
4312 * bit is reserved, so we leave it masked.
4314 if (IS_G4X(dev_priv)) {
4315 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4316 GM45_ERROR_MEM_PRIV |
4317 GM45_ERROR_CP_PRIV |
4318 I915_ERROR_MEMORY_REFRESH);
4320 error_mask = ~(I915_ERROR_PAGE_TABLE |
4321 I915_ERROR_MEMORY_REFRESH);
4323 I915_WRITE(EMR, error_mask);
4325 I915_WRITE(IMR, dev_priv->irq_mask);
4326 I915_WRITE(IER, enable_mask);
4329 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4330 POSTING_READ(PORT_HOTPLUG_EN);
4332 i915_enable_asle_pipestat(dev_priv);
4337 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4341 assert_spin_locked(&dev_priv->irq_lock);
4343 /* Note HDMI and DP share hotplug bits */
4344 /* enable bits are the same for all generations */
4345 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4346 /* Programming the CRT detection parameters tends
4347 to generate a spurious hotplug event about three
4348 seconds later. So just do it once.
4350 if (IS_G4X(dev_priv))
4351 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4352 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4354 /* Ignore TV since it's buggy */
4355 i915_hotplug_interrupt_update_locked(dev_priv,
4356 HOTPLUG_INT_EN_MASK |
4357 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4358 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4362 static irqreturn_t i965_irq_handler(int irq, void *arg)
4364 struct drm_device *dev = arg;
4365 struct drm_i915_private *dev_priv = to_i915(dev);
4367 u32 pipe_stats[I915_MAX_PIPES];
4368 int ret = IRQ_NONE, pipe;
4370 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4371 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4373 if (!intel_irqs_enabled(dev_priv))
4376 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4377 disable_rpm_wakeref_asserts(dev_priv);
4379 iir = I915_READ(IIR);
4382 bool irq_received = (iir & ~flip_mask) != 0;
4383 bool blc_event = false;
4385 /* Can't rely on pipestat interrupt bit in iir as it might
4386 * have been cleared after the pipestat interrupt was received.
4387 * It doesn't set the bit in iir again, but it still produces
4388 * interrupts (for non-MSI).
4390 spin_lock(&dev_priv->irq_lock);
4391 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4392 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4394 for_each_pipe(dev_priv, pipe) {
4395 i915_reg_t reg = PIPESTAT(pipe);
4396 pipe_stats[pipe] = I915_READ(reg);
4399 * Clear the PIPE*STAT regs before the IIR
4401 if (pipe_stats[pipe] & 0x8000ffff) {
4402 I915_WRITE(reg, pipe_stats[pipe]);
4403 irq_received = true;
4406 spin_unlock(&dev_priv->irq_lock);
4413 /* Consume port. Then clear IIR or we'll miss events */
4414 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4415 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4417 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4420 I915_WRITE(IIR, iir & ~flip_mask);
4421 new_iir = I915_READ(IIR); /* Flush posted writes */
4423 if (iir & I915_USER_INTERRUPT)
4424 notify_ring(&dev_priv->engine[RCS]);
4425 if (iir & I915_BSD_USER_INTERRUPT)
4426 notify_ring(&dev_priv->engine[VCS]);
4428 for_each_pipe(dev_priv, pipe) {
4429 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4430 i915_handle_vblank(dev_priv, pipe, pipe, iir))
4431 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4433 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4436 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4437 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4439 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4440 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4443 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4444 intel_opregion_asle_intr(dev_priv);
4446 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4447 gmbus_irq_handler(dev_priv);
4449 /* With MSI, interrupts are only generated when iir
4450 * transitions from zero to nonzero. If another bit got
4451 * set while we were handling the existing iir bits, then
4452 * we would never get another interrupt.
4454 * This is fine on non-MSI as well, as if we hit this path
4455 * we avoid exiting the interrupt handler only to generate
4458 * Note that for MSI this could cause a stray interrupt report
4459 * if an interrupt landed in the time between writing IIR and
4460 * the posting read. This should be rare enough to never
4461 * trigger the 99% of 100,000 interrupts test for disabling
4467 enable_rpm_wakeref_asserts(dev_priv);
4472 static void i965_irq_uninstall(struct drm_device * dev)
4474 struct drm_i915_private *dev_priv = to_i915(dev);
4480 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4481 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4483 I915_WRITE(HWSTAM, 0xffffffff);
4484 for_each_pipe(dev_priv, pipe)
4485 I915_WRITE(PIPESTAT(pipe), 0);
4486 I915_WRITE(IMR, 0xffffffff);
4487 I915_WRITE(IER, 0x0);
4489 for_each_pipe(dev_priv, pipe)
4490 I915_WRITE(PIPESTAT(pipe),
4491 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4492 I915_WRITE(IIR, I915_READ(IIR));
4496 * intel_irq_init - initializes irq support
4497 * @dev_priv: i915 device instance
4499 * This function initializes all the irq support including work items, timers
4500 * and all the vtables. It does not setup the interrupt itself though.
4502 void intel_irq_init(struct drm_i915_private *dev_priv)
4504 struct drm_device *dev = &dev_priv->drm;
4506 intel_hpd_init_work(dev_priv);
4508 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4509 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4511 /* Let's track the enabled rps events */
4512 if (IS_VALLEYVIEW(dev_priv))
4513 /* WaGsvRC0ResidencyMethod:vlv */
4514 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4516 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4518 dev_priv->rps.pm_intr_keep = 0;
4521 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4522 * if GEN6_PM_UP_EI_EXPIRED is masked.
4524 * TODO: verify if this can be reproduced on VLV,CHV.
4526 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4527 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4529 if (INTEL_INFO(dev_priv)->gen >= 8)
4530 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
4532 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4533 i915_hangcheck_elapsed);
4535 if (IS_GEN2(dev_priv)) {
4536 /* Gen2 doesn't have a hardware frame counter */
4537 dev->max_vblank_count = 0;
4538 dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
4539 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4540 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4541 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4543 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4544 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4548 * Opt out of the vblank disable timer on everything except gen2.
4549 * Gen2 doesn't have a hardware frame counter and so depends on
4550 * vblank interrupts to produce sane vblank seuquence numbers.
4552 if (!IS_GEN2(dev_priv))
4553 dev->vblank_disable_immediate = true;
4555 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4556 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4558 if (IS_CHERRYVIEW(dev_priv)) {
4559 dev->driver->irq_handler = cherryview_irq_handler;
4560 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4561 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4562 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4563 dev->driver->enable_vblank = valleyview_enable_vblank;
4564 dev->driver->disable_vblank = valleyview_disable_vblank;
4565 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4566 } else if (IS_VALLEYVIEW(dev_priv)) {
4567 dev->driver->irq_handler = valleyview_irq_handler;
4568 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4569 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4570 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4571 dev->driver->enable_vblank = valleyview_enable_vblank;
4572 dev->driver->disable_vblank = valleyview_disable_vblank;
4573 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4574 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4575 dev->driver->irq_handler = gen8_irq_handler;
4576 dev->driver->irq_preinstall = gen8_irq_reset;
4577 dev->driver->irq_postinstall = gen8_irq_postinstall;
4578 dev->driver->irq_uninstall = gen8_irq_uninstall;
4579 dev->driver->enable_vblank = gen8_enable_vblank;
4580 dev->driver->disable_vblank = gen8_disable_vblank;
4581 if (IS_BROXTON(dev))
4582 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4583 else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
4584 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4586 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4587 } else if (HAS_PCH_SPLIT(dev)) {
4588 dev->driver->irq_handler = ironlake_irq_handler;
4589 dev->driver->irq_preinstall = ironlake_irq_reset;
4590 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4591 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4592 dev->driver->enable_vblank = ironlake_enable_vblank;
4593 dev->driver->disable_vblank = ironlake_disable_vblank;
4594 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4596 if (IS_GEN2(dev_priv)) {
4597 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4598 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4599 dev->driver->irq_handler = i8xx_irq_handler;
4600 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4601 } else if (IS_GEN3(dev_priv)) {
4602 dev->driver->irq_preinstall = i915_irq_preinstall;
4603 dev->driver->irq_postinstall = i915_irq_postinstall;
4604 dev->driver->irq_uninstall = i915_irq_uninstall;
4605 dev->driver->irq_handler = i915_irq_handler;
4607 dev->driver->irq_preinstall = i965_irq_preinstall;
4608 dev->driver->irq_postinstall = i965_irq_postinstall;
4609 dev->driver->irq_uninstall = i965_irq_uninstall;
4610 dev->driver->irq_handler = i965_irq_handler;
4612 if (I915_HAS_HOTPLUG(dev_priv))
4613 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4614 dev->driver->enable_vblank = i915_enable_vblank;
4615 dev->driver->disable_vblank = i915_disable_vblank;
4620 * intel_irq_install - enables the hardware interrupt
4621 * @dev_priv: i915 device instance
4623 * This function enables the hardware interrupt handling, but leaves the hotplug
4624 * handling still disabled. It is called after intel_irq_init().
4626 * In the driver load and resume code we need working interrupts in a few places
4627 * but don't want to deal with the hassle of concurrent probe and hotplug
4628 * workers. Hence the split into this two-stage approach.
4630 int intel_irq_install(struct drm_i915_private *dev_priv)
4633 * We enable some interrupt sources in our postinstall hooks, so mark
4634 * interrupts as enabled _before_ actually enabling them to avoid
4635 * special cases in our ordering checks.
4637 dev_priv->pm.irqs_enabled = true;
4639 return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4643 * intel_irq_uninstall - finilizes all irq handling
4644 * @dev_priv: i915 device instance
4646 * This stops interrupt and hotplug handling and unregisters and frees all
4647 * resources acquired in the init functions.
4649 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4651 drm_irq_uninstall(&dev_priv->drm);
4652 intel_hpd_cancel_work(dev_priv);
4653 dev_priv->pm.irqs_enabled = false;
4657 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4658 * @dev_priv: i915 device instance
4660 * This function is used to disable interrupts at runtime, both in the runtime
4661 * pm and the system suspend/resume code.
4663 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4665 dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4666 dev_priv->pm.irqs_enabled = false;
4667 synchronize_irq(dev_priv->drm.irq);
4671 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4672 * @dev_priv: i915 device instance
4674 * This function is used to enable interrupts at runtime, both in the runtime
4675 * pm and the system suspend/resume code.
4677 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4679 dev_priv->pm.irqs_enabled = true;
4680 dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4681 dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);