drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 static void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (INTEL_INFO(dev)->gen >= 4)
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low;
 206
 207         if (!i915_pipe_enabled(dev, pipe)) {
 208                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 209                                 "pipe %d\n", pipe);
 210                 return 0;
 211         }
 212
 213         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 214         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 223                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 224                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 225         } while (high1 != high2);
 226
 227         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 228         low >>= PIPE_FRAME_LOW_SHIFT;
 229         return (high1 << 8) | low;
 230 }
 231
 232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 233 {
 234         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 235         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 236
 237         if (!i915_pipe_enabled(dev, pipe)) {
 238                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 239                                         "pipe %d\n", pipe);
 240                 return 0;
 241         }
 242
 243         return I915_READ(reg);
 244 }
 245
 246 /*
 247  * Handle hotplug events outside the interrupt handler proper.
 248  */
 249 static void i915_hotplug_work_func(struct work_struct *work)
 250 {
 251         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 252                                                     hotplug_work);
 253         struct drm_device *dev = dev_priv->dev;
 254         struct drm_mode_config *mode_config = &dev->mode_config;
 255         struct intel_encoder *encoder;
 256
 257         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 258                 if (encoder->hot_plug)
 259                         encoder->hot_plug(encoder);
 260
 261         /* Just fire off a uevent and let userspace tell us what to do */
 262         drm_helper_hpd_irq_event(dev);
 263 }
 264
 265 static void i915_handle_rps_change(struct drm_device *dev)
 266 {
 267         drm_i915_private_t *dev_priv = dev->dev_private;
 268         u32 busy_up, busy_down, max_avg, min_avg;
 269         u8 new_delay = dev_priv->cur_delay;
 270
 271         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 272         busy_up = I915_READ(RCPREVBSYTUPAVG);
 273         busy_down = I915_READ(RCPREVBSYTDNAVG);
 274         max_avg = I915_READ(RCBMAXAVG);
 275         min_avg = I915_READ(RCBMINAVG);
 276
 277         /* Handle RCS change request from hw */
 278         if (busy_up > max_avg) {
 279                 if (dev_priv->cur_delay != dev_priv->max_delay)
 280                         new_delay = dev_priv->cur_delay - 1;
 281                 if (new_delay < dev_priv->max_delay)
 282                         new_delay = dev_priv->max_delay;
 283         } else if (busy_down < min_avg) {
 284                 if (dev_priv->cur_delay != dev_priv->min_delay)
 285                         new_delay = dev_priv->cur_delay + 1;
 286                 if (new_delay > dev_priv->min_delay)
 287                         new_delay = dev_priv->min_delay;
 288         }
 289
 290         if (ironlake_set_drps(dev, new_delay))
 291                 dev_priv->cur_delay = new_delay;
 292
 293         return;
 294 }
 295
 296 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 297 {
 298         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 299         int ret = IRQ_NONE;
 300         u32 de_iir, gt_iir, de_ier, pch_iir;
 301         u32 hotplug_mask;
 302         struct drm_i915_master_private *master_priv;
 303         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 304         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 305
 306         if (IS_GEN6(dev))
 307                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 308
 309         /* disable master interrupt before clearing iir  */
 310         de_ier = I915_READ(DEIER);
 311         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 312         (void)I915_READ(DEIER);
 313
 314         de_iir = I915_READ(DEIIR);
 315         gt_iir = I915_READ(GTIIR);
 316         pch_iir = I915_READ(SDEIIR);
 317
 318         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 319                 goto done;
 320
 321         if (HAS_PCH_CPT(dev))
 322                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 323         else
 324                 hotplug_mask = SDE_HOTPLUG_MASK;
 325
 326         ret = IRQ_HANDLED;
 327
 328         if (dev->primary->master) {
 329                 master_priv = dev->primary->master->driver_priv;
 330                 if (master_priv->sarea_priv)
 331                         master_priv->sarea_priv->last_dispatch =
 332                                 READ_BREADCRUMB(dev_priv);
 333         }
 334
 335         if (gt_iir & GT_PIPE_NOTIFY) {
 336                 u32 seqno = render_ring->get_seqno(dev, render_ring);
 337                 render_ring->irq_gem_seqno = seqno;
 338                 trace_i915_gem_request_complete(dev, seqno);
 339                 wake_up_all(&dev_priv->render_ring.irq_queue);
 340                 dev_priv->hangcheck_count = 0;
 341                 mod_timer(&dev_priv->hangcheck_timer,
 342                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 343         }
 344         if (gt_iir & bsd_usr_interrupt)
 345                 wake_up_all(&dev_priv->bsd_ring.irq_queue);
 346
 347         if (de_iir & DE_GSE)
 348                 intel_opregion_gse_intr(dev);
 349
 350         if (de_iir & DE_PLANEA_FLIP_DONE) {
 351                 intel_prepare_page_flip(dev, 0);
 352                 intel_finish_page_flip_plane(dev, 0);
 353         }
 354
 355         if (de_iir & DE_PLANEB_FLIP_DONE) {
 356                 intel_prepare_page_flip(dev, 1);
 357                 intel_finish_page_flip_plane(dev, 1);
 358         }
 359
 360         if (de_iir & DE_PIPEA_VBLANK)
 361                 drm_handle_vblank(dev, 0);
 362
 363         if (de_iir & DE_PIPEB_VBLANK)
 364                 drm_handle_vblank(dev, 1);
 365
 366         /* check event from PCH */
 367         if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
 368                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 369
 370         if (de_iir & DE_PCU_EVENT) {
 371                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 372                 i915_handle_rps_change(dev);
 373         }
 374
 375         /* should clear PCH hotplug event before clear CPU irq */
 376         I915_WRITE(SDEIIR, pch_iir);
 377         I915_WRITE(GTIIR, gt_iir);
 378         I915_WRITE(DEIIR, de_iir);
 379
 380 done:
 381         I915_WRITE(DEIER, de_ier);
 382         (void)I915_READ(DEIER);
 383
 384         return ret;
 385 }
 386
 387 /**
 388  * i915_error_work_func - do process context error handling work
 389  * @work: work struct
 390  *
 391  * Fire an error uevent so userspace can see that a hang or error
 392  * was detected.
 393  */
 394 static void i915_error_work_func(struct work_struct *work)
 395 {
 396         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 397                                                     error_work);
 398         struct drm_device *dev = dev_priv->dev;
 399         char *error_event[] = { "ERROR=1", NULL };
 400         char *reset_event[] = { "RESET=1", NULL };
 401         char *reset_done_event[] = { "ERROR=0", NULL };
 402
 403         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 404
 405         if (atomic_read(&dev_priv->mm.wedged)) {
 406                 DRM_DEBUG_DRIVER("resetting chip\n");
 407                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 408                 if (!i915_reset(dev, GRDOM_RENDER)) {
 409                         atomic_set(&dev_priv->mm.wedged, 0);
 410                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 411                 }
 412                 complete_all(&dev_priv->error_completion);
 413         }
 414 }
 415
 416 #ifdef CONFIG_DEBUG_FS
 417 static struct drm_i915_error_object *
 418 i915_error_object_create(struct drm_device *dev,
 419                          struct drm_gem_object *src)
 420 {
 421         drm_i915_private_t *dev_priv = dev->dev_private;
 422         struct drm_i915_error_object *dst;
 423         struct drm_i915_gem_object *src_priv;
 424         int page, page_count;
 425         u32 reloc_offset;
 426
 427         if (src == NULL)
 428                 return NULL;
 429
 430         src_priv = to_intel_bo(src);
 431         if (src_priv->pages == NULL)
 432                 return NULL;
 433
 434         page_count = src->size / PAGE_SIZE;
 435
 436         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 437         if (dst == NULL)
 438                 return NULL;
 439
 440         reloc_offset = src_priv->gtt_offset;
 441         for (page = 0; page < page_count; page++) {
 442                 unsigned long flags;
 443                 void __iomem *s;
 444                 void *d;
 445
 446                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 447                 if (d == NULL)
 448                         goto unwind;
 449
 450                 local_irq_save(flags);
 451                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 452                                              reloc_offset,
 453                                              KM_IRQ0);
 454                 memcpy_fromio(d, s, PAGE_SIZE);
 455                 io_mapping_unmap_atomic(s, KM_IRQ0);
 456                 local_irq_restore(flags);
 457
 458                 dst->pages[page] = d;
 459
 460                 reloc_offset += PAGE_SIZE;
 461         }
 462         dst->page_count = page_count;
 463         dst->gtt_offset = src_priv->gtt_offset;
 464
 465         return dst;
 466
 467 unwind:
 468         while (page--)
 469                 kfree(dst->pages[page]);
 470         kfree(dst);
 471         return NULL;
 472 }
 473
 474 static void
 475 i915_error_object_free(struct drm_i915_error_object *obj)
 476 {
 477         int page;
 478
 479         if (obj == NULL)
 480                 return;
 481
 482         for (page = 0; page < obj->page_count; page++)
 483                 kfree(obj->pages[page]);
 484
 485         kfree(obj);
 486 }
 487
 488 static void
 489 i915_error_state_free(struct drm_device *dev,
 490                       struct drm_i915_error_state *error)
 491 {
 492         i915_error_object_free(error->batchbuffer[0]);
 493         i915_error_object_free(error->batchbuffer[1]);
 494         i915_error_object_free(error->ringbuffer);
 495         kfree(error->active_bo);
 496         kfree(error->overlay);
 497         kfree(error);
 498 }
 499
 500 static u32
 501 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 502 {
 503         u32 cmd;
 504
 505         if (IS_I830(dev) || IS_845G(dev))
 506                 cmd = MI_BATCH_BUFFER;
 507         else if (INTEL_INFO(dev)->gen >= 4)
 508                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 509                        MI_BATCH_NON_SECURE_I965);
 510         else
 511                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 512
 513         return ring[0] == cmd ? ring[1] : 0;
 514 }
 515
 516 static u32
 517 i915_ringbuffer_last_batch(struct drm_device *dev)
 518 {
 519         struct drm_i915_private *dev_priv = dev->dev_private;
 520         u32 head, bbaddr;
 521         u32 *ring;
 522
 523         /* Locate the current position in the ringbuffer and walk back
 524          * to find the most recently dispatched batch buffer.
 525          */
 526         bbaddr = 0;
 527         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 528         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 529
 530         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 531                 bbaddr = i915_get_bbaddr(dev, ring);
 532                 if (bbaddr)
 533                         break;
 534         }
 535
 536         if (bbaddr == 0) {
 537                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 538                                 + dev_priv->render_ring.size);
 539                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 540                         bbaddr = i915_get_bbaddr(dev, ring);
 541                         if (bbaddr)
 542                                 break;
 543                 }
 544         }
 545
 546         return bbaddr;
 547 }
 548
 549 /**
 550  * i915_capture_error_state - capture an error record for later analysis
 551  * @dev: drm device
 552  *
 553  * Should be called when an error is detected (either a hang or an error
 554  * interrupt) to capture error state from the time of the error.  Fills
 555  * out a structure which becomes available in debugfs for user level tools
 556  * to pick up.
 557  */
 558 static void i915_capture_error_state(struct drm_device *dev)
 559 {
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561         struct drm_i915_gem_object *obj_priv;
 562         struct drm_i915_error_state *error;
 563         struct drm_gem_object *batchbuffer[2];
 564         unsigned long flags;
 565         u32 bbaddr;
 566         int count;
 567
 568         spin_lock_irqsave(&dev_priv->error_lock, flags);
 569         error = dev_priv->first_error;
 570         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 571         if (error)
 572                 return;
 573
 574         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 575         if (!error) {
 576                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 577                 return;
 578         }
 579
 580         DRM_DEBUG_DRIVER("generating error event\n");
 581
 582         error->seqno =
 583                 dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring);
 584         error->eir = I915_READ(EIR);
 585         error->pgtbl_er = I915_READ(PGTBL_ER);
 586         error->pipeastat = I915_READ(PIPEASTAT);
 587         error->pipebstat = I915_READ(PIPEBSTAT);
 588         error->instpm = I915_READ(INSTPM);
 589         if (INTEL_INFO(dev)->gen < 4) {
 590                 error->ipeir = I915_READ(IPEIR);
 591                 error->ipehr = I915_READ(IPEHR);
 592                 error->instdone = I915_READ(INSTDONE);
 593                 error->acthd = I915_READ(ACTHD);
 594                 error->bbaddr = 0;
 595         } else {
 596                 error->ipeir = I915_READ(IPEIR_I965);
 597                 error->ipehr = I915_READ(IPEHR_I965);
 598                 error->instdone = I915_READ(INSTDONE_I965);
 599                 error->instps = I915_READ(INSTPS);
 600                 error->instdone1 = I915_READ(INSTDONE1);
 601                 error->acthd = I915_READ(ACTHD_I965);
 602                 error->bbaddr = I915_READ64(BB_ADDR);
 603         }
 604
 605         bbaddr = i915_ringbuffer_last_batch(dev);
 606
 607         /* Grab the current batchbuffer, most likely to have crashed. */
 608         batchbuffer[0] = NULL;
 609         batchbuffer[1] = NULL;
 610         count = 0;
 611         list_for_each_entry(obj_priv,
 612                         &dev_priv->render_ring.active_list, list) {
 613
 614                 struct drm_gem_object *obj = &obj_priv->base;
 615
 616                 if (batchbuffer[0] == NULL &&
 617                     bbaddr >= obj_priv->gtt_offset &&
 618                     bbaddr < obj_priv->gtt_offset + obj->size)
 619                         batchbuffer[0] = obj;
 620
 621                 if (batchbuffer[1] == NULL &&
 622                     error->acthd >= obj_priv->gtt_offset &&
 623                     error->acthd < obj_priv->gtt_offset + obj->size)
 624                         batchbuffer[1] = obj;
 625
 626                 count++;
 627         }
 628         /* Scan the other lists for completeness for those bizarre errors. */
 629         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 630                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
 631                         struct drm_gem_object *obj = &obj_priv->base;
 632
 633                         if (batchbuffer[0] == NULL &&
 634                             bbaddr >= obj_priv->gtt_offset &&
 635                             bbaddr < obj_priv->gtt_offset + obj->size)
 636                                 batchbuffer[0] = obj;
 637
 638                         if (batchbuffer[1] == NULL &&
 639                             error->acthd >= obj_priv->gtt_offset &&
 640                             error->acthd < obj_priv->gtt_offset + obj->size)
 641                                 batchbuffer[1] = obj;
 642
 643                         if (batchbuffer[0] && batchbuffer[1])
 644                                 break;
 645                 }
 646         }
 647         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 648                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 649                         struct drm_gem_object *obj = &obj_priv->base;
 650
 651                         if (batchbuffer[0] == NULL &&
 652                             bbaddr >= obj_priv->gtt_offset &&
 653                             bbaddr < obj_priv->gtt_offset + obj->size)
 654                                 batchbuffer[0] = obj;
 655
 656                         if (batchbuffer[1] == NULL &&
 657                             error->acthd >= obj_priv->gtt_offset &&
 658                             error->acthd < obj_priv->gtt_offset + obj->size)
 659                                 batchbuffer[1] = obj;
 660
 661                         if (batchbuffer[0] && batchbuffer[1])
 662                                 break;
 663                 }
 664         }
 665
 666         /* We need to copy these to an anonymous buffer as the simplest
 667          * method to avoid being overwritten by userpace.
 668          */
 669         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 670         if (batchbuffer[1] != batchbuffer[0])
 671                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 672         else
 673                 error->batchbuffer[1] = NULL;
 674
 675         /* Record the ringbuffer */
 676         error->ringbuffer = i915_error_object_create(dev,
 677                         dev_priv->render_ring.gem_object);
 678
 679         /* Record buffers on the active list. */
 680         error->active_bo = NULL;
 681         error->active_bo_count = 0;
 682
 683         if (count)
 684                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 685                                            GFP_ATOMIC);
 686
 687         if (error->active_bo) {
 688                 int i = 0;
 689                 list_for_each_entry(obj_priv,
 690                                 &dev_priv->render_ring.active_list, list) {
 691                         struct drm_gem_object *obj = &obj_priv->base;
 692
 693                         error->active_bo[i].size = obj->size;
 694                         error->active_bo[i].name = obj->name;
 695                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 696                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 697                         error->active_bo[i].read_domains = obj->read_domains;
 698                         error->active_bo[i].write_domain = obj->write_domain;
 699                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 700                         error->active_bo[i].pinned = 0;
 701                         if (obj_priv->pin_count > 0)
 702                                 error->active_bo[i].pinned = 1;
 703                         if (obj_priv->user_pin_count > 0)
 704                                 error->active_bo[i].pinned = -1;
 705                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 706                         error->active_bo[i].dirty = obj_priv->dirty;
 707                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 708
 709                         if (++i == count)
 710                                 break;
 711                 }
 712                 error->active_bo_count = i;
 713         }
 714
 715         do_gettimeofday(&error->time);
 716
 717         error->overlay = intel_overlay_capture_error_state(dev);
 718
 719         spin_lock_irqsave(&dev_priv->error_lock, flags);
 720         if (dev_priv->first_error == NULL) {
 721                 dev_priv->first_error = error;
 722                 error = NULL;
 723         }
 724         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 725
 726         if (error)
 727                 i915_error_state_free(dev, error);
 728 }
 729
 730 void i915_destroy_error_state(struct drm_device *dev)
 731 {
 732         struct drm_i915_private *dev_priv = dev->dev_private;
 733         struct drm_i915_error_state *error;
 734
 735         spin_lock(&dev_priv->error_lock);
 736         error = dev_priv->first_error;
 737         dev_priv->first_error = NULL;
 738         spin_unlock(&dev_priv->error_lock);
 739
 740         if (error)
 741                 i915_error_state_free(dev, error);
 742 }
 743 #else
 744 #define i915_capture_error_state(x)
 745 #endif
 746
 747 static void i915_report_and_clear_eir(struct drm_device *dev)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750         u32 eir = I915_READ(EIR);
 751
 752         if (!eir)
 753                 return;
 754
 755         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 756                eir);
 757
 758         if (IS_G4X(dev)) {
 759                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 760                         u32 ipeir = I915_READ(IPEIR_I965);
 761
 762                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 763                                I915_READ(IPEIR_I965));
 764                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 765                                I915_READ(IPEHR_I965));
 766                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 767                                I915_READ(INSTDONE_I965));
 768                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 769                                I915_READ(INSTPS));
 770                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 771                                I915_READ(INSTDONE1));
 772                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 773                                I915_READ(ACTHD_I965));
 774                         I915_WRITE(IPEIR_I965, ipeir);
 775                         (void)I915_READ(IPEIR_I965);
 776                 }
 777                 if (eir & GM45_ERROR_PAGE_TABLE) {
 778                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 779                         printk(KERN_ERR "page table error\n");
 780                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 781                                pgtbl_err);
 782                         I915_WRITE(PGTBL_ER, pgtbl_err);
 783                         (void)I915_READ(PGTBL_ER);
 784                 }
 785         }
 786
 787         if (!IS_GEN2(dev)) {
 788                 if (eir & I915_ERROR_PAGE_TABLE) {
 789                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 790                         printk(KERN_ERR "page table error\n");
 791                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 792                                pgtbl_err);
 793                         I915_WRITE(PGTBL_ER, pgtbl_err);
 794                         (void)I915_READ(PGTBL_ER);
 795                 }
 796         }
 797
 798         if (eir & I915_ERROR_MEMORY_REFRESH) {
 799                 u32 pipea_stats = I915_READ(PIPEASTAT);
 800                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 801
 802                 printk(KERN_ERR "memory refresh error\n");
 803                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 804                        pipea_stats);
 805                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 806                        pipeb_stats);
 807                 /* pipestat has already been acked */
 808         }
 809         if (eir & I915_ERROR_INSTRUCTION) {
 810                 printk(KERN_ERR "instruction error\n");
 811                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 812                        I915_READ(INSTPM));
 813                 if (INTEL_INFO(dev)->gen < 4) {
 814                         u32 ipeir = I915_READ(IPEIR);
 815
 816                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 817                                I915_READ(IPEIR));
 818                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 819                                I915_READ(IPEHR));
 820                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 821                                I915_READ(INSTDONE));
 822                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 823                                I915_READ(ACTHD));
 824                         I915_WRITE(IPEIR, ipeir);
 825                         (void)I915_READ(IPEIR);
 826                 } else {
 827                         u32 ipeir = I915_READ(IPEIR_I965);
 828
 829                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 830                                I915_READ(IPEIR_I965));
 831                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 832                                I915_READ(IPEHR_I965));
 833                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 834                                I915_READ(INSTDONE_I965));
 835                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 836                                I915_READ(INSTPS));
 837                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 838                                I915_READ(INSTDONE1));
 839                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 840                                I915_READ(ACTHD_I965));
 841                         I915_WRITE(IPEIR_I965, ipeir);
 842                         (void)I915_READ(IPEIR_I965);
 843                 }
 844         }
 845
 846         I915_WRITE(EIR, eir);
 847         (void)I915_READ(EIR);
 848         eir = I915_READ(EIR);
 849         if (eir) {
 850                 /*
 851                  * some errors might have become stuck,
 852                  * mask them.
 853                  */
 854                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 855                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 856                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 857         }
 858 }
 859
 860 /**
 861  * i915_handle_error - handle an error interrupt
 862  * @dev: drm device
 863  *
 864  * Do some basic checking of regsiter state at error interrupt time and
 865  * dump it to the syslog.  Also call i915_capture_error_state() to make
 866  * sure we get a record and make it available in debugfs.  Fire a uevent
 867  * so userspace knows something bad happened (should trigger collection
 868  * of a ring dump etc.).
 869  */
 870 static void i915_handle_error(struct drm_device *dev, bool wedged)
 871 {
 872         struct drm_i915_private *dev_priv = dev->dev_private;
 873
 874         i915_capture_error_state(dev);
 875         i915_report_and_clear_eir(dev);
 876
 877         if (wedged) {
 878                 INIT_COMPLETION(dev_priv->error_completion);
 879                 atomic_set(&dev_priv->mm.wedged, 1);
 880
 881                 /*
 882                  * Wakeup waiting processes so they don't hang
 883                  */
 884                 wake_up_all(&dev_priv->render_ring.irq_queue);
 885                 if (HAS_BSD(dev))
 886                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
 887         }
 888
 889         queue_work(dev_priv->wq, &dev_priv->error_work);
 890 }
 891
 892 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 893 {
 894         drm_i915_private_t *dev_priv = dev->dev_private;
 895         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 897         struct drm_i915_gem_object *obj_priv;
 898         struct intel_unpin_work *work;
 899         unsigned long flags;
 900         bool stall_detected;
 901
 902         /* Ignore early vblank irqs */
 903         if (intel_crtc == NULL)
 904                 return;
 905
 906         spin_lock_irqsave(&dev->event_lock, flags);
 907         work = intel_crtc->unpin_work;
 908
 909         if (work == NULL || work->pending || !work->enable_stall_check) {
 910                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 911                 spin_unlock_irqrestore(&dev->event_lock, flags);
 912                 return;
 913         }
 914
 915         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 916         obj_priv = to_intel_bo(work->pending_flip_obj);
 917         if (INTEL_INFO(dev)->gen >= 4) {
 918                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 919                 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
 920         } else {
 921                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 922                 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
 923                                                         crtc->y * crtc->fb->pitch +
 924                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 925         }
 926
 927         spin_unlock_irqrestore(&dev->event_lock, flags);
 928
 929         if (stall_detected) {
 930                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 931                 intel_prepare_page_flip(dev, intel_crtc->plane);
 932         }
 933 }
 934
 935 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 936 {
 937         struct drm_device *dev = (struct drm_device *) arg;
 938         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 939         struct drm_i915_master_private *master_priv;
 940         u32 iir, new_iir;
 941         u32 pipea_stats, pipeb_stats;
 942         u32 vblank_status;
 943         int vblank = 0;
 944         unsigned long irqflags;
 945         int irq_received;
 946         int ret = IRQ_NONE;
 947         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 948
 949         atomic_inc(&dev_priv->irq_received);
 950
 951         if (HAS_PCH_SPLIT(dev))
 952                 return ironlake_irq_handler(dev);
 953
 954         iir = I915_READ(IIR);
 955
 956         if (INTEL_INFO(dev)->gen >= 4)
 957                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 958         else
 959                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 960
 961         for (;;) {
 962                 irq_received = iir != 0;
 963
 964                 /* Can't rely on pipestat interrupt bit in iir as it might
 965                  * have been cleared after the pipestat interrupt was received.
 966                  * It doesn't set the bit in iir again, but it still produces
 967                  * interrupts (for non-MSI).
 968                  */
 969                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 970                 pipea_stats = I915_READ(PIPEASTAT);
 971                 pipeb_stats = I915_READ(PIPEBSTAT);
 972
 973                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 974                         i915_handle_error(dev, false);
 975
 976                 /*
 977                  * Clear the PIPE(A|B)STAT regs before the IIR
 978                  */
 979                 if (pipea_stats & 0x8000ffff) {
 980                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 981                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 982                         I915_WRITE(PIPEASTAT, pipea_stats);
 983                         irq_received = 1;
 984                 }
 985
 986                 if (pipeb_stats & 0x8000ffff) {
 987                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 988                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 989                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 990                         irq_received = 1;
 991                 }
 992                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 993
 994                 if (!irq_received)
 995                         break;
 996
 997                 ret = IRQ_HANDLED;
 998
 999                 /* Consume port.  Then clear IIR or we'll miss events */
1000                 if ((I915_HAS_HOTPLUG(dev)) &&
1001                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1002                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1003
1004                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1005                                   hotplug_status);
1006                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1007                                 queue_work(dev_priv->wq,
1008                                            &dev_priv->hotplug_work);
1009
1010                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1011                         I915_READ(PORT_HOTPLUG_STAT);
1012                 }
1013
1014                 I915_WRITE(IIR, iir);
1015                 new_iir = I915_READ(IIR); /* Flush posted writes */
1016
1017                 if (dev->primary->master) {
1018                         master_priv = dev->primary->master->driver_priv;
1019                         if (master_priv->sarea_priv)
1020                                 master_priv->sarea_priv->last_dispatch =
1021                                         READ_BREADCRUMB(dev_priv);
1022                 }
1023
1024                 if (iir & I915_USER_INTERRUPT) {
1025                         u32 seqno = render_ring->get_seqno(dev, render_ring);
1026                         render_ring->irq_gem_seqno = seqno;
1027                         trace_i915_gem_request_complete(dev, seqno);
1028                         wake_up_all(&dev_priv->render_ring.irq_queue);
1029                         dev_priv->hangcheck_count = 0;
1030                         mod_timer(&dev_priv->hangcheck_timer,
1031                                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1032                 }
1033
1034                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1035                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
1036
1037                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1038                         intel_prepare_page_flip(dev, 0);
1039                         if (dev_priv->flip_pending_is_done)
1040                                 intel_finish_page_flip_plane(dev, 0);
1041                 }
1042
1043                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1044                         intel_prepare_page_flip(dev, 1);
1045                         if (dev_priv->flip_pending_is_done)
1046                                 intel_finish_page_flip_plane(dev, 1);
1047                 }
1048
1049                 if (pipea_stats & vblank_status) {
1050                         vblank++;
1051                         drm_handle_vblank(dev, 0);
1052                         if (!dev_priv->flip_pending_is_done) {
1053                                 i915_pageflip_stall_check(dev, 0);
1054                                 intel_finish_page_flip(dev, 0);
1055                         }
1056                 }
1057
1058                 if (pipeb_stats & vblank_status) {
1059                         vblank++;
1060                         drm_handle_vblank(dev, 1);
1061                         if (!dev_priv->flip_pending_is_done) {
1062                                 i915_pageflip_stall_check(dev, 1);
1063                                 intel_finish_page_flip(dev, 1);
1064                         }
1065                 }
1066
1067                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1068                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1069                     (iir & I915_ASLE_INTERRUPT))
1070                         intel_opregion_asle_intr(dev);
1071
1072                 /* With MSI, interrupts are only generated when iir
1073                  * transitions from zero to nonzero.  If another bit got
1074                  * set while we were handling the existing iir bits, then
1075                  * we would never get another interrupt.
1076                  *
1077                  * This is fine on non-MSI as well, as if we hit this path
1078                  * we avoid exiting the interrupt handler only to generate
1079                  * another one.
1080                  *
1081                  * Note that for MSI this could cause a stray interrupt report
1082                  * if an interrupt landed in the time between writing IIR and
1083                  * the posting read.  This should be rare enough to never
1084                  * trigger the 99% of 100,000 interrupts test for disabling
1085                  * stray interrupts.
1086                  */
1087                 iir = new_iir;
1088         }
1089
1090         return ret;
1091 }
1092
1093 static int i915_emit_irq(struct drm_device * dev)
1094 {
1095         drm_i915_private_t *dev_priv = dev->dev_private;
1096         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1097
1098         i915_kernel_lost_context(dev);
1099
1100         DRM_DEBUG_DRIVER("\n");
1101
1102         dev_priv->counter++;
1103         if (dev_priv->counter > 0x7FFFFFFFUL)
1104                 dev_priv->counter = 1;
1105         if (master_priv->sarea_priv)
1106                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1107
1108         BEGIN_LP_RING(4);
1109         OUT_RING(MI_STORE_DWORD_INDEX);
1110         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1111         OUT_RING(dev_priv->counter);
1112         OUT_RING(MI_USER_INTERRUPT);
1113         ADVANCE_LP_RING();
1114
1115         return dev_priv->counter;
1116 }
1117
1118 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1119 {
1120         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1121         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1122
1123         if (dev_priv->trace_irq_seqno == 0)
1124                 render_ring->user_irq_get(dev, render_ring);
1125
1126         dev_priv->trace_irq_seqno = seqno;
1127 }
1128
1129 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1130 {
1131         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1132         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1133         int ret = 0;
1134         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1135
1136         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1137                   READ_BREADCRUMB(dev_priv));
1138
1139         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1140                 if (master_priv->sarea_priv)
1141                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1142                 return 0;
1143         }
1144
1145         if (master_priv->sarea_priv)
1146                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1147
1148         render_ring->user_irq_get(dev, render_ring);
1149         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1150                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1151         render_ring->user_irq_put(dev, render_ring);
1152
1153         if (ret == -EBUSY) {
1154                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1155                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1156         }
1157
1158         return ret;
1159 }
1160
1161 /* Needs the lock as it touches the ring.
1162  */
1163 int i915_irq_emit(struct drm_device *dev, void *data,
1164                          struct drm_file *file_priv)
1165 {
1166         drm_i915_private_t *dev_priv = dev->dev_private;
1167         drm_i915_irq_emit_t *emit = data;
1168         int result;
1169
1170         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1171                 DRM_ERROR("called with no initialization\n");
1172                 return -EINVAL;
1173         }
1174
1175         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1176
1177         mutex_lock(&dev->struct_mutex);
1178         result = i915_emit_irq(dev);
1179         mutex_unlock(&dev->struct_mutex);
1180
1181         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1182                 DRM_ERROR("copy_to_user\n");
1183                 return -EFAULT;
1184         }
1185
1186         return 0;
1187 }
1188
1189 /* Doesn't need the hardware lock.
1190  */
1191 int i915_irq_wait(struct drm_device *dev, void *data,
1192                          struct drm_file *file_priv)
1193 {
1194         drm_i915_private_t *dev_priv = dev->dev_private;
1195         drm_i915_irq_wait_t *irqwait = data;
1196
1197         if (!dev_priv) {
1198                 DRM_ERROR("called with no initialization\n");
1199                 return -EINVAL;
1200         }
1201
1202         return i915_wait_irq(dev, irqwait->irq_seq);
1203 }
1204
1205 /* Called from drm generic code, passed 'crtc' which
1206  * we use as a pipe index
1207  */
1208 int i915_enable_vblank(struct drm_device *dev, int pipe)
1209 {
1210         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1211         unsigned long irqflags;
1212
1213         if (!i915_pipe_enabled(dev, pipe))
1214                 return -EINVAL;
1215
1216         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1217         if (HAS_PCH_SPLIT(dev))
1218                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1219                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1220         else if (INTEL_INFO(dev)->gen >= 4)
1221                 i915_enable_pipestat(dev_priv, pipe,
1222                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1223         else
1224                 i915_enable_pipestat(dev_priv, pipe,
1225                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1226         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1227         return 0;
1228 }
1229
1230 /* Called from drm generic code, passed 'crtc' which
1231  * we use as a pipe index
1232  */
1233 void i915_disable_vblank(struct drm_device *dev, int pipe)
1234 {
1235         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1236         unsigned long irqflags;
1237
1238         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1239         if (HAS_PCH_SPLIT(dev))
1240                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1241                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1242         else
1243                 i915_disable_pipestat(dev_priv, pipe,
1244                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1245                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1246         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1247 }
1248
1249 void i915_enable_interrupt (struct drm_device *dev)
1250 {
1251         struct drm_i915_private *dev_priv = dev->dev_private;
1252
1253         if (!HAS_PCH_SPLIT(dev))
1254                 intel_opregion_enable_asle(dev);
1255         dev_priv->irq_enabled = 1;
1256 }
1257
1258
1259 /* Set the vblank monitor pipe
1260  */
1261 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1262                          struct drm_file *file_priv)
1263 {
1264         drm_i915_private_t *dev_priv = dev->dev_private;
1265
1266         if (!dev_priv) {
1267                 DRM_ERROR("called with no initialization\n");
1268                 return -EINVAL;
1269         }
1270
1271         return 0;
1272 }
1273
1274 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1275                          struct drm_file *file_priv)
1276 {
1277         drm_i915_private_t *dev_priv = dev->dev_private;
1278         drm_i915_vblank_pipe_t *pipe = data;
1279
1280         if (!dev_priv) {
1281                 DRM_ERROR("called with no initialization\n");
1282                 return -EINVAL;
1283         }
1284
1285         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1286
1287         return 0;
1288 }
1289
1290 /**
1291  * Schedule buffer swap at given vertical blank.
1292  */
1293 int i915_vblank_swap(struct drm_device *dev, void *data,
1294                      struct drm_file *file_priv)
1295 {
1296         /* The delayed swap mechanism was fundamentally racy, and has been
1297          * removed.  The model was that the client requested a delayed flip/swap
1298          * from the kernel, then waited for vblank before continuing to perform
1299          * rendering.  The problem was that the kernel might wake the client
1300          * up before it dispatched the vblank swap (since the lock has to be
1301          * held while touching the ringbuffer), in which case the client would
1302          * clear and start the next frame before the swap occurred, and
1303          * flicker would occur in addition to likely missing the vblank.
1304          *
1305          * In the absence of this ioctl, userland falls back to a correct path
1306          * of waiting for a vblank, then dispatching the swap on its own.
1307          * Context switching to userland and back is plenty fast enough for
1308          * meeting the requirements of vblank swapping.
1309          */
1310         return -EINVAL;
1311 }
1312
1313 static struct drm_i915_gem_request *
1314 i915_get_tail_request(struct drm_device *dev)
1315 {
1316         drm_i915_private_t *dev_priv = dev->dev_private;
1317         return list_entry(dev_priv->render_ring.request_list.prev,
1318                         struct drm_i915_gem_request, list);
1319 }
1320
1321 /**
1322  * This is called when the chip hasn't reported back with completed
1323  * batchbuffers in a long time. The first time this is called we simply record
1324  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1325  * again, we assume the chip is wedged and try to fix it.
1326  */
1327 void i915_hangcheck_elapsed(unsigned long data)
1328 {
1329         struct drm_device *dev = (struct drm_device *)data;
1330         drm_i915_private_t *dev_priv = dev->dev_private;
1331         uint32_t acthd, instdone, instdone1;
1332
1333         if (INTEL_INFO(dev)->gen < 4) {
1334                 acthd = I915_READ(ACTHD);
1335                 instdone = I915_READ(INSTDONE);
1336                 instdone1 = 0;
1337         } else {
1338                 acthd = I915_READ(ACTHD_I965);
1339                 instdone = I915_READ(INSTDONE_I965);
1340                 instdone1 = I915_READ(INSTDONE1);
1341         }
1342
1343         /* If all work is done then ACTHD clearly hasn't advanced. */
1344         if (list_empty(&dev_priv->render_ring.request_list) ||
1345                 i915_seqno_passed(dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring),
1346                                   i915_get_tail_request(dev)->seqno)) {
1347                 bool missed_wakeup = false;
1348
1349                 dev_priv->hangcheck_count = 0;
1350
1351                 /* Issue a wake-up to catch stuck h/w. */
1352                 if (dev_priv->render_ring.waiting_gem_seqno &&
1353                     waitqueue_active(&dev_priv->render_ring.irq_queue)) {
1354                         wake_up_all(&dev_priv->render_ring.irq_queue);
1355                         missed_wakeup = true;
1356                 }
1357
1358                 if (dev_priv->bsd_ring.waiting_gem_seqno &&
1359                     waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
1360                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
1361                         missed_wakeup = true;
1362                 }
1363
1364                 if (missed_wakeup)
1365                         DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1366                 return;
1367         }
1368
1369         if (dev_priv->last_acthd == acthd &&
1370             dev_priv->last_instdone == instdone &&
1371             dev_priv->last_instdone1 == instdone1) {
1372                 if (dev_priv->hangcheck_count++ > 1) {
1373                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1374
1375                         if (!IS_GEN2(dev)) {
1376                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1377                                  * If so we can simply poke the RB_WAIT bit
1378                                  * and break the hang. This should work on
1379                                  * all but the second generation chipsets.
1380                                  */
1381                                 u32 tmp = I915_READ(PRB0_CTL);
1382                                 if (tmp & RING_WAIT) {
1383                                         I915_WRITE(PRB0_CTL, tmp);
1384                                         POSTING_READ(PRB0_CTL);
1385                                         goto out;
1386                                 }
1387                         }
1388
1389                         i915_handle_error(dev, true);
1390                         return;
1391                 }
1392         } else {
1393                 dev_priv->hangcheck_count = 0;
1394
1395                 dev_priv->last_acthd = acthd;
1396                 dev_priv->last_instdone = instdone;
1397                 dev_priv->last_instdone1 = instdone1;
1398         }
1399
1400 out:
1401         /* Reset timer case chip hangs without another request being added */
1402         mod_timer(&dev_priv->hangcheck_timer,
1403                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1404 }
1405
1406 /* drm_dma.h hooks
1407 */
1408 static void ironlake_irq_preinstall(struct drm_device *dev)
1409 {
1410         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1411
1412         I915_WRITE(HWSTAM, 0xeffe);
1413
1414         /* XXX hotplug from PCH */
1415
1416         I915_WRITE(DEIMR, 0xffffffff);
1417         I915_WRITE(DEIER, 0x0);
1418         (void) I915_READ(DEIER);
1419
1420         /* and GT */
1421         I915_WRITE(GTIMR, 0xffffffff);
1422         I915_WRITE(GTIER, 0x0);
1423         (void) I915_READ(GTIER);
1424
1425         /* south display irq */
1426         I915_WRITE(SDEIMR, 0xffffffff);
1427         I915_WRITE(SDEIER, 0x0);
1428         (void) I915_READ(SDEIER);
1429 }
1430
1431 static int ironlake_irq_postinstall(struct drm_device *dev)
1432 {
1433         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1434         /* enable kind of interrupts always enabled */
1435         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1436                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1437         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1438         u32 hotplug_mask;
1439
1440         dev_priv->irq_mask_reg = ~display_mask;
1441         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1442
1443         /* should always can generate irq */
1444         I915_WRITE(DEIIR, I915_READ(DEIIR));
1445         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1446         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1447         (void) I915_READ(DEIER);
1448
1449         if (IS_GEN6(dev))
1450                 render_mask = GT_PIPE_NOTIFY | GT_GEN6_BSD_USER_INTERRUPT;
1451
1452         dev_priv->gt_irq_mask_reg = ~render_mask;
1453         dev_priv->gt_irq_enable_reg = render_mask;
1454
1455         I915_WRITE(GTIIR, I915_READ(GTIIR));
1456         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1457         if (IS_GEN6(dev)) {
1458                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1459                 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1460         }
1461
1462         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1463         (void) I915_READ(GTIER);
1464
1465         if (HAS_PCH_CPT(dev)) {
1466                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1467                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1468         } else {
1469                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1470                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1471         }
1472
1473         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1474         dev_priv->pch_irq_enable_reg = hotplug_mask;
1475
1476         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1477         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1478         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1479         (void) I915_READ(SDEIER);
1480
1481         if (IS_IRONLAKE_M(dev)) {
1482                 /* Clear & enable PCU event interrupts */
1483                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1484                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1485                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1486         }
1487
1488         return 0;
1489 }
1490
1491 void i915_driver_irq_preinstall(struct drm_device * dev)
1492 {
1493         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1494
1495         atomic_set(&dev_priv->irq_received, 0);
1496
1497         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1498         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1499
1500         if (HAS_PCH_SPLIT(dev)) {
1501                 ironlake_irq_preinstall(dev);
1502                 return;
1503         }
1504
1505         if (I915_HAS_HOTPLUG(dev)) {
1506                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1507                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1508         }
1509
1510         I915_WRITE(HWSTAM, 0xeffe);
1511         I915_WRITE(PIPEASTAT, 0);
1512         I915_WRITE(PIPEBSTAT, 0);
1513         I915_WRITE(IMR, 0xffffffff);
1514         I915_WRITE(IER, 0x0);
1515         (void) I915_READ(IER);
1516 }
1517
1518 /*
1519  * Must be called after intel_modeset_init or hotplug interrupts won't be
1520  * enabled correctly.
1521  */
1522 int i915_driver_irq_postinstall(struct drm_device *dev)
1523 {
1524         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1525         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1526         u32 error_mask;
1527
1528         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1529
1530         if (HAS_BSD(dev))
1531                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1532
1533         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1534
1535         if (HAS_PCH_SPLIT(dev))
1536                 return ironlake_irq_postinstall(dev);
1537
1538         /* Unmask the interrupts that we always want on. */
1539         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1540
1541         dev_priv->pipestat[0] = 0;
1542         dev_priv->pipestat[1] = 0;
1543
1544         if (I915_HAS_HOTPLUG(dev)) {
1545                 /* Enable in IER... */
1546                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1547                 /* and unmask in IMR */
1548                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1549         }
1550
1551         /*
1552          * Enable some error detection, note the instruction error mask
1553          * bit is reserved, so we leave it masked.
1554          */
1555         if (IS_G4X(dev)) {
1556                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1557                                GM45_ERROR_MEM_PRIV |
1558                                GM45_ERROR_CP_PRIV |
1559                                I915_ERROR_MEMORY_REFRESH);
1560         } else {
1561                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1562                                I915_ERROR_MEMORY_REFRESH);
1563         }
1564         I915_WRITE(EMR, error_mask);
1565
1566         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1567         I915_WRITE(IER, enable_mask);
1568         (void) I915_READ(IER);
1569
1570         if (I915_HAS_HOTPLUG(dev)) {
1571                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1572
1573                 /* Note HDMI and DP share bits */
1574                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1575                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1576                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1577                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1578                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1579                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1580                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1581                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1582                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1583                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1584                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1585                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1586
1587                         /* Programming the CRT detection parameters tends
1588                            to generate a spurious hotplug event about three
1589                            seconds later.  So just do it once.
1590                         */
1591                         if (IS_G4X(dev))
1592                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1593                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1594                 }
1595
1596                 /* Ignore TV since it's buggy */
1597
1598                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1599         }
1600
1601         intel_opregion_enable_asle(dev);
1602
1603         return 0;
1604 }
1605
1606 static void ironlake_irq_uninstall(struct drm_device *dev)
1607 {
1608         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1609         I915_WRITE(HWSTAM, 0xffffffff);
1610
1611         I915_WRITE(DEIMR, 0xffffffff);
1612         I915_WRITE(DEIER, 0x0);
1613         I915_WRITE(DEIIR, I915_READ(DEIIR));
1614
1615         I915_WRITE(GTIMR, 0xffffffff);
1616         I915_WRITE(GTIER, 0x0);
1617         I915_WRITE(GTIIR, I915_READ(GTIIR));
1618 }
1619
1620 void i915_driver_irq_uninstall(struct drm_device * dev)
1621 {
1622         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1623
1624         if (!dev_priv)
1625                 return;
1626
1627         dev_priv->vblank_pipe = 0;
1628
1629         if (HAS_PCH_SPLIT(dev)) {
1630                 ironlake_irq_uninstall(dev);
1631                 return;
1632         }
1633
1634         if (I915_HAS_HOTPLUG(dev)) {
1635                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1636                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1637         }
1638
1639         I915_WRITE(HWSTAM, 0xffffffff);
1640         I915_WRITE(PIPEASTAT, 0);
1641         I915_WRITE(PIPEBSTAT, 0);
1642         I915_WRITE(IMR, 0xffffffff);
1643         I915_WRITE(IER, 0x0);
1644
1645         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1646         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1647         I915_WRITE(IIR, I915_READ(IIR));
1648 }