drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <linux/ascii85.h>
  31 #include <linux/nmi.h>
  32 #include <linux/scatterlist.h>
  33 #include <linux/stop_machine.h>
  34 #include <linux/utsname.h>
  35 #include <linux/zlib.h>
  36
  37 #include <drm/drm_print.h>
  38
  39 #include "i915_gpu_error.h"
  40 #include "i915_drv.h"
  41
  42 static inline const struct intel_engine_cs *
  43 engine_lookup(const struct drm_i915_private *i915, unsigned int id)
  44 {
  45         if (id >= I915_NUM_ENGINES)
  46                 return NULL;
  47
  48         return i915->engine[id];
  49 }
  50
  51 static inline const char *
  52 __engine_name(const struct intel_engine_cs *engine)
  53 {
  54         return engine ? engine->name : "";
  55 }
  56
  57 static const char *
  58 engine_name(const struct drm_i915_private *i915, unsigned int id)
  59 {
  60         return __engine_name(engine_lookup(i915, id));
  61 }
  62
  63 static const char *tiling_flag(int tiling)
  64 {
  65         switch (tiling) {
  66         default:
  67         case I915_TILING_NONE: return "";
  68         case I915_TILING_X: return " X";
  69         case I915_TILING_Y: return " Y";
  70         }
  71 }
  72
  73 static const char *dirty_flag(int dirty)
  74 {
  75         return dirty ? " dirty" : "";
  76 }
  77
  78 static const char *purgeable_flag(int purgeable)
  79 {
  80         return purgeable ? " purgeable" : "";
  81 }
  82
  83 static void __sg_set_buf(struct scatterlist *sg,
  84                          void *addr, unsigned int len, loff_t it)
  85 {
  86         sg->page_link = (unsigned long)virt_to_page(addr);
  87         sg->offset = offset_in_page(addr);
  88         sg->length = len;
  89         sg->dma_address = it;
  90 }
  91
  92 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
  93 {
  94         if (!len)
  95                 return false;
  96
  97         if (e->bytes + len + 1 <= e->size)
  98                 return true;
  99
 100         if (e->bytes) {
 101                 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
 102                 e->iter += e->bytes;
 103                 e->buf = NULL;
 104                 e->bytes = 0;
 105         }
 106
 107         if (e->cur == e->end) {
 108                 struct scatterlist *sgl;
 109
 110                 sgl = (typeof(sgl))__get_free_page(GFP_KERNEL);
 111                 if (!sgl) {
 112                         e->err = -ENOMEM;
 113                         return false;
 114                 }
 115
 116                 if (e->cur) {
 117                         e->cur->offset = 0;
 118                         e->cur->length = 0;
 119                         e->cur->page_link =
 120                                 (unsigned long)sgl | SG_CHAIN;
 121                 } else {
 122                         e->sgl = sgl;
 123                 }
 124
 125                 e->cur = sgl;
 126                 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
 127         }
 128
 129         e->size = ALIGN(len + 1, SZ_64K);
 130         e->buf = kmalloc(e->size, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
 131         if (!e->buf) {
 132                 e->size = PAGE_ALIGN(len + 1);
 133                 e->buf = kmalloc(e->size, GFP_KERNEL);
 134         }
 135         if (!e->buf) {
 136                 e->err = -ENOMEM;
 137                 return false;
 138         }
 139
 140         return true;
 141 }
 142
 143 __printf(2, 0)
 144 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 145                                const char *fmt, va_list args)
 146 {
 147         va_list ap;
 148         int len;
 149
 150         if (e->err)
 151                 return;
 152
 153         va_copy(ap, args);
 154         len = vsnprintf(NULL, 0, fmt, ap);
 155         va_end(ap);
 156         if (len <= 0) {
 157                 e->err = len;
 158                 return;
 159         }
 160
 161         if (!__i915_error_grow(e, len))
 162                 return;
 163
 164         GEM_BUG_ON(e->bytes >= e->size);
 165         len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
 166         if (len < 0) {
 167                 e->err = len;
 168                 return;
 169         }
 170         e->bytes += len;
 171 }
 172
 173 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
 174 {
 175         unsigned len;
 176
 177         if (e->err || !str)
 178                 return;
 179
 180         len = strlen(str);
 181         if (!__i915_error_grow(e, len))
 182                 return;
 183
 184         GEM_BUG_ON(e->bytes + len > e->size);
 185         memcpy(e->buf + e->bytes, str, len);
 186         e->bytes += len;
 187 }
 188
 189 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 190 #define err_puts(e, s) i915_error_puts(e, s)
 191
 192 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
 193 {
 194         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
 195 }
 196
 197 static inline struct drm_printer
 198 i915_error_printer(struct drm_i915_error_state_buf *e)
 199 {
 200         struct drm_printer p = {
 201                 .printfn = __i915_printfn_error,
 202                 .arg = e,
 203         };
 204         return p;
 205 }
 206
 207 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 208
 209 struct compress {
 210         struct z_stream_s zstream;
 211         void *tmp;
 212 };
 213
 214 static bool compress_init(struct compress *c)
 215 {
 216         struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
 217
 218         zstream->workspace =
 219                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 220                         GFP_ATOMIC | __GFP_NOWARN);
 221         if (!zstream->workspace)
 222                 return false;
 223
 224         if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
 225                 kfree(zstream->workspace);
 226                 return false;
 227         }
 228
 229         c->tmp = NULL;
 230         if (i915_has_memcpy_from_wc())
 231                 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 232
 233         return true;
 234 }
 235
 236 static void *compress_next_page(struct drm_i915_error_object *dst)
 237 {
 238         unsigned long page;
 239
 240         if (dst->page_count >= dst->num_pages)
 241                 return ERR_PTR(-ENOSPC);
 242
 243         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 244         if (!page)
 245                 return ERR_PTR(-ENOMEM);
 246
 247         return dst->pages[dst->page_count++] = (void *)page;
 248 }
 249
 250 static int compress_page(struct compress *c,
 251                          void *src,
 252                          struct drm_i915_error_object *dst)
 253 {
 254         struct z_stream_s *zstream = &c->zstream;
 255
 256         zstream->next_in = src;
 257         if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 258                 zstream->next_in = c->tmp;
 259         zstream->avail_in = PAGE_SIZE;
 260
 261         do {
 262                 if (zstream->avail_out == 0) {
 263                         zstream->next_out = compress_next_page(dst);
 264                         if (IS_ERR(zstream->next_out))
 265                                 return PTR_ERR(zstream->next_out);
 266
 267                         zstream->avail_out = PAGE_SIZE;
 268                 }
 269
 270                 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
 271                         return -EIO;
 272
 273                 touch_nmi_watchdog();
 274         } while (zstream->avail_in);
 275
 276         /* Fallback to uncompressed if we increase size? */
 277         if (0 && zstream->total_out > zstream->total_in)
 278                 return -E2BIG;
 279
 280         return 0;
 281 }
 282
 283 static int compress_flush(struct compress *c,
 284                           struct drm_i915_error_object *dst)
 285 {
 286         struct z_stream_s *zstream = &c->zstream;
 287
 288         do {
 289                 switch (zlib_deflate(zstream, Z_FINISH)) {
 290                 case Z_OK: /* more space requested */
 291                         zstream->next_out = compress_next_page(dst);
 292                         if (IS_ERR(zstream->next_out))
 293                                 return PTR_ERR(zstream->next_out);
 294
 295                         zstream->avail_out = PAGE_SIZE;
 296                         break;
 297
 298                 case Z_STREAM_END:
 299                         goto end;
 300
 301                 default: /* any error */
 302                         return -EIO;
 303                 }
 304         } while (1);
 305
 306 end:
 307         memset(zstream->next_out, 0, zstream->avail_out);
 308         dst->unused = zstream->avail_out;
 309         return 0;
 310 }
 311
 312 static void compress_fini(struct compress *c,
 313                           struct drm_i915_error_object *dst)
 314 {
 315         struct z_stream_s *zstream = &c->zstream;
 316
 317         zlib_deflateEnd(zstream);
 318         kfree(zstream->workspace);
 319         if (c->tmp)
 320                 free_page((unsigned long)c->tmp);
 321 }
 322
 323 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 324 {
 325         err_puts(m, ":");
 326 }
 327
 328 #else
 329
 330 struct compress {
 331 };
 332
 333 static bool compress_init(struct compress *c)
 334 {
 335         return true;
 336 }
 337
 338 static int compress_page(struct compress *c,
 339                          void *src,
 340                          struct drm_i915_error_object *dst)
 341 {
 342         unsigned long page;
 343         void *ptr;
 344
 345         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 346         if (!page)
 347                 return -ENOMEM;
 348
 349         ptr = (void *)page;
 350         if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
 351                 memcpy(ptr, src, PAGE_SIZE);
 352         dst->pages[dst->page_count++] = ptr;
 353
 354         return 0;
 355 }
 356
 357 static int compress_flush(struct compress *c,
 358                           struct drm_i915_error_object *dst)
 359 {
 360         return 0;
 361 }
 362
 363 static void compress_fini(struct compress *c,
 364                           struct drm_i915_error_object *dst)
 365 {
 366 }
 367
 368 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 369 {
 370         err_puts(m, "~");
 371 }
 372
 373 #endif
 374
 375 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 376                                 const char *name,
 377                                 struct drm_i915_error_buffer *err,
 378                                 int count)
 379 {
 380         err_printf(m, "%s [%d]:\n", name, count);
 381
 382         while (count--) {
 383                 err_printf(m, "    %08x_%08x %8u %02x %02x %02x",
 384                            upper_32_bits(err->gtt_offset),
 385                            lower_32_bits(err->gtt_offset),
 386                            err->size,
 387                            err->read_domains,
 388                            err->write_domain,
 389                            err->wseqno);
 390                 err_puts(m, tiling_flag(err->tiling));
 391                 err_puts(m, dirty_flag(err->dirty));
 392                 err_puts(m, purgeable_flag(err->purgeable));
 393                 err_puts(m, err->userptr ? " userptr" : "");
 394                 err_puts(m, err->engine != -1 ? " " : "");
 395                 err_puts(m, engine_name(m->i915, err->engine));
 396                 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
 397
 398                 if (err->name)
 399                         err_printf(m, " (name: %d)", err->name);
 400                 if (err->fence_reg != I915_FENCE_REG_NONE)
 401                         err_printf(m, " (fence: %d)", err->fence_reg);
 402
 403                 err_puts(m, "\n");
 404                 err++;
 405         }
 406 }
 407
 408 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 409                                  const struct drm_i915_error_engine *ee)
 410 {
 411         int slice;
 412         int subslice;
 413
 414         err_printf(m, "  INSTDONE: 0x%08x\n",
 415                    ee->instdone.instdone);
 416
 417         if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
 418                 return;
 419
 420         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 421                    ee->instdone.slice_common);
 422
 423         if (INTEL_GEN(m->i915) <= 6)
 424                 return;
 425
 426         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 427                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 428                            slice, subslice,
 429                            ee->instdone.sampler[slice][subslice]);
 430
 431         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 432                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 433                            slice, subslice,
 434                            ee->instdone.row[slice][subslice]);
 435 }
 436
 437 static const char *bannable(const struct drm_i915_error_context *ctx)
 438 {
 439         return ctx->bannable ? "" : " (unbannable)";
 440 }
 441
 442 static void error_print_request(struct drm_i915_error_state_buf *m,
 443                                 const char *prefix,
 444                                 const struct drm_i915_error_request *erq,
 445                                 const unsigned long epoch)
 446 {
 447         if (!erq->seqno)
 448                 return;
 449
 450         err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, prio %d, emitted %dms, start %08x, head %08x, tail %08x\n",
 451                    prefix, erq->pid, erq->ban_score,
 452                    erq->context, erq->seqno, erq->sched_attr.priority,
 453                    jiffies_to_msecs(erq->jiffies - epoch),
 454                    erq->start, erq->head, erq->tail);
 455 }
 456
 457 static void error_print_context(struct drm_i915_error_state_buf *m,
 458                                 const char *header,
 459                                 const struct drm_i915_error_context *ctx)
 460 {
 461         err_printf(m, "%s%s[%d] user_handle %d hw_id %d, prio %d, ban score %d%s guilty %d active %d\n",
 462                    header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
 463                    ctx->sched_attr.priority, ctx->ban_score, bannable(ctx),
 464                    ctx->guilty, ctx->active);
 465 }
 466
 467 static void error_print_engine(struct drm_i915_error_state_buf *m,
 468                                const struct drm_i915_error_engine *ee,
 469                                const unsigned long epoch)
 470 {
 471         int n;
 472
 473         err_printf(m, "%s command stream:\n",
 474                    engine_name(m->i915, ee->engine_id));
 475         err_printf(m, "  IDLE?: %s\n", yesno(ee->idle));
 476         err_printf(m, "  START: 0x%08x\n", ee->start);
 477         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 478         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 479                    ee->tail, ee->rq_post, ee->rq_tail);
 480         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 481         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 482         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 483         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 484                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 485         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 486         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 487
 488         error_print_instdone(m, ee);
 489
 490         if (ee->batchbuffer) {
 491                 u64 start = ee->batchbuffer->gtt_offset;
 492                 u64 end = start + ee->batchbuffer->gtt_size;
 493
 494                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 495                            upper_32_bits(start), lower_32_bits(start),
 496                            upper_32_bits(end), lower_32_bits(end));
 497         }
 498         if (INTEL_GEN(m->i915) >= 4) {
 499                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 500                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 501                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 502                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 503         }
 504         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 505         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 506                    lower_32_bits(ee->faddr));
 507         if (INTEL_GEN(m->i915) >= 6) {
 508                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 509                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 510                 err_printf(m, "  SYNC_0: 0x%08x\n",
 511                            ee->semaphore_mboxes[0]);
 512                 err_printf(m, "  SYNC_1: 0x%08x\n",
 513                            ee->semaphore_mboxes[1]);
 514                 if (HAS_VEBOX(m->i915))
 515                         err_printf(m, "  SYNC_2: 0x%08x\n",
 516                                    ee->semaphore_mboxes[2]);
 517         }
 518         if (HAS_PPGTT(m->i915)) {
 519                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 520
 521                 if (INTEL_GEN(m->i915) >= 8) {
 522                         int i;
 523                         for (i = 0; i < 4; i++)
 524                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 525                                            i, ee->vm_info.pdp[i]);
 526                 } else {
 527                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 528                                    ee->vm_info.pp_dir_base);
 529                 }
 530         }
 531         err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
 532         err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
 533         err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
 534         err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
 535         err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
 536         err_printf(m, "  hangcheck stall: %s\n", yesno(ee->hangcheck_stalled));
 537         err_printf(m, "  hangcheck action: %s\n",
 538                    hangcheck_action_to_str(ee->hangcheck_action));
 539         err_printf(m, "  hangcheck action timestamp: %dms (%lu%s)\n",
 540                    jiffies_to_msecs(ee->hangcheck_timestamp - epoch),
 541                    ee->hangcheck_timestamp,
 542                    ee->hangcheck_timestamp == epoch ? "; epoch" : "");
 543         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 544
 545         for (n = 0; n < ee->num_ports; n++) {
 546                 err_printf(m, "  ELSP[%d]:", n);
 547                 error_print_request(m, " ", &ee->execlist[n], epoch);
 548         }
 549
 550         error_print_context(m, "  Active context: ", &ee->context);
 551 }
 552
 553 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 554 {
 555         va_list args;
 556
 557         va_start(args, f);
 558         i915_error_vprintf(e, f, args);
 559         va_end(args);
 560 }
 561
 562 static void print_error_obj(struct drm_i915_error_state_buf *m,
 563                             struct intel_engine_cs *engine,
 564                             const char *name,
 565                             struct drm_i915_error_object *obj)
 566 {
 567         char out[ASCII85_BUFSZ];
 568         int page;
 569
 570         if (!obj)
 571                 return;
 572
 573         if (name) {
 574                 err_printf(m, "%s --- %s = 0x%08x %08x\n",
 575                            engine ? engine->name : "global", name,
 576                            upper_32_bits(obj->gtt_offset),
 577                            lower_32_bits(obj->gtt_offset));
 578         }
 579
 580         err_compression_marker(m);
 581         for (page = 0; page < obj->page_count; page++) {
 582                 int i, len;
 583
 584                 len = PAGE_SIZE;
 585                 if (page == obj->page_count - 1)
 586                         len -= obj->unused;
 587                 len = ascii85_encode_len(len);
 588
 589                 for (i = 0; i < len; i++)
 590                         err_puts(m, ascii85_encode(obj->pages[page][i], out));
 591         }
 592         err_puts(m, "\n");
 593 }
 594
 595 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 596                                    const struct intel_device_info *info,
 597                                    const struct intel_runtime_info *runtime,
 598                                    const struct intel_driver_caps *caps)
 599 {
 600         struct drm_printer p = i915_error_printer(m);
 601
 602         intel_device_info_dump_flags(info, &p);
 603         intel_driver_caps_print(caps, &p);
 604         intel_device_info_dump_topology(&runtime->sseu, &p);
 605 }
 606
 607 static void err_print_params(struct drm_i915_error_state_buf *m,
 608                              const struct i915_params *params)
 609 {
 610         struct drm_printer p = i915_error_printer(m);
 611
 612         i915_params_dump(params, &p);
 613 }
 614
 615 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 616                             struct drm_i915_private *i915)
 617 {
 618         struct pci_dev *pdev = i915->drm.pdev;
 619
 620         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 621         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 622         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 623                    pdev->subsystem_vendor,
 624                    pdev->subsystem_device);
 625 }
 626
 627 static void err_print_uc(struct drm_i915_error_state_buf *m,
 628                          const struct i915_error_uc *error_uc)
 629 {
 630         struct drm_printer p = i915_error_printer(m);
 631         const struct i915_gpu_state *error =
 632                 container_of(error_uc, typeof(*error), uc);
 633
 634         if (!error->device_info.has_guc)
 635                 return;
 636
 637         intel_uc_fw_dump(&error_uc->guc_fw, &p);
 638         intel_uc_fw_dump(&error_uc->huc_fw, &p);
 639         print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
 640 }
 641
 642 static void err_free_sgl(struct scatterlist *sgl)
 643 {
 644         while (sgl) {
 645                 struct scatterlist *sg;
 646
 647                 for (sg = sgl; !sg_is_chain(sg); sg++) {
 648                         kfree(sg_virt(sg));
 649                         if (sg_is_last(sg))
 650                                 break;
 651                 }
 652
 653                 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
 654                 free_page((unsigned long)sgl);
 655                 sgl = sg;
 656         }
 657 }
 658
 659 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
 660                                struct i915_gpu_state *error)
 661 {
 662         struct drm_i915_error_object *obj;
 663         struct timespec64 ts;
 664         int i, j;
 665
 666         if (*error->error_msg)
 667                 err_printf(m, "%s\n", error->error_msg);
 668         err_printf(m, "Kernel: %s %s\n",
 669                    init_utsname()->release,
 670                    init_utsname()->machine);
 671         ts = ktime_to_timespec64(error->time);
 672         err_printf(m, "Time: %lld s %ld us\n",
 673                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 674         ts = ktime_to_timespec64(error->boottime);
 675         err_printf(m, "Boottime: %lld s %ld us\n",
 676                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 677         ts = ktime_to_timespec64(error->uptime);
 678         err_printf(m, "Uptime: %lld s %ld us\n",
 679                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 680         err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ);
 681         err_printf(m, "Capture: %lu jiffies; %d ms ago, %d ms after epoch\n",
 682                    error->capture,
 683                    jiffies_to_msecs(jiffies - error->capture),
 684                    jiffies_to_msecs(error->capture - error->epoch));
 685
 686         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 687                 if (error->engine[i].hangcheck_stalled &&
 688                     error->engine[i].context.pid) {
 689                         err_printf(m, "Active process (on ring %s): %s [%d], score %d%s\n",
 690                                    engine_name(m->i915, i),
 691                                    error->engine[i].context.comm,
 692                                    error->engine[i].context.pid,
 693                                    error->engine[i].context.ban_score,
 694                                    bannable(&error->engine[i].context));
 695                 }
 696         }
 697         err_printf(m, "Reset count: %u\n", error->reset_count);
 698         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 699         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 700         err_print_pciid(m, m->i915);
 701
 702         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 703
 704         if (HAS_CSR(m->i915)) {
 705                 struct intel_csr *csr = &m->i915->csr;
 706
 707                 err_printf(m, "DMC loaded: %s\n",
 708                            yesno(csr->dmc_payload != NULL));
 709                 err_printf(m, "DMC fw version: %d.%d\n",
 710                            CSR_VERSION_MAJOR(csr->version),
 711                            CSR_VERSION_MINOR(csr->version));
 712         }
 713
 714         err_printf(m, "GT awake: %s\n", yesno(error->awake));
 715         err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
 716         err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
 717         err_printf(m, "EIR: 0x%08x\n", error->eir);
 718         err_printf(m, "IER: 0x%08x\n", error->ier);
 719         for (i = 0; i < error->ngtier; i++)
 720                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]);
 721         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 722         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 723         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 724         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 725         err_printf(m, "Missed interrupts: 0x%08lx\n",
 726                    m->i915->gpu_error.missed_irq_rings);
 727
 728         for (i = 0; i < error->nfence; i++)
 729                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 730
 731         if (INTEL_GEN(m->i915) >= 6) {
 732                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 733
 734                 if (INTEL_GEN(m->i915) >= 8)
 735                         err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 736                                    error->fault_data1, error->fault_data0);
 737
 738                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 739         }
 740
 741         if (IS_GEN(m->i915, 7))
 742                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 743
 744         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 745                 if (error->engine[i].engine_id != -1)
 746                         error_print_engine(m, &error->engine[i], error->epoch);
 747         }
 748
 749         for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
 750                 char buf[128];
 751                 int len, first = 1;
 752
 753                 if (!error->active_vm[i])
 754                         break;
 755
 756                 len = scnprintf(buf, sizeof(buf), "Active (");
 757                 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
 758                         if (error->engine[j].vm != error->active_vm[i])
 759                                 continue;
 760
 761                         len += scnprintf(buf + len, sizeof(buf), "%s%s",
 762                                          first ? "" : ", ",
 763                                          m->i915->engine[j]->name);
 764                         first = 0;
 765                 }
 766                 scnprintf(buf + len, sizeof(buf), ")");
 767                 print_error_buffers(m, buf,
 768                                     error->active_bo[i],
 769                                     error->active_bo_count[i]);
 770         }
 771
 772         print_error_buffers(m, "Pinned (global)",
 773                             error->pinned_bo,
 774                             error->pinned_bo_count);
 775
 776         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 777                 const struct drm_i915_error_engine *ee = &error->engine[i];
 778
 779                 obj = ee->batchbuffer;
 780                 if (obj) {
 781                         err_puts(m, m->i915->engine[i]->name);
 782                         if (ee->context.pid)
 783                                 err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d%s)",
 784                                            ee->context.comm,
 785                                            ee->context.pid,
 786                                            ee->context.handle,
 787                                            ee->context.hw_id,
 788                                            ee->context.ban_score,
 789                                            bannable(&ee->context));
 790                         err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
 791                                    upper_32_bits(obj->gtt_offset),
 792                                    lower_32_bits(obj->gtt_offset));
 793                         print_error_obj(m, m->i915->engine[i], NULL, obj);
 794                 }
 795
 796                 for (j = 0; j < ee->user_bo_count; j++)
 797                         print_error_obj(m, m->i915->engine[i],
 798                                         "user", ee->user_bo[j]);
 799
 800                 if (ee->num_requests) {
 801                         err_printf(m, "%s --- %d requests\n",
 802                                    m->i915->engine[i]->name,
 803                                    ee->num_requests);
 804                         for (j = 0; j < ee->num_requests; j++)
 805                                 error_print_request(m, " ",
 806                                                     &ee->requests[j],
 807                                                     error->epoch);
 808                 }
 809
 810                 if (IS_ERR(ee->waiters)) {
 811                         err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
 812                                    m->i915->engine[i]->name);
 813                 } else if (ee->num_waiters) {
 814                         err_printf(m, "%s --- %d waiters\n",
 815                                    m->i915->engine[i]->name,
 816                                    ee->num_waiters);
 817                         for (j = 0; j < ee->num_waiters; j++) {
 818                                 err_printf(m, " seqno 0x%08x for %s [%d]\n",
 819                                            ee->waiters[j].seqno,
 820                                            ee->waiters[j].comm,
 821                                            ee->waiters[j].pid);
 822                         }
 823                 }
 824
 825                 print_error_obj(m, m->i915->engine[i],
 826                                 "ringbuffer", ee->ringbuffer);
 827
 828                 print_error_obj(m, m->i915->engine[i],
 829                                 "HW Status", ee->hws_page);
 830
 831                 print_error_obj(m, m->i915->engine[i],
 832                                 "HW context", ee->ctx);
 833
 834                 print_error_obj(m, m->i915->engine[i],
 835                                 "WA context", ee->wa_ctx);
 836
 837                 print_error_obj(m, m->i915->engine[i],
 838                                 "WA batchbuffer", ee->wa_batchbuffer);
 839
 840                 print_error_obj(m, m->i915->engine[i],
 841                                 "NULL context", ee->default_state);
 842         }
 843
 844         if (error->overlay)
 845                 intel_overlay_print_error_state(m, error->overlay);
 846
 847         if (error->display)
 848                 intel_display_print_error_state(m, error->display);
 849
 850         err_print_capabilities(m, &error->device_info, &error->runtime_info,
 851                                &error->driver_caps);
 852         err_print_params(m, &error->params);
 853         err_print_uc(m, &error->uc);
 854 }
 855
 856 static int err_print_to_sgl(struct i915_gpu_state *error)
 857 {
 858         struct drm_i915_error_state_buf m;
 859
 860         if (IS_ERR(error))
 861                 return PTR_ERR(error);
 862
 863         if (READ_ONCE(error->sgl))
 864                 return 0;
 865
 866         memset(&m, 0, sizeof(m));
 867         m.i915 = error->i915;
 868
 869         __err_print_to_sgl(&m, error);
 870
 871         if (m.buf) {
 872                 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
 873                 m.bytes = 0;
 874                 m.buf = NULL;
 875         }
 876         if (m.cur) {
 877                 GEM_BUG_ON(m.end < m.cur);
 878                 sg_mark_end(m.cur - 1);
 879         }
 880         GEM_BUG_ON(m.sgl && !m.cur);
 881
 882         if (m.err) {
 883                 err_free_sgl(m.sgl);
 884                 return m.err;
 885         }
 886
 887         if (cmpxchg(&error->sgl, NULL, m.sgl))
 888                 err_free_sgl(m.sgl);
 889
 890         return 0;
 891 }
 892
 893 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
 894                                       char *buf, loff_t off, size_t rem)
 895 {
 896         struct scatterlist *sg;
 897         size_t count;
 898         loff_t pos;
 899         int err;
 900
 901         if (!error || !rem)
 902                 return 0;
 903
 904         err = err_print_to_sgl(error);
 905         if (err)
 906                 return err;
 907
 908         sg = READ_ONCE(error->fit);
 909         if (!sg || off < sg->dma_address)
 910                 sg = error->sgl;
 911         if (!sg)
 912                 return 0;
 913
 914         pos = sg->dma_address;
 915         count = 0;
 916         do {
 917                 size_t len, start;
 918
 919                 if (sg_is_chain(sg)) {
 920                         sg = sg_chain_ptr(sg);
 921                         GEM_BUG_ON(sg_is_chain(sg));
 922                 }
 923
 924                 len = sg->length;
 925                 if (pos + len <= off) {
 926                         pos += len;
 927                         continue;
 928                 }
 929
 930                 start = sg->offset;
 931                 if (pos < off) {
 932                         GEM_BUG_ON(off - pos > len);
 933                         len -= off - pos;
 934                         start += off - pos;
 935                         pos = off;
 936                 }
 937
 938                 len = min(len, rem);
 939                 GEM_BUG_ON(!len || len > sg->length);
 940
 941                 memcpy(buf, page_address(sg_page(sg)) + start, len);
 942
 943                 count += len;
 944                 pos += len;
 945
 946                 buf += len;
 947                 rem -= len;
 948                 if (!rem) {
 949                         WRITE_ONCE(error->fit, sg);
 950                         break;
 951                 }
 952         } while (!sg_is_last(sg++));
 953
 954         return count;
 955 }
 956
 957 static void i915_error_object_free(struct drm_i915_error_object *obj)
 958 {
 959         int page;
 960
 961         if (obj == NULL)
 962                 return;
 963
 964         for (page = 0; page < obj->page_count; page++)
 965                 free_page((unsigned long)obj->pages[page]);
 966
 967         kfree(obj);
 968 }
 969
 970
 971 static void cleanup_params(struct i915_gpu_state *error)
 972 {
 973         i915_params_free(&error->params);
 974 }
 975
 976 static void cleanup_uc_state(struct i915_gpu_state *error)
 977 {
 978         struct i915_error_uc *error_uc = &error->uc;
 979
 980         kfree(error_uc->guc_fw.path);
 981         kfree(error_uc->huc_fw.path);
 982         i915_error_object_free(error_uc->guc_log);
 983 }
 984
 985 void __i915_gpu_state_free(struct kref *error_ref)
 986 {
 987         struct i915_gpu_state *error =
 988                 container_of(error_ref, typeof(*error), ref);
 989         long i, j;
 990
 991         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 992                 struct drm_i915_error_engine *ee = &error->engine[i];
 993
 994                 for (j = 0; j < ee->user_bo_count; j++)
 995                         i915_error_object_free(ee->user_bo[j]);
 996                 kfree(ee->user_bo);
 997
 998                 i915_error_object_free(ee->batchbuffer);
 999                 i915_error_object_free(ee->wa_batchbuffer);
1000                 i915_error_object_free(ee->ringbuffer);
1001                 i915_error_object_free(ee->hws_page);
1002                 i915_error_object_free(ee->ctx);
1003                 i915_error_object_free(ee->wa_ctx);
1004
1005                 kfree(ee->requests);
1006                 if (!IS_ERR_OR_NULL(ee->waiters))
1007                         kfree(ee->waiters);
1008         }
1009
1010         for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
1011                 kfree(error->active_bo[i]);
1012         kfree(error->pinned_bo);
1013
1014         kfree(error->overlay);
1015         kfree(error->display);
1016
1017         cleanup_params(error);
1018         cleanup_uc_state(error);
1019
1020         err_free_sgl(error->sgl);
1021         kfree(error);
1022 }
1023
1024 static struct drm_i915_error_object *
1025 i915_error_object_create(struct drm_i915_private *i915,
1026                          struct i915_vma *vma)
1027 {
1028         struct i915_ggtt *ggtt = &i915->ggtt;
1029         const u64 slot = ggtt->error_capture.start;
1030         struct drm_i915_error_object *dst;
1031         struct compress compress;
1032         unsigned long num_pages;
1033         struct sgt_iter iter;
1034         dma_addr_t dma;
1035         int ret;
1036
1037         if (!vma || !vma->pages)
1038                 return NULL;
1039
1040         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
1041         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
1042         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
1043                       GFP_ATOMIC | __GFP_NOWARN);
1044         if (!dst)
1045                 return NULL;
1046
1047         dst->gtt_offset = vma->node.start;
1048         dst->gtt_size = vma->node.size;
1049         dst->num_pages = num_pages;
1050         dst->page_count = 0;
1051         dst->unused = 0;
1052
1053         if (!compress_init(&compress)) {
1054                 kfree(dst);
1055                 return NULL;
1056         }
1057
1058         ret = -EINVAL;
1059         for_each_sgt_dma(dma, iter, vma->pages) {
1060                 void __iomem *s;
1061
1062                 ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
1063
1064                 s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
1065                 ret = compress_page(&compress, (void  __force *)s, dst);
1066                 io_mapping_unmap_atomic(s);
1067                 if (ret)
1068                         break;
1069         }
1070
1071         if (ret || compress_flush(&compress, dst)) {
1072                 while (dst->page_count--)
1073                         free_page((unsigned long)dst->pages[dst->page_count]);
1074                 kfree(dst);
1075                 dst = NULL;
1076         }
1077
1078         compress_fini(&compress, dst);
1079         return dst;
1080 }
1081
1082 /* The error capture is special as tries to run underneath the normal
1083  * locking rules - so we use the raw version of the i915_gem_active lookup.
1084  */
1085 static inline u32
1086 __active_get_seqno(struct i915_gem_active *active)
1087 {
1088         struct i915_request *request;
1089
1090         request = __i915_gem_active_peek(active);
1091         return request ? request->global_seqno : 0;
1092 }
1093
1094 static inline int
1095 __active_get_engine_id(struct i915_gem_active *active)
1096 {
1097         struct i915_request *request;
1098
1099         request = __i915_gem_active_peek(active);
1100         return request ? request->engine->id : -1;
1101 }
1102
1103 static void capture_bo(struct drm_i915_error_buffer *err,
1104                        struct i915_vma *vma)
1105 {
1106         struct drm_i915_gem_object *obj = vma->obj;
1107
1108         err->size = obj->base.size;
1109         err->name = obj->base.name;
1110
1111         err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
1112         err->engine = __active_get_engine_id(&obj->frontbuffer_write);
1113
1114         err->gtt_offset = vma->node.start;
1115         err->read_domains = obj->read_domains;
1116         err->write_domain = obj->write_domain;
1117         err->fence_reg = vma->fence ? vma->fence->id : -1;
1118         err->tiling = i915_gem_object_get_tiling(obj);
1119         err->dirty = obj->mm.dirty;
1120         err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
1121         err->userptr = obj->userptr.mm != NULL;
1122         err->cache_level = obj->cache_level;
1123 }
1124
1125 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
1126                             int count, struct list_head *head,
1127                             bool pinned_only)
1128 {
1129         struct i915_vma *vma;
1130         int i = 0;
1131
1132         list_for_each_entry(vma, head, vm_link) {
1133                 if (!vma->obj)
1134                         continue;
1135
1136                 if (pinned_only && !i915_vma_is_pinned(vma))
1137                         continue;
1138
1139                 capture_bo(err++, vma);
1140                 if (++i == count)
1141                         break;
1142         }
1143
1144         return i;
1145 }
1146
1147 /* Generate a semi-unique error code. The code is not meant to have meaning, The
1148  * code's only purpose is to try to prevent false duplicated bug reports by
1149  * grossly estimating a GPU error state.
1150  *
1151  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1152  * the hang if we could strip the GTT offset information from it.
1153  *
1154  * It's only a small step better than a random number in its current form.
1155  */
1156 static u32 i915_error_generate_code(struct drm_i915_private *dev_priv,
1157                                     struct i915_gpu_state *error,
1158                                     int *engine_id)
1159 {
1160         u32 error_code = 0;
1161         int i;
1162
1163         /* IPEHR would be an ideal way to detect errors, as it's the gross
1164          * measure of "the command that hung." However, has some very common
1165          * synchronization commands which almost always appear in the case
1166          * strictly a client bug. Use instdone to differentiate those some.
1167          */
1168         for (i = 0; i < I915_NUM_ENGINES; i++) {
1169                 if (error->engine[i].hangcheck_stalled) {
1170                         if (engine_id)
1171                                 *engine_id = i;
1172
1173                         return error->engine[i].ipehr ^
1174                                error->engine[i].instdone.instdone;
1175                 }
1176         }
1177
1178         return error_code;
1179 }
1180
1181 static void gem_record_fences(struct i915_gpu_state *error)
1182 {
1183         struct drm_i915_private *dev_priv = error->i915;
1184         int i;
1185
1186         if (INTEL_GEN(dev_priv) >= 6) {
1187                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1188                         error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
1189         } else if (INTEL_GEN(dev_priv) >= 4) {
1190                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1191                         error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
1192         } else {
1193                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1194                         error->fence[i] = I915_READ(FENCE_REG(i));
1195         }
1196         error->nfence = i;
1197 }
1198
1199 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
1200                                         struct drm_i915_error_engine *ee)
1201 {
1202         struct drm_i915_private *dev_priv = engine->i915;
1203
1204         ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
1205         ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1206         if (HAS_VEBOX(dev_priv))
1207                 ee->semaphore_mboxes[2] =
1208                         I915_READ(RING_SYNC_2(engine->mmio_base));
1209 }
1210
1211 static void error_record_engine_waiters(struct intel_engine_cs *engine,
1212                                         struct drm_i915_error_engine *ee)
1213 {
1214         struct intel_breadcrumbs *b = &engine->breadcrumbs;
1215         struct drm_i915_error_waiter *waiter;
1216         struct rb_node *rb;
1217         int count;
1218
1219         ee->num_waiters = 0;
1220         ee->waiters = NULL;
1221
1222         if (RB_EMPTY_ROOT(&b->waiters))
1223                 return;
1224
1225         if (!spin_trylock_irq(&b->rb_lock)) {
1226                 ee->waiters = ERR_PTR(-EDEADLK);
1227                 return;
1228         }
1229
1230         count = 0;
1231         for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
1232                 count++;
1233         spin_unlock_irq(&b->rb_lock);
1234
1235         waiter = NULL;
1236         if (count)
1237                 waiter = kmalloc_array(count,
1238                                        sizeof(struct drm_i915_error_waiter),
1239                                        GFP_ATOMIC);
1240         if (!waiter)
1241                 return;
1242
1243         if (!spin_trylock_irq(&b->rb_lock)) {
1244                 kfree(waiter);
1245                 ee->waiters = ERR_PTR(-EDEADLK);
1246                 return;
1247         }
1248
1249         ee->waiters = waiter;
1250         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1251                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1252
1253                 strcpy(waiter->comm, w->tsk->comm);
1254                 waiter->pid = w->tsk->pid;
1255                 waiter->seqno = w->seqno;
1256                 waiter++;
1257
1258                 if (++ee->num_waiters == count)
1259                         break;
1260         }
1261         spin_unlock_irq(&b->rb_lock);
1262 }
1263
1264 static void error_record_engine_registers(struct i915_gpu_state *error,
1265                                           struct intel_engine_cs *engine,
1266                                           struct drm_i915_error_engine *ee)
1267 {
1268         struct drm_i915_private *dev_priv = engine->i915;
1269
1270         if (INTEL_GEN(dev_priv) >= 6) {
1271                 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1272                 if (INTEL_GEN(dev_priv) >= 8) {
1273                         ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
1274                 } else {
1275                         gen6_record_semaphore_state(engine, ee);
1276                         ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1277                 }
1278         }
1279
1280         if (INTEL_GEN(dev_priv) >= 4) {
1281                 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1282                 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1283                 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1284                 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1285                 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1286                 if (INTEL_GEN(dev_priv) >= 8) {
1287                         ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1288                         ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1289                 }
1290                 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1291         } else {
1292                 ee->faddr = I915_READ(DMA_FADD_I8XX);
1293                 ee->ipeir = I915_READ(IPEIR);
1294                 ee->ipehr = I915_READ(IPEHR);
1295         }
1296
1297         intel_engine_get_instdone(engine, &ee->instdone);
1298
1299         ee->waiting = intel_engine_has_waiter(engine);
1300         ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1301         ee->acthd = intel_engine_get_active_head(engine);
1302         ee->seqno = intel_engine_get_seqno(engine);
1303         ee->last_seqno = intel_engine_last_submit(engine);
1304         ee->start = I915_READ_START(engine);
1305         ee->head = I915_READ_HEAD(engine);
1306         ee->tail = I915_READ_TAIL(engine);
1307         ee->ctl = I915_READ_CTL(engine);
1308         if (INTEL_GEN(dev_priv) > 2)
1309                 ee->mode = I915_READ_MODE(engine);
1310
1311         if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1312                 i915_reg_t mmio;
1313
1314                 if (IS_GEN(dev_priv, 7)) {
1315                         switch (engine->id) {
1316                         default:
1317                         case RCS:
1318                                 mmio = RENDER_HWS_PGA_GEN7;
1319                                 break;
1320                         case BCS:
1321                                 mmio = BLT_HWS_PGA_GEN7;
1322                                 break;
1323                         case VCS:
1324                                 mmio = BSD_HWS_PGA_GEN7;
1325                                 break;
1326                         case VECS:
1327                                 mmio = VEBOX_HWS_PGA_GEN7;
1328                                 break;
1329                         }
1330                 } else if (IS_GEN(engine->i915, 6)) {
1331                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1332                 } else {
1333                         /* XXX: gen8 returns to sanity */
1334                         mmio = RING_HWS_PGA(engine->mmio_base);
1335                 }
1336
1337                 ee->hws = I915_READ(mmio);
1338         }
1339
1340         ee->idle = intel_engine_is_idle(engine);
1341         ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1342         ee->hangcheck_action = engine->hangcheck.action;
1343         ee->hangcheck_stalled = engine->hangcheck.stalled;
1344         ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
1345                                                   engine);
1346
1347         if (HAS_PPGTT(dev_priv)) {
1348                 int i;
1349
1350                 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1351
1352                 if (IS_GEN(dev_priv, 6))
1353                         ee->vm_info.pp_dir_base =
1354                                 I915_READ(RING_PP_DIR_BASE_READ(engine));
1355                 else if (IS_GEN(dev_priv, 7))
1356                         ee->vm_info.pp_dir_base =
1357                                 I915_READ(RING_PP_DIR_BASE(engine));
1358                 else if (INTEL_GEN(dev_priv) >= 8)
1359                         for (i = 0; i < 4; i++) {
1360                                 ee->vm_info.pdp[i] =
1361                                         I915_READ(GEN8_RING_PDP_UDW(engine, i));
1362                                 ee->vm_info.pdp[i] <<= 32;
1363                                 ee->vm_info.pdp[i] |=
1364                                         I915_READ(GEN8_RING_PDP_LDW(engine, i));
1365                         }
1366         }
1367 }
1368
1369 static void record_request(struct i915_request *request,
1370                            struct drm_i915_error_request *erq)
1371 {
1372         struct i915_gem_context *ctx = request->gem_context;
1373
1374         erq->context = ctx->hw_id;
1375         erq->sched_attr = request->sched.attr;
1376         erq->ban_score = atomic_read(&ctx->ban_score);
1377         erq->seqno = request->global_seqno;
1378         erq->jiffies = request->emitted_jiffies;
1379         erq->start = i915_ggtt_offset(request->ring->vma);
1380         erq->head = request->head;
1381         erq->tail = request->tail;
1382
1383         rcu_read_lock();
1384         erq->pid = ctx->pid ? pid_nr(ctx->pid) : 0;
1385         rcu_read_unlock();
1386 }
1387
1388 static void engine_record_requests(struct intel_engine_cs *engine,
1389                                    struct i915_request *first,
1390                                    struct drm_i915_error_engine *ee)
1391 {
1392         struct i915_request *request;
1393         int count;
1394
1395         count = 0;
1396         request = first;
1397         list_for_each_entry_from(request, &engine->timeline.requests, link)
1398                 count++;
1399         if (!count)
1400                 return;
1401
1402         ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1403         if (!ee->requests)
1404                 return;
1405
1406         ee->num_requests = count;
1407
1408         count = 0;
1409         request = first;
1410         list_for_each_entry_from(request, &engine->timeline.requests, link) {
1411                 if (count >= ee->num_requests) {
1412                         /*
1413                          * If the ring request list was changed in
1414                          * between the point where the error request
1415                          * list was created and dimensioned and this
1416                          * point then just exit early to avoid crashes.
1417                          *
1418                          * We don't need to communicate that the
1419                          * request list changed state during error
1420                          * state capture and that the error state is
1421                          * slightly incorrect as a consequence since we
1422                          * are typically only interested in the request
1423                          * list state at the point of error state
1424                          * capture, not in any changes happening during
1425                          * the capture.
1426                          */
1427                         break;
1428                 }
1429
1430                 record_request(request, &ee->requests[count++]);
1431         }
1432         ee->num_requests = count;
1433 }
1434
1435 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1436                                           struct drm_i915_error_engine *ee)
1437 {
1438         const struct intel_engine_execlists * const execlists = &engine->execlists;
1439         unsigned int n;
1440
1441         for (n = 0; n < execlists_num_ports(execlists); n++) {
1442                 struct i915_request *rq = port_request(&execlists->port[n]);
1443
1444                 if (!rq)
1445                         break;
1446
1447                 record_request(rq, &ee->execlist[n]);
1448         }
1449
1450         ee->num_ports = n;
1451 }
1452
1453 static void record_context(struct drm_i915_error_context *e,
1454                            struct i915_gem_context *ctx)
1455 {
1456         if (ctx->pid) {
1457                 struct task_struct *task;
1458
1459                 rcu_read_lock();
1460                 task = pid_task(ctx->pid, PIDTYPE_PID);
1461                 if (task) {
1462                         strcpy(e->comm, task->comm);
1463                         e->pid = task->pid;
1464                 }
1465                 rcu_read_unlock();
1466         }
1467
1468         e->handle = ctx->user_handle;
1469         e->hw_id = ctx->hw_id;
1470         e->sched_attr = ctx->sched;
1471         e->ban_score = atomic_read(&ctx->ban_score);
1472         e->bannable = i915_gem_context_is_bannable(ctx);
1473         e->guilty = atomic_read(&ctx->guilty_count);
1474         e->active = atomic_read(&ctx->active_count);
1475 }
1476
1477 static void request_record_user_bo(struct i915_request *request,
1478                                    struct drm_i915_error_engine *ee)
1479 {
1480         struct i915_capture_list *c;
1481         struct drm_i915_error_object **bo;
1482         long count, max;
1483
1484         max = 0;
1485         for (c = request->capture_list; c; c = c->next)
1486                 max++;
1487         if (!max)
1488                 return;
1489
1490         bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
1491         if (!bo) {
1492                 /* If we can't capture everything, try to capture something. */
1493                 max = min_t(long, max, PAGE_SIZE / sizeof(*bo));
1494                 bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
1495         }
1496         if (!bo)
1497                 return;
1498
1499         count = 0;
1500         for (c = request->capture_list; c; c = c->next) {
1501                 bo[count] = i915_error_object_create(request->i915, c->vma);
1502                 if (!bo[count])
1503                         break;
1504                 if (++count == max)
1505                         break;
1506         }
1507
1508         ee->user_bo = bo;
1509         ee->user_bo_count = count;
1510 }
1511
1512 static struct drm_i915_error_object *
1513 capture_object(struct drm_i915_private *dev_priv,
1514                struct drm_i915_gem_object *obj)
1515 {
1516         if (obj && i915_gem_object_has_pages(obj)) {
1517                 struct i915_vma fake = {
1518                         .node = { .start = U64_MAX, .size = obj->base.size },
1519                         .size = obj->base.size,
1520                         .pages = obj->mm.pages,
1521                         .obj = obj,
1522                 };
1523
1524                 return i915_error_object_create(dev_priv, &fake);
1525         } else {
1526                 return NULL;
1527         }
1528 }
1529
1530 static void gem_record_rings(struct i915_gpu_state *error)
1531 {
1532         struct drm_i915_private *i915 = error->i915;
1533         struct i915_ggtt *ggtt = &i915->ggtt;
1534         int i;
1535
1536         for (i = 0; i < I915_NUM_ENGINES; i++) {
1537                 struct intel_engine_cs *engine = i915->engine[i];
1538                 struct drm_i915_error_engine *ee = &error->engine[i];
1539                 struct i915_request *request;
1540
1541                 ee->engine_id = -1;
1542
1543                 if (!engine)
1544                         continue;
1545
1546                 ee->engine_id = i;
1547
1548                 error_record_engine_registers(error, engine, ee);
1549                 error_record_engine_waiters(engine, ee);
1550                 error_record_engine_execlists(engine, ee);
1551
1552                 request = i915_gem_find_active_request(engine);
1553                 if (request) {
1554                         struct i915_gem_context *ctx = request->gem_context;
1555                         struct intel_ring *ring;
1556
1557                         ee->vm = ctx->ppgtt ? &ctx->ppgtt->vm : &ggtt->vm;
1558
1559                         record_context(&ee->context, ctx);
1560
1561                         /* We need to copy these to an anonymous buffer
1562                          * as the simplest method to avoid being overwritten
1563                          * by userspace.
1564                          */
1565                         ee->batchbuffer =
1566                                 i915_error_object_create(i915, request->batch);
1567
1568                         if (HAS_BROKEN_CS_TLB(i915))
1569                                 ee->wa_batchbuffer =
1570                                         i915_error_object_create(i915,
1571                                                                  i915->gt.scratch);
1572                         request_record_user_bo(request, ee);
1573
1574                         ee->ctx =
1575                                 i915_error_object_create(i915,
1576                                                          request->hw_context->state);
1577
1578                         error->simulated |=
1579                                 i915_gem_context_no_error_capture(ctx);
1580
1581                         ee->rq_head = request->head;
1582                         ee->rq_post = request->postfix;
1583                         ee->rq_tail = request->tail;
1584
1585                         ring = request->ring;
1586                         ee->cpu_ring_head = ring->head;
1587                         ee->cpu_ring_tail = ring->tail;
1588                         ee->ringbuffer =
1589                                 i915_error_object_create(i915, ring->vma);
1590
1591                         engine_record_requests(engine, request, ee);
1592                 }
1593
1594                 ee->hws_page =
1595                         i915_error_object_create(i915,
1596                                                  engine->status_page.vma);
1597
1598                 ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma);
1599
1600                 ee->default_state = capture_object(i915, engine->default_state);
1601         }
1602 }
1603
1604 static void gem_capture_vm(struct i915_gpu_state *error,
1605                            struct i915_address_space *vm,
1606                            int idx)
1607 {
1608         struct drm_i915_error_buffer *active_bo;
1609         struct i915_vma *vma;
1610         int count;
1611
1612         count = 0;
1613         list_for_each_entry(vma, &vm->active_list, vm_link)
1614                 count++;
1615
1616         active_bo = NULL;
1617         if (count)
1618                 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1619         if (active_bo)
1620                 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1621         else
1622                 count = 0;
1623
1624         error->active_vm[idx] = vm;
1625         error->active_bo[idx] = active_bo;
1626         error->active_bo_count[idx] = count;
1627 }
1628
1629 static void capture_active_buffers(struct i915_gpu_state *error)
1630 {
1631         int cnt = 0, i, j;
1632
1633         BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1634         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1635         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1636
1637         /* Scan each engine looking for unique active contexts/vm */
1638         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1639                 struct drm_i915_error_engine *ee = &error->engine[i];
1640                 bool found;
1641
1642                 if (!ee->vm)
1643                         continue;
1644
1645                 found = false;
1646                 for (j = 0; j < i && !found; j++)
1647                         found = error->engine[j].vm == ee->vm;
1648                 if (!found)
1649                         gem_capture_vm(error, ee->vm, cnt++);
1650         }
1651 }
1652
1653 static void capture_pinned_buffers(struct i915_gpu_state *error)
1654 {
1655         struct i915_address_space *vm = &error->i915->ggtt.vm;
1656         struct drm_i915_error_buffer *bo;
1657         struct i915_vma *vma;
1658         int count_inactive, count_active;
1659
1660         count_inactive = 0;
1661         list_for_each_entry(vma, &vm->inactive_list, vm_link)
1662                 count_inactive++;
1663
1664         count_active = 0;
1665         list_for_each_entry(vma, &vm->active_list, vm_link)
1666                 count_active++;
1667
1668         bo = NULL;
1669         if (count_inactive + count_active)
1670                 bo = kcalloc(count_inactive + count_active,
1671                              sizeof(*bo), GFP_ATOMIC);
1672         if (!bo)
1673                 return;
1674
1675         count_inactive = capture_error_bo(bo, count_inactive,
1676                                           &vm->active_list, true);
1677         count_active = capture_error_bo(bo + count_inactive, count_active,
1678                                         &vm->inactive_list, true);
1679         error->pinned_bo_count = count_inactive + count_active;
1680         error->pinned_bo = bo;
1681 }
1682
1683 static void capture_uc_state(struct i915_gpu_state *error)
1684 {
1685         struct drm_i915_private *i915 = error->i915;
1686         struct i915_error_uc *error_uc = &error->uc;
1687
1688         /* Capturing uC state won't be useful if there is no GuC */
1689         if (!error->device_info.has_guc)
1690                 return;
1691
1692         error_uc->guc_fw = i915->guc.fw;
1693         error_uc->huc_fw = i915->huc.fw;
1694
1695         /* Non-default firmware paths will be specified by the modparam.
1696          * As modparams are generally accesible from the userspace make
1697          * explicit copies of the firmware paths.
1698          */
1699         error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC);
1700         error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC);
1701         error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma);
1702 }
1703
1704 /* Capture all registers which don't fit into another category. */
1705 static void capture_reg_state(struct i915_gpu_state *error)
1706 {
1707         struct drm_i915_private *dev_priv = error->i915;
1708         int i;
1709
1710         /* General organization
1711          * 1. Registers specific to a single generation
1712          * 2. Registers which belong to multiple generations
1713          * 3. Feature specific registers.
1714          * 4. Everything else
1715          * Please try to follow the order.
1716          */
1717
1718         /* 1: Registers specific to a single generation */
1719         if (IS_VALLEYVIEW(dev_priv)) {
1720                 error->gtier[0] = I915_READ(GTIER);
1721                 error->ier = I915_READ(VLV_IER);
1722                 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1723         }
1724
1725         if (IS_GEN(dev_priv, 7))
1726                 error->err_int = I915_READ(GEN7_ERR_INT);
1727
1728         if (INTEL_GEN(dev_priv) >= 8) {
1729                 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1730                 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1731         }
1732
1733         if (IS_GEN(dev_priv, 6)) {
1734                 error->forcewake = I915_READ_FW(FORCEWAKE);
1735                 error->gab_ctl = I915_READ(GAB_CTL);
1736                 error->gfx_mode = I915_READ(GFX_MODE);
1737         }
1738
1739         /* 2: Registers which belong to multiple generations */
1740         if (INTEL_GEN(dev_priv) >= 7)
1741                 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1742
1743         if (INTEL_GEN(dev_priv) >= 6) {
1744                 error->derrmr = I915_READ(DERRMR);
1745                 error->error = I915_READ(ERROR_GEN6);
1746                 error->done_reg = I915_READ(DONE_REG);
1747         }
1748
1749         if (INTEL_GEN(dev_priv) >= 5)
1750                 error->ccid = I915_READ(CCID);
1751
1752         /* 3: Feature specific registers */
1753         if (IS_GEN_RANGE(dev_priv, 6, 7)) {
1754                 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1755                 error->gac_eco = I915_READ(GAC_ECO_BITS);
1756         }
1757
1758         /* 4: Everything else */
1759         if (INTEL_GEN(dev_priv) >= 11) {
1760                 error->ier = I915_READ(GEN8_DE_MISC_IER);
1761                 error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
1762                 error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
1763                 error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE);
1764                 error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1765                 error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE);
1766                 error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE);
1767                 error->ngtier = 6;
1768         } else if (INTEL_GEN(dev_priv) >= 8) {
1769                 error->ier = I915_READ(GEN8_DE_MISC_IER);
1770                 for (i = 0; i < 4; i++)
1771                         error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1772                 error->ngtier = 4;
1773         } else if (HAS_PCH_SPLIT(dev_priv)) {
1774                 error->ier = I915_READ(DEIER);
1775                 error->gtier[0] = I915_READ(GTIER);
1776                 error->ngtier = 1;
1777         } else if (IS_GEN(dev_priv, 2)) {
1778                 error->ier = I915_READ16(IER);
1779         } else if (!IS_VALLEYVIEW(dev_priv)) {
1780                 error->ier = I915_READ(IER);
1781         }
1782         error->eir = I915_READ(EIR);
1783         error->pgtbl_er = I915_READ(PGTBL_ER);
1784 }
1785
1786 static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1787                                    struct i915_gpu_state *error,
1788                                    u32 engine_mask,
1789                                    const char *error_msg)
1790 {
1791         u32 ecode;
1792         int engine_id = -1, len;
1793
1794         ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1795
1796         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1797                         "GPU HANG: ecode %d:%d:0x%08x",
1798                         INTEL_GEN(dev_priv), engine_id, ecode);
1799
1800         if (engine_id != -1 && error->engine[engine_id].context.pid)
1801                 len += scnprintf(error->error_msg + len,
1802                                  sizeof(error->error_msg) - len,
1803                                  ", in %s [%d]",
1804                                  error->engine[engine_id].context.comm,
1805                                  error->engine[engine_id].context.pid);
1806
1807         scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1808                   ", reason: %s, action: %s",
1809                   error_msg,
1810                   engine_mask ? "reset" : "continue");
1811 }
1812
1813 static void capture_gen_state(struct i915_gpu_state *error)
1814 {
1815         struct drm_i915_private *i915 = error->i915;
1816
1817         error->awake = i915->gt.awake;
1818         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1819         error->suspended = i915->runtime_pm.suspended;
1820
1821         error->iommu = -1;
1822 #ifdef CONFIG_INTEL_IOMMU
1823         error->iommu = intel_iommu_gfx_mapped;
1824 #endif
1825         error->reset_count = i915_reset_count(&i915->gpu_error);
1826         error->suspend_count = i915->suspend_count;
1827
1828         memcpy(&error->device_info,
1829                INTEL_INFO(i915),
1830                sizeof(error->device_info));
1831         memcpy(&error->runtime_info,
1832                RUNTIME_INFO(i915),
1833                sizeof(error->runtime_info));
1834         error->driver_caps = i915->caps;
1835 }
1836
1837 static void capture_params(struct i915_gpu_state *error)
1838 {
1839         i915_params_copy(&error->params, &i915_modparams);
1840 }
1841
1842 static unsigned long capture_find_epoch(const struct i915_gpu_state *error)
1843 {
1844         unsigned long epoch = error->capture;
1845         int i;
1846
1847         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1848                 const struct drm_i915_error_engine *ee = &error->engine[i];
1849
1850                 if (ee->hangcheck_stalled &&
1851                     time_before(ee->hangcheck_timestamp, epoch))
1852                         epoch = ee->hangcheck_timestamp;
1853         }
1854
1855         return epoch;
1856 }
1857
1858 static void capture_finish(struct i915_gpu_state *error)
1859 {
1860         struct i915_ggtt *ggtt = &error->i915->ggtt;
1861         const u64 slot = ggtt->error_capture.start;
1862
1863         ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1864 }
1865
1866 static int capture(void *data)
1867 {
1868         struct i915_gpu_state *error = data;
1869
1870         error->time = ktime_get_real();
1871         error->boottime = ktime_get_boottime();
1872         error->uptime = ktime_sub(ktime_get(),
1873                                   error->i915->gt.last_init_time);
1874         error->capture = jiffies;
1875
1876         capture_params(error);
1877         capture_gen_state(error);
1878         capture_uc_state(error);
1879         capture_reg_state(error);
1880         gem_record_fences(error);
1881         gem_record_rings(error);
1882         capture_active_buffers(error);
1883         capture_pinned_buffers(error);
1884
1885         error->overlay = intel_overlay_capture_error_state(error->i915);
1886         error->display = intel_display_capture_error_state(error->i915);
1887
1888         error->epoch = capture_find_epoch(error);
1889
1890         capture_finish(error);
1891         return 0;
1892 }
1893
1894 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1895
1896 struct i915_gpu_state *
1897 i915_capture_gpu_state(struct drm_i915_private *i915)
1898 {
1899         struct i915_gpu_state *error;
1900
1901         /* Check if GPU capture has been disabled */
1902         error = READ_ONCE(i915->gpu_error.first_error);
1903         if (IS_ERR(error))
1904                 return error;
1905
1906         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1907         if (!error) {
1908                 i915_disable_error_state(i915, -ENOMEM);
1909                 return ERR_PTR(-ENOMEM);
1910         }
1911
1912         kref_init(&error->ref);
1913         error->i915 = i915;
1914
1915         stop_machine(capture, error, NULL);
1916
1917         return error;
1918 }
1919
1920 /**
1921  * i915_capture_error_state - capture an error record for later analysis
1922  * @i915: i915 device
1923  * @engine_mask: the mask of engines triggering the hang
1924  * @error_msg: a message to insert into the error capture header
1925  *
1926  * Should be called when an error is detected (either a hang or an error
1927  * interrupt) to capture error state from the time of the error.  Fills
1928  * out a structure which becomes available in debugfs for user level tools
1929  * to pick up.
1930  */
1931 void i915_capture_error_state(struct drm_i915_private *i915,
1932                               u32 engine_mask,
1933                               const char *error_msg)
1934 {
1935         static bool warned;
1936         struct i915_gpu_state *error;
1937         unsigned long flags;
1938
1939         if (!i915_modparams.error_capture)
1940                 return;
1941
1942         if (READ_ONCE(i915->gpu_error.first_error))
1943                 return;
1944
1945         error = i915_capture_gpu_state(i915);
1946         if (IS_ERR(error))
1947                 return;
1948
1949         i915_error_capture_msg(i915, error, engine_mask, error_msg);
1950         DRM_INFO("%s\n", error->error_msg);
1951
1952         if (!error->simulated) {
1953                 spin_lock_irqsave(&i915->gpu_error.lock, flags);
1954                 if (!i915->gpu_error.first_error) {
1955                         i915->gpu_error.first_error = error;
1956                         error = NULL;
1957                 }
1958                 spin_unlock_irqrestore(&i915->gpu_error.lock, flags);
1959         }
1960
1961         if (error) {
1962                 __i915_gpu_state_free(&error->ref);
1963                 return;
1964         }
1965
1966         if (!warned &&
1967             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1968                 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1969                 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1970                 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1971                 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1972                 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1973                          i915->drm.primary->index);
1974                 warned = true;
1975         }
1976 }
1977
1978 struct i915_gpu_state *
1979 i915_first_error_state(struct drm_i915_private *i915)
1980 {
1981         struct i915_gpu_state *error;
1982
1983         spin_lock_irq(&i915->gpu_error.lock);
1984         error = i915->gpu_error.first_error;
1985         if (!IS_ERR_OR_NULL(error))
1986                 i915_gpu_state_get(error);
1987         spin_unlock_irq(&i915->gpu_error.lock);
1988
1989         return error;
1990 }
1991
1992 void i915_reset_error_state(struct drm_i915_private *i915)
1993 {
1994         struct i915_gpu_state *error;
1995
1996         spin_lock_irq(&i915->gpu_error.lock);
1997         error = i915->gpu_error.first_error;
1998         if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
1999                 i915->gpu_error.first_error = NULL;
2000         spin_unlock_irq(&i915->gpu_error.lock);
2001
2002         if (!IS_ERR_OR_NULL(error))
2003                 i915_gpu_state_put(error);
2004 }
2005
2006 void i915_disable_error_state(struct drm_i915_private *i915, int err)
2007 {
2008         spin_lock_irq(&i915->gpu_error.lock);
2009         if (!i915->gpu_error.first_error)
2010                 i915->gpu_error.first_error = ERR_PTR(err);
2011         spin_unlock_irq(&i915->gpu_error.lock);
2012 }