2 * Copyright (c) 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
30 #include <linux/ascii85.h>
31 #include <linux/nmi.h>
32 #include <linux/pagevec.h>
33 #include <linux/scatterlist.h>
34 #include <linux/utsname.h>
35 #include <linux/zlib.h>
37 #include <drm/drm_print.h>
39 #include "display/intel_dmc.h"
40 #include "display/intel_overlay.h"
42 #include "gem/i915_gem_context.h"
43 #include "gem/i915_gem_lmem.h"
44 #include "gt/intel_gt.h"
45 #include "gt/intel_gt_pm.h"
48 #include "i915_gpu_error.h"
49 #include "i915_memcpy.h"
50 #include "i915_scatterlist.h"
52 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
53 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
55 static void __sg_set_buf(struct scatterlist *sg,
56 void *addr, unsigned int len, loff_t it)
58 sg->page_link = (unsigned long)virt_to_page(addr);
59 sg->offset = offset_in_page(addr);
64 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
69 if (e->bytes + len + 1 <= e->size)
73 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
79 if (e->cur == e->end) {
80 struct scatterlist *sgl;
82 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
92 (unsigned long)sgl | SG_CHAIN;
98 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
101 e->size = ALIGN(len + 1, SZ_64K);
102 e->buf = kmalloc(e->size, ALLOW_FAIL);
104 e->size = PAGE_ALIGN(len + 1);
105 e->buf = kmalloc(e->size, GFP_KERNEL);
116 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
117 const char *fmt, va_list args)
126 len = vsnprintf(NULL, 0, fmt, ap);
133 if (!__i915_error_grow(e, len))
136 GEM_BUG_ON(e->bytes >= e->size);
137 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
145 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
153 if (!__i915_error_grow(e, len))
156 GEM_BUG_ON(e->bytes + len > e->size);
157 memcpy(e->buf + e->bytes, str, len);
161 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
162 #define err_puts(e, s) i915_error_puts(e, s)
164 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
166 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
169 static inline struct drm_printer
170 i915_error_printer(struct drm_i915_error_state_buf *e)
172 struct drm_printer p = {
173 .printfn = __i915_printfn_error,
179 /* single threaded page allocator with a reserved stash for emergencies */
180 static void pool_fini(struct pagevec *pv)
185 static int pool_refill(struct pagevec *pv, gfp_t gfp)
187 while (pagevec_space(pv)) {
200 static int pool_init(struct pagevec *pv, gfp_t gfp)
206 err = pool_refill(pv, gfp);
213 static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
218 if (!p && pagevec_count(pv))
219 p = pv->pages[--pv->nr];
221 return p ? page_address(p) : NULL;
224 static void pool_free(struct pagevec *pv, void *addr)
226 struct page *p = virt_to_page(addr);
228 if (pagevec_space(pv))
234 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
236 struct i915_vma_compress {
238 struct z_stream_s zstream;
242 static bool compress_init(struct i915_vma_compress *c)
244 struct z_stream_s *zstream = &c->zstream;
246 if (pool_init(&c->pool, ALLOW_FAIL))
250 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
252 if (!zstream->workspace) {
258 if (i915_has_memcpy_from_wc())
259 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
264 static bool compress_start(struct i915_vma_compress *c)
266 struct z_stream_s *zstream = &c->zstream;
267 void *workspace = zstream->workspace;
269 memset(zstream, 0, sizeof(*zstream));
270 zstream->workspace = workspace;
272 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
275 static void *compress_next_page(struct i915_vma_compress *c,
276 struct i915_vma_coredump *dst)
280 if (dst->page_count >= dst->num_pages)
281 return ERR_PTR(-ENOSPC);
283 page = pool_alloc(&c->pool, ALLOW_FAIL);
285 return ERR_PTR(-ENOMEM);
287 return dst->pages[dst->page_count++] = page;
290 static int compress_page(struct i915_vma_compress *c,
292 struct i915_vma_coredump *dst,
295 struct z_stream_s *zstream = &c->zstream;
297 zstream->next_in = src;
298 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
299 zstream->next_in = c->tmp;
300 zstream->avail_in = PAGE_SIZE;
303 if (zstream->avail_out == 0) {
304 zstream->next_out = compress_next_page(c, dst);
305 if (IS_ERR(zstream->next_out))
306 return PTR_ERR(zstream->next_out);
308 zstream->avail_out = PAGE_SIZE;
311 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
315 } while (zstream->avail_in);
317 /* Fallback to uncompressed if we increase size? */
318 if (0 && zstream->total_out > zstream->total_in)
324 static int compress_flush(struct i915_vma_compress *c,
325 struct i915_vma_coredump *dst)
327 struct z_stream_s *zstream = &c->zstream;
330 switch (zlib_deflate(zstream, Z_FINISH)) {
331 case Z_OK: /* more space requested */
332 zstream->next_out = compress_next_page(c, dst);
333 if (IS_ERR(zstream->next_out))
334 return PTR_ERR(zstream->next_out);
336 zstream->avail_out = PAGE_SIZE;
342 default: /* any error */
348 memset(zstream->next_out, 0, zstream->avail_out);
349 dst->unused = zstream->avail_out;
353 static void compress_finish(struct i915_vma_compress *c)
355 zlib_deflateEnd(&c->zstream);
358 static void compress_fini(struct i915_vma_compress *c)
360 kfree(c->zstream.workspace);
362 pool_free(&c->pool, c->tmp);
366 static void err_compression_marker(struct drm_i915_error_state_buf *m)
373 struct i915_vma_compress {
377 static bool compress_init(struct i915_vma_compress *c)
379 return pool_init(&c->pool, ALLOW_FAIL) == 0;
382 static bool compress_start(struct i915_vma_compress *c)
387 static int compress_page(struct i915_vma_compress *c,
389 struct i915_vma_coredump *dst,
394 ptr = pool_alloc(&c->pool, ALLOW_FAIL);
398 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
399 memcpy(ptr, src, PAGE_SIZE);
400 dst->pages[dst->page_count++] = ptr;
406 static int compress_flush(struct i915_vma_compress *c,
407 struct i915_vma_coredump *dst)
412 static void compress_finish(struct i915_vma_compress *c)
416 static void compress_fini(struct i915_vma_compress *c)
421 static void err_compression_marker(struct drm_i915_error_state_buf *m)
428 static void error_print_instdone(struct drm_i915_error_state_buf *m,
429 const struct intel_engine_coredump *ee)
431 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu;
436 err_printf(m, " INSTDONE: 0x%08x\n",
437 ee->instdone.instdone);
439 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3)
442 err_printf(m, " SC_INSTDONE: 0x%08x\n",
443 ee->instdone.slice_common);
445 if (GRAPHICS_VER(m->i915) <= 6)
448 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 50)) {
449 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice)
450 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
452 ee->instdone.sampler[slice][subslice]);
454 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice)
455 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
457 ee->instdone.row[slice][subslice]);
459 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
460 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
462 ee->instdone.sampler[slice][subslice]);
464 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
465 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
467 ee->instdone.row[slice][subslice]);
470 if (GRAPHICS_VER(m->i915) < 12)
473 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) {
474 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice)
475 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n",
477 ee->instdone.geom_svg[slice][subslice]);
480 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n",
481 ee->instdone.slice_common_extra[0]);
482 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n",
483 ee->instdone.slice_common_extra[1]);
486 static void error_print_request(struct drm_i915_error_state_buf *m,
488 const struct i915_request_coredump *erq)
493 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n",
494 prefix, erq->pid, erq->context, erq->seqno,
495 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
496 &erq->flags) ? "!" : "",
497 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
498 &erq->flags) ? "+" : "",
499 erq->sched_attr.priority,
500 erq->head, erq->tail);
503 static void error_print_context(struct drm_i915_error_state_buf *m,
505 const struct i915_gem_context_coredump *ctx)
507 const u32 period = m->i915->gt.clock_period_ns;
509 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n",
510 header, ctx->comm, ctx->pid, ctx->sched_attr.priority,
511 ctx->guilty, ctx->active,
512 ctx->total_runtime * period,
513 mul_u32_u32(ctx->avg_runtime, period));
516 static struct i915_vma_coredump *
517 __find_vma(struct i915_vma_coredump *vma, const char *name)
520 if (strcmp(vma->name, name) == 0)
528 static struct i915_vma_coredump *
529 find_batch(const struct intel_engine_coredump *ee)
531 return __find_vma(ee->vma, "batch");
534 static void error_print_engine(struct drm_i915_error_state_buf *m,
535 const struct intel_engine_coredump *ee)
537 struct i915_vma_coredump *batch;
540 err_printf(m, "%s command stream:\n", ee->engine->name);
541 err_printf(m, " CCID: 0x%08x\n", ee->ccid);
542 err_printf(m, " START: 0x%08x\n", ee->start);
543 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
544 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",
545 ee->tail, ee->rq_post, ee->rq_tail);
546 err_printf(m, " CTL: 0x%08x\n", ee->ctl);
547 err_printf(m, " MODE: 0x%08x\n", ee->mode);
548 err_printf(m, " HWS: 0x%08x\n", ee->hws);
549 err_printf(m, " ACTHD: 0x%08x %08x\n",
550 (u32)(ee->acthd>>32), (u32)ee->acthd);
551 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
552 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
553 err_printf(m, " ESR: 0x%08x\n", ee->esr);
555 error_print_instdone(m, ee);
557 batch = find_batch(ee);
559 u64 start = batch->gtt_offset;
560 u64 end = start + batch->gtt_size;
562 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",
563 upper_32_bits(start), lower_32_bits(start),
564 upper_32_bits(end), lower_32_bits(end));
566 if (GRAPHICS_VER(m->i915) >= 4) {
567 err_printf(m, " BBADDR: 0x%08x_%08x\n",
568 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
569 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
570 err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
572 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
573 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
574 lower_32_bits(ee->faddr));
575 if (GRAPHICS_VER(m->i915) >= 6) {
576 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
577 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
579 if (HAS_PPGTT(m->i915)) {
580 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
582 if (GRAPHICS_VER(m->i915) >= 8) {
584 for (i = 0; i < 4; i++)
585 err_printf(m, " PDP%d: 0x%016llx\n",
586 i, ee->vm_info.pdp[i]);
588 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
589 ee->vm_info.pp_dir_base);
592 err_printf(m, " hung: %u\n", ee->hung);
593 err_printf(m, " engine reset count: %u\n", ee->reset_count);
595 for (n = 0; n < ee->num_ports; n++) {
596 err_printf(m, " ELSP[%d]:", n);
597 error_print_request(m, " ", &ee->execlist[n]);
600 error_print_context(m, " Active context: ", &ee->context);
603 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
608 i915_error_vprintf(e, f, args);
612 static void print_error_vma(struct drm_i915_error_state_buf *m,
613 const struct intel_engine_cs *engine,
614 const struct i915_vma_coredump *vma)
616 char out[ASCII85_BUFSZ];
622 err_printf(m, "%s --- %s = 0x%08x %08x\n",
623 engine ? engine->name : "global", vma->name,
624 upper_32_bits(vma->gtt_offset),
625 lower_32_bits(vma->gtt_offset));
627 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)
628 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);
630 err_compression_marker(m);
631 for (page = 0; page < vma->page_count; page++) {
635 if (page == vma->page_count - 1)
637 len = ascii85_encode_len(len);
639 for (i = 0; i < len; i++)
640 err_puts(m, ascii85_encode(vma->pages[page][i], out));
645 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
646 struct i915_gpu_coredump *error)
648 struct drm_printer p = i915_error_printer(m);
650 intel_device_info_print_static(&error->device_info, &p);
651 intel_device_info_print_runtime(&error->runtime_info, &p);
652 intel_driver_caps_print(&error->driver_caps, &p);
655 static void err_print_params(struct drm_i915_error_state_buf *m,
656 const struct i915_params *params)
658 struct drm_printer p = i915_error_printer(m);
660 i915_params_dump(params, &p);
663 static void err_print_pciid(struct drm_i915_error_state_buf *m,
664 struct drm_i915_private *i915)
666 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
668 err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
669 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
670 err_printf(m, "PCI Subsystem: %04x:%04x\n",
671 pdev->subsystem_vendor,
672 pdev->subsystem_device);
675 static void err_print_uc(struct drm_i915_error_state_buf *m,
676 const struct intel_uc_coredump *error_uc)
678 struct drm_printer p = i915_error_printer(m);
680 intel_uc_fw_dump(&error_uc->guc_fw, &p);
681 intel_uc_fw_dump(&error_uc->huc_fw, &p);
682 print_error_vma(m, NULL, error_uc->guc_log);
685 static void err_free_sgl(struct scatterlist *sgl)
688 struct scatterlist *sg;
690 for (sg = sgl; !sg_is_chain(sg); sg++) {
696 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
697 free_page((unsigned long)sgl);
702 static void err_print_gt_info(struct drm_i915_error_state_buf *m,
703 struct intel_gt_coredump *gt)
705 struct drm_printer p = i915_error_printer(m);
707 intel_gt_info_print(>->info, &p);
708 intel_sseu_print_topology(>->info.sseu, &p);
711 static void err_print_gt(struct drm_i915_error_state_buf *m,
712 struct intel_gt_coredump *gt)
714 const struct intel_engine_coredump *ee;
717 err_printf(m, "GT awake: %s\n", yesno(gt->awake));
718 err_printf(m, "EIR: 0x%08x\n", gt->eir);
719 err_printf(m, "IER: 0x%08x\n", gt->ier);
720 for (i = 0; i < gt->ngtier; i++)
721 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
722 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
723 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
724 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
726 for (i = 0; i < gt->nfence; i++)
727 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]);
729 if (IS_GRAPHICS_VER(m->i915, 6, 11)) {
730 err_printf(m, "ERROR: 0x%08x\n", gt->error);
731 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
734 if (GRAPHICS_VER(m->i915) >= 8)
735 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
736 gt->fault_data1, gt->fault_data0);
738 if (GRAPHICS_VER(m->i915) == 7)
739 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
741 if (IS_GRAPHICS_VER(m->i915, 8, 11))
742 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
744 if (GRAPHICS_VER(m->i915) == 12)
745 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
747 if (GRAPHICS_VER(m->i915) >= 12) {
750 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
752 * SFC_DONE resides in the VD forcewake domain, so it
753 * only exists if the corresponding VCS engine is
756 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
757 !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
760 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i,
764 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done);
767 for (ee = gt->engine; ee; ee = ee->next) {
768 const struct i915_vma_coredump *vma;
770 error_print_engine(m, ee);
771 for (vma = ee->vma; vma; vma = vma->next)
772 print_error_vma(m, ee->engine, vma);
776 err_print_uc(m, gt->uc);
778 err_print_gt_info(m, gt);
781 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
782 struct i915_gpu_coredump *error)
784 const struct intel_engine_coredump *ee;
785 struct timespec64 ts;
787 if (*error->error_msg)
788 err_printf(m, "%s\n", error->error_msg);
789 err_printf(m, "Kernel: %s %s\n",
790 init_utsname()->release,
791 init_utsname()->machine);
792 err_printf(m, "Driver: %s\n", DRIVER_DATE);
793 ts = ktime_to_timespec64(error->time);
794 err_printf(m, "Time: %lld s %ld us\n",
795 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
796 ts = ktime_to_timespec64(error->boottime);
797 err_printf(m, "Boottime: %lld s %ld us\n",
798 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
799 ts = ktime_to_timespec64(error->uptime);
800 err_printf(m, "Uptime: %lld s %ld us\n",
801 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
802 err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
803 error->capture, jiffies_to_msecs(jiffies - error->capture));
805 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
806 err_printf(m, "Active process (on ring %s): %s [%d]\n",
811 err_printf(m, "Reset count: %u\n", error->reset_count);
812 err_printf(m, "Suspend count: %u\n", error->suspend_count);
813 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
814 err_printf(m, "Subplatform: 0x%x\n",
815 intel_subplatform(&error->runtime_info,
816 error->device_info.platform));
817 err_print_pciid(m, m->i915);
819 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
821 if (HAS_DMC(m->i915)) {
822 struct intel_dmc *dmc = &m->i915->dmc;
824 err_printf(m, "DMC loaded: %s\n",
825 yesno(intel_dmc_has_payload(m->i915) != 0));
826 err_printf(m, "DMC fw version: %d.%d\n",
827 DMC_VERSION_MAJOR(dmc->version),
828 DMC_VERSION_MINOR(dmc->version));
831 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
832 err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
835 err_print_gt(m, error->gt);
838 intel_overlay_print_error_state(m, error->overlay);
840 err_print_capabilities(m, error);
841 err_print_params(m, &error->params);
844 static int err_print_to_sgl(struct i915_gpu_coredump *error)
846 struct drm_i915_error_state_buf m;
849 return PTR_ERR(error);
851 if (READ_ONCE(error->sgl))
854 memset(&m, 0, sizeof(m));
855 m.i915 = error->i915;
857 __err_print_to_sgl(&m, error);
860 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
865 GEM_BUG_ON(m.end < m.cur);
866 sg_mark_end(m.cur - 1);
868 GEM_BUG_ON(m.sgl && !m.cur);
875 if (cmpxchg(&error->sgl, NULL, m.sgl))
881 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
882 char *buf, loff_t off, size_t rem)
884 struct scatterlist *sg;
892 err = err_print_to_sgl(error);
896 sg = READ_ONCE(error->fit);
897 if (!sg || off < sg->dma_address)
902 pos = sg->dma_address;
907 if (sg_is_chain(sg)) {
908 sg = sg_chain_ptr(sg);
909 GEM_BUG_ON(sg_is_chain(sg));
913 if (pos + len <= off) {
920 GEM_BUG_ON(off - pos > len);
927 GEM_BUG_ON(!len || len > sg->length);
929 memcpy(buf, page_address(sg_page(sg)) + start, len);
937 WRITE_ONCE(error->fit, sg);
940 } while (!sg_is_last(sg++));
945 static void i915_vma_coredump_free(struct i915_vma_coredump *vma)
948 struct i915_vma_coredump *next = vma->next;
951 for (page = 0; page < vma->page_count; page++)
952 free_page((unsigned long)vma->pages[page]);
959 static void cleanup_params(struct i915_gpu_coredump *error)
961 i915_params_free(&error->params);
964 static void cleanup_uc(struct intel_uc_coredump *uc)
966 kfree(uc->guc_fw.path);
967 kfree(uc->huc_fw.path);
968 i915_vma_coredump_free(uc->guc_log);
973 static void cleanup_gt(struct intel_gt_coredump *gt)
976 struct intel_engine_coredump *ee = gt->engine;
978 gt->engine = ee->next;
980 i915_vma_coredump_free(ee->vma);
990 void __i915_gpu_coredump_free(struct kref *error_ref)
992 struct i915_gpu_coredump *error =
993 container_of(error_ref, typeof(*error), ref);
996 struct intel_gt_coredump *gt = error->gt;
998 error->gt = gt->next;
1002 kfree(error->overlay);
1004 cleanup_params(error);
1006 err_free_sgl(error->sgl);
1010 static struct i915_vma_coredump *
1011 i915_vma_coredump_create(const struct intel_gt *gt,
1012 const struct i915_vma *vma,
1014 struct i915_vma_compress *compress)
1016 struct i915_ggtt *ggtt = gt->ggtt;
1017 const u64 slot = ggtt->error_capture.start;
1018 struct i915_vma_coredump *dst;
1019 unsigned long num_pages;
1020 struct sgt_iter iter;
1025 if (!vma || !vma->pages || !compress)
1028 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
1029 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
1030 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL);
1034 if (!compress_start(compress)) {
1039 strcpy(dst->name, name);
1042 dst->gtt_offset = vma->node.start;
1043 dst->gtt_size = vma->node.size;
1044 dst->gtt_page_sizes = vma->page_sizes.gtt;
1045 dst->num_pages = num_pages;
1046 dst->page_count = 0;
1050 if (drm_mm_node_allocated(&ggtt->error_capture)) {
1054 for_each_sgt_daddr(dma, iter, vma->pages) {
1055 mutex_lock(&ggtt->error_mutex);
1056 ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1057 I915_CACHE_NONE, 0);
1060 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
1061 ret = compress_page(compress,
1062 (void __force *)s, dst,
1064 io_mapping_unmap(s);
1067 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1068 mutex_unlock(&ggtt->error_mutex);
1072 } else if (__i915_gem_object_is_lmem(vma->obj)) {
1073 struct intel_memory_region *mem = vma->obj->mm.region;
1076 for_each_sgt_daddr(dma, iter, vma->pages) {
1079 s = io_mapping_map_wc(&mem->iomap,
1080 dma - mem->region.start,
1082 ret = compress_page(compress,
1083 (void __force *)s, dst,
1085 io_mapping_unmap(s);
1092 for_each_sgt_page(page, iter, vma->pages) {
1095 drm_clflush_pages(&page, 1);
1098 ret = compress_page(compress, s, dst, false);
1101 drm_clflush_pages(&page, 1);
1108 if (ret || compress_flush(compress, dst)) {
1109 while (dst->page_count--)
1110 pool_free(&compress->pool, dst->pages[dst->page_count]);
1114 compress_finish(compress);
1119 static void gt_record_fences(struct intel_gt_coredump *gt)
1121 struct i915_ggtt *ggtt = gt->_gt->ggtt;
1122 struct intel_uncore *uncore = gt->_gt->uncore;
1125 if (GRAPHICS_VER(uncore->i915) >= 6) {
1126 for (i = 0; i < ggtt->num_fences; i++)
1128 intel_uncore_read64(uncore,
1129 FENCE_REG_GEN6_LO(i));
1130 } else if (GRAPHICS_VER(uncore->i915) >= 4) {
1131 for (i = 0; i < ggtt->num_fences; i++)
1133 intel_uncore_read64(uncore,
1134 FENCE_REG_965_LO(i));
1136 for (i = 0; i < ggtt->num_fences; i++)
1138 intel_uncore_read(uncore, FENCE_REG(i));
1143 static void engine_record_registers(struct intel_engine_coredump *ee)
1145 const struct intel_engine_cs *engine = ee->engine;
1146 struct drm_i915_private *i915 = engine->i915;
1148 if (GRAPHICS_VER(i915) >= 6) {
1149 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1151 if (GRAPHICS_VER(i915) >= 12)
1152 ee->fault_reg = intel_uncore_read(engine->uncore,
1153 GEN12_RING_FAULT_REG);
1154 else if (GRAPHICS_VER(i915) >= 8)
1155 ee->fault_reg = intel_uncore_read(engine->uncore,
1156 GEN8_RING_FAULT_REG);
1158 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1161 if (GRAPHICS_VER(i915) >= 4) {
1162 ee->esr = ENGINE_READ(engine, RING_ESR);
1163 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1164 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1165 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1166 ee->instps = ENGINE_READ(engine, RING_INSTPS);
1167 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1168 ee->ccid = ENGINE_READ(engine, CCID);
1169 if (GRAPHICS_VER(i915) >= 8) {
1170 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1171 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1173 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1175 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1176 ee->ipeir = ENGINE_READ(engine, IPEIR);
1177 ee->ipehr = ENGINE_READ(engine, IPEHR);
1180 intel_engine_get_instdone(engine, &ee->instdone);
1182 ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1183 ee->acthd = intel_engine_get_active_head(engine);
1184 ee->start = ENGINE_READ(engine, RING_START);
1185 ee->head = ENGINE_READ(engine, RING_HEAD);
1186 ee->tail = ENGINE_READ(engine, RING_TAIL);
1187 ee->ctl = ENGINE_READ(engine, RING_CTL);
1188 if (GRAPHICS_VER(i915) > 2)
1189 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1191 if (!HWS_NEEDS_PHYSICAL(i915)) {
1194 if (GRAPHICS_VER(i915) == 7) {
1195 switch (engine->id) {
1197 MISSING_CASE(engine->id);
1200 mmio = RENDER_HWS_PGA_GEN7;
1203 mmio = BLT_HWS_PGA_GEN7;
1206 mmio = BSD_HWS_PGA_GEN7;
1209 mmio = VEBOX_HWS_PGA_GEN7;
1212 } else if (GRAPHICS_VER(engine->i915) == 6) {
1213 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1215 /* XXX: gen8 returns to sanity */
1216 mmio = RING_HWS_PGA(engine->mmio_base);
1219 ee->hws = intel_uncore_read(engine->uncore, mmio);
1222 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);
1224 if (HAS_PPGTT(i915)) {
1227 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1229 if (GRAPHICS_VER(i915) == 6) {
1230 ee->vm_info.pp_dir_base =
1231 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1232 } else if (GRAPHICS_VER(i915) == 7) {
1233 ee->vm_info.pp_dir_base =
1234 ENGINE_READ(engine, RING_PP_DIR_BASE);
1235 } else if (GRAPHICS_VER(i915) >= 8) {
1236 u32 base = engine->mmio_base;
1238 for (i = 0; i < 4; i++) {
1239 ee->vm_info.pdp[i] =
1240 intel_uncore_read(engine->uncore,
1241 GEN8_RING_PDP_UDW(base, i));
1242 ee->vm_info.pdp[i] <<= 32;
1243 ee->vm_info.pdp[i] |=
1244 intel_uncore_read(engine->uncore,
1245 GEN8_RING_PDP_LDW(base, i));
1251 static void record_request(const struct i915_request *request,
1252 struct i915_request_coredump *erq)
1254 erq->flags = request->fence.flags;
1255 erq->context = request->fence.context;
1256 erq->seqno = request->fence.seqno;
1257 erq->sched_attr = request->sched.attr;
1258 erq->head = request->head;
1259 erq->tail = request->tail;
1263 if (!intel_context_is_closed(request->context)) {
1264 const struct i915_gem_context *ctx;
1266 ctx = rcu_dereference(request->context->gem_context);
1268 erq->pid = pid_nr(ctx->pid);
1273 static void engine_record_execlists(struct intel_engine_coredump *ee)
1275 const struct intel_engine_execlists * const el = &ee->engine->execlists;
1276 struct i915_request * const *port = el->active;
1280 record_request(*port++, &ee->execlist[n++]);
1285 static bool record_context(struct i915_gem_context_coredump *e,
1286 const struct i915_request *rq)
1288 struct i915_gem_context *ctx;
1289 struct task_struct *task;
1293 ctx = rcu_dereference(rq->context->gem_context);
1294 if (ctx && !kref_get_unless_zero(&ctx->ref))
1301 task = pid_task(ctx->pid, PIDTYPE_PID);
1303 strcpy(e->comm, task->comm);
1308 e->sched_attr = ctx->sched;
1309 e->guilty = atomic_read(&ctx->guilty_count);
1310 e->active = atomic_read(&ctx->active_count);
1312 e->total_runtime = rq->context->runtime.total;
1313 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg);
1315 simulated = i915_gem_context_no_error_capture(ctx);
1317 i915_gem_context_put(ctx);
1321 struct intel_engine_capture_vma {
1322 struct intel_engine_capture_vma *next;
1323 struct i915_vma *vma;
1327 static struct intel_engine_capture_vma *
1328 capture_vma(struct intel_engine_capture_vma *next,
1329 struct i915_vma *vma,
1333 struct intel_engine_capture_vma *c;
1338 c = kmalloc(sizeof(*c), gfp);
1342 if (!i915_active_acquire_if_busy(&vma->active)) {
1347 strcpy(c->name, name);
1348 c->vma = vma; /* reference held while active */
1354 static struct intel_engine_capture_vma *
1355 capture_user(struct intel_engine_capture_vma *capture,
1356 const struct i915_request *rq,
1359 struct i915_capture_list *c;
1361 for (c = rq->capture_list; c; c = c->next)
1362 capture = capture_vma(capture, c->vma, "user", gfp);
1367 static void add_vma(struct intel_engine_coredump *ee,
1368 struct i915_vma_coredump *vma)
1371 vma->next = ee->vma;
1376 struct intel_engine_coredump *
1377 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
1379 struct intel_engine_coredump *ee;
1381 ee = kzalloc(sizeof(*ee), gfp);
1385 ee->engine = engine;
1387 engine_record_registers(ee);
1388 engine_record_execlists(ee);
1393 struct intel_engine_capture_vma *
1394 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
1395 struct i915_request *rq,
1398 struct intel_engine_capture_vma *vma = NULL;
1400 ee->simulated |= record_context(&ee->context, rq);
1405 * We need to copy these to an anonymous buffer
1406 * as the simplest method to avoid being overwritten
1409 vma = capture_vma(vma, rq->batch, "batch", gfp);
1410 vma = capture_user(vma, rq, gfp);
1411 vma = capture_vma(vma, rq->ring->vma, "ring", gfp);
1412 vma = capture_vma(vma, rq->context->state, "HW context", gfp);
1414 ee->rq_head = rq->head;
1415 ee->rq_post = rq->postfix;
1416 ee->rq_tail = rq->tail;
1422 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
1423 struct intel_engine_capture_vma *capture,
1424 struct i915_vma_compress *compress)
1426 const struct intel_engine_cs *engine = ee->engine;
1429 struct intel_engine_capture_vma *this = capture;
1430 struct i915_vma *vma = this->vma;
1433 i915_vma_coredump_create(engine->gt,
1437 i915_active_release(&vma->active);
1439 capture = this->next;
1444 i915_vma_coredump_create(engine->gt,
1445 engine->status_page.vma,
1450 i915_vma_coredump_create(engine->gt,
1456 static struct intel_engine_coredump *
1457 capture_engine(struct intel_engine_cs *engine,
1458 struct i915_vma_compress *compress)
1460 struct intel_engine_capture_vma *capture = NULL;
1461 struct intel_engine_coredump *ee;
1462 struct intel_context *ce;
1463 struct i915_request *rq = NULL;
1464 unsigned long flags;
1466 ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
1470 ce = intel_engine_get_hung_context(engine);
1472 intel_engine_clear_hung_context(engine);
1473 rq = intel_context_find_active_request(ce);
1474 if (!rq || !i915_request_started(rq))
1475 goto no_request_capture;
1478 * Getting here with GuC enabled means it is a forced error capture
1479 * with no actual hang. So, no need to attempt the execlist search.
1481 if (!intel_uc_uses_guc_submission(&engine->gt->uc)) {
1482 spin_lock_irqsave(&engine->sched_engine->lock, flags);
1483 rq = intel_engine_execlist_find_hung_request(engine);
1484 spin_unlock_irqrestore(&engine->sched_engine->lock,
1489 capture = intel_engine_coredump_add_request(ee, rq,
1497 intel_engine_coredump_add_vma(ee, capture, compress);
1503 gt_record_engines(struct intel_gt_coredump *gt,
1504 intel_engine_mask_t engine_mask,
1505 struct i915_vma_compress *compress)
1507 struct intel_engine_cs *engine;
1508 enum intel_engine_id id;
1510 for_each_engine(engine, gt->_gt, id) {
1511 struct intel_engine_coredump *ee;
1513 /* Refill our page pool before entering atomic section */
1514 pool_refill(&compress->pool, ALLOW_FAIL);
1516 ee = capture_engine(engine, compress);
1520 ee->hung = engine->mask & engine_mask;
1522 gt->simulated |= ee->simulated;
1523 if (ee->simulated) {
1528 ee->next = gt->engine;
1533 static struct intel_uc_coredump *
1534 gt_record_uc(struct intel_gt_coredump *gt,
1535 struct i915_vma_compress *compress)
1537 const struct intel_uc *uc = >->_gt->uc;
1538 struct intel_uc_coredump *error_uc;
1540 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);
1544 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1545 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1547 /* Non-default firmware paths will be specified by the modparam.
1548 * As modparams are generally accesible from the userspace make
1549 * explicit copies of the firmware paths.
1551 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
1552 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL);
1554 i915_vma_coredump_create(gt->_gt,
1555 uc->guc.log.vma, "GuC log buffer",
1561 /* Capture all registers which don't fit into another category. */
1562 static void gt_record_regs(struct intel_gt_coredump *gt)
1564 struct intel_uncore *uncore = gt->_gt->uncore;
1565 struct drm_i915_private *i915 = uncore->i915;
1569 * General organization
1570 * 1. Registers specific to a single generation
1571 * 2. Registers which belong to multiple generations
1572 * 3. Feature specific registers.
1573 * 4. Everything else
1574 * Please try to follow the order.
1577 /* 1: Registers specific to a single generation */
1578 if (IS_VALLEYVIEW(i915)) {
1579 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1580 gt->ier = intel_uncore_read(uncore, VLV_IER);
1581 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1584 if (GRAPHICS_VER(i915) == 7)
1585 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1587 if (GRAPHICS_VER(i915) >= 12) {
1588 gt->fault_data0 = intel_uncore_read(uncore,
1589 GEN12_FAULT_TLB_DATA0);
1590 gt->fault_data1 = intel_uncore_read(uncore,
1591 GEN12_FAULT_TLB_DATA1);
1592 } else if (GRAPHICS_VER(i915) >= 8) {
1593 gt->fault_data0 = intel_uncore_read(uncore,
1594 GEN8_FAULT_TLB_DATA0);
1595 gt->fault_data1 = intel_uncore_read(uncore,
1596 GEN8_FAULT_TLB_DATA1);
1599 if (GRAPHICS_VER(i915) == 6) {
1600 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1601 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1602 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1605 /* 2: Registers which belong to multiple generations */
1606 if (GRAPHICS_VER(i915) >= 7)
1607 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1609 if (GRAPHICS_VER(i915) >= 6) {
1610 gt->derrmr = intel_uncore_read(uncore, DERRMR);
1611 if (GRAPHICS_VER(i915) < 12) {
1612 gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1613 gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1617 /* 3: Feature specific registers */
1618 if (IS_GRAPHICS_VER(i915, 6, 7)) {
1619 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1620 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1623 if (IS_GRAPHICS_VER(i915, 8, 11))
1624 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1626 if (GRAPHICS_VER(i915) == 12)
1627 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1629 if (GRAPHICS_VER(i915) >= 12) {
1630 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
1632 * SFC_DONE resides in the VD forcewake domain, so it
1633 * only exists if the corresponding VCS engine is
1636 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
1637 !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
1641 intel_uncore_read(uncore, GEN12_SFC_DONE(i));
1644 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1647 /* 4: Everything else */
1648 if (GRAPHICS_VER(i915) >= 11) {
1649 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1651 intel_uncore_read(uncore,
1652 GEN11_RENDER_COPY_INTR_ENABLE);
1654 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1656 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1658 intel_uncore_read(uncore,
1659 GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1661 intel_uncore_read(uncore,
1662 GEN11_CRYPTO_RSVD_INTR_ENABLE);
1664 intel_uncore_read(uncore,
1665 GEN11_GUNIT_CSME_INTR_ENABLE);
1667 } else if (GRAPHICS_VER(i915) >= 8) {
1668 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1669 for (i = 0; i < 4; i++)
1671 intel_uncore_read(uncore, GEN8_GT_IER(i));
1673 } else if (HAS_PCH_SPLIT(i915)) {
1674 gt->ier = intel_uncore_read(uncore, DEIER);
1675 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1677 } else if (GRAPHICS_VER(i915) == 2) {
1678 gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1679 } else if (!IS_VALLEYVIEW(i915)) {
1680 gt->ier = intel_uncore_read(uncore, GEN2_IER);
1682 gt->eir = intel_uncore_read(uncore, EIR);
1683 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1686 static void gt_record_info(struct intel_gt_coredump *gt)
1688 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info));
1692 * Generate a semi-unique error code. The code is not meant to have meaning, The
1693 * code's only purpose is to try to prevent false duplicated bug reports by
1694 * grossly estimating a GPU error state.
1696 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1697 * the hang if we could strip the GTT offset information from it.
1699 * It's only a small step better than a random number in its current form.
1701 static u32 generate_ecode(const struct intel_engine_coredump *ee)
1704 * IPEHR would be an ideal way to detect errors, as it's the gross
1705 * measure of "the command that hung." However, has some very common
1706 * synchronization commands which almost always appear in the case
1707 * strictly a client bug. Use instdone to differentiate those some.
1709 return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1712 static const char *error_msg(struct i915_gpu_coredump *error)
1714 struct intel_engine_coredump *first = NULL;
1715 unsigned int hung_classes = 0;
1716 struct intel_gt_coredump *gt;
1719 for (gt = error->gt; gt; gt = gt->next) {
1720 struct intel_engine_coredump *cs;
1722 for (cs = gt->engine; cs; cs = cs->next) {
1724 hung_classes |= BIT(cs->engine->uabi_class);
1731 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1732 "GPU HANG: ecode %d:%x:%08x",
1733 GRAPHICS_VER(error->i915), hung_classes,
1734 generate_ecode(first));
1735 if (first && first->context.pid) {
1736 /* Just show the first executing process, more is confusing */
1737 len += scnprintf(error->error_msg + len,
1738 sizeof(error->error_msg) - len,
1740 first->context.comm, first->context.pid);
1743 return error->error_msg;
1746 static void capture_gen(struct i915_gpu_coredump *error)
1748 struct drm_i915_private *i915 = error->i915;
1750 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1751 error->suspended = i915->runtime_pm.suspended;
1754 #ifdef CONFIG_INTEL_IOMMU
1755 error->iommu = intel_iommu_gfx_mapped;
1757 error->reset_count = i915_reset_count(&i915->gpu_error);
1758 error->suspend_count = i915->suspend_count;
1760 i915_params_copy(&error->params, &i915->params);
1761 memcpy(&error->device_info,
1763 sizeof(error->device_info));
1764 memcpy(&error->runtime_info,
1766 sizeof(error->runtime_info));
1767 error->driver_caps = i915->caps;
1770 struct i915_gpu_coredump *
1771 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
1773 struct i915_gpu_coredump *error;
1775 if (!i915->params.error_capture)
1778 error = kzalloc(sizeof(*error), gfp);
1782 kref_init(&error->ref);
1785 error->time = ktime_get_real();
1786 error->boottime = ktime_get_boottime();
1787 error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time);
1788 error->capture = jiffies;
1795 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1797 struct intel_gt_coredump *
1798 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
1800 struct intel_gt_coredump *gc;
1802 gc = kzalloc(sizeof(*gc), gfp);
1807 gc->awake = intel_gt_pm_is_awake(gt);
1810 gt_record_fences(gc);
1815 struct i915_vma_compress *
1816 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
1818 struct i915_vma_compress *compress;
1820 compress = kmalloc(sizeof(*compress), ALLOW_FAIL);
1824 if (!compress_init(compress)) {
1832 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
1833 struct i915_vma_compress *compress)
1838 compress_fini(compress);
1842 struct i915_gpu_coredump *
1843 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask)
1845 struct drm_i915_private *i915 = gt->i915;
1846 struct i915_gpu_coredump *error;
1848 /* Check if GPU capture has been disabled */
1849 error = READ_ONCE(i915->gpu_error.first_error);
1853 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);
1855 return ERR_PTR(-ENOMEM);
1857 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL);
1859 struct i915_vma_compress *compress;
1861 compress = i915_vma_capture_prepare(error->gt);
1865 return ERR_PTR(-ENOMEM);
1868 gt_record_info(error->gt);
1869 gt_record_engines(error->gt, engine_mask, compress);
1871 if (INTEL_INFO(i915)->has_gt_uc)
1872 error->gt->uc = gt_record_uc(error->gt, compress);
1874 i915_vma_capture_finish(error->gt, compress);
1876 error->simulated |= error->gt->simulated;
1879 error->overlay = intel_overlay_capture_error_state(i915);
1884 void i915_error_state_store(struct i915_gpu_coredump *error)
1886 struct drm_i915_private *i915;
1889 if (IS_ERR_OR_NULL(error))
1893 drm_info(&i915->drm, "%s\n", error_msg(error));
1895 if (error->simulated ||
1896 cmpxchg(&i915->gpu_error.first_error, NULL, error))
1899 i915_gpu_coredump_get(error);
1901 if (!xchg(&warned, true) &&
1902 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1903 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1904 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
1905 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n");
1906 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1907 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
1908 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1909 i915->drm.primary->index);
1914 * i915_capture_error_state - capture an error record for later analysis
1915 * @gt: intel_gt which originated the hang
1916 * @engine_mask: hung engines
1919 * Should be called when an error is detected (either a hang or an error
1920 * interrupt) to capture error state from the time of the error. Fills
1921 * out a structure which becomes available in debugfs for user level tools
1924 void i915_capture_error_state(struct intel_gt *gt,
1925 intel_engine_mask_t engine_mask)
1927 struct i915_gpu_coredump *error;
1929 error = i915_gpu_coredump(gt, engine_mask);
1930 if (IS_ERR(error)) {
1931 cmpxchg(>->i915->gpu_error.first_error, NULL, error);
1935 i915_error_state_store(error);
1936 i915_gpu_coredump_put(error);
1939 struct i915_gpu_coredump *
1940 i915_first_error_state(struct drm_i915_private *i915)
1942 struct i915_gpu_coredump *error;
1944 spin_lock_irq(&i915->gpu_error.lock);
1945 error = i915->gpu_error.first_error;
1946 if (!IS_ERR_OR_NULL(error))
1947 i915_gpu_coredump_get(error);
1948 spin_unlock_irq(&i915->gpu_error.lock);
1953 void i915_reset_error_state(struct drm_i915_private *i915)
1955 struct i915_gpu_coredump *error;
1957 spin_lock_irq(&i915->gpu_error.lock);
1958 error = i915->gpu_error.first_error;
1959 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
1960 i915->gpu_error.first_error = NULL;
1961 spin_unlock_irq(&i915->gpu_error.lock);
1963 if (!IS_ERR_OR_NULL(error))
1964 i915_gpu_coredump_put(error);
1967 void i915_disable_error_state(struct drm_i915_private *i915, int err)
1969 spin_lock_irq(&i915->gpu_error.lock);
1970 if (!i915->gpu_error.first_error)
1971 i915->gpu_error.first_error = ERR_PTR(err);
1972 spin_unlock_irq(&i915->gpu_error.lock);