2 * Copyright © 2008-2015 Intel Corporation
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/prefetch.h>
26 #include <linux/dma-fence-array.h>
30 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
35 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
37 return to_request(fence)->timeline->common->name;
40 static bool i915_fence_signaled(struct dma_fence *fence)
42 return i915_gem_request_completed(to_request(fence));
45 static bool i915_fence_enable_signaling(struct dma_fence *fence)
47 if (i915_fence_signaled(fence))
50 intel_engine_enable_signaling(to_request(fence));
54 static signed long i915_fence_wait(struct dma_fence *fence,
58 return i915_wait_request(to_request(fence), interruptible, timeout);
61 static void i915_fence_release(struct dma_fence *fence)
63 struct drm_i915_gem_request *req = to_request(fence);
65 /* The request is put onto a RCU freelist (i.e. the address
66 * is immediately reused), mark the fences as being freed now.
67 * Otherwise the debugobjects for the fences are only marked as
68 * freed when the slab cache itself is freed, and so we would get
69 * caught trying to reuse dead objects.
71 i915_sw_fence_fini(&req->submit);
72 i915_sw_fence_fini(&req->execute);
74 kmem_cache_free(req->i915->requests, req);
77 const struct dma_fence_ops i915_fence_ops = {
78 .get_driver_name = i915_fence_get_driver_name,
79 .get_timeline_name = i915_fence_get_timeline_name,
80 .enable_signaling = i915_fence_enable_signaling,
81 .signaled = i915_fence_signaled,
82 .wait = i915_fence_wait,
83 .release = i915_fence_release,
86 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
87 struct drm_file *file)
89 struct drm_i915_private *dev_private;
90 struct drm_i915_file_private *file_priv;
92 WARN_ON(!req || !file || req->file_priv);
100 dev_private = req->i915;
101 file_priv = file->driver_priv;
103 spin_lock(&file_priv->mm.lock);
104 req->file_priv = file_priv;
105 list_add_tail(&req->client_list, &file_priv->mm.request_list);
106 spin_unlock(&file_priv->mm.lock);
112 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
114 struct drm_i915_file_private *file_priv = request->file_priv;
119 spin_lock(&file_priv->mm.lock);
120 list_del(&request->client_list);
121 request->file_priv = NULL;
122 spin_unlock(&file_priv->mm.lock);
125 static struct i915_dependency *
126 i915_dependency_alloc(struct drm_i915_private *i915)
128 return kmem_cache_alloc(i915->dependencies, GFP_KERNEL);
132 i915_dependency_free(struct drm_i915_private *i915,
133 struct i915_dependency *dep)
135 kmem_cache_free(i915->dependencies, dep);
139 __i915_priotree_add_dependency(struct i915_priotree *pt,
140 struct i915_priotree *signal,
141 struct i915_dependency *dep,
144 INIT_LIST_HEAD(&dep->dfs_link);
145 list_add(&dep->wait_link, &signal->waiters_list);
146 list_add(&dep->signal_link, &pt->signalers_list);
147 dep->signaler = signal;
152 i915_priotree_add_dependency(struct drm_i915_private *i915,
153 struct i915_priotree *pt,
154 struct i915_priotree *signal)
156 struct i915_dependency *dep;
158 dep = i915_dependency_alloc(i915);
162 __i915_priotree_add_dependency(pt, signal, dep, I915_DEPENDENCY_ALLOC);
167 i915_priotree_fini(struct drm_i915_private *i915, struct i915_priotree *pt)
169 struct i915_dependency *dep, *next;
171 GEM_BUG_ON(!RB_EMPTY_NODE(&pt->node));
173 /* Everyone we depended upon (the fences we wait to be signaled)
174 * should retire before us and remove themselves from our list.
175 * However, retirement is run independently on each timeline and
176 * so we may be called out-of-order.
178 list_for_each_entry_safe(dep, next, &pt->signalers_list, signal_link) {
179 list_del(&dep->wait_link);
180 if (dep->flags & I915_DEPENDENCY_ALLOC)
181 i915_dependency_free(i915, dep);
184 /* Remove ourselves from everyone who depends upon us */
185 list_for_each_entry_safe(dep, next, &pt->waiters_list, wait_link) {
186 list_del(&dep->signal_link);
187 if (dep->flags & I915_DEPENDENCY_ALLOC)
188 i915_dependency_free(i915, dep);
193 i915_priotree_init(struct i915_priotree *pt)
195 INIT_LIST_HEAD(&pt->signalers_list);
196 INIT_LIST_HEAD(&pt->waiters_list);
197 RB_CLEAR_NODE(&pt->node);
198 pt->priority = INT_MIN;
201 void i915_gem_retire_noop(struct i915_gem_active *active,
202 struct drm_i915_gem_request *request)
204 /* Space left intentionally blank */
207 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
209 struct intel_engine_cs *engine = request->engine;
210 struct i915_gem_active *active, *next;
212 lockdep_assert_held(&request->i915->drm.struct_mutex);
213 GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
214 GEM_BUG_ON(!i915_sw_fence_signaled(&request->execute));
215 GEM_BUG_ON(!i915_gem_request_completed(request));
216 GEM_BUG_ON(!request->i915->gt.active_requests);
218 trace_i915_gem_request_retire(request);
220 spin_lock_irq(&engine->timeline->lock);
221 list_del_init(&request->link);
222 spin_unlock_irq(&engine->timeline->lock);
224 /* We know the GPU must have read the request to have
225 * sent us the seqno + interrupt, so use the position
226 * of tail of the request to update the last known position
229 * Note this requires that we are always called in request
232 list_del(&request->ring_link);
233 request->ring->last_retired_head = request->postfix;
234 if (!--request->i915->gt.active_requests) {
235 GEM_BUG_ON(!request->i915->gt.awake);
236 mod_delayed_work(request->i915->wq,
237 &request->i915->gt.idle_work,
238 msecs_to_jiffies(100));
241 /* Walk through the active list, calling retire on each. This allows
242 * objects to track their GPU activity and mark themselves as idle
243 * when their *last* active request is completed (updating state
244 * tracking lists for eviction, active references for GEM, etc).
246 * As the ->retire() may free the node, we decouple it first and
247 * pass along the auxiliary information (to avoid dereferencing
248 * the node after the callback).
250 list_for_each_entry_safe(active, next, &request->active_list, link) {
251 /* In microbenchmarks or focusing upon time inside the kernel,
252 * we may spend an inordinate amount of time simply handling
253 * the retirement of requests and processing their callbacks.
254 * Of which, this loop itself is particularly hot due to the
255 * cache misses when jumping around the list of i915_gem_active.
256 * So we try to keep this loop as streamlined as possible and
257 * also prefetch the next i915_gem_active to try and hide
258 * the likely cache miss.
262 INIT_LIST_HEAD(&active->link);
263 RCU_INIT_POINTER(active->request, NULL);
265 active->retire(active, request);
268 i915_gem_request_remove_from_client(request);
270 /* Retirement decays the ban score as it is a sign of ctx progress */
271 if (request->ctx->ban_score > 0)
272 request->ctx->ban_score--;
274 /* The backing object for the context is done after switching to the
275 * *next* context. Therefore we cannot retire the previous context until
276 * the next context has already started running. However, since we
277 * cannot take the required locks at i915_gem_request_submit() we
278 * defer the unpinning of the active context to now, retirement of
279 * the subsequent request.
281 if (engine->last_retired_context)
282 engine->context_unpin(engine, engine->last_retired_context);
283 engine->last_retired_context = request->ctx;
285 dma_fence_signal(&request->fence);
287 i915_priotree_fini(request->i915, &request->priotree);
288 i915_gem_request_put(request);
291 void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
293 struct intel_engine_cs *engine = req->engine;
294 struct drm_i915_gem_request *tmp;
296 lockdep_assert_held(&req->i915->drm.struct_mutex);
297 GEM_BUG_ON(!i915_gem_request_completed(req));
299 if (list_empty(&req->link))
303 tmp = list_first_entry(&engine->timeline->requests,
306 i915_gem_request_retire(tmp);
307 } while (tmp != req);
310 static int i915_gem_init_global_seqno(struct drm_i915_private *i915, u32 seqno)
312 struct i915_gem_timeline *timeline = &i915->gt.global_timeline;
313 struct intel_engine_cs *engine;
314 enum intel_engine_id id;
317 /* Carefully retire all requests without writing to the rings */
318 ret = i915_gem_wait_for_idle(i915,
319 I915_WAIT_INTERRUPTIBLE |
324 i915_gem_retire_requests(i915);
325 GEM_BUG_ON(i915->gt.active_requests > 1);
327 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
328 if (!i915_seqno_passed(seqno, atomic_read(&timeline->seqno))) {
329 while (intel_breadcrumbs_busy(i915))
330 cond_resched(); /* spin until threads are complete */
332 atomic_set(&timeline->seqno, seqno);
334 /* Finally reset hw state */
335 for_each_engine(engine, i915, id)
336 intel_engine_init_global_seqno(engine, seqno);
338 list_for_each_entry(timeline, &i915->gt.timelines, link) {
339 for_each_engine(engine, i915, id) {
340 struct intel_timeline *tl = &timeline->engine[id];
342 memset(tl->sync_seqno, 0, sizeof(tl->sync_seqno));
349 int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
351 struct drm_i915_private *dev_priv = to_i915(dev);
353 lockdep_assert_held(&dev_priv->drm.struct_mutex);
358 /* HWS page needs to be set less than what we
359 * will inject to ring
361 return i915_gem_init_global_seqno(dev_priv, seqno - 1);
364 static int reserve_global_seqno(struct drm_i915_private *i915)
366 u32 active_requests = ++i915->gt.active_requests;
367 u32 seqno = atomic_read(&i915->gt.global_timeline.seqno);
370 /* Reservation is fine until we need to wrap around */
371 if (likely(seqno + active_requests > seqno))
374 ret = i915_gem_init_global_seqno(i915, 0);
376 i915->gt.active_requests--;
383 static u32 __timeline_get_seqno(struct i915_gem_timeline *tl)
385 /* seqno only incremented under a mutex */
386 return ++tl->seqno.counter;
389 static u32 timeline_get_seqno(struct i915_gem_timeline *tl)
391 return atomic_inc_return(&tl->seqno);
394 void __i915_gem_request_submit(struct drm_i915_gem_request *request)
396 struct intel_engine_cs *engine = request->engine;
397 struct intel_timeline *timeline;
400 /* Transfer from per-context onto the global per-engine timeline */
401 timeline = engine->timeline;
402 GEM_BUG_ON(timeline == request->timeline);
403 assert_spin_locked(&timeline->lock);
405 seqno = timeline_get_seqno(timeline->common);
407 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
409 GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno, seqno));
410 request->previous_seqno = timeline->last_submitted_seqno;
411 timeline->last_submitted_seqno = seqno;
413 /* We may be recursing from the signal callback of another i915 fence */
414 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
415 request->global_seqno = seqno;
416 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
417 intel_engine_enable_signaling(request);
418 spin_unlock(&request->lock);
420 GEM_BUG_ON(!request->global_seqno);
421 engine->emit_breadcrumb(request,
422 request->ring->vaddr + request->postfix);
424 spin_lock(&request->timeline->lock);
425 list_move_tail(&request->link, &timeline->requests);
426 spin_unlock(&request->timeline->lock);
428 i915_sw_fence_commit(&request->execute);
431 void i915_gem_request_submit(struct drm_i915_gem_request *request)
433 struct intel_engine_cs *engine = request->engine;
436 /* Will be called from irq-context when using foreign fences. */
437 spin_lock_irqsave(&engine->timeline->lock, flags);
439 __i915_gem_request_submit(request);
441 spin_unlock_irqrestore(&engine->timeline->lock, flags);
444 static int __i915_sw_fence_call
445 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
447 struct drm_i915_gem_request *request =
448 container_of(fence, typeof(*request), submit);
452 request->engine->submit_request(request);
456 i915_gem_request_put(request);
463 static int __i915_sw_fence_call
464 execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
466 struct drm_i915_gem_request *request =
467 container_of(fence, typeof(*request), execute);
474 i915_gem_request_put(request);
482 * i915_gem_request_alloc - allocate a request structure
484 * @engine: engine that we wish to issue the request on.
485 * @ctx: context that the request will be associated with.
486 * This can be NULL if the request is not directly related to
487 * any specific user context, in which case this function will
488 * choose an appropriate context to use.
490 * Returns a pointer to the allocated request if successful,
491 * or an error code if not.
493 struct drm_i915_gem_request *
494 i915_gem_request_alloc(struct intel_engine_cs *engine,
495 struct i915_gem_context *ctx)
497 struct drm_i915_private *dev_priv = engine->i915;
498 struct drm_i915_gem_request *req;
501 lockdep_assert_held(&dev_priv->drm.struct_mutex);
503 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
504 * EIO if the GPU is already wedged.
506 if (i915_terminally_wedged(&dev_priv->gpu_error))
507 return ERR_PTR(-EIO);
509 /* Pinning the contexts may generate requests in order to acquire
510 * GGTT space, so do this first before we reserve a seqno for
513 ret = engine->context_pin(engine, ctx);
517 ret = reserve_global_seqno(dev_priv);
521 /* Move the oldest request to the slab-cache (if not in use!) */
522 req = list_first_entry_or_null(&engine->timeline->requests,
524 if (req && __i915_gem_request_completed(req))
525 i915_gem_request_retire(req);
527 /* Beware: Dragons be flying overhead.
529 * We use RCU to look up requests in flight. The lookups may
530 * race with the request being allocated from the slab freelist.
531 * That is the request we are writing to here, may be in the process
532 * of being read by __i915_gem_active_get_rcu(). As such,
533 * we have to be very careful when overwriting the contents. During
534 * the RCU lookup, we change chase the request->engine pointer,
535 * read the request->global_seqno and increment the reference count.
537 * The reference count is incremented atomically. If it is zero,
538 * the lookup knows the request is unallocated and complete. Otherwise,
539 * it is either still in use, or has been reallocated and reset
540 * with dma_fence_init(). This increment is safe for release as we
541 * check that the request we have a reference to and matches the active
544 * Before we increment the refcount, we chase the request->engine
545 * pointer. We must not call kmem_cache_zalloc() or else we set
546 * that pointer to NULL and cause a crash during the lookup. If
547 * we see the request is completed (based on the value of the
548 * old engine and seqno), the lookup is complete and reports NULL.
549 * If we decide the request is not completed (new engine or seqno),
550 * then we grab a reference and double check that it is still the
551 * active request - which it won't be and restart the lookup.
553 * Do not use kmem_cache_zalloc() here!
555 req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
561 req->timeline = i915_gem_context_lookup_timeline(ctx, engine);
562 GEM_BUG_ON(req->timeline == engine->timeline);
564 spin_lock_init(&req->lock);
565 dma_fence_init(&req->fence,
568 req->timeline->fence_context,
569 __timeline_get_seqno(req->timeline->common));
571 /* We bump the ref for the fence chain */
572 i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify);
573 i915_sw_fence_init(&i915_gem_request_get(req)->execute, execute_notify);
575 /* Ensure that the execute fence completes after the submit fence -
576 * as we complete the execute fence from within the submit fence
577 * callback, its completion would otherwise be visible first.
579 i915_sw_fence_await_sw_fence(&req->execute, &req->submit, &req->execq);
581 i915_priotree_init(&req->priotree);
583 INIT_LIST_HEAD(&req->active_list);
584 req->i915 = dev_priv;
585 req->engine = engine;
588 /* No zalloc, must clear what we need by hand */
589 req->global_seqno = 0;
590 req->file_priv = NULL;
594 * Reserve space in the ring buffer for all the commands required to
595 * eventually emit this request. This is to guarantee that the
596 * i915_add_request() call can't fail. Note that the reserve may need
597 * to be redone if the request is not actually submitted straight
598 * away, e.g. because a GPU scheduler has deferred it.
600 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
601 GEM_BUG_ON(req->reserved_space < engine->emit_breadcrumb_sz);
603 ret = engine->request_alloc(req);
607 /* Record the position of the start of the request so that
608 * should we detect the updated seqno part-way through the
609 * GPU processing the request, we never over-estimate the
610 * position of the head.
612 req->head = req->ring->tail;
617 /* Make sure we didn't add ourselves to external state before freeing */
618 GEM_BUG_ON(!list_empty(&req->active_list));
619 GEM_BUG_ON(!list_empty(&req->priotree.signalers_list));
620 GEM_BUG_ON(!list_empty(&req->priotree.waiters_list));
622 kmem_cache_free(dev_priv->requests, req);
624 dev_priv->gt.active_requests--;
626 engine->context_unpin(engine, ctx);
631 i915_gem_request_await_request(struct drm_i915_gem_request *to,
632 struct drm_i915_gem_request *from)
636 GEM_BUG_ON(to == from);
638 if (to->engine->schedule) {
639 ret = i915_priotree_add_dependency(to->i915,
646 if (to->timeline == from->timeline)
649 if (to->engine == from->engine) {
650 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
653 return ret < 0 ? ret : 0;
656 if (!from->global_seqno) {
657 ret = i915_sw_fence_await_dma_fence(&to->submit,
660 return ret < 0 ? ret : 0;
663 if (from->global_seqno <= to->timeline->sync_seqno[from->engine->id])
666 trace_i915_gem_ring_sync_to(to, from);
667 if (!i915.semaphores) {
668 if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) {
669 ret = i915_sw_fence_await_dma_fence(&to->submit,
676 ret = to->engine->semaphore.sync_to(to, from);
681 to->timeline->sync_seqno[from->engine->id] = from->global_seqno;
686 i915_gem_request_await_dma_fence(struct drm_i915_gem_request *req,
687 struct dma_fence *fence)
689 struct dma_fence_array *array;
693 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
696 if (dma_fence_is_i915(fence))
697 return i915_gem_request_await_request(req, to_request(fence));
699 if (!dma_fence_is_array(fence)) {
700 ret = i915_sw_fence_await_dma_fence(&req->submit,
701 fence, I915_FENCE_TIMEOUT,
703 return ret < 0 ? ret : 0;
706 /* Note that if the fence-array was created in signal-on-any mode,
707 * we should *not* decompose it into its individual fences. However,
708 * we don't currently store which mode the fence-array is operating
709 * in. Fortunately, the only user of signal-on-any is private to
710 * amdgpu and we should not see any incoming fence-array from
711 * sync-file being in signal-on-any mode.
714 array = to_dma_fence_array(fence);
715 for (i = 0; i < array->num_fences; i++) {
716 struct dma_fence *child = array->fences[i];
718 if (dma_fence_is_i915(child))
719 ret = i915_gem_request_await_request(req,
722 ret = i915_sw_fence_await_dma_fence(&req->submit,
723 child, I915_FENCE_TIMEOUT,
733 * i915_gem_request_await_object - set this request to (async) wait upon a bo
735 * @to: request we are wishing to use
736 * @obj: object which may be in use on another ring.
738 * This code is meant to abstract object synchronization with the GPU.
739 * Conceptually we serialise writes between engines inside the GPU.
740 * We only allow one engine to write into a buffer at any time, but
741 * multiple readers. To ensure each has a coherent view of memory, we must:
743 * - If there is an outstanding write request to the object, the new
744 * request must wait for it to complete (either CPU or in hw, requests
745 * on the same ring will be naturally ordered).
747 * - If we are a write request (pending_write_domain is set), the new
748 * request must wait for outstanding read requests to complete.
750 * Returns 0 if successful, else propagates up the lower layer error.
753 i915_gem_request_await_object(struct drm_i915_gem_request *to,
754 struct drm_i915_gem_object *obj,
757 struct dma_fence *excl;
761 struct dma_fence **shared;
762 unsigned int count, i;
764 ret = reservation_object_get_fences_rcu(obj->resv,
765 &excl, &count, &shared);
769 for (i = 0; i < count; i++) {
770 ret = i915_gem_request_await_dma_fence(to, shared[i]);
774 dma_fence_put(shared[i]);
777 for (; i < count; i++)
778 dma_fence_put(shared[i]);
781 excl = reservation_object_get_excl_rcu(obj->resv);
786 ret = i915_gem_request_await_dma_fence(to, excl);
794 static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
796 struct drm_i915_private *dev_priv = engine->i915;
798 if (dev_priv->gt.awake)
801 GEM_BUG_ON(!dev_priv->gt.active_requests);
803 intel_runtime_pm_get_noresume(dev_priv);
804 dev_priv->gt.awake = true;
806 intel_enable_gt_powersave(dev_priv);
807 i915_update_gfx_val(dev_priv);
808 if (INTEL_GEN(dev_priv) >= 6)
809 gen6_rps_busy(dev_priv);
811 queue_delayed_work(dev_priv->wq,
812 &dev_priv->gt.retire_work,
813 round_jiffies_up_relative(HZ));
817 * NB: This function is not allowed to fail. Doing so would mean the the
818 * request is not being tracked for completion but the work itself is
819 * going to happen on the hardware. This would be a Bad Thing(tm).
821 void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
823 struct intel_engine_cs *engine = request->engine;
824 struct intel_ring *ring = request->ring;
825 struct intel_timeline *timeline = request->timeline;
826 struct drm_i915_gem_request *prev;
829 lockdep_assert_held(&request->i915->drm.struct_mutex);
830 trace_i915_gem_request_add(request);
832 /* Make sure that no request gazumped us - if it was allocated after
833 * our i915_gem_request_alloc() and called __i915_add_request() before
834 * us, the timeline will hold its seqno which is later than ours.
836 GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno,
837 request->fence.seqno));
840 * To ensure that this call will not fail, space for its emissions
841 * should already have been reserved in the ring buffer. Let the ring
842 * know that it is time to use that space up.
844 request->reserved_space = 0;
847 * Emit any outstanding flushes - execbuf can fail to emit the flush
848 * after having emitted the batchbuffer command. Hence we need to fix
849 * things up similar to emitting the lazy request. The difference here
850 * is that the flush _must_ happen before the next request, no matter
854 err = engine->emit_flush(request, EMIT_FLUSH);
856 /* Not allowed to fail! */
857 WARN(err, "engine->emit_flush() failed: %d!\n", err);
860 /* Record the position of the start of the breadcrumb so that
861 * should we detect the updated seqno part-way through the
862 * GPU processing the request, we never over-estimate the
863 * position of the ring's HEAD.
865 err = intel_ring_begin(request, engine->emit_breadcrumb_sz);
867 request->postfix = ring->tail;
868 ring->tail += engine->emit_breadcrumb_sz * sizeof(u32);
870 /* Seal the request and mark it as pending execution. Note that
871 * we may inspect this state, without holding any locks, during
872 * hangcheck. Hence we apply the barrier to ensure that we do not
873 * see a more recent value in the hws than we are tracking.
876 prev = i915_gem_active_raw(&timeline->last_request,
877 &request->i915->drm.struct_mutex);
879 i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
881 if (engine->schedule)
882 __i915_priotree_add_dependency(&request->priotree,
888 spin_lock_irq(&timeline->lock);
889 list_add_tail(&request->link, &timeline->requests);
890 spin_unlock_irq(&timeline->lock);
892 GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno,
893 request->fence.seqno));
895 timeline->last_submitted_seqno = request->fence.seqno;
896 i915_gem_active_set(&timeline->last_request, request);
898 list_add_tail(&request->ring_link, &ring->request_list);
899 request->emitted_jiffies = jiffies;
901 i915_gem_mark_busy(engine);
903 /* Let the backend know a new request has arrived that may need
904 * to adjust the existing execution schedule due to a high priority
905 * request - i.e. we may want to preempt the current request in order
906 * to run a high priority dependency chain *before* we can execute this
909 * This is called before the request is ready to run so that we can
910 * decide whether to preempt the entire chain so that it is ready to
911 * run at the earliest possible convenience.
913 if (engine->schedule)
914 engine->schedule(request, request->ctx->priority);
917 i915_sw_fence_commit(&request->submit);
918 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
921 static void reset_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
925 spin_lock_irqsave(&q->lock, flags);
926 if (list_empty(&wait->task_list))
927 __add_wait_queue(q, wait);
928 spin_unlock_irqrestore(&q->lock, flags);
931 static unsigned long local_clock_us(unsigned int *cpu)
935 /* Cheaply and approximately convert from nanoseconds to microseconds.
936 * The result and subsequent calculations are also defined in the same
937 * approximate microseconds units. The principal source of timing
938 * error here is from the simple truncation.
940 * Note that local_clock() is only defined wrt to the current CPU;
941 * the comparisons are no longer valid if we switch CPUs. Instead of
942 * blocking preemption for the entire busywait, we can detect the CPU
943 * switch and use that as indicator of system load and a reason to
944 * stop busywaiting, see busywait_stop().
947 t = local_clock() >> 10;
953 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
955 unsigned int this_cpu;
957 if (time_after(local_clock_us(&this_cpu), timeout))
960 return this_cpu != cpu;
963 bool __i915_spin_request(const struct drm_i915_gem_request *req,
964 int state, unsigned long timeout_us)
968 /* When waiting for high frequency requests, e.g. during synchronous
969 * rendering split between the CPU and GPU, the finite amount of time
970 * required to set up the irq and wait upon it limits the response
971 * rate. By busywaiting on the request completion for a short while we
972 * can service the high frequency waits as quick as possible. However,
973 * if it is a slow request, we want to sleep as quickly as possible.
974 * The tradeoff between waiting and sleeping is roughly the time it
975 * takes to sleep on a request, on the order of a microsecond.
978 timeout_us += local_clock_us(&cpu);
980 if (__i915_gem_request_completed(req))
983 if (signal_pending_state(state, current))
986 if (busywait_stop(timeout_us, cpu))
990 } while (!need_resched());
996 __i915_request_wait_for_execute(struct drm_i915_gem_request *request,
1000 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1001 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1002 wait_queue_head_t *q = &request->i915->gpu_error.wait_queue;
1006 if (flags & I915_WAIT_LOCKED)
1007 add_wait_queue(q, &reset);
1010 prepare_to_wait(&request->execute.wait, &wait, state);
1012 if (i915_sw_fence_done(&request->execute))
1015 if (flags & I915_WAIT_LOCKED &&
1016 i915_reset_in_progress(&request->i915->gpu_error)) {
1017 __set_current_state(TASK_RUNNING);
1018 i915_reset(request->i915);
1019 reset_wait_queue(q, &reset);
1023 if (signal_pending_state(state, current)) {
1024 timeout = -ERESTARTSYS;
1028 timeout = io_schedule_timeout(timeout);
1030 finish_wait(&request->execute.wait, &wait);
1032 if (flags & I915_WAIT_LOCKED)
1033 remove_wait_queue(q, &reset);
1039 * i915_wait_request - wait until execution of request has finished
1040 * @req: the request to wait upon
1041 * @flags: how to wait
1042 * @timeout: how long to wait in jiffies
1044 * i915_wait_request() waits for the request to be completed, for a
1045 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1048 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
1049 * in via the flags, and vice versa if the struct_mutex is not held, the caller
1050 * must not specify that the wait is locked.
1052 * Returns the remaining time (in jiffies) if the request completed, which may
1053 * be zero or -ETIME if the request is unfinished after the timeout expires.
1054 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1055 * pending before the request completes.
1057 long i915_wait_request(struct drm_i915_gem_request *req,
1061 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1062 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1064 struct intel_wait wait;
1067 #if IS_ENABLED(CONFIG_LOCKDEP)
1068 GEM_BUG_ON(debug_locks &&
1069 !!lockdep_is_held(&req->i915->drm.struct_mutex) !=
1070 !!(flags & I915_WAIT_LOCKED));
1072 GEM_BUG_ON(timeout < 0);
1074 if (i915_gem_request_completed(req))
1080 trace_i915_gem_request_wait_begin(req);
1082 if (!i915_sw_fence_done(&req->execute)) {
1083 timeout = __i915_request_wait_for_execute(req, flags, timeout);
1087 GEM_BUG_ON(!i915_sw_fence_done(&req->execute));
1089 GEM_BUG_ON(!i915_sw_fence_done(&req->submit));
1090 GEM_BUG_ON(!req->global_seqno);
1092 /* Optimistic short spin before touching IRQs */
1093 if (i915_spin_request(req, state, 5))
1096 set_current_state(state);
1097 if (flags & I915_WAIT_LOCKED)
1098 add_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1100 intel_wait_init(&wait, req->global_seqno);
1101 if (intel_engine_add_wait(req->engine, &wait))
1102 /* In order to check that we haven't missed the interrupt
1103 * as we enabled it, we need to kick ourselves to do a
1104 * coherent check on the seqno before we sleep.
1109 if (signal_pending_state(state, current)) {
1110 timeout = -ERESTARTSYS;
1119 timeout = io_schedule_timeout(timeout);
1121 if (intel_wait_complete(&wait))
1124 set_current_state(state);
1127 /* Carefully check if the request is complete, giving time
1128 * for the seqno to be visible following the interrupt.
1129 * We also have to check in case we are kicked by the GPU
1130 * reset in order to drop the struct_mutex.
1132 if (__i915_request_irq_complete(req))
1135 /* If the GPU is hung, and we hold the lock, reset the GPU
1136 * and then check for completion. On a full reset, the engine's
1137 * HW seqno will be advanced passed us and we are complete.
1138 * If we do a partial reset, we have to wait for the GPU to
1139 * resume and update the breadcrumb.
1141 * If we don't hold the mutex, we can just wait for the worker
1142 * to come along and update the breadcrumb (either directly
1143 * itself, or indirectly by recovering the GPU).
1145 if (flags & I915_WAIT_LOCKED &&
1146 i915_reset_in_progress(&req->i915->gpu_error)) {
1147 __set_current_state(TASK_RUNNING);
1148 i915_reset(req->i915);
1149 reset_wait_queue(&req->i915->gpu_error.wait_queue,
1154 /* Only spin if we know the GPU is processing this request */
1155 if (i915_spin_request(req, state, 2))
1159 intel_engine_remove_wait(req->engine, &wait);
1160 if (flags & I915_WAIT_LOCKED)
1161 remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1162 __set_current_state(TASK_RUNNING);
1165 trace_i915_gem_request_wait_end(req);
1170 static void engine_retire_requests(struct intel_engine_cs *engine)
1172 struct drm_i915_gem_request *request, *next;
1174 list_for_each_entry_safe(request, next,
1175 &engine->timeline->requests, link) {
1176 if (!__i915_gem_request_completed(request))
1179 i915_gem_request_retire(request);
1183 void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
1185 struct intel_engine_cs *engine;
1186 enum intel_engine_id id;
1188 lockdep_assert_held(&dev_priv->drm.struct_mutex);
1190 if (!dev_priv->gt.active_requests)
1193 for_each_engine(engine, dev_priv, id)
1194 engine_retire_requests(engine);