drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 #define GEN6_PPGTT_PD_ENTRIES 512
  32 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
  33 typedef uint64_t gen8_gtt_pte_t;
  34 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
  35
  36 /* PPGTT stuff */
  37 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  38 #define HSW_GTT_ADDR_ENCODE(addr)       ((addr) | (((addr) >> 28) & 0x7f0))
  39
  40 #define GEN6_PDE_VALID                  (1 << 0)
  41 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  42 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  43
  44 #define GEN6_PTE_VALID                  (1 << 0)
  45 #define GEN6_PTE_UNCACHED               (1 << 1)
  46 #define HSW_PTE_UNCACHED                (0)
  47 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  48 #define GEN7_PTE_CACHE_L3_LLC           (3 << 1)
  49 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  50 #define HSW_PTE_ADDR_ENCODE(addr)       HSW_GTT_ADDR_ENCODE(addr)
  51
  52 /* Cacheability Control is a 4-bit value. The low three bits are stored in *
  53  * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
  54  */
  55 #define HSW_CACHEABILITY_CONTROL(bits)  ((((bits) & 0x7) << 1) | \
  56                                          (((bits) & 0x8) << (11 - 3)))
  57 #define HSW_WB_LLC_AGE3                 HSW_CACHEABILITY_CONTROL(0x2)
  58 #define HSW_WB_LLC_AGE0                 HSW_CACHEABILITY_CONTROL(0x3)
  59 #define HSW_WB_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0xb)
  60 #define HSW_WT_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0x6)
  61
  62 #define GEN8_PTES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
  63 #define GEN8_PDES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
  64 #define GEN8_LEGACY_PDPS                4
  65
  66 #define PPAT_UNCACHED_INDEX             (_PAGE_PWT | _PAGE_PCD)
  67 #define PPAT_CACHED_PDE_INDEX           0 /* WB LLC */
  68 #define PPAT_CACHED_INDEX               _PAGE_PAT /* WB LLCeLLC */
  69 #define PPAT_DISPLAY_ELLC_INDEX         _PAGE_PCD /* WT eLLC */
  70
  71 static void ppgtt_bind_vma(struct i915_vma *vma,
  72                            enum i915_cache_level cache_level,
  73                            u32 flags);
  74 static void ppgtt_unbind_vma(struct i915_vma *vma);
  75
  76 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
  77                                              enum i915_cache_level level,
  78                                              bool valid)
  79 {
  80         gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
  81         pte |= addr;
  82         if (level != I915_CACHE_NONE)
  83                 pte |= PPAT_CACHED_INDEX;
  84         else
  85                 pte |= PPAT_UNCACHED_INDEX;
  86         return pte;
  87 }
  88
  89 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
  90                                              dma_addr_t addr,
  91                                              enum i915_cache_level level)
  92 {
  93         gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
  94         pde |= addr;
  95         if (level != I915_CACHE_NONE)
  96                 pde |= PPAT_CACHED_PDE_INDEX;
  97         else
  98                 pde |= PPAT_UNCACHED_INDEX;
  99         return pde;
 100 }
 101
 102 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
 103                                      enum i915_cache_level level,
 104                                      bool valid)
 105 {
 106         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 107         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 108
 109         switch (level) {
 110         case I915_CACHE_L3_LLC:
 111         case I915_CACHE_LLC:
 112                 pte |= GEN6_PTE_CACHE_LLC;
 113                 break;
 114         case I915_CACHE_NONE:
 115                 pte |= GEN6_PTE_UNCACHED;
 116                 break;
 117         default:
 118                 WARN_ON(1);
 119         }
 120
 121         return pte;
 122 }
 123
 124 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
 125                                      enum i915_cache_level level,
 126                                      bool valid)
 127 {
 128         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 129         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 130
 131         switch (level) {
 132         case I915_CACHE_L3_LLC:
 133                 pte |= GEN7_PTE_CACHE_L3_LLC;
 134                 break;
 135         case I915_CACHE_LLC:
 136                 pte |= GEN6_PTE_CACHE_LLC;
 137                 break;
 138         case I915_CACHE_NONE:
 139                 pte |= GEN6_PTE_UNCACHED;
 140                 break;
 141         default:
 142                 WARN_ON(1);
 143         }
 144
 145         return pte;
 146 }
 147
 148 #define BYT_PTE_WRITEABLE               (1 << 1)
 149 #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
 150
 151 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
 152                                      enum i915_cache_level level,
 153                                      bool valid)
 154 {
 155         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 156         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 157
 158         /* Mark the page as writeable.  Other platforms don't have a
 159          * setting for read-only/writable, so this matches that behavior.
 160          */
 161         pte |= BYT_PTE_WRITEABLE;
 162
 163         if (level != I915_CACHE_NONE)
 164                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 165
 166         return pte;
 167 }
 168
 169 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
 170                                      enum i915_cache_level level,
 171                                      bool valid)
 172 {
 173         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 174         pte |= HSW_PTE_ADDR_ENCODE(addr);
 175
 176         if (level != I915_CACHE_NONE)
 177                 pte |= HSW_WB_LLC_AGE3;
 178
 179         return pte;
 180 }
 181
 182 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 183                                       enum i915_cache_level level,
 184                                       bool valid)
 185 {
 186         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 187         pte |= HSW_PTE_ADDR_ENCODE(addr);
 188
 189         switch (level) {
 190         case I915_CACHE_NONE:
 191                 break;
 192         case I915_CACHE_WT:
 193                 pte |= HSW_WT_ELLC_LLC_AGE0;
 194                 break;
 195         default:
 196                 pte |= HSW_WB_ELLC_LLC_AGE0;
 197                 break;
 198         }
 199
 200         return pte;
 201 }
 202
 203 /* Broadwell Page Directory Pointer Descriptors */
 204 static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
 205                            uint64_t val, bool synchronous)
 206 {
 207         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 208         int ret;
 209
 210         BUG_ON(entry >= 4);
 211
 212         if (synchronous) {
 213                 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
 214                 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
 215                 return 0;
 216         }
 217
 218         ret = intel_ring_begin(ring, 6);
 219         if (ret)
 220                 return ret;
 221
 222         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 223         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 224         intel_ring_emit(ring, (u32)(val >> 32));
 225         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 226         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 227         intel_ring_emit(ring, (u32)(val));
 228         intel_ring_advance(ring);
 229
 230         return 0;
 231 }
 232
 233 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 234 {
 235         struct drm_device *dev = ppgtt->base.dev;
 236         struct drm_i915_private *dev_priv = dev->dev_private;
 237         struct intel_ring_buffer *ring;
 238         int i, j, ret;
 239
 240         /* bit of a hack to find the actual last used pd */
 241         int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 242
 243         for_each_ring(ring, dev_priv, j) {
 244                 I915_WRITE(RING_MODE_GEN7(ring),
 245                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 246         }
 247
 248         for (i = used_pd - 1; i >= 0; i--) {
 249                 dma_addr_t addr = ppgtt->pd_dma_addr[i];
 250                 for_each_ring(ring, dev_priv, j) {
 251                         ret = gen8_write_pdp(ring, i, addr,
 252                                              i915_reset_in_progress(&dev_priv->gpu_error));
 253                         if (ret)
 254                                 goto err_out;
 255                 }
 256         }
 257         return 0;
 258
 259 err_out:
 260         for_each_ring(ring, dev_priv, j)
 261                 I915_WRITE(RING_MODE_GEN7(ring),
 262                            _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
 263         return ret;
 264 }
 265
 266 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 267                                    unsigned first_entry,
 268                                    unsigned num_entries,
 269                                    bool use_scratch)
 270 {
 271         struct i915_hw_ppgtt *ppgtt =
 272                 container_of(vm, struct i915_hw_ppgtt, base);
 273         gen8_gtt_pte_t *pt_vaddr, scratch_pte;
 274         unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
 275         unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE;
 276         unsigned last_pte, i;
 277
 278         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 279                                       I915_CACHE_LLC, use_scratch);
 280
 281         while (num_entries) {
 282                 struct page *page_table = &ppgtt->gen8_pt_pages[act_pt];
 283
 284                 last_pte = first_pte + num_entries;
 285                 if (last_pte > GEN8_PTES_PER_PAGE)
 286                         last_pte = GEN8_PTES_PER_PAGE;
 287
 288                 pt_vaddr = kmap_atomic(page_table);
 289
 290                 for (i = first_pte; i < last_pte; i++)
 291                         pt_vaddr[i] = scratch_pte;
 292
 293                 kunmap_atomic(pt_vaddr);
 294
 295                 num_entries -= last_pte - first_pte;
 296                 first_pte = 0;
 297                 act_pt++;
 298         }
 299 }
 300
 301 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 302                                       struct sg_table *pages,
 303                                       unsigned first_entry,
 304                                       enum i915_cache_level cache_level)
 305 {
 306         struct i915_hw_ppgtt *ppgtt =
 307                 container_of(vm, struct i915_hw_ppgtt, base);
 308         gen8_gtt_pte_t *pt_vaddr;
 309         unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE;
 310         unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE;
 311         struct sg_page_iter sg_iter;
 312
 313         pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
 314         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 315                 dma_addr_t page_addr;
 316
 317                 page_addr = sg_dma_address(sg_iter.sg) +
 318                                 (sg_iter.sg_pgoffset << PAGE_SHIFT);
 319                 pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level,
 320                                                     true);
 321                 if (++act_pte == GEN8_PTES_PER_PAGE) {
 322                         kunmap_atomic(pt_vaddr);
 323                         act_pt++;
 324                         pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]);
 325                         act_pte = 0;
 326
 327                 }
 328         }
 329         kunmap_atomic(pt_vaddr);
 330 }
 331
 332 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 333 {
 334         struct i915_hw_ppgtt *ppgtt =
 335                 container_of(vm, struct i915_hw_ppgtt, base);
 336         int i, j;
 337
 338         drm_mm_takedown(&vm->mm);
 339
 340         for (i = 0; i < ppgtt->num_pd_pages ; i++) {
 341                 if (ppgtt->pd_dma_addr[i]) {
 342                         pci_unmap_page(ppgtt->base.dev->pdev,
 343                                        ppgtt->pd_dma_addr[i],
 344                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 345
 346                         for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 347                                 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 348                                 if (addr)
 349                                         pci_unmap_page(ppgtt->base.dev->pdev,
 350                                                        addr,
 351                                                        PAGE_SIZE,
 352                                                        PCI_DMA_BIDIRECTIONAL);
 353
 354                         }
 355                 }
 356                 kfree(ppgtt->gen8_pt_dma_addr[i]);
 357         }
 358
 359         __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
 360         __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
 361 }
 362
 363 /**
 364  * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a
 365  * net effect resembling a 2-level page table in normal x86 terms. Each PDP
 366  * represents 1GB of memory
 367  * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space.
 368  *
 369  * TODO: Do something with the size parameter
 370  **/
 371 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 372 {
 373         struct page *pt_pages;
 374         int i, j, ret = -ENOMEM;
 375         const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
 376         const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 377
 378         if (size % (1<<30))
 379                 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
 380
 381         /* FIXME: split allocation into smaller pieces. For now we only ever do
 382          * this once, but with full PPGTT, the multiple contiguous allocations
 383          * will be bad.
 384          */
 385         ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
 386         if (!ppgtt->pd_pages)
 387                 return -ENOMEM;
 388
 389         pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT));
 390         if (!pt_pages) {
 391                 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
 392                 return -ENOMEM;
 393         }
 394
 395         ppgtt->gen8_pt_pages = pt_pages;
 396         ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 397         ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT);
 398         ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 399         ppgtt->enable = gen8_ppgtt_enable;
 400         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 401         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 402         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 403         ppgtt->base.start = 0;
 404         ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
 405
 406         BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
 407
 408         /*
 409          * - Create a mapping for the page directories.
 410          * - For each page directory:
 411          *      allocate space for page table mappings.
 412          *      map each page table
 413          */
 414         for (i = 0; i < max_pdp; i++) {
 415                 dma_addr_t temp;
 416                 temp = pci_map_page(ppgtt->base.dev->pdev,
 417                                     &ppgtt->pd_pages[i], 0,
 418                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 419                 if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
 420                         goto err_out;
 421
 422                 ppgtt->pd_dma_addr[i] = temp;
 423
 424                 ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL);
 425                 if (!ppgtt->gen8_pt_dma_addr[i])
 426                         goto err_out;
 427
 428                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 429                         struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
 430                         temp = pci_map_page(ppgtt->base.dev->pdev,
 431                                             p, 0, PAGE_SIZE,
 432                                             PCI_DMA_BIDIRECTIONAL);
 433
 434                         if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
 435                                 goto err_out;
 436
 437                         ppgtt->gen8_pt_dma_addr[i][j] = temp;
 438                 }
 439         }
 440
 441         /* For now, the PPGTT helper functions all require that the PDEs are
 442          * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
 443          * will never need to touch the PDEs again */
 444         for (i = 0; i < max_pdp; i++) {
 445                 gen8_ppgtt_pde_t *pd_vaddr;
 446                 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
 447                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 448                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 449                         pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 450                                                       I915_CACHE_LLC);
 451                 }
 452                 kunmap_atomic(pd_vaddr);
 453         }
 454
 455         ppgtt->base.clear_range(&ppgtt->base, 0,
 456                                 ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE,
 457                                 true);
 458
 459         DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 460                          ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 461         DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
 462                          ppgtt->num_pt_pages,
 463                          (ppgtt->num_pt_pages - num_pt_pages) +
 464                          size % (1<<30));
 465         return 0;
 466
 467 err_out:
 468         ppgtt->base.cleanup(&ppgtt->base);
 469         return ret;
 470 }
 471
 472 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 473 {
 474         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 475         gen6_gtt_pte_t __iomem *pd_addr;
 476         uint32_t pd_entry;
 477         int i;
 478
 479         WARN_ON(ppgtt->pd_offset & 0x3f);
 480         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 481                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 482         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 483                 dma_addr_t pt_addr;
 484
 485                 pt_addr = ppgtt->pt_dma_addr[i];
 486                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 487                 pd_entry |= GEN6_PDE_VALID;
 488
 489                 writel(pd_entry, pd_addr + i);
 490         }
 491         readl(pd_addr);
 492 }
 493
 494 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 495 {
 496         struct drm_device *dev = ppgtt->base.dev;
 497         drm_i915_private_t *dev_priv = dev->dev_private;
 498         uint32_t pd_offset;
 499         struct intel_ring_buffer *ring;
 500         int i;
 501
 502         BUG_ON(ppgtt->pd_offset & 0x3f);
 503
 504         gen6_write_pdes(ppgtt);
 505
 506         pd_offset = ppgtt->pd_offset;
 507         pd_offset /= 64; /* in cachelines, */
 508         pd_offset <<= 16;
 509
 510         if (INTEL_INFO(dev)->gen == 6) {
 511                 uint32_t ecochk, gab_ctl, ecobits;
 512
 513                 ecobits = I915_READ(GAC_ECO_BITS);
 514                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 515                                          ECOBITS_PPGTT_CACHE64B);
 516
 517                 gab_ctl = I915_READ(GAB_CTL);
 518                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 519
 520                 ecochk = I915_READ(GAM_ECOCHK);
 521                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 522                                        ECOCHK_PPGTT_CACHE64B);
 523                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 524         } else if (INTEL_INFO(dev)->gen >= 7) {
 525                 uint32_t ecochk, ecobits;
 526
 527                 ecobits = I915_READ(GAC_ECO_BITS);
 528                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 529
 530                 ecochk = I915_READ(GAM_ECOCHK);
 531                 if (IS_HASWELL(dev)) {
 532                         ecochk |= ECOCHK_PPGTT_WB_HSW;
 533                 } else {
 534                         ecochk |= ECOCHK_PPGTT_LLC_IVB;
 535                         ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 536                 }
 537                 I915_WRITE(GAM_ECOCHK, ecochk);
 538                 /* GFX_MODE is per-ring on gen7+ */
 539         }
 540
 541         for_each_ring(ring, dev_priv, i) {
 542                 if (INTEL_INFO(dev)->gen >= 7)
 543                         I915_WRITE(RING_MODE_GEN7(ring),
 544                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 545
 546                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 547                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 548         }
 549         return 0;
 550 }
 551
 552 /* PPGTT support for Sandybdrige/Gen6 and later */
 553 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 554                                    unsigned first_entry,
 555                                    unsigned num_entries,
 556                                    bool use_scratch)
 557 {
 558         struct i915_hw_ppgtt *ppgtt =
 559                 container_of(vm, struct i915_hw_ppgtt, base);
 560         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 561         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 562         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 563         unsigned last_pte, i;
 564
 565         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 566
 567         while (num_entries) {
 568                 last_pte = first_pte + num_entries;
 569                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 570                         last_pte = I915_PPGTT_PT_ENTRIES;
 571
 572                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 573
 574                 for (i = first_pte; i < last_pte; i++)
 575                         pt_vaddr[i] = scratch_pte;
 576
 577                 kunmap_atomic(pt_vaddr);
 578
 579                 num_entries -= last_pte - first_pte;
 580                 first_pte = 0;
 581                 act_pt++;
 582         }
 583 }
 584
 585 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 586                                       struct sg_table *pages,
 587                                       unsigned first_entry,
 588                                       enum i915_cache_level cache_level)
 589 {
 590         struct i915_hw_ppgtt *ppgtt =
 591                 container_of(vm, struct i915_hw_ppgtt, base);
 592         gen6_gtt_pte_t *pt_vaddr;
 593         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 594         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 595         struct sg_page_iter sg_iter;
 596
 597         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 598         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 599                 dma_addr_t page_addr;
 600
 601                 page_addr = sg_page_iter_dma_address(&sg_iter);
 602                 pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true);
 603                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 604                         kunmap_atomic(pt_vaddr);
 605                         act_pt++;
 606                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 607                         act_pte = 0;
 608
 609                 }
 610         }
 611         kunmap_atomic(pt_vaddr);
 612 }
 613
 614 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 615 {
 616         struct i915_hw_ppgtt *ppgtt =
 617                 container_of(vm, struct i915_hw_ppgtt, base);
 618         int i;
 619
 620         drm_mm_takedown(&ppgtt->base.mm);
 621         drm_mm_remove_node(&ppgtt->node);
 622
 623         if (ppgtt->pt_dma_addr) {
 624                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 625                         pci_unmap_page(ppgtt->base.dev->pdev,
 626                                        ppgtt->pt_dma_addr[i],
 627                                        4096, PCI_DMA_BIDIRECTIONAL);
 628         }
 629
 630         kfree(ppgtt->pt_dma_addr);
 631         for (i = 0; i < ppgtt->num_pd_entries; i++)
 632                 __free_page(ppgtt->pt_pages[i]);
 633         kfree(ppgtt->pt_pages);
 634         kfree(ppgtt);
 635 }
 636
 637 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 638 {
 639 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
 640 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
 641         struct drm_device *dev = ppgtt->base.dev;
 642         struct drm_i915_private *dev_priv = dev->dev_private;
 643         bool retried = false;
 644         int i, ret;
 645
 646         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
 647          * allocator works in address space sizes, so it's multiplied by page
 648          * size. We allocate at the top of the GTT to avoid fragmentation.
 649          */
 650         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
 651 alloc:
 652         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
 653                                                   &ppgtt->node, GEN6_PD_SIZE,
 654                                                   GEN6_PD_ALIGN, 0,
 655                                                   0, dev_priv->gtt.base.total,
 656                                                   DRM_MM_SEARCH_DEFAULT);
 657         if (ret == -ENOSPC && !retried) {
 658                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
 659                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
 660                                                I915_CACHE_NONE, false, true);
 661                 if (ret)
 662                         return ret;
 663
 664                 retried = true;
 665                 goto alloc;
 666         }
 667
 668         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
 669                 DRM_DEBUG("Forced to use aperture for PDEs\n");
 670
 671         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
 672         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
 673         ppgtt->enable = gen6_ppgtt_enable;
 674         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
 675         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
 676         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
 677         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
 678         ppgtt->base.start = 0;
 679         ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
 680         ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
 681                                   GFP_KERNEL);
 682         if (!ppgtt->pt_pages) {
 683                 drm_mm_remove_node(&ppgtt->node);
 684                 return -ENOMEM;
 685         }
 686
 687         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 688                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 689                 if (!ppgtt->pt_pages[i])
 690                         goto err_pt_alloc;
 691         }
 692
 693         ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
 694                                      GFP_KERNEL);
 695         if (!ppgtt->pt_dma_addr)
 696                 goto err_pt_alloc;
 697
 698         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 699                 dma_addr_t pt_addr;
 700
 701                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 702                                        PCI_DMA_BIDIRECTIONAL);
 703
 704                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 705                         ret = -EIO;
 706                         goto err_pd_pin;
 707
 708                 }
 709                 ppgtt->pt_dma_addr[i] = pt_addr;
 710         }
 711
 712         ppgtt->base.clear_range(&ppgtt->base, 0,
 713                                 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
 714
 715         DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
 716                          ppgtt->node.size >> 20,
 717                          ppgtt->node.start / PAGE_SIZE);
 718         ppgtt->pd_offset =
 719                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
 720
 721         return 0;
 722
 723 err_pd_pin:
 724         if (ppgtt->pt_dma_addr) {
 725                 for (i--; i >= 0; i--)
 726                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 727                                        4096, PCI_DMA_BIDIRECTIONAL);
 728         }
 729 err_pt_alloc:
 730         kfree(ppgtt->pt_dma_addr);
 731         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 732                 if (ppgtt->pt_pages[i])
 733                         __free_page(ppgtt->pt_pages[i]);
 734         }
 735         kfree(ppgtt->pt_pages);
 736         drm_mm_remove_node(&ppgtt->node);
 737
 738         return ret;
 739 }
 740
 741 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         struct i915_hw_ppgtt *ppgtt;
 745         int ret;
 746
 747         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 748         if (!ppgtt)
 749                 return -ENOMEM;
 750
 751         ppgtt->base.dev = dev;
 752
 753         if (INTEL_INFO(dev)->gen < 8)
 754                 ret = gen6_ppgtt_init(ppgtt);
 755         else if (IS_GEN8(dev))
 756                 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
 757         else
 758                 BUG();
 759
 760         if (ret)
 761                 kfree(ppgtt);
 762         else {
 763                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 764                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
 765                             ppgtt->base.total);
 766         }
 767
 768         return ret;
 769 }
 770
 771 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 772 {
 773         struct drm_i915_private *dev_priv = dev->dev_private;
 774         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 775
 776         if (!ppgtt)
 777                 return;
 778
 779         ppgtt->base.cleanup(&ppgtt->base);
 780         dev_priv->mm.aliasing_ppgtt = NULL;
 781 }
 782
 783 static void __always_unused
 784 ppgtt_bind_vma(struct i915_vma *vma,
 785                enum i915_cache_level cache_level,
 786                u32 flags)
 787 {
 788         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
 789
 790         WARN_ON(flags);
 791
 792         vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level);
 793 }
 794
 795 static void __always_unused ppgtt_unbind_vma(struct i915_vma *vma)
 796 {
 797         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
 798
 799         vma->vm->clear_range(vma->vm,
 800                              entry,
 801                              vma->obj->base.size >> PAGE_SHIFT,
 802                              true);
 803 }
 804
 805 extern int intel_iommu_gfx_mapped;
 806 /* Certain Gen5 chipsets require require idling the GPU before
 807  * unmapping anything from the GTT when VT-d is enabled.
 808  */
 809 static inline bool needs_idle_maps(struct drm_device *dev)
 810 {
 811 #ifdef CONFIG_INTEL_IOMMU
 812         /* Query intel_iommu to see if we need the workaround. Presumably that
 813          * was loaded first.
 814          */
 815         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 816                 return true;
 817 #endif
 818         return false;
 819 }
 820
 821 static bool do_idling(struct drm_i915_private *dev_priv)
 822 {
 823         bool ret = dev_priv->mm.interruptible;
 824
 825         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 826                 dev_priv->mm.interruptible = false;
 827                 if (i915_gpu_idle(dev_priv->dev)) {
 828                         DRM_ERROR("Couldn't idle GPU\n");
 829                         /* Wait a bit, in hopes it avoids the hang */
 830                         udelay(10);
 831                 }
 832         }
 833
 834         return ret;
 835 }
 836
 837 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 838 {
 839         if (unlikely(dev_priv->gtt.do_idle_maps))
 840                 dev_priv->mm.interruptible = interruptible;
 841 }
 842
 843 void i915_check_and_clear_faults(struct drm_device *dev)
 844 {
 845         struct drm_i915_private *dev_priv = dev->dev_private;
 846         struct intel_ring_buffer *ring;
 847         int i;
 848
 849         if (INTEL_INFO(dev)->gen < 6)
 850                 return;
 851
 852         for_each_ring(ring, dev_priv, i) {
 853                 u32 fault_reg;
 854                 fault_reg = I915_READ(RING_FAULT_REG(ring));
 855                 if (fault_reg & RING_FAULT_VALID) {
 856                         DRM_DEBUG_DRIVER("Unexpected fault\n"
 857                                          "\tAddr: 0x%08lx\\n"
 858                                          "\tAddress space: %s\n"
 859                                          "\tSource ID: %d\n"
 860                                          "\tType: %d\n",
 861                                          fault_reg & PAGE_MASK,
 862                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
 863                                          RING_FAULT_SRCID(fault_reg),
 864                                          RING_FAULT_FAULT_TYPE(fault_reg));
 865                         I915_WRITE(RING_FAULT_REG(ring),
 866                                    fault_reg & ~RING_FAULT_VALID);
 867                 }
 868         }
 869         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
 870 }
 871
 872 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
 873 {
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875
 876         /* Don't bother messing with faults pre GEN6 as we have little
 877          * documentation supporting that it's a good idea.
 878          */
 879         if (INTEL_INFO(dev)->gen < 6)
 880                 return;
 881
 882         i915_check_and_clear_faults(dev);
 883
 884         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 885                                        dev_priv->gtt.base.start / PAGE_SIZE,
 886                                        dev_priv->gtt.base.total / PAGE_SIZE,
 887                                        false);
 888 }
 889
 890 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 891 {
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893         struct drm_i915_gem_object *obj;
 894
 895         i915_check_and_clear_faults(dev);
 896
 897         /* First fill our portion of the GTT with scratch pages */
 898         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 899                                        dev_priv->gtt.base.start / PAGE_SIZE,
 900                                        dev_priv->gtt.base.total / PAGE_SIZE,
 901                                        true);
 902
 903         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 904                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
 905                                                            &dev_priv->gtt.base);
 906                 if (!vma)
 907                         continue;
 908
 909                 i915_gem_clflush_object(obj, obj->pin_display);
 910                 /* The bind_vma code tries to be smart about tracking mappings.
 911                  * Unfortunately above, we've just wiped out the mappings
 912                  * without telling our object about it. So we need to fake it.
 913                  */
 914                 obj->has_global_gtt_mapping = 0;
 915                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
 916         }
 917
 918         i915_gem_chipset_flush(dev);
 919 }
 920
 921 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 922 {
 923         if (obj->has_dma_mapping)
 924                 return 0;
 925
 926         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 927                         obj->pages->sgl, obj->pages->nents,
 928                         PCI_DMA_BIDIRECTIONAL))
 929                 return -ENOSPC;
 930
 931         return 0;
 932 }
 933
 934 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
 935 {
 936 #ifdef writeq
 937         writeq(pte, addr);
 938 #else
 939         iowrite32((u32)pte, addr);
 940         iowrite32(pte >> 32, addr + 4);
 941 #endif
 942 }
 943
 944 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 945                                      struct sg_table *st,
 946                                      unsigned int first_entry,
 947                                      enum i915_cache_level level)
 948 {
 949         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 950         gen8_gtt_pte_t __iomem *gtt_entries =
 951                 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 952         int i = 0;
 953         struct sg_page_iter sg_iter;
 954         dma_addr_t addr;
 955
 956         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 957                 addr = sg_dma_address(sg_iter.sg) +
 958                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
 959                 gen8_set_pte(&gtt_entries[i],
 960                              gen8_pte_encode(addr, level, true));
 961                 i++;
 962         }
 963
 964         /*
 965          * XXX: This serves as a posting read to make sure that the PTE has
 966          * actually been updated. There is some concern that even though
 967          * registers and PTEs are within the same BAR that they are potentially
 968          * of NUMA access patterns. Therefore, even with the way we assume
 969          * hardware should work, we must keep this posting read for paranoia.
 970          */
 971         if (i != 0)
 972                 WARN_ON(readq(&gtt_entries[i-1])
 973                         != gen8_pte_encode(addr, level, true));
 974
 975 #if 0 /* TODO: Still needed on GEN8? */
 976         /* This next bit makes the above posting read even more important. We
 977          * want to flush the TLBs only after we're certain all the PTE updates
 978          * have finished.
 979          */
 980         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 981         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 982 #endif
 983 }
 984
 985 /*
 986  * Binds an object into the global gtt with the specified cache level. The object
 987  * will be accessible to the GPU via commands whose operands reference offsets
 988  * within the global GTT as well as accessible by the GPU through the GMADR
 989  * mapped BAR (dev_priv->mm.gtt->gtt).
 990  */
 991 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 992                                      struct sg_table *st,
 993                                      unsigned int first_entry,
 994                                      enum i915_cache_level level)
 995 {
 996         struct drm_i915_private *dev_priv = vm->dev->dev_private;
 997         gen6_gtt_pte_t __iomem *gtt_entries =
 998                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 999         int i = 0;
1000         struct sg_page_iter sg_iter;
1001         dma_addr_t addr;
1002
1003         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1004                 addr = sg_page_iter_dma_address(&sg_iter);
1005                 iowrite32(vm->pte_encode(addr, level, true), &gtt_entries[i]);
1006                 i++;
1007         }
1008
1009         /* XXX: This serves as a posting read to make sure that the PTE has
1010          * actually been updated. There is some concern that even though
1011          * registers and PTEs are within the same BAR that they are potentially
1012          * of NUMA access patterns. Therefore, even with the way we assume
1013          * hardware should work, we must keep this posting read for paranoia.
1014          */
1015         if (i != 0)
1016                 WARN_ON(readl(&gtt_entries[i-1]) !=
1017                         vm->pte_encode(addr, level, true));
1018
1019         /* This next bit makes the above posting read even more important. We
1020          * want to flush the TLBs only after we're certain all the PTE updates
1021          * have finished.
1022          */
1023         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1024         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1025 }
1026
1027 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1028                                   unsigned int first_entry,
1029                                   unsigned int num_entries,
1030                                   bool use_scratch)
1031 {
1032         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1033         gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1034                 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1035         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1036         int i;
1037
1038         if (WARN(num_entries > max_entries,
1039                  "First entry = %d; Num entries = %d (max=%d)\n",
1040                  first_entry, num_entries, max_entries))
1041                 num_entries = max_entries;
1042
1043         scratch_pte = gen8_pte_encode(vm->scratch.addr,
1044                                       I915_CACHE_LLC,
1045                                       use_scratch);
1046         for (i = 0; i < num_entries; i++)
1047                 gen8_set_pte(&gtt_base[i], scratch_pte);
1048         readl(gtt_base);
1049 }
1050
1051 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1052                                   unsigned int first_entry,
1053                                   unsigned int num_entries,
1054                                   bool use_scratch)
1055 {
1056         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1057         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1058                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1059         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1060         int i;
1061
1062         if (WARN(num_entries > max_entries,
1063                  "First entry = %d; Num entries = %d (max=%d)\n",
1064                  first_entry, num_entries, max_entries))
1065                 num_entries = max_entries;
1066
1067         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
1068
1069         for (i = 0; i < num_entries; i++)
1070                 iowrite32(scratch_pte, &gtt_base[i]);
1071         readl(gtt_base);
1072 }
1073
1074
1075 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1076                                enum i915_cache_level cache_level,
1077                                u32 unused)
1078 {
1079         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1080         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1081                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1082
1083         BUG_ON(!i915_is_ggtt(vma->vm));
1084         intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags);
1085         vma->obj->has_global_gtt_mapping = 1;
1086 }
1087
1088 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1089                                   unsigned int first_entry,
1090                                   unsigned int num_entries,
1091                                   bool unused)
1092 {
1093         intel_gtt_clear_range(first_entry, num_entries);
1094 }
1095
1096 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1097 {
1098         const unsigned int first = vma->node.start >> PAGE_SHIFT;
1099         const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1100
1101         BUG_ON(!i915_is_ggtt(vma->vm));
1102         vma->obj->has_global_gtt_mapping = 0;
1103         intel_gtt_clear_range(first, size);
1104 }
1105
1106 static void ggtt_bind_vma(struct i915_vma *vma,
1107                           enum i915_cache_level cache_level,
1108                           u32 flags)
1109 {
1110         struct drm_device *dev = vma->vm->dev;
1111         struct drm_i915_private *dev_priv = dev->dev_private;
1112         struct drm_i915_gem_object *obj = vma->obj;
1113         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1114
1115         /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1116          * or we have a global mapping already but the cacheability flags have
1117          * changed, set the global PTEs.
1118          *
1119          * If there is an aliasing PPGTT it is anecdotally faster, so use that
1120          * instead if none of the above hold true.
1121          *
1122          * NB: A global mapping should only be needed for special regions like
1123          * "gtt mappable", SNB errata, or if specified via special execbuf
1124          * flags. At all other times, the GPU will use the aliasing PPGTT.
1125          */
1126         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1127                 if (!obj->has_global_gtt_mapping ||
1128                     (cache_level != obj->cache_level)) {
1129                         vma->vm->insert_entries(vma->vm, obj->pages, entry,
1130                                                 cache_level);
1131                         obj->has_global_gtt_mapping = 1;
1132                 }
1133         }
1134
1135         if (dev_priv->mm.aliasing_ppgtt &&
1136             (!obj->has_aliasing_ppgtt_mapping ||
1137              (cache_level != obj->cache_level))) {
1138                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1139                 appgtt->base.insert_entries(&appgtt->base,
1140                                             vma->obj->pages, entry, cache_level);
1141                 vma->obj->has_aliasing_ppgtt_mapping = 1;
1142         }
1143 }
1144
1145 static void ggtt_unbind_vma(struct i915_vma *vma)
1146 {
1147         struct drm_device *dev = vma->vm->dev;
1148         struct drm_i915_private *dev_priv = dev->dev_private;
1149         struct drm_i915_gem_object *obj = vma->obj;
1150         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1151
1152         if (obj->has_global_gtt_mapping) {
1153                 vma->vm->clear_range(vma->vm, entry,
1154                                      vma->obj->base.size >> PAGE_SHIFT,
1155                                      true);
1156                 obj->has_global_gtt_mapping = 0;
1157         }
1158
1159         if (obj->has_aliasing_ppgtt_mapping) {
1160                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1161                 appgtt->base.clear_range(&appgtt->base,
1162                                          entry,
1163                                          obj->base.size >> PAGE_SHIFT,
1164                                          true);
1165                 obj->has_aliasing_ppgtt_mapping = 0;
1166         }
1167 }
1168
1169 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1170 {
1171         struct drm_device *dev = obj->base.dev;
1172         struct drm_i915_private *dev_priv = dev->dev_private;
1173         bool interruptible;
1174
1175         interruptible = do_idling(dev_priv);
1176
1177         if (!obj->has_dma_mapping)
1178                 dma_unmap_sg(&dev->pdev->dev,
1179                              obj->pages->sgl, obj->pages->nents,
1180                              PCI_DMA_BIDIRECTIONAL);
1181
1182         undo_idling(dev_priv, interruptible);
1183 }
1184
1185 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1186                                   unsigned long color,
1187                                   unsigned long *start,
1188                                   unsigned long *end)
1189 {
1190         if (node->color != color)
1191                 *start += 4096;
1192
1193         if (!list_empty(&node->node_list)) {
1194                 node = list_entry(node->node_list.next,
1195                                   struct drm_mm_node,
1196                                   node_list);
1197                 if (node->allocated && node->color != color)
1198                         *end -= 4096;
1199         }
1200 }
1201
1202 void i915_gem_setup_global_gtt(struct drm_device *dev,
1203                                unsigned long start,
1204                                unsigned long mappable_end,
1205                                unsigned long end)
1206 {
1207         /* Let GEM Manage all of the aperture.
1208          *
1209          * However, leave one page at the end still bound to the scratch page.
1210          * There are a number of places where the hardware apparently prefetches
1211          * past the end of the object, and we've seen multiple hangs with the
1212          * GPU head pointer stuck in a batchbuffer bound at the last page of the
1213          * aperture.  One page should be enough to keep any prefetching inside
1214          * of the aperture.
1215          */
1216         struct drm_i915_private *dev_priv = dev->dev_private;
1217         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1218         struct drm_mm_node *entry;
1219         struct drm_i915_gem_object *obj;
1220         unsigned long hole_start, hole_end;
1221
1222         BUG_ON(mappable_end > end);
1223
1224         /* Subtract the guard page ... */
1225         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1226         if (!HAS_LLC(dev))
1227                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1228
1229         /* Mark any preallocated objects as occupied */
1230         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1231                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1232                 int ret;
1233                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1234                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
1235
1236                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1237                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1238                 if (ret)
1239                         DRM_DEBUG_KMS("Reservation failed\n");
1240                 obj->has_global_gtt_mapping = 1;
1241         }
1242
1243         dev_priv->gtt.base.start = start;
1244         dev_priv->gtt.base.total = end - start;
1245
1246         /* Clear any non-preallocated blocks */
1247         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1248                 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
1249                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1250                               hole_start, hole_end);
1251                 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
1252         }
1253
1254         /* And finally clear the reserved guard page */
1255         ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
1256 }
1257
1258 static bool
1259 intel_enable_ppgtt(struct drm_device *dev)
1260 {
1261         if (i915_enable_ppgtt >= 0)
1262                 return i915_enable_ppgtt;
1263
1264 #ifdef CONFIG_INTEL_IOMMU
1265         /* Disable ppgtt on SNB if VT-d is on. */
1266         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
1267                 return false;
1268 #endif
1269
1270         return true;
1271 }
1272
1273 void i915_gem_init_global_gtt(struct drm_device *dev)
1274 {
1275         struct drm_i915_private *dev_priv = dev->dev_private;
1276         unsigned long gtt_size, mappable_size;
1277
1278         gtt_size = dev_priv->gtt.base.total;
1279         mappable_size = dev_priv->gtt.mappable_end;
1280
1281         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1282         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
1283                 int ret;
1284
1285                 ret = i915_gem_init_aliasing_ppgtt(dev);
1286                 if (ret)
1287                         DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
1288         }
1289 }
1290
1291 static int setup_scratch_page(struct drm_device *dev)
1292 {
1293         struct drm_i915_private *dev_priv = dev->dev_private;
1294         struct page *page;
1295         dma_addr_t dma_addr;
1296
1297         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1298         if (page == NULL)
1299                 return -ENOMEM;
1300         get_page(page);
1301         set_pages_uc(page, 1);
1302
1303 #ifdef CONFIG_INTEL_IOMMU
1304         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1305                                 PCI_DMA_BIDIRECTIONAL);
1306         if (pci_dma_mapping_error(dev->pdev, dma_addr))
1307                 return -EINVAL;
1308 #else
1309         dma_addr = page_to_phys(page);
1310 #endif
1311         dev_priv->gtt.base.scratch.page = page;
1312         dev_priv->gtt.base.scratch.addr = dma_addr;
1313
1314         return 0;
1315 }
1316
1317 static void teardown_scratch_page(struct drm_device *dev)
1318 {
1319         struct drm_i915_private *dev_priv = dev->dev_private;
1320         struct page *page = dev_priv->gtt.base.scratch.page;
1321
1322         set_pages_wb(page, 1);
1323         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1324                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1325         put_page(page);
1326         __free_page(page);
1327 }
1328
1329 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1330 {
1331         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1332         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1333         return snb_gmch_ctl << 20;
1334 }
1335
1336 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1337 {
1338         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1339         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1340         if (bdw_gmch_ctl)
1341                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1342         if (bdw_gmch_ctl > 4) {
1343                 WARN_ON(!i915_preliminary_hw_support);
1344                 return 4<<20;
1345         }
1346
1347         return bdw_gmch_ctl << 20;
1348 }
1349
1350 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1351 {
1352         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1353         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1354         return snb_gmch_ctl << 25; /* 32 MB units */
1355 }
1356
1357 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1358 {
1359         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1360         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1361         return bdw_gmch_ctl << 25; /* 32 MB units */
1362 }
1363
1364 static int ggtt_probe_common(struct drm_device *dev,
1365                              size_t gtt_size)
1366 {
1367         struct drm_i915_private *dev_priv = dev->dev_private;
1368         phys_addr_t gtt_bus_addr;
1369         int ret;
1370
1371         /* For Modern GENs the PTEs and register space are split in the BAR */
1372         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
1373                 (pci_resource_len(dev->pdev, 0) / 2);
1374
1375         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
1376         if (!dev_priv->gtt.gsm) {
1377                 DRM_ERROR("Failed to map the gtt page table\n");
1378                 return -ENOMEM;
1379         }
1380
1381         ret = setup_scratch_page(dev);
1382         if (ret) {
1383                 DRM_ERROR("Scratch setup failed\n");
1384                 /* iounmap will also get called at remove, but meh */
1385                 iounmap(dev_priv->gtt.gsm);
1386         }
1387
1388         return ret;
1389 }
1390
1391 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1392  * bits. When using advanced contexts each context stores its own PAT, but
1393  * writing this data shouldn't be harmful even in those cases. */
1394 static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
1395 {
1396 #define GEN8_PPAT_UC            (0<<0)
1397 #define GEN8_PPAT_WC            (1<<0)
1398 #define GEN8_PPAT_WT            (2<<0)
1399 #define GEN8_PPAT_WB            (3<<0)
1400 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
1401 /* FIXME(BDW): Bspec is completely confused about cache control bits. */
1402 #define GEN8_PPAT_LLC           (1<<2)
1403 #define GEN8_PPAT_LLCELLC       (2<<2)
1404 #define GEN8_PPAT_LLCeLLC       (3<<2)
1405 #define GEN8_PPAT_AGE(x)        (x<<4)
1406 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
1407         uint64_t pat;
1408
1409         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
1410               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1411               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1412               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
1413               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1414               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1415               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1416               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1417
1418         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1419          * write would work. */
1420         I915_WRITE(GEN8_PRIVATE_PAT, pat);
1421         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1422 }
1423
1424 static int gen8_gmch_probe(struct drm_device *dev,
1425                            size_t *gtt_total,
1426                            size_t *stolen,
1427                            phys_addr_t *mappable_base,
1428                            unsigned long *mappable_end)
1429 {
1430         struct drm_i915_private *dev_priv = dev->dev_private;
1431         unsigned int gtt_size;
1432         u16 snb_gmch_ctl;
1433         int ret;
1434
1435         /* TODO: We're not aware of mappable constraints on gen8 yet */
1436         *mappable_base = pci_resource_start(dev->pdev, 2);
1437         *mappable_end = pci_resource_len(dev->pdev, 2);
1438
1439         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1440                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1441
1442         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1443
1444         *stolen = gen8_get_stolen_size(snb_gmch_ctl);
1445
1446         gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
1447         *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
1448
1449         gen8_setup_private_ppat(dev_priv);
1450
1451         ret = ggtt_probe_common(dev, gtt_size);
1452
1453         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
1454         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
1455
1456         return ret;
1457 }
1458
1459 static int gen6_gmch_probe(struct drm_device *dev,
1460                            size_t *gtt_total,
1461                            size_t *stolen,
1462                            phys_addr_t *mappable_base,
1463                            unsigned long *mappable_end)
1464 {
1465         struct drm_i915_private *dev_priv = dev->dev_private;
1466         unsigned int gtt_size;
1467         u16 snb_gmch_ctl;
1468         int ret;
1469
1470         *mappable_base = pci_resource_start(dev->pdev, 2);
1471         *mappable_end = pci_resource_len(dev->pdev, 2);
1472
1473         /* 64/512MB is the current min/max we actually know of, but this is just
1474          * a coarse sanity check.
1475          */
1476         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
1477                 DRM_ERROR("Unknown GMADR size (%lx)\n",
1478                           dev_priv->gtt.mappable_end);
1479                 return -ENXIO;
1480         }
1481
1482         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
1483                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
1484         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1485
1486         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
1487
1488         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
1489         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
1490
1491         ret = ggtt_probe_common(dev, gtt_size);
1492
1493         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
1494         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
1495
1496         return ret;
1497 }
1498
1499 static void gen6_gmch_remove(struct i915_address_space *vm)
1500 {
1501
1502         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1503
1504         drm_mm_takedown(&vm->mm);
1505         iounmap(gtt->gsm);
1506         teardown_scratch_page(vm->dev);
1507 }
1508
1509 static int i915_gmch_probe(struct drm_device *dev,
1510                            size_t *gtt_total,
1511                            size_t *stolen,
1512                            phys_addr_t *mappable_base,
1513                            unsigned long *mappable_end)
1514 {
1515         struct drm_i915_private *dev_priv = dev->dev_private;
1516         int ret;
1517
1518         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
1519         if (!ret) {
1520                 DRM_ERROR("failed to set up gmch\n");
1521                 return -EIO;
1522         }
1523
1524         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
1525
1526         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
1527         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
1528
1529         return 0;
1530 }
1531
1532 static void i915_gmch_remove(struct i915_address_space *vm)
1533 {
1534         intel_gmch_remove();
1535 }
1536
1537 int i915_gem_gtt_init(struct drm_device *dev)
1538 {
1539         struct drm_i915_private *dev_priv = dev->dev_private;
1540         struct i915_gtt *gtt = &dev_priv->gtt;
1541         int ret;
1542
1543         if (INTEL_INFO(dev)->gen <= 5) {
1544                 gtt->gtt_probe = i915_gmch_probe;
1545                 gtt->base.cleanup = i915_gmch_remove;
1546         } else if (INTEL_INFO(dev)->gen < 8) {
1547                 gtt->gtt_probe = gen6_gmch_probe;
1548                 gtt->base.cleanup = gen6_gmch_remove;
1549                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
1550                         gtt->base.pte_encode = iris_pte_encode;
1551                 else if (IS_HASWELL(dev))
1552                         gtt->base.pte_encode = hsw_pte_encode;
1553                 else if (IS_VALLEYVIEW(dev))
1554                         gtt->base.pte_encode = byt_pte_encode;
1555                 else if (INTEL_INFO(dev)->gen >= 7)
1556                         gtt->base.pte_encode = ivb_pte_encode;
1557                 else
1558                         gtt->base.pte_encode = snb_pte_encode;
1559         } else {
1560                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
1561                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
1562         }
1563
1564         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
1565                              &gtt->mappable_base, &gtt->mappable_end);
1566         if (ret)
1567                 return ret;
1568
1569         gtt->base.dev = dev;
1570
1571         /* GMADR is the PCI mmio aperture into the global GTT. */
1572         DRM_INFO("Memory usable by graphics device = %zdM\n",
1573                  gtt->base.total >> 20);
1574         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
1575         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
1576
1577         return 0;
1578 }
1579
1580 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
1581                                               struct i915_address_space *vm)
1582 {
1583         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
1584         if (vma == NULL)
1585                 return ERR_PTR(-ENOMEM);
1586
1587         INIT_LIST_HEAD(&vma->vma_link);
1588         INIT_LIST_HEAD(&vma->mm_list);
1589         INIT_LIST_HEAD(&vma->exec_list);
1590         vma->vm = vm;
1591         vma->obj = obj;
1592
1593         switch (INTEL_INFO(vm->dev)->gen) {
1594         case 8:
1595         case 7:
1596         case 6:
1597                 vma->unbind_vma = ggtt_unbind_vma;
1598                 vma->bind_vma = ggtt_bind_vma;
1599                 break;
1600         case 5:
1601         case 4:
1602         case 3:
1603         case 2:
1604                 BUG_ON(!i915_is_ggtt(vm));
1605                 vma->unbind_vma = i915_ggtt_unbind_vma;
1606                 vma->bind_vma = i915_ggtt_bind_vma;
1607                 break;
1608         default:
1609                 BUG();
1610         }
1611
1612         /* Keep GGTT vmas first to make debug easier */
1613         if (i915_is_ggtt(vm))
1614                 list_add(&vma->vma_link, &obj->vma_list);
1615         else
1616                 list_add_tail(&vma->vma_link, &obj->vma_list);
1617
1618         return vma;
1619 }
1620
1621 struct i915_vma *
1622 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
1623                                   struct i915_address_space *vm)
1624 {
1625         struct i915_vma *vma;
1626
1627         vma = i915_gem_obj_to_vma(obj, vm);
1628         if (!vma)
1629                 vma = __i915_gem_vma_create(obj, vm);
1630
1631         return vma;
1632 }