drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/slab.h> /* fault-inject.h is not standalone! */
  27
  28 #include <linux/fault-inject.h>
  29 #include <linux/log2.h>
  30 #include <linux/random.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/stop_machine.h>
  33
  34 #include <asm/set_memory.h>
  35
  36 #include <drm/drmP.h>
  37 #include <drm/i915_drm.h>
  38
  39 #include "i915_drv.h"
  40 #include "i915_vgpu.h"
  41 #include "i915_trace.h"
  42 #include "intel_drv.h"
  43 #include "intel_frontbuffer.h"
  44
  45 #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM)
  46
  47 /**
  48  * DOC: Global GTT views
  49  *
  50  * Background and previous state
  51  *
  52  * Historically objects could exists (be bound) in global GTT space only as
  53  * singular instances with a view representing all of the object's backing pages
  54  * in a linear fashion. This view will be called a normal view.
  55  *
  56  * To support multiple views of the same object, where the number of mapped
  57  * pages is not equal to the backing store, or where the layout of the pages
  58  * is not linear, concept of a GGTT view was added.
  59  *
  60  * One example of an alternative view is a stereo display driven by a single
  61  * image. In this case we would have a framebuffer looking like this
  62  * (2x2 pages):
  63  *
  64  *    12
  65  *    34
  66  *
  67  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  68  * rendering. In contrast, fed to the display engine would be an alternative
  69  * view which could look something like this:
  70  *
  71  *   1212
  72  *   3434
  73  *
  74  * In this example both the size and layout of pages in the alternative view is
  75  * different from the normal view.
  76  *
  77  * Implementation and usage
  78  *
  79  * GGTT views are implemented using VMAs and are distinguished via enum
  80  * i915_ggtt_view_type and struct i915_ggtt_view.
  81  *
  82  * A new flavour of core GEM functions which work with GGTT bound objects were
  83  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  84  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  85  * parameter encapsulating all metadata required to implement a view.
  86  *
  87  * As a helper for callers which are only interested in the normal view,
  88  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  89  * GEM API functions, the ones not taking the view parameter, are operating on,
  90  * or with the normal GGTT view.
  91  *
  92  * Code wanting to add or use a new GGTT view needs to:
  93  *
  94  * 1. Add a new enum with a suitable name.
  95  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  96  * 3. Add support to i915_get_vma_pages().
  97  *
  98  * New views are required to build a scatter-gather table from within the
  99  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
 100  * exists for the lifetime of an VMA.
 101  *
 102  * Core API is designed to have copy semantics which means that passed in
 103  * struct i915_ggtt_view does not need to be persistent (left around after
 104  * calling the core API functions).
 105  *
 106  */
 107
 108 static int
 109 i915_get_ggtt_vma_pages(struct i915_vma *vma);
 110
 111 static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
 112 {
 113         /* Note that as an uncached mmio write, this should flush the
 114          * WCB of the writes into the GGTT before it triggers the invalidate.
 115          */
 116         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 117 }
 118
 119 static void guc_ggtt_invalidate(struct drm_i915_private *dev_priv)
 120 {
 121         gen6_ggtt_invalidate(dev_priv);
 122         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 123 }
 124
 125 static void gmch_ggtt_invalidate(struct drm_i915_private *dev_priv)
 126 {
 127         intel_gtt_chipset_flush();
 128 }
 129
 130 static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
 131 {
 132         i915->ggtt.invalidate(i915);
 133 }
 134
 135 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 136                                 int enable_ppgtt)
 137 {
 138         bool has_aliasing_ppgtt;
 139         bool has_full_ppgtt;
 140         bool has_full_48bit_ppgtt;
 141
 142         has_aliasing_ppgtt = dev_priv->info.has_aliasing_ppgtt;
 143         has_full_ppgtt = dev_priv->info.has_full_ppgtt;
 144         has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
 145
 146         if (intel_vgpu_active(dev_priv)) {
 147                 /* GVT-g has no support for 32bit ppgtt */
 148                 has_full_ppgtt = false;
 149                 has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
 150         }
 151
 152         if (!has_aliasing_ppgtt)
 153                 return 0;
 154
 155         /*
 156          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 157          * execlists, the sole mechanism available to submit work.
 158          */
 159         if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
 160                 return 0;
 161
 162         if (enable_ppgtt == 1)
 163                 return 1;
 164
 165         if (enable_ppgtt == 2 && has_full_ppgtt)
 166                 return 2;
 167
 168         if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
 169                 return 3;
 170
 171         /* Disable ppgtt on SNB if VT-d is on. */
 172         if (IS_GEN6(dev_priv) && intel_vtd_active()) {
 173                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 174                 return 0;
 175         }
 176
 177         /* Early VLV doesn't have this */
 178         if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) {
 179                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 180                 return 0;
 181         }
 182
 183         if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) {
 184                 if (has_full_48bit_ppgtt)
 185                         return 3;
 186
 187                 if (has_full_ppgtt)
 188                         return 2;
 189         }
 190
 191         return has_aliasing_ppgtt ? 1 : 0;
 192 }
 193
 194 static int ppgtt_bind_vma(struct i915_vma *vma,
 195                           enum i915_cache_level cache_level,
 196                           u32 unused)
 197 {
 198         u32 pte_flags;
 199         int ret;
 200
 201         if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
 202                 ret = vma->vm->allocate_va_range(vma->vm, vma->node.start,
 203                                                  vma->size);
 204                 if (ret)
 205                         return ret;
 206         }
 207
 208         vma->pages = vma->obj->mm.pages;
 209
 210         /* Currently applicable only to VLV */
 211         pte_flags = 0;
 212         if (vma->obj->gt_ro)
 213                 pte_flags |= PTE_READ_ONLY;
 214
 215         vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
 216
 217         return 0;
 218 }
 219
 220 static void ppgtt_unbind_vma(struct i915_vma *vma)
 221 {
 222         vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
 223 }
 224
 225 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 226                                   enum i915_cache_level level)
 227 {
 228         gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW;
 229         pte |= addr;
 230
 231         switch (level) {
 232         case I915_CACHE_NONE:
 233                 pte |= PPAT_UNCACHED_INDEX;
 234                 break;
 235         case I915_CACHE_WT:
 236                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 237                 break;
 238         default:
 239                 pte |= PPAT_CACHED_INDEX;
 240                 break;
 241         }
 242
 243         return pte;
 244 }
 245
 246 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
 247                                   const enum i915_cache_level level)
 248 {
 249         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 250         pde |= addr;
 251         if (level != I915_CACHE_NONE)
 252                 pde |= PPAT_CACHED_PDE_INDEX;
 253         else
 254                 pde |= PPAT_UNCACHED_INDEX;
 255         return pde;
 256 }
 257
 258 #define gen8_pdpe_encode gen8_pde_encode
 259 #define gen8_pml4e_encode gen8_pde_encode
 260
 261 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 262                                  enum i915_cache_level level,
 263                                  u32 unused)
 264 {
 265         gen6_pte_t pte = GEN6_PTE_VALID;
 266         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 267
 268         switch (level) {
 269         case I915_CACHE_L3_LLC:
 270         case I915_CACHE_LLC:
 271                 pte |= GEN6_PTE_CACHE_LLC;
 272                 break;
 273         case I915_CACHE_NONE:
 274                 pte |= GEN6_PTE_UNCACHED;
 275                 break;
 276         default:
 277                 MISSING_CASE(level);
 278         }
 279
 280         return pte;
 281 }
 282
 283 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 284                                  enum i915_cache_level level,
 285                                  u32 unused)
 286 {
 287         gen6_pte_t pte = GEN6_PTE_VALID;
 288         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 289
 290         switch (level) {
 291         case I915_CACHE_L3_LLC:
 292                 pte |= GEN7_PTE_CACHE_L3_LLC;
 293                 break;
 294         case I915_CACHE_LLC:
 295                 pte |= GEN6_PTE_CACHE_LLC;
 296                 break;
 297         case I915_CACHE_NONE:
 298                 pte |= GEN6_PTE_UNCACHED;
 299                 break;
 300         default:
 301                 MISSING_CASE(level);
 302         }
 303
 304         return pte;
 305 }
 306
 307 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 308                                  enum i915_cache_level level,
 309                                  u32 flags)
 310 {
 311         gen6_pte_t pte = GEN6_PTE_VALID;
 312         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 313
 314         if (!(flags & PTE_READ_ONLY))
 315                 pte |= BYT_PTE_WRITEABLE;
 316
 317         if (level != I915_CACHE_NONE)
 318                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 319
 320         return pte;
 321 }
 322
 323 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 324                                  enum i915_cache_level level,
 325                                  u32 unused)
 326 {
 327         gen6_pte_t pte = GEN6_PTE_VALID;
 328         pte |= HSW_PTE_ADDR_ENCODE(addr);
 329
 330         if (level != I915_CACHE_NONE)
 331                 pte |= HSW_WB_LLC_AGE3;
 332
 333         return pte;
 334 }
 335
 336 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 337                                   enum i915_cache_level level,
 338                                   u32 unused)
 339 {
 340         gen6_pte_t pte = GEN6_PTE_VALID;
 341         pte |= HSW_PTE_ADDR_ENCODE(addr);
 342
 343         switch (level) {
 344         case I915_CACHE_NONE:
 345                 break;
 346         case I915_CACHE_WT:
 347                 pte |= HSW_WT_ELLC_LLC_AGE3;
 348                 break;
 349         default:
 350                 pte |= HSW_WB_ELLC_LLC_AGE3;
 351                 break;
 352         }
 353
 354         return pte;
 355 }
 356
 357 static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp)
 358 {
 359         struct page *page;
 360
 361         if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1)))
 362                 i915_gem_shrink_all(vm->i915);
 363
 364         if (vm->free_pages.nr)
 365                 return vm->free_pages.pages[--vm->free_pages.nr];
 366
 367         page = alloc_page(gfp);
 368         if (!page)
 369                 return NULL;
 370
 371         if (vm->pt_kmap_wc)
 372                 set_pages_array_wc(&page, 1);
 373
 374         return page;
 375 }
 376
 377 static void vm_free_pages_release(struct i915_address_space *vm)
 378 {
 379         GEM_BUG_ON(!pagevec_count(&vm->free_pages));
 380
 381         if (vm->pt_kmap_wc)
 382                 set_pages_array_wb(vm->free_pages.pages,
 383                                    pagevec_count(&vm->free_pages));
 384
 385         __pagevec_release(&vm->free_pages);
 386 }
 387
 388 static void vm_free_page(struct i915_address_space *vm, struct page *page)
 389 {
 390         if (!pagevec_add(&vm->free_pages, page))
 391                 vm_free_pages_release(vm);
 392 }
 393
 394 static int __setup_page_dma(struct i915_address_space *vm,
 395                             struct i915_page_dma *p,
 396                             gfp_t gfp)
 397 {
 398         p->page = vm_alloc_page(vm, gfp | __GFP_NOWARN | __GFP_NORETRY);
 399         if (unlikely(!p->page))
 400                 return -ENOMEM;
 401
 402         p->daddr = dma_map_page(vm->dma, p->page, 0, PAGE_SIZE,
 403                                 PCI_DMA_BIDIRECTIONAL);
 404         if (unlikely(dma_mapping_error(vm->dma, p->daddr))) {
 405                 vm_free_page(vm, p->page);
 406                 return -ENOMEM;
 407         }
 408
 409         return 0;
 410 }
 411
 412 static int setup_page_dma(struct i915_address_space *vm,
 413                           struct i915_page_dma *p)
 414 {
 415         return __setup_page_dma(vm, p, I915_GFP_DMA);
 416 }
 417
 418 static void cleanup_page_dma(struct i915_address_space *vm,
 419                              struct i915_page_dma *p)
 420 {
 421         dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 422         vm_free_page(vm, p->page);
 423 }
 424
 425 #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
 426
 427 #define setup_px(vm, px) setup_page_dma((vm), px_base(px))
 428 #define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
 429 #define fill_px(ppgtt, px, v) fill_page_dma((vm), px_base(px), (v))
 430 #define fill32_px(ppgtt, px, v) fill_page_dma_32((vm), px_base(px), (v))
 431
 432 static void fill_page_dma(struct i915_address_space *vm,
 433                           struct i915_page_dma *p,
 434                           const u64 val)
 435 {
 436         u64 * const vaddr = kmap_atomic(p->page);
 437         int i;
 438
 439         for (i = 0; i < 512; i++)
 440                 vaddr[i] = val;
 441
 442         kunmap_atomic(vaddr);
 443 }
 444
 445 static void fill_page_dma_32(struct i915_address_space *vm,
 446                              struct i915_page_dma *p,
 447                              const u32 v)
 448 {
 449         fill_page_dma(vm, p, (u64)v << 32 | v);
 450 }
 451
 452 static int
 453 setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
 454 {
 455         return __setup_page_dma(vm, &vm->scratch_page, gfp | __GFP_ZERO);
 456 }
 457
 458 static void cleanup_scratch_page(struct i915_address_space *vm)
 459 {
 460         cleanup_page_dma(vm, &vm->scratch_page);
 461 }
 462
 463 static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
 464 {
 465         struct i915_page_table *pt;
 466
 467         pt = kmalloc(sizeof(*pt), GFP_KERNEL | __GFP_NOWARN);
 468         if (unlikely(!pt))
 469                 return ERR_PTR(-ENOMEM);
 470
 471         if (unlikely(setup_px(vm, pt))) {
 472                 kfree(pt);
 473                 return ERR_PTR(-ENOMEM);
 474         }
 475
 476         pt->used_ptes = 0;
 477         return pt;
 478 }
 479
 480 static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt)
 481 {
 482         cleanup_px(vm, pt);
 483         kfree(pt);
 484 }
 485
 486 static void gen8_initialize_pt(struct i915_address_space *vm,
 487                                struct i915_page_table *pt)
 488 {
 489         fill_px(vm, pt,
 490                 gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC));
 491 }
 492
 493 static void gen6_initialize_pt(struct i915_address_space *vm,
 494                                struct i915_page_table *pt)
 495 {
 496         fill32_px(vm, pt,
 497                   vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0));
 498 }
 499
 500 static struct i915_page_directory *alloc_pd(struct i915_address_space *vm)
 501 {
 502         struct i915_page_directory *pd;
 503
 504         pd = kzalloc(sizeof(*pd), GFP_KERNEL | __GFP_NOWARN);
 505         if (unlikely(!pd))
 506                 return ERR_PTR(-ENOMEM);
 507
 508         if (unlikely(setup_px(vm, pd))) {
 509                 kfree(pd);
 510                 return ERR_PTR(-ENOMEM);
 511         }
 512
 513         pd->used_pdes = 0;
 514         return pd;
 515 }
 516
 517 static void free_pd(struct i915_address_space *vm,
 518                     struct i915_page_directory *pd)
 519 {
 520         cleanup_px(vm, pd);
 521         kfree(pd);
 522 }
 523
 524 static void gen8_initialize_pd(struct i915_address_space *vm,
 525                                struct i915_page_directory *pd)
 526 {
 527         unsigned int i;
 528
 529         fill_px(vm, pd,
 530                 gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC));
 531         for (i = 0; i < I915_PDES; i++)
 532                 pd->page_table[i] = vm->scratch_pt;
 533 }
 534
 535 static int __pdp_init(struct i915_address_space *vm,
 536                       struct i915_page_directory_pointer *pdp)
 537 {
 538         const unsigned int pdpes = i915_pdpes_per_pdp(vm);
 539         unsigned int i;
 540
 541         pdp->page_directory = kmalloc_array(pdpes, sizeof(*pdp->page_directory),
 542                                             GFP_KERNEL | __GFP_NOWARN);
 543         if (unlikely(!pdp->page_directory))
 544                 return -ENOMEM;
 545
 546         for (i = 0; i < pdpes; i++)
 547                 pdp->page_directory[i] = vm->scratch_pd;
 548
 549         return 0;
 550 }
 551
 552 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 553 {
 554         kfree(pdp->page_directory);
 555         pdp->page_directory = NULL;
 556 }
 557
 558 static inline bool use_4lvl(const struct i915_address_space *vm)
 559 {
 560         return i915_vm_is_48bit(vm);
 561 }
 562
 563 static struct i915_page_directory_pointer *
 564 alloc_pdp(struct i915_address_space *vm)
 565 {
 566         struct i915_page_directory_pointer *pdp;
 567         int ret = -ENOMEM;
 568
 569         WARN_ON(!use_4lvl(vm));
 570
 571         pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
 572         if (!pdp)
 573                 return ERR_PTR(-ENOMEM);
 574
 575         ret = __pdp_init(vm, pdp);
 576         if (ret)
 577                 goto fail_bitmap;
 578
 579         ret = setup_px(vm, pdp);
 580         if (ret)
 581                 goto fail_page_m;
 582
 583         return pdp;
 584
 585 fail_page_m:
 586         __pdp_fini(pdp);
 587 fail_bitmap:
 588         kfree(pdp);
 589
 590         return ERR_PTR(ret);
 591 }
 592
 593 static void free_pdp(struct i915_address_space *vm,
 594                      struct i915_page_directory_pointer *pdp)
 595 {
 596         __pdp_fini(pdp);
 597
 598         if (!use_4lvl(vm))
 599                 return;
 600
 601         cleanup_px(vm, pdp);
 602         kfree(pdp);
 603 }
 604
 605 static void gen8_initialize_pdp(struct i915_address_space *vm,
 606                                 struct i915_page_directory_pointer *pdp)
 607 {
 608         gen8_ppgtt_pdpe_t scratch_pdpe;
 609
 610         scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
 611
 612         fill_px(vm, pdp, scratch_pdpe);
 613 }
 614
 615 static void gen8_initialize_pml4(struct i915_address_space *vm,
 616                                  struct i915_pml4 *pml4)
 617 {
 618         unsigned int i;
 619
 620         fill_px(vm, pml4,
 621                 gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC));
 622         for (i = 0; i < GEN8_PML4ES_PER_PML4; i++)
 623                 pml4->pdps[i] = vm->scratch_pdp;
 624 }
 625
 626 /* Broadwell Page Directory Pointer Descriptors */
 627 static int gen8_write_pdp(struct drm_i915_gem_request *req,
 628                           unsigned entry,
 629                           dma_addr_t addr)
 630 {
 631         struct intel_engine_cs *engine = req->engine;
 632         u32 *cs;
 633
 634         BUG_ON(entry >= 4);
 635
 636         cs = intel_ring_begin(req, 6);
 637         if (IS_ERR(cs))
 638                 return PTR_ERR(cs);
 639
 640         *cs++ = MI_LOAD_REGISTER_IMM(1);
 641         *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, entry));
 642         *cs++ = upper_32_bits(addr);
 643         *cs++ = MI_LOAD_REGISTER_IMM(1);
 644         *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, entry));
 645         *cs++ = lower_32_bits(addr);
 646         intel_ring_advance(req, cs);
 647
 648         return 0;
 649 }
 650
 651 static int gen8_mm_switch_3lvl(struct i915_hw_ppgtt *ppgtt,
 652                                struct drm_i915_gem_request *req)
 653 {
 654         int i, ret;
 655
 656         for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
 657                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 658
 659                 ret = gen8_write_pdp(req, i, pd_daddr);
 660                 if (ret)
 661                         return ret;
 662         }
 663
 664         return 0;
 665 }
 666
 667 static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt *ppgtt,
 668                                struct drm_i915_gem_request *req)
 669 {
 670         return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
 671 }
 672
 673 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
 674  * the page table structures, we mark them dirty so that
 675  * context switching/execlist queuing code takes extra steps
 676  * to ensure that tlbs are flushed.
 677  */
 678 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
 679 {
 680         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask;
 681 }
 682
 683 /* Removes entries from a single page table, releasing it if it's empty.
 684  * Caller can use the return value to update higher-level entries.
 685  */
 686 static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
 687                                 struct i915_page_table *pt,
 688                                 u64 start, u64 length)
 689 {
 690         unsigned int num_entries = gen8_pte_count(start, length);
 691         unsigned int pte = gen8_pte_index(start);
 692         unsigned int pte_end = pte + num_entries;
 693         const gen8_pte_t scratch_pte =
 694                 gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC);
 695         gen8_pte_t *vaddr;
 696
 697         GEM_BUG_ON(num_entries > pt->used_ptes);
 698
 699         pt->used_ptes -= num_entries;
 700         if (!pt->used_ptes)
 701                 return true;
 702
 703         vaddr = kmap_atomic_px(pt);
 704         while (pte < pte_end)
 705                 vaddr[pte++] = scratch_pte;
 706         kunmap_atomic(vaddr);
 707
 708         return false;
 709 }
 710
 711 static void gen8_ppgtt_set_pde(struct i915_address_space *vm,
 712                                struct i915_page_directory *pd,
 713                                struct i915_page_table *pt,
 714                                unsigned int pde)
 715 {
 716         gen8_pde_t *vaddr;
 717
 718         pd->page_table[pde] = pt;
 719
 720         vaddr = kmap_atomic_px(pd);
 721         vaddr[pde] = gen8_pde_encode(px_dma(pt), I915_CACHE_LLC);
 722         kunmap_atomic(vaddr);
 723 }
 724
 725 static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
 726                                 struct i915_page_directory *pd,
 727                                 u64 start, u64 length)
 728 {
 729         struct i915_page_table *pt;
 730         u32 pde;
 731
 732         gen8_for_each_pde(pt, pd, start, length, pde) {
 733                 GEM_BUG_ON(pt == vm->scratch_pt);
 734
 735                 if (!gen8_ppgtt_clear_pt(vm, pt, start, length))
 736                         continue;
 737
 738                 gen8_ppgtt_set_pde(vm, pd, vm->scratch_pt, pde);
 739                 GEM_BUG_ON(!pd->used_pdes);
 740                 pd->used_pdes--;
 741
 742                 free_pt(vm, pt);
 743         }
 744
 745         return !pd->used_pdes;
 746 }
 747
 748 static void gen8_ppgtt_set_pdpe(struct i915_address_space *vm,
 749                                 struct i915_page_directory_pointer *pdp,
 750                                 struct i915_page_directory *pd,
 751                                 unsigned int pdpe)
 752 {
 753         gen8_ppgtt_pdpe_t *vaddr;
 754
 755         pdp->page_directory[pdpe] = pd;
 756         if (!use_4lvl(vm))
 757                 return;
 758
 759         vaddr = kmap_atomic_px(pdp);
 760         vaddr[pdpe] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
 761         kunmap_atomic(vaddr);
 762 }
 763
 764 /* Removes entries from a single page dir pointer, releasing it if it's empty.
 765  * Caller can use the return value to update higher-level entries
 766  */
 767 static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
 768                                  struct i915_page_directory_pointer *pdp,
 769                                  u64 start, u64 length)
 770 {
 771         struct i915_page_directory *pd;
 772         unsigned int pdpe;
 773
 774         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
 775                 GEM_BUG_ON(pd == vm->scratch_pd);
 776
 777                 if (!gen8_ppgtt_clear_pd(vm, pd, start, length))
 778                         continue;
 779
 780                 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
 781                 GEM_BUG_ON(!pdp->used_pdpes);
 782                 pdp->used_pdpes--;
 783
 784                 free_pd(vm, pd);
 785         }
 786
 787         return !pdp->used_pdpes;
 788 }
 789
 790 static void gen8_ppgtt_clear_3lvl(struct i915_address_space *vm,
 791                                   u64 start, u64 length)
 792 {
 793         gen8_ppgtt_clear_pdp(vm, &i915_vm_to_ppgtt(vm)->pdp, start, length);
 794 }
 795
 796 static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4,
 797                                  struct i915_page_directory_pointer *pdp,
 798                                  unsigned int pml4e)
 799 {
 800         gen8_ppgtt_pml4e_t *vaddr;
 801
 802         pml4->pdps[pml4e] = pdp;
 803
 804         vaddr = kmap_atomic_px(pml4);
 805         vaddr[pml4e] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
 806         kunmap_atomic(vaddr);
 807 }
 808
 809 /* Removes entries from a single pml4.
 810  * This is the top-level structure in 4-level page tables used on gen8+.
 811  * Empty entries are always scratch pml4e.
 812  */
 813 static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
 814                                   u64 start, u64 length)
 815 {
 816         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 817         struct i915_pml4 *pml4 = &ppgtt->pml4;
 818         struct i915_page_directory_pointer *pdp;
 819         unsigned int pml4e;
 820
 821         GEM_BUG_ON(!use_4lvl(vm));
 822
 823         gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
 824                 GEM_BUG_ON(pdp == vm->scratch_pdp);
 825
 826                 if (!gen8_ppgtt_clear_pdp(vm, pdp, start, length))
 827                         continue;
 828
 829                 gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
 830
 831                 free_pdp(vm, pdp);
 832         }
 833 }
 834
 835 static inline struct sgt_dma {
 836         struct scatterlist *sg;
 837         dma_addr_t dma, max;
 838 } sgt_dma(struct i915_vma *vma) {
 839         struct scatterlist *sg = vma->pages->sgl;
 840         dma_addr_t addr = sg_dma_address(sg);
 841         return (struct sgt_dma) { sg, addr, addr + sg->length };
 842 }
 843
 844 struct gen8_insert_pte {
 845         u16 pml4e;
 846         u16 pdpe;
 847         u16 pde;
 848         u16 pte;
 849 };
 850
 851 static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start)
 852 {
 853         return (struct gen8_insert_pte) {
 854                  gen8_pml4e_index(start),
 855                  gen8_pdpe_index(start),
 856                  gen8_pde_index(start),
 857                  gen8_pte_index(start),
 858         };
 859 }
 860
 861 static __always_inline bool
 862 gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
 863                               struct i915_page_directory_pointer *pdp,
 864                               struct sgt_dma *iter,
 865                               struct gen8_insert_pte *idx,
 866                               enum i915_cache_level cache_level)
 867 {
 868         struct i915_page_directory *pd;
 869         const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level);
 870         gen8_pte_t *vaddr;
 871         bool ret;
 872
 873         GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base));
 874         pd = pdp->page_directory[idx->pdpe];
 875         vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
 876         do {
 877                 vaddr[idx->pte] = pte_encode | iter->dma;
 878
 879                 iter->dma += PAGE_SIZE;
 880                 if (iter->dma >= iter->max) {
 881                         iter->sg = __sg_next(iter->sg);
 882                         if (!iter->sg) {
 883                                 ret = false;
 884                                 break;
 885                         }
 886
 887                         iter->dma = sg_dma_address(iter->sg);
 888                         iter->max = iter->dma + iter->sg->length;
 889                 }
 890
 891                 if (++idx->pte == GEN8_PTES) {
 892                         idx->pte = 0;
 893
 894                         if (++idx->pde == I915_PDES) {
 895                                 idx->pde = 0;
 896
 897                                 /* Limited by sg length for 3lvl */
 898                                 if (++idx->pdpe == GEN8_PML4ES_PER_PML4) {
 899                                         idx->pdpe = 0;
 900                                         ret = true;
 901                                         break;
 902                                 }
 903
 904                                 GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base));
 905                                 pd = pdp->page_directory[idx->pdpe];
 906                         }
 907
 908                         kunmap_atomic(vaddr);
 909                         vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
 910                 }
 911         } while (1);
 912         kunmap_atomic(vaddr);
 913
 914         return ret;
 915 }
 916
 917 static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
 918                                    struct i915_vma *vma,
 919                                    enum i915_cache_level cache_level,
 920                                    u32 unused)
 921 {
 922         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 923         struct sgt_dma iter = sgt_dma(vma);
 924         struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
 925
 926         gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx,
 927                                       cache_level);
 928 }
 929
 930 static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
 931                                    struct i915_vma *vma,
 932                                    enum i915_cache_level cache_level,
 933                                    u32 unused)
 934 {
 935         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 936         struct sgt_dma iter = sgt_dma(vma);
 937         struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
 938         struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
 939
 940         while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], &iter,
 941                                              &idx, cache_level))
 942                 GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
 943 }
 944
 945 static void gen8_free_page_tables(struct i915_address_space *vm,
 946                                   struct i915_page_directory *pd)
 947 {
 948         int i;
 949
 950         if (!px_page(pd))
 951                 return;
 952
 953         for (i = 0; i < I915_PDES; i++) {
 954                 if (pd->page_table[i] != vm->scratch_pt)
 955                         free_pt(vm, pd->page_table[i]);
 956         }
 957 }
 958
 959 static int gen8_init_scratch(struct i915_address_space *vm)
 960 {
 961         int ret;
 962
 963         ret = setup_scratch_page(vm, I915_GFP_DMA);
 964         if (ret)
 965                 return ret;
 966
 967         vm->scratch_pt = alloc_pt(vm);
 968         if (IS_ERR(vm->scratch_pt)) {
 969                 ret = PTR_ERR(vm->scratch_pt);
 970                 goto free_scratch_page;
 971         }
 972
 973         vm->scratch_pd = alloc_pd(vm);
 974         if (IS_ERR(vm->scratch_pd)) {
 975                 ret = PTR_ERR(vm->scratch_pd);
 976                 goto free_pt;
 977         }
 978
 979         if (use_4lvl(vm)) {
 980                 vm->scratch_pdp = alloc_pdp(vm);
 981                 if (IS_ERR(vm->scratch_pdp)) {
 982                         ret = PTR_ERR(vm->scratch_pdp);
 983                         goto free_pd;
 984                 }
 985         }
 986
 987         gen8_initialize_pt(vm, vm->scratch_pt);
 988         gen8_initialize_pd(vm, vm->scratch_pd);
 989         if (use_4lvl(vm))
 990                 gen8_initialize_pdp(vm, vm->scratch_pdp);
 991
 992         return 0;
 993
 994 free_pd:
 995         free_pd(vm, vm->scratch_pd);
 996 free_pt:
 997         free_pt(vm, vm->scratch_pt);
 998 free_scratch_page:
 999         cleanup_scratch_page(vm);
1000
1001         return ret;
1002 }
1003
1004 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
1005 {
1006         struct i915_address_space *vm = &ppgtt->base;
1007         struct drm_i915_private *dev_priv = vm->i915;
1008         enum vgt_g2v_type msg;
1009         int i;
1010
1011         if (use_4lvl(vm)) {
1012                 const u64 daddr = px_dma(&ppgtt->pml4);
1013
1014                 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
1015                 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
1016
1017                 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
1018                                 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
1019         } else {
1020                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1021                         const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
1022
1023                         I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
1024                         I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
1025                 }
1026
1027                 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
1028                                 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
1029         }
1030
1031         I915_WRITE(vgtif_reg(g2v_notify), msg);
1032
1033         return 0;
1034 }
1035
1036 static void gen8_free_scratch(struct i915_address_space *vm)
1037 {
1038         if (use_4lvl(vm))
1039                 free_pdp(vm, vm->scratch_pdp);
1040         free_pd(vm, vm->scratch_pd);
1041         free_pt(vm, vm->scratch_pt);
1042         cleanup_scratch_page(vm);
1043 }
1044
1045 static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space *vm,
1046                                     struct i915_page_directory_pointer *pdp)
1047 {
1048         const unsigned int pdpes = i915_pdpes_per_pdp(vm);
1049         int i;
1050
1051         for (i = 0; i < pdpes; i++) {
1052                 if (pdp->page_directory[i] == vm->scratch_pd)
1053                         continue;
1054
1055                 gen8_free_page_tables(vm, pdp->page_directory[i]);
1056                 free_pd(vm, pdp->page_directory[i]);
1057         }
1058
1059         free_pdp(vm, pdp);
1060 }
1061
1062 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
1063 {
1064         int i;
1065
1066         for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) {
1067                 if (ppgtt->pml4.pdps[i] == ppgtt->base.scratch_pdp)
1068                         continue;
1069
1070                 gen8_ppgtt_cleanup_3lvl(&ppgtt->base, ppgtt->pml4.pdps[i]);
1071         }
1072
1073         cleanup_px(&ppgtt->base, &ppgtt->pml4);
1074 }
1075
1076 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
1077 {
1078         struct drm_i915_private *dev_priv = vm->i915;
1079         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1080
1081         if (intel_vgpu_active(dev_priv))
1082                 gen8_ppgtt_notify_vgt(ppgtt, false);
1083
1084         if (use_4lvl(vm))
1085                 gen8_ppgtt_cleanup_4lvl(ppgtt);
1086         else
1087                 gen8_ppgtt_cleanup_3lvl(&ppgtt->base, &ppgtt->pdp);
1088
1089         gen8_free_scratch(vm);
1090 }
1091
1092 static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm,
1093                                struct i915_page_directory *pd,
1094                                u64 start, u64 length)
1095 {
1096         struct i915_page_table *pt;
1097         u64 from = start;
1098         unsigned int pde;
1099
1100         gen8_for_each_pde(pt, pd, start, length, pde) {
1101                 if (pt == vm->scratch_pt) {
1102                         pt = alloc_pt(vm);
1103                         if (IS_ERR(pt))
1104                                 goto unwind;
1105
1106                         gen8_initialize_pt(vm, pt);
1107
1108                         gen8_ppgtt_set_pde(vm, pd, pt, pde);
1109                         pd->used_pdes++;
1110                         GEM_BUG_ON(pd->used_pdes > I915_PDES);
1111                 }
1112
1113                 pt->used_ptes += gen8_pte_count(start, length);
1114         }
1115         return 0;
1116
1117 unwind:
1118         gen8_ppgtt_clear_pd(vm, pd, from, start - from);
1119         return -ENOMEM;
1120 }
1121
1122 static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm,
1123                                 struct i915_page_directory_pointer *pdp,
1124                                 u64 start, u64 length)
1125 {
1126         struct i915_page_directory *pd;
1127         u64 from = start;
1128         unsigned int pdpe;
1129         int ret;
1130
1131         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1132                 if (pd == vm->scratch_pd) {
1133                         pd = alloc_pd(vm);
1134                         if (IS_ERR(pd))
1135                                 goto unwind;
1136
1137                         gen8_initialize_pd(vm, pd);
1138                         gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
1139                         pdp->used_pdpes++;
1140                         GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm));
1141
1142                         mark_tlbs_dirty(i915_vm_to_ppgtt(vm));
1143                 }
1144
1145                 ret = gen8_ppgtt_alloc_pd(vm, pd, start, length);
1146                 if (unlikely(ret))
1147                         goto unwind_pd;
1148         }
1149
1150         return 0;
1151
1152 unwind_pd:
1153         if (!pd->used_pdes) {
1154                 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
1155                 GEM_BUG_ON(!pdp->used_pdpes);
1156                 pdp->used_pdpes--;
1157                 free_pd(vm, pd);
1158         }
1159 unwind:
1160         gen8_ppgtt_clear_pdp(vm, pdp, from, start - from);
1161         return -ENOMEM;
1162 }
1163
1164 static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm,
1165                                  u64 start, u64 length)
1166 {
1167         return gen8_ppgtt_alloc_pdp(vm,
1168                                     &i915_vm_to_ppgtt(vm)->pdp, start, length);
1169 }
1170
1171 static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
1172                                  u64 start, u64 length)
1173 {
1174         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1175         struct i915_pml4 *pml4 = &ppgtt->pml4;
1176         struct i915_page_directory_pointer *pdp;
1177         u64 from = start;
1178         u32 pml4e;
1179         int ret;
1180
1181         gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1182                 if (pml4->pdps[pml4e] == vm->scratch_pdp) {
1183                         pdp = alloc_pdp(vm);
1184                         if (IS_ERR(pdp))
1185                                 goto unwind;
1186
1187                         gen8_initialize_pdp(vm, pdp);
1188                         gen8_ppgtt_set_pml4e(pml4, pdp, pml4e);
1189                 }
1190
1191                 ret = gen8_ppgtt_alloc_pdp(vm, pdp, start, length);
1192                 if (unlikely(ret))
1193                         goto unwind_pdp;
1194         }
1195
1196         return 0;
1197
1198 unwind_pdp:
1199         if (!pdp->used_pdpes) {
1200                 gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
1201                 free_pdp(vm, pdp);
1202         }
1203 unwind:
1204         gen8_ppgtt_clear_4lvl(vm, from, start - from);
1205         return -ENOMEM;
1206 }
1207
1208 static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt,
1209                           struct i915_page_directory_pointer *pdp,
1210                           u64 start, u64 length,
1211                           gen8_pte_t scratch_pte,
1212                           struct seq_file *m)
1213 {
1214         struct i915_address_space *vm = &ppgtt->base;
1215         struct i915_page_directory *pd;
1216         u32 pdpe;
1217
1218         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1219                 struct i915_page_table *pt;
1220                 u64 pd_len = length;
1221                 u64 pd_start = start;
1222                 u32 pde;
1223
1224                 if (pdp->page_directory[pdpe] == ppgtt->base.scratch_pd)
1225                         continue;
1226
1227                 seq_printf(m, "\tPDPE #%d\n", pdpe);
1228                 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
1229                         u32 pte;
1230                         gen8_pte_t *pt_vaddr;
1231
1232                         if (pd->page_table[pde] == ppgtt->base.scratch_pt)
1233                                 continue;
1234
1235                         pt_vaddr = kmap_atomic_px(pt);
1236                         for (pte = 0; pte < GEN8_PTES; pte += 4) {
1237                                 u64 va = (pdpe << GEN8_PDPE_SHIFT |
1238                                           pde << GEN8_PDE_SHIFT |
1239                                           pte << GEN8_PTE_SHIFT);
1240                                 int i;
1241                                 bool found = false;
1242
1243                                 for (i = 0; i < 4; i++)
1244                                         if (pt_vaddr[pte + i] != scratch_pte)
1245                                                 found = true;
1246                                 if (!found)
1247                                         continue;
1248
1249                                 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1250                                 for (i = 0; i < 4; i++) {
1251                                         if (pt_vaddr[pte + i] != scratch_pte)
1252                                                 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1253                                         else
1254                                                 seq_puts(m, "  SCRATCH ");
1255                                 }
1256                                 seq_puts(m, "\n");
1257                         }
1258                         kunmap_atomic(pt_vaddr);
1259                 }
1260         }
1261 }
1262
1263 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1264 {
1265         struct i915_address_space *vm = &ppgtt->base;
1266         const gen8_pte_t scratch_pte =
1267                 gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC);
1268         u64 start = 0, length = ppgtt->base.total;
1269
1270         if (use_4lvl(vm)) {
1271                 u64 pml4e;
1272                 struct i915_pml4 *pml4 = &ppgtt->pml4;
1273                 struct i915_page_directory_pointer *pdp;
1274
1275                 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1276                         if (pml4->pdps[pml4e] == ppgtt->base.scratch_pdp)
1277                                 continue;
1278
1279                         seq_printf(m, "    PML4E #%llu\n", pml4e);
1280                         gen8_dump_pdp(ppgtt, pdp, start, length, scratch_pte, m);
1281                 }
1282         } else {
1283                 gen8_dump_pdp(ppgtt, &ppgtt->pdp, start, length, scratch_pte, m);
1284         }
1285 }
1286
1287 static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
1288 {
1289         struct i915_address_space *vm = &ppgtt->base;
1290         struct i915_page_directory_pointer *pdp = &ppgtt->pdp;
1291         struct i915_page_directory *pd;
1292         u64 start = 0, length = ppgtt->base.total;
1293         u64 from = start;
1294         unsigned int pdpe;
1295
1296         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1297                 pd = alloc_pd(vm);
1298                 if (IS_ERR(pd))
1299                         goto unwind;
1300
1301                 gen8_initialize_pd(vm, pd);
1302                 gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
1303                 pdp->used_pdpes++;
1304         }
1305
1306         pdp->used_pdpes++; /* never remove */
1307         return 0;
1308
1309 unwind:
1310         start -= from;
1311         gen8_for_each_pdpe(pd, pdp, from, start, pdpe) {
1312                 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
1313                 free_pd(vm, pd);
1314         }
1315         pdp->used_pdpes = 0;
1316         return -ENOMEM;
1317 }
1318
1319 /*
1320  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1321  * with a net effect resembling a 2-level page table in normal x86 terms. Each
1322  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1323  * space.
1324  *
1325  */
1326 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1327 {
1328         struct i915_address_space *vm = &ppgtt->base;
1329         struct drm_i915_private *dev_priv = vm->i915;
1330         int ret;
1331
1332         ppgtt->base.total = USES_FULL_48BIT_PPGTT(dev_priv) ?
1333                 1ULL << 48 :
1334                 1ULL << 32;
1335
1336         ret = gen8_init_scratch(&ppgtt->base);
1337         if (ret) {
1338                 ppgtt->base.total = 0;
1339                 return ret;
1340         }
1341
1342         /* There are only few exceptions for gen >=6. chv and bxt.
1343          * And we are not sure about the latter so play safe for now.
1344          */
1345         if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
1346                 ppgtt->base.pt_kmap_wc = true;
1347
1348         if (use_4lvl(vm)) {
1349                 ret = setup_px(&ppgtt->base, &ppgtt->pml4);
1350                 if (ret)
1351                         goto free_scratch;
1352
1353                 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1354
1355                 ppgtt->switch_mm = gen8_mm_switch_4lvl;
1356                 ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_4lvl;
1357                 ppgtt->base.insert_entries = gen8_ppgtt_insert_4lvl;
1358                 ppgtt->base.clear_range = gen8_ppgtt_clear_4lvl;
1359         } else {
1360                 ret = __pdp_init(&ppgtt->base, &ppgtt->pdp);
1361                 if (ret)
1362                         goto free_scratch;
1363
1364                 if (intel_vgpu_active(dev_priv)) {
1365                         ret = gen8_preallocate_top_level_pdp(ppgtt);
1366                         if (ret) {
1367                                 __pdp_fini(&ppgtt->pdp);
1368                                 goto free_scratch;
1369                         }
1370                 }
1371
1372                 ppgtt->switch_mm = gen8_mm_switch_3lvl;
1373                 ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_3lvl;
1374                 ppgtt->base.insert_entries = gen8_ppgtt_insert_3lvl;
1375                 ppgtt->base.clear_range = gen8_ppgtt_clear_3lvl;
1376         }
1377
1378         if (intel_vgpu_active(dev_priv))
1379                 gen8_ppgtt_notify_vgt(ppgtt, true);
1380
1381         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1382         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1383         ppgtt->base.bind_vma = ppgtt_bind_vma;
1384         ppgtt->debug_dump = gen8_dump_ppgtt;
1385
1386         return 0;
1387
1388 free_scratch:
1389         gen8_free_scratch(&ppgtt->base);
1390         return ret;
1391 }
1392
1393 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1394 {
1395         struct i915_address_space *vm = &ppgtt->base;
1396         struct i915_page_table *unused;
1397         gen6_pte_t scratch_pte;
1398         u32 pd_entry, pte, pde;
1399         u32 start = 0, length = ppgtt->base.total;
1400
1401         scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
1402                                      I915_CACHE_LLC, 0);
1403
1404         gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) {
1405                 u32 expected;
1406                 gen6_pte_t *pt_vaddr;
1407                 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1408                 pd_entry = readl(ppgtt->pd_addr + pde);
1409                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1410
1411                 if (pd_entry != expected)
1412                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1413                                    pde,
1414                                    pd_entry,
1415                                    expected);
1416                 seq_printf(m, "\tPDE: %x\n", pd_entry);
1417
1418                 pt_vaddr = kmap_atomic_px(ppgtt->pd.page_table[pde]);
1419
1420                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1421                         unsigned long va =
1422                                 (pde * PAGE_SIZE * GEN6_PTES) +
1423                                 (pte * PAGE_SIZE);
1424                         int i;
1425                         bool found = false;
1426                         for (i = 0; i < 4; i++)
1427                                 if (pt_vaddr[pte + i] != scratch_pte)
1428                                         found = true;
1429                         if (!found)
1430                                 continue;
1431
1432                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1433                         for (i = 0; i < 4; i++) {
1434                                 if (pt_vaddr[pte + i] != scratch_pte)
1435                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1436                                 else
1437                                         seq_puts(m, "  SCRATCH ");
1438                         }
1439                         seq_puts(m, "\n");
1440                 }
1441                 kunmap_atomic(pt_vaddr);
1442         }
1443 }
1444
1445 /* Write pde (index) from the page directory @pd to the page table @pt */
1446 static inline void gen6_write_pde(const struct i915_hw_ppgtt *ppgtt,
1447                                   const unsigned int pde,
1448                                   const struct i915_page_table *pt)
1449 {
1450         /* Caller needs to make sure the write completes if necessary */
1451         writel_relaxed(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID,
1452                        ppgtt->pd_addr + pde);
1453 }
1454
1455 /* Write all the page tables found in the ppgtt structure to incrementing page
1456  * directories. */
1457 static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt,
1458                                   u32 start, u32 length)
1459 {
1460         struct i915_page_table *pt;
1461         unsigned int pde;
1462
1463         gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde)
1464                 gen6_write_pde(ppgtt, pde, pt);
1465
1466         mark_tlbs_dirty(ppgtt);
1467         wmb();
1468 }
1469
1470 static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1471 {
1472         GEM_BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1473         return ppgtt->pd.base.ggtt_offset << 10;
1474 }
1475
1476 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1477                          struct drm_i915_gem_request *req)
1478 {
1479         struct intel_engine_cs *engine = req->engine;
1480         u32 *cs;
1481
1482         /* NB: TLBs must be flushed and invalidated before a switch */
1483         cs = intel_ring_begin(req, 6);
1484         if (IS_ERR(cs))
1485                 return PTR_ERR(cs);
1486
1487         *cs++ = MI_LOAD_REGISTER_IMM(2);
1488         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
1489         *cs++ = PP_DIR_DCLV_2G;
1490         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1491         *cs++ = get_pd_offset(ppgtt);
1492         *cs++ = MI_NOOP;
1493         intel_ring_advance(req, cs);
1494
1495         return 0;
1496 }
1497
1498 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1499                           struct drm_i915_gem_request *req)
1500 {
1501         struct intel_engine_cs *engine = req->engine;
1502         u32 *cs;
1503
1504         /* NB: TLBs must be flushed and invalidated before a switch */
1505         cs = intel_ring_begin(req, 6);
1506         if (IS_ERR(cs))
1507                 return PTR_ERR(cs);
1508
1509         *cs++ = MI_LOAD_REGISTER_IMM(2);
1510         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
1511         *cs++ = PP_DIR_DCLV_2G;
1512         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1513         *cs++ = get_pd_offset(ppgtt);
1514         *cs++ = MI_NOOP;
1515         intel_ring_advance(req, cs);
1516
1517         return 0;
1518 }
1519
1520 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1521                           struct drm_i915_gem_request *req)
1522 {
1523         struct intel_engine_cs *engine = req->engine;
1524         struct drm_i915_private *dev_priv = req->i915;
1525
1526         I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1527         I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
1528         return 0;
1529 }
1530
1531 static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
1532 {
1533         struct intel_engine_cs *engine;
1534         enum intel_engine_id id;
1535
1536         for_each_engine(engine, dev_priv, id) {
1537                 u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
1538                                  GEN8_GFX_PPGTT_48B : 0;
1539                 I915_WRITE(RING_MODE_GEN7(engine),
1540                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
1541         }
1542 }
1543
1544 static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
1545 {
1546         struct intel_engine_cs *engine;
1547         u32 ecochk, ecobits;
1548         enum intel_engine_id id;
1549
1550         ecobits = I915_READ(GAC_ECO_BITS);
1551         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1552
1553         ecochk = I915_READ(GAM_ECOCHK);
1554         if (IS_HASWELL(dev_priv)) {
1555                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1556         } else {
1557                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1558                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1559         }
1560         I915_WRITE(GAM_ECOCHK, ecochk);
1561
1562         for_each_engine(engine, dev_priv, id) {
1563                 /* GFX_MODE is per-ring on gen7+ */
1564                 I915_WRITE(RING_MODE_GEN7(engine),
1565                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1566         }
1567 }
1568
1569 static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
1570 {
1571         u32 ecochk, gab_ctl, ecobits;
1572
1573         ecobits = I915_READ(GAC_ECO_BITS);
1574         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1575                    ECOBITS_PPGTT_CACHE64B);
1576
1577         gab_ctl = I915_READ(GAB_CTL);
1578         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1579
1580         ecochk = I915_READ(GAM_ECOCHK);
1581         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1582
1583         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1584 }
1585
1586 /* PPGTT support for Sandybdrige/Gen6 and later */
1587 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1588                                    u64 start, u64 length)
1589 {
1590         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1591         unsigned int first_entry = start >> PAGE_SHIFT;
1592         unsigned int pde = first_entry / GEN6_PTES;
1593         unsigned int pte = first_entry % GEN6_PTES;
1594         unsigned int num_entries = length >> PAGE_SHIFT;
1595         gen6_pte_t scratch_pte =
1596                 vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
1597
1598         while (num_entries) {
1599                 struct i915_page_table *pt = ppgtt->pd.page_table[pde++];
1600                 unsigned int end = min(pte + num_entries, GEN6_PTES);
1601                 gen6_pte_t *vaddr;
1602
1603                 num_entries -= end - pte;
1604
1605                 /* Note that the hw doesn't support removing PDE on the fly
1606                  * (they are cached inside the context with no means to
1607                  * invalidate the cache), so we can only reset the PTE
1608                  * entries back to scratch.
1609                  */
1610
1611                 vaddr = kmap_atomic_px(pt);
1612                 do {
1613                         vaddr[pte++] = scratch_pte;
1614                 } while (pte < end);
1615                 kunmap_atomic(vaddr);
1616
1617                 pte = 0;
1618         }
1619 }
1620
1621 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1622                                       struct i915_vma *vma,
1623                                       enum i915_cache_level cache_level,
1624                                       u32 flags)
1625 {
1626         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1627         unsigned first_entry = vma->node.start >> PAGE_SHIFT;
1628         unsigned act_pt = first_entry / GEN6_PTES;
1629         unsigned act_pte = first_entry % GEN6_PTES;
1630         const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
1631         struct sgt_dma iter = sgt_dma(vma);
1632         gen6_pte_t *vaddr;
1633
1634         vaddr = kmap_atomic_px(ppgtt->pd.page_table[act_pt]);
1635         do {
1636                 vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
1637
1638                 iter.dma += PAGE_SIZE;
1639                 if (iter.dma == iter.max) {
1640                         iter.sg = __sg_next(iter.sg);
1641                         if (!iter.sg)
1642                                 break;
1643
1644                         iter.dma = sg_dma_address(iter.sg);
1645                         iter.max = iter.dma + iter.sg->length;
1646                 }
1647
1648                 if (++act_pte == GEN6_PTES) {
1649                         kunmap_atomic(vaddr);
1650                         vaddr = kmap_atomic_px(ppgtt->pd.page_table[++act_pt]);
1651                         act_pte = 0;
1652                 }
1653         } while (1);
1654         kunmap_atomic(vaddr);
1655 }
1656
1657 static int gen6_alloc_va_range(struct i915_address_space *vm,
1658                                u64 start, u64 length)
1659 {
1660         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1661         struct i915_page_table *pt;
1662         u64 from = start;
1663         unsigned int pde;
1664         bool flush = false;
1665
1666         gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) {
1667                 if (pt == vm->scratch_pt) {
1668                         pt = alloc_pt(vm);
1669                         if (IS_ERR(pt))
1670                                 goto unwind_out;
1671
1672                         gen6_initialize_pt(vm, pt);
1673                         ppgtt->pd.page_table[pde] = pt;
1674                         gen6_write_pde(ppgtt, pde, pt);
1675                         flush = true;
1676                 }
1677         }
1678
1679         if (flush) {
1680                 mark_tlbs_dirty(ppgtt);
1681                 wmb();
1682         }
1683
1684         return 0;
1685
1686 unwind_out:
1687         gen6_ppgtt_clear_range(vm, from, start);
1688         return -ENOMEM;
1689 }
1690
1691 static int gen6_init_scratch(struct i915_address_space *vm)
1692 {
1693         int ret;
1694
1695         ret = setup_scratch_page(vm, I915_GFP_DMA);
1696         if (ret)
1697                 return ret;
1698
1699         vm->scratch_pt = alloc_pt(vm);
1700         if (IS_ERR(vm->scratch_pt)) {
1701                 cleanup_scratch_page(vm);
1702                 return PTR_ERR(vm->scratch_pt);
1703         }
1704
1705         gen6_initialize_pt(vm, vm->scratch_pt);
1706
1707         return 0;
1708 }
1709
1710 static void gen6_free_scratch(struct i915_address_space *vm)
1711 {
1712         free_pt(vm, vm->scratch_pt);
1713         cleanup_scratch_page(vm);
1714 }
1715
1716 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1717 {
1718         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1719         struct i915_page_directory *pd = &ppgtt->pd;
1720         struct i915_page_table *pt;
1721         u32 pde;
1722
1723         drm_mm_remove_node(&ppgtt->node);
1724
1725         gen6_for_all_pdes(pt, pd, pde)
1726                 if (pt != vm->scratch_pt)
1727                         free_pt(vm, pt);
1728
1729         gen6_free_scratch(vm);
1730 }
1731
1732 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1733 {
1734         struct i915_address_space *vm = &ppgtt->base;
1735         struct drm_i915_private *dev_priv = ppgtt->base.i915;
1736         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1737         int ret;
1738
1739         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1740          * allocator works in address space sizes, so it's multiplied by page
1741          * size. We allocate at the top of the GTT to avoid fragmentation.
1742          */
1743         BUG_ON(!drm_mm_initialized(&ggtt->base.mm));
1744
1745         ret = gen6_init_scratch(vm);
1746         if (ret)
1747                 return ret;
1748
1749         ret = i915_gem_gtt_insert(&ggtt->base, &ppgtt->node,
1750                                   GEN6_PD_SIZE, GEN6_PD_ALIGN,
1751                                   I915_COLOR_UNEVICTABLE,
1752                                   0, ggtt->base.total,
1753                                   PIN_HIGH);
1754         if (ret)
1755                 goto err_out;
1756
1757         if (ppgtt->node.start < ggtt->mappable_end)
1758                 DRM_DEBUG("Forced to use aperture for PDEs\n");
1759
1760         ppgtt->pd.base.ggtt_offset =
1761                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1762
1763         ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm +
1764                 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
1765
1766         return 0;
1767
1768 err_out:
1769         gen6_free_scratch(vm);
1770         return ret;
1771 }
1772
1773 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1774 {
1775         return gen6_ppgtt_allocate_page_directories(ppgtt);
1776 }
1777
1778 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1779                                   u64 start, u64 length)
1780 {
1781         struct i915_page_table *unused;
1782         u32 pde;
1783
1784         gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde)
1785                 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
1786 }
1787
1788 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1789 {
1790         struct drm_i915_private *dev_priv = ppgtt->base.i915;
1791         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1792         int ret;
1793
1794         ppgtt->base.pte_encode = ggtt->base.pte_encode;
1795         if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv))
1796                 ppgtt->switch_mm = gen6_mm_switch;
1797         else if (IS_HASWELL(dev_priv))
1798                 ppgtt->switch_mm = hsw_mm_switch;
1799         else if (IS_GEN7(dev_priv))
1800                 ppgtt->switch_mm = gen7_mm_switch;
1801         else
1802                 BUG();
1803
1804         ret = gen6_ppgtt_alloc(ppgtt);
1805         if (ret)
1806                 return ret;
1807
1808         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1809
1810         gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1811         gen6_write_page_range(ppgtt, 0, ppgtt->base.total);
1812
1813         ret = gen6_alloc_va_range(&ppgtt->base, 0, ppgtt->base.total);
1814         if (ret) {
1815                 gen6_ppgtt_cleanup(&ppgtt->base);
1816                 return ret;
1817         }
1818
1819         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1820         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1821         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1822         ppgtt->base.bind_vma = ppgtt_bind_vma;
1823         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1824         ppgtt->debug_dump = gen6_dump_ppgtt;
1825
1826         DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1827                          ppgtt->node.size >> 20,
1828                          ppgtt->node.start / PAGE_SIZE);
1829
1830         DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n",
1831                          ppgtt->pd.base.ggtt_offset << 10);
1832
1833         return 0;
1834 }
1835
1836 static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
1837                            struct drm_i915_private *dev_priv)
1838 {
1839         ppgtt->base.i915 = dev_priv;
1840         ppgtt->base.dma = &dev_priv->drm.pdev->dev;
1841
1842         if (INTEL_INFO(dev_priv)->gen < 8)
1843                 return gen6_ppgtt_init(ppgtt);
1844         else
1845                 return gen8_ppgtt_init(ppgtt);
1846 }
1847
1848 static void i915_address_space_init(struct i915_address_space *vm,
1849                                     struct drm_i915_private *dev_priv,
1850                                     const char *name)
1851 {
1852         i915_gem_timeline_init(dev_priv, &vm->timeline, name);
1853
1854         drm_mm_init(&vm->mm, 0, vm->total);
1855         vm->mm.head_node.color = I915_COLOR_UNEVICTABLE;
1856
1857         INIT_LIST_HEAD(&vm->active_list);
1858         INIT_LIST_HEAD(&vm->inactive_list);
1859         INIT_LIST_HEAD(&vm->unbound_list);
1860
1861         list_add_tail(&vm->global_link, &dev_priv->vm_list);
1862         pagevec_init(&vm->free_pages);
1863 }
1864
1865 static void i915_address_space_fini(struct i915_address_space *vm)
1866 {
1867         if (pagevec_count(&vm->free_pages))
1868                 vm_free_pages_release(vm);
1869
1870         i915_gem_timeline_fini(&vm->timeline);
1871         drm_mm_takedown(&vm->mm);
1872         list_del(&vm->global_link);
1873 }
1874
1875 static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
1876 {
1877         /* This function is for gtt related workarounds. This function is
1878          * called on driver load and after a GPU reset, so you can place
1879          * workarounds here even if they get overwritten by GPU reset.
1880          */
1881         /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
1882         if (IS_BROADWELL(dev_priv))
1883                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
1884         else if (IS_CHERRYVIEW(dev_priv))
1885                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
1886         else if (IS_GEN9_BC(dev_priv))
1887                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
1888         else if (IS_GEN9_LP(dev_priv))
1889                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
1890 }
1891
1892 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
1893 {
1894         gtt_write_workarounds(dev_priv);
1895
1896         /* In the case of execlists, PPGTT is enabled by the context descriptor
1897          * and the PDPs are contained within the context itself.  We don't
1898          * need to do anything here. */
1899         if (i915.enable_execlists)
1900                 return 0;
1901
1902         if (!USES_PPGTT(dev_priv))
1903                 return 0;
1904
1905         if (IS_GEN6(dev_priv))
1906                 gen6_ppgtt_enable(dev_priv);
1907         else if (IS_GEN7(dev_priv))
1908                 gen7_ppgtt_enable(dev_priv);
1909         else if (INTEL_GEN(dev_priv) >= 8)
1910                 gen8_ppgtt_enable(dev_priv);
1911         else
1912                 MISSING_CASE(INTEL_GEN(dev_priv));
1913
1914         return 0;
1915 }
1916
1917 struct i915_hw_ppgtt *
1918 i915_ppgtt_create(struct drm_i915_private *dev_priv,
1919                   struct drm_i915_file_private *fpriv,
1920                   const char *name)
1921 {
1922         struct i915_hw_ppgtt *ppgtt;
1923         int ret;
1924
1925         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1926         if (!ppgtt)
1927                 return ERR_PTR(-ENOMEM);
1928
1929         ret = __hw_ppgtt_init(ppgtt, dev_priv);
1930         if (ret) {
1931                 kfree(ppgtt);
1932                 return ERR_PTR(ret);
1933         }
1934
1935         kref_init(&ppgtt->ref);
1936         i915_address_space_init(&ppgtt->base, dev_priv, name);
1937         ppgtt->base.file = fpriv;
1938
1939         trace_i915_ppgtt_create(&ppgtt->base);
1940
1941         return ppgtt;
1942 }
1943
1944 void i915_ppgtt_close(struct i915_address_space *vm)
1945 {
1946         struct list_head *phases[] = {
1947                 &vm->active_list,
1948                 &vm->inactive_list,
1949                 &vm->unbound_list,
1950                 NULL,
1951         }, **phase;
1952
1953         GEM_BUG_ON(vm->closed);
1954         vm->closed = true;
1955
1956         for (phase = phases; *phase; phase++) {
1957                 struct i915_vma *vma, *vn;
1958
1959                 list_for_each_entry_safe(vma, vn, *phase, vm_link)
1960                         if (!i915_vma_is_closed(vma))
1961                                 i915_vma_close(vma);
1962         }
1963 }
1964
1965 void i915_ppgtt_release(struct kref *kref)
1966 {
1967         struct i915_hw_ppgtt *ppgtt =
1968                 container_of(kref, struct i915_hw_ppgtt, ref);
1969
1970         trace_i915_ppgtt_release(&ppgtt->base);
1971
1972         /* vmas should already be unbound and destroyed */
1973         WARN_ON(!list_empty(&ppgtt->base.active_list));
1974         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1975         WARN_ON(!list_empty(&ppgtt->base.unbound_list));
1976
1977         ppgtt->base.cleanup(&ppgtt->base);
1978         i915_address_space_fini(&ppgtt->base);
1979         kfree(ppgtt);
1980 }
1981
1982 /* Certain Gen5 chipsets require require idling the GPU before
1983  * unmapping anything from the GTT when VT-d is enabled.
1984  */
1985 static bool needs_idle_maps(struct drm_i915_private *dev_priv)
1986 {
1987         /* Query intel_iommu to see if we need the workaround. Presumably that
1988          * was loaded first.
1989          */
1990         return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
1991 }
1992
1993 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
1994 {
1995         struct intel_engine_cs *engine;
1996         enum intel_engine_id id;
1997
1998         if (INTEL_INFO(dev_priv)->gen < 6)
1999                 return;
2000
2001         for_each_engine(engine, dev_priv, id) {
2002                 u32 fault_reg;
2003                 fault_reg = I915_READ(RING_FAULT_REG(engine));
2004                 if (fault_reg & RING_FAULT_VALID) {
2005                         DRM_DEBUG_DRIVER("Unexpected fault\n"
2006                                          "\tAddr: 0x%08lx\n"
2007                                          "\tAddress space: %s\n"
2008                                          "\tSource ID: %d\n"
2009                                          "\tType: %d\n",
2010                                          fault_reg & PAGE_MASK,
2011                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2012                                          RING_FAULT_SRCID(fault_reg),
2013                                          RING_FAULT_FAULT_TYPE(fault_reg));
2014                         I915_WRITE(RING_FAULT_REG(engine),
2015                                    fault_reg & ~RING_FAULT_VALID);
2016                 }
2017         }
2018
2019         /* Engine specific init may not have been done till this point. */
2020         if (dev_priv->engine[RCS])
2021                 POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
2022 }
2023
2024 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
2025 {
2026         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2027
2028         /* Don't bother messing with faults pre GEN6 as we have little
2029          * documentation supporting that it's a good idea.
2030          */
2031         if (INTEL_GEN(dev_priv) < 6)
2032                 return;
2033
2034         i915_check_and_clear_faults(dev_priv);
2035
2036         ggtt->base.clear_range(&ggtt->base, 0, ggtt->base.total);
2037
2038         i915_ggtt_invalidate(dev_priv);
2039 }
2040
2041 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
2042                                struct sg_table *pages)
2043 {
2044         do {
2045                 if (dma_map_sg(&obj->base.dev->pdev->dev,
2046                                pages->sgl, pages->nents,
2047                                PCI_DMA_BIDIRECTIONAL))
2048                         return 0;
2049
2050                 /* If the DMA remap fails, one cause can be that we have
2051                  * too many objects pinned in a small remapping table,
2052                  * such as swiotlb. Incrementally purge all other objects and
2053                  * try again - if there are no more pages to remove from
2054                  * the DMA remapper, i915_gem_shrink will return 0.
2055                  */
2056                 GEM_BUG_ON(obj->mm.pages == pages);
2057         } while (i915_gem_shrink(to_i915(obj->base.dev),
2058                                  obj->base.size >> PAGE_SHIFT, NULL,
2059                                  I915_SHRINK_BOUND |
2060                                  I915_SHRINK_UNBOUND |
2061                                  I915_SHRINK_ACTIVE));
2062
2063         return -ENOSPC;
2064 }
2065
2066 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2067 {
2068         writeq(pte, addr);
2069 }
2070
2071 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
2072                                   dma_addr_t addr,
2073                                   u64 offset,
2074                                   enum i915_cache_level level,
2075                                   u32 unused)
2076 {
2077         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2078         gen8_pte_t __iomem *pte =
2079                 (gen8_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT);
2080
2081         gen8_set_pte(pte, gen8_pte_encode(addr, level));
2082
2083         ggtt->invalidate(vm->i915);
2084 }
2085
2086 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2087                                      struct i915_vma *vma,
2088                                      enum i915_cache_level level,
2089                                      u32 unused)
2090 {
2091         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2092         struct sgt_iter sgt_iter;
2093         gen8_pte_t __iomem *gtt_entries;
2094         const gen8_pte_t pte_encode = gen8_pte_encode(0, level);
2095         dma_addr_t addr;
2096
2097         gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm;
2098         gtt_entries += vma->node.start >> PAGE_SHIFT;
2099         for_each_sgt_dma(addr, sgt_iter, vma->pages)
2100                 gen8_set_pte(gtt_entries++, pte_encode | addr);
2101
2102         wmb();
2103
2104         /* This next bit makes the above posting read even more important. We
2105          * want to flush the TLBs only after we're certain all the PTE updates
2106          * have finished.
2107          */
2108         ggtt->invalidate(vm->i915);
2109 }
2110
2111 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
2112                                   dma_addr_t addr,
2113                                   u64 offset,
2114                                   enum i915_cache_level level,
2115                                   u32 flags)
2116 {
2117         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2118         gen6_pte_t __iomem *pte =
2119                 (gen6_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT);
2120
2121         iowrite32(vm->pte_encode(addr, level, flags), pte);
2122
2123         ggtt->invalidate(vm->i915);
2124 }
2125
2126 /*
2127  * Binds an object into the global gtt with the specified cache level. The object
2128  * will be accessible to the GPU via commands whose operands reference offsets
2129  * within the global GTT as well as accessible by the GPU through the GMADR
2130  * mapped BAR (dev_priv->mm.gtt->gtt).
2131  */
2132 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2133                                      struct i915_vma *vma,
2134                                      enum i915_cache_level level,
2135                                      u32 flags)
2136 {
2137         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2138         gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm;
2139         unsigned int i = vma->node.start >> PAGE_SHIFT;
2140         struct sgt_iter iter;
2141         dma_addr_t addr;
2142         for_each_sgt_dma(addr, iter, vma->pages)
2143                 iowrite32(vm->pte_encode(addr, level, flags), &entries[i++]);
2144         wmb();
2145
2146         /* This next bit makes the above posting read even more important. We
2147          * want to flush the TLBs only after we're certain all the PTE updates
2148          * have finished.
2149          */
2150         ggtt->invalidate(vm->i915);
2151 }
2152
2153 static void nop_clear_range(struct i915_address_space *vm,
2154                             u64 start, u64 length)
2155 {
2156 }
2157
2158 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2159                                   u64 start, u64 length)
2160 {
2161         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2162         unsigned first_entry = start >> PAGE_SHIFT;
2163         unsigned num_entries = length >> PAGE_SHIFT;
2164         const gen8_pte_t scratch_pte =
2165                 gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC);
2166         gen8_pte_t __iomem *gtt_base =
2167                 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2168         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2169         int i;
2170
2171         if (WARN(num_entries > max_entries,
2172                  "First entry = %d; Num entries = %d (max=%d)\n",
2173                  first_entry, num_entries, max_entries))
2174                 num_entries = max_entries;
2175
2176         for (i = 0; i < num_entries; i++)
2177                 gen8_set_pte(&gtt_base[i], scratch_pte);
2178 }
2179
2180 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
2181 {
2182         struct drm_i915_private *dev_priv = vm->i915;
2183
2184         /*
2185          * Make sure the internal GAM fifo has been cleared of all GTT
2186          * writes before exiting stop_machine(). This guarantees that
2187          * any aperture accesses waiting to start in another process
2188          * cannot back up behind the GTT writes causing a hang.
2189          * The register can be any arbitrary GAM register.
2190          */
2191         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2192 }
2193
2194 struct insert_page {
2195         struct i915_address_space *vm;
2196         dma_addr_t addr;
2197         u64 offset;
2198         enum i915_cache_level level;
2199 };
2200
2201 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
2202 {
2203         struct insert_page *arg = _arg;
2204
2205         gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
2206         bxt_vtd_ggtt_wa(arg->vm);
2207
2208         return 0;
2209 }
2210
2211 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
2212                                           dma_addr_t addr,
2213                                           u64 offset,
2214                                           enum i915_cache_level level,
2215                                           u32 unused)
2216 {
2217         struct insert_page arg = { vm, addr, offset, level };
2218
2219         stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
2220 }
2221
2222 struct insert_entries {
2223         struct i915_address_space *vm;
2224         struct i915_vma *vma;
2225         enum i915_cache_level level;
2226 };
2227
2228 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
2229 {
2230         struct insert_entries *arg = _arg;
2231
2232         gen8_ggtt_insert_entries(arg->vm, arg->vma, arg->level, 0);
2233         bxt_vtd_ggtt_wa(arg->vm);
2234
2235         return 0;
2236 }
2237
2238 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2239                                              struct i915_vma *vma,
2240                                              enum i915_cache_level level,
2241                                              u32 unused)
2242 {
2243         struct insert_entries arg = { vm, vma, level };
2244
2245         stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
2246 }
2247
2248 struct clear_range {
2249         struct i915_address_space *vm;
2250         u64 start;
2251         u64 length;
2252 };
2253
2254 static int bxt_vtd_ggtt_clear_range__cb(void *_arg)
2255 {
2256         struct clear_range *arg = _arg;
2257
2258         gen8_ggtt_clear_range(arg->vm, arg->start, arg->length);
2259         bxt_vtd_ggtt_wa(arg->vm);
2260
2261         return 0;
2262 }
2263
2264 static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space *vm,
2265                                           u64 start,
2266                                           u64 length)
2267 {
2268         struct clear_range arg = { vm, start, length };
2269
2270         stop_machine(bxt_vtd_ggtt_clear_range__cb, &arg, NULL);
2271 }
2272
2273 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2274                                   u64 start, u64 length)
2275 {
2276         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2277         unsigned first_entry = start >> PAGE_SHIFT;
2278         unsigned num_entries = length >> PAGE_SHIFT;
2279         gen6_pte_t scratch_pte, __iomem *gtt_base =
2280                 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2281         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2282         int i;
2283
2284         if (WARN(num_entries > max_entries,
2285                  "First entry = %d; Num entries = %d (max=%d)\n",
2286                  first_entry, num_entries, max_entries))
2287                 num_entries = max_entries;
2288
2289         scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
2290                                      I915_CACHE_LLC, 0);
2291
2292         for (i = 0; i < num_entries; i++)
2293                 iowrite32(scratch_pte, &gtt_base[i]);
2294 }
2295
2296 static void i915_ggtt_insert_page(struct i915_address_space *vm,
2297                                   dma_addr_t addr,
2298                                   u64 offset,
2299                                   enum i915_cache_level cache_level,
2300                                   u32 unused)
2301 {
2302         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2303                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2304
2305         intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
2306 }
2307
2308 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2309                                      struct i915_vma *vma,
2310                                      enum i915_cache_level cache_level,
2311                                      u32 unused)
2312 {
2313         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2314                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2315
2316         intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
2317                                     flags);
2318 }
2319
2320 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2321                                   u64 start, u64 length)
2322 {
2323         intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
2324 }
2325
2326 static int ggtt_bind_vma(struct i915_vma *vma,
2327                          enum i915_cache_level cache_level,
2328                          u32 flags)
2329 {
2330         struct drm_i915_private *i915 = vma->vm->i915;
2331         struct drm_i915_gem_object *obj = vma->obj;
2332         u32 pte_flags;
2333
2334         if (unlikely(!vma->pages)) {
2335                 int ret = i915_get_ggtt_vma_pages(vma);
2336                 if (ret)
2337                         return ret;
2338         }
2339
2340         /* Currently applicable only to VLV */
2341         pte_flags = 0;
2342         if (obj->gt_ro)
2343                 pte_flags |= PTE_READ_ONLY;
2344
2345         intel_runtime_pm_get(i915);
2346         vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
2347         intel_runtime_pm_put(i915);
2348
2349         /*
2350          * Without aliasing PPGTT there's no difference between
2351          * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2352          * upgrade to both bound if we bind either to avoid double-binding.
2353          */
2354         vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
2355
2356         return 0;
2357 }
2358
2359 static void ggtt_unbind_vma(struct i915_vma *vma)
2360 {
2361         struct drm_i915_private *i915 = vma->vm->i915;
2362
2363         intel_runtime_pm_get(i915);
2364         vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
2365         intel_runtime_pm_put(i915);
2366 }
2367
2368 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2369                                  enum i915_cache_level cache_level,
2370                                  u32 flags)
2371 {
2372         struct drm_i915_private *i915 = vma->vm->i915;
2373         u32 pte_flags;
2374         int ret;
2375
2376         if (unlikely(!vma->pages)) {
2377                 ret = i915_get_ggtt_vma_pages(vma);
2378                 if (ret)
2379                         return ret;
2380         }
2381
2382         /* Currently applicable only to VLV */
2383         pte_flags = 0;
2384         if (vma->obj->gt_ro)
2385                 pte_flags |= PTE_READ_ONLY;
2386
2387         if (flags & I915_VMA_LOCAL_BIND) {
2388                 struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt;
2389
2390                 if (!(vma->flags & I915_VMA_LOCAL_BIND) &&
2391                     appgtt->base.allocate_va_range) {
2392                         ret = appgtt->base.allocate_va_range(&appgtt->base,
2393                                                              vma->node.start,
2394                                                              vma->size);
2395                         if (ret)
2396                                 goto err_pages;
2397                 }
2398
2399                 appgtt->base.insert_entries(&appgtt->base, vma, cache_level,
2400                                             pte_flags);
2401         }
2402
2403         if (flags & I915_VMA_GLOBAL_BIND) {
2404                 intel_runtime_pm_get(i915);
2405                 vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
2406                 intel_runtime_pm_put(i915);
2407         }
2408
2409         return 0;
2410
2411 err_pages:
2412         if (!(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND))) {
2413                 if (vma->pages != vma->obj->mm.pages) {
2414                         GEM_BUG_ON(!vma->pages);
2415                         sg_free_table(vma->pages);
2416                         kfree(vma->pages);
2417                 }
2418                 vma->pages = NULL;
2419         }
2420         return ret;
2421 }
2422
2423 static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
2424 {
2425         struct drm_i915_private *i915 = vma->vm->i915;
2426
2427         if (vma->flags & I915_VMA_GLOBAL_BIND) {
2428                 intel_runtime_pm_get(i915);
2429                 vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
2430                 intel_runtime_pm_put(i915);
2431         }
2432
2433         if (vma->flags & I915_VMA_LOCAL_BIND) {
2434                 struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->base;
2435
2436                 vm->clear_range(vm, vma->node.start, vma->size);
2437         }
2438 }
2439
2440 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
2441                                struct sg_table *pages)
2442 {
2443         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2444         struct device *kdev = &dev_priv->drm.pdev->dev;
2445         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2446
2447         if (unlikely(ggtt->do_idle_maps)) {
2448                 if (i915_gem_wait_for_idle(dev_priv, 0)) {
2449                         DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2450                         /* Wait a bit, in hopes it avoids the hang */
2451                         udelay(10);
2452                 }
2453         }
2454
2455         dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL);
2456 }
2457
2458 static void i915_gtt_color_adjust(const struct drm_mm_node *node,
2459                                   unsigned long color,
2460                                   u64 *start,
2461                                   u64 *end)
2462 {
2463         if (node->allocated && node->color != color)
2464                 *start += I915_GTT_PAGE_SIZE;
2465
2466         /* Also leave a space between the unallocated reserved node after the
2467          * GTT and any objects within the GTT, i.e. we use the color adjustment
2468          * to insert a guard page to prevent prefetches crossing over the
2469          * GTT boundary.
2470          */
2471         node = list_next_entry(node, node_list);
2472         if (node->color != color)
2473                 *end -= I915_GTT_PAGE_SIZE;
2474 }
2475
2476 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
2477 {
2478         struct i915_ggtt *ggtt = &i915->ggtt;
2479         struct i915_hw_ppgtt *ppgtt;
2480         int err;
2481
2482         ppgtt = i915_ppgtt_create(i915, ERR_PTR(-EPERM), "[alias]");
2483         if (IS_ERR(ppgtt))
2484                 return PTR_ERR(ppgtt);
2485
2486         if (WARN_ON(ppgtt->base.total < ggtt->base.total)) {
2487                 err = -ENODEV;
2488                 goto err_ppgtt;
2489         }
2490
2491         if (ppgtt->base.allocate_va_range) {
2492                 /* Note we only pre-allocate as far as the end of the global
2493                  * GTT. On 48b / 4-level page-tables, the difference is very,
2494                  * very significant! We have to preallocate as GVT/vgpu does
2495                  * not like the page directory disappearing.
2496                  */
2497                 err = ppgtt->base.allocate_va_range(&ppgtt->base,
2498                                                     0, ggtt->base.total);
2499                 if (err)
2500                         goto err_ppgtt;
2501         }
2502
2503         i915->mm.aliasing_ppgtt = ppgtt;
2504
2505         WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma);
2506         ggtt->base.bind_vma = aliasing_gtt_bind_vma;
2507
2508         WARN_ON(ggtt->base.unbind_vma != ggtt_unbind_vma);
2509         ggtt->base.unbind_vma = aliasing_gtt_unbind_vma;
2510
2511         return 0;
2512
2513 err_ppgtt:
2514         i915_ppgtt_put(ppgtt);
2515         return err;
2516 }
2517
2518 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915)
2519 {
2520         struct i915_ggtt *ggtt = &i915->ggtt;
2521         struct i915_hw_ppgtt *ppgtt;
2522
2523         ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt);
2524         if (!ppgtt)
2525                 return;
2526
2527         i915_ppgtt_put(ppgtt);
2528
2529         ggtt->base.bind_vma = ggtt_bind_vma;
2530         ggtt->base.unbind_vma = ggtt_unbind_vma;
2531 }
2532
2533 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
2534 {
2535         /* Let GEM Manage all of the aperture.
2536          *
2537          * However, leave one page at the end still bound to the scratch page.
2538          * There are a number of places where the hardware apparently prefetches
2539          * past the end of the object, and we've seen multiple hangs with the
2540          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2541          * aperture.  One page should be enough to keep any prefetching inside
2542          * of the aperture.
2543          */
2544         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2545         unsigned long hole_start, hole_end;
2546         struct drm_mm_node *entry;
2547         int ret;
2548
2549         ret = intel_vgt_balloon(dev_priv);
2550         if (ret)
2551                 return ret;
2552
2553         /* Reserve a mappable slot for our lockless error capture */
2554         ret = drm_mm_insert_node_in_range(&ggtt->base.mm, &ggtt->error_capture,
2555                                           PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
2556                                           0, ggtt->mappable_end,
2557                                           DRM_MM_INSERT_LOW);
2558         if (ret)
2559                 return ret;
2560
2561         /* Clear any non-preallocated blocks */
2562         drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) {
2563                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2564                               hole_start, hole_end);
2565                 ggtt->base.clear_range(&ggtt->base, hole_start,
2566                                        hole_end - hole_start);
2567         }
2568
2569         /* And finally clear the reserved guard page */
2570         ggtt->base.clear_range(&ggtt->base,
2571                                ggtt->base.total - PAGE_SIZE, PAGE_SIZE);
2572
2573         if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
2574                 ret = i915_gem_init_aliasing_ppgtt(dev_priv);
2575                 if (ret)
2576                         goto err;
2577         }
2578
2579         return 0;
2580
2581 err:
2582         drm_mm_remove_node(&ggtt->error_capture);
2583         return ret;
2584 }
2585
2586 /**
2587  * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2588  * @dev_priv: i915 device
2589  */
2590 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
2591 {
2592         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2593         struct i915_vma *vma, *vn;
2594
2595         ggtt->base.closed = true;
2596
2597         mutex_lock(&dev_priv->drm.struct_mutex);
2598         WARN_ON(!list_empty(&ggtt->base.active_list));
2599         list_for_each_entry_safe(vma, vn, &ggtt->base.inactive_list, vm_link)
2600                 WARN_ON(i915_vma_unbind(vma));
2601         mutex_unlock(&dev_priv->drm.struct_mutex);
2602
2603         i915_gem_cleanup_stolen(&dev_priv->drm);
2604
2605         mutex_lock(&dev_priv->drm.struct_mutex);
2606         i915_gem_fini_aliasing_ppgtt(dev_priv);
2607
2608         if (drm_mm_node_allocated(&ggtt->error_capture))
2609                 drm_mm_remove_node(&ggtt->error_capture);
2610
2611         if (drm_mm_initialized(&ggtt->base.mm)) {
2612                 intel_vgt_deballoon(dev_priv);
2613                 i915_address_space_fini(&ggtt->base);
2614         }
2615
2616         ggtt->base.cleanup(&ggtt->base);
2617         mutex_unlock(&dev_priv->drm.struct_mutex);
2618
2619         arch_phys_wc_del(ggtt->mtrr);
2620         io_mapping_fini(&ggtt->mappable);
2621 }
2622
2623 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2624 {
2625         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2626         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2627         return snb_gmch_ctl << 20;
2628 }
2629
2630 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2631 {
2632         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2633         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2634         if (bdw_gmch_ctl)
2635                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2636
2637 #ifdef CONFIG_X86_32
2638         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2639         if (bdw_gmch_ctl > 4)
2640                 bdw_gmch_ctl = 4;
2641 #endif
2642
2643         return bdw_gmch_ctl << 20;
2644 }
2645
2646 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2647 {
2648         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2649         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2650
2651         if (gmch_ctrl)
2652                 return 1 << (20 + gmch_ctrl);
2653
2654         return 0;
2655 }
2656
2657 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2658 {
2659         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2660         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2661         return (size_t)snb_gmch_ctl << 25; /* 32 MB units */
2662 }
2663
2664 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2665 {
2666         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2667         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2668         return (size_t)bdw_gmch_ctl << 25; /* 32 MB units */
2669 }
2670
2671 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2672 {
2673         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2674         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2675
2676         /*
2677          * 0x0  to 0x10: 32MB increments starting at 0MB
2678          * 0x11 to 0x16: 4MB increments starting at 8MB
2679          * 0x17 to 0x1d: 4MB increments start at 36MB
2680          */
2681         if (gmch_ctrl < 0x11)
2682                 return (size_t)gmch_ctrl << 25;
2683         else if (gmch_ctrl < 0x17)
2684                 return (size_t)(gmch_ctrl - 0x11 + 2) << 22;
2685         else
2686                 return (size_t)(gmch_ctrl - 0x17 + 9) << 22;
2687 }
2688
2689 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2690 {
2691         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2692         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2693
2694         if (gen9_gmch_ctl < 0xf0)
2695                 return (size_t)gen9_gmch_ctl << 25; /* 32 MB units */
2696         else
2697                 /* 4MB increments starting at 0xf0 for 4MB */
2698                 return (size_t)(gen9_gmch_ctl - 0xf0 + 1) << 22;
2699 }
2700
2701 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
2702 {
2703         struct drm_i915_private *dev_priv = ggtt->base.i915;
2704         struct pci_dev *pdev = dev_priv->drm.pdev;
2705         phys_addr_t phys_addr;
2706         int ret;
2707
2708         /* For Modern GENs the PTEs and register space are split in the BAR */
2709         phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
2710
2711         /*
2712          * On BXT writes larger than 64 bit to the GTT pagetable range will be
2713          * dropped. For WC mappings in general we have 64 byte burst writes
2714          * when the WC buffer is flushed, so we can't use it, but have to
2715          * resort to an uncached mapping. The WC issue is easily caught by the
2716          * readback check when writing GTT PTE entries.
2717          */
2718         if (IS_GEN9_LP(dev_priv))
2719                 ggtt->gsm = ioremap_nocache(phys_addr, size);
2720         else
2721                 ggtt->gsm = ioremap_wc(phys_addr, size);
2722         if (!ggtt->gsm) {
2723                 DRM_ERROR("Failed to map the ggtt page table\n");
2724                 return -ENOMEM;
2725         }
2726
2727         ret = setup_scratch_page(&ggtt->base, GFP_DMA32);
2728         if (ret) {
2729                 DRM_ERROR("Scratch setup failed\n");
2730                 /* iounmap will also get called at remove, but meh */
2731                 iounmap(ggtt->gsm);
2732                 return ret;
2733         }
2734
2735         return 0;
2736 }
2737
2738 static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
2739 {
2740         /* XXX: spec is unclear if this is still needed for CNL+ */
2741         if (!USES_PPGTT(dev_priv)) {
2742                 I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC);
2743                 return;
2744         }
2745
2746         I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
2747         I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
2748         I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
2749         I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
2750         I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
2751         I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
2752         I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
2753         I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2754 }
2755
2756 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2757  * bits. When using advanced contexts each context stores its own PAT, but
2758  * writing this data shouldn't be harmful even in those cases. */
2759 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2760 {
2761         u64 pat;
2762
2763         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
2764               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2765               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2766               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
2767               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2768               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2769               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2770               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2771
2772         if (!USES_PPGTT(dev_priv))
2773                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2774                  * so RTL will always use the value corresponding to
2775                  * pat_sel = 000".
2776                  * So let's disable cache for GGTT to avoid screen corruptions.
2777                  * MOCS still can be used though.
2778                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2779                  * before this patch, i.e. the same uncached + snooping access
2780                  * like on gen6/7 seems to be in effect.
2781                  * - So this just fixes blitter/render access. Again it looks
2782                  * like it's not just uncached access, but uncached + snooping.
2783                  * So we can still hold onto all our assumptions wrt cpu
2784                  * clflushing on LLC machines.
2785                  */
2786                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2787
2788         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2789          * write would work. */
2790         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2791         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2792 }
2793
2794 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2795 {
2796         u64 pat;
2797
2798         /*
2799          * Map WB on BDW to snooped on CHV.
2800          *
2801          * Only the snoop bit has meaning for CHV, the rest is
2802          * ignored.
2803          *
2804          * The hardware will never snoop for certain types of accesses:
2805          * - CPU GTT (GMADR->GGTT->no snoop->memory)
2806          * - PPGTT page tables
2807          * - some other special cycles
2808          *
2809          * As with BDW, we also need to consider the following for GT accesses:
2810          * "For GGTT, there is NO pat_sel[2:0] from the entry,
2811          * so RTL will always use the value corresponding to
2812          * pat_sel = 000".
2813          * Which means we must set the snoop bit in PAT entry 0
2814          * in order to keep the global status page working.
2815          */
2816         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2817               GEN8_PPAT(1, 0) |
2818               GEN8_PPAT(2, 0) |
2819               GEN8_PPAT(3, 0) |
2820               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2821               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2822               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2823               GEN8_PPAT(7, CHV_PPAT_SNOOP);
2824
2825         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2826         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2827 }
2828
2829 static void gen6_gmch_remove(struct i915_address_space *vm)
2830 {
2831         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2832
2833         iounmap(ggtt->gsm);
2834         cleanup_scratch_page(vm);
2835 }
2836
2837 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
2838 {
2839         struct drm_i915_private *dev_priv = ggtt->base.i915;
2840         struct pci_dev *pdev = dev_priv->drm.pdev;
2841         unsigned int size;
2842         u16 snb_gmch_ctl;
2843         int err;
2844
2845         /* TODO: We're not aware of mappable constraints on gen8 yet */
2846         ggtt->mappable_base = pci_resource_start(pdev, 2);
2847         ggtt->mappable_end = pci_resource_len(pdev, 2);
2848
2849         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
2850         if (!err)
2851                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
2852         if (err)
2853                 DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
2854
2855         pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2856
2857         if (INTEL_GEN(dev_priv) >= 9) {
2858                 ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
2859                 size = gen8_get_total_gtt_size(snb_gmch_ctl);
2860         } else if (IS_CHERRYVIEW(dev_priv)) {
2861                 ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
2862                 size = chv_get_total_gtt_size(snb_gmch_ctl);
2863         } else {
2864                 ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
2865                 size = gen8_get_total_gtt_size(snb_gmch_ctl);
2866         }
2867
2868         ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2869
2870         if (INTEL_GEN(dev_priv) >= 10)
2871                 cnl_setup_private_ppat(dev_priv);
2872         else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
2873                 chv_setup_private_ppat(dev_priv);
2874         else
2875                 bdw_setup_private_ppat(dev_priv);
2876
2877         ggtt->base.cleanup = gen6_gmch_remove;
2878         ggtt->base.bind_vma = ggtt_bind_vma;
2879         ggtt->base.unbind_vma = ggtt_unbind_vma;
2880         ggtt->base.insert_page = gen8_ggtt_insert_page;
2881         ggtt->base.clear_range = nop_clear_range;
2882         if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
2883                 ggtt->base.clear_range = gen8_ggtt_clear_range;
2884
2885         ggtt->base.insert_entries = gen8_ggtt_insert_entries;
2886
2887         /* Serialize GTT updates with aperture access on BXT if VT-d is on. */
2888         if (intel_ggtt_update_needs_vtd_wa(dev_priv)) {
2889                 ggtt->base.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
2890                 ggtt->base.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
2891                 if (ggtt->base.clear_range != nop_clear_range)
2892                         ggtt->base.clear_range = bxt_vtd_ggtt_clear_range__BKL;
2893         }
2894
2895         ggtt->invalidate = gen6_ggtt_invalidate;
2896
2897         return ggtt_probe_common(ggtt, size);
2898 }
2899
2900 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
2901 {
2902         struct drm_i915_private *dev_priv = ggtt->base.i915;
2903         struct pci_dev *pdev = dev_priv->drm.pdev;
2904         unsigned int size;
2905         u16 snb_gmch_ctl;
2906         int err;
2907
2908         ggtt->mappable_base = pci_resource_start(pdev, 2);
2909         ggtt->mappable_end = pci_resource_len(pdev, 2);
2910
2911         /* 64/512MB is the current min/max we actually know of, but this is just
2912          * a coarse sanity check.
2913          */
2914         if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
2915                 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end);
2916                 return -ENXIO;
2917         }
2918
2919         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
2920         if (!err)
2921                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
2922         if (err)
2923                 DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
2924         pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2925
2926         ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
2927
2928         size = gen6_get_total_gtt_size(snb_gmch_ctl);
2929         ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2930
2931         ggtt->base.clear_range = gen6_ggtt_clear_range;
2932         ggtt->base.insert_page = gen6_ggtt_insert_page;
2933         ggtt->base.insert_entries = gen6_ggtt_insert_entries;
2934         ggtt->base.bind_vma = ggtt_bind_vma;
2935         ggtt->base.unbind_vma = ggtt_unbind_vma;
2936         ggtt->base.cleanup = gen6_gmch_remove;
2937
2938         ggtt->invalidate = gen6_ggtt_invalidate;
2939
2940         if (HAS_EDRAM(dev_priv))
2941                 ggtt->base.pte_encode = iris_pte_encode;
2942         else if (IS_HASWELL(dev_priv))
2943                 ggtt->base.pte_encode = hsw_pte_encode;
2944         else if (IS_VALLEYVIEW(dev_priv))
2945                 ggtt->base.pte_encode = byt_pte_encode;
2946         else if (INTEL_GEN(dev_priv) >= 7)
2947                 ggtt->base.pte_encode = ivb_pte_encode;
2948         else
2949                 ggtt->base.pte_encode = snb_pte_encode;
2950
2951         return ggtt_probe_common(ggtt, size);
2952 }
2953
2954 static void i915_gmch_remove(struct i915_address_space *vm)
2955 {
2956         intel_gmch_remove();
2957 }
2958
2959 static int i915_gmch_probe(struct i915_ggtt *ggtt)
2960 {
2961         struct drm_i915_private *dev_priv = ggtt->base.i915;
2962         int ret;
2963
2964         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL);
2965         if (!ret) {
2966                 DRM_ERROR("failed to set up gmch\n");
2967                 return -EIO;
2968         }
2969
2970         intel_gtt_get(&ggtt->base.total,
2971                       &ggtt->stolen_size,
2972                       &ggtt->mappable_base,
2973                       &ggtt->mappable_end);
2974
2975         ggtt->do_idle_maps = needs_idle_maps(dev_priv);
2976         ggtt->base.insert_page = i915_ggtt_insert_page;
2977         ggtt->base.insert_entries = i915_ggtt_insert_entries;
2978         ggtt->base.clear_range = i915_ggtt_clear_range;
2979         ggtt->base.bind_vma = ggtt_bind_vma;
2980         ggtt->base.unbind_vma = ggtt_unbind_vma;
2981         ggtt->base.cleanup = i915_gmch_remove;
2982
2983         ggtt->invalidate = gmch_ggtt_invalidate;
2984
2985         if (unlikely(ggtt->do_idle_maps))
2986                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2987
2988         return 0;
2989 }
2990
2991 /**
2992  * i915_ggtt_probe_hw - Probe GGTT hardware location
2993  * @dev_priv: i915 device
2994  */
2995 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
2996 {
2997         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2998         int ret;
2999
3000         ggtt->base.i915 = dev_priv;
3001         ggtt->base.dma = &dev_priv->drm.pdev->dev;
3002
3003         if (INTEL_GEN(dev_priv) <= 5)
3004                 ret = i915_gmch_probe(ggtt);
3005         else if (INTEL_GEN(dev_priv) < 8)
3006                 ret = gen6_gmch_probe(ggtt);
3007         else
3008                 ret = gen8_gmch_probe(ggtt);
3009         if (ret)
3010                 return ret;
3011
3012         /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
3013          * This is easier than doing range restriction on the fly, as we
3014          * currently don't have any bits spare to pass in this upper
3015          * restriction!
3016          */
3017         if (HAS_GUC(dev_priv) && i915.enable_guc_loading) {
3018                 ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
3019                 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3020         }
3021
3022         if ((ggtt->base.total - 1) >> 32) {
3023                 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3024                           " of address space! Found %lldM!\n",
3025                           ggtt->base.total >> 20);
3026                 ggtt->base.total = 1ULL << 32;
3027                 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3028         }
3029
3030         if (ggtt->mappable_end > ggtt->base.total) {
3031                 DRM_ERROR("mappable aperture extends past end of GGTT,"
3032                           " aperture=%llx, total=%llx\n",
3033                           ggtt->mappable_end, ggtt->base.total);
3034                 ggtt->mappable_end = ggtt->base.total;
3035         }
3036
3037         /* GMADR is the PCI mmio aperture into the global GTT. */
3038         DRM_INFO("Memory usable by graphics device = %lluM\n",
3039                  ggtt->base.total >> 20);
3040         DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20);
3041         DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt->stolen_size >> 20);
3042         if (intel_vtd_active())
3043                 DRM_INFO("VT-d active for gfx access\n");
3044
3045         return 0;
3046 }
3047
3048 /**
3049  * i915_ggtt_init_hw - Initialize GGTT hardware
3050  * @dev_priv: i915 device
3051  */
3052 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
3053 {
3054         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3055         int ret;
3056
3057         INIT_LIST_HEAD(&dev_priv->vm_list);
3058
3059         /* Note that we use page colouring to enforce a guard page at the
3060          * end of the address space. This is required as the CS may prefetch
3061          * beyond the end of the batch buffer, across the page boundary,
3062          * and beyond the end of the GTT if we do not provide a guard.
3063          */
3064         mutex_lock(&dev_priv->drm.struct_mutex);
3065         i915_address_space_init(&ggtt->base, dev_priv, "[global]");
3066         if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
3067                 ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
3068         mutex_unlock(&dev_priv->drm.struct_mutex);
3069
3070         if (!io_mapping_init_wc(&dev_priv->ggtt.mappable,
3071                                 dev_priv->ggtt.mappable_base,
3072                                 dev_priv->ggtt.mappable_end)) {
3073                 ret = -EIO;
3074                 goto out_gtt_cleanup;
3075         }
3076
3077         ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end);
3078
3079         /*
3080          * Initialise stolen early so that we may reserve preallocated
3081          * objects for the BIOS to KMS transition.
3082          */
3083         ret = i915_gem_init_stolen(dev_priv);
3084         if (ret)
3085                 goto out_gtt_cleanup;
3086
3087         return 0;
3088
3089 out_gtt_cleanup:
3090         ggtt->base.cleanup(&ggtt->base);
3091         return ret;
3092 }
3093
3094 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
3095 {
3096         if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt())
3097                 return -EIO;
3098
3099         return 0;
3100 }
3101
3102 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
3103 {
3104         GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
3105
3106         i915->ggtt.invalidate = guc_ggtt_invalidate;
3107 }
3108
3109 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
3110 {
3111         /* We should only be called after i915_ggtt_enable_guc() */
3112         GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
3113
3114         i915->ggtt.invalidate = gen6_ggtt_invalidate;
3115 }
3116
3117 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
3118 {
3119         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3120         struct drm_i915_gem_object *obj, *on;
3121
3122         i915_check_and_clear_faults(dev_priv);
3123
3124         /* First fill our portion of the GTT with scratch pages */
3125         ggtt->base.clear_range(&ggtt->base, 0, ggtt->base.total);
3126
3127         ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */
3128
3129         /* clflush objects bound into the GGTT and rebind them. */
3130         list_for_each_entry_safe(obj, on,
3131                                  &dev_priv->mm.bound_list, global_link) {
3132                 bool ggtt_bound = false;
3133                 struct i915_vma *vma;
3134
3135                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3136                         if (vma->vm != &ggtt->base)
3137                                 continue;
3138
3139                         if (!i915_vma_unbind(vma))
3140                                 continue;
3141
3142                         WARN_ON(i915_vma_bind(vma, obj->cache_level,
3143                                               PIN_UPDATE));
3144                         ggtt_bound = true;
3145                 }
3146
3147                 if (ggtt_bound)
3148                         WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
3149         }
3150
3151         ggtt->base.closed = false;
3152
3153         if (INTEL_GEN(dev_priv) >= 8) {
3154                 if (INTEL_GEN(dev_priv) >= 10)
3155                         cnl_setup_private_ppat(dev_priv);
3156                 else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
3157                         chv_setup_private_ppat(dev_priv);
3158                 else
3159                         bdw_setup_private_ppat(dev_priv);
3160
3161                 return;
3162         }
3163
3164         if (USES_PPGTT(dev_priv)) {
3165                 struct i915_address_space *vm;
3166
3167                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3168                         struct i915_hw_ppgtt *ppgtt;
3169
3170                         if (i915_is_ggtt(vm))
3171                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
3172                         else
3173                                 ppgtt = i915_vm_to_ppgtt(vm);
3174
3175                         gen6_write_page_range(ppgtt, 0, ppgtt->base.total);
3176                 }
3177         }
3178
3179         i915_ggtt_invalidate(dev_priv);
3180 }
3181
3182 static struct scatterlist *
3183 rotate_pages(const dma_addr_t *in, unsigned int offset,
3184              unsigned int width, unsigned int height,
3185              unsigned int stride,
3186              struct sg_table *st, struct scatterlist *sg)
3187 {
3188         unsigned int column, row;
3189         unsigned int src_idx;
3190
3191         for (column = 0; column < width; column++) {
3192                 src_idx = stride * (height - 1) + column;
3193                 for (row = 0; row < height; row++) {
3194                         st->nents++;
3195                         /* We don't need the pages, but need to initialize
3196                          * the entries so the sg list can be happily traversed.
3197                          * The only thing we need are DMA addresses.
3198                          */
3199                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
3200                         sg_dma_address(sg) = in[offset + src_idx];
3201                         sg_dma_len(sg) = PAGE_SIZE;
3202                         sg = sg_next(sg);
3203                         src_idx -= stride;
3204                 }
3205         }
3206
3207         return sg;
3208 }
3209
3210 static noinline struct sg_table *
3211 intel_rotate_pages(struct intel_rotation_info *rot_info,
3212                    struct drm_i915_gem_object *obj)
3213 {
3214         const unsigned long n_pages = obj->base.size / PAGE_SIZE;
3215         unsigned int size = intel_rotation_info_size(rot_info);
3216         struct sgt_iter sgt_iter;
3217         dma_addr_t dma_addr;
3218         unsigned long i;
3219         dma_addr_t *page_addr_list;
3220         struct sg_table *st;
3221         struct scatterlist *sg;
3222         int ret = -ENOMEM;
3223
3224         /* Allocate a temporary list of source pages for random access. */
3225         page_addr_list = kvmalloc_array(n_pages,
3226                                         sizeof(dma_addr_t),
3227                                         GFP_KERNEL);
3228         if (!page_addr_list)
3229                 return ERR_PTR(ret);
3230
3231         /* Allocate target SG list. */
3232         st = kmalloc(sizeof(*st), GFP_KERNEL);
3233         if (!st)
3234                 goto err_st_alloc;
3235
3236         ret = sg_alloc_table(st, size, GFP_KERNEL);
3237         if (ret)
3238                 goto err_sg_alloc;
3239
3240         /* Populate source page list from the object. */
3241         i = 0;
3242         for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages)
3243                 page_addr_list[i++] = dma_addr;
3244
3245         GEM_BUG_ON(i != n_pages);
3246         st->nents = 0;
3247         sg = st->sgl;
3248
3249         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
3250                 sg = rotate_pages(page_addr_list, rot_info->plane[i].offset,
3251                                   rot_info->plane[i].width, rot_info->plane[i].height,
3252                                   rot_info->plane[i].stride, st, sg);
3253         }
3254
3255         DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n",
3256                       obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size);
3257
3258         kvfree(page_addr_list);
3259
3260         return st;
3261
3262 err_sg_alloc:
3263         kfree(st);
3264 err_st_alloc:
3265         kvfree(page_addr_list);
3266
3267         DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
3268                       obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size);
3269
3270         return ERR_PTR(ret);
3271 }
3272
3273 static noinline struct sg_table *
3274 intel_partial_pages(const struct i915_ggtt_view *view,
3275                     struct drm_i915_gem_object *obj)
3276 {
3277         struct sg_table *st;
3278         struct scatterlist *sg, *iter;
3279         unsigned int count = view->partial.size;
3280         unsigned int offset;
3281         int ret = -ENOMEM;
3282
3283         st = kmalloc(sizeof(*st), GFP_KERNEL);
3284         if (!st)
3285                 goto err_st_alloc;
3286
3287         ret = sg_alloc_table(st, count, GFP_KERNEL);
3288         if (ret)
3289                 goto err_sg_alloc;
3290
3291         iter = i915_gem_object_get_sg(obj, view->partial.offset, &offset);
3292         GEM_BUG_ON(!iter);
3293
3294         sg = st->sgl;
3295         st->nents = 0;
3296         do {
3297                 unsigned int len;
3298
3299                 len = min(iter->length - (offset << PAGE_SHIFT),
3300                           count << PAGE_SHIFT);
3301                 sg_set_page(sg, NULL, len, 0);
3302                 sg_dma_address(sg) =
3303                         sg_dma_address(iter) + (offset << PAGE_SHIFT);
3304                 sg_dma_len(sg) = len;
3305
3306                 st->nents++;
3307                 count -= len >> PAGE_SHIFT;
3308                 if (count == 0) {
3309                         sg_mark_end(sg);
3310                         return st;
3311                 }
3312
3313                 sg = __sg_next(sg);
3314                 iter = __sg_next(iter);
3315                 offset = 0;
3316         } while (1);
3317
3318 err_sg_alloc:
3319         kfree(st);
3320 err_st_alloc:
3321         return ERR_PTR(ret);
3322 }
3323
3324 static int
3325 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3326 {
3327         int ret;
3328
3329         /* The vma->pages are only valid within the lifespan of the borrowed
3330          * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
3331          * must be the vma->pages. A simple rule is that vma->pages must only
3332          * be accessed when the obj->mm.pages are pinned.
3333          */
3334         GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj));
3335
3336         switch (vma->ggtt_view.type) {
3337         case I915_GGTT_VIEW_NORMAL:
3338                 vma->pages = vma->obj->mm.pages;
3339                 return 0;
3340
3341         case I915_GGTT_VIEW_ROTATED:
3342                 vma->pages =
3343                         intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
3344                 break;
3345
3346         case I915_GGTT_VIEW_PARTIAL:
3347                 vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
3348                 break;
3349
3350         default:
3351                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3352                           vma->ggtt_view.type);
3353                 return -EINVAL;
3354         }
3355
3356         ret = 0;
3357         if (unlikely(IS_ERR(vma->pages))) {
3358                 ret = PTR_ERR(vma->pages);
3359                 vma->pages = NULL;
3360                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3361                           vma->ggtt_view.type, ret);
3362         }
3363         return ret;
3364 }
3365
3366 /**
3367  * i915_gem_gtt_reserve - reserve a node in an address_space (GTT)
3368  * @vm: the &struct i915_address_space
3369  * @node: the &struct drm_mm_node (typically i915_vma.mode)
3370  * @size: how much space to allocate inside the GTT,
3371  *        must be #I915_GTT_PAGE_SIZE aligned
3372  * @offset: where to insert inside the GTT,
3373  *          must be #I915_GTT_MIN_ALIGNMENT aligned, and the node
3374  *          (@offset + @size) must fit within the address space
3375  * @color: color to apply to node, if this node is not from a VMA,
3376  *         color must be #I915_COLOR_UNEVICTABLE
3377  * @flags: control search and eviction behaviour
3378  *
3379  * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside
3380  * the address space (using @size and @color). If the @node does not fit, it
3381  * tries to evict any overlapping nodes from the GTT, including any
3382  * neighbouring nodes if the colors do not match (to ensure guard pages between
3383  * differing domains). See i915_gem_evict_for_node() for the gory details
3384  * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on
3385  * evicting active overlapping objects, and any overlapping node that is pinned
3386  * or marked as unevictable will also result in failure.
3387  *
3388  * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3389  * asked to wait for eviction and interrupted.
3390  */
3391 int i915_gem_gtt_reserve(struct i915_address_space *vm,
3392                          struct drm_mm_node *node,
3393                          u64 size, u64 offset, unsigned long color,
3394                          unsigned int flags)
3395 {
3396         int err;
3397
3398         GEM_BUG_ON(!size);
3399         GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
3400         GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
3401         GEM_BUG_ON(range_overflows(offset, size, vm->total));
3402         GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->base);
3403         GEM_BUG_ON(drm_mm_node_allocated(node));
3404
3405         node->size = size;
3406         node->start = offset;
3407         node->color = color;
3408
3409         err = drm_mm_reserve_node(&vm->mm, node);
3410         if (err != -ENOSPC)
3411                 return err;
3412
3413         if (flags & PIN_NOEVICT)
3414                 return -ENOSPC;
3415
3416         err = i915_gem_evict_for_node(vm, node, flags);
3417         if (err == 0)
3418                 err = drm_mm_reserve_node(&vm->mm, node);
3419
3420         return err;
3421 }
3422
3423 static u64 random_offset(u64 start, u64 end, u64 len, u64 align)
3424 {
3425         u64 range, addr;
3426
3427         GEM_BUG_ON(range_overflows(start, len, end));
3428         GEM_BUG_ON(round_up(start, align) > round_down(end - len, align));
3429
3430         range = round_down(end - len, align) - round_up(start, align);
3431         if (range) {
3432                 if (sizeof(unsigned long) == sizeof(u64)) {
3433                         addr = get_random_long();
3434                 } else {
3435                         addr = get_random_int();
3436                         if (range > U32_MAX) {
3437                                 addr <<= 32;
3438                                 addr |= get_random_int();
3439                         }
3440                 }
3441                 div64_u64_rem(addr, range, &addr);
3442                 start += addr;
3443         }
3444
3445         return round_up(start, align);
3446 }
3447
3448 /**
3449  * i915_gem_gtt_insert - insert a node into an address_space (GTT)
3450  * @vm: the &struct i915_address_space
3451  * @node: the &struct drm_mm_node (typically i915_vma.node)
3452  * @size: how much space to allocate inside the GTT,
3453  *        must be #I915_GTT_PAGE_SIZE aligned
3454  * @alignment: required alignment of starting offset, may be 0 but
3455  *             if specified, this must be a power-of-two and at least
3456  *             #I915_GTT_MIN_ALIGNMENT
3457  * @color: color to apply to node
3458  * @start: start of any range restriction inside GTT (0 for all),
3459  *         must be #I915_GTT_PAGE_SIZE aligned
3460  * @end: end of any range restriction inside GTT (U64_MAX for all),
3461  *       must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX
3462  * @flags: control search and eviction behaviour
3463  *
3464  * i915_gem_gtt_insert() first searches for an available hole into which
3465  * is can insert the node. The hole address is aligned to @alignment and
3466  * its @size must then fit entirely within the [@start, @end] bounds. The
3467  * nodes on either side of the hole must match @color, or else a guard page
3468  * will be inserted between the two nodes (or the node evicted). If no
3469  * suitable hole is found, first a victim is randomly selected and tested
3470  * for eviction, otherwise then the LRU list of objects within the GTT
3471  * is scanned to find the first set of replacement nodes to create the hole.
3472  * Those old overlapping nodes are evicted from the GTT (and so must be
3473  * rebound before any future use). Any node that is currently pinned cannot
3474  * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently
3475  * active and #PIN_NONBLOCK is specified, that node is also skipped when
3476  * searching for an eviction candidate. See i915_gem_evict_something() for
3477  * the gory details on the eviction algorithm.
3478  *
3479  * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3480  * asked to wait for eviction and interrupted.
3481  */
3482 int i915_gem_gtt_insert(struct i915_address_space *vm,
3483                         struct drm_mm_node *node,
3484                         u64 size, u64 alignment, unsigned long color,
3485                         u64 start, u64 end, unsigned int flags)
3486 {
3487         enum drm_mm_insert_mode mode;
3488         u64 offset;
3489         int err;
3490
3491         lockdep_assert_held(&vm->i915->drm.struct_mutex);
3492         GEM_BUG_ON(!size);
3493         GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
3494         GEM_BUG_ON(alignment && !is_power_of_2(alignment));
3495         GEM_BUG_ON(alignment && !IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
3496         GEM_BUG_ON(start >= end);
3497         GEM_BUG_ON(start > 0  && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
3498         GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
3499         GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->base);
3500         GEM_BUG_ON(drm_mm_node_allocated(node));
3501
3502         if (unlikely(range_overflows(start, size, end)))
3503                 return -ENOSPC;
3504
3505         if (unlikely(round_up(start, alignment) > round_down(end - size, alignment)))
3506                 return -ENOSPC;
3507
3508         mode = DRM_MM_INSERT_BEST;
3509         if (flags & PIN_HIGH)
3510                 mode = DRM_MM_INSERT_HIGH;
3511         if (flags & PIN_MAPPABLE)
3512                 mode = DRM_MM_INSERT_LOW;
3513
3514         /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks,
3515          * so we know that we always have a minimum alignment of 4096.
3516          * The drm_mm range manager is optimised to return results
3517          * with zero alignment, so where possible use the optimal
3518          * path.
3519          */
3520         BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT > I915_GTT_PAGE_SIZE);
3521         if (alignment <= I915_GTT_MIN_ALIGNMENT)
3522                 alignment = 0;
3523
3524         err = drm_mm_insert_node_in_range(&vm->mm, node,
3525                                           size, alignment, color,
3526                                           start, end, mode);
3527         if (err != -ENOSPC)
3528                 return err;
3529
3530         if (flags & PIN_NOEVICT)
3531                 return -ENOSPC;
3532
3533         /* No free space, pick a slot at random.
3534          *
3535          * There is a pathological case here using a GTT shared between
3536          * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt):
3537          *
3538          *    |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->|
3539          *         (64k objects)             (448k objects)
3540          *
3541          * Now imagine that the eviction LRU is ordered top-down (just because
3542          * pathology meets real life), and that we need to evict an object to
3543          * make room inside the aperture. The eviction scan then has to walk
3544          * the 448k list before it finds one within range. And now imagine that
3545          * it has to search for a new hole between every byte inside the memcpy,
3546          * for several simultaneous clients.
3547          *
3548          * On a full-ppgtt system, if we have run out of available space, there
3549          * will be lots and lots of objects in the eviction list! Again,
3550          * searching that LRU list may be slow if we are also applying any
3551          * range restrictions (e.g. restriction to low 4GiB) and so, for
3552          * simplicity and similarilty between different GTT, try the single
3553          * random replacement first.
3554          */
3555         offset = random_offset(start, end,
3556                                size, alignment ?: I915_GTT_MIN_ALIGNMENT);
3557         err = i915_gem_gtt_reserve(vm, node, size, offset, color, flags);
3558         if (err != -ENOSPC)
3559                 return err;
3560
3561         /* Randomly selected placement is pinned, do a search */
3562         err = i915_gem_evict_something(vm, size, alignment, color,
3563                                        start, end, flags);
3564         if (err)
3565                 return err;
3566
3567         return drm_mm_insert_node_in_range(&vm->mm, node,
3568                                            size, alignment, color,
3569                                            start, end, DRM_MM_INSERT_EVICT);
3570 }
3571
3572 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3573 #include "selftests/mock_gtt.c"
3574 #include "selftests/i915_gem_gtt.c"
3575 #endif