2 * Copyright © 2010 Daniel Vetter
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <drm/i915_drm.h>
28 #include "i915_trace.h"
29 #include "intel_drv.h"
31 typedef uint32_t gtt_pte_t;
34 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
36 #define GEN6_PDE_VALID (1 << 0)
37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
38 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
40 #define GEN6_PTE_VALID (1 << 0)
41 #define GEN6_PTE_UNCACHED (1 << 1)
42 #define HSW_PTE_UNCACHED (0)
43 #define GEN6_PTE_CACHE_LLC (2 << 1)
44 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
45 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
47 static inline gtt_pte_t pte_encode(struct drm_device *dev,
49 enum i915_cache_level level)
51 gtt_pte_t pte = GEN6_PTE_VALID;
52 pte |= GEN6_PTE_ADDR_ENCODE(addr);
55 case I915_CACHE_LLC_MLC:
56 /* Haswell doesn't set L3 this way */
58 pte |= GEN6_PTE_CACHE_LLC;
60 pte |= GEN6_PTE_CACHE_LLC_MLC;
63 pte |= GEN6_PTE_CACHE_LLC;
67 pte |= HSW_PTE_UNCACHED;
69 pte |= GEN6_PTE_UNCACHED;
79 /* PPGTT support for Sandybdrige/Gen6 and later */
80 static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
85 gtt_pte_t scratch_pte;
86 unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
87 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
90 scratch_pte = pte_encode(ppgtt->dev, ppgtt->scratch_page_dma_addr,
94 last_pte = first_pte + num_entries;
95 if (last_pte > I915_PPGTT_PT_ENTRIES)
96 last_pte = I915_PPGTT_PT_ENTRIES;
98 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
100 for (i = first_pte; i < last_pte; i++)
101 pt_vaddr[i] = scratch_pte;
103 kunmap_atomic(pt_vaddr);
105 num_entries -= last_pte - first_pte;
111 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 struct i915_hw_ppgtt *ppgtt;
115 unsigned first_pd_entry_in_global_pt;
119 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
120 * entries. For aliasing ppgtt support we just steal them at the end for
122 first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
124 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
129 ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
130 ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
132 if (!ppgtt->pt_pages)
135 for (i = 0; i < ppgtt->num_pd_entries; i++) {
136 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
137 if (!ppgtt->pt_pages[i])
141 if (dev_priv->mm.gtt->needs_dmar) {
142 ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t)
143 *ppgtt->num_pd_entries,
145 if (!ppgtt->pt_dma_addr)
148 for (i = 0; i < ppgtt->num_pd_entries; i++) {
151 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i],
153 PCI_DMA_BIDIRECTIONAL);
155 if (pci_dma_mapping_error(dev->pdev,
161 ppgtt->pt_dma_addr[i] = pt_addr;
165 ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;
167 i915_ppgtt_clear_range(ppgtt, 0,
168 ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
170 ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t);
172 dev_priv->mm.aliasing_ppgtt = ppgtt;
177 if (ppgtt->pt_dma_addr) {
178 for (i--; i >= 0; i--)
179 pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
180 4096, PCI_DMA_BIDIRECTIONAL);
183 kfree(ppgtt->pt_dma_addr);
184 for (i = 0; i < ppgtt->num_pd_entries; i++) {
185 if (ppgtt->pt_pages[i])
186 __free_page(ppgtt->pt_pages[i]);
188 kfree(ppgtt->pt_pages);
195 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
204 if (ppgtt->pt_dma_addr) {
205 for (i = 0; i < ppgtt->num_pd_entries; i++)
206 pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
207 4096, PCI_DMA_BIDIRECTIONAL);
210 kfree(ppgtt->pt_dma_addr);
211 for (i = 0; i < ppgtt->num_pd_entries; i++)
212 __free_page(ppgtt->pt_pages[i]);
213 kfree(ppgtt->pt_pages);
217 static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt,
218 const struct sg_table *pages,
219 unsigned first_entry,
220 enum i915_cache_level cache_level)
223 unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
224 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
225 unsigned i, j, m, segment_len;
226 dma_addr_t page_addr;
227 struct scatterlist *sg;
229 /* init sg walking */
232 segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
235 while (i < pages->nents) {
236 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
238 for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
239 page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
240 pt_vaddr[j] = pte_encode(ppgtt->dev, page_addr,
243 /* grab the next page */
244 if (++m == segment_len) {
245 if (++i == pages->nents)
249 segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
254 kunmap_atomic(pt_vaddr);
261 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
262 struct drm_i915_gem_object *obj,
263 enum i915_cache_level cache_level)
265 i915_ppgtt_insert_sg_entries(ppgtt,
267 obj->gtt_space->start >> PAGE_SHIFT,
271 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
272 struct drm_i915_gem_object *obj)
274 i915_ppgtt_clear_range(ppgtt,
275 obj->gtt_space->start >> PAGE_SHIFT,
276 obj->base.size >> PAGE_SHIFT);
279 void i915_gem_init_ppgtt(struct drm_device *dev)
281 drm_i915_private_t *dev_priv = dev->dev_private;
283 struct intel_ring_buffer *ring;
284 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
285 gtt_pte_t __iomem *pd_addr;
289 if (!dev_priv->mm.aliasing_ppgtt)
293 pd_addr = (gtt_pte_t __iomem*)dev_priv->gtt.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t);
294 for (i = 0; i < ppgtt->num_pd_entries; i++) {
297 if (dev_priv->mm.gtt->needs_dmar)
298 pt_addr = ppgtt->pt_dma_addr[i];
300 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
302 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
303 pd_entry |= GEN6_PDE_VALID;
305 writel(pd_entry, pd_addr + i);
309 pd_offset = ppgtt->pd_offset;
310 pd_offset /= 64; /* in cachelines, */
313 if (INTEL_INFO(dev)->gen == 6) {
314 uint32_t ecochk, gab_ctl, ecobits;
316 ecobits = I915_READ(GAC_ECO_BITS);
317 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
319 gab_ctl = I915_READ(GAB_CTL);
320 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
322 ecochk = I915_READ(GAM_ECOCHK);
323 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
324 ECOCHK_PPGTT_CACHE64B);
325 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
326 } else if (INTEL_INFO(dev)->gen >= 7) {
327 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
328 /* GFX_MODE is per-ring on gen7+ */
331 for_each_ring(ring, dev_priv, i) {
332 if (INTEL_INFO(dev)->gen >= 7)
333 I915_WRITE(RING_MODE_GEN7(ring),
334 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
336 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
337 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
341 static bool do_idling(struct drm_i915_private *dev_priv)
343 bool ret = dev_priv->mm.interruptible;
345 if (unlikely(dev_priv->mm.gtt->do_idle_maps)) {
346 dev_priv->mm.interruptible = false;
347 if (i915_gpu_idle(dev_priv->dev)) {
348 DRM_ERROR("Couldn't idle GPU\n");
349 /* Wait a bit, in hopes it avoids the hang */
357 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
359 if (unlikely(dev_priv->mm.gtt->do_idle_maps))
360 dev_priv->mm.interruptible = interruptible;
364 static void i915_ggtt_clear_range(struct drm_device *dev,
365 unsigned first_entry,
366 unsigned num_entries)
368 struct drm_i915_private *dev_priv = dev->dev_private;
369 gtt_pte_t scratch_pte;
370 gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
371 const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;
374 if (INTEL_INFO(dev)->gen < 6) {
375 intel_gtt_clear_range(first_entry, num_entries);
379 if (WARN(num_entries > max_entries,
380 "First entry = %d; Num entries = %d (max=%d)\n",
381 first_entry, num_entries, max_entries))
382 num_entries = max_entries;
384 scratch_pte = pte_encode(dev, dev_priv->mm.gtt->scratch_page_dma, I915_CACHE_LLC);
385 for (i = 0; i < num_entries; i++)
386 iowrite32(scratch_pte, >t_base[i]);
390 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 struct drm_i915_gem_object *obj;
395 /* First fill our portion of the GTT with scratch pages */
396 i915_ggtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
397 dev_priv->gtt.total / PAGE_SIZE);
399 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
400 i915_gem_clflush_object(obj);
401 i915_gem_gtt_bind_object(obj, obj->cache_level);
404 i915_gem_chipset_flush(dev);
407 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
409 if (obj->has_dma_mapping)
412 if (!dma_map_sg(&obj->base.dev->pdev->dev,
413 obj->pages->sgl, obj->pages->nents,
414 PCI_DMA_BIDIRECTIONAL))
421 * Binds an object into the global gtt with the specified cache level. The object
422 * will be accessible to the GPU via commands whose operands reference offsets
423 * within the global GTT as well as accessible by the GPU through the GMADR
424 * mapped BAR (dev_priv->mm.gtt->gtt).
426 static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj,
427 enum i915_cache_level level)
429 struct drm_device *dev = obj->base.dev;
430 struct drm_i915_private *dev_priv = dev->dev_private;
431 struct sg_table *st = obj->pages;
432 struct scatterlist *sg = st->sgl;
433 const int first_entry = obj->gtt_space->start >> PAGE_SHIFT;
434 const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;
435 gtt_pte_t __iomem *gtt_entries =
436 (gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
438 unsigned int len, m = 0;
441 for_each_sg(st->sgl, sg, st->nents, unused) {
442 len = sg_dma_len(sg) >> PAGE_SHIFT;
443 for (m = 0; m < len; m++) {
444 addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
445 iowrite32(pte_encode(dev, addr, level), >t_entries[i]);
450 BUG_ON(i > max_entries);
451 BUG_ON(i != obj->base.size / PAGE_SIZE);
453 /* XXX: This serves as a posting read to make sure that the PTE has
454 * actually been updated. There is some concern that even though
455 * registers and PTEs are within the same BAR that they are potentially
456 * of NUMA access patterns. Therefore, even with the way we assume
457 * hardware should work, we must keep this posting read for paranoia.
460 WARN_ON(readl(>t_entries[i-1]) != pte_encode(dev, addr, level));
462 /* This next bit makes the above posting read even more important. We
463 * want to flush the TLBs only after we're certain all the PTE updates
466 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
467 POSTING_READ(GFX_FLSH_CNTL_GEN6);
470 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
471 enum i915_cache_level cache_level)
473 struct drm_device *dev = obj->base.dev;
474 if (INTEL_INFO(dev)->gen < 6) {
475 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
476 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
477 intel_gtt_insert_sg_entries(obj->pages,
478 obj->gtt_space->start >> PAGE_SHIFT,
481 gen6_ggtt_bind_object(obj, cache_level);
484 obj->has_global_gtt_mapping = 1;
487 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
489 i915_ggtt_clear_range(obj->base.dev,
490 obj->gtt_space->start >> PAGE_SHIFT,
491 obj->base.size >> PAGE_SHIFT);
493 obj->has_global_gtt_mapping = 0;
496 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
498 struct drm_device *dev = obj->base.dev;
499 struct drm_i915_private *dev_priv = dev->dev_private;
502 interruptible = do_idling(dev_priv);
504 if (!obj->has_dma_mapping)
505 dma_unmap_sg(&dev->pdev->dev,
506 obj->pages->sgl, obj->pages->nents,
507 PCI_DMA_BIDIRECTIONAL);
509 undo_idling(dev_priv, interruptible);
512 static void i915_gtt_color_adjust(struct drm_mm_node *node,
514 unsigned long *start,
517 if (node->color != color)
520 if (!list_empty(&node->node_list)) {
521 node = list_entry(node->node_list.next,
524 if (node->allocated && node->color != color)
529 void i915_gem_setup_global_gtt(struct drm_device *dev,
531 unsigned long mappable_end,
534 drm_i915_private_t *dev_priv = dev->dev_private;
535 struct drm_mm_node *entry;
536 struct drm_i915_gem_object *obj;
537 unsigned long hole_start, hole_end;
539 BUG_ON(mappable_end > end);
541 /* Subtract the guard page ... */
542 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
544 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
546 /* Mark any preallocated objects as occupied */
547 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
548 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
549 obj->gtt_offset, obj->base.size);
551 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
552 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
556 obj->has_global_gtt_mapping = 1;
559 dev_priv->gtt.start = start;
560 dev_priv->gtt.total = end - start;
562 /* Clear any non-preallocated blocks */
563 drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
564 hole_start, hole_end) {
565 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
566 hole_start, hole_end);
567 i915_ggtt_clear_range(dev,
568 hole_start / PAGE_SIZE,
569 (hole_end-hole_start) / PAGE_SIZE);
572 /* And finally clear the reserved guard page */
573 i915_ggtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
577 intel_enable_ppgtt(struct drm_device *dev)
579 if (i915_enable_ppgtt >= 0)
580 return i915_enable_ppgtt;
582 #ifdef CONFIG_INTEL_IOMMU
583 /* Disable ppgtt on SNB if VT-d is on. */
584 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
591 void i915_gem_init_global_gtt(struct drm_device *dev)
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 unsigned long gtt_size, mappable_size;
597 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
598 mappable_size = dev_priv->gtt.mappable_end;
600 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
601 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
602 * aperture accordingly when using aliasing ppgtt. */
603 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
605 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
607 ret = i915_gem_init_aliasing_ppgtt(dev);
609 mutex_unlock(&dev->struct_mutex);
613 /* Let GEM Manage all of the aperture.
615 * However, leave one page at the end still bound to the scratch
616 * page. There are a number of places where the hardware
617 * apparently prefetches past the end of the object, and we've
618 * seen multiple hangs with the GPU head pointer stuck in a
619 * batchbuffer bound at the last page of the aperture. One page
620 * should be enough to keep any prefetching inside of the
623 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
627 static int setup_scratch_page(struct drm_device *dev)
629 struct drm_i915_private *dev_priv = dev->dev_private;
633 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
637 set_pages_uc(page, 1);
639 #ifdef CONFIG_INTEL_IOMMU
640 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
641 PCI_DMA_BIDIRECTIONAL);
642 if (pci_dma_mapping_error(dev->pdev, dma_addr))
645 dma_addr = page_to_phys(page);
647 dev_priv->mm.gtt->scratch_page = page;
648 dev_priv->mm.gtt->scratch_page_dma = dma_addr;
653 static void teardown_scratch_page(struct drm_device *dev)
655 struct drm_i915_private *dev_priv = dev->dev_private;
656 set_pages_wb(dev_priv->mm.gtt->scratch_page, 1);
657 pci_unmap_page(dev->pdev, dev_priv->mm.gtt->scratch_page_dma,
658 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
659 put_page(dev_priv->mm.gtt->scratch_page);
660 __free_page(dev_priv->mm.gtt->scratch_page);
663 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
665 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
666 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
667 return snb_gmch_ctl << 20;
670 static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl)
672 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
673 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
674 return snb_gmch_ctl << 25; /* 32 MB units */
677 static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl)
679 static const int stolen_decoder[] = {
680 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
681 snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
682 snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
683 return stolen_decoder[snb_gmch_ctl] << 20;
686 int i915_gem_gtt_init(struct drm_device *dev)
688 struct drm_i915_private *dev_priv = dev->dev_private;
689 phys_addr_t gtt_bus_addr;
693 dev_priv->gtt.mappable_base = pci_resource_start(dev->pdev, 2);
694 dev_priv->gtt.mappable_end = pci_resource_len(dev->pdev, 2);
696 /* On modern platforms we need not worry ourself with the legacy
697 * hostbridge query stuff. Skip it entirely
699 if (INTEL_INFO(dev)->gen < 6) {
700 ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL);
702 DRM_ERROR("failed to set up gmch\n");
706 dev_priv->mm.gtt = intel_gtt_get();
707 if (!dev_priv->mm.gtt) {
708 DRM_ERROR("Failed to initialize GTT\n");
715 dev_priv->mm.gtt = kzalloc(sizeof(*dev_priv->mm.gtt), GFP_KERNEL);
716 if (!dev_priv->mm.gtt)
719 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
720 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
722 #ifdef CONFIG_INTEL_IOMMU
723 dev_priv->mm.gtt->needs_dmar = 1;
726 /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
727 gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20);
730 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
731 dev_priv->mm.gtt->gtt_total_entries =
732 gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t);
733 if (INTEL_INFO(dev)->gen < 7)
734 dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
736 dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl);
738 /* 64/512MB is the current min/max we actually know of, but this is just a
739 * coarse sanity check.
741 if ((dev_priv->gtt.mappable_end < (64<<20) ||
742 (dev_priv->gtt.mappable_end > (512<<20)))) {
743 DRM_ERROR("Unknown GMADR size (%lx)\n",
744 dev_priv->gtt.mappable_end);
749 ret = setup_scratch_page(dev);
751 DRM_ERROR("Scratch setup failed\n");
755 dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr,
756 dev_priv->mm.gtt->gtt_total_entries * sizeof(gtt_pte_t));
757 if (!dev_priv->gtt.gsm) {
758 DRM_ERROR("Failed to map the gtt page table\n");
759 teardown_scratch_page(dev);
764 /* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */
765 DRM_INFO("Memory usable by graphics device = %dM\n", dev_priv->mm.gtt->gtt_total_entries >> 8);
766 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", dev_priv->gtt.mappable_end >> 20);
767 DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv->mm.gtt->stolen_size >> 20);
772 kfree(dev_priv->mm.gtt);
773 if (INTEL_INFO(dev)->gen < 6)
778 void i915_gem_gtt_fini(struct drm_device *dev)
780 struct drm_i915_private *dev_priv = dev->dev_private;
781 iounmap(dev_priv->gtt.gsm);
782 teardown_scratch_page(dev);
783 if (INTEL_INFO(dev)->gen < 6)
785 kfree(dev_priv->mm.gtt);