2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
27 #include <linux/stop_machine.h>
29 #include <drm/i915_drm.h>
31 #include "i915_vgpu.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
35 #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM)
38 * DOC: Global GTT views
40 * Background and previous state
42 * Historically objects could exists (be bound) in global GTT space only as
43 * singular instances with a view representing all of the object's backing pages
44 * in a linear fashion. This view will be called a normal view.
46 * To support multiple views of the same object, where the number of mapped
47 * pages is not equal to the backing store, or where the layout of the pages
48 * is not linear, concept of a GGTT view was added.
50 * One example of an alternative view is a stereo display driven by a single
51 * image. In this case we would have a framebuffer looking like this
57 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
58 * rendering. In contrast, fed to the display engine would be an alternative
59 * view which could look something like this:
64 * In this example both the size and layout of pages in the alternative view is
65 * different from the normal view.
67 * Implementation and usage
69 * GGTT views are implemented using VMAs and are distinguished via enum
70 * i915_ggtt_view_type and struct i915_ggtt_view.
72 * A new flavour of core GEM functions which work with GGTT bound objects were
73 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
74 * renaming in large amounts of code. They take the struct i915_ggtt_view
75 * parameter encapsulating all metadata required to implement a view.
77 * As a helper for callers which are only interested in the normal view,
78 * globally const i915_ggtt_view_normal singleton instance exists. All old core
79 * GEM API functions, the ones not taking the view parameter, are operating on,
80 * or with the normal GGTT view.
82 * Code wanting to add or use a new GGTT view needs to:
84 * 1. Add a new enum with a suitable name.
85 * 2. Extend the metadata in the i915_ggtt_view structure if required.
86 * 3. Add support to i915_get_vma_pages().
88 * New views are required to build a scatter-gather table from within the
89 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
90 * exists for the lifetime of an VMA.
92 * Core API is designed to have copy semantics which means that passed in
93 * struct i915_ggtt_view does not need to be persistent (left around after
94 * calling the core API functions).
98 static inline struct i915_ggtt *
99 i915_vm_to_ggtt(struct i915_address_space *vm)
101 GEM_BUG_ON(!i915_is_ggtt(vm));
102 return container_of(vm, struct i915_ggtt, base);
106 i915_get_ggtt_vma_pages(struct i915_vma *vma);
108 const struct i915_ggtt_view i915_ggtt_view_normal = {
109 .type = I915_GGTT_VIEW_NORMAL,
111 const struct i915_ggtt_view i915_ggtt_view_rotated = {
112 .type = I915_GGTT_VIEW_ROTATED,
115 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
118 bool has_aliasing_ppgtt;
120 bool has_full_48bit_ppgtt;
122 has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6;
123 has_full_ppgtt = INTEL_GEN(dev_priv) >= 7;
124 has_full_48bit_ppgtt =
125 IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9;
127 if (intel_vgpu_active(dev_priv)) {
128 /* emulation is too hard */
129 has_full_ppgtt = false;
130 has_full_48bit_ppgtt = false;
133 if (!has_aliasing_ppgtt)
137 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
138 * execlists, the sole mechanism available to submit work.
140 if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
143 if (enable_ppgtt == 1)
146 if (enable_ppgtt == 2 && has_full_ppgtt)
149 if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
152 #ifdef CONFIG_INTEL_IOMMU
153 /* Disable ppgtt on SNB if VT-d is on. */
154 if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) {
155 DRM_INFO("Disabling PPGTT because VT-d is on\n");
160 /* Early VLV doesn't have this */
161 if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) {
162 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
166 if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt)
167 return has_full_48bit_ppgtt ? 3 : 2;
169 return has_aliasing_ppgtt ? 1 : 0;
172 static int ppgtt_bind_vma(struct i915_vma *vma,
173 enum i915_cache_level cache_level,
178 vma->pages = vma->obj->pages;
180 /* Currently applicable only to VLV */
182 pte_flags |= PTE_READ_ONLY;
184 vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start,
185 cache_level, pte_flags);
190 static void ppgtt_unbind_vma(struct i915_vma *vma)
192 vma->vm->clear_range(vma->vm,
198 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
199 enum i915_cache_level level,
202 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
206 case I915_CACHE_NONE:
207 pte |= PPAT_UNCACHED_INDEX;
210 pte |= PPAT_DISPLAY_ELLC_INDEX;
213 pte |= PPAT_CACHED_INDEX;
220 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
221 const enum i915_cache_level level)
223 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
225 if (level != I915_CACHE_NONE)
226 pde |= PPAT_CACHED_PDE_INDEX;
228 pde |= PPAT_UNCACHED_INDEX;
232 #define gen8_pdpe_encode gen8_pde_encode
233 #define gen8_pml4e_encode gen8_pde_encode
235 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
236 enum i915_cache_level level,
237 bool valid, u32 unused)
239 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
240 pte |= GEN6_PTE_ADDR_ENCODE(addr);
243 case I915_CACHE_L3_LLC:
245 pte |= GEN6_PTE_CACHE_LLC;
247 case I915_CACHE_NONE:
248 pte |= GEN6_PTE_UNCACHED;
257 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
258 enum i915_cache_level level,
259 bool valid, u32 unused)
261 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
262 pte |= GEN6_PTE_ADDR_ENCODE(addr);
265 case I915_CACHE_L3_LLC:
266 pte |= GEN7_PTE_CACHE_L3_LLC;
269 pte |= GEN6_PTE_CACHE_LLC;
271 case I915_CACHE_NONE:
272 pte |= GEN6_PTE_UNCACHED;
281 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
282 enum i915_cache_level level,
283 bool valid, u32 flags)
285 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
286 pte |= GEN6_PTE_ADDR_ENCODE(addr);
288 if (!(flags & PTE_READ_ONLY))
289 pte |= BYT_PTE_WRITEABLE;
291 if (level != I915_CACHE_NONE)
292 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
297 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
298 enum i915_cache_level level,
299 bool valid, u32 unused)
301 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
302 pte |= HSW_PTE_ADDR_ENCODE(addr);
304 if (level != I915_CACHE_NONE)
305 pte |= HSW_WB_LLC_AGE3;
310 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
311 enum i915_cache_level level,
312 bool valid, u32 unused)
314 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
315 pte |= HSW_PTE_ADDR_ENCODE(addr);
318 case I915_CACHE_NONE:
321 pte |= HSW_WT_ELLC_LLC_AGE3;
324 pte |= HSW_WB_ELLC_LLC_AGE3;
331 static int __setup_page_dma(struct drm_device *dev,
332 struct i915_page_dma *p, gfp_t flags)
334 struct device *kdev = &dev->pdev->dev;
336 p->page = alloc_page(flags);
340 p->daddr = dma_map_page(kdev,
341 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
343 if (dma_mapping_error(kdev, p->daddr)) {
344 __free_page(p->page);
351 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
353 return __setup_page_dma(dev, p, I915_GFP_DMA);
356 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
358 struct pci_dev *pdev = dev->pdev;
360 if (WARN_ON(!p->page))
363 dma_unmap_page(&pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
364 __free_page(p->page);
365 memset(p, 0, sizeof(*p));
368 static void *kmap_page_dma(struct i915_page_dma *p)
370 return kmap_atomic(p->page);
373 /* We use the flushing unmap only with ppgtt structures:
374 * page directories, page tables and scratch pages.
376 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
378 /* There are only few exceptions for gen >=6. chv and bxt.
379 * And we are not sure about the latter so play safe for now.
381 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
382 drm_clflush_virt_range(vaddr, PAGE_SIZE);
384 kunmap_atomic(vaddr);
387 #define kmap_px(px) kmap_page_dma(px_base(px))
388 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
390 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
391 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
392 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
393 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
395 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
399 uint64_t * const vaddr = kmap_page_dma(p);
401 for (i = 0; i < 512; i++)
404 kunmap_page_dma(dev, vaddr);
407 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
408 const uint32_t val32)
414 fill_page_dma(dev, p, v);
418 setup_scratch_page(struct drm_device *dev,
419 struct i915_page_dma *scratch,
422 return __setup_page_dma(dev, scratch, gfp | __GFP_ZERO);
425 static void cleanup_scratch_page(struct drm_device *dev,
426 struct i915_page_dma *scratch)
428 cleanup_page_dma(dev, scratch);
431 static struct i915_page_table *alloc_pt(struct drm_device *dev)
433 struct i915_page_table *pt;
434 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
435 GEN8_PTES : GEN6_PTES;
438 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
440 return ERR_PTR(-ENOMEM);
442 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
448 ret = setup_px(dev, pt);
455 kfree(pt->used_ptes);
462 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
465 kfree(pt->used_ptes);
469 static void gen8_initialize_pt(struct i915_address_space *vm,
470 struct i915_page_table *pt)
472 gen8_pte_t scratch_pte;
474 scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
475 I915_CACHE_LLC, true);
477 fill_px(vm->dev, pt, scratch_pte);
480 static void gen6_initialize_pt(struct i915_address_space *vm,
481 struct i915_page_table *pt)
483 gen6_pte_t scratch_pte;
485 WARN_ON(vm->scratch_page.daddr == 0);
487 scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
488 I915_CACHE_LLC, true, 0);
490 fill32_px(vm->dev, pt, scratch_pte);
493 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
495 struct i915_page_directory *pd;
498 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
500 return ERR_PTR(-ENOMEM);
502 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
503 sizeof(*pd->used_pdes), GFP_KERNEL);
507 ret = setup_px(dev, pd);
514 kfree(pd->used_pdes);
521 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
525 kfree(pd->used_pdes);
530 static void gen8_initialize_pd(struct i915_address_space *vm,
531 struct i915_page_directory *pd)
533 gen8_pde_t scratch_pde;
535 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
537 fill_px(vm->dev, pd, scratch_pde);
540 static int __pdp_init(struct drm_device *dev,
541 struct i915_page_directory_pointer *pdp)
543 size_t pdpes = I915_PDPES_PER_PDP(dev);
545 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
546 sizeof(unsigned long),
548 if (!pdp->used_pdpes)
551 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
553 if (!pdp->page_directory) {
554 kfree(pdp->used_pdpes);
555 /* the PDP might be the statically allocated top level. Keep it
556 * as clean as possible */
557 pdp->used_pdpes = NULL;
564 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
566 kfree(pdp->used_pdpes);
567 kfree(pdp->page_directory);
568 pdp->page_directory = NULL;
572 i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
574 struct i915_page_directory_pointer *pdp;
577 WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
579 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
581 return ERR_PTR(-ENOMEM);
583 ret = __pdp_init(dev, pdp);
587 ret = setup_px(dev, pdp);
601 static void free_pdp(struct drm_device *dev,
602 struct i915_page_directory_pointer *pdp)
605 if (USES_FULL_48BIT_PPGTT(dev)) {
606 cleanup_px(dev, pdp);
611 static void gen8_initialize_pdp(struct i915_address_space *vm,
612 struct i915_page_directory_pointer *pdp)
614 gen8_ppgtt_pdpe_t scratch_pdpe;
616 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
618 fill_px(vm->dev, pdp, scratch_pdpe);
621 static void gen8_initialize_pml4(struct i915_address_space *vm,
622 struct i915_pml4 *pml4)
624 gen8_ppgtt_pml4e_t scratch_pml4e;
626 scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
629 fill_px(vm->dev, pml4, scratch_pml4e);
633 gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
634 struct i915_page_directory_pointer *pdp,
635 struct i915_page_directory *pd,
638 gen8_ppgtt_pdpe_t *page_directorypo;
640 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
643 page_directorypo = kmap_px(pdp);
644 page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
645 kunmap_px(ppgtt, page_directorypo);
649 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
650 struct i915_pml4 *pml4,
651 struct i915_page_directory_pointer *pdp,
654 gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
656 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
657 pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
658 kunmap_px(ppgtt, pagemap);
661 /* Broadwell Page Directory Pointer Descriptors */
662 static int gen8_write_pdp(struct drm_i915_gem_request *req,
666 struct intel_ring *ring = req->ring;
667 struct intel_engine_cs *engine = req->engine;
672 ret = intel_ring_begin(req, 6);
676 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
677 intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry));
678 intel_ring_emit(ring, upper_32_bits(addr));
679 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
680 intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry));
681 intel_ring_emit(ring, lower_32_bits(addr));
682 intel_ring_advance(ring);
687 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
688 struct drm_i915_gem_request *req)
692 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
693 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
695 ret = gen8_write_pdp(req, i, pd_daddr);
703 static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
704 struct drm_i915_gem_request *req)
706 return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
709 static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
710 struct i915_page_directory_pointer *pdp,
713 gen8_pte_t scratch_pte)
715 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
716 gen8_pte_t *pt_vaddr;
717 unsigned pdpe = gen8_pdpe_index(start);
718 unsigned pde = gen8_pde_index(start);
719 unsigned pte = gen8_pte_index(start);
720 unsigned num_entries = length >> PAGE_SHIFT;
721 unsigned last_pte, i;
726 while (num_entries) {
727 struct i915_page_directory *pd;
728 struct i915_page_table *pt;
730 if (WARN_ON(!pdp->page_directory[pdpe]))
733 pd = pdp->page_directory[pdpe];
735 if (WARN_ON(!pd->page_table[pde]))
738 pt = pd->page_table[pde];
740 if (WARN_ON(!px_page(pt)))
743 last_pte = pte + num_entries;
744 if (last_pte > GEN8_PTES)
745 last_pte = GEN8_PTES;
747 pt_vaddr = kmap_px(pt);
749 for (i = pte; i < last_pte; i++) {
750 pt_vaddr[i] = scratch_pte;
754 kunmap_px(ppgtt, pt_vaddr);
757 if (++pde == I915_PDES) {
758 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
765 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
770 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
771 gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
772 I915_CACHE_LLC, use_scratch);
774 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
775 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
779 struct i915_page_directory_pointer *pdp;
781 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
782 gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
789 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
790 struct i915_page_directory_pointer *pdp,
791 struct sg_page_iter *sg_iter,
793 enum i915_cache_level cache_level)
795 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
796 gen8_pte_t *pt_vaddr;
797 unsigned pdpe = gen8_pdpe_index(start);
798 unsigned pde = gen8_pde_index(start);
799 unsigned pte = gen8_pte_index(start);
803 while (__sg_page_iter_next(sg_iter)) {
804 if (pt_vaddr == NULL) {
805 struct i915_page_directory *pd = pdp->page_directory[pdpe];
806 struct i915_page_table *pt = pd->page_table[pde];
807 pt_vaddr = kmap_px(pt);
811 gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
813 if (++pte == GEN8_PTES) {
814 kunmap_px(ppgtt, pt_vaddr);
816 if (++pde == I915_PDES) {
817 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
826 kunmap_px(ppgtt, pt_vaddr);
829 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
830 struct sg_table *pages,
832 enum i915_cache_level cache_level,
835 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
836 struct sg_page_iter sg_iter;
838 __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
840 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
841 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
844 struct i915_page_directory_pointer *pdp;
846 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
848 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
849 gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
855 static void gen8_free_page_tables(struct drm_device *dev,
856 struct i915_page_directory *pd)
863 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
864 if (WARN_ON(!pd->page_table[i]))
867 free_pt(dev, pd->page_table[i]);
868 pd->page_table[i] = NULL;
872 static int gen8_init_scratch(struct i915_address_space *vm)
874 struct drm_device *dev = vm->dev;
877 ret = setup_scratch_page(dev, &vm->scratch_page, I915_GFP_DMA);
881 vm->scratch_pt = alloc_pt(dev);
882 if (IS_ERR(vm->scratch_pt)) {
883 ret = PTR_ERR(vm->scratch_pt);
884 goto free_scratch_page;
887 vm->scratch_pd = alloc_pd(dev);
888 if (IS_ERR(vm->scratch_pd)) {
889 ret = PTR_ERR(vm->scratch_pd);
893 if (USES_FULL_48BIT_PPGTT(dev)) {
894 vm->scratch_pdp = alloc_pdp(dev);
895 if (IS_ERR(vm->scratch_pdp)) {
896 ret = PTR_ERR(vm->scratch_pdp);
901 gen8_initialize_pt(vm, vm->scratch_pt);
902 gen8_initialize_pd(vm, vm->scratch_pd);
903 if (USES_FULL_48BIT_PPGTT(dev))
904 gen8_initialize_pdp(vm, vm->scratch_pdp);
909 free_pd(dev, vm->scratch_pd);
911 free_pt(dev, vm->scratch_pt);
913 cleanup_scratch_page(dev, &vm->scratch_page);
918 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
920 enum vgt_g2v_type msg;
921 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
924 if (USES_FULL_48BIT_PPGTT(dev_priv)) {
925 u64 daddr = px_dma(&ppgtt->pml4);
927 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
928 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
930 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
931 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
933 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
934 u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
936 I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
937 I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
940 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
941 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
944 I915_WRITE(vgtif_reg(g2v_notify), msg);
949 static void gen8_free_scratch(struct i915_address_space *vm)
951 struct drm_device *dev = vm->dev;
953 if (USES_FULL_48BIT_PPGTT(dev))
954 free_pdp(dev, vm->scratch_pdp);
955 free_pd(dev, vm->scratch_pd);
956 free_pt(dev, vm->scratch_pt);
957 cleanup_scratch_page(dev, &vm->scratch_page);
960 static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
961 struct i915_page_directory_pointer *pdp)
965 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
966 if (WARN_ON(!pdp->page_directory[i]))
969 gen8_free_page_tables(dev, pdp->page_directory[i]);
970 free_pd(dev, pdp->page_directory[i]);
976 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
980 for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
981 if (WARN_ON(!ppgtt->pml4.pdps[i]))
984 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
987 cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
990 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
992 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
994 if (intel_vgpu_active(to_i915(vm->dev)))
995 gen8_ppgtt_notify_vgt(ppgtt, false);
997 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
998 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
1000 gen8_ppgtt_cleanup_4lvl(ppgtt);
1002 gen8_free_scratch(vm);
1006 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
1007 * @vm: Master vm structure.
1008 * @pd: Page directory for this address range.
1009 * @start: Starting virtual address to begin allocations.
1010 * @length: Size of the allocations.
1011 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1012 * caller to free on error.
1014 * Allocate the required number of page tables. Extremely similar to
1015 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1016 * the page directory boundary (instead of the page directory pointer). That
1017 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1018 * possible, and likely that the caller will need to use multiple calls of this
1019 * function to achieve the appropriate allocation.
1021 * Return: 0 if success; negative error code otherwise.
1023 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
1024 struct i915_page_directory *pd,
1027 unsigned long *new_pts)
1029 struct drm_device *dev = vm->dev;
1030 struct i915_page_table *pt;
1033 gen8_for_each_pde(pt, pd, start, length, pde) {
1034 /* Don't reallocate page tables */
1035 if (test_bit(pde, pd->used_pdes)) {
1036 /* Scratch is never allocated this way */
1037 WARN_ON(pt == vm->scratch_pt);
1045 gen8_initialize_pt(vm, pt);
1046 pd->page_table[pde] = pt;
1047 __set_bit(pde, new_pts);
1048 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
1054 for_each_set_bit(pde, new_pts, I915_PDES)
1055 free_pt(dev, pd->page_table[pde]);
1061 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1062 * @vm: Master vm structure.
1063 * @pdp: Page directory pointer for this address range.
1064 * @start: Starting virtual address to begin allocations.
1065 * @length: Size of the allocations.
1066 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1067 * caller to free on error.
1069 * Allocate the required number of page directories starting at the pde index of
1070 * @start, and ending at the pde index @start + @length. This function will skip
1071 * over already allocated page directories within the range, and only allocate
1072 * new ones, setting the appropriate pointer within the pdp as well as the
1073 * correct position in the bitmap @new_pds.
1075 * The function will only allocate the pages within the range for a give page
1076 * directory pointer. In other words, if @start + @length straddles a virtually
1077 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1078 * required by the caller, This is not currently possible, and the BUG in the
1079 * code will prevent it.
1081 * Return: 0 if success; negative error code otherwise.
1084 gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1085 struct i915_page_directory_pointer *pdp,
1088 unsigned long *new_pds)
1090 struct drm_device *dev = vm->dev;
1091 struct i915_page_directory *pd;
1093 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1095 WARN_ON(!bitmap_empty(new_pds, pdpes));
1097 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1098 if (test_bit(pdpe, pdp->used_pdpes))
1105 gen8_initialize_pd(vm, pd);
1106 pdp->page_directory[pdpe] = pd;
1107 __set_bit(pdpe, new_pds);
1108 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
1114 for_each_set_bit(pdpe, new_pds, pdpes)
1115 free_pd(dev, pdp->page_directory[pdpe]);
1121 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1122 * @vm: Master vm structure.
1123 * @pml4: Page map level 4 for this address range.
1124 * @start: Starting virtual address to begin allocations.
1125 * @length: Size of the allocations.
1126 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1127 * caller to free on error.
1129 * Allocate the required number of page directory pointers. Extremely similar to
1130 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1131 * The main difference is here we are limited by the pml4 boundary (instead of
1132 * the page directory pointer).
1134 * Return: 0 if success; negative error code otherwise.
1137 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1138 struct i915_pml4 *pml4,
1141 unsigned long *new_pdps)
1143 struct drm_device *dev = vm->dev;
1144 struct i915_page_directory_pointer *pdp;
1147 WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1149 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1150 if (!test_bit(pml4e, pml4->used_pml4es)) {
1151 pdp = alloc_pdp(dev);
1155 gen8_initialize_pdp(vm, pdp);
1156 pml4->pdps[pml4e] = pdp;
1157 __set_bit(pml4e, new_pdps);
1158 trace_i915_page_directory_pointer_entry_alloc(vm,
1168 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1169 free_pdp(dev, pml4->pdps[pml4e]);
1175 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
1181 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1182 * of these are based on the number of PDPEs in the system.
1185 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
1186 unsigned long **new_pts,
1192 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
1196 pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1207 free_gen8_temp_bitmaps(pds, pts);
1211 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1212 * the page table structures, we mark them dirty so that
1213 * context switching/execlist queuing code takes extra steps
1214 * to ensure that tlbs are flushed.
1216 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1218 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1221 static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1222 struct i915_page_directory_pointer *pdp,
1226 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1227 unsigned long *new_page_dirs, *new_page_tables;
1228 struct drm_device *dev = vm->dev;
1229 struct i915_page_directory *pd;
1230 const uint64_t orig_start = start;
1231 const uint64_t orig_length = length;
1233 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1236 /* Wrap is never okay since we can only represent 48b, and we don't
1237 * actually use the other side of the canonical address space.
1239 if (WARN_ON(start + length < start))
1242 if (WARN_ON(start + length > vm->total))
1245 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1249 /* Do the allocations first so we can easily bail out */
1250 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1253 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1257 /* For every page directory referenced, allocate page tables */
1258 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1259 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
1260 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
1266 length = orig_length;
1268 /* Allocations have completed successfully, so set the bitmaps, and do
1270 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1271 gen8_pde_t *const page_directory = kmap_px(pd);
1272 struct i915_page_table *pt;
1273 uint64_t pd_len = length;
1274 uint64_t pd_start = start;
1277 /* Every pd should be allocated, we just did that above. */
1280 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
1281 /* Same reasoning as pd */
1284 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1286 /* Set our used ptes within the page table */
1287 bitmap_set(pt->used_ptes,
1288 gen8_pte_index(pd_start),
1289 gen8_pte_count(pd_start, pd_len));
1291 /* Our pde is now pointing to the pagetable, pt */
1292 __set_bit(pde, pd->used_pdes);
1294 /* Map the PDE to the page table */
1295 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1297 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1298 gen8_pte_index(start),
1299 gen8_pte_count(start, length),
1302 /* NB: We haven't yet mapped ptes to pages. At this
1303 * point we're still relying on insert_entries() */
1306 kunmap_px(ppgtt, page_directory);
1307 __set_bit(pdpe, pdp->used_pdpes);
1308 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
1311 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1312 mark_tlbs_dirty(ppgtt);
1319 for_each_set_bit(temp, new_page_tables + pdpe *
1320 BITS_TO_LONGS(I915_PDES), I915_PDES)
1321 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
1324 for_each_set_bit(pdpe, new_page_dirs, pdpes)
1325 free_pd(dev, pdp->page_directory[pdpe]);
1327 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1328 mark_tlbs_dirty(ppgtt);
1332 static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1333 struct i915_pml4 *pml4,
1337 DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
1338 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1339 struct i915_page_directory_pointer *pdp;
1343 /* Do the pml4 allocations first, so we don't need to track the newly
1344 * allocated tables below the pdp */
1345 bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1347 /* The pagedirectory and pagetable allocations are done in the shared 3
1348 * and 4 level code. Just allocate the pdps.
1350 ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1355 WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1356 "The allocation has spanned more than 512GB. "
1357 "It is highly likely this is incorrect.");
1359 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1362 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1366 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1369 bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1370 GEN8_PML4ES_PER_PML4);
1375 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1376 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1381 static int gen8_alloc_va_range(struct i915_address_space *vm,
1382 uint64_t start, uint64_t length)
1384 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1386 if (USES_FULL_48BIT_PPGTT(vm->dev))
1387 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1389 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1392 static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1393 uint64_t start, uint64_t length,
1394 gen8_pte_t scratch_pte,
1397 struct i915_page_directory *pd;
1400 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1401 struct i915_page_table *pt;
1402 uint64_t pd_len = length;
1403 uint64_t pd_start = start;
1406 if (!test_bit(pdpe, pdp->used_pdpes))
1409 seq_printf(m, "\tPDPE #%d\n", pdpe);
1410 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
1412 gen8_pte_t *pt_vaddr;
1414 if (!test_bit(pde, pd->used_pdes))
1417 pt_vaddr = kmap_px(pt);
1418 for (pte = 0; pte < GEN8_PTES; pte += 4) {
1420 (pdpe << GEN8_PDPE_SHIFT) |
1421 (pde << GEN8_PDE_SHIFT) |
1422 (pte << GEN8_PTE_SHIFT);
1426 for (i = 0; i < 4; i++)
1427 if (pt_vaddr[pte + i] != scratch_pte)
1432 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1433 for (i = 0; i < 4; i++) {
1434 if (pt_vaddr[pte + i] != scratch_pte)
1435 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1437 seq_puts(m, " SCRATCH ");
1441 /* don't use kunmap_px, it could trigger
1442 * an unnecessary flush.
1444 kunmap_atomic(pt_vaddr);
1449 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1451 struct i915_address_space *vm = &ppgtt->base;
1452 uint64_t start = ppgtt->base.start;
1453 uint64_t length = ppgtt->base.total;
1454 gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
1455 I915_CACHE_LLC, true);
1457 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1458 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1461 struct i915_pml4 *pml4 = &ppgtt->pml4;
1462 struct i915_page_directory_pointer *pdp;
1464 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1465 if (!test_bit(pml4e, pml4->used_pml4es))
1468 seq_printf(m, " PML4E #%llu\n", pml4e);
1469 gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1474 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1476 unsigned long *new_page_dirs, *new_page_tables;
1477 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1480 /* We allocate temp bitmap for page tables for no gain
1481 * but as this is for init only, lets keep the things simple
1483 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1487 /* Allocate for all pdps regardless of how the ppgtt
1490 ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1494 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1496 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1502 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1503 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1504 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1508 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1512 ret = gen8_init_scratch(&ppgtt->base);
1516 ppgtt->base.start = 0;
1517 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1518 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1519 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1520 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1521 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1522 ppgtt->base.bind_vma = ppgtt_bind_vma;
1523 ppgtt->debug_dump = gen8_dump_ppgtt;
1525 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1526 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1530 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1532 ppgtt->base.total = 1ULL << 48;
1533 ppgtt->switch_mm = gen8_48b_mm_switch;
1535 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
1539 ppgtt->base.total = 1ULL << 32;
1540 ppgtt->switch_mm = gen8_legacy_mm_switch;
1541 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1545 if (intel_vgpu_active(to_i915(ppgtt->base.dev))) {
1546 ret = gen8_preallocate_top_level_pdps(ppgtt);
1552 if (intel_vgpu_active(to_i915(ppgtt->base.dev)))
1553 gen8_ppgtt_notify_vgt(ppgtt, true);
1558 gen8_free_scratch(&ppgtt->base);
1562 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1564 struct i915_address_space *vm = &ppgtt->base;
1565 struct i915_page_table *unused;
1566 gen6_pte_t scratch_pte;
1569 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1571 scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
1572 I915_CACHE_LLC, true, 0);
1574 gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) {
1576 gen6_pte_t *pt_vaddr;
1577 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1578 pd_entry = readl(ppgtt->pd_addr + pde);
1579 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1581 if (pd_entry != expected)
1582 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1586 seq_printf(m, "\tPDE: %x\n", pd_entry);
1588 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1590 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1592 (pde * PAGE_SIZE * GEN6_PTES) +
1596 for (i = 0; i < 4; i++)
1597 if (pt_vaddr[pte + i] != scratch_pte)
1602 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1603 for (i = 0; i < 4; i++) {
1604 if (pt_vaddr[pte + i] != scratch_pte)
1605 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1607 seq_puts(m, " SCRATCH ");
1611 kunmap_px(ppgtt, pt_vaddr);
1615 /* Write pde (index) from the page directory @pd to the page table @pt */
1616 static void gen6_write_pde(struct i915_page_directory *pd,
1617 const int pde, struct i915_page_table *pt)
1619 /* Caller needs to make sure the write completes if necessary */
1620 struct i915_hw_ppgtt *ppgtt =
1621 container_of(pd, struct i915_hw_ppgtt, pd);
1624 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1625 pd_entry |= GEN6_PDE_VALID;
1627 writel(pd_entry, ppgtt->pd_addr + pde);
1630 /* Write all the page tables found in the ppgtt structure to incrementing page
1632 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1633 struct i915_page_directory *pd,
1634 uint32_t start, uint32_t length)
1636 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1637 struct i915_page_table *pt;
1640 gen6_for_each_pde(pt, pd, start, length, pde)
1641 gen6_write_pde(pd, pde, pt);
1643 /* Make sure write is complete before other code can use this page
1644 * table. Also require for WC mapped PTEs */
1648 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1650 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1652 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1655 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1656 struct drm_i915_gem_request *req)
1658 struct intel_ring *ring = req->ring;
1659 struct intel_engine_cs *engine = req->engine;
1662 /* NB: TLBs must be flushed and invalidated before a switch */
1663 ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);
1667 ret = intel_ring_begin(req, 6);
1671 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1672 intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine));
1673 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1674 intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine));
1675 intel_ring_emit(ring, get_pd_offset(ppgtt));
1676 intel_ring_emit(ring, MI_NOOP);
1677 intel_ring_advance(ring);
1682 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1683 struct drm_i915_gem_request *req)
1685 struct intel_ring *ring = req->ring;
1686 struct intel_engine_cs *engine = req->engine;
1689 /* NB: TLBs must be flushed and invalidated before a switch */
1690 ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);
1694 ret = intel_ring_begin(req, 6);
1698 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1699 intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine));
1700 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1701 intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine));
1702 intel_ring_emit(ring, get_pd_offset(ppgtt));
1703 intel_ring_emit(ring, MI_NOOP);
1704 intel_ring_advance(ring);
1706 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1707 if (engine->id != RCS) {
1708 ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);
1716 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1717 struct drm_i915_gem_request *req)
1719 struct intel_engine_cs *engine = req->engine;
1720 struct drm_i915_private *dev_priv = req->i915;
1722 I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1723 I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
1727 static void gen8_ppgtt_enable(struct drm_device *dev)
1729 struct drm_i915_private *dev_priv = to_i915(dev);
1730 struct intel_engine_cs *engine;
1732 for_each_engine(engine, dev_priv) {
1733 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
1734 I915_WRITE(RING_MODE_GEN7(engine),
1735 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
1739 static void gen7_ppgtt_enable(struct drm_device *dev)
1741 struct drm_i915_private *dev_priv = to_i915(dev);
1742 struct intel_engine_cs *engine;
1743 uint32_t ecochk, ecobits;
1745 ecobits = I915_READ(GAC_ECO_BITS);
1746 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1748 ecochk = I915_READ(GAM_ECOCHK);
1749 if (IS_HASWELL(dev)) {
1750 ecochk |= ECOCHK_PPGTT_WB_HSW;
1752 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1753 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1755 I915_WRITE(GAM_ECOCHK, ecochk);
1757 for_each_engine(engine, dev_priv) {
1758 /* GFX_MODE is per-ring on gen7+ */
1759 I915_WRITE(RING_MODE_GEN7(engine),
1760 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1764 static void gen6_ppgtt_enable(struct drm_device *dev)
1766 struct drm_i915_private *dev_priv = to_i915(dev);
1767 uint32_t ecochk, gab_ctl, ecobits;
1769 ecobits = I915_READ(GAC_ECO_BITS);
1770 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1771 ECOBITS_PPGTT_CACHE64B);
1773 gab_ctl = I915_READ(GAB_CTL);
1774 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1776 ecochk = I915_READ(GAM_ECOCHK);
1777 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1779 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1782 /* PPGTT support for Sandybdrige/Gen6 and later */
1783 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1788 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1789 gen6_pte_t *pt_vaddr, scratch_pte;
1790 unsigned first_entry = start >> PAGE_SHIFT;
1791 unsigned num_entries = length >> PAGE_SHIFT;
1792 unsigned act_pt = first_entry / GEN6_PTES;
1793 unsigned first_pte = first_entry % GEN6_PTES;
1794 unsigned last_pte, i;
1796 scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
1797 I915_CACHE_LLC, true, 0);
1799 while (num_entries) {
1800 last_pte = first_pte + num_entries;
1801 if (last_pte > GEN6_PTES)
1802 last_pte = GEN6_PTES;
1804 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1806 for (i = first_pte; i < last_pte; i++)
1807 pt_vaddr[i] = scratch_pte;
1809 kunmap_px(ppgtt, pt_vaddr);
1811 num_entries -= last_pte - first_pte;
1817 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1818 struct sg_table *pages,
1820 enum i915_cache_level cache_level, u32 flags)
1822 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1823 unsigned first_entry = start >> PAGE_SHIFT;
1824 unsigned act_pt = first_entry / GEN6_PTES;
1825 unsigned act_pte = first_entry % GEN6_PTES;
1826 gen6_pte_t *pt_vaddr = NULL;
1827 struct sgt_iter sgt_iter;
1830 for_each_sgt_dma(addr, sgt_iter, pages) {
1831 if (pt_vaddr == NULL)
1832 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1835 vm->pte_encode(addr, cache_level, true, flags);
1837 if (++act_pte == GEN6_PTES) {
1838 kunmap_px(ppgtt, pt_vaddr);
1846 kunmap_px(ppgtt, pt_vaddr);
1849 static int gen6_alloc_va_range(struct i915_address_space *vm,
1850 uint64_t start_in, uint64_t length_in)
1852 DECLARE_BITMAP(new_page_tables, I915_PDES);
1853 struct drm_device *dev = vm->dev;
1854 struct drm_i915_private *dev_priv = to_i915(dev);
1855 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1856 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1857 struct i915_page_table *pt;
1858 uint32_t start, length, start_save, length_save;
1862 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1865 start = start_save = start_in;
1866 length = length_save = length_in;
1868 bitmap_zero(new_page_tables, I915_PDES);
1870 /* The allocation is done in two stages so that we can bail out with
1871 * minimal amount of pain. The first stage finds new page tables that
1872 * need allocation. The second stage marks use ptes within the page
1875 gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) {
1876 if (pt != vm->scratch_pt) {
1877 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1881 /* We've already allocated a page table */
1882 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1890 gen6_initialize_pt(vm, pt);
1892 ppgtt->pd.page_table[pde] = pt;
1893 __set_bit(pde, new_page_tables);
1894 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1898 length = length_save;
1900 gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) {
1901 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1903 bitmap_zero(tmp_bitmap, GEN6_PTES);
1904 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1905 gen6_pte_count(start, length));
1907 if (__test_and_clear_bit(pde, new_page_tables))
1908 gen6_write_pde(&ppgtt->pd, pde, pt);
1910 trace_i915_page_table_entry_map(vm, pde, pt,
1911 gen6_pte_index(start),
1912 gen6_pte_count(start, length),
1914 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1918 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1920 /* Make sure write is complete before other code can use this page
1921 * table. Also require for WC mapped PTEs */
1924 mark_tlbs_dirty(ppgtt);
1928 for_each_set_bit(pde, new_page_tables, I915_PDES) {
1929 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1931 ppgtt->pd.page_table[pde] = vm->scratch_pt;
1932 free_pt(vm->dev, pt);
1935 mark_tlbs_dirty(ppgtt);
1939 static int gen6_init_scratch(struct i915_address_space *vm)
1941 struct drm_device *dev = vm->dev;
1944 ret = setup_scratch_page(dev, &vm->scratch_page, I915_GFP_DMA);
1948 vm->scratch_pt = alloc_pt(dev);
1949 if (IS_ERR(vm->scratch_pt)) {
1950 cleanup_scratch_page(dev, &vm->scratch_page);
1951 return PTR_ERR(vm->scratch_pt);
1954 gen6_initialize_pt(vm, vm->scratch_pt);
1959 static void gen6_free_scratch(struct i915_address_space *vm)
1961 struct drm_device *dev = vm->dev;
1963 free_pt(dev, vm->scratch_pt);
1964 cleanup_scratch_page(dev, &vm->scratch_page);
1967 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1969 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1970 struct i915_page_directory *pd = &ppgtt->pd;
1971 struct drm_device *dev = vm->dev;
1972 struct i915_page_table *pt;
1975 drm_mm_remove_node(&ppgtt->node);
1977 gen6_for_all_pdes(pt, pd, pde)
1978 if (pt != vm->scratch_pt)
1981 gen6_free_scratch(vm);
1984 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1986 struct i915_address_space *vm = &ppgtt->base;
1987 struct drm_device *dev = ppgtt->base.dev;
1988 struct drm_i915_private *dev_priv = to_i915(dev);
1989 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1990 bool retried = false;
1993 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1994 * allocator works in address space sizes, so it's multiplied by page
1995 * size. We allocate at the top of the GTT to avoid fragmentation.
1997 BUG_ON(!drm_mm_initialized(&ggtt->base.mm));
1999 ret = gen6_init_scratch(vm);
2004 ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm,
2005 &ppgtt->node, GEN6_PD_SIZE,
2007 0, ggtt->base.total,
2009 if (ret == -ENOSPC && !retried) {
2010 ret = i915_gem_evict_something(&ggtt->base,
2011 GEN6_PD_SIZE, GEN6_PD_ALIGN,
2013 0, ggtt->base.total,
2026 if (ppgtt->node.start < ggtt->mappable_end)
2027 DRM_DEBUG("Forced to use aperture for PDEs\n");
2032 gen6_free_scratch(vm);
2036 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2038 return gen6_ppgtt_allocate_page_directories(ppgtt);
2041 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2042 uint64_t start, uint64_t length)
2044 struct i915_page_table *unused;
2047 gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde)
2048 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
2051 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
2053 struct drm_device *dev = ppgtt->base.dev;
2054 struct drm_i915_private *dev_priv = to_i915(dev);
2055 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2058 ppgtt->base.pte_encode = ggtt->base.pte_encode;
2059 if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
2060 ppgtt->switch_mm = gen6_mm_switch;
2061 else if (IS_HASWELL(dev))
2062 ppgtt->switch_mm = hsw_mm_switch;
2063 else if (IS_GEN7(dev))
2064 ppgtt->switch_mm = gen7_mm_switch;
2068 ret = gen6_ppgtt_alloc(ppgtt);
2072 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
2073 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2074 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
2075 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2076 ppgtt->base.bind_vma = ppgtt_bind_vma;
2077 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
2078 ppgtt->base.start = 0;
2079 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
2080 ppgtt->debug_dump = gen6_dump_ppgtt;
2082 ppgtt->pd.base.ggtt_offset =
2083 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
2085 ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm +
2086 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
2088 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
2090 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2092 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2093 ppgtt->node.size >> 20,
2094 ppgtt->node.start / PAGE_SIZE);
2096 DRM_DEBUG("Adding PPGTT at offset %x\n",
2097 ppgtt->pd.base.ggtt_offset << 10);
2102 static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
2103 struct drm_i915_private *dev_priv)
2105 ppgtt->base.dev = &dev_priv->drm;
2107 if (INTEL_INFO(dev_priv)->gen < 8)
2108 return gen6_ppgtt_init(ppgtt);
2110 return gen8_ppgtt_init(ppgtt);
2113 static void i915_address_space_init(struct i915_address_space *vm,
2114 struct drm_i915_private *dev_priv)
2116 drm_mm_init(&vm->mm, vm->start, vm->total);
2117 INIT_LIST_HEAD(&vm->active_list);
2118 INIT_LIST_HEAD(&vm->inactive_list);
2119 INIT_LIST_HEAD(&vm->unbound_list);
2120 list_add_tail(&vm->global_link, &dev_priv->vm_list);
2123 static void gtt_write_workarounds(struct drm_device *dev)
2125 struct drm_i915_private *dev_priv = to_i915(dev);
2127 /* This function is for gtt related workarounds. This function is
2128 * called on driver load and after a GPU reset, so you can place
2129 * workarounds here even if they get overwritten by GPU reset.
2131 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2132 if (IS_BROADWELL(dev))
2133 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
2134 else if (IS_CHERRYVIEW(dev))
2135 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
2136 else if (IS_SKYLAKE(dev))
2137 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
2138 else if (IS_BROXTON(dev))
2139 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
2142 static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
2143 struct drm_i915_private *dev_priv,
2144 struct drm_i915_file_private *file_priv)
2148 ret = __hw_ppgtt_init(ppgtt, dev_priv);
2150 kref_init(&ppgtt->ref);
2151 i915_address_space_init(&ppgtt->base, dev_priv);
2152 ppgtt->base.file = file_priv;
2158 int i915_ppgtt_init_hw(struct drm_device *dev)
2160 gtt_write_workarounds(dev);
2162 /* In the case of execlists, PPGTT is enabled by the context descriptor
2163 * and the PDPs are contained within the context itself. We don't
2164 * need to do anything here. */
2165 if (i915.enable_execlists)
2168 if (!USES_PPGTT(dev))
2172 gen6_ppgtt_enable(dev);
2173 else if (IS_GEN7(dev))
2174 gen7_ppgtt_enable(dev);
2175 else if (INTEL_INFO(dev)->gen >= 8)
2176 gen8_ppgtt_enable(dev);
2178 MISSING_CASE(INTEL_INFO(dev)->gen);
2183 struct i915_hw_ppgtt *
2184 i915_ppgtt_create(struct drm_i915_private *dev_priv,
2185 struct drm_i915_file_private *fpriv)
2187 struct i915_hw_ppgtt *ppgtt;
2190 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2192 return ERR_PTR(-ENOMEM);
2194 ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv);
2197 return ERR_PTR(ret);
2200 trace_i915_ppgtt_create(&ppgtt->base);
2205 void i915_ppgtt_release(struct kref *kref)
2207 struct i915_hw_ppgtt *ppgtt =
2208 container_of(kref, struct i915_hw_ppgtt, ref);
2210 trace_i915_ppgtt_release(&ppgtt->base);
2212 /* vmas should already be unbound and destroyed */
2213 WARN_ON(!list_empty(&ppgtt->base.active_list));
2214 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2215 WARN_ON(!list_empty(&ppgtt->base.unbound_list));
2217 list_del(&ppgtt->base.global_link);
2218 drm_mm_takedown(&ppgtt->base.mm);
2220 ppgtt->base.cleanup(&ppgtt->base);
2224 /* Certain Gen5 chipsets require require idling the GPU before
2225 * unmapping anything from the GTT when VT-d is enabled.
2227 static bool needs_idle_maps(struct drm_i915_private *dev_priv)
2229 #ifdef CONFIG_INTEL_IOMMU
2230 /* Query intel_iommu to see if we need the workaround. Presumably that
2233 if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped)
2239 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
2241 struct intel_engine_cs *engine;
2243 if (INTEL_INFO(dev_priv)->gen < 6)
2246 for_each_engine(engine, dev_priv) {
2248 fault_reg = I915_READ(RING_FAULT_REG(engine));
2249 if (fault_reg & RING_FAULT_VALID) {
2250 DRM_DEBUG_DRIVER("Unexpected fault\n"
2252 "\tAddress space: %s\n"
2255 fault_reg & PAGE_MASK,
2256 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2257 RING_FAULT_SRCID(fault_reg),
2258 RING_FAULT_FAULT_TYPE(fault_reg));
2259 I915_WRITE(RING_FAULT_REG(engine),
2260 fault_reg & ~RING_FAULT_VALID);
2263 POSTING_READ(RING_FAULT_REG(&dev_priv->engine[RCS]));
2266 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2268 if (INTEL_INFO(dev_priv)->gen < 6) {
2269 intel_gtt_chipset_flush();
2271 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2272 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2276 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2278 struct drm_i915_private *dev_priv = to_i915(dev);
2279 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2281 /* Don't bother messing with faults pre GEN6 as we have little
2282 * documentation supporting that it's a good idea.
2284 if (INTEL_INFO(dev)->gen < 6)
2287 i915_check_and_clear_faults(dev_priv);
2289 ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
2292 i915_ggtt_flush(dev_priv);
2295 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
2297 if (!dma_map_sg(&obj->base.dev->pdev->dev,
2298 obj->pages->sgl, obj->pages->nents,
2299 PCI_DMA_BIDIRECTIONAL))
2305 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2310 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
2313 enum i915_cache_level level,
2316 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2317 gen8_pte_t __iomem *pte =
2318 (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
2319 (offset >> PAGE_SHIFT);
2322 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2324 gen8_set_pte(pte, gen8_pte_encode(addr, level, true));
2326 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2327 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2329 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2332 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2333 struct sg_table *st,
2335 enum i915_cache_level level, u32 unused)
2337 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2338 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2339 struct sgt_iter sgt_iter;
2340 gen8_pte_t __iomem *gtt_entries;
2341 gen8_pte_t gtt_entry;
2346 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2348 gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT);
2350 for_each_sgt_dma(addr, sgt_iter, st) {
2351 gtt_entry = gen8_pte_encode(addr, level, true);
2352 gen8_set_pte(>t_entries[i++], gtt_entry);
2356 * XXX: This serves as a posting read to make sure that the PTE has
2357 * actually been updated. There is some concern that even though
2358 * registers and PTEs are within the same BAR that they are potentially
2359 * of NUMA access patterns. Therefore, even with the way we assume
2360 * hardware should work, we must keep this posting read for paranoia.
2363 WARN_ON(readq(>t_entries[i-1]) != gtt_entry);
2365 /* This next bit makes the above posting read even more important. We
2366 * want to flush the TLBs only after we're certain all the PTE updates
2369 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2370 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2372 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2375 struct insert_entries {
2376 struct i915_address_space *vm;
2377 struct sg_table *st;
2379 enum i915_cache_level level;
2383 static int gen8_ggtt_insert_entries__cb(void *_arg)
2385 struct insert_entries *arg = _arg;
2386 gen8_ggtt_insert_entries(arg->vm, arg->st,
2387 arg->start, arg->level, arg->flags);
2391 static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2392 struct sg_table *st,
2394 enum i915_cache_level level,
2397 struct insert_entries arg = { vm, st, start, level, flags };
2398 stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
2401 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
2404 enum i915_cache_level level,
2407 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2408 gen6_pte_t __iomem *pte =
2409 (gen6_pte_t __iomem *)dev_priv->ggtt.gsm +
2410 (offset >> PAGE_SHIFT);
2413 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2415 iowrite32(vm->pte_encode(addr, level, true, flags), pte);
2417 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2418 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2420 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2424 * Binds an object into the global gtt with the specified cache level. The object
2425 * will be accessible to the GPU via commands whose operands reference offsets
2426 * within the global GTT as well as accessible by the GPU through the GMADR
2427 * mapped BAR (dev_priv->mm.gtt->gtt).
2429 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2430 struct sg_table *st,
2432 enum i915_cache_level level, u32 flags)
2434 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2435 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2436 struct sgt_iter sgt_iter;
2437 gen6_pte_t __iomem *gtt_entries;
2438 gen6_pte_t gtt_entry;
2443 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2445 gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT);
2447 for_each_sgt_dma(addr, sgt_iter, st) {
2448 gtt_entry = vm->pte_encode(addr, level, true, flags);
2449 iowrite32(gtt_entry, >t_entries[i++]);
2452 /* XXX: This serves as a posting read to make sure that the PTE has
2453 * actually been updated. There is some concern that even though
2454 * registers and PTEs are within the same BAR that they are potentially
2455 * of NUMA access patterns. Therefore, even with the way we assume
2456 * hardware should work, we must keep this posting read for paranoia.
2459 WARN_ON(readl(>t_entries[i-1]) != gtt_entry);
2461 /* This next bit makes the above posting read even more important. We
2462 * want to flush the TLBs only after we're certain all the PTE updates
2465 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2466 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2468 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2471 static void nop_clear_range(struct i915_address_space *vm,
2478 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2483 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2484 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2485 unsigned first_entry = start >> PAGE_SHIFT;
2486 unsigned num_entries = length >> PAGE_SHIFT;
2487 gen8_pte_t scratch_pte, __iomem *gtt_base =
2488 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2489 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2493 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2495 if (WARN(num_entries > max_entries,
2496 "First entry = %d; Num entries = %d (max=%d)\n",
2497 first_entry, num_entries, max_entries))
2498 num_entries = max_entries;
2500 scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
2503 for (i = 0; i < num_entries; i++)
2504 gen8_set_pte(>t_base[i], scratch_pte);
2507 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2510 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2515 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2516 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2517 unsigned first_entry = start >> PAGE_SHIFT;
2518 unsigned num_entries = length >> PAGE_SHIFT;
2519 gen6_pte_t scratch_pte, __iomem *gtt_base =
2520 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2521 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2525 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2527 if (WARN(num_entries > max_entries,
2528 "First entry = %d; Num entries = %d (max=%d)\n",
2529 first_entry, num_entries, max_entries))
2530 num_entries = max_entries;
2532 scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
2533 I915_CACHE_LLC, use_scratch, 0);
2535 for (i = 0; i < num_entries; i++)
2536 iowrite32(scratch_pte, >t_base[i]);
2539 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2542 static void i915_ggtt_insert_page(struct i915_address_space *vm,
2545 enum i915_cache_level cache_level,
2548 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2549 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2550 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2553 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2555 intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
2557 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2560 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2561 struct sg_table *pages,
2563 enum i915_cache_level cache_level, u32 unused)
2565 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2566 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2567 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2570 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2572 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
2574 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2578 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2583 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2584 unsigned first_entry = start >> PAGE_SHIFT;
2585 unsigned num_entries = length >> PAGE_SHIFT;
2588 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2590 intel_gtt_clear_range(first_entry, num_entries);
2592 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2595 static int ggtt_bind_vma(struct i915_vma *vma,
2596 enum i915_cache_level cache_level,
2599 struct drm_i915_gem_object *obj = vma->obj;
2603 ret = i915_get_ggtt_vma_pages(vma);
2607 /* Currently applicable only to VLV */
2609 pte_flags |= PTE_READ_ONLY;
2611 vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start,
2612 cache_level, pte_flags);
2615 * Without aliasing PPGTT there's no difference between
2616 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2617 * upgrade to both bound if we bind either to avoid double-binding.
2619 vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
2624 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2625 enum i915_cache_level cache_level,
2631 ret = i915_get_ggtt_vma_pages(vma);
2635 /* Currently applicable only to VLV */
2637 if (vma->obj->gt_ro)
2638 pte_flags |= PTE_READ_ONLY;
2641 if (flags & I915_VMA_GLOBAL_BIND) {
2642 vma->vm->insert_entries(vma->vm,
2643 vma->pages, vma->node.start,
2644 cache_level, pte_flags);
2647 if (flags & I915_VMA_LOCAL_BIND) {
2648 struct i915_hw_ppgtt *appgtt =
2649 to_i915(vma->vm->dev)->mm.aliasing_ppgtt;
2650 appgtt->base.insert_entries(&appgtt->base,
2651 vma->pages, vma->node.start,
2652 cache_level, pte_flags);
2658 static void ggtt_unbind_vma(struct i915_vma *vma)
2660 struct i915_hw_ppgtt *appgtt = to_i915(vma->vm->dev)->mm.aliasing_ppgtt;
2661 const u64 size = min(vma->size, vma->node.size);
2663 if (vma->flags & I915_VMA_GLOBAL_BIND)
2664 vma->vm->clear_range(vma->vm,
2665 vma->node.start, size,
2668 if (vma->flags & I915_VMA_LOCAL_BIND && appgtt)
2669 appgtt->base.clear_range(&appgtt->base,
2670 vma->node.start, size,
2674 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2676 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2677 struct device *kdev = &dev_priv->drm.pdev->dev;
2678 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2680 if (unlikely(ggtt->do_idle_maps)) {
2681 if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) {
2682 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2683 /* Wait a bit, in hopes it avoids the hang */
2688 dma_unmap_sg(kdev, obj->pages->sgl, obj->pages->nents,
2689 PCI_DMA_BIDIRECTIONAL);
2692 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2693 unsigned long color,
2697 if (node->color != color)
2700 node = list_first_entry_or_null(&node->node_list,
2703 if (node && node->allocated && node->color != color)
2707 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
2709 /* Let GEM Manage all of the aperture.
2711 * However, leave one page at the end still bound to the scratch page.
2712 * There are a number of places where the hardware apparently prefetches
2713 * past the end of the object, and we've seen multiple hangs with the
2714 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2715 * aperture. One page should be enough to keep any prefetching inside
2718 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2719 unsigned long hole_start, hole_end;
2720 struct drm_mm_node *entry;
2723 ret = intel_vgt_balloon(dev_priv);
2727 /* Clear any non-preallocated blocks */
2728 drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) {
2729 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2730 hole_start, hole_end);
2731 ggtt->base.clear_range(&ggtt->base, hole_start,
2732 hole_end - hole_start, true);
2735 /* And finally clear the reserved guard page */
2736 ggtt->base.clear_range(&ggtt->base,
2737 ggtt->base.total - PAGE_SIZE, PAGE_SIZE,
2740 if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
2741 struct i915_hw_ppgtt *ppgtt;
2743 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2747 ret = __hw_ppgtt_init(ppgtt, dev_priv);
2753 if (ppgtt->base.allocate_va_range)
2754 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2757 ppgtt->base.cleanup(&ppgtt->base);
2762 ppgtt->base.clear_range(&ppgtt->base,
2767 dev_priv->mm.aliasing_ppgtt = ppgtt;
2768 WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma);
2769 ggtt->base.bind_vma = aliasing_gtt_bind_vma;
2776 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2777 * @dev_priv: i915 device
2779 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
2781 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2783 if (dev_priv->mm.aliasing_ppgtt) {
2784 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2785 ppgtt->base.cleanup(&ppgtt->base);
2789 i915_gem_cleanup_stolen(&dev_priv->drm);
2791 if (drm_mm_initialized(&ggtt->base.mm)) {
2792 intel_vgt_deballoon(dev_priv);
2794 drm_mm_takedown(&ggtt->base.mm);
2795 list_del(&ggtt->base.global_link);
2798 ggtt->base.cleanup(&ggtt->base);
2800 arch_phys_wc_del(ggtt->mtrr);
2801 io_mapping_fini(&ggtt->mappable);
2804 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2806 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2807 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2808 return snb_gmch_ctl << 20;
2811 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2813 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2814 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2816 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2818 #ifdef CONFIG_X86_32
2819 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2820 if (bdw_gmch_ctl > 4)
2824 return bdw_gmch_ctl << 20;
2827 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2829 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2830 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2833 return 1 << (20 + gmch_ctrl);
2838 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2840 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2841 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2842 return snb_gmch_ctl << 25; /* 32 MB units */
2845 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2847 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2848 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2849 return bdw_gmch_ctl << 25; /* 32 MB units */
2852 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2854 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2855 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2858 * 0x0 to 0x10: 32MB increments starting at 0MB
2859 * 0x11 to 0x16: 4MB increments starting at 8MB
2860 * 0x17 to 0x1d: 4MB increments start at 36MB
2862 if (gmch_ctrl < 0x11)
2863 return gmch_ctrl << 25;
2864 else if (gmch_ctrl < 0x17)
2865 return (gmch_ctrl - 0x11 + 2) << 22;
2867 return (gmch_ctrl - 0x17 + 9) << 22;
2870 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2872 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2873 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2875 if (gen9_gmch_ctl < 0xf0)
2876 return gen9_gmch_ctl << 25; /* 32 MB units */
2878 /* 4MB increments starting at 0xf0 for 4MB */
2879 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2882 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
2884 struct pci_dev *pdev = ggtt->base.dev->pdev;
2885 phys_addr_t phys_addr;
2888 /* For Modern GENs the PTEs and register space are split in the BAR */
2889 phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
2892 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2893 * dropped. For WC mappings in general we have 64 byte burst writes
2894 * when the WC buffer is flushed, so we can't use it, but have to
2895 * resort to an uncached mapping. The WC issue is easily caught by the
2896 * readback check when writing GTT PTE entries.
2898 if (IS_BROXTON(ggtt->base.dev))
2899 ggtt->gsm = ioremap_nocache(phys_addr, size);
2901 ggtt->gsm = ioremap_wc(phys_addr, size);
2903 DRM_ERROR("Failed to map the ggtt page table\n");
2907 ret = setup_scratch_page(ggtt->base.dev,
2908 &ggtt->base.scratch_page,
2911 DRM_ERROR("Scratch setup failed\n");
2912 /* iounmap will also get called at remove, but meh */
2920 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2921 * bits. When using advanced contexts each context stores its own PAT, but
2922 * writing this data shouldn't be harmful even in those cases. */
2923 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2927 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2928 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2929 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2930 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2931 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2932 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2933 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2934 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2936 if (!USES_PPGTT(dev_priv))
2937 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2938 * so RTL will always use the value corresponding to
2940 * So let's disable cache for GGTT to avoid screen corruptions.
2941 * MOCS still can be used though.
2942 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2943 * before this patch, i.e. the same uncached + snooping access
2944 * like on gen6/7 seems to be in effect.
2945 * - So this just fixes blitter/render access. Again it looks
2946 * like it's not just uncached access, but uncached + snooping.
2947 * So we can still hold onto all our assumptions wrt cpu
2948 * clflushing on LLC machines.
2950 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2952 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2953 * write would work. */
2954 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2955 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2958 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2963 * Map WB on BDW to snooped on CHV.
2965 * Only the snoop bit has meaning for CHV, the rest is
2968 * The hardware will never snoop for certain types of accesses:
2969 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2970 * - PPGTT page tables
2971 * - some other special cycles
2973 * As with BDW, we also need to consider the following for GT accesses:
2974 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2975 * so RTL will always use the value corresponding to
2977 * Which means we must set the snoop bit in PAT entry 0
2978 * in order to keep the global status page working.
2980 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2984 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2985 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2986 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2987 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2989 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2990 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2993 static void gen6_gmch_remove(struct i915_address_space *vm)
2995 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2998 cleanup_scratch_page(vm->dev, &vm->scratch_page);
3001 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
3003 struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev);
3004 struct pci_dev *pdev = dev_priv->drm.pdev;
3008 /* TODO: We're not aware of mappable constraints on gen8 yet */
3009 ggtt->mappable_base = pci_resource_start(pdev, 2);
3010 ggtt->mappable_end = pci_resource_len(pdev, 2);
3012 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39)))
3013 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
3015 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3017 if (INTEL_GEN(dev_priv) >= 9) {
3018 ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
3019 size = gen8_get_total_gtt_size(snb_gmch_ctl);
3020 } else if (IS_CHERRYVIEW(dev_priv)) {
3021 ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
3022 size = chv_get_total_gtt_size(snb_gmch_ctl);
3024 ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
3025 size = gen8_get_total_gtt_size(snb_gmch_ctl);
3028 ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
3030 if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
3031 chv_setup_private_ppat(dev_priv);
3033 bdw_setup_private_ppat(dev_priv);
3035 ggtt->base.cleanup = gen6_gmch_remove;
3036 ggtt->base.bind_vma = ggtt_bind_vma;
3037 ggtt->base.unbind_vma = ggtt_unbind_vma;
3038 ggtt->base.insert_page = gen8_ggtt_insert_page;
3039 ggtt->base.clear_range = nop_clear_range;
3040 if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
3041 ggtt->base.clear_range = gen8_ggtt_clear_range;
3043 ggtt->base.insert_entries = gen8_ggtt_insert_entries;
3044 if (IS_CHERRYVIEW(dev_priv))
3045 ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
3047 return ggtt_probe_common(ggtt, size);
3050 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
3052 struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev);
3053 struct pci_dev *pdev = dev_priv->drm.pdev;
3057 ggtt->mappable_base = pci_resource_start(pdev, 2);
3058 ggtt->mappable_end = pci_resource_len(pdev, 2);
3060 /* 64/512MB is the current min/max we actually know of, but this is just
3061 * a coarse sanity check.
3063 if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
3064 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end);
3068 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
3069 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
3070 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3072 ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
3074 size = gen6_get_total_gtt_size(snb_gmch_ctl);
3075 ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
3077 ggtt->base.clear_range = gen6_ggtt_clear_range;
3078 ggtt->base.insert_page = gen6_ggtt_insert_page;
3079 ggtt->base.insert_entries = gen6_ggtt_insert_entries;
3080 ggtt->base.bind_vma = ggtt_bind_vma;
3081 ggtt->base.unbind_vma = ggtt_unbind_vma;
3082 ggtt->base.cleanup = gen6_gmch_remove;
3084 if (HAS_EDRAM(dev_priv))
3085 ggtt->base.pte_encode = iris_pte_encode;
3086 else if (IS_HASWELL(dev_priv))
3087 ggtt->base.pte_encode = hsw_pte_encode;
3088 else if (IS_VALLEYVIEW(dev_priv))
3089 ggtt->base.pte_encode = byt_pte_encode;
3090 else if (INTEL_GEN(dev_priv) >= 7)
3091 ggtt->base.pte_encode = ivb_pte_encode;
3093 ggtt->base.pte_encode = snb_pte_encode;
3095 return ggtt_probe_common(ggtt, size);
3098 static void i915_gmch_remove(struct i915_address_space *vm)
3100 intel_gmch_remove();
3103 static int i915_gmch_probe(struct i915_ggtt *ggtt)
3105 struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev);
3108 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL);
3110 DRM_ERROR("failed to set up gmch\n");
3114 intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size,
3115 &ggtt->mappable_base, &ggtt->mappable_end);
3117 ggtt->do_idle_maps = needs_idle_maps(dev_priv);
3118 ggtt->base.insert_page = i915_ggtt_insert_page;
3119 ggtt->base.insert_entries = i915_ggtt_insert_entries;
3120 ggtt->base.clear_range = i915_ggtt_clear_range;
3121 ggtt->base.bind_vma = ggtt_bind_vma;
3122 ggtt->base.unbind_vma = ggtt_unbind_vma;
3123 ggtt->base.cleanup = i915_gmch_remove;
3125 if (unlikely(ggtt->do_idle_maps))
3126 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3132 * i915_ggtt_probe_hw - Probe GGTT hardware location
3133 * @dev_priv: i915 device
3135 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
3137 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3140 ggtt->base.dev = &dev_priv->drm;
3142 if (INTEL_GEN(dev_priv) <= 5)
3143 ret = i915_gmch_probe(ggtt);
3144 else if (INTEL_GEN(dev_priv) < 8)
3145 ret = gen6_gmch_probe(ggtt);
3147 ret = gen8_gmch_probe(ggtt);
3151 if ((ggtt->base.total - 1) >> 32) {
3152 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3153 " of address space! Found %lldM!\n",
3154 ggtt->base.total >> 20);
3155 ggtt->base.total = 1ULL << 32;
3156 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3159 if (ggtt->mappable_end > ggtt->base.total) {
3160 DRM_ERROR("mappable aperture extends past end of GGTT,"
3161 " aperture=%llx, total=%llx\n",
3162 ggtt->mappable_end, ggtt->base.total);
3163 ggtt->mappable_end = ggtt->base.total;
3166 /* GMADR is the PCI mmio aperture into the global GTT. */
3167 DRM_INFO("Memory usable by graphics device = %lluM\n",
3168 ggtt->base.total >> 20);
3169 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20);
3170 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20);
3171 #ifdef CONFIG_INTEL_IOMMU
3172 if (intel_iommu_gfx_mapped)
3173 DRM_INFO("VT-d active for gfx access\n");
3180 * i915_ggtt_init_hw - Initialize GGTT hardware
3181 * @dev_priv: i915 device
3183 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
3185 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3188 INIT_LIST_HEAD(&dev_priv->vm_list);
3190 /* Subtract the guard page before address space initialization to
3191 * shrink the range used by drm_mm.
3193 ggtt->base.total -= PAGE_SIZE;
3194 i915_address_space_init(&ggtt->base, dev_priv);
3195 ggtt->base.total += PAGE_SIZE;
3196 if (!HAS_LLC(dev_priv))
3197 ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
3199 if (!io_mapping_init_wc(&dev_priv->ggtt.mappable,
3200 dev_priv->ggtt.mappable_base,
3201 dev_priv->ggtt.mappable_end)) {
3203 goto out_gtt_cleanup;
3206 ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end);
3209 * Initialise stolen early so that we may reserve preallocated
3210 * objects for the BIOS to KMS transition.
3212 ret = i915_gem_init_stolen(&dev_priv->drm);
3214 goto out_gtt_cleanup;
3219 ggtt->base.cleanup(&ggtt->base);
3223 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
3225 if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt())
3231 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3233 struct drm_i915_private *dev_priv = to_i915(dev);
3234 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3235 struct drm_i915_gem_object *obj, *on;
3237 i915_check_and_clear_faults(dev_priv);
3239 /* First fill our portion of the GTT with scratch pages */
3240 ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
3243 ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */
3245 /* clflush objects bound into the GGTT and rebind them. */
3246 list_for_each_entry_safe(obj, on,
3247 &dev_priv->mm.bound_list, global_list) {
3248 bool ggtt_bound = false;
3249 struct i915_vma *vma;
3251 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3252 if (vma->vm != &ggtt->base)
3255 if (!i915_vma_unbind(vma))
3258 WARN_ON(i915_vma_bind(vma, obj->cache_level,
3264 WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
3267 ggtt->base.closed = false;
3269 if (INTEL_INFO(dev)->gen >= 8) {
3270 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3271 chv_setup_private_ppat(dev_priv);
3273 bdw_setup_private_ppat(dev_priv);
3278 if (USES_PPGTT(dev)) {
3279 struct i915_address_space *vm;
3281 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3282 /* TODO: Perhaps it shouldn't be gen6 specific */
3284 struct i915_hw_ppgtt *ppgtt;
3286 if (i915_is_ggtt(vm))
3287 ppgtt = dev_priv->mm.aliasing_ppgtt;
3289 ppgtt = i915_vm_to_ppgtt(vm);
3291 gen6_write_page_range(dev_priv, &ppgtt->pd,
3292 0, ppgtt->base.total);
3296 i915_ggtt_flush(dev_priv);
3300 i915_vma_retire(struct i915_gem_active *active,
3301 struct drm_i915_gem_request *rq)
3303 const unsigned int idx = rq->engine->id;
3304 struct i915_vma *vma =
3305 container_of(active, struct i915_vma, last_read[idx]);
3307 GEM_BUG_ON(!i915_vma_has_active_engine(vma, idx));
3309 i915_vma_clear_active(vma, idx);
3310 if (i915_vma_is_active(vma))
3313 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
3314 if (unlikely(i915_vma_is_closed(vma) && !i915_vma_is_pinned(vma)))
3315 WARN_ON(i915_vma_unbind(vma));
3318 void i915_vma_destroy(struct i915_vma *vma)
3320 GEM_BUG_ON(vma->node.allocated);
3321 GEM_BUG_ON(i915_vma_is_active(vma));
3322 GEM_BUG_ON(!i915_vma_is_closed(vma));
3323 GEM_BUG_ON(vma->fence);
3325 list_del(&vma->vm_link);
3326 if (!i915_vma_is_ggtt(vma))
3327 i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
3329 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
3332 void i915_vma_close(struct i915_vma *vma)
3334 GEM_BUG_ON(i915_vma_is_closed(vma));
3335 vma->flags |= I915_VMA_CLOSED;
3337 list_del_init(&vma->obj_link);
3338 if (!i915_vma_is_active(vma) && !i915_vma_is_pinned(vma))
3339 WARN_ON(i915_vma_unbind(vma));
3342 static struct i915_vma *
3343 __i915_vma_create(struct drm_i915_gem_object *obj,
3344 struct i915_address_space *vm,
3345 const struct i915_ggtt_view *view)
3347 struct i915_vma *vma;
3350 GEM_BUG_ON(vm->closed);
3352 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
3354 return ERR_PTR(-ENOMEM);
3356 INIT_LIST_HEAD(&vma->exec_list);
3357 for (i = 0; i < ARRAY_SIZE(vma->last_read); i++)
3358 init_request_active(&vma->last_read[i], i915_vma_retire);
3359 init_request_active(&vma->last_fence, NULL);
3360 list_add(&vma->vm_link, &vm->unbound_list);
3363 vma->size = obj->base.size;
3366 vma->ggtt_view = *view;
3367 if (view->type == I915_GGTT_VIEW_PARTIAL) {
3368 vma->size = view->params.partial.size;
3369 vma->size <<= PAGE_SHIFT;
3370 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3372 intel_rotation_info_size(&view->params.rotated);
3373 vma->size <<= PAGE_SHIFT;
3377 if (i915_is_ggtt(vm)) {
3378 vma->flags |= I915_VMA_GGTT;
3380 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
3383 list_add_tail(&vma->obj_link, &obj->vma_list);
3387 static inline bool vma_matches(struct i915_vma *vma,
3388 struct i915_address_space *vm,
3389 const struct i915_ggtt_view *view)
3394 if (!i915_vma_is_ggtt(vma))
3398 return vma->ggtt_view.type == 0;
3400 if (vma->ggtt_view.type != view->type)
3403 return memcmp(&vma->ggtt_view.params,
3405 sizeof(view->params)) == 0;
3409 i915_vma_create(struct drm_i915_gem_object *obj,
3410 struct i915_address_space *vm,
3411 const struct i915_ggtt_view *view)
3413 GEM_BUG_ON(view && !i915_is_ggtt(vm));
3414 GEM_BUG_ON(i915_gem_obj_to_vma(obj, vm, view));
3416 return __i915_vma_create(obj, vm, view);
3420 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3421 struct i915_address_space *vm,
3422 const struct i915_ggtt_view *view)
3424 struct i915_vma *vma;
3426 list_for_each_entry_reverse(vma, &obj->vma_list, obj_link)
3427 if (vma_matches(vma, vm, view))
3434 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3435 struct i915_address_space *vm,
3436 const struct i915_ggtt_view *view)
3438 struct i915_vma *vma;
3440 GEM_BUG_ON(view && !i915_is_ggtt(vm));
3442 vma = i915_gem_obj_to_vma(obj, vm, view);
3444 vma = __i915_vma_create(obj, vm, view);
3446 GEM_BUG_ON(i915_vma_is_closed(vma));
3450 static struct scatterlist *
3451 rotate_pages(const dma_addr_t *in, unsigned int offset,
3452 unsigned int width, unsigned int height,
3453 unsigned int stride,
3454 struct sg_table *st, struct scatterlist *sg)
3456 unsigned int column, row;
3457 unsigned int src_idx;
3459 for (column = 0; column < width; column++) {
3460 src_idx = stride * (height - 1) + column;
3461 for (row = 0; row < height; row++) {
3463 /* We don't need the pages, but need to initialize
3464 * the entries so the sg list can be happily traversed.
3465 * The only thing we need are DMA addresses.
3467 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3468 sg_dma_address(sg) = in[offset + src_idx];
3469 sg_dma_len(sg) = PAGE_SIZE;
3478 static struct sg_table *
3479 intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info,
3480 struct drm_i915_gem_object *obj)
3482 const size_t n_pages = obj->base.size / PAGE_SIZE;
3483 unsigned int size = intel_rotation_info_size(rot_info);
3484 struct sgt_iter sgt_iter;
3485 dma_addr_t dma_addr;
3487 dma_addr_t *page_addr_list;
3488 struct sg_table *st;
3489 struct scatterlist *sg;
3492 /* Allocate a temporary list of source pages for random access. */
3493 page_addr_list = drm_malloc_gfp(n_pages,
3496 if (!page_addr_list)
3497 return ERR_PTR(ret);
3499 /* Allocate target SG list. */
3500 st = kmalloc(sizeof(*st), GFP_KERNEL);
3504 ret = sg_alloc_table(st, size, GFP_KERNEL);
3508 /* Populate source page list from the object. */
3510 for_each_sgt_dma(dma_addr, sgt_iter, obj->pages)
3511 page_addr_list[i++] = dma_addr;
3513 GEM_BUG_ON(i != n_pages);
3517 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
3518 sg = rotate_pages(page_addr_list, rot_info->plane[i].offset,
3519 rot_info->plane[i].width, rot_info->plane[i].height,
3520 rot_info->plane[i].stride, st, sg);
3523 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n",
3524 obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size);
3526 drm_free_large(page_addr_list);
3533 drm_free_large(page_addr_list);
3535 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
3536 obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size);
3538 return ERR_PTR(ret);
3541 static struct sg_table *
3542 intel_partial_pages(const struct i915_ggtt_view *view,
3543 struct drm_i915_gem_object *obj)
3545 struct sg_table *st;
3546 struct scatterlist *sg;
3547 struct sg_page_iter obj_sg_iter;
3550 st = kmalloc(sizeof(*st), GFP_KERNEL);
3554 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3560 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3561 view->params.partial.offset)
3563 if (st->nents >= view->params.partial.size)
3566 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3567 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3568 sg_dma_len(sg) = PAGE_SIZE;
3579 return ERR_PTR(ret);
3583 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3590 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3591 vma->pages = vma->obj->pages;
3592 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3594 intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj);
3595 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3596 vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
3598 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3599 vma->ggtt_view.type);
3602 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3603 vma->ggtt_view.type);
3605 } else if (IS_ERR(vma->pages)) {
3606 ret = PTR_ERR(vma->pages);
3608 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3609 vma->ggtt_view.type, ret);
3616 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3618 * @cache_level: mapping cache level
3619 * @flags: flags like global or local mapping
3621 * DMA addresses are taken from the scatter-gather table of this object (or of
3622 * this VMA in case of non-default GGTT views) and PTE entries set up.
3623 * Note that DMA addresses are also the only part of the SG table we care about.
3625 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3632 if (WARN_ON(flags == 0))
3636 if (flags & PIN_GLOBAL)
3637 bind_flags |= I915_VMA_GLOBAL_BIND;
3638 if (flags & PIN_USER)
3639 bind_flags |= I915_VMA_LOCAL_BIND;
3641 vma_flags = vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND);
3642 if (flags & PIN_UPDATE)
3643 bind_flags |= vma_flags;
3645 bind_flags &= ~vma_flags;
3646 if (bind_flags == 0)
3649 if (vma_flags == 0 && vma->vm->allocate_va_range) {
3650 trace_i915_va_alloc(vma);
3651 ret = vma->vm->allocate_va_range(vma->vm,
3658 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
3662 vma->flags |= bind_flags;
3666 void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
3670 /* Access through the GTT requires the device to be awake. */
3671 assert_rpm_wakelock_held(to_i915(vma->vm->dev));
3673 lockdep_assert_held(&vma->vm->dev->struct_mutex);
3674 if (WARN_ON(!i915_vma_is_map_and_fenceable(vma)))
3675 return IO_ERR_PTR(-ENODEV);
3677 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
3678 GEM_BUG_ON((vma->flags & I915_VMA_GLOBAL_BIND) == 0);
3682 ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->mappable,
3686 return IO_ERR_PTR(-ENOMEM);
3691 __i915_vma_pin(vma);
3695 void i915_vma_unpin_and_release(struct i915_vma **p_vma)
3697 struct i915_vma *vma;
3699 vma = fetch_and_zero(p_vma);
3703 i915_vma_unpin(vma);