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25 #include <drm/i915_drm.h>
29 * DOC: fence register handling
31 * Important to avoid confusions: "fences" in the i915 driver are not execution
32 * fences used to track command completion but hardware detiler objects which
33 * wrap a given range of the global GTT. Each platform has only a fairly limited
34 * set of these objects.
36 * Fences are used to detile GTT memory mappings. They're also connected to the
37 * hardware frontbuffer render tracking and hence interract with frontbuffer
38 * conmpression. Furthermore on older platforms fences are required for tiled
39 * objects used by the display engine. They can also be used by the render
40 * engine - they're required for blitter commands and are optional for render
41 * commands. But on gen4+ both display (with the exception of fbc) and rendering
42 * have their own tiling state bits and don't need fences.
44 * Also note that fences only support X and Y tiling and hence can't be used for
45 * the fancier new tiling formats like W, Ys and Yf.
47 * Finally note that because fences are such a restricted resource they're
48 * dynamically associated with objects. Furthermore fence state is committed to
49 * the hardware lazily to avoid unecessary stalls on gen2/3. Therefore code must
50 * explictly call i915_gem_object_get_fence() to synchronize fencing status
51 * for cpu access. Also note that some code wants an unfenced view, for those
52 * cases the fence can be removed forcefully with i915_gem_object_put_fence().
54 * Internally these functions will synchronize with userspace access by removing
55 * CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.
58 static void i965_write_fence_reg(struct drm_device *dev, int reg,
59 struct drm_i915_gem_object *obj)
61 struct drm_i915_private *dev_priv = dev->dev_private;
63 int fence_pitch_shift;
65 if (INTEL_INFO(dev)->gen >= 6) {
66 fence_reg = FENCE_REG_SANDYBRIDGE_0;
67 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
69 fence_reg = FENCE_REG_965_0;
70 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
75 /* To w/a incoherency with non-atomic 64-bit register updates,
76 * we split the 64-bit update into two 32-bit writes. In order
77 * for a partial fence not to be evaluated between writes, we
78 * precede the update with write to turn off the fence register,
79 * and only enable the fence as the last step.
81 * For extra levels of paranoia, we make sure each step lands
82 * before applying the next step.
84 I915_WRITE(fence_reg, 0);
85 POSTING_READ(fence_reg);
88 u32 size = i915_gem_obj_ggtt_size(obj);
91 /* Adjust fence size to match tiled area */
92 if (obj->tiling_mode != I915_TILING_NONE) {
93 uint32_t row_size = obj->stride *
94 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
95 size = (size / row_size) * row_size;
98 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
100 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
101 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
102 if (obj->tiling_mode == I915_TILING_Y)
103 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
104 val |= I965_FENCE_REG_VALID;
106 I915_WRITE(fence_reg + 4, val >> 32);
107 POSTING_READ(fence_reg + 4);
109 I915_WRITE(fence_reg + 0, val);
110 POSTING_READ(fence_reg);
112 I915_WRITE(fence_reg + 4, 0);
113 POSTING_READ(fence_reg + 4);
117 static void i915_write_fence_reg(struct drm_device *dev, int reg,
118 struct drm_i915_gem_object *obj)
120 struct drm_i915_private *dev_priv = dev->dev_private;
124 u32 size = i915_gem_obj_ggtt_size(obj);
128 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
129 (size & -size) != size ||
130 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
131 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
132 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
134 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
139 /* Note: pitch better be a power of two tile widths */
140 pitch_val = obj->stride / tile_width;
141 pitch_val = ffs(pitch_val) - 1;
143 val = i915_gem_obj_ggtt_offset(obj);
144 if (obj->tiling_mode == I915_TILING_Y)
145 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
146 val |= I915_FENCE_SIZE_BITS(size);
147 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
148 val |= I830_FENCE_REG_VALID;
153 reg = FENCE_REG_830_0 + reg * 4;
155 reg = FENCE_REG_945_8 + (reg - 8) * 4;
157 I915_WRITE(reg, val);
161 static void i830_write_fence_reg(struct drm_device *dev, int reg,
162 struct drm_i915_gem_object *obj)
164 struct drm_i915_private *dev_priv = dev->dev_private;
168 u32 size = i915_gem_obj_ggtt_size(obj);
171 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
172 (size & -size) != size ||
173 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
174 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
175 i915_gem_obj_ggtt_offset(obj), size);
177 pitch_val = obj->stride / 128;
178 pitch_val = ffs(pitch_val) - 1;
180 val = i915_gem_obj_ggtt_offset(obj);
181 if (obj->tiling_mode == I915_TILING_Y)
182 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
183 val |= I830_FENCE_SIZE_BITS(size);
184 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
185 val |= I830_FENCE_REG_VALID;
189 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
190 POSTING_READ(FENCE_REG_830_0 + reg * 4);
193 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
195 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
198 static void i915_gem_write_fence(struct drm_device *dev, int reg,
199 struct drm_i915_gem_object *obj)
201 struct drm_i915_private *dev_priv = dev->dev_private;
203 /* Ensure that all CPU reads are completed before installing a fence
204 * and all writes before removing the fence.
206 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
209 WARN(obj && (!obj->stride || !obj->tiling_mode),
210 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
211 obj->stride, obj->tiling_mode);
214 i830_write_fence_reg(dev, reg, obj);
215 else if (IS_GEN3(dev))
216 i915_write_fence_reg(dev, reg, obj);
217 else if (INTEL_INFO(dev)->gen >= 4)
218 i965_write_fence_reg(dev, reg, obj);
220 /* And similarly be paranoid that no direct access to this region
221 * is reordered to before the fence is installed.
223 if (i915_gem_object_needs_mb(obj))
227 static inline int fence_number(struct drm_i915_private *dev_priv,
228 struct drm_i915_fence_reg *fence)
230 return fence - dev_priv->fence_regs;
233 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
234 struct drm_i915_fence_reg *fence,
237 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
238 int reg = fence_number(dev_priv, fence);
240 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
243 obj->fence_reg = reg;
245 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
247 obj->fence_reg = I915_FENCE_REG_NONE;
249 list_del_init(&fence->lru_list);
251 obj->fence_dirty = false;
254 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
256 if (obj->tiling_mode)
257 i915_gem_release_mmap(obj);
259 /* As we do not have an associated fence register, we will force
260 * a tiling change if we ever need to acquire one.
262 obj->fence_dirty = false;
263 obj->fence_reg = I915_FENCE_REG_NONE;
267 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
269 if (obj->last_fenced_req) {
270 int ret = i915_wait_request(obj->last_fenced_req);
274 i915_gem_request_assign(&obj->last_fenced_req, NULL);
281 * i915_gem_object_put_fence - force-remove fence for an object
282 * @obj: object to map through a fence reg
284 * This function force-removes any fence from the given object, which is useful
285 * if the kernel wants to do untiled GTT access.
289 * 0 on success, negative error code on failure.
292 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
294 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
295 struct drm_i915_fence_reg *fence;
298 ret = i915_gem_object_wait_fence(obj);
302 if (obj->fence_reg == I915_FENCE_REG_NONE)
305 fence = &dev_priv->fence_regs[obj->fence_reg];
307 if (WARN_ON(fence->pin_count))
310 i915_gem_object_fence_lost(obj);
311 i915_gem_object_update_fence(obj, fence, false);
316 static struct drm_i915_fence_reg *
317 i915_find_fence_reg(struct drm_device *dev)
319 struct drm_i915_private *dev_priv = dev->dev_private;
320 struct drm_i915_fence_reg *reg, *avail;
323 /* First try to find a free reg */
325 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
326 reg = &dev_priv->fence_regs[i];
337 /* None available, try to steal one or wait for a user to finish */
338 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
346 /* Wait for completion of pending flips which consume fences */
347 if (intel_has_pending_fb_unpin(dev))
348 return ERR_PTR(-EAGAIN);
350 return ERR_PTR(-EDEADLK);
354 * i915_gem_object_get_fence - set up fencing for an object
355 * @obj: object to map through a fence reg
357 * When mapping objects through the GTT, userspace wants to be able to write
358 * to them without having to worry about swizzling if the object is tiled.
359 * This function walks the fence regs looking for a free one for @obj,
360 * stealing one if it can't find any.
362 * It then sets up the reg based on the object's properties: address, pitch
365 * For an untiled surface, this removes any existing fence.
369 * 0 on success, negative error code on failure.
372 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
374 struct drm_device *dev = obj->base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376 bool enable = obj->tiling_mode != I915_TILING_NONE;
377 struct drm_i915_fence_reg *reg;
380 /* Have we updated the tiling parameters upon the object and so
381 * will need to serialise the write to the associated fence register?
383 if (obj->fence_dirty) {
384 ret = i915_gem_object_wait_fence(obj);
389 /* Just update our place in the LRU if our fence is getting reused. */
390 if (obj->fence_reg != I915_FENCE_REG_NONE) {
391 reg = &dev_priv->fence_regs[obj->fence_reg];
392 if (!obj->fence_dirty) {
393 list_move_tail(®->lru_list,
394 &dev_priv->mm.fence_list);
398 if (WARN_ON(!obj->map_and_fenceable))
401 reg = i915_find_fence_reg(dev);
406 struct drm_i915_gem_object *old = reg->obj;
408 ret = i915_gem_object_wait_fence(old);
412 i915_gem_object_fence_lost(old);
417 i915_gem_object_update_fence(obj, reg, enable);
423 * i915_gem_object_pin_fence - pin fencing state
424 * @obj: object to pin fencing for
426 * This pins the fencing state (whether tiled or untiled) to make sure the
427 * object is ready to be used as a scanout target. Fencing status must be
428 * synchronize first by calling i915_gem_object_get_fence():
430 * The resulting fence pin reference must be released again with
431 * i915_gem_object_unpin_fence().
435 * True if the object has a fence, false otherwise.
438 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
440 if (obj->fence_reg != I915_FENCE_REG_NONE) {
441 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
442 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
445 dev_priv->fence_regs[obj->fence_reg].pin_count >
446 ggtt_vma->pin_count);
447 dev_priv->fence_regs[obj->fence_reg].pin_count++;
454 * i915_gem_object_unpin_fence - unpin fencing state
455 * @obj: object to unpin fencing for
457 * This releases the fence pin reference acquired through
458 * i915_gem_object_pin_fence. It will handle both objects with and without an
459 * attached fence correctly, callers do not need to distinguish this.
462 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
464 if (obj->fence_reg != I915_FENCE_REG_NONE) {
465 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
466 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
467 dev_priv->fence_regs[obj->fence_reg].pin_count--;
472 * i915_gem_restore_fences - restore fence state
475 * Restore the hw fence state to match the software tracking again, to be called
476 * after a gpu reset and on resume.
478 void i915_gem_restore_fences(struct drm_device *dev)
480 struct drm_i915_private *dev_priv = dev->dev_private;
483 for (i = 0; i < dev_priv->num_fence_regs; i++) {
484 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
487 * Commit delayed tiling changes if we have an object still
488 * attached to the fence, otherwise just clear the fence.
491 i915_gem_object_update_fence(reg->obj, reg,
492 reg->obj->tiling_mode);
494 i915_gem_write_fence(dev, i, NULL);