2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/sync_file.h>
32 #include <linux/uaccess.h>
35 #include <drm/drm_syncobj.h>
36 #include <drm/i915_drm.h>
39 #include "i915_gem_clflush.h"
40 #include "i915_trace.h"
41 #include "intel_drv.h"
42 #include "intel_frontbuffer.h"
48 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
51 #define __EXEC_OBJECT_HAS_REF BIT(31)
52 #define __EXEC_OBJECT_HAS_PIN BIT(30)
53 #define __EXEC_OBJECT_HAS_FENCE BIT(29)
54 #define __EXEC_OBJECT_NEEDS_MAP BIT(28)
55 #define __EXEC_OBJECT_NEEDS_BIAS BIT(27)
56 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */
57 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
59 #define __EXEC_HAS_RELOC BIT(31)
60 #define __EXEC_VALIDATED BIT(30)
61 #define __EXEC_INTERNAL_FLAGS (~0u << 30)
62 #define UPDATE PIN_OFFSET_FIXED
64 #define BATCH_OFFSET_BIAS (256*1024)
66 #define __I915_EXEC_ILLEGAL_FLAGS \
67 (__I915_EXEC_UNKNOWN_FLAGS | I915_EXEC_CONSTANTS_MASK)
70 * DOC: User command execution
72 * Userspace submits commands to be executed on the GPU as an instruction
73 * stream within a GEM object we call a batchbuffer. This instructions may
74 * refer to other GEM objects containing auxiliary state such as kernels,
75 * samplers, render targets and even secondary batchbuffers. Userspace does
76 * not know where in the GPU memory these objects reside and so before the
77 * batchbuffer is passed to the GPU for execution, those addresses in the
78 * batchbuffer and auxiliary objects are updated. This is known as relocation,
79 * or patching. To try and avoid having to relocate each object on the next
80 * execution, userspace is told the location of those objects in this pass,
81 * but this remains just a hint as the kernel may choose a new location for
82 * any object in the future.
84 * Processing an execbuf ioctl is conceptually split up into a few phases.
86 * 1. Validation - Ensure all the pointers, handles and flags are valid.
87 * 2. Reservation - Assign GPU address space for every object
88 * 3. Relocation - Update any addresses to point to the final locations
89 * 4. Serialisation - Order the request with respect to its dependencies
90 * 5. Construction - Construct a request to execute the batchbuffer
91 * 6. Submission (at some point in the future execution)
93 * Reserving resources for the execbuf is the most complicated phase. We
94 * neither want to have to migrate the object in the address space, nor do
95 * we want to have to update any relocations pointing to this object. Ideally,
96 * we want to leave the object where it is and for all the existing relocations
97 * to match. If the object is given a new address, or if userspace thinks the
98 * object is elsewhere, we have to parse all the relocation entries and update
99 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
100 * all the target addresses in all of its objects match the value in the
101 * relocation entries and that they all match the presumed offsets given by the
102 * list of execbuffer objects. Using this knowledge, we know that if we haven't
103 * moved any buffers, all the relocation entries are valid and we can skip
104 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
105 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
107 * The addresses written in the objects must match the corresponding
108 * reloc.presumed_offset which in turn must match the corresponding
111 * Any render targets written to in the batch must be flagged with
114 * To avoid stalling, execobject.offset should match the current
115 * address of that object within the active context.
117 * The reservation is done is multiple phases. First we try and keep any
118 * object already bound in its current location - so as long as meets the
119 * constraints imposed by the new execbuffer. Any object left unbound after the
120 * first pass is then fitted into any available idle space. If an object does
121 * not fit, all objects are removed from the reservation and the process rerun
122 * after sorting the objects into a priority order (more difficult to fit
123 * objects are tried first). Failing that, the entire VM is cleared and we try
124 * to fit the execbuf once last time before concluding that it simply will not
127 * A small complication to all of this is that we allow userspace not only to
128 * specify an alignment and a size for the object in the address space, but
129 * we also allow userspace to specify the exact offset. This objects are
130 * simpler to place (the location is known a priori) all we have to do is make
131 * sure the space is available.
133 * Once all the objects are in place, patching up the buried pointers to point
134 * to the final locations is a fairly simple job of walking over the relocation
135 * entry arrays, looking up the right address and rewriting the value into
136 * the object. Simple! ... The relocation entries are stored in user memory
137 * and so to access them we have to copy them into a local buffer. That copy
138 * has to avoid taking any pagefaults as they may lead back to a GEM object
139 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
140 * the relocation into multiple passes. First we try to do everything within an
141 * atomic context (avoid the pagefaults) which requires that we never wait. If
142 * we detect that we may wait, or if we need to fault, then we have to fallback
143 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
144 * bells yet?) Dropping the mutex means that we lose all the state we have
145 * built up so far for the execbuf and we must reset any global data. However,
146 * we do leave the objects pinned in their final locations - which is a
147 * potential issue for concurrent execbufs. Once we have left the mutex, we can
148 * allocate and copy all the relocation entries into a large array at our
149 * leisure, reacquire the mutex, reclaim all the objects and other state and
150 * then proceed to update any incorrect addresses with the objects.
152 * As we process the relocation entries, we maintain a record of whether the
153 * object is being written to. Using NORELOC, we expect userspace to provide
154 * this information instead. We also check whether we can skip the relocation
155 * by comparing the expected value inside the relocation entry with the target's
156 * final address. If they differ, we have to map the current object and rewrite
157 * the 4 or 8 byte pointer within.
159 * Serialising an execbuf is quite simple according to the rules of the GEM
160 * ABI. Execution within each context is ordered by the order of submission.
161 * Writes to any GEM object are in order of submission and are exclusive. Reads
162 * from a GEM object are unordered with respect to other reads, but ordered by
163 * writes. A write submitted after a read cannot occur before the read, and
164 * similarly any read submitted after a write cannot occur before the write.
165 * Writes are ordered between engines such that only one write occurs at any
166 * time (completing any reads beforehand) - using semaphores where available
167 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
168 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
169 * reads before starting, and any read (either using set-domain or pread) must
170 * flush all GPU writes before starting. (Note we only employ a barrier before,
171 * we currently rely on userspace not concurrently starting a new execution
172 * whilst reading or writing to an object. This may be an advantage or not
173 * depending on how much you trust userspace not to shoot themselves in the
174 * foot.) Serialisation may just result in the request being inserted into
175 * a DAG awaiting its turn, but most simple is to wait on the CPU until
176 * all dependencies are resolved.
178 * After all of that, is just a matter of closing the request and handing it to
179 * the hardware (well, leaving it in a queue to be executed). However, we also
180 * offer the ability for batchbuffers to be run with elevated privileges so
181 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
182 * Before any batch is given extra privileges we first must check that it
183 * contains no nefarious instructions, we check that each instruction is from
184 * our whitelist and all registers are also from an allowed list. We first
185 * copy the user's batchbuffer to a shadow (so that the user doesn't have
186 * access to it, either by the CPU or GPU as we scan it) and then parse each
187 * instruction. If everything is ok, we set a flag telling the hardware to run
188 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
191 struct i915_execbuffer {
192 struct drm_i915_private *i915; /** i915 backpointer */
193 struct drm_file *file; /** per-file lookup tables and limits */
194 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
195 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
196 struct i915_vma **vma;
199 struct intel_engine_cs *engine; /** engine to queue the request to */
200 struct i915_gem_context *ctx; /** context for building the request */
201 struct i915_address_space *vm; /** GTT and vma for the request */
203 struct drm_i915_gem_request *request; /** our request to build */
204 struct i915_vma *batch; /** identity of the batch obj/vma */
206 /** actual size of execobj[] as we may extend it for the cmdparser */
207 unsigned int buffer_count;
209 /** list of vma not yet bound during reservation phase */
210 struct list_head unbound;
212 /** list of vma that have execobj.relocation_count */
213 struct list_head relocs;
216 * Track the most recently used object for relocations, as we
217 * frequently have to perform multiple relocations within the same
221 struct drm_mm_node node; /** temporary GTT binding */
222 unsigned long vaddr; /** Current kmap address */
223 unsigned long page; /** Currently mapped page index */
224 unsigned int gen; /** Cached value of INTEL_GEN */
225 bool use_64bit_reloc : 1;
228 bool needs_unfenced : 1;
230 struct drm_i915_gem_request *rq;
232 unsigned int rq_size;
235 u64 invalid_flags; /** Set of execobj.flags that are invalid */
236 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
238 u32 batch_start_offset; /** Location within object of batch */
239 u32 batch_len; /** Length of batch within object */
240 u32 batch_flags; /** Flags composed for emit_bb_start() */
243 * Indicate either the size of the hastable used to resolve
244 * relocation handles, or if negative that we are using a direct
245 * index into the execobj[].
248 struct hlist_head *buckets; /** ht for relocation handles */
251 #define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
254 * Used to convert any address to canonical form.
255 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
256 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
257 * addresses to be in a canonical form:
258 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
259 * canonical form [63:48] == [47]."
261 #define GEN8_HIGH_ADDRESS_BIT 47
262 static inline u64 gen8_canonical_addr(u64 address)
264 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
267 static inline u64 gen8_noncanonical_addr(u64 address)
269 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
272 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
274 return eb->engine->needs_cmd_parser && eb->batch_len;
277 static int eb_create(struct i915_execbuffer *eb)
279 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
280 unsigned int size = 1 + ilog2(eb->buffer_count);
283 * Without a 1:1 association between relocation handles and
284 * the execobject[] index, we instead create a hashtable.
285 * We size it dynamically based on available memory, starting
286 * first with 1:1 assocative hash and scaling back until
287 * the allocation succeeds.
289 * Later on we use a positive lut_size to indicate we are
290 * using this hashtable, and a negative value to indicate a
296 /* While we can still reduce the allocation size, don't
297 * raise a warning and allow the allocation to fail.
298 * On the last pass though, we want to try as hard
299 * as possible to perform the allocation and warn
304 flags |= __GFP_NORETRY | __GFP_NOWARN;
306 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
317 eb->lut_size = -eb->buffer_count;
324 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
325 const struct i915_vma *vma,
328 if (vma->node.size < entry->pad_to_size)
331 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
334 if (flags & EXEC_OBJECT_PINNED &&
335 vma->node.start != entry->offset)
338 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
339 vma->node.start < BATCH_OFFSET_BIAS)
342 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
343 (vma->node.start + vma->node.size - 1) >> 32)
350 eb_pin_vma(struct i915_execbuffer *eb,
351 const struct drm_i915_gem_exec_object2 *entry,
352 struct i915_vma *vma)
354 unsigned int exec_flags = *vma->exec_flags;
358 pin_flags = vma->node.start;
360 pin_flags = entry->offset & PIN_OFFSET_MASK;
362 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
363 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_GTT))
364 pin_flags |= PIN_GLOBAL;
366 if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags)))
369 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
370 if (unlikely(i915_vma_pin_fence(vma))) {
376 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
379 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
380 return !eb_vma_misplaced(entry, vma, exec_flags);
383 static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
385 GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
387 if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
388 __i915_vma_unpin_fence(vma);
390 __i915_vma_unpin(vma);
394 eb_unreserve_vma(struct i915_vma *vma, unsigned int *flags)
396 if (!(*flags & __EXEC_OBJECT_HAS_PIN))
399 __eb_unreserve_vma(vma, *flags);
400 *flags &= ~__EXEC_OBJECT_RESERVED;
404 eb_validate_vma(struct i915_execbuffer *eb,
405 struct drm_i915_gem_exec_object2 *entry,
406 struct i915_vma *vma)
408 if (unlikely(entry->flags & eb->invalid_flags))
411 if (unlikely(entry->alignment && !is_power_of_2(entry->alignment)))
415 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
416 * any non-page-aligned or non-canonical addresses.
418 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
419 entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
422 /* pad_to_size was once a reserved field, so sanitize it */
423 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
424 if (unlikely(offset_in_page(entry->pad_to_size)))
427 entry->pad_to_size = 0;
430 if (unlikely(vma->exec_flags)) {
431 DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n",
432 entry->handle, (int)(entry - eb->exec));
437 * From drm_mm perspective address space is continuous,
438 * so from this point we're always using non-canonical
441 entry->offset = gen8_noncanonical_addr(entry->offset);
443 if (!eb->reloc_cache.has_fence) {
444 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
446 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
447 eb->reloc_cache.needs_unfenced) &&
448 i915_gem_object_is_tiled(vma->obj))
449 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
452 if (!(entry->flags & EXEC_OBJECT_PINNED))
453 entry->flags |= eb->context_flags;
459 eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma)
461 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
464 GEM_BUG_ON(i915_vma_is_closed(vma));
466 if (!(eb->args->flags & __EXEC_VALIDATED)) {
467 err = eb_validate_vma(eb, entry, vma);
472 if (eb->lut_size > 0) {
473 vma->exec_handle = entry->handle;
474 hlist_add_head(&vma->exec_node,
475 &eb->buckets[hash_32(entry->handle,
479 if (entry->relocation_count)
480 list_add_tail(&vma->reloc_link, &eb->relocs);
483 * Stash a pointer from the vma to execobj, so we can query its flags,
484 * size, alignment etc as provided by the user. Also we stash a pointer
485 * to the vma inside the execobj so that we can use a direct lookup
486 * to find the right target VMA when doing relocations.
489 eb->flags[i] = entry->flags;
490 vma->exec_flags = &eb->flags[i];
493 if (eb_pin_vma(eb, entry, vma)) {
494 if (entry->offset != vma->node.start) {
495 entry->offset = vma->node.start | UPDATE;
496 eb->args->flags |= __EXEC_HAS_RELOC;
499 eb_unreserve_vma(vma, vma->exec_flags);
501 list_add_tail(&vma->exec_link, &eb->unbound);
502 if (drm_mm_node_allocated(&vma->node))
503 err = i915_vma_unbind(vma);
508 static inline int use_cpu_reloc(const struct reloc_cache *cache,
509 const struct drm_i915_gem_object *obj)
511 if (!i915_gem_object_has_struct_page(obj))
514 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
517 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
520 return (cache->has_llc ||
522 obj->cache_level != I915_CACHE_NONE);
525 static int eb_reserve_vma(const struct i915_execbuffer *eb,
526 struct i915_vma *vma)
528 struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
529 unsigned int exec_flags = *vma->exec_flags;
533 pin_flags = PIN_USER | PIN_NONBLOCK;
534 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
535 pin_flags |= PIN_GLOBAL;
538 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
539 * limit address to the first 4GBs for unflagged objects.
541 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
542 pin_flags |= PIN_ZONE_4G;
544 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
545 pin_flags |= PIN_MAPPABLE;
547 if (exec_flags & EXEC_OBJECT_PINNED) {
548 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
549 pin_flags &= ~PIN_NONBLOCK; /* force overlapping checks */
550 } else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) {
551 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
554 err = i915_vma_pin(vma,
555 entry->pad_to_size, entry->alignment,
560 if (entry->offset != vma->node.start) {
561 entry->offset = vma->node.start | UPDATE;
562 eb->args->flags |= __EXEC_HAS_RELOC;
565 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
566 err = i915_vma_pin_fence(vma);
573 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
576 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
577 GEM_BUG_ON(eb_vma_misplaced(entry, vma, exec_flags));
582 static int eb_reserve(struct i915_execbuffer *eb)
584 const unsigned int count = eb->buffer_count;
585 struct list_head last;
586 struct i915_vma *vma;
587 unsigned int i, pass;
591 * Attempt to pin all of the buffers into the GTT.
592 * This is done in 3 phases:
594 * 1a. Unbind all objects that do not match the GTT constraints for
595 * the execbuffer (fenceable, mappable, alignment etc).
596 * 1b. Increment pin count for already bound objects.
597 * 2. Bind new objects.
598 * 3. Decrement pin count.
600 * This avoid unnecessary unbinding of later objects in order to make
601 * room for the earlier objects *unless* we need to defragment.
607 list_for_each_entry(vma, &eb->unbound, exec_link) {
608 err = eb_reserve_vma(eb, vma);
615 /* Resort *all* the objects into priority order */
616 INIT_LIST_HEAD(&eb->unbound);
617 INIT_LIST_HEAD(&last);
618 for (i = 0; i < count; i++) {
619 unsigned int flags = eb->flags[i];
620 struct i915_vma *vma = eb->vma[i];
622 if (flags & EXEC_OBJECT_PINNED &&
623 flags & __EXEC_OBJECT_HAS_PIN)
626 eb_unreserve_vma(vma, &eb->flags[i]);
628 if (flags & EXEC_OBJECT_PINNED)
629 list_add(&vma->exec_link, &eb->unbound);
630 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
631 list_add_tail(&vma->exec_link, &eb->unbound);
633 list_add_tail(&vma->exec_link, &last);
635 list_splice_tail(&last, &eb->unbound);
642 /* Too fragmented, unbind everything and retry */
643 err = i915_gem_evict_vm(eb->vm);
654 static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
656 if (eb->args->flags & I915_EXEC_BATCH_FIRST)
659 return eb->buffer_count - 1;
662 static int eb_select_context(struct i915_execbuffer *eb)
664 struct i915_gem_context *ctx;
666 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
671 eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base;
673 eb->context_flags = 0;
674 if (ctx->flags & CONTEXT_NO_ZEROMAP)
675 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
680 static int eb_lookup_vmas(struct i915_execbuffer *eb)
682 struct radix_tree_root *handles_vma = &eb->ctx->handles_vma;
683 struct drm_i915_gem_object *obj;
687 if (unlikely(i915_gem_context_is_closed(eb->ctx)))
690 if (unlikely(i915_gem_context_is_banned(eb->ctx)))
693 INIT_LIST_HEAD(&eb->relocs);
694 INIT_LIST_HEAD(&eb->unbound);
696 for (i = 0; i < eb->buffer_count; i++) {
697 u32 handle = eb->exec[i].handle;
698 struct i915_lut_handle *lut;
699 struct i915_vma *vma;
701 vma = radix_tree_lookup(handles_vma, handle);
705 obj = i915_gem_object_lookup(eb->file, handle);
706 if (unlikely(!obj)) {
711 vma = i915_vma_instance(obj, eb->vm, NULL);
712 if (unlikely(IS_ERR(vma))) {
717 lut = kmem_cache_alloc(eb->i915->luts, GFP_KERNEL);
718 if (unlikely(!lut)) {
723 err = radix_tree_insert(handles_vma, handle, vma);
729 /* transfer ref to ctx */
731 list_add(&lut->obj_link, &obj->lut_list);
732 list_add(&lut->ctx_link, &eb->ctx->handles_list);
734 lut->handle = handle;
737 err = eb_add_vma(eb, i, vma);
741 GEM_BUG_ON(vma != eb->vma[i]);
742 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
745 /* take note of the batch buffer before we might reorder the lists */
746 i = eb_batch_index(eb);
747 eb->batch = eb->vma[i];
748 GEM_BUG_ON(eb->batch->exec_flags != &eb->flags[i]);
751 * SNA is doing fancy tricks with compressing batch buffers, which leads
752 * to negative relocation deltas. Usually that works out ok since the
753 * relocate address is still positive, except when the batch is placed
754 * very low in the GTT. Ensure this doesn't happen.
756 * Note that actual hangs have only been observed on gen7, but for
757 * paranoia do it everywhere.
759 if (!(eb->flags[i] & EXEC_OBJECT_PINNED))
760 eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS;
761 if (eb->reloc_cache.has_fence)
762 eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE;
764 eb->args->flags |= __EXEC_VALIDATED;
765 return eb_reserve(eb);
768 i915_gem_object_put(obj);
774 static struct i915_vma *
775 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
777 if (eb->lut_size < 0) {
778 if (handle >= -eb->lut_size)
780 return eb->vma[handle];
782 struct hlist_head *head;
783 struct i915_vma *vma;
785 head = &eb->buckets[hash_32(handle, eb->lut_size)];
786 hlist_for_each_entry(vma, head, exec_node) {
787 if (vma->exec_handle == handle)
794 static void eb_release_vmas(const struct i915_execbuffer *eb)
796 const unsigned int count = eb->buffer_count;
799 for (i = 0; i < count; i++) {
800 struct i915_vma *vma = eb->vma[i];
801 unsigned int flags = eb->flags[i];
806 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
807 vma->exec_flags = NULL;
810 if (flags & __EXEC_OBJECT_HAS_PIN)
811 __eb_unreserve_vma(vma, flags);
813 if (flags & __EXEC_OBJECT_HAS_REF)
818 static void eb_reset_vmas(const struct i915_execbuffer *eb)
821 if (eb->lut_size > 0)
822 memset(eb->buckets, 0,
823 sizeof(struct hlist_head) << eb->lut_size);
826 static void eb_destroy(const struct i915_execbuffer *eb)
828 GEM_BUG_ON(eb->reloc_cache.rq);
830 if (eb->lut_size > 0)
835 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
836 const struct i915_vma *target)
838 return gen8_canonical_addr((int)reloc->delta + target->node.start);
841 static void reloc_cache_init(struct reloc_cache *cache,
842 struct drm_i915_private *i915)
846 /* Must be a variable in the struct to allow GCC to unroll. */
847 cache->gen = INTEL_GEN(i915);
848 cache->has_llc = HAS_LLC(i915);
849 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
850 cache->has_fence = cache->gen < 4;
851 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
852 cache->node.allocated = false;
857 static inline void *unmask_page(unsigned long p)
859 return (void *)(uintptr_t)(p & PAGE_MASK);
862 static inline unsigned int unmask_flags(unsigned long p)
864 return p & ~PAGE_MASK;
867 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
869 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
871 struct drm_i915_private *i915 =
872 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
876 static void reloc_gpu_flush(struct reloc_cache *cache)
878 GEM_BUG_ON(cache->rq_size >= cache->rq->batch->obj->base.size / sizeof(u32));
879 cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
880 i915_gem_object_unpin_map(cache->rq->batch->obj);
881 i915_gem_chipset_flush(cache->rq->i915);
883 __i915_add_request(cache->rq, true);
887 static void reloc_cache_reset(struct reloc_cache *cache)
892 reloc_gpu_flush(cache);
897 vaddr = unmask_page(cache->vaddr);
898 if (cache->vaddr & KMAP) {
899 if (cache->vaddr & CLFLUSH_AFTER)
902 kunmap_atomic(vaddr);
903 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
906 io_mapping_unmap_atomic((void __iomem *)vaddr);
907 if (cache->node.allocated) {
908 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
910 ggtt->base.clear_range(&ggtt->base,
913 drm_mm_remove_node(&cache->node);
915 i915_vma_unpin((struct i915_vma *)cache->node.mm);
923 static void *reloc_kmap(struct drm_i915_gem_object *obj,
924 struct reloc_cache *cache,
930 kunmap_atomic(unmask_page(cache->vaddr));
932 unsigned int flushes;
935 err = i915_gem_obj_prepare_shmem_write(obj, &flushes);
939 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
940 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
942 cache->vaddr = flushes | KMAP;
943 cache->node.mm = (void *)obj;
948 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
949 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
955 static void *reloc_iomap(struct drm_i915_gem_object *obj,
956 struct reloc_cache *cache,
959 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
960 unsigned long offset;
964 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
966 struct i915_vma *vma;
969 if (use_cpu_reloc(cache, obj))
972 err = i915_gem_object_set_to_gtt_domain(obj, true);
976 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
981 memset(&cache->node, 0, sizeof(cache->node));
982 err = drm_mm_insert_node_in_range
983 (&ggtt->base.mm, &cache->node,
984 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
985 0, ggtt->mappable_end,
987 if (err) /* no inactive aperture space, use cpu reloc */
990 err = i915_vma_put_fence(vma);
996 cache->node.start = vma->node.start;
997 cache->node.mm = (void *)vma;
1001 offset = cache->node.start;
1002 if (cache->node.allocated) {
1004 ggtt->base.insert_page(&ggtt->base,
1005 i915_gem_object_get_dma_address(obj, page),
1006 offset, I915_CACHE_NONE, 0);
1008 offset += page << PAGE_SHIFT;
1011 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->mappable,
1014 cache->vaddr = (unsigned long)vaddr;
1019 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1020 struct reloc_cache *cache,
1025 if (cache->page == page) {
1026 vaddr = unmask_page(cache->vaddr);
1029 if ((cache->vaddr & KMAP) == 0)
1030 vaddr = reloc_iomap(obj, cache, page);
1032 vaddr = reloc_kmap(obj, cache, page);
1038 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1040 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1041 if (flushes & CLFLUSH_BEFORE) {
1049 * Writes to the same cacheline are serialised by the CPU
1050 * (including clflush). On the write path, we only require
1051 * that it hits memory in an orderly fashion and place
1052 * mb barriers at the start and end of the relocation phase
1053 * to ensure ordering of clflush wrt to the system.
1055 if (flushes & CLFLUSH_AFTER)
1061 static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
1062 struct i915_vma *vma,
1065 struct reloc_cache *cache = &eb->reloc_cache;
1066 struct drm_i915_gem_object *obj;
1067 struct drm_i915_gem_request *rq;
1068 struct i915_vma *batch;
1072 GEM_BUG_ON(vma->obj->base.write_domain & I915_GEM_DOMAIN_CPU);
1074 obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE);
1076 return PTR_ERR(obj);
1078 cmd = i915_gem_object_pin_map(obj,
1082 i915_gem_object_unpin_pages(obj);
1084 return PTR_ERR(cmd);
1086 err = i915_gem_object_set_to_wc_domain(obj, false);
1090 batch = i915_vma_instance(obj, vma->vm, NULL);
1091 if (IS_ERR(batch)) {
1092 err = PTR_ERR(batch);
1096 err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK);
1100 rq = i915_gem_request_alloc(eb->engine, eb->ctx);
1106 err = i915_gem_request_await_object(rq, vma->obj, true);
1110 err = eb->engine->emit_flush(rq, EMIT_INVALIDATE);
1114 err = i915_switch_context(rq);
1118 err = eb->engine->emit_bb_start(rq,
1119 batch->node.start, PAGE_SIZE,
1120 cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
1124 GEM_BUG_ON(!reservation_object_test_signaled_rcu(batch->resv, true));
1125 i915_vma_move_to_active(batch, rq, 0);
1126 reservation_object_lock(batch->resv, NULL);
1127 reservation_object_add_excl_fence(batch->resv, &rq->fence);
1128 reservation_object_unlock(batch->resv);
1129 i915_vma_unpin(batch);
1131 i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1132 reservation_object_lock(vma->resv, NULL);
1133 reservation_object_add_excl_fence(vma->resv, &rq->fence);
1134 reservation_object_unlock(vma->resv);
1139 cache->rq_cmd = cmd;
1142 /* Return with batch mapping (cmd) still pinned */
1146 i915_add_request(rq);
1148 i915_vma_unpin(batch);
1150 i915_gem_object_unpin_map(obj);
1154 static u32 *reloc_gpu(struct i915_execbuffer *eb,
1155 struct i915_vma *vma,
1158 struct reloc_cache *cache = &eb->reloc_cache;
1161 if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))
1162 reloc_gpu_flush(cache);
1164 if (unlikely(!cache->rq)) {
1167 /* If we need to copy for the cmdparser, we will stall anyway */
1168 if (eb_use_cmdparser(eb))
1169 return ERR_PTR(-EWOULDBLOCK);
1171 if (!intel_engine_can_store_dword(eb->engine))
1172 return ERR_PTR(-ENODEV);
1174 err = __reloc_gpu_alloc(eb, vma, len);
1176 return ERR_PTR(err);
1179 cmd = cache->rq_cmd + cache->rq_size;
1180 cache->rq_size += len;
1186 relocate_entry(struct i915_vma *vma,
1187 const struct drm_i915_gem_relocation_entry *reloc,
1188 struct i915_execbuffer *eb,
1189 const struct i915_vma *target)
1191 u64 offset = reloc->offset;
1192 u64 target_offset = relocation_target(reloc, target);
1193 bool wide = eb->reloc_cache.use_64bit_reloc;
1196 if (!eb->reloc_cache.vaddr &&
1197 (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
1198 !reservation_object_test_signaled_rcu(vma->resv, true))) {
1199 const unsigned int gen = eb->reloc_cache.gen;
1205 len = offset & 7 ? 8 : 5;
1211 batch = reloc_gpu(eb, vma, len);
1215 addr = gen8_canonical_addr(vma->node.start + offset);
1218 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1219 *batch++ = lower_32_bits(addr);
1220 *batch++ = upper_32_bits(addr);
1221 *batch++ = lower_32_bits(target_offset);
1223 addr = gen8_canonical_addr(addr + 4);
1225 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1226 *batch++ = lower_32_bits(addr);
1227 *batch++ = upper_32_bits(addr);
1228 *batch++ = upper_32_bits(target_offset);
1230 *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
1231 *batch++ = lower_32_bits(addr);
1232 *batch++ = upper_32_bits(addr);
1233 *batch++ = lower_32_bits(target_offset);
1234 *batch++ = upper_32_bits(target_offset);
1236 } else if (gen >= 6) {
1237 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1240 *batch++ = target_offset;
1241 } else if (gen >= 4) {
1242 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1245 *batch++ = target_offset;
1247 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1249 *batch++ = target_offset;
1256 vaddr = reloc_vaddr(vma->obj, &eb->reloc_cache, offset >> PAGE_SHIFT);
1258 return PTR_ERR(vaddr);
1260 clflush_write32(vaddr + offset_in_page(offset),
1261 lower_32_bits(target_offset),
1262 eb->reloc_cache.vaddr);
1265 offset += sizeof(u32);
1266 target_offset >>= 32;
1272 return target->node.start | UPDATE;
1276 eb_relocate_entry(struct i915_execbuffer *eb,
1277 struct i915_vma *vma,
1278 const struct drm_i915_gem_relocation_entry *reloc)
1280 struct i915_vma *target;
1283 /* we've already hold a reference to all valid objects */
1284 target = eb_get_vma(eb, reloc->target_handle);
1285 if (unlikely(!target))
1288 /* Validate that the target is in a valid r/w GPU domain */
1289 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1290 DRM_DEBUG("reloc with multiple write domains: "
1291 "target %d offset %d "
1292 "read %08x write %08x",
1293 reloc->target_handle,
1294 (int) reloc->offset,
1295 reloc->read_domains,
1296 reloc->write_domain);
1299 if (unlikely((reloc->write_domain | reloc->read_domains)
1300 & ~I915_GEM_GPU_DOMAINS)) {
1301 DRM_DEBUG("reloc with read/write non-GPU domains: "
1302 "target %d offset %d "
1303 "read %08x write %08x",
1304 reloc->target_handle,
1305 (int) reloc->offset,
1306 reloc->read_domains,
1307 reloc->write_domain);
1311 if (reloc->write_domain) {
1312 *target->exec_flags |= EXEC_OBJECT_WRITE;
1315 * Sandybridge PPGTT errata: We need a global gtt mapping
1316 * for MI and pipe_control writes because the gpu doesn't
1317 * properly redirect them through the ppgtt for non_secure
1320 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1321 IS_GEN6(eb->i915)) {
1322 err = i915_vma_bind(target, target->obj->cache_level,
1325 "Unexpected failure to bind target VMA!"))
1331 * If the relocation already has the right value in it, no
1332 * more work needs to be done.
1334 if (!DBG_FORCE_RELOC &&
1335 gen8_canonical_addr(target->node.start) == reloc->presumed_offset)
1338 /* Check that the relocation address is valid... */
1339 if (unlikely(reloc->offset >
1340 vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1341 DRM_DEBUG("Relocation beyond object bounds: "
1342 "target %d offset %d size %d.\n",
1343 reloc->target_handle,
1348 if (unlikely(reloc->offset & 3)) {
1349 DRM_DEBUG("Relocation not 4-byte aligned: "
1350 "target %d offset %d.\n",
1351 reloc->target_handle,
1352 (int)reloc->offset);
1357 * If we write into the object, we need to force the synchronisation
1358 * barrier, either with an asynchronous clflush or if we executed the
1359 * patching using the GPU (though that should be serialised by the
1360 * timeline). To be completely sure, and since we are required to
1361 * do relocations we are already stalling, disable the user's opt
1362 * out of our synchronisation.
1364 *vma->exec_flags &= ~EXEC_OBJECT_ASYNC;
1366 /* and update the user's relocation entry */
1367 return relocate_entry(vma, reloc, eb, target);
1370 static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
1372 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1373 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1374 struct drm_i915_gem_relocation_entry __user *urelocs;
1375 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1376 unsigned int remain;
1378 urelocs = u64_to_user_ptr(entry->relocs_ptr);
1379 remain = entry->relocation_count;
1380 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1384 * We must check that the entire relocation array is safe
1385 * to read. However, if the array is not writable the user loses
1386 * the updated relocation values.
1388 if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(*urelocs))))
1392 struct drm_i915_gem_relocation_entry *r = stack;
1393 unsigned int count =
1394 min_t(unsigned int, remain, ARRAY_SIZE(stack));
1395 unsigned int copied;
1398 * This is the fast path and we cannot handle a pagefault
1399 * whilst holding the struct mutex lest the user pass in the
1400 * relocations contained within a mmaped bo. For in such a case
1401 * we, the page fault handler would call i915_gem_fault() and
1402 * we would try to acquire the struct mutex again. Obviously
1403 * this is bad and so lockdep complains vehemently.
1405 pagefault_disable();
1406 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1408 if (unlikely(copied)) {
1415 u64 offset = eb_relocate_entry(eb, vma, r);
1417 if (likely(offset == 0)) {
1418 } else if ((s64)offset < 0) {
1419 remain = (int)offset;
1423 * Note that reporting an error now
1424 * leaves everything in an inconsistent
1425 * state as we have *already* changed
1426 * the relocation value inside the
1427 * object. As we have not changed the
1428 * reloc.presumed_offset or will not
1429 * change the execobject.offset, on the
1430 * call we may not rewrite the value
1431 * inside the object, leaving it
1432 * dangling and causing a GPU hang. Unless
1433 * userspace dynamically rebuilds the
1434 * relocations on each execbuf rather than
1435 * presume a static tree.
1437 * We did previously check if the relocations
1438 * were writable (access_ok), an error now
1439 * would be a strange race with mprotect,
1440 * having already demonstrated that we
1441 * can read from this userspace address.
1443 offset = gen8_canonical_addr(offset & ~UPDATE);
1445 &urelocs[r-stack].presumed_offset);
1447 } while (r++, --count);
1448 urelocs += ARRAY_SIZE(stack);
1451 reloc_cache_reset(&eb->reloc_cache);
1456 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma)
1458 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1459 struct drm_i915_gem_relocation_entry *relocs =
1460 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1464 for (i = 0; i < entry->relocation_count; i++) {
1465 u64 offset = eb_relocate_entry(eb, vma, &relocs[i]);
1467 if ((s64)offset < 0) {
1474 reloc_cache_reset(&eb->reloc_cache);
1478 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1480 const char __user *addr, *end;
1482 char __maybe_unused c;
1484 size = entry->relocation_count;
1488 if (size > N_RELOC(ULONG_MAX))
1491 addr = u64_to_user_ptr(entry->relocs_ptr);
1492 size *= sizeof(struct drm_i915_gem_relocation_entry);
1493 if (!access_ok(VERIFY_READ, addr, size))
1497 for (; addr < end; addr += PAGE_SIZE) {
1498 int err = __get_user(c, addr);
1502 return __get_user(c, end - 1);
1505 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1507 const unsigned int count = eb->buffer_count;
1511 for (i = 0; i < count; i++) {
1512 const unsigned int nreloc = eb->exec[i].relocation_count;
1513 struct drm_i915_gem_relocation_entry __user *urelocs;
1514 struct drm_i915_gem_relocation_entry *relocs;
1516 unsigned long copied;
1521 err = check_relocations(&eb->exec[i]);
1525 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1526 size = nreloc * sizeof(*relocs);
1528 relocs = kvmalloc_array(size, 1, GFP_KERNEL);
1535 /* copy_from_user is limited to < 4GiB */
1539 min_t(u64, BIT_ULL(31), size - copied);
1541 if (__copy_from_user((char *)relocs + copied,
1542 (char __user *)urelocs + copied,
1550 } while (copied < size);
1553 * As we do not update the known relocation offsets after
1554 * relocating (due to the complexities in lock handling),
1555 * we need to mark them as invalid now so that we force the
1556 * relocation processing next time. Just in case the target
1557 * object is evicted and then rebound into its old
1558 * presumed_offset before the next execbuffer - if that
1559 * happened we would make the mistake of assuming that the
1560 * relocations were valid.
1562 user_access_begin();
1563 for (copied = 0; copied < nreloc; copied++)
1565 &urelocs[copied].presumed_offset,
1570 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1577 struct drm_i915_gem_relocation_entry *relocs =
1578 u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1579 if (eb->exec[i].relocation_count)
1585 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1587 const unsigned int count = eb->buffer_count;
1590 if (unlikely(i915_modparams.prefault_disable))
1593 for (i = 0; i < count; i++) {
1596 err = check_relocations(&eb->exec[i]);
1604 static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
1606 struct drm_device *dev = &eb->i915->drm;
1607 bool have_copy = false;
1608 struct i915_vma *vma;
1612 if (signal_pending(current)) {
1617 /* We may process another execbuffer during the unlock... */
1619 mutex_unlock(&dev->struct_mutex);
1622 * We take 3 passes through the slowpatch.
1624 * 1 - we try to just prefault all the user relocation entries and
1625 * then attempt to reuse the atomic pagefault disabled fast path again.
1627 * 2 - we copy the user entries to a local buffer here outside of the
1628 * local and allow ourselves to wait upon any rendering before
1631 * 3 - we already have a local copy of the relocation entries, but
1632 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1635 err = eb_prefault_relocations(eb);
1636 } else if (!have_copy) {
1637 err = eb_copy_relocations(eb);
1638 have_copy = err == 0;
1644 mutex_lock(&dev->struct_mutex);
1648 /* A frequent cause for EAGAIN are currently unavailable client pages */
1649 flush_workqueue(eb->i915->mm.userptr_wq);
1651 err = i915_mutex_lock_interruptible(dev);
1653 mutex_lock(&dev->struct_mutex);
1657 /* reacquire the objects */
1658 err = eb_lookup_vmas(eb);
1662 GEM_BUG_ON(!eb->batch);
1664 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1666 pagefault_disable();
1667 err = eb_relocate_vma(eb, vma);
1672 err = eb_relocate_vma_slow(eb, vma);
1679 * Leave the user relocations as are, this is the painfully slow path,
1680 * and we want to avoid the complication of dropping the lock whilst
1681 * having buffers reserved in the aperture and so causing spurious
1682 * ENOSPC for random operations.
1691 const unsigned int count = eb->buffer_count;
1694 for (i = 0; i < count; i++) {
1695 const struct drm_i915_gem_exec_object2 *entry =
1697 struct drm_i915_gem_relocation_entry *relocs;
1699 if (!entry->relocation_count)
1702 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1710 static int eb_relocate(struct i915_execbuffer *eb)
1712 if (eb_lookup_vmas(eb))
1715 /* The objects are in their final locations, apply the relocations. */
1716 if (eb->args->flags & __EXEC_HAS_RELOC) {
1717 struct i915_vma *vma;
1719 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1720 if (eb_relocate_vma(eb, vma))
1728 return eb_relocate_slow(eb);
1731 static void eb_export_fence(struct i915_vma *vma,
1732 struct drm_i915_gem_request *req,
1735 struct reservation_object *resv = vma->resv;
1738 * Ignore errors from failing to allocate the new fence, we can't
1739 * handle an error right now. Worst case should be missed
1740 * synchronisation leading to rendering corruption.
1742 reservation_object_lock(resv, NULL);
1743 if (flags & EXEC_OBJECT_WRITE)
1744 reservation_object_add_excl_fence(resv, &req->fence);
1745 else if (reservation_object_reserve_shared(resv) == 0)
1746 reservation_object_add_shared_fence(resv, &req->fence);
1747 reservation_object_unlock(resv);
1750 static int eb_move_to_gpu(struct i915_execbuffer *eb)
1752 const unsigned int count = eb->buffer_count;
1756 for (i = 0; i < count; i++) {
1757 unsigned int flags = eb->flags[i];
1758 struct i915_vma *vma = eb->vma[i];
1759 struct drm_i915_gem_object *obj = vma->obj;
1761 if (flags & EXEC_OBJECT_CAPTURE) {
1762 struct i915_gem_capture_list *capture;
1764 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1765 if (unlikely(!capture))
1768 capture->next = eb->request->capture_list;
1769 capture->vma = eb->vma[i];
1770 eb->request->capture_list = capture;
1774 * If the GPU is not _reading_ through the CPU cache, we need
1775 * to make sure that any writes (both previous GPU writes from
1776 * before a change in snooping levels and normal CPU writes)
1777 * caught in that cache are flushed to main memory.
1780 * obj->cache_dirty &&
1781 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
1782 * but gcc's optimiser doesn't handle that as well and emits
1783 * two jumps instead of one. Maybe one day...
1785 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
1786 if (i915_gem_clflush_object(obj, 0))
1787 flags &= ~EXEC_OBJECT_ASYNC;
1790 if (flags & EXEC_OBJECT_ASYNC)
1793 err = i915_gem_request_await_object
1794 (eb->request, obj, flags & EXEC_OBJECT_WRITE);
1799 for (i = 0; i < count; i++) {
1800 unsigned int flags = eb->flags[i];
1801 struct i915_vma *vma = eb->vma[i];
1803 i915_vma_move_to_active(vma, eb->request, flags);
1804 eb_export_fence(vma, eb->request, flags);
1806 __eb_unreserve_vma(vma, flags);
1807 vma->exec_flags = NULL;
1809 if (unlikely(flags & __EXEC_OBJECT_HAS_REF))
1814 /* Unconditionally flush any chipset caches (for streaming writes). */
1815 i915_gem_chipset_flush(eb->i915);
1817 /* Unconditionally invalidate GPU caches and TLBs. */
1818 return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
1821 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1823 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
1826 /* Kernel clipping was a DRI1 misfeature */
1827 if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
1828 if (exec->num_cliprects || exec->cliprects_ptr)
1832 if (exec->DR4 == 0xffffffff) {
1833 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1836 if (exec->DR1 || exec->DR4)
1839 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1845 void i915_vma_move_to_active(struct i915_vma *vma,
1846 struct drm_i915_gem_request *req,
1849 struct drm_i915_gem_object *obj = vma->obj;
1850 const unsigned int idx = req->engine->id;
1852 lockdep_assert_held(&req->i915->drm.struct_mutex);
1853 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1856 * Add a reference if we're newly entering the active list.
1857 * The order in which we add operations to the retirement queue is
1858 * vital here: mark_active adds to the start of the callback list,
1859 * such that subsequent callbacks are called first. Therefore we
1860 * add the active reference first and queue for it to be dropped
1863 if (!i915_vma_is_active(vma))
1864 obj->active_count++;
1865 i915_vma_set_active(vma, idx);
1866 i915_gem_active_set(&vma->last_read[idx], req);
1867 list_move_tail(&vma->vm_link, &vma->vm->active_list);
1869 obj->base.write_domain = 0;
1870 if (flags & EXEC_OBJECT_WRITE) {
1871 obj->base.write_domain = I915_GEM_DOMAIN_RENDER;
1873 if (intel_fb_obj_invalidate(obj, ORIGIN_CS))
1874 i915_gem_active_set(&obj->frontbuffer_write, req);
1876 obj->base.read_domains = 0;
1878 obj->base.read_domains |= I915_GEM_GPU_DOMAINS;
1880 if (flags & EXEC_OBJECT_NEEDS_FENCE)
1881 i915_gem_active_set(&vma->last_fence, req);
1884 static int i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1889 if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1890 DRM_DEBUG("sol reset is gen7/rcs only\n");
1894 cs = intel_ring_begin(req, 4 * 2 + 2);
1898 *cs++ = MI_LOAD_REGISTER_IMM(4);
1899 for (i = 0; i < 4; i++) {
1900 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
1904 intel_ring_advance(req, cs);
1909 static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master)
1911 struct drm_i915_gem_object *shadow_batch_obj;
1912 struct i915_vma *vma;
1915 shadow_batch_obj = i915_gem_batch_pool_get(&eb->engine->batch_pool,
1916 PAGE_ALIGN(eb->batch_len));
1917 if (IS_ERR(shadow_batch_obj))
1918 return ERR_CAST(shadow_batch_obj);
1920 err = intel_engine_cmd_parser(eb->engine,
1923 eb->batch_start_offset,
1927 if (err == -EACCES) /* unhandled chained batch */
1934 vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
1938 eb->vma[eb->buffer_count] = i915_vma_get(vma);
1939 eb->flags[eb->buffer_count] =
1940 __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF;
1941 vma->exec_flags = &eb->flags[eb->buffer_count];
1945 i915_gem_object_unpin_pages(shadow_batch_obj);
1950 add_to_client(struct drm_i915_gem_request *req, struct drm_file *file)
1952 req->file_priv = file->driver_priv;
1953 list_add_tail(&req->client_link, &req->file_priv->mm.request_list);
1956 static int eb_submit(struct i915_execbuffer *eb)
1960 err = eb_move_to_gpu(eb);
1964 err = i915_switch_context(eb->request);
1968 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
1969 err = i915_reset_gen7_sol_offsets(eb->request);
1974 err = eb->engine->emit_bb_start(eb->request,
1975 eb->batch->node.start +
1976 eb->batch_start_offset,
1986 * Find one BSD ring to dispatch the corresponding BSD command.
1987 * The engine index is returned.
1990 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
1991 struct drm_file *file)
1993 struct drm_i915_file_private *file_priv = file->driver_priv;
1995 /* Check whether the file_priv has already selected one ring. */
1996 if ((int)file_priv->bsd_engine < 0)
1997 file_priv->bsd_engine = atomic_fetch_xor(1,
1998 &dev_priv->mm.bsd_engine_dispatch_index);
2000 return file_priv->bsd_engine;
2003 #define I915_USER_RINGS (4)
2005 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
2006 [I915_EXEC_DEFAULT] = RCS,
2007 [I915_EXEC_RENDER] = RCS,
2008 [I915_EXEC_BLT] = BCS,
2009 [I915_EXEC_BSD] = VCS,
2010 [I915_EXEC_VEBOX] = VECS
2013 static struct intel_engine_cs *
2014 eb_select_engine(struct drm_i915_private *dev_priv,
2015 struct drm_file *file,
2016 struct drm_i915_gem_execbuffer2 *args)
2018 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2019 struct intel_engine_cs *engine;
2021 if (user_ring_id > I915_USER_RINGS) {
2022 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
2026 if ((user_ring_id != I915_EXEC_BSD) &&
2027 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
2028 DRM_DEBUG("execbuf with non bsd ring but with invalid "
2029 "bsd dispatch flags: %d\n", (int)(args->flags));
2033 if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
2034 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2036 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2037 bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
2038 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2039 bsd_idx <= I915_EXEC_BSD_RING2) {
2040 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2043 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
2048 engine = dev_priv->engine[_VCS(bsd_idx)];
2050 engine = dev_priv->engine[user_ring_map[user_ring_id]];
2054 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
2062 __free_fence_array(struct drm_syncobj **fences, unsigned int n)
2065 drm_syncobj_put(ptr_mask_bits(fences[n], 2));
2069 static struct drm_syncobj **
2070 get_fence_array(struct drm_i915_gem_execbuffer2 *args,
2071 struct drm_file *file)
2073 const unsigned int nfences = args->num_cliprects;
2074 struct drm_i915_gem_exec_fence __user *user;
2075 struct drm_syncobj **fences;
2079 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2082 if (nfences > SIZE_MAX / sizeof(*fences))
2083 return ERR_PTR(-EINVAL);
2085 user = u64_to_user_ptr(args->cliprects_ptr);
2086 if (!access_ok(VERIFY_READ, user, nfences * 2 * sizeof(u32)))
2087 return ERR_PTR(-EFAULT);
2089 fences = kvmalloc_array(args->num_cliprects, sizeof(*fences),
2090 __GFP_NOWARN | GFP_KERNEL);
2092 return ERR_PTR(-ENOMEM);
2094 for (n = 0; n < nfences; n++) {
2095 struct drm_i915_gem_exec_fence fence;
2096 struct drm_syncobj *syncobj;
2098 if (__copy_from_user(&fence, user++, sizeof(fence))) {
2103 syncobj = drm_syncobj_find(file, fence.handle);
2105 DRM_DEBUG("Invalid syncobj handle provided\n");
2110 fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
2116 __free_fence_array(fences, n);
2117 return ERR_PTR(err);
2121 put_fence_array(struct drm_i915_gem_execbuffer2 *args,
2122 struct drm_syncobj **fences)
2125 __free_fence_array(fences, args->num_cliprects);
2129 await_fence_array(struct i915_execbuffer *eb,
2130 struct drm_syncobj **fences)
2132 const unsigned int nfences = eb->args->num_cliprects;
2136 for (n = 0; n < nfences; n++) {
2137 struct drm_syncobj *syncobj;
2138 struct dma_fence *fence;
2141 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2142 if (!(flags & I915_EXEC_FENCE_WAIT))
2145 fence = drm_syncobj_fence_get(syncobj);
2149 err = i915_gem_request_await_dma_fence(eb->request, fence);
2150 dma_fence_put(fence);
2159 signal_fence_array(struct i915_execbuffer *eb,
2160 struct drm_syncobj **fences)
2162 const unsigned int nfences = eb->args->num_cliprects;
2163 struct dma_fence * const fence = &eb->request->fence;
2166 for (n = 0; n < nfences; n++) {
2167 struct drm_syncobj *syncobj;
2170 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2171 if (!(flags & I915_EXEC_FENCE_SIGNAL))
2174 drm_syncobj_replace_fence(syncobj, fence);
2179 i915_gem_do_execbuffer(struct drm_device *dev,
2180 struct drm_file *file,
2181 struct drm_i915_gem_execbuffer2 *args,
2182 struct drm_i915_gem_exec_object2 *exec,
2183 struct drm_syncobj **fences)
2185 struct i915_execbuffer eb;
2186 struct dma_fence *in_fence = NULL;
2187 struct sync_file *out_fence = NULL;
2188 int out_fence_fd = -1;
2191 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
2192 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
2193 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
2195 eb.i915 = to_i915(dev);
2198 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
2199 args->flags |= __EXEC_HAS_RELOC;
2202 eb.vma = (struct i915_vma **)(exec + args->buffer_count + 1);
2204 eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
2206 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
2207 if (USES_FULL_PPGTT(eb.i915))
2208 eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
2209 reloc_cache_init(&eb.reloc_cache, eb.i915);
2211 eb.buffer_count = args->buffer_count;
2212 eb.batch_start_offset = args->batch_start_offset;
2213 eb.batch_len = args->batch_len;
2216 if (args->flags & I915_EXEC_SECURE) {
2217 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
2220 eb.batch_flags |= I915_DISPATCH_SECURE;
2222 if (args->flags & I915_EXEC_IS_PINNED)
2223 eb.batch_flags |= I915_DISPATCH_PINNED;
2225 eb.engine = eb_select_engine(eb.i915, file, args);
2229 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
2230 if (!HAS_RESOURCE_STREAMER(eb.i915)) {
2231 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
2234 if (eb.engine->id != RCS) {
2235 DRM_DEBUG("RS is not available on %s\n",
2240 eb.batch_flags |= I915_DISPATCH_RS;
2243 if (args->flags & I915_EXEC_FENCE_IN) {
2244 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
2249 if (args->flags & I915_EXEC_FENCE_OUT) {
2250 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
2251 if (out_fence_fd < 0) {
2257 err = eb_create(&eb);
2261 GEM_BUG_ON(!eb.lut_size);
2263 err = eb_select_context(&eb);
2268 * Take a local wakeref for preparing to dispatch the execbuf as
2269 * we expect to access the hardware fairly frequently in the
2270 * process. Upon first dispatch, we acquire another prolonged
2271 * wakeref that we hold until the GPU has been idle for at least
2274 intel_runtime_pm_get(eb.i915);
2276 err = i915_mutex_lock_interruptible(dev);
2280 err = eb_relocate(&eb);
2283 * If the user expects the execobject.offset and
2284 * reloc.presumed_offset to be an exact match,
2285 * as for using NO_RELOC, then we cannot update
2286 * the execobject.offset until we have completed
2289 args->flags &= ~__EXEC_HAS_RELOC;
2293 if (unlikely(*eb.batch->exec_flags & EXEC_OBJECT_WRITE)) {
2294 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
2298 if (eb.batch_start_offset > eb.batch->size ||
2299 eb.batch_len > eb.batch->size - eb.batch_start_offset) {
2300 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
2305 if (eb_use_cmdparser(&eb)) {
2306 struct i915_vma *vma;
2308 vma = eb_parse(&eb, drm_is_current_master(file));
2316 * Batch parsed and accepted:
2318 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
2319 * bit from MI_BATCH_BUFFER_START commands issued in
2320 * the dispatch_execbuffer implementations. We
2321 * specifically don't want that set on batches the
2322 * command parser has accepted.
2324 eb.batch_flags |= I915_DISPATCH_SECURE;
2325 eb.batch_start_offset = 0;
2330 if (eb.batch_len == 0)
2331 eb.batch_len = eb.batch->size - eb.batch_start_offset;
2334 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2335 * batch" bit. Hence we need to pin secure batches into the global gtt.
2336 * hsw should have this fixed, but bdw mucks it up again. */
2337 if (eb.batch_flags & I915_DISPATCH_SECURE) {
2338 struct i915_vma *vma;
2341 * So on first glance it looks freaky that we pin the batch here
2342 * outside of the reservation loop. But:
2343 * - The batch is already pinned into the relevant ppgtt, so we
2344 * already have the backing storage fully allocated.
2345 * - No other BO uses the global gtt (well contexts, but meh),
2346 * so we don't really have issues with multiple objects not
2347 * fitting due to fragmentation.
2348 * So this is actually safe.
2350 vma = i915_gem_object_ggtt_pin(eb.batch->obj, NULL, 0, 0, 0);
2359 /* All GPU relocation batches must be submitted prior to the user rq */
2360 GEM_BUG_ON(eb.reloc_cache.rq);
2362 /* Allocate a request for this batch buffer nice and early. */
2363 eb.request = i915_gem_request_alloc(eb.engine, eb.ctx);
2364 if (IS_ERR(eb.request)) {
2365 err = PTR_ERR(eb.request);
2366 goto err_batch_unpin;
2370 err = i915_gem_request_await_dma_fence(eb.request, in_fence);
2376 err = await_fence_array(&eb, fences);
2381 if (out_fence_fd != -1) {
2382 out_fence = sync_file_create(&eb.request->fence);
2390 * Whilst this request exists, batch_obj will be on the
2391 * active_list, and so will hold the active reference. Only when this
2392 * request is retired will the the batch_obj be moved onto the
2393 * inactive_list and lose its active reference. Hence we do not need
2394 * to explicitly hold another reference here.
2396 eb.request->batch = eb.batch;
2398 trace_i915_gem_request_queue(eb.request, eb.batch_flags);
2399 err = eb_submit(&eb);
2401 __i915_add_request(eb.request, err == 0);
2402 add_to_client(eb.request, file);
2405 signal_fence_array(&eb, fences);
2409 fd_install(out_fence_fd, out_fence->file);
2410 args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */
2411 args->rsvd2 |= (u64)out_fence_fd << 32;
2414 fput(out_fence->file);
2419 if (eb.batch_flags & I915_DISPATCH_SECURE)
2420 i915_vma_unpin(eb.batch);
2423 eb_release_vmas(&eb);
2424 mutex_unlock(&dev->struct_mutex);
2426 intel_runtime_pm_put(eb.i915);
2427 i915_gem_context_put(eb.ctx);
2431 if (out_fence_fd != -1)
2432 put_unused_fd(out_fence_fd);
2434 dma_fence_put(in_fence);
2439 * Legacy execbuffer just creates an exec2 list from the original exec object
2440 * list array and passes it to the real function.
2443 i915_gem_execbuffer(struct drm_device *dev, void *data,
2444 struct drm_file *file)
2446 const size_t sz = (sizeof(struct drm_i915_gem_exec_object2) +
2447 sizeof(struct i915_vma *) +
2448 sizeof(unsigned int));
2449 struct drm_i915_gem_execbuffer *args = data;
2450 struct drm_i915_gem_execbuffer2 exec2;
2451 struct drm_i915_gem_exec_object *exec_list = NULL;
2452 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
2456 if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) {
2457 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
2461 exec2.buffers_ptr = args->buffers_ptr;
2462 exec2.buffer_count = args->buffer_count;
2463 exec2.batch_start_offset = args->batch_start_offset;
2464 exec2.batch_len = args->batch_len;
2465 exec2.DR1 = args->DR1;
2466 exec2.DR4 = args->DR4;
2467 exec2.num_cliprects = args->num_cliprects;
2468 exec2.cliprects_ptr = args->cliprects_ptr;
2469 exec2.flags = I915_EXEC_RENDER;
2470 i915_execbuffer2_set_context_id(exec2, 0);
2472 if (!i915_gem_check_execbuffer(&exec2))
2475 /* Copy in the exec list from userland */
2476 exec_list = kvmalloc_array(args->buffer_count, sizeof(*exec_list),
2477 __GFP_NOWARN | GFP_KERNEL);
2478 exec2_list = kvmalloc_array(args->buffer_count + 1, sz,
2479 __GFP_NOWARN | GFP_KERNEL);
2480 if (exec_list == NULL || exec2_list == NULL) {
2481 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2482 args->buffer_count);
2487 err = copy_from_user(exec_list,
2488 u64_to_user_ptr(args->buffers_ptr),
2489 sizeof(*exec_list) * args->buffer_count);
2491 DRM_DEBUG("copy %d exec entries failed %d\n",
2492 args->buffer_count, err);
2498 for (i = 0; i < args->buffer_count; i++) {
2499 exec2_list[i].handle = exec_list[i].handle;
2500 exec2_list[i].relocation_count = exec_list[i].relocation_count;
2501 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
2502 exec2_list[i].alignment = exec_list[i].alignment;
2503 exec2_list[i].offset = exec_list[i].offset;
2504 if (INTEL_GEN(to_i915(dev)) < 4)
2505 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
2507 exec2_list[i].flags = 0;
2510 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL);
2511 if (exec2.flags & __EXEC_HAS_RELOC) {
2512 struct drm_i915_gem_exec_object __user *user_exec_list =
2513 u64_to_user_ptr(args->buffers_ptr);
2515 /* Copy the new buffer offsets back to the user's exec list. */
2516 for (i = 0; i < args->buffer_count; i++) {
2517 if (!(exec2_list[i].offset & UPDATE))
2520 exec2_list[i].offset =
2521 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2522 exec2_list[i].offset &= PIN_OFFSET_MASK;
2523 if (__copy_to_user(&user_exec_list[i].offset,
2524 &exec2_list[i].offset,
2525 sizeof(user_exec_list[i].offset)))
2536 i915_gem_execbuffer2(struct drm_device *dev, void *data,
2537 struct drm_file *file)
2539 const size_t sz = (sizeof(struct drm_i915_gem_exec_object2) +
2540 sizeof(struct i915_vma *) +
2541 sizeof(unsigned int));
2542 struct drm_i915_gem_execbuffer2 *args = data;
2543 struct drm_i915_gem_exec_object2 *exec2_list;
2544 struct drm_syncobj **fences = NULL;
2547 if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) {
2548 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
2552 if (!i915_gem_check_execbuffer(args))
2555 /* Allocate an extra slot for use by the command parser */
2556 exec2_list = kvmalloc_array(args->buffer_count + 1, sz,
2557 __GFP_NOWARN | GFP_KERNEL);
2558 if (exec2_list == NULL) {
2559 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2560 args->buffer_count);
2563 if (copy_from_user(exec2_list,
2564 u64_to_user_ptr(args->buffers_ptr),
2565 sizeof(*exec2_list) * args->buffer_count)) {
2566 DRM_DEBUG("copy %d exec entries failed\n", args->buffer_count);
2571 if (args->flags & I915_EXEC_FENCE_ARRAY) {
2572 fences = get_fence_array(args, file);
2573 if (IS_ERR(fences)) {
2575 return PTR_ERR(fences);
2579 err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences);
2582 * Now that we have begun execution of the batchbuffer, we ignore
2583 * any new error after this point. Also given that we have already
2584 * updated the associated relocations, we try to write out the current
2585 * object locations irrespective of any error.
2587 if (args->flags & __EXEC_HAS_RELOC) {
2588 struct drm_i915_gem_exec_object2 __user *user_exec_list =
2589 u64_to_user_ptr(args->buffers_ptr);
2592 /* Copy the new buffer offsets back to the user's exec list. */
2593 user_access_begin();
2594 for (i = 0; i < args->buffer_count; i++) {
2595 if (!(exec2_list[i].offset & UPDATE))
2598 exec2_list[i].offset =
2599 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2600 unsafe_put_user(exec2_list[i].offset,
2601 &user_exec_list[i].offset,
2608 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
2609 put_fence_array(args, fences);