2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
38 struct hlist_head buckets[0];
41 static struct eb_objects *
44 struct eb_objects *eb;
45 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
46 BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head)));
49 eb = kzalloc(count*sizeof(struct hlist_head) +
50 sizeof(struct eb_objects),
60 eb_reset(struct eb_objects *eb)
62 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
66 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
68 hlist_add_head(&obj->exec_node,
69 &eb->buckets[obj->exec_handle & eb->and]);
72 static struct drm_i915_gem_object *
73 eb_get_object(struct eb_objects *eb, unsigned long handle)
75 struct hlist_head *head;
76 struct hlist_node *node;
77 struct drm_i915_gem_object *obj;
79 head = &eb->buckets[handle & eb->and];
80 hlist_for_each(node, head) {
81 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
82 if (obj->exec_handle == handle)
90 eb_destroy(struct eb_objects *eb)
95 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
97 return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
98 !obj->map_and_fenceable ||
99 obj->cache_level != I915_CACHE_NONE);
103 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
104 struct eb_objects *eb,
105 struct drm_i915_gem_relocation_entry *reloc)
107 struct drm_device *dev = obj->base.dev;
108 struct drm_gem_object *target_obj;
109 struct drm_i915_gem_object *target_i915_obj;
110 uint32_t target_offset;
113 /* we've already hold a reference to all valid objects */
114 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
115 if (unlikely(target_obj == NULL))
118 target_i915_obj = to_intel_bo(target_obj);
119 target_offset = target_i915_obj->gtt_offset;
121 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
122 * pipe_control writes because the gpu doesn't properly redirect them
123 * through the ppgtt for non_secure batchbuffers. */
124 if (unlikely(IS_GEN6(dev) &&
125 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
126 !target_i915_obj->has_global_gtt_mapping)) {
127 i915_gem_gtt_bind_object(target_i915_obj,
128 target_i915_obj->cache_level);
131 /* Validate that the target is in a valid r/w GPU domain */
132 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
133 DRM_DEBUG("reloc with multiple write domains: "
134 "obj %p target %d offset %d "
135 "read %08x write %08x",
136 obj, reloc->target_handle,
139 reloc->write_domain);
142 if (unlikely((reloc->write_domain | reloc->read_domains)
143 & ~I915_GEM_GPU_DOMAINS)) {
144 DRM_DEBUG("reloc with read/write non-GPU domains: "
145 "obj %p target %d offset %d "
146 "read %08x write %08x",
147 obj, reloc->target_handle,
150 reloc->write_domain);
153 if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
154 reloc->write_domain != target_obj->pending_write_domain)) {
155 DRM_DEBUG("Write domain conflict: "
156 "obj %p target %d offset %d "
157 "new %08x old %08x\n",
158 obj, reloc->target_handle,
161 target_obj->pending_write_domain);
165 target_obj->pending_read_domains |= reloc->read_domains;
166 target_obj->pending_write_domain |= reloc->write_domain;
168 /* If the relocation already has the right value in it, no
169 * more work needs to be done.
171 if (target_offset == reloc->presumed_offset)
174 /* Check that the relocation address is valid... */
175 if (unlikely(reloc->offset > obj->base.size - 4)) {
176 DRM_DEBUG("Relocation beyond object bounds: "
177 "obj %p target %d offset %d size %d.\n",
178 obj, reloc->target_handle,
180 (int) obj->base.size);
183 if (unlikely(reloc->offset & 3)) {
184 DRM_DEBUG("Relocation not 4-byte aligned: "
185 "obj %p target %d offset %d.\n",
186 obj, reloc->target_handle,
187 (int) reloc->offset);
191 /* We can't wait for rendering with pagefaults disabled */
192 if (obj->active && in_atomic())
195 reloc->delta += target_offset;
196 if (use_cpu_reloc(obj)) {
197 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
200 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
204 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
205 reloc->offset >> PAGE_SHIFT));
206 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
207 kunmap_atomic(vaddr);
209 struct drm_i915_private *dev_priv = dev->dev_private;
210 uint32_t __iomem *reloc_entry;
211 void __iomem *reloc_page;
213 ret = i915_gem_object_set_to_gtt_domain(obj, true);
217 ret = i915_gem_object_put_fence(obj);
221 /* Map the page containing the relocation we're going to perform. */
222 reloc->offset += obj->gtt_offset;
223 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
224 reloc->offset & PAGE_MASK);
225 reloc_entry = (uint32_t __iomem *)
226 (reloc_page + (reloc->offset & ~PAGE_MASK));
227 iowrite32(reloc->delta, reloc_entry);
228 io_mapping_unmap_atomic(reloc_page);
231 /* and update the user's relocation entry */
232 reloc->presumed_offset = target_offset;
238 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
239 struct eb_objects *eb)
241 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
242 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
243 struct drm_i915_gem_relocation_entry __user *user_relocs;
244 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
247 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
249 remain = entry->relocation_count;
251 struct drm_i915_gem_relocation_entry *r = stack_reloc;
253 if (count > ARRAY_SIZE(stack_reloc))
254 count = ARRAY_SIZE(stack_reloc);
257 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
261 u64 offset = r->presumed_offset;
263 ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
267 if (r->presumed_offset != offset &&
268 __copy_to_user_inatomic(&user_relocs->presumed_offset,
270 sizeof(r->presumed_offset))) {
284 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
285 struct eb_objects *eb,
286 struct drm_i915_gem_relocation_entry *relocs)
288 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
291 for (i = 0; i < entry->relocation_count; i++) {
292 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
301 i915_gem_execbuffer_relocate(struct drm_device *dev,
302 struct eb_objects *eb,
303 struct list_head *objects)
305 struct drm_i915_gem_object *obj;
308 /* This is the fast path and we cannot handle a pagefault whilst
309 * holding the struct mutex lest the user pass in the relocations
310 * contained within a mmaped bo. For in such a case we, the page
311 * fault handler would call i915_gem_fault() and we would try to
312 * acquire the struct mutex again. Obviously this is bad and so
313 * lockdep complains vehemently.
316 list_for_each_entry(obj, objects, exec_list) {
317 ret = i915_gem_execbuffer_relocate_object(obj, eb);
326 #define __EXEC_OBJECT_HAS_PIN (1<<31)
327 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
330 need_reloc_mappable(struct drm_i915_gem_object *obj)
332 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
333 return entry->relocation_count && !use_cpu_reloc(obj);
337 i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
338 struct intel_ring_buffer *ring)
340 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
341 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
342 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
343 bool need_fence, need_mappable;
347 has_fenced_gpu_access &&
348 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
349 obj->tiling_mode != I915_TILING_NONE;
350 need_mappable = need_fence || need_reloc_mappable(obj);
352 ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false);
356 entry->flags |= __EXEC_OBJECT_HAS_PIN;
358 if (has_fenced_gpu_access) {
359 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
360 ret = i915_gem_object_get_fence(obj);
364 if (i915_gem_object_pin_fence(obj))
365 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
367 obj->pending_fenced_gpu_access = true;
371 /* Ensure ppgtt mapping exists if needed */
372 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
373 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
374 obj, obj->cache_level);
376 obj->has_aliasing_ppgtt_mapping = 1;
379 entry->offset = obj->gtt_offset;
384 i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj)
386 struct drm_i915_gem_exec_object2 *entry;
391 entry = obj->exec_entry;
393 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
394 i915_gem_object_unpin_fence(obj);
396 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
397 i915_gem_object_unpin(obj);
399 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
403 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
404 struct drm_file *file,
405 struct list_head *objects)
407 struct drm_i915_gem_object *obj;
408 struct list_head ordered_objects;
409 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
412 INIT_LIST_HEAD(&ordered_objects);
413 while (!list_empty(objects)) {
414 struct drm_i915_gem_exec_object2 *entry;
415 bool need_fence, need_mappable;
417 obj = list_first_entry(objects,
418 struct drm_i915_gem_object,
420 entry = obj->exec_entry;
423 has_fenced_gpu_access &&
424 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
425 obj->tiling_mode != I915_TILING_NONE;
426 need_mappable = need_fence || need_reloc_mappable(obj);
429 list_move(&obj->exec_list, &ordered_objects);
431 list_move_tail(&obj->exec_list, &ordered_objects);
433 obj->base.pending_read_domains = 0;
434 obj->base.pending_write_domain = 0;
435 obj->pending_fenced_gpu_access = false;
437 list_splice(&ordered_objects, objects);
439 /* Attempt to pin all of the buffers into the GTT.
440 * This is done in 3 phases:
442 * 1a. Unbind all objects that do not match the GTT constraints for
443 * the execbuffer (fenceable, mappable, alignment etc).
444 * 1b. Increment pin count for already bound objects.
445 * 2. Bind new objects.
446 * 3. Decrement pin count.
448 * This avoid unnecessary unbinding of later objects in order to make
449 * room for the earlier objects *unless* we need to defragment.
455 /* Unbind any ill-fitting objects or pin. */
456 list_for_each_entry(obj, objects, exec_list) {
457 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
458 bool need_fence, need_mappable;
464 has_fenced_gpu_access &&
465 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
466 obj->tiling_mode != I915_TILING_NONE;
467 need_mappable = need_fence || need_reloc_mappable(obj);
469 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
470 (need_mappable && !obj->map_and_fenceable))
471 ret = i915_gem_object_unbind(obj);
473 ret = i915_gem_execbuffer_reserve_object(obj, ring);
478 /* Bind fresh objects */
479 list_for_each_entry(obj, objects, exec_list) {
483 ret = i915_gem_execbuffer_reserve_object(obj, ring);
488 err: /* Decrement pin count for bound objects */
489 list_for_each_entry(obj, objects, exec_list)
490 i915_gem_execbuffer_unreserve_object(obj);
492 if (ret != -ENOSPC || retry++)
495 ret = i915_gem_evict_everything(ring->dev);
502 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
503 struct drm_file *file,
504 struct intel_ring_buffer *ring,
505 struct list_head *objects,
506 struct eb_objects *eb,
507 struct drm_i915_gem_exec_object2 *exec,
510 struct drm_i915_gem_relocation_entry *reloc;
511 struct drm_i915_gem_object *obj;
515 /* We may process another execbuffer during the unlock... */
516 while (!list_empty(objects)) {
517 obj = list_first_entry(objects,
518 struct drm_i915_gem_object,
520 list_del_init(&obj->exec_list);
521 drm_gem_object_unreference(&obj->base);
524 mutex_unlock(&dev->struct_mutex);
527 for (i = 0; i < count; i++)
528 total += exec[i].relocation_count;
530 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
531 reloc = drm_malloc_ab(total, sizeof(*reloc));
532 if (reloc == NULL || reloc_offset == NULL) {
533 drm_free_large(reloc);
534 drm_free_large(reloc_offset);
535 mutex_lock(&dev->struct_mutex);
540 for (i = 0; i < count; i++) {
541 struct drm_i915_gem_relocation_entry __user *user_relocs;
543 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
545 if (copy_from_user(reloc+total, user_relocs,
546 exec[i].relocation_count * sizeof(*reloc))) {
548 mutex_lock(&dev->struct_mutex);
552 reloc_offset[i] = total;
553 total += exec[i].relocation_count;
556 ret = i915_mutex_lock_interruptible(dev);
558 mutex_lock(&dev->struct_mutex);
562 /* reacquire the objects */
564 for (i = 0; i < count; i++) {
565 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
567 if (&obj->base == NULL) {
568 DRM_DEBUG("Invalid object handle %d at index %d\n",
574 list_add_tail(&obj->exec_list, objects);
575 obj->exec_handle = exec[i].handle;
576 obj->exec_entry = &exec[i];
577 eb_add_object(eb, obj);
580 ret = i915_gem_execbuffer_reserve(ring, file, objects);
584 list_for_each_entry(obj, objects, exec_list) {
585 int offset = obj->exec_entry - exec;
586 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
587 reloc + reloc_offset[offset]);
592 /* Leave the user relocations as are, this is the painfully slow path,
593 * and we want to avoid the complication of dropping the lock whilst
594 * having buffers reserved in the aperture and so causing spurious
595 * ENOSPC for random operations.
599 drm_free_large(reloc);
600 drm_free_large(reloc_offset);
605 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
607 u32 plane, flip_mask;
610 /* Check for any pending flips. As we only maintain a flip queue depth
611 * of 1, we can simply insert a WAIT for the next display flip prior
612 * to executing the batch and avoid stalling the CPU.
615 for (plane = 0; flips >> plane; plane++) {
616 if (((flips >> plane) & 1) == 0)
620 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
622 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
624 ret = intel_ring_begin(ring, 2);
628 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
629 intel_ring_emit(ring, MI_NOOP);
630 intel_ring_advance(ring);
637 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
638 struct list_head *objects)
640 struct drm_i915_gem_object *obj;
641 uint32_t flush_domains = 0;
645 list_for_each_entry(obj, objects, exec_list) {
646 ret = i915_gem_object_sync(obj, ring);
650 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
651 i915_gem_clflush_object(obj);
653 if (obj->base.pending_write_domain)
654 flips |= atomic_read(&obj->pending_flip);
656 flush_domains |= obj->base.write_domain;
660 ret = i915_gem_execbuffer_wait_for_flips(ring, flips);
665 if (flush_domains & I915_GEM_DOMAIN_CPU)
666 i915_gem_chipset_flush(ring->dev);
668 if (flush_domains & I915_GEM_DOMAIN_GTT)
671 /* Unconditionally invalidate gpu caches and ensure that we do flush
672 * any residual writes from the previous batch.
674 return intel_ring_invalidate_all_caches(ring);
678 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
680 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
684 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
689 for (i = 0; i < count; i++) {
690 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
691 int length; /* limited by fault_in_pages_readable() */
693 /* First check for malicious input causing overflow */
694 if (exec[i].relocation_count >
695 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
698 length = exec[i].relocation_count *
699 sizeof(struct drm_i915_gem_relocation_entry);
700 if (!access_ok(VERIFY_READ, ptr, length))
703 /* we may also need to update the presumed offsets */
704 if (!access_ok(VERIFY_WRITE, ptr, length))
707 if (fault_in_multipages_readable(ptr, length))
715 i915_gem_execbuffer_move_to_active(struct list_head *objects,
716 struct intel_ring_buffer *ring)
718 struct drm_i915_gem_object *obj;
720 list_for_each_entry(obj, objects, exec_list) {
721 u32 old_read = obj->base.read_domains;
722 u32 old_write = obj->base.write_domain;
724 obj->base.read_domains = obj->base.pending_read_domains;
725 obj->base.write_domain = obj->base.pending_write_domain;
726 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
728 i915_gem_object_move_to_active(obj, ring);
729 if (obj->base.write_domain) {
731 obj->last_write_seqno = intel_ring_get_seqno(ring);
732 if (obj->pin_count) /* check for potential scanout */
733 intel_mark_fb_busy(obj);
736 trace_i915_gem_object_change_domain(obj, old_read, old_write);
741 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
742 struct drm_file *file,
743 struct intel_ring_buffer *ring)
745 /* Unconditionally force add_request to emit a full flush. */
746 ring->gpu_caches_dirty = true;
748 /* Add a breadcrumb for the completion of the batch buffer */
749 (void)i915_add_request(ring, file, NULL);
753 i915_reset_gen7_sol_offsets(struct drm_device *dev,
754 struct intel_ring_buffer *ring)
756 drm_i915_private_t *dev_priv = dev->dev_private;
759 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
762 ret = intel_ring_begin(ring, 4 * 3);
766 for (i = 0; i < 4; i++) {
767 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
768 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
769 intel_ring_emit(ring, 0);
772 intel_ring_advance(ring);
778 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
779 struct drm_file *file,
780 struct drm_i915_gem_execbuffer2 *args,
781 struct drm_i915_gem_exec_object2 *exec)
783 drm_i915_private_t *dev_priv = dev->dev_private;
784 struct list_head objects;
785 struct eb_objects *eb;
786 struct drm_i915_gem_object *batch_obj;
787 struct drm_clip_rect *cliprects = NULL;
788 struct intel_ring_buffer *ring;
789 u32 ctx_id = i915_execbuffer2_get_context_id(*args);
790 u32 exec_start, exec_len;
795 if (!i915_gem_check_execbuffer(args)) {
796 DRM_DEBUG("execbuf with invalid offset/length\n");
800 ret = validate_exec_list(exec, args->buffer_count);
805 if (args->flags & I915_EXEC_SECURE) {
806 if (!file->is_master || !capable(CAP_SYS_ADMIN))
809 flags |= I915_DISPATCH_SECURE;
812 switch (args->flags & I915_EXEC_RING_MASK) {
813 case I915_EXEC_DEFAULT:
814 case I915_EXEC_RENDER:
815 ring = &dev_priv->ring[RCS];
818 ring = &dev_priv->ring[VCS];
820 DRM_DEBUG("Ring %s doesn't support contexts\n",
826 ring = &dev_priv->ring[BCS];
828 DRM_DEBUG("Ring %s doesn't support contexts\n",
834 DRM_DEBUG("execbuf with unknown ring: %d\n",
835 (int)(args->flags & I915_EXEC_RING_MASK));
838 if (!intel_ring_initialized(ring)) {
839 DRM_DEBUG("execbuf with invalid ring: %d\n",
840 (int)(args->flags & I915_EXEC_RING_MASK));
844 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
845 mask = I915_EXEC_CONSTANTS_MASK;
847 case I915_EXEC_CONSTANTS_REL_GENERAL:
848 case I915_EXEC_CONSTANTS_ABSOLUTE:
849 case I915_EXEC_CONSTANTS_REL_SURFACE:
850 if (ring == &dev_priv->ring[RCS] &&
851 mode != dev_priv->relative_constants_mode) {
852 if (INTEL_INFO(dev)->gen < 4)
855 if (INTEL_INFO(dev)->gen > 5 &&
856 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
859 /* The HW changed the meaning on this bit on gen6 */
860 if (INTEL_INFO(dev)->gen >= 6)
861 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
865 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
869 if (args->buffer_count < 1) {
870 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
874 if (args->num_cliprects != 0) {
875 if (ring != &dev_priv->ring[RCS]) {
876 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
880 if (INTEL_INFO(dev)->gen >= 5) {
881 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
885 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
886 DRM_DEBUG("execbuf with %u cliprects\n",
887 args->num_cliprects);
891 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
893 if (cliprects == NULL) {
898 if (copy_from_user(cliprects,
899 (struct drm_clip_rect __user *)(uintptr_t)
901 sizeof(*cliprects)*args->num_cliprects)) {
907 ret = i915_mutex_lock_interruptible(dev);
911 if (dev_priv->mm.suspended) {
912 mutex_unlock(&dev->struct_mutex);
917 eb = eb_create(args->buffer_count);
919 mutex_unlock(&dev->struct_mutex);
924 /* Look up object handles */
925 INIT_LIST_HEAD(&objects);
926 for (i = 0; i < args->buffer_count; i++) {
927 struct drm_i915_gem_object *obj;
929 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
931 if (&obj->base == NULL) {
932 DRM_DEBUG("Invalid object handle %d at index %d\n",
934 /* prevent error path from reading uninitialized data */
939 if (!list_empty(&obj->exec_list)) {
940 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
941 obj, exec[i].handle, i);
946 list_add_tail(&obj->exec_list, &objects);
947 obj->exec_handle = exec[i].handle;
948 obj->exec_entry = &exec[i];
949 eb_add_object(eb, obj);
952 /* take note of the batch buffer before we might reorder the lists */
953 batch_obj = list_entry(objects.prev,
954 struct drm_i915_gem_object,
957 /* Move the objects en-masse into the GTT, evicting if necessary. */
958 ret = i915_gem_execbuffer_reserve(ring, file, &objects);
962 /* The objects are in their final locations, apply the relocations. */
963 ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
965 if (ret == -EFAULT) {
966 ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
970 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
976 /* Set the pending read domains for the batch buffer to COMMAND */
977 if (batch_obj->base.pending_write_domain) {
978 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
982 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
984 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
985 * batch" bit. Hence we need to pin secure batches into the global gtt.
986 * hsw should have this fixed, but let's be paranoid and do it
987 * unconditionally for now. */
988 if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
989 i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
991 ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
995 ret = i915_switch_context(ring, file, ctx_id);
999 if (ring == &dev_priv->ring[RCS] &&
1000 mode != dev_priv->relative_constants_mode) {
1001 ret = intel_ring_begin(ring, 4);
1005 intel_ring_emit(ring, MI_NOOP);
1006 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1007 intel_ring_emit(ring, INSTPM);
1008 intel_ring_emit(ring, mask << 16 | mode);
1009 intel_ring_advance(ring);
1011 dev_priv->relative_constants_mode = mode;
1014 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1015 ret = i915_reset_gen7_sol_offsets(dev, ring);
1020 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1021 exec_len = args->batch_len;
1023 for (i = 0; i < args->num_cliprects; i++) {
1024 ret = i915_emit_box(dev, &cliprects[i],
1025 args->DR1, args->DR4);
1029 ret = ring->dispatch_execbuffer(ring,
1030 exec_start, exec_len,
1036 ret = ring->dispatch_execbuffer(ring,
1037 exec_start, exec_len,
1043 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
1045 i915_gem_execbuffer_move_to_active(&objects, ring);
1046 i915_gem_execbuffer_retire_commands(dev, file, ring);
1050 while (!list_empty(&objects)) {
1051 struct drm_i915_gem_object *obj;
1053 obj = list_first_entry(&objects,
1054 struct drm_i915_gem_object,
1056 list_del_init(&obj->exec_list);
1057 drm_gem_object_unreference(&obj->base);
1060 mutex_unlock(&dev->struct_mutex);
1068 * Legacy execbuffer just creates an exec2 list from the original exec object
1069 * list array and passes it to the real function.
1072 i915_gem_execbuffer(struct drm_device *dev, void *data,
1073 struct drm_file *file)
1075 struct drm_i915_gem_execbuffer *args = data;
1076 struct drm_i915_gem_execbuffer2 exec2;
1077 struct drm_i915_gem_exec_object *exec_list = NULL;
1078 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1081 if (args->buffer_count < 1) {
1082 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1086 /* Copy in the exec list from userland */
1087 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1088 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1089 if (exec_list == NULL || exec2_list == NULL) {
1090 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1091 args->buffer_count);
1092 drm_free_large(exec_list);
1093 drm_free_large(exec2_list);
1096 ret = copy_from_user(exec_list,
1097 (void __user *)(uintptr_t)args->buffers_ptr,
1098 sizeof(*exec_list) * args->buffer_count);
1100 DRM_DEBUG("copy %d exec entries failed %d\n",
1101 args->buffer_count, ret);
1102 drm_free_large(exec_list);
1103 drm_free_large(exec2_list);
1107 for (i = 0; i < args->buffer_count; i++) {
1108 exec2_list[i].handle = exec_list[i].handle;
1109 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1110 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1111 exec2_list[i].alignment = exec_list[i].alignment;
1112 exec2_list[i].offset = exec_list[i].offset;
1113 if (INTEL_INFO(dev)->gen < 4)
1114 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1116 exec2_list[i].flags = 0;
1119 exec2.buffers_ptr = args->buffers_ptr;
1120 exec2.buffer_count = args->buffer_count;
1121 exec2.batch_start_offset = args->batch_start_offset;
1122 exec2.batch_len = args->batch_len;
1123 exec2.DR1 = args->DR1;
1124 exec2.DR4 = args->DR4;
1125 exec2.num_cliprects = args->num_cliprects;
1126 exec2.cliprects_ptr = args->cliprects_ptr;
1127 exec2.flags = I915_EXEC_RENDER;
1128 i915_execbuffer2_set_context_id(exec2, 0);
1130 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1132 /* Copy the new buffer offsets back to the user's exec list. */
1133 for (i = 0; i < args->buffer_count; i++)
1134 exec_list[i].offset = exec2_list[i].offset;
1135 /* ... and back out to userspace */
1136 ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr,
1138 sizeof(*exec_list) * args->buffer_count);
1141 DRM_DEBUG("failed to copy %d exec entries "
1142 "back to user (%d)\n",
1143 args->buffer_count, ret);
1147 drm_free_large(exec_list);
1148 drm_free_large(exec2_list);
1153 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1154 struct drm_file *file)
1156 struct drm_i915_gem_execbuffer2 *args = data;
1157 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1160 if (args->buffer_count < 1 ||
1161 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1162 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1166 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1167 GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1168 if (exec2_list == NULL)
1169 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1170 args->buffer_count);
1171 if (exec2_list == NULL) {
1172 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1173 args->buffer_count);
1176 ret = copy_from_user(exec2_list,
1177 (struct drm_i915_relocation_entry __user *)
1178 (uintptr_t) args->buffers_ptr,
1179 sizeof(*exec2_list) * args->buffer_count);
1181 DRM_DEBUG("copy %d exec entries failed %d\n",
1182 args->buffer_count, ret);
1183 drm_free_large(exec2_list);
1187 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1189 /* Copy the new buffer offsets back to the user's exec list. */
1190 ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr,
1192 sizeof(*exec2_list) * args->buffer_count);
1195 DRM_DEBUG("failed to copy %d exec entries "
1196 "back to user (%d)\n",
1197 args->buffer_count, ret);
1201 drm_free_large(exec2_list);