2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct drm_device *dev)
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 struct completion *x = &dev_priv->error_completion;
97 if (!atomic_read(&dev_priv->mm.wedged))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret < 0) {
113 if (atomic_read(&dev_priv->mm.wedged)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x->wait.lock, flags);
121 spin_unlock_irqrestore(&x->wait.lock, flags);
126 int i915_mutex_lock_interruptible(struct drm_device *dev)
130 ret = i915_gem_wait_for_error(dev);
134 ret = mutex_lock_interruptible(&dev->struct_mutex);
138 WARN_ON(i915_verify_lists(dev));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
145 return obj->gtt_space && !obj->active;
149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
150 struct drm_file *file)
152 struct drm_i915_gem_init *args = data;
154 if (drm_core_check_feature(dev, DRIVER_MODESET))
157 if (args->gtt_start >= args->gtt_end ||
158 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev)->gen >= 5)
165 mutex_lock(&dev->struct_mutex);
166 i915_gem_init_global_gtt(dev, args->gtt_start,
167 args->gtt_end, args->gtt_end);
168 mutex_unlock(&dev->struct_mutex);
174 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
175 struct drm_file *file)
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 struct drm_i915_gem_get_aperture *args = data;
179 struct drm_i915_gem_object *obj;
183 mutex_lock(&dev->struct_mutex);
184 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
186 pinned += obj->gtt_space->size;
187 mutex_unlock(&dev->struct_mutex);
189 args->aper_size = dev_priv->mm.gtt_total;
190 args->aper_available_size = args->aper_size - pinned;
196 i915_gem_create(struct drm_file *file,
197 struct drm_device *dev,
201 struct drm_i915_gem_object *obj;
205 size = roundup(size, PAGE_SIZE);
209 /* Allocate the new object */
210 obj = i915_gem_alloc_object(dev, size);
214 ret = drm_gem_handle_create(file, &obj->base, &handle);
216 drm_gem_object_release(&obj->base);
217 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
222 /* drop reference from allocate - handle holds it now */
223 drm_gem_object_unreference(&obj->base);
224 trace_i915_gem_object_create(obj);
231 i915_gem_dumb_create(struct drm_file *file,
232 struct drm_device *dev,
233 struct drm_mode_create_dumb *args)
235 /* have to work out size/pitch and return them */
236 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
237 args->size = args->pitch * args->height;
238 return i915_gem_create(file, dev,
239 args->size, &args->handle);
242 int i915_gem_dumb_destroy(struct drm_file *file,
243 struct drm_device *dev,
246 return drm_gem_handle_delete(file, handle);
250 * Creates a new mm object and returns a handle to it.
253 i915_gem_create_ioctl(struct drm_device *dev, void *data,
254 struct drm_file *file)
256 struct drm_i915_gem_create *args = data;
258 return i915_gem_create(file, dev,
259 args->size, &args->handle);
262 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
264 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
266 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
267 obj->tiling_mode != I915_TILING_NONE;
271 __copy_to_user_swizzled(char __user *cpu_vaddr,
272 const char *gpu_vaddr, int gpu_offset,
275 int ret, cpu_offset = 0;
278 int cacheline_end = ALIGN(gpu_offset + 1, 64);
279 int this_length = min(cacheline_end - gpu_offset, length);
280 int swizzled_gpu_offset = gpu_offset ^ 64;
282 ret = __copy_to_user(cpu_vaddr + cpu_offset,
283 gpu_vaddr + swizzled_gpu_offset,
288 cpu_offset += this_length;
289 gpu_offset += this_length;
290 length -= this_length;
297 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
298 const char __user *cpu_vaddr,
301 int ret, cpu_offset = 0;
304 int cacheline_end = ALIGN(gpu_offset + 1, 64);
305 int this_length = min(cacheline_end - gpu_offset, length);
306 int swizzled_gpu_offset = gpu_offset ^ 64;
308 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
309 cpu_vaddr + cpu_offset,
314 cpu_offset += this_length;
315 gpu_offset += this_length;
316 length -= this_length;
322 /* Per-page copy function for the shmem pread fastpath.
323 * Flushes invalid cachelines before reading the target if
324 * needs_clflush is set. */
326 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
327 char __user *user_data,
328 bool page_do_bit17_swizzling, bool needs_clflush)
333 if (unlikely(page_do_bit17_swizzling))
336 vaddr = kmap_atomic(page);
338 drm_clflush_virt_range(vaddr + shmem_page_offset,
340 ret = __copy_to_user_inatomic(user_data,
341 vaddr + shmem_page_offset,
343 kunmap_atomic(vaddr);
345 return ret ? -EFAULT : 0;
349 shmem_clflush_swizzled_range(char *addr, unsigned long length,
352 if (unlikely(swizzled)) {
353 unsigned long start = (unsigned long) addr;
354 unsigned long end = (unsigned long) addr + length;
356 /* For swizzling simply ensure that we always flush both
357 * channels. Lame, but simple and it works. Swizzled
358 * pwrite/pread is far from a hotpath - current userspace
359 * doesn't use it at all. */
360 start = round_down(start, 128);
361 end = round_up(end, 128);
363 drm_clflush_virt_range((void *)start, end - start);
365 drm_clflush_virt_range(addr, length);
370 /* Only difference to the fast-path function is that this can handle bit17
371 * and uses non-atomic copy and kmap functions. */
373 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
374 char __user *user_data,
375 bool page_do_bit17_swizzling, bool needs_clflush)
382 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
384 page_do_bit17_swizzling);
386 if (page_do_bit17_swizzling)
387 ret = __copy_to_user_swizzled(user_data,
388 vaddr, shmem_page_offset,
391 ret = __copy_to_user(user_data,
392 vaddr + shmem_page_offset,
396 return ret ? - EFAULT : 0;
400 i915_gem_shmem_pread(struct drm_device *dev,
401 struct drm_i915_gem_object *obj,
402 struct drm_i915_gem_pread *args,
403 struct drm_file *file)
405 char __user *user_data;
408 int shmem_page_offset, page_length, ret = 0;
409 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
410 int hit_slowpath = 0;
412 int needs_clflush = 0;
413 struct scatterlist *sg;
416 user_data = (char __user *) (uintptr_t) args->data_ptr;
419 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
421 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
422 /* If we're not in the cpu read domain, set ourself into the gtt
423 * read domain and manually flush cachelines (if required). This
424 * optimizes for the case when the gpu will dirty the data
425 * anyway again before the next pread happens. */
426 if (obj->cache_level == I915_CACHE_NONE)
428 if (obj->gtt_space) {
429 ret = i915_gem_object_set_to_gtt_domain(obj, false);
435 ret = i915_gem_object_get_pages(obj);
439 i915_gem_object_pin_pages(obj);
441 offset = args->offset;
443 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
446 if (i < offset >> PAGE_SHIFT)
452 /* Operation in this page
454 * shmem_page_offset = offset within page in shmem file
455 * page_length = bytes to copy for this page
457 shmem_page_offset = offset_in_page(offset);
458 page_length = remain;
459 if ((shmem_page_offset + page_length) > PAGE_SIZE)
460 page_length = PAGE_SIZE - shmem_page_offset;
463 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
464 (page_to_phys(page) & (1 << 17)) != 0;
466 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
467 user_data, page_do_bit17_swizzling,
473 mutex_unlock(&dev->struct_mutex);
476 ret = fault_in_multipages_writeable(user_data, remain);
477 /* Userspace is tricking us, but we've already clobbered
478 * its pages with the prefault and promised to write the
479 * data up to the first fault. Hence ignore any errors
480 * and just continue. */
485 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
486 user_data, page_do_bit17_swizzling,
489 mutex_lock(&dev->struct_mutex);
492 mark_page_accessed(page);
497 remain -= page_length;
498 user_data += page_length;
499 offset += page_length;
503 i915_gem_object_unpin_pages(obj);
506 /* Fixup: Kill any reinstated backing storage pages */
507 if (obj->madv == __I915_MADV_PURGED)
508 i915_gem_object_truncate(obj);
515 * Reads data from the object referenced by handle.
517 * On error, the contents of *data are undefined.
520 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
521 struct drm_file *file)
523 struct drm_i915_gem_pread *args = data;
524 struct drm_i915_gem_object *obj;
530 if (!access_ok(VERIFY_WRITE,
531 (char __user *)(uintptr_t)args->data_ptr,
535 ret = i915_mutex_lock_interruptible(dev);
539 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
540 if (&obj->base == NULL) {
545 /* Bounds check source. */
546 if (args->offset > obj->base.size ||
547 args->size > obj->base.size - args->offset) {
552 /* prime objects have no backing filp to GEM pread/pwrite
555 if (!obj->base.filp) {
560 trace_i915_gem_object_pread(obj, args->offset, args->size);
562 ret = i915_gem_shmem_pread(dev, obj, args, file);
565 drm_gem_object_unreference(&obj->base);
567 mutex_unlock(&dev->struct_mutex);
571 /* This is the fast write path which cannot handle
572 * page faults in the source data
576 fast_user_write(struct io_mapping *mapping,
577 loff_t page_base, int page_offset,
578 char __user *user_data,
581 void __iomem *vaddr_atomic;
583 unsigned long unwritten;
585 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
586 /* We can use the cpu mem copy function because this is X86. */
587 vaddr = (void __force*)vaddr_atomic + page_offset;
588 unwritten = __copy_from_user_inatomic_nocache(vaddr,
590 io_mapping_unmap_atomic(vaddr_atomic);
595 * This is the fast pwrite path, where we copy the data directly from the
596 * user into the GTT, uncached.
599 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
600 struct drm_i915_gem_object *obj,
601 struct drm_i915_gem_pwrite *args,
602 struct drm_file *file)
604 drm_i915_private_t *dev_priv = dev->dev_private;
606 loff_t offset, page_base;
607 char __user *user_data;
608 int page_offset, page_length, ret;
610 ret = i915_gem_object_pin(obj, 0, true, true);
614 ret = i915_gem_object_set_to_gtt_domain(obj, true);
618 ret = i915_gem_object_put_fence(obj);
622 user_data = (char __user *) (uintptr_t) args->data_ptr;
625 offset = obj->gtt_offset + args->offset;
628 /* Operation in this page
630 * page_base = page offset within aperture
631 * page_offset = offset within page
632 * page_length = bytes to copy for this page
634 page_base = offset & PAGE_MASK;
635 page_offset = offset_in_page(offset);
636 page_length = remain;
637 if ((page_offset + remain) > PAGE_SIZE)
638 page_length = PAGE_SIZE - page_offset;
640 /* If we get a fault while copying data, then (presumably) our
641 * source page isn't available. Return the error and we'll
642 * retry in the slow path.
644 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
645 page_offset, user_data, page_length)) {
650 remain -= page_length;
651 user_data += page_length;
652 offset += page_length;
656 i915_gem_object_unpin(obj);
661 /* Per-page copy function for the shmem pwrite fastpath.
662 * Flushes invalid cachelines before writing to the target if
663 * needs_clflush_before is set and flushes out any written cachelines after
664 * writing if needs_clflush is set. */
666 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
667 char __user *user_data,
668 bool page_do_bit17_swizzling,
669 bool needs_clflush_before,
670 bool needs_clflush_after)
675 if (unlikely(page_do_bit17_swizzling))
678 vaddr = kmap_atomic(page);
679 if (needs_clflush_before)
680 drm_clflush_virt_range(vaddr + shmem_page_offset,
682 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
685 if (needs_clflush_after)
686 drm_clflush_virt_range(vaddr + shmem_page_offset,
688 kunmap_atomic(vaddr);
690 return ret ? -EFAULT : 0;
693 /* Only difference to the fast-path function is that this can handle bit17
694 * and uses non-atomic copy and kmap functions. */
696 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
697 char __user *user_data,
698 bool page_do_bit17_swizzling,
699 bool needs_clflush_before,
700 bool needs_clflush_after)
706 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
707 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
709 page_do_bit17_swizzling);
710 if (page_do_bit17_swizzling)
711 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
715 ret = __copy_from_user(vaddr + shmem_page_offset,
718 if (needs_clflush_after)
719 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
721 page_do_bit17_swizzling);
724 return ret ? -EFAULT : 0;
728 i915_gem_shmem_pwrite(struct drm_device *dev,
729 struct drm_i915_gem_object *obj,
730 struct drm_i915_gem_pwrite *args,
731 struct drm_file *file)
735 char __user *user_data;
736 int shmem_page_offset, page_length, ret = 0;
737 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
738 int hit_slowpath = 0;
739 int needs_clflush_after = 0;
740 int needs_clflush_before = 0;
742 struct scatterlist *sg;
744 user_data = (char __user *) (uintptr_t) args->data_ptr;
747 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
749 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
750 /* If we're not in the cpu write domain, set ourself into the gtt
751 * write domain and manually flush cachelines (if required). This
752 * optimizes for the case when the gpu will use the data
753 * right away and we therefore have to clflush anyway. */
754 if (obj->cache_level == I915_CACHE_NONE)
755 needs_clflush_after = 1;
756 if (obj->gtt_space) {
757 ret = i915_gem_object_set_to_gtt_domain(obj, true);
762 /* Same trick applies for invalidate partially written cachelines before
764 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
765 && obj->cache_level == I915_CACHE_NONE)
766 needs_clflush_before = 1;
768 ret = i915_gem_object_get_pages(obj);
772 i915_gem_object_pin_pages(obj);
774 offset = args->offset;
777 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
779 int partial_cacheline_write;
781 if (i < offset >> PAGE_SHIFT)
787 /* Operation in this page
789 * shmem_page_offset = offset within page in shmem file
790 * page_length = bytes to copy for this page
792 shmem_page_offset = offset_in_page(offset);
794 page_length = remain;
795 if ((shmem_page_offset + page_length) > PAGE_SIZE)
796 page_length = PAGE_SIZE - shmem_page_offset;
798 /* If we don't overwrite a cacheline completely we need to be
799 * careful to have up-to-date data by first clflushing. Don't
800 * overcomplicate things and flush the entire patch. */
801 partial_cacheline_write = needs_clflush_before &&
802 ((shmem_page_offset | page_length)
803 & (boot_cpu_data.x86_clflush_size - 1));
806 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
807 (page_to_phys(page) & (1 << 17)) != 0;
809 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
810 user_data, page_do_bit17_swizzling,
811 partial_cacheline_write,
812 needs_clflush_after);
817 mutex_unlock(&dev->struct_mutex);
818 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
819 user_data, page_do_bit17_swizzling,
820 partial_cacheline_write,
821 needs_clflush_after);
823 mutex_lock(&dev->struct_mutex);
826 set_page_dirty(page);
827 mark_page_accessed(page);
832 remain -= page_length;
833 user_data += page_length;
834 offset += page_length;
838 i915_gem_object_unpin_pages(obj);
841 /* Fixup: Kill any reinstated backing storage pages */
842 if (obj->madv == __I915_MADV_PURGED)
843 i915_gem_object_truncate(obj);
844 /* and flush dirty cachelines in case the object isn't in the cpu write
846 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
847 i915_gem_clflush_object(obj);
848 i915_gem_chipset_flush(dev);
852 if (needs_clflush_after)
853 i915_gem_chipset_flush(dev);
859 * Writes data to the object referenced by handle.
861 * On error, the contents of the buffer that were to be modified are undefined.
864 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
865 struct drm_file *file)
867 struct drm_i915_gem_pwrite *args = data;
868 struct drm_i915_gem_object *obj;
874 if (!access_ok(VERIFY_READ,
875 (char __user *)(uintptr_t)args->data_ptr,
879 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
884 ret = i915_mutex_lock_interruptible(dev);
888 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
889 if (&obj->base == NULL) {
894 /* Bounds check destination. */
895 if (args->offset > obj->base.size ||
896 args->size > obj->base.size - args->offset) {
901 /* prime objects have no backing filp to GEM pread/pwrite
904 if (!obj->base.filp) {
909 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
912 /* We can only do the GTT pwrite on untiled buffers, as otherwise
913 * it would end up going through the fenced access, and we'll get
914 * different detiling behavior between reading and writing.
915 * pread/pwrite currently are reading and writing from the CPU
916 * perspective, requiring manual detiling by the client.
919 ret = i915_gem_phys_pwrite(dev, obj, args, file);
923 if (obj->cache_level == I915_CACHE_NONE &&
924 obj->tiling_mode == I915_TILING_NONE &&
925 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
926 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
927 /* Note that the gtt paths might fail with non-page-backed user
928 * pointers (e.g. gtt mappings when moving data between
929 * textures). Fallback to the shmem path in that case. */
932 if (ret == -EFAULT || ret == -ENOSPC)
933 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
936 drm_gem_object_unreference(&obj->base);
938 mutex_unlock(&dev->struct_mutex);
943 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
946 if (atomic_read(&dev_priv->mm.wedged)) {
947 struct completion *x = &dev_priv->error_completion;
948 bool recovery_complete;
951 /* Give the error handler a chance to run. */
952 spin_lock_irqsave(&x->wait.lock, flags);
953 recovery_complete = x->done > 0;
954 spin_unlock_irqrestore(&x->wait.lock, flags);
956 /* Non-interruptible callers can't handle -EAGAIN, hence return
957 * -EIO unconditionally for these. */
961 /* Recovery complete, but still wedged means reset failure. */
962 if (recovery_complete)
972 * Compare seqno against outstanding lazy request. Emit a request if they are
976 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
980 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
983 if (seqno == ring->outstanding_lazy_request)
984 ret = i915_add_request(ring, NULL, NULL);
990 * __wait_seqno - wait until execution of seqno has finished
991 * @ring: the ring expected to report seqno
993 * @interruptible: do an interruptible wait (normally yes)
994 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
996 * Returns 0 if the seqno was found within the alloted time. Else returns the
997 * errno with remaining time filled in timeout argument.
999 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1000 bool interruptible, struct timespec *timeout)
1002 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1003 struct timespec before, now, wait_time={1,0};
1004 unsigned long timeout_jiffies;
1006 bool wait_forever = true;
1009 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1012 trace_i915_gem_request_wait_begin(ring, seqno);
1014 if (timeout != NULL) {
1015 wait_time = *timeout;
1016 wait_forever = false;
1019 timeout_jiffies = timespec_to_jiffies(&wait_time);
1021 if (WARN_ON(!ring->irq_get(ring)))
1024 /* Record current time in case interrupted by signal, or wedged * */
1025 getrawmonotonic(&before);
1028 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1029 atomic_read(&dev_priv->mm.wedged))
1032 end = wait_event_interruptible_timeout(ring->irq_queue,
1036 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1039 ret = i915_gem_check_wedge(dev_priv, interruptible);
1042 } while (end == 0 && wait_forever);
1044 getrawmonotonic(&now);
1046 ring->irq_put(ring);
1047 trace_i915_gem_request_wait_end(ring, seqno);
1051 struct timespec sleep_time = timespec_sub(now, before);
1052 *timeout = timespec_sub(*timeout, sleep_time);
1057 case -EAGAIN: /* Wedged */
1058 case -ERESTARTSYS: /* Signal */
1060 case 0: /* Timeout */
1062 set_normalized_timespec(timeout, 0, 0);
1064 default: /* Completed */
1065 WARN_ON(end < 0); /* We're not aware of other errors */
1071 * Waits for a sequence number to be signaled, and cleans up the
1072 * request and object lists appropriately for that event.
1075 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1077 struct drm_device *dev = ring->dev;
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1079 bool interruptible = dev_priv->mm.interruptible;
1082 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1085 ret = i915_gem_check_wedge(dev_priv, interruptible);
1089 ret = i915_gem_check_olr(ring, seqno);
1093 return __wait_seqno(ring, seqno, interruptible, NULL);
1097 * Ensures that all rendering to the object has completed and the object is
1098 * safe to unbind from the GTT or access from the CPU.
1100 static __must_check int
1101 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1104 struct intel_ring_buffer *ring = obj->ring;
1108 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1112 ret = i915_wait_seqno(ring, seqno);
1116 i915_gem_retire_requests_ring(ring);
1118 /* Manually manage the write flush as we may have not yet
1119 * retired the buffer.
1121 if (obj->last_write_seqno &&
1122 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1123 obj->last_write_seqno = 0;
1124 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1130 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1131 * as the object state may change during this call.
1133 static __must_check int
1134 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1137 struct drm_device *dev = obj->base.dev;
1138 struct drm_i915_private *dev_priv = dev->dev_private;
1139 struct intel_ring_buffer *ring = obj->ring;
1143 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1144 BUG_ON(!dev_priv->mm.interruptible);
1146 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1150 ret = i915_gem_check_wedge(dev_priv, true);
1154 ret = i915_gem_check_olr(ring, seqno);
1158 mutex_unlock(&dev->struct_mutex);
1159 ret = __wait_seqno(ring, seqno, true, NULL);
1160 mutex_lock(&dev->struct_mutex);
1162 i915_gem_retire_requests_ring(ring);
1164 /* Manually manage the write flush as we may have not yet
1165 * retired the buffer.
1167 if (obj->last_write_seqno &&
1168 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1169 obj->last_write_seqno = 0;
1170 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1177 * Called when user space prepares to use an object with the CPU, either
1178 * through the mmap ioctl's mapping or a GTT mapping.
1181 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1182 struct drm_file *file)
1184 struct drm_i915_gem_set_domain *args = data;
1185 struct drm_i915_gem_object *obj;
1186 uint32_t read_domains = args->read_domains;
1187 uint32_t write_domain = args->write_domain;
1190 /* Only handle setting domains to types used by the CPU. */
1191 if (write_domain & I915_GEM_GPU_DOMAINS)
1194 if (read_domains & I915_GEM_GPU_DOMAINS)
1197 /* Having something in the write domain implies it's in the read
1198 * domain, and only that read domain. Enforce that in the request.
1200 if (write_domain != 0 && read_domains != write_domain)
1203 ret = i915_mutex_lock_interruptible(dev);
1207 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1208 if (&obj->base == NULL) {
1213 /* Try to flush the object off the GPU without holding the lock.
1214 * We will repeat the flush holding the lock in the normal manner
1215 * to catch cases where we are gazumped.
1217 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1221 if (read_domains & I915_GEM_DOMAIN_GTT) {
1222 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1224 /* Silently promote "you're not bound, there was nothing to do"
1225 * to success, since the client was just asking us to
1226 * make sure everything was done.
1231 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1235 drm_gem_object_unreference(&obj->base);
1237 mutex_unlock(&dev->struct_mutex);
1242 * Called when user space has done writes to this buffer
1245 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1246 struct drm_file *file)
1248 struct drm_i915_gem_sw_finish *args = data;
1249 struct drm_i915_gem_object *obj;
1252 ret = i915_mutex_lock_interruptible(dev);
1256 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1257 if (&obj->base == NULL) {
1262 /* Pinned buffers may be scanout, so flush the cache */
1264 i915_gem_object_flush_cpu_write_domain(obj);
1266 drm_gem_object_unreference(&obj->base);
1268 mutex_unlock(&dev->struct_mutex);
1273 * Maps the contents of an object, returning the address it is mapped
1276 * While the mapping holds a reference on the contents of the object, it doesn't
1277 * imply a ref on the object itself.
1280 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1281 struct drm_file *file)
1283 struct drm_i915_gem_mmap *args = data;
1284 struct drm_gem_object *obj;
1287 obj = drm_gem_object_lookup(dev, file, args->handle);
1291 /* prime objects have no backing filp to GEM mmap
1295 drm_gem_object_unreference_unlocked(obj);
1299 addr = vm_mmap(obj->filp, 0, args->size,
1300 PROT_READ | PROT_WRITE, MAP_SHARED,
1302 drm_gem_object_unreference_unlocked(obj);
1303 if (IS_ERR((void *)addr))
1306 args->addr_ptr = (uint64_t) addr;
1312 * i915_gem_fault - fault a page into the GTT
1313 * vma: VMA in question
1316 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1317 * from userspace. The fault handler takes care of binding the object to
1318 * the GTT (if needed), allocating and programming a fence register (again,
1319 * only if needed based on whether the old reg is still valid or the object
1320 * is tiled) and inserting a new PTE into the faulting process.
1322 * Note that the faulting process may involve evicting existing objects
1323 * from the GTT and/or fence registers to make room. So performance may
1324 * suffer if the GTT working set is large or there are few fence registers
1327 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1329 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1330 struct drm_device *dev = obj->base.dev;
1331 drm_i915_private_t *dev_priv = dev->dev_private;
1332 pgoff_t page_offset;
1335 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1337 /* We don't use vmf->pgoff since that has the fake offset */
1338 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1341 ret = i915_mutex_lock_interruptible(dev);
1345 trace_i915_gem_object_fault(obj, page_offset, true, write);
1347 /* Now bind it into the GTT if needed */
1348 ret = i915_gem_object_pin(obj, 0, true, false);
1352 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1356 ret = i915_gem_object_get_fence(obj);
1360 obj->fault_mappable = true;
1362 pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1365 /* Finally, remap it using the new GTT offset */
1366 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1368 i915_gem_object_unpin(obj);
1370 mutex_unlock(&dev->struct_mutex);
1374 /* If this -EIO is due to a gpu hang, give the reset code a
1375 * chance to clean up the mess. Otherwise return the proper
1377 if (!atomic_read(&dev_priv->mm.wedged))
1378 return VM_FAULT_SIGBUS;
1380 /* Give the error handler a chance to run and move the
1381 * objects off the GPU active list. Next time we service the
1382 * fault, we should be able to transition the page into the
1383 * GTT without touching the GPU (and so avoid further
1384 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1385 * with coherency, just lost writes.
1393 * EBUSY is ok: this just means that another thread
1394 * already did the job.
1396 return VM_FAULT_NOPAGE;
1398 return VM_FAULT_OOM;
1400 return VM_FAULT_SIGBUS;
1402 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1403 return VM_FAULT_SIGBUS;
1408 * i915_gem_release_mmap - remove physical page mappings
1409 * @obj: obj in question
1411 * Preserve the reservation of the mmapping with the DRM core code, but
1412 * relinquish ownership of the pages back to the system.
1414 * It is vital that we remove the page mapping if we have mapped a tiled
1415 * object through the GTT and then lose the fence register due to
1416 * resource pressure. Similarly if the object has been moved out of the
1417 * aperture, than pages mapped into userspace must be revoked. Removing the
1418 * mapping will then trigger a page fault on the next user access, allowing
1419 * fixup by i915_gem_fault().
1422 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1424 if (!obj->fault_mappable)
1427 if (obj->base.dev->dev_mapping)
1428 unmap_mapping_range(obj->base.dev->dev_mapping,
1429 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1432 obj->fault_mappable = false;
1436 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1440 if (INTEL_INFO(dev)->gen >= 4 ||
1441 tiling_mode == I915_TILING_NONE)
1444 /* Previous chips need a power-of-two fence region when tiling */
1445 if (INTEL_INFO(dev)->gen == 3)
1446 gtt_size = 1024*1024;
1448 gtt_size = 512*1024;
1450 while (gtt_size < size)
1457 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1458 * @obj: object to check
1460 * Return the required GTT alignment for an object, taking into account
1461 * potential fence register mapping.
1464 i915_gem_get_gtt_alignment(struct drm_device *dev,
1469 * Minimum alignment is 4k (GTT page size), but might be greater
1470 * if a fence register is needed for the object.
1472 if (INTEL_INFO(dev)->gen >= 4 ||
1473 tiling_mode == I915_TILING_NONE)
1477 * Previous chips need to be aligned to the size of the smallest
1478 * fence register that can contain the object.
1480 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1484 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1487 * @size: size of the object
1488 * @tiling_mode: tiling mode of the object
1490 * Return the required GTT alignment for an object, only taking into account
1491 * unfenced tiled surface requirements.
1494 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1499 * Minimum alignment is 4k (GTT page size) for sane hw.
1501 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1502 tiling_mode == I915_TILING_NONE)
1505 /* Previous hardware however needs to be aligned to a power-of-two
1506 * tile height. The simplest method for determining this is to reuse
1507 * the power-of-tile object size.
1509 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1512 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1514 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1517 if (obj->base.map_list.map)
1520 ret = drm_gem_create_mmap_offset(&obj->base);
1524 /* Badly fragmented mmap space? The only way we can recover
1525 * space is by destroying unwanted objects. We can't randomly release
1526 * mmap_offsets as userspace expects them to be persistent for the
1527 * lifetime of the objects. The closest we can is to release the
1528 * offsets on purgeable objects by truncating it and marking it purged,
1529 * which prevents userspace from ever using that object again.
1531 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1532 ret = drm_gem_create_mmap_offset(&obj->base);
1536 i915_gem_shrink_all(dev_priv);
1537 return drm_gem_create_mmap_offset(&obj->base);
1540 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1542 if (!obj->base.map_list.map)
1545 drm_gem_free_mmap_offset(&obj->base);
1549 i915_gem_mmap_gtt(struct drm_file *file,
1550 struct drm_device *dev,
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_i915_gem_object *obj;
1558 ret = i915_mutex_lock_interruptible(dev);
1562 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1563 if (&obj->base == NULL) {
1568 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1573 if (obj->madv != I915_MADV_WILLNEED) {
1574 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1579 ret = i915_gem_object_create_mmap_offset(obj);
1583 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1586 drm_gem_object_unreference(&obj->base);
1588 mutex_unlock(&dev->struct_mutex);
1593 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1595 * @data: GTT mapping ioctl data
1596 * @file: GEM object info
1598 * Simply returns the fake offset to userspace so it can mmap it.
1599 * The mmap call will end up in drm_gem_mmap(), which will set things
1600 * up so we can get faults in the handler above.
1602 * The fault handler will take care of binding the object into the GTT
1603 * (since it may have been evicted to make room for something), allocating
1604 * a fence register, and mapping the appropriate aperture address into
1608 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1609 struct drm_file *file)
1611 struct drm_i915_gem_mmap_gtt *args = data;
1613 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1616 /* Immediately discard the backing storage */
1618 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1620 struct inode *inode;
1622 i915_gem_object_free_mmap_offset(obj);
1624 if (obj->base.filp == NULL)
1627 /* Our goal here is to return as much of the memory as
1628 * is possible back to the system as we are called from OOM.
1629 * To do this we must instruct the shmfs to drop all of its
1630 * backing pages, *now*.
1632 inode = obj->base.filp->f_path.dentry->d_inode;
1633 shmem_truncate_range(inode, 0, (loff_t)-1);
1635 obj->madv = __I915_MADV_PURGED;
1639 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1641 return obj->madv == I915_MADV_DONTNEED;
1645 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1647 int page_count = obj->base.size / PAGE_SIZE;
1648 struct scatterlist *sg;
1651 BUG_ON(obj->madv == __I915_MADV_PURGED);
1653 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1655 /* In the event of a disaster, abandon all caches and
1656 * hope for the best.
1658 WARN_ON(ret != -EIO);
1659 i915_gem_clflush_object(obj);
1660 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1663 if (i915_gem_object_needs_bit17_swizzle(obj))
1664 i915_gem_object_save_bit_17_swizzle(obj);
1666 if (obj->madv == I915_MADV_DONTNEED)
1669 for_each_sg(obj->pages->sgl, sg, page_count, i) {
1670 struct page *page = sg_page(sg);
1673 set_page_dirty(page);
1675 if (obj->madv == I915_MADV_WILLNEED)
1676 mark_page_accessed(page);
1678 page_cache_release(page);
1682 sg_free_table(obj->pages);
1687 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1689 const struct drm_i915_gem_object_ops *ops = obj->ops;
1691 if (obj->pages == NULL)
1694 BUG_ON(obj->gtt_space);
1696 if (obj->pages_pin_count)
1699 ops->put_pages(obj);
1702 list_del(&obj->gtt_list);
1703 if (i915_gem_object_is_purgeable(obj))
1704 i915_gem_object_truncate(obj);
1710 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1712 struct drm_i915_gem_object *obj, *next;
1715 list_for_each_entry_safe(obj, next,
1716 &dev_priv->mm.unbound_list,
1718 if (i915_gem_object_is_purgeable(obj) &&
1719 i915_gem_object_put_pages(obj) == 0) {
1720 count += obj->base.size >> PAGE_SHIFT;
1721 if (count >= target)
1726 list_for_each_entry_safe(obj, next,
1727 &dev_priv->mm.inactive_list,
1729 if (i915_gem_object_is_purgeable(obj) &&
1730 i915_gem_object_unbind(obj) == 0 &&
1731 i915_gem_object_put_pages(obj) == 0) {
1732 count += obj->base.size >> PAGE_SHIFT;
1733 if (count >= target)
1742 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1744 struct drm_i915_gem_object *obj, *next;
1746 i915_gem_evict_everything(dev_priv->dev);
1748 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1749 i915_gem_object_put_pages(obj);
1753 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1755 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1757 struct address_space *mapping;
1758 struct sg_table *st;
1759 struct scatterlist *sg;
1763 /* Assert that the object is not currently in any GPU domain. As it
1764 * wasn't in the GTT, there shouldn't be any way it could have been in
1767 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1768 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1770 st = kmalloc(sizeof(*st), GFP_KERNEL);
1774 page_count = obj->base.size / PAGE_SIZE;
1775 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1781 /* Get the list of pages out of our struct file. They'll be pinned
1782 * at this point until we release them.
1784 * Fail silently without starting the shrinker
1786 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1787 gfp = mapping_gfp_mask(mapping);
1788 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1789 gfp &= ~(__GFP_IO | __GFP_WAIT);
1790 for_each_sg(st->sgl, sg, page_count, i) {
1791 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1793 i915_gem_purge(dev_priv, page_count);
1794 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1797 /* We've tried hard to allocate the memory by reaping
1798 * our own buffer, now let the real VM do its job and
1799 * go down in flames if truly OOM.
1801 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
1802 gfp |= __GFP_IO | __GFP_WAIT;
1804 i915_gem_shrink_all(dev_priv);
1805 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1809 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1810 gfp &= ~(__GFP_IO | __GFP_WAIT);
1813 sg_set_page(sg, page, PAGE_SIZE, 0);
1818 if (i915_gem_object_needs_bit17_swizzle(obj))
1819 i915_gem_object_do_bit_17_swizzle(obj);
1824 for_each_sg(st->sgl, sg, i, page_count)
1825 page_cache_release(sg_page(sg));
1828 return PTR_ERR(page);
1831 /* Ensure that the associated pages are gathered from the backing storage
1832 * and pinned into our object. i915_gem_object_get_pages() may be called
1833 * multiple times before they are released by a single call to
1834 * i915_gem_object_put_pages() - once the pages are no longer referenced
1835 * either as a result of memory pressure (reaping pages under the shrinker)
1836 * or as the object is itself released.
1839 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1841 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1842 const struct drm_i915_gem_object_ops *ops = obj->ops;
1848 BUG_ON(obj->pages_pin_count);
1850 ret = ops->get_pages(obj);
1854 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1859 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1860 struct intel_ring_buffer *ring)
1862 struct drm_device *dev = obj->base.dev;
1863 struct drm_i915_private *dev_priv = dev->dev_private;
1864 u32 seqno = intel_ring_get_seqno(ring);
1866 BUG_ON(ring == NULL);
1869 /* Add a reference if we're newly entering the active list. */
1871 drm_gem_object_reference(&obj->base);
1875 /* Move from whatever list we were on to the tail of execution. */
1876 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1877 list_move_tail(&obj->ring_list, &ring->active_list);
1879 obj->last_read_seqno = seqno;
1881 if (obj->fenced_gpu_access) {
1882 obj->last_fenced_seqno = seqno;
1884 /* Bump MRU to take account of the delayed flush */
1885 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1886 struct drm_i915_fence_reg *reg;
1888 reg = &dev_priv->fence_regs[obj->fence_reg];
1889 list_move_tail(®->lru_list,
1890 &dev_priv->mm.fence_list);
1896 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1898 struct drm_device *dev = obj->base.dev;
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1901 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1902 BUG_ON(!obj->active);
1904 if (obj->pin_count) /* are we a framebuffer? */
1905 intel_mark_fb_idle(obj);
1907 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1909 list_del_init(&obj->ring_list);
1912 obj->last_read_seqno = 0;
1913 obj->last_write_seqno = 0;
1914 obj->base.write_domain = 0;
1916 obj->last_fenced_seqno = 0;
1917 obj->fenced_gpu_access = false;
1920 drm_gem_object_unreference(&obj->base);
1922 WARN_ON(i915_verify_lists(dev));
1926 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1928 struct drm_i915_private *dev_priv = dev->dev_private;
1929 struct intel_ring_buffer *ring;
1932 /* The hardware uses various monotonic 32-bit counters, if we
1933 * detect that they will wraparound we need to idle the GPU
1934 * and reset those counters.
1937 for_each_ring(ring, dev_priv, i) {
1938 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1939 ret |= ring->sync_seqno[j] != 0;
1944 ret = i915_gpu_idle(dev);
1948 i915_gem_retire_requests(dev);
1949 for_each_ring(ring, dev_priv, i) {
1950 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1951 ring->sync_seqno[j] = 0;
1958 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1962 /* reserve 0 for non-seqno */
1963 if (dev_priv->next_seqno == 0) {
1964 int ret = i915_gem_handle_seqno_wrap(dev);
1968 dev_priv->next_seqno = 1;
1971 *seqno = dev_priv->next_seqno++;
1976 i915_add_request(struct intel_ring_buffer *ring,
1977 struct drm_file *file,
1980 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1981 struct drm_i915_gem_request *request;
1982 u32 request_ring_position;
1987 * Emit any outstanding flushes - execbuf can fail to emit the flush
1988 * after having emitted the batchbuffer command. Hence we need to fix
1989 * things up similar to emitting the lazy request. The difference here
1990 * is that the flush _must_ happen before the next request, no matter
1993 ret = intel_ring_flush_all_caches(ring);
1997 request = kmalloc(sizeof(*request), GFP_KERNEL);
1998 if (request == NULL)
2002 /* Record the position of the start of the request so that
2003 * should we detect the updated seqno part-way through the
2004 * GPU processing the request, we never over-estimate the
2005 * position of the head.
2007 request_ring_position = intel_ring_get_tail(ring);
2009 ret = ring->add_request(ring);
2015 request->seqno = intel_ring_get_seqno(ring);
2016 request->ring = ring;
2017 request->tail = request_ring_position;
2018 request->emitted_jiffies = jiffies;
2019 was_empty = list_empty(&ring->request_list);
2020 list_add_tail(&request->list, &ring->request_list);
2021 request->file_priv = NULL;
2024 struct drm_i915_file_private *file_priv = file->driver_priv;
2026 spin_lock(&file_priv->mm.lock);
2027 request->file_priv = file_priv;
2028 list_add_tail(&request->client_list,
2029 &file_priv->mm.request_list);
2030 spin_unlock(&file_priv->mm.lock);
2033 trace_i915_gem_request_add(ring, request->seqno);
2034 ring->outstanding_lazy_request = 0;
2036 if (!dev_priv->mm.suspended) {
2037 if (i915_enable_hangcheck) {
2038 mod_timer(&dev_priv->hangcheck_timer,
2039 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2042 queue_delayed_work(dev_priv->wq,
2043 &dev_priv->mm.retire_work,
2044 round_jiffies_up_relative(HZ));
2045 intel_mark_busy(dev_priv->dev);
2050 *out_seqno = request->seqno;
2055 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2057 struct drm_i915_file_private *file_priv = request->file_priv;
2062 spin_lock(&file_priv->mm.lock);
2063 if (request->file_priv) {
2064 list_del(&request->client_list);
2065 request->file_priv = NULL;
2067 spin_unlock(&file_priv->mm.lock);
2070 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2071 struct intel_ring_buffer *ring)
2073 while (!list_empty(&ring->request_list)) {
2074 struct drm_i915_gem_request *request;
2076 request = list_first_entry(&ring->request_list,
2077 struct drm_i915_gem_request,
2080 list_del(&request->list);
2081 i915_gem_request_remove_from_client(request);
2085 while (!list_empty(&ring->active_list)) {
2086 struct drm_i915_gem_object *obj;
2088 obj = list_first_entry(&ring->active_list,
2089 struct drm_i915_gem_object,
2092 i915_gem_object_move_to_inactive(obj);
2096 static void i915_gem_reset_fences(struct drm_device *dev)
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2101 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2102 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2104 i915_gem_write_fence(dev, i, NULL);
2107 i915_gem_object_fence_lost(reg->obj);
2111 INIT_LIST_HEAD(®->lru_list);
2114 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2117 void i915_gem_reset(struct drm_device *dev)
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct drm_i915_gem_object *obj;
2121 struct intel_ring_buffer *ring;
2124 for_each_ring(ring, dev_priv, i)
2125 i915_gem_reset_ring_lists(dev_priv, ring);
2127 /* Move everything out of the GPU domains to ensure we do any
2128 * necessary invalidation upon reuse.
2130 list_for_each_entry(obj,
2131 &dev_priv->mm.inactive_list,
2134 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2137 /* The fence registers are invalidated so clear them out */
2138 i915_gem_reset_fences(dev);
2142 * This function clears the request list as sequence numbers are passed.
2145 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2149 if (list_empty(&ring->request_list))
2152 WARN_ON(i915_verify_lists(ring->dev));
2154 seqno = ring->get_seqno(ring, true);
2156 while (!list_empty(&ring->request_list)) {
2157 struct drm_i915_gem_request *request;
2159 request = list_first_entry(&ring->request_list,
2160 struct drm_i915_gem_request,
2163 if (!i915_seqno_passed(seqno, request->seqno))
2166 trace_i915_gem_request_retire(ring, request->seqno);
2167 /* We know the GPU must have read the request to have
2168 * sent us the seqno + interrupt, so use the position
2169 * of tail of the request to update the last known position
2172 ring->last_retired_head = request->tail;
2174 list_del(&request->list);
2175 i915_gem_request_remove_from_client(request);
2179 /* Move any buffers on the active list that are no longer referenced
2180 * by the ringbuffer to the flushing/inactive lists as appropriate.
2182 while (!list_empty(&ring->active_list)) {
2183 struct drm_i915_gem_object *obj;
2185 obj = list_first_entry(&ring->active_list,
2186 struct drm_i915_gem_object,
2189 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2192 i915_gem_object_move_to_inactive(obj);
2195 if (unlikely(ring->trace_irq_seqno &&
2196 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2197 ring->irq_put(ring);
2198 ring->trace_irq_seqno = 0;
2201 WARN_ON(i915_verify_lists(ring->dev));
2205 i915_gem_retire_requests(struct drm_device *dev)
2207 drm_i915_private_t *dev_priv = dev->dev_private;
2208 struct intel_ring_buffer *ring;
2211 for_each_ring(ring, dev_priv, i)
2212 i915_gem_retire_requests_ring(ring);
2216 i915_gem_retire_work_handler(struct work_struct *work)
2218 drm_i915_private_t *dev_priv;
2219 struct drm_device *dev;
2220 struct intel_ring_buffer *ring;
2224 dev_priv = container_of(work, drm_i915_private_t,
2225 mm.retire_work.work);
2226 dev = dev_priv->dev;
2228 /* Come back later if the device is busy... */
2229 if (!mutex_trylock(&dev->struct_mutex)) {
2230 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2231 round_jiffies_up_relative(HZ));
2235 i915_gem_retire_requests(dev);
2237 /* Send a periodic flush down the ring so we don't hold onto GEM
2238 * objects indefinitely.
2241 for_each_ring(ring, dev_priv, i) {
2242 if (ring->gpu_caches_dirty)
2243 i915_add_request(ring, NULL, NULL);
2245 idle &= list_empty(&ring->request_list);
2248 if (!dev_priv->mm.suspended && !idle)
2249 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2250 round_jiffies_up_relative(HZ));
2252 intel_mark_idle(dev);
2254 mutex_unlock(&dev->struct_mutex);
2258 * Ensures that an object will eventually get non-busy by flushing any required
2259 * write domains, emitting any outstanding lazy request and retiring and
2260 * completed requests.
2263 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2268 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2272 i915_gem_retire_requests_ring(obj->ring);
2279 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2280 * @DRM_IOCTL_ARGS: standard ioctl arguments
2282 * Returns 0 if successful, else an error is returned with the remaining time in
2283 * the timeout parameter.
2284 * -ETIME: object is still busy after timeout
2285 * -ERESTARTSYS: signal interrupted the wait
2286 * -ENONENT: object doesn't exist
2287 * Also possible, but rare:
2288 * -EAGAIN: GPU wedged
2290 * -ENODEV: Internal IRQ fail
2291 * -E?: The add request failed
2293 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2294 * non-zero timeout parameter the wait ioctl will wait for the given number of
2295 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2296 * without holding struct_mutex the object may become re-busied before this
2297 * function completes. A similar but shorter * race condition exists in the busy
2301 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2303 struct drm_i915_gem_wait *args = data;
2304 struct drm_i915_gem_object *obj;
2305 struct intel_ring_buffer *ring = NULL;
2306 struct timespec timeout_stack, *timeout = NULL;
2310 if (args->timeout_ns >= 0) {
2311 timeout_stack = ns_to_timespec(args->timeout_ns);
2312 timeout = &timeout_stack;
2315 ret = i915_mutex_lock_interruptible(dev);
2319 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2320 if (&obj->base == NULL) {
2321 mutex_unlock(&dev->struct_mutex);
2325 /* Need to make sure the object gets inactive eventually. */
2326 ret = i915_gem_object_flush_active(obj);
2331 seqno = obj->last_read_seqno;
2338 /* Do this after OLR check to make sure we make forward progress polling
2339 * on this IOCTL with a 0 timeout (like busy ioctl)
2341 if (!args->timeout_ns) {
2346 drm_gem_object_unreference(&obj->base);
2347 mutex_unlock(&dev->struct_mutex);
2349 ret = __wait_seqno(ring, seqno, true, timeout);
2351 WARN_ON(!timespec_valid(timeout));
2352 args->timeout_ns = timespec_to_ns(timeout);
2357 drm_gem_object_unreference(&obj->base);
2358 mutex_unlock(&dev->struct_mutex);
2363 * i915_gem_object_sync - sync an object to a ring.
2365 * @obj: object which may be in use on another ring.
2366 * @to: ring we wish to use the object on. May be NULL.
2368 * This code is meant to abstract object synchronization with the GPU.
2369 * Calling with NULL implies synchronizing the object with the CPU
2370 * rather than a particular GPU ring.
2372 * Returns 0 if successful, else propagates up the lower layer error.
2375 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2376 struct intel_ring_buffer *to)
2378 struct intel_ring_buffer *from = obj->ring;
2382 if (from == NULL || to == from)
2385 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2386 return i915_gem_object_wait_rendering(obj, false);
2388 idx = intel_ring_sync_index(from, to);
2390 seqno = obj->last_read_seqno;
2391 if (seqno <= from->sync_seqno[idx])
2394 ret = i915_gem_check_olr(obj->ring, seqno);
2398 ret = to->sync_to(to, from, seqno);
2400 from->sync_seqno[idx] = seqno;
2405 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2407 u32 old_write_domain, old_read_domains;
2409 /* Act a barrier for all accesses through the GTT */
2412 /* Force a pagefault for domain tracking on next user access */
2413 i915_gem_release_mmap(obj);
2415 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2418 old_read_domains = obj->base.read_domains;
2419 old_write_domain = obj->base.write_domain;
2421 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2422 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2424 trace_i915_gem_object_change_domain(obj,
2430 * Unbinds an object from the GTT aperture.
2433 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2435 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2438 if (obj->gtt_space == NULL)
2444 BUG_ON(obj->pages == NULL);
2446 ret = i915_gem_object_finish_gpu(obj);
2449 /* Continue on if we fail due to EIO, the GPU is hung so we
2450 * should be safe and we need to cleanup or else we might
2451 * cause memory corruption through use-after-free.
2454 i915_gem_object_finish_gtt(obj);
2456 /* release the fence reg _after_ flushing */
2457 ret = i915_gem_object_put_fence(obj);
2461 trace_i915_gem_object_unbind(obj);
2463 if (obj->has_global_gtt_mapping)
2464 i915_gem_gtt_unbind_object(obj);
2465 if (obj->has_aliasing_ppgtt_mapping) {
2466 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2467 obj->has_aliasing_ppgtt_mapping = 0;
2469 i915_gem_gtt_finish_object(obj);
2471 list_del(&obj->mm_list);
2472 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2473 /* Avoid an unnecessary call to unbind on rebind. */
2474 obj->map_and_fenceable = true;
2476 drm_mm_put_block(obj->gtt_space);
2477 obj->gtt_space = NULL;
2478 obj->gtt_offset = 0;
2483 static int i915_ring_idle(struct intel_ring_buffer *ring)
2488 /* We need to add any requests required to flush the objects and ring */
2489 if (ring->outstanding_lazy_request) {
2490 ret = i915_add_request(ring, NULL, NULL);
2495 /* Wait upon the last request to be completed */
2496 if (list_empty(&ring->request_list))
2499 seqno = list_entry(ring->request_list.prev,
2500 struct drm_i915_gem_request,
2503 return i915_wait_seqno(ring, seqno);
2506 int i915_gpu_idle(struct drm_device *dev)
2508 drm_i915_private_t *dev_priv = dev->dev_private;
2509 struct intel_ring_buffer *ring;
2512 /* Flush everything onto the inactive list. */
2513 for_each_ring(ring, dev_priv, i) {
2514 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2518 ret = i915_ring_idle(ring);
2526 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2527 struct drm_i915_gem_object *obj)
2529 drm_i915_private_t *dev_priv = dev->dev_private;
2533 u32 size = obj->gtt_space->size;
2535 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2537 val |= obj->gtt_offset & 0xfffff000;
2538 val |= (uint64_t)((obj->stride / 128) - 1) <<
2539 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2541 if (obj->tiling_mode == I915_TILING_Y)
2542 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2543 val |= I965_FENCE_REG_VALID;
2547 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2548 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2551 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2552 struct drm_i915_gem_object *obj)
2554 drm_i915_private_t *dev_priv = dev->dev_private;
2558 u32 size = obj->gtt_space->size;
2560 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2562 val |= obj->gtt_offset & 0xfffff000;
2563 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2564 if (obj->tiling_mode == I915_TILING_Y)
2565 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2566 val |= I965_FENCE_REG_VALID;
2570 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2571 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2574 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2575 struct drm_i915_gem_object *obj)
2577 drm_i915_private_t *dev_priv = dev->dev_private;
2581 u32 size = obj->gtt_space->size;
2585 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2586 (size & -size) != size ||
2587 (obj->gtt_offset & (size - 1)),
2588 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2589 obj->gtt_offset, obj->map_and_fenceable, size);
2591 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2596 /* Note: pitch better be a power of two tile widths */
2597 pitch_val = obj->stride / tile_width;
2598 pitch_val = ffs(pitch_val) - 1;
2600 val = obj->gtt_offset;
2601 if (obj->tiling_mode == I915_TILING_Y)
2602 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2603 val |= I915_FENCE_SIZE_BITS(size);
2604 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2605 val |= I830_FENCE_REG_VALID;
2610 reg = FENCE_REG_830_0 + reg * 4;
2612 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2614 I915_WRITE(reg, val);
2618 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2619 struct drm_i915_gem_object *obj)
2621 drm_i915_private_t *dev_priv = dev->dev_private;
2625 u32 size = obj->gtt_space->size;
2628 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2629 (size & -size) != size ||
2630 (obj->gtt_offset & (size - 1)),
2631 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2632 obj->gtt_offset, size);
2634 pitch_val = obj->stride / 128;
2635 pitch_val = ffs(pitch_val) - 1;
2637 val = obj->gtt_offset;
2638 if (obj->tiling_mode == I915_TILING_Y)
2639 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2640 val |= I830_FENCE_SIZE_BITS(size);
2641 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2642 val |= I830_FENCE_REG_VALID;
2646 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2647 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2650 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2651 struct drm_i915_gem_object *obj)
2653 switch (INTEL_INFO(dev)->gen) {
2655 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2657 case 4: i965_write_fence_reg(dev, reg, obj); break;
2658 case 3: i915_write_fence_reg(dev, reg, obj); break;
2659 case 2: i830_write_fence_reg(dev, reg, obj); break;
2664 static inline int fence_number(struct drm_i915_private *dev_priv,
2665 struct drm_i915_fence_reg *fence)
2667 return fence - dev_priv->fence_regs;
2670 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2671 struct drm_i915_fence_reg *fence,
2674 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2675 int reg = fence_number(dev_priv, fence);
2677 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2680 obj->fence_reg = reg;
2682 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2684 obj->fence_reg = I915_FENCE_REG_NONE;
2686 list_del_init(&fence->lru_list);
2691 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2693 if (obj->last_fenced_seqno) {
2694 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2698 obj->last_fenced_seqno = 0;
2701 /* Ensure that all CPU reads are completed before installing a fence
2702 * and all writes before removing the fence.
2704 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2707 obj->fenced_gpu_access = false;
2712 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2714 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2717 ret = i915_gem_object_flush_fence(obj);
2721 if (obj->fence_reg == I915_FENCE_REG_NONE)
2724 i915_gem_object_update_fence(obj,
2725 &dev_priv->fence_regs[obj->fence_reg],
2727 i915_gem_object_fence_lost(obj);
2732 static struct drm_i915_fence_reg *
2733 i915_find_fence_reg(struct drm_device *dev)
2735 struct drm_i915_private *dev_priv = dev->dev_private;
2736 struct drm_i915_fence_reg *reg, *avail;
2739 /* First try to find a free reg */
2741 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2742 reg = &dev_priv->fence_regs[i];
2746 if (!reg->pin_count)
2753 /* None available, try to steal one or wait for a user to finish */
2754 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2765 * i915_gem_object_get_fence - set up fencing for an object
2766 * @obj: object to map through a fence reg
2768 * When mapping objects through the GTT, userspace wants to be able to write
2769 * to them without having to worry about swizzling if the object is tiled.
2770 * This function walks the fence regs looking for a free one for @obj,
2771 * stealing one if it can't find any.
2773 * It then sets up the reg based on the object's properties: address, pitch
2774 * and tiling format.
2776 * For an untiled surface, this removes any existing fence.
2779 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2781 struct drm_device *dev = obj->base.dev;
2782 struct drm_i915_private *dev_priv = dev->dev_private;
2783 bool enable = obj->tiling_mode != I915_TILING_NONE;
2784 struct drm_i915_fence_reg *reg;
2787 /* Have we updated the tiling parameters upon the object and so
2788 * will need to serialise the write to the associated fence register?
2790 if (obj->fence_dirty) {
2791 ret = i915_gem_object_flush_fence(obj);
2796 /* Just update our place in the LRU if our fence is getting reused. */
2797 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2798 reg = &dev_priv->fence_regs[obj->fence_reg];
2799 if (!obj->fence_dirty) {
2800 list_move_tail(®->lru_list,
2801 &dev_priv->mm.fence_list);
2804 } else if (enable) {
2805 reg = i915_find_fence_reg(dev);
2810 struct drm_i915_gem_object *old = reg->obj;
2812 ret = i915_gem_object_flush_fence(old);
2816 i915_gem_object_fence_lost(old);
2821 i915_gem_object_update_fence(obj, reg, enable);
2822 obj->fence_dirty = false;
2827 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2828 struct drm_mm_node *gtt_space,
2829 unsigned long cache_level)
2831 struct drm_mm_node *other;
2833 /* On non-LLC machines we have to be careful when putting differing
2834 * types of snoopable memory together to avoid the prefetcher
2835 * crossing memory domains and dieing.
2840 if (gtt_space == NULL)
2843 if (list_empty(>t_space->node_list))
2846 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2847 if (other->allocated && !other->hole_follows && other->color != cache_level)
2850 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2851 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2857 static void i915_gem_verify_gtt(struct drm_device *dev)
2860 struct drm_i915_private *dev_priv = dev->dev_private;
2861 struct drm_i915_gem_object *obj;
2864 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2865 if (obj->gtt_space == NULL) {
2866 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2871 if (obj->cache_level != obj->gtt_space->color) {
2872 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2873 obj->gtt_space->start,
2874 obj->gtt_space->start + obj->gtt_space->size,
2876 obj->gtt_space->color);
2881 if (!i915_gem_valid_gtt_space(dev,
2883 obj->cache_level)) {
2884 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2885 obj->gtt_space->start,
2886 obj->gtt_space->start + obj->gtt_space->size,
2898 * Finds free space in the GTT aperture and binds the object there.
2901 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2903 bool map_and_fenceable,
2906 struct drm_device *dev = obj->base.dev;
2907 drm_i915_private_t *dev_priv = dev->dev_private;
2908 struct drm_mm_node *free_space;
2909 u32 size, fence_size, fence_alignment, unfenced_alignment;
2910 bool mappable, fenceable;
2913 if (obj->madv != I915_MADV_WILLNEED) {
2914 DRM_ERROR("Attempting to bind a purgeable object\n");
2918 fence_size = i915_gem_get_gtt_size(dev,
2921 fence_alignment = i915_gem_get_gtt_alignment(dev,
2924 unfenced_alignment =
2925 i915_gem_get_unfenced_gtt_alignment(dev,
2930 alignment = map_and_fenceable ? fence_alignment :
2932 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2933 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2937 size = map_and_fenceable ? fence_size : obj->base.size;
2939 /* If the object is bigger than the entire aperture, reject it early
2940 * before evicting everything in a vain attempt to find space.
2942 if (obj->base.size >
2943 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2944 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2948 ret = i915_gem_object_get_pages(obj);
2952 i915_gem_object_pin_pages(obj);
2955 if (map_and_fenceable)
2956 free_space = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2957 size, alignment, obj->cache_level,
2958 0, dev_priv->mm.gtt_mappable_end,
2961 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2962 size, alignment, obj->cache_level,
2965 if (free_space != NULL) {
2966 if (map_and_fenceable)
2968 drm_mm_get_block_range_generic(free_space,
2969 size, alignment, obj->cache_level,
2970 0, dev_priv->mm.gtt_mappable_end,
2974 drm_mm_get_block_generic(free_space,
2975 size, alignment, obj->cache_level,
2978 if (free_space == NULL) {
2979 ret = i915_gem_evict_something(dev, size, alignment,
2984 i915_gem_object_unpin_pages(obj);
2990 if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2992 obj->cache_level))) {
2993 i915_gem_object_unpin_pages(obj);
2994 drm_mm_put_block(free_space);
2998 ret = i915_gem_gtt_prepare_object(obj);
3000 i915_gem_object_unpin_pages(obj);
3001 drm_mm_put_block(free_space);
3005 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
3006 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3008 obj->gtt_space = free_space;
3009 obj->gtt_offset = free_space->start;
3012 free_space->size == fence_size &&
3013 (free_space->start & (fence_alignment - 1)) == 0;
3016 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3018 obj->map_and_fenceable = mappable && fenceable;
3020 i915_gem_object_unpin_pages(obj);
3021 trace_i915_gem_object_bind(obj, map_and_fenceable);
3022 i915_gem_verify_gtt(dev);
3027 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3029 /* If we don't have a page list set up, then we're not pinned
3030 * to GPU, and we can ignore the cache flush because it'll happen
3031 * again at bind time.
3033 if (obj->pages == NULL)
3036 /* If the GPU is snooping the contents of the CPU cache,
3037 * we do not need to manually clear the CPU cache lines. However,
3038 * the caches are only snooped when the render cache is
3039 * flushed/invalidated. As we always have to emit invalidations
3040 * and flushes when moving into and out of the RENDER domain, correct
3041 * snooping behaviour occurs naturally as the result of our domain
3044 if (obj->cache_level != I915_CACHE_NONE)
3047 trace_i915_gem_object_clflush(obj);
3049 drm_clflush_sg(obj->pages);
3052 /** Flushes the GTT write domain for the object if it's dirty. */
3054 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3056 uint32_t old_write_domain;
3058 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3061 /* No actual flushing is required for the GTT write domain. Writes
3062 * to it immediately go to main memory as far as we know, so there's
3063 * no chipset flush. It also doesn't land in render cache.
3065 * However, we do have to enforce the order so that all writes through
3066 * the GTT land before any writes to the device, such as updates to
3071 old_write_domain = obj->base.write_domain;
3072 obj->base.write_domain = 0;
3074 trace_i915_gem_object_change_domain(obj,
3075 obj->base.read_domains,
3079 /** Flushes the CPU write domain for the object if it's dirty. */
3081 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3083 uint32_t old_write_domain;
3085 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3088 i915_gem_clflush_object(obj);
3089 i915_gem_chipset_flush(obj->base.dev);
3090 old_write_domain = obj->base.write_domain;
3091 obj->base.write_domain = 0;
3093 trace_i915_gem_object_change_domain(obj,
3094 obj->base.read_domains,
3099 * Moves a single object to the GTT read, and possibly write domain.
3101 * This function returns when the move is complete, including waiting on
3105 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3107 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3108 uint32_t old_write_domain, old_read_domains;
3111 /* Not valid to be called on unbound objects. */
3112 if (obj->gtt_space == NULL)
3115 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3118 ret = i915_gem_object_wait_rendering(obj, !write);
3122 i915_gem_object_flush_cpu_write_domain(obj);
3124 old_write_domain = obj->base.write_domain;
3125 old_read_domains = obj->base.read_domains;
3127 /* It should now be out of any other write domains, and we can update
3128 * the domain values for our changes.
3130 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3131 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3133 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3134 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3138 trace_i915_gem_object_change_domain(obj,
3142 /* And bump the LRU for this access */
3143 if (i915_gem_object_is_inactive(obj))
3144 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3149 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3150 enum i915_cache_level cache_level)
3152 struct drm_device *dev = obj->base.dev;
3153 drm_i915_private_t *dev_priv = dev->dev_private;
3156 if (obj->cache_level == cache_level)
3159 if (obj->pin_count) {
3160 DRM_DEBUG("can not change the cache level of pinned objects\n");
3164 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3165 ret = i915_gem_object_unbind(obj);
3170 if (obj->gtt_space) {
3171 ret = i915_gem_object_finish_gpu(obj);
3175 i915_gem_object_finish_gtt(obj);
3177 /* Before SandyBridge, you could not use tiling or fence
3178 * registers with snooped memory, so relinquish any fences
3179 * currently pointing to our region in the aperture.
3181 if (INTEL_INFO(dev)->gen < 6) {
3182 ret = i915_gem_object_put_fence(obj);
3187 if (obj->has_global_gtt_mapping)
3188 i915_gem_gtt_bind_object(obj, cache_level);
3189 if (obj->has_aliasing_ppgtt_mapping)
3190 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3193 obj->gtt_space->color = cache_level;
3196 if (cache_level == I915_CACHE_NONE) {
3197 u32 old_read_domains, old_write_domain;
3199 /* If we're coming from LLC cached, then we haven't
3200 * actually been tracking whether the data is in the
3201 * CPU cache or not, since we only allow one bit set
3202 * in obj->write_domain and have been skipping the clflushes.
3203 * Just set it to the CPU cache for now.
3205 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3206 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3208 old_read_domains = obj->base.read_domains;
3209 old_write_domain = obj->base.write_domain;
3211 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3212 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3214 trace_i915_gem_object_change_domain(obj,
3219 obj->cache_level = cache_level;
3220 i915_gem_verify_gtt(dev);
3224 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3225 struct drm_file *file)
3227 struct drm_i915_gem_caching *args = data;
3228 struct drm_i915_gem_object *obj;
3231 ret = i915_mutex_lock_interruptible(dev);
3235 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3236 if (&obj->base == NULL) {
3241 args->caching = obj->cache_level != I915_CACHE_NONE;
3243 drm_gem_object_unreference(&obj->base);
3245 mutex_unlock(&dev->struct_mutex);
3249 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3250 struct drm_file *file)
3252 struct drm_i915_gem_caching *args = data;
3253 struct drm_i915_gem_object *obj;
3254 enum i915_cache_level level;
3257 switch (args->caching) {
3258 case I915_CACHING_NONE:
3259 level = I915_CACHE_NONE;
3261 case I915_CACHING_CACHED:
3262 level = I915_CACHE_LLC;
3268 ret = i915_mutex_lock_interruptible(dev);
3272 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3273 if (&obj->base == NULL) {
3278 ret = i915_gem_object_set_cache_level(obj, level);
3280 drm_gem_object_unreference(&obj->base);
3282 mutex_unlock(&dev->struct_mutex);
3287 * Prepare buffer for display plane (scanout, cursors, etc).
3288 * Can be called from an uninterruptible phase (modesetting) and allows
3289 * any flushes to be pipelined (for pageflips).
3292 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3294 struct intel_ring_buffer *pipelined)
3296 u32 old_read_domains, old_write_domain;
3299 if (pipelined != obj->ring) {
3300 ret = i915_gem_object_sync(obj, pipelined);
3305 /* The display engine is not coherent with the LLC cache on gen6. As
3306 * a result, we make sure that the pinning that is about to occur is
3307 * done with uncached PTEs. This is lowest common denominator for all
3310 * However for gen6+, we could do better by using the GFDT bit instead
3311 * of uncaching, which would allow us to flush all the LLC-cached data
3312 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3314 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3318 /* As the user may map the buffer once pinned in the display plane
3319 * (e.g. libkms for the bootup splash), we have to ensure that we
3320 * always use map_and_fenceable for all scanout buffers.
3322 ret = i915_gem_object_pin(obj, alignment, true, false);
3326 i915_gem_object_flush_cpu_write_domain(obj);
3328 old_write_domain = obj->base.write_domain;
3329 old_read_domains = obj->base.read_domains;
3331 /* It should now be out of any other write domains, and we can update
3332 * the domain values for our changes.
3334 obj->base.write_domain = 0;
3335 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3337 trace_i915_gem_object_change_domain(obj,
3345 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3349 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3352 ret = i915_gem_object_wait_rendering(obj, false);
3356 /* Ensure that we invalidate the GPU's caches and TLBs. */
3357 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3362 * Moves a single object to the CPU read, and possibly write domain.
3364 * This function returns when the move is complete, including waiting on
3368 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3370 uint32_t old_write_domain, old_read_domains;
3373 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3376 ret = i915_gem_object_wait_rendering(obj, !write);
3380 i915_gem_object_flush_gtt_write_domain(obj);
3382 old_write_domain = obj->base.write_domain;
3383 old_read_domains = obj->base.read_domains;
3385 /* Flush the CPU cache if it's still invalid. */
3386 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3387 i915_gem_clflush_object(obj);
3389 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3392 /* It should now be out of any other write domains, and we can update
3393 * the domain values for our changes.
3395 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3397 /* If we're writing through the CPU, then the GPU read domains will
3398 * need to be invalidated at next use.
3401 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3402 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3405 trace_i915_gem_object_change_domain(obj,
3412 /* Throttle our rendering by waiting until the ring has completed our requests
3413 * emitted over 20 msec ago.
3415 * Note that if we were to use the current jiffies each time around the loop,
3416 * we wouldn't escape the function with any frames outstanding if the time to
3417 * render a frame was over 20ms.
3419 * This should get us reasonable parallelism between CPU and GPU but also
3420 * relatively low latency when blocking on a particular request to finish.
3423 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 struct drm_i915_file_private *file_priv = file->driver_priv;
3427 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3428 struct drm_i915_gem_request *request;
3429 struct intel_ring_buffer *ring = NULL;
3433 if (atomic_read(&dev_priv->mm.wedged))
3436 spin_lock(&file_priv->mm.lock);
3437 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3438 if (time_after_eq(request->emitted_jiffies, recent_enough))
3441 ring = request->ring;
3442 seqno = request->seqno;
3444 spin_unlock(&file_priv->mm.lock);
3449 ret = __wait_seqno(ring, seqno, true, NULL);
3451 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3457 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3459 bool map_and_fenceable,
3464 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3467 if (obj->gtt_space != NULL) {
3468 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3469 (map_and_fenceable && !obj->map_and_fenceable)) {
3470 WARN(obj->pin_count,
3471 "bo is already pinned with incorrect alignment:"
3472 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3473 " obj->map_and_fenceable=%d\n",
3474 obj->gtt_offset, alignment,
3476 obj->map_and_fenceable);
3477 ret = i915_gem_object_unbind(obj);
3483 if (obj->gtt_space == NULL) {
3484 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3486 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3492 if (!dev_priv->mm.aliasing_ppgtt)
3493 i915_gem_gtt_bind_object(obj, obj->cache_level);
3496 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3497 i915_gem_gtt_bind_object(obj, obj->cache_level);
3500 obj->pin_mappable |= map_and_fenceable;
3506 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3508 BUG_ON(obj->pin_count == 0);
3509 BUG_ON(obj->gtt_space == NULL);
3511 if (--obj->pin_count == 0)
3512 obj->pin_mappable = false;
3516 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3517 struct drm_file *file)
3519 struct drm_i915_gem_pin *args = data;
3520 struct drm_i915_gem_object *obj;
3523 ret = i915_mutex_lock_interruptible(dev);
3527 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3528 if (&obj->base == NULL) {
3533 if (obj->madv != I915_MADV_WILLNEED) {
3534 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3539 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3540 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3546 obj->user_pin_count++;
3547 obj->pin_filp = file;
3548 if (obj->user_pin_count == 1) {
3549 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3554 /* XXX - flush the CPU caches for pinned objects
3555 * as the X server doesn't manage domains yet
3557 i915_gem_object_flush_cpu_write_domain(obj);
3558 args->offset = obj->gtt_offset;
3560 drm_gem_object_unreference(&obj->base);
3562 mutex_unlock(&dev->struct_mutex);
3567 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3568 struct drm_file *file)
3570 struct drm_i915_gem_pin *args = data;
3571 struct drm_i915_gem_object *obj;
3574 ret = i915_mutex_lock_interruptible(dev);
3578 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3579 if (&obj->base == NULL) {
3584 if (obj->pin_filp != file) {
3585 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3590 obj->user_pin_count--;
3591 if (obj->user_pin_count == 0) {
3592 obj->pin_filp = NULL;
3593 i915_gem_object_unpin(obj);
3597 drm_gem_object_unreference(&obj->base);
3599 mutex_unlock(&dev->struct_mutex);
3604 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3605 struct drm_file *file)
3607 struct drm_i915_gem_busy *args = data;
3608 struct drm_i915_gem_object *obj;
3611 ret = i915_mutex_lock_interruptible(dev);
3615 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3616 if (&obj->base == NULL) {
3621 /* Count all active objects as busy, even if they are currently not used
3622 * by the gpu. Users of this interface expect objects to eventually
3623 * become non-busy without any further actions, therefore emit any
3624 * necessary flushes here.
3626 ret = i915_gem_object_flush_active(obj);
3628 args->busy = obj->active;
3630 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3631 args->busy |= intel_ring_flag(obj->ring) << 16;
3634 drm_gem_object_unreference(&obj->base);
3636 mutex_unlock(&dev->struct_mutex);
3641 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3642 struct drm_file *file_priv)
3644 return i915_gem_ring_throttle(dev, file_priv);
3648 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3649 struct drm_file *file_priv)
3651 struct drm_i915_gem_madvise *args = data;
3652 struct drm_i915_gem_object *obj;
3655 switch (args->madv) {
3656 case I915_MADV_DONTNEED:
3657 case I915_MADV_WILLNEED:
3663 ret = i915_mutex_lock_interruptible(dev);
3667 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3668 if (&obj->base == NULL) {
3673 if (obj->pin_count) {
3678 if (obj->madv != __I915_MADV_PURGED)
3679 obj->madv = args->madv;
3681 /* if the object is no longer attached, discard its backing storage */
3682 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3683 i915_gem_object_truncate(obj);
3685 args->retained = obj->madv != __I915_MADV_PURGED;
3688 drm_gem_object_unreference(&obj->base);
3690 mutex_unlock(&dev->struct_mutex);
3694 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3695 const struct drm_i915_gem_object_ops *ops)
3697 INIT_LIST_HEAD(&obj->mm_list);
3698 INIT_LIST_HEAD(&obj->gtt_list);
3699 INIT_LIST_HEAD(&obj->ring_list);
3700 INIT_LIST_HEAD(&obj->exec_list);
3704 obj->fence_reg = I915_FENCE_REG_NONE;
3705 obj->madv = I915_MADV_WILLNEED;
3706 /* Avoid an unnecessary call to unbind on the first bind. */
3707 obj->map_and_fenceable = true;
3709 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3712 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3713 .get_pages = i915_gem_object_get_pages_gtt,
3714 .put_pages = i915_gem_object_put_pages_gtt,
3717 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3720 struct drm_i915_gem_object *obj;
3721 struct address_space *mapping;
3724 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3728 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3733 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3734 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3735 /* 965gm cannot relocate objects above 4GiB. */
3736 mask &= ~__GFP_HIGHMEM;
3737 mask |= __GFP_DMA32;
3740 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3741 mapping_set_gfp_mask(mapping, mask);
3743 i915_gem_object_init(obj, &i915_gem_object_ops);
3745 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3746 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3749 /* On some devices, we can have the GPU use the LLC (the CPU
3750 * cache) for about a 10% performance improvement
3751 * compared to uncached. Graphics requests other than
3752 * display scanout are coherent with the CPU in
3753 * accessing this cache. This means in this mode we
3754 * don't need to clflush on the CPU side, and on the
3755 * GPU side we only need to flush internal caches to
3756 * get data visible to the CPU.
3758 * However, we maintain the display planes as UC, and so
3759 * need to rebind when first used as such.
3761 obj->cache_level = I915_CACHE_LLC;
3763 obj->cache_level = I915_CACHE_NONE;
3768 int i915_gem_init_object(struct drm_gem_object *obj)
3775 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3777 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3778 struct drm_device *dev = obj->base.dev;
3779 drm_i915_private_t *dev_priv = dev->dev_private;
3781 trace_i915_gem_object_destroy(obj);
3784 i915_gem_detach_phys_object(dev, obj);
3787 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3788 bool was_interruptible;
3790 was_interruptible = dev_priv->mm.interruptible;
3791 dev_priv->mm.interruptible = false;
3793 WARN_ON(i915_gem_object_unbind(obj));
3795 dev_priv->mm.interruptible = was_interruptible;
3798 obj->pages_pin_count = 0;
3799 i915_gem_object_put_pages(obj);
3800 i915_gem_object_free_mmap_offset(obj);
3804 if (obj->base.import_attach)
3805 drm_prime_gem_destroy(&obj->base, NULL);
3807 drm_gem_object_release(&obj->base);
3808 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3815 i915_gem_idle(struct drm_device *dev)
3817 drm_i915_private_t *dev_priv = dev->dev_private;
3820 mutex_lock(&dev->struct_mutex);
3822 if (dev_priv->mm.suspended) {
3823 mutex_unlock(&dev->struct_mutex);
3827 ret = i915_gpu_idle(dev);
3829 mutex_unlock(&dev->struct_mutex);
3832 i915_gem_retire_requests(dev);
3834 /* Under UMS, be paranoid and evict. */
3835 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3836 i915_gem_evict_everything(dev);
3838 i915_gem_reset_fences(dev);
3840 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3841 * We need to replace this with a semaphore, or something.
3842 * And not confound mm.suspended!
3844 dev_priv->mm.suspended = 1;
3845 del_timer_sync(&dev_priv->hangcheck_timer);
3847 i915_kernel_lost_context(dev);
3848 i915_gem_cleanup_ringbuffer(dev);
3850 mutex_unlock(&dev->struct_mutex);
3852 /* Cancel the retire work handler, which should be idle now. */
3853 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3858 void i915_gem_l3_remap(struct drm_device *dev)
3860 drm_i915_private_t *dev_priv = dev->dev_private;
3864 if (!IS_IVYBRIDGE(dev))
3867 if (!dev_priv->l3_parity.remap_info)
3870 misccpctl = I915_READ(GEN7_MISCCPCTL);
3871 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3872 POSTING_READ(GEN7_MISCCPCTL);
3874 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3875 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3876 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3877 DRM_DEBUG("0x%x was already programmed to %x\n",
3878 GEN7_L3LOG_BASE + i, remap);
3879 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3880 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3881 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3884 /* Make sure all the writes land before disabling dop clock gating */
3885 POSTING_READ(GEN7_L3LOG_BASE);
3887 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3890 void i915_gem_init_swizzling(struct drm_device *dev)
3892 drm_i915_private_t *dev_priv = dev->dev_private;
3894 if (INTEL_INFO(dev)->gen < 5 ||
3895 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3898 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3899 DISP_TILE_SURFACE_SWIZZLING);
3904 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3906 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3908 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3912 intel_enable_blt(struct drm_device *dev)
3917 /* The blitter was dysfunctional on early prototypes */
3918 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3919 DRM_INFO("BLT not supported on this pre-production hardware;"
3920 " graphics performance will be degraded.\n");
3928 i915_gem_init_hw(struct drm_device *dev)
3930 drm_i915_private_t *dev_priv = dev->dev_private;
3933 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3936 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3937 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3939 i915_gem_l3_remap(dev);
3941 i915_gem_init_swizzling(dev);
3943 ret = intel_init_render_ring_buffer(dev);
3948 ret = intel_init_bsd_ring_buffer(dev);
3950 goto cleanup_render_ring;
3953 if (intel_enable_blt(dev)) {
3954 ret = intel_init_blt_ring_buffer(dev);
3956 goto cleanup_bsd_ring;
3959 dev_priv->next_seqno = 1;
3962 * XXX: There was some w/a described somewhere suggesting loading
3963 * contexts before PPGTT.
3965 i915_gem_context_init(dev);
3966 i915_gem_init_ppgtt(dev);
3971 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3972 cleanup_render_ring:
3973 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3978 intel_enable_ppgtt(struct drm_device *dev)
3980 if (i915_enable_ppgtt >= 0)
3981 return i915_enable_ppgtt;
3983 #ifdef CONFIG_INTEL_IOMMU
3984 /* Disable ppgtt on SNB if VT-d is on. */
3985 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3992 int i915_gem_init(struct drm_device *dev)
3994 struct drm_i915_private *dev_priv = dev->dev_private;
3995 unsigned long gtt_size, mappable_size;
3998 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3999 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
4001 mutex_lock(&dev->struct_mutex);
4002 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
4003 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
4004 * aperture accordingly when using aliasing ppgtt. */
4005 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
4007 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
4009 ret = i915_gem_init_aliasing_ppgtt(dev);
4011 mutex_unlock(&dev->struct_mutex);
4015 /* Let GEM Manage all of the aperture.
4017 * However, leave one page at the end still bound to the scratch
4018 * page. There are a number of places where the hardware
4019 * apparently prefetches past the end of the object, and we've
4020 * seen multiple hangs with the GPU head pointer stuck in a
4021 * batchbuffer bound at the last page of the aperture. One page
4022 * should be enough to keep any prefetching inside of the
4025 i915_gem_init_global_gtt(dev, 0, mappable_size,
4029 ret = i915_gem_init_hw(dev);
4030 mutex_unlock(&dev->struct_mutex);
4032 i915_gem_cleanup_aliasing_ppgtt(dev);
4036 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4037 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4038 dev_priv->dri1.allow_batchbuffer = 1;
4043 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4045 drm_i915_private_t *dev_priv = dev->dev_private;
4046 struct intel_ring_buffer *ring;
4049 for_each_ring(ring, dev_priv, i)
4050 intel_cleanup_ring_buffer(ring);
4054 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4055 struct drm_file *file_priv)
4057 drm_i915_private_t *dev_priv = dev->dev_private;
4060 if (drm_core_check_feature(dev, DRIVER_MODESET))
4063 if (atomic_read(&dev_priv->mm.wedged)) {
4064 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4065 atomic_set(&dev_priv->mm.wedged, 0);
4068 mutex_lock(&dev->struct_mutex);
4069 dev_priv->mm.suspended = 0;
4071 ret = i915_gem_init_hw(dev);
4073 mutex_unlock(&dev->struct_mutex);
4077 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4078 mutex_unlock(&dev->struct_mutex);
4080 ret = drm_irq_install(dev);
4082 goto cleanup_ringbuffer;
4087 mutex_lock(&dev->struct_mutex);
4088 i915_gem_cleanup_ringbuffer(dev);
4089 dev_priv->mm.suspended = 1;
4090 mutex_unlock(&dev->struct_mutex);
4096 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4097 struct drm_file *file_priv)
4099 if (drm_core_check_feature(dev, DRIVER_MODESET))
4102 drm_irq_uninstall(dev);
4103 return i915_gem_idle(dev);
4107 i915_gem_lastclose(struct drm_device *dev)
4111 if (drm_core_check_feature(dev, DRIVER_MODESET))
4114 ret = i915_gem_idle(dev);
4116 DRM_ERROR("failed to idle hardware: %d\n", ret);
4120 init_ring_lists(struct intel_ring_buffer *ring)
4122 INIT_LIST_HEAD(&ring->active_list);
4123 INIT_LIST_HEAD(&ring->request_list);
4127 i915_gem_load(struct drm_device *dev)
4130 drm_i915_private_t *dev_priv = dev->dev_private;
4132 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4133 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4134 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4135 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4136 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4137 for (i = 0; i < I915_NUM_RINGS; i++)
4138 init_ring_lists(&dev_priv->ring[i]);
4139 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4140 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4141 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4142 i915_gem_retire_work_handler);
4143 init_completion(&dev_priv->error_completion);
4145 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4147 I915_WRITE(MI_ARB_STATE,
4148 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4151 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4153 /* Old X drivers will take 0-2 for front, back, depth buffers */
4154 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4155 dev_priv->fence_reg_start = 3;
4157 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4158 dev_priv->num_fence_regs = 16;
4160 dev_priv->num_fence_regs = 8;
4162 /* Initialize fence registers to zero */
4163 i915_gem_reset_fences(dev);
4165 i915_gem_detect_bit_6_swizzle(dev);
4166 init_waitqueue_head(&dev_priv->pending_flip_queue);
4168 dev_priv->mm.interruptible = true;
4170 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4171 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4172 register_shrinker(&dev_priv->mm.inactive_shrinker);
4176 * Create a physically contiguous memory object for this object
4177 * e.g. for cursor + overlay regs
4179 static int i915_gem_init_phys_object(struct drm_device *dev,
4180 int id, int size, int align)
4182 drm_i915_private_t *dev_priv = dev->dev_private;
4183 struct drm_i915_gem_phys_object *phys_obj;
4186 if (dev_priv->mm.phys_objs[id - 1] || !size)
4189 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4195 phys_obj->handle = drm_pci_alloc(dev, size, align);
4196 if (!phys_obj->handle) {
4201 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4204 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4212 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4214 drm_i915_private_t *dev_priv = dev->dev_private;
4215 struct drm_i915_gem_phys_object *phys_obj;
4217 if (!dev_priv->mm.phys_objs[id - 1])
4220 phys_obj = dev_priv->mm.phys_objs[id - 1];
4221 if (phys_obj->cur_obj) {
4222 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4226 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4228 drm_pci_free(dev, phys_obj->handle);
4230 dev_priv->mm.phys_objs[id - 1] = NULL;
4233 void i915_gem_free_all_phys_object(struct drm_device *dev)
4237 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4238 i915_gem_free_phys_object(dev, i);
4241 void i915_gem_detach_phys_object(struct drm_device *dev,
4242 struct drm_i915_gem_object *obj)
4244 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4251 vaddr = obj->phys_obj->handle->vaddr;
4253 page_count = obj->base.size / PAGE_SIZE;
4254 for (i = 0; i < page_count; i++) {
4255 struct page *page = shmem_read_mapping_page(mapping, i);
4256 if (!IS_ERR(page)) {
4257 char *dst = kmap_atomic(page);
4258 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4261 drm_clflush_pages(&page, 1);
4263 set_page_dirty(page);
4264 mark_page_accessed(page);
4265 page_cache_release(page);
4268 i915_gem_chipset_flush(dev);
4270 obj->phys_obj->cur_obj = NULL;
4271 obj->phys_obj = NULL;
4275 i915_gem_attach_phys_object(struct drm_device *dev,
4276 struct drm_i915_gem_object *obj,
4280 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4281 drm_i915_private_t *dev_priv = dev->dev_private;
4286 if (id > I915_MAX_PHYS_OBJECT)
4289 if (obj->phys_obj) {
4290 if (obj->phys_obj->id == id)
4292 i915_gem_detach_phys_object(dev, obj);
4295 /* create a new object */
4296 if (!dev_priv->mm.phys_objs[id - 1]) {
4297 ret = i915_gem_init_phys_object(dev, id,
4298 obj->base.size, align);
4300 DRM_ERROR("failed to init phys object %d size: %zu\n",
4301 id, obj->base.size);
4306 /* bind to the object */
4307 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4308 obj->phys_obj->cur_obj = obj;
4310 page_count = obj->base.size / PAGE_SIZE;
4312 for (i = 0; i < page_count; i++) {
4316 page = shmem_read_mapping_page(mapping, i);
4318 return PTR_ERR(page);
4320 src = kmap_atomic(page);
4321 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4322 memcpy(dst, src, PAGE_SIZE);
4325 mark_page_accessed(page);
4326 page_cache_release(page);
4333 i915_gem_phys_pwrite(struct drm_device *dev,
4334 struct drm_i915_gem_object *obj,
4335 struct drm_i915_gem_pwrite *args,
4336 struct drm_file *file_priv)
4338 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4339 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4341 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4342 unsigned long unwritten;
4344 /* The physical object once assigned is fixed for the lifetime
4345 * of the obj, so we can safely drop the lock and continue
4348 mutex_unlock(&dev->struct_mutex);
4349 unwritten = copy_from_user(vaddr, user_data, args->size);
4350 mutex_lock(&dev->struct_mutex);
4355 i915_gem_chipset_flush(dev);
4359 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4361 struct drm_i915_file_private *file_priv = file->driver_priv;
4363 /* Clean up our request list when the client is going away, so that
4364 * later retire_requests won't dereference our soon-to-be-gone
4367 spin_lock(&file_priv->mm.lock);
4368 while (!list_empty(&file_priv->mm.request_list)) {
4369 struct drm_i915_gem_request *request;
4371 request = list_first_entry(&file_priv->mm.request_list,
4372 struct drm_i915_gem_request,
4374 list_del(&request->client_list);
4375 request->file_priv = NULL;
4377 spin_unlock(&file_priv->mm.lock);
4380 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4382 if (!mutex_is_locked(mutex))
4385 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4386 return mutex->owner == task;
4388 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4394 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4396 struct drm_i915_private *dev_priv =
4397 container_of(shrinker,
4398 struct drm_i915_private,
4399 mm.inactive_shrinker);
4400 struct drm_device *dev = dev_priv->dev;
4401 struct drm_i915_gem_object *obj;
4402 int nr_to_scan = sc->nr_to_scan;
4406 if (!mutex_trylock(&dev->struct_mutex)) {
4407 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4414 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4416 i915_gem_shrink_all(dev_priv);
4420 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4421 if (obj->pages_pin_count == 0)
4422 cnt += obj->base.size >> PAGE_SHIFT;
4423 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4424 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4425 cnt += obj->base.size >> PAGE_SHIFT;
4428 mutex_unlock(&dev->struct_mutex);