2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
43 static __must_check int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
47 i915_gem_object_retire(struct drm_i915_gem_object *obj);
49 static void i915_gem_write_fence(struct drm_device *dev, int reg,
50 struct drm_i915_gem_object *obj);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
52 struct drm_i915_fence_reg *fence,
55 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
56 struct shrink_control *sc);
57 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
58 struct shrink_control *sc);
59 static int i915_gem_shrinker_oom(struct notifier_block *nb,
62 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
64 static bool cpu_cache_is_coherent(struct drm_device *dev,
65 enum i915_cache_level level)
67 return HAS_LLC(dev) || level != I915_CACHE_NONE;
70 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
72 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
75 return obj->pin_display;
78 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
81 i915_gem_release_mmap(obj);
83 /* As we do not have an associated fence register, we will force
84 * a tiling change if we ever need to acquire one.
86 obj->fence_dirty = false;
87 obj->fence_reg = I915_FENCE_REG_NONE;
90 /* some bookkeeping */
91 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
94 spin_lock(&dev_priv->mm.object_stat_lock);
95 dev_priv->mm.object_count++;
96 dev_priv->mm.object_memory += size;
97 spin_unlock(&dev_priv->mm.object_stat_lock);
100 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
103 spin_lock(&dev_priv->mm.object_stat_lock);
104 dev_priv->mm.object_count--;
105 dev_priv->mm.object_memory -= size;
106 spin_unlock(&dev_priv->mm.object_stat_lock);
110 i915_gem_wait_for_error(struct i915_gpu_error *error)
114 #define EXIT_COND (!i915_reset_in_progress(error) || \
115 i915_terminally_wedged(error))
120 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
121 * userspace. If it takes that long something really bad is going on and
122 * we should simply try to bail out and fail as gracefully as possible.
124 ret = wait_event_interruptible_timeout(error->reset_queue,
128 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
130 } else if (ret < 0) {
138 int i915_mutex_lock_interruptible(struct drm_device *dev)
140 struct drm_i915_private *dev_priv = dev->dev_private;
143 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
147 ret = mutex_lock_interruptible(&dev->struct_mutex);
151 WARN_ON(i915_verify_lists(dev));
156 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
157 struct drm_file *file)
159 struct drm_i915_private *dev_priv = dev->dev_private;
160 struct drm_i915_gem_get_aperture *args = data;
161 struct drm_i915_gem_object *obj;
165 mutex_lock(&dev->struct_mutex);
166 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
167 if (i915_gem_obj_is_pinned(obj))
168 pinned += i915_gem_obj_ggtt_size(obj);
169 mutex_unlock(&dev->struct_mutex);
171 args->aper_size = dev_priv->gtt.base.total;
172 args->aper_available_size = args->aper_size - pinned;
178 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
180 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
181 char *vaddr = obj->phys_handle->vaddr;
183 struct scatterlist *sg;
186 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
189 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
193 page = shmem_read_mapping_page(mapping, i);
195 return PTR_ERR(page);
197 src = kmap_atomic(page);
198 memcpy(vaddr, src, PAGE_SIZE);
199 drm_clflush_virt_range(vaddr, PAGE_SIZE);
202 page_cache_release(page);
206 i915_gem_chipset_flush(obj->base.dev);
208 st = kmalloc(sizeof(*st), GFP_KERNEL);
212 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
219 sg->length = obj->base.size;
221 sg_dma_address(sg) = obj->phys_handle->busaddr;
222 sg_dma_len(sg) = obj->base.size;
225 obj->has_dma_mapping = true;
230 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
234 BUG_ON(obj->madv == __I915_MADV_PURGED);
236 ret = i915_gem_object_set_to_cpu_domain(obj, true);
238 /* In the event of a disaster, abandon all caches and
241 WARN_ON(ret != -EIO);
242 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
245 if (obj->madv == I915_MADV_DONTNEED)
249 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
250 char *vaddr = obj->phys_handle->vaddr;
253 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
257 page = shmem_read_mapping_page(mapping, i);
261 dst = kmap_atomic(page);
262 drm_clflush_virt_range(vaddr, PAGE_SIZE);
263 memcpy(dst, vaddr, PAGE_SIZE);
266 set_page_dirty(page);
267 if (obj->madv == I915_MADV_WILLNEED)
268 mark_page_accessed(page);
269 page_cache_release(page);
275 sg_free_table(obj->pages);
278 obj->has_dma_mapping = false;
282 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
284 drm_pci_free(obj->base.dev, obj->phys_handle);
287 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
288 .get_pages = i915_gem_object_get_pages_phys,
289 .put_pages = i915_gem_object_put_pages_phys,
290 .release = i915_gem_object_release_phys,
294 drop_pages(struct drm_i915_gem_object *obj)
296 struct i915_vma *vma, *next;
299 drm_gem_object_reference(&obj->base);
300 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
301 if (i915_vma_unbind(vma))
304 ret = i915_gem_object_put_pages(obj);
305 drm_gem_object_unreference(&obj->base);
311 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
314 drm_dma_handle_t *phys;
317 if (obj->phys_handle) {
318 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
324 if (obj->madv != I915_MADV_WILLNEED)
327 if (obj->base.filp == NULL)
330 ret = drop_pages(obj);
334 /* create a new object */
335 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
339 obj->phys_handle = phys;
340 obj->ops = &i915_gem_phys_ops;
342 return i915_gem_object_get_pages(obj);
346 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
347 struct drm_i915_gem_pwrite *args,
348 struct drm_file *file_priv)
350 struct drm_device *dev = obj->base.dev;
351 void *vaddr = obj->phys_handle->vaddr + args->offset;
352 char __user *user_data = to_user_ptr(args->data_ptr);
355 /* We manually control the domain here and pretend that it
356 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
358 ret = i915_gem_object_wait_rendering(obj, false);
362 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
363 unsigned long unwritten;
365 /* The physical object once assigned is fixed for the lifetime
366 * of the obj, so we can safely drop the lock and continue
369 mutex_unlock(&dev->struct_mutex);
370 unwritten = copy_from_user(vaddr, user_data, args->size);
371 mutex_lock(&dev->struct_mutex);
376 drm_clflush_virt_range(vaddr, args->size);
377 i915_gem_chipset_flush(dev);
381 void *i915_gem_object_alloc(struct drm_device *dev)
383 struct drm_i915_private *dev_priv = dev->dev_private;
384 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
387 void i915_gem_object_free(struct drm_i915_gem_object *obj)
389 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
390 kmem_cache_free(dev_priv->slab, obj);
394 i915_gem_create(struct drm_file *file,
395 struct drm_device *dev,
399 struct drm_i915_gem_object *obj;
403 size = roundup(size, PAGE_SIZE);
407 /* Allocate the new object */
408 obj = i915_gem_alloc_object(dev, size);
412 ret = drm_gem_handle_create(file, &obj->base, &handle);
413 /* drop reference from allocate - handle holds it now */
414 drm_gem_object_unreference_unlocked(&obj->base);
423 i915_gem_dumb_create(struct drm_file *file,
424 struct drm_device *dev,
425 struct drm_mode_create_dumb *args)
427 /* have to work out size/pitch and return them */
428 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
429 args->size = args->pitch * args->height;
430 return i915_gem_create(file, dev,
431 args->size, &args->handle);
435 * Creates a new mm object and returns a handle to it.
438 i915_gem_create_ioctl(struct drm_device *dev, void *data,
439 struct drm_file *file)
441 struct drm_i915_gem_create *args = data;
443 return i915_gem_create(file, dev,
444 args->size, &args->handle);
448 __copy_to_user_swizzled(char __user *cpu_vaddr,
449 const char *gpu_vaddr, int gpu_offset,
452 int ret, cpu_offset = 0;
455 int cacheline_end = ALIGN(gpu_offset + 1, 64);
456 int this_length = min(cacheline_end - gpu_offset, length);
457 int swizzled_gpu_offset = gpu_offset ^ 64;
459 ret = __copy_to_user(cpu_vaddr + cpu_offset,
460 gpu_vaddr + swizzled_gpu_offset,
465 cpu_offset += this_length;
466 gpu_offset += this_length;
467 length -= this_length;
474 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
475 const char __user *cpu_vaddr,
478 int ret, cpu_offset = 0;
481 int cacheline_end = ALIGN(gpu_offset + 1, 64);
482 int this_length = min(cacheline_end - gpu_offset, length);
483 int swizzled_gpu_offset = gpu_offset ^ 64;
485 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
486 cpu_vaddr + cpu_offset,
491 cpu_offset += this_length;
492 gpu_offset += this_length;
493 length -= this_length;
500 * Pins the specified object's pages and synchronizes the object with
501 * GPU accesses. Sets needs_clflush to non-zero if the caller should
502 * flush the object from the CPU cache.
504 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
514 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
515 /* If we're not in the cpu read domain, set ourself into the gtt
516 * read domain and manually flush cachelines (if required). This
517 * optimizes for the case when the gpu will dirty the data
518 * anyway again before the next pread happens. */
519 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
521 ret = i915_gem_object_wait_rendering(obj, true);
525 i915_gem_object_retire(obj);
528 ret = i915_gem_object_get_pages(obj);
532 i915_gem_object_pin_pages(obj);
537 /* Per-page copy function for the shmem pread fastpath.
538 * Flushes invalid cachelines before reading the target if
539 * needs_clflush is set. */
541 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
542 char __user *user_data,
543 bool page_do_bit17_swizzling, bool needs_clflush)
548 if (unlikely(page_do_bit17_swizzling))
551 vaddr = kmap_atomic(page);
553 drm_clflush_virt_range(vaddr + shmem_page_offset,
555 ret = __copy_to_user_inatomic(user_data,
556 vaddr + shmem_page_offset,
558 kunmap_atomic(vaddr);
560 return ret ? -EFAULT : 0;
564 shmem_clflush_swizzled_range(char *addr, unsigned long length,
567 if (unlikely(swizzled)) {
568 unsigned long start = (unsigned long) addr;
569 unsigned long end = (unsigned long) addr + length;
571 /* For swizzling simply ensure that we always flush both
572 * channels. Lame, but simple and it works. Swizzled
573 * pwrite/pread is far from a hotpath - current userspace
574 * doesn't use it at all. */
575 start = round_down(start, 128);
576 end = round_up(end, 128);
578 drm_clflush_virt_range((void *)start, end - start);
580 drm_clflush_virt_range(addr, length);
585 /* Only difference to the fast-path function is that this can handle bit17
586 * and uses non-atomic copy and kmap functions. */
588 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
589 char __user *user_data,
590 bool page_do_bit17_swizzling, bool needs_clflush)
597 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
599 page_do_bit17_swizzling);
601 if (page_do_bit17_swizzling)
602 ret = __copy_to_user_swizzled(user_data,
603 vaddr, shmem_page_offset,
606 ret = __copy_to_user(user_data,
607 vaddr + shmem_page_offset,
611 return ret ? - EFAULT : 0;
615 i915_gem_shmem_pread(struct drm_device *dev,
616 struct drm_i915_gem_object *obj,
617 struct drm_i915_gem_pread *args,
618 struct drm_file *file)
620 char __user *user_data;
623 int shmem_page_offset, page_length, ret = 0;
624 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
626 int needs_clflush = 0;
627 struct sg_page_iter sg_iter;
629 user_data = to_user_ptr(args->data_ptr);
632 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
634 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
638 offset = args->offset;
640 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
641 offset >> PAGE_SHIFT) {
642 struct page *page = sg_page_iter_page(&sg_iter);
647 /* Operation in this page
649 * shmem_page_offset = offset within page in shmem file
650 * page_length = bytes to copy for this page
652 shmem_page_offset = offset_in_page(offset);
653 page_length = remain;
654 if ((shmem_page_offset + page_length) > PAGE_SIZE)
655 page_length = PAGE_SIZE - shmem_page_offset;
657 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
658 (page_to_phys(page) & (1 << 17)) != 0;
660 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
661 user_data, page_do_bit17_swizzling,
666 mutex_unlock(&dev->struct_mutex);
668 if (likely(!i915.prefault_disable) && !prefaulted) {
669 ret = fault_in_multipages_writeable(user_data, remain);
670 /* Userspace is tricking us, but we've already clobbered
671 * its pages with the prefault and promised to write the
672 * data up to the first fault. Hence ignore any errors
673 * and just continue. */
678 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
679 user_data, page_do_bit17_swizzling,
682 mutex_lock(&dev->struct_mutex);
688 remain -= page_length;
689 user_data += page_length;
690 offset += page_length;
694 i915_gem_object_unpin_pages(obj);
700 * Reads data from the object referenced by handle.
702 * On error, the contents of *data are undefined.
705 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
706 struct drm_file *file)
708 struct drm_i915_gem_pread *args = data;
709 struct drm_i915_gem_object *obj;
715 if (!access_ok(VERIFY_WRITE,
716 to_user_ptr(args->data_ptr),
720 ret = i915_mutex_lock_interruptible(dev);
724 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
725 if (&obj->base == NULL) {
730 /* Bounds check source. */
731 if (args->offset > obj->base.size ||
732 args->size > obj->base.size - args->offset) {
737 /* prime objects have no backing filp to GEM pread/pwrite
740 if (!obj->base.filp) {
745 trace_i915_gem_object_pread(obj, args->offset, args->size);
747 ret = i915_gem_shmem_pread(dev, obj, args, file);
750 drm_gem_object_unreference(&obj->base);
752 mutex_unlock(&dev->struct_mutex);
756 /* This is the fast write path which cannot handle
757 * page faults in the source data
761 fast_user_write(struct io_mapping *mapping,
762 loff_t page_base, int page_offset,
763 char __user *user_data,
766 void __iomem *vaddr_atomic;
768 unsigned long unwritten;
770 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
771 /* We can use the cpu mem copy function because this is X86. */
772 vaddr = (void __force*)vaddr_atomic + page_offset;
773 unwritten = __copy_from_user_inatomic_nocache(vaddr,
775 io_mapping_unmap_atomic(vaddr_atomic);
780 * This is the fast pwrite path, where we copy the data directly from the
781 * user into the GTT, uncached.
784 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
785 struct drm_i915_gem_object *obj,
786 struct drm_i915_gem_pwrite *args,
787 struct drm_file *file)
789 struct drm_i915_private *dev_priv = dev->dev_private;
791 loff_t offset, page_base;
792 char __user *user_data;
793 int page_offset, page_length, ret;
795 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
799 ret = i915_gem_object_set_to_gtt_domain(obj, true);
803 ret = i915_gem_object_put_fence(obj);
807 user_data = to_user_ptr(args->data_ptr);
810 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
813 /* Operation in this page
815 * page_base = page offset within aperture
816 * page_offset = offset within page
817 * page_length = bytes to copy for this page
819 page_base = offset & PAGE_MASK;
820 page_offset = offset_in_page(offset);
821 page_length = remain;
822 if ((page_offset + remain) > PAGE_SIZE)
823 page_length = PAGE_SIZE - page_offset;
825 /* If we get a fault while copying data, then (presumably) our
826 * source page isn't available. Return the error and we'll
827 * retry in the slow path.
829 if (fast_user_write(dev_priv->gtt.mappable, page_base,
830 page_offset, user_data, page_length)) {
835 remain -= page_length;
836 user_data += page_length;
837 offset += page_length;
841 i915_gem_object_ggtt_unpin(obj);
846 /* Per-page copy function for the shmem pwrite fastpath.
847 * Flushes invalid cachelines before writing to the target if
848 * needs_clflush_before is set and flushes out any written cachelines after
849 * writing if needs_clflush is set. */
851 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
852 char __user *user_data,
853 bool page_do_bit17_swizzling,
854 bool needs_clflush_before,
855 bool needs_clflush_after)
860 if (unlikely(page_do_bit17_swizzling))
863 vaddr = kmap_atomic(page);
864 if (needs_clflush_before)
865 drm_clflush_virt_range(vaddr + shmem_page_offset,
867 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
868 user_data, page_length);
869 if (needs_clflush_after)
870 drm_clflush_virt_range(vaddr + shmem_page_offset,
872 kunmap_atomic(vaddr);
874 return ret ? -EFAULT : 0;
877 /* Only difference to the fast-path function is that this can handle bit17
878 * and uses non-atomic copy and kmap functions. */
880 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
881 char __user *user_data,
882 bool page_do_bit17_swizzling,
883 bool needs_clflush_before,
884 bool needs_clflush_after)
890 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
891 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
893 page_do_bit17_swizzling);
894 if (page_do_bit17_swizzling)
895 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
899 ret = __copy_from_user(vaddr + shmem_page_offset,
902 if (needs_clflush_after)
903 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
905 page_do_bit17_swizzling);
908 return ret ? -EFAULT : 0;
912 i915_gem_shmem_pwrite(struct drm_device *dev,
913 struct drm_i915_gem_object *obj,
914 struct drm_i915_gem_pwrite *args,
915 struct drm_file *file)
919 char __user *user_data;
920 int shmem_page_offset, page_length, ret = 0;
921 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
922 int hit_slowpath = 0;
923 int needs_clflush_after = 0;
924 int needs_clflush_before = 0;
925 struct sg_page_iter sg_iter;
927 user_data = to_user_ptr(args->data_ptr);
930 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
932 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
933 /* If we're not in the cpu write domain, set ourself into the gtt
934 * write domain and manually flush cachelines (if required). This
935 * optimizes for the case when the gpu will use the data
936 * right away and we therefore have to clflush anyway. */
937 needs_clflush_after = cpu_write_needs_clflush(obj);
938 ret = i915_gem_object_wait_rendering(obj, false);
942 i915_gem_object_retire(obj);
944 /* Same trick applies to invalidate partially written cachelines read
946 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
947 needs_clflush_before =
948 !cpu_cache_is_coherent(dev, obj->cache_level);
950 ret = i915_gem_object_get_pages(obj);
954 i915_gem_object_pin_pages(obj);
956 offset = args->offset;
959 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
960 offset >> PAGE_SHIFT) {
961 struct page *page = sg_page_iter_page(&sg_iter);
962 int partial_cacheline_write;
967 /* Operation in this page
969 * shmem_page_offset = offset within page in shmem file
970 * page_length = bytes to copy for this page
972 shmem_page_offset = offset_in_page(offset);
974 page_length = remain;
975 if ((shmem_page_offset + page_length) > PAGE_SIZE)
976 page_length = PAGE_SIZE - shmem_page_offset;
978 /* If we don't overwrite a cacheline completely we need to be
979 * careful to have up-to-date data by first clflushing. Don't
980 * overcomplicate things and flush the entire patch. */
981 partial_cacheline_write = needs_clflush_before &&
982 ((shmem_page_offset | page_length)
983 & (boot_cpu_data.x86_clflush_size - 1));
985 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
986 (page_to_phys(page) & (1 << 17)) != 0;
988 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
989 user_data, page_do_bit17_swizzling,
990 partial_cacheline_write,
991 needs_clflush_after);
996 mutex_unlock(&dev->struct_mutex);
997 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
998 user_data, page_do_bit17_swizzling,
999 partial_cacheline_write,
1000 needs_clflush_after);
1002 mutex_lock(&dev->struct_mutex);
1008 remain -= page_length;
1009 user_data += page_length;
1010 offset += page_length;
1014 i915_gem_object_unpin_pages(obj);
1018 * Fixup: Flush cpu caches in case we didn't flush the dirty
1019 * cachelines in-line while writing and the object moved
1020 * out of the cpu write domain while we've dropped the lock.
1022 if (!needs_clflush_after &&
1023 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1024 if (i915_gem_clflush_object(obj, obj->pin_display))
1025 i915_gem_chipset_flush(dev);
1029 if (needs_clflush_after)
1030 i915_gem_chipset_flush(dev);
1036 * Writes data to the object referenced by handle.
1038 * On error, the contents of the buffer that were to be modified are undefined.
1041 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1042 struct drm_file *file)
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 struct drm_i915_gem_pwrite *args = data;
1046 struct drm_i915_gem_object *obj;
1049 if (args->size == 0)
1052 if (!access_ok(VERIFY_READ,
1053 to_user_ptr(args->data_ptr),
1057 if (likely(!i915.prefault_disable)) {
1058 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1064 intel_runtime_pm_get(dev_priv);
1066 ret = i915_mutex_lock_interruptible(dev);
1070 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1071 if (&obj->base == NULL) {
1076 /* Bounds check destination. */
1077 if (args->offset > obj->base.size ||
1078 args->size > obj->base.size - args->offset) {
1083 /* prime objects have no backing filp to GEM pread/pwrite
1086 if (!obj->base.filp) {
1091 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1094 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095 * it would end up going through the fenced access, and we'll get
1096 * different detiling behavior between reading and writing.
1097 * pread/pwrite currently are reading and writing from the CPU
1098 * perspective, requiring manual detiling by the client.
1100 if (obj->tiling_mode == I915_TILING_NONE &&
1101 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1102 cpu_write_needs_clflush(obj)) {
1103 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1104 /* Note that the gtt paths might fail with non-page-backed user
1105 * pointers (e.g. gtt mappings when moving data between
1106 * textures). Fallback to the shmem path in that case. */
1109 if (ret == -EFAULT || ret == -ENOSPC) {
1110 if (obj->phys_handle)
1111 ret = i915_gem_phys_pwrite(obj, args, file);
1113 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1117 drm_gem_object_unreference(&obj->base);
1119 mutex_unlock(&dev->struct_mutex);
1121 intel_runtime_pm_put(dev_priv);
1127 i915_gem_check_wedge(struct i915_gpu_error *error,
1130 if (i915_reset_in_progress(error)) {
1131 /* Non-interruptible callers can't handle -EAGAIN, hence return
1132 * -EIO unconditionally for these. */
1136 /* Recovery complete, but the reset failed ... */
1137 if (i915_terminally_wedged(error))
1141 * Check if GPU Reset is in progress - we need intel_ring_begin
1142 * to work properly to reinit the hw state while the gpu is
1143 * still marked as reset-in-progress. Handle this with a flag.
1145 if (!error->reload_in_reset)
1153 * Compare arbitrary request against outstanding lazy request. Emit on match.
1156 i915_gem_check_olr(struct drm_i915_gem_request *req)
1160 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1163 if (req == req->ring->outstanding_lazy_request)
1164 ret = i915_add_request(req->ring);
1169 static void fake_irq(unsigned long data)
1171 wake_up_process((struct task_struct *)data);
1174 static bool missed_irq(struct drm_i915_private *dev_priv,
1175 struct intel_engine_cs *ring)
1177 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1180 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1182 if (file_priv == NULL)
1185 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1189 * __i915_wait_request - wait until execution of request has finished
1191 * @reset_counter: reset sequence associated with the given request
1192 * @interruptible: do an interruptible wait (normally yes)
1193 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1195 * Note: It is of utmost importance that the passed in seqno and reset_counter
1196 * values have been read by the caller in an smp safe manner. Where read-side
1197 * locks are involved, it is sufficient to read the reset_counter before
1198 * unlocking the lock that protects the seqno. For lockless tricks, the
1199 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1202 * Returns 0 if the request was found within the alloted time. Else returns the
1203 * errno with remaining time filled in timeout argument.
1205 int __i915_wait_request(struct drm_i915_gem_request *req,
1206 unsigned reset_counter,
1209 struct drm_i915_file_private *file_priv)
1211 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1212 struct drm_device *dev = ring->dev;
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214 const bool irq_test_in_progress =
1215 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1217 unsigned long timeout_expire;
1221 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1223 if (i915_gem_request_completed(req, true))
1226 timeout_expire = timeout ?
1227 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1229 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1230 gen6_rps_boost(dev_priv);
1232 mod_delayed_work(dev_priv->wq,
1233 &file_priv->mm.idle_work,
1234 msecs_to_jiffies(100));
1237 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1240 /* Record current time in case interrupted by signal, or wedged */
1241 trace_i915_gem_request_wait_begin(req);
1242 before = ktime_get_raw_ns();
1244 struct timer_list timer;
1246 prepare_to_wait(&ring->irq_queue, &wait,
1247 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1249 /* We need to check whether any gpu reset happened in between
1250 * the caller grabbing the seqno and now ... */
1251 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1252 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1253 * is truely gone. */
1254 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1260 if (i915_gem_request_completed(req, false)) {
1265 if (interruptible && signal_pending(current)) {
1270 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1275 timer.function = NULL;
1276 if (timeout || missed_irq(dev_priv, ring)) {
1277 unsigned long expire;
1279 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1280 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1281 mod_timer(&timer, expire);
1286 if (timer.function) {
1287 del_singleshot_timer_sync(&timer);
1288 destroy_timer_on_stack(&timer);
1291 now = ktime_get_raw_ns();
1292 trace_i915_gem_request_wait_end(req);
1294 if (!irq_test_in_progress)
1295 ring->irq_put(ring);
1297 finish_wait(&ring->irq_queue, &wait);
1300 s64 tres = *timeout - (now - before);
1302 *timeout = tres < 0 ? 0 : tres;
1305 * Apparently ktime isn't accurate enough and occasionally has a
1306 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1307 * things up to make the test happy. We allow up to 1 jiffy.
1309 * This is a regrssion from the timespec->ktime conversion.
1311 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1319 * Waits for a request to be signaled, and cleans up the
1320 * request and object lists appropriately for that event.
1323 i915_wait_request(struct drm_i915_gem_request *req)
1325 struct drm_device *dev;
1326 struct drm_i915_private *dev_priv;
1328 unsigned reset_counter;
1331 BUG_ON(req == NULL);
1333 dev = req->ring->dev;
1334 dev_priv = dev->dev_private;
1335 interruptible = dev_priv->mm.interruptible;
1337 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1339 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1343 ret = i915_gem_check_olr(req);
1347 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1348 i915_gem_request_reference(req);
1349 ret = __i915_wait_request(req, reset_counter,
1350 interruptible, NULL, NULL);
1351 i915_gem_request_unreference(req);
1356 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1361 /* Manually manage the write flush as we may have not yet
1362 * retired the buffer.
1364 * Note that the last_write_req is always the earlier of
1365 * the two (read/write) requests, so if we haved successfully waited,
1366 * we know we have passed the last write.
1368 i915_gem_request_assign(&obj->last_write_req, NULL);
1374 * Ensures that all rendering to the object has completed and the object is
1375 * safe to unbind from the GTT or access from the CPU.
1377 static __must_check int
1378 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1381 struct drm_i915_gem_request *req;
1384 req = readonly ? obj->last_write_req : obj->last_read_req;
1388 ret = i915_wait_request(req);
1392 return i915_gem_object_wait_rendering__tail(obj);
1395 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1396 * as the object state may change during this call.
1398 static __must_check int
1399 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1400 struct drm_i915_file_private *file_priv,
1403 struct drm_i915_gem_request *req;
1404 struct drm_device *dev = obj->base.dev;
1405 struct drm_i915_private *dev_priv = dev->dev_private;
1406 unsigned reset_counter;
1409 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1410 BUG_ON(!dev_priv->mm.interruptible);
1412 req = readonly ? obj->last_write_req : obj->last_read_req;
1416 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1420 ret = i915_gem_check_olr(req);
1424 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1425 i915_gem_request_reference(req);
1426 mutex_unlock(&dev->struct_mutex);
1427 ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1428 mutex_lock(&dev->struct_mutex);
1429 i915_gem_request_unreference(req);
1433 return i915_gem_object_wait_rendering__tail(obj);
1437 * Called when user space prepares to use an object with the CPU, either
1438 * through the mmap ioctl's mapping or a GTT mapping.
1441 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1442 struct drm_file *file)
1444 struct drm_i915_gem_set_domain *args = data;
1445 struct drm_i915_gem_object *obj;
1446 uint32_t read_domains = args->read_domains;
1447 uint32_t write_domain = args->write_domain;
1450 /* Only handle setting domains to types used by the CPU. */
1451 if (write_domain & I915_GEM_GPU_DOMAINS)
1454 if (read_domains & I915_GEM_GPU_DOMAINS)
1457 /* Having something in the write domain implies it's in the read
1458 * domain, and only that read domain. Enforce that in the request.
1460 if (write_domain != 0 && read_domains != write_domain)
1463 ret = i915_mutex_lock_interruptible(dev);
1467 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1468 if (&obj->base == NULL) {
1473 /* Try to flush the object off the GPU without holding the lock.
1474 * We will repeat the flush holding the lock in the normal manner
1475 * to catch cases where we are gazumped.
1477 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1483 if (read_domains & I915_GEM_DOMAIN_GTT)
1484 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1486 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1489 drm_gem_object_unreference(&obj->base);
1491 mutex_unlock(&dev->struct_mutex);
1496 * Called when user space has done writes to this buffer
1499 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1500 struct drm_file *file)
1502 struct drm_i915_gem_sw_finish *args = data;
1503 struct drm_i915_gem_object *obj;
1506 ret = i915_mutex_lock_interruptible(dev);
1510 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1511 if (&obj->base == NULL) {
1516 /* Pinned buffers may be scanout, so flush the cache */
1517 if (obj->pin_display)
1518 i915_gem_object_flush_cpu_write_domain(obj);
1520 drm_gem_object_unreference(&obj->base);
1522 mutex_unlock(&dev->struct_mutex);
1527 * Maps the contents of an object, returning the address it is mapped
1530 * While the mapping holds a reference on the contents of the object, it doesn't
1531 * imply a ref on the object itself.
1535 * DRM driver writers who look a this function as an example for how to do GEM
1536 * mmap support, please don't implement mmap support like here. The modern way
1537 * to implement DRM mmap support is with an mmap offset ioctl (like
1538 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1539 * That way debug tooling like valgrind will understand what's going on, hiding
1540 * the mmap call in a driver private ioctl will break that. The i915 driver only
1541 * does cpu mmaps this way because we didn't know better.
1544 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1545 struct drm_file *file)
1547 struct drm_i915_gem_mmap *args = data;
1548 struct drm_gem_object *obj;
1551 if (args->flags & ~(I915_MMAP_WC))
1554 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1557 obj = drm_gem_object_lookup(dev, file, args->handle);
1561 /* prime objects have no backing filp to GEM mmap
1565 drm_gem_object_unreference_unlocked(obj);
1569 addr = vm_mmap(obj->filp, 0, args->size,
1570 PROT_READ | PROT_WRITE, MAP_SHARED,
1572 if (args->flags & I915_MMAP_WC) {
1573 struct mm_struct *mm = current->mm;
1574 struct vm_area_struct *vma;
1576 down_write(&mm->mmap_sem);
1577 vma = find_vma(mm, addr);
1580 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1583 up_write(&mm->mmap_sem);
1585 drm_gem_object_unreference_unlocked(obj);
1586 if (IS_ERR((void *)addr))
1589 args->addr_ptr = (uint64_t) addr;
1595 * i915_gem_fault - fault a page into the GTT
1596 * vma: VMA in question
1599 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1600 * from userspace. The fault handler takes care of binding the object to
1601 * the GTT (if needed), allocating and programming a fence register (again,
1602 * only if needed based on whether the old reg is still valid or the object
1603 * is tiled) and inserting a new PTE into the faulting process.
1605 * Note that the faulting process may involve evicting existing objects
1606 * from the GTT and/or fence registers to make room. So performance may
1607 * suffer if the GTT working set is large or there are few fence registers
1610 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1612 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1613 struct drm_device *dev = obj->base.dev;
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1615 pgoff_t page_offset;
1618 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1620 intel_runtime_pm_get(dev_priv);
1622 /* We don't use vmf->pgoff since that has the fake offset */
1623 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1626 ret = i915_mutex_lock_interruptible(dev);
1630 trace_i915_gem_object_fault(obj, page_offset, true, write);
1632 /* Try to flush the object off the GPU first without holding the lock.
1633 * Upon reacquiring the lock, we will perform our sanity checks and then
1634 * repeat the flush holding the lock in the normal manner to catch cases
1635 * where we are gazumped.
1637 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1641 /* Access to snoopable pages through the GTT is incoherent. */
1642 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1647 /* Now bind it into the GTT if needed */
1648 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1652 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1656 ret = i915_gem_object_get_fence(obj);
1660 /* Finally, remap it using the new GTT offset */
1661 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1664 if (!obj->fault_mappable) {
1665 unsigned long size = min_t(unsigned long,
1666 vma->vm_end - vma->vm_start,
1670 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1671 ret = vm_insert_pfn(vma,
1672 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1678 obj->fault_mappable = true;
1680 ret = vm_insert_pfn(vma,
1681 (unsigned long)vmf->virtual_address,
1684 i915_gem_object_ggtt_unpin(obj);
1686 mutex_unlock(&dev->struct_mutex);
1691 * We eat errors when the gpu is terminally wedged to avoid
1692 * userspace unduly crashing (gl has no provisions for mmaps to
1693 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1694 * and so needs to be reported.
1696 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1697 ret = VM_FAULT_SIGBUS;
1702 * EAGAIN means the gpu is hung and we'll wait for the error
1703 * handler to reset everything when re-faulting in
1704 * i915_mutex_lock_interruptible.
1711 * EBUSY is ok: this just means that another thread
1712 * already did the job.
1714 ret = VM_FAULT_NOPAGE;
1721 ret = VM_FAULT_SIGBUS;
1724 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1725 ret = VM_FAULT_SIGBUS;
1729 intel_runtime_pm_put(dev_priv);
1734 * i915_gem_release_mmap - remove physical page mappings
1735 * @obj: obj in question
1737 * Preserve the reservation of the mmapping with the DRM core code, but
1738 * relinquish ownership of the pages back to the system.
1740 * It is vital that we remove the page mapping if we have mapped a tiled
1741 * object through the GTT and then lose the fence register due to
1742 * resource pressure. Similarly if the object has been moved out of the
1743 * aperture, than pages mapped into userspace must be revoked. Removing the
1744 * mapping will then trigger a page fault on the next user access, allowing
1745 * fixup by i915_gem_fault().
1748 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1750 if (!obj->fault_mappable)
1753 drm_vma_node_unmap(&obj->base.vma_node,
1754 obj->base.dev->anon_inode->i_mapping);
1755 obj->fault_mappable = false;
1759 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1761 struct drm_i915_gem_object *obj;
1763 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1764 i915_gem_release_mmap(obj);
1768 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1772 if (INTEL_INFO(dev)->gen >= 4 ||
1773 tiling_mode == I915_TILING_NONE)
1776 /* Previous chips need a power-of-two fence region when tiling */
1777 if (INTEL_INFO(dev)->gen == 3)
1778 gtt_size = 1024*1024;
1780 gtt_size = 512*1024;
1782 while (gtt_size < size)
1789 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1790 * @obj: object to check
1792 * Return the required GTT alignment for an object, taking into account
1793 * potential fence register mapping.
1796 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1797 int tiling_mode, bool fenced)
1800 * Minimum alignment is 4k (GTT page size), but might be greater
1801 * if a fence register is needed for the object.
1803 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1804 tiling_mode == I915_TILING_NONE)
1808 * Previous chips need to be aligned to the size of the smallest
1809 * fence register that can contain the object.
1811 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1814 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1816 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1819 if (drm_vma_node_has_offset(&obj->base.vma_node))
1822 dev_priv->mm.shrinker_no_lock_stealing = true;
1824 ret = drm_gem_create_mmap_offset(&obj->base);
1828 /* Badly fragmented mmap space? The only way we can recover
1829 * space is by destroying unwanted objects. We can't randomly release
1830 * mmap_offsets as userspace expects them to be persistent for the
1831 * lifetime of the objects. The closest we can is to release the
1832 * offsets on purgeable objects by truncating it and marking it purged,
1833 * which prevents userspace from ever using that object again.
1835 i915_gem_shrink(dev_priv,
1836 obj->base.size >> PAGE_SHIFT,
1838 I915_SHRINK_UNBOUND |
1839 I915_SHRINK_PURGEABLE);
1840 ret = drm_gem_create_mmap_offset(&obj->base);
1844 i915_gem_shrink_all(dev_priv);
1845 ret = drm_gem_create_mmap_offset(&obj->base);
1847 dev_priv->mm.shrinker_no_lock_stealing = false;
1852 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1854 drm_gem_free_mmap_offset(&obj->base);
1858 i915_gem_mmap_gtt(struct drm_file *file,
1859 struct drm_device *dev,
1863 struct drm_i915_private *dev_priv = dev->dev_private;
1864 struct drm_i915_gem_object *obj;
1867 ret = i915_mutex_lock_interruptible(dev);
1871 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1872 if (&obj->base == NULL) {
1877 if (obj->base.size > dev_priv->gtt.mappable_end) {
1882 if (obj->madv != I915_MADV_WILLNEED) {
1883 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1888 ret = i915_gem_object_create_mmap_offset(obj);
1892 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1895 drm_gem_object_unreference(&obj->base);
1897 mutex_unlock(&dev->struct_mutex);
1902 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1904 * @data: GTT mapping ioctl data
1905 * @file: GEM object info
1907 * Simply returns the fake offset to userspace so it can mmap it.
1908 * The mmap call will end up in drm_gem_mmap(), which will set things
1909 * up so we can get faults in the handler above.
1911 * The fault handler will take care of binding the object into the GTT
1912 * (since it may have been evicted to make room for something), allocating
1913 * a fence register, and mapping the appropriate aperture address into
1917 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1918 struct drm_file *file)
1920 struct drm_i915_gem_mmap_gtt *args = data;
1922 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1926 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1928 return obj->madv == I915_MADV_DONTNEED;
1931 /* Immediately discard the backing storage */
1933 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1935 i915_gem_object_free_mmap_offset(obj);
1937 if (obj->base.filp == NULL)
1940 /* Our goal here is to return as much of the memory as
1941 * is possible back to the system as we are called from OOM.
1942 * To do this we must instruct the shmfs to drop all of its
1943 * backing pages, *now*.
1945 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1946 obj->madv = __I915_MADV_PURGED;
1949 /* Try to discard unwanted pages */
1951 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1953 struct address_space *mapping;
1955 switch (obj->madv) {
1956 case I915_MADV_DONTNEED:
1957 i915_gem_object_truncate(obj);
1958 case __I915_MADV_PURGED:
1962 if (obj->base.filp == NULL)
1965 mapping = file_inode(obj->base.filp)->i_mapping,
1966 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1970 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1972 struct sg_page_iter sg_iter;
1975 BUG_ON(obj->madv == __I915_MADV_PURGED);
1977 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1979 /* In the event of a disaster, abandon all caches and
1980 * hope for the best.
1982 WARN_ON(ret != -EIO);
1983 i915_gem_clflush_object(obj, true);
1984 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1987 if (i915_gem_object_needs_bit17_swizzle(obj))
1988 i915_gem_object_save_bit_17_swizzle(obj);
1990 if (obj->madv == I915_MADV_DONTNEED)
1993 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1994 struct page *page = sg_page_iter_page(&sg_iter);
1997 set_page_dirty(page);
1999 if (obj->madv == I915_MADV_WILLNEED)
2000 mark_page_accessed(page);
2002 page_cache_release(page);
2006 sg_free_table(obj->pages);
2011 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2013 const struct drm_i915_gem_object_ops *ops = obj->ops;
2015 if (obj->pages == NULL)
2018 if (obj->pages_pin_count)
2021 BUG_ON(i915_gem_obj_bound_any(obj));
2023 /* ->put_pages might need to allocate memory for the bit17 swizzle
2024 * array, hence protect them from being reaped by removing them from gtt
2026 list_del(&obj->global_list);
2028 ops->put_pages(obj);
2031 i915_gem_object_invalidate(obj);
2037 i915_gem_shrink(struct drm_i915_private *dev_priv,
2038 long target, unsigned flags)
2041 struct list_head *list;
2044 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2045 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2048 unsigned long count = 0;
2051 * As we may completely rewrite the (un)bound list whilst unbinding
2052 * (due to retiring requests) we have to strictly process only
2053 * one element of the list at the time, and recheck the list
2054 * on every iteration.
2056 * In particular, we must hold a reference whilst removing the
2057 * object as we may end up waiting for and/or retiring the objects.
2058 * This might release the final reference (held by the active list)
2059 * and result in the object being freed from under us. This is
2060 * similar to the precautions the eviction code must take whilst
2063 * Also note that although these lists do not hold a reference to
2064 * the object we can safely grab one here: The final object
2065 * unreferencing and the bound_list are both protected by the
2066 * dev->struct_mutex and so we won't ever be able to observe an
2067 * object on the bound_list with a reference count equals 0.
2069 for (phase = phases; phase->list; phase++) {
2070 struct list_head still_in_list;
2072 if ((flags & phase->bit) == 0)
2075 INIT_LIST_HEAD(&still_in_list);
2076 while (count < target && !list_empty(phase->list)) {
2077 struct drm_i915_gem_object *obj;
2078 struct i915_vma *vma, *v;
2080 obj = list_first_entry(phase->list,
2081 typeof(*obj), global_list);
2082 list_move_tail(&obj->global_list, &still_in_list);
2084 if (flags & I915_SHRINK_PURGEABLE &&
2085 !i915_gem_object_is_purgeable(obj))
2088 drm_gem_object_reference(&obj->base);
2090 /* For the unbound phase, this should be a no-op! */
2091 list_for_each_entry_safe(vma, v,
2092 &obj->vma_list, vma_link)
2093 if (i915_vma_unbind(vma))
2096 if (i915_gem_object_put_pages(obj) == 0)
2097 count += obj->base.size >> PAGE_SHIFT;
2099 drm_gem_object_unreference(&obj->base);
2101 list_splice(&still_in_list, phase->list);
2107 static unsigned long
2108 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2110 i915_gem_evict_everything(dev_priv->dev);
2111 return i915_gem_shrink(dev_priv, LONG_MAX,
2112 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2116 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2118 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2120 struct address_space *mapping;
2121 struct sg_table *st;
2122 struct scatterlist *sg;
2123 struct sg_page_iter sg_iter;
2125 unsigned long last_pfn = 0; /* suppress gcc warning */
2128 /* Assert that the object is not currently in any GPU domain. As it
2129 * wasn't in the GTT, there shouldn't be any way it could have been in
2132 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2133 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2135 st = kmalloc(sizeof(*st), GFP_KERNEL);
2139 page_count = obj->base.size / PAGE_SIZE;
2140 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2145 /* Get the list of pages out of our struct file. They'll be pinned
2146 * at this point until we release them.
2148 * Fail silently without starting the shrinker
2150 mapping = file_inode(obj->base.filp)->i_mapping;
2151 gfp = mapping_gfp_mask(mapping);
2152 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2153 gfp &= ~(__GFP_IO | __GFP_WAIT);
2156 for (i = 0; i < page_count; i++) {
2157 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2159 i915_gem_shrink(dev_priv,
2162 I915_SHRINK_UNBOUND |
2163 I915_SHRINK_PURGEABLE);
2164 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2167 /* We've tried hard to allocate the memory by reaping
2168 * our own buffer, now let the real VM do its job and
2169 * go down in flames if truly OOM.
2171 i915_gem_shrink_all(dev_priv);
2172 page = shmem_read_mapping_page(mapping, i);
2176 #ifdef CONFIG_SWIOTLB
2177 if (swiotlb_nr_tbl()) {
2179 sg_set_page(sg, page, PAGE_SIZE, 0);
2184 if (!i || page_to_pfn(page) != last_pfn + 1) {
2188 sg_set_page(sg, page, PAGE_SIZE, 0);
2190 sg->length += PAGE_SIZE;
2192 last_pfn = page_to_pfn(page);
2194 /* Check that the i965g/gm workaround works. */
2195 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2197 #ifdef CONFIG_SWIOTLB
2198 if (!swiotlb_nr_tbl())
2203 if (i915_gem_object_needs_bit17_swizzle(obj))
2204 i915_gem_object_do_bit_17_swizzle(obj);
2206 if (obj->tiling_mode != I915_TILING_NONE &&
2207 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2208 i915_gem_object_pin_pages(obj);
2214 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2215 page_cache_release(sg_page_iter_page(&sg_iter));
2219 /* shmemfs first checks if there is enough memory to allocate the page
2220 * and reports ENOSPC should there be insufficient, along with the usual
2221 * ENOMEM for a genuine allocation failure.
2223 * We use ENOSPC in our driver to mean that we have run out of aperture
2224 * space and so want to translate the error from shmemfs back to our
2225 * usual understanding of ENOMEM.
2227 if (PTR_ERR(page) == -ENOSPC)
2230 return PTR_ERR(page);
2233 /* Ensure that the associated pages are gathered from the backing storage
2234 * and pinned into our object. i915_gem_object_get_pages() may be called
2235 * multiple times before they are released by a single call to
2236 * i915_gem_object_put_pages() - once the pages are no longer referenced
2237 * either as a result of memory pressure (reaping pages under the shrinker)
2238 * or as the object is itself released.
2241 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2243 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2244 const struct drm_i915_gem_object_ops *ops = obj->ops;
2250 if (obj->madv != I915_MADV_WILLNEED) {
2251 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2255 BUG_ON(obj->pages_pin_count);
2257 ret = ops->get_pages(obj);
2261 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2266 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2267 struct intel_engine_cs *ring)
2269 struct drm_i915_gem_request *req;
2270 struct intel_engine_cs *old_ring;
2272 BUG_ON(ring == NULL);
2274 req = intel_ring_get_request(ring);
2275 old_ring = i915_gem_request_get_ring(obj->last_read_req);
2277 if (old_ring != ring && obj->last_write_req) {
2278 /* Keep the request relative to the current ring */
2279 i915_gem_request_assign(&obj->last_write_req, req);
2282 /* Add a reference if we're newly entering the active list. */
2284 drm_gem_object_reference(&obj->base);
2288 list_move_tail(&obj->ring_list, &ring->active_list);
2290 i915_gem_request_assign(&obj->last_read_req, req);
2293 void i915_vma_move_to_active(struct i915_vma *vma,
2294 struct intel_engine_cs *ring)
2296 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2297 return i915_gem_object_move_to_active(vma->obj, ring);
2301 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2303 struct i915_vma *vma;
2305 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2306 BUG_ON(!obj->active);
2308 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2309 if (!list_empty(&vma->mm_list))
2310 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2313 intel_fb_obj_flush(obj, true);
2315 list_del_init(&obj->ring_list);
2317 i915_gem_request_assign(&obj->last_read_req, NULL);
2318 i915_gem_request_assign(&obj->last_write_req, NULL);
2319 obj->base.write_domain = 0;
2321 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2324 drm_gem_object_unreference(&obj->base);
2326 WARN_ON(i915_verify_lists(dev));
2330 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2332 if (obj->last_read_req == NULL)
2335 if (i915_gem_request_completed(obj->last_read_req, true))
2336 i915_gem_object_move_to_inactive(obj);
2340 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 struct intel_engine_cs *ring;
2346 /* Carefully retire all requests without writing to the rings */
2347 for_each_ring(ring, dev_priv, i) {
2348 ret = intel_ring_idle(ring);
2352 i915_gem_retire_requests(dev);
2354 /* Finally reset hw state */
2355 for_each_ring(ring, dev_priv, i) {
2356 intel_ring_init_seqno(ring, seqno);
2358 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2359 ring->semaphore.sync_seqno[j] = 0;
2365 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2373 /* HWS page needs to be set less than what we
2374 * will inject to ring
2376 ret = i915_gem_init_seqno(dev, seqno - 1);
2380 /* Carefully set the last_seqno value so that wrap
2381 * detection still works
2383 dev_priv->next_seqno = seqno;
2384 dev_priv->last_seqno = seqno - 1;
2385 if (dev_priv->last_seqno == 0)
2386 dev_priv->last_seqno--;
2392 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2394 struct drm_i915_private *dev_priv = dev->dev_private;
2396 /* reserve 0 for non-seqno */
2397 if (dev_priv->next_seqno == 0) {
2398 int ret = i915_gem_init_seqno(dev, 0);
2402 dev_priv->next_seqno = 1;
2405 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2409 int __i915_add_request(struct intel_engine_cs *ring,
2410 struct drm_file *file,
2411 struct drm_i915_gem_object *obj)
2413 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2414 struct drm_i915_gem_request *request;
2415 struct intel_ringbuffer *ringbuf;
2419 request = ring->outstanding_lazy_request;
2420 if (WARN_ON(request == NULL))
2423 if (i915.enable_execlists) {
2424 ringbuf = request->ctx->engine[ring->id].ringbuf;
2426 ringbuf = ring->buffer;
2428 request_start = intel_ring_get_tail(ringbuf);
2430 * Emit any outstanding flushes - execbuf can fail to emit the flush
2431 * after having emitted the batchbuffer command. Hence we need to fix
2432 * things up similar to emitting the lazy request. The difference here
2433 * is that the flush _must_ happen before the next request, no matter
2436 if (i915.enable_execlists) {
2437 ret = logical_ring_flush_all_caches(ringbuf, request->ctx);
2441 ret = intel_ring_flush_all_caches(ring);
2446 /* Record the position of the start of the request so that
2447 * should we detect the updated seqno part-way through the
2448 * GPU processing the request, we never over-estimate the
2449 * position of the head.
2451 request->postfix = intel_ring_get_tail(ringbuf);
2453 if (i915.enable_execlists) {
2454 ret = ring->emit_request(ringbuf, request);
2458 ret = ring->add_request(ring);
2463 request->head = request_start;
2464 request->tail = intel_ring_get_tail(ringbuf);
2466 /* Whilst this request exists, batch_obj will be on the
2467 * active_list, and so will hold the active reference. Only when this
2468 * request is retired will the the batch_obj be moved onto the
2469 * inactive_list and lose its active reference. Hence we do not need
2470 * to explicitly hold another reference here.
2472 request->batch_obj = obj;
2474 if (!i915.enable_execlists) {
2475 /* Hold a reference to the current context so that we can inspect
2476 * it later in case a hangcheck error event fires.
2478 request->ctx = ring->last_context;
2480 i915_gem_context_reference(request->ctx);
2483 request->emitted_jiffies = jiffies;
2484 list_add_tail(&request->list, &ring->request_list);
2485 request->file_priv = NULL;
2488 struct drm_i915_file_private *file_priv = file->driver_priv;
2490 spin_lock(&file_priv->mm.lock);
2491 request->file_priv = file_priv;
2492 list_add_tail(&request->client_list,
2493 &file_priv->mm.request_list);
2494 spin_unlock(&file_priv->mm.lock);
2497 trace_i915_gem_request_add(request);
2498 ring->outstanding_lazy_request = NULL;
2500 i915_queue_hangcheck(ring->dev);
2502 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2503 queue_delayed_work(dev_priv->wq,
2504 &dev_priv->mm.retire_work,
2505 round_jiffies_up_relative(HZ));
2506 intel_mark_busy(dev_priv->dev);
2512 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2514 struct drm_i915_file_private *file_priv = request->file_priv;
2519 spin_lock(&file_priv->mm.lock);
2520 list_del(&request->client_list);
2521 request->file_priv = NULL;
2522 spin_unlock(&file_priv->mm.lock);
2525 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2526 const struct intel_context *ctx)
2528 unsigned long elapsed;
2530 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2532 if (ctx->hang_stats.banned)
2535 if (ctx->hang_stats.ban_period_seconds &&
2536 elapsed <= ctx->hang_stats.ban_period_seconds) {
2537 if (!i915_gem_context_is_default(ctx)) {
2538 DRM_DEBUG("context hanging too fast, banning!\n");
2540 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2541 if (i915_stop_ring_allow_warn(dev_priv))
2542 DRM_ERROR("gpu hanging too fast, banning!\n");
2550 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2551 struct intel_context *ctx,
2554 struct i915_ctx_hang_stats *hs;
2559 hs = &ctx->hang_stats;
2562 hs->banned = i915_context_is_banned(dev_priv, ctx);
2564 hs->guilty_ts = get_seconds();
2566 hs->batch_pending++;
2570 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2572 list_del(&request->list);
2573 i915_gem_request_remove_from_client(request);
2575 i915_gem_request_unreference(request);
2578 void i915_gem_request_free(struct kref *req_ref)
2580 struct drm_i915_gem_request *req = container_of(req_ref,
2582 struct intel_context *ctx = req->ctx;
2585 if (i915.enable_execlists) {
2586 struct intel_engine_cs *ring = req->ring;
2588 if (ctx != ring->default_context)
2589 intel_lr_context_unpin(ring, ctx);
2592 i915_gem_context_unreference(ctx);
2598 struct drm_i915_gem_request *
2599 i915_gem_find_active_request(struct intel_engine_cs *ring)
2601 struct drm_i915_gem_request *request;
2603 list_for_each_entry(request, &ring->request_list, list) {
2604 if (i915_gem_request_completed(request, false))
2613 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2614 struct intel_engine_cs *ring)
2616 struct drm_i915_gem_request *request;
2619 request = i915_gem_find_active_request(ring);
2621 if (request == NULL)
2624 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2626 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2628 list_for_each_entry_continue(request, &ring->request_list, list)
2629 i915_set_reset_status(dev_priv, request->ctx, false);
2632 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2633 struct intel_engine_cs *ring)
2635 while (!list_empty(&ring->active_list)) {
2636 struct drm_i915_gem_object *obj;
2638 obj = list_first_entry(&ring->active_list,
2639 struct drm_i915_gem_object,
2642 i915_gem_object_move_to_inactive(obj);
2646 * Clear the execlists queue up before freeing the requests, as those
2647 * are the ones that keep the context and ringbuffer backing objects
2650 while (!list_empty(&ring->execlist_queue)) {
2651 struct drm_i915_gem_request *submit_req;
2653 submit_req = list_first_entry(&ring->execlist_queue,
2654 struct drm_i915_gem_request,
2656 list_del(&submit_req->execlist_link);
2657 intel_runtime_pm_put(dev_priv);
2659 if (submit_req->ctx != ring->default_context)
2660 intel_lr_context_unpin(ring, submit_req->ctx);
2662 i915_gem_request_unreference(submit_req);
2666 * We must free the requests after all the corresponding objects have
2667 * been moved off active lists. Which is the same order as the normal
2668 * retire_requests function does. This is important if object hold
2669 * implicit references on things like e.g. ppgtt address spaces through
2672 while (!list_empty(&ring->request_list)) {
2673 struct drm_i915_gem_request *request;
2675 request = list_first_entry(&ring->request_list,
2676 struct drm_i915_gem_request,
2679 i915_gem_free_request(request);
2682 /* This may not have been flushed before the reset, so clean it now */
2683 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2686 void i915_gem_restore_fences(struct drm_device *dev)
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2691 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2692 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2695 * Commit delayed tiling changes if we have an object still
2696 * attached to the fence, otherwise just clear the fence.
2699 i915_gem_object_update_fence(reg->obj, reg,
2700 reg->obj->tiling_mode);
2702 i915_gem_write_fence(dev, i, NULL);
2707 void i915_gem_reset(struct drm_device *dev)
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 struct intel_engine_cs *ring;
2714 * Before we free the objects from the requests, we need to inspect
2715 * them for finding the guilty party. As the requests only borrow
2716 * their reference to the objects, the inspection must be done first.
2718 for_each_ring(ring, dev_priv, i)
2719 i915_gem_reset_ring_status(dev_priv, ring);
2721 for_each_ring(ring, dev_priv, i)
2722 i915_gem_reset_ring_cleanup(dev_priv, ring);
2724 i915_gem_context_reset(dev);
2726 i915_gem_restore_fences(dev);
2730 * This function clears the request list as sequence numbers are passed.
2733 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2735 if (list_empty(&ring->request_list))
2738 WARN_ON(i915_verify_lists(ring->dev));
2740 /* Retire requests first as we use it above for the early return.
2741 * If we retire requests last, we may use a later seqno and so clear
2742 * the requests lists without clearing the active list, leading to
2745 while (!list_empty(&ring->request_list)) {
2746 struct drm_i915_gem_request *request;
2747 struct intel_ringbuffer *ringbuf;
2749 request = list_first_entry(&ring->request_list,
2750 struct drm_i915_gem_request,
2753 if (!i915_gem_request_completed(request, true))
2756 trace_i915_gem_request_retire(request);
2758 /* This is one of the few common intersection points
2759 * between legacy ringbuffer submission and execlists:
2760 * we need to tell them apart in order to find the correct
2761 * ringbuffer to which the request belongs to.
2763 if (i915.enable_execlists) {
2764 struct intel_context *ctx = request->ctx;
2765 ringbuf = ctx->engine[ring->id].ringbuf;
2767 ringbuf = ring->buffer;
2769 /* We know the GPU must have read the request to have
2770 * sent us the seqno + interrupt, so use the position
2771 * of tail of the request to update the last known position
2774 ringbuf->last_retired_head = request->postfix;
2776 i915_gem_free_request(request);
2779 /* Move any buffers on the active list that are no longer referenced
2780 * by the ringbuffer to the flushing/inactive lists as appropriate,
2781 * before we free the context associated with the requests.
2783 while (!list_empty(&ring->active_list)) {
2784 struct drm_i915_gem_object *obj;
2786 obj = list_first_entry(&ring->active_list,
2787 struct drm_i915_gem_object,
2790 if (!i915_gem_request_completed(obj->last_read_req, true))
2793 i915_gem_object_move_to_inactive(obj);
2796 if (unlikely(ring->trace_irq_req &&
2797 i915_gem_request_completed(ring->trace_irq_req, true))) {
2798 ring->irq_put(ring);
2799 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2802 WARN_ON(i915_verify_lists(ring->dev));
2806 i915_gem_retire_requests(struct drm_device *dev)
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_engine_cs *ring;
2813 for_each_ring(ring, dev_priv, i) {
2814 i915_gem_retire_requests_ring(ring);
2815 idle &= list_empty(&ring->request_list);
2816 if (i915.enable_execlists) {
2817 unsigned long flags;
2819 spin_lock_irqsave(&ring->execlist_lock, flags);
2820 idle &= list_empty(&ring->execlist_queue);
2821 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2823 intel_execlists_retire_requests(ring);
2828 mod_delayed_work(dev_priv->wq,
2829 &dev_priv->mm.idle_work,
2830 msecs_to_jiffies(100));
2836 i915_gem_retire_work_handler(struct work_struct *work)
2838 struct drm_i915_private *dev_priv =
2839 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2840 struct drm_device *dev = dev_priv->dev;
2843 /* Come back later if the device is busy... */
2845 if (mutex_trylock(&dev->struct_mutex)) {
2846 idle = i915_gem_retire_requests(dev);
2847 mutex_unlock(&dev->struct_mutex);
2850 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2851 round_jiffies_up_relative(HZ));
2855 i915_gem_idle_work_handler(struct work_struct *work)
2857 struct drm_i915_private *dev_priv =
2858 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2860 intel_mark_idle(dev_priv->dev);
2864 * Ensures that an object will eventually get non-busy by flushing any required
2865 * write domains, emitting any outstanding lazy request and retiring and
2866 * completed requests.
2869 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2871 struct intel_engine_cs *ring;
2875 ring = i915_gem_request_get_ring(obj->last_read_req);
2877 ret = i915_gem_check_olr(obj->last_read_req);
2881 i915_gem_retire_requests_ring(ring);
2888 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2889 * @DRM_IOCTL_ARGS: standard ioctl arguments
2891 * Returns 0 if successful, else an error is returned with the remaining time in
2892 * the timeout parameter.
2893 * -ETIME: object is still busy after timeout
2894 * -ERESTARTSYS: signal interrupted the wait
2895 * -ENONENT: object doesn't exist
2896 * Also possible, but rare:
2897 * -EAGAIN: GPU wedged
2899 * -ENODEV: Internal IRQ fail
2900 * -E?: The add request failed
2902 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2903 * non-zero timeout parameter the wait ioctl will wait for the given number of
2904 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2905 * without holding struct_mutex the object may become re-busied before this
2906 * function completes. A similar but shorter * race condition exists in the busy
2910 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 struct drm_i915_gem_wait *args = data;
2914 struct drm_i915_gem_object *obj;
2915 struct drm_i915_gem_request *req;
2916 unsigned reset_counter;
2919 if (args->flags != 0)
2922 ret = i915_mutex_lock_interruptible(dev);
2926 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2927 if (&obj->base == NULL) {
2928 mutex_unlock(&dev->struct_mutex);
2932 /* Need to make sure the object gets inactive eventually. */
2933 ret = i915_gem_object_flush_active(obj);
2937 if (!obj->active || !obj->last_read_req)
2940 req = obj->last_read_req;
2942 /* Do this after OLR check to make sure we make forward progress polling
2943 * on this IOCTL with a timeout == 0 (like busy ioctl)
2945 if (args->timeout_ns == 0) {
2950 drm_gem_object_unreference(&obj->base);
2951 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2952 i915_gem_request_reference(req);
2953 mutex_unlock(&dev->struct_mutex);
2955 ret = __i915_wait_request(req, reset_counter, true,
2956 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
2958 mutex_lock(&dev->struct_mutex);
2959 i915_gem_request_unreference(req);
2960 mutex_unlock(&dev->struct_mutex);
2964 drm_gem_object_unreference(&obj->base);
2965 mutex_unlock(&dev->struct_mutex);
2970 * i915_gem_object_sync - sync an object to a ring.
2972 * @obj: object which may be in use on another ring.
2973 * @to: ring we wish to use the object on. May be NULL.
2975 * This code is meant to abstract object synchronization with the GPU.
2976 * Calling with NULL implies synchronizing the object with the CPU
2977 * rather than a particular GPU ring.
2979 * Returns 0 if successful, else propagates up the lower layer error.
2982 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2983 struct intel_engine_cs *to)
2985 struct intel_engine_cs *from;
2989 from = i915_gem_request_get_ring(obj->last_read_req);
2991 if (from == NULL || to == from)
2994 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2995 return i915_gem_object_wait_rendering(obj, false);
2997 idx = intel_ring_sync_index(from, to);
2999 seqno = i915_gem_request_get_seqno(obj->last_read_req);
3000 /* Optimization: Avoid semaphore sync when we are sure we already
3001 * waited for an object with higher seqno */
3002 if (seqno <= from->semaphore.sync_seqno[idx])
3005 ret = i915_gem_check_olr(obj->last_read_req);
3009 trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
3010 ret = to->semaphore.sync_to(to, from, seqno);
3012 /* We use last_read_req because sync_to()
3013 * might have just caused seqno wrap under
3016 from->semaphore.sync_seqno[idx] =
3017 i915_gem_request_get_seqno(obj->last_read_req);
3022 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3024 u32 old_write_domain, old_read_domains;
3026 /* Force a pagefault for domain tracking on next user access */
3027 i915_gem_release_mmap(obj);
3029 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3032 /* Wait for any direct GTT access to complete */
3035 old_read_domains = obj->base.read_domains;
3036 old_write_domain = obj->base.write_domain;
3038 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3039 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3041 trace_i915_gem_object_change_domain(obj,
3046 int i915_vma_unbind(struct i915_vma *vma)
3048 struct drm_i915_gem_object *obj = vma->obj;
3049 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3052 if (list_empty(&vma->vma_link))
3055 if (!drm_mm_node_allocated(&vma->node)) {
3056 i915_gem_vma_destroy(vma);
3063 BUG_ON(obj->pages == NULL);
3065 ret = i915_gem_object_finish_gpu(obj);
3068 /* Continue on if we fail due to EIO, the GPU is hung so we
3069 * should be safe and we need to cleanup or else we might
3070 * cause memory corruption through use-after-free.
3073 if (i915_is_ggtt(vma->vm) &&
3074 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3075 i915_gem_object_finish_gtt(obj);
3077 /* release the fence reg _after_ flushing */
3078 ret = i915_gem_object_put_fence(obj);
3083 trace_i915_vma_unbind(vma);
3085 vma->unbind_vma(vma);
3087 list_del_init(&vma->mm_list);
3088 if (i915_is_ggtt(vma->vm)) {
3089 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3090 obj->map_and_fenceable = false;
3091 } else if (vma->ggtt_view.pages) {
3092 sg_free_table(vma->ggtt_view.pages);
3093 kfree(vma->ggtt_view.pages);
3094 vma->ggtt_view.pages = NULL;
3098 drm_mm_remove_node(&vma->node);
3099 i915_gem_vma_destroy(vma);
3101 /* Since the unbound list is global, only move to that list if
3102 * no more VMAs exist. */
3103 if (list_empty(&obj->vma_list)) {
3104 /* Throw away the active reference before
3105 * moving to the unbound list. */
3106 i915_gem_object_retire(obj);
3108 i915_gem_gtt_finish_object(obj);
3109 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3112 /* And finally now the object is completely decoupled from this vma,
3113 * we can drop its hold on the backing storage and allow it to be
3114 * reaped by the shrinker.
3116 i915_gem_object_unpin_pages(obj);
3121 int i915_gpu_idle(struct drm_device *dev)
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_engine_cs *ring;
3127 /* Flush everything onto the inactive list. */
3128 for_each_ring(ring, dev_priv, i) {
3129 if (!i915.enable_execlists) {
3130 ret = i915_switch_context(ring, ring->default_context);
3135 ret = intel_ring_idle(ring);
3143 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3144 struct drm_i915_gem_object *obj)
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3148 int fence_pitch_shift;
3150 if (INTEL_INFO(dev)->gen >= 6) {
3151 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3152 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3154 fence_reg = FENCE_REG_965_0;
3155 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3158 fence_reg += reg * 8;
3160 /* To w/a incoherency with non-atomic 64-bit register updates,
3161 * we split the 64-bit update into two 32-bit writes. In order
3162 * for a partial fence not to be evaluated between writes, we
3163 * precede the update with write to turn off the fence register,
3164 * and only enable the fence as the last step.
3166 * For extra levels of paranoia, we make sure each step lands
3167 * before applying the next step.
3169 I915_WRITE(fence_reg, 0);
3170 POSTING_READ(fence_reg);
3173 u32 size = i915_gem_obj_ggtt_size(obj);
3176 /* Adjust fence size to match tiled area */
3177 if (obj->tiling_mode != I915_TILING_NONE) {
3178 uint32_t row_size = obj->stride *
3179 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
3180 size = (size / row_size) * row_size;
3183 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3185 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3186 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3187 if (obj->tiling_mode == I915_TILING_Y)
3188 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3189 val |= I965_FENCE_REG_VALID;
3191 I915_WRITE(fence_reg + 4, val >> 32);
3192 POSTING_READ(fence_reg + 4);
3194 I915_WRITE(fence_reg + 0, val);
3195 POSTING_READ(fence_reg);
3197 I915_WRITE(fence_reg + 4, 0);
3198 POSTING_READ(fence_reg + 4);
3202 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3203 struct drm_i915_gem_object *obj)
3205 struct drm_i915_private *dev_priv = dev->dev_private;
3209 u32 size = i915_gem_obj_ggtt_size(obj);
3213 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3214 (size & -size) != size ||
3215 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3216 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3217 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3219 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3224 /* Note: pitch better be a power of two tile widths */
3225 pitch_val = obj->stride / tile_width;
3226 pitch_val = ffs(pitch_val) - 1;
3228 val = i915_gem_obj_ggtt_offset(obj);
3229 if (obj->tiling_mode == I915_TILING_Y)
3230 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3231 val |= I915_FENCE_SIZE_BITS(size);
3232 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3233 val |= I830_FENCE_REG_VALID;
3238 reg = FENCE_REG_830_0 + reg * 4;
3240 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3242 I915_WRITE(reg, val);
3246 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3247 struct drm_i915_gem_object *obj)
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3253 u32 size = i915_gem_obj_ggtt_size(obj);
3256 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3257 (size & -size) != size ||
3258 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3259 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3260 i915_gem_obj_ggtt_offset(obj), size);
3262 pitch_val = obj->stride / 128;
3263 pitch_val = ffs(pitch_val) - 1;
3265 val = i915_gem_obj_ggtt_offset(obj);
3266 if (obj->tiling_mode == I915_TILING_Y)
3267 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3268 val |= I830_FENCE_SIZE_BITS(size);
3269 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3270 val |= I830_FENCE_REG_VALID;
3274 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3275 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3278 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3280 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3283 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3284 struct drm_i915_gem_object *obj)
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3288 /* Ensure that all CPU reads are completed before installing a fence
3289 * and all writes before removing the fence.
3291 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3294 WARN(obj && (!obj->stride || !obj->tiling_mode),
3295 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3296 obj->stride, obj->tiling_mode);
3299 i830_write_fence_reg(dev, reg, obj);
3300 else if (IS_GEN3(dev))
3301 i915_write_fence_reg(dev, reg, obj);
3302 else if (INTEL_INFO(dev)->gen >= 4)
3303 i965_write_fence_reg(dev, reg, obj);
3305 /* And similarly be paranoid that no direct access to this region
3306 * is reordered to before the fence is installed.
3308 if (i915_gem_object_needs_mb(obj))
3312 static inline int fence_number(struct drm_i915_private *dev_priv,
3313 struct drm_i915_fence_reg *fence)
3315 return fence - dev_priv->fence_regs;
3318 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3319 struct drm_i915_fence_reg *fence,
3322 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3323 int reg = fence_number(dev_priv, fence);
3325 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3328 obj->fence_reg = reg;
3330 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3332 obj->fence_reg = I915_FENCE_REG_NONE;
3334 list_del_init(&fence->lru_list);
3336 obj->fence_dirty = false;
3340 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3342 if (obj->last_fenced_req) {
3343 int ret = i915_wait_request(obj->last_fenced_req);
3347 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3354 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3356 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3357 struct drm_i915_fence_reg *fence;
3360 ret = i915_gem_object_wait_fence(obj);
3364 if (obj->fence_reg == I915_FENCE_REG_NONE)
3367 fence = &dev_priv->fence_regs[obj->fence_reg];
3369 if (WARN_ON(fence->pin_count))
3372 i915_gem_object_fence_lost(obj);
3373 i915_gem_object_update_fence(obj, fence, false);
3378 static struct drm_i915_fence_reg *
3379 i915_find_fence_reg(struct drm_device *dev)
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct drm_i915_fence_reg *reg, *avail;
3385 /* First try to find a free reg */
3387 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3388 reg = &dev_priv->fence_regs[i];
3392 if (!reg->pin_count)
3399 /* None available, try to steal one or wait for a user to finish */
3400 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3408 /* Wait for completion of pending flips which consume fences */
3409 if (intel_has_pending_fb_unpin(dev))
3410 return ERR_PTR(-EAGAIN);
3412 return ERR_PTR(-EDEADLK);
3416 * i915_gem_object_get_fence - set up fencing for an object
3417 * @obj: object to map through a fence reg
3419 * When mapping objects through the GTT, userspace wants to be able to write
3420 * to them without having to worry about swizzling if the object is tiled.
3421 * This function walks the fence regs looking for a free one for @obj,
3422 * stealing one if it can't find any.
3424 * It then sets up the reg based on the object's properties: address, pitch
3425 * and tiling format.
3427 * For an untiled surface, this removes any existing fence.
3430 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3432 struct drm_device *dev = obj->base.dev;
3433 struct drm_i915_private *dev_priv = dev->dev_private;
3434 bool enable = obj->tiling_mode != I915_TILING_NONE;
3435 struct drm_i915_fence_reg *reg;
3438 /* Have we updated the tiling parameters upon the object and so
3439 * will need to serialise the write to the associated fence register?
3441 if (obj->fence_dirty) {
3442 ret = i915_gem_object_wait_fence(obj);
3447 /* Just update our place in the LRU if our fence is getting reused. */
3448 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3449 reg = &dev_priv->fence_regs[obj->fence_reg];
3450 if (!obj->fence_dirty) {
3451 list_move_tail(®->lru_list,
3452 &dev_priv->mm.fence_list);
3455 } else if (enable) {
3456 if (WARN_ON(!obj->map_and_fenceable))
3459 reg = i915_find_fence_reg(dev);
3461 return PTR_ERR(reg);
3464 struct drm_i915_gem_object *old = reg->obj;
3466 ret = i915_gem_object_wait_fence(old);
3470 i915_gem_object_fence_lost(old);
3475 i915_gem_object_update_fence(obj, reg, enable);
3480 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3481 unsigned long cache_level)
3483 struct drm_mm_node *gtt_space = &vma->node;
3484 struct drm_mm_node *other;
3487 * On some machines we have to be careful when putting differing types
3488 * of snoopable memory together to avoid the prefetcher crossing memory
3489 * domains and dying. During vm initialisation, we decide whether or not
3490 * these constraints apply and set the drm_mm.color_adjust
3493 if (vma->vm->mm.color_adjust == NULL)
3496 if (!drm_mm_node_allocated(gtt_space))
3499 if (list_empty(>t_space->node_list))
3502 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3503 if (other->allocated && !other->hole_follows && other->color != cache_level)
3506 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3507 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3514 * Finds free space in the GTT aperture and binds the object there.
3516 static struct i915_vma *
3517 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3518 struct i915_address_space *vm,
3521 const struct i915_ggtt_view *view)
3523 struct drm_device *dev = obj->base.dev;
3524 struct drm_i915_private *dev_priv = dev->dev_private;
3525 u32 size, fence_size, fence_alignment, unfenced_alignment;
3526 unsigned long start =
3527 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3529 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3530 struct i915_vma *vma;
3533 fence_size = i915_gem_get_gtt_size(dev,
3536 fence_alignment = i915_gem_get_gtt_alignment(dev,
3538 obj->tiling_mode, true);
3539 unfenced_alignment =
3540 i915_gem_get_gtt_alignment(dev,
3542 obj->tiling_mode, false);
3545 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3547 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3548 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3549 return ERR_PTR(-EINVAL);
3552 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3554 /* If the object is bigger than the entire aperture, reject it early
3555 * before evicting everything in a vain attempt to find space.
3557 if (obj->base.size > end) {
3558 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3560 flags & PIN_MAPPABLE ? "mappable" : "total",
3562 return ERR_PTR(-E2BIG);
3565 ret = i915_gem_object_get_pages(obj);
3567 return ERR_PTR(ret);
3569 i915_gem_object_pin_pages(obj);
3571 vma = i915_gem_obj_lookup_or_create_vma_view(obj, vm, view);
3576 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3580 DRM_MM_SEARCH_DEFAULT,
3581 DRM_MM_CREATE_DEFAULT);
3583 ret = i915_gem_evict_something(dev, vm, size, alignment,
3592 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3594 goto err_remove_node;
3597 ret = i915_gem_gtt_prepare_object(obj);
3599 goto err_remove_node;
3601 trace_i915_vma_bind(vma, flags);
3602 ret = i915_vma_bind(vma, obj->cache_level,
3603 flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3605 goto err_finish_gtt;
3607 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3608 list_add_tail(&vma->mm_list, &vm->inactive_list);
3613 i915_gem_gtt_finish_object(obj);
3615 drm_mm_remove_node(&vma->node);
3617 i915_gem_vma_destroy(vma);
3620 i915_gem_object_unpin_pages(obj);
3625 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3628 /* If we don't have a page list set up, then we're not pinned
3629 * to GPU, and we can ignore the cache flush because it'll happen
3630 * again at bind time.
3632 if (obj->pages == NULL)
3636 * Stolen memory is always coherent with the GPU as it is explicitly
3637 * marked as wc by the system, or the system is cache-coherent.
3639 if (obj->stolen || obj->phys_handle)
3642 /* If the GPU is snooping the contents of the CPU cache,
3643 * we do not need to manually clear the CPU cache lines. However,
3644 * the caches are only snooped when the render cache is
3645 * flushed/invalidated. As we always have to emit invalidations
3646 * and flushes when moving into and out of the RENDER domain, correct
3647 * snooping behaviour occurs naturally as the result of our domain
3650 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3651 obj->cache_dirty = true;
3655 trace_i915_gem_object_clflush(obj);
3656 drm_clflush_sg(obj->pages);
3657 obj->cache_dirty = false;
3662 /** Flushes the GTT write domain for the object if it's dirty. */
3664 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3666 uint32_t old_write_domain;
3668 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3671 /* No actual flushing is required for the GTT write domain. Writes
3672 * to it immediately go to main memory as far as we know, so there's
3673 * no chipset flush. It also doesn't land in render cache.
3675 * However, we do have to enforce the order so that all writes through
3676 * the GTT land before any writes to the device, such as updates to
3681 old_write_domain = obj->base.write_domain;
3682 obj->base.write_domain = 0;
3684 intel_fb_obj_flush(obj, false);
3686 trace_i915_gem_object_change_domain(obj,
3687 obj->base.read_domains,
3691 /** Flushes the CPU write domain for the object if it's dirty. */
3693 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3695 uint32_t old_write_domain;
3697 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3700 if (i915_gem_clflush_object(obj, obj->pin_display))
3701 i915_gem_chipset_flush(obj->base.dev);
3703 old_write_domain = obj->base.write_domain;
3704 obj->base.write_domain = 0;
3706 intel_fb_obj_flush(obj, false);
3708 trace_i915_gem_object_change_domain(obj,
3709 obj->base.read_domains,
3714 * Moves a single object to the GTT read, and possibly write domain.
3716 * This function returns when the move is complete, including waiting on
3720 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3722 uint32_t old_write_domain, old_read_domains;
3723 struct i915_vma *vma;
3726 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3729 ret = i915_gem_object_wait_rendering(obj, !write);
3733 i915_gem_object_retire(obj);
3735 /* Flush and acquire obj->pages so that we are coherent through
3736 * direct access in memory with previous cached writes through
3737 * shmemfs and that our cache domain tracking remains valid.
3738 * For example, if the obj->filp was moved to swap without us
3739 * being notified and releasing the pages, we would mistakenly
3740 * continue to assume that the obj remained out of the CPU cached
3743 ret = i915_gem_object_get_pages(obj);
3747 i915_gem_object_flush_cpu_write_domain(obj);
3749 /* Serialise direct access to this object with the barriers for
3750 * coherent writes from the GPU, by effectively invalidating the
3751 * GTT domain upon first access.
3753 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3756 old_write_domain = obj->base.write_domain;
3757 old_read_domains = obj->base.read_domains;
3759 /* It should now be out of any other write domains, and we can update
3760 * the domain values for our changes.
3762 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3763 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3765 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3766 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3771 intel_fb_obj_invalidate(obj, NULL);
3773 trace_i915_gem_object_change_domain(obj,
3777 /* And bump the LRU for this access */
3778 vma = i915_gem_obj_to_ggtt(obj);
3779 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3780 list_move_tail(&vma->mm_list,
3781 &to_i915(obj->base.dev)->gtt.base.inactive_list);
3786 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3787 enum i915_cache_level cache_level)
3789 struct drm_device *dev = obj->base.dev;
3790 struct i915_vma *vma, *next;
3793 if (obj->cache_level == cache_level)
3796 if (i915_gem_obj_is_pinned(obj)) {
3797 DRM_DEBUG("can not change the cache level of pinned objects\n");
3801 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3802 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3803 ret = i915_vma_unbind(vma);
3809 if (i915_gem_obj_bound_any(obj)) {
3810 ret = i915_gem_object_finish_gpu(obj);
3814 i915_gem_object_finish_gtt(obj);
3816 /* Before SandyBridge, you could not use tiling or fence
3817 * registers with snooped memory, so relinquish any fences
3818 * currently pointing to our region in the aperture.
3820 if (INTEL_INFO(dev)->gen < 6) {
3821 ret = i915_gem_object_put_fence(obj);
3826 list_for_each_entry(vma, &obj->vma_list, vma_link)
3827 if (drm_mm_node_allocated(&vma->node)) {
3828 ret = i915_vma_bind(vma, cache_level,
3829 vma->bound & GLOBAL_BIND);
3835 list_for_each_entry(vma, &obj->vma_list, vma_link)
3836 vma->node.color = cache_level;
3837 obj->cache_level = cache_level;
3839 if (obj->cache_dirty &&
3840 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3841 cpu_write_needs_clflush(obj)) {
3842 if (i915_gem_clflush_object(obj, true))
3843 i915_gem_chipset_flush(obj->base.dev);
3849 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3850 struct drm_file *file)
3852 struct drm_i915_gem_caching *args = data;
3853 struct drm_i915_gem_object *obj;
3856 ret = i915_mutex_lock_interruptible(dev);
3860 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3861 if (&obj->base == NULL) {
3866 switch (obj->cache_level) {
3867 case I915_CACHE_LLC:
3868 case I915_CACHE_L3_LLC:
3869 args->caching = I915_CACHING_CACHED;
3873 args->caching = I915_CACHING_DISPLAY;
3877 args->caching = I915_CACHING_NONE;
3881 drm_gem_object_unreference(&obj->base);
3883 mutex_unlock(&dev->struct_mutex);
3887 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3888 struct drm_file *file)
3890 struct drm_i915_gem_caching *args = data;
3891 struct drm_i915_gem_object *obj;
3892 enum i915_cache_level level;
3895 switch (args->caching) {
3896 case I915_CACHING_NONE:
3897 level = I915_CACHE_NONE;
3899 case I915_CACHING_CACHED:
3900 level = I915_CACHE_LLC;
3902 case I915_CACHING_DISPLAY:
3903 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3909 ret = i915_mutex_lock_interruptible(dev);
3913 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3914 if (&obj->base == NULL) {
3919 ret = i915_gem_object_set_cache_level(obj, level);
3921 drm_gem_object_unreference(&obj->base);
3923 mutex_unlock(&dev->struct_mutex);
3927 static bool is_pin_display(struct drm_i915_gem_object *obj)
3929 struct i915_vma *vma;
3931 vma = i915_gem_obj_to_ggtt(obj);
3935 /* There are 2 sources that pin objects:
3936 * 1. The display engine (scanouts, sprites, cursors);
3937 * 2. Reservations for execbuffer;
3939 * We can ignore reservations as we hold the struct_mutex and
3940 * are only called outside of the reservation path.
3942 return vma->pin_count;
3946 * Prepare buffer for display plane (scanout, cursors, etc).
3947 * Can be called from an uninterruptible phase (modesetting) and allows
3948 * any flushes to be pipelined (for pageflips).
3951 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3953 struct intel_engine_cs *pipelined)
3955 u32 old_read_domains, old_write_domain;
3956 bool was_pin_display;
3959 if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
3960 ret = i915_gem_object_sync(obj, pipelined);
3965 /* Mark the pin_display early so that we account for the
3966 * display coherency whilst setting up the cache domains.
3968 was_pin_display = obj->pin_display;
3969 obj->pin_display = true;
3971 /* The display engine is not coherent with the LLC cache on gen6. As
3972 * a result, we make sure that the pinning that is about to occur is
3973 * done with uncached PTEs. This is lowest common denominator for all
3976 * However for gen6+, we could do better by using the GFDT bit instead
3977 * of uncaching, which would allow us to flush all the LLC-cached data
3978 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3980 ret = i915_gem_object_set_cache_level(obj,
3981 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3983 goto err_unpin_display;
3985 /* As the user may map the buffer once pinned in the display plane
3986 * (e.g. libkms for the bootup splash), we have to ensure that we
3987 * always use map_and_fenceable for all scanout buffers.
3989 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3991 goto err_unpin_display;
3993 i915_gem_object_flush_cpu_write_domain(obj);
3995 old_write_domain = obj->base.write_domain;
3996 old_read_domains = obj->base.read_domains;
3998 /* It should now be out of any other write domains, and we can update
3999 * the domain values for our changes.
4001 obj->base.write_domain = 0;
4002 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4004 trace_i915_gem_object_change_domain(obj,
4011 WARN_ON(was_pin_display != is_pin_display(obj));
4012 obj->pin_display = was_pin_display;
4017 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
4019 i915_gem_object_ggtt_unpin(obj);
4020 obj->pin_display = is_pin_display(obj);
4024 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4028 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4031 ret = i915_gem_object_wait_rendering(obj, false);
4035 /* Ensure that we invalidate the GPU's caches and TLBs. */
4036 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4041 * Moves a single object to the CPU read, and possibly write domain.
4043 * This function returns when the move is complete, including waiting on
4047 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4049 uint32_t old_write_domain, old_read_domains;
4052 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4055 ret = i915_gem_object_wait_rendering(obj, !write);
4059 i915_gem_object_retire(obj);
4060 i915_gem_object_flush_gtt_write_domain(obj);
4062 old_write_domain = obj->base.write_domain;
4063 old_read_domains = obj->base.read_domains;
4065 /* Flush the CPU cache if it's still invalid. */
4066 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4067 i915_gem_clflush_object(obj, false);
4069 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4072 /* It should now be out of any other write domains, and we can update
4073 * the domain values for our changes.
4075 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4077 /* If we're writing through the CPU, then the GPU read domains will
4078 * need to be invalidated at next use.
4081 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4082 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4086 intel_fb_obj_invalidate(obj, NULL);
4088 trace_i915_gem_object_change_domain(obj,
4095 /* Throttle our rendering by waiting until the ring has completed our requests
4096 * emitted over 20 msec ago.
4098 * Note that if we were to use the current jiffies each time around the loop,
4099 * we wouldn't escape the function with any frames outstanding if the time to
4100 * render a frame was over 20ms.
4102 * This should get us reasonable parallelism between CPU and GPU but also
4103 * relatively low latency when blocking on a particular request to finish.
4106 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109 struct drm_i915_file_private *file_priv = file->driver_priv;
4110 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4111 struct drm_i915_gem_request *request, *target = NULL;
4112 unsigned reset_counter;
4115 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4119 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4123 spin_lock(&file_priv->mm.lock);
4124 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4125 if (time_after_eq(request->emitted_jiffies, recent_enough))
4130 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4132 i915_gem_request_reference(target);
4133 spin_unlock(&file_priv->mm.lock);
4138 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4140 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4142 mutex_lock(&dev->struct_mutex);
4143 i915_gem_request_unreference(target);
4144 mutex_unlock(&dev->struct_mutex);
4150 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4152 struct drm_i915_gem_object *obj = vma->obj;
4155 vma->node.start & (alignment - 1))
4158 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4161 if (flags & PIN_OFFSET_BIAS &&
4162 vma->node.start < (flags & PIN_OFFSET_MASK))
4169 i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
4170 struct i915_address_space *vm,
4173 const struct i915_ggtt_view *view)
4175 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4176 struct i915_vma *vma;
4180 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4183 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4186 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4189 vma = i915_gem_obj_to_vma_view(obj, vm, view);
4191 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4194 if (i915_vma_misplaced(vma, alignment, flags)) {
4195 WARN(vma->pin_count,
4196 "bo is already pinned with incorrect alignment:"
4197 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4198 " obj->map_and_fenceable=%d\n",
4199 i915_gem_obj_offset_view(obj, vm, view->type),
4201 !!(flags & PIN_MAPPABLE),
4202 obj->map_and_fenceable);
4203 ret = i915_vma_unbind(vma);
4211 bound = vma ? vma->bound : 0;
4212 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4213 vma = i915_gem_object_bind_to_vm(obj, vm, alignment,
4216 return PTR_ERR(vma);
4219 if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) {
4220 ret = i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND);
4225 if ((bound ^ vma->bound) & GLOBAL_BIND) {
4226 bool mappable, fenceable;
4227 u32 fence_size, fence_alignment;
4229 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4232 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4237 fenceable = (vma->node.size == fence_size &&
4238 (vma->node.start & (fence_alignment - 1)) == 0);
4240 mappable = (vma->node.start + obj->base.size <=
4241 dev_priv->gtt.mappable_end);
4243 obj->map_and_fenceable = mappable && fenceable;
4246 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4249 if (flags & PIN_MAPPABLE)
4250 obj->pin_mappable |= true;
4256 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4258 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4261 BUG_ON(vma->pin_count == 0);
4262 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4264 if (--vma->pin_count == 0)
4265 obj->pin_mappable = false;
4269 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4271 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4272 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4273 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4275 WARN_ON(!ggtt_vma ||
4276 dev_priv->fence_regs[obj->fence_reg].pin_count >
4277 ggtt_vma->pin_count);
4278 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4285 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4287 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4288 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4289 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4290 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4295 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4296 struct drm_file *file)
4298 struct drm_i915_gem_busy *args = data;
4299 struct drm_i915_gem_object *obj;
4302 ret = i915_mutex_lock_interruptible(dev);
4306 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4307 if (&obj->base == NULL) {
4312 /* Count all active objects as busy, even if they are currently not used
4313 * by the gpu. Users of this interface expect objects to eventually
4314 * become non-busy without any further actions, therefore emit any
4315 * necessary flushes here.
4317 ret = i915_gem_object_flush_active(obj);
4319 args->busy = obj->active;
4320 if (obj->last_read_req) {
4321 struct intel_engine_cs *ring;
4322 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4323 ring = i915_gem_request_get_ring(obj->last_read_req);
4324 args->busy |= intel_ring_flag(ring) << 16;
4327 drm_gem_object_unreference(&obj->base);
4329 mutex_unlock(&dev->struct_mutex);
4334 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4335 struct drm_file *file_priv)
4337 return i915_gem_ring_throttle(dev, file_priv);
4341 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4342 struct drm_file *file_priv)
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345 struct drm_i915_gem_madvise *args = data;
4346 struct drm_i915_gem_object *obj;
4349 switch (args->madv) {
4350 case I915_MADV_DONTNEED:
4351 case I915_MADV_WILLNEED:
4357 ret = i915_mutex_lock_interruptible(dev);
4361 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4362 if (&obj->base == NULL) {
4367 if (i915_gem_obj_is_pinned(obj)) {
4373 obj->tiling_mode != I915_TILING_NONE &&
4374 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4375 if (obj->madv == I915_MADV_WILLNEED)
4376 i915_gem_object_unpin_pages(obj);
4377 if (args->madv == I915_MADV_WILLNEED)
4378 i915_gem_object_pin_pages(obj);
4381 if (obj->madv != __I915_MADV_PURGED)
4382 obj->madv = args->madv;
4384 /* if the object is no longer attached, discard its backing storage */
4385 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4386 i915_gem_object_truncate(obj);
4388 args->retained = obj->madv != __I915_MADV_PURGED;
4391 drm_gem_object_unreference(&obj->base);
4393 mutex_unlock(&dev->struct_mutex);
4397 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4398 const struct drm_i915_gem_object_ops *ops)
4400 INIT_LIST_HEAD(&obj->global_list);
4401 INIT_LIST_HEAD(&obj->ring_list);
4402 INIT_LIST_HEAD(&obj->obj_exec_link);
4403 INIT_LIST_HEAD(&obj->vma_list);
4404 INIT_LIST_HEAD(&obj->batch_pool_list);
4408 obj->fence_reg = I915_FENCE_REG_NONE;
4409 obj->madv = I915_MADV_WILLNEED;
4411 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4414 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4415 .get_pages = i915_gem_object_get_pages_gtt,
4416 .put_pages = i915_gem_object_put_pages_gtt,
4419 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4422 struct drm_i915_gem_object *obj;
4423 struct address_space *mapping;
4426 obj = i915_gem_object_alloc(dev);
4430 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4431 i915_gem_object_free(obj);
4435 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4436 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4437 /* 965gm cannot relocate objects above 4GiB. */
4438 mask &= ~__GFP_HIGHMEM;
4439 mask |= __GFP_DMA32;
4442 mapping = file_inode(obj->base.filp)->i_mapping;
4443 mapping_set_gfp_mask(mapping, mask);
4445 i915_gem_object_init(obj, &i915_gem_object_ops);
4447 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4448 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4451 /* On some devices, we can have the GPU use the LLC (the CPU
4452 * cache) for about a 10% performance improvement
4453 * compared to uncached. Graphics requests other than
4454 * display scanout are coherent with the CPU in
4455 * accessing this cache. This means in this mode we
4456 * don't need to clflush on the CPU side, and on the
4457 * GPU side we only need to flush internal caches to
4458 * get data visible to the CPU.
4460 * However, we maintain the display planes as UC, and so
4461 * need to rebind when first used as such.
4463 obj->cache_level = I915_CACHE_LLC;
4465 obj->cache_level = I915_CACHE_NONE;
4467 trace_i915_gem_object_create(obj);
4472 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4474 /* If we are the last user of the backing storage (be it shmemfs
4475 * pages or stolen etc), we know that the pages are going to be
4476 * immediately released. In this case, we can then skip copying
4477 * back the contents from the GPU.
4480 if (obj->madv != I915_MADV_WILLNEED)
4483 if (obj->base.filp == NULL)
4486 /* At first glance, this looks racy, but then again so would be
4487 * userspace racing mmap against close. However, the first external
4488 * reference to the filp can only be obtained through the
4489 * i915_gem_mmap_ioctl() which safeguards us against the user
4490 * acquiring such a reference whilst we are in the middle of
4491 * freeing the object.
4493 return atomic_long_read(&obj->base.filp->f_count) == 1;
4496 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4498 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4499 struct drm_device *dev = obj->base.dev;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 struct i915_vma *vma, *next;
4503 intel_runtime_pm_get(dev_priv);
4505 trace_i915_gem_object_destroy(obj);
4507 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4511 ret = i915_vma_unbind(vma);
4512 if (WARN_ON(ret == -ERESTARTSYS)) {
4513 bool was_interruptible;
4515 was_interruptible = dev_priv->mm.interruptible;
4516 dev_priv->mm.interruptible = false;
4518 WARN_ON(i915_vma_unbind(vma));
4520 dev_priv->mm.interruptible = was_interruptible;
4524 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4525 * before progressing. */
4527 i915_gem_object_unpin_pages(obj);
4529 WARN_ON(obj->frontbuffer_bits);
4531 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4532 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4533 obj->tiling_mode != I915_TILING_NONE)
4534 i915_gem_object_unpin_pages(obj);
4536 if (WARN_ON(obj->pages_pin_count))
4537 obj->pages_pin_count = 0;
4538 if (discard_backing_storage(obj))
4539 obj->madv = I915_MADV_DONTNEED;
4540 i915_gem_object_put_pages(obj);
4541 i915_gem_object_free_mmap_offset(obj);
4545 if (obj->base.import_attach)
4546 drm_prime_gem_destroy(&obj->base, NULL);
4548 if (obj->ops->release)
4549 obj->ops->release(obj);
4551 drm_gem_object_release(&obj->base);
4552 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4555 i915_gem_object_free(obj);
4557 intel_runtime_pm_put(dev_priv);
4560 struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
4561 struct i915_address_space *vm,
4562 const struct i915_ggtt_view *view)
4564 struct i915_vma *vma;
4565 list_for_each_entry(vma, &obj->vma_list, vma_link)
4566 if (vma->vm == vm && vma->ggtt_view.type == view->type)
4572 void i915_gem_vma_destroy(struct i915_vma *vma)
4574 struct i915_address_space *vm = NULL;
4575 WARN_ON(vma->node.allocated);
4577 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4578 if (!list_empty(&vma->exec_list))
4583 if (!i915_is_ggtt(vm))
4584 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4586 list_del(&vma->vma_link);
4592 i915_gem_stop_ringbuffers(struct drm_device *dev)
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 struct intel_engine_cs *ring;
4598 for_each_ring(ring, dev_priv, i)
4599 dev_priv->gt.stop_ring(ring);
4603 i915_gem_suspend(struct drm_device *dev)
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4608 mutex_lock(&dev->struct_mutex);
4609 ret = i915_gpu_idle(dev);
4613 i915_gem_retire_requests(dev);
4615 /* Under UMS, be paranoid and evict. */
4616 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4617 i915_gem_evict_everything(dev);
4619 i915_gem_stop_ringbuffers(dev);
4620 mutex_unlock(&dev->struct_mutex);
4622 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4623 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4624 flush_delayed_work(&dev_priv->mm.idle_work);
4626 /* Assert that we sucessfully flushed all the work and
4627 * reset the GPU back to its idle, low power state.
4629 WARN_ON(dev_priv->mm.busy);
4634 mutex_unlock(&dev->struct_mutex);
4638 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4640 struct drm_device *dev = ring->dev;
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4642 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4643 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4646 if (!HAS_L3_DPF(dev) || !remap_info)
4649 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4654 * Note: We do not worry about the concurrent register cacheline hang
4655 * here because no other code should access these registers other than
4656 * at initialization time.
4658 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4659 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4660 intel_ring_emit(ring, reg_base + i);
4661 intel_ring_emit(ring, remap_info[i/4]);
4664 intel_ring_advance(ring);
4669 void i915_gem_init_swizzling(struct drm_device *dev)
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4673 if (INTEL_INFO(dev)->gen < 5 ||
4674 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4677 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4678 DISP_TILE_SURFACE_SWIZZLING);
4683 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4685 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4686 else if (IS_GEN7(dev))
4687 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4688 else if (IS_GEN8(dev))
4689 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4695 intel_enable_blt(struct drm_device *dev)
4700 /* The blitter was dysfunctional on early prototypes */
4701 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4702 DRM_INFO("BLT not supported on this pre-production hardware;"
4703 " graphics performance will be degraded.\n");
4710 static void init_unused_ring(struct drm_device *dev, u32 base)
4712 struct drm_i915_private *dev_priv = dev->dev_private;
4714 I915_WRITE(RING_CTL(base), 0);
4715 I915_WRITE(RING_HEAD(base), 0);
4716 I915_WRITE(RING_TAIL(base), 0);
4717 I915_WRITE(RING_START(base), 0);
4720 static void init_unused_rings(struct drm_device *dev)
4723 init_unused_ring(dev, PRB1_BASE);
4724 init_unused_ring(dev, SRB0_BASE);
4725 init_unused_ring(dev, SRB1_BASE);
4726 init_unused_ring(dev, SRB2_BASE);
4727 init_unused_ring(dev, SRB3_BASE);
4728 } else if (IS_GEN2(dev)) {
4729 init_unused_ring(dev, SRB0_BASE);
4730 init_unused_ring(dev, SRB1_BASE);
4731 } else if (IS_GEN3(dev)) {
4732 init_unused_ring(dev, PRB1_BASE);
4733 init_unused_ring(dev, PRB2_BASE);
4737 int i915_gem_init_rings(struct drm_device *dev)
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4742 ret = intel_init_render_ring_buffer(dev);
4747 ret = intel_init_bsd_ring_buffer(dev);
4749 goto cleanup_render_ring;
4752 if (intel_enable_blt(dev)) {
4753 ret = intel_init_blt_ring_buffer(dev);
4755 goto cleanup_bsd_ring;
4758 if (HAS_VEBOX(dev)) {
4759 ret = intel_init_vebox_ring_buffer(dev);
4761 goto cleanup_blt_ring;
4764 if (HAS_BSD2(dev)) {
4765 ret = intel_init_bsd2_ring_buffer(dev);
4767 goto cleanup_vebox_ring;
4770 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4772 goto cleanup_bsd2_ring;
4777 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4779 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4781 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4783 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4784 cleanup_render_ring:
4785 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4791 i915_gem_init_hw(struct drm_device *dev)
4793 struct drm_i915_private *dev_priv = dev->dev_private;
4794 struct intel_engine_cs *ring;
4797 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4800 /* Double layer security blanket, see i915_gem_init() */
4801 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4803 if (dev_priv->ellc_size)
4804 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4806 if (IS_HASWELL(dev))
4807 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4808 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4810 if (HAS_PCH_NOP(dev)) {
4811 if (IS_IVYBRIDGE(dev)) {
4812 u32 temp = I915_READ(GEN7_MSG_CTL);
4813 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4814 I915_WRITE(GEN7_MSG_CTL, temp);
4815 } else if (INTEL_INFO(dev)->gen >= 7) {
4816 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4817 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4818 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4822 i915_gem_init_swizzling(dev);
4825 * At least 830 can leave some of the unused rings
4826 * "active" (ie. head != tail) after resume which
4827 * will prevent c3 entry. Makes sure all unused rings
4830 init_unused_rings(dev);
4832 for_each_ring(ring, dev_priv, i) {
4833 ret = ring->init_hw(ring);
4838 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4839 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4841 ret = i915_ppgtt_init_hw(dev);
4842 if (ret && ret != -EIO) {
4843 DRM_ERROR("PPGTT enable failed %d\n", ret);
4844 i915_gem_cleanup_ringbuffer(dev);
4847 ret = i915_gem_context_enable(dev_priv);
4848 if (ret && ret != -EIO) {
4849 DRM_ERROR("Context enable failed %d\n", ret);
4850 i915_gem_cleanup_ringbuffer(dev);
4856 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4860 int i915_gem_init(struct drm_device *dev)
4862 struct drm_i915_private *dev_priv = dev->dev_private;
4865 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4866 i915.enable_execlists);
4868 mutex_lock(&dev->struct_mutex);
4870 if (IS_VALLEYVIEW(dev)) {
4871 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4872 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4873 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4874 VLV_GTLC_ALLOWWAKEACK), 10))
4875 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4878 if (!i915.enable_execlists) {
4879 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4880 dev_priv->gt.init_rings = i915_gem_init_rings;
4881 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4882 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4884 dev_priv->gt.do_execbuf = intel_execlists_submission;
4885 dev_priv->gt.init_rings = intel_logical_rings_init;
4886 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4887 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4890 /* This is just a security blanket to placate dragons.
4891 * On some systems, we very sporadically observe that the first TLBs
4892 * used by the CS may be stale, despite us poking the TLB reset. If
4893 * we hold the forcewake during initialisation these problems
4894 * just magically go away.
4896 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4898 ret = i915_gem_init_userptr(dev);
4902 i915_gem_init_global_gtt(dev);
4904 ret = i915_gem_context_init(dev);
4908 ret = dev_priv->gt.init_rings(dev);
4912 ret = i915_gem_init_hw(dev);
4914 /* Allow ring initialisation to fail by marking the GPU as
4915 * wedged. But we only want to do this where the GPU is angry,
4916 * for all other failure, such as an allocation failure, bail.
4918 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4919 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4924 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4925 mutex_unlock(&dev->struct_mutex);
4931 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4933 struct drm_i915_private *dev_priv = dev->dev_private;
4934 struct intel_engine_cs *ring;
4937 for_each_ring(ring, dev_priv, i)
4938 dev_priv->gt.cleanup_ring(ring);
4942 init_ring_lists(struct intel_engine_cs *ring)
4944 INIT_LIST_HEAD(&ring->active_list);
4945 INIT_LIST_HEAD(&ring->request_list);
4948 void i915_init_vm(struct drm_i915_private *dev_priv,
4949 struct i915_address_space *vm)
4951 if (!i915_is_ggtt(vm))
4952 drm_mm_init(&vm->mm, vm->start, vm->total);
4953 vm->dev = dev_priv->dev;
4954 INIT_LIST_HEAD(&vm->active_list);
4955 INIT_LIST_HEAD(&vm->inactive_list);
4956 INIT_LIST_HEAD(&vm->global_link);
4957 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4961 i915_gem_load(struct drm_device *dev)
4963 struct drm_i915_private *dev_priv = dev->dev_private;
4967 kmem_cache_create("i915_gem_object",
4968 sizeof(struct drm_i915_gem_object), 0,
4972 INIT_LIST_HEAD(&dev_priv->vm_list);
4973 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4975 INIT_LIST_HEAD(&dev_priv->context_list);
4976 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4977 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4978 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4979 for (i = 0; i < I915_NUM_RINGS; i++)
4980 init_ring_lists(&dev_priv->ring[i]);
4981 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4982 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4983 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4984 i915_gem_retire_work_handler);
4985 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4986 i915_gem_idle_work_handler);
4987 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4989 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4990 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4991 I915_WRITE(MI_ARB_STATE,
4992 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4995 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4997 /* Old X drivers will take 0-2 for front, back, depth buffers */
4998 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4999 dev_priv->fence_reg_start = 3;
5001 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5002 dev_priv->num_fence_regs = 32;
5003 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5004 dev_priv->num_fence_regs = 16;
5006 dev_priv->num_fence_regs = 8;
5008 /* Initialize fence registers to zero */
5009 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5010 i915_gem_restore_fences(dev);
5012 i915_gem_detect_bit_6_swizzle(dev);
5013 init_waitqueue_head(&dev_priv->pending_flip_queue);
5015 dev_priv->mm.interruptible = true;
5017 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
5018 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
5019 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
5020 register_shrinker(&dev_priv->mm.shrinker);
5022 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
5023 register_oom_notifier(&dev_priv->mm.oom_notifier);
5025 i915_gem_batch_pool_init(dev, &dev_priv->mm.batch_pool);
5027 mutex_init(&dev_priv->fb_tracking.lock);
5030 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5032 struct drm_i915_file_private *file_priv = file->driver_priv;
5034 cancel_delayed_work_sync(&file_priv->mm.idle_work);
5036 /* Clean up our request list when the client is going away, so that
5037 * later retire_requests won't dereference our soon-to-be-gone
5040 spin_lock(&file_priv->mm.lock);
5041 while (!list_empty(&file_priv->mm.request_list)) {
5042 struct drm_i915_gem_request *request;
5044 request = list_first_entry(&file_priv->mm.request_list,
5045 struct drm_i915_gem_request,
5047 list_del(&request->client_list);
5048 request->file_priv = NULL;
5050 spin_unlock(&file_priv->mm.lock);
5054 i915_gem_file_idle_work_handler(struct work_struct *work)
5056 struct drm_i915_file_private *file_priv =
5057 container_of(work, typeof(*file_priv), mm.idle_work.work);
5059 atomic_set(&file_priv->rps_wait_boost, false);
5062 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5064 struct drm_i915_file_private *file_priv;
5067 DRM_DEBUG_DRIVER("\n");
5069 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5073 file->driver_priv = file_priv;
5074 file_priv->dev_priv = dev->dev_private;
5075 file_priv->file = file;
5077 spin_lock_init(&file_priv->mm.lock);
5078 INIT_LIST_HEAD(&file_priv->mm.request_list);
5079 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5080 i915_gem_file_idle_work_handler);
5082 ret = i915_gem_context_open(dev, file);
5090 * i915_gem_track_fb - update frontbuffer tracking
5091 * old: current GEM buffer for the frontbuffer slots
5092 * new: new GEM buffer for the frontbuffer slots
5093 * frontbuffer_bits: bitmask of frontbuffer slots
5095 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5096 * from @old and setting them in @new. Both @old and @new can be NULL.
5098 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5099 struct drm_i915_gem_object *new,
5100 unsigned frontbuffer_bits)
5103 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5104 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5105 old->frontbuffer_bits &= ~frontbuffer_bits;
5109 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5110 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5111 new->frontbuffer_bits |= frontbuffer_bits;
5115 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5117 if (!mutex_is_locked(mutex))
5120 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5121 return mutex->owner == task;
5123 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5128 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5130 if (!mutex_trylock(&dev->struct_mutex)) {
5131 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5134 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5144 static int num_vma_bound(struct drm_i915_gem_object *obj)
5146 struct i915_vma *vma;
5149 list_for_each_entry(vma, &obj->vma_list, vma_link)
5150 if (drm_mm_node_allocated(&vma->node))
5156 static unsigned long
5157 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5159 struct drm_i915_private *dev_priv =
5160 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5161 struct drm_device *dev = dev_priv->dev;
5162 struct drm_i915_gem_object *obj;
5163 unsigned long count;
5166 if (!i915_gem_shrinker_lock(dev, &unlock))
5170 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5171 if (obj->pages_pin_count == 0)
5172 count += obj->base.size >> PAGE_SHIFT;
5174 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5175 if (!i915_gem_obj_is_pinned(obj) &&
5176 obj->pages_pin_count == num_vma_bound(obj))
5177 count += obj->base.size >> PAGE_SHIFT;
5181 mutex_unlock(&dev->struct_mutex);
5186 /* All the new VM stuff */
5187 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
5188 struct i915_address_space *vm,
5189 enum i915_ggtt_view_type view)
5191 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5192 struct i915_vma *vma;
5194 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5196 list_for_each_entry(vma, &o->vma_list, vma_link) {
5197 if (vma->vm == vm && vma->ggtt_view.type == view)
5198 return vma->node.start;
5201 WARN(1, "%s vma for this object not found.\n",
5202 i915_is_ggtt(vm) ? "global" : "ppgtt");
5206 bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
5207 struct i915_address_space *vm,
5208 enum i915_ggtt_view_type view)
5210 struct i915_vma *vma;
5212 list_for_each_entry(vma, &o->vma_list, vma_link)
5213 if (vma->vm == vm &&
5214 vma->ggtt_view.type == view &&
5215 drm_mm_node_allocated(&vma->node))
5221 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5223 struct i915_vma *vma;
5225 list_for_each_entry(vma, &o->vma_list, vma_link)
5226 if (drm_mm_node_allocated(&vma->node))
5232 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5233 struct i915_address_space *vm)
5235 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5236 struct i915_vma *vma;
5238 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5240 BUG_ON(list_empty(&o->vma_list));
5242 list_for_each_entry(vma, &o->vma_list, vma_link)
5244 return vma->node.size;
5249 static unsigned long
5250 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5252 struct drm_i915_private *dev_priv =
5253 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5254 struct drm_device *dev = dev_priv->dev;
5255 unsigned long freed;
5258 if (!i915_gem_shrinker_lock(dev, &unlock))
5261 freed = i915_gem_shrink(dev_priv,
5264 I915_SHRINK_UNBOUND |
5265 I915_SHRINK_PURGEABLE);
5266 if (freed < sc->nr_to_scan)
5267 freed += i915_gem_shrink(dev_priv,
5268 sc->nr_to_scan - freed,
5270 I915_SHRINK_UNBOUND);
5272 mutex_unlock(&dev->struct_mutex);
5278 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5280 struct drm_i915_private *dev_priv =
5281 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5282 struct drm_device *dev = dev_priv->dev;
5283 struct drm_i915_gem_object *obj;
5284 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5285 unsigned long pinned, bound, unbound, freed_pages;
5286 bool was_interruptible;
5289 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5290 schedule_timeout_killable(1);
5291 if (fatal_signal_pending(current))
5295 pr_err("Unable to purge GPU memory due lock contention.\n");
5299 was_interruptible = dev_priv->mm.interruptible;
5300 dev_priv->mm.interruptible = false;
5302 freed_pages = i915_gem_shrink_all(dev_priv);
5304 dev_priv->mm.interruptible = was_interruptible;
5306 /* Because we may be allocating inside our own driver, we cannot
5307 * assert that there are no objects with pinned pages that are not
5308 * being pointed to by hardware.
5310 unbound = bound = pinned = 0;
5311 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5312 if (!obj->base.filp) /* not backed by a freeable object */
5315 if (obj->pages_pin_count)
5316 pinned += obj->base.size;
5318 unbound += obj->base.size;
5320 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5321 if (!obj->base.filp)
5324 if (obj->pages_pin_count)
5325 pinned += obj->base.size;
5327 bound += obj->base.size;
5331 mutex_unlock(&dev->struct_mutex);
5333 if (freed_pages || unbound || bound)
5334 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5335 freed_pages << PAGE_SHIFT, pinned);
5336 if (unbound || bound)
5337 pr_err("%lu and %lu bytes still available in the "
5338 "bound and unbound GPU page lists.\n",
5341 *(unsigned long *)ptr += freed_pages;
5345 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5347 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
5348 struct i915_vma *vma;
5350 list_for_each_entry(vma, &obj->vma_list, vma_link)
5351 if (vma->vm == ggtt &&
5352 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)