2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
46 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
48 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
49 static void i915_gem_write_fence(struct drm_device *dev, int reg,
50 struct drm_i915_gem_object *obj);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
52 struct drm_i915_fence_reg *fence,
55 static bool cpu_cache_is_coherent(struct drm_device *dev,
56 enum i915_cache_level level)
58 return HAS_LLC(dev) || level != I915_CACHE_NONE;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
63 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
66 return obj->pin_display;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
72 i915_gem_release_mmap(obj);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj->fence_dirty = false;
78 obj->fence_reg = I915_FENCE_REG_NONE;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
85 spin_lock(&dev_priv->mm.object_stat_lock);
86 dev_priv->mm.object_count++;
87 dev_priv->mm.object_memory += size;
88 spin_unlock(&dev_priv->mm.object_stat_lock);
91 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
94 spin_lock(&dev_priv->mm.object_stat_lock);
95 dev_priv->mm.object_count--;
96 dev_priv->mm.object_memory -= size;
97 spin_unlock(&dev_priv->mm.object_stat_lock);
101 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret = wait_event_interruptible_timeout(error->reset_queue,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret < 0) {
129 int i915_mutex_lock_interruptible(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
134 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
138 ret = mutex_lock_interruptible(&dev->struct_mutex);
142 WARN_ON(i915_verify_lists(dev));
147 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_i915_gem_get_aperture *args = data;
152 struct drm_i915_gem_object *obj;
156 mutex_lock(&dev->struct_mutex);
157 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
158 if (i915_gem_obj_is_pinned(obj))
159 pinned += i915_gem_obj_ggtt_size(obj);
160 mutex_unlock(&dev->struct_mutex);
162 args->aper_size = dev_priv->gtt.base.total;
163 args->aper_available_size = args->aper_size - pinned;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
171 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
172 char *vaddr = obj->phys_handle->vaddr;
174 struct scatterlist *sg;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
180 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
184 page = shmem_read_mapping_page(mapping, i);
186 return PTR_ERR(page);
188 src = kmap_atomic(page);
189 memcpy(vaddr, src, PAGE_SIZE);
190 drm_clflush_virt_range(vaddr, PAGE_SIZE);
193 page_cache_release(page);
197 i915_gem_chipset_flush(obj->base.dev);
199 st = kmalloc(sizeof(*st), GFP_KERNEL);
203 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
210 sg->length = obj->base.size;
212 sg_dma_address(sg) = obj->phys_handle->busaddr;
213 sg_dma_len(sg) = obj->base.size;
216 obj->has_dma_mapping = true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
225 BUG_ON(obj->madv == __I915_MADV_PURGED);
227 ret = i915_gem_object_set_to_cpu_domain(obj, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret != -EIO);
233 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
236 if (obj->madv == I915_MADV_DONTNEED)
240 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
241 char *vaddr = obj->phys_handle->vaddr;
244 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
248 page = shmem_read_mapping_page(mapping, i);
252 dst = kmap_atomic(page);
253 drm_clflush_virt_range(vaddr, PAGE_SIZE);
254 memcpy(dst, vaddr, PAGE_SIZE);
257 set_page_dirty(page);
258 if (obj->madv == I915_MADV_WILLNEED)
259 mark_page_accessed(page);
260 page_cache_release(page);
266 sg_free_table(obj->pages);
269 obj->has_dma_mapping = false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
275 drm_pci_free(obj->base.dev, obj->phys_handle);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
279 .get_pages = i915_gem_object_get_pages_phys,
280 .put_pages = i915_gem_object_put_pages_phys,
281 .release = i915_gem_object_release_phys,
285 drop_pages(struct drm_i915_gem_object *obj)
287 struct i915_vma *vma, *next;
290 drm_gem_object_reference(&obj->base);
291 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
292 if (i915_vma_unbind(vma))
295 ret = i915_gem_object_put_pages(obj);
296 drm_gem_object_unreference(&obj->base);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
305 drm_dma_handle_t *phys;
308 if (obj->phys_handle) {
309 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
315 if (obj->madv != I915_MADV_WILLNEED)
318 if (obj->base.filp == NULL)
321 ret = drop_pages(obj);
325 /* create a new object */
326 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
330 obj->phys_handle = phys;
331 obj->ops = &i915_gem_phys_ops;
333 return i915_gem_object_get_pages(obj);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
338 struct drm_i915_gem_pwrite *args,
339 struct drm_file *file_priv)
341 struct drm_device *dev = obj->base.dev;
342 void *vaddr = obj->phys_handle->vaddr + args->offset;
343 char __user *user_data = to_user_ptr(args->data_ptr);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret = i915_gem_object_wait_rendering(obj, false);
353 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
354 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
355 unsigned long unwritten;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev->struct_mutex);
362 unwritten = copy_from_user(vaddr, user_data, args->size);
363 mutex_lock(&dev->struct_mutex);
370 drm_clflush_virt_range(vaddr, args->size);
371 i915_gem_chipset_flush(dev);
374 intel_fb_obj_flush(obj, false);
378 void *i915_gem_object_alloc(struct drm_device *dev)
380 struct drm_i915_private *dev_priv = dev->dev_private;
381 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
384 void i915_gem_object_free(struct drm_i915_gem_object *obj)
386 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
387 kmem_cache_free(dev_priv->objects, obj);
391 i915_gem_create(struct drm_file *file,
392 struct drm_device *dev,
396 struct drm_i915_gem_object *obj;
400 size = roundup(size, PAGE_SIZE);
404 /* Allocate the new object */
405 obj = i915_gem_alloc_object(dev, size);
409 ret = drm_gem_handle_create(file, &obj->base, &handle);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj->base);
420 i915_gem_dumb_create(struct drm_file *file,
421 struct drm_device *dev,
422 struct drm_mode_create_dumb *args)
424 /* have to work out size/pitch and return them */
425 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
426 args->size = args->pitch * args->height;
427 return i915_gem_create(file, dev,
428 args->size, &args->handle);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device *dev, void *data,
436 struct drm_file *file)
438 struct drm_i915_gem_create *args = data;
440 return i915_gem_create(file, dev,
441 args->size, &args->handle);
445 __copy_to_user_swizzled(char __user *cpu_vaddr,
446 const char *gpu_vaddr, int gpu_offset,
449 int ret, cpu_offset = 0;
452 int cacheline_end = ALIGN(gpu_offset + 1, 64);
453 int this_length = min(cacheline_end - gpu_offset, length);
454 int swizzled_gpu_offset = gpu_offset ^ 64;
456 ret = __copy_to_user(cpu_vaddr + cpu_offset,
457 gpu_vaddr + swizzled_gpu_offset,
462 cpu_offset += this_length;
463 gpu_offset += this_length;
464 length -= this_length;
471 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
472 const char __user *cpu_vaddr,
475 int ret, cpu_offset = 0;
478 int cacheline_end = ALIGN(gpu_offset + 1, 64);
479 int this_length = min(cacheline_end - gpu_offset, length);
480 int swizzled_gpu_offset = gpu_offset ^ 64;
482 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
483 cpu_vaddr + cpu_offset,
488 cpu_offset += this_length;
489 gpu_offset += this_length;
490 length -= this_length;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
511 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
518 ret = i915_gem_object_wait_rendering(obj, true);
523 ret = i915_gem_object_get_pages(obj);
527 i915_gem_object_pin_pages(obj);
532 /* Per-page copy function for the shmem pread fastpath.
533 * Flushes invalid cachelines before reading the target if
534 * needs_clflush is set. */
536 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
537 char __user *user_data,
538 bool page_do_bit17_swizzling, bool needs_clflush)
543 if (unlikely(page_do_bit17_swizzling))
546 vaddr = kmap_atomic(page);
548 drm_clflush_virt_range(vaddr + shmem_page_offset,
550 ret = __copy_to_user_inatomic(user_data,
551 vaddr + shmem_page_offset,
553 kunmap_atomic(vaddr);
555 return ret ? -EFAULT : 0;
559 shmem_clflush_swizzled_range(char *addr, unsigned long length,
562 if (unlikely(swizzled)) {
563 unsigned long start = (unsigned long) addr;
564 unsigned long end = (unsigned long) addr + length;
566 /* For swizzling simply ensure that we always flush both
567 * channels. Lame, but simple and it works. Swizzled
568 * pwrite/pread is far from a hotpath - current userspace
569 * doesn't use it at all. */
570 start = round_down(start, 128);
571 end = round_up(end, 128);
573 drm_clflush_virt_range((void *)start, end - start);
575 drm_clflush_virt_range(addr, length);
580 /* Only difference to the fast-path function is that this can handle bit17
581 * and uses non-atomic copy and kmap functions. */
583 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
584 char __user *user_data,
585 bool page_do_bit17_swizzling, bool needs_clflush)
592 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
594 page_do_bit17_swizzling);
596 if (page_do_bit17_swizzling)
597 ret = __copy_to_user_swizzled(user_data,
598 vaddr, shmem_page_offset,
601 ret = __copy_to_user(user_data,
602 vaddr + shmem_page_offset,
606 return ret ? - EFAULT : 0;
610 i915_gem_shmem_pread(struct drm_device *dev,
611 struct drm_i915_gem_object *obj,
612 struct drm_i915_gem_pread *args,
613 struct drm_file *file)
615 char __user *user_data;
618 int shmem_page_offset, page_length, ret = 0;
619 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
621 int needs_clflush = 0;
622 struct sg_page_iter sg_iter;
624 user_data = to_user_ptr(args->data_ptr);
627 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
629 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
633 offset = args->offset;
635 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
636 offset >> PAGE_SHIFT) {
637 struct page *page = sg_page_iter_page(&sg_iter);
642 /* Operation in this page
644 * shmem_page_offset = offset within page in shmem file
645 * page_length = bytes to copy for this page
647 shmem_page_offset = offset_in_page(offset);
648 page_length = remain;
649 if ((shmem_page_offset + page_length) > PAGE_SIZE)
650 page_length = PAGE_SIZE - shmem_page_offset;
652 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
653 (page_to_phys(page) & (1 << 17)) != 0;
655 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
656 user_data, page_do_bit17_swizzling,
661 mutex_unlock(&dev->struct_mutex);
663 if (likely(!i915.prefault_disable) && !prefaulted) {
664 ret = fault_in_multipages_writeable(user_data, remain);
665 /* Userspace is tricking us, but we've already clobbered
666 * its pages with the prefault and promised to write the
667 * data up to the first fault. Hence ignore any errors
668 * and just continue. */
673 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
674 user_data, page_do_bit17_swizzling,
677 mutex_lock(&dev->struct_mutex);
683 remain -= page_length;
684 user_data += page_length;
685 offset += page_length;
689 i915_gem_object_unpin_pages(obj);
695 * Reads data from the object referenced by handle.
697 * On error, the contents of *data are undefined.
700 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
701 struct drm_file *file)
703 struct drm_i915_gem_pread *args = data;
704 struct drm_i915_gem_object *obj;
710 if (!access_ok(VERIFY_WRITE,
711 to_user_ptr(args->data_ptr),
715 ret = i915_mutex_lock_interruptible(dev);
719 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
720 if (&obj->base == NULL) {
725 /* Bounds check source. */
726 if (args->offset > obj->base.size ||
727 args->size > obj->base.size - args->offset) {
732 /* prime objects have no backing filp to GEM pread/pwrite
735 if (!obj->base.filp) {
740 trace_i915_gem_object_pread(obj, args->offset, args->size);
742 ret = i915_gem_shmem_pread(dev, obj, args, file);
745 drm_gem_object_unreference(&obj->base);
747 mutex_unlock(&dev->struct_mutex);
751 /* This is the fast write path which cannot handle
752 * page faults in the source data
756 fast_user_write(struct io_mapping *mapping,
757 loff_t page_base, int page_offset,
758 char __user *user_data,
761 void __iomem *vaddr_atomic;
763 unsigned long unwritten;
765 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
766 /* We can use the cpu mem copy function because this is X86. */
767 vaddr = (void __force*)vaddr_atomic + page_offset;
768 unwritten = __copy_from_user_inatomic_nocache(vaddr,
770 io_mapping_unmap_atomic(vaddr_atomic);
775 * This is the fast pwrite path, where we copy the data directly from the
776 * user into the GTT, uncached.
779 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
780 struct drm_i915_gem_object *obj,
781 struct drm_i915_gem_pwrite *args,
782 struct drm_file *file)
784 struct drm_i915_private *dev_priv = dev->dev_private;
786 loff_t offset, page_base;
787 char __user *user_data;
788 int page_offset, page_length, ret;
790 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
794 ret = i915_gem_object_set_to_gtt_domain(obj, true);
798 ret = i915_gem_object_put_fence(obj);
802 user_data = to_user_ptr(args->data_ptr);
805 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
807 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
810 /* Operation in this page
812 * page_base = page offset within aperture
813 * page_offset = offset within page
814 * page_length = bytes to copy for this page
816 page_base = offset & PAGE_MASK;
817 page_offset = offset_in_page(offset);
818 page_length = remain;
819 if ((page_offset + remain) > PAGE_SIZE)
820 page_length = PAGE_SIZE - page_offset;
822 /* If we get a fault while copying data, then (presumably) our
823 * source page isn't available. Return the error and we'll
824 * retry in the slow path.
826 if (fast_user_write(dev_priv->gtt.mappable, page_base,
827 page_offset, user_data, page_length)) {
832 remain -= page_length;
833 user_data += page_length;
834 offset += page_length;
838 intel_fb_obj_flush(obj, false);
840 i915_gem_object_ggtt_unpin(obj);
845 /* Per-page copy function for the shmem pwrite fastpath.
846 * Flushes invalid cachelines before writing to the target if
847 * needs_clflush_before is set and flushes out any written cachelines after
848 * writing if needs_clflush is set. */
850 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
851 char __user *user_data,
852 bool page_do_bit17_swizzling,
853 bool needs_clflush_before,
854 bool needs_clflush_after)
859 if (unlikely(page_do_bit17_swizzling))
862 vaddr = kmap_atomic(page);
863 if (needs_clflush_before)
864 drm_clflush_virt_range(vaddr + shmem_page_offset,
866 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
867 user_data, page_length);
868 if (needs_clflush_after)
869 drm_clflush_virt_range(vaddr + shmem_page_offset,
871 kunmap_atomic(vaddr);
873 return ret ? -EFAULT : 0;
876 /* Only difference to the fast-path function is that this can handle bit17
877 * and uses non-atomic copy and kmap functions. */
879 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
880 char __user *user_data,
881 bool page_do_bit17_swizzling,
882 bool needs_clflush_before,
883 bool needs_clflush_after)
889 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
890 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
892 page_do_bit17_swizzling);
893 if (page_do_bit17_swizzling)
894 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
898 ret = __copy_from_user(vaddr + shmem_page_offset,
901 if (needs_clflush_after)
902 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
904 page_do_bit17_swizzling);
907 return ret ? -EFAULT : 0;
911 i915_gem_shmem_pwrite(struct drm_device *dev,
912 struct drm_i915_gem_object *obj,
913 struct drm_i915_gem_pwrite *args,
914 struct drm_file *file)
918 char __user *user_data;
919 int shmem_page_offset, page_length, ret = 0;
920 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
921 int hit_slowpath = 0;
922 int needs_clflush_after = 0;
923 int needs_clflush_before = 0;
924 struct sg_page_iter sg_iter;
926 user_data = to_user_ptr(args->data_ptr);
929 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
931 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
932 /* If we're not in the cpu write domain, set ourself into the gtt
933 * write domain and manually flush cachelines (if required). This
934 * optimizes for the case when the gpu will use the data
935 * right away and we therefore have to clflush anyway. */
936 needs_clflush_after = cpu_write_needs_clflush(obj);
937 ret = i915_gem_object_wait_rendering(obj, false);
941 /* Same trick applies to invalidate partially written cachelines read
943 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
944 needs_clflush_before =
945 !cpu_cache_is_coherent(dev, obj->cache_level);
947 ret = i915_gem_object_get_pages(obj);
951 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
953 i915_gem_object_pin_pages(obj);
955 offset = args->offset;
958 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
959 offset >> PAGE_SHIFT) {
960 struct page *page = sg_page_iter_page(&sg_iter);
961 int partial_cacheline_write;
966 /* Operation in this page
968 * shmem_page_offset = offset within page in shmem file
969 * page_length = bytes to copy for this page
971 shmem_page_offset = offset_in_page(offset);
973 page_length = remain;
974 if ((shmem_page_offset + page_length) > PAGE_SIZE)
975 page_length = PAGE_SIZE - shmem_page_offset;
977 /* If we don't overwrite a cacheline completely we need to be
978 * careful to have up-to-date data by first clflushing. Don't
979 * overcomplicate things and flush the entire patch. */
980 partial_cacheline_write = needs_clflush_before &&
981 ((shmem_page_offset | page_length)
982 & (boot_cpu_data.x86_clflush_size - 1));
984 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
985 (page_to_phys(page) & (1 << 17)) != 0;
987 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
988 user_data, page_do_bit17_swizzling,
989 partial_cacheline_write,
990 needs_clflush_after);
995 mutex_unlock(&dev->struct_mutex);
996 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
997 user_data, page_do_bit17_swizzling,
998 partial_cacheline_write,
999 needs_clflush_after);
1001 mutex_lock(&dev->struct_mutex);
1007 remain -= page_length;
1008 user_data += page_length;
1009 offset += page_length;
1013 i915_gem_object_unpin_pages(obj);
1017 * Fixup: Flush cpu caches in case we didn't flush the dirty
1018 * cachelines in-line while writing and the object moved
1019 * out of the cpu write domain while we've dropped the lock.
1021 if (!needs_clflush_after &&
1022 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1023 if (i915_gem_clflush_object(obj, obj->pin_display))
1024 i915_gem_chipset_flush(dev);
1028 if (needs_clflush_after)
1029 i915_gem_chipset_flush(dev);
1031 intel_fb_obj_flush(obj, false);
1036 * Writes data to the object referenced by handle.
1038 * On error, the contents of the buffer that were to be modified are undefined.
1041 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1042 struct drm_file *file)
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 struct drm_i915_gem_pwrite *args = data;
1046 struct drm_i915_gem_object *obj;
1049 if (args->size == 0)
1052 if (!access_ok(VERIFY_READ,
1053 to_user_ptr(args->data_ptr),
1057 if (likely(!i915.prefault_disable)) {
1058 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1064 intel_runtime_pm_get(dev_priv);
1066 ret = i915_mutex_lock_interruptible(dev);
1070 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1071 if (&obj->base == NULL) {
1076 /* Bounds check destination. */
1077 if (args->offset > obj->base.size ||
1078 args->size > obj->base.size - args->offset) {
1083 /* prime objects have no backing filp to GEM pread/pwrite
1086 if (!obj->base.filp) {
1091 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1094 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095 * it would end up going through the fenced access, and we'll get
1096 * different detiling behavior between reading and writing.
1097 * pread/pwrite currently are reading and writing from the CPU
1098 * perspective, requiring manual detiling by the client.
1100 if (obj->tiling_mode == I915_TILING_NONE &&
1101 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1102 cpu_write_needs_clflush(obj)) {
1103 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1104 /* Note that the gtt paths might fail with non-page-backed user
1105 * pointers (e.g. gtt mappings when moving data between
1106 * textures). Fallback to the shmem path in that case. */
1109 if (ret == -EFAULT || ret == -ENOSPC) {
1110 if (obj->phys_handle)
1111 ret = i915_gem_phys_pwrite(obj, args, file);
1113 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1117 drm_gem_object_unreference(&obj->base);
1119 mutex_unlock(&dev->struct_mutex);
1121 intel_runtime_pm_put(dev_priv);
1127 i915_gem_check_wedge(struct i915_gpu_error *error,
1130 if (i915_reset_in_progress(error)) {
1131 /* Non-interruptible callers can't handle -EAGAIN, hence return
1132 * -EIO unconditionally for these. */
1136 /* Recovery complete, but the reset failed ... */
1137 if (i915_terminally_wedged(error))
1141 * Check if GPU Reset is in progress - we need intel_ring_begin
1142 * to work properly to reinit the hw state while the gpu is
1143 * still marked as reset-in-progress. Handle this with a flag.
1145 if (!error->reload_in_reset)
1152 static void fake_irq(unsigned long data)
1154 wake_up_process((struct task_struct *)data);
1157 static bool missed_irq(struct drm_i915_private *dev_priv,
1158 struct intel_engine_cs *ring)
1160 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1163 static int __i915_spin_request(struct drm_i915_gem_request *req)
1165 unsigned long timeout;
1167 if (i915_gem_request_get_ring(req)->irq_refcount)
1170 timeout = jiffies + 1;
1171 while (!need_resched()) {
1172 if (i915_gem_request_completed(req, true))
1175 if (time_after_eq(jiffies, timeout))
1178 cpu_relax_lowlatency();
1180 if (i915_gem_request_completed(req, false))
1187 * __i915_wait_request - wait until execution of request has finished
1189 * @reset_counter: reset sequence associated with the given request
1190 * @interruptible: do an interruptible wait (normally yes)
1191 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1193 * Note: It is of utmost importance that the passed in seqno and reset_counter
1194 * values have been read by the caller in an smp safe manner. Where read-side
1195 * locks are involved, it is sufficient to read the reset_counter before
1196 * unlocking the lock that protects the seqno. For lockless tricks, the
1197 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1200 * Returns 0 if the request was found within the alloted time. Else returns the
1201 * errno with remaining time filled in timeout argument.
1203 int __i915_wait_request(struct drm_i915_gem_request *req,
1204 unsigned reset_counter,
1207 struct intel_rps_client *rps)
1209 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1210 struct drm_device *dev = ring->dev;
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 const bool irq_test_in_progress =
1213 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1215 unsigned long timeout_expire;
1219 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1221 if (list_empty(&req->list))
1224 if (i915_gem_request_completed(req, true))
1227 timeout_expire = timeout ?
1228 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1230 if (INTEL_INFO(dev_priv)->gen >= 6)
1231 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1233 /* Record current time in case interrupted by signal, or wedged */
1234 trace_i915_gem_request_wait_begin(req);
1235 before = ktime_get_raw_ns();
1237 /* Optimistic spin for the next jiffie before touching IRQs */
1238 ret = __i915_spin_request(req);
1242 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1248 struct timer_list timer;
1250 prepare_to_wait(&ring->irq_queue, &wait,
1251 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1253 /* We need to check whether any gpu reset happened in between
1254 * the caller grabbing the seqno and now ... */
1255 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1256 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1257 * is truely gone. */
1258 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1264 if (i915_gem_request_completed(req, false)) {
1269 if (interruptible && signal_pending(current)) {
1274 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1279 timer.function = NULL;
1280 if (timeout || missed_irq(dev_priv, ring)) {
1281 unsigned long expire;
1283 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1284 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1285 mod_timer(&timer, expire);
1290 if (timer.function) {
1291 del_singleshot_timer_sync(&timer);
1292 destroy_timer_on_stack(&timer);
1295 if (!irq_test_in_progress)
1296 ring->irq_put(ring);
1298 finish_wait(&ring->irq_queue, &wait);
1301 now = ktime_get_raw_ns();
1302 trace_i915_gem_request_wait_end(req);
1305 s64 tres = *timeout - (now - before);
1307 *timeout = tres < 0 ? 0 : tres;
1310 * Apparently ktime isn't accurate enough and occasionally has a
1311 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1312 * things up to make the test happy. We allow up to 1 jiffy.
1314 * This is a regrssion from the timespec->ktime conversion.
1316 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1323 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1324 struct drm_file *file)
1326 struct drm_i915_private *dev_private;
1327 struct drm_i915_file_private *file_priv;
1329 WARN_ON(!req || !file || req->file_priv);
1337 dev_private = req->ring->dev->dev_private;
1338 file_priv = file->driver_priv;
1340 spin_lock(&file_priv->mm.lock);
1341 req->file_priv = file_priv;
1342 list_add_tail(&req->client_list, &file_priv->mm.request_list);
1343 spin_unlock(&file_priv->mm.lock);
1345 req->pid = get_pid(task_pid(current));
1351 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1353 struct drm_i915_file_private *file_priv = request->file_priv;
1358 spin_lock(&file_priv->mm.lock);
1359 list_del(&request->client_list);
1360 request->file_priv = NULL;
1361 spin_unlock(&file_priv->mm.lock);
1363 put_pid(request->pid);
1364 request->pid = NULL;
1367 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1369 trace_i915_gem_request_retire(request);
1371 /* We know the GPU must have read the request to have
1372 * sent us the seqno + interrupt, so use the position
1373 * of tail of the request to update the last known position
1376 * Note this requires that we are always called in request
1379 request->ringbuf->last_retired_head = request->postfix;
1381 list_del_init(&request->list);
1382 i915_gem_request_remove_from_client(request);
1384 i915_gem_request_unreference(request);
1388 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1390 struct intel_engine_cs *engine = req->ring;
1391 struct drm_i915_gem_request *tmp;
1393 lockdep_assert_held(&engine->dev->struct_mutex);
1395 if (list_empty(&req->list))
1399 tmp = list_first_entry(&engine->request_list,
1400 typeof(*tmp), list);
1402 i915_gem_request_retire(tmp);
1403 } while (tmp != req);
1405 WARN_ON(i915_verify_lists(engine->dev));
1409 * Waits for a request to be signaled, and cleans up the
1410 * request and object lists appropriately for that event.
1413 i915_wait_request(struct drm_i915_gem_request *req)
1415 struct drm_device *dev;
1416 struct drm_i915_private *dev_priv;
1420 BUG_ON(req == NULL);
1422 dev = req->ring->dev;
1423 dev_priv = dev->dev_private;
1424 interruptible = dev_priv->mm.interruptible;
1426 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1428 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1432 ret = __i915_wait_request(req,
1433 atomic_read(&dev_priv->gpu_error.reset_counter),
1434 interruptible, NULL, NULL);
1438 __i915_gem_request_retire__upto(req);
1443 * Ensures that all rendering to the object has completed and the object is
1444 * safe to unbind from the GTT or access from the CPU.
1447 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1456 if (obj->last_write_req != NULL) {
1457 ret = i915_wait_request(obj->last_write_req);
1461 i = obj->last_write_req->ring->id;
1462 if (obj->last_read_req[i] == obj->last_write_req)
1463 i915_gem_object_retire__read(obj, i);
1465 i915_gem_object_retire__write(obj);
1468 for (i = 0; i < I915_NUM_RINGS; i++) {
1469 if (obj->last_read_req[i] == NULL)
1472 ret = i915_wait_request(obj->last_read_req[i]);
1476 i915_gem_object_retire__read(obj, i);
1478 RQ_BUG_ON(obj->active);
1485 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1486 struct drm_i915_gem_request *req)
1488 int ring = req->ring->id;
1490 if (obj->last_read_req[ring] == req)
1491 i915_gem_object_retire__read(obj, ring);
1492 else if (obj->last_write_req == req)
1493 i915_gem_object_retire__write(obj);
1495 __i915_gem_request_retire__upto(req);
1498 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1499 * as the object state may change during this call.
1501 static __must_check int
1502 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1503 struct intel_rps_client *rps,
1506 struct drm_device *dev = obj->base.dev;
1507 struct drm_i915_private *dev_priv = dev->dev_private;
1508 struct drm_i915_gem_request *requests[I915_NUM_RINGS];
1509 unsigned reset_counter;
1512 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1513 BUG_ON(!dev_priv->mm.interruptible);
1518 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1522 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1525 struct drm_i915_gem_request *req;
1527 req = obj->last_write_req;
1531 requests[n++] = i915_gem_request_reference(req);
1533 for (i = 0; i < I915_NUM_RINGS; i++) {
1534 struct drm_i915_gem_request *req;
1536 req = obj->last_read_req[i];
1540 requests[n++] = i915_gem_request_reference(req);
1544 mutex_unlock(&dev->struct_mutex);
1545 for (i = 0; ret == 0 && i < n; i++)
1546 ret = __i915_wait_request(requests[i], reset_counter, true,
1548 mutex_lock(&dev->struct_mutex);
1550 for (i = 0; i < n; i++) {
1552 i915_gem_object_retire_request(obj, requests[i]);
1553 i915_gem_request_unreference(requests[i]);
1559 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1561 struct drm_i915_file_private *fpriv = file->driver_priv;
1566 * Called when user space prepares to use an object with the CPU, either
1567 * through the mmap ioctl's mapping or a GTT mapping.
1570 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1571 struct drm_file *file)
1573 struct drm_i915_gem_set_domain *args = data;
1574 struct drm_i915_gem_object *obj;
1575 uint32_t read_domains = args->read_domains;
1576 uint32_t write_domain = args->write_domain;
1579 /* Only handle setting domains to types used by the CPU. */
1580 if (write_domain & I915_GEM_GPU_DOMAINS)
1583 if (read_domains & I915_GEM_GPU_DOMAINS)
1586 /* Having something in the write domain implies it's in the read
1587 * domain, and only that read domain. Enforce that in the request.
1589 if (write_domain != 0 && read_domains != write_domain)
1592 ret = i915_mutex_lock_interruptible(dev);
1596 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1597 if (&obj->base == NULL) {
1602 /* Try to flush the object off the GPU without holding the lock.
1603 * We will repeat the flush holding the lock in the normal manner
1604 * to catch cases where we are gazumped.
1606 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1607 to_rps_client(file),
1612 if (read_domains & I915_GEM_DOMAIN_GTT)
1613 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1615 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1618 drm_gem_object_unreference(&obj->base);
1620 mutex_unlock(&dev->struct_mutex);
1625 * Called when user space has done writes to this buffer
1628 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1629 struct drm_file *file)
1631 struct drm_i915_gem_sw_finish *args = data;
1632 struct drm_i915_gem_object *obj;
1635 ret = i915_mutex_lock_interruptible(dev);
1639 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1640 if (&obj->base == NULL) {
1645 /* Pinned buffers may be scanout, so flush the cache */
1646 if (obj->pin_display)
1647 i915_gem_object_flush_cpu_write_domain(obj);
1649 drm_gem_object_unreference(&obj->base);
1651 mutex_unlock(&dev->struct_mutex);
1656 * Maps the contents of an object, returning the address it is mapped
1659 * While the mapping holds a reference on the contents of the object, it doesn't
1660 * imply a ref on the object itself.
1664 * DRM driver writers who look a this function as an example for how to do GEM
1665 * mmap support, please don't implement mmap support like here. The modern way
1666 * to implement DRM mmap support is with an mmap offset ioctl (like
1667 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1668 * That way debug tooling like valgrind will understand what's going on, hiding
1669 * the mmap call in a driver private ioctl will break that. The i915 driver only
1670 * does cpu mmaps this way because we didn't know better.
1673 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1674 struct drm_file *file)
1676 struct drm_i915_gem_mmap *args = data;
1677 struct drm_gem_object *obj;
1680 if (args->flags & ~(I915_MMAP_WC))
1683 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1686 obj = drm_gem_object_lookup(dev, file, args->handle);
1690 /* prime objects have no backing filp to GEM mmap
1694 drm_gem_object_unreference_unlocked(obj);
1698 addr = vm_mmap(obj->filp, 0, args->size,
1699 PROT_READ | PROT_WRITE, MAP_SHARED,
1701 if (args->flags & I915_MMAP_WC) {
1702 struct mm_struct *mm = current->mm;
1703 struct vm_area_struct *vma;
1705 down_write(&mm->mmap_sem);
1706 vma = find_vma(mm, addr);
1709 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1712 up_write(&mm->mmap_sem);
1714 drm_gem_object_unreference_unlocked(obj);
1715 if (IS_ERR((void *)addr))
1718 args->addr_ptr = (uint64_t) addr;
1724 * i915_gem_fault - fault a page into the GTT
1725 * vma: VMA in question
1728 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1729 * from userspace. The fault handler takes care of binding the object to
1730 * the GTT (if needed), allocating and programming a fence register (again,
1731 * only if needed based on whether the old reg is still valid or the object
1732 * is tiled) and inserting a new PTE into the faulting process.
1734 * Note that the faulting process may involve evicting existing objects
1735 * from the GTT and/or fence registers to make room. So performance may
1736 * suffer if the GTT working set is large or there are few fence registers
1739 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1741 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1742 struct drm_device *dev = obj->base.dev;
1743 struct drm_i915_private *dev_priv = dev->dev_private;
1744 struct i915_ggtt_view view = i915_ggtt_view_normal;
1745 pgoff_t page_offset;
1748 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1750 intel_runtime_pm_get(dev_priv);
1752 /* We don't use vmf->pgoff since that has the fake offset */
1753 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1756 ret = i915_mutex_lock_interruptible(dev);
1760 trace_i915_gem_object_fault(obj, page_offset, true, write);
1762 /* Try to flush the object off the GPU first without holding the lock.
1763 * Upon reacquiring the lock, we will perform our sanity checks and then
1764 * repeat the flush holding the lock in the normal manner to catch cases
1765 * where we are gazumped.
1767 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1771 /* Access to snoopable pages through the GTT is incoherent. */
1772 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1777 /* Use a partial view if the object is bigger than the aperture. */
1778 if (obj->base.size >= dev_priv->gtt.mappable_end &&
1779 obj->tiling_mode == I915_TILING_NONE) {
1780 static const unsigned int chunk_size = 256; // 1 MiB
1782 memset(&view, 0, sizeof(view));
1783 view.type = I915_GGTT_VIEW_PARTIAL;
1784 view.params.partial.offset = rounddown(page_offset, chunk_size);
1785 view.params.partial.size =
1788 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1789 view.params.partial.offset);
1792 /* Now pin it into the GTT if needed */
1793 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1797 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1801 ret = i915_gem_object_get_fence(obj);
1805 /* Finally, remap it using the new GTT offset */
1806 pfn = dev_priv->gtt.mappable_base +
1807 i915_gem_obj_ggtt_offset_view(obj, &view);
1810 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1811 /* Overriding existing pages in partial view does not cause
1812 * us any trouble as TLBs are still valid because the fault
1813 * is due to userspace losing part of the mapping or never
1814 * having accessed it before (at this partials' range).
1816 unsigned long base = vma->vm_start +
1817 (view.params.partial.offset << PAGE_SHIFT);
1820 for (i = 0; i < view.params.partial.size; i++) {
1821 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1826 obj->fault_mappable = true;
1828 if (!obj->fault_mappable) {
1829 unsigned long size = min_t(unsigned long,
1830 vma->vm_end - vma->vm_start,
1834 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1835 ret = vm_insert_pfn(vma,
1836 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1842 obj->fault_mappable = true;
1844 ret = vm_insert_pfn(vma,
1845 (unsigned long)vmf->virtual_address,
1849 i915_gem_object_ggtt_unpin_view(obj, &view);
1851 mutex_unlock(&dev->struct_mutex);
1856 * We eat errors when the gpu is terminally wedged to avoid
1857 * userspace unduly crashing (gl has no provisions for mmaps to
1858 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1859 * and so needs to be reported.
1861 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1862 ret = VM_FAULT_SIGBUS;
1867 * EAGAIN means the gpu is hung and we'll wait for the error
1868 * handler to reset everything when re-faulting in
1869 * i915_mutex_lock_interruptible.
1876 * EBUSY is ok: this just means that another thread
1877 * already did the job.
1879 ret = VM_FAULT_NOPAGE;
1886 ret = VM_FAULT_SIGBUS;
1889 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1890 ret = VM_FAULT_SIGBUS;
1894 intel_runtime_pm_put(dev_priv);
1899 * i915_gem_release_mmap - remove physical page mappings
1900 * @obj: obj in question
1902 * Preserve the reservation of the mmapping with the DRM core code, but
1903 * relinquish ownership of the pages back to the system.
1905 * It is vital that we remove the page mapping if we have mapped a tiled
1906 * object through the GTT and then lose the fence register due to
1907 * resource pressure. Similarly if the object has been moved out of the
1908 * aperture, than pages mapped into userspace must be revoked. Removing the
1909 * mapping will then trigger a page fault on the next user access, allowing
1910 * fixup by i915_gem_fault().
1913 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1915 if (!obj->fault_mappable)
1918 drm_vma_node_unmap(&obj->base.vma_node,
1919 obj->base.dev->anon_inode->i_mapping);
1920 obj->fault_mappable = false;
1924 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1926 struct drm_i915_gem_object *obj;
1928 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1929 i915_gem_release_mmap(obj);
1933 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1937 if (INTEL_INFO(dev)->gen >= 4 ||
1938 tiling_mode == I915_TILING_NONE)
1941 /* Previous chips need a power-of-two fence region when tiling */
1942 if (INTEL_INFO(dev)->gen == 3)
1943 gtt_size = 1024*1024;
1945 gtt_size = 512*1024;
1947 while (gtt_size < size)
1954 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1955 * @obj: object to check
1957 * Return the required GTT alignment for an object, taking into account
1958 * potential fence register mapping.
1961 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1962 int tiling_mode, bool fenced)
1965 * Minimum alignment is 4k (GTT page size), but might be greater
1966 * if a fence register is needed for the object.
1968 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1969 tiling_mode == I915_TILING_NONE)
1973 * Previous chips need to be aligned to the size of the smallest
1974 * fence register that can contain the object.
1976 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1979 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1981 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1984 if (drm_vma_node_has_offset(&obj->base.vma_node))
1987 dev_priv->mm.shrinker_no_lock_stealing = true;
1989 ret = drm_gem_create_mmap_offset(&obj->base);
1993 /* Badly fragmented mmap space? The only way we can recover
1994 * space is by destroying unwanted objects. We can't randomly release
1995 * mmap_offsets as userspace expects them to be persistent for the
1996 * lifetime of the objects. The closest we can is to release the
1997 * offsets on purgeable objects by truncating it and marking it purged,
1998 * which prevents userspace from ever using that object again.
2000 i915_gem_shrink(dev_priv,
2001 obj->base.size >> PAGE_SHIFT,
2003 I915_SHRINK_UNBOUND |
2004 I915_SHRINK_PURGEABLE);
2005 ret = drm_gem_create_mmap_offset(&obj->base);
2009 i915_gem_shrink_all(dev_priv);
2010 ret = drm_gem_create_mmap_offset(&obj->base);
2012 dev_priv->mm.shrinker_no_lock_stealing = false;
2017 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2019 drm_gem_free_mmap_offset(&obj->base);
2023 i915_gem_mmap_gtt(struct drm_file *file,
2024 struct drm_device *dev,
2028 struct drm_i915_gem_object *obj;
2031 ret = i915_mutex_lock_interruptible(dev);
2035 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2036 if (&obj->base == NULL) {
2041 if (obj->madv != I915_MADV_WILLNEED) {
2042 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2047 ret = i915_gem_object_create_mmap_offset(obj);
2051 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2054 drm_gem_object_unreference(&obj->base);
2056 mutex_unlock(&dev->struct_mutex);
2061 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2063 * @data: GTT mapping ioctl data
2064 * @file: GEM object info
2066 * Simply returns the fake offset to userspace so it can mmap it.
2067 * The mmap call will end up in drm_gem_mmap(), which will set things
2068 * up so we can get faults in the handler above.
2070 * The fault handler will take care of binding the object into the GTT
2071 * (since it may have been evicted to make room for something), allocating
2072 * a fence register, and mapping the appropriate aperture address into
2076 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2077 struct drm_file *file)
2079 struct drm_i915_gem_mmap_gtt *args = data;
2081 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2084 /* Immediately discard the backing storage */
2086 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2088 i915_gem_object_free_mmap_offset(obj);
2090 if (obj->base.filp == NULL)
2093 /* Our goal here is to return as much of the memory as
2094 * is possible back to the system as we are called from OOM.
2095 * To do this we must instruct the shmfs to drop all of its
2096 * backing pages, *now*.
2098 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2099 obj->madv = __I915_MADV_PURGED;
2102 /* Try to discard unwanted pages */
2104 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2106 struct address_space *mapping;
2108 switch (obj->madv) {
2109 case I915_MADV_DONTNEED:
2110 i915_gem_object_truncate(obj);
2111 case __I915_MADV_PURGED:
2115 if (obj->base.filp == NULL)
2118 mapping = file_inode(obj->base.filp)->i_mapping,
2119 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2123 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2125 struct sg_page_iter sg_iter;
2128 BUG_ON(obj->madv == __I915_MADV_PURGED);
2130 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2132 /* In the event of a disaster, abandon all caches and
2133 * hope for the best.
2135 WARN_ON(ret != -EIO);
2136 i915_gem_clflush_object(obj, true);
2137 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2140 if (i915_gem_object_needs_bit17_swizzle(obj))
2141 i915_gem_object_save_bit_17_swizzle(obj);
2143 if (obj->madv == I915_MADV_DONTNEED)
2146 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2147 struct page *page = sg_page_iter_page(&sg_iter);
2150 set_page_dirty(page);
2152 if (obj->madv == I915_MADV_WILLNEED)
2153 mark_page_accessed(page);
2155 page_cache_release(page);
2159 sg_free_table(obj->pages);
2164 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2166 const struct drm_i915_gem_object_ops *ops = obj->ops;
2168 if (obj->pages == NULL)
2171 if (obj->pages_pin_count)
2174 BUG_ON(i915_gem_obj_bound_any(obj));
2176 /* ->put_pages might need to allocate memory for the bit17 swizzle
2177 * array, hence protect them from being reaped by removing them from gtt
2179 list_del(&obj->global_list);
2181 ops->put_pages(obj);
2184 i915_gem_object_invalidate(obj);
2190 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2192 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2194 struct address_space *mapping;
2195 struct sg_table *st;
2196 struct scatterlist *sg;
2197 struct sg_page_iter sg_iter;
2199 unsigned long last_pfn = 0; /* suppress gcc warning */
2202 /* Assert that the object is not currently in any GPU domain. As it
2203 * wasn't in the GTT, there shouldn't be any way it could have been in
2206 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2207 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2209 st = kmalloc(sizeof(*st), GFP_KERNEL);
2213 page_count = obj->base.size / PAGE_SIZE;
2214 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2219 /* Get the list of pages out of our struct file. They'll be pinned
2220 * at this point until we release them.
2222 * Fail silently without starting the shrinker
2224 mapping = file_inode(obj->base.filp)->i_mapping;
2225 gfp = mapping_gfp_mask(mapping);
2226 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2227 gfp &= ~(__GFP_IO | __GFP_WAIT);
2230 for (i = 0; i < page_count; i++) {
2231 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2233 i915_gem_shrink(dev_priv,
2236 I915_SHRINK_UNBOUND |
2237 I915_SHRINK_PURGEABLE);
2238 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2241 /* We've tried hard to allocate the memory by reaping
2242 * our own buffer, now let the real VM do its job and
2243 * go down in flames if truly OOM.
2245 i915_gem_shrink_all(dev_priv);
2246 page = shmem_read_mapping_page(mapping, i);
2250 #ifdef CONFIG_SWIOTLB
2251 if (swiotlb_nr_tbl()) {
2253 sg_set_page(sg, page, PAGE_SIZE, 0);
2258 if (!i || page_to_pfn(page) != last_pfn + 1) {
2262 sg_set_page(sg, page, PAGE_SIZE, 0);
2264 sg->length += PAGE_SIZE;
2266 last_pfn = page_to_pfn(page);
2268 /* Check that the i965g/gm workaround works. */
2269 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2271 #ifdef CONFIG_SWIOTLB
2272 if (!swiotlb_nr_tbl())
2277 if (i915_gem_object_needs_bit17_swizzle(obj))
2278 i915_gem_object_do_bit_17_swizzle(obj);
2280 if (obj->tiling_mode != I915_TILING_NONE &&
2281 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2282 i915_gem_object_pin_pages(obj);
2288 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2289 page_cache_release(sg_page_iter_page(&sg_iter));
2293 /* shmemfs first checks if there is enough memory to allocate the page
2294 * and reports ENOSPC should there be insufficient, along with the usual
2295 * ENOMEM for a genuine allocation failure.
2297 * We use ENOSPC in our driver to mean that we have run out of aperture
2298 * space and so want to translate the error from shmemfs back to our
2299 * usual understanding of ENOMEM.
2301 if (PTR_ERR(page) == -ENOSPC)
2304 return PTR_ERR(page);
2307 /* Ensure that the associated pages are gathered from the backing storage
2308 * and pinned into our object. i915_gem_object_get_pages() may be called
2309 * multiple times before they are released by a single call to
2310 * i915_gem_object_put_pages() - once the pages are no longer referenced
2311 * either as a result of memory pressure (reaping pages under the shrinker)
2312 * or as the object is itself released.
2315 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2317 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2318 const struct drm_i915_gem_object_ops *ops = obj->ops;
2324 if (obj->madv != I915_MADV_WILLNEED) {
2325 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2329 BUG_ON(obj->pages_pin_count);
2331 ret = ops->get_pages(obj);
2335 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2337 obj->get_page.sg = obj->pages->sgl;
2338 obj->get_page.last = 0;
2343 void i915_vma_move_to_active(struct i915_vma *vma,
2344 struct drm_i915_gem_request *req)
2346 struct drm_i915_gem_object *obj = vma->obj;
2347 struct intel_engine_cs *ring;
2349 ring = i915_gem_request_get_ring(req);
2351 /* Add a reference if we're newly entering the active list. */
2352 if (obj->active == 0)
2353 drm_gem_object_reference(&obj->base);
2354 obj->active |= intel_ring_flag(ring);
2356 list_move_tail(&obj->ring_list[ring->id], &ring->active_list);
2357 i915_gem_request_assign(&obj->last_read_req[ring->id], req);
2359 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2363 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2365 RQ_BUG_ON(obj->last_write_req == NULL);
2366 RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring)));
2368 i915_gem_request_assign(&obj->last_write_req, NULL);
2369 intel_fb_obj_flush(obj, true);
2373 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2375 struct i915_vma *vma;
2377 RQ_BUG_ON(obj->last_read_req[ring] == NULL);
2378 RQ_BUG_ON(!(obj->active & (1 << ring)));
2380 list_del_init(&obj->ring_list[ring]);
2381 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2383 if (obj->last_write_req && obj->last_write_req->ring->id == ring)
2384 i915_gem_object_retire__write(obj);
2386 obj->active &= ~(1 << ring);
2390 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2391 if (!list_empty(&vma->mm_list))
2392 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2395 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2396 drm_gem_object_unreference(&obj->base);
2400 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403 struct intel_engine_cs *ring;
2406 /* Carefully retire all requests without writing to the rings */
2407 for_each_ring(ring, dev_priv, i) {
2408 ret = intel_ring_idle(ring);
2412 i915_gem_retire_requests(dev);
2414 /* Finally reset hw state */
2415 for_each_ring(ring, dev_priv, i) {
2416 intel_ring_init_seqno(ring, seqno);
2418 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2419 ring->semaphore.sync_seqno[j] = 0;
2425 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2427 struct drm_i915_private *dev_priv = dev->dev_private;
2433 /* HWS page needs to be set less than what we
2434 * will inject to ring
2436 ret = i915_gem_init_seqno(dev, seqno - 1);
2440 /* Carefully set the last_seqno value so that wrap
2441 * detection still works
2443 dev_priv->next_seqno = seqno;
2444 dev_priv->last_seqno = seqno - 1;
2445 if (dev_priv->last_seqno == 0)
2446 dev_priv->last_seqno--;
2452 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2456 /* reserve 0 for non-seqno */
2457 if (dev_priv->next_seqno == 0) {
2458 int ret = i915_gem_init_seqno(dev, 0);
2462 dev_priv->next_seqno = 1;
2465 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2470 * NB: This function is not allowed to fail. Doing so would mean the the
2471 * request is not being tracked for completion but the work itself is
2472 * going to happen on the hardware. This would be a Bad Thing(tm).
2474 void __i915_add_request(struct drm_i915_gem_request *request,
2475 struct drm_i915_gem_object *obj,
2478 struct intel_engine_cs *ring;
2479 struct drm_i915_private *dev_priv;
2480 struct intel_ringbuffer *ringbuf;
2484 if (WARN_ON(request == NULL))
2487 ring = request->ring;
2488 dev_priv = ring->dev->dev_private;
2489 ringbuf = request->ringbuf;
2492 * To ensure that this call will not fail, space for its emissions
2493 * should already have been reserved in the ring buffer. Let the ring
2494 * know that it is time to use that space up.
2496 intel_ring_reserved_space_use(ringbuf);
2498 request_start = intel_ring_get_tail(ringbuf);
2500 * Emit any outstanding flushes - execbuf can fail to emit the flush
2501 * after having emitted the batchbuffer command. Hence we need to fix
2502 * things up similar to emitting the lazy request. The difference here
2503 * is that the flush _must_ happen before the next request, no matter
2507 if (i915.enable_execlists)
2508 ret = logical_ring_flush_all_caches(request);
2510 ret = intel_ring_flush_all_caches(request);
2511 /* Not allowed to fail! */
2512 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2515 /* Record the position of the start of the request so that
2516 * should we detect the updated seqno part-way through the
2517 * GPU processing the request, we never over-estimate the
2518 * position of the head.
2520 request->postfix = intel_ring_get_tail(ringbuf);
2522 if (i915.enable_execlists)
2523 ret = ring->emit_request(request);
2525 ret = ring->add_request(request);
2527 request->tail = intel_ring_get_tail(ringbuf);
2529 /* Not allowed to fail! */
2530 WARN(ret, "emit|add_request failed: %d!\n", ret);
2532 request->head = request_start;
2534 /* Whilst this request exists, batch_obj will be on the
2535 * active_list, and so will hold the active reference. Only when this
2536 * request is retired will the the batch_obj be moved onto the
2537 * inactive_list and lose its active reference. Hence we do not need
2538 * to explicitly hold another reference here.
2540 request->batch_obj = obj;
2542 request->emitted_jiffies = jiffies;
2543 list_add_tail(&request->list, &ring->request_list);
2545 trace_i915_gem_request_add(request);
2547 i915_queue_hangcheck(ring->dev);
2549 queue_delayed_work(dev_priv->wq,
2550 &dev_priv->mm.retire_work,
2551 round_jiffies_up_relative(HZ));
2552 intel_mark_busy(dev_priv->dev);
2554 /* Sanity check that the reserved size was large enough. */
2555 intel_ring_reserved_space_end(ringbuf);
2558 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2559 const struct intel_context *ctx)
2561 unsigned long elapsed;
2563 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2565 if (ctx->hang_stats.banned)
2568 if (ctx->hang_stats.ban_period_seconds &&
2569 elapsed <= ctx->hang_stats.ban_period_seconds) {
2570 if (!i915_gem_context_is_default(ctx)) {
2571 DRM_DEBUG("context hanging too fast, banning!\n");
2573 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2574 if (i915_stop_ring_allow_warn(dev_priv))
2575 DRM_ERROR("gpu hanging too fast, banning!\n");
2583 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2584 struct intel_context *ctx,
2587 struct i915_ctx_hang_stats *hs;
2592 hs = &ctx->hang_stats;
2595 hs->banned = i915_context_is_banned(dev_priv, ctx);
2597 hs->guilty_ts = get_seconds();
2599 hs->batch_pending++;
2603 void i915_gem_request_free(struct kref *req_ref)
2605 struct drm_i915_gem_request *req = container_of(req_ref,
2607 struct intel_context *ctx = req->ctx;
2610 i915_gem_request_remove_from_client(req);
2613 if (i915.enable_execlists) {
2614 struct intel_engine_cs *ring = req->ring;
2616 if (ctx != ring->default_context)
2617 intel_lr_context_unpin(ring, ctx);
2620 i915_gem_context_unreference(ctx);
2623 kmem_cache_free(req->i915->requests, req);
2626 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2627 struct intel_context *ctx,
2628 struct drm_i915_gem_request **req_out)
2630 struct drm_i915_private *dev_priv = to_i915(ring->dev);
2631 struct drm_i915_gem_request *req;
2639 req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2643 ret = i915_gem_get_seqno(ring->dev, &req->seqno);
2647 kref_init(&req->ref);
2648 req->i915 = dev_priv;
2651 i915_gem_context_reference(req->ctx);
2653 if (i915.enable_execlists)
2654 ret = intel_logical_ring_alloc_request_extras(req);
2656 ret = intel_ring_alloc_request_extras(req);
2658 i915_gem_context_unreference(req->ctx);
2663 * Reserve space in the ring buffer for all the commands required to
2664 * eventually emit this request. This is to guarantee that the
2665 * i915_add_request() call can't fail. Note that the reserve may need
2666 * to be redone if the request is not actually submitted straight
2667 * away, e.g. because a GPU scheduler has deferred it.
2669 if (i915.enable_execlists)
2670 ret = intel_logical_ring_reserve_space(req);
2672 ret = intel_ring_reserve_space(req);
2675 * At this point, the request is fully allocated even if not
2676 * fully prepared. Thus it can be cleaned up using the proper
2679 i915_gem_request_cancel(req);
2687 kmem_cache_free(dev_priv->requests, req);
2691 void i915_gem_request_cancel(struct drm_i915_gem_request *req)
2693 intel_ring_reserved_space_cancel(req->ringbuf);
2695 i915_gem_request_unreference(req);
2698 struct drm_i915_gem_request *
2699 i915_gem_find_active_request(struct intel_engine_cs *ring)
2701 struct drm_i915_gem_request *request;
2703 list_for_each_entry(request, &ring->request_list, list) {
2704 if (i915_gem_request_completed(request, false))
2713 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2714 struct intel_engine_cs *ring)
2716 struct drm_i915_gem_request *request;
2719 request = i915_gem_find_active_request(ring);
2721 if (request == NULL)
2724 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2726 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2728 list_for_each_entry_continue(request, &ring->request_list, list)
2729 i915_set_reset_status(dev_priv, request->ctx, false);
2732 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2733 struct intel_engine_cs *ring)
2735 while (!list_empty(&ring->active_list)) {
2736 struct drm_i915_gem_object *obj;
2738 obj = list_first_entry(&ring->active_list,
2739 struct drm_i915_gem_object,
2740 ring_list[ring->id]);
2742 i915_gem_object_retire__read(obj, ring->id);
2746 * Clear the execlists queue up before freeing the requests, as those
2747 * are the ones that keep the context and ringbuffer backing objects
2750 while (!list_empty(&ring->execlist_queue)) {
2751 struct drm_i915_gem_request *submit_req;
2753 submit_req = list_first_entry(&ring->execlist_queue,
2754 struct drm_i915_gem_request,
2756 list_del(&submit_req->execlist_link);
2758 if (submit_req->ctx != ring->default_context)
2759 intel_lr_context_unpin(ring, submit_req->ctx);
2761 i915_gem_request_unreference(submit_req);
2765 * We must free the requests after all the corresponding objects have
2766 * been moved off active lists. Which is the same order as the normal
2767 * retire_requests function does. This is important if object hold
2768 * implicit references on things like e.g. ppgtt address spaces through
2771 while (!list_empty(&ring->request_list)) {
2772 struct drm_i915_gem_request *request;
2774 request = list_first_entry(&ring->request_list,
2775 struct drm_i915_gem_request,
2778 i915_gem_request_retire(request);
2782 void i915_gem_restore_fences(struct drm_device *dev)
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2787 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2788 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2791 * Commit delayed tiling changes if we have an object still
2792 * attached to the fence, otherwise just clear the fence.
2795 i915_gem_object_update_fence(reg->obj, reg,
2796 reg->obj->tiling_mode);
2798 i915_gem_write_fence(dev, i, NULL);
2803 void i915_gem_reset(struct drm_device *dev)
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_engine_cs *ring;
2810 * Before we free the objects from the requests, we need to inspect
2811 * them for finding the guilty party. As the requests only borrow
2812 * their reference to the objects, the inspection must be done first.
2814 for_each_ring(ring, dev_priv, i)
2815 i915_gem_reset_ring_status(dev_priv, ring);
2817 for_each_ring(ring, dev_priv, i)
2818 i915_gem_reset_ring_cleanup(dev_priv, ring);
2820 i915_gem_context_reset(dev);
2822 i915_gem_restore_fences(dev);
2824 WARN_ON(i915_verify_lists(dev));
2828 * This function clears the request list as sequence numbers are passed.
2831 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2833 WARN_ON(i915_verify_lists(ring->dev));
2835 /* Retire requests first as we use it above for the early return.
2836 * If we retire requests last, we may use a later seqno and so clear
2837 * the requests lists without clearing the active list, leading to
2840 while (!list_empty(&ring->request_list)) {
2841 struct drm_i915_gem_request *request;
2843 request = list_first_entry(&ring->request_list,
2844 struct drm_i915_gem_request,
2847 if (!i915_gem_request_completed(request, true))
2850 i915_gem_request_retire(request);
2853 /* Move any buffers on the active list that are no longer referenced
2854 * by the ringbuffer to the flushing/inactive lists as appropriate,
2855 * before we free the context associated with the requests.
2857 while (!list_empty(&ring->active_list)) {
2858 struct drm_i915_gem_object *obj;
2860 obj = list_first_entry(&ring->active_list,
2861 struct drm_i915_gem_object,
2862 ring_list[ring->id]);
2864 if (!list_empty(&obj->last_read_req[ring->id]->list))
2867 i915_gem_object_retire__read(obj, ring->id);
2870 if (unlikely(ring->trace_irq_req &&
2871 i915_gem_request_completed(ring->trace_irq_req, true))) {
2872 ring->irq_put(ring);
2873 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2876 WARN_ON(i915_verify_lists(ring->dev));
2880 i915_gem_retire_requests(struct drm_device *dev)
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 struct intel_engine_cs *ring;
2887 for_each_ring(ring, dev_priv, i) {
2888 i915_gem_retire_requests_ring(ring);
2889 idle &= list_empty(&ring->request_list);
2890 if (i915.enable_execlists) {
2891 unsigned long flags;
2893 spin_lock_irqsave(&ring->execlist_lock, flags);
2894 idle &= list_empty(&ring->execlist_queue);
2895 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2897 intel_execlists_retire_requests(ring);
2902 mod_delayed_work(dev_priv->wq,
2903 &dev_priv->mm.idle_work,
2904 msecs_to_jiffies(100));
2910 i915_gem_retire_work_handler(struct work_struct *work)
2912 struct drm_i915_private *dev_priv =
2913 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2914 struct drm_device *dev = dev_priv->dev;
2917 /* Come back later if the device is busy... */
2919 if (mutex_trylock(&dev->struct_mutex)) {
2920 idle = i915_gem_retire_requests(dev);
2921 mutex_unlock(&dev->struct_mutex);
2924 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2925 round_jiffies_up_relative(HZ));
2929 i915_gem_idle_work_handler(struct work_struct *work)
2931 struct drm_i915_private *dev_priv =
2932 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2933 struct drm_device *dev = dev_priv->dev;
2934 struct intel_engine_cs *ring;
2937 for_each_ring(ring, dev_priv, i)
2938 if (!list_empty(&ring->request_list))
2941 intel_mark_idle(dev);
2943 if (mutex_trylock(&dev->struct_mutex)) {
2944 struct intel_engine_cs *ring;
2947 for_each_ring(ring, dev_priv, i)
2948 i915_gem_batch_pool_fini(&ring->batch_pool);
2950 mutex_unlock(&dev->struct_mutex);
2955 * Ensures that an object will eventually get non-busy by flushing any required
2956 * write domains, emitting any outstanding lazy request and retiring and
2957 * completed requests.
2960 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2967 for (i = 0; i < I915_NUM_RINGS; i++) {
2968 struct drm_i915_gem_request *req;
2970 req = obj->last_read_req[i];
2974 if (list_empty(&req->list))
2977 if (i915_gem_request_completed(req, true)) {
2978 __i915_gem_request_retire__upto(req);
2980 i915_gem_object_retire__read(obj, i);
2988 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2989 * @DRM_IOCTL_ARGS: standard ioctl arguments
2991 * Returns 0 if successful, else an error is returned with the remaining time in
2992 * the timeout parameter.
2993 * -ETIME: object is still busy after timeout
2994 * -ERESTARTSYS: signal interrupted the wait
2995 * -ENONENT: object doesn't exist
2996 * Also possible, but rare:
2997 * -EAGAIN: GPU wedged
2999 * -ENODEV: Internal IRQ fail
3000 * -E?: The add request failed
3002 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3003 * non-zero timeout parameter the wait ioctl will wait for the given number of
3004 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3005 * without holding struct_mutex the object may become re-busied before this
3006 * function completes. A similar but shorter * race condition exists in the busy
3010 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3012 struct drm_i915_private *dev_priv = dev->dev_private;
3013 struct drm_i915_gem_wait *args = data;
3014 struct drm_i915_gem_object *obj;
3015 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3016 unsigned reset_counter;
3020 if (args->flags != 0)
3023 ret = i915_mutex_lock_interruptible(dev);
3027 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3028 if (&obj->base == NULL) {
3029 mutex_unlock(&dev->struct_mutex);
3033 /* Need to make sure the object gets inactive eventually. */
3034 ret = i915_gem_object_flush_active(obj);
3041 /* Do this after OLR check to make sure we make forward progress polling
3042 * on this IOCTL with a timeout == 0 (like busy ioctl)
3044 if (args->timeout_ns == 0) {
3049 drm_gem_object_unreference(&obj->base);
3050 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3052 for (i = 0; i < I915_NUM_RINGS; i++) {
3053 if (obj->last_read_req[i] == NULL)
3056 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3059 mutex_unlock(&dev->struct_mutex);
3061 for (i = 0; i < n; i++) {
3063 ret = __i915_wait_request(req[i], reset_counter, true,
3064 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3066 i915_gem_request_unreference__unlocked(req[i]);
3071 drm_gem_object_unreference(&obj->base);
3072 mutex_unlock(&dev->struct_mutex);
3077 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3078 struct intel_engine_cs *to,
3079 struct drm_i915_gem_request *from_req,
3080 struct drm_i915_gem_request **to_req)
3082 struct intel_engine_cs *from;
3085 from = i915_gem_request_get_ring(from_req);
3089 if (i915_gem_request_completed(from_req, true))
3092 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3093 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3094 ret = __i915_wait_request(from_req,
3095 atomic_read(&i915->gpu_error.reset_counter),
3096 i915->mm.interruptible,
3098 &i915->rps.semaphores);
3102 i915_gem_object_retire_request(obj, from_req);
3104 int idx = intel_ring_sync_index(from, to);
3105 u32 seqno = i915_gem_request_get_seqno(from_req);
3109 if (seqno <= from->semaphore.sync_seqno[idx])
3112 if (*to_req == NULL) {
3113 ret = i915_gem_request_alloc(to, to->default_context, to_req);
3118 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3119 ret = to->semaphore.sync_to(*to_req, from, seqno);
3123 /* We use last_read_req because sync_to()
3124 * might have just caused seqno wrap under
3127 from->semaphore.sync_seqno[idx] =
3128 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3135 * i915_gem_object_sync - sync an object to a ring.
3137 * @obj: object which may be in use on another ring.
3138 * @to: ring we wish to use the object on. May be NULL.
3139 * @to_req: request we wish to use the object for. See below.
3140 * This will be allocated and returned if a request is
3141 * required but not passed in.
3143 * This code is meant to abstract object synchronization with the GPU.
3144 * Calling with NULL implies synchronizing the object with the CPU
3145 * rather than a particular GPU ring. Conceptually we serialise writes
3146 * between engines inside the GPU. We only allow one engine to write
3147 * into a buffer at any time, but multiple readers. To ensure each has
3148 * a coherent view of memory, we must:
3150 * - If there is an outstanding write request to the object, the new
3151 * request must wait for it to complete (either CPU or in hw, requests
3152 * on the same ring will be naturally ordered).
3154 * - If we are a write request (pending_write_domain is set), the new
3155 * request must wait for outstanding read requests to complete.
3157 * For CPU synchronisation (NULL to) no request is required. For syncing with
3158 * rings to_req must be non-NULL. However, a request does not have to be
3159 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3160 * request will be allocated automatically and returned through *to_req. Note
3161 * that it is not guaranteed that commands will be emitted (because the system
3162 * might already be idle). Hence there is no need to create a request that
3163 * might never have any work submitted. Note further that if a request is
3164 * returned in *to_req, it is the responsibility of the caller to submit
3165 * that request (after potentially adding more work to it).
3167 * Returns 0 if successful, else propagates up the lower layer error.
3170 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3171 struct intel_engine_cs *to,
3172 struct drm_i915_gem_request **to_req)
3174 const bool readonly = obj->base.pending_write_domain == 0;
3175 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3182 return i915_gem_object_wait_rendering(obj, readonly);
3186 if (obj->last_write_req)
3187 req[n++] = obj->last_write_req;
3189 for (i = 0; i < I915_NUM_RINGS; i++)
3190 if (obj->last_read_req[i])
3191 req[n++] = obj->last_read_req[i];
3193 for (i = 0; i < n; i++) {
3194 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3202 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3204 u32 old_write_domain, old_read_domains;
3206 /* Force a pagefault for domain tracking on next user access */
3207 i915_gem_release_mmap(obj);
3209 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3212 /* Wait for any direct GTT access to complete */
3215 old_read_domains = obj->base.read_domains;
3216 old_write_domain = obj->base.write_domain;
3218 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3219 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3221 trace_i915_gem_object_change_domain(obj,
3226 int i915_vma_unbind(struct i915_vma *vma)
3228 struct drm_i915_gem_object *obj = vma->obj;
3229 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3232 if (list_empty(&vma->vma_link))
3235 if (!drm_mm_node_allocated(&vma->node)) {
3236 i915_gem_vma_destroy(vma);
3243 BUG_ON(obj->pages == NULL);
3245 ret = i915_gem_object_wait_rendering(obj, false);
3248 /* Continue on if we fail due to EIO, the GPU is hung so we
3249 * should be safe and we need to cleanup or else we might
3250 * cause memory corruption through use-after-free.
3253 if (i915_is_ggtt(vma->vm) &&
3254 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3255 i915_gem_object_finish_gtt(obj);
3257 /* release the fence reg _after_ flushing */
3258 ret = i915_gem_object_put_fence(obj);
3263 trace_i915_vma_unbind(vma);
3265 vma->vm->unbind_vma(vma);
3268 list_del_init(&vma->mm_list);
3269 if (i915_is_ggtt(vma->vm)) {
3270 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3271 obj->map_and_fenceable = false;
3272 } else if (vma->ggtt_view.pages) {
3273 sg_free_table(vma->ggtt_view.pages);
3274 kfree(vma->ggtt_view.pages);
3275 vma->ggtt_view.pages = NULL;
3279 drm_mm_remove_node(&vma->node);
3280 i915_gem_vma_destroy(vma);
3282 /* Since the unbound list is global, only move to that list if
3283 * no more VMAs exist. */
3284 if (list_empty(&obj->vma_list)) {
3285 i915_gem_gtt_finish_object(obj);
3286 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3289 /* And finally now the object is completely decoupled from this vma,
3290 * we can drop its hold on the backing storage and allow it to be
3291 * reaped by the shrinker.
3293 i915_gem_object_unpin_pages(obj);
3298 int i915_gpu_idle(struct drm_device *dev)
3300 struct drm_i915_private *dev_priv = dev->dev_private;
3301 struct intel_engine_cs *ring;
3304 /* Flush everything onto the inactive list. */
3305 for_each_ring(ring, dev_priv, i) {
3306 if (!i915.enable_execlists) {
3307 struct drm_i915_gem_request *req;
3309 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
3313 ret = i915_switch_context(req);
3315 i915_gem_request_cancel(req);
3319 i915_add_request_no_flush(req);
3322 ret = intel_ring_idle(ring);
3327 WARN_ON(i915_verify_lists(dev));
3331 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3332 struct drm_i915_gem_object *obj)
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3336 int fence_pitch_shift;
3338 if (INTEL_INFO(dev)->gen >= 6) {
3339 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3340 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3342 fence_reg = FENCE_REG_965_0;
3343 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3346 fence_reg += reg * 8;
3348 /* To w/a incoherency with non-atomic 64-bit register updates,
3349 * we split the 64-bit update into two 32-bit writes. In order
3350 * for a partial fence not to be evaluated between writes, we
3351 * precede the update with write to turn off the fence register,
3352 * and only enable the fence as the last step.
3354 * For extra levels of paranoia, we make sure each step lands
3355 * before applying the next step.
3357 I915_WRITE(fence_reg, 0);
3358 POSTING_READ(fence_reg);
3361 u32 size = i915_gem_obj_ggtt_size(obj);
3364 /* Adjust fence size to match tiled area */
3365 if (obj->tiling_mode != I915_TILING_NONE) {
3366 uint32_t row_size = obj->stride *
3367 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
3368 size = (size / row_size) * row_size;
3371 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3373 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3374 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3375 if (obj->tiling_mode == I915_TILING_Y)
3376 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3377 val |= I965_FENCE_REG_VALID;
3379 I915_WRITE(fence_reg + 4, val >> 32);
3380 POSTING_READ(fence_reg + 4);
3382 I915_WRITE(fence_reg + 0, val);
3383 POSTING_READ(fence_reg);
3385 I915_WRITE(fence_reg + 4, 0);
3386 POSTING_READ(fence_reg + 4);
3390 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3391 struct drm_i915_gem_object *obj)
3393 struct drm_i915_private *dev_priv = dev->dev_private;
3397 u32 size = i915_gem_obj_ggtt_size(obj);
3401 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3402 (size & -size) != size ||
3403 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3404 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3405 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3407 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3412 /* Note: pitch better be a power of two tile widths */
3413 pitch_val = obj->stride / tile_width;
3414 pitch_val = ffs(pitch_val) - 1;
3416 val = i915_gem_obj_ggtt_offset(obj);
3417 if (obj->tiling_mode == I915_TILING_Y)
3418 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3419 val |= I915_FENCE_SIZE_BITS(size);
3420 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3421 val |= I830_FENCE_REG_VALID;
3426 reg = FENCE_REG_830_0 + reg * 4;
3428 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3430 I915_WRITE(reg, val);
3434 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3435 struct drm_i915_gem_object *obj)
3437 struct drm_i915_private *dev_priv = dev->dev_private;
3441 u32 size = i915_gem_obj_ggtt_size(obj);
3444 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3445 (size & -size) != size ||
3446 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3447 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3448 i915_gem_obj_ggtt_offset(obj), size);
3450 pitch_val = obj->stride / 128;
3451 pitch_val = ffs(pitch_val) - 1;
3453 val = i915_gem_obj_ggtt_offset(obj);
3454 if (obj->tiling_mode == I915_TILING_Y)
3455 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3456 val |= I830_FENCE_SIZE_BITS(size);
3457 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3458 val |= I830_FENCE_REG_VALID;
3462 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3463 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3466 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3468 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3471 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3472 struct drm_i915_gem_object *obj)
3474 struct drm_i915_private *dev_priv = dev->dev_private;
3476 /* Ensure that all CPU reads are completed before installing a fence
3477 * and all writes before removing the fence.
3479 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3482 WARN(obj && (!obj->stride || !obj->tiling_mode),
3483 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3484 obj->stride, obj->tiling_mode);
3487 i830_write_fence_reg(dev, reg, obj);
3488 else if (IS_GEN3(dev))
3489 i915_write_fence_reg(dev, reg, obj);
3490 else if (INTEL_INFO(dev)->gen >= 4)
3491 i965_write_fence_reg(dev, reg, obj);
3493 /* And similarly be paranoid that no direct access to this region
3494 * is reordered to before the fence is installed.
3496 if (i915_gem_object_needs_mb(obj))
3500 static inline int fence_number(struct drm_i915_private *dev_priv,
3501 struct drm_i915_fence_reg *fence)
3503 return fence - dev_priv->fence_regs;
3506 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3507 struct drm_i915_fence_reg *fence,
3510 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3511 int reg = fence_number(dev_priv, fence);
3513 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3516 obj->fence_reg = reg;
3518 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3520 obj->fence_reg = I915_FENCE_REG_NONE;
3522 list_del_init(&fence->lru_list);
3524 obj->fence_dirty = false;
3528 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3530 if (obj->last_fenced_req) {
3531 int ret = i915_wait_request(obj->last_fenced_req);
3535 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3542 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3544 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3545 struct drm_i915_fence_reg *fence;
3548 ret = i915_gem_object_wait_fence(obj);
3552 if (obj->fence_reg == I915_FENCE_REG_NONE)
3555 fence = &dev_priv->fence_regs[obj->fence_reg];
3557 if (WARN_ON(fence->pin_count))
3560 i915_gem_object_fence_lost(obj);
3561 i915_gem_object_update_fence(obj, fence, false);
3566 static struct drm_i915_fence_reg *
3567 i915_find_fence_reg(struct drm_device *dev)
3569 struct drm_i915_private *dev_priv = dev->dev_private;
3570 struct drm_i915_fence_reg *reg, *avail;
3573 /* First try to find a free reg */
3575 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3576 reg = &dev_priv->fence_regs[i];
3580 if (!reg->pin_count)
3587 /* None available, try to steal one or wait for a user to finish */
3588 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3596 /* Wait for completion of pending flips which consume fences */
3597 if (intel_has_pending_fb_unpin(dev))
3598 return ERR_PTR(-EAGAIN);
3600 return ERR_PTR(-EDEADLK);
3604 * i915_gem_object_get_fence - set up fencing for an object
3605 * @obj: object to map through a fence reg
3607 * When mapping objects through the GTT, userspace wants to be able to write
3608 * to them without having to worry about swizzling if the object is tiled.
3609 * This function walks the fence regs looking for a free one for @obj,
3610 * stealing one if it can't find any.
3612 * It then sets up the reg based on the object's properties: address, pitch
3613 * and tiling format.
3615 * For an untiled surface, this removes any existing fence.
3618 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3620 struct drm_device *dev = obj->base.dev;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 bool enable = obj->tiling_mode != I915_TILING_NONE;
3623 struct drm_i915_fence_reg *reg;
3626 /* Have we updated the tiling parameters upon the object and so
3627 * will need to serialise the write to the associated fence register?
3629 if (obj->fence_dirty) {
3630 ret = i915_gem_object_wait_fence(obj);
3635 /* Just update our place in the LRU if our fence is getting reused. */
3636 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3637 reg = &dev_priv->fence_regs[obj->fence_reg];
3638 if (!obj->fence_dirty) {
3639 list_move_tail(®->lru_list,
3640 &dev_priv->mm.fence_list);
3643 } else if (enable) {
3644 if (WARN_ON(!obj->map_and_fenceable))
3647 reg = i915_find_fence_reg(dev);
3649 return PTR_ERR(reg);
3652 struct drm_i915_gem_object *old = reg->obj;
3654 ret = i915_gem_object_wait_fence(old);
3658 i915_gem_object_fence_lost(old);
3663 i915_gem_object_update_fence(obj, reg, enable);
3668 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3669 unsigned long cache_level)
3671 struct drm_mm_node *gtt_space = &vma->node;
3672 struct drm_mm_node *other;
3675 * On some machines we have to be careful when putting differing types
3676 * of snoopable memory together to avoid the prefetcher crossing memory
3677 * domains and dying. During vm initialisation, we decide whether or not
3678 * these constraints apply and set the drm_mm.color_adjust
3681 if (vma->vm->mm.color_adjust == NULL)
3684 if (!drm_mm_node_allocated(gtt_space))
3687 if (list_empty(>t_space->node_list))
3690 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3691 if (other->allocated && !other->hole_follows && other->color != cache_level)
3694 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3695 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3702 * Finds free space in the GTT aperture and binds the object or a view of it
3705 static struct i915_vma *
3706 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3707 struct i915_address_space *vm,
3708 const struct i915_ggtt_view *ggtt_view,
3712 struct drm_device *dev = obj->base.dev;
3713 struct drm_i915_private *dev_priv = dev->dev_private;
3714 u32 size, fence_size, fence_alignment, unfenced_alignment;
3715 unsigned long start =
3716 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3718 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3719 struct i915_vma *vma;
3722 if (i915_is_ggtt(vm)) {
3725 if (WARN_ON(!ggtt_view))
3726 return ERR_PTR(-EINVAL);
3728 view_size = i915_ggtt_view_size(obj, ggtt_view);
3730 fence_size = i915_gem_get_gtt_size(dev,
3733 fence_alignment = i915_gem_get_gtt_alignment(dev,
3737 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3741 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3743 fence_size = i915_gem_get_gtt_size(dev,
3746 fence_alignment = i915_gem_get_gtt_alignment(dev,
3750 unfenced_alignment =
3751 i915_gem_get_gtt_alignment(dev,
3755 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3759 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3761 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3762 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3763 ggtt_view ? ggtt_view->type : 0,
3765 return ERR_PTR(-EINVAL);
3768 /* If binding the object/GGTT view requires more space than the entire
3769 * aperture has, reject it early before evicting everything in a vain
3770 * attempt to find space.
3773 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3774 ggtt_view ? ggtt_view->type : 0,
3776 flags & PIN_MAPPABLE ? "mappable" : "total",
3778 return ERR_PTR(-E2BIG);
3781 ret = i915_gem_object_get_pages(obj);
3783 return ERR_PTR(ret);
3785 i915_gem_object_pin_pages(obj);
3787 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3788 i915_gem_obj_lookup_or_create_vma(obj, vm);
3794 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3798 DRM_MM_SEARCH_DEFAULT,
3799 DRM_MM_CREATE_DEFAULT);
3801 ret = i915_gem_evict_something(dev, vm, size, alignment,
3810 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3812 goto err_remove_node;
3815 ret = i915_gem_gtt_prepare_object(obj);
3817 goto err_remove_node;
3819 trace_i915_vma_bind(vma, flags);
3820 ret = i915_vma_bind(vma, obj->cache_level, flags);
3822 goto err_finish_gtt;
3824 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3825 list_add_tail(&vma->mm_list, &vm->inactive_list);
3830 i915_gem_gtt_finish_object(obj);
3832 drm_mm_remove_node(&vma->node);
3834 i915_gem_vma_destroy(vma);
3837 i915_gem_object_unpin_pages(obj);
3842 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3845 /* If we don't have a page list set up, then we're not pinned
3846 * to GPU, and we can ignore the cache flush because it'll happen
3847 * again at bind time.
3849 if (obj->pages == NULL)
3853 * Stolen memory is always coherent with the GPU as it is explicitly
3854 * marked as wc by the system, or the system is cache-coherent.
3856 if (obj->stolen || obj->phys_handle)
3859 /* If the GPU is snooping the contents of the CPU cache,
3860 * we do not need to manually clear the CPU cache lines. However,
3861 * the caches are only snooped when the render cache is
3862 * flushed/invalidated. As we always have to emit invalidations
3863 * and flushes when moving into and out of the RENDER domain, correct
3864 * snooping behaviour occurs naturally as the result of our domain
3867 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3868 obj->cache_dirty = true;
3872 trace_i915_gem_object_clflush(obj);
3873 drm_clflush_sg(obj->pages);
3874 obj->cache_dirty = false;
3879 /** Flushes the GTT write domain for the object if it's dirty. */
3881 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3883 uint32_t old_write_domain;
3885 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3888 /* No actual flushing is required for the GTT write domain. Writes
3889 * to it immediately go to main memory as far as we know, so there's
3890 * no chipset flush. It also doesn't land in render cache.
3892 * However, we do have to enforce the order so that all writes through
3893 * the GTT land before any writes to the device, such as updates to
3898 old_write_domain = obj->base.write_domain;
3899 obj->base.write_domain = 0;
3901 intel_fb_obj_flush(obj, false);
3903 trace_i915_gem_object_change_domain(obj,
3904 obj->base.read_domains,
3908 /** Flushes the CPU write domain for the object if it's dirty. */
3910 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3912 uint32_t old_write_domain;
3914 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3917 if (i915_gem_clflush_object(obj, obj->pin_display))
3918 i915_gem_chipset_flush(obj->base.dev);
3920 old_write_domain = obj->base.write_domain;
3921 obj->base.write_domain = 0;
3923 intel_fb_obj_flush(obj, false);
3925 trace_i915_gem_object_change_domain(obj,
3926 obj->base.read_domains,
3931 * Moves a single object to the GTT read, and possibly write domain.
3933 * This function returns when the move is complete, including waiting on
3937 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3939 uint32_t old_write_domain, old_read_domains;
3940 struct i915_vma *vma;
3943 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3946 ret = i915_gem_object_wait_rendering(obj, !write);
3950 /* Flush and acquire obj->pages so that we are coherent through
3951 * direct access in memory with previous cached writes through
3952 * shmemfs and that our cache domain tracking remains valid.
3953 * For example, if the obj->filp was moved to swap without us
3954 * being notified and releasing the pages, we would mistakenly
3955 * continue to assume that the obj remained out of the CPU cached
3958 ret = i915_gem_object_get_pages(obj);
3962 i915_gem_object_flush_cpu_write_domain(obj);
3964 /* Serialise direct access to this object with the barriers for
3965 * coherent writes from the GPU, by effectively invalidating the
3966 * GTT domain upon first access.
3968 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3971 old_write_domain = obj->base.write_domain;
3972 old_read_domains = obj->base.read_domains;
3974 /* It should now be out of any other write domains, and we can update
3975 * the domain values for our changes.
3977 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3978 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3980 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3981 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3986 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
3988 trace_i915_gem_object_change_domain(obj,
3992 /* And bump the LRU for this access */
3993 vma = i915_gem_obj_to_ggtt(obj);
3994 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3995 list_move_tail(&vma->mm_list,
3996 &to_i915(obj->base.dev)->gtt.base.inactive_list);
4001 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
4002 enum i915_cache_level cache_level)
4004 struct drm_device *dev = obj->base.dev;
4005 struct i915_vma *vma, *next;
4008 if (obj->cache_level == cache_level)
4011 if (i915_gem_obj_is_pinned(obj)) {
4012 DRM_DEBUG("can not change the cache level of pinned objects\n");
4016 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4017 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
4018 ret = i915_vma_unbind(vma);
4024 if (i915_gem_obj_bound_any(obj)) {
4025 ret = i915_gem_object_wait_rendering(obj, false);
4029 i915_gem_object_finish_gtt(obj);
4031 /* Before SandyBridge, you could not use tiling or fence
4032 * registers with snooped memory, so relinquish any fences
4033 * currently pointing to our region in the aperture.
4035 if (INTEL_INFO(dev)->gen < 6) {
4036 ret = i915_gem_object_put_fence(obj);
4041 list_for_each_entry(vma, &obj->vma_list, vma_link)
4042 if (drm_mm_node_allocated(&vma->node)) {
4043 ret = i915_vma_bind(vma, cache_level,
4050 list_for_each_entry(vma, &obj->vma_list, vma_link)
4051 vma->node.color = cache_level;
4052 obj->cache_level = cache_level;
4054 if (obj->cache_dirty &&
4055 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
4056 cpu_write_needs_clflush(obj)) {
4057 if (i915_gem_clflush_object(obj, true))
4058 i915_gem_chipset_flush(obj->base.dev);
4064 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
4065 struct drm_file *file)
4067 struct drm_i915_gem_caching *args = data;
4068 struct drm_i915_gem_object *obj;
4070 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4071 if (&obj->base == NULL)
4074 switch (obj->cache_level) {
4075 case I915_CACHE_LLC:
4076 case I915_CACHE_L3_LLC:
4077 args->caching = I915_CACHING_CACHED;
4081 args->caching = I915_CACHING_DISPLAY;
4085 args->caching = I915_CACHING_NONE;
4089 drm_gem_object_unreference_unlocked(&obj->base);
4093 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
4094 struct drm_file *file)
4096 struct drm_i915_gem_caching *args = data;
4097 struct drm_i915_gem_object *obj;
4098 enum i915_cache_level level;
4101 switch (args->caching) {
4102 case I915_CACHING_NONE:
4103 level = I915_CACHE_NONE;
4105 case I915_CACHING_CACHED:
4106 level = I915_CACHE_LLC;
4108 case I915_CACHING_DISPLAY:
4109 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
4115 ret = i915_mutex_lock_interruptible(dev);
4119 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4120 if (&obj->base == NULL) {
4125 ret = i915_gem_object_set_cache_level(obj, level);
4127 drm_gem_object_unreference(&obj->base);
4129 mutex_unlock(&dev->struct_mutex);
4134 * Prepare buffer for display plane (scanout, cursors, etc).
4135 * Can be called from an uninterruptible phase (modesetting) and allows
4136 * any flushes to be pipelined (for pageflips).
4139 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4141 struct intel_engine_cs *pipelined,
4142 struct drm_i915_gem_request **pipelined_request,
4143 const struct i915_ggtt_view *view)
4145 u32 old_read_domains, old_write_domain;
4148 ret = i915_gem_object_sync(obj, pipelined, pipelined_request);
4152 /* Mark the pin_display early so that we account for the
4153 * display coherency whilst setting up the cache domains.
4157 /* The display engine is not coherent with the LLC cache on gen6. As
4158 * a result, we make sure that the pinning that is about to occur is
4159 * done with uncached PTEs. This is lowest common denominator for all
4162 * However for gen6+, we could do better by using the GFDT bit instead
4163 * of uncaching, which would allow us to flush all the LLC-cached data
4164 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4166 ret = i915_gem_object_set_cache_level(obj,
4167 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4169 goto err_unpin_display;
4171 /* As the user may map the buffer once pinned in the display plane
4172 * (e.g. libkms for the bootup splash), we have to ensure that we
4173 * always use map_and_fenceable for all scanout buffers.
4175 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4176 view->type == I915_GGTT_VIEW_NORMAL ?
4179 goto err_unpin_display;
4181 i915_gem_object_flush_cpu_write_domain(obj);
4183 old_write_domain = obj->base.write_domain;
4184 old_read_domains = obj->base.read_domains;
4186 /* It should now be out of any other write domains, and we can update
4187 * the domain values for our changes.
4189 obj->base.write_domain = 0;
4190 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4192 trace_i915_gem_object_change_domain(obj,
4204 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4205 const struct i915_ggtt_view *view)
4207 if (WARN_ON(obj->pin_display == 0))
4210 i915_gem_object_ggtt_unpin_view(obj, view);
4216 * Moves a single object to the CPU read, and possibly write domain.
4218 * This function returns when the move is complete, including waiting on
4222 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4224 uint32_t old_write_domain, old_read_domains;
4227 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4230 ret = i915_gem_object_wait_rendering(obj, !write);
4234 i915_gem_object_flush_gtt_write_domain(obj);
4236 old_write_domain = obj->base.write_domain;
4237 old_read_domains = obj->base.read_domains;
4239 /* Flush the CPU cache if it's still invalid. */
4240 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4241 i915_gem_clflush_object(obj, false);
4243 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4246 /* It should now be out of any other write domains, and we can update
4247 * the domain values for our changes.
4249 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4251 /* If we're writing through the CPU, then the GPU read domains will
4252 * need to be invalidated at next use.
4255 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4256 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4260 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
4262 trace_i915_gem_object_change_domain(obj,
4269 /* Throttle our rendering by waiting until the ring has completed our requests
4270 * emitted over 20 msec ago.
4272 * Note that if we were to use the current jiffies each time around the loop,
4273 * we wouldn't escape the function with any frames outstanding if the time to
4274 * render a frame was over 20ms.
4276 * This should get us reasonable parallelism between CPU and GPU but also
4277 * relatively low latency when blocking on a particular request to finish.
4280 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 struct drm_i915_file_private *file_priv = file->driver_priv;
4284 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4285 struct drm_i915_gem_request *request, *target = NULL;
4286 unsigned reset_counter;
4289 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4293 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4297 spin_lock(&file_priv->mm.lock);
4298 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4299 if (time_after_eq(request->emitted_jiffies, recent_enough))
4303 * Note that the request might not have been submitted yet.
4304 * In which case emitted_jiffies will be zero.
4306 if (!request->emitted_jiffies)
4311 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4313 i915_gem_request_reference(target);
4314 spin_unlock(&file_priv->mm.lock);
4319 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4321 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4323 i915_gem_request_unreference__unlocked(target);
4329 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4331 struct drm_i915_gem_object *obj = vma->obj;
4334 vma->node.start & (alignment - 1))
4337 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4340 if (flags & PIN_OFFSET_BIAS &&
4341 vma->node.start < (flags & PIN_OFFSET_MASK))
4348 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4349 struct i915_address_space *vm,
4350 const struct i915_ggtt_view *ggtt_view,
4354 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4355 struct i915_vma *vma;
4359 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4362 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4365 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4368 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4371 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4372 i915_gem_obj_to_vma(obj, vm);
4375 return PTR_ERR(vma);
4378 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4381 if (i915_vma_misplaced(vma, alignment, flags)) {
4382 unsigned long offset;
4383 offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) :
4384 i915_gem_obj_offset(obj, vm);
4385 WARN(vma->pin_count,
4386 "bo is already pinned in %s with incorrect alignment:"
4387 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4388 " obj->map_and_fenceable=%d\n",
4389 ggtt_view ? "ggtt" : "ppgtt",
4392 !!(flags & PIN_MAPPABLE),
4393 obj->map_and_fenceable);
4394 ret = i915_vma_unbind(vma);
4402 bound = vma ? vma->bound : 0;
4403 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4404 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4407 return PTR_ERR(vma);
4409 ret = i915_vma_bind(vma, obj->cache_level, flags);
4414 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4415 (bound ^ vma->bound) & GLOBAL_BIND) {
4416 bool mappable, fenceable;
4417 u32 fence_size, fence_alignment;
4419 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4422 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4427 fenceable = (vma->node.size == fence_size &&
4428 (vma->node.start & (fence_alignment - 1)) == 0);
4430 mappable = (vma->node.start + fence_size <=
4431 dev_priv->gtt.mappable_end);
4433 obj->map_and_fenceable = mappable && fenceable;
4435 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4443 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4444 struct i915_address_space *vm,
4448 return i915_gem_object_do_pin(obj, vm,
4449 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4454 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4455 const struct i915_ggtt_view *view,
4459 if (WARN_ONCE(!view, "no view specified"))
4462 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4463 alignment, flags | PIN_GLOBAL);
4467 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4468 const struct i915_ggtt_view *view)
4470 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4473 WARN_ON(vma->pin_count == 0);
4474 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4480 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4482 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4483 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4484 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4486 WARN_ON(!ggtt_vma ||
4487 dev_priv->fence_regs[obj->fence_reg].pin_count >
4488 ggtt_vma->pin_count);
4489 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4496 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4498 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4499 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4500 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4501 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4506 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4507 struct drm_file *file)
4509 struct drm_i915_gem_busy *args = data;
4510 struct drm_i915_gem_object *obj;
4513 ret = i915_mutex_lock_interruptible(dev);
4517 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4518 if (&obj->base == NULL) {
4523 /* Count all active objects as busy, even if they are currently not used
4524 * by the gpu. Users of this interface expect objects to eventually
4525 * become non-busy without any further actions, therefore emit any
4526 * necessary flushes here.
4528 ret = i915_gem_object_flush_active(obj);
4532 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4533 args->busy = obj->active << 16;
4534 if (obj->last_write_req)
4535 args->busy |= obj->last_write_req->ring->id;
4538 drm_gem_object_unreference(&obj->base);
4540 mutex_unlock(&dev->struct_mutex);
4545 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4546 struct drm_file *file_priv)
4548 return i915_gem_ring_throttle(dev, file_priv);
4552 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4553 struct drm_file *file_priv)
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556 struct drm_i915_gem_madvise *args = data;
4557 struct drm_i915_gem_object *obj;
4560 switch (args->madv) {
4561 case I915_MADV_DONTNEED:
4562 case I915_MADV_WILLNEED:
4568 ret = i915_mutex_lock_interruptible(dev);
4572 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4573 if (&obj->base == NULL) {
4578 if (i915_gem_obj_is_pinned(obj)) {
4584 obj->tiling_mode != I915_TILING_NONE &&
4585 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4586 if (obj->madv == I915_MADV_WILLNEED)
4587 i915_gem_object_unpin_pages(obj);
4588 if (args->madv == I915_MADV_WILLNEED)
4589 i915_gem_object_pin_pages(obj);
4592 if (obj->madv != __I915_MADV_PURGED)
4593 obj->madv = args->madv;
4595 /* if the object is no longer attached, discard its backing storage */
4596 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4597 i915_gem_object_truncate(obj);
4599 args->retained = obj->madv != __I915_MADV_PURGED;
4602 drm_gem_object_unreference(&obj->base);
4604 mutex_unlock(&dev->struct_mutex);
4608 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4609 const struct drm_i915_gem_object_ops *ops)
4613 INIT_LIST_HEAD(&obj->global_list);
4614 for (i = 0; i < I915_NUM_RINGS; i++)
4615 INIT_LIST_HEAD(&obj->ring_list[i]);
4616 INIT_LIST_HEAD(&obj->obj_exec_link);
4617 INIT_LIST_HEAD(&obj->vma_list);
4618 INIT_LIST_HEAD(&obj->batch_pool_link);
4622 obj->fence_reg = I915_FENCE_REG_NONE;
4623 obj->madv = I915_MADV_WILLNEED;
4625 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4628 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4629 .get_pages = i915_gem_object_get_pages_gtt,
4630 .put_pages = i915_gem_object_put_pages_gtt,
4633 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4636 struct drm_i915_gem_object *obj;
4637 struct address_space *mapping;
4640 obj = i915_gem_object_alloc(dev);
4644 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4645 i915_gem_object_free(obj);
4649 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4650 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4651 /* 965gm cannot relocate objects above 4GiB. */
4652 mask &= ~__GFP_HIGHMEM;
4653 mask |= __GFP_DMA32;
4656 mapping = file_inode(obj->base.filp)->i_mapping;
4657 mapping_set_gfp_mask(mapping, mask);
4659 i915_gem_object_init(obj, &i915_gem_object_ops);
4661 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4662 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4665 /* On some devices, we can have the GPU use the LLC (the CPU
4666 * cache) for about a 10% performance improvement
4667 * compared to uncached. Graphics requests other than
4668 * display scanout are coherent with the CPU in
4669 * accessing this cache. This means in this mode we
4670 * don't need to clflush on the CPU side, and on the
4671 * GPU side we only need to flush internal caches to
4672 * get data visible to the CPU.
4674 * However, we maintain the display planes as UC, and so
4675 * need to rebind when first used as such.
4677 obj->cache_level = I915_CACHE_LLC;
4679 obj->cache_level = I915_CACHE_NONE;
4681 trace_i915_gem_object_create(obj);
4686 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4688 /* If we are the last user of the backing storage (be it shmemfs
4689 * pages or stolen etc), we know that the pages are going to be
4690 * immediately released. In this case, we can then skip copying
4691 * back the contents from the GPU.
4694 if (obj->madv != I915_MADV_WILLNEED)
4697 if (obj->base.filp == NULL)
4700 /* At first glance, this looks racy, but then again so would be
4701 * userspace racing mmap against close. However, the first external
4702 * reference to the filp can only be obtained through the
4703 * i915_gem_mmap_ioctl() which safeguards us against the user
4704 * acquiring such a reference whilst we are in the middle of
4705 * freeing the object.
4707 return atomic_long_read(&obj->base.filp->f_count) == 1;
4710 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4712 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4713 struct drm_device *dev = obj->base.dev;
4714 struct drm_i915_private *dev_priv = dev->dev_private;
4715 struct i915_vma *vma, *next;
4717 intel_runtime_pm_get(dev_priv);
4719 trace_i915_gem_object_destroy(obj);
4721 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4725 ret = i915_vma_unbind(vma);
4726 if (WARN_ON(ret == -ERESTARTSYS)) {
4727 bool was_interruptible;
4729 was_interruptible = dev_priv->mm.interruptible;
4730 dev_priv->mm.interruptible = false;
4732 WARN_ON(i915_vma_unbind(vma));
4734 dev_priv->mm.interruptible = was_interruptible;
4738 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4739 * before progressing. */
4741 i915_gem_object_unpin_pages(obj);
4743 WARN_ON(obj->frontbuffer_bits);
4745 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4746 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4747 obj->tiling_mode != I915_TILING_NONE)
4748 i915_gem_object_unpin_pages(obj);
4750 if (WARN_ON(obj->pages_pin_count))
4751 obj->pages_pin_count = 0;
4752 if (discard_backing_storage(obj))
4753 obj->madv = I915_MADV_DONTNEED;
4754 i915_gem_object_put_pages(obj);
4755 i915_gem_object_free_mmap_offset(obj);
4759 if (obj->base.import_attach)
4760 drm_prime_gem_destroy(&obj->base, NULL);
4762 if (obj->ops->release)
4763 obj->ops->release(obj);
4765 drm_gem_object_release(&obj->base);
4766 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4769 i915_gem_object_free(obj);
4771 intel_runtime_pm_put(dev_priv);
4774 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4775 struct i915_address_space *vm)
4777 struct i915_vma *vma;
4778 list_for_each_entry(vma, &obj->vma_list, vma_link) {
4779 if (i915_is_ggtt(vma->vm) &&
4780 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
4788 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4789 const struct i915_ggtt_view *view)
4791 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4792 struct i915_vma *vma;
4794 if (WARN_ONCE(!view, "no view specified"))
4795 return ERR_PTR(-EINVAL);
4797 list_for_each_entry(vma, &obj->vma_list, vma_link)
4798 if (vma->vm == ggtt &&
4799 i915_ggtt_view_equal(&vma->ggtt_view, view))
4804 void i915_gem_vma_destroy(struct i915_vma *vma)
4806 struct i915_address_space *vm = NULL;
4807 WARN_ON(vma->node.allocated);
4809 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4810 if (!list_empty(&vma->exec_list))
4815 if (!i915_is_ggtt(vm))
4816 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4818 list_del(&vma->vma_link);
4820 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4824 i915_gem_stop_ringbuffers(struct drm_device *dev)
4826 struct drm_i915_private *dev_priv = dev->dev_private;
4827 struct intel_engine_cs *ring;
4830 for_each_ring(ring, dev_priv, i)
4831 dev_priv->gt.stop_ring(ring);
4835 i915_gem_suspend(struct drm_device *dev)
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4840 mutex_lock(&dev->struct_mutex);
4841 ret = i915_gpu_idle(dev);
4845 i915_gem_retire_requests(dev);
4847 i915_gem_stop_ringbuffers(dev);
4848 mutex_unlock(&dev->struct_mutex);
4850 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4851 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4852 flush_delayed_work(&dev_priv->mm.idle_work);
4854 /* Assert that we sucessfully flushed all the work and
4855 * reset the GPU back to its idle, low power state.
4857 WARN_ON(dev_priv->mm.busy);
4862 mutex_unlock(&dev->struct_mutex);
4866 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
4868 struct intel_engine_cs *ring = req->ring;
4869 struct drm_device *dev = ring->dev;
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4872 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4875 if (!HAS_L3_DPF(dev) || !remap_info)
4878 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
4883 * Note: We do not worry about the concurrent register cacheline hang
4884 * here because no other code should access these registers other than
4885 * at initialization time.
4887 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4888 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4889 intel_ring_emit(ring, reg_base + i);
4890 intel_ring_emit(ring, remap_info[i/4]);
4893 intel_ring_advance(ring);
4898 void i915_gem_init_swizzling(struct drm_device *dev)
4900 struct drm_i915_private *dev_priv = dev->dev_private;
4902 if (INTEL_INFO(dev)->gen < 5 ||
4903 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4906 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4907 DISP_TILE_SURFACE_SWIZZLING);
4912 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4914 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4915 else if (IS_GEN7(dev))
4916 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4917 else if (IS_GEN8(dev))
4918 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4924 intel_enable_blt(struct drm_device *dev)
4929 /* The blitter was dysfunctional on early prototypes */
4930 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4931 DRM_INFO("BLT not supported on this pre-production hardware;"
4932 " graphics performance will be degraded.\n");
4939 static void init_unused_ring(struct drm_device *dev, u32 base)
4941 struct drm_i915_private *dev_priv = dev->dev_private;
4943 I915_WRITE(RING_CTL(base), 0);
4944 I915_WRITE(RING_HEAD(base), 0);
4945 I915_WRITE(RING_TAIL(base), 0);
4946 I915_WRITE(RING_START(base), 0);
4949 static void init_unused_rings(struct drm_device *dev)
4952 init_unused_ring(dev, PRB1_BASE);
4953 init_unused_ring(dev, SRB0_BASE);
4954 init_unused_ring(dev, SRB1_BASE);
4955 init_unused_ring(dev, SRB2_BASE);
4956 init_unused_ring(dev, SRB3_BASE);
4957 } else if (IS_GEN2(dev)) {
4958 init_unused_ring(dev, SRB0_BASE);
4959 init_unused_ring(dev, SRB1_BASE);
4960 } else if (IS_GEN3(dev)) {
4961 init_unused_ring(dev, PRB1_BASE);
4962 init_unused_ring(dev, PRB2_BASE);
4966 int i915_gem_init_rings(struct drm_device *dev)
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4971 ret = intel_init_render_ring_buffer(dev);
4976 ret = intel_init_bsd_ring_buffer(dev);
4978 goto cleanup_render_ring;
4981 if (intel_enable_blt(dev)) {
4982 ret = intel_init_blt_ring_buffer(dev);
4984 goto cleanup_bsd_ring;
4987 if (HAS_VEBOX(dev)) {
4988 ret = intel_init_vebox_ring_buffer(dev);
4990 goto cleanup_blt_ring;
4993 if (HAS_BSD2(dev)) {
4994 ret = intel_init_bsd2_ring_buffer(dev);
4996 goto cleanup_vebox_ring;
4999 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
5001 goto cleanup_bsd2_ring;
5006 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
5008 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
5010 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
5012 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
5013 cleanup_render_ring:
5014 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
5020 i915_gem_init_hw(struct drm_device *dev)
5022 struct drm_i915_private *dev_priv = dev->dev_private;
5023 struct intel_engine_cs *ring;
5026 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
5029 /* Double layer security blanket, see i915_gem_init() */
5030 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5032 if (dev_priv->ellc_size)
5033 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
5035 if (IS_HASWELL(dev))
5036 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
5037 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
5039 if (HAS_PCH_NOP(dev)) {
5040 if (IS_IVYBRIDGE(dev)) {
5041 u32 temp = I915_READ(GEN7_MSG_CTL);
5042 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
5043 I915_WRITE(GEN7_MSG_CTL, temp);
5044 } else if (INTEL_INFO(dev)->gen >= 7) {
5045 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
5046 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
5047 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
5051 i915_gem_init_swizzling(dev);
5054 * At least 830 can leave some of the unused rings
5055 * "active" (ie. head != tail) after resume which
5056 * will prevent c3 entry. Makes sure all unused rings
5059 init_unused_rings(dev);
5061 BUG_ON(!dev_priv->ring[RCS].default_context);
5063 ret = i915_ppgtt_init_hw(dev);
5065 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
5069 /* Need to do basic initialisation of all rings first: */
5070 for_each_ring(ring, dev_priv, i) {
5071 ret = ring->init_hw(ring);
5076 /* Now it is safe to go back round and do everything else: */
5077 for_each_ring(ring, dev_priv, i) {
5078 struct drm_i915_gem_request *req;
5080 WARN_ON(!ring->default_context);
5082 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
5084 i915_gem_cleanup_ringbuffer(dev);
5088 if (ring->id == RCS) {
5089 for (j = 0; j < NUM_L3_SLICES(dev); j++)
5090 i915_gem_l3_remap(req, j);
5093 ret = i915_ppgtt_init_ring(req);
5094 if (ret && ret != -EIO) {
5095 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret);
5096 i915_gem_request_cancel(req);
5097 i915_gem_cleanup_ringbuffer(dev);
5101 ret = i915_gem_context_enable(req);
5102 if (ret && ret != -EIO) {
5103 DRM_ERROR("Context enable ring #%d failed %d\n", i, ret);
5104 i915_gem_request_cancel(req);
5105 i915_gem_cleanup_ringbuffer(dev);
5109 i915_add_request_no_flush(req);
5113 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5117 int i915_gem_init(struct drm_device *dev)
5119 struct drm_i915_private *dev_priv = dev->dev_private;
5122 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
5123 i915.enable_execlists);
5125 mutex_lock(&dev->struct_mutex);
5127 if (IS_VALLEYVIEW(dev)) {
5128 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5129 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
5130 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
5131 VLV_GTLC_ALLOWWAKEACK), 10))
5132 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5135 if (!i915.enable_execlists) {
5136 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
5137 dev_priv->gt.init_rings = i915_gem_init_rings;
5138 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
5139 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
5141 dev_priv->gt.execbuf_submit = intel_execlists_submission;
5142 dev_priv->gt.init_rings = intel_logical_rings_init;
5143 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
5144 dev_priv->gt.stop_ring = intel_logical_ring_stop;
5147 /* This is just a security blanket to placate dragons.
5148 * On some systems, we very sporadically observe that the first TLBs
5149 * used by the CS may be stale, despite us poking the TLB reset. If
5150 * we hold the forcewake during initialisation these problems
5151 * just magically go away.
5153 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5155 ret = i915_gem_init_userptr(dev);
5159 i915_gem_init_global_gtt(dev);
5161 ret = i915_gem_context_init(dev);
5165 ret = dev_priv->gt.init_rings(dev);
5169 ret = i915_gem_init_hw(dev);
5171 /* Allow ring initialisation to fail by marking the GPU as
5172 * wedged. But we only want to do this where the GPU is angry,
5173 * for all other failure, such as an allocation failure, bail.
5175 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5176 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5181 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5182 mutex_unlock(&dev->struct_mutex);
5188 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
5190 struct drm_i915_private *dev_priv = dev->dev_private;
5191 struct intel_engine_cs *ring;
5194 for_each_ring(ring, dev_priv, i)
5195 dev_priv->gt.cleanup_ring(ring);
5199 init_ring_lists(struct intel_engine_cs *ring)
5201 INIT_LIST_HEAD(&ring->active_list);
5202 INIT_LIST_HEAD(&ring->request_list);
5205 void i915_init_vm(struct drm_i915_private *dev_priv,
5206 struct i915_address_space *vm)
5208 if (!i915_is_ggtt(vm))
5209 drm_mm_init(&vm->mm, vm->start, vm->total);
5210 vm->dev = dev_priv->dev;
5211 INIT_LIST_HEAD(&vm->active_list);
5212 INIT_LIST_HEAD(&vm->inactive_list);
5213 INIT_LIST_HEAD(&vm->global_link);
5214 list_add_tail(&vm->global_link, &dev_priv->vm_list);
5218 i915_gem_load(struct drm_device *dev)
5220 struct drm_i915_private *dev_priv = dev->dev_private;
5224 kmem_cache_create("i915_gem_object",
5225 sizeof(struct drm_i915_gem_object), 0,
5229 kmem_cache_create("i915_gem_vma",
5230 sizeof(struct i915_vma), 0,
5233 dev_priv->requests =
5234 kmem_cache_create("i915_gem_request",
5235 sizeof(struct drm_i915_gem_request), 0,
5239 INIT_LIST_HEAD(&dev_priv->vm_list);
5240 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5242 INIT_LIST_HEAD(&dev_priv->context_list);
5243 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5244 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5245 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5246 for (i = 0; i < I915_NUM_RINGS; i++)
5247 init_ring_lists(&dev_priv->ring[i]);
5248 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5249 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5250 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5251 i915_gem_retire_work_handler);
5252 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5253 i915_gem_idle_work_handler);
5254 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5256 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5258 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5259 dev_priv->num_fence_regs = 32;
5260 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5261 dev_priv->num_fence_regs = 16;
5263 dev_priv->num_fence_regs = 8;
5265 if (intel_vgpu_active(dev))
5266 dev_priv->num_fence_regs =
5267 I915_READ(vgtif_reg(avail_rs.fence_num));
5269 /* Initialize fence registers to zero */
5270 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5271 i915_gem_restore_fences(dev);
5273 i915_gem_detect_bit_6_swizzle(dev);
5274 init_waitqueue_head(&dev_priv->pending_flip_queue);
5276 dev_priv->mm.interruptible = true;
5278 i915_gem_shrinker_init(dev_priv);
5280 mutex_init(&dev_priv->fb_tracking.lock);
5283 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5285 struct drm_i915_file_private *file_priv = file->driver_priv;
5287 /* Clean up our request list when the client is going away, so that
5288 * later retire_requests won't dereference our soon-to-be-gone
5291 spin_lock(&file_priv->mm.lock);
5292 while (!list_empty(&file_priv->mm.request_list)) {
5293 struct drm_i915_gem_request *request;
5295 request = list_first_entry(&file_priv->mm.request_list,
5296 struct drm_i915_gem_request,
5298 list_del(&request->client_list);
5299 request->file_priv = NULL;
5301 spin_unlock(&file_priv->mm.lock);
5303 if (!list_empty(&file_priv->rps.link)) {
5304 spin_lock(&to_i915(dev)->rps.client_lock);
5305 list_del(&file_priv->rps.link);
5306 spin_unlock(&to_i915(dev)->rps.client_lock);
5310 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5312 struct drm_i915_file_private *file_priv;
5315 DRM_DEBUG_DRIVER("\n");
5317 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5321 file->driver_priv = file_priv;
5322 file_priv->dev_priv = dev->dev_private;
5323 file_priv->file = file;
5324 INIT_LIST_HEAD(&file_priv->rps.link);
5326 spin_lock_init(&file_priv->mm.lock);
5327 INIT_LIST_HEAD(&file_priv->mm.request_list);
5329 ret = i915_gem_context_open(dev, file);
5337 * i915_gem_track_fb - update frontbuffer tracking
5338 * old: current GEM buffer for the frontbuffer slots
5339 * new: new GEM buffer for the frontbuffer slots
5340 * frontbuffer_bits: bitmask of frontbuffer slots
5342 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5343 * from @old and setting them in @new. Both @old and @new can be NULL.
5345 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5346 struct drm_i915_gem_object *new,
5347 unsigned frontbuffer_bits)
5350 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5351 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5352 old->frontbuffer_bits &= ~frontbuffer_bits;
5356 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5357 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5358 new->frontbuffer_bits |= frontbuffer_bits;
5362 /* All the new VM stuff */
5364 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5365 struct i915_address_space *vm)
5367 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5368 struct i915_vma *vma;
5370 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5372 list_for_each_entry(vma, &o->vma_list, vma_link) {
5373 if (i915_is_ggtt(vma->vm) &&
5374 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5377 return vma->node.start;
5380 WARN(1, "%s vma for this object not found.\n",
5381 i915_is_ggtt(vm) ? "global" : "ppgtt");
5386 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5387 const struct i915_ggtt_view *view)
5389 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5390 struct i915_vma *vma;
5392 list_for_each_entry(vma, &o->vma_list, vma_link)
5393 if (vma->vm == ggtt &&
5394 i915_ggtt_view_equal(&vma->ggtt_view, view))
5395 return vma->node.start;
5397 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5401 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5402 struct i915_address_space *vm)
5404 struct i915_vma *vma;
5406 list_for_each_entry(vma, &o->vma_list, vma_link) {
5407 if (i915_is_ggtt(vma->vm) &&
5408 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5410 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5417 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5418 const struct i915_ggtt_view *view)
5420 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5421 struct i915_vma *vma;
5423 list_for_each_entry(vma, &o->vma_list, vma_link)
5424 if (vma->vm == ggtt &&
5425 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5426 drm_mm_node_allocated(&vma->node))
5432 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5434 struct i915_vma *vma;
5436 list_for_each_entry(vma, &o->vma_list, vma_link)
5437 if (drm_mm_node_allocated(&vma->node))
5443 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5444 struct i915_address_space *vm)
5446 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5447 struct i915_vma *vma;
5449 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5451 BUG_ON(list_empty(&o->vma_list));
5453 list_for_each_entry(vma, &o->vma_list, vma_link) {
5454 if (i915_is_ggtt(vma->vm) &&
5455 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5458 return vma->node.size;
5463 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5465 struct i915_vma *vma;
5466 list_for_each_entry(vma, &obj->vma_list, vma_link)
5467 if (vma->pin_count > 0)